diff --git a/quasar_wrapper.fir b/quasar_wrapper.fir index 84163548..532e2e0c 100644 --- a/quasar_wrapper.fir +++ b/quasar_wrapper.fir @@ -77,15 +77,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch @[el2_lib.scala 474:26] + inst clkhdr of gated_latch @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_1 : output Q : Clock @@ -101,15 +101,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_1 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_1 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_2 : output Q : Clock @@ -125,15 +125,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_2 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_2 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_3 : output Q : Clock @@ -149,15 +149,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_3 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_3 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_4 : output Q : Clock @@ -173,15 +173,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_4 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_4 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_5 : output Q : Clock @@ -197,15 +197,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_5 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_5 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_6 : output Q : Clock @@ -221,15 +221,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_6 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_6 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_7 : output Q : Clock @@ -245,15 +245,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_7 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_7 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_8 : output Q : Clock @@ -269,15 +269,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_8 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_8 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_9 : output Q : Clock @@ -293,15 +293,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_9 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_9 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_10 : output Q : Clock @@ -317,15 +317,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_10 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_10 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_11 : output Q : Clock @@ -341,15 +341,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_11 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_11 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_12 : output Q : Clock @@ -365,15 +365,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_12 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_12 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_13 : output Q : Clock @@ -389,15 +389,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_13 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_13 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_14 : output Q : Clock @@ -413,15 +413,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_14 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_14 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_15 : output Q : Clock @@ -437,15 +437,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_15 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_15 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_16 : output Q : Clock @@ -461,15 +461,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_16 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_16 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_17 : output Q : Clock @@ -485,15 +485,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_17 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_17 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_18 : output Q : Clock @@ -509,15 +509,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_18 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_18 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_19 : output Q : Clock @@ -533,15 +533,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_19 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_19 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_20 : output Q : Clock @@ -557,15 +557,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_20 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_20 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_21 : output Q : Clock @@ -581,15 +581,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_21 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_21 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_22 : output Q : Clock @@ -605,15 +605,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_22 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_22 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_23 : output Q : Clock @@ -629,15 +629,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_23 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_23 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_24 : output Q : Clock @@ -653,15 +653,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_24 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_24 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_25 : output Q : Clock @@ -677,15 +677,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_25 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_25 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_26 : output Q : Clock @@ -701,15 +701,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_26 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_26 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_27 : output Q : Clock @@ -725,15 +725,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_27 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_27 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_28 : output Q : Clock @@ -749,15 +749,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_28 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_28 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_29 : output Q : Clock @@ -773,15 +773,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_29 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_29 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_30 : output Q : Clock @@ -797,15 +797,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_30 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_30 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_31 : output Q : Clock @@ -821,15 +821,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_31 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_31 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_32 : output Q : Clock @@ -845,15 +845,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_32 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_32 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_33 : output Q : Clock @@ -869,15 +869,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_33 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_33 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_34 : output Q : Clock @@ -893,15 +893,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_34 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_34 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_35 : output Q : Clock @@ -917,15 +917,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_35 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_35 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_36 : output Q : Clock @@ -941,15 +941,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_36 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_36 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_37 : output Q : Clock @@ -965,15 +965,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_37 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_37 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_38 : output Q : Clock @@ -989,15 +989,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_38 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_38 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_39 : output Q : Clock @@ -1013,15 +1013,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_39 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_39 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_40 : output Q : Clock @@ -1037,15 +1037,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_40 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_40 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_41 : output Q : Clock @@ -1061,15 +1061,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_41 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_41 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_42 : output Q : Clock @@ -1085,15 +1085,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_42 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_42 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_43 : output Q : Clock @@ -1109,15 +1109,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_43 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_43 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_44 : output Q : Clock @@ -1133,15 +1133,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_44 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_44 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_45 : output Q : Clock @@ -1157,15 +1157,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_45 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_45 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_46 : output Q : Clock @@ -1181,15 +1181,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_46 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_46 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_47 : output Q : Clock @@ -1205,15 +1205,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_47 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_47 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_48 : output Q : Clock @@ -1229,15 +1229,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_48 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_48 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_49 : output Q : Clock @@ -1253,15 +1253,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_49 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_49 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_50 : output Q : Clock @@ -1277,15 +1277,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_50 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_50 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_51 : output Q : Clock @@ -1301,15 +1301,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_51 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_51 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_52 : output Q : Clock @@ -1325,15 +1325,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_52 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_52 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_53 : output Q : Clock @@ -1349,15 +1349,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_53 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_53 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_54 : output Q : Clock @@ -1373,15 +1373,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_54 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_54 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_55 : output Q : Clock @@ -1397,15 +1397,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_55 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_55 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_56 : output Q : Clock @@ -1421,15 +1421,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_56 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_56 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_57 : output Q : Clock @@ -1445,15 +1445,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_57 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_57 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_58 : output Q : Clock @@ -1469,15 +1469,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_58 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_58 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_59 : output Q : Clock @@ -1493,15 +1493,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_59 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_59 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_60 : output Q : Clock @@ -1517,15 +1517,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_60 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_60 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_61 : output Q : Clock @@ -1541,15 +1541,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_61 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_61 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_62 : output Q : Clock @@ -1565,15 +1565,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_62 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_62 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_63 : output Q : Clock @@ -1589,15 +1589,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_63 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_63 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_64 : output Q : Clock @@ -1613,15 +1613,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_64 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_64 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_65 : output Q : Clock @@ -1637,15 +1637,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_65 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_65 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_66 : output Q : Clock @@ -1661,15 +1661,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_66 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_66 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_67 : output Q : Clock @@ -1685,15 +1685,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_67 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_67 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_68 : output Q : Clock @@ -1709,15 +1709,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_68 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_68 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_69 : output Q : Clock @@ -1733,15 +1733,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_69 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_69 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_70 : output Q : Clock @@ -1757,15 +1757,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_70 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_70 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_71 : output Q : Clock @@ -1781,15 +1781,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_71 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_71 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_72 : output Q : Clock @@ -1805,15 +1805,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_72 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_72 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_73 : output Q : Clock @@ -1829,15 +1829,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_73 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_73 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_74 : output Q : Clock @@ -1853,15 +1853,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_74 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_74 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_75 : output Q : Clock @@ -1877,15 +1877,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_75 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_75 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_76 : output Q : Clock @@ -1901,15 +1901,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_76 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_76 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_77 : output Q : Clock @@ -1925,15 +1925,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_77 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_77 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_78 : output Q : Clock @@ -1949,15 +1949,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_78 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_78 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_79 : output Q : Clock @@ -1973,15 +1973,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_79 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_79 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_80 : output Q : Clock @@ -1997,15 +1997,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_80 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_80 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_81 : output Q : Clock @@ -2021,15 +2021,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_81 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_81 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_82 : output Q : Clock @@ -2045,15 +2045,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_82 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_82 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_83 : output Q : Clock @@ -2069,15 +2069,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_83 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_83 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_84 : output Q : Clock @@ -2093,15 +2093,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_84 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_84 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_85 : output Q : Clock @@ -2117,15 +2117,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_85 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_85 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_86 : output Q : Clock @@ -2141,15 +2141,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_86 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_86 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_87 : output Q : Clock @@ -2165,15 +2165,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_87 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_87 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_88 : output Q : Clock @@ -2189,15 +2189,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_88 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_88 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_89 : output Q : Clock @@ -2213,15 +2213,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_89 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_89 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_90 : output Q : Clock @@ -2237,15 +2237,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_90 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_90 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_91 : output Q : Clock @@ -2261,15 +2261,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_91 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_91 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_92 : output Q : Clock @@ -2285,15 +2285,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_92 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_92 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_93 : output Q : Clock @@ -2309,15 +2309,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_93 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_93 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] module ifu_mem_ctl : input clock : Clock @@ -2376,12 +2376,12 @@ circuit quasar_wrapper : ic_ignore_2nd_miss_f <= UInt<1>("h00") wire ic_debug_rd_en_ff : UInt<1> ic_debug_rd_en_ff <= UInt<1>("h00") - inst rvclkhdr of rvclkhdr @[el2_lib.scala 483:22] + inst rvclkhdr of rvclkhdr @[lib.scala 343:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr.io.en <= ic_debug_rd_en_ff @[el2_lib.scala 485:16] - rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr.io.clk <= clock @[lib.scala 344:17] + rvclkhdr.io.en <= ic_debug_rd_en_ff @[lib.scala 345:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] reg flush_final_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 90:53] flush_final_f <= io.exu_flush_final @[ifu_mem_ctl.scala 90:53] node _T = or(io.ifc_fetch_req_bf_raw, ifc_fetch_req_f) @[ifu_mem_ctl.scala 91:53] @@ -2389,18 +2389,18 @@ circuit quasar_wrapper : node _T_2 = or(_T_1, io.exu_flush_final) @[ifu_mem_ctl.scala 91:86] node fetch_bf_f_c1_clken = or(_T_2, scnd_miss_req) @[ifu_mem_ctl.scala 91:107] node debug_c1_clken = or(io.ic.debug_rd_en, io.ic.debug_wr_en) @[ifu_mem_ctl.scala 92:42] - inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 483:22] + inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 343:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_1.io.en <= debug_c1_clken @[el2_lib.scala 485:16] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 483:22] + rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_1.io.en <= debug_c1_clken @[lib.scala 345:16] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 343:22] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_2.io.en <= fetch_bf_f_c1_clken @[el2_lib.scala 485:16] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_2.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_2.io.en <= fetch_bf_f_c1_clken @[lib.scala 345:16] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 346:23] node _T_3 = orr(iccm_single_ecc_error) @[ifu_mem_ctl.scala 95:52] node _T_4 = bits(dma_iccm_req_f, 0, 0) @[ifu_mem_ctl.scala 95:78] node _T_5 = and(_T_3, _T_4) @[ifu_mem_ctl.scala 95:55] @@ -2846,12 +2846,12 @@ circuit quasar_wrapper : node miss_addr_in = mux(_T_304, _T_305, _T_308) @[ifu_mem_ctl.scala 219:25] node _T_309 = or(bus_ifu_bus_clk_en, ic_act_miss_f) @[ifu_mem_ctl.scala 221:57] node _T_310 = or(_T_309, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 221:73] - inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 483:22] + inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 343:22] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_3.io.en <= _T_310 @[el2_lib.scala 485:16] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_3.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_3.io.en <= _T_310 @[lib.scala 345:16] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 346:23] reg _T_311 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 222:48] _T_311 <= miss_addr_in @[ifu_mem_ctl.scala 222:48] miss_addr <= _T_311 @[ifu_mem_ctl.scala 222:13] @@ -2935,1256 +2935,1256 @@ circuit quasar_wrapper : ifu_bus_rdata_ff <= UInt<1>("h00") wire ic_miss_buff_half : UInt<64> ic_miss_buff_half <= UInt<1>("h00") - wire _T_353 : UInt<1>[35] @[el2_lib.scala 395:18] - wire _T_354 : UInt<1>[35] @[el2_lib.scala 396:18] - wire _T_355 : UInt<1>[35] @[el2_lib.scala 397:18] - wire _T_356 : UInt<1>[31] @[el2_lib.scala 398:18] - wire _T_357 : UInt<1>[31] @[el2_lib.scala 399:18] - wire _T_358 : UInt<1>[31] @[el2_lib.scala 400:18] - wire _T_359 : UInt<1>[7] @[el2_lib.scala 401:18] - node _T_360 = bits(ifu_bus_rdata_ff, 0, 0) @[el2_lib.scala 408:36] - _T_353[0] <= _T_360 @[el2_lib.scala 408:30] - node _T_361 = bits(ifu_bus_rdata_ff, 0, 0) @[el2_lib.scala 409:36] - _T_354[0] <= _T_361 @[el2_lib.scala 409:30] - node _T_362 = bits(ifu_bus_rdata_ff, 1, 1) @[el2_lib.scala 408:36] - _T_353[1] <= _T_362 @[el2_lib.scala 408:30] - node _T_363 = bits(ifu_bus_rdata_ff, 1, 1) @[el2_lib.scala 410:36] - _T_355[0] <= _T_363 @[el2_lib.scala 410:30] - node _T_364 = bits(ifu_bus_rdata_ff, 2, 2) @[el2_lib.scala 409:36] - _T_354[1] <= _T_364 @[el2_lib.scala 409:30] - node _T_365 = bits(ifu_bus_rdata_ff, 2, 2) @[el2_lib.scala 410:36] - _T_355[1] <= _T_365 @[el2_lib.scala 410:30] - node _T_366 = bits(ifu_bus_rdata_ff, 3, 3) @[el2_lib.scala 408:36] - _T_353[2] <= _T_366 @[el2_lib.scala 408:30] - node _T_367 = bits(ifu_bus_rdata_ff, 3, 3) @[el2_lib.scala 409:36] - _T_354[2] <= _T_367 @[el2_lib.scala 409:30] - node _T_368 = bits(ifu_bus_rdata_ff, 3, 3) @[el2_lib.scala 410:36] - _T_355[2] <= _T_368 @[el2_lib.scala 410:30] - node _T_369 = bits(ifu_bus_rdata_ff, 4, 4) @[el2_lib.scala 408:36] - _T_353[3] <= _T_369 @[el2_lib.scala 408:30] - node _T_370 = bits(ifu_bus_rdata_ff, 4, 4) @[el2_lib.scala 411:36] - _T_356[0] <= _T_370 @[el2_lib.scala 411:30] - node _T_371 = bits(ifu_bus_rdata_ff, 5, 5) @[el2_lib.scala 409:36] - _T_354[3] <= _T_371 @[el2_lib.scala 409:30] - node _T_372 = bits(ifu_bus_rdata_ff, 5, 5) @[el2_lib.scala 411:36] - _T_356[1] <= _T_372 @[el2_lib.scala 411:30] - node _T_373 = bits(ifu_bus_rdata_ff, 6, 6) @[el2_lib.scala 408:36] - _T_353[4] <= _T_373 @[el2_lib.scala 408:30] - node _T_374 = bits(ifu_bus_rdata_ff, 6, 6) @[el2_lib.scala 409:36] - _T_354[4] <= _T_374 @[el2_lib.scala 409:30] - node _T_375 = bits(ifu_bus_rdata_ff, 6, 6) @[el2_lib.scala 411:36] - _T_356[2] <= _T_375 @[el2_lib.scala 411:30] - node _T_376 = bits(ifu_bus_rdata_ff, 7, 7) @[el2_lib.scala 410:36] - _T_355[3] <= _T_376 @[el2_lib.scala 410:30] - node _T_377 = bits(ifu_bus_rdata_ff, 7, 7) @[el2_lib.scala 411:36] - _T_356[3] <= _T_377 @[el2_lib.scala 411:30] - node _T_378 = bits(ifu_bus_rdata_ff, 8, 8) @[el2_lib.scala 408:36] - _T_353[5] <= _T_378 @[el2_lib.scala 408:30] - node _T_379 = bits(ifu_bus_rdata_ff, 8, 8) @[el2_lib.scala 410:36] - _T_355[4] <= _T_379 @[el2_lib.scala 410:30] - node _T_380 = bits(ifu_bus_rdata_ff, 8, 8) @[el2_lib.scala 411:36] - _T_356[4] <= _T_380 @[el2_lib.scala 411:30] - node _T_381 = bits(ifu_bus_rdata_ff, 9, 9) @[el2_lib.scala 409:36] - _T_354[5] <= _T_381 @[el2_lib.scala 409:30] - node _T_382 = bits(ifu_bus_rdata_ff, 9, 9) @[el2_lib.scala 410:36] - _T_355[5] <= _T_382 @[el2_lib.scala 410:30] - node _T_383 = bits(ifu_bus_rdata_ff, 9, 9) @[el2_lib.scala 411:36] - _T_356[5] <= _T_383 @[el2_lib.scala 411:30] - node _T_384 = bits(ifu_bus_rdata_ff, 10, 10) @[el2_lib.scala 408:36] - _T_353[6] <= _T_384 @[el2_lib.scala 408:30] - node _T_385 = bits(ifu_bus_rdata_ff, 10, 10) @[el2_lib.scala 409:36] - _T_354[6] <= _T_385 @[el2_lib.scala 409:30] - node _T_386 = bits(ifu_bus_rdata_ff, 10, 10) @[el2_lib.scala 410:36] - _T_355[6] <= _T_386 @[el2_lib.scala 410:30] - node _T_387 = bits(ifu_bus_rdata_ff, 10, 10) @[el2_lib.scala 411:36] - _T_356[6] <= _T_387 @[el2_lib.scala 411:30] - node _T_388 = bits(ifu_bus_rdata_ff, 11, 11) @[el2_lib.scala 408:36] - _T_353[7] <= _T_388 @[el2_lib.scala 408:30] - node _T_389 = bits(ifu_bus_rdata_ff, 11, 11) @[el2_lib.scala 412:36] - _T_357[0] <= _T_389 @[el2_lib.scala 412:30] - node _T_390 = bits(ifu_bus_rdata_ff, 12, 12) @[el2_lib.scala 409:36] - _T_354[7] <= _T_390 @[el2_lib.scala 409:30] - node _T_391 = bits(ifu_bus_rdata_ff, 12, 12) @[el2_lib.scala 412:36] - _T_357[1] <= _T_391 @[el2_lib.scala 412:30] - node _T_392 = bits(ifu_bus_rdata_ff, 13, 13) @[el2_lib.scala 408:36] - _T_353[8] <= _T_392 @[el2_lib.scala 408:30] - node _T_393 = bits(ifu_bus_rdata_ff, 13, 13) @[el2_lib.scala 409:36] - _T_354[8] <= _T_393 @[el2_lib.scala 409:30] - node _T_394 = bits(ifu_bus_rdata_ff, 13, 13) @[el2_lib.scala 412:36] - _T_357[2] <= _T_394 @[el2_lib.scala 412:30] - node _T_395 = bits(ifu_bus_rdata_ff, 14, 14) @[el2_lib.scala 410:36] - _T_355[7] <= _T_395 @[el2_lib.scala 410:30] - node _T_396 = bits(ifu_bus_rdata_ff, 14, 14) @[el2_lib.scala 412:36] - _T_357[3] <= _T_396 @[el2_lib.scala 412:30] - node _T_397 = bits(ifu_bus_rdata_ff, 15, 15) @[el2_lib.scala 408:36] - _T_353[9] <= _T_397 @[el2_lib.scala 408:30] - node _T_398 = bits(ifu_bus_rdata_ff, 15, 15) @[el2_lib.scala 410:36] - _T_355[8] <= _T_398 @[el2_lib.scala 410:30] - node _T_399 = bits(ifu_bus_rdata_ff, 15, 15) @[el2_lib.scala 412:36] - _T_357[4] <= _T_399 @[el2_lib.scala 412:30] - node _T_400 = bits(ifu_bus_rdata_ff, 16, 16) @[el2_lib.scala 409:36] - _T_354[9] <= _T_400 @[el2_lib.scala 409:30] - node _T_401 = bits(ifu_bus_rdata_ff, 16, 16) @[el2_lib.scala 410:36] - _T_355[9] <= _T_401 @[el2_lib.scala 410:30] - node _T_402 = bits(ifu_bus_rdata_ff, 16, 16) @[el2_lib.scala 412:36] - _T_357[5] <= _T_402 @[el2_lib.scala 412:30] - node _T_403 = bits(ifu_bus_rdata_ff, 17, 17) @[el2_lib.scala 408:36] - _T_353[10] <= _T_403 @[el2_lib.scala 408:30] - node _T_404 = bits(ifu_bus_rdata_ff, 17, 17) @[el2_lib.scala 409:36] - _T_354[10] <= _T_404 @[el2_lib.scala 409:30] - node _T_405 = bits(ifu_bus_rdata_ff, 17, 17) @[el2_lib.scala 410:36] - _T_355[10] <= _T_405 @[el2_lib.scala 410:30] - node _T_406 = bits(ifu_bus_rdata_ff, 17, 17) @[el2_lib.scala 412:36] - _T_357[6] <= _T_406 @[el2_lib.scala 412:30] - node _T_407 = bits(ifu_bus_rdata_ff, 18, 18) @[el2_lib.scala 411:36] - _T_356[7] <= _T_407 @[el2_lib.scala 411:30] - node _T_408 = bits(ifu_bus_rdata_ff, 18, 18) @[el2_lib.scala 412:36] - _T_357[7] <= _T_408 @[el2_lib.scala 412:30] - node _T_409 = bits(ifu_bus_rdata_ff, 19, 19) @[el2_lib.scala 408:36] - _T_353[11] <= _T_409 @[el2_lib.scala 408:30] - node _T_410 = bits(ifu_bus_rdata_ff, 19, 19) @[el2_lib.scala 411:36] - _T_356[8] <= _T_410 @[el2_lib.scala 411:30] - node _T_411 = bits(ifu_bus_rdata_ff, 19, 19) @[el2_lib.scala 412:36] - _T_357[8] <= _T_411 @[el2_lib.scala 412:30] - node _T_412 = bits(ifu_bus_rdata_ff, 20, 20) @[el2_lib.scala 409:36] - _T_354[11] <= _T_412 @[el2_lib.scala 409:30] - node _T_413 = bits(ifu_bus_rdata_ff, 20, 20) @[el2_lib.scala 411:36] - _T_356[9] <= _T_413 @[el2_lib.scala 411:30] - node _T_414 = bits(ifu_bus_rdata_ff, 20, 20) @[el2_lib.scala 412:36] - _T_357[9] <= _T_414 @[el2_lib.scala 412:30] - node _T_415 = bits(ifu_bus_rdata_ff, 21, 21) @[el2_lib.scala 408:36] - _T_353[12] <= _T_415 @[el2_lib.scala 408:30] - node _T_416 = bits(ifu_bus_rdata_ff, 21, 21) @[el2_lib.scala 409:36] - _T_354[12] <= _T_416 @[el2_lib.scala 409:30] - node _T_417 = bits(ifu_bus_rdata_ff, 21, 21) @[el2_lib.scala 411:36] - _T_356[10] <= _T_417 @[el2_lib.scala 411:30] - node _T_418 = bits(ifu_bus_rdata_ff, 21, 21) @[el2_lib.scala 412:36] - _T_357[10] <= _T_418 @[el2_lib.scala 412:30] - node _T_419 = bits(ifu_bus_rdata_ff, 22, 22) @[el2_lib.scala 410:36] - _T_355[11] <= _T_419 @[el2_lib.scala 410:30] - node _T_420 = bits(ifu_bus_rdata_ff, 22, 22) @[el2_lib.scala 411:36] - _T_356[11] <= _T_420 @[el2_lib.scala 411:30] - node _T_421 = bits(ifu_bus_rdata_ff, 22, 22) @[el2_lib.scala 412:36] - _T_357[11] <= _T_421 @[el2_lib.scala 412:30] - node _T_422 = bits(ifu_bus_rdata_ff, 23, 23) @[el2_lib.scala 408:36] - _T_353[13] <= _T_422 @[el2_lib.scala 408:30] - node _T_423 = bits(ifu_bus_rdata_ff, 23, 23) @[el2_lib.scala 410:36] - _T_355[12] <= _T_423 @[el2_lib.scala 410:30] - node _T_424 = bits(ifu_bus_rdata_ff, 23, 23) @[el2_lib.scala 411:36] - _T_356[12] <= _T_424 @[el2_lib.scala 411:30] - node _T_425 = bits(ifu_bus_rdata_ff, 23, 23) @[el2_lib.scala 412:36] - _T_357[12] <= _T_425 @[el2_lib.scala 412:30] - node _T_426 = bits(ifu_bus_rdata_ff, 24, 24) @[el2_lib.scala 409:36] - _T_354[13] <= _T_426 @[el2_lib.scala 409:30] - node _T_427 = bits(ifu_bus_rdata_ff, 24, 24) @[el2_lib.scala 410:36] - _T_355[13] <= _T_427 @[el2_lib.scala 410:30] - node _T_428 = bits(ifu_bus_rdata_ff, 24, 24) @[el2_lib.scala 411:36] - _T_356[13] <= _T_428 @[el2_lib.scala 411:30] - node _T_429 = bits(ifu_bus_rdata_ff, 24, 24) @[el2_lib.scala 412:36] - _T_357[13] <= _T_429 @[el2_lib.scala 412:30] - node _T_430 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 408:36] - _T_353[14] <= _T_430 @[el2_lib.scala 408:30] - node _T_431 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 409:36] - _T_354[14] <= _T_431 @[el2_lib.scala 409:30] - node _T_432 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 410:36] - _T_355[14] <= _T_432 @[el2_lib.scala 410:30] - node _T_433 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 411:36] - _T_356[14] <= _T_433 @[el2_lib.scala 411:30] - node _T_434 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 412:36] - _T_357[14] <= _T_434 @[el2_lib.scala 412:30] - node _T_435 = bits(ifu_bus_rdata_ff, 26, 26) @[el2_lib.scala 408:36] - _T_353[15] <= _T_435 @[el2_lib.scala 408:30] - node _T_436 = bits(ifu_bus_rdata_ff, 26, 26) @[el2_lib.scala 413:36] - _T_358[0] <= _T_436 @[el2_lib.scala 413:30] - node _T_437 = bits(ifu_bus_rdata_ff, 27, 27) @[el2_lib.scala 409:36] - _T_354[15] <= _T_437 @[el2_lib.scala 409:30] - node _T_438 = bits(ifu_bus_rdata_ff, 27, 27) @[el2_lib.scala 413:36] - _T_358[1] <= _T_438 @[el2_lib.scala 413:30] - node _T_439 = bits(ifu_bus_rdata_ff, 28, 28) @[el2_lib.scala 408:36] - _T_353[16] <= _T_439 @[el2_lib.scala 408:30] - node _T_440 = bits(ifu_bus_rdata_ff, 28, 28) @[el2_lib.scala 409:36] - _T_354[16] <= _T_440 @[el2_lib.scala 409:30] - node _T_441 = bits(ifu_bus_rdata_ff, 28, 28) @[el2_lib.scala 413:36] - _T_358[2] <= _T_441 @[el2_lib.scala 413:30] - node _T_442 = bits(ifu_bus_rdata_ff, 29, 29) @[el2_lib.scala 410:36] - _T_355[15] <= _T_442 @[el2_lib.scala 410:30] - node _T_443 = bits(ifu_bus_rdata_ff, 29, 29) @[el2_lib.scala 413:36] - _T_358[3] <= _T_443 @[el2_lib.scala 413:30] - node _T_444 = bits(ifu_bus_rdata_ff, 30, 30) @[el2_lib.scala 408:36] - _T_353[17] <= _T_444 @[el2_lib.scala 408:30] - node _T_445 = bits(ifu_bus_rdata_ff, 30, 30) @[el2_lib.scala 410:36] - _T_355[16] <= _T_445 @[el2_lib.scala 410:30] - node _T_446 = bits(ifu_bus_rdata_ff, 30, 30) @[el2_lib.scala 413:36] - _T_358[4] <= _T_446 @[el2_lib.scala 413:30] - node _T_447 = bits(ifu_bus_rdata_ff, 31, 31) @[el2_lib.scala 409:36] - _T_354[17] <= _T_447 @[el2_lib.scala 409:30] - node _T_448 = bits(ifu_bus_rdata_ff, 31, 31) @[el2_lib.scala 410:36] - _T_355[17] <= _T_448 @[el2_lib.scala 410:30] - node _T_449 = bits(ifu_bus_rdata_ff, 31, 31) @[el2_lib.scala 413:36] - _T_358[5] <= _T_449 @[el2_lib.scala 413:30] - node _T_450 = bits(ifu_bus_rdata_ff, 32, 32) @[el2_lib.scala 408:36] - _T_353[18] <= _T_450 @[el2_lib.scala 408:30] - node _T_451 = bits(ifu_bus_rdata_ff, 32, 32) @[el2_lib.scala 409:36] - _T_354[18] <= _T_451 @[el2_lib.scala 409:30] - node _T_452 = bits(ifu_bus_rdata_ff, 32, 32) @[el2_lib.scala 410:36] - _T_355[18] <= _T_452 @[el2_lib.scala 410:30] - node _T_453 = bits(ifu_bus_rdata_ff, 32, 32) @[el2_lib.scala 413:36] - _T_358[6] <= _T_453 @[el2_lib.scala 413:30] - node _T_454 = bits(ifu_bus_rdata_ff, 33, 33) @[el2_lib.scala 411:36] - _T_356[15] <= _T_454 @[el2_lib.scala 411:30] - node _T_455 = bits(ifu_bus_rdata_ff, 33, 33) @[el2_lib.scala 413:36] - _T_358[7] <= _T_455 @[el2_lib.scala 413:30] - node _T_456 = bits(ifu_bus_rdata_ff, 34, 34) @[el2_lib.scala 408:36] - _T_353[19] <= _T_456 @[el2_lib.scala 408:30] - node _T_457 = bits(ifu_bus_rdata_ff, 34, 34) @[el2_lib.scala 411:36] - _T_356[16] <= _T_457 @[el2_lib.scala 411:30] - node _T_458 = bits(ifu_bus_rdata_ff, 34, 34) @[el2_lib.scala 413:36] - _T_358[8] <= _T_458 @[el2_lib.scala 413:30] - node _T_459 = bits(ifu_bus_rdata_ff, 35, 35) @[el2_lib.scala 409:36] - _T_354[19] <= _T_459 @[el2_lib.scala 409:30] - node _T_460 = bits(ifu_bus_rdata_ff, 35, 35) @[el2_lib.scala 411:36] - _T_356[17] <= _T_460 @[el2_lib.scala 411:30] - node _T_461 = bits(ifu_bus_rdata_ff, 35, 35) @[el2_lib.scala 413:36] - _T_358[9] <= _T_461 @[el2_lib.scala 413:30] - node _T_462 = bits(ifu_bus_rdata_ff, 36, 36) @[el2_lib.scala 408:36] - _T_353[20] <= _T_462 @[el2_lib.scala 408:30] - node _T_463 = bits(ifu_bus_rdata_ff, 36, 36) @[el2_lib.scala 409:36] - _T_354[20] <= _T_463 @[el2_lib.scala 409:30] - node _T_464 = bits(ifu_bus_rdata_ff, 36, 36) @[el2_lib.scala 411:36] - _T_356[18] <= _T_464 @[el2_lib.scala 411:30] - node _T_465 = bits(ifu_bus_rdata_ff, 36, 36) @[el2_lib.scala 413:36] - _T_358[10] <= _T_465 @[el2_lib.scala 413:30] - node _T_466 = bits(ifu_bus_rdata_ff, 37, 37) @[el2_lib.scala 410:36] - _T_355[19] <= _T_466 @[el2_lib.scala 410:30] - node _T_467 = bits(ifu_bus_rdata_ff, 37, 37) @[el2_lib.scala 411:36] - _T_356[19] <= _T_467 @[el2_lib.scala 411:30] - node _T_468 = bits(ifu_bus_rdata_ff, 37, 37) @[el2_lib.scala 413:36] - _T_358[11] <= _T_468 @[el2_lib.scala 413:30] - node _T_469 = bits(ifu_bus_rdata_ff, 38, 38) @[el2_lib.scala 408:36] - _T_353[21] <= _T_469 @[el2_lib.scala 408:30] - node _T_470 = bits(ifu_bus_rdata_ff, 38, 38) @[el2_lib.scala 410:36] - _T_355[20] <= _T_470 @[el2_lib.scala 410:30] - node _T_471 = bits(ifu_bus_rdata_ff, 38, 38) @[el2_lib.scala 411:36] - _T_356[20] <= _T_471 @[el2_lib.scala 411:30] - node _T_472 = bits(ifu_bus_rdata_ff, 38, 38) @[el2_lib.scala 413:36] - _T_358[12] <= _T_472 @[el2_lib.scala 413:30] - node _T_473 = bits(ifu_bus_rdata_ff, 39, 39) @[el2_lib.scala 409:36] - _T_354[21] <= _T_473 @[el2_lib.scala 409:30] - node _T_474 = bits(ifu_bus_rdata_ff, 39, 39) @[el2_lib.scala 410:36] - _T_355[21] <= _T_474 @[el2_lib.scala 410:30] - node _T_475 = bits(ifu_bus_rdata_ff, 39, 39) @[el2_lib.scala 411:36] - _T_356[21] <= _T_475 @[el2_lib.scala 411:30] - node _T_476 = bits(ifu_bus_rdata_ff, 39, 39) @[el2_lib.scala 413:36] - _T_358[13] <= _T_476 @[el2_lib.scala 413:30] - node _T_477 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 408:36] - _T_353[22] <= _T_477 @[el2_lib.scala 408:30] - node _T_478 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 409:36] - _T_354[22] <= _T_478 @[el2_lib.scala 409:30] - node _T_479 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 410:36] - _T_355[22] <= _T_479 @[el2_lib.scala 410:30] - node _T_480 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 411:36] - _T_356[22] <= _T_480 @[el2_lib.scala 411:30] - node _T_481 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 413:36] - _T_358[14] <= _T_481 @[el2_lib.scala 413:30] - node _T_482 = bits(ifu_bus_rdata_ff, 41, 41) @[el2_lib.scala 412:36] - _T_357[15] <= _T_482 @[el2_lib.scala 412:30] - node _T_483 = bits(ifu_bus_rdata_ff, 41, 41) @[el2_lib.scala 413:36] - _T_358[15] <= _T_483 @[el2_lib.scala 413:30] - node _T_484 = bits(ifu_bus_rdata_ff, 42, 42) @[el2_lib.scala 408:36] - _T_353[23] <= _T_484 @[el2_lib.scala 408:30] - node _T_485 = bits(ifu_bus_rdata_ff, 42, 42) @[el2_lib.scala 412:36] - _T_357[16] <= _T_485 @[el2_lib.scala 412:30] - node _T_486 = bits(ifu_bus_rdata_ff, 42, 42) @[el2_lib.scala 413:36] - _T_358[16] <= _T_486 @[el2_lib.scala 413:30] - node _T_487 = bits(ifu_bus_rdata_ff, 43, 43) @[el2_lib.scala 409:36] - _T_354[23] <= _T_487 @[el2_lib.scala 409:30] - node _T_488 = bits(ifu_bus_rdata_ff, 43, 43) @[el2_lib.scala 412:36] - _T_357[17] <= _T_488 @[el2_lib.scala 412:30] - node _T_489 = bits(ifu_bus_rdata_ff, 43, 43) @[el2_lib.scala 413:36] - _T_358[17] <= _T_489 @[el2_lib.scala 413:30] - node _T_490 = bits(ifu_bus_rdata_ff, 44, 44) @[el2_lib.scala 408:36] - _T_353[24] <= _T_490 @[el2_lib.scala 408:30] - node _T_491 = bits(ifu_bus_rdata_ff, 44, 44) @[el2_lib.scala 409:36] - _T_354[24] <= _T_491 @[el2_lib.scala 409:30] - node _T_492 = bits(ifu_bus_rdata_ff, 44, 44) @[el2_lib.scala 412:36] - _T_357[18] <= _T_492 @[el2_lib.scala 412:30] - node _T_493 = bits(ifu_bus_rdata_ff, 44, 44) @[el2_lib.scala 413:36] - _T_358[18] <= _T_493 @[el2_lib.scala 413:30] - node _T_494 = bits(ifu_bus_rdata_ff, 45, 45) @[el2_lib.scala 410:36] - _T_355[23] <= _T_494 @[el2_lib.scala 410:30] - node _T_495 = bits(ifu_bus_rdata_ff, 45, 45) @[el2_lib.scala 412:36] - _T_357[19] <= _T_495 @[el2_lib.scala 412:30] - node _T_496 = bits(ifu_bus_rdata_ff, 45, 45) @[el2_lib.scala 413:36] - _T_358[19] <= _T_496 @[el2_lib.scala 413:30] - node _T_497 = bits(ifu_bus_rdata_ff, 46, 46) @[el2_lib.scala 408:36] - _T_353[25] <= _T_497 @[el2_lib.scala 408:30] - node _T_498 = bits(ifu_bus_rdata_ff, 46, 46) @[el2_lib.scala 410:36] - _T_355[24] <= _T_498 @[el2_lib.scala 410:30] - node _T_499 = bits(ifu_bus_rdata_ff, 46, 46) @[el2_lib.scala 412:36] - _T_357[20] <= _T_499 @[el2_lib.scala 412:30] - node _T_500 = bits(ifu_bus_rdata_ff, 46, 46) @[el2_lib.scala 413:36] - _T_358[20] <= _T_500 @[el2_lib.scala 413:30] - node _T_501 = bits(ifu_bus_rdata_ff, 47, 47) @[el2_lib.scala 409:36] - _T_354[25] <= _T_501 @[el2_lib.scala 409:30] - node _T_502 = bits(ifu_bus_rdata_ff, 47, 47) @[el2_lib.scala 410:36] - _T_355[25] <= _T_502 @[el2_lib.scala 410:30] - node _T_503 = bits(ifu_bus_rdata_ff, 47, 47) @[el2_lib.scala 412:36] - _T_357[21] <= _T_503 @[el2_lib.scala 412:30] - node _T_504 = bits(ifu_bus_rdata_ff, 47, 47) @[el2_lib.scala 413:36] - _T_358[21] <= _T_504 @[el2_lib.scala 413:30] - node _T_505 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 408:36] - _T_353[26] <= _T_505 @[el2_lib.scala 408:30] - node _T_506 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 409:36] - _T_354[26] <= _T_506 @[el2_lib.scala 409:30] - node _T_507 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 410:36] - _T_355[26] <= _T_507 @[el2_lib.scala 410:30] - node _T_508 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 412:36] - _T_357[22] <= _T_508 @[el2_lib.scala 412:30] - node _T_509 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 413:36] - _T_358[22] <= _T_509 @[el2_lib.scala 413:30] - node _T_510 = bits(ifu_bus_rdata_ff, 49, 49) @[el2_lib.scala 411:36] - _T_356[23] <= _T_510 @[el2_lib.scala 411:30] - node _T_511 = bits(ifu_bus_rdata_ff, 49, 49) @[el2_lib.scala 412:36] - _T_357[23] <= _T_511 @[el2_lib.scala 412:30] - node _T_512 = bits(ifu_bus_rdata_ff, 49, 49) @[el2_lib.scala 413:36] - _T_358[23] <= _T_512 @[el2_lib.scala 413:30] - node _T_513 = bits(ifu_bus_rdata_ff, 50, 50) @[el2_lib.scala 408:36] - _T_353[27] <= _T_513 @[el2_lib.scala 408:30] - node _T_514 = bits(ifu_bus_rdata_ff, 50, 50) @[el2_lib.scala 411:36] - _T_356[24] <= _T_514 @[el2_lib.scala 411:30] - node _T_515 = bits(ifu_bus_rdata_ff, 50, 50) @[el2_lib.scala 412:36] - _T_357[24] <= _T_515 @[el2_lib.scala 412:30] - node _T_516 = bits(ifu_bus_rdata_ff, 50, 50) @[el2_lib.scala 413:36] - _T_358[24] <= _T_516 @[el2_lib.scala 413:30] - node _T_517 = bits(ifu_bus_rdata_ff, 51, 51) @[el2_lib.scala 409:36] - _T_354[27] <= _T_517 @[el2_lib.scala 409:30] - node _T_518 = bits(ifu_bus_rdata_ff, 51, 51) @[el2_lib.scala 411:36] - _T_356[25] <= _T_518 @[el2_lib.scala 411:30] - node _T_519 = bits(ifu_bus_rdata_ff, 51, 51) @[el2_lib.scala 412:36] - _T_357[25] <= _T_519 @[el2_lib.scala 412:30] - node _T_520 = bits(ifu_bus_rdata_ff, 51, 51) @[el2_lib.scala 413:36] - _T_358[25] <= _T_520 @[el2_lib.scala 413:30] - node _T_521 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 408:36] - _T_353[28] <= _T_521 @[el2_lib.scala 408:30] - node _T_522 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 409:36] - _T_354[28] <= _T_522 @[el2_lib.scala 409:30] - node _T_523 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 411:36] - _T_356[26] <= _T_523 @[el2_lib.scala 411:30] - node _T_524 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 412:36] - _T_357[26] <= _T_524 @[el2_lib.scala 412:30] - node _T_525 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 413:36] - _T_358[26] <= _T_525 @[el2_lib.scala 413:30] - node _T_526 = bits(ifu_bus_rdata_ff, 53, 53) @[el2_lib.scala 410:36] - _T_355[27] <= _T_526 @[el2_lib.scala 410:30] - node _T_527 = bits(ifu_bus_rdata_ff, 53, 53) @[el2_lib.scala 411:36] - _T_356[27] <= _T_527 @[el2_lib.scala 411:30] - node _T_528 = bits(ifu_bus_rdata_ff, 53, 53) @[el2_lib.scala 412:36] - _T_357[27] <= _T_528 @[el2_lib.scala 412:30] - node _T_529 = bits(ifu_bus_rdata_ff, 53, 53) @[el2_lib.scala 413:36] - _T_358[27] <= _T_529 @[el2_lib.scala 413:30] - node _T_530 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 408:36] - _T_353[29] <= _T_530 @[el2_lib.scala 408:30] - node _T_531 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 410:36] - _T_355[28] <= _T_531 @[el2_lib.scala 410:30] - node _T_532 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 411:36] - _T_356[28] <= _T_532 @[el2_lib.scala 411:30] - node _T_533 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 412:36] - _T_357[28] <= _T_533 @[el2_lib.scala 412:30] - node _T_534 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 413:36] - _T_358[28] <= _T_534 @[el2_lib.scala 413:30] - node _T_535 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 409:36] - _T_354[29] <= _T_535 @[el2_lib.scala 409:30] - node _T_536 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 410:36] - _T_355[29] <= _T_536 @[el2_lib.scala 410:30] - node _T_537 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 411:36] - _T_356[29] <= _T_537 @[el2_lib.scala 411:30] - node _T_538 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 412:36] - _T_357[29] <= _T_538 @[el2_lib.scala 412:30] - node _T_539 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 413:36] - _T_358[29] <= _T_539 @[el2_lib.scala 413:30] - node _T_540 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 408:36] - _T_353[30] <= _T_540 @[el2_lib.scala 408:30] - node _T_541 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 409:36] - _T_354[30] <= _T_541 @[el2_lib.scala 409:30] - node _T_542 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 410:36] - _T_355[30] <= _T_542 @[el2_lib.scala 410:30] - node _T_543 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 411:36] - _T_356[30] <= _T_543 @[el2_lib.scala 411:30] - node _T_544 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 412:36] - _T_357[30] <= _T_544 @[el2_lib.scala 412:30] - node _T_545 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 413:36] - _T_358[30] <= _T_545 @[el2_lib.scala 413:30] - node _T_546 = bits(ifu_bus_rdata_ff, 57, 57) @[el2_lib.scala 408:36] - _T_353[31] <= _T_546 @[el2_lib.scala 408:30] - node _T_547 = bits(ifu_bus_rdata_ff, 57, 57) @[el2_lib.scala 414:36] - _T_359[0] <= _T_547 @[el2_lib.scala 414:30] - node _T_548 = bits(ifu_bus_rdata_ff, 58, 58) @[el2_lib.scala 409:36] - _T_354[31] <= _T_548 @[el2_lib.scala 409:30] - node _T_549 = bits(ifu_bus_rdata_ff, 58, 58) @[el2_lib.scala 414:36] - _T_359[1] <= _T_549 @[el2_lib.scala 414:30] - node _T_550 = bits(ifu_bus_rdata_ff, 59, 59) @[el2_lib.scala 408:36] - _T_353[32] <= _T_550 @[el2_lib.scala 408:30] - node _T_551 = bits(ifu_bus_rdata_ff, 59, 59) @[el2_lib.scala 409:36] - _T_354[32] <= _T_551 @[el2_lib.scala 409:30] - node _T_552 = bits(ifu_bus_rdata_ff, 59, 59) @[el2_lib.scala 414:36] - _T_359[2] <= _T_552 @[el2_lib.scala 414:30] - node _T_553 = bits(ifu_bus_rdata_ff, 60, 60) @[el2_lib.scala 410:36] - _T_355[31] <= _T_553 @[el2_lib.scala 410:30] - node _T_554 = bits(ifu_bus_rdata_ff, 60, 60) @[el2_lib.scala 414:36] - _T_359[3] <= _T_554 @[el2_lib.scala 414:30] - node _T_555 = bits(ifu_bus_rdata_ff, 61, 61) @[el2_lib.scala 408:36] - _T_353[33] <= _T_555 @[el2_lib.scala 408:30] - node _T_556 = bits(ifu_bus_rdata_ff, 61, 61) @[el2_lib.scala 410:36] - _T_355[32] <= _T_556 @[el2_lib.scala 410:30] - node _T_557 = bits(ifu_bus_rdata_ff, 61, 61) @[el2_lib.scala 414:36] - _T_359[4] <= _T_557 @[el2_lib.scala 414:30] - node _T_558 = bits(ifu_bus_rdata_ff, 62, 62) @[el2_lib.scala 409:36] - _T_354[33] <= _T_558 @[el2_lib.scala 409:30] - node _T_559 = bits(ifu_bus_rdata_ff, 62, 62) @[el2_lib.scala 410:36] - _T_355[33] <= _T_559 @[el2_lib.scala 410:30] - node _T_560 = bits(ifu_bus_rdata_ff, 62, 62) @[el2_lib.scala 414:36] - _T_359[5] <= _T_560 @[el2_lib.scala 414:30] - node _T_561 = bits(ifu_bus_rdata_ff, 63, 63) @[el2_lib.scala 408:36] - _T_353[34] <= _T_561 @[el2_lib.scala 408:30] - node _T_562 = bits(ifu_bus_rdata_ff, 63, 63) @[el2_lib.scala 409:36] - _T_354[34] <= _T_562 @[el2_lib.scala 409:30] - node _T_563 = bits(ifu_bus_rdata_ff, 63, 63) @[el2_lib.scala 410:36] - _T_355[34] <= _T_563 @[el2_lib.scala 410:30] - node _T_564 = bits(ifu_bus_rdata_ff, 63, 63) @[el2_lib.scala 414:36] - _T_359[6] <= _T_564 @[el2_lib.scala 414:30] - node _T_565 = cat(_T_359[2], _T_359[1]) @[el2_lib.scala 416:13] - node _T_566 = cat(_T_565, _T_359[0]) @[el2_lib.scala 416:13] - node _T_567 = cat(_T_359[4], _T_359[3]) @[el2_lib.scala 416:13] - node _T_568 = cat(_T_359[6], _T_359[5]) @[el2_lib.scala 416:13] - node _T_569 = cat(_T_568, _T_567) @[el2_lib.scala 416:13] - node _T_570 = cat(_T_569, _T_566) @[el2_lib.scala 416:13] - node _T_571 = xorr(_T_570) @[el2_lib.scala 416:20] - node _T_572 = cat(_T_358[2], _T_358[1]) @[el2_lib.scala 416:30] - node _T_573 = cat(_T_572, _T_358[0]) @[el2_lib.scala 416:30] - node _T_574 = cat(_T_358[4], _T_358[3]) @[el2_lib.scala 416:30] - node _T_575 = cat(_T_358[6], _T_358[5]) @[el2_lib.scala 416:30] - node _T_576 = cat(_T_575, _T_574) @[el2_lib.scala 416:30] - node _T_577 = cat(_T_576, _T_573) @[el2_lib.scala 416:30] - node _T_578 = cat(_T_358[8], _T_358[7]) @[el2_lib.scala 416:30] - node _T_579 = cat(_T_358[10], _T_358[9]) @[el2_lib.scala 416:30] - node _T_580 = cat(_T_579, _T_578) @[el2_lib.scala 416:30] - node _T_581 = cat(_T_358[12], _T_358[11]) @[el2_lib.scala 416:30] - node _T_582 = cat(_T_358[14], _T_358[13]) @[el2_lib.scala 416:30] - node _T_583 = cat(_T_582, _T_581) @[el2_lib.scala 416:30] - node _T_584 = cat(_T_583, _T_580) @[el2_lib.scala 416:30] - node _T_585 = cat(_T_584, _T_577) @[el2_lib.scala 416:30] - node _T_586 = cat(_T_358[16], _T_358[15]) @[el2_lib.scala 416:30] - node _T_587 = cat(_T_358[18], _T_358[17]) @[el2_lib.scala 416:30] - node _T_588 = cat(_T_587, _T_586) @[el2_lib.scala 416:30] - node _T_589 = cat(_T_358[20], _T_358[19]) @[el2_lib.scala 416:30] - node _T_590 = cat(_T_358[22], _T_358[21]) @[el2_lib.scala 416:30] - node _T_591 = cat(_T_590, _T_589) @[el2_lib.scala 416:30] - node _T_592 = cat(_T_591, _T_588) @[el2_lib.scala 416:30] - node _T_593 = cat(_T_358[24], _T_358[23]) @[el2_lib.scala 416:30] - node _T_594 = cat(_T_358[26], _T_358[25]) @[el2_lib.scala 416:30] - node _T_595 = cat(_T_594, _T_593) @[el2_lib.scala 416:30] - node _T_596 = cat(_T_358[28], _T_358[27]) @[el2_lib.scala 416:30] - node _T_597 = cat(_T_358[30], _T_358[29]) @[el2_lib.scala 416:30] - node _T_598 = cat(_T_597, _T_596) @[el2_lib.scala 416:30] - node _T_599 = cat(_T_598, _T_595) @[el2_lib.scala 416:30] - node _T_600 = cat(_T_599, _T_592) @[el2_lib.scala 416:30] - node _T_601 = cat(_T_600, _T_585) @[el2_lib.scala 416:30] - node _T_602 = xorr(_T_601) @[el2_lib.scala 416:37] - node _T_603 = cat(_T_357[2], _T_357[1]) @[el2_lib.scala 416:47] - node _T_604 = cat(_T_603, _T_357[0]) @[el2_lib.scala 416:47] - node _T_605 = cat(_T_357[4], _T_357[3]) @[el2_lib.scala 416:47] - node _T_606 = cat(_T_357[6], _T_357[5]) @[el2_lib.scala 416:47] - node _T_607 = cat(_T_606, _T_605) @[el2_lib.scala 416:47] - node _T_608 = cat(_T_607, _T_604) @[el2_lib.scala 416:47] - node _T_609 = cat(_T_357[8], _T_357[7]) @[el2_lib.scala 416:47] - node _T_610 = cat(_T_357[10], _T_357[9]) @[el2_lib.scala 416:47] - node _T_611 = cat(_T_610, _T_609) @[el2_lib.scala 416:47] - node _T_612 = cat(_T_357[12], _T_357[11]) @[el2_lib.scala 416:47] - node _T_613 = cat(_T_357[14], _T_357[13]) @[el2_lib.scala 416:47] - node _T_614 = cat(_T_613, _T_612) @[el2_lib.scala 416:47] - node _T_615 = cat(_T_614, _T_611) @[el2_lib.scala 416:47] - node _T_616 = cat(_T_615, _T_608) @[el2_lib.scala 416:47] - node _T_617 = cat(_T_357[16], _T_357[15]) @[el2_lib.scala 416:47] - node _T_618 = cat(_T_357[18], _T_357[17]) @[el2_lib.scala 416:47] - node _T_619 = cat(_T_618, _T_617) @[el2_lib.scala 416:47] - node _T_620 = cat(_T_357[20], _T_357[19]) @[el2_lib.scala 416:47] - node _T_621 = cat(_T_357[22], _T_357[21]) @[el2_lib.scala 416:47] - node _T_622 = cat(_T_621, _T_620) @[el2_lib.scala 416:47] - node _T_623 = cat(_T_622, _T_619) @[el2_lib.scala 416:47] - node _T_624 = cat(_T_357[24], _T_357[23]) @[el2_lib.scala 416:47] - node _T_625 = cat(_T_357[26], _T_357[25]) @[el2_lib.scala 416:47] - node _T_626 = cat(_T_625, _T_624) @[el2_lib.scala 416:47] - node _T_627 = cat(_T_357[28], _T_357[27]) @[el2_lib.scala 416:47] - node _T_628 = cat(_T_357[30], _T_357[29]) @[el2_lib.scala 416:47] - node _T_629 = cat(_T_628, _T_627) @[el2_lib.scala 416:47] - node _T_630 = cat(_T_629, _T_626) @[el2_lib.scala 416:47] - node _T_631 = cat(_T_630, _T_623) @[el2_lib.scala 416:47] - node _T_632 = cat(_T_631, _T_616) @[el2_lib.scala 416:47] - node _T_633 = xorr(_T_632) @[el2_lib.scala 416:54] - node _T_634 = cat(_T_356[2], _T_356[1]) @[el2_lib.scala 416:64] - node _T_635 = cat(_T_634, _T_356[0]) @[el2_lib.scala 416:64] - node _T_636 = cat(_T_356[4], _T_356[3]) @[el2_lib.scala 416:64] - node _T_637 = cat(_T_356[6], _T_356[5]) @[el2_lib.scala 416:64] - node _T_638 = cat(_T_637, _T_636) @[el2_lib.scala 416:64] - node _T_639 = cat(_T_638, _T_635) @[el2_lib.scala 416:64] - node _T_640 = cat(_T_356[8], _T_356[7]) @[el2_lib.scala 416:64] - node _T_641 = cat(_T_356[10], _T_356[9]) @[el2_lib.scala 416:64] - node _T_642 = cat(_T_641, _T_640) @[el2_lib.scala 416:64] - node _T_643 = cat(_T_356[12], _T_356[11]) @[el2_lib.scala 416:64] - node _T_644 = cat(_T_356[14], _T_356[13]) @[el2_lib.scala 416:64] - node _T_645 = cat(_T_644, _T_643) @[el2_lib.scala 416:64] - node _T_646 = cat(_T_645, _T_642) @[el2_lib.scala 416:64] - node _T_647 = cat(_T_646, _T_639) @[el2_lib.scala 416:64] - node _T_648 = cat(_T_356[16], _T_356[15]) @[el2_lib.scala 416:64] - node _T_649 = cat(_T_356[18], _T_356[17]) @[el2_lib.scala 416:64] - node _T_650 = cat(_T_649, _T_648) @[el2_lib.scala 416:64] - node _T_651 = cat(_T_356[20], _T_356[19]) @[el2_lib.scala 416:64] - node _T_652 = cat(_T_356[22], _T_356[21]) @[el2_lib.scala 416:64] - node _T_653 = cat(_T_652, _T_651) @[el2_lib.scala 416:64] - node _T_654 = cat(_T_653, _T_650) @[el2_lib.scala 416:64] - node _T_655 = cat(_T_356[24], _T_356[23]) @[el2_lib.scala 416:64] - node _T_656 = cat(_T_356[26], _T_356[25]) @[el2_lib.scala 416:64] - node _T_657 = cat(_T_656, _T_655) @[el2_lib.scala 416:64] - node _T_658 = cat(_T_356[28], _T_356[27]) @[el2_lib.scala 416:64] - node _T_659 = cat(_T_356[30], _T_356[29]) @[el2_lib.scala 416:64] - node _T_660 = cat(_T_659, _T_658) @[el2_lib.scala 416:64] - node _T_661 = cat(_T_660, _T_657) @[el2_lib.scala 416:64] - node _T_662 = cat(_T_661, _T_654) @[el2_lib.scala 416:64] - node _T_663 = cat(_T_662, _T_647) @[el2_lib.scala 416:64] - node _T_664 = xorr(_T_663) @[el2_lib.scala 416:71] - node _T_665 = cat(_T_355[1], _T_355[0]) @[el2_lib.scala 416:81] - node _T_666 = cat(_T_355[3], _T_355[2]) @[el2_lib.scala 416:81] - node _T_667 = cat(_T_666, _T_665) @[el2_lib.scala 416:81] - node _T_668 = cat(_T_355[5], _T_355[4]) @[el2_lib.scala 416:81] - node _T_669 = cat(_T_355[7], _T_355[6]) @[el2_lib.scala 416:81] - node _T_670 = cat(_T_669, _T_668) @[el2_lib.scala 416:81] - node _T_671 = cat(_T_670, _T_667) @[el2_lib.scala 416:81] - node _T_672 = cat(_T_355[9], _T_355[8]) @[el2_lib.scala 416:81] - node _T_673 = cat(_T_355[11], _T_355[10]) @[el2_lib.scala 416:81] - node _T_674 = cat(_T_673, _T_672) @[el2_lib.scala 416:81] - node _T_675 = cat(_T_355[13], _T_355[12]) @[el2_lib.scala 416:81] - node _T_676 = cat(_T_355[16], _T_355[15]) @[el2_lib.scala 416:81] - node _T_677 = cat(_T_676, _T_355[14]) @[el2_lib.scala 416:81] - node _T_678 = cat(_T_677, _T_675) @[el2_lib.scala 416:81] - node _T_679 = cat(_T_678, _T_674) @[el2_lib.scala 416:81] - node _T_680 = cat(_T_679, _T_671) @[el2_lib.scala 416:81] - node _T_681 = cat(_T_355[18], _T_355[17]) @[el2_lib.scala 416:81] - node _T_682 = cat(_T_355[20], _T_355[19]) @[el2_lib.scala 416:81] - node _T_683 = cat(_T_682, _T_681) @[el2_lib.scala 416:81] - node _T_684 = cat(_T_355[22], _T_355[21]) @[el2_lib.scala 416:81] - node _T_685 = cat(_T_355[25], _T_355[24]) @[el2_lib.scala 416:81] - node _T_686 = cat(_T_685, _T_355[23]) @[el2_lib.scala 416:81] - node _T_687 = cat(_T_686, _T_684) @[el2_lib.scala 416:81] - node _T_688 = cat(_T_687, _T_683) @[el2_lib.scala 416:81] - node _T_689 = cat(_T_355[27], _T_355[26]) @[el2_lib.scala 416:81] - node _T_690 = cat(_T_355[29], _T_355[28]) @[el2_lib.scala 416:81] - node _T_691 = cat(_T_690, _T_689) @[el2_lib.scala 416:81] - node _T_692 = cat(_T_355[31], _T_355[30]) @[el2_lib.scala 416:81] - node _T_693 = cat(_T_355[34], _T_355[33]) @[el2_lib.scala 416:81] - node _T_694 = cat(_T_693, _T_355[32]) @[el2_lib.scala 416:81] - node _T_695 = cat(_T_694, _T_692) @[el2_lib.scala 416:81] - node _T_696 = cat(_T_695, _T_691) @[el2_lib.scala 416:81] - node _T_697 = cat(_T_696, _T_688) @[el2_lib.scala 416:81] - node _T_698 = cat(_T_697, _T_680) @[el2_lib.scala 416:81] - node _T_699 = xorr(_T_698) @[el2_lib.scala 416:88] - node _T_700 = cat(_T_354[1], _T_354[0]) @[el2_lib.scala 416:98] - node _T_701 = cat(_T_354[3], _T_354[2]) @[el2_lib.scala 416:98] - node _T_702 = cat(_T_701, _T_700) @[el2_lib.scala 416:98] - node _T_703 = cat(_T_354[5], _T_354[4]) @[el2_lib.scala 416:98] - node _T_704 = cat(_T_354[7], _T_354[6]) @[el2_lib.scala 416:98] - node _T_705 = cat(_T_704, _T_703) @[el2_lib.scala 416:98] - node _T_706 = cat(_T_705, _T_702) @[el2_lib.scala 416:98] - node _T_707 = cat(_T_354[9], _T_354[8]) @[el2_lib.scala 416:98] - node _T_708 = cat(_T_354[11], _T_354[10]) @[el2_lib.scala 416:98] - node _T_709 = cat(_T_708, _T_707) @[el2_lib.scala 416:98] - node _T_710 = cat(_T_354[13], _T_354[12]) @[el2_lib.scala 416:98] - node _T_711 = cat(_T_354[16], _T_354[15]) @[el2_lib.scala 416:98] - node _T_712 = cat(_T_711, _T_354[14]) @[el2_lib.scala 416:98] - node _T_713 = cat(_T_712, _T_710) @[el2_lib.scala 416:98] - node _T_714 = cat(_T_713, _T_709) @[el2_lib.scala 416:98] - node _T_715 = cat(_T_714, _T_706) @[el2_lib.scala 416:98] - node _T_716 = cat(_T_354[18], _T_354[17]) @[el2_lib.scala 416:98] - node _T_717 = cat(_T_354[20], _T_354[19]) @[el2_lib.scala 416:98] - node _T_718 = cat(_T_717, _T_716) @[el2_lib.scala 416:98] - node _T_719 = cat(_T_354[22], _T_354[21]) @[el2_lib.scala 416:98] - node _T_720 = cat(_T_354[25], _T_354[24]) @[el2_lib.scala 416:98] - node _T_721 = cat(_T_720, _T_354[23]) @[el2_lib.scala 416:98] - node _T_722 = cat(_T_721, _T_719) @[el2_lib.scala 416:98] - node _T_723 = cat(_T_722, _T_718) @[el2_lib.scala 416:98] - node _T_724 = cat(_T_354[27], _T_354[26]) @[el2_lib.scala 416:98] - node _T_725 = cat(_T_354[29], _T_354[28]) @[el2_lib.scala 416:98] - node _T_726 = cat(_T_725, _T_724) @[el2_lib.scala 416:98] - node _T_727 = cat(_T_354[31], _T_354[30]) @[el2_lib.scala 416:98] - node _T_728 = cat(_T_354[34], _T_354[33]) @[el2_lib.scala 416:98] - node _T_729 = cat(_T_728, _T_354[32]) @[el2_lib.scala 416:98] - node _T_730 = cat(_T_729, _T_727) @[el2_lib.scala 416:98] - node _T_731 = cat(_T_730, _T_726) @[el2_lib.scala 416:98] - node _T_732 = cat(_T_731, _T_723) @[el2_lib.scala 416:98] - node _T_733 = cat(_T_732, _T_715) @[el2_lib.scala 416:98] - node _T_734 = xorr(_T_733) @[el2_lib.scala 416:105] - node _T_735 = cat(_T_353[1], _T_353[0]) @[el2_lib.scala 416:115] - node _T_736 = cat(_T_353[3], _T_353[2]) @[el2_lib.scala 416:115] - node _T_737 = cat(_T_736, _T_735) @[el2_lib.scala 416:115] - node _T_738 = cat(_T_353[5], _T_353[4]) @[el2_lib.scala 416:115] - node _T_739 = cat(_T_353[7], _T_353[6]) @[el2_lib.scala 416:115] - node _T_740 = cat(_T_739, _T_738) @[el2_lib.scala 416:115] - node _T_741 = cat(_T_740, _T_737) @[el2_lib.scala 416:115] - node _T_742 = cat(_T_353[9], _T_353[8]) @[el2_lib.scala 416:115] - node _T_743 = cat(_T_353[11], _T_353[10]) @[el2_lib.scala 416:115] - node _T_744 = cat(_T_743, _T_742) @[el2_lib.scala 416:115] - node _T_745 = cat(_T_353[13], _T_353[12]) @[el2_lib.scala 416:115] - node _T_746 = cat(_T_353[16], _T_353[15]) @[el2_lib.scala 416:115] - node _T_747 = cat(_T_746, _T_353[14]) @[el2_lib.scala 416:115] - node _T_748 = cat(_T_747, _T_745) @[el2_lib.scala 416:115] - node _T_749 = cat(_T_748, _T_744) @[el2_lib.scala 416:115] - node _T_750 = cat(_T_749, _T_741) @[el2_lib.scala 416:115] - node _T_751 = cat(_T_353[18], _T_353[17]) @[el2_lib.scala 416:115] - node _T_752 = cat(_T_353[20], _T_353[19]) @[el2_lib.scala 416:115] - node _T_753 = cat(_T_752, _T_751) @[el2_lib.scala 416:115] - node _T_754 = cat(_T_353[22], _T_353[21]) @[el2_lib.scala 416:115] - node _T_755 = cat(_T_353[25], _T_353[24]) @[el2_lib.scala 416:115] - node _T_756 = cat(_T_755, _T_353[23]) @[el2_lib.scala 416:115] - node _T_757 = cat(_T_756, _T_754) @[el2_lib.scala 416:115] - node _T_758 = cat(_T_757, _T_753) @[el2_lib.scala 416:115] - node _T_759 = cat(_T_353[27], _T_353[26]) @[el2_lib.scala 416:115] - node _T_760 = cat(_T_353[29], _T_353[28]) @[el2_lib.scala 416:115] - node _T_761 = cat(_T_760, _T_759) @[el2_lib.scala 416:115] - node _T_762 = cat(_T_353[31], _T_353[30]) @[el2_lib.scala 416:115] - node _T_763 = cat(_T_353[34], _T_353[33]) @[el2_lib.scala 416:115] - node _T_764 = cat(_T_763, _T_353[32]) @[el2_lib.scala 416:115] - node _T_765 = cat(_T_764, _T_762) @[el2_lib.scala 416:115] - node _T_766 = cat(_T_765, _T_761) @[el2_lib.scala 416:115] - node _T_767 = cat(_T_766, _T_758) @[el2_lib.scala 416:115] - node _T_768 = cat(_T_767, _T_750) @[el2_lib.scala 416:115] - node _T_769 = xorr(_T_768) @[el2_lib.scala 416:122] + wire _T_353 : UInt<1>[35] @[lib.scala 255:18] + wire _T_354 : UInt<1>[35] @[lib.scala 256:18] + wire _T_355 : UInt<1>[35] @[lib.scala 257:18] + wire _T_356 : UInt<1>[31] @[lib.scala 258:18] + wire _T_357 : UInt<1>[31] @[lib.scala 259:18] + wire _T_358 : UInt<1>[31] @[lib.scala 260:18] + wire _T_359 : UInt<1>[7] @[lib.scala 261:18] + node _T_360 = bits(ifu_bus_rdata_ff, 0, 0) @[lib.scala 268:36] + _T_353[0] <= _T_360 @[lib.scala 268:30] + node _T_361 = bits(ifu_bus_rdata_ff, 0, 0) @[lib.scala 269:36] + _T_354[0] <= _T_361 @[lib.scala 269:30] + node _T_362 = bits(ifu_bus_rdata_ff, 1, 1) @[lib.scala 268:36] + _T_353[1] <= _T_362 @[lib.scala 268:30] + node _T_363 = bits(ifu_bus_rdata_ff, 1, 1) @[lib.scala 270:36] + _T_355[0] <= _T_363 @[lib.scala 270:30] + node _T_364 = bits(ifu_bus_rdata_ff, 2, 2) @[lib.scala 269:36] + _T_354[1] <= _T_364 @[lib.scala 269:30] + node _T_365 = bits(ifu_bus_rdata_ff, 2, 2) @[lib.scala 270:36] + _T_355[1] <= _T_365 @[lib.scala 270:30] + node _T_366 = bits(ifu_bus_rdata_ff, 3, 3) @[lib.scala 268:36] + _T_353[2] <= _T_366 @[lib.scala 268:30] + node _T_367 = bits(ifu_bus_rdata_ff, 3, 3) @[lib.scala 269:36] + _T_354[2] <= _T_367 @[lib.scala 269:30] + node _T_368 = bits(ifu_bus_rdata_ff, 3, 3) @[lib.scala 270:36] + _T_355[2] <= _T_368 @[lib.scala 270:30] + node _T_369 = bits(ifu_bus_rdata_ff, 4, 4) @[lib.scala 268:36] + _T_353[3] <= _T_369 @[lib.scala 268:30] + node _T_370 = bits(ifu_bus_rdata_ff, 4, 4) @[lib.scala 271:36] + _T_356[0] <= _T_370 @[lib.scala 271:30] + node _T_371 = bits(ifu_bus_rdata_ff, 5, 5) @[lib.scala 269:36] + _T_354[3] <= _T_371 @[lib.scala 269:30] + node _T_372 = bits(ifu_bus_rdata_ff, 5, 5) @[lib.scala 271:36] + _T_356[1] <= _T_372 @[lib.scala 271:30] + node _T_373 = bits(ifu_bus_rdata_ff, 6, 6) @[lib.scala 268:36] + _T_353[4] <= _T_373 @[lib.scala 268:30] + node _T_374 = bits(ifu_bus_rdata_ff, 6, 6) @[lib.scala 269:36] + _T_354[4] <= _T_374 @[lib.scala 269:30] + node _T_375 = bits(ifu_bus_rdata_ff, 6, 6) @[lib.scala 271:36] + _T_356[2] <= _T_375 @[lib.scala 271:30] + node _T_376 = bits(ifu_bus_rdata_ff, 7, 7) @[lib.scala 270:36] + _T_355[3] <= _T_376 @[lib.scala 270:30] + node _T_377 = bits(ifu_bus_rdata_ff, 7, 7) @[lib.scala 271:36] + _T_356[3] <= _T_377 @[lib.scala 271:30] + node _T_378 = bits(ifu_bus_rdata_ff, 8, 8) @[lib.scala 268:36] + _T_353[5] <= _T_378 @[lib.scala 268:30] + node _T_379 = bits(ifu_bus_rdata_ff, 8, 8) @[lib.scala 270:36] + _T_355[4] <= _T_379 @[lib.scala 270:30] + node _T_380 = bits(ifu_bus_rdata_ff, 8, 8) @[lib.scala 271:36] + _T_356[4] <= _T_380 @[lib.scala 271:30] + node _T_381 = bits(ifu_bus_rdata_ff, 9, 9) @[lib.scala 269:36] + _T_354[5] <= _T_381 @[lib.scala 269:30] + node _T_382 = bits(ifu_bus_rdata_ff, 9, 9) @[lib.scala 270:36] + _T_355[5] <= _T_382 @[lib.scala 270:30] + node _T_383 = bits(ifu_bus_rdata_ff, 9, 9) @[lib.scala 271:36] + _T_356[5] <= _T_383 @[lib.scala 271:30] + node _T_384 = bits(ifu_bus_rdata_ff, 10, 10) @[lib.scala 268:36] + _T_353[6] <= _T_384 @[lib.scala 268:30] + node _T_385 = bits(ifu_bus_rdata_ff, 10, 10) @[lib.scala 269:36] + _T_354[6] <= _T_385 @[lib.scala 269:30] + node _T_386 = bits(ifu_bus_rdata_ff, 10, 10) @[lib.scala 270:36] + _T_355[6] <= _T_386 @[lib.scala 270:30] + node _T_387 = bits(ifu_bus_rdata_ff, 10, 10) @[lib.scala 271:36] + _T_356[6] <= _T_387 @[lib.scala 271:30] + node _T_388 = bits(ifu_bus_rdata_ff, 11, 11) @[lib.scala 268:36] + _T_353[7] <= _T_388 @[lib.scala 268:30] + node _T_389 = bits(ifu_bus_rdata_ff, 11, 11) @[lib.scala 272:36] + _T_357[0] <= _T_389 @[lib.scala 272:30] + node _T_390 = bits(ifu_bus_rdata_ff, 12, 12) @[lib.scala 269:36] + _T_354[7] <= _T_390 @[lib.scala 269:30] + node _T_391 = bits(ifu_bus_rdata_ff, 12, 12) @[lib.scala 272:36] + _T_357[1] <= _T_391 @[lib.scala 272:30] + node _T_392 = bits(ifu_bus_rdata_ff, 13, 13) @[lib.scala 268:36] + _T_353[8] <= _T_392 @[lib.scala 268:30] + node _T_393 = bits(ifu_bus_rdata_ff, 13, 13) @[lib.scala 269:36] + _T_354[8] <= _T_393 @[lib.scala 269:30] + node _T_394 = bits(ifu_bus_rdata_ff, 13, 13) @[lib.scala 272:36] + _T_357[2] <= _T_394 @[lib.scala 272:30] + node _T_395 = bits(ifu_bus_rdata_ff, 14, 14) @[lib.scala 270:36] + _T_355[7] <= _T_395 @[lib.scala 270:30] + node _T_396 = bits(ifu_bus_rdata_ff, 14, 14) @[lib.scala 272:36] + _T_357[3] <= _T_396 @[lib.scala 272:30] + node _T_397 = bits(ifu_bus_rdata_ff, 15, 15) @[lib.scala 268:36] + _T_353[9] <= _T_397 @[lib.scala 268:30] + node _T_398 = bits(ifu_bus_rdata_ff, 15, 15) @[lib.scala 270:36] + _T_355[8] <= _T_398 @[lib.scala 270:30] + node _T_399 = bits(ifu_bus_rdata_ff, 15, 15) @[lib.scala 272:36] + _T_357[4] <= _T_399 @[lib.scala 272:30] + node _T_400 = bits(ifu_bus_rdata_ff, 16, 16) @[lib.scala 269:36] + _T_354[9] <= _T_400 @[lib.scala 269:30] + node _T_401 = bits(ifu_bus_rdata_ff, 16, 16) @[lib.scala 270:36] + _T_355[9] <= _T_401 @[lib.scala 270:30] + node _T_402 = bits(ifu_bus_rdata_ff, 16, 16) @[lib.scala 272:36] + _T_357[5] <= _T_402 @[lib.scala 272:30] + node _T_403 = bits(ifu_bus_rdata_ff, 17, 17) @[lib.scala 268:36] + _T_353[10] <= _T_403 @[lib.scala 268:30] + node _T_404 = bits(ifu_bus_rdata_ff, 17, 17) @[lib.scala 269:36] + _T_354[10] <= _T_404 @[lib.scala 269:30] + node _T_405 = bits(ifu_bus_rdata_ff, 17, 17) @[lib.scala 270:36] + _T_355[10] <= _T_405 @[lib.scala 270:30] + node _T_406 = bits(ifu_bus_rdata_ff, 17, 17) @[lib.scala 272:36] + _T_357[6] <= _T_406 @[lib.scala 272:30] + node _T_407 = bits(ifu_bus_rdata_ff, 18, 18) @[lib.scala 271:36] + _T_356[7] <= _T_407 @[lib.scala 271:30] + node _T_408 = bits(ifu_bus_rdata_ff, 18, 18) @[lib.scala 272:36] + _T_357[7] <= _T_408 @[lib.scala 272:30] + node _T_409 = bits(ifu_bus_rdata_ff, 19, 19) @[lib.scala 268:36] + _T_353[11] <= _T_409 @[lib.scala 268:30] + node _T_410 = bits(ifu_bus_rdata_ff, 19, 19) @[lib.scala 271:36] + _T_356[8] <= _T_410 @[lib.scala 271:30] + node _T_411 = bits(ifu_bus_rdata_ff, 19, 19) @[lib.scala 272:36] + _T_357[8] <= _T_411 @[lib.scala 272:30] + node _T_412 = bits(ifu_bus_rdata_ff, 20, 20) @[lib.scala 269:36] + _T_354[11] <= _T_412 @[lib.scala 269:30] + node _T_413 = bits(ifu_bus_rdata_ff, 20, 20) @[lib.scala 271:36] + _T_356[9] <= _T_413 @[lib.scala 271:30] + node _T_414 = bits(ifu_bus_rdata_ff, 20, 20) @[lib.scala 272:36] + _T_357[9] <= _T_414 @[lib.scala 272:30] + node _T_415 = bits(ifu_bus_rdata_ff, 21, 21) @[lib.scala 268:36] + _T_353[12] <= _T_415 @[lib.scala 268:30] + node _T_416 = bits(ifu_bus_rdata_ff, 21, 21) @[lib.scala 269:36] + _T_354[12] <= _T_416 @[lib.scala 269:30] + node _T_417 = bits(ifu_bus_rdata_ff, 21, 21) @[lib.scala 271:36] + _T_356[10] <= _T_417 @[lib.scala 271:30] + node _T_418 = bits(ifu_bus_rdata_ff, 21, 21) @[lib.scala 272:36] + _T_357[10] <= _T_418 @[lib.scala 272:30] + node _T_419 = bits(ifu_bus_rdata_ff, 22, 22) @[lib.scala 270:36] + _T_355[11] <= _T_419 @[lib.scala 270:30] + node _T_420 = bits(ifu_bus_rdata_ff, 22, 22) @[lib.scala 271:36] + _T_356[11] <= _T_420 @[lib.scala 271:30] + node _T_421 = bits(ifu_bus_rdata_ff, 22, 22) @[lib.scala 272:36] + _T_357[11] <= _T_421 @[lib.scala 272:30] + node _T_422 = bits(ifu_bus_rdata_ff, 23, 23) @[lib.scala 268:36] + _T_353[13] <= _T_422 @[lib.scala 268:30] + node _T_423 = bits(ifu_bus_rdata_ff, 23, 23) @[lib.scala 270:36] + _T_355[12] <= _T_423 @[lib.scala 270:30] + node _T_424 = bits(ifu_bus_rdata_ff, 23, 23) @[lib.scala 271:36] + _T_356[12] <= _T_424 @[lib.scala 271:30] + node _T_425 = bits(ifu_bus_rdata_ff, 23, 23) @[lib.scala 272:36] + _T_357[12] <= _T_425 @[lib.scala 272:30] + node _T_426 = bits(ifu_bus_rdata_ff, 24, 24) @[lib.scala 269:36] + _T_354[13] <= _T_426 @[lib.scala 269:30] + node _T_427 = bits(ifu_bus_rdata_ff, 24, 24) @[lib.scala 270:36] + _T_355[13] <= _T_427 @[lib.scala 270:30] + node _T_428 = bits(ifu_bus_rdata_ff, 24, 24) @[lib.scala 271:36] + _T_356[13] <= _T_428 @[lib.scala 271:30] + node _T_429 = bits(ifu_bus_rdata_ff, 24, 24) @[lib.scala 272:36] + _T_357[13] <= _T_429 @[lib.scala 272:30] + node _T_430 = bits(ifu_bus_rdata_ff, 25, 25) @[lib.scala 268:36] + _T_353[14] <= _T_430 @[lib.scala 268:30] + node _T_431 = bits(ifu_bus_rdata_ff, 25, 25) @[lib.scala 269:36] + _T_354[14] <= _T_431 @[lib.scala 269:30] + node _T_432 = bits(ifu_bus_rdata_ff, 25, 25) @[lib.scala 270:36] + _T_355[14] <= _T_432 @[lib.scala 270:30] + node _T_433 = bits(ifu_bus_rdata_ff, 25, 25) @[lib.scala 271:36] + _T_356[14] <= _T_433 @[lib.scala 271:30] + node _T_434 = bits(ifu_bus_rdata_ff, 25, 25) @[lib.scala 272:36] + _T_357[14] <= _T_434 @[lib.scala 272:30] + node _T_435 = bits(ifu_bus_rdata_ff, 26, 26) @[lib.scala 268:36] + _T_353[15] <= _T_435 @[lib.scala 268:30] + node _T_436 = bits(ifu_bus_rdata_ff, 26, 26) @[lib.scala 273:36] + _T_358[0] <= _T_436 @[lib.scala 273:30] + node _T_437 = bits(ifu_bus_rdata_ff, 27, 27) @[lib.scala 269:36] + _T_354[15] <= _T_437 @[lib.scala 269:30] + node _T_438 = bits(ifu_bus_rdata_ff, 27, 27) @[lib.scala 273:36] + _T_358[1] <= _T_438 @[lib.scala 273:30] + node _T_439 = bits(ifu_bus_rdata_ff, 28, 28) @[lib.scala 268:36] + _T_353[16] <= _T_439 @[lib.scala 268:30] + node _T_440 = bits(ifu_bus_rdata_ff, 28, 28) @[lib.scala 269:36] + _T_354[16] <= _T_440 @[lib.scala 269:30] + node _T_441 = bits(ifu_bus_rdata_ff, 28, 28) @[lib.scala 273:36] + _T_358[2] <= _T_441 @[lib.scala 273:30] + node _T_442 = bits(ifu_bus_rdata_ff, 29, 29) @[lib.scala 270:36] + _T_355[15] <= _T_442 @[lib.scala 270:30] + node _T_443 = bits(ifu_bus_rdata_ff, 29, 29) @[lib.scala 273:36] + _T_358[3] <= _T_443 @[lib.scala 273:30] + node _T_444 = bits(ifu_bus_rdata_ff, 30, 30) @[lib.scala 268:36] + _T_353[17] <= _T_444 @[lib.scala 268:30] + node _T_445 = bits(ifu_bus_rdata_ff, 30, 30) @[lib.scala 270:36] + _T_355[16] <= _T_445 @[lib.scala 270:30] + node _T_446 = bits(ifu_bus_rdata_ff, 30, 30) @[lib.scala 273:36] + _T_358[4] <= _T_446 @[lib.scala 273:30] + node _T_447 = bits(ifu_bus_rdata_ff, 31, 31) @[lib.scala 269:36] + _T_354[17] <= _T_447 @[lib.scala 269:30] + node _T_448 = bits(ifu_bus_rdata_ff, 31, 31) @[lib.scala 270:36] + _T_355[17] <= _T_448 @[lib.scala 270:30] + node _T_449 = bits(ifu_bus_rdata_ff, 31, 31) @[lib.scala 273:36] + _T_358[5] <= _T_449 @[lib.scala 273:30] + node _T_450 = bits(ifu_bus_rdata_ff, 32, 32) @[lib.scala 268:36] + _T_353[18] <= _T_450 @[lib.scala 268:30] + node _T_451 = bits(ifu_bus_rdata_ff, 32, 32) @[lib.scala 269:36] + _T_354[18] <= _T_451 @[lib.scala 269:30] + node _T_452 = bits(ifu_bus_rdata_ff, 32, 32) @[lib.scala 270:36] + _T_355[18] <= _T_452 @[lib.scala 270:30] + node _T_453 = bits(ifu_bus_rdata_ff, 32, 32) @[lib.scala 273:36] + _T_358[6] <= _T_453 @[lib.scala 273:30] + node _T_454 = bits(ifu_bus_rdata_ff, 33, 33) @[lib.scala 271:36] + _T_356[15] <= _T_454 @[lib.scala 271:30] + node _T_455 = bits(ifu_bus_rdata_ff, 33, 33) @[lib.scala 273:36] + _T_358[7] <= _T_455 @[lib.scala 273:30] + node _T_456 = bits(ifu_bus_rdata_ff, 34, 34) @[lib.scala 268:36] + _T_353[19] <= _T_456 @[lib.scala 268:30] + node _T_457 = bits(ifu_bus_rdata_ff, 34, 34) @[lib.scala 271:36] + _T_356[16] <= _T_457 @[lib.scala 271:30] + node _T_458 = bits(ifu_bus_rdata_ff, 34, 34) @[lib.scala 273:36] + _T_358[8] <= _T_458 @[lib.scala 273:30] + node _T_459 = bits(ifu_bus_rdata_ff, 35, 35) @[lib.scala 269:36] + _T_354[19] <= _T_459 @[lib.scala 269:30] + node _T_460 = bits(ifu_bus_rdata_ff, 35, 35) @[lib.scala 271:36] + _T_356[17] <= _T_460 @[lib.scala 271:30] + node _T_461 = bits(ifu_bus_rdata_ff, 35, 35) @[lib.scala 273:36] + _T_358[9] <= _T_461 @[lib.scala 273:30] + node _T_462 = bits(ifu_bus_rdata_ff, 36, 36) @[lib.scala 268:36] + _T_353[20] <= _T_462 @[lib.scala 268:30] + node _T_463 = bits(ifu_bus_rdata_ff, 36, 36) @[lib.scala 269:36] + _T_354[20] <= _T_463 @[lib.scala 269:30] + node _T_464 = bits(ifu_bus_rdata_ff, 36, 36) @[lib.scala 271:36] + _T_356[18] <= _T_464 @[lib.scala 271:30] + node _T_465 = bits(ifu_bus_rdata_ff, 36, 36) @[lib.scala 273:36] + _T_358[10] <= _T_465 @[lib.scala 273:30] + node _T_466 = bits(ifu_bus_rdata_ff, 37, 37) @[lib.scala 270:36] + _T_355[19] <= _T_466 @[lib.scala 270:30] + node _T_467 = bits(ifu_bus_rdata_ff, 37, 37) @[lib.scala 271:36] + _T_356[19] <= _T_467 @[lib.scala 271:30] + node _T_468 = bits(ifu_bus_rdata_ff, 37, 37) @[lib.scala 273:36] + _T_358[11] <= _T_468 @[lib.scala 273:30] + node _T_469 = bits(ifu_bus_rdata_ff, 38, 38) @[lib.scala 268:36] + _T_353[21] <= _T_469 @[lib.scala 268:30] + node _T_470 = bits(ifu_bus_rdata_ff, 38, 38) @[lib.scala 270:36] + _T_355[20] <= _T_470 @[lib.scala 270:30] + node _T_471 = bits(ifu_bus_rdata_ff, 38, 38) @[lib.scala 271:36] + _T_356[20] <= _T_471 @[lib.scala 271:30] + node _T_472 = bits(ifu_bus_rdata_ff, 38, 38) @[lib.scala 273:36] + _T_358[12] <= _T_472 @[lib.scala 273:30] + node _T_473 = bits(ifu_bus_rdata_ff, 39, 39) @[lib.scala 269:36] + _T_354[21] <= _T_473 @[lib.scala 269:30] + node _T_474 = bits(ifu_bus_rdata_ff, 39, 39) @[lib.scala 270:36] + _T_355[21] <= _T_474 @[lib.scala 270:30] + node _T_475 = bits(ifu_bus_rdata_ff, 39, 39) @[lib.scala 271:36] + _T_356[21] <= _T_475 @[lib.scala 271:30] + node _T_476 = bits(ifu_bus_rdata_ff, 39, 39) @[lib.scala 273:36] + _T_358[13] <= _T_476 @[lib.scala 273:30] + node _T_477 = bits(ifu_bus_rdata_ff, 40, 40) @[lib.scala 268:36] + _T_353[22] <= _T_477 @[lib.scala 268:30] + node _T_478 = bits(ifu_bus_rdata_ff, 40, 40) @[lib.scala 269:36] + _T_354[22] <= _T_478 @[lib.scala 269:30] + node _T_479 = bits(ifu_bus_rdata_ff, 40, 40) @[lib.scala 270:36] + _T_355[22] <= _T_479 @[lib.scala 270:30] + node _T_480 = bits(ifu_bus_rdata_ff, 40, 40) @[lib.scala 271:36] + _T_356[22] <= _T_480 @[lib.scala 271:30] + node _T_481 = bits(ifu_bus_rdata_ff, 40, 40) @[lib.scala 273:36] + _T_358[14] <= _T_481 @[lib.scala 273:30] + node _T_482 = bits(ifu_bus_rdata_ff, 41, 41) @[lib.scala 272:36] + _T_357[15] <= _T_482 @[lib.scala 272:30] + node _T_483 = bits(ifu_bus_rdata_ff, 41, 41) @[lib.scala 273:36] + _T_358[15] <= _T_483 @[lib.scala 273:30] + node _T_484 = bits(ifu_bus_rdata_ff, 42, 42) @[lib.scala 268:36] + _T_353[23] <= _T_484 @[lib.scala 268:30] + node _T_485 = bits(ifu_bus_rdata_ff, 42, 42) @[lib.scala 272:36] + _T_357[16] <= _T_485 @[lib.scala 272:30] + node _T_486 = bits(ifu_bus_rdata_ff, 42, 42) @[lib.scala 273:36] + _T_358[16] <= _T_486 @[lib.scala 273:30] + node _T_487 = bits(ifu_bus_rdata_ff, 43, 43) @[lib.scala 269:36] + _T_354[23] <= _T_487 @[lib.scala 269:30] + node _T_488 = bits(ifu_bus_rdata_ff, 43, 43) @[lib.scala 272:36] + _T_357[17] <= _T_488 @[lib.scala 272:30] + node _T_489 = bits(ifu_bus_rdata_ff, 43, 43) @[lib.scala 273:36] + _T_358[17] <= _T_489 @[lib.scala 273:30] + node _T_490 = bits(ifu_bus_rdata_ff, 44, 44) @[lib.scala 268:36] + _T_353[24] <= _T_490 @[lib.scala 268:30] + node _T_491 = bits(ifu_bus_rdata_ff, 44, 44) @[lib.scala 269:36] + _T_354[24] <= _T_491 @[lib.scala 269:30] + node _T_492 = bits(ifu_bus_rdata_ff, 44, 44) @[lib.scala 272:36] + _T_357[18] <= _T_492 @[lib.scala 272:30] + node _T_493 = bits(ifu_bus_rdata_ff, 44, 44) @[lib.scala 273:36] + _T_358[18] <= _T_493 @[lib.scala 273:30] + node _T_494 = bits(ifu_bus_rdata_ff, 45, 45) @[lib.scala 270:36] + _T_355[23] <= _T_494 @[lib.scala 270:30] + node _T_495 = bits(ifu_bus_rdata_ff, 45, 45) @[lib.scala 272:36] + _T_357[19] <= _T_495 @[lib.scala 272:30] + node _T_496 = bits(ifu_bus_rdata_ff, 45, 45) @[lib.scala 273:36] + _T_358[19] <= _T_496 @[lib.scala 273:30] + node _T_497 = bits(ifu_bus_rdata_ff, 46, 46) @[lib.scala 268:36] + _T_353[25] <= _T_497 @[lib.scala 268:30] + node _T_498 = bits(ifu_bus_rdata_ff, 46, 46) @[lib.scala 270:36] + _T_355[24] <= _T_498 @[lib.scala 270:30] + node _T_499 = bits(ifu_bus_rdata_ff, 46, 46) @[lib.scala 272:36] + _T_357[20] <= _T_499 @[lib.scala 272:30] + node _T_500 = bits(ifu_bus_rdata_ff, 46, 46) @[lib.scala 273:36] + _T_358[20] <= _T_500 @[lib.scala 273:30] + node _T_501 = bits(ifu_bus_rdata_ff, 47, 47) @[lib.scala 269:36] + _T_354[25] <= _T_501 @[lib.scala 269:30] + node _T_502 = bits(ifu_bus_rdata_ff, 47, 47) @[lib.scala 270:36] + _T_355[25] <= _T_502 @[lib.scala 270:30] + node _T_503 = bits(ifu_bus_rdata_ff, 47, 47) @[lib.scala 272:36] + _T_357[21] <= _T_503 @[lib.scala 272:30] + node _T_504 = bits(ifu_bus_rdata_ff, 47, 47) @[lib.scala 273:36] + _T_358[21] <= _T_504 @[lib.scala 273:30] + node _T_505 = bits(ifu_bus_rdata_ff, 48, 48) @[lib.scala 268:36] + _T_353[26] <= _T_505 @[lib.scala 268:30] + node _T_506 = bits(ifu_bus_rdata_ff, 48, 48) @[lib.scala 269:36] + _T_354[26] <= _T_506 @[lib.scala 269:30] + node _T_507 = bits(ifu_bus_rdata_ff, 48, 48) @[lib.scala 270:36] + _T_355[26] <= _T_507 @[lib.scala 270:30] + node _T_508 = bits(ifu_bus_rdata_ff, 48, 48) @[lib.scala 272:36] + _T_357[22] <= _T_508 @[lib.scala 272:30] + node _T_509 = bits(ifu_bus_rdata_ff, 48, 48) @[lib.scala 273:36] + _T_358[22] <= _T_509 @[lib.scala 273:30] + node _T_510 = bits(ifu_bus_rdata_ff, 49, 49) @[lib.scala 271:36] + _T_356[23] <= _T_510 @[lib.scala 271:30] + node _T_511 = bits(ifu_bus_rdata_ff, 49, 49) @[lib.scala 272:36] + _T_357[23] <= _T_511 @[lib.scala 272:30] + node _T_512 = bits(ifu_bus_rdata_ff, 49, 49) @[lib.scala 273:36] + _T_358[23] <= _T_512 @[lib.scala 273:30] + node _T_513 = bits(ifu_bus_rdata_ff, 50, 50) @[lib.scala 268:36] + _T_353[27] <= _T_513 @[lib.scala 268:30] + node _T_514 = bits(ifu_bus_rdata_ff, 50, 50) @[lib.scala 271:36] + _T_356[24] <= _T_514 @[lib.scala 271:30] + node _T_515 = bits(ifu_bus_rdata_ff, 50, 50) @[lib.scala 272:36] + _T_357[24] <= _T_515 @[lib.scala 272:30] + node _T_516 = bits(ifu_bus_rdata_ff, 50, 50) @[lib.scala 273:36] + _T_358[24] <= _T_516 @[lib.scala 273:30] + node _T_517 = bits(ifu_bus_rdata_ff, 51, 51) @[lib.scala 269:36] + _T_354[27] <= _T_517 @[lib.scala 269:30] + node _T_518 = bits(ifu_bus_rdata_ff, 51, 51) @[lib.scala 271:36] + _T_356[25] <= _T_518 @[lib.scala 271:30] + node _T_519 = bits(ifu_bus_rdata_ff, 51, 51) @[lib.scala 272:36] + _T_357[25] <= _T_519 @[lib.scala 272:30] + node _T_520 = bits(ifu_bus_rdata_ff, 51, 51) @[lib.scala 273:36] + _T_358[25] <= _T_520 @[lib.scala 273:30] + node _T_521 = bits(ifu_bus_rdata_ff, 52, 52) @[lib.scala 268:36] + _T_353[28] <= _T_521 @[lib.scala 268:30] + node _T_522 = bits(ifu_bus_rdata_ff, 52, 52) @[lib.scala 269:36] + _T_354[28] <= _T_522 @[lib.scala 269:30] + node _T_523 = bits(ifu_bus_rdata_ff, 52, 52) @[lib.scala 271:36] + _T_356[26] <= _T_523 @[lib.scala 271:30] + node _T_524 = bits(ifu_bus_rdata_ff, 52, 52) @[lib.scala 272:36] + _T_357[26] <= _T_524 @[lib.scala 272:30] + node _T_525 = bits(ifu_bus_rdata_ff, 52, 52) @[lib.scala 273:36] + _T_358[26] <= _T_525 @[lib.scala 273:30] + node _T_526 = bits(ifu_bus_rdata_ff, 53, 53) @[lib.scala 270:36] + _T_355[27] <= _T_526 @[lib.scala 270:30] + node _T_527 = bits(ifu_bus_rdata_ff, 53, 53) @[lib.scala 271:36] + _T_356[27] <= _T_527 @[lib.scala 271:30] + node _T_528 = bits(ifu_bus_rdata_ff, 53, 53) @[lib.scala 272:36] + _T_357[27] <= _T_528 @[lib.scala 272:30] + node _T_529 = bits(ifu_bus_rdata_ff, 53, 53) @[lib.scala 273:36] + _T_358[27] <= _T_529 @[lib.scala 273:30] + node _T_530 = bits(ifu_bus_rdata_ff, 54, 54) @[lib.scala 268:36] + _T_353[29] <= _T_530 @[lib.scala 268:30] + node _T_531 = bits(ifu_bus_rdata_ff, 54, 54) @[lib.scala 270:36] + _T_355[28] <= _T_531 @[lib.scala 270:30] + node _T_532 = bits(ifu_bus_rdata_ff, 54, 54) @[lib.scala 271:36] + _T_356[28] <= _T_532 @[lib.scala 271:30] + node _T_533 = bits(ifu_bus_rdata_ff, 54, 54) @[lib.scala 272:36] + _T_357[28] <= _T_533 @[lib.scala 272:30] + node _T_534 = bits(ifu_bus_rdata_ff, 54, 54) @[lib.scala 273:36] + _T_358[28] <= _T_534 @[lib.scala 273:30] + node _T_535 = bits(ifu_bus_rdata_ff, 55, 55) @[lib.scala 269:36] + _T_354[29] <= _T_535 @[lib.scala 269:30] + node _T_536 = bits(ifu_bus_rdata_ff, 55, 55) @[lib.scala 270:36] + _T_355[29] <= _T_536 @[lib.scala 270:30] + node _T_537 = bits(ifu_bus_rdata_ff, 55, 55) @[lib.scala 271:36] + _T_356[29] <= _T_537 @[lib.scala 271:30] + node _T_538 = bits(ifu_bus_rdata_ff, 55, 55) @[lib.scala 272:36] + _T_357[29] <= _T_538 @[lib.scala 272:30] + node _T_539 = bits(ifu_bus_rdata_ff, 55, 55) @[lib.scala 273:36] + _T_358[29] <= _T_539 @[lib.scala 273:30] + node _T_540 = bits(ifu_bus_rdata_ff, 56, 56) @[lib.scala 268:36] + _T_353[30] <= _T_540 @[lib.scala 268:30] + node _T_541 = bits(ifu_bus_rdata_ff, 56, 56) @[lib.scala 269:36] + _T_354[30] <= _T_541 @[lib.scala 269:30] + node _T_542 = bits(ifu_bus_rdata_ff, 56, 56) @[lib.scala 270:36] + _T_355[30] <= _T_542 @[lib.scala 270:30] + node _T_543 = bits(ifu_bus_rdata_ff, 56, 56) @[lib.scala 271:36] + _T_356[30] <= _T_543 @[lib.scala 271:30] + node _T_544 = bits(ifu_bus_rdata_ff, 56, 56) @[lib.scala 272:36] + _T_357[30] <= _T_544 @[lib.scala 272:30] + node _T_545 = bits(ifu_bus_rdata_ff, 56, 56) @[lib.scala 273:36] + _T_358[30] <= _T_545 @[lib.scala 273:30] + node _T_546 = bits(ifu_bus_rdata_ff, 57, 57) @[lib.scala 268:36] + _T_353[31] <= _T_546 @[lib.scala 268:30] + node _T_547 = bits(ifu_bus_rdata_ff, 57, 57) @[lib.scala 274:36] + _T_359[0] <= _T_547 @[lib.scala 274:30] + node _T_548 = bits(ifu_bus_rdata_ff, 58, 58) @[lib.scala 269:36] + _T_354[31] <= _T_548 @[lib.scala 269:30] + node _T_549 = bits(ifu_bus_rdata_ff, 58, 58) @[lib.scala 274:36] + _T_359[1] <= _T_549 @[lib.scala 274:30] + node _T_550 = bits(ifu_bus_rdata_ff, 59, 59) @[lib.scala 268:36] + _T_353[32] <= _T_550 @[lib.scala 268:30] + node _T_551 = bits(ifu_bus_rdata_ff, 59, 59) @[lib.scala 269:36] + _T_354[32] <= _T_551 @[lib.scala 269:30] + node _T_552 = bits(ifu_bus_rdata_ff, 59, 59) @[lib.scala 274:36] + _T_359[2] <= _T_552 @[lib.scala 274:30] + node _T_553 = bits(ifu_bus_rdata_ff, 60, 60) @[lib.scala 270:36] + _T_355[31] <= _T_553 @[lib.scala 270:30] + node _T_554 = bits(ifu_bus_rdata_ff, 60, 60) @[lib.scala 274:36] + _T_359[3] <= _T_554 @[lib.scala 274:30] + node _T_555 = bits(ifu_bus_rdata_ff, 61, 61) @[lib.scala 268:36] + _T_353[33] <= _T_555 @[lib.scala 268:30] + node _T_556 = bits(ifu_bus_rdata_ff, 61, 61) @[lib.scala 270:36] + _T_355[32] <= _T_556 @[lib.scala 270:30] + node _T_557 = bits(ifu_bus_rdata_ff, 61, 61) @[lib.scala 274:36] + _T_359[4] <= _T_557 @[lib.scala 274:30] + node _T_558 = bits(ifu_bus_rdata_ff, 62, 62) @[lib.scala 269:36] + _T_354[33] <= _T_558 @[lib.scala 269:30] + node _T_559 = bits(ifu_bus_rdata_ff, 62, 62) @[lib.scala 270:36] + _T_355[33] <= _T_559 @[lib.scala 270:30] + node _T_560 = bits(ifu_bus_rdata_ff, 62, 62) @[lib.scala 274:36] + _T_359[5] <= _T_560 @[lib.scala 274:30] + node _T_561 = bits(ifu_bus_rdata_ff, 63, 63) @[lib.scala 268:36] + _T_353[34] <= _T_561 @[lib.scala 268:30] + node _T_562 = bits(ifu_bus_rdata_ff, 63, 63) @[lib.scala 269:36] + _T_354[34] <= _T_562 @[lib.scala 269:30] + node _T_563 = bits(ifu_bus_rdata_ff, 63, 63) @[lib.scala 270:36] + _T_355[34] <= _T_563 @[lib.scala 270:30] + node _T_564 = bits(ifu_bus_rdata_ff, 63, 63) @[lib.scala 274:36] + _T_359[6] <= _T_564 @[lib.scala 274:30] + node _T_565 = cat(_T_359[2], _T_359[1]) @[lib.scala 276:13] + node _T_566 = cat(_T_565, _T_359[0]) @[lib.scala 276:13] + node _T_567 = cat(_T_359[4], _T_359[3]) @[lib.scala 276:13] + node _T_568 = cat(_T_359[6], _T_359[5]) @[lib.scala 276:13] + node _T_569 = cat(_T_568, _T_567) @[lib.scala 276:13] + node _T_570 = cat(_T_569, _T_566) @[lib.scala 276:13] + node _T_571 = xorr(_T_570) @[lib.scala 276:20] + node _T_572 = cat(_T_358[2], _T_358[1]) @[lib.scala 276:30] + node _T_573 = cat(_T_572, _T_358[0]) @[lib.scala 276:30] + node _T_574 = cat(_T_358[4], _T_358[3]) @[lib.scala 276:30] + node _T_575 = cat(_T_358[6], _T_358[5]) @[lib.scala 276:30] + node _T_576 = cat(_T_575, _T_574) @[lib.scala 276:30] + node _T_577 = cat(_T_576, _T_573) @[lib.scala 276:30] + node _T_578 = cat(_T_358[8], _T_358[7]) @[lib.scala 276:30] + node _T_579 = cat(_T_358[10], _T_358[9]) @[lib.scala 276:30] + node _T_580 = cat(_T_579, _T_578) @[lib.scala 276:30] + node _T_581 = cat(_T_358[12], _T_358[11]) @[lib.scala 276:30] + node _T_582 = cat(_T_358[14], _T_358[13]) @[lib.scala 276:30] + node _T_583 = cat(_T_582, _T_581) @[lib.scala 276:30] + node _T_584 = cat(_T_583, _T_580) @[lib.scala 276:30] + node _T_585 = cat(_T_584, _T_577) @[lib.scala 276:30] + node _T_586 = cat(_T_358[16], _T_358[15]) @[lib.scala 276:30] + node _T_587 = cat(_T_358[18], _T_358[17]) @[lib.scala 276:30] + node _T_588 = cat(_T_587, _T_586) @[lib.scala 276:30] + node _T_589 = cat(_T_358[20], _T_358[19]) @[lib.scala 276:30] + node _T_590 = cat(_T_358[22], _T_358[21]) @[lib.scala 276:30] + node _T_591 = cat(_T_590, _T_589) @[lib.scala 276:30] + node _T_592 = cat(_T_591, _T_588) @[lib.scala 276:30] + node _T_593 = cat(_T_358[24], _T_358[23]) @[lib.scala 276:30] + node _T_594 = cat(_T_358[26], _T_358[25]) @[lib.scala 276:30] + node _T_595 = cat(_T_594, _T_593) @[lib.scala 276:30] + node _T_596 = cat(_T_358[28], _T_358[27]) @[lib.scala 276:30] + node _T_597 = cat(_T_358[30], _T_358[29]) @[lib.scala 276:30] + node _T_598 = cat(_T_597, _T_596) @[lib.scala 276:30] + node _T_599 = cat(_T_598, _T_595) @[lib.scala 276:30] + node _T_600 = cat(_T_599, _T_592) @[lib.scala 276:30] + node _T_601 = cat(_T_600, _T_585) @[lib.scala 276:30] + node _T_602 = xorr(_T_601) @[lib.scala 276:37] + node _T_603 = cat(_T_357[2], _T_357[1]) @[lib.scala 276:47] + node _T_604 = cat(_T_603, _T_357[0]) @[lib.scala 276:47] + node _T_605 = cat(_T_357[4], _T_357[3]) @[lib.scala 276:47] + node _T_606 = cat(_T_357[6], _T_357[5]) @[lib.scala 276:47] + node _T_607 = cat(_T_606, _T_605) @[lib.scala 276:47] + node _T_608 = cat(_T_607, _T_604) @[lib.scala 276:47] + node _T_609 = cat(_T_357[8], _T_357[7]) @[lib.scala 276:47] + node _T_610 = cat(_T_357[10], _T_357[9]) @[lib.scala 276:47] + node _T_611 = cat(_T_610, _T_609) @[lib.scala 276:47] + node _T_612 = cat(_T_357[12], _T_357[11]) @[lib.scala 276:47] + node _T_613 = cat(_T_357[14], _T_357[13]) @[lib.scala 276:47] + node _T_614 = cat(_T_613, _T_612) @[lib.scala 276:47] + node _T_615 = cat(_T_614, _T_611) @[lib.scala 276:47] + node _T_616 = cat(_T_615, _T_608) @[lib.scala 276:47] + node _T_617 = cat(_T_357[16], _T_357[15]) @[lib.scala 276:47] + node _T_618 = cat(_T_357[18], _T_357[17]) @[lib.scala 276:47] + node _T_619 = cat(_T_618, _T_617) @[lib.scala 276:47] + node _T_620 = cat(_T_357[20], _T_357[19]) @[lib.scala 276:47] + node _T_621 = cat(_T_357[22], _T_357[21]) @[lib.scala 276:47] + node _T_622 = cat(_T_621, _T_620) @[lib.scala 276:47] + node _T_623 = cat(_T_622, _T_619) @[lib.scala 276:47] + node _T_624 = cat(_T_357[24], _T_357[23]) @[lib.scala 276:47] + node _T_625 = cat(_T_357[26], _T_357[25]) @[lib.scala 276:47] + node _T_626 = cat(_T_625, _T_624) @[lib.scala 276:47] + node _T_627 = cat(_T_357[28], _T_357[27]) @[lib.scala 276:47] + node _T_628 = cat(_T_357[30], _T_357[29]) @[lib.scala 276:47] + node _T_629 = cat(_T_628, _T_627) @[lib.scala 276:47] + node _T_630 = cat(_T_629, _T_626) @[lib.scala 276:47] + node _T_631 = cat(_T_630, _T_623) @[lib.scala 276:47] + node _T_632 = cat(_T_631, _T_616) @[lib.scala 276:47] + node _T_633 = xorr(_T_632) @[lib.scala 276:54] + node _T_634 = cat(_T_356[2], _T_356[1]) @[lib.scala 276:64] + node _T_635 = cat(_T_634, _T_356[0]) @[lib.scala 276:64] + node _T_636 = cat(_T_356[4], _T_356[3]) @[lib.scala 276:64] + node _T_637 = cat(_T_356[6], _T_356[5]) @[lib.scala 276:64] + node _T_638 = cat(_T_637, _T_636) @[lib.scala 276:64] + node _T_639 = cat(_T_638, _T_635) @[lib.scala 276:64] + node _T_640 = cat(_T_356[8], _T_356[7]) @[lib.scala 276:64] + node _T_641 = cat(_T_356[10], _T_356[9]) @[lib.scala 276:64] + node _T_642 = cat(_T_641, _T_640) @[lib.scala 276:64] + node _T_643 = cat(_T_356[12], _T_356[11]) @[lib.scala 276:64] + node _T_644 = cat(_T_356[14], _T_356[13]) @[lib.scala 276:64] + node _T_645 = cat(_T_644, _T_643) @[lib.scala 276:64] + node _T_646 = cat(_T_645, _T_642) @[lib.scala 276:64] + node _T_647 = cat(_T_646, _T_639) @[lib.scala 276:64] + node _T_648 = cat(_T_356[16], _T_356[15]) @[lib.scala 276:64] + node _T_649 = cat(_T_356[18], _T_356[17]) @[lib.scala 276:64] + node _T_650 = cat(_T_649, _T_648) @[lib.scala 276:64] + node _T_651 = cat(_T_356[20], _T_356[19]) @[lib.scala 276:64] + node _T_652 = cat(_T_356[22], _T_356[21]) @[lib.scala 276:64] + node _T_653 = cat(_T_652, _T_651) @[lib.scala 276:64] + node _T_654 = cat(_T_653, _T_650) @[lib.scala 276:64] + node _T_655 = cat(_T_356[24], _T_356[23]) @[lib.scala 276:64] + node _T_656 = cat(_T_356[26], _T_356[25]) @[lib.scala 276:64] + node _T_657 = cat(_T_656, _T_655) @[lib.scala 276:64] + node _T_658 = cat(_T_356[28], _T_356[27]) @[lib.scala 276:64] + node _T_659 = cat(_T_356[30], _T_356[29]) @[lib.scala 276:64] + node _T_660 = cat(_T_659, _T_658) @[lib.scala 276:64] + node _T_661 = cat(_T_660, _T_657) @[lib.scala 276:64] + node _T_662 = cat(_T_661, _T_654) @[lib.scala 276:64] + node _T_663 = cat(_T_662, _T_647) @[lib.scala 276:64] + node _T_664 = xorr(_T_663) @[lib.scala 276:71] + node _T_665 = cat(_T_355[1], _T_355[0]) @[lib.scala 276:81] + node _T_666 = cat(_T_355[3], _T_355[2]) @[lib.scala 276:81] + node _T_667 = cat(_T_666, _T_665) @[lib.scala 276:81] + node _T_668 = cat(_T_355[5], _T_355[4]) @[lib.scala 276:81] + node _T_669 = cat(_T_355[7], _T_355[6]) @[lib.scala 276:81] + node _T_670 = cat(_T_669, _T_668) @[lib.scala 276:81] + node _T_671 = cat(_T_670, _T_667) @[lib.scala 276:81] + node _T_672 = cat(_T_355[9], _T_355[8]) @[lib.scala 276:81] + node _T_673 = cat(_T_355[11], _T_355[10]) @[lib.scala 276:81] + node _T_674 = cat(_T_673, _T_672) @[lib.scala 276:81] + node _T_675 = cat(_T_355[13], _T_355[12]) @[lib.scala 276:81] + node _T_676 = cat(_T_355[16], _T_355[15]) @[lib.scala 276:81] + node _T_677 = cat(_T_676, _T_355[14]) @[lib.scala 276:81] + node _T_678 = cat(_T_677, _T_675) @[lib.scala 276:81] + node _T_679 = cat(_T_678, _T_674) @[lib.scala 276:81] + node _T_680 = cat(_T_679, _T_671) @[lib.scala 276:81] + node _T_681 = cat(_T_355[18], _T_355[17]) @[lib.scala 276:81] + node _T_682 = cat(_T_355[20], _T_355[19]) @[lib.scala 276:81] + node _T_683 = cat(_T_682, _T_681) @[lib.scala 276:81] + node _T_684 = cat(_T_355[22], _T_355[21]) @[lib.scala 276:81] + node _T_685 = cat(_T_355[25], _T_355[24]) @[lib.scala 276:81] + node _T_686 = cat(_T_685, _T_355[23]) @[lib.scala 276:81] + node _T_687 = cat(_T_686, _T_684) @[lib.scala 276:81] + node _T_688 = cat(_T_687, _T_683) @[lib.scala 276:81] + node _T_689 = cat(_T_355[27], _T_355[26]) @[lib.scala 276:81] + node _T_690 = cat(_T_355[29], _T_355[28]) @[lib.scala 276:81] + node _T_691 = cat(_T_690, _T_689) @[lib.scala 276:81] + node _T_692 = cat(_T_355[31], _T_355[30]) @[lib.scala 276:81] + node _T_693 = cat(_T_355[34], _T_355[33]) @[lib.scala 276:81] + node _T_694 = cat(_T_693, _T_355[32]) @[lib.scala 276:81] + node _T_695 = cat(_T_694, _T_692) @[lib.scala 276:81] + node _T_696 = cat(_T_695, _T_691) @[lib.scala 276:81] + node _T_697 = cat(_T_696, _T_688) @[lib.scala 276:81] + node _T_698 = cat(_T_697, _T_680) @[lib.scala 276:81] + node _T_699 = xorr(_T_698) @[lib.scala 276:88] + node _T_700 = cat(_T_354[1], _T_354[0]) @[lib.scala 276:98] + node _T_701 = cat(_T_354[3], _T_354[2]) @[lib.scala 276:98] + node _T_702 = cat(_T_701, _T_700) @[lib.scala 276:98] + node _T_703 = cat(_T_354[5], _T_354[4]) @[lib.scala 276:98] + node _T_704 = cat(_T_354[7], _T_354[6]) @[lib.scala 276:98] + node _T_705 = cat(_T_704, _T_703) @[lib.scala 276:98] + node _T_706 = cat(_T_705, _T_702) @[lib.scala 276:98] + node _T_707 = cat(_T_354[9], _T_354[8]) @[lib.scala 276:98] + node _T_708 = cat(_T_354[11], _T_354[10]) @[lib.scala 276:98] + node _T_709 = cat(_T_708, _T_707) @[lib.scala 276:98] + node _T_710 = cat(_T_354[13], _T_354[12]) @[lib.scala 276:98] + node _T_711 = cat(_T_354[16], _T_354[15]) @[lib.scala 276:98] + node _T_712 = cat(_T_711, _T_354[14]) @[lib.scala 276:98] + node _T_713 = cat(_T_712, _T_710) @[lib.scala 276:98] + node _T_714 = cat(_T_713, _T_709) @[lib.scala 276:98] + node _T_715 = cat(_T_714, _T_706) @[lib.scala 276:98] + node _T_716 = cat(_T_354[18], _T_354[17]) @[lib.scala 276:98] + node _T_717 = cat(_T_354[20], _T_354[19]) @[lib.scala 276:98] + node _T_718 = cat(_T_717, _T_716) @[lib.scala 276:98] + node _T_719 = cat(_T_354[22], _T_354[21]) @[lib.scala 276:98] + node _T_720 = cat(_T_354[25], _T_354[24]) @[lib.scala 276:98] + node _T_721 = cat(_T_720, _T_354[23]) @[lib.scala 276:98] + node _T_722 = cat(_T_721, _T_719) @[lib.scala 276:98] + node _T_723 = cat(_T_722, _T_718) @[lib.scala 276:98] + node _T_724 = cat(_T_354[27], _T_354[26]) @[lib.scala 276:98] + node _T_725 = cat(_T_354[29], _T_354[28]) @[lib.scala 276:98] + node _T_726 = cat(_T_725, _T_724) @[lib.scala 276:98] + node _T_727 = cat(_T_354[31], _T_354[30]) @[lib.scala 276:98] + node _T_728 = cat(_T_354[34], _T_354[33]) @[lib.scala 276:98] + node _T_729 = cat(_T_728, _T_354[32]) @[lib.scala 276:98] + node _T_730 = cat(_T_729, _T_727) @[lib.scala 276:98] + node _T_731 = cat(_T_730, _T_726) @[lib.scala 276:98] + node _T_732 = cat(_T_731, _T_723) @[lib.scala 276:98] + node _T_733 = cat(_T_732, _T_715) @[lib.scala 276:98] + node _T_734 = xorr(_T_733) @[lib.scala 276:105] + node _T_735 = cat(_T_353[1], _T_353[0]) @[lib.scala 276:115] + node _T_736 = cat(_T_353[3], _T_353[2]) @[lib.scala 276:115] + node _T_737 = cat(_T_736, _T_735) @[lib.scala 276:115] + node _T_738 = cat(_T_353[5], _T_353[4]) @[lib.scala 276:115] + node _T_739 = cat(_T_353[7], _T_353[6]) @[lib.scala 276:115] + node _T_740 = cat(_T_739, _T_738) @[lib.scala 276:115] + node _T_741 = cat(_T_740, _T_737) @[lib.scala 276:115] + node _T_742 = cat(_T_353[9], _T_353[8]) @[lib.scala 276:115] + node _T_743 = cat(_T_353[11], _T_353[10]) @[lib.scala 276:115] + node _T_744 = cat(_T_743, _T_742) @[lib.scala 276:115] + node _T_745 = cat(_T_353[13], _T_353[12]) @[lib.scala 276:115] + node _T_746 = cat(_T_353[16], _T_353[15]) @[lib.scala 276:115] + node _T_747 = cat(_T_746, _T_353[14]) @[lib.scala 276:115] + node _T_748 = cat(_T_747, _T_745) @[lib.scala 276:115] + node _T_749 = cat(_T_748, _T_744) @[lib.scala 276:115] + node _T_750 = cat(_T_749, _T_741) @[lib.scala 276:115] + node _T_751 = cat(_T_353[18], _T_353[17]) @[lib.scala 276:115] + node _T_752 = cat(_T_353[20], _T_353[19]) @[lib.scala 276:115] + node _T_753 = cat(_T_752, _T_751) @[lib.scala 276:115] + node _T_754 = cat(_T_353[22], _T_353[21]) @[lib.scala 276:115] + node _T_755 = cat(_T_353[25], _T_353[24]) @[lib.scala 276:115] + node _T_756 = cat(_T_755, _T_353[23]) @[lib.scala 276:115] + node _T_757 = cat(_T_756, _T_754) @[lib.scala 276:115] + node _T_758 = cat(_T_757, _T_753) @[lib.scala 276:115] + node _T_759 = cat(_T_353[27], _T_353[26]) @[lib.scala 276:115] + node _T_760 = cat(_T_353[29], _T_353[28]) @[lib.scala 276:115] + node _T_761 = cat(_T_760, _T_759) @[lib.scala 276:115] + node _T_762 = cat(_T_353[31], _T_353[30]) @[lib.scala 276:115] + node _T_763 = cat(_T_353[34], _T_353[33]) @[lib.scala 276:115] + node _T_764 = cat(_T_763, _T_353[32]) @[lib.scala 276:115] + node _T_765 = cat(_T_764, _T_762) @[lib.scala 276:115] + node _T_766 = cat(_T_765, _T_761) @[lib.scala 276:115] + node _T_767 = cat(_T_766, _T_758) @[lib.scala 276:115] + node _T_768 = cat(_T_767, _T_750) @[lib.scala 276:115] + node _T_769 = xorr(_T_768) @[lib.scala 276:122] node _T_770 = cat(_T_699, _T_734) @[Cat.scala 29:58] node _T_771 = cat(_T_770, _T_769) @[Cat.scala 29:58] node _T_772 = cat(_T_633, _T_664) @[Cat.scala 29:58] node _T_773 = cat(_T_571, _T_602) @[Cat.scala 29:58] node _T_774 = cat(_T_773, _T_772) @[Cat.scala 29:58] node ic_wr_ecc = cat(_T_774, _T_771) @[Cat.scala 29:58] - wire _T_775 : UInt<1>[35] @[el2_lib.scala 395:18] - wire _T_776 : UInt<1>[35] @[el2_lib.scala 396:18] - wire _T_777 : UInt<1>[35] @[el2_lib.scala 397:18] - wire _T_778 : UInt<1>[31] @[el2_lib.scala 398:18] - wire _T_779 : UInt<1>[31] @[el2_lib.scala 399:18] - wire _T_780 : UInt<1>[31] @[el2_lib.scala 400:18] - wire _T_781 : UInt<1>[7] @[el2_lib.scala 401:18] - node _T_782 = bits(ic_miss_buff_half, 0, 0) @[el2_lib.scala 408:36] - _T_775[0] <= _T_782 @[el2_lib.scala 408:30] - node _T_783 = bits(ic_miss_buff_half, 0, 0) @[el2_lib.scala 409:36] - _T_776[0] <= _T_783 @[el2_lib.scala 409:30] - node _T_784 = bits(ic_miss_buff_half, 1, 1) @[el2_lib.scala 408:36] - _T_775[1] <= _T_784 @[el2_lib.scala 408:30] - node _T_785 = bits(ic_miss_buff_half, 1, 1) @[el2_lib.scala 410:36] - _T_777[0] <= _T_785 @[el2_lib.scala 410:30] - node _T_786 = bits(ic_miss_buff_half, 2, 2) @[el2_lib.scala 409:36] - _T_776[1] <= _T_786 @[el2_lib.scala 409:30] - node _T_787 = bits(ic_miss_buff_half, 2, 2) @[el2_lib.scala 410:36] - _T_777[1] <= _T_787 @[el2_lib.scala 410:30] - node _T_788 = bits(ic_miss_buff_half, 3, 3) @[el2_lib.scala 408:36] - _T_775[2] <= _T_788 @[el2_lib.scala 408:30] - node _T_789 = bits(ic_miss_buff_half, 3, 3) @[el2_lib.scala 409:36] - _T_776[2] <= _T_789 @[el2_lib.scala 409:30] - node _T_790 = bits(ic_miss_buff_half, 3, 3) @[el2_lib.scala 410:36] - _T_777[2] <= _T_790 @[el2_lib.scala 410:30] - node _T_791 = bits(ic_miss_buff_half, 4, 4) @[el2_lib.scala 408:36] - _T_775[3] <= _T_791 @[el2_lib.scala 408:30] - node _T_792 = bits(ic_miss_buff_half, 4, 4) @[el2_lib.scala 411:36] - _T_778[0] <= _T_792 @[el2_lib.scala 411:30] - node _T_793 = bits(ic_miss_buff_half, 5, 5) @[el2_lib.scala 409:36] - _T_776[3] <= _T_793 @[el2_lib.scala 409:30] - node _T_794 = bits(ic_miss_buff_half, 5, 5) @[el2_lib.scala 411:36] - _T_778[1] <= _T_794 @[el2_lib.scala 411:30] - node _T_795 = bits(ic_miss_buff_half, 6, 6) @[el2_lib.scala 408:36] - _T_775[4] <= _T_795 @[el2_lib.scala 408:30] - node _T_796 = bits(ic_miss_buff_half, 6, 6) @[el2_lib.scala 409:36] - _T_776[4] <= _T_796 @[el2_lib.scala 409:30] - node _T_797 = bits(ic_miss_buff_half, 6, 6) @[el2_lib.scala 411:36] - _T_778[2] <= _T_797 @[el2_lib.scala 411:30] - node _T_798 = bits(ic_miss_buff_half, 7, 7) @[el2_lib.scala 410:36] - _T_777[3] <= _T_798 @[el2_lib.scala 410:30] - node _T_799 = bits(ic_miss_buff_half, 7, 7) @[el2_lib.scala 411:36] - _T_778[3] <= _T_799 @[el2_lib.scala 411:30] - node _T_800 = bits(ic_miss_buff_half, 8, 8) @[el2_lib.scala 408:36] - _T_775[5] <= _T_800 @[el2_lib.scala 408:30] - node _T_801 = bits(ic_miss_buff_half, 8, 8) @[el2_lib.scala 410:36] - _T_777[4] <= _T_801 @[el2_lib.scala 410:30] - node _T_802 = bits(ic_miss_buff_half, 8, 8) @[el2_lib.scala 411:36] - _T_778[4] <= _T_802 @[el2_lib.scala 411:30] - node _T_803 = bits(ic_miss_buff_half, 9, 9) @[el2_lib.scala 409:36] - _T_776[5] <= _T_803 @[el2_lib.scala 409:30] - node _T_804 = bits(ic_miss_buff_half, 9, 9) @[el2_lib.scala 410:36] - _T_777[5] <= _T_804 @[el2_lib.scala 410:30] - node _T_805 = bits(ic_miss_buff_half, 9, 9) @[el2_lib.scala 411:36] - _T_778[5] <= _T_805 @[el2_lib.scala 411:30] - node _T_806 = bits(ic_miss_buff_half, 10, 10) @[el2_lib.scala 408:36] - _T_775[6] <= _T_806 @[el2_lib.scala 408:30] - node _T_807 = bits(ic_miss_buff_half, 10, 10) @[el2_lib.scala 409:36] - _T_776[6] <= _T_807 @[el2_lib.scala 409:30] - node _T_808 = bits(ic_miss_buff_half, 10, 10) @[el2_lib.scala 410:36] - _T_777[6] <= _T_808 @[el2_lib.scala 410:30] - node _T_809 = bits(ic_miss_buff_half, 10, 10) @[el2_lib.scala 411:36] - _T_778[6] <= _T_809 @[el2_lib.scala 411:30] - node _T_810 = bits(ic_miss_buff_half, 11, 11) @[el2_lib.scala 408:36] - _T_775[7] <= _T_810 @[el2_lib.scala 408:30] - node _T_811 = bits(ic_miss_buff_half, 11, 11) @[el2_lib.scala 412:36] - _T_779[0] <= _T_811 @[el2_lib.scala 412:30] - node _T_812 = bits(ic_miss_buff_half, 12, 12) @[el2_lib.scala 409:36] - _T_776[7] <= _T_812 @[el2_lib.scala 409:30] - node _T_813 = bits(ic_miss_buff_half, 12, 12) @[el2_lib.scala 412:36] - _T_779[1] <= _T_813 @[el2_lib.scala 412:30] - node _T_814 = bits(ic_miss_buff_half, 13, 13) @[el2_lib.scala 408:36] - _T_775[8] <= _T_814 @[el2_lib.scala 408:30] - node _T_815 = bits(ic_miss_buff_half, 13, 13) @[el2_lib.scala 409:36] - _T_776[8] <= _T_815 @[el2_lib.scala 409:30] - node _T_816 = bits(ic_miss_buff_half, 13, 13) @[el2_lib.scala 412:36] - _T_779[2] <= _T_816 @[el2_lib.scala 412:30] - node _T_817 = bits(ic_miss_buff_half, 14, 14) @[el2_lib.scala 410:36] - _T_777[7] <= _T_817 @[el2_lib.scala 410:30] - node _T_818 = bits(ic_miss_buff_half, 14, 14) @[el2_lib.scala 412:36] - _T_779[3] <= _T_818 @[el2_lib.scala 412:30] - node _T_819 = bits(ic_miss_buff_half, 15, 15) @[el2_lib.scala 408:36] - _T_775[9] <= _T_819 @[el2_lib.scala 408:30] - node _T_820 = bits(ic_miss_buff_half, 15, 15) @[el2_lib.scala 410:36] - _T_777[8] <= _T_820 @[el2_lib.scala 410:30] - node _T_821 = bits(ic_miss_buff_half, 15, 15) @[el2_lib.scala 412:36] - _T_779[4] <= _T_821 @[el2_lib.scala 412:30] - node _T_822 = bits(ic_miss_buff_half, 16, 16) @[el2_lib.scala 409:36] - _T_776[9] <= _T_822 @[el2_lib.scala 409:30] - node _T_823 = bits(ic_miss_buff_half, 16, 16) @[el2_lib.scala 410:36] - _T_777[9] <= _T_823 @[el2_lib.scala 410:30] - node _T_824 = bits(ic_miss_buff_half, 16, 16) @[el2_lib.scala 412:36] - _T_779[5] <= _T_824 @[el2_lib.scala 412:30] - node _T_825 = bits(ic_miss_buff_half, 17, 17) @[el2_lib.scala 408:36] - _T_775[10] <= _T_825 @[el2_lib.scala 408:30] - node _T_826 = bits(ic_miss_buff_half, 17, 17) @[el2_lib.scala 409:36] - _T_776[10] <= _T_826 @[el2_lib.scala 409:30] - node _T_827 = bits(ic_miss_buff_half, 17, 17) @[el2_lib.scala 410:36] - _T_777[10] <= _T_827 @[el2_lib.scala 410:30] - node _T_828 = bits(ic_miss_buff_half, 17, 17) @[el2_lib.scala 412:36] - _T_779[6] <= _T_828 @[el2_lib.scala 412:30] - node _T_829 = bits(ic_miss_buff_half, 18, 18) @[el2_lib.scala 411:36] - _T_778[7] <= _T_829 @[el2_lib.scala 411:30] - node _T_830 = bits(ic_miss_buff_half, 18, 18) @[el2_lib.scala 412:36] - _T_779[7] <= _T_830 @[el2_lib.scala 412:30] - node _T_831 = bits(ic_miss_buff_half, 19, 19) @[el2_lib.scala 408:36] - _T_775[11] <= _T_831 @[el2_lib.scala 408:30] - node _T_832 = bits(ic_miss_buff_half, 19, 19) @[el2_lib.scala 411:36] - _T_778[8] <= _T_832 @[el2_lib.scala 411:30] - node _T_833 = bits(ic_miss_buff_half, 19, 19) @[el2_lib.scala 412:36] - _T_779[8] <= _T_833 @[el2_lib.scala 412:30] - node _T_834 = bits(ic_miss_buff_half, 20, 20) @[el2_lib.scala 409:36] - _T_776[11] <= _T_834 @[el2_lib.scala 409:30] - node _T_835 = bits(ic_miss_buff_half, 20, 20) @[el2_lib.scala 411:36] - _T_778[9] <= _T_835 @[el2_lib.scala 411:30] - node _T_836 = bits(ic_miss_buff_half, 20, 20) @[el2_lib.scala 412:36] - _T_779[9] <= _T_836 @[el2_lib.scala 412:30] - node _T_837 = bits(ic_miss_buff_half, 21, 21) @[el2_lib.scala 408:36] - _T_775[12] <= _T_837 @[el2_lib.scala 408:30] - node _T_838 = bits(ic_miss_buff_half, 21, 21) @[el2_lib.scala 409:36] - _T_776[12] <= _T_838 @[el2_lib.scala 409:30] - node _T_839 = bits(ic_miss_buff_half, 21, 21) @[el2_lib.scala 411:36] - _T_778[10] <= _T_839 @[el2_lib.scala 411:30] - node _T_840 = bits(ic_miss_buff_half, 21, 21) @[el2_lib.scala 412:36] - _T_779[10] <= _T_840 @[el2_lib.scala 412:30] - node _T_841 = bits(ic_miss_buff_half, 22, 22) @[el2_lib.scala 410:36] - _T_777[11] <= _T_841 @[el2_lib.scala 410:30] - node _T_842 = bits(ic_miss_buff_half, 22, 22) @[el2_lib.scala 411:36] - _T_778[11] <= _T_842 @[el2_lib.scala 411:30] - node _T_843 = bits(ic_miss_buff_half, 22, 22) @[el2_lib.scala 412:36] - _T_779[11] <= _T_843 @[el2_lib.scala 412:30] - node _T_844 = bits(ic_miss_buff_half, 23, 23) @[el2_lib.scala 408:36] - _T_775[13] <= _T_844 @[el2_lib.scala 408:30] - node _T_845 = bits(ic_miss_buff_half, 23, 23) @[el2_lib.scala 410:36] - _T_777[12] <= _T_845 @[el2_lib.scala 410:30] - node _T_846 = bits(ic_miss_buff_half, 23, 23) @[el2_lib.scala 411:36] - _T_778[12] <= _T_846 @[el2_lib.scala 411:30] - node _T_847 = bits(ic_miss_buff_half, 23, 23) @[el2_lib.scala 412:36] - _T_779[12] <= _T_847 @[el2_lib.scala 412:30] - node _T_848 = bits(ic_miss_buff_half, 24, 24) @[el2_lib.scala 409:36] - _T_776[13] <= _T_848 @[el2_lib.scala 409:30] - node _T_849 = bits(ic_miss_buff_half, 24, 24) @[el2_lib.scala 410:36] - _T_777[13] <= _T_849 @[el2_lib.scala 410:30] - node _T_850 = bits(ic_miss_buff_half, 24, 24) @[el2_lib.scala 411:36] - _T_778[13] <= _T_850 @[el2_lib.scala 411:30] - node _T_851 = bits(ic_miss_buff_half, 24, 24) @[el2_lib.scala 412:36] - _T_779[13] <= _T_851 @[el2_lib.scala 412:30] - node _T_852 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 408:36] - _T_775[14] <= _T_852 @[el2_lib.scala 408:30] - node _T_853 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 409:36] - _T_776[14] <= _T_853 @[el2_lib.scala 409:30] - node _T_854 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 410:36] - _T_777[14] <= _T_854 @[el2_lib.scala 410:30] - node _T_855 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 411:36] - _T_778[14] <= _T_855 @[el2_lib.scala 411:30] - node _T_856 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 412:36] - _T_779[14] <= _T_856 @[el2_lib.scala 412:30] - node _T_857 = bits(ic_miss_buff_half, 26, 26) @[el2_lib.scala 408:36] - _T_775[15] <= _T_857 @[el2_lib.scala 408:30] - node _T_858 = bits(ic_miss_buff_half, 26, 26) @[el2_lib.scala 413:36] - _T_780[0] <= _T_858 @[el2_lib.scala 413:30] - node _T_859 = bits(ic_miss_buff_half, 27, 27) @[el2_lib.scala 409:36] - _T_776[15] <= _T_859 @[el2_lib.scala 409:30] - node _T_860 = bits(ic_miss_buff_half, 27, 27) @[el2_lib.scala 413:36] - _T_780[1] <= _T_860 @[el2_lib.scala 413:30] - node _T_861 = bits(ic_miss_buff_half, 28, 28) @[el2_lib.scala 408:36] - _T_775[16] <= _T_861 @[el2_lib.scala 408:30] - node _T_862 = bits(ic_miss_buff_half, 28, 28) @[el2_lib.scala 409:36] - _T_776[16] <= _T_862 @[el2_lib.scala 409:30] - node _T_863 = bits(ic_miss_buff_half, 28, 28) @[el2_lib.scala 413:36] - _T_780[2] <= _T_863 @[el2_lib.scala 413:30] - node _T_864 = bits(ic_miss_buff_half, 29, 29) @[el2_lib.scala 410:36] - _T_777[15] <= _T_864 @[el2_lib.scala 410:30] - node _T_865 = bits(ic_miss_buff_half, 29, 29) @[el2_lib.scala 413:36] - _T_780[3] <= _T_865 @[el2_lib.scala 413:30] - node _T_866 = bits(ic_miss_buff_half, 30, 30) @[el2_lib.scala 408:36] - _T_775[17] <= _T_866 @[el2_lib.scala 408:30] - node _T_867 = bits(ic_miss_buff_half, 30, 30) @[el2_lib.scala 410:36] - _T_777[16] <= _T_867 @[el2_lib.scala 410:30] - node _T_868 = bits(ic_miss_buff_half, 30, 30) @[el2_lib.scala 413:36] - _T_780[4] <= _T_868 @[el2_lib.scala 413:30] - node _T_869 = bits(ic_miss_buff_half, 31, 31) @[el2_lib.scala 409:36] - _T_776[17] <= _T_869 @[el2_lib.scala 409:30] - node _T_870 = bits(ic_miss_buff_half, 31, 31) @[el2_lib.scala 410:36] - _T_777[17] <= _T_870 @[el2_lib.scala 410:30] - node _T_871 = bits(ic_miss_buff_half, 31, 31) @[el2_lib.scala 413:36] - _T_780[5] <= _T_871 @[el2_lib.scala 413:30] - node _T_872 = bits(ic_miss_buff_half, 32, 32) @[el2_lib.scala 408:36] - _T_775[18] <= _T_872 @[el2_lib.scala 408:30] - node _T_873 = bits(ic_miss_buff_half, 32, 32) @[el2_lib.scala 409:36] - _T_776[18] <= _T_873 @[el2_lib.scala 409:30] - node _T_874 = bits(ic_miss_buff_half, 32, 32) @[el2_lib.scala 410:36] - _T_777[18] <= _T_874 @[el2_lib.scala 410:30] - node _T_875 = bits(ic_miss_buff_half, 32, 32) @[el2_lib.scala 413:36] - _T_780[6] <= _T_875 @[el2_lib.scala 413:30] - node _T_876 = bits(ic_miss_buff_half, 33, 33) @[el2_lib.scala 411:36] - _T_778[15] <= _T_876 @[el2_lib.scala 411:30] - node _T_877 = bits(ic_miss_buff_half, 33, 33) @[el2_lib.scala 413:36] - _T_780[7] <= _T_877 @[el2_lib.scala 413:30] - node _T_878 = bits(ic_miss_buff_half, 34, 34) @[el2_lib.scala 408:36] - _T_775[19] <= _T_878 @[el2_lib.scala 408:30] - node _T_879 = bits(ic_miss_buff_half, 34, 34) @[el2_lib.scala 411:36] - _T_778[16] <= _T_879 @[el2_lib.scala 411:30] - node _T_880 = bits(ic_miss_buff_half, 34, 34) @[el2_lib.scala 413:36] - _T_780[8] <= _T_880 @[el2_lib.scala 413:30] - node _T_881 = bits(ic_miss_buff_half, 35, 35) @[el2_lib.scala 409:36] - _T_776[19] <= _T_881 @[el2_lib.scala 409:30] - node _T_882 = bits(ic_miss_buff_half, 35, 35) @[el2_lib.scala 411:36] - _T_778[17] <= _T_882 @[el2_lib.scala 411:30] - node _T_883 = bits(ic_miss_buff_half, 35, 35) @[el2_lib.scala 413:36] - _T_780[9] <= _T_883 @[el2_lib.scala 413:30] - node _T_884 = bits(ic_miss_buff_half, 36, 36) @[el2_lib.scala 408:36] - _T_775[20] <= _T_884 @[el2_lib.scala 408:30] - node _T_885 = bits(ic_miss_buff_half, 36, 36) @[el2_lib.scala 409:36] - _T_776[20] <= _T_885 @[el2_lib.scala 409:30] - node _T_886 = bits(ic_miss_buff_half, 36, 36) @[el2_lib.scala 411:36] - _T_778[18] <= _T_886 @[el2_lib.scala 411:30] - node _T_887 = bits(ic_miss_buff_half, 36, 36) @[el2_lib.scala 413:36] - _T_780[10] <= _T_887 @[el2_lib.scala 413:30] - node _T_888 = bits(ic_miss_buff_half, 37, 37) @[el2_lib.scala 410:36] - _T_777[19] <= _T_888 @[el2_lib.scala 410:30] - node _T_889 = bits(ic_miss_buff_half, 37, 37) @[el2_lib.scala 411:36] - _T_778[19] <= _T_889 @[el2_lib.scala 411:30] - node _T_890 = bits(ic_miss_buff_half, 37, 37) @[el2_lib.scala 413:36] - _T_780[11] <= _T_890 @[el2_lib.scala 413:30] - node _T_891 = bits(ic_miss_buff_half, 38, 38) @[el2_lib.scala 408:36] - _T_775[21] <= _T_891 @[el2_lib.scala 408:30] - node _T_892 = bits(ic_miss_buff_half, 38, 38) @[el2_lib.scala 410:36] - _T_777[20] <= _T_892 @[el2_lib.scala 410:30] - node _T_893 = bits(ic_miss_buff_half, 38, 38) @[el2_lib.scala 411:36] - _T_778[20] <= _T_893 @[el2_lib.scala 411:30] - node _T_894 = bits(ic_miss_buff_half, 38, 38) @[el2_lib.scala 413:36] - _T_780[12] <= _T_894 @[el2_lib.scala 413:30] - node _T_895 = bits(ic_miss_buff_half, 39, 39) @[el2_lib.scala 409:36] - _T_776[21] <= _T_895 @[el2_lib.scala 409:30] - node _T_896 = bits(ic_miss_buff_half, 39, 39) @[el2_lib.scala 410:36] - _T_777[21] <= _T_896 @[el2_lib.scala 410:30] - node _T_897 = bits(ic_miss_buff_half, 39, 39) @[el2_lib.scala 411:36] - _T_778[21] <= _T_897 @[el2_lib.scala 411:30] - node _T_898 = bits(ic_miss_buff_half, 39, 39) @[el2_lib.scala 413:36] - _T_780[13] <= _T_898 @[el2_lib.scala 413:30] - node _T_899 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 408:36] - _T_775[22] <= _T_899 @[el2_lib.scala 408:30] - node _T_900 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 409:36] - _T_776[22] <= _T_900 @[el2_lib.scala 409:30] - node _T_901 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 410:36] - _T_777[22] <= _T_901 @[el2_lib.scala 410:30] - node _T_902 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 411:36] - _T_778[22] <= _T_902 @[el2_lib.scala 411:30] - node _T_903 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 413:36] - _T_780[14] <= _T_903 @[el2_lib.scala 413:30] - node _T_904 = bits(ic_miss_buff_half, 41, 41) @[el2_lib.scala 412:36] - _T_779[15] <= _T_904 @[el2_lib.scala 412:30] - node _T_905 = bits(ic_miss_buff_half, 41, 41) @[el2_lib.scala 413:36] - _T_780[15] <= _T_905 @[el2_lib.scala 413:30] - node _T_906 = bits(ic_miss_buff_half, 42, 42) @[el2_lib.scala 408:36] - _T_775[23] <= _T_906 @[el2_lib.scala 408:30] - node _T_907 = bits(ic_miss_buff_half, 42, 42) @[el2_lib.scala 412:36] - _T_779[16] <= _T_907 @[el2_lib.scala 412:30] - node _T_908 = bits(ic_miss_buff_half, 42, 42) @[el2_lib.scala 413:36] - _T_780[16] <= _T_908 @[el2_lib.scala 413:30] - node _T_909 = bits(ic_miss_buff_half, 43, 43) @[el2_lib.scala 409:36] - _T_776[23] <= _T_909 @[el2_lib.scala 409:30] - node _T_910 = bits(ic_miss_buff_half, 43, 43) @[el2_lib.scala 412:36] - _T_779[17] <= _T_910 @[el2_lib.scala 412:30] - node _T_911 = bits(ic_miss_buff_half, 43, 43) @[el2_lib.scala 413:36] - _T_780[17] <= _T_911 @[el2_lib.scala 413:30] - node _T_912 = bits(ic_miss_buff_half, 44, 44) @[el2_lib.scala 408:36] - _T_775[24] <= _T_912 @[el2_lib.scala 408:30] - node _T_913 = bits(ic_miss_buff_half, 44, 44) @[el2_lib.scala 409:36] - _T_776[24] <= _T_913 @[el2_lib.scala 409:30] - node _T_914 = bits(ic_miss_buff_half, 44, 44) @[el2_lib.scala 412:36] - _T_779[18] <= _T_914 @[el2_lib.scala 412:30] - node _T_915 = bits(ic_miss_buff_half, 44, 44) @[el2_lib.scala 413:36] - _T_780[18] <= _T_915 @[el2_lib.scala 413:30] - node _T_916 = bits(ic_miss_buff_half, 45, 45) @[el2_lib.scala 410:36] - _T_777[23] <= _T_916 @[el2_lib.scala 410:30] - node _T_917 = bits(ic_miss_buff_half, 45, 45) @[el2_lib.scala 412:36] - _T_779[19] <= _T_917 @[el2_lib.scala 412:30] - node _T_918 = bits(ic_miss_buff_half, 45, 45) @[el2_lib.scala 413:36] - _T_780[19] <= _T_918 @[el2_lib.scala 413:30] - node _T_919 = bits(ic_miss_buff_half, 46, 46) @[el2_lib.scala 408:36] - _T_775[25] <= _T_919 @[el2_lib.scala 408:30] - node _T_920 = bits(ic_miss_buff_half, 46, 46) @[el2_lib.scala 410:36] - _T_777[24] <= _T_920 @[el2_lib.scala 410:30] - node _T_921 = bits(ic_miss_buff_half, 46, 46) @[el2_lib.scala 412:36] - _T_779[20] <= _T_921 @[el2_lib.scala 412:30] - node _T_922 = bits(ic_miss_buff_half, 46, 46) @[el2_lib.scala 413:36] - _T_780[20] <= _T_922 @[el2_lib.scala 413:30] - node _T_923 = bits(ic_miss_buff_half, 47, 47) @[el2_lib.scala 409:36] - _T_776[25] <= _T_923 @[el2_lib.scala 409:30] - node _T_924 = bits(ic_miss_buff_half, 47, 47) @[el2_lib.scala 410:36] - _T_777[25] <= _T_924 @[el2_lib.scala 410:30] - node _T_925 = bits(ic_miss_buff_half, 47, 47) @[el2_lib.scala 412:36] - _T_779[21] <= _T_925 @[el2_lib.scala 412:30] - node _T_926 = bits(ic_miss_buff_half, 47, 47) @[el2_lib.scala 413:36] - _T_780[21] <= _T_926 @[el2_lib.scala 413:30] - node _T_927 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 408:36] - _T_775[26] <= _T_927 @[el2_lib.scala 408:30] - node _T_928 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 409:36] - _T_776[26] <= _T_928 @[el2_lib.scala 409:30] - node _T_929 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 410:36] - _T_777[26] <= _T_929 @[el2_lib.scala 410:30] - node _T_930 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 412:36] - _T_779[22] <= _T_930 @[el2_lib.scala 412:30] - node _T_931 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 413:36] - _T_780[22] <= _T_931 @[el2_lib.scala 413:30] - node _T_932 = bits(ic_miss_buff_half, 49, 49) @[el2_lib.scala 411:36] - _T_778[23] <= _T_932 @[el2_lib.scala 411:30] - node _T_933 = bits(ic_miss_buff_half, 49, 49) @[el2_lib.scala 412:36] - _T_779[23] <= _T_933 @[el2_lib.scala 412:30] - node _T_934 = bits(ic_miss_buff_half, 49, 49) @[el2_lib.scala 413:36] - _T_780[23] <= _T_934 @[el2_lib.scala 413:30] - node _T_935 = bits(ic_miss_buff_half, 50, 50) @[el2_lib.scala 408:36] - _T_775[27] <= _T_935 @[el2_lib.scala 408:30] - node _T_936 = bits(ic_miss_buff_half, 50, 50) @[el2_lib.scala 411:36] - _T_778[24] <= _T_936 @[el2_lib.scala 411:30] - node _T_937 = bits(ic_miss_buff_half, 50, 50) @[el2_lib.scala 412:36] - _T_779[24] <= _T_937 @[el2_lib.scala 412:30] - node _T_938 = bits(ic_miss_buff_half, 50, 50) @[el2_lib.scala 413:36] - _T_780[24] <= _T_938 @[el2_lib.scala 413:30] - node _T_939 = bits(ic_miss_buff_half, 51, 51) @[el2_lib.scala 409:36] - _T_776[27] <= _T_939 @[el2_lib.scala 409:30] - node _T_940 = bits(ic_miss_buff_half, 51, 51) @[el2_lib.scala 411:36] - _T_778[25] <= _T_940 @[el2_lib.scala 411:30] - node _T_941 = bits(ic_miss_buff_half, 51, 51) @[el2_lib.scala 412:36] - _T_779[25] <= _T_941 @[el2_lib.scala 412:30] - node _T_942 = bits(ic_miss_buff_half, 51, 51) @[el2_lib.scala 413:36] - _T_780[25] <= _T_942 @[el2_lib.scala 413:30] - node _T_943 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 408:36] - _T_775[28] <= _T_943 @[el2_lib.scala 408:30] - node _T_944 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 409:36] - _T_776[28] <= _T_944 @[el2_lib.scala 409:30] - node _T_945 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 411:36] - _T_778[26] <= _T_945 @[el2_lib.scala 411:30] - node _T_946 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 412:36] - _T_779[26] <= _T_946 @[el2_lib.scala 412:30] - node _T_947 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 413:36] - _T_780[26] <= _T_947 @[el2_lib.scala 413:30] - node _T_948 = bits(ic_miss_buff_half, 53, 53) @[el2_lib.scala 410:36] - _T_777[27] <= _T_948 @[el2_lib.scala 410:30] - node _T_949 = bits(ic_miss_buff_half, 53, 53) @[el2_lib.scala 411:36] - _T_778[27] <= _T_949 @[el2_lib.scala 411:30] - node _T_950 = bits(ic_miss_buff_half, 53, 53) @[el2_lib.scala 412:36] - _T_779[27] <= _T_950 @[el2_lib.scala 412:30] - node _T_951 = bits(ic_miss_buff_half, 53, 53) @[el2_lib.scala 413:36] - _T_780[27] <= _T_951 @[el2_lib.scala 413:30] - node _T_952 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 408:36] - _T_775[29] <= _T_952 @[el2_lib.scala 408:30] - node _T_953 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 410:36] - _T_777[28] <= _T_953 @[el2_lib.scala 410:30] - node _T_954 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 411:36] - _T_778[28] <= _T_954 @[el2_lib.scala 411:30] - node _T_955 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 412:36] - _T_779[28] <= _T_955 @[el2_lib.scala 412:30] - node _T_956 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 413:36] - _T_780[28] <= _T_956 @[el2_lib.scala 413:30] - node _T_957 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 409:36] - _T_776[29] <= _T_957 @[el2_lib.scala 409:30] - node _T_958 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 410:36] - _T_777[29] <= _T_958 @[el2_lib.scala 410:30] - node _T_959 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 411:36] - _T_778[29] <= _T_959 @[el2_lib.scala 411:30] - node _T_960 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 412:36] - _T_779[29] <= _T_960 @[el2_lib.scala 412:30] - node _T_961 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 413:36] - _T_780[29] <= _T_961 @[el2_lib.scala 413:30] - node _T_962 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 408:36] - _T_775[30] <= _T_962 @[el2_lib.scala 408:30] - node _T_963 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 409:36] - _T_776[30] <= _T_963 @[el2_lib.scala 409:30] - node _T_964 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 410:36] - _T_777[30] <= _T_964 @[el2_lib.scala 410:30] - node _T_965 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 411:36] - _T_778[30] <= _T_965 @[el2_lib.scala 411:30] - node _T_966 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 412:36] - _T_779[30] <= _T_966 @[el2_lib.scala 412:30] - node _T_967 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 413:36] - _T_780[30] <= _T_967 @[el2_lib.scala 413:30] - node _T_968 = bits(ic_miss_buff_half, 57, 57) @[el2_lib.scala 408:36] - _T_775[31] <= _T_968 @[el2_lib.scala 408:30] - node _T_969 = bits(ic_miss_buff_half, 57, 57) @[el2_lib.scala 414:36] - _T_781[0] <= _T_969 @[el2_lib.scala 414:30] - node _T_970 = bits(ic_miss_buff_half, 58, 58) @[el2_lib.scala 409:36] - _T_776[31] <= _T_970 @[el2_lib.scala 409:30] - node _T_971 = bits(ic_miss_buff_half, 58, 58) @[el2_lib.scala 414:36] - _T_781[1] <= _T_971 @[el2_lib.scala 414:30] - node _T_972 = bits(ic_miss_buff_half, 59, 59) @[el2_lib.scala 408:36] - _T_775[32] <= _T_972 @[el2_lib.scala 408:30] - node _T_973 = bits(ic_miss_buff_half, 59, 59) @[el2_lib.scala 409:36] - _T_776[32] <= _T_973 @[el2_lib.scala 409:30] - node _T_974 = bits(ic_miss_buff_half, 59, 59) @[el2_lib.scala 414:36] - _T_781[2] <= _T_974 @[el2_lib.scala 414:30] - node _T_975 = bits(ic_miss_buff_half, 60, 60) @[el2_lib.scala 410:36] - _T_777[31] <= _T_975 @[el2_lib.scala 410:30] - node _T_976 = bits(ic_miss_buff_half, 60, 60) @[el2_lib.scala 414:36] - _T_781[3] <= _T_976 @[el2_lib.scala 414:30] - node _T_977 = bits(ic_miss_buff_half, 61, 61) @[el2_lib.scala 408:36] - _T_775[33] <= _T_977 @[el2_lib.scala 408:30] - node _T_978 = bits(ic_miss_buff_half, 61, 61) @[el2_lib.scala 410:36] - _T_777[32] <= _T_978 @[el2_lib.scala 410:30] - node _T_979 = bits(ic_miss_buff_half, 61, 61) @[el2_lib.scala 414:36] - _T_781[4] <= _T_979 @[el2_lib.scala 414:30] - node _T_980 = bits(ic_miss_buff_half, 62, 62) @[el2_lib.scala 409:36] - _T_776[33] <= _T_980 @[el2_lib.scala 409:30] - node _T_981 = bits(ic_miss_buff_half, 62, 62) @[el2_lib.scala 410:36] - _T_777[33] <= _T_981 @[el2_lib.scala 410:30] - node _T_982 = bits(ic_miss_buff_half, 62, 62) @[el2_lib.scala 414:36] - _T_781[5] <= _T_982 @[el2_lib.scala 414:30] - node _T_983 = bits(ic_miss_buff_half, 63, 63) @[el2_lib.scala 408:36] - _T_775[34] <= _T_983 @[el2_lib.scala 408:30] - node _T_984 = bits(ic_miss_buff_half, 63, 63) @[el2_lib.scala 409:36] - _T_776[34] <= _T_984 @[el2_lib.scala 409:30] - node _T_985 = bits(ic_miss_buff_half, 63, 63) @[el2_lib.scala 410:36] - _T_777[34] <= _T_985 @[el2_lib.scala 410:30] - node _T_986 = bits(ic_miss_buff_half, 63, 63) @[el2_lib.scala 414:36] - _T_781[6] <= _T_986 @[el2_lib.scala 414:30] - node _T_987 = cat(_T_781[2], _T_781[1]) @[el2_lib.scala 416:13] - node _T_988 = cat(_T_987, _T_781[0]) @[el2_lib.scala 416:13] - node _T_989 = cat(_T_781[4], _T_781[3]) @[el2_lib.scala 416:13] - node _T_990 = cat(_T_781[6], _T_781[5]) @[el2_lib.scala 416:13] - node _T_991 = cat(_T_990, _T_989) @[el2_lib.scala 416:13] - node _T_992 = cat(_T_991, _T_988) @[el2_lib.scala 416:13] - node _T_993 = xorr(_T_992) @[el2_lib.scala 416:20] - node _T_994 = cat(_T_780[2], _T_780[1]) @[el2_lib.scala 416:30] - node _T_995 = cat(_T_994, _T_780[0]) @[el2_lib.scala 416:30] - node _T_996 = cat(_T_780[4], _T_780[3]) @[el2_lib.scala 416:30] - node _T_997 = cat(_T_780[6], _T_780[5]) @[el2_lib.scala 416:30] - node _T_998 = cat(_T_997, _T_996) @[el2_lib.scala 416:30] - node _T_999 = cat(_T_998, _T_995) @[el2_lib.scala 416:30] - node _T_1000 = cat(_T_780[8], _T_780[7]) @[el2_lib.scala 416:30] - node _T_1001 = cat(_T_780[10], _T_780[9]) @[el2_lib.scala 416:30] - node _T_1002 = cat(_T_1001, _T_1000) @[el2_lib.scala 416:30] - node _T_1003 = cat(_T_780[12], _T_780[11]) @[el2_lib.scala 416:30] - node _T_1004 = cat(_T_780[14], _T_780[13]) @[el2_lib.scala 416:30] - node _T_1005 = cat(_T_1004, _T_1003) @[el2_lib.scala 416:30] - node _T_1006 = cat(_T_1005, _T_1002) @[el2_lib.scala 416:30] - node _T_1007 = cat(_T_1006, _T_999) @[el2_lib.scala 416:30] - node _T_1008 = cat(_T_780[16], _T_780[15]) @[el2_lib.scala 416:30] - node _T_1009 = cat(_T_780[18], _T_780[17]) @[el2_lib.scala 416:30] - node _T_1010 = cat(_T_1009, _T_1008) @[el2_lib.scala 416:30] - node _T_1011 = cat(_T_780[20], _T_780[19]) @[el2_lib.scala 416:30] - node _T_1012 = cat(_T_780[22], _T_780[21]) @[el2_lib.scala 416:30] - node _T_1013 = cat(_T_1012, _T_1011) @[el2_lib.scala 416:30] - node _T_1014 = cat(_T_1013, _T_1010) @[el2_lib.scala 416:30] - node _T_1015 = cat(_T_780[24], _T_780[23]) @[el2_lib.scala 416:30] - node _T_1016 = cat(_T_780[26], _T_780[25]) @[el2_lib.scala 416:30] - node _T_1017 = cat(_T_1016, _T_1015) @[el2_lib.scala 416:30] - node _T_1018 = cat(_T_780[28], _T_780[27]) @[el2_lib.scala 416:30] - node _T_1019 = cat(_T_780[30], _T_780[29]) @[el2_lib.scala 416:30] - node _T_1020 = cat(_T_1019, _T_1018) @[el2_lib.scala 416:30] - node _T_1021 = cat(_T_1020, _T_1017) @[el2_lib.scala 416:30] - node _T_1022 = cat(_T_1021, _T_1014) @[el2_lib.scala 416:30] - node _T_1023 = cat(_T_1022, _T_1007) @[el2_lib.scala 416:30] - node _T_1024 = xorr(_T_1023) @[el2_lib.scala 416:37] - node _T_1025 = cat(_T_779[2], _T_779[1]) @[el2_lib.scala 416:47] - node _T_1026 = cat(_T_1025, _T_779[0]) @[el2_lib.scala 416:47] - node _T_1027 = cat(_T_779[4], _T_779[3]) @[el2_lib.scala 416:47] - node _T_1028 = cat(_T_779[6], _T_779[5]) @[el2_lib.scala 416:47] - node _T_1029 = cat(_T_1028, _T_1027) @[el2_lib.scala 416:47] - node _T_1030 = cat(_T_1029, _T_1026) @[el2_lib.scala 416:47] - node _T_1031 = cat(_T_779[8], _T_779[7]) @[el2_lib.scala 416:47] - node _T_1032 = cat(_T_779[10], _T_779[9]) @[el2_lib.scala 416:47] - node _T_1033 = cat(_T_1032, _T_1031) @[el2_lib.scala 416:47] - node _T_1034 = cat(_T_779[12], _T_779[11]) @[el2_lib.scala 416:47] - node _T_1035 = cat(_T_779[14], _T_779[13]) @[el2_lib.scala 416:47] - node _T_1036 = cat(_T_1035, _T_1034) @[el2_lib.scala 416:47] - node _T_1037 = cat(_T_1036, _T_1033) @[el2_lib.scala 416:47] - node _T_1038 = cat(_T_1037, _T_1030) @[el2_lib.scala 416:47] - node _T_1039 = cat(_T_779[16], _T_779[15]) @[el2_lib.scala 416:47] - node _T_1040 = cat(_T_779[18], _T_779[17]) @[el2_lib.scala 416:47] - node _T_1041 = cat(_T_1040, _T_1039) @[el2_lib.scala 416:47] - node _T_1042 = cat(_T_779[20], _T_779[19]) @[el2_lib.scala 416:47] - node _T_1043 = cat(_T_779[22], _T_779[21]) @[el2_lib.scala 416:47] - node _T_1044 = cat(_T_1043, _T_1042) @[el2_lib.scala 416:47] - node _T_1045 = cat(_T_1044, _T_1041) @[el2_lib.scala 416:47] - node _T_1046 = cat(_T_779[24], _T_779[23]) @[el2_lib.scala 416:47] - node _T_1047 = cat(_T_779[26], _T_779[25]) @[el2_lib.scala 416:47] - node _T_1048 = cat(_T_1047, _T_1046) @[el2_lib.scala 416:47] - node _T_1049 = cat(_T_779[28], _T_779[27]) @[el2_lib.scala 416:47] - node _T_1050 = cat(_T_779[30], _T_779[29]) @[el2_lib.scala 416:47] - node _T_1051 = cat(_T_1050, _T_1049) @[el2_lib.scala 416:47] - node _T_1052 = cat(_T_1051, _T_1048) @[el2_lib.scala 416:47] - node _T_1053 = cat(_T_1052, _T_1045) @[el2_lib.scala 416:47] - node _T_1054 = cat(_T_1053, _T_1038) @[el2_lib.scala 416:47] - node _T_1055 = xorr(_T_1054) @[el2_lib.scala 416:54] - node _T_1056 = cat(_T_778[2], _T_778[1]) @[el2_lib.scala 416:64] - node _T_1057 = cat(_T_1056, _T_778[0]) @[el2_lib.scala 416:64] - node _T_1058 = cat(_T_778[4], _T_778[3]) @[el2_lib.scala 416:64] - node _T_1059 = cat(_T_778[6], _T_778[5]) @[el2_lib.scala 416:64] - node _T_1060 = cat(_T_1059, _T_1058) @[el2_lib.scala 416:64] - node _T_1061 = cat(_T_1060, _T_1057) @[el2_lib.scala 416:64] - node _T_1062 = cat(_T_778[8], _T_778[7]) @[el2_lib.scala 416:64] - node _T_1063 = cat(_T_778[10], _T_778[9]) @[el2_lib.scala 416:64] - node _T_1064 = cat(_T_1063, _T_1062) @[el2_lib.scala 416:64] - node _T_1065 = cat(_T_778[12], _T_778[11]) @[el2_lib.scala 416:64] - node _T_1066 = cat(_T_778[14], _T_778[13]) @[el2_lib.scala 416:64] - node _T_1067 = cat(_T_1066, _T_1065) @[el2_lib.scala 416:64] - node _T_1068 = cat(_T_1067, _T_1064) @[el2_lib.scala 416:64] - node _T_1069 = cat(_T_1068, _T_1061) @[el2_lib.scala 416:64] - node _T_1070 = cat(_T_778[16], _T_778[15]) @[el2_lib.scala 416:64] - node _T_1071 = cat(_T_778[18], _T_778[17]) @[el2_lib.scala 416:64] - node _T_1072 = cat(_T_1071, _T_1070) @[el2_lib.scala 416:64] - node _T_1073 = cat(_T_778[20], _T_778[19]) @[el2_lib.scala 416:64] - node _T_1074 = cat(_T_778[22], _T_778[21]) @[el2_lib.scala 416:64] - node _T_1075 = cat(_T_1074, _T_1073) @[el2_lib.scala 416:64] - node _T_1076 = cat(_T_1075, _T_1072) @[el2_lib.scala 416:64] - node _T_1077 = cat(_T_778[24], _T_778[23]) @[el2_lib.scala 416:64] - node _T_1078 = cat(_T_778[26], _T_778[25]) @[el2_lib.scala 416:64] - node _T_1079 = cat(_T_1078, _T_1077) @[el2_lib.scala 416:64] - node _T_1080 = cat(_T_778[28], _T_778[27]) @[el2_lib.scala 416:64] - node _T_1081 = cat(_T_778[30], _T_778[29]) @[el2_lib.scala 416:64] - node _T_1082 = cat(_T_1081, _T_1080) @[el2_lib.scala 416:64] - node _T_1083 = cat(_T_1082, _T_1079) @[el2_lib.scala 416:64] - node _T_1084 = cat(_T_1083, _T_1076) @[el2_lib.scala 416:64] - node _T_1085 = cat(_T_1084, _T_1069) @[el2_lib.scala 416:64] - node _T_1086 = xorr(_T_1085) @[el2_lib.scala 416:71] - node _T_1087 = cat(_T_777[1], _T_777[0]) @[el2_lib.scala 416:81] - node _T_1088 = cat(_T_777[3], _T_777[2]) @[el2_lib.scala 416:81] - node _T_1089 = cat(_T_1088, _T_1087) @[el2_lib.scala 416:81] - node _T_1090 = cat(_T_777[5], _T_777[4]) @[el2_lib.scala 416:81] - node _T_1091 = cat(_T_777[7], _T_777[6]) @[el2_lib.scala 416:81] - node _T_1092 = cat(_T_1091, _T_1090) @[el2_lib.scala 416:81] - node _T_1093 = cat(_T_1092, _T_1089) @[el2_lib.scala 416:81] - node _T_1094 = cat(_T_777[9], _T_777[8]) @[el2_lib.scala 416:81] - node _T_1095 = cat(_T_777[11], _T_777[10]) @[el2_lib.scala 416:81] - node _T_1096 = cat(_T_1095, _T_1094) @[el2_lib.scala 416:81] - node _T_1097 = cat(_T_777[13], _T_777[12]) @[el2_lib.scala 416:81] - node _T_1098 = cat(_T_777[16], _T_777[15]) @[el2_lib.scala 416:81] - node _T_1099 = cat(_T_1098, _T_777[14]) @[el2_lib.scala 416:81] - node _T_1100 = cat(_T_1099, _T_1097) @[el2_lib.scala 416:81] - node _T_1101 = cat(_T_1100, _T_1096) @[el2_lib.scala 416:81] - node _T_1102 = cat(_T_1101, _T_1093) @[el2_lib.scala 416:81] - node _T_1103 = cat(_T_777[18], _T_777[17]) @[el2_lib.scala 416:81] - node _T_1104 = cat(_T_777[20], _T_777[19]) @[el2_lib.scala 416:81] - node _T_1105 = cat(_T_1104, _T_1103) @[el2_lib.scala 416:81] - node _T_1106 = cat(_T_777[22], _T_777[21]) @[el2_lib.scala 416:81] - node _T_1107 = cat(_T_777[25], _T_777[24]) @[el2_lib.scala 416:81] - node _T_1108 = cat(_T_1107, _T_777[23]) @[el2_lib.scala 416:81] - node _T_1109 = cat(_T_1108, _T_1106) @[el2_lib.scala 416:81] - node _T_1110 = cat(_T_1109, _T_1105) @[el2_lib.scala 416:81] - node _T_1111 = cat(_T_777[27], _T_777[26]) @[el2_lib.scala 416:81] - node _T_1112 = cat(_T_777[29], _T_777[28]) @[el2_lib.scala 416:81] - node _T_1113 = cat(_T_1112, _T_1111) @[el2_lib.scala 416:81] - node _T_1114 = cat(_T_777[31], _T_777[30]) @[el2_lib.scala 416:81] - node _T_1115 = cat(_T_777[34], _T_777[33]) @[el2_lib.scala 416:81] - node _T_1116 = cat(_T_1115, _T_777[32]) @[el2_lib.scala 416:81] - node _T_1117 = cat(_T_1116, _T_1114) @[el2_lib.scala 416:81] - node _T_1118 = cat(_T_1117, _T_1113) @[el2_lib.scala 416:81] - node _T_1119 = cat(_T_1118, _T_1110) @[el2_lib.scala 416:81] - node _T_1120 = cat(_T_1119, _T_1102) @[el2_lib.scala 416:81] - node _T_1121 = xorr(_T_1120) @[el2_lib.scala 416:88] - node _T_1122 = cat(_T_776[1], _T_776[0]) @[el2_lib.scala 416:98] - node _T_1123 = cat(_T_776[3], _T_776[2]) @[el2_lib.scala 416:98] - node _T_1124 = cat(_T_1123, _T_1122) @[el2_lib.scala 416:98] - node _T_1125 = cat(_T_776[5], _T_776[4]) @[el2_lib.scala 416:98] - node _T_1126 = cat(_T_776[7], _T_776[6]) @[el2_lib.scala 416:98] - node _T_1127 = cat(_T_1126, _T_1125) @[el2_lib.scala 416:98] - node _T_1128 = cat(_T_1127, _T_1124) @[el2_lib.scala 416:98] - node _T_1129 = cat(_T_776[9], _T_776[8]) @[el2_lib.scala 416:98] - node _T_1130 = cat(_T_776[11], _T_776[10]) @[el2_lib.scala 416:98] - node _T_1131 = cat(_T_1130, _T_1129) @[el2_lib.scala 416:98] - node _T_1132 = cat(_T_776[13], _T_776[12]) @[el2_lib.scala 416:98] - node _T_1133 = cat(_T_776[16], _T_776[15]) @[el2_lib.scala 416:98] - node _T_1134 = cat(_T_1133, _T_776[14]) @[el2_lib.scala 416:98] - node _T_1135 = cat(_T_1134, _T_1132) @[el2_lib.scala 416:98] - node _T_1136 = cat(_T_1135, _T_1131) @[el2_lib.scala 416:98] - node _T_1137 = cat(_T_1136, _T_1128) @[el2_lib.scala 416:98] - node _T_1138 = cat(_T_776[18], _T_776[17]) @[el2_lib.scala 416:98] - node _T_1139 = cat(_T_776[20], _T_776[19]) @[el2_lib.scala 416:98] - node _T_1140 = cat(_T_1139, _T_1138) @[el2_lib.scala 416:98] - node _T_1141 = cat(_T_776[22], _T_776[21]) @[el2_lib.scala 416:98] - node _T_1142 = cat(_T_776[25], _T_776[24]) @[el2_lib.scala 416:98] - node _T_1143 = cat(_T_1142, _T_776[23]) @[el2_lib.scala 416:98] - node _T_1144 = cat(_T_1143, _T_1141) @[el2_lib.scala 416:98] - node _T_1145 = cat(_T_1144, _T_1140) @[el2_lib.scala 416:98] - node _T_1146 = cat(_T_776[27], _T_776[26]) @[el2_lib.scala 416:98] - node _T_1147 = cat(_T_776[29], _T_776[28]) @[el2_lib.scala 416:98] - node _T_1148 = cat(_T_1147, _T_1146) @[el2_lib.scala 416:98] - node _T_1149 = cat(_T_776[31], _T_776[30]) @[el2_lib.scala 416:98] - node _T_1150 = cat(_T_776[34], _T_776[33]) @[el2_lib.scala 416:98] - node _T_1151 = cat(_T_1150, _T_776[32]) @[el2_lib.scala 416:98] - node _T_1152 = cat(_T_1151, _T_1149) @[el2_lib.scala 416:98] - node _T_1153 = cat(_T_1152, _T_1148) @[el2_lib.scala 416:98] - node _T_1154 = cat(_T_1153, _T_1145) @[el2_lib.scala 416:98] - node _T_1155 = cat(_T_1154, _T_1137) @[el2_lib.scala 416:98] - node _T_1156 = xorr(_T_1155) @[el2_lib.scala 416:105] - node _T_1157 = cat(_T_775[1], _T_775[0]) @[el2_lib.scala 416:115] - node _T_1158 = cat(_T_775[3], _T_775[2]) @[el2_lib.scala 416:115] - node _T_1159 = cat(_T_1158, _T_1157) @[el2_lib.scala 416:115] - node _T_1160 = cat(_T_775[5], _T_775[4]) @[el2_lib.scala 416:115] - node _T_1161 = cat(_T_775[7], _T_775[6]) @[el2_lib.scala 416:115] - node _T_1162 = cat(_T_1161, _T_1160) @[el2_lib.scala 416:115] - node _T_1163 = cat(_T_1162, _T_1159) @[el2_lib.scala 416:115] - node _T_1164 = cat(_T_775[9], _T_775[8]) @[el2_lib.scala 416:115] - node _T_1165 = cat(_T_775[11], _T_775[10]) @[el2_lib.scala 416:115] - node _T_1166 = cat(_T_1165, _T_1164) @[el2_lib.scala 416:115] - node _T_1167 = cat(_T_775[13], _T_775[12]) @[el2_lib.scala 416:115] - node _T_1168 = cat(_T_775[16], _T_775[15]) @[el2_lib.scala 416:115] - node _T_1169 = cat(_T_1168, _T_775[14]) @[el2_lib.scala 416:115] - node _T_1170 = cat(_T_1169, _T_1167) @[el2_lib.scala 416:115] - node _T_1171 = cat(_T_1170, _T_1166) @[el2_lib.scala 416:115] - node _T_1172 = cat(_T_1171, _T_1163) @[el2_lib.scala 416:115] - node _T_1173 = cat(_T_775[18], _T_775[17]) @[el2_lib.scala 416:115] - node _T_1174 = cat(_T_775[20], _T_775[19]) @[el2_lib.scala 416:115] - node _T_1175 = cat(_T_1174, _T_1173) @[el2_lib.scala 416:115] - node _T_1176 = cat(_T_775[22], _T_775[21]) @[el2_lib.scala 416:115] - node _T_1177 = cat(_T_775[25], _T_775[24]) @[el2_lib.scala 416:115] - node _T_1178 = cat(_T_1177, _T_775[23]) @[el2_lib.scala 416:115] - node _T_1179 = cat(_T_1178, _T_1176) @[el2_lib.scala 416:115] - node _T_1180 = cat(_T_1179, _T_1175) @[el2_lib.scala 416:115] - node _T_1181 = cat(_T_775[27], _T_775[26]) @[el2_lib.scala 416:115] - node _T_1182 = cat(_T_775[29], _T_775[28]) @[el2_lib.scala 416:115] - node _T_1183 = cat(_T_1182, _T_1181) @[el2_lib.scala 416:115] - node _T_1184 = cat(_T_775[31], _T_775[30]) @[el2_lib.scala 416:115] - node _T_1185 = cat(_T_775[34], _T_775[33]) @[el2_lib.scala 416:115] - node _T_1186 = cat(_T_1185, _T_775[32]) @[el2_lib.scala 416:115] - node _T_1187 = cat(_T_1186, _T_1184) @[el2_lib.scala 416:115] - node _T_1188 = cat(_T_1187, _T_1183) @[el2_lib.scala 416:115] - node _T_1189 = cat(_T_1188, _T_1180) @[el2_lib.scala 416:115] - node _T_1190 = cat(_T_1189, _T_1172) @[el2_lib.scala 416:115] - node _T_1191 = xorr(_T_1190) @[el2_lib.scala 416:122] + wire _T_775 : UInt<1>[35] @[lib.scala 255:18] + wire _T_776 : UInt<1>[35] @[lib.scala 256:18] + wire _T_777 : UInt<1>[35] @[lib.scala 257:18] + wire _T_778 : UInt<1>[31] @[lib.scala 258:18] + wire _T_779 : UInt<1>[31] @[lib.scala 259:18] + wire _T_780 : UInt<1>[31] @[lib.scala 260:18] + wire _T_781 : UInt<1>[7] @[lib.scala 261:18] + node _T_782 = bits(ic_miss_buff_half, 0, 0) @[lib.scala 268:36] + _T_775[0] <= _T_782 @[lib.scala 268:30] + node _T_783 = bits(ic_miss_buff_half, 0, 0) @[lib.scala 269:36] + _T_776[0] <= _T_783 @[lib.scala 269:30] + node _T_784 = bits(ic_miss_buff_half, 1, 1) @[lib.scala 268:36] + _T_775[1] <= _T_784 @[lib.scala 268:30] + node _T_785 = bits(ic_miss_buff_half, 1, 1) @[lib.scala 270:36] + _T_777[0] <= _T_785 @[lib.scala 270:30] + node _T_786 = bits(ic_miss_buff_half, 2, 2) @[lib.scala 269:36] + _T_776[1] <= _T_786 @[lib.scala 269:30] + node _T_787 = bits(ic_miss_buff_half, 2, 2) @[lib.scala 270:36] + _T_777[1] <= _T_787 @[lib.scala 270:30] + node _T_788 = bits(ic_miss_buff_half, 3, 3) @[lib.scala 268:36] + _T_775[2] <= _T_788 @[lib.scala 268:30] + node _T_789 = bits(ic_miss_buff_half, 3, 3) @[lib.scala 269:36] + _T_776[2] <= _T_789 @[lib.scala 269:30] + node _T_790 = bits(ic_miss_buff_half, 3, 3) @[lib.scala 270:36] + _T_777[2] <= _T_790 @[lib.scala 270:30] + node _T_791 = bits(ic_miss_buff_half, 4, 4) @[lib.scala 268:36] + _T_775[3] <= _T_791 @[lib.scala 268:30] + node _T_792 = bits(ic_miss_buff_half, 4, 4) @[lib.scala 271:36] + _T_778[0] <= _T_792 @[lib.scala 271:30] + node _T_793 = bits(ic_miss_buff_half, 5, 5) @[lib.scala 269:36] + _T_776[3] <= _T_793 @[lib.scala 269:30] + node _T_794 = bits(ic_miss_buff_half, 5, 5) @[lib.scala 271:36] + _T_778[1] <= _T_794 @[lib.scala 271:30] + node _T_795 = bits(ic_miss_buff_half, 6, 6) @[lib.scala 268:36] + _T_775[4] <= _T_795 @[lib.scala 268:30] + node _T_796 = bits(ic_miss_buff_half, 6, 6) @[lib.scala 269:36] + _T_776[4] <= _T_796 @[lib.scala 269:30] + node _T_797 = bits(ic_miss_buff_half, 6, 6) @[lib.scala 271:36] + _T_778[2] <= _T_797 @[lib.scala 271:30] + node _T_798 = bits(ic_miss_buff_half, 7, 7) @[lib.scala 270:36] + _T_777[3] <= _T_798 @[lib.scala 270:30] + node _T_799 = bits(ic_miss_buff_half, 7, 7) @[lib.scala 271:36] + _T_778[3] <= _T_799 @[lib.scala 271:30] + node _T_800 = bits(ic_miss_buff_half, 8, 8) @[lib.scala 268:36] + _T_775[5] <= _T_800 @[lib.scala 268:30] + node _T_801 = bits(ic_miss_buff_half, 8, 8) @[lib.scala 270:36] + _T_777[4] <= _T_801 @[lib.scala 270:30] + node _T_802 = bits(ic_miss_buff_half, 8, 8) @[lib.scala 271:36] + _T_778[4] <= _T_802 @[lib.scala 271:30] + node _T_803 = bits(ic_miss_buff_half, 9, 9) @[lib.scala 269:36] + _T_776[5] <= _T_803 @[lib.scala 269:30] + node _T_804 = bits(ic_miss_buff_half, 9, 9) @[lib.scala 270:36] + _T_777[5] <= _T_804 @[lib.scala 270:30] + node _T_805 = bits(ic_miss_buff_half, 9, 9) @[lib.scala 271:36] + _T_778[5] <= _T_805 @[lib.scala 271:30] + node _T_806 = bits(ic_miss_buff_half, 10, 10) @[lib.scala 268:36] + _T_775[6] <= _T_806 @[lib.scala 268:30] + node _T_807 = bits(ic_miss_buff_half, 10, 10) @[lib.scala 269:36] + _T_776[6] <= _T_807 @[lib.scala 269:30] + node _T_808 = bits(ic_miss_buff_half, 10, 10) @[lib.scala 270:36] + _T_777[6] <= _T_808 @[lib.scala 270:30] + node _T_809 = bits(ic_miss_buff_half, 10, 10) @[lib.scala 271:36] + _T_778[6] <= _T_809 @[lib.scala 271:30] + node _T_810 = bits(ic_miss_buff_half, 11, 11) @[lib.scala 268:36] + _T_775[7] <= _T_810 @[lib.scala 268:30] + node _T_811 = bits(ic_miss_buff_half, 11, 11) @[lib.scala 272:36] + _T_779[0] <= _T_811 @[lib.scala 272:30] + node _T_812 = bits(ic_miss_buff_half, 12, 12) @[lib.scala 269:36] + _T_776[7] <= _T_812 @[lib.scala 269:30] + node _T_813 = bits(ic_miss_buff_half, 12, 12) @[lib.scala 272:36] + _T_779[1] <= _T_813 @[lib.scala 272:30] + node _T_814 = bits(ic_miss_buff_half, 13, 13) @[lib.scala 268:36] + _T_775[8] <= _T_814 @[lib.scala 268:30] + node _T_815 = bits(ic_miss_buff_half, 13, 13) @[lib.scala 269:36] + _T_776[8] <= _T_815 @[lib.scala 269:30] + node _T_816 = bits(ic_miss_buff_half, 13, 13) @[lib.scala 272:36] + _T_779[2] <= _T_816 @[lib.scala 272:30] + node _T_817 = bits(ic_miss_buff_half, 14, 14) @[lib.scala 270:36] + _T_777[7] <= _T_817 @[lib.scala 270:30] + node _T_818 = bits(ic_miss_buff_half, 14, 14) @[lib.scala 272:36] + _T_779[3] <= _T_818 @[lib.scala 272:30] + node _T_819 = bits(ic_miss_buff_half, 15, 15) @[lib.scala 268:36] + _T_775[9] <= _T_819 @[lib.scala 268:30] + node _T_820 = bits(ic_miss_buff_half, 15, 15) @[lib.scala 270:36] + _T_777[8] <= _T_820 @[lib.scala 270:30] + node _T_821 = bits(ic_miss_buff_half, 15, 15) @[lib.scala 272:36] + _T_779[4] <= _T_821 @[lib.scala 272:30] + node _T_822 = bits(ic_miss_buff_half, 16, 16) @[lib.scala 269:36] + _T_776[9] <= _T_822 @[lib.scala 269:30] + node _T_823 = bits(ic_miss_buff_half, 16, 16) @[lib.scala 270:36] + _T_777[9] <= _T_823 @[lib.scala 270:30] + node _T_824 = bits(ic_miss_buff_half, 16, 16) @[lib.scala 272:36] + _T_779[5] <= _T_824 @[lib.scala 272:30] + node _T_825 = bits(ic_miss_buff_half, 17, 17) @[lib.scala 268:36] + _T_775[10] <= _T_825 @[lib.scala 268:30] + node _T_826 = bits(ic_miss_buff_half, 17, 17) @[lib.scala 269:36] + _T_776[10] <= _T_826 @[lib.scala 269:30] + node _T_827 = bits(ic_miss_buff_half, 17, 17) @[lib.scala 270:36] + _T_777[10] <= _T_827 @[lib.scala 270:30] + node _T_828 = bits(ic_miss_buff_half, 17, 17) @[lib.scala 272:36] + _T_779[6] <= _T_828 @[lib.scala 272:30] + node _T_829 = bits(ic_miss_buff_half, 18, 18) @[lib.scala 271:36] + _T_778[7] <= _T_829 @[lib.scala 271:30] + node _T_830 = bits(ic_miss_buff_half, 18, 18) @[lib.scala 272:36] + _T_779[7] <= _T_830 @[lib.scala 272:30] + node _T_831 = bits(ic_miss_buff_half, 19, 19) @[lib.scala 268:36] + _T_775[11] <= _T_831 @[lib.scala 268:30] + node _T_832 = bits(ic_miss_buff_half, 19, 19) @[lib.scala 271:36] + _T_778[8] <= _T_832 @[lib.scala 271:30] + node _T_833 = bits(ic_miss_buff_half, 19, 19) @[lib.scala 272:36] + _T_779[8] <= _T_833 @[lib.scala 272:30] + node _T_834 = bits(ic_miss_buff_half, 20, 20) @[lib.scala 269:36] + _T_776[11] <= _T_834 @[lib.scala 269:30] + node _T_835 = bits(ic_miss_buff_half, 20, 20) @[lib.scala 271:36] + _T_778[9] <= _T_835 @[lib.scala 271:30] + node _T_836 = bits(ic_miss_buff_half, 20, 20) @[lib.scala 272:36] + _T_779[9] <= _T_836 @[lib.scala 272:30] + node _T_837 = bits(ic_miss_buff_half, 21, 21) @[lib.scala 268:36] + _T_775[12] <= _T_837 @[lib.scala 268:30] + node _T_838 = bits(ic_miss_buff_half, 21, 21) @[lib.scala 269:36] + _T_776[12] <= _T_838 @[lib.scala 269:30] + node _T_839 = bits(ic_miss_buff_half, 21, 21) @[lib.scala 271:36] + _T_778[10] <= _T_839 @[lib.scala 271:30] + node _T_840 = bits(ic_miss_buff_half, 21, 21) @[lib.scala 272:36] + _T_779[10] <= _T_840 @[lib.scala 272:30] + node _T_841 = bits(ic_miss_buff_half, 22, 22) @[lib.scala 270:36] + _T_777[11] <= _T_841 @[lib.scala 270:30] + node _T_842 = bits(ic_miss_buff_half, 22, 22) @[lib.scala 271:36] + _T_778[11] <= _T_842 @[lib.scala 271:30] + node _T_843 = bits(ic_miss_buff_half, 22, 22) @[lib.scala 272:36] + _T_779[11] <= _T_843 @[lib.scala 272:30] + node _T_844 = bits(ic_miss_buff_half, 23, 23) @[lib.scala 268:36] + _T_775[13] <= _T_844 @[lib.scala 268:30] + node _T_845 = bits(ic_miss_buff_half, 23, 23) @[lib.scala 270:36] + _T_777[12] <= _T_845 @[lib.scala 270:30] + node _T_846 = bits(ic_miss_buff_half, 23, 23) @[lib.scala 271:36] + _T_778[12] <= _T_846 @[lib.scala 271:30] + node _T_847 = bits(ic_miss_buff_half, 23, 23) @[lib.scala 272:36] + _T_779[12] <= _T_847 @[lib.scala 272:30] + node _T_848 = bits(ic_miss_buff_half, 24, 24) @[lib.scala 269:36] + _T_776[13] <= _T_848 @[lib.scala 269:30] + node _T_849 = bits(ic_miss_buff_half, 24, 24) @[lib.scala 270:36] + _T_777[13] <= _T_849 @[lib.scala 270:30] + node _T_850 = bits(ic_miss_buff_half, 24, 24) @[lib.scala 271:36] + _T_778[13] <= _T_850 @[lib.scala 271:30] + node _T_851 = bits(ic_miss_buff_half, 24, 24) @[lib.scala 272:36] + _T_779[13] <= _T_851 @[lib.scala 272:30] + node _T_852 = bits(ic_miss_buff_half, 25, 25) @[lib.scala 268:36] + _T_775[14] <= _T_852 @[lib.scala 268:30] + node _T_853 = bits(ic_miss_buff_half, 25, 25) @[lib.scala 269:36] + _T_776[14] <= _T_853 @[lib.scala 269:30] + node _T_854 = bits(ic_miss_buff_half, 25, 25) @[lib.scala 270:36] + _T_777[14] <= _T_854 @[lib.scala 270:30] + node _T_855 = bits(ic_miss_buff_half, 25, 25) @[lib.scala 271:36] + _T_778[14] <= _T_855 @[lib.scala 271:30] + node _T_856 = bits(ic_miss_buff_half, 25, 25) @[lib.scala 272:36] + _T_779[14] <= _T_856 @[lib.scala 272:30] + node _T_857 = bits(ic_miss_buff_half, 26, 26) @[lib.scala 268:36] + _T_775[15] <= _T_857 @[lib.scala 268:30] + node _T_858 = bits(ic_miss_buff_half, 26, 26) @[lib.scala 273:36] + _T_780[0] <= _T_858 @[lib.scala 273:30] + node _T_859 = bits(ic_miss_buff_half, 27, 27) @[lib.scala 269:36] + _T_776[15] <= _T_859 @[lib.scala 269:30] + node _T_860 = bits(ic_miss_buff_half, 27, 27) @[lib.scala 273:36] + _T_780[1] <= _T_860 @[lib.scala 273:30] + node _T_861 = bits(ic_miss_buff_half, 28, 28) @[lib.scala 268:36] + _T_775[16] <= _T_861 @[lib.scala 268:30] + node _T_862 = bits(ic_miss_buff_half, 28, 28) @[lib.scala 269:36] + _T_776[16] <= _T_862 @[lib.scala 269:30] + node _T_863 = bits(ic_miss_buff_half, 28, 28) @[lib.scala 273:36] + _T_780[2] <= _T_863 @[lib.scala 273:30] + node _T_864 = bits(ic_miss_buff_half, 29, 29) @[lib.scala 270:36] + _T_777[15] <= _T_864 @[lib.scala 270:30] + node _T_865 = bits(ic_miss_buff_half, 29, 29) @[lib.scala 273:36] + _T_780[3] <= _T_865 @[lib.scala 273:30] + node _T_866 = bits(ic_miss_buff_half, 30, 30) @[lib.scala 268:36] + _T_775[17] <= _T_866 @[lib.scala 268:30] + node _T_867 = bits(ic_miss_buff_half, 30, 30) @[lib.scala 270:36] + _T_777[16] <= _T_867 @[lib.scala 270:30] + node _T_868 = bits(ic_miss_buff_half, 30, 30) @[lib.scala 273:36] + _T_780[4] <= _T_868 @[lib.scala 273:30] + node _T_869 = bits(ic_miss_buff_half, 31, 31) @[lib.scala 269:36] + _T_776[17] <= _T_869 @[lib.scala 269:30] + node _T_870 = bits(ic_miss_buff_half, 31, 31) @[lib.scala 270:36] + _T_777[17] <= _T_870 @[lib.scala 270:30] + node _T_871 = bits(ic_miss_buff_half, 31, 31) @[lib.scala 273:36] + _T_780[5] <= _T_871 @[lib.scala 273:30] + node _T_872 = bits(ic_miss_buff_half, 32, 32) @[lib.scala 268:36] + _T_775[18] <= _T_872 @[lib.scala 268:30] + node _T_873 = bits(ic_miss_buff_half, 32, 32) @[lib.scala 269:36] + _T_776[18] <= _T_873 @[lib.scala 269:30] + node _T_874 = bits(ic_miss_buff_half, 32, 32) @[lib.scala 270:36] + _T_777[18] <= _T_874 @[lib.scala 270:30] + node _T_875 = bits(ic_miss_buff_half, 32, 32) @[lib.scala 273:36] + _T_780[6] <= _T_875 @[lib.scala 273:30] + node _T_876 = bits(ic_miss_buff_half, 33, 33) @[lib.scala 271:36] + _T_778[15] <= _T_876 @[lib.scala 271:30] + node _T_877 = bits(ic_miss_buff_half, 33, 33) @[lib.scala 273:36] + _T_780[7] <= _T_877 @[lib.scala 273:30] + node _T_878 = bits(ic_miss_buff_half, 34, 34) @[lib.scala 268:36] + _T_775[19] <= _T_878 @[lib.scala 268:30] + node _T_879 = bits(ic_miss_buff_half, 34, 34) @[lib.scala 271:36] + _T_778[16] <= _T_879 @[lib.scala 271:30] + node _T_880 = bits(ic_miss_buff_half, 34, 34) @[lib.scala 273:36] + _T_780[8] <= _T_880 @[lib.scala 273:30] + node _T_881 = bits(ic_miss_buff_half, 35, 35) @[lib.scala 269:36] + _T_776[19] <= _T_881 @[lib.scala 269:30] + node _T_882 = bits(ic_miss_buff_half, 35, 35) @[lib.scala 271:36] + _T_778[17] <= _T_882 @[lib.scala 271:30] + node _T_883 = bits(ic_miss_buff_half, 35, 35) @[lib.scala 273:36] + _T_780[9] <= _T_883 @[lib.scala 273:30] + node _T_884 = bits(ic_miss_buff_half, 36, 36) @[lib.scala 268:36] + _T_775[20] <= _T_884 @[lib.scala 268:30] + node _T_885 = bits(ic_miss_buff_half, 36, 36) @[lib.scala 269:36] + _T_776[20] <= _T_885 @[lib.scala 269:30] + node _T_886 = bits(ic_miss_buff_half, 36, 36) @[lib.scala 271:36] + _T_778[18] <= _T_886 @[lib.scala 271:30] + node _T_887 = bits(ic_miss_buff_half, 36, 36) @[lib.scala 273:36] + _T_780[10] <= _T_887 @[lib.scala 273:30] + node _T_888 = bits(ic_miss_buff_half, 37, 37) @[lib.scala 270:36] + _T_777[19] <= _T_888 @[lib.scala 270:30] + node _T_889 = bits(ic_miss_buff_half, 37, 37) @[lib.scala 271:36] + _T_778[19] <= _T_889 @[lib.scala 271:30] + node _T_890 = bits(ic_miss_buff_half, 37, 37) @[lib.scala 273:36] + _T_780[11] <= _T_890 @[lib.scala 273:30] + node _T_891 = bits(ic_miss_buff_half, 38, 38) @[lib.scala 268:36] + _T_775[21] <= _T_891 @[lib.scala 268:30] + node _T_892 = bits(ic_miss_buff_half, 38, 38) @[lib.scala 270:36] + _T_777[20] <= _T_892 @[lib.scala 270:30] + node _T_893 = bits(ic_miss_buff_half, 38, 38) @[lib.scala 271:36] + _T_778[20] <= _T_893 @[lib.scala 271:30] + node _T_894 = bits(ic_miss_buff_half, 38, 38) @[lib.scala 273:36] + _T_780[12] <= _T_894 @[lib.scala 273:30] + node _T_895 = bits(ic_miss_buff_half, 39, 39) @[lib.scala 269:36] + _T_776[21] <= _T_895 @[lib.scala 269:30] + node _T_896 = bits(ic_miss_buff_half, 39, 39) @[lib.scala 270:36] + _T_777[21] <= _T_896 @[lib.scala 270:30] + node _T_897 = bits(ic_miss_buff_half, 39, 39) @[lib.scala 271:36] + _T_778[21] <= _T_897 @[lib.scala 271:30] + node _T_898 = bits(ic_miss_buff_half, 39, 39) @[lib.scala 273:36] + _T_780[13] <= _T_898 @[lib.scala 273:30] + node _T_899 = bits(ic_miss_buff_half, 40, 40) @[lib.scala 268:36] + _T_775[22] <= _T_899 @[lib.scala 268:30] + node _T_900 = bits(ic_miss_buff_half, 40, 40) @[lib.scala 269:36] + _T_776[22] <= _T_900 @[lib.scala 269:30] + node _T_901 = bits(ic_miss_buff_half, 40, 40) @[lib.scala 270:36] + _T_777[22] <= _T_901 @[lib.scala 270:30] + node _T_902 = bits(ic_miss_buff_half, 40, 40) @[lib.scala 271:36] + _T_778[22] <= _T_902 @[lib.scala 271:30] + node _T_903 = bits(ic_miss_buff_half, 40, 40) @[lib.scala 273:36] + _T_780[14] <= _T_903 @[lib.scala 273:30] + node _T_904 = bits(ic_miss_buff_half, 41, 41) @[lib.scala 272:36] + _T_779[15] <= _T_904 @[lib.scala 272:30] + node _T_905 = bits(ic_miss_buff_half, 41, 41) @[lib.scala 273:36] + _T_780[15] <= _T_905 @[lib.scala 273:30] + node _T_906 = bits(ic_miss_buff_half, 42, 42) @[lib.scala 268:36] + _T_775[23] <= _T_906 @[lib.scala 268:30] + node _T_907 = bits(ic_miss_buff_half, 42, 42) @[lib.scala 272:36] + _T_779[16] <= _T_907 @[lib.scala 272:30] + node _T_908 = bits(ic_miss_buff_half, 42, 42) @[lib.scala 273:36] + _T_780[16] <= _T_908 @[lib.scala 273:30] + node _T_909 = bits(ic_miss_buff_half, 43, 43) @[lib.scala 269:36] + _T_776[23] <= _T_909 @[lib.scala 269:30] + node _T_910 = bits(ic_miss_buff_half, 43, 43) @[lib.scala 272:36] + _T_779[17] <= _T_910 @[lib.scala 272:30] + node _T_911 = bits(ic_miss_buff_half, 43, 43) @[lib.scala 273:36] + _T_780[17] <= _T_911 @[lib.scala 273:30] + node _T_912 = bits(ic_miss_buff_half, 44, 44) @[lib.scala 268:36] + _T_775[24] <= _T_912 @[lib.scala 268:30] + node _T_913 = bits(ic_miss_buff_half, 44, 44) @[lib.scala 269:36] + _T_776[24] <= _T_913 @[lib.scala 269:30] + node _T_914 = bits(ic_miss_buff_half, 44, 44) @[lib.scala 272:36] + _T_779[18] <= _T_914 @[lib.scala 272:30] + node _T_915 = bits(ic_miss_buff_half, 44, 44) @[lib.scala 273:36] + _T_780[18] <= _T_915 @[lib.scala 273:30] + node _T_916 = bits(ic_miss_buff_half, 45, 45) @[lib.scala 270:36] + _T_777[23] <= _T_916 @[lib.scala 270:30] + node _T_917 = bits(ic_miss_buff_half, 45, 45) @[lib.scala 272:36] + _T_779[19] <= _T_917 @[lib.scala 272:30] + node _T_918 = bits(ic_miss_buff_half, 45, 45) @[lib.scala 273:36] + _T_780[19] <= _T_918 @[lib.scala 273:30] + node _T_919 = bits(ic_miss_buff_half, 46, 46) @[lib.scala 268:36] + _T_775[25] <= _T_919 @[lib.scala 268:30] + node _T_920 = bits(ic_miss_buff_half, 46, 46) @[lib.scala 270:36] + _T_777[24] <= _T_920 @[lib.scala 270:30] + node _T_921 = bits(ic_miss_buff_half, 46, 46) @[lib.scala 272:36] + _T_779[20] <= _T_921 @[lib.scala 272:30] + node _T_922 = bits(ic_miss_buff_half, 46, 46) @[lib.scala 273:36] + _T_780[20] <= _T_922 @[lib.scala 273:30] + node _T_923 = bits(ic_miss_buff_half, 47, 47) @[lib.scala 269:36] + _T_776[25] <= _T_923 @[lib.scala 269:30] + node _T_924 = bits(ic_miss_buff_half, 47, 47) @[lib.scala 270:36] + _T_777[25] <= _T_924 @[lib.scala 270:30] + node _T_925 = bits(ic_miss_buff_half, 47, 47) @[lib.scala 272:36] + _T_779[21] <= _T_925 @[lib.scala 272:30] + node _T_926 = bits(ic_miss_buff_half, 47, 47) @[lib.scala 273:36] + _T_780[21] <= _T_926 @[lib.scala 273:30] + node _T_927 = bits(ic_miss_buff_half, 48, 48) @[lib.scala 268:36] + _T_775[26] <= _T_927 @[lib.scala 268:30] + node _T_928 = bits(ic_miss_buff_half, 48, 48) @[lib.scala 269:36] + _T_776[26] <= _T_928 @[lib.scala 269:30] + node _T_929 = bits(ic_miss_buff_half, 48, 48) @[lib.scala 270:36] + _T_777[26] <= _T_929 @[lib.scala 270:30] + node _T_930 = bits(ic_miss_buff_half, 48, 48) @[lib.scala 272:36] + _T_779[22] <= _T_930 @[lib.scala 272:30] + node _T_931 = bits(ic_miss_buff_half, 48, 48) @[lib.scala 273:36] + _T_780[22] <= _T_931 @[lib.scala 273:30] + node _T_932 = bits(ic_miss_buff_half, 49, 49) @[lib.scala 271:36] + _T_778[23] <= _T_932 @[lib.scala 271:30] + node _T_933 = bits(ic_miss_buff_half, 49, 49) @[lib.scala 272:36] + _T_779[23] <= _T_933 @[lib.scala 272:30] + node _T_934 = bits(ic_miss_buff_half, 49, 49) @[lib.scala 273:36] + _T_780[23] <= _T_934 @[lib.scala 273:30] + node _T_935 = bits(ic_miss_buff_half, 50, 50) @[lib.scala 268:36] + _T_775[27] <= _T_935 @[lib.scala 268:30] + node _T_936 = bits(ic_miss_buff_half, 50, 50) @[lib.scala 271:36] + _T_778[24] <= _T_936 @[lib.scala 271:30] + node _T_937 = bits(ic_miss_buff_half, 50, 50) @[lib.scala 272:36] + _T_779[24] <= _T_937 @[lib.scala 272:30] + node _T_938 = bits(ic_miss_buff_half, 50, 50) @[lib.scala 273:36] + _T_780[24] <= _T_938 @[lib.scala 273:30] + node _T_939 = bits(ic_miss_buff_half, 51, 51) @[lib.scala 269:36] + _T_776[27] <= _T_939 @[lib.scala 269:30] + node _T_940 = bits(ic_miss_buff_half, 51, 51) @[lib.scala 271:36] + _T_778[25] <= _T_940 @[lib.scala 271:30] + node _T_941 = bits(ic_miss_buff_half, 51, 51) @[lib.scala 272:36] + _T_779[25] <= _T_941 @[lib.scala 272:30] + node _T_942 = bits(ic_miss_buff_half, 51, 51) @[lib.scala 273:36] + _T_780[25] <= _T_942 @[lib.scala 273:30] + node _T_943 = bits(ic_miss_buff_half, 52, 52) @[lib.scala 268:36] + _T_775[28] <= _T_943 @[lib.scala 268:30] + node _T_944 = bits(ic_miss_buff_half, 52, 52) @[lib.scala 269:36] + _T_776[28] <= _T_944 @[lib.scala 269:30] + node _T_945 = bits(ic_miss_buff_half, 52, 52) @[lib.scala 271:36] + _T_778[26] <= _T_945 @[lib.scala 271:30] + node _T_946 = bits(ic_miss_buff_half, 52, 52) @[lib.scala 272:36] + _T_779[26] <= _T_946 @[lib.scala 272:30] + node _T_947 = bits(ic_miss_buff_half, 52, 52) @[lib.scala 273:36] + _T_780[26] <= _T_947 @[lib.scala 273:30] + node _T_948 = bits(ic_miss_buff_half, 53, 53) @[lib.scala 270:36] + _T_777[27] <= _T_948 @[lib.scala 270:30] + node _T_949 = bits(ic_miss_buff_half, 53, 53) @[lib.scala 271:36] + _T_778[27] <= _T_949 @[lib.scala 271:30] + node _T_950 = bits(ic_miss_buff_half, 53, 53) @[lib.scala 272:36] + _T_779[27] <= _T_950 @[lib.scala 272:30] + node _T_951 = bits(ic_miss_buff_half, 53, 53) @[lib.scala 273:36] + _T_780[27] <= _T_951 @[lib.scala 273:30] + node _T_952 = bits(ic_miss_buff_half, 54, 54) @[lib.scala 268:36] + _T_775[29] <= _T_952 @[lib.scala 268:30] + node _T_953 = bits(ic_miss_buff_half, 54, 54) @[lib.scala 270:36] + _T_777[28] <= _T_953 @[lib.scala 270:30] + node _T_954 = bits(ic_miss_buff_half, 54, 54) @[lib.scala 271:36] + _T_778[28] <= _T_954 @[lib.scala 271:30] + node _T_955 = bits(ic_miss_buff_half, 54, 54) @[lib.scala 272:36] + _T_779[28] <= _T_955 @[lib.scala 272:30] + node _T_956 = bits(ic_miss_buff_half, 54, 54) @[lib.scala 273:36] + _T_780[28] <= _T_956 @[lib.scala 273:30] + node _T_957 = bits(ic_miss_buff_half, 55, 55) @[lib.scala 269:36] + _T_776[29] <= _T_957 @[lib.scala 269:30] + node _T_958 = bits(ic_miss_buff_half, 55, 55) @[lib.scala 270:36] + _T_777[29] <= _T_958 @[lib.scala 270:30] + node _T_959 = bits(ic_miss_buff_half, 55, 55) @[lib.scala 271:36] + _T_778[29] <= _T_959 @[lib.scala 271:30] + node _T_960 = bits(ic_miss_buff_half, 55, 55) @[lib.scala 272:36] + _T_779[29] <= _T_960 @[lib.scala 272:30] + node _T_961 = bits(ic_miss_buff_half, 55, 55) @[lib.scala 273:36] + _T_780[29] <= _T_961 @[lib.scala 273:30] + node _T_962 = bits(ic_miss_buff_half, 56, 56) @[lib.scala 268:36] + _T_775[30] <= _T_962 @[lib.scala 268:30] + node _T_963 = bits(ic_miss_buff_half, 56, 56) @[lib.scala 269:36] + _T_776[30] <= _T_963 @[lib.scala 269:30] + node _T_964 = bits(ic_miss_buff_half, 56, 56) @[lib.scala 270:36] + _T_777[30] <= _T_964 @[lib.scala 270:30] + node _T_965 = bits(ic_miss_buff_half, 56, 56) @[lib.scala 271:36] + _T_778[30] <= _T_965 @[lib.scala 271:30] + node _T_966 = bits(ic_miss_buff_half, 56, 56) @[lib.scala 272:36] + _T_779[30] <= _T_966 @[lib.scala 272:30] + node _T_967 = bits(ic_miss_buff_half, 56, 56) @[lib.scala 273:36] + _T_780[30] <= _T_967 @[lib.scala 273:30] + node _T_968 = bits(ic_miss_buff_half, 57, 57) @[lib.scala 268:36] + _T_775[31] <= _T_968 @[lib.scala 268:30] + node _T_969 = bits(ic_miss_buff_half, 57, 57) @[lib.scala 274:36] + _T_781[0] <= _T_969 @[lib.scala 274:30] + node _T_970 = bits(ic_miss_buff_half, 58, 58) @[lib.scala 269:36] + _T_776[31] <= _T_970 @[lib.scala 269:30] + node _T_971 = bits(ic_miss_buff_half, 58, 58) @[lib.scala 274:36] + _T_781[1] <= _T_971 @[lib.scala 274:30] + node _T_972 = bits(ic_miss_buff_half, 59, 59) @[lib.scala 268:36] + _T_775[32] <= _T_972 @[lib.scala 268:30] + node _T_973 = bits(ic_miss_buff_half, 59, 59) @[lib.scala 269:36] + _T_776[32] <= _T_973 @[lib.scala 269:30] + node _T_974 = bits(ic_miss_buff_half, 59, 59) @[lib.scala 274:36] + _T_781[2] <= _T_974 @[lib.scala 274:30] + node _T_975 = bits(ic_miss_buff_half, 60, 60) @[lib.scala 270:36] + _T_777[31] <= _T_975 @[lib.scala 270:30] + node _T_976 = bits(ic_miss_buff_half, 60, 60) @[lib.scala 274:36] + _T_781[3] <= _T_976 @[lib.scala 274:30] + node _T_977 = bits(ic_miss_buff_half, 61, 61) @[lib.scala 268:36] + _T_775[33] <= _T_977 @[lib.scala 268:30] + node _T_978 = bits(ic_miss_buff_half, 61, 61) @[lib.scala 270:36] + _T_777[32] <= _T_978 @[lib.scala 270:30] + node _T_979 = bits(ic_miss_buff_half, 61, 61) @[lib.scala 274:36] + _T_781[4] <= _T_979 @[lib.scala 274:30] + node _T_980 = bits(ic_miss_buff_half, 62, 62) @[lib.scala 269:36] + _T_776[33] <= _T_980 @[lib.scala 269:30] + node _T_981 = bits(ic_miss_buff_half, 62, 62) @[lib.scala 270:36] + _T_777[33] <= _T_981 @[lib.scala 270:30] + node _T_982 = bits(ic_miss_buff_half, 62, 62) @[lib.scala 274:36] + _T_781[5] <= _T_982 @[lib.scala 274:30] + node _T_983 = bits(ic_miss_buff_half, 63, 63) @[lib.scala 268:36] + _T_775[34] <= _T_983 @[lib.scala 268:30] + node _T_984 = bits(ic_miss_buff_half, 63, 63) @[lib.scala 269:36] + _T_776[34] <= _T_984 @[lib.scala 269:30] + node _T_985 = bits(ic_miss_buff_half, 63, 63) @[lib.scala 270:36] + _T_777[34] <= _T_985 @[lib.scala 270:30] + node _T_986 = bits(ic_miss_buff_half, 63, 63) @[lib.scala 274:36] + _T_781[6] <= _T_986 @[lib.scala 274:30] + node _T_987 = cat(_T_781[2], _T_781[1]) @[lib.scala 276:13] + node _T_988 = cat(_T_987, _T_781[0]) @[lib.scala 276:13] + node _T_989 = cat(_T_781[4], _T_781[3]) @[lib.scala 276:13] + node _T_990 = cat(_T_781[6], _T_781[5]) @[lib.scala 276:13] + node _T_991 = cat(_T_990, _T_989) @[lib.scala 276:13] + node _T_992 = cat(_T_991, _T_988) @[lib.scala 276:13] + node _T_993 = xorr(_T_992) @[lib.scala 276:20] + node _T_994 = cat(_T_780[2], _T_780[1]) @[lib.scala 276:30] + node _T_995 = cat(_T_994, _T_780[0]) @[lib.scala 276:30] + node _T_996 = cat(_T_780[4], _T_780[3]) @[lib.scala 276:30] + node _T_997 = cat(_T_780[6], _T_780[5]) @[lib.scala 276:30] + node _T_998 = cat(_T_997, _T_996) @[lib.scala 276:30] + node _T_999 = cat(_T_998, _T_995) @[lib.scala 276:30] + node _T_1000 = cat(_T_780[8], _T_780[7]) @[lib.scala 276:30] + node _T_1001 = cat(_T_780[10], _T_780[9]) @[lib.scala 276:30] + node _T_1002 = cat(_T_1001, _T_1000) @[lib.scala 276:30] + node _T_1003 = cat(_T_780[12], _T_780[11]) @[lib.scala 276:30] + node _T_1004 = cat(_T_780[14], _T_780[13]) @[lib.scala 276:30] + node _T_1005 = cat(_T_1004, _T_1003) @[lib.scala 276:30] + node _T_1006 = cat(_T_1005, _T_1002) @[lib.scala 276:30] + node _T_1007 = cat(_T_1006, _T_999) @[lib.scala 276:30] + node _T_1008 = cat(_T_780[16], _T_780[15]) @[lib.scala 276:30] + node _T_1009 = cat(_T_780[18], _T_780[17]) @[lib.scala 276:30] + node _T_1010 = cat(_T_1009, _T_1008) @[lib.scala 276:30] + node _T_1011 = cat(_T_780[20], _T_780[19]) @[lib.scala 276:30] + node _T_1012 = cat(_T_780[22], _T_780[21]) @[lib.scala 276:30] + node _T_1013 = cat(_T_1012, _T_1011) @[lib.scala 276:30] + node _T_1014 = cat(_T_1013, _T_1010) @[lib.scala 276:30] + node _T_1015 = cat(_T_780[24], _T_780[23]) @[lib.scala 276:30] + node _T_1016 = cat(_T_780[26], _T_780[25]) @[lib.scala 276:30] + node _T_1017 = cat(_T_1016, _T_1015) @[lib.scala 276:30] + node _T_1018 = cat(_T_780[28], _T_780[27]) @[lib.scala 276:30] + node _T_1019 = cat(_T_780[30], _T_780[29]) @[lib.scala 276:30] + node _T_1020 = cat(_T_1019, _T_1018) @[lib.scala 276:30] + node _T_1021 = cat(_T_1020, _T_1017) @[lib.scala 276:30] + node _T_1022 = cat(_T_1021, _T_1014) @[lib.scala 276:30] + node _T_1023 = cat(_T_1022, _T_1007) @[lib.scala 276:30] + node _T_1024 = xorr(_T_1023) @[lib.scala 276:37] + node _T_1025 = cat(_T_779[2], _T_779[1]) @[lib.scala 276:47] + node _T_1026 = cat(_T_1025, _T_779[0]) @[lib.scala 276:47] + node _T_1027 = cat(_T_779[4], _T_779[3]) @[lib.scala 276:47] + node _T_1028 = cat(_T_779[6], _T_779[5]) @[lib.scala 276:47] + node _T_1029 = cat(_T_1028, _T_1027) @[lib.scala 276:47] + node _T_1030 = cat(_T_1029, _T_1026) @[lib.scala 276:47] + node _T_1031 = cat(_T_779[8], _T_779[7]) @[lib.scala 276:47] + node _T_1032 = cat(_T_779[10], _T_779[9]) @[lib.scala 276:47] + node _T_1033 = cat(_T_1032, _T_1031) @[lib.scala 276:47] + node _T_1034 = cat(_T_779[12], _T_779[11]) @[lib.scala 276:47] + node _T_1035 = cat(_T_779[14], _T_779[13]) @[lib.scala 276:47] + node _T_1036 = cat(_T_1035, _T_1034) @[lib.scala 276:47] + node _T_1037 = cat(_T_1036, _T_1033) @[lib.scala 276:47] + node _T_1038 = cat(_T_1037, _T_1030) @[lib.scala 276:47] + node _T_1039 = cat(_T_779[16], _T_779[15]) @[lib.scala 276:47] + node _T_1040 = cat(_T_779[18], _T_779[17]) @[lib.scala 276:47] + node _T_1041 = cat(_T_1040, _T_1039) @[lib.scala 276:47] + node _T_1042 = cat(_T_779[20], _T_779[19]) @[lib.scala 276:47] + node _T_1043 = cat(_T_779[22], _T_779[21]) @[lib.scala 276:47] + node _T_1044 = cat(_T_1043, _T_1042) @[lib.scala 276:47] + node _T_1045 = cat(_T_1044, _T_1041) @[lib.scala 276:47] + node _T_1046 = cat(_T_779[24], _T_779[23]) @[lib.scala 276:47] + node _T_1047 = cat(_T_779[26], _T_779[25]) @[lib.scala 276:47] + node _T_1048 = cat(_T_1047, _T_1046) @[lib.scala 276:47] + node _T_1049 = cat(_T_779[28], _T_779[27]) @[lib.scala 276:47] + node _T_1050 = cat(_T_779[30], _T_779[29]) @[lib.scala 276:47] + node _T_1051 = cat(_T_1050, _T_1049) @[lib.scala 276:47] + node _T_1052 = cat(_T_1051, _T_1048) @[lib.scala 276:47] + node _T_1053 = cat(_T_1052, _T_1045) @[lib.scala 276:47] + node _T_1054 = cat(_T_1053, _T_1038) @[lib.scala 276:47] + node _T_1055 = xorr(_T_1054) @[lib.scala 276:54] + node _T_1056 = cat(_T_778[2], _T_778[1]) @[lib.scala 276:64] + node _T_1057 = cat(_T_1056, _T_778[0]) @[lib.scala 276:64] + node _T_1058 = cat(_T_778[4], _T_778[3]) @[lib.scala 276:64] + node _T_1059 = cat(_T_778[6], _T_778[5]) @[lib.scala 276:64] + node _T_1060 = cat(_T_1059, _T_1058) @[lib.scala 276:64] + node _T_1061 = cat(_T_1060, _T_1057) @[lib.scala 276:64] + node _T_1062 = cat(_T_778[8], _T_778[7]) @[lib.scala 276:64] + node _T_1063 = cat(_T_778[10], _T_778[9]) @[lib.scala 276:64] + node _T_1064 = cat(_T_1063, _T_1062) @[lib.scala 276:64] + node _T_1065 = cat(_T_778[12], _T_778[11]) @[lib.scala 276:64] + node _T_1066 = cat(_T_778[14], _T_778[13]) @[lib.scala 276:64] + node _T_1067 = cat(_T_1066, _T_1065) @[lib.scala 276:64] + node _T_1068 = cat(_T_1067, _T_1064) @[lib.scala 276:64] + node _T_1069 = cat(_T_1068, _T_1061) @[lib.scala 276:64] + node _T_1070 = cat(_T_778[16], _T_778[15]) @[lib.scala 276:64] + node _T_1071 = cat(_T_778[18], _T_778[17]) @[lib.scala 276:64] + node _T_1072 = cat(_T_1071, _T_1070) @[lib.scala 276:64] + node _T_1073 = cat(_T_778[20], _T_778[19]) @[lib.scala 276:64] + node _T_1074 = cat(_T_778[22], _T_778[21]) @[lib.scala 276:64] + node _T_1075 = cat(_T_1074, _T_1073) @[lib.scala 276:64] + node _T_1076 = cat(_T_1075, _T_1072) @[lib.scala 276:64] + node _T_1077 = cat(_T_778[24], _T_778[23]) @[lib.scala 276:64] + node _T_1078 = cat(_T_778[26], _T_778[25]) @[lib.scala 276:64] + node _T_1079 = cat(_T_1078, _T_1077) @[lib.scala 276:64] + node _T_1080 = cat(_T_778[28], _T_778[27]) @[lib.scala 276:64] + node _T_1081 = cat(_T_778[30], _T_778[29]) @[lib.scala 276:64] + node _T_1082 = cat(_T_1081, _T_1080) @[lib.scala 276:64] + node _T_1083 = cat(_T_1082, _T_1079) @[lib.scala 276:64] + node _T_1084 = cat(_T_1083, _T_1076) @[lib.scala 276:64] + node _T_1085 = cat(_T_1084, _T_1069) @[lib.scala 276:64] + node _T_1086 = xorr(_T_1085) @[lib.scala 276:71] + node _T_1087 = cat(_T_777[1], _T_777[0]) @[lib.scala 276:81] + node _T_1088 = cat(_T_777[3], _T_777[2]) @[lib.scala 276:81] + node _T_1089 = cat(_T_1088, _T_1087) @[lib.scala 276:81] + node _T_1090 = cat(_T_777[5], _T_777[4]) @[lib.scala 276:81] + node _T_1091 = cat(_T_777[7], _T_777[6]) @[lib.scala 276:81] + node _T_1092 = cat(_T_1091, _T_1090) @[lib.scala 276:81] + node _T_1093 = cat(_T_1092, _T_1089) @[lib.scala 276:81] + node _T_1094 = cat(_T_777[9], _T_777[8]) @[lib.scala 276:81] + node _T_1095 = cat(_T_777[11], _T_777[10]) @[lib.scala 276:81] + node _T_1096 = cat(_T_1095, _T_1094) @[lib.scala 276:81] + node _T_1097 = cat(_T_777[13], _T_777[12]) @[lib.scala 276:81] + node _T_1098 = cat(_T_777[16], _T_777[15]) @[lib.scala 276:81] + node _T_1099 = cat(_T_1098, _T_777[14]) @[lib.scala 276:81] + node _T_1100 = cat(_T_1099, _T_1097) @[lib.scala 276:81] + node _T_1101 = cat(_T_1100, _T_1096) @[lib.scala 276:81] + node _T_1102 = cat(_T_1101, _T_1093) @[lib.scala 276:81] + node _T_1103 = cat(_T_777[18], _T_777[17]) @[lib.scala 276:81] + node _T_1104 = cat(_T_777[20], _T_777[19]) @[lib.scala 276:81] + node _T_1105 = cat(_T_1104, _T_1103) @[lib.scala 276:81] + node _T_1106 = cat(_T_777[22], _T_777[21]) @[lib.scala 276:81] + node _T_1107 = cat(_T_777[25], _T_777[24]) @[lib.scala 276:81] + node _T_1108 = cat(_T_1107, _T_777[23]) @[lib.scala 276:81] + node _T_1109 = cat(_T_1108, _T_1106) @[lib.scala 276:81] + node _T_1110 = cat(_T_1109, _T_1105) @[lib.scala 276:81] + node _T_1111 = cat(_T_777[27], _T_777[26]) @[lib.scala 276:81] + node _T_1112 = cat(_T_777[29], _T_777[28]) @[lib.scala 276:81] + node _T_1113 = cat(_T_1112, _T_1111) @[lib.scala 276:81] + node _T_1114 = cat(_T_777[31], _T_777[30]) @[lib.scala 276:81] + node _T_1115 = cat(_T_777[34], _T_777[33]) @[lib.scala 276:81] + node _T_1116 = cat(_T_1115, _T_777[32]) @[lib.scala 276:81] + node _T_1117 = cat(_T_1116, _T_1114) @[lib.scala 276:81] + node _T_1118 = cat(_T_1117, _T_1113) @[lib.scala 276:81] + node _T_1119 = cat(_T_1118, _T_1110) @[lib.scala 276:81] + node _T_1120 = cat(_T_1119, _T_1102) @[lib.scala 276:81] + node _T_1121 = xorr(_T_1120) @[lib.scala 276:88] + node _T_1122 = cat(_T_776[1], _T_776[0]) @[lib.scala 276:98] + node _T_1123 = cat(_T_776[3], _T_776[2]) @[lib.scala 276:98] + node _T_1124 = cat(_T_1123, _T_1122) @[lib.scala 276:98] + node _T_1125 = cat(_T_776[5], _T_776[4]) @[lib.scala 276:98] + node _T_1126 = cat(_T_776[7], _T_776[6]) @[lib.scala 276:98] + node _T_1127 = cat(_T_1126, _T_1125) @[lib.scala 276:98] + node _T_1128 = cat(_T_1127, _T_1124) @[lib.scala 276:98] + node _T_1129 = cat(_T_776[9], _T_776[8]) @[lib.scala 276:98] + node _T_1130 = cat(_T_776[11], _T_776[10]) @[lib.scala 276:98] + node _T_1131 = cat(_T_1130, _T_1129) @[lib.scala 276:98] + node _T_1132 = cat(_T_776[13], _T_776[12]) @[lib.scala 276:98] + node _T_1133 = cat(_T_776[16], _T_776[15]) @[lib.scala 276:98] + node _T_1134 = cat(_T_1133, _T_776[14]) @[lib.scala 276:98] + node _T_1135 = cat(_T_1134, _T_1132) @[lib.scala 276:98] + node _T_1136 = cat(_T_1135, _T_1131) @[lib.scala 276:98] + node _T_1137 = cat(_T_1136, _T_1128) @[lib.scala 276:98] + node _T_1138 = cat(_T_776[18], _T_776[17]) @[lib.scala 276:98] + node _T_1139 = cat(_T_776[20], _T_776[19]) @[lib.scala 276:98] + node _T_1140 = cat(_T_1139, _T_1138) @[lib.scala 276:98] + node _T_1141 = cat(_T_776[22], _T_776[21]) @[lib.scala 276:98] + node _T_1142 = cat(_T_776[25], _T_776[24]) @[lib.scala 276:98] + node _T_1143 = cat(_T_1142, _T_776[23]) @[lib.scala 276:98] + node _T_1144 = cat(_T_1143, _T_1141) @[lib.scala 276:98] + node _T_1145 = cat(_T_1144, _T_1140) @[lib.scala 276:98] + node _T_1146 = cat(_T_776[27], _T_776[26]) @[lib.scala 276:98] + node _T_1147 = cat(_T_776[29], _T_776[28]) @[lib.scala 276:98] + node _T_1148 = cat(_T_1147, _T_1146) @[lib.scala 276:98] + node _T_1149 = cat(_T_776[31], _T_776[30]) @[lib.scala 276:98] + node _T_1150 = cat(_T_776[34], _T_776[33]) @[lib.scala 276:98] + node _T_1151 = cat(_T_1150, _T_776[32]) @[lib.scala 276:98] + node _T_1152 = cat(_T_1151, _T_1149) @[lib.scala 276:98] + node _T_1153 = cat(_T_1152, _T_1148) @[lib.scala 276:98] + node _T_1154 = cat(_T_1153, _T_1145) @[lib.scala 276:98] + node _T_1155 = cat(_T_1154, _T_1137) @[lib.scala 276:98] + node _T_1156 = xorr(_T_1155) @[lib.scala 276:105] + node _T_1157 = cat(_T_775[1], _T_775[0]) @[lib.scala 276:115] + node _T_1158 = cat(_T_775[3], _T_775[2]) @[lib.scala 276:115] + node _T_1159 = cat(_T_1158, _T_1157) @[lib.scala 276:115] + node _T_1160 = cat(_T_775[5], _T_775[4]) @[lib.scala 276:115] + node _T_1161 = cat(_T_775[7], _T_775[6]) @[lib.scala 276:115] + node _T_1162 = cat(_T_1161, _T_1160) @[lib.scala 276:115] + node _T_1163 = cat(_T_1162, _T_1159) @[lib.scala 276:115] + node _T_1164 = cat(_T_775[9], _T_775[8]) @[lib.scala 276:115] + node _T_1165 = cat(_T_775[11], _T_775[10]) @[lib.scala 276:115] + node _T_1166 = cat(_T_1165, _T_1164) @[lib.scala 276:115] + node _T_1167 = cat(_T_775[13], _T_775[12]) @[lib.scala 276:115] + node _T_1168 = cat(_T_775[16], _T_775[15]) @[lib.scala 276:115] + node _T_1169 = cat(_T_1168, _T_775[14]) @[lib.scala 276:115] + node _T_1170 = cat(_T_1169, _T_1167) @[lib.scala 276:115] + node _T_1171 = cat(_T_1170, _T_1166) @[lib.scala 276:115] + node _T_1172 = cat(_T_1171, _T_1163) @[lib.scala 276:115] + node _T_1173 = cat(_T_775[18], _T_775[17]) @[lib.scala 276:115] + node _T_1174 = cat(_T_775[20], _T_775[19]) @[lib.scala 276:115] + node _T_1175 = cat(_T_1174, _T_1173) @[lib.scala 276:115] + node _T_1176 = cat(_T_775[22], _T_775[21]) @[lib.scala 276:115] + node _T_1177 = cat(_T_775[25], _T_775[24]) @[lib.scala 276:115] + node _T_1178 = cat(_T_1177, _T_775[23]) @[lib.scala 276:115] + node _T_1179 = cat(_T_1178, _T_1176) @[lib.scala 276:115] + node _T_1180 = cat(_T_1179, _T_1175) @[lib.scala 276:115] + node _T_1181 = cat(_T_775[27], _T_775[26]) @[lib.scala 276:115] + node _T_1182 = cat(_T_775[29], _T_775[28]) @[lib.scala 276:115] + node _T_1183 = cat(_T_1182, _T_1181) @[lib.scala 276:115] + node _T_1184 = cat(_T_775[31], _T_775[30]) @[lib.scala 276:115] + node _T_1185 = cat(_T_775[34], _T_775[33]) @[lib.scala 276:115] + node _T_1186 = cat(_T_1185, _T_775[32]) @[lib.scala 276:115] + node _T_1187 = cat(_T_1186, _T_1184) @[lib.scala 276:115] + node _T_1188 = cat(_T_1187, _T_1183) @[lib.scala 276:115] + node _T_1189 = cat(_T_1188, _T_1180) @[lib.scala 276:115] + node _T_1190 = cat(_T_1189, _T_1172) @[lib.scala 276:115] + node _T_1191 = xorr(_T_1190) @[lib.scala 276:122] node _T_1192 = cat(_T_1121, _T_1156) @[Cat.scala 29:58] node _T_1193 = cat(_T_1192, _T_1191) @[Cat.scala 29:58] node _T_1194 = cat(_T_1055, _T_1086) @[Cat.scala 29:58] @@ -4223,24 +4223,24 @@ circuit quasar_wrapper : _T_1212 <= ifu_ic_debug_rd_data_in @[ifu_mem_ctl.scala 263:76] io.dec_mem_ctrl.ifu_ic_debug_rd_data <= _T_1212 @[ifu_mem_ctl.scala 263:40] node _T_1213 = bits(ifu_bus_rdata_ff, 15, 0) @[ifu_mem_ctl.scala 264:74] - node _T_1214 = xorr(_T_1213) @[el2_lib.scala 204:13] + node _T_1214 = xorr(_T_1213) @[lib.scala 64:13] node _T_1215 = bits(ifu_bus_rdata_ff, 31, 16) @[ifu_mem_ctl.scala 264:74] - node _T_1216 = xorr(_T_1215) @[el2_lib.scala 204:13] + node _T_1216 = xorr(_T_1215) @[lib.scala 64:13] node _T_1217 = bits(ifu_bus_rdata_ff, 47, 32) @[ifu_mem_ctl.scala 264:74] - node _T_1218 = xorr(_T_1217) @[el2_lib.scala 204:13] + node _T_1218 = xorr(_T_1217) @[lib.scala 64:13] node _T_1219 = bits(ifu_bus_rdata_ff, 63, 48) @[ifu_mem_ctl.scala 264:74] - node _T_1220 = xorr(_T_1219) @[el2_lib.scala 204:13] + node _T_1220 = xorr(_T_1219) @[lib.scala 64:13] node _T_1221 = cat(_T_1220, _T_1218) @[Cat.scala 29:58] node _T_1222 = cat(_T_1221, _T_1216) @[Cat.scala 29:58] node ic_wr_parity = cat(_T_1222, _T_1214) @[Cat.scala 29:58] node _T_1223 = bits(ic_miss_buff_half, 15, 0) @[ifu_mem_ctl.scala 265:82] - node _T_1224 = xorr(_T_1223) @[el2_lib.scala 204:13] + node _T_1224 = xorr(_T_1223) @[lib.scala 64:13] node _T_1225 = bits(ic_miss_buff_half, 31, 16) @[ifu_mem_ctl.scala 265:82] - node _T_1226 = xorr(_T_1225) @[el2_lib.scala 204:13] + node _T_1226 = xorr(_T_1225) @[lib.scala 64:13] node _T_1227 = bits(ic_miss_buff_half, 47, 32) @[ifu_mem_ctl.scala 265:82] - node _T_1228 = xorr(_T_1227) @[el2_lib.scala 204:13] + node _T_1228 = xorr(_T_1227) @[lib.scala 64:13] node _T_1229 = bits(ic_miss_buff_half, 63, 48) @[ifu_mem_ctl.scala 265:82] - node _T_1230 = xorr(_T_1229) @[el2_lib.scala 204:13] + node _T_1230 = xorr(_T_1229) @[lib.scala 64:13] node _T_1231 = cat(_T_1230, _T_1228) @[Cat.scala 29:58] node _T_1232 = cat(_T_1231, _T_1226) @[Cat.scala 29:58] node ic_miss_buff_parity = cat(_T_1232, _T_1224) @[Cat.scala 29:58] @@ -4376,54 +4376,54 @@ circuit quasar_wrapper : node _T_1296 = eq(ifu_bus_rsp_tag, UInt<3>("h07")) @[ifu_mem_ctl.scala 312:91] node write_fill_data_7 = and(bus_ifu_wr_en, _T_1296) @[ifu_mem_ctl.scala 312:73] wire ic_miss_buff_data : UInt<32>[16] @[ifu_mem_ctl.scala 313:31] - inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 483:22] + inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 343:22] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_4.io.en <= write_fill_data_0 @[el2_lib.scala 485:16] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 483:22] + rvclkhdr_4.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_4.io.en <= write_fill_data_0 @[lib.scala 345:16] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 343:22] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_5.io.en <= write_fill_data_1 @[el2_lib.scala 485:16] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 483:22] + rvclkhdr_5.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_5.io.en <= write_fill_data_1 @[lib.scala 345:16] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 343:22] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset - rvclkhdr_6.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_6.io.en <= write_fill_data_2 @[el2_lib.scala 485:16] - rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 483:22] + rvclkhdr_6.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_6.io.en <= write_fill_data_2 @[lib.scala 345:16] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 343:22] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset - rvclkhdr_7.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_7.io.en <= write_fill_data_3 @[el2_lib.scala 485:16] - rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_8 of rvclkhdr_8 @[el2_lib.scala 483:22] + rvclkhdr_7.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_7.io.en <= write_fill_data_3 @[lib.scala 345:16] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 343:22] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset - rvclkhdr_8.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_8.io.en <= write_fill_data_4 @[el2_lib.scala 485:16] - rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_9 of rvclkhdr_9 @[el2_lib.scala 483:22] + rvclkhdr_8.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_8.io.en <= write_fill_data_4 @[lib.scala 345:16] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 343:22] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset - rvclkhdr_9.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_9.io.en <= write_fill_data_5 @[el2_lib.scala 485:16] - rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_10 of rvclkhdr_10 @[el2_lib.scala 483:22] + rvclkhdr_9.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_9.io.en <= write_fill_data_5 @[lib.scala 345:16] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_10 of rvclkhdr_10 @[lib.scala 343:22] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset - rvclkhdr_10.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_10.io.en <= write_fill_data_6 @[el2_lib.scala 485:16] - rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_11 of rvclkhdr_11 @[el2_lib.scala 483:22] + rvclkhdr_10.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_10.io.en <= write_fill_data_6 @[lib.scala 345:16] + rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_11 of rvclkhdr_11 @[lib.scala 343:22] rvclkhdr_11.clock <= clock rvclkhdr_11.reset <= reset - rvclkhdr_11.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_11.io.en <= write_fill_data_7 @[el2_lib.scala 485:16] - rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_11.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_11.io.en <= write_fill_data_7 @[lib.scala 345:16] + rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 346:23] node _T_1297 = bits(ic_miss_buff_data_in, 31, 0) @[ifu_mem_ctl.scala 316:86] reg _T_1298 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 316:65] _T_1298 <= _T_1297 @[ifu_mem_ctl.scala 316:65] @@ -4432,54 +4432,54 @@ circuit quasar_wrapper : reg _T_1300 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 317:67] _T_1300 <= _T_1299 @[ifu_mem_ctl.scala 317:67] ic_miss_buff_data[1] <= _T_1300 @[ifu_mem_ctl.scala 317:28] - inst rvclkhdr_12 of rvclkhdr_12 @[el2_lib.scala 483:22] + inst rvclkhdr_12 of rvclkhdr_12 @[lib.scala 343:22] rvclkhdr_12.clock <= clock rvclkhdr_12.reset <= reset - rvclkhdr_12.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_12.io.en <= write_fill_data_0 @[el2_lib.scala 485:16] - rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_13 of rvclkhdr_13 @[el2_lib.scala 483:22] + rvclkhdr_12.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_12.io.en <= write_fill_data_0 @[lib.scala 345:16] + rvclkhdr_12.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_13 of rvclkhdr_13 @[lib.scala 343:22] rvclkhdr_13.clock <= clock rvclkhdr_13.reset <= reset - rvclkhdr_13.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_13.io.en <= write_fill_data_1 @[el2_lib.scala 485:16] - rvclkhdr_13.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_14 of rvclkhdr_14 @[el2_lib.scala 483:22] + rvclkhdr_13.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_13.io.en <= write_fill_data_1 @[lib.scala 345:16] + rvclkhdr_13.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_14 of rvclkhdr_14 @[lib.scala 343:22] rvclkhdr_14.clock <= clock rvclkhdr_14.reset <= reset - rvclkhdr_14.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_14.io.en <= write_fill_data_2 @[el2_lib.scala 485:16] - rvclkhdr_14.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_15 of rvclkhdr_15 @[el2_lib.scala 483:22] + rvclkhdr_14.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_14.io.en <= write_fill_data_2 @[lib.scala 345:16] + rvclkhdr_14.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_15 of rvclkhdr_15 @[lib.scala 343:22] rvclkhdr_15.clock <= clock rvclkhdr_15.reset <= reset - rvclkhdr_15.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_15.io.en <= write_fill_data_3 @[el2_lib.scala 485:16] - rvclkhdr_15.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_16 of rvclkhdr_16 @[el2_lib.scala 483:22] + rvclkhdr_15.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_15.io.en <= write_fill_data_3 @[lib.scala 345:16] + rvclkhdr_15.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_16 of rvclkhdr_16 @[lib.scala 343:22] rvclkhdr_16.clock <= clock rvclkhdr_16.reset <= reset - rvclkhdr_16.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_16.io.en <= write_fill_data_4 @[el2_lib.scala 485:16] - rvclkhdr_16.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_17 of rvclkhdr_17 @[el2_lib.scala 483:22] + rvclkhdr_16.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_16.io.en <= write_fill_data_4 @[lib.scala 345:16] + rvclkhdr_16.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_17 of rvclkhdr_17 @[lib.scala 343:22] rvclkhdr_17.clock <= clock rvclkhdr_17.reset <= reset - rvclkhdr_17.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_17.io.en <= write_fill_data_5 @[el2_lib.scala 485:16] - rvclkhdr_17.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_18 of rvclkhdr_18 @[el2_lib.scala 483:22] + rvclkhdr_17.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_17.io.en <= write_fill_data_5 @[lib.scala 345:16] + rvclkhdr_17.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_18 of rvclkhdr_18 @[lib.scala 343:22] rvclkhdr_18.clock <= clock rvclkhdr_18.reset <= reset - rvclkhdr_18.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_18.io.en <= write_fill_data_6 @[el2_lib.scala 485:16] - rvclkhdr_18.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_19 of rvclkhdr_19 @[el2_lib.scala 483:22] + rvclkhdr_18.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_18.io.en <= write_fill_data_6 @[lib.scala 345:16] + rvclkhdr_18.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_19 of rvclkhdr_19 @[lib.scala 343:22] rvclkhdr_19.clock <= clock rvclkhdr_19.reset <= reset - rvclkhdr_19.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_19.io.en <= write_fill_data_7 @[el2_lib.scala 485:16] - rvclkhdr_19.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_19.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_19.io.en <= write_fill_data_7 @[lib.scala 345:16] + rvclkhdr_19.io.scan_mode <= io.scan_mode @[lib.scala 346:23] node _T_1301 = bits(ic_miss_buff_data_in, 31, 0) @[ifu_mem_ctl.scala 316:86] reg _T_1302 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 316:65] _T_1302 <= _T_1301 @[ifu_mem_ctl.scala 316:65] @@ -4488,54 +4488,54 @@ circuit quasar_wrapper : reg _T_1304 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 317:67] _T_1304 <= _T_1303 @[ifu_mem_ctl.scala 317:67] ic_miss_buff_data[3] <= _T_1304 @[ifu_mem_ctl.scala 317:28] - inst rvclkhdr_20 of rvclkhdr_20 @[el2_lib.scala 483:22] + inst rvclkhdr_20 of rvclkhdr_20 @[lib.scala 343:22] rvclkhdr_20.clock <= clock rvclkhdr_20.reset <= reset - rvclkhdr_20.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_20.io.en <= write_fill_data_0 @[el2_lib.scala 485:16] - rvclkhdr_20.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_21 of rvclkhdr_21 @[el2_lib.scala 483:22] + rvclkhdr_20.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_20.io.en <= write_fill_data_0 @[lib.scala 345:16] + rvclkhdr_20.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_21 of rvclkhdr_21 @[lib.scala 343:22] rvclkhdr_21.clock <= clock rvclkhdr_21.reset <= reset - rvclkhdr_21.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_21.io.en <= write_fill_data_1 @[el2_lib.scala 485:16] - rvclkhdr_21.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_22 of rvclkhdr_22 @[el2_lib.scala 483:22] + rvclkhdr_21.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_21.io.en <= write_fill_data_1 @[lib.scala 345:16] + rvclkhdr_21.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_22 of rvclkhdr_22 @[lib.scala 343:22] rvclkhdr_22.clock <= clock rvclkhdr_22.reset <= reset - rvclkhdr_22.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_22.io.en <= write_fill_data_2 @[el2_lib.scala 485:16] - rvclkhdr_22.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_23 of rvclkhdr_23 @[el2_lib.scala 483:22] + rvclkhdr_22.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_22.io.en <= write_fill_data_2 @[lib.scala 345:16] + rvclkhdr_22.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_23 of rvclkhdr_23 @[lib.scala 343:22] rvclkhdr_23.clock <= clock rvclkhdr_23.reset <= reset - rvclkhdr_23.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_23.io.en <= write_fill_data_3 @[el2_lib.scala 485:16] - rvclkhdr_23.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_24 of rvclkhdr_24 @[el2_lib.scala 483:22] + rvclkhdr_23.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_23.io.en <= write_fill_data_3 @[lib.scala 345:16] + rvclkhdr_23.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_24 of rvclkhdr_24 @[lib.scala 343:22] rvclkhdr_24.clock <= clock rvclkhdr_24.reset <= reset - rvclkhdr_24.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_24.io.en <= write_fill_data_4 @[el2_lib.scala 485:16] - rvclkhdr_24.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_25 of rvclkhdr_25 @[el2_lib.scala 483:22] + rvclkhdr_24.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_24.io.en <= write_fill_data_4 @[lib.scala 345:16] + rvclkhdr_24.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_25 of rvclkhdr_25 @[lib.scala 343:22] rvclkhdr_25.clock <= clock rvclkhdr_25.reset <= reset - rvclkhdr_25.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_25.io.en <= write_fill_data_5 @[el2_lib.scala 485:16] - rvclkhdr_25.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_26 of rvclkhdr_26 @[el2_lib.scala 483:22] + rvclkhdr_25.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_25.io.en <= write_fill_data_5 @[lib.scala 345:16] + rvclkhdr_25.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_26 of rvclkhdr_26 @[lib.scala 343:22] rvclkhdr_26.clock <= clock rvclkhdr_26.reset <= reset - rvclkhdr_26.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_26.io.en <= write_fill_data_6 @[el2_lib.scala 485:16] - rvclkhdr_26.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_27 of rvclkhdr_27 @[el2_lib.scala 483:22] + rvclkhdr_26.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_26.io.en <= write_fill_data_6 @[lib.scala 345:16] + rvclkhdr_26.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_27 of rvclkhdr_27 @[lib.scala 343:22] rvclkhdr_27.clock <= clock rvclkhdr_27.reset <= reset - rvclkhdr_27.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_27.io.en <= write_fill_data_7 @[el2_lib.scala 485:16] - rvclkhdr_27.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_27.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_27.io.en <= write_fill_data_7 @[lib.scala 345:16] + rvclkhdr_27.io.scan_mode <= io.scan_mode @[lib.scala 346:23] node _T_1305 = bits(ic_miss_buff_data_in, 31, 0) @[ifu_mem_ctl.scala 316:86] reg _T_1306 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 316:65] _T_1306 <= _T_1305 @[ifu_mem_ctl.scala 316:65] @@ -4544,54 +4544,54 @@ circuit quasar_wrapper : reg _T_1308 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 317:67] _T_1308 <= _T_1307 @[ifu_mem_ctl.scala 317:67] ic_miss_buff_data[5] <= _T_1308 @[ifu_mem_ctl.scala 317:28] - inst rvclkhdr_28 of rvclkhdr_28 @[el2_lib.scala 483:22] + inst rvclkhdr_28 of rvclkhdr_28 @[lib.scala 343:22] rvclkhdr_28.clock <= clock rvclkhdr_28.reset <= reset - rvclkhdr_28.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_28.io.en <= write_fill_data_0 @[el2_lib.scala 485:16] - rvclkhdr_28.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_29 of rvclkhdr_29 @[el2_lib.scala 483:22] + rvclkhdr_28.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_28.io.en <= write_fill_data_0 @[lib.scala 345:16] + rvclkhdr_28.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_29 of rvclkhdr_29 @[lib.scala 343:22] rvclkhdr_29.clock <= clock rvclkhdr_29.reset <= reset - rvclkhdr_29.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_29.io.en <= write_fill_data_1 @[el2_lib.scala 485:16] - rvclkhdr_29.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_30 of rvclkhdr_30 @[el2_lib.scala 483:22] + rvclkhdr_29.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_29.io.en <= write_fill_data_1 @[lib.scala 345:16] + rvclkhdr_29.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_30 of rvclkhdr_30 @[lib.scala 343:22] rvclkhdr_30.clock <= clock rvclkhdr_30.reset <= reset - rvclkhdr_30.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_30.io.en <= write_fill_data_2 @[el2_lib.scala 485:16] - rvclkhdr_30.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_31 of rvclkhdr_31 @[el2_lib.scala 483:22] + rvclkhdr_30.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_30.io.en <= write_fill_data_2 @[lib.scala 345:16] + rvclkhdr_30.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_31 of rvclkhdr_31 @[lib.scala 343:22] rvclkhdr_31.clock <= clock rvclkhdr_31.reset <= reset - rvclkhdr_31.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_31.io.en <= write_fill_data_3 @[el2_lib.scala 485:16] - rvclkhdr_31.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_32 of rvclkhdr_32 @[el2_lib.scala 483:22] + rvclkhdr_31.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_31.io.en <= write_fill_data_3 @[lib.scala 345:16] + rvclkhdr_31.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_32 of rvclkhdr_32 @[lib.scala 343:22] rvclkhdr_32.clock <= clock rvclkhdr_32.reset <= reset - rvclkhdr_32.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_32.io.en <= write_fill_data_4 @[el2_lib.scala 485:16] - rvclkhdr_32.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_33 of rvclkhdr_33 @[el2_lib.scala 483:22] + rvclkhdr_32.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_32.io.en <= write_fill_data_4 @[lib.scala 345:16] + rvclkhdr_32.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_33 of rvclkhdr_33 @[lib.scala 343:22] rvclkhdr_33.clock <= clock rvclkhdr_33.reset <= reset - rvclkhdr_33.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_33.io.en <= write_fill_data_5 @[el2_lib.scala 485:16] - rvclkhdr_33.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_34 of rvclkhdr_34 @[el2_lib.scala 483:22] + rvclkhdr_33.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_33.io.en <= write_fill_data_5 @[lib.scala 345:16] + rvclkhdr_33.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_34 of rvclkhdr_34 @[lib.scala 343:22] rvclkhdr_34.clock <= clock rvclkhdr_34.reset <= reset - rvclkhdr_34.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_34.io.en <= write_fill_data_6 @[el2_lib.scala 485:16] - rvclkhdr_34.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_35 of rvclkhdr_35 @[el2_lib.scala 483:22] + rvclkhdr_34.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_34.io.en <= write_fill_data_6 @[lib.scala 345:16] + rvclkhdr_34.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_35 of rvclkhdr_35 @[lib.scala 343:22] rvclkhdr_35.clock <= clock rvclkhdr_35.reset <= reset - rvclkhdr_35.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_35.io.en <= write_fill_data_7 @[el2_lib.scala 485:16] - rvclkhdr_35.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_35.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_35.io.en <= write_fill_data_7 @[lib.scala 345:16] + rvclkhdr_35.io.scan_mode <= io.scan_mode @[lib.scala 346:23] node _T_1309 = bits(ic_miss_buff_data_in, 31, 0) @[ifu_mem_ctl.scala 316:86] reg _T_1310 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 316:65] _T_1310 <= _T_1309 @[ifu_mem_ctl.scala 316:65] @@ -4600,54 +4600,54 @@ circuit quasar_wrapper : reg _T_1312 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 317:67] _T_1312 <= _T_1311 @[ifu_mem_ctl.scala 317:67] ic_miss_buff_data[7] <= _T_1312 @[ifu_mem_ctl.scala 317:28] - inst rvclkhdr_36 of rvclkhdr_36 @[el2_lib.scala 483:22] + inst rvclkhdr_36 of rvclkhdr_36 @[lib.scala 343:22] rvclkhdr_36.clock <= clock rvclkhdr_36.reset <= reset - rvclkhdr_36.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_36.io.en <= write_fill_data_0 @[el2_lib.scala 485:16] - rvclkhdr_36.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_37 of rvclkhdr_37 @[el2_lib.scala 483:22] + rvclkhdr_36.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_36.io.en <= write_fill_data_0 @[lib.scala 345:16] + rvclkhdr_36.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_37 of rvclkhdr_37 @[lib.scala 343:22] rvclkhdr_37.clock <= clock rvclkhdr_37.reset <= reset - rvclkhdr_37.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_37.io.en <= write_fill_data_1 @[el2_lib.scala 485:16] - rvclkhdr_37.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_38 of rvclkhdr_38 @[el2_lib.scala 483:22] + rvclkhdr_37.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_37.io.en <= write_fill_data_1 @[lib.scala 345:16] + rvclkhdr_37.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_38 of rvclkhdr_38 @[lib.scala 343:22] rvclkhdr_38.clock <= clock rvclkhdr_38.reset <= reset - rvclkhdr_38.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_38.io.en <= write_fill_data_2 @[el2_lib.scala 485:16] - rvclkhdr_38.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_39 of rvclkhdr_39 @[el2_lib.scala 483:22] + rvclkhdr_38.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_38.io.en <= write_fill_data_2 @[lib.scala 345:16] + rvclkhdr_38.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_39 of rvclkhdr_39 @[lib.scala 343:22] rvclkhdr_39.clock <= clock rvclkhdr_39.reset <= reset - rvclkhdr_39.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_39.io.en <= write_fill_data_3 @[el2_lib.scala 485:16] - rvclkhdr_39.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_40 of rvclkhdr_40 @[el2_lib.scala 483:22] + rvclkhdr_39.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_39.io.en <= write_fill_data_3 @[lib.scala 345:16] + rvclkhdr_39.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_40 of rvclkhdr_40 @[lib.scala 343:22] rvclkhdr_40.clock <= clock rvclkhdr_40.reset <= reset - rvclkhdr_40.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_40.io.en <= write_fill_data_4 @[el2_lib.scala 485:16] - rvclkhdr_40.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_41 of rvclkhdr_41 @[el2_lib.scala 483:22] + rvclkhdr_40.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_40.io.en <= write_fill_data_4 @[lib.scala 345:16] + rvclkhdr_40.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_41 of rvclkhdr_41 @[lib.scala 343:22] rvclkhdr_41.clock <= clock rvclkhdr_41.reset <= reset - rvclkhdr_41.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_41.io.en <= write_fill_data_5 @[el2_lib.scala 485:16] - rvclkhdr_41.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_42 of rvclkhdr_42 @[el2_lib.scala 483:22] + rvclkhdr_41.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_41.io.en <= write_fill_data_5 @[lib.scala 345:16] + rvclkhdr_41.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_42 of rvclkhdr_42 @[lib.scala 343:22] rvclkhdr_42.clock <= clock rvclkhdr_42.reset <= reset - rvclkhdr_42.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_42.io.en <= write_fill_data_6 @[el2_lib.scala 485:16] - rvclkhdr_42.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_43 of rvclkhdr_43 @[el2_lib.scala 483:22] + rvclkhdr_42.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_42.io.en <= write_fill_data_6 @[lib.scala 345:16] + rvclkhdr_42.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_43 of rvclkhdr_43 @[lib.scala 343:22] rvclkhdr_43.clock <= clock rvclkhdr_43.reset <= reset - rvclkhdr_43.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_43.io.en <= write_fill_data_7 @[el2_lib.scala 485:16] - rvclkhdr_43.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_43.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_43.io.en <= write_fill_data_7 @[lib.scala 345:16] + rvclkhdr_43.io.scan_mode <= io.scan_mode @[lib.scala 346:23] node _T_1313 = bits(ic_miss_buff_data_in, 31, 0) @[ifu_mem_ctl.scala 316:86] reg _T_1314 : UInt, rvclkhdr_40.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 316:65] _T_1314 <= _T_1313 @[ifu_mem_ctl.scala 316:65] @@ -4656,54 +4656,54 @@ circuit quasar_wrapper : reg _T_1316 : UInt, rvclkhdr_40.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 317:67] _T_1316 <= _T_1315 @[ifu_mem_ctl.scala 317:67] ic_miss_buff_data[9] <= _T_1316 @[ifu_mem_ctl.scala 317:28] - inst rvclkhdr_44 of rvclkhdr_44 @[el2_lib.scala 483:22] + inst rvclkhdr_44 of rvclkhdr_44 @[lib.scala 343:22] rvclkhdr_44.clock <= clock rvclkhdr_44.reset <= reset - rvclkhdr_44.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_44.io.en <= write_fill_data_0 @[el2_lib.scala 485:16] - rvclkhdr_44.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_45 of rvclkhdr_45 @[el2_lib.scala 483:22] + rvclkhdr_44.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_44.io.en <= write_fill_data_0 @[lib.scala 345:16] + rvclkhdr_44.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_45 of rvclkhdr_45 @[lib.scala 343:22] rvclkhdr_45.clock <= clock rvclkhdr_45.reset <= reset - rvclkhdr_45.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_45.io.en <= write_fill_data_1 @[el2_lib.scala 485:16] - rvclkhdr_45.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_46 of rvclkhdr_46 @[el2_lib.scala 483:22] + rvclkhdr_45.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_45.io.en <= write_fill_data_1 @[lib.scala 345:16] + rvclkhdr_45.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_46 of rvclkhdr_46 @[lib.scala 343:22] rvclkhdr_46.clock <= clock rvclkhdr_46.reset <= reset - rvclkhdr_46.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_46.io.en <= write_fill_data_2 @[el2_lib.scala 485:16] - rvclkhdr_46.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_47 of rvclkhdr_47 @[el2_lib.scala 483:22] + rvclkhdr_46.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_46.io.en <= write_fill_data_2 @[lib.scala 345:16] + rvclkhdr_46.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_47 of rvclkhdr_47 @[lib.scala 343:22] rvclkhdr_47.clock <= clock rvclkhdr_47.reset <= reset - rvclkhdr_47.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_47.io.en <= write_fill_data_3 @[el2_lib.scala 485:16] - rvclkhdr_47.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_48 of rvclkhdr_48 @[el2_lib.scala 483:22] + rvclkhdr_47.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_47.io.en <= write_fill_data_3 @[lib.scala 345:16] + rvclkhdr_47.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_48 of rvclkhdr_48 @[lib.scala 343:22] rvclkhdr_48.clock <= clock rvclkhdr_48.reset <= reset - rvclkhdr_48.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_48.io.en <= write_fill_data_4 @[el2_lib.scala 485:16] - rvclkhdr_48.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_49 of rvclkhdr_49 @[el2_lib.scala 483:22] + rvclkhdr_48.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_48.io.en <= write_fill_data_4 @[lib.scala 345:16] + rvclkhdr_48.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_49 of rvclkhdr_49 @[lib.scala 343:22] rvclkhdr_49.clock <= clock rvclkhdr_49.reset <= reset - rvclkhdr_49.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_49.io.en <= write_fill_data_5 @[el2_lib.scala 485:16] - rvclkhdr_49.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_50 of rvclkhdr_50 @[el2_lib.scala 483:22] + rvclkhdr_49.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_49.io.en <= write_fill_data_5 @[lib.scala 345:16] + rvclkhdr_49.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_50 of rvclkhdr_50 @[lib.scala 343:22] rvclkhdr_50.clock <= clock rvclkhdr_50.reset <= reset - rvclkhdr_50.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_50.io.en <= write_fill_data_6 @[el2_lib.scala 485:16] - rvclkhdr_50.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_51 of rvclkhdr_51 @[el2_lib.scala 483:22] + rvclkhdr_50.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_50.io.en <= write_fill_data_6 @[lib.scala 345:16] + rvclkhdr_50.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_51 of rvclkhdr_51 @[lib.scala 343:22] rvclkhdr_51.clock <= clock rvclkhdr_51.reset <= reset - rvclkhdr_51.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_51.io.en <= write_fill_data_7 @[el2_lib.scala 485:16] - rvclkhdr_51.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_51.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_51.io.en <= write_fill_data_7 @[lib.scala 345:16] + rvclkhdr_51.io.scan_mode <= io.scan_mode @[lib.scala 346:23] node _T_1317 = bits(ic_miss_buff_data_in, 31, 0) @[ifu_mem_ctl.scala 316:86] reg _T_1318 : UInt, rvclkhdr_49.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 316:65] _T_1318 <= _T_1317 @[ifu_mem_ctl.scala 316:65] @@ -4712,54 +4712,54 @@ circuit quasar_wrapper : reg _T_1320 : UInt, rvclkhdr_49.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 317:67] _T_1320 <= _T_1319 @[ifu_mem_ctl.scala 317:67] ic_miss_buff_data[11] <= _T_1320 @[ifu_mem_ctl.scala 317:28] - inst rvclkhdr_52 of rvclkhdr_52 @[el2_lib.scala 483:22] + inst rvclkhdr_52 of rvclkhdr_52 @[lib.scala 343:22] rvclkhdr_52.clock <= clock rvclkhdr_52.reset <= reset - rvclkhdr_52.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_52.io.en <= write_fill_data_0 @[el2_lib.scala 485:16] - rvclkhdr_52.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_53 of rvclkhdr_53 @[el2_lib.scala 483:22] + rvclkhdr_52.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_52.io.en <= write_fill_data_0 @[lib.scala 345:16] + rvclkhdr_52.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_53 of rvclkhdr_53 @[lib.scala 343:22] rvclkhdr_53.clock <= clock rvclkhdr_53.reset <= reset - rvclkhdr_53.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_53.io.en <= write_fill_data_1 @[el2_lib.scala 485:16] - rvclkhdr_53.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_54 of rvclkhdr_54 @[el2_lib.scala 483:22] + rvclkhdr_53.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_53.io.en <= write_fill_data_1 @[lib.scala 345:16] + rvclkhdr_53.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_54 of rvclkhdr_54 @[lib.scala 343:22] rvclkhdr_54.clock <= clock rvclkhdr_54.reset <= reset - rvclkhdr_54.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_54.io.en <= write_fill_data_2 @[el2_lib.scala 485:16] - rvclkhdr_54.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_55 of rvclkhdr_55 @[el2_lib.scala 483:22] + rvclkhdr_54.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_54.io.en <= write_fill_data_2 @[lib.scala 345:16] + rvclkhdr_54.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_55 of rvclkhdr_55 @[lib.scala 343:22] rvclkhdr_55.clock <= clock rvclkhdr_55.reset <= reset - rvclkhdr_55.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_55.io.en <= write_fill_data_3 @[el2_lib.scala 485:16] - rvclkhdr_55.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_56 of rvclkhdr_56 @[el2_lib.scala 483:22] + rvclkhdr_55.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_55.io.en <= write_fill_data_3 @[lib.scala 345:16] + rvclkhdr_55.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_56 of rvclkhdr_56 @[lib.scala 343:22] rvclkhdr_56.clock <= clock rvclkhdr_56.reset <= reset - rvclkhdr_56.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_56.io.en <= write_fill_data_4 @[el2_lib.scala 485:16] - rvclkhdr_56.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_57 of rvclkhdr_57 @[el2_lib.scala 483:22] + rvclkhdr_56.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_56.io.en <= write_fill_data_4 @[lib.scala 345:16] + rvclkhdr_56.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_57 of rvclkhdr_57 @[lib.scala 343:22] rvclkhdr_57.clock <= clock rvclkhdr_57.reset <= reset - rvclkhdr_57.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_57.io.en <= write_fill_data_5 @[el2_lib.scala 485:16] - rvclkhdr_57.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_58 of rvclkhdr_58 @[el2_lib.scala 483:22] + rvclkhdr_57.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_57.io.en <= write_fill_data_5 @[lib.scala 345:16] + rvclkhdr_57.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_58 of rvclkhdr_58 @[lib.scala 343:22] rvclkhdr_58.clock <= clock rvclkhdr_58.reset <= reset - rvclkhdr_58.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_58.io.en <= write_fill_data_6 @[el2_lib.scala 485:16] - rvclkhdr_58.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_59 of rvclkhdr_59 @[el2_lib.scala 483:22] + rvclkhdr_58.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_58.io.en <= write_fill_data_6 @[lib.scala 345:16] + rvclkhdr_58.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_59 of rvclkhdr_59 @[lib.scala 343:22] rvclkhdr_59.clock <= clock rvclkhdr_59.reset <= reset - rvclkhdr_59.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_59.io.en <= write_fill_data_7 @[el2_lib.scala 485:16] - rvclkhdr_59.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_59.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_59.io.en <= write_fill_data_7 @[lib.scala 345:16] + rvclkhdr_59.io.scan_mode <= io.scan_mode @[lib.scala 346:23] node _T_1321 = bits(ic_miss_buff_data_in, 31, 0) @[ifu_mem_ctl.scala 316:86] reg _T_1322 : UInt, rvclkhdr_58.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 316:65] _T_1322 <= _T_1321 @[ifu_mem_ctl.scala 316:65] @@ -4768,54 +4768,54 @@ circuit quasar_wrapper : reg _T_1324 : UInt, rvclkhdr_58.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 317:67] _T_1324 <= _T_1323 @[ifu_mem_ctl.scala 317:67] ic_miss_buff_data[13] <= _T_1324 @[ifu_mem_ctl.scala 317:28] - inst rvclkhdr_60 of rvclkhdr_60 @[el2_lib.scala 483:22] + inst rvclkhdr_60 of rvclkhdr_60 @[lib.scala 343:22] rvclkhdr_60.clock <= clock rvclkhdr_60.reset <= reset - rvclkhdr_60.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_60.io.en <= write_fill_data_0 @[el2_lib.scala 485:16] - rvclkhdr_60.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_61 of rvclkhdr_61 @[el2_lib.scala 483:22] + rvclkhdr_60.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_60.io.en <= write_fill_data_0 @[lib.scala 345:16] + rvclkhdr_60.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_61 of rvclkhdr_61 @[lib.scala 343:22] rvclkhdr_61.clock <= clock rvclkhdr_61.reset <= reset - rvclkhdr_61.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_61.io.en <= write_fill_data_1 @[el2_lib.scala 485:16] - rvclkhdr_61.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_62 of rvclkhdr_62 @[el2_lib.scala 483:22] + rvclkhdr_61.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_61.io.en <= write_fill_data_1 @[lib.scala 345:16] + rvclkhdr_61.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_62 of rvclkhdr_62 @[lib.scala 343:22] rvclkhdr_62.clock <= clock rvclkhdr_62.reset <= reset - rvclkhdr_62.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_62.io.en <= write_fill_data_2 @[el2_lib.scala 485:16] - rvclkhdr_62.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_63 of rvclkhdr_63 @[el2_lib.scala 483:22] + rvclkhdr_62.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_62.io.en <= write_fill_data_2 @[lib.scala 345:16] + rvclkhdr_62.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_63 of rvclkhdr_63 @[lib.scala 343:22] rvclkhdr_63.clock <= clock rvclkhdr_63.reset <= reset - rvclkhdr_63.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_63.io.en <= write_fill_data_3 @[el2_lib.scala 485:16] - rvclkhdr_63.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_64 of rvclkhdr_64 @[el2_lib.scala 483:22] + rvclkhdr_63.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_63.io.en <= write_fill_data_3 @[lib.scala 345:16] + rvclkhdr_63.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_64 of rvclkhdr_64 @[lib.scala 343:22] rvclkhdr_64.clock <= clock rvclkhdr_64.reset <= reset - rvclkhdr_64.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_64.io.en <= write_fill_data_4 @[el2_lib.scala 485:16] - rvclkhdr_64.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_65 of rvclkhdr_65 @[el2_lib.scala 483:22] + rvclkhdr_64.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_64.io.en <= write_fill_data_4 @[lib.scala 345:16] + rvclkhdr_64.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_65 of rvclkhdr_65 @[lib.scala 343:22] rvclkhdr_65.clock <= clock rvclkhdr_65.reset <= reset - rvclkhdr_65.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_65.io.en <= write_fill_data_5 @[el2_lib.scala 485:16] - rvclkhdr_65.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_66 of rvclkhdr_66 @[el2_lib.scala 483:22] + rvclkhdr_65.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_65.io.en <= write_fill_data_5 @[lib.scala 345:16] + rvclkhdr_65.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_66 of rvclkhdr_66 @[lib.scala 343:22] rvclkhdr_66.clock <= clock rvclkhdr_66.reset <= reset - rvclkhdr_66.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_66.io.en <= write_fill_data_6 @[el2_lib.scala 485:16] - rvclkhdr_66.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_67 of rvclkhdr_67 @[el2_lib.scala 483:22] + rvclkhdr_66.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_66.io.en <= write_fill_data_6 @[lib.scala 345:16] + rvclkhdr_66.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_67 of rvclkhdr_67 @[lib.scala 343:22] rvclkhdr_67.clock <= clock rvclkhdr_67.reset <= reset - rvclkhdr_67.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_67.io.en <= write_fill_data_7 @[el2_lib.scala 485:16] - rvclkhdr_67.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_67.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_67.io.en <= write_fill_data_7 @[lib.scala 345:16] + rvclkhdr_67.io.scan_mode <= io.scan_mode @[lib.scala 346:23] node _T_1325 = bits(ic_miss_buff_data_in, 31, 0) @[ifu_mem_ctl.scala 316:86] reg _T_1326 : UInt, rvclkhdr_67.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 316:65] _T_1326 <= _T_1325 @[ifu_mem_ctl.scala 316:65] @@ -6244,19 +6244,19 @@ circuit quasar_wrapper : skip @[Reg.scala 28:19] err_stop_state <= _T_2586 @[ifu_mem_ctl.scala 459:18] bus_ifu_bus_clk_en <= io.ifu_bus_clk_en @[ifu_mem_ctl.scala 460:22] - inst rvclkhdr_68 of rvclkhdr_68 @[el2_lib.scala 483:22] + inst rvclkhdr_68 of rvclkhdr_68 @[lib.scala 343:22] rvclkhdr_68.clock <= clock rvclkhdr_68.reset <= reset - rvclkhdr_68.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_68.io.en <= bus_ifu_bus_clk_en @[el2_lib.scala 485:16] - rvclkhdr_68.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_68.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_68.io.en <= bus_ifu_bus_clk_en @[lib.scala 345:16] + rvclkhdr_68.io.scan_mode <= io.scan_mode @[lib.scala 346:23] node _T_2587 = or(bus_ifu_bus_clk_en, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 462:59] - inst rvclkhdr_69 of rvclkhdr_69 @[el2_lib.scala 483:22] + inst rvclkhdr_69 of rvclkhdr_69 @[lib.scala 343:22] rvclkhdr_69.clock <= clock rvclkhdr_69.reset <= reset - rvclkhdr_69.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_69.io.en <= _T_2587 @[el2_lib.scala 485:16] - rvclkhdr_69.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_69.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_69.io.en <= _T_2587 @[lib.scala 345:16] + rvclkhdr_69.io.scan_mode <= io.scan_mode @[lib.scala 346:23] reg bus_ifu_bus_clk_en_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 463:61] bus_ifu_bus_clk_en_ff <= bus_ifu_bus_clk_en @[ifu_mem_ctl.scala 463:61] reg _T_2588 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 464:52] @@ -6519,372 +6519,372 @@ circuit quasar_wrapper : node _T_2721 = and(_T_2720, io.dma_mem_ctl.dma_mem_sz) @[ifu_mem_ctl.scala 572:59] io.iccm.wr_size <= _T_2721 @[ifu_mem_ctl.scala 572:19] node _T_2722 = bits(io.dma_mem_ctl.dma_mem_wdata, 63, 32) @[ifu_mem_ctl.scala 574:66] - node _T_2723 = bits(_T_2722, 0, 0) @[el2_lib.scala 259:58] - node _T_2724 = bits(_T_2722, 1, 1) @[el2_lib.scala 259:58] - node _T_2725 = bits(_T_2722, 3, 3) @[el2_lib.scala 259:58] - node _T_2726 = bits(_T_2722, 4, 4) @[el2_lib.scala 259:58] - node _T_2727 = bits(_T_2722, 6, 6) @[el2_lib.scala 259:58] - node _T_2728 = bits(_T_2722, 8, 8) @[el2_lib.scala 259:58] - node _T_2729 = bits(_T_2722, 10, 10) @[el2_lib.scala 259:58] - node _T_2730 = bits(_T_2722, 11, 11) @[el2_lib.scala 259:58] - node _T_2731 = bits(_T_2722, 13, 13) @[el2_lib.scala 259:58] - node _T_2732 = bits(_T_2722, 15, 15) @[el2_lib.scala 259:58] - node _T_2733 = bits(_T_2722, 17, 17) @[el2_lib.scala 259:58] - node _T_2734 = bits(_T_2722, 19, 19) @[el2_lib.scala 259:58] - node _T_2735 = bits(_T_2722, 21, 21) @[el2_lib.scala 259:58] - node _T_2736 = bits(_T_2722, 23, 23) @[el2_lib.scala 259:58] - node _T_2737 = bits(_T_2722, 25, 25) @[el2_lib.scala 259:58] - node _T_2738 = bits(_T_2722, 26, 26) @[el2_lib.scala 259:58] - node _T_2739 = bits(_T_2722, 28, 28) @[el2_lib.scala 259:58] - node _T_2740 = bits(_T_2722, 30, 30) @[el2_lib.scala 259:58] - node _T_2741 = xor(_T_2723, _T_2724) @[el2_lib.scala 259:74] - node _T_2742 = xor(_T_2741, _T_2725) @[el2_lib.scala 259:74] - node _T_2743 = xor(_T_2742, _T_2726) @[el2_lib.scala 259:74] - node _T_2744 = xor(_T_2743, _T_2727) @[el2_lib.scala 259:74] - node _T_2745 = xor(_T_2744, _T_2728) @[el2_lib.scala 259:74] - node _T_2746 = xor(_T_2745, _T_2729) @[el2_lib.scala 259:74] - node _T_2747 = xor(_T_2746, _T_2730) @[el2_lib.scala 259:74] - node _T_2748 = xor(_T_2747, _T_2731) @[el2_lib.scala 259:74] - node _T_2749 = xor(_T_2748, _T_2732) @[el2_lib.scala 259:74] - node _T_2750 = xor(_T_2749, _T_2733) @[el2_lib.scala 259:74] - node _T_2751 = xor(_T_2750, _T_2734) @[el2_lib.scala 259:74] - node _T_2752 = xor(_T_2751, _T_2735) @[el2_lib.scala 259:74] - node _T_2753 = xor(_T_2752, _T_2736) @[el2_lib.scala 259:74] - node _T_2754 = xor(_T_2753, _T_2737) @[el2_lib.scala 259:74] - node _T_2755 = xor(_T_2754, _T_2738) @[el2_lib.scala 259:74] - node _T_2756 = xor(_T_2755, _T_2739) @[el2_lib.scala 259:74] - node _T_2757 = xor(_T_2756, _T_2740) @[el2_lib.scala 259:74] - node _T_2758 = bits(_T_2722, 0, 0) @[el2_lib.scala 259:58] - node _T_2759 = bits(_T_2722, 2, 2) @[el2_lib.scala 259:58] - node _T_2760 = bits(_T_2722, 3, 3) @[el2_lib.scala 259:58] - node _T_2761 = bits(_T_2722, 5, 5) @[el2_lib.scala 259:58] - node _T_2762 = bits(_T_2722, 6, 6) @[el2_lib.scala 259:58] - node _T_2763 = bits(_T_2722, 9, 9) @[el2_lib.scala 259:58] - node _T_2764 = bits(_T_2722, 10, 10) @[el2_lib.scala 259:58] - node _T_2765 = bits(_T_2722, 12, 12) @[el2_lib.scala 259:58] - node _T_2766 = bits(_T_2722, 13, 13) @[el2_lib.scala 259:58] - node _T_2767 = bits(_T_2722, 16, 16) @[el2_lib.scala 259:58] - node _T_2768 = bits(_T_2722, 17, 17) @[el2_lib.scala 259:58] - node _T_2769 = bits(_T_2722, 20, 20) @[el2_lib.scala 259:58] - node _T_2770 = bits(_T_2722, 21, 21) @[el2_lib.scala 259:58] - node _T_2771 = bits(_T_2722, 24, 24) @[el2_lib.scala 259:58] - node _T_2772 = bits(_T_2722, 25, 25) @[el2_lib.scala 259:58] - node _T_2773 = bits(_T_2722, 27, 27) @[el2_lib.scala 259:58] - node _T_2774 = bits(_T_2722, 28, 28) @[el2_lib.scala 259:58] - node _T_2775 = bits(_T_2722, 31, 31) @[el2_lib.scala 259:58] - node _T_2776 = xor(_T_2758, _T_2759) @[el2_lib.scala 259:74] - node _T_2777 = xor(_T_2776, _T_2760) @[el2_lib.scala 259:74] - node _T_2778 = xor(_T_2777, _T_2761) @[el2_lib.scala 259:74] - node _T_2779 = xor(_T_2778, _T_2762) @[el2_lib.scala 259:74] - node _T_2780 = xor(_T_2779, _T_2763) @[el2_lib.scala 259:74] - node _T_2781 = xor(_T_2780, _T_2764) @[el2_lib.scala 259:74] - node _T_2782 = xor(_T_2781, _T_2765) @[el2_lib.scala 259:74] - node _T_2783 = xor(_T_2782, _T_2766) @[el2_lib.scala 259:74] - node _T_2784 = xor(_T_2783, _T_2767) @[el2_lib.scala 259:74] - node _T_2785 = xor(_T_2784, _T_2768) @[el2_lib.scala 259:74] - node _T_2786 = xor(_T_2785, _T_2769) @[el2_lib.scala 259:74] - node _T_2787 = xor(_T_2786, _T_2770) @[el2_lib.scala 259:74] - node _T_2788 = xor(_T_2787, _T_2771) @[el2_lib.scala 259:74] - node _T_2789 = xor(_T_2788, _T_2772) @[el2_lib.scala 259:74] - node _T_2790 = xor(_T_2789, _T_2773) @[el2_lib.scala 259:74] - node _T_2791 = xor(_T_2790, _T_2774) @[el2_lib.scala 259:74] - node _T_2792 = xor(_T_2791, _T_2775) @[el2_lib.scala 259:74] - node _T_2793 = bits(_T_2722, 1, 1) @[el2_lib.scala 259:58] - node _T_2794 = bits(_T_2722, 2, 2) @[el2_lib.scala 259:58] - node _T_2795 = bits(_T_2722, 3, 3) @[el2_lib.scala 259:58] - node _T_2796 = bits(_T_2722, 7, 7) @[el2_lib.scala 259:58] - node _T_2797 = bits(_T_2722, 8, 8) @[el2_lib.scala 259:58] - node _T_2798 = bits(_T_2722, 9, 9) @[el2_lib.scala 259:58] - node _T_2799 = bits(_T_2722, 10, 10) @[el2_lib.scala 259:58] - node _T_2800 = bits(_T_2722, 14, 14) @[el2_lib.scala 259:58] - node _T_2801 = bits(_T_2722, 15, 15) @[el2_lib.scala 259:58] - node _T_2802 = bits(_T_2722, 16, 16) @[el2_lib.scala 259:58] - node _T_2803 = bits(_T_2722, 17, 17) @[el2_lib.scala 259:58] - node _T_2804 = bits(_T_2722, 22, 22) @[el2_lib.scala 259:58] - node _T_2805 = bits(_T_2722, 23, 23) @[el2_lib.scala 259:58] - node _T_2806 = bits(_T_2722, 24, 24) @[el2_lib.scala 259:58] - node _T_2807 = bits(_T_2722, 25, 25) @[el2_lib.scala 259:58] - node _T_2808 = bits(_T_2722, 29, 29) @[el2_lib.scala 259:58] - node _T_2809 = bits(_T_2722, 30, 30) @[el2_lib.scala 259:58] - node _T_2810 = bits(_T_2722, 31, 31) @[el2_lib.scala 259:58] - node _T_2811 = xor(_T_2793, _T_2794) @[el2_lib.scala 259:74] - node _T_2812 = xor(_T_2811, _T_2795) @[el2_lib.scala 259:74] - node _T_2813 = xor(_T_2812, _T_2796) @[el2_lib.scala 259:74] - node _T_2814 = xor(_T_2813, _T_2797) @[el2_lib.scala 259:74] - node _T_2815 = xor(_T_2814, _T_2798) @[el2_lib.scala 259:74] - node _T_2816 = xor(_T_2815, _T_2799) @[el2_lib.scala 259:74] - node _T_2817 = xor(_T_2816, _T_2800) @[el2_lib.scala 259:74] - node _T_2818 = xor(_T_2817, _T_2801) @[el2_lib.scala 259:74] - node _T_2819 = xor(_T_2818, _T_2802) @[el2_lib.scala 259:74] - node _T_2820 = xor(_T_2819, _T_2803) @[el2_lib.scala 259:74] - node _T_2821 = xor(_T_2820, _T_2804) @[el2_lib.scala 259:74] - node _T_2822 = xor(_T_2821, _T_2805) @[el2_lib.scala 259:74] - node _T_2823 = xor(_T_2822, _T_2806) @[el2_lib.scala 259:74] - node _T_2824 = xor(_T_2823, _T_2807) @[el2_lib.scala 259:74] - node _T_2825 = xor(_T_2824, _T_2808) @[el2_lib.scala 259:74] - node _T_2826 = xor(_T_2825, _T_2809) @[el2_lib.scala 259:74] - node _T_2827 = xor(_T_2826, _T_2810) @[el2_lib.scala 259:74] - node _T_2828 = bits(_T_2722, 4, 4) @[el2_lib.scala 259:58] - node _T_2829 = bits(_T_2722, 5, 5) @[el2_lib.scala 259:58] - node _T_2830 = bits(_T_2722, 6, 6) @[el2_lib.scala 259:58] - node _T_2831 = bits(_T_2722, 7, 7) @[el2_lib.scala 259:58] - node _T_2832 = bits(_T_2722, 8, 8) @[el2_lib.scala 259:58] - node _T_2833 = bits(_T_2722, 9, 9) @[el2_lib.scala 259:58] - node _T_2834 = bits(_T_2722, 10, 10) @[el2_lib.scala 259:58] - node _T_2835 = bits(_T_2722, 18, 18) @[el2_lib.scala 259:58] - node _T_2836 = bits(_T_2722, 19, 19) @[el2_lib.scala 259:58] - node _T_2837 = bits(_T_2722, 20, 20) @[el2_lib.scala 259:58] - node _T_2838 = bits(_T_2722, 21, 21) @[el2_lib.scala 259:58] - node _T_2839 = bits(_T_2722, 22, 22) @[el2_lib.scala 259:58] - node _T_2840 = bits(_T_2722, 23, 23) @[el2_lib.scala 259:58] - node _T_2841 = bits(_T_2722, 24, 24) @[el2_lib.scala 259:58] - node _T_2842 = bits(_T_2722, 25, 25) @[el2_lib.scala 259:58] - node _T_2843 = xor(_T_2828, _T_2829) @[el2_lib.scala 259:74] - node _T_2844 = xor(_T_2843, _T_2830) @[el2_lib.scala 259:74] - node _T_2845 = xor(_T_2844, _T_2831) @[el2_lib.scala 259:74] - node _T_2846 = xor(_T_2845, _T_2832) @[el2_lib.scala 259:74] - node _T_2847 = xor(_T_2846, _T_2833) @[el2_lib.scala 259:74] - node _T_2848 = xor(_T_2847, _T_2834) @[el2_lib.scala 259:74] - node _T_2849 = xor(_T_2848, _T_2835) @[el2_lib.scala 259:74] - node _T_2850 = xor(_T_2849, _T_2836) @[el2_lib.scala 259:74] - node _T_2851 = xor(_T_2850, _T_2837) @[el2_lib.scala 259:74] - node _T_2852 = xor(_T_2851, _T_2838) @[el2_lib.scala 259:74] - node _T_2853 = xor(_T_2852, _T_2839) @[el2_lib.scala 259:74] - node _T_2854 = xor(_T_2853, _T_2840) @[el2_lib.scala 259:74] - node _T_2855 = xor(_T_2854, _T_2841) @[el2_lib.scala 259:74] - node _T_2856 = xor(_T_2855, _T_2842) @[el2_lib.scala 259:74] - node _T_2857 = bits(_T_2722, 11, 11) @[el2_lib.scala 259:58] - node _T_2858 = bits(_T_2722, 12, 12) @[el2_lib.scala 259:58] - node _T_2859 = bits(_T_2722, 13, 13) @[el2_lib.scala 259:58] - node _T_2860 = bits(_T_2722, 14, 14) @[el2_lib.scala 259:58] - node _T_2861 = bits(_T_2722, 15, 15) @[el2_lib.scala 259:58] - node _T_2862 = bits(_T_2722, 16, 16) @[el2_lib.scala 259:58] - node _T_2863 = bits(_T_2722, 17, 17) @[el2_lib.scala 259:58] - node _T_2864 = bits(_T_2722, 18, 18) @[el2_lib.scala 259:58] - node _T_2865 = bits(_T_2722, 19, 19) @[el2_lib.scala 259:58] - node _T_2866 = bits(_T_2722, 20, 20) @[el2_lib.scala 259:58] - node _T_2867 = bits(_T_2722, 21, 21) @[el2_lib.scala 259:58] - node _T_2868 = bits(_T_2722, 22, 22) @[el2_lib.scala 259:58] - node _T_2869 = bits(_T_2722, 23, 23) @[el2_lib.scala 259:58] - node _T_2870 = bits(_T_2722, 24, 24) @[el2_lib.scala 259:58] - node _T_2871 = bits(_T_2722, 25, 25) @[el2_lib.scala 259:58] - node _T_2872 = xor(_T_2857, _T_2858) @[el2_lib.scala 259:74] - node _T_2873 = xor(_T_2872, _T_2859) @[el2_lib.scala 259:74] - node _T_2874 = xor(_T_2873, _T_2860) @[el2_lib.scala 259:74] - node _T_2875 = xor(_T_2874, _T_2861) @[el2_lib.scala 259:74] - node _T_2876 = xor(_T_2875, _T_2862) @[el2_lib.scala 259:74] - node _T_2877 = xor(_T_2876, _T_2863) @[el2_lib.scala 259:74] - node _T_2878 = xor(_T_2877, _T_2864) @[el2_lib.scala 259:74] - node _T_2879 = xor(_T_2878, _T_2865) @[el2_lib.scala 259:74] - node _T_2880 = xor(_T_2879, _T_2866) @[el2_lib.scala 259:74] - node _T_2881 = xor(_T_2880, _T_2867) @[el2_lib.scala 259:74] - node _T_2882 = xor(_T_2881, _T_2868) @[el2_lib.scala 259:74] - node _T_2883 = xor(_T_2882, _T_2869) @[el2_lib.scala 259:74] - node _T_2884 = xor(_T_2883, _T_2870) @[el2_lib.scala 259:74] - node _T_2885 = xor(_T_2884, _T_2871) @[el2_lib.scala 259:74] - node _T_2886 = bits(_T_2722, 26, 26) @[el2_lib.scala 259:58] - node _T_2887 = bits(_T_2722, 27, 27) @[el2_lib.scala 259:58] - node _T_2888 = bits(_T_2722, 28, 28) @[el2_lib.scala 259:58] - node _T_2889 = bits(_T_2722, 29, 29) @[el2_lib.scala 259:58] - node _T_2890 = bits(_T_2722, 30, 30) @[el2_lib.scala 259:58] - node _T_2891 = bits(_T_2722, 31, 31) @[el2_lib.scala 259:58] - node _T_2892 = xor(_T_2886, _T_2887) @[el2_lib.scala 259:74] - node _T_2893 = xor(_T_2892, _T_2888) @[el2_lib.scala 259:74] - node _T_2894 = xor(_T_2893, _T_2889) @[el2_lib.scala 259:74] - node _T_2895 = xor(_T_2894, _T_2890) @[el2_lib.scala 259:74] - node _T_2896 = xor(_T_2895, _T_2891) @[el2_lib.scala 259:74] + node _T_2723 = bits(_T_2722, 0, 0) @[lib.scala 119:58] + node _T_2724 = bits(_T_2722, 1, 1) @[lib.scala 119:58] + node _T_2725 = bits(_T_2722, 3, 3) @[lib.scala 119:58] + node _T_2726 = bits(_T_2722, 4, 4) @[lib.scala 119:58] + node _T_2727 = bits(_T_2722, 6, 6) @[lib.scala 119:58] + node _T_2728 = bits(_T_2722, 8, 8) @[lib.scala 119:58] + node _T_2729 = bits(_T_2722, 10, 10) @[lib.scala 119:58] + node _T_2730 = bits(_T_2722, 11, 11) @[lib.scala 119:58] + node _T_2731 = bits(_T_2722, 13, 13) @[lib.scala 119:58] + node _T_2732 = bits(_T_2722, 15, 15) @[lib.scala 119:58] + node _T_2733 = bits(_T_2722, 17, 17) @[lib.scala 119:58] + node _T_2734 = bits(_T_2722, 19, 19) @[lib.scala 119:58] + node _T_2735 = bits(_T_2722, 21, 21) @[lib.scala 119:58] + node _T_2736 = bits(_T_2722, 23, 23) @[lib.scala 119:58] + node _T_2737 = bits(_T_2722, 25, 25) @[lib.scala 119:58] + node _T_2738 = bits(_T_2722, 26, 26) @[lib.scala 119:58] + node _T_2739 = bits(_T_2722, 28, 28) @[lib.scala 119:58] + node _T_2740 = bits(_T_2722, 30, 30) @[lib.scala 119:58] + node _T_2741 = xor(_T_2723, _T_2724) @[lib.scala 119:74] + node _T_2742 = xor(_T_2741, _T_2725) @[lib.scala 119:74] + node _T_2743 = xor(_T_2742, _T_2726) @[lib.scala 119:74] + node _T_2744 = xor(_T_2743, _T_2727) @[lib.scala 119:74] + node _T_2745 = xor(_T_2744, _T_2728) @[lib.scala 119:74] + node _T_2746 = xor(_T_2745, _T_2729) @[lib.scala 119:74] + node _T_2747 = xor(_T_2746, _T_2730) @[lib.scala 119:74] + node _T_2748 = xor(_T_2747, _T_2731) @[lib.scala 119:74] + node _T_2749 = xor(_T_2748, _T_2732) @[lib.scala 119:74] + node _T_2750 = xor(_T_2749, _T_2733) @[lib.scala 119:74] + node _T_2751 = xor(_T_2750, _T_2734) @[lib.scala 119:74] + node _T_2752 = xor(_T_2751, _T_2735) @[lib.scala 119:74] + node _T_2753 = xor(_T_2752, _T_2736) @[lib.scala 119:74] + node _T_2754 = xor(_T_2753, _T_2737) @[lib.scala 119:74] + node _T_2755 = xor(_T_2754, _T_2738) @[lib.scala 119:74] + node _T_2756 = xor(_T_2755, _T_2739) @[lib.scala 119:74] + node _T_2757 = xor(_T_2756, _T_2740) @[lib.scala 119:74] + node _T_2758 = bits(_T_2722, 0, 0) @[lib.scala 119:58] + node _T_2759 = bits(_T_2722, 2, 2) @[lib.scala 119:58] + node _T_2760 = bits(_T_2722, 3, 3) @[lib.scala 119:58] + node _T_2761 = bits(_T_2722, 5, 5) @[lib.scala 119:58] + node _T_2762 = bits(_T_2722, 6, 6) @[lib.scala 119:58] + node _T_2763 = bits(_T_2722, 9, 9) @[lib.scala 119:58] + node _T_2764 = bits(_T_2722, 10, 10) @[lib.scala 119:58] + node _T_2765 = bits(_T_2722, 12, 12) @[lib.scala 119:58] + node _T_2766 = bits(_T_2722, 13, 13) @[lib.scala 119:58] + node _T_2767 = bits(_T_2722, 16, 16) @[lib.scala 119:58] + node _T_2768 = bits(_T_2722, 17, 17) @[lib.scala 119:58] + node _T_2769 = bits(_T_2722, 20, 20) @[lib.scala 119:58] + node _T_2770 = bits(_T_2722, 21, 21) @[lib.scala 119:58] + node _T_2771 = bits(_T_2722, 24, 24) @[lib.scala 119:58] + node _T_2772 = bits(_T_2722, 25, 25) @[lib.scala 119:58] + node _T_2773 = bits(_T_2722, 27, 27) @[lib.scala 119:58] + node _T_2774 = bits(_T_2722, 28, 28) @[lib.scala 119:58] + node _T_2775 = bits(_T_2722, 31, 31) @[lib.scala 119:58] + node _T_2776 = xor(_T_2758, _T_2759) @[lib.scala 119:74] + node _T_2777 = xor(_T_2776, _T_2760) @[lib.scala 119:74] + node _T_2778 = xor(_T_2777, _T_2761) @[lib.scala 119:74] + node _T_2779 = xor(_T_2778, _T_2762) @[lib.scala 119:74] + node _T_2780 = xor(_T_2779, _T_2763) @[lib.scala 119:74] + node _T_2781 = xor(_T_2780, _T_2764) @[lib.scala 119:74] + node _T_2782 = xor(_T_2781, _T_2765) @[lib.scala 119:74] + node _T_2783 = xor(_T_2782, _T_2766) @[lib.scala 119:74] + node _T_2784 = xor(_T_2783, _T_2767) @[lib.scala 119:74] + node _T_2785 = xor(_T_2784, _T_2768) @[lib.scala 119:74] + node _T_2786 = xor(_T_2785, _T_2769) @[lib.scala 119:74] + node _T_2787 = xor(_T_2786, _T_2770) @[lib.scala 119:74] + node _T_2788 = xor(_T_2787, _T_2771) @[lib.scala 119:74] + node _T_2789 = xor(_T_2788, _T_2772) @[lib.scala 119:74] + node _T_2790 = xor(_T_2789, _T_2773) @[lib.scala 119:74] + node _T_2791 = xor(_T_2790, _T_2774) @[lib.scala 119:74] + node _T_2792 = xor(_T_2791, _T_2775) @[lib.scala 119:74] + node _T_2793 = bits(_T_2722, 1, 1) @[lib.scala 119:58] + node _T_2794 = bits(_T_2722, 2, 2) @[lib.scala 119:58] + node _T_2795 = bits(_T_2722, 3, 3) @[lib.scala 119:58] + node _T_2796 = bits(_T_2722, 7, 7) @[lib.scala 119:58] + node _T_2797 = bits(_T_2722, 8, 8) @[lib.scala 119:58] + node _T_2798 = bits(_T_2722, 9, 9) @[lib.scala 119:58] + node _T_2799 = bits(_T_2722, 10, 10) @[lib.scala 119:58] + node _T_2800 = bits(_T_2722, 14, 14) @[lib.scala 119:58] + node _T_2801 = bits(_T_2722, 15, 15) @[lib.scala 119:58] + node _T_2802 = bits(_T_2722, 16, 16) @[lib.scala 119:58] + node _T_2803 = bits(_T_2722, 17, 17) @[lib.scala 119:58] + node _T_2804 = bits(_T_2722, 22, 22) @[lib.scala 119:58] + node _T_2805 = bits(_T_2722, 23, 23) @[lib.scala 119:58] + node _T_2806 = bits(_T_2722, 24, 24) @[lib.scala 119:58] + node _T_2807 = bits(_T_2722, 25, 25) @[lib.scala 119:58] + node _T_2808 = bits(_T_2722, 29, 29) @[lib.scala 119:58] + node _T_2809 = bits(_T_2722, 30, 30) @[lib.scala 119:58] + node _T_2810 = bits(_T_2722, 31, 31) @[lib.scala 119:58] + node _T_2811 = xor(_T_2793, _T_2794) @[lib.scala 119:74] + node _T_2812 = xor(_T_2811, _T_2795) @[lib.scala 119:74] + node _T_2813 = xor(_T_2812, _T_2796) @[lib.scala 119:74] + node _T_2814 = xor(_T_2813, _T_2797) @[lib.scala 119:74] + node _T_2815 = xor(_T_2814, _T_2798) @[lib.scala 119:74] + node _T_2816 = xor(_T_2815, _T_2799) @[lib.scala 119:74] + node _T_2817 = xor(_T_2816, _T_2800) @[lib.scala 119:74] + node _T_2818 = xor(_T_2817, _T_2801) @[lib.scala 119:74] + node _T_2819 = xor(_T_2818, _T_2802) @[lib.scala 119:74] + node _T_2820 = xor(_T_2819, _T_2803) @[lib.scala 119:74] + node _T_2821 = xor(_T_2820, _T_2804) @[lib.scala 119:74] + node _T_2822 = xor(_T_2821, _T_2805) @[lib.scala 119:74] + node _T_2823 = xor(_T_2822, _T_2806) @[lib.scala 119:74] + node _T_2824 = xor(_T_2823, _T_2807) @[lib.scala 119:74] + node _T_2825 = xor(_T_2824, _T_2808) @[lib.scala 119:74] + node _T_2826 = xor(_T_2825, _T_2809) @[lib.scala 119:74] + node _T_2827 = xor(_T_2826, _T_2810) @[lib.scala 119:74] + node _T_2828 = bits(_T_2722, 4, 4) @[lib.scala 119:58] + node _T_2829 = bits(_T_2722, 5, 5) @[lib.scala 119:58] + node _T_2830 = bits(_T_2722, 6, 6) @[lib.scala 119:58] + node _T_2831 = bits(_T_2722, 7, 7) @[lib.scala 119:58] + node _T_2832 = bits(_T_2722, 8, 8) @[lib.scala 119:58] + node _T_2833 = bits(_T_2722, 9, 9) @[lib.scala 119:58] + node _T_2834 = bits(_T_2722, 10, 10) @[lib.scala 119:58] + node _T_2835 = bits(_T_2722, 18, 18) @[lib.scala 119:58] + node _T_2836 = bits(_T_2722, 19, 19) @[lib.scala 119:58] + node _T_2837 = bits(_T_2722, 20, 20) @[lib.scala 119:58] + node _T_2838 = bits(_T_2722, 21, 21) @[lib.scala 119:58] + node _T_2839 = bits(_T_2722, 22, 22) @[lib.scala 119:58] + node _T_2840 = bits(_T_2722, 23, 23) @[lib.scala 119:58] + node _T_2841 = bits(_T_2722, 24, 24) @[lib.scala 119:58] + node _T_2842 = bits(_T_2722, 25, 25) @[lib.scala 119:58] + node _T_2843 = xor(_T_2828, _T_2829) @[lib.scala 119:74] + node _T_2844 = xor(_T_2843, _T_2830) @[lib.scala 119:74] + node _T_2845 = xor(_T_2844, _T_2831) @[lib.scala 119:74] + node _T_2846 = xor(_T_2845, _T_2832) @[lib.scala 119:74] + node _T_2847 = xor(_T_2846, _T_2833) @[lib.scala 119:74] + node _T_2848 = xor(_T_2847, _T_2834) @[lib.scala 119:74] + node _T_2849 = xor(_T_2848, _T_2835) @[lib.scala 119:74] + node _T_2850 = xor(_T_2849, _T_2836) @[lib.scala 119:74] + node _T_2851 = xor(_T_2850, _T_2837) @[lib.scala 119:74] + node _T_2852 = xor(_T_2851, _T_2838) @[lib.scala 119:74] + node _T_2853 = xor(_T_2852, _T_2839) @[lib.scala 119:74] + node _T_2854 = xor(_T_2853, _T_2840) @[lib.scala 119:74] + node _T_2855 = xor(_T_2854, _T_2841) @[lib.scala 119:74] + node _T_2856 = xor(_T_2855, _T_2842) @[lib.scala 119:74] + node _T_2857 = bits(_T_2722, 11, 11) @[lib.scala 119:58] + node _T_2858 = bits(_T_2722, 12, 12) @[lib.scala 119:58] + node _T_2859 = bits(_T_2722, 13, 13) @[lib.scala 119:58] + node _T_2860 = bits(_T_2722, 14, 14) @[lib.scala 119:58] + node _T_2861 = bits(_T_2722, 15, 15) @[lib.scala 119:58] + node _T_2862 = bits(_T_2722, 16, 16) @[lib.scala 119:58] + node _T_2863 = bits(_T_2722, 17, 17) @[lib.scala 119:58] + node _T_2864 = bits(_T_2722, 18, 18) @[lib.scala 119:58] + node _T_2865 = bits(_T_2722, 19, 19) @[lib.scala 119:58] + node _T_2866 = bits(_T_2722, 20, 20) @[lib.scala 119:58] + node _T_2867 = bits(_T_2722, 21, 21) @[lib.scala 119:58] + node _T_2868 = bits(_T_2722, 22, 22) @[lib.scala 119:58] + node _T_2869 = bits(_T_2722, 23, 23) @[lib.scala 119:58] + node _T_2870 = bits(_T_2722, 24, 24) @[lib.scala 119:58] + node _T_2871 = bits(_T_2722, 25, 25) @[lib.scala 119:58] + node _T_2872 = xor(_T_2857, _T_2858) @[lib.scala 119:74] + node _T_2873 = xor(_T_2872, _T_2859) @[lib.scala 119:74] + node _T_2874 = xor(_T_2873, _T_2860) @[lib.scala 119:74] + node _T_2875 = xor(_T_2874, _T_2861) @[lib.scala 119:74] + node _T_2876 = xor(_T_2875, _T_2862) @[lib.scala 119:74] + node _T_2877 = xor(_T_2876, _T_2863) @[lib.scala 119:74] + node _T_2878 = xor(_T_2877, _T_2864) @[lib.scala 119:74] + node _T_2879 = xor(_T_2878, _T_2865) @[lib.scala 119:74] + node _T_2880 = xor(_T_2879, _T_2866) @[lib.scala 119:74] + node _T_2881 = xor(_T_2880, _T_2867) @[lib.scala 119:74] + node _T_2882 = xor(_T_2881, _T_2868) @[lib.scala 119:74] + node _T_2883 = xor(_T_2882, _T_2869) @[lib.scala 119:74] + node _T_2884 = xor(_T_2883, _T_2870) @[lib.scala 119:74] + node _T_2885 = xor(_T_2884, _T_2871) @[lib.scala 119:74] + node _T_2886 = bits(_T_2722, 26, 26) @[lib.scala 119:58] + node _T_2887 = bits(_T_2722, 27, 27) @[lib.scala 119:58] + node _T_2888 = bits(_T_2722, 28, 28) @[lib.scala 119:58] + node _T_2889 = bits(_T_2722, 29, 29) @[lib.scala 119:58] + node _T_2890 = bits(_T_2722, 30, 30) @[lib.scala 119:58] + node _T_2891 = bits(_T_2722, 31, 31) @[lib.scala 119:58] + node _T_2892 = xor(_T_2886, _T_2887) @[lib.scala 119:74] + node _T_2893 = xor(_T_2892, _T_2888) @[lib.scala 119:74] + node _T_2894 = xor(_T_2893, _T_2889) @[lib.scala 119:74] + node _T_2895 = xor(_T_2894, _T_2890) @[lib.scala 119:74] + node _T_2896 = xor(_T_2895, _T_2891) @[lib.scala 119:74] node _T_2897 = cat(_T_2827, _T_2792) @[Cat.scala 29:58] node _T_2898 = cat(_T_2897, _T_2757) @[Cat.scala 29:58] node _T_2899 = cat(_T_2896, _T_2885) @[Cat.scala 29:58] node _T_2900 = cat(_T_2899, _T_2856) @[Cat.scala 29:58] node _T_2901 = cat(_T_2900, _T_2898) @[Cat.scala 29:58] - node _T_2902 = xorr(_T_2722) @[el2_lib.scala 267:13] - node _T_2903 = xorr(_T_2901) @[el2_lib.scala 267:23] - node _T_2904 = xor(_T_2902, _T_2903) @[el2_lib.scala 267:18] + node _T_2902 = xorr(_T_2722) @[lib.scala 127:13] + node _T_2903 = xorr(_T_2901) @[lib.scala 127:23] + node _T_2904 = xor(_T_2902, _T_2903) @[lib.scala 127:18] node _T_2905 = cat(_T_2904, _T_2901) @[Cat.scala 29:58] node _T_2906 = bits(io.dma_mem_ctl.dma_mem_wdata, 31, 0) @[ifu_mem_ctl.scala 574:117] - node _T_2907 = bits(_T_2906, 0, 0) @[el2_lib.scala 259:58] - node _T_2908 = bits(_T_2906, 1, 1) @[el2_lib.scala 259:58] - node _T_2909 = bits(_T_2906, 3, 3) @[el2_lib.scala 259:58] - node _T_2910 = bits(_T_2906, 4, 4) @[el2_lib.scala 259:58] - node _T_2911 = bits(_T_2906, 6, 6) @[el2_lib.scala 259:58] - node _T_2912 = bits(_T_2906, 8, 8) @[el2_lib.scala 259:58] - node _T_2913 = bits(_T_2906, 10, 10) @[el2_lib.scala 259:58] - node _T_2914 = bits(_T_2906, 11, 11) @[el2_lib.scala 259:58] - node _T_2915 = bits(_T_2906, 13, 13) @[el2_lib.scala 259:58] - node _T_2916 = bits(_T_2906, 15, 15) @[el2_lib.scala 259:58] - node _T_2917 = bits(_T_2906, 17, 17) @[el2_lib.scala 259:58] - node _T_2918 = bits(_T_2906, 19, 19) @[el2_lib.scala 259:58] - node _T_2919 = bits(_T_2906, 21, 21) @[el2_lib.scala 259:58] - node _T_2920 = bits(_T_2906, 23, 23) @[el2_lib.scala 259:58] - node _T_2921 = bits(_T_2906, 25, 25) @[el2_lib.scala 259:58] - node _T_2922 = bits(_T_2906, 26, 26) @[el2_lib.scala 259:58] - node _T_2923 = bits(_T_2906, 28, 28) @[el2_lib.scala 259:58] - node _T_2924 = bits(_T_2906, 30, 30) @[el2_lib.scala 259:58] - node _T_2925 = xor(_T_2907, _T_2908) @[el2_lib.scala 259:74] - node _T_2926 = xor(_T_2925, _T_2909) @[el2_lib.scala 259:74] - node _T_2927 = xor(_T_2926, _T_2910) @[el2_lib.scala 259:74] - node _T_2928 = xor(_T_2927, _T_2911) @[el2_lib.scala 259:74] - node _T_2929 = xor(_T_2928, _T_2912) @[el2_lib.scala 259:74] - node _T_2930 = xor(_T_2929, _T_2913) @[el2_lib.scala 259:74] - node _T_2931 = xor(_T_2930, _T_2914) @[el2_lib.scala 259:74] - node _T_2932 = xor(_T_2931, _T_2915) @[el2_lib.scala 259:74] - node _T_2933 = xor(_T_2932, _T_2916) @[el2_lib.scala 259:74] - node _T_2934 = xor(_T_2933, _T_2917) @[el2_lib.scala 259:74] - node _T_2935 = xor(_T_2934, _T_2918) @[el2_lib.scala 259:74] - node _T_2936 = xor(_T_2935, _T_2919) @[el2_lib.scala 259:74] - node _T_2937 = xor(_T_2936, _T_2920) @[el2_lib.scala 259:74] - node _T_2938 = xor(_T_2937, _T_2921) @[el2_lib.scala 259:74] - node _T_2939 = xor(_T_2938, _T_2922) @[el2_lib.scala 259:74] - node _T_2940 = xor(_T_2939, _T_2923) @[el2_lib.scala 259:74] - node _T_2941 = xor(_T_2940, _T_2924) @[el2_lib.scala 259:74] - node _T_2942 = bits(_T_2906, 0, 0) @[el2_lib.scala 259:58] - node _T_2943 = bits(_T_2906, 2, 2) @[el2_lib.scala 259:58] - node _T_2944 = bits(_T_2906, 3, 3) @[el2_lib.scala 259:58] - node _T_2945 = bits(_T_2906, 5, 5) @[el2_lib.scala 259:58] - node _T_2946 = bits(_T_2906, 6, 6) @[el2_lib.scala 259:58] - node _T_2947 = bits(_T_2906, 9, 9) @[el2_lib.scala 259:58] - node _T_2948 = bits(_T_2906, 10, 10) @[el2_lib.scala 259:58] - node _T_2949 = bits(_T_2906, 12, 12) @[el2_lib.scala 259:58] - node _T_2950 = bits(_T_2906, 13, 13) @[el2_lib.scala 259:58] - node _T_2951 = bits(_T_2906, 16, 16) @[el2_lib.scala 259:58] - node _T_2952 = bits(_T_2906, 17, 17) @[el2_lib.scala 259:58] - node _T_2953 = bits(_T_2906, 20, 20) @[el2_lib.scala 259:58] - node _T_2954 = bits(_T_2906, 21, 21) @[el2_lib.scala 259:58] - node _T_2955 = bits(_T_2906, 24, 24) @[el2_lib.scala 259:58] - node _T_2956 = bits(_T_2906, 25, 25) @[el2_lib.scala 259:58] - node _T_2957 = bits(_T_2906, 27, 27) @[el2_lib.scala 259:58] - node _T_2958 = bits(_T_2906, 28, 28) @[el2_lib.scala 259:58] - node _T_2959 = bits(_T_2906, 31, 31) @[el2_lib.scala 259:58] - node _T_2960 = xor(_T_2942, _T_2943) @[el2_lib.scala 259:74] - node _T_2961 = xor(_T_2960, _T_2944) @[el2_lib.scala 259:74] - node _T_2962 = xor(_T_2961, _T_2945) @[el2_lib.scala 259:74] - node _T_2963 = xor(_T_2962, _T_2946) @[el2_lib.scala 259:74] - node _T_2964 = xor(_T_2963, _T_2947) @[el2_lib.scala 259:74] - node _T_2965 = xor(_T_2964, _T_2948) @[el2_lib.scala 259:74] - node _T_2966 = xor(_T_2965, _T_2949) @[el2_lib.scala 259:74] - node _T_2967 = xor(_T_2966, _T_2950) @[el2_lib.scala 259:74] - node _T_2968 = xor(_T_2967, _T_2951) @[el2_lib.scala 259:74] - node _T_2969 = xor(_T_2968, _T_2952) @[el2_lib.scala 259:74] - node _T_2970 = xor(_T_2969, _T_2953) @[el2_lib.scala 259:74] - node _T_2971 = xor(_T_2970, _T_2954) @[el2_lib.scala 259:74] - node _T_2972 = xor(_T_2971, _T_2955) @[el2_lib.scala 259:74] - node _T_2973 = xor(_T_2972, _T_2956) @[el2_lib.scala 259:74] - node _T_2974 = xor(_T_2973, _T_2957) @[el2_lib.scala 259:74] - node _T_2975 = xor(_T_2974, _T_2958) @[el2_lib.scala 259:74] - node _T_2976 = xor(_T_2975, _T_2959) @[el2_lib.scala 259:74] - node _T_2977 = bits(_T_2906, 1, 1) @[el2_lib.scala 259:58] - node _T_2978 = bits(_T_2906, 2, 2) @[el2_lib.scala 259:58] - node _T_2979 = bits(_T_2906, 3, 3) @[el2_lib.scala 259:58] - node _T_2980 = bits(_T_2906, 7, 7) @[el2_lib.scala 259:58] - node _T_2981 = bits(_T_2906, 8, 8) @[el2_lib.scala 259:58] - node _T_2982 = bits(_T_2906, 9, 9) @[el2_lib.scala 259:58] - node _T_2983 = bits(_T_2906, 10, 10) @[el2_lib.scala 259:58] - node _T_2984 = bits(_T_2906, 14, 14) @[el2_lib.scala 259:58] - node _T_2985 = bits(_T_2906, 15, 15) @[el2_lib.scala 259:58] - node _T_2986 = bits(_T_2906, 16, 16) @[el2_lib.scala 259:58] - node _T_2987 = bits(_T_2906, 17, 17) @[el2_lib.scala 259:58] - node _T_2988 = bits(_T_2906, 22, 22) @[el2_lib.scala 259:58] - node _T_2989 = bits(_T_2906, 23, 23) @[el2_lib.scala 259:58] - node _T_2990 = bits(_T_2906, 24, 24) @[el2_lib.scala 259:58] - node _T_2991 = bits(_T_2906, 25, 25) @[el2_lib.scala 259:58] - node _T_2992 = bits(_T_2906, 29, 29) @[el2_lib.scala 259:58] - node _T_2993 = bits(_T_2906, 30, 30) @[el2_lib.scala 259:58] - node _T_2994 = bits(_T_2906, 31, 31) @[el2_lib.scala 259:58] - node _T_2995 = xor(_T_2977, _T_2978) @[el2_lib.scala 259:74] - node _T_2996 = xor(_T_2995, _T_2979) @[el2_lib.scala 259:74] - node _T_2997 = xor(_T_2996, _T_2980) @[el2_lib.scala 259:74] - node _T_2998 = xor(_T_2997, _T_2981) @[el2_lib.scala 259:74] - node _T_2999 = xor(_T_2998, _T_2982) @[el2_lib.scala 259:74] - node _T_3000 = xor(_T_2999, _T_2983) @[el2_lib.scala 259:74] - node _T_3001 = xor(_T_3000, _T_2984) @[el2_lib.scala 259:74] - node _T_3002 = xor(_T_3001, _T_2985) @[el2_lib.scala 259:74] - node _T_3003 = xor(_T_3002, _T_2986) @[el2_lib.scala 259:74] - node _T_3004 = xor(_T_3003, _T_2987) @[el2_lib.scala 259:74] - node _T_3005 = xor(_T_3004, _T_2988) @[el2_lib.scala 259:74] - node _T_3006 = xor(_T_3005, _T_2989) @[el2_lib.scala 259:74] - node _T_3007 = xor(_T_3006, _T_2990) @[el2_lib.scala 259:74] - node _T_3008 = xor(_T_3007, _T_2991) @[el2_lib.scala 259:74] - node _T_3009 = xor(_T_3008, _T_2992) @[el2_lib.scala 259:74] - node _T_3010 = xor(_T_3009, _T_2993) @[el2_lib.scala 259:74] - node _T_3011 = xor(_T_3010, _T_2994) @[el2_lib.scala 259:74] - node _T_3012 = bits(_T_2906, 4, 4) @[el2_lib.scala 259:58] - node _T_3013 = bits(_T_2906, 5, 5) @[el2_lib.scala 259:58] - node _T_3014 = bits(_T_2906, 6, 6) @[el2_lib.scala 259:58] - node _T_3015 = bits(_T_2906, 7, 7) @[el2_lib.scala 259:58] - node _T_3016 = bits(_T_2906, 8, 8) @[el2_lib.scala 259:58] - node _T_3017 = bits(_T_2906, 9, 9) @[el2_lib.scala 259:58] - node _T_3018 = bits(_T_2906, 10, 10) @[el2_lib.scala 259:58] - node _T_3019 = bits(_T_2906, 18, 18) @[el2_lib.scala 259:58] - node _T_3020 = bits(_T_2906, 19, 19) @[el2_lib.scala 259:58] - node _T_3021 = bits(_T_2906, 20, 20) @[el2_lib.scala 259:58] - node _T_3022 = bits(_T_2906, 21, 21) @[el2_lib.scala 259:58] - node _T_3023 = bits(_T_2906, 22, 22) @[el2_lib.scala 259:58] - node _T_3024 = bits(_T_2906, 23, 23) @[el2_lib.scala 259:58] - node _T_3025 = bits(_T_2906, 24, 24) @[el2_lib.scala 259:58] - node _T_3026 = bits(_T_2906, 25, 25) @[el2_lib.scala 259:58] - node _T_3027 = xor(_T_3012, _T_3013) @[el2_lib.scala 259:74] - node _T_3028 = xor(_T_3027, _T_3014) @[el2_lib.scala 259:74] - node _T_3029 = xor(_T_3028, _T_3015) @[el2_lib.scala 259:74] - node _T_3030 = xor(_T_3029, _T_3016) @[el2_lib.scala 259:74] - node _T_3031 = xor(_T_3030, _T_3017) @[el2_lib.scala 259:74] - node _T_3032 = xor(_T_3031, _T_3018) @[el2_lib.scala 259:74] - node _T_3033 = xor(_T_3032, _T_3019) @[el2_lib.scala 259:74] - node _T_3034 = xor(_T_3033, _T_3020) @[el2_lib.scala 259:74] - node _T_3035 = xor(_T_3034, _T_3021) @[el2_lib.scala 259:74] - node _T_3036 = xor(_T_3035, _T_3022) @[el2_lib.scala 259:74] - node _T_3037 = xor(_T_3036, _T_3023) @[el2_lib.scala 259:74] - node _T_3038 = xor(_T_3037, _T_3024) @[el2_lib.scala 259:74] - node _T_3039 = xor(_T_3038, _T_3025) @[el2_lib.scala 259:74] - node _T_3040 = xor(_T_3039, _T_3026) @[el2_lib.scala 259:74] - node _T_3041 = bits(_T_2906, 11, 11) @[el2_lib.scala 259:58] - node _T_3042 = bits(_T_2906, 12, 12) @[el2_lib.scala 259:58] - node _T_3043 = bits(_T_2906, 13, 13) @[el2_lib.scala 259:58] - node _T_3044 = bits(_T_2906, 14, 14) @[el2_lib.scala 259:58] - node _T_3045 = bits(_T_2906, 15, 15) @[el2_lib.scala 259:58] - node _T_3046 = bits(_T_2906, 16, 16) @[el2_lib.scala 259:58] - node _T_3047 = bits(_T_2906, 17, 17) @[el2_lib.scala 259:58] - node _T_3048 = bits(_T_2906, 18, 18) @[el2_lib.scala 259:58] - node _T_3049 = bits(_T_2906, 19, 19) @[el2_lib.scala 259:58] - node _T_3050 = bits(_T_2906, 20, 20) @[el2_lib.scala 259:58] - node _T_3051 = bits(_T_2906, 21, 21) @[el2_lib.scala 259:58] - node _T_3052 = bits(_T_2906, 22, 22) @[el2_lib.scala 259:58] - node _T_3053 = bits(_T_2906, 23, 23) @[el2_lib.scala 259:58] - node _T_3054 = bits(_T_2906, 24, 24) @[el2_lib.scala 259:58] - node _T_3055 = bits(_T_2906, 25, 25) @[el2_lib.scala 259:58] - node _T_3056 = xor(_T_3041, _T_3042) @[el2_lib.scala 259:74] - node _T_3057 = xor(_T_3056, _T_3043) @[el2_lib.scala 259:74] - node _T_3058 = xor(_T_3057, _T_3044) @[el2_lib.scala 259:74] - node _T_3059 = xor(_T_3058, _T_3045) @[el2_lib.scala 259:74] - node _T_3060 = xor(_T_3059, _T_3046) @[el2_lib.scala 259:74] - node _T_3061 = xor(_T_3060, _T_3047) @[el2_lib.scala 259:74] - node _T_3062 = xor(_T_3061, _T_3048) @[el2_lib.scala 259:74] - node _T_3063 = xor(_T_3062, _T_3049) @[el2_lib.scala 259:74] - node _T_3064 = xor(_T_3063, _T_3050) @[el2_lib.scala 259:74] - node _T_3065 = xor(_T_3064, _T_3051) @[el2_lib.scala 259:74] - node _T_3066 = xor(_T_3065, _T_3052) @[el2_lib.scala 259:74] - node _T_3067 = xor(_T_3066, _T_3053) @[el2_lib.scala 259:74] - node _T_3068 = xor(_T_3067, _T_3054) @[el2_lib.scala 259:74] - node _T_3069 = xor(_T_3068, _T_3055) @[el2_lib.scala 259:74] - node _T_3070 = bits(_T_2906, 26, 26) @[el2_lib.scala 259:58] - node _T_3071 = bits(_T_2906, 27, 27) @[el2_lib.scala 259:58] - node _T_3072 = bits(_T_2906, 28, 28) @[el2_lib.scala 259:58] - node _T_3073 = bits(_T_2906, 29, 29) @[el2_lib.scala 259:58] - node _T_3074 = bits(_T_2906, 30, 30) @[el2_lib.scala 259:58] - node _T_3075 = bits(_T_2906, 31, 31) @[el2_lib.scala 259:58] - node _T_3076 = xor(_T_3070, _T_3071) @[el2_lib.scala 259:74] - node _T_3077 = xor(_T_3076, _T_3072) @[el2_lib.scala 259:74] - node _T_3078 = xor(_T_3077, _T_3073) @[el2_lib.scala 259:74] - node _T_3079 = xor(_T_3078, _T_3074) @[el2_lib.scala 259:74] - node _T_3080 = xor(_T_3079, _T_3075) @[el2_lib.scala 259:74] + node _T_2907 = bits(_T_2906, 0, 0) @[lib.scala 119:58] + node _T_2908 = bits(_T_2906, 1, 1) @[lib.scala 119:58] + node _T_2909 = bits(_T_2906, 3, 3) @[lib.scala 119:58] + node _T_2910 = bits(_T_2906, 4, 4) @[lib.scala 119:58] + node _T_2911 = bits(_T_2906, 6, 6) @[lib.scala 119:58] + node _T_2912 = bits(_T_2906, 8, 8) @[lib.scala 119:58] + node _T_2913 = bits(_T_2906, 10, 10) @[lib.scala 119:58] + node _T_2914 = bits(_T_2906, 11, 11) @[lib.scala 119:58] + node _T_2915 = bits(_T_2906, 13, 13) @[lib.scala 119:58] + node _T_2916 = bits(_T_2906, 15, 15) @[lib.scala 119:58] + node _T_2917 = bits(_T_2906, 17, 17) @[lib.scala 119:58] + node _T_2918 = bits(_T_2906, 19, 19) @[lib.scala 119:58] + node _T_2919 = bits(_T_2906, 21, 21) @[lib.scala 119:58] + node _T_2920 = bits(_T_2906, 23, 23) @[lib.scala 119:58] + node _T_2921 = bits(_T_2906, 25, 25) @[lib.scala 119:58] + node _T_2922 = bits(_T_2906, 26, 26) @[lib.scala 119:58] + node _T_2923 = bits(_T_2906, 28, 28) @[lib.scala 119:58] + node _T_2924 = bits(_T_2906, 30, 30) @[lib.scala 119:58] + node _T_2925 = xor(_T_2907, _T_2908) @[lib.scala 119:74] + node _T_2926 = xor(_T_2925, _T_2909) @[lib.scala 119:74] + node _T_2927 = xor(_T_2926, _T_2910) @[lib.scala 119:74] + node _T_2928 = xor(_T_2927, _T_2911) @[lib.scala 119:74] + node _T_2929 = xor(_T_2928, _T_2912) @[lib.scala 119:74] + node _T_2930 = xor(_T_2929, _T_2913) @[lib.scala 119:74] + node _T_2931 = xor(_T_2930, _T_2914) @[lib.scala 119:74] + node _T_2932 = xor(_T_2931, _T_2915) @[lib.scala 119:74] + node _T_2933 = xor(_T_2932, _T_2916) @[lib.scala 119:74] + node _T_2934 = xor(_T_2933, _T_2917) @[lib.scala 119:74] + node _T_2935 = xor(_T_2934, _T_2918) @[lib.scala 119:74] + node _T_2936 = xor(_T_2935, _T_2919) @[lib.scala 119:74] + node _T_2937 = xor(_T_2936, _T_2920) @[lib.scala 119:74] + node _T_2938 = xor(_T_2937, _T_2921) @[lib.scala 119:74] + node _T_2939 = xor(_T_2938, _T_2922) @[lib.scala 119:74] + node _T_2940 = xor(_T_2939, _T_2923) @[lib.scala 119:74] + node _T_2941 = xor(_T_2940, _T_2924) @[lib.scala 119:74] + node _T_2942 = bits(_T_2906, 0, 0) @[lib.scala 119:58] + node _T_2943 = bits(_T_2906, 2, 2) @[lib.scala 119:58] + node _T_2944 = bits(_T_2906, 3, 3) @[lib.scala 119:58] + node _T_2945 = bits(_T_2906, 5, 5) @[lib.scala 119:58] + node _T_2946 = bits(_T_2906, 6, 6) @[lib.scala 119:58] + node _T_2947 = bits(_T_2906, 9, 9) @[lib.scala 119:58] + node _T_2948 = bits(_T_2906, 10, 10) @[lib.scala 119:58] + node _T_2949 = bits(_T_2906, 12, 12) @[lib.scala 119:58] + node _T_2950 = bits(_T_2906, 13, 13) @[lib.scala 119:58] + node _T_2951 = bits(_T_2906, 16, 16) @[lib.scala 119:58] + node _T_2952 = bits(_T_2906, 17, 17) @[lib.scala 119:58] + node _T_2953 = bits(_T_2906, 20, 20) @[lib.scala 119:58] + node _T_2954 = bits(_T_2906, 21, 21) @[lib.scala 119:58] + node _T_2955 = bits(_T_2906, 24, 24) @[lib.scala 119:58] + node _T_2956 = bits(_T_2906, 25, 25) @[lib.scala 119:58] + node _T_2957 = bits(_T_2906, 27, 27) @[lib.scala 119:58] + node _T_2958 = bits(_T_2906, 28, 28) @[lib.scala 119:58] + node _T_2959 = bits(_T_2906, 31, 31) @[lib.scala 119:58] + node _T_2960 = xor(_T_2942, _T_2943) @[lib.scala 119:74] + node _T_2961 = xor(_T_2960, _T_2944) @[lib.scala 119:74] + node _T_2962 = xor(_T_2961, _T_2945) @[lib.scala 119:74] + node _T_2963 = xor(_T_2962, _T_2946) @[lib.scala 119:74] + node _T_2964 = xor(_T_2963, _T_2947) @[lib.scala 119:74] + node _T_2965 = xor(_T_2964, _T_2948) @[lib.scala 119:74] + node _T_2966 = xor(_T_2965, _T_2949) @[lib.scala 119:74] + node _T_2967 = xor(_T_2966, _T_2950) @[lib.scala 119:74] + node _T_2968 = xor(_T_2967, _T_2951) @[lib.scala 119:74] + node _T_2969 = xor(_T_2968, _T_2952) @[lib.scala 119:74] + node _T_2970 = xor(_T_2969, _T_2953) @[lib.scala 119:74] + node _T_2971 = xor(_T_2970, _T_2954) @[lib.scala 119:74] + node _T_2972 = xor(_T_2971, _T_2955) @[lib.scala 119:74] + node _T_2973 = xor(_T_2972, _T_2956) @[lib.scala 119:74] + node _T_2974 = xor(_T_2973, _T_2957) @[lib.scala 119:74] + node _T_2975 = xor(_T_2974, _T_2958) @[lib.scala 119:74] + node _T_2976 = xor(_T_2975, _T_2959) @[lib.scala 119:74] + node _T_2977 = bits(_T_2906, 1, 1) @[lib.scala 119:58] + node _T_2978 = bits(_T_2906, 2, 2) @[lib.scala 119:58] + node _T_2979 = bits(_T_2906, 3, 3) @[lib.scala 119:58] + node _T_2980 = bits(_T_2906, 7, 7) @[lib.scala 119:58] + node _T_2981 = bits(_T_2906, 8, 8) @[lib.scala 119:58] + node _T_2982 = bits(_T_2906, 9, 9) @[lib.scala 119:58] + node _T_2983 = bits(_T_2906, 10, 10) @[lib.scala 119:58] + node _T_2984 = bits(_T_2906, 14, 14) @[lib.scala 119:58] + node _T_2985 = bits(_T_2906, 15, 15) @[lib.scala 119:58] + node _T_2986 = bits(_T_2906, 16, 16) @[lib.scala 119:58] + node _T_2987 = bits(_T_2906, 17, 17) @[lib.scala 119:58] + node _T_2988 = bits(_T_2906, 22, 22) @[lib.scala 119:58] + node _T_2989 = bits(_T_2906, 23, 23) @[lib.scala 119:58] + node _T_2990 = bits(_T_2906, 24, 24) @[lib.scala 119:58] + node _T_2991 = bits(_T_2906, 25, 25) @[lib.scala 119:58] + node _T_2992 = bits(_T_2906, 29, 29) @[lib.scala 119:58] + node _T_2993 = bits(_T_2906, 30, 30) @[lib.scala 119:58] + node _T_2994 = bits(_T_2906, 31, 31) @[lib.scala 119:58] + node _T_2995 = xor(_T_2977, _T_2978) @[lib.scala 119:74] + node _T_2996 = xor(_T_2995, _T_2979) @[lib.scala 119:74] + node _T_2997 = xor(_T_2996, _T_2980) @[lib.scala 119:74] + node _T_2998 = xor(_T_2997, _T_2981) @[lib.scala 119:74] + node _T_2999 = xor(_T_2998, _T_2982) @[lib.scala 119:74] + node _T_3000 = xor(_T_2999, _T_2983) @[lib.scala 119:74] + node _T_3001 = xor(_T_3000, _T_2984) @[lib.scala 119:74] + node _T_3002 = xor(_T_3001, _T_2985) @[lib.scala 119:74] + node _T_3003 = xor(_T_3002, _T_2986) @[lib.scala 119:74] + node _T_3004 = xor(_T_3003, _T_2987) @[lib.scala 119:74] + node _T_3005 = xor(_T_3004, _T_2988) @[lib.scala 119:74] + node _T_3006 = xor(_T_3005, _T_2989) @[lib.scala 119:74] + node _T_3007 = xor(_T_3006, _T_2990) @[lib.scala 119:74] + node _T_3008 = xor(_T_3007, _T_2991) @[lib.scala 119:74] + node _T_3009 = xor(_T_3008, _T_2992) @[lib.scala 119:74] + node _T_3010 = xor(_T_3009, _T_2993) @[lib.scala 119:74] + node _T_3011 = xor(_T_3010, _T_2994) @[lib.scala 119:74] + node _T_3012 = bits(_T_2906, 4, 4) @[lib.scala 119:58] + node _T_3013 = bits(_T_2906, 5, 5) @[lib.scala 119:58] + node _T_3014 = bits(_T_2906, 6, 6) @[lib.scala 119:58] + node _T_3015 = bits(_T_2906, 7, 7) @[lib.scala 119:58] + node _T_3016 = bits(_T_2906, 8, 8) @[lib.scala 119:58] + node _T_3017 = bits(_T_2906, 9, 9) @[lib.scala 119:58] + node _T_3018 = bits(_T_2906, 10, 10) @[lib.scala 119:58] + node _T_3019 = bits(_T_2906, 18, 18) @[lib.scala 119:58] + node _T_3020 = bits(_T_2906, 19, 19) @[lib.scala 119:58] + node _T_3021 = bits(_T_2906, 20, 20) @[lib.scala 119:58] + node _T_3022 = bits(_T_2906, 21, 21) @[lib.scala 119:58] + node _T_3023 = bits(_T_2906, 22, 22) @[lib.scala 119:58] + node _T_3024 = bits(_T_2906, 23, 23) @[lib.scala 119:58] + node _T_3025 = bits(_T_2906, 24, 24) @[lib.scala 119:58] + node _T_3026 = bits(_T_2906, 25, 25) @[lib.scala 119:58] + node _T_3027 = xor(_T_3012, _T_3013) @[lib.scala 119:74] + node _T_3028 = xor(_T_3027, _T_3014) @[lib.scala 119:74] + node _T_3029 = xor(_T_3028, _T_3015) @[lib.scala 119:74] + node _T_3030 = xor(_T_3029, _T_3016) @[lib.scala 119:74] + node _T_3031 = xor(_T_3030, _T_3017) @[lib.scala 119:74] + node _T_3032 = xor(_T_3031, _T_3018) @[lib.scala 119:74] + node _T_3033 = xor(_T_3032, _T_3019) @[lib.scala 119:74] + node _T_3034 = xor(_T_3033, _T_3020) @[lib.scala 119:74] + node _T_3035 = xor(_T_3034, _T_3021) @[lib.scala 119:74] + node _T_3036 = xor(_T_3035, _T_3022) @[lib.scala 119:74] + node _T_3037 = xor(_T_3036, _T_3023) @[lib.scala 119:74] + node _T_3038 = xor(_T_3037, _T_3024) @[lib.scala 119:74] + node _T_3039 = xor(_T_3038, _T_3025) @[lib.scala 119:74] + node _T_3040 = xor(_T_3039, _T_3026) @[lib.scala 119:74] + node _T_3041 = bits(_T_2906, 11, 11) @[lib.scala 119:58] + node _T_3042 = bits(_T_2906, 12, 12) @[lib.scala 119:58] + node _T_3043 = bits(_T_2906, 13, 13) @[lib.scala 119:58] + node _T_3044 = bits(_T_2906, 14, 14) @[lib.scala 119:58] + node _T_3045 = bits(_T_2906, 15, 15) @[lib.scala 119:58] + node _T_3046 = bits(_T_2906, 16, 16) @[lib.scala 119:58] + node _T_3047 = bits(_T_2906, 17, 17) @[lib.scala 119:58] + node _T_3048 = bits(_T_2906, 18, 18) @[lib.scala 119:58] + node _T_3049 = bits(_T_2906, 19, 19) @[lib.scala 119:58] + node _T_3050 = bits(_T_2906, 20, 20) @[lib.scala 119:58] + node _T_3051 = bits(_T_2906, 21, 21) @[lib.scala 119:58] + node _T_3052 = bits(_T_2906, 22, 22) @[lib.scala 119:58] + node _T_3053 = bits(_T_2906, 23, 23) @[lib.scala 119:58] + node _T_3054 = bits(_T_2906, 24, 24) @[lib.scala 119:58] + node _T_3055 = bits(_T_2906, 25, 25) @[lib.scala 119:58] + node _T_3056 = xor(_T_3041, _T_3042) @[lib.scala 119:74] + node _T_3057 = xor(_T_3056, _T_3043) @[lib.scala 119:74] + node _T_3058 = xor(_T_3057, _T_3044) @[lib.scala 119:74] + node _T_3059 = xor(_T_3058, _T_3045) @[lib.scala 119:74] + node _T_3060 = xor(_T_3059, _T_3046) @[lib.scala 119:74] + node _T_3061 = xor(_T_3060, _T_3047) @[lib.scala 119:74] + node _T_3062 = xor(_T_3061, _T_3048) @[lib.scala 119:74] + node _T_3063 = xor(_T_3062, _T_3049) @[lib.scala 119:74] + node _T_3064 = xor(_T_3063, _T_3050) @[lib.scala 119:74] + node _T_3065 = xor(_T_3064, _T_3051) @[lib.scala 119:74] + node _T_3066 = xor(_T_3065, _T_3052) @[lib.scala 119:74] + node _T_3067 = xor(_T_3066, _T_3053) @[lib.scala 119:74] + node _T_3068 = xor(_T_3067, _T_3054) @[lib.scala 119:74] + node _T_3069 = xor(_T_3068, _T_3055) @[lib.scala 119:74] + node _T_3070 = bits(_T_2906, 26, 26) @[lib.scala 119:58] + node _T_3071 = bits(_T_2906, 27, 27) @[lib.scala 119:58] + node _T_3072 = bits(_T_2906, 28, 28) @[lib.scala 119:58] + node _T_3073 = bits(_T_2906, 29, 29) @[lib.scala 119:58] + node _T_3074 = bits(_T_2906, 30, 30) @[lib.scala 119:58] + node _T_3075 = bits(_T_2906, 31, 31) @[lib.scala 119:58] + node _T_3076 = xor(_T_3070, _T_3071) @[lib.scala 119:74] + node _T_3077 = xor(_T_3076, _T_3072) @[lib.scala 119:74] + node _T_3078 = xor(_T_3077, _T_3073) @[lib.scala 119:74] + node _T_3079 = xor(_T_3078, _T_3074) @[lib.scala 119:74] + node _T_3080 = xor(_T_3079, _T_3075) @[lib.scala 119:74] node _T_3081 = cat(_T_3011, _T_2976) @[Cat.scala 29:58] node _T_3082 = cat(_T_3081, _T_2941) @[Cat.scala 29:58] node _T_3083 = cat(_T_3080, _T_3069) @[Cat.scala 29:58] node _T_3084 = cat(_T_3083, _T_3040) @[Cat.scala 29:58] node _T_3085 = cat(_T_3084, _T_3082) @[Cat.scala 29:58] - node _T_3086 = xorr(_T_2906) @[el2_lib.scala 267:13] - node _T_3087 = xorr(_T_3085) @[el2_lib.scala 267:23] - node _T_3088 = xor(_T_3086, _T_3087) @[el2_lib.scala 267:18] + node _T_3086 = xorr(_T_2906) @[lib.scala 127:13] + node _T_3087 = xorr(_T_3085) @[lib.scala 127:23] + node _T_3088 = xor(_T_3086, _T_3087) @[lib.scala 127:18] node _T_3089 = cat(_T_3088, _T_3085) @[Cat.scala 29:58] node dma_mem_ecc = cat(_T_2905, _T_3089) @[Cat.scala 29:58] wire iccm_ecc_corr_data_ff : UInt<39> @@ -6973,443 +6973,443 @@ circuit quasar_wrapper : node _T_3136 = bits(iccm_ecc_word_enable, 0, 0) @[ifu_mem_ctl.scala 606:73] node _T_3137 = bits(io.iccm.rd_data_ecc, 31, 0) @[ifu_mem_ctl.scala 606:93] node _T_3138 = bits(io.iccm.rd_data_ecc, 38, 32) @[ifu_mem_ctl.scala 606:128] - wire _T_3139 : UInt<1>[18] @[el2_lib.scala 313:18] - wire _T_3140 : UInt<1>[18] @[el2_lib.scala 314:18] - wire _T_3141 : UInt<1>[18] @[el2_lib.scala 315:18] - wire _T_3142 : UInt<1>[15] @[el2_lib.scala 316:18] - wire _T_3143 : UInt<1>[15] @[el2_lib.scala 317:18] - wire _T_3144 : UInt<1>[6] @[el2_lib.scala 318:18] - node _T_3145 = bits(_T_3137, 0, 0) @[el2_lib.scala 325:36] - _T_3139[0] <= _T_3145 @[el2_lib.scala 325:30] - node _T_3146 = bits(_T_3137, 0, 0) @[el2_lib.scala 326:36] - _T_3140[0] <= _T_3146 @[el2_lib.scala 326:30] - node _T_3147 = bits(_T_3137, 1, 1) @[el2_lib.scala 325:36] - _T_3139[1] <= _T_3147 @[el2_lib.scala 325:30] - node _T_3148 = bits(_T_3137, 1, 1) @[el2_lib.scala 327:36] - _T_3141[0] <= _T_3148 @[el2_lib.scala 327:30] - node _T_3149 = bits(_T_3137, 2, 2) @[el2_lib.scala 326:36] - _T_3140[1] <= _T_3149 @[el2_lib.scala 326:30] - node _T_3150 = bits(_T_3137, 2, 2) @[el2_lib.scala 327:36] - _T_3141[1] <= _T_3150 @[el2_lib.scala 327:30] - node _T_3151 = bits(_T_3137, 3, 3) @[el2_lib.scala 325:36] - _T_3139[2] <= _T_3151 @[el2_lib.scala 325:30] - node _T_3152 = bits(_T_3137, 3, 3) @[el2_lib.scala 326:36] - _T_3140[2] <= _T_3152 @[el2_lib.scala 326:30] - node _T_3153 = bits(_T_3137, 3, 3) @[el2_lib.scala 327:36] - _T_3141[2] <= _T_3153 @[el2_lib.scala 327:30] - node _T_3154 = bits(_T_3137, 4, 4) @[el2_lib.scala 325:36] - _T_3139[3] <= _T_3154 @[el2_lib.scala 325:30] - node _T_3155 = bits(_T_3137, 4, 4) @[el2_lib.scala 328:36] - _T_3142[0] <= _T_3155 @[el2_lib.scala 328:30] - node _T_3156 = bits(_T_3137, 5, 5) @[el2_lib.scala 326:36] - _T_3140[3] <= _T_3156 @[el2_lib.scala 326:30] - node _T_3157 = bits(_T_3137, 5, 5) @[el2_lib.scala 328:36] - _T_3142[1] <= _T_3157 @[el2_lib.scala 328:30] - node _T_3158 = bits(_T_3137, 6, 6) @[el2_lib.scala 325:36] - _T_3139[4] <= _T_3158 @[el2_lib.scala 325:30] - node _T_3159 = bits(_T_3137, 6, 6) @[el2_lib.scala 326:36] - _T_3140[4] <= _T_3159 @[el2_lib.scala 326:30] - node _T_3160 = bits(_T_3137, 6, 6) @[el2_lib.scala 328:36] - _T_3142[2] <= _T_3160 @[el2_lib.scala 328:30] - node _T_3161 = bits(_T_3137, 7, 7) @[el2_lib.scala 327:36] - _T_3141[3] <= _T_3161 @[el2_lib.scala 327:30] - node _T_3162 = bits(_T_3137, 7, 7) @[el2_lib.scala 328:36] - _T_3142[3] <= _T_3162 @[el2_lib.scala 328:30] - node _T_3163 = bits(_T_3137, 8, 8) @[el2_lib.scala 325:36] - _T_3139[5] <= _T_3163 @[el2_lib.scala 325:30] - node _T_3164 = bits(_T_3137, 8, 8) @[el2_lib.scala 327:36] - _T_3141[4] <= _T_3164 @[el2_lib.scala 327:30] - node _T_3165 = bits(_T_3137, 8, 8) @[el2_lib.scala 328:36] - _T_3142[4] <= _T_3165 @[el2_lib.scala 328:30] - node _T_3166 = bits(_T_3137, 9, 9) @[el2_lib.scala 326:36] - _T_3140[5] <= _T_3166 @[el2_lib.scala 326:30] - node _T_3167 = bits(_T_3137, 9, 9) @[el2_lib.scala 327:36] - _T_3141[5] <= _T_3167 @[el2_lib.scala 327:30] - node _T_3168 = bits(_T_3137, 9, 9) @[el2_lib.scala 328:36] - _T_3142[5] <= _T_3168 @[el2_lib.scala 328:30] - node _T_3169 = bits(_T_3137, 10, 10) @[el2_lib.scala 325:36] - _T_3139[6] <= _T_3169 @[el2_lib.scala 325:30] - node _T_3170 = bits(_T_3137, 10, 10) @[el2_lib.scala 326:36] - _T_3140[6] <= _T_3170 @[el2_lib.scala 326:30] - node _T_3171 = bits(_T_3137, 10, 10) @[el2_lib.scala 327:36] - _T_3141[6] <= _T_3171 @[el2_lib.scala 327:30] - node _T_3172 = bits(_T_3137, 10, 10) @[el2_lib.scala 328:36] - _T_3142[6] <= _T_3172 @[el2_lib.scala 328:30] - node _T_3173 = bits(_T_3137, 11, 11) @[el2_lib.scala 325:36] - _T_3139[7] <= _T_3173 @[el2_lib.scala 325:30] - node _T_3174 = bits(_T_3137, 11, 11) @[el2_lib.scala 329:36] - _T_3143[0] <= _T_3174 @[el2_lib.scala 329:30] - node _T_3175 = bits(_T_3137, 12, 12) @[el2_lib.scala 326:36] - _T_3140[7] <= _T_3175 @[el2_lib.scala 326:30] - node _T_3176 = bits(_T_3137, 12, 12) @[el2_lib.scala 329:36] - _T_3143[1] <= _T_3176 @[el2_lib.scala 329:30] - node _T_3177 = bits(_T_3137, 13, 13) @[el2_lib.scala 325:36] - _T_3139[8] <= _T_3177 @[el2_lib.scala 325:30] - node _T_3178 = bits(_T_3137, 13, 13) @[el2_lib.scala 326:36] - _T_3140[8] <= _T_3178 @[el2_lib.scala 326:30] - node _T_3179 = bits(_T_3137, 13, 13) @[el2_lib.scala 329:36] - _T_3143[2] <= _T_3179 @[el2_lib.scala 329:30] - node _T_3180 = bits(_T_3137, 14, 14) @[el2_lib.scala 327:36] - _T_3141[7] <= _T_3180 @[el2_lib.scala 327:30] - node _T_3181 = bits(_T_3137, 14, 14) @[el2_lib.scala 329:36] - _T_3143[3] <= _T_3181 @[el2_lib.scala 329:30] - node _T_3182 = bits(_T_3137, 15, 15) @[el2_lib.scala 325:36] - _T_3139[9] <= _T_3182 @[el2_lib.scala 325:30] - node _T_3183 = bits(_T_3137, 15, 15) @[el2_lib.scala 327:36] - _T_3141[8] <= _T_3183 @[el2_lib.scala 327:30] - node _T_3184 = bits(_T_3137, 15, 15) @[el2_lib.scala 329:36] - _T_3143[4] <= _T_3184 @[el2_lib.scala 329:30] - node _T_3185 = bits(_T_3137, 16, 16) @[el2_lib.scala 326:36] - _T_3140[9] <= _T_3185 @[el2_lib.scala 326:30] - node _T_3186 = bits(_T_3137, 16, 16) @[el2_lib.scala 327:36] - _T_3141[9] <= _T_3186 @[el2_lib.scala 327:30] - node _T_3187 = bits(_T_3137, 16, 16) @[el2_lib.scala 329:36] - _T_3143[5] <= _T_3187 @[el2_lib.scala 329:30] - node _T_3188 = bits(_T_3137, 17, 17) @[el2_lib.scala 325:36] - _T_3139[10] <= _T_3188 @[el2_lib.scala 325:30] - node _T_3189 = bits(_T_3137, 17, 17) @[el2_lib.scala 326:36] - _T_3140[10] <= _T_3189 @[el2_lib.scala 326:30] - node _T_3190 = bits(_T_3137, 17, 17) @[el2_lib.scala 327:36] - _T_3141[10] <= _T_3190 @[el2_lib.scala 327:30] - node _T_3191 = bits(_T_3137, 17, 17) @[el2_lib.scala 329:36] - _T_3143[6] <= _T_3191 @[el2_lib.scala 329:30] - node _T_3192 = bits(_T_3137, 18, 18) @[el2_lib.scala 328:36] - _T_3142[7] <= _T_3192 @[el2_lib.scala 328:30] - node _T_3193 = bits(_T_3137, 18, 18) @[el2_lib.scala 329:36] - _T_3143[7] <= _T_3193 @[el2_lib.scala 329:30] - node _T_3194 = bits(_T_3137, 19, 19) @[el2_lib.scala 325:36] - _T_3139[11] <= _T_3194 @[el2_lib.scala 325:30] - node _T_3195 = bits(_T_3137, 19, 19) @[el2_lib.scala 328:36] - _T_3142[8] <= _T_3195 @[el2_lib.scala 328:30] - node _T_3196 = bits(_T_3137, 19, 19) @[el2_lib.scala 329:36] - _T_3143[8] <= _T_3196 @[el2_lib.scala 329:30] - node _T_3197 = bits(_T_3137, 20, 20) @[el2_lib.scala 326:36] - _T_3140[11] <= _T_3197 @[el2_lib.scala 326:30] - node _T_3198 = bits(_T_3137, 20, 20) @[el2_lib.scala 328:36] - _T_3142[9] <= _T_3198 @[el2_lib.scala 328:30] - node _T_3199 = bits(_T_3137, 20, 20) @[el2_lib.scala 329:36] - _T_3143[9] <= _T_3199 @[el2_lib.scala 329:30] - node _T_3200 = bits(_T_3137, 21, 21) @[el2_lib.scala 325:36] - _T_3139[12] <= _T_3200 @[el2_lib.scala 325:30] - node _T_3201 = bits(_T_3137, 21, 21) @[el2_lib.scala 326:36] - _T_3140[12] <= _T_3201 @[el2_lib.scala 326:30] - node _T_3202 = bits(_T_3137, 21, 21) @[el2_lib.scala 328:36] - _T_3142[10] <= _T_3202 @[el2_lib.scala 328:30] - node _T_3203 = bits(_T_3137, 21, 21) @[el2_lib.scala 329:36] - _T_3143[10] <= _T_3203 @[el2_lib.scala 329:30] - node _T_3204 = bits(_T_3137, 22, 22) @[el2_lib.scala 327:36] - _T_3141[11] <= _T_3204 @[el2_lib.scala 327:30] - node _T_3205 = bits(_T_3137, 22, 22) @[el2_lib.scala 328:36] - _T_3142[11] <= _T_3205 @[el2_lib.scala 328:30] - node _T_3206 = bits(_T_3137, 22, 22) @[el2_lib.scala 329:36] - _T_3143[11] <= _T_3206 @[el2_lib.scala 329:30] - node _T_3207 = bits(_T_3137, 23, 23) @[el2_lib.scala 325:36] - _T_3139[13] <= _T_3207 @[el2_lib.scala 325:30] - node _T_3208 = bits(_T_3137, 23, 23) @[el2_lib.scala 327:36] - _T_3141[12] <= _T_3208 @[el2_lib.scala 327:30] - node _T_3209 = bits(_T_3137, 23, 23) @[el2_lib.scala 328:36] - _T_3142[12] <= _T_3209 @[el2_lib.scala 328:30] - node _T_3210 = bits(_T_3137, 23, 23) @[el2_lib.scala 329:36] - _T_3143[12] <= _T_3210 @[el2_lib.scala 329:30] - node _T_3211 = bits(_T_3137, 24, 24) @[el2_lib.scala 326:36] - _T_3140[13] <= _T_3211 @[el2_lib.scala 326:30] - node _T_3212 = bits(_T_3137, 24, 24) @[el2_lib.scala 327:36] - _T_3141[13] <= _T_3212 @[el2_lib.scala 327:30] - node _T_3213 = bits(_T_3137, 24, 24) @[el2_lib.scala 328:36] - _T_3142[13] <= _T_3213 @[el2_lib.scala 328:30] - node _T_3214 = bits(_T_3137, 24, 24) @[el2_lib.scala 329:36] - _T_3143[13] <= _T_3214 @[el2_lib.scala 329:30] - node _T_3215 = bits(_T_3137, 25, 25) @[el2_lib.scala 325:36] - _T_3139[14] <= _T_3215 @[el2_lib.scala 325:30] - node _T_3216 = bits(_T_3137, 25, 25) @[el2_lib.scala 326:36] - _T_3140[14] <= _T_3216 @[el2_lib.scala 326:30] - node _T_3217 = bits(_T_3137, 25, 25) @[el2_lib.scala 327:36] - _T_3141[14] <= _T_3217 @[el2_lib.scala 327:30] - node _T_3218 = bits(_T_3137, 25, 25) @[el2_lib.scala 328:36] - _T_3142[14] <= _T_3218 @[el2_lib.scala 328:30] - node _T_3219 = bits(_T_3137, 25, 25) @[el2_lib.scala 329:36] - _T_3143[14] <= _T_3219 @[el2_lib.scala 329:30] - node _T_3220 = bits(_T_3137, 26, 26) @[el2_lib.scala 325:36] - _T_3139[15] <= _T_3220 @[el2_lib.scala 325:30] - node _T_3221 = bits(_T_3137, 26, 26) @[el2_lib.scala 330:36] - _T_3144[0] <= _T_3221 @[el2_lib.scala 330:30] - node _T_3222 = bits(_T_3137, 27, 27) @[el2_lib.scala 326:36] - _T_3140[15] <= _T_3222 @[el2_lib.scala 326:30] - node _T_3223 = bits(_T_3137, 27, 27) @[el2_lib.scala 330:36] - _T_3144[1] <= _T_3223 @[el2_lib.scala 330:30] - node _T_3224 = bits(_T_3137, 28, 28) @[el2_lib.scala 325:36] - _T_3139[16] <= _T_3224 @[el2_lib.scala 325:30] - node _T_3225 = bits(_T_3137, 28, 28) @[el2_lib.scala 326:36] - _T_3140[16] <= _T_3225 @[el2_lib.scala 326:30] - node _T_3226 = bits(_T_3137, 28, 28) @[el2_lib.scala 330:36] - _T_3144[2] <= _T_3226 @[el2_lib.scala 330:30] - node _T_3227 = bits(_T_3137, 29, 29) @[el2_lib.scala 327:36] - _T_3141[15] <= _T_3227 @[el2_lib.scala 327:30] - node _T_3228 = bits(_T_3137, 29, 29) @[el2_lib.scala 330:36] - _T_3144[3] <= _T_3228 @[el2_lib.scala 330:30] - node _T_3229 = bits(_T_3137, 30, 30) @[el2_lib.scala 325:36] - _T_3139[17] <= _T_3229 @[el2_lib.scala 325:30] - node _T_3230 = bits(_T_3137, 30, 30) @[el2_lib.scala 327:36] - _T_3141[16] <= _T_3230 @[el2_lib.scala 327:30] - node _T_3231 = bits(_T_3137, 30, 30) @[el2_lib.scala 330:36] - _T_3144[4] <= _T_3231 @[el2_lib.scala 330:30] - node _T_3232 = bits(_T_3137, 31, 31) @[el2_lib.scala 326:36] - _T_3140[17] <= _T_3232 @[el2_lib.scala 326:30] - node _T_3233 = bits(_T_3137, 31, 31) @[el2_lib.scala 327:36] - _T_3141[17] <= _T_3233 @[el2_lib.scala 327:30] - node _T_3234 = bits(_T_3137, 31, 31) @[el2_lib.scala 330:36] - _T_3144[5] <= _T_3234 @[el2_lib.scala 330:30] - node _T_3235 = xorr(_T_3137) @[el2_lib.scala 333:30] - node _T_3236 = xorr(_T_3138) @[el2_lib.scala 333:44] - node _T_3237 = xor(_T_3235, _T_3236) @[el2_lib.scala 333:35] - node _T_3238 = not(UInt<1>("h00")) @[el2_lib.scala 333:52] - node _T_3239 = and(_T_3237, _T_3238) @[el2_lib.scala 333:50] - node _T_3240 = bits(_T_3138, 5, 5) @[el2_lib.scala 333:68] - node _T_3241 = cat(_T_3144[2], _T_3144[1]) @[el2_lib.scala 333:76] - node _T_3242 = cat(_T_3241, _T_3144[0]) @[el2_lib.scala 333:76] - node _T_3243 = cat(_T_3144[5], _T_3144[4]) @[el2_lib.scala 333:76] - node _T_3244 = cat(_T_3243, _T_3144[3]) @[el2_lib.scala 333:76] - node _T_3245 = cat(_T_3244, _T_3242) @[el2_lib.scala 333:76] - node _T_3246 = xorr(_T_3245) @[el2_lib.scala 333:83] - node _T_3247 = xor(_T_3240, _T_3246) @[el2_lib.scala 333:71] - node _T_3248 = bits(_T_3138, 4, 4) @[el2_lib.scala 333:95] - node _T_3249 = cat(_T_3143[2], _T_3143[1]) @[el2_lib.scala 333:103] - node _T_3250 = cat(_T_3249, _T_3143[0]) @[el2_lib.scala 333:103] - node _T_3251 = cat(_T_3143[4], _T_3143[3]) @[el2_lib.scala 333:103] - node _T_3252 = cat(_T_3143[6], _T_3143[5]) @[el2_lib.scala 333:103] - node _T_3253 = cat(_T_3252, _T_3251) @[el2_lib.scala 333:103] - node _T_3254 = cat(_T_3253, _T_3250) @[el2_lib.scala 333:103] - node _T_3255 = cat(_T_3143[8], _T_3143[7]) @[el2_lib.scala 333:103] - node _T_3256 = cat(_T_3143[10], _T_3143[9]) @[el2_lib.scala 333:103] - node _T_3257 = cat(_T_3256, _T_3255) @[el2_lib.scala 333:103] - node _T_3258 = cat(_T_3143[12], _T_3143[11]) @[el2_lib.scala 333:103] - node _T_3259 = cat(_T_3143[14], _T_3143[13]) @[el2_lib.scala 333:103] - node _T_3260 = cat(_T_3259, _T_3258) @[el2_lib.scala 333:103] - node _T_3261 = cat(_T_3260, _T_3257) @[el2_lib.scala 333:103] - node _T_3262 = cat(_T_3261, _T_3254) @[el2_lib.scala 333:103] - node _T_3263 = xorr(_T_3262) @[el2_lib.scala 333:110] - node _T_3264 = xor(_T_3248, _T_3263) @[el2_lib.scala 333:98] - node _T_3265 = bits(_T_3138, 3, 3) @[el2_lib.scala 333:122] - node _T_3266 = cat(_T_3142[2], _T_3142[1]) @[el2_lib.scala 333:130] - node _T_3267 = cat(_T_3266, _T_3142[0]) @[el2_lib.scala 333:130] - node _T_3268 = cat(_T_3142[4], _T_3142[3]) @[el2_lib.scala 333:130] - node _T_3269 = cat(_T_3142[6], _T_3142[5]) @[el2_lib.scala 333:130] - node _T_3270 = cat(_T_3269, _T_3268) @[el2_lib.scala 333:130] - node _T_3271 = cat(_T_3270, _T_3267) @[el2_lib.scala 333:130] - node _T_3272 = cat(_T_3142[8], _T_3142[7]) @[el2_lib.scala 333:130] - node _T_3273 = cat(_T_3142[10], _T_3142[9]) @[el2_lib.scala 333:130] - node _T_3274 = cat(_T_3273, _T_3272) @[el2_lib.scala 333:130] - node _T_3275 = cat(_T_3142[12], _T_3142[11]) @[el2_lib.scala 333:130] - node _T_3276 = cat(_T_3142[14], _T_3142[13]) @[el2_lib.scala 333:130] - node _T_3277 = cat(_T_3276, _T_3275) @[el2_lib.scala 333:130] - node _T_3278 = cat(_T_3277, _T_3274) @[el2_lib.scala 333:130] - node _T_3279 = cat(_T_3278, _T_3271) @[el2_lib.scala 333:130] - node _T_3280 = xorr(_T_3279) @[el2_lib.scala 333:137] - node _T_3281 = xor(_T_3265, _T_3280) @[el2_lib.scala 333:125] - node _T_3282 = bits(_T_3138, 2, 2) @[el2_lib.scala 333:149] - node _T_3283 = cat(_T_3141[1], _T_3141[0]) @[el2_lib.scala 333:157] - node _T_3284 = cat(_T_3141[3], _T_3141[2]) @[el2_lib.scala 333:157] - node _T_3285 = cat(_T_3284, _T_3283) @[el2_lib.scala 333:157] - node _T_3286 = cat(_T_3141[5], _T_3141[4]) @[el2_lib.scala 333:157] - node _T_3287 = cat(_T_3141[8], _T_3141[7]) @[el2_lib.scala 333:157] - node _T_3288 = cat(_T_3287, _T_3141[6]) @[el2_lib.scala 333:157] - node _T_3289 = cat(_T_3288, _T_3286) @[el2_lib.scala 333:157] - node _T_3290 = cat(_T_3289, _T_3285) @[el2_lib.scala 333:157] - node _T_3291 = cat(_T_3141[10], _T_3141[9]) @[el2_lib.scala 333:157] - node _T_3292 = cat(_T_3141[12], _T_3141[11]) @[el2_lib.scala 333:157] - node _T_3293 = cat(_T_3292, _T_3291) @[el2_lib.scala 333:157] - node _T_3294 = cat(_T_3141[14], _T_3141[13]) @[el2_lib.scala 333:157] - node _T_3295 = cat(_T_3141[17], _T_3141[16]) @[el2_lib.scala 333:157] - node _T_3296 = cat(_T_3295, _T_3141[15]) @[el2_lib.scala 333:157] - node _T_3297 = cat(_T_3296, _T_3294) @[el2_lib.scala 333:157] - node _T_3298 = cat(_T_3297, _T_3293) @[el2_lib.scala 333:157] - node _T_3299 = cat(_T_3298, _T_3290) @[el2_lib.scala 333:157] - node _T_3300 = xorr(_T_3299) @[el2_lib.scala 333:164] - node _T_3301 = xor(_T_3282, _T_3300) @[el2_lib.scala 333:152] - node _T_3302 = bits(_T_3138, 1, 1) @[el2_lib.scala 333:176] - node _T_3303 = cat(_T_3140[1], _T_3140[0]) @[el2_lib.scala 333:184] - node _T_3304 = cat(_T_3140[3], _T_3140[2]) @[el2_lib.scala 333:184] - node _T_3305 = cat(_T_3304, _T_3303) @[el2_lib.scala 333:184] - node _T_3306 = cat(_T_3140[5], _T_3140[4]) @[el2_lib.scala 333:184] - node _T_3307 = cat(_T_3140[8], _T_3140[7]) @[el2_lib.scala 333:184] - node _T_3308 = cat(_T_3307, _T_3140[6]) @[el2_lib.scala 333:184] - node _T_3309 = cat(_T_3308, _T_3306) @[el2_lib.scala 333:184] - node _T_3310 = cat(_T_3309, _T_3305) @[el2_lib.scala 333:184] - node _T_3311 = cat(_T_3140[10], _T_3140[9]) @[el2_lib.scala 333:184] - node _T_3312 = cat(_T_3140[12], _T_3140[11]) @[el2_lib.scala 333:184] - node _T_3313 = cat(_T_3312, _T_3311) @[el2_lib.scala 333:184] - node _T_3314 = cat(_T_3140[14], _T_3140[13]) @[el2_lib.scala 333:184] - node _T_3315 = cat(_T_3140[17], _T_3140[16]) @[el2_lib.scala 333:184] - node _T_3316 = cat(_T_3315, _T_3140[15]) @[el2_lib.scala 333:184] - node _T_3317 = cat(_T_3316, _T_3314) @[el2_lib.scala 333:184] - node _T_3318 = cat(_T_3317, _T_3313) @[el2_lib.scala 333:184] - node _T_3319 = cat(_T_3318, _T_3310) @[el2_lib.scala 333:184] - node _T_3320 = xorr(_T_3319) @[el2_lib.scala 333:191] - node _T_3321 = xor(_T_3302, _T_3320) @[el2_lib.scala 333:179] - node _T_3322 = bits(_T_3138, 0, 0) @[el2_lib.scala 333:203] - node _T_3323 = cat(_T_3139[1], _T_3139[0]) @[el2_lib.scala 333:211] - node _T_3324 = cat(_T_3139[3], _T_3139[2]) @[el2_lib.scala 333:211] - node _T_3325 = cat(_T_3324, _T_3323) @[el2_lib.scala 333:211] - node _T_3326 = cat(_T_3139[5], _T_3139[4]) @[el2_lib.scala 333:211] - node _T_3327 = cat(_T_3139[8], _T_3139[7]) @[el2_lib.scala 333:211] - node _T_3328 = cat(_T_3327, _T_3139[6]) @[el2_lib.scala 333:211] - node _T_3329 = cat(_T_3328, _T_3326) @[el2_lib.scala 333:211] - node _T_3330 = cat(_T_3329, _T_3325) @[el2_lib.scala 333:211] - node _T_3331 = cat(_T_3139[10], _T_3139[9]) @[el2_lib.scala 333:211] - node _T_3332 = cat(_T_3139[12], _T_3139[11]) @[el2_lib.scala 333:211] - node _T_3333 = cat(_T_3332, _T_3331) @[el2_lib.scala 333:211] - node _T_3334 = cat(_T_3139[14], _T_3139[13]) @[el2_lib.scala 333:211] - node _T_3335 = cat(_T_3139[17], _T_3139[16]) @[el2_lib.scala 333:211] - node _T_3336 = cat(_T_3335, _T_3139[15]) @[el2_lib.scala 333:211] - node _T_3337 = cat(_T_3336, _T_3334) @[el2_lib.scala 333:211] - node _T_3338 = cat(_T_3337, _T_3333) @[el2_lib.scala 333:211] - node _T_3339 = cat(_T_3338, _T_3330) @[el2_lib.scala 333:211] - node _T_3340 = xorr(_T_3339) @[el2_lib.scala 333:218] - node _T_3341 = xor(_T_3322, _T_3340) @[el2_lib.scala 333:206] + wire _T_3139 : UInt<1>[18] @[lib.scala 173:18] + wire _T_3140 : UInt<1>[18] @[lib.scala 174:18] + wire _T_3141 : UInt<1>[18] @[lib.scala 175:18] + wire _T_3142 : UInt<1>[15] @[lib.scala 176:18] + wire _T_3143 : UInt<1>[15] @[lib.scala 177:18] + wire _T_3144 : UInt<1>[6] @[lib.scala 178:18] + node _T_3145 = bits(_T_3137, 0, 0) @[lib.scala 185:36] + _T_3139[0] <= _T_3145 @[lib.scala 185:30] + node _T_3146 = bits(_T_3137, 0, 0) @[lib.scala 186:36] + _T_3140[0] <= _T_3146 @[lib.scala 186:30] + node _T_3147 = bits(_T_3137, 1, 1) @[lib.scala 185:36] + _T_3139[1] <= _T_3147 @[lib.scala 185:30] + node _T_3148 = bits(_T_3137, 1, 1) @[lib.scala 187:36] + _T_3141[0] <= _T_3148 @[lib.scala 187:30] + node _T_3149 = bits(_T_3137, 2, 2) @[lib.scala 186:36] + _T_3140[1] <= _T_3149 @[lib.scala 186:30] + node _T_3150 = bits(_T_3137, 2, 2) @[lib.scala 187:36] + _T_3141[1] <= _T_3150 @[lib.scala 187:30] + node _T_3151 = bits(_T_3137, 3, 3) @[lib.scala 185:36] + _T_3139[2] <= _T_3151 @[lib.scala 185:30] + node _T_3152 = bits(_T_3137, 3, 3) @[lib.scala 186:36] + _T_3140[2] <= _T_3152 @[lib.scala 186:30] + node _T_3153 = bits(_T_3137, 3, 3) @[lib.scala 187:36] + _T_3141[2] <= _T_3153 @[lib.scala 187:30] + node _T_3154 = bits(_T_3137, 4, 4) @[lib.scala 185:36] + _T_3139[3] <= _T_3154 @[lib.scala 185:30] + node _T_3155 = bits(_T_3137, 4, 4) @[lib.scala 188:36] + _T_3142[0] <= _T_3155 @[lib.scala 188:30] + node _T_3156 = bits(_T_3137, 5, 5) @[lib.scala 186:36] + _T_3140[3] <= _T_3156 @[lib.scala 186:30] + node _T_3157 = bits(_T_3137, 5, 5) @[lib.scala 188:36] + _T_3142[1] <= _T_3157 @[lib.scala 188:30] + node _T_3158 = bits(_T_3137, 6, 6) @[lib.scala 185:36] + _T_3139[4] <= _T_3158 @[lib.scala 185:30] + node _T_3159 = bits(_T_3137, 6, 6) @[lib.scala 186:36] + _T_3140[4] <= _T_3159 @[lib.scala 186:30] + node _T_3160 = bits(_T_3137, 6, 6) @[lib.scala 188:36] + _T_3142[2] <= _T_3160 @[lib.scala 188:30] + node _T_3161 = bits(_T_3137, 7, 7) @[lib.scala 187:36] + _T_3141[3] <= _T_3161 @[lib.scala 187:30] + node _T_3162 = bits(_T_3137, 7, 7) @[lib.scala 188:36] + _T_3142[3] <= _T_3162 @[lib.scala 188:30] + node _T_3163 = bits(_T_3137, 8, 8) @[lib.scala 185:36] + _T_3139[5] <= _T_3163 @[lib.scala 185:30] + node _T_3164 = bits(_T_3137, 8, 8) @[lib.scala 187:36] + _T_3141[4] <= _T_3164 @[lib.scala 187:30] + node _T_3165 = bits(_T_3137, 8, 8) @[lib.scala 188:36] + _T_3142[4] <= _T_3165 @[lib.scala 188:30] + node _T_3166 = bits(_T_3137, 9, 9) @[lib.scala 186:36] + _T_3140[5] <= _T_3166 @[lib.scala 186:30] + node _T_3167 = bits(_T_3137, 9, 9) @[lib.scala 187:36] + _T_3141[5] <= _T_3167 @[lib.scala 187:30] + node _T_3168 = bits(_T_3137, 9, 9) @[lib.scala 188:36] + _T_3142[5] <= _T_3168 @[lib.scala 188:30] + node _T_3169 = bits(_T_3137, 10, 10) @[lib.scala 185:36] + _T_3139[6] <= _T_3169 @[lib.scala 185:30] + node _T_3170 = bits(_T_3137, 10, 10) @[lib.scala 186:36] + _T_3140[6] <= _T_3170 @[lib.scala 186:30] + node _T_3171 = bits(_T_3137, 10, 10) @[lib.scala 187:36] + _T_3141[6] <= _T_3171 @[lib.scala 187:30] + node _T_3172 = bits(_T_3137, 10, 10) @[lib.scala 188:36] + _T_3142[6] <= _T_3172 @[lib.scala 188:30] + node _T_3173 = bits(_T_3137, 11, 11) @[lib.scala 185:36] + _T_3139[7] <= _T_3173 @[lib.scala 185:30] + node _T_3174 = bits(_T_3137, 11, 11) @[lib.scala 189:36] + _T_3143[0] <= _T_3174 @[lib.scala 189:30] + node _T_3175 = bits(_T_3137, 12, 12) @[lib.scala 186:36] + _T_3140[7] <= _T_3175 @[lib.scala 186:30] + node _T_3176 = bits(_T_3137, 12, 12) @[lib.scala 189:36] + _T_3143[1] <= _T_3176 @[lib.scala 189:30] + node _T_3177 = bits(_T_3137, 13, 13) @[lib.scala 185:36] + _T_3139[8] <= _T_3177 @[lib.scala 185:30] + node _T_3178 = bits(_T_3137, 13, 13) @[lib.scala 186:36] + _T_3140[8] <= _T_3178 @[lib.scala 186:30] + node _T_3179 = bits(_T_3137, 13, 13) @[lib.scala 189:36] + _T_3143[2] <= _T_3179 @[lib.scala 189:30] + node _T_3180 = bits(_T_3137, 14, 14) @[lib.scala 187:36] + _T_3141[7] <= _T_3180 @[lib.scala 187:30] + node _T_3181 = bits(_T_3137, 14, 14) @[lib.scala 189:36] + _T_3143[3] <= _T_3181 @[lib.scala 189:30] + node _T_3182 = bits(_T_3137, 15, 15) @[lib.scala 185:36] + _T_3139[9] <= _T_3182 @[lib.scala 185:30] + node _T_3183 = bits(_T_3137, 15, 15) @[lib.scala 187:36] + _T_3141[8] <= _T_3183 @[lib.scala 187:30] + node _T_3184 = bits(_T_3137, 15, 15) @[lib.scala 189:36] + _T_3143[4] <= _T_3184 @[lib.scala 189:30] + node _T_3185 = bits(_T_3137, 16, 16) @[lib.scala 186:36] + _T_3140[9] <= _T_3185 @[lib.scala 186:30] + node _T_3186 = bits(_T_3137, 16, 16) @[lib.scala 187:36] + _T_3141[9] <= _T_3186 @[lib.scala 187:30] + node _T_3187 = bits(_T_3137, 16, 16) @[lib.scala 189:36] + _T_3143[5] <= _T_3187 @[lib.scala 189:30] + node _T_3188 = bits(_T_3137, 17, 17) @[lib.scala 185:36] + _T_3139[10] <= _T_3188 @[lib.scala 185:30] + node _T_3189 = bits(_T_3137, 17, 17) @[lib.scala 186:36] + _T_3140[10] <= _T_3189 @[lib.scala 186:30] + node _T_3190 = bits(_T_3137, 17, 17) @[lib.scala 187:36] + _T_3141[10] <= _T_3190 @[lib.scala 187:30] + node _T_3191 = bits(_T_3137, 17, 17) @[lib.scala 189:36] + _T_3143[6] <= _T_3191 @[lib.scala 189:30] + node _T_3192 = bits(_T_3137, 18, 18) @[lib.scala 188:36] + _T_3142[7] <= _T_3192 @[lib.scala 188:30] + node _T_3193 = bits(_T_3137, 18, 18) @[lib.scala 189:36] + _T_3143[7] <= _T_3193 @[lib.scala 189:30] + node _T_3194 = bits(_T_3137, 19, 19) @[lib.scala 185:36] + _T_3139[11] <= _T_3194 @[lib.scala 185:30] + node _T_3195 = bits(_T_3137, 19, 19) @[lib.scala 188:36] + _T_3142[8] <= _T_3195 @[lib.scala 188:30] + node _T_3196 = bits(_T_3137, 19, 19) @[lib.scala 189:36] + _T_3143[8] <= _T_3196 @[lib.scala 189:30] + node _T_3197 = bits(_T_3137, 20, 20) @[lib.scala 186:36] + _T_3140[11] <= _T_3197 @[lib.scala 186:30] + node _T_3198 = bits(_T_3137, 20, 20) @[lib.scala 188:36] + _T_3142[9] <= _T_3198 @[lib.scala 188:30] + node _T_3199 = bits(_T_3137, 20, 20) @[lib.scala 189:36] + _T_3143[9] <= _T_3199 @[lib.scala 189:30] + node _T_3200 = bits(_T_3137, 21, 21) @[lib.scala 185:36] + _T_3139[12] <= _T_3200 @[lib.scala 185:30] + node _T_3201 = bits(_T_3137, 21, 21) @[lib.scala 186:36] + _T_3140[12] <= _T_3201 @[lib.scala 186:30] + node _T_3202 = bits(_T_3137, 21, 21) @[lib.scala 188:36] + _T_3142[10] <= _T_3202 @[lib.scala 188:30] + node _T_3203 = bits(_T_3137, 21, 21) @[lib.scala 189:36] + _T_3143[10] <= _T_3203 @[lib.scala 189:30] + node _T_3204 = bits(_T_3137, 22, 22) @[lib.scala 187:36] + _T_3141[11] <= _T_3204 @[lib.scala 187:30] + node _T_3205 = bits(_T_3137, 22, 22) @[lib.scala 188:36] + _T_3142[11] <= _T_3205 @[lib.scala 188:30] + node _T_3206 = bits(_T_3137, 22, 22) @[lib.scala 189:36] + _T_3143[11] <= _T_3206 @[lib.scala 189:30] + node _T_3207 = bits(_T_3137, 23, 23) @[lib.scala 185:36] + _T_3139[13] <= _T_3207 @[lib.scala 185:30] + node _T_3208 = bits(_T_3137, 23, 23) @[lib.scala 187:36] + _T_3141[12] <= _T_3208 @[lib.scala 187:30] + node _T_3209 = bits(_T_3137, 23, 23) @[lib.scala 188:36] + _T_3142[12] <= _T_3209 @[lib.scala 188:30] + node _T_3210 = bits(_T_3137, 23, 23) @[lib.scala 189:36] + _T_3143[12] <= _T_3210 @[lib.scala 189:30] + node _T_3211 = bits(_T_3137, 24, 24) @[lib.scala 186:36] + _T_3140[13] <= _T_3211 @[lib.scala 186:30] + node _T_3212 = bits(_T_3137, 24, 24) @[lib.scala 187:36] + _T_3141[13] <= _T_3212 @[lib.scala 187:30] + node _T_3213 = bits(_T_3137, 24, 24) @[lib.scala 188:36] + _T_3142[13] <= _T_3213 @[lib.scala 188:30] + node _T_3214 = bits(_T_3137, 24, 24) @[lib.scala 189:36] + _T_3143[13] <= _T_3214 @[lib.scala 189:30] + node _T_3215 = bits(_T_3137, 25, 25) @[lib.scala 185:36] + _T_3139[14] <= _T_3215 @[lib.scala 185:30] + node _T_3216 = bits(_T_3137, 25, 25) @[lib.scala 186:36] + _T_3140[14] <= _T_3216 @[lib.scala 186:30] + node _T_3217 = bits(_T_3137, 25, 25) @[lib.scala 187:36] + _T_3141[14] <= _T_3217 @[lib.scala 187:30] + node _T_3218 = bits(_T_3137, 25, 25) @[lib.scala 188:36] + _T_3142[14] <= _T_3218 @[lib.scala 188:30] + node _T_3219 = bits(_T_3137, 25, 25) @[lib.scala 189:36] + _T_3143[14] <= _T_3219 @[lib.scala 189:30] + node _T_3220 = bits(_T_3137, 26, 26) @[lib.scala 185:36] + _T_3139[15] <= _T_3220 @[lib.scala 185:30] + node _T_3221 = bits(_T_3137, 26, 26) @[lib.scala 190:36] + _T_3144[0] <= _T_3221 @[lib.scala 190:30] + node _T_3222 = bits(_T_3137, 27, 27) @[lib.scala 186:36] + _T_3140[15] <= _T_3222 @[lib.scala 186:30] + node _T_3223 = bits(_T_3137, 27, 27) @[lib.scala 190:36] + _T_3144[1] <= _T_3223 @[lib.scala 190:30] + node _T_3224 = bits(_T_3137, 28, 28) @[lib.scala 185:36] + _T_3139[16] <= _T_3224 @[lib.scala 185:30] + node _T_3225 = bits(_T_3137, 28, 28) @[lib.scala 186:36] + _T_3140[16] <= _T_3225 @[lib.scala 186:30] + node _T_3226 = bits(_T_3137, 28, 28) @[lib.scala 190:36] + _T_3144[2] <= _T_3226 @[lib.scala 190:30] + node _T_3227 = bits(_T_3137, 29, 29) @[lib.scala 187:36] + _T_3141[15] <= _T_3227 @[lib.scala 187:30] + node _T_3228 = bits(_T_3137, 29, 29) @[lib.scala 190:36] + _T_3144[3] <= _T_3228 @[lib.scala 190:30] + node _T_3229 = bits(_T_3137, 30, 30) @[lib.scala 185:36] + _T_3139[17] <= _T_3229 @[lib.scala 185:30] + node _T_3230 = bits(_T_3137, 30, 30) @[lib.scala 187:36] + _T_3141[16] <= _T_3230 @[lib.scala 187:30] + node _T_3231 = bits(_T_3137, 30, 30) @[lib.scala 190:36] + _T_3144[4] <= _T_3231 @[lib.scala 190:30] + node _T_3232 = bits(_T_3137, 31, 31) @[lib.scala 186:36] + _T_3140[17] <= _T_3232 @[lib.scala 186:30] + node _T_3233 = bits(_T_3137, 31, 31) @[lib.scala 187:36] + _T_3141[17] <= _T_3233 @[lib.scala 187:30] + node _T_3234 = bits(_T_3137, 31, 31) @[lib.scala 190:36] + _T_3144[5] <= _T_3234 @[lib.scala 190:30] + node _T_3235 = xorr(_T_3137) @[lib.scala 193:30] + node _T_3236 = xorr(_T_3138) @[lib.scala 193:44] + node _T_3237 = xor(_T_3235, _T_3236) @[lib.scala 193:35] + node _T_3238 = not(UInt<1>("h00")) @[lib.scala 193:52] + node _T_3239 = and(_T_3237, _T_3238) @[lib.scala 193:50] + node _T_3240 = bits(_T_3138, 5, 5) @[lib.scala 193:68] + node _T_3241 = cat(_T_3144[2], _T_3144[1]) @[lib.scala 193:76] + node _T_3242 = cat(_T_3241, _T_3144[0]) @[lib.scala 193:76] + node _T_3243 = cat(_T_3144[5], _T_3144[4]) @[lib.scala 193:76] + node _T_3244 = cat(_T_3243, _T_3144[3]) @[lib.scala 193:76] + node _T_3245 = cat(_T_3244, _T_3242) @[lib.scala 193:76] + node _T_3246 = xorr(_T_3245) @[lib.scala 193:83] + node _T_3247 = xor(_T_3240, _T_3246) @[lib.scala 193:71] + node _T_3248 = bits(_T_3138, 4, 4) @[lib.scala 193:95] + node _T_3249 = cat(_T_3143[2], _T_3143[1]) @[lib.scala 193:103] + node _T_3250 = cat(_T_3249, _T_3143[0]) @[lib.scala 193:103] + node _T_3251 = cat(_T_3143[4], _T_3143[3]) @[lib.scala 193:103] + node _T_3252 = cat(_T_3143[6], _T_3143[5]) @[lib.scala 193:103] + node _T_3253 = cat(_T_3252, _T_3251) @[lib.scala 193:103] + node _T_3254 = cat(_T_3253, _T_3250) @[lib.scala 193:103] + node _T_3255 = cat(_T_3143[8], _T_3143[7]) @[lib.scala 193:103] + node _T_3256 = cat(_T_3143[10], _T_3143[9]) @[lib.scala 193:103] + node _T_3257 = cat(_T_3256, _T_3255) @[lib.scala 193:103] + node _T_3258 = cat(_T_3143[12], _T_3143[11]) @[lib.scala 193:103] + node _T_3259 = cat(_T_3143[14], _T_3143[13]) @[lib.scala 193:103] + node _T_3260 = cat(_T_3259, _T_3258) @[lib.scala 193:103] + node _T_3261 = cat(_T_3260, _T_3257) @[lib.scala 193:103] + node _T_3262 = cat(_T_3261, _T_3254) @[lib.scala 193:103] + node _T_3263 = xorr(_T_3262) @[lib.scala 193:110] + node _T_3264 = xor(_T_3248, _T_3263) @[lib.scala 193:98] + node _T_3265 = bits(_T_3138, 3, 3) @[lib.scala 193:122] + node _T_3266 = cat(_T_3142[2], _T_3142[1]) @[lib.scala 193:130] + node _T_3267 = cat(_T_3266, _T_3142[0]) @[lib.scala 193:130] + node _T_3268 = cat(_T_3142[4], _T_3142[3]) @[lib.scala 193:130] + node _T_3269 = cat(_T_3142[6], _T_3142[5]) @[lib.scala 193:130] + node _T_3270 = cat(_T_3269, _T_3268) @[lib.scala 193:130] + node _T_3271 = cat(_T_3270, _T_3267) @[lib.scala 193:130] + node _T_3272 = cat(_T_3142[8], _T_3142[7]) @[lib.scala 193:130] + node _T_3273 = cat(_T_3142[10], _T_3142[9]) @[lib.scala 193:130] + node _T_3274 = cat(_T_3273, _T_3272) @[lib.scala 193:130] + node _T_3275 = cat(_T_3142[12], _T_3142[11]) @[lib.scala 193:130] + node _T_3276 = cat(_T_3142[14], _T_3142[13]) @[lib.scala 193:130] + node _T_3277 = cat(_T_3276, _T_3275) @[lib.scala 193:130] + node _T_3278 = cat(_T_3277, _T_3274) @[lib.scala 193:130] + node _T_3279 = cat(_T_3278, _T_3271) @[lib.scala 193:130] + node _T_3280 = xorr(_T_3279) @[lib.scala 193:137] + node _T_3281 = xor(_T_3265, _T_3280) @[lib.scala 193:125] + node _T_3282 = bits(_T_3138, 2, 2) @[lib.scala 193:149] + node _T_3283 = cat(_T_3141[1], _T_3141[0]) @[lib.scala 193:157] + node _T_3284 = cat(_T_3141[3], _T_3141[2]) @[lib.scala 193:157] + node _T_3285 = cat(_T_3284, _T_3283) @[lib.scala 193:157] + node _T_3286 = cat(_T_3141[5], _T_3141[4]) @[lib.scala 193:157] + node _T_3287 = cat(_T_3141[8], _T_3141[7]) @[lib.scala 193:157] + node _T_3288 = cat(_T_3287, _T_3141[6]) @[lib.scala 193:157] + node _T_3289 = cat(_T_3288, _T_3286) @[lib.scala 193:157] + node _T_3290 = cat(_T_3289, _T_3285) @[lib.scala 193:157] + node _T_3291 = cat(_T_3141[10], _T_3141[9]) @[lib.scala 193:157] + node _T_3292 = cat(_T_3141[12], _T_3141[11]) @[lib.scala 193:157] + node _T_3293 = cat(_T_3292, _T_3291) @[lib.scala 193:157] + node _T_3294 = cat(_T_3141[14], _T_3141[13]) @[lib.scala 193:157] + node _T_3295 = cat(_T_3141[17], _T_3141[16]) @[lib.scala 193:157] + node _T_3296 = cat(_T_3295, _T_3141[15]) @[lib.scala 193:157] + node _T_3297 = cat(_T_3296, _T_3294) @[lib.scala 193:157] + node _T_3298 = cat(_T_3297, _T_3293) @[lib.scala 193:157] + node _T_3299 = cat(_T_3298, _T_3290) @[lib.scala 193:157] + node _T_3300 = xorr(_T_3299) @[lib.scala 193:164] + node _T_3301 = xor(_T_3282, _T_3300) @[lib.scala 193:152] + node _T_3302 = bits(_T_3138, 1, 1) @[lib.scala 193:176] + node _T_3303 = cat(_T_3140[1], _T_3140[0]) @[lib.scala 193:184] + node _T_3304 = cat(_T_3140[3], _T_3140[2]) @[lib.scala 193:184] + node _T_3305 = cat(_T_3304, _T_3303) @[lib.scala 193:184] + node _T_3306 = cat(_T_3140[5], _T_3140[4]) @[lib.scala 193:184] + node _T_3307 = cat(_T_3140[8], _T_3140[7]) @[lib.scala 193:184] + node _T_3308 = cat(_T_3307, _T_3140[6]) @[lib.scala 193:184] + node _T_3309 = cat(_T_3308, _T_3306) @[lib.scala 193:184] + node _T_3310 = cat(_T_3309, _T_3305) @[lib.scala 193:184] + node _T_3311 = cat(_T_3140[10], _T_3140[9]) @[lib.scala 193:184] + node _T_3312 = cat(_T_3140[12], _T_3140[11]) @[lib.scala 193:184] + node _T_3313 = cat(_T_3312, _T_3311) @[lib.scala 193:184] + node _T_3314 = cat(_T_3140[14], _T_3140[13]) @[lib.scala 193:184] + node _T_3315 = cat(_T_3140[17], _T_3140[16]) @[lib.scala 193:184] + node _T_3316 = cat(_T_3315, _T_3140[15]) @[lib.scala 193:184] + node _T_3317 = cat(_T_3316, _T_3314) @[lib.scala 193:184] + node _T_3318 = cat(_T_3317, _T_3313) @[lib.scala 193:184] + node _T_3319 = cat(_T_3318, _T_3310) @[lib.scala 193:184] + node _T_3320 = xorr(_T_3319) @[lib.scala 193:191] + node _T_3321 = xor(_T_3302, _T_3320) @[lib.scala 193:179] + node _T_3322 = bits(_T_3138, 0, 0) @[lib.scala 193:203] + node _T_3323 = cat(_T_3139[1], _T_3139[0]) @[lib.scala 193:211] + node _T_3324 = cat(_T_3139[3], _T_3139[2]) @[lib.scala 193:211] + node _T_3325 = cat(_T_3324, _T_3323) @[lib.scala 193:211] + node _T_3326 = cat(_T_3139[5], _T_3139[4]) @[lib.scala 193:211] + node _T_3327 = cat(_T_3139[8], _T_3139[7]) @[lib.scala 193:211] + node _T_3328 = cat(_T_3327, _T_3139[6]) @[lib.scala 193:211] + node _T_3329 = cat(_T_3328, _T_3326) @[lib.scala 193:211] + node _T_3330 = cat(_T_3329, _T_3325) @[lib.scala 193:211] + node _T_3331 = cat(_T_3139[10], _T_3139[9]) @[lib.scala 193:211] + node _T_3332 = cat(_T_3139[12], _T_3139[11]) @[lib.scala 193:211] + node _T_3333 = cat(_T_3332, _T_3331) @[lib.scala 193:211] + node _T_3334 = cat(_T_3139[14], _T_3139[13]) @[lib.scala 193:211] + node _T_3335 = cat(_T_3139[17], _T_3139[16]) @[lib.scala 193:211] + node _T_3336 = cat(_T_3335, _T_3139[15]) @[lib.scala 193:211] + node _T_3337 = cat(_T_3336, _T_3334) @[lib.scala 193:211] + node _T_3338 = cat(_T_3337, _T_3333) @[lib.scala 193:211] + node _T_3339 = cat(_T_3338, _T_3330) @[lib.scala 193:211] + node _T_3340 = xorr(_T_3339) @[lib.scala 193:218] + node _T_3341 = xor(_T_3322, _T_3340) @[lib.scala 193:206] node _T_3342 = cat(_T_3301, _T_3321) @[Cat.scala 29:58] node _T_3343 = cat(_T_3342, _T_3341) @[Cat.scala 29:58] node _T_3344 = cat(_T_3264, _T_3281) @[Cat.scala 29:58] node _T_3345 = cat(_T_3239, _T_3247) @[Cat.scala 29:58] node _T_3346 = cat(_T_3345, _T_3344) @[Cat.scala 29:58] node _T_3347 = cat(_T_3346, _T_3343) @[Cat.scala 29:58] - node _T_3348 = neq(_T_3347, UInt<1>("h00")) @[el2_lib.scala 334:44] - node _T_3349 = and(_T_3136, _T_3348) @[el2_lib.scala 334:32] - node _T_3350 = bits(_T_3347, 6, 6) @[el2_lib.scala 334:64] - node _T_3351 = and(_T_3349, _T_3350) @[el2_lib.scala 334:53] - node _T_3352 = neq(_T_3347, UInt<1>("h00")) @[el2_lib.scala 335:44] - node _T_3353 = and(_T_3136, _T_3352) @[el2_lib.scala 335:32] - node _T_3354 = bits(_T_3347, 6, 6) @[el2_lib.scala 335:65] - node _T_3355 = not(_T_3354) @[el2_lib.scala 335:55] - node _T_3356 = and(_T_3353, _T_3355) @[el2_lib.scala 335:53] - wire _T_3357 : UInt<1>[39] @[el2_lib.scala 336:26] - node _T_3358 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3359 = eq(_T_3358, UInt<1>("h01")) @[el2_lib.scala 339:41] - _T_3357[0] <= _T_3359 @[el2_lib.scala 339:23] - node _T_3360 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3361 = eq(_T_3360, UInt<2>("h02")) @[el2_lib.scala 339:41] - _T_3357[1] <= _T_3361 @[el2_lib.scala 339:23] - node _T_3362 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3363 = eq(_T_3362, UInt<2>("h03")) @[el2_lib.scala 339:41] - _T_3357[2] <= _T_3363 @[el2_lib.scala 339:23] - node _T_3364 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3365 = eq(_T_3364, UInt<3>("h04")) @[el2_lib.scala 339:41] - _T_3357[3] <= _T_3365 @[el2_lib.scala 339:23] - node _T_3366 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3367 = eq(_T_3366, UInt<3>("h05")) @[el2_lib.scala 339:41] - _T_3357[4] <= _T_3367 @[el2_lib.scala 339:23] - node _T_3368 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3369 = eq(_T_3368, UInt<3>("h06")) @[el2_lib.scala 339:41] - _T_3357[5] <= _T_3369 @[el2_lib.scala 339:23] - node _T_3370 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3371 = eq(_T_3370, UInt<3>("h07")) @[el2_lib.scala 339:41] - _T_3357[6] <= _T_3371 @[el2_lib.scala 339:23] - node _T_3372 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3373 = eq(_T_3372, UInt<4>("h08")) @[el2_lib.scala 339:41] - _T_3357[7] <= _T_3373 @[el2_lib.scala 339:23] - node _T_3374 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3375 = eq(_T_3374, UInt<4>("h09")) @[el2_lib.scala 339:41] - _T_3357[8] <= _T_3375 @[el2_lib.scala 339:23] - node _T_3376 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3377 = eq(_T_3376, UInt<4>("h0a")) @[el2_lib.scala 339:41] - _T_3357[9] <= _T_3377 @[el2_lib.scala 339:23] - node _T_3378 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3379 = eq(_T_3378, UInt<4>("h0b")) @[el2_lib.scala 339:41] - _T_3357[10] <= _T_3379 @[el2_lib.scala 339:23] - node _T_3380 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3381 = eq(_T_3380, UInt<4>("h0c")) @[el2_lib.scala 339:41] - _T_3357[11] <= _T_3381 @[el2_lib.scala 339:23] - node _T_3382 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3383 = eq(_T_3382, UInt<4>("h0d")) @[el2_lib.scala 339:41] - _T_3357[12] <= _T_3383 @[el2_lib.scala 339:23] - node _T_3384 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3385 = eq(_T_3384, UInt<4>("h0e")) @[el2_lib.scala 339:41] - _T_3357[13] <= _T_3385 @[el2_lib.scala 339:23] - node _T_3386 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3387 = eq(_T_3386, UInt<4>("h0f")) @[el2_lib.scala 339:41] - _T_3357[14] <= _T_3387 @[el2_lib.scala 339:23] - node _T_3388 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3389 = eq(_T_3388, UInt<5>("h010")) @[el2_lib.scala 339:41] - _T_3357[15] <= _T_3389 @[el2_lib.scala 339:23] - node _T_3390 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3391 = eq(_T_3390, UInt<5>("h011")) @[el2_lib.scala 339:41] - _T_3357[16] <= _T_3391 @[el2_lib.scala 339:23] - node _T_3392 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3393 = eq(_T_3392, UInt<5>("h012")) @[el2_lib.scala 339:41] - _T_3357[17] <= _T_3393 @[el2_lib.scala 339:23] - node _T_3394 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3395 = eq(_T_3394, UInt<5>("h013")) @[el2_lib.scala 339:41] - _T_3357[18] <= _T_3395 @[el2_lib.scala 339:23] - node _T_3396 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3397 = eq(_T_3396, UInt<5>("h014")) @[el2_lib.scala 339:41] - _T_3357[19] <= _T_3397 @[el2_lib.scala 339:23] - node _T_3398 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3399 = eq(_T_3398, UInt<5>("h015")) @[el2_lib.scala 339:41] - _T_3357[20] <= _T_3399 @[el2_lib.scala 339:23] - node _T_3400 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3401 = eq(_T_3400, UInt<5>("h016")) @[el2_lib.scala 339:41] - _T_3357[21] <= _T_3401 @[el2_lib.scala 339:23] - node _T_3402 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3403 = eq(_T_3402, UInt<5>("h017")) @[el2_lib.scala 339:41] - _T_3357[22] <= _T_3403 @[el2_lib.scala 339:23] - node _T_3404 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3405 = eq(_T_3404, UInt<5>("h018")) @[el2_lib.scala 339:41] - _T_3357[23] <= _T_3405 @[el2_lib.scala 339:23] - node _T_3406 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3407 = eq(_T_3406, UInt<5>("h019")) @[el2_lib.scala 339:41] - _T_3357[24] <= _T_3407 @[el2_lib.scala 339:23] - node _T_3408 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3409 = eq(_T_3408, UInt<5>("h01a")) @[el2_lib.scala 339:41] - _T_3357[25] <= _T_3409 @[el2_lib.scala 339:23] - node _T_3410 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3411 = eq(_T_3410, UInt<5>("h01b")) @[el2_lib.scala 339:41] - _T_3357[26] <= _T_3411 @[el2_lib.scala 339:23] - node _T_3412 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3413 = eq(_T_3412, UInt<5>("h01c")) @[el2_lib.scala 339:41] - _T_3357[27] <= _T_3413 @[el2_lib.scala 339:23] - node _T_3414 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3415 = eq(_T_3414, UInt<5>("h01d")) @[el2_lib.scala 339:41] - _T_3357[28] <= _T_3415 @[el2_lib.scala 339:23] - node _T_3416 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3417 = eq(_T_3416, UInt<5>("h01e")) @[el2_lib.scala 339:41] - _T_3357[29] <= _T_3417 @[el2_lib.scala 339:23] - node _T_3418 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3419 = eq(_T_3418, UInt<5>("h01f")) @[el2_lib.scala 339:41] - _T_3357[30] <= _T_3419 @[el2_lib.scala 339:23] - node _T_3420 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3421 = eq(_T_3420, UInt<6>("h020")) @[el2_lib.scala 339:41] - _T_3357[31] <= _T_3421 @[el2_lib.scala 339:23] - node _T_3422 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3423 = eq(_T_3422, UInt<6>("h021")) @[el2_lib.scala 339:41] - _T_3357[32] <= _T_3423 @[el2_lib.scala 339:23] - node _T_3424 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3425 = eq(_T_3424, UInt<6>("h022")) @[el2_lib.scala 339:41] - _T_3357[33] <= _T_3425 @[el2_lib.scala 339:23] - node _T_3426 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3427 = eq(_T_3426, UInt<6>("h023")) @[el2_lib.scala 339:41] - _T_3357[34] <= _T_3427 @[el2_lib.scala 339:23] - node _T_3428 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3429 = eq(_T_3428, UInt<6>("h024")) @[el2_lib.scala 339:41] - _T_3357[35] <= _T_3429 @[el2_lib.scala 339:23] - node _T_3430 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3431 = eq(_T_3430, UInt<6>("h025")) @[el2_lib.scala 339:41] - _T_3357[36] <= _T_3431 @[el2_lib.scala 339:23] - node _T_3432 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3433 = eq(_T_3432, UInt<6>("h026")) @[el2_lib.scala 339:41] - _T_3357[37] <= _T_3433 @[el2_lib.scala 339:23] - node _T_3434 = bits(_T_3347, 5, 0) @[el2_lib.scala 339:35] - node _T_3435 = eq(_T_3434, UInt<6>("h027")) @[el2_lib.scala 339:41] - _T_3357[38] <= _T_3435 @[el2_lib.scala 339:23] - node _T_3436 = bits(_T_3138, 6, 6) @[el2_lib.scala 341:37] - node _T_3437 = bits(_T_3137, 31, 26) @[el2_lib.scala 341:45] - node _T_3438 = bits(_T_3138, 5, 5) @[el2_lib.scala 341:60] - node _T_3439 = bits(_T_3137, 25, 11) @[el2_lib.scala 341:68] - node _T_3440 = bits(_T_3138, 4, 4) @[el2_lib.scala 341:83] - node _T_3441 = bits(_T_3137, 10, 4) @[el2_lib.scala 341:91] - node _T_3442 = bits(_T_3138, 3, 3) @[el2_lib.scala 341:105] - node _T_3443 = bits(_T_3137, 3, 1) @[el2_lib.scala 341:113] - node _T_3444 = bits(_T_3138, 2, 2) @[el2_lib.scala 341:126] - node _T_3445 = bits(_T_3137, 0, 0) @[el2_lib.scala 341:134] - node _T_3446 = bits(_T_3138, 1, 0) @[el2_lib.scala 341:145] + node _T_3348 = neq(_T_3347, UInt<1>("h00")) @[lib.scala 194:44] + node _T_3349 = and(_T_3136, _T_3348) @[lib.scala 194:32] + node _T_3350 = bits(_T_3347, 6, 6) @[lib.scala 194:64] + node _T_3351 = and(_T_3349, _T_3350) @[lib.scala 194:53] + node _T_3352 = neq(_T_3347, UInt<1>("h00")) @[lib.scala 195:44] + node _T_3353 = and(_T_3136, _T_3352) @[lib.scala 195:32] + node _T_3354 = bits(_T_3347, 6, 6) @[lib.scala 195:65] + node _T_3355 = not(_T_3354) @[lib.scala 195:55] + node _T_3356 = and(_T_3353, _T_3355) @[lib.scala 195:53] + wire _T_3357 : UInt<1>[39] @[lib.scala 196:26] + node _T_3358 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3359 = eq(_T_3358, UInt<1>("h01")) @[lib.scala 199:41] + _T_3357[0] <= _T_3359 @[lib.scala 199:23] + node _T_3360 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3361 = eq(_T_3360, UInt<2>("h02")) @[lib.scala 199:41] + _T_3357[1] <= _T_3361 @[lib.scala 199:23] + node _T_3362 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3363 = eq(_T_3362, UInt<2>("h03")) @[lib.scala 199:41] + _T_3357[2] <= _T_3363 @[lib.scala 199:23] + node _T_3364 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3365 = eq(_T_3364, UInt<3>("h04")) @[lib.scala 199:41] + _T_3357[3] <= _T_3365 @[lib.scala 199:23] + node _T_3366 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3367 = eq(_T_3366, UInt<3>("h05")) @[lib.scala 199:41] + _T_3357[4] <= _T_3367 @[lib.scala 199:23] + node _T_3368 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3369 = eq(_T_3368, UInt<3>("h06")) @[lib.scala 199:41] + _T_3357[5] <= _T_3369 @[lib.scala 199:23] + node _T_3370 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3371 = eq(_T_3370, UInt<3>("h07")) @[lib.scala 199:41] + _T_3357[6] <= _T_3371 @[lib.scala 199:23] + node _T_3372 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3373 = eq(_T_3372, UInt<4>("h08")) @[lib.scala 199:41] + _T_3357[7] <= _T_3373 @[lib.scala 199:23] + node _T_3374 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3375 = eq(_T_3374, UInt<4>("h09")) @[lib.scala 199:41] + _T_3357[8] <= _T_3375 @[lib.scala 199:23] + node _T_3376 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3377 = eq(_T_3376, UInt<4>("h0a")) @[lib.scala 199:41] + _T_3357[9] <= _T_3377 @[lib.scala 199:23] + node _T_3378 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3379 = eq(_T_3378, UInt<4>("h0b")) @[lib.scala 199:41] + _T_3357[10] <= _T_3379 @[lib.scala 199:23] + node _T_3380 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3381 = eq(_T_3380, UInt<4>("h0c")) @[lib.scala 199:41] + _T_3357[11] <= _T_3381 @[lib.scala 199:23] + node _T_3382 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3383 = eq(_T_3382, UInt<4>("h0d")) @[lib.scala 199:41] + _T_3357[12] <= _T_3383 @[lib.scala 199:23] + node _T_3384 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3385 = eq(_T_3384, UInt<4>("h0e")) @[lib.scala 199:41] + _T_3357[13] <= _T_3385 @[lib.scala 199:23] + node _T_3386 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3387 = eq(_T_3386, UInt<4>("h0f")) @[lib.scala 199:41] + _T_3357[14] <= _T_3387 @[lib.scala 199:23] + node _T_3388 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3389 = eq(_T_3388, UInt<5>("h010")) @[lib.scala 199:41] + _T_3357[15] <= _T_3389 @[lib.scala 199:23] + node _T_3390 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3391 = eq(_T_3390, UInt<5>("h011")) @[lib.scala 199:41] + _T_3357[16] <= _T_3391 @[lib.scala 199:23] + node _T_3392 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3393 = eq(_T_3392, UInt<5>("h012")) @[lib.scala 199:41] + _T_3357[17] <= _T_3393 @[lib.scala 199:23] + node _T_3394 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3395 = eq(_T_3394, UInt<5>("h013")) @[lib.scala 199:41] + _T_3357[18] <= _T_3395 @[lib.scala 199:23] + node _T_3396 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3397 = eq(_T_3396, UInt<5>("h014")) @[lib.scala 199:41] + _T_3357[19] <= _T_3397 @[lib.scala 199:23] + node _T_3398 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3399 = eq(_T_3398, UInt<5>("h015")) @[lib.scala 199:41] + _T_3357[20] <= _T_3399 @[lib.scala 199:23] + node _T_3400 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3401 = eq(_T_3400, UInt<5>("h016")) @[lib.scala 199:41] + _T_3357[21] <= _T_3401 @[lib.scala 199:23] + node _T_3402 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3403 = eq(_T_3402, UInt<5>("h017")) @[lib.scala 199:41] + _T_3357[22] <= _T_3403 @[lib.scala 199:23] + node _T_3404 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3405 = eq(_T_3404, UInt<5>("h018")) @[lib.scala 199:41] + _T_3357[23] <= _T_3405 @[lib.scala 199:23] + node _T_3406 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3407 = eq(_T_3406, UInt<5>("h019")) @[lib.scala 199:41] + _T_3357[24] <= _T_3407 @[lib.scala 199:23] + node _T_3408 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3409 = eq(_T_3408, UInt<5>("h01a")) @[lib.scala 199:41] + _T_3357[25] <= _T_3409 @[lib.scala 199:23] + node _T_3410 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3411 = eq(_T_3410, UInt<5>("h01b")) @[lib.scala 199:41] + _T_3357[26] <= _T_3411 @[lib.scala 199:23] + node _T_3412 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3413 = eq(_T_3412, UInt<5>("h01c")) @[lib.scala 199:41] + _T_3357[27] <= _T_3413 @[lib.scala 199:23] + node _T_3414 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3415 = eq(_T_3414, UInt<5>("h01d")) @[lib.scala 199:41] + _T_3357[28] <= _T_3415 @[lib.scala 199:23] + node _T_3416 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3417 = eq(_T_3416, UInt<5>("h01e")) @[lib.scala 199:41] + _T_3357[29] <= _T_3417 @[lib.scala 199:23] + node _T_3418 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3419 = eq(_T_3418, UInt<5>("h01f")) @[lib.scala 199:41] + _T_3357[30] <= _T_3419 @[lib.scala 199:23] + node _T_3420 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3421 = eq(_T_3420, UInt<6>("h020")) @[lib.scala 199:41] + _T_3357[31] <= _T_3421 @[lib.scala 199:23] + node _T_3422 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3423 = eq(_T_3422, UInt<6>("h021")) @[lib.scala 199:41] + _T_3357[32] <= _T_3423 @[lib.scala 199:23] + node _T_3424 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3425 = eq(_T_3424, UInt<6>("h022")) @[lib.scala 199:41] + _T_3357[33] <= _T_3425 @[lib.scala 199:23] + node _T_3426 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3427 = eq(_T_3426, UInt<6>("h023")) @[lib.scala 199:41] + _T_3357[34] <= _T_3427 @[lib.scala 199:23] + node _T_3428 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3429 = eq(_T_3428, UInt<6>("h024")) @[lib.scala 199:41] + _T_3357[35] <= _T_3429 @[lib.scala 199:23] + node _T_3430 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3431 = eq(_T_3430, UInt<6>("h025")) @[lib.scala 199:41] + _T_3357[36] <= _T_3431 @[lib.scala 199:23] + node _T_3432 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3433 = eq(_T_3432, UInt<6>("h026")) @[lib.scala 199:41] + _T_3357[37] <= _T_3433 @[lib.scala 199:23] + node _T_3434 = bits(_T_3347, 5, 0) @[lib.scala 199:35] + node _T_3435 = eq(_T_3434, UInt<6>("h027")) @[lib.scala 199:41] + _T_3357[38] <= _T_3435 @[lib.scala 199:23] + node _T_3436 = bits(_T_3138, 6, 6) @[lib.scala 201:37] + node _T_3437 = bits(_T_3137, 31, 26) @[lib.scala 201:45] + node _T_3438 = bits(_T_3138, 5, 5) @[lib.scala 201:60] + node _T_3439 = bits(_T_3137, 25, 11) @[lib.scala 201:68] + node _T_3440 = bits(_T_3138, 4, 4) @[lib.scala 201:83] + node _T_3441 = bits(_T_3137, 10, 4) @[lib.scala 201:91] + node _T_3442 = bits(_T_3138, 3, 3) @[lib.scala 201:105] + node _T_3443 = bits(_T_3137, 3, 1) @[lib.scala 201:113] + node _T_3444 = bits(_T_3138, 2, 2) @[lib.scala 201:126] + node _T_3445 = bits(_T_3137, 0, 0) @[lib.scala 201:134] + node _T_3446 = bits(_T_3138, 1, 0) @[lib.scala 201:145] node _T_3447 = cat(_T_3445, _T_3446) @[Cat.scala 29:58] node _T_3448 = cat(_T_3442, _T_3443) @[Cat.scala 29:58] node _T_3449 = cat(_T_3448, _T_3444) @[Cat.scala 29:58] @@ -7420,65 +7420,65 @@ circuit quasar_wrapper : node _T_3454 = cat(_T_3453, _T_3438) @[Cat.scala 29:58] node _T_3455 = cat(_T_3454, _T_3452) @[Cat.scala 29:58] node _T_3456 = cat(_T_3455, _T_3450) @[Cat.scala 29:58] - node _T_3457 = bits(_T_3351, 0, 0) @[el2_lib.scala 342:49] - node _T_3458 = cat(_T_3357[1], _T_3357[0]) @[el2_lib.scala 342:69] - node _T_3459 = cat(_T_3357[3], _T_3357[2]) @[el2_lib.scala 342:69] - node _T_3460 = cat(_T_3459, _T_3458) @[el2_lib.scala 342:69] - node _T_3461 = cat(_T_3357[5], _T_3357[4]) @[el2_lib.scala 342:69] - node _T_3462 = cat(_T_3357[8], _T_3357[7]) @[el2_lib.scala 342:69] - node _T_3463 = cat(_T_3462, _T_3357[6]) @[el2_lib.scala 342:69] - node _T_3464 = cat(_T_3463, _T_3461) @[el2_lib.scala 342:69] - node _T_3465 = cat(_T_3464, _T_3460) @[el2_lib.scala 342:69] - node _T_3466 = cat(_T_3357[10], _T_3357[9]) @[el2_lib.scala 342:69] - node _T_3467 = cat(_T_3357[13], _T_3357[12]) @[el2_lib.scala 342:69] - node _T_3468 = cat(_T_3467, _T_3357[11]) @[el2_lib.scala 342:69] - node _T_3469 = cat(_T_3468, _T_3466) @[el2_lib.scala 342:69] - node _T_3470 = cat(_T_3357[15], _T_3357[14]) @[el2_lib.scala 342:69] - node _T_3471 = cat(_T_3357[18], _T_3357[17]) @[el2_lib.scala 342:69] - node _T_3472 = cat(_T_3471, _T_3357[16]) @[el2_lib.scala 342:69] - node _T_3473 = cat(_T_3472, _T_3470) @[el2_lib.scala 342:69] - node _T_3474 = cat(_T_3473, _T_3469) @[el2_lib.scala 342:69] - node _T_3475 = cat(_T_3474, _T_3465) @[el2_lib.scala 342:69] - node _T_3476 = cat(_T_3357[20], _T_3357[19]) @[el2_lib.scala 342:69] - node _T_3477 = cat(_T_3357[23], _T_3357[22]) @[el2_lib.scala 342:69] - node _T_3478 = cat(_T_3477, _T_3357[21]) @[el2_lib.scala 342:69] - node _T_3479 = cat(_T_3478, _T_3476) @[el2_lib.scala 342:69] - node _T_3480 = cat(_T_3357[25], _T_3357[24]) @[el2_lib.scala 342:69] - node _T_3481 = cat(_T_3357[28], _T_3357[27]) @[el2_lib.scala 342:69] - node _T_3482 = cat(_T_3481, _T_3357[26]) @[el2_lib.scala 342:69] - node _T_3483 = cat(_T_3482, _T_3480) @[el2_lib.scala 342:69] - node _T_3484 = cat(_T_3483, _T_3479) @[el2_lib.scala 342:69] - node _T_3485 = cat(_T_3357[30], _T_3357[29]) @[el2_lib.scala 342:69] - node _T_3486 = cat(_T_3357[33], _T_3357[32]) @[el2_lib.scala 342:69] - node _T_3487 = cat(_T_3486, _T_3357[31]) @[el2_lib.scala 342:69] - node _T_3488 = cat(_T_3487, _T_3485) @[el2_lib.scala 342:69] - node _T_3489 = cat(_T_3357[35], _T_3357[34]) @[el2_lib.scala 342:69] - node _T_3490 = cat(_T_3357[38], _T_3357[37]) @[el2_lib.scala 342:69] - node _T_3491 = cat(_T_3490, _T_3357[36]) @[el2_lib.scala 342:69] - node _T_3492 = cat(_T_3491, _T_3489) @[el2_lib.scala 342:69] - node _T_3493 = cat(_T_3492, _T_3488) @[el2_lib.scala 342:69] - node _T_3494 = cat(_T_3493, _T_3484) @[el2_lib.scala 342:69] - node _T_3495 = cat(_T_3494, _T_3475) @[el2_lib.scala 342:69] - node _T_3496 = xor(_T_3495, _T_3456) @[el2_lib.scala 342:76] - node _T_3497 = mux(_T_3457, _T_3496, _T_3456) @[el2_lib.scala 342:31] - node _T_3498 = bits(_T_3497, 37, 32) @[el2_lib.scala 344:37] - node _T_3499 = bits(_T_3497, 30, 16) @[el2_lib.scala 344:61] - node _T_3500 = bits(_T_3497, 14, 8) @[el2_lib.scala 344:86] - node _T_3501 = bits(_T_3497, 6, 4) @[el2_lib.scala 344:110] - node _T_3502 = bits(_T_3497, 2, 2) @[el2_lib.scala 344:133] + node _T_3457 = bits(_T_3351, 0, 0) @[lib.scala 202:49] + node _T_3458 = cat(_T_3357[1], _T_3357[0]) @[lib.scala 202:69] + node _T_3459 = cat(_T_3357[3], _T_3357[2]) @[lib.scala 202:69] + node _T_3460 = cat(_T_3459, _T_3458) @[lib.scala 202:69] + node _T_3461 = cat(_T_3357[5], _T_3357[4]) @[lib.scala 202:69] + node _T_3462 = cat(_T_3357[8], _T_3357[7]) @[lib.scala 202:69] + node _T_3463 = cat(_T_3462, _T_3357[6]) @[lib.scala 202:69] + node _T_3464 = cat(_T_3463, _T_3461) @[lib.scala 202:69] + node _T_3465 = cat(_T_3464, _T_3460) @[lib.scala 202:69] + node _T_3466 = cat(_T_3357[10], _T_3357[9]) @[lib.scala 202:69] + node _T_3467 = cat(_T_3357[13], _T_3357[12]) @[lib.scala 202:69] + node _T_3468 = cat(_T_3467, _T_3357[11]) @[lib.scala 202:69] + node _T_3469 = cat(_T_3468, _T_3466) @[lib.scala 202:69] + node _T_3470 = cat(_T_3357[15], _T_3357[14]) @[lib.scala 202:69] + node _T_3471 = cat(_T_3357[18], _T_3357[17]) @[lib.scala 202:69] + node _T_3472 = cat(_T_3471, _T_3357[16]) @[lib.scala 202:69] + node _T_3473 = cat(_T_3472, _T_3470) @[lib.scala 202:69] + node _T_3474 = cat(_T_3473, _T_3469) @[lib.scala 202:69] + node _T_3475 = cat(_T_3474, _T_3465) @[lib.scala 202:69] + node _T_3476 = cat(_T_3357[20], _T_3357[19]) @[lib.scala 202:69] + node _T_3477 = cat(_T_3357[23], _T_3357[22]) @[lib.scala 202:69] + node _T_3478 = cat(_T_3477, _T_3357[21]) @[lib.scala 202:69] + node _T_3479 = cat(_T_3478, _T_3476) @[lib.scala 202:69] + node _T_3480 = cat(_T_3357[25], _T_3357[24]) @[lib.scala 202:69] + node _T_3481 = cat(_T_3357[28], _T_3357[27]) @[lib.scala 202:69] + node _T_3482 = cat(_T_3481, _T_3357[26]) @[lib.scala 202:69] + node _T_3483 = cat(_T_3482, _T_3480) @[lib.scala 202:69] + node _T_3484 = cat(_T_3483, _T_3479) @[lib.scala 202:69] + node _T_3485 = cat(_T_3357[30], _T_3357[29]) @[lib.scala 202:69] + node _T_3486 = cat(_T_3357[33], _T_3357[32]) @[lib.scala 202:69] + node _T_3487 = cat(_T_3486, _T_3357[31]) @[lib.scala 202:69] + node _T_3488 = cat(_T_3487, _T_3485) @[lib.scala 202:69] + node _T_3489 = cat(_T_3357[35], _T_3357[34]) @[lib.scala 202:69] + node _T_3490 = cat(_T_3357[38], _T_3357[37]) @[lib.scala 202:69] + node _T_3491 = cat(_T_3490, _T_3357[36]) @[lib.scala 202:69] + node _T_3492 = cat(_T_3491, _T_3489) @[lib.scala 202:69] + node _T_3493 = cat(_T_3492, _T_3488) @[lib.scala 202:69] + node _T_3494 = cat(_T_3493, _T_3484) @[lib.scala 202:69] + node _T_3495 = cat(_T_3494, _T_3475) @[lib.scala 202:69] + node _T_3496 = xor(_T_3495, _T_3456) @[lib.scala 202:76] + node _T_3497 = mux(_T_3457, _T_3496, _T_3456) @[lib.scala 202:31] + node _T_3498 = bits(_T_3497, 37, 32) @[lib.scala 204:37] + node _T_3499 = bits(_T_3497, 30, 16) @[lib.scala 204:61] + node _T_3500 = bits(_T_3497, 14, 8) @[lib.scala 204:86] + node _T_3501 = bits(_T_3497, 6, 4) @[lib.scala 204:110] + node _T_3502 = bits(_T_3497, 2, 2) @[lib.scala 204:133] node _T_3503 = cat(_T_3501, _T_3502) @[Cat.scala 29:58] node _T_3504 = cat(_T_3498, _T_3499) @[Cat.scala 29:58] node _T_3505 = cat(_T_3504, _T_3500) @[Cat.scala 29:58] node _T_3506 = cat(_T_3505, _T_3503) @[Cat.scala 29:58] - node _T_3507 = bits(_T_3497, 38, 38) @[el2_lib.scala 345:39] - node _T_3508 = bits(_T_3347, 6, 0) @[el2_lib.scala 345:56] - node _T_3509 = eq(_T_3508, UInt<7>("h040")) @[el2_lib.scala 345:62] - node _T_3510 = xor(_T_3507, _T_3509) @[el2_lib.scala 345:44] - node _T_3511 = bits(_T_3497, 31, 31) @[el2_lib.scala 345:102] - node _T_3512 = bits(_T_3497, 15, 15) @[el2_lib.scala 345:124] - node _T_3513 = bits(_T_3497, 7, 7) @[el2_lib.scala 345:146] - node _T_3514 = bits(_T_3497, 3, 3) @[el2_lib.scala 345:167] - node _T_3515 = bits(_T_3497, 1, 0) @[el2_lib.scala 345:188] + node _T_3507 = bits(_T_3497, 38, 38) @[lib.scala 205:39] + node _T_3508 = bits(_T_3347, 6, 0) @[lib.scala 205:56] + node _T_3509 = eq(_T_3508, UInt<7>("h040")) @[lib.scala 205:62] + node _T_3510 = xor(_T_3507, _T_3509) @[lib.scala 205:44] + node _T_3511 = bits(_T_3497, 31, 31) @[lib.scala 205:102] + node _T_3512 = bits(_T_3497, 15, 15) @[lib.scala 205:124] + node _T_3513 = bits(_T_3497, 7, 7) @[lib.scala 205:146] + node _T_3514 = bits(_T_3497, 3, 3) @[lib.scala 205:167] + node _T_3515 = bits(_T_3497, 1, 0) @[lib.scala 205:188] node _T_3516 = cat(_T_3513, _T_3514) @[Cat.scala 29:58] node _T_3517 = cat(_T_3516, _T_3515) @[Cat.scala 29:58] node _T_3518 = cat(_T_3510, _T_3511) @[Cat.scala 29:58] @@ -7487,443 +7487,443 @@ circuit quasar_wrapper : node _T_3521 = bits(iccm_ecc_word_enable, 1, 1) @[ifu_mem_ctl.scala 606:73] node _T_3522 = bits(io.iccm.rd_data_ecc, 70, 39) @[ifu_mem_ctl.scala 606:93] node _T_3523 = bits(io.iccm.rd_data_ecc, 77, 71) @[ifu_mem_ctl.scala 606:128] - wire _T_3524 : UInt<1>[18] @[el2_lib.scala 313:18] - wire _T_3525 : UInt<1>[18] @[el2_lib.scala 314:18] - wire _T_3526 : UInt<1>[18] @[el2_lib.scala 315:18] - wire _T_3527 : UInt<1>[15] @[el2_lib.scala 316:18] - wire _T_3528 : UInt<1>[15] @[el2_lib.scala 317:18] - wire _T_3529 : UInt<1>[6] @[el2_lib.scala 318:18] - node _T_3530 = bits(_T_3522, 0, 0) @[el2_lib.scala 325:36] - _T_3524[0] <= _T_3530 @[el2_lib.scala 325:30] - node _T_3531 = bits(_T_3522, 0, 0) @[el2_lib.scala 326:36] - _T_3525[0] <= _T_3531 @[el2_lib.scala 326:30] - node _T_3532 = bits(_T_3522, 1, 1) @[el2_lib.scala 325:36] - _T_3524[1] <= _T_3532 @[el2_lib.scala 325:30] - node _T_3533 = bits(_T_3522, 1, 1) @[el2_lib.scala 327:36] - _T_3526[0] <= _T_3533 @[el2_lib.scala 327:30] - node _T_3534 = bits(_T_3522, 2, 2) @[el2_lib.scala 326:36] - _T_3525[1] <= _T_3534 @[el2_lib.scala 326:30] - node _T_3535 = bits(_T_3522, 2, 2) @[el2_lib.scala 327:36] - _T_3526[1] <= _T_3535 @[el2_lib.scala 327:30] - node _T_3536 = bits(_T_3522, 3, 3) @[el2_lib.scala 325:36] - _T_3524[2] <= _T_3536 @[el2_lib.scala 325:30] - node _T_3537 = bits(_T_3522, 3, 3) @[el2_lib.scala 326:36] - _T_3525[2] <= _T_3537 @[el2_lib.scala 326:30] - node _T_3538 = bits(_T_3522, 3, 3) @[el2_lib.scala 327:36] - _T_3526[2] <= _T_3538 @[el2_lib.scala 327:30] - node _T_3539 = bits(_T_3522, 4, 4) @[el2_lib.scala 325:36] - _T_3524[3] <= _T_3539 @[el2_lib.scala 325:30] - node _T_3540 = bits(_T_3522, 4, 4) @[el2_lib.scala 328:36] - _T_3527[0] <= _T_3540 @[el2_lib.scala 328:30] - node _T_3541 = bits(_T_3522, 5, 5) @[el2_lib.scala 326:36] - _T_3525[3] <= _T_3541 @[el2_lib.scala 326:30] - node _T_3542 = bits(_T_3522, 5, 5) @[el2_lib.scala 328:36] - _T_3527[1] <= _T_3542 @[el2_lib.scala 328:30] - node _T_3543 = bits(_T_3522, 6, 6) @[el2_lib.scala 325:36] - _T_3524[4] <= _T_3543 @[el2_lib.scala 325:30] - node _T_3544 = bits(_T_3522, 6, 6) @[el2_lib.scala 326:36] - _T_3525[4] <= _T_3544 @[el2_lib.scala 326:30] - node _T_3545 = bits(_T_3522, 6, 6) @[el2_lib.scala 328:36] - _T_3527[2] <= _T_3545 @[el2_lib.scala 328:30] - node _T_3546 = bits(_T_3522, 7, 7) @[el2_lib.scala 327:36] - _T_3526[3] <= _T_3546 @[el2_lib.scala 327:30] - node _T_3547 = bits(_T_3522, 7, 7) @[el2_lib.scala 328:36] - _T_3527[3] <= _T_3547 @[el2_lib.scala 328:30] - node _T_3548 = bits(_T_3522, 8, 8) @[el2_lib.scala 325:36] - _T_3524[5] <= _T_3548 @[el2_lib.scala 325:30] - node _T_3549 = bits(_T_3522, 8, 8) @[el2_lib.scala 327:36] - _T_3526[4] <= _T_3549 @[el2_lib.scala 327:30] - node _T_3550 = bits(_T_3522, 8, 8) @[el2_lib.scala 328:36] - _T_3527[4] <= _T_3550 @[el2_lib.scala 328:30] - node _T_3551 = bits(_T_3522, 9, 9) @[el2_lib.scala 326:36] - _T_3525[5] <= _T_3551 @[el2_lib.scala 326:30] - node _T_3552 = bits(_T_3522, 9, 9) @[el2_lib.scala 327:36] - _T_3526[5] <= _T_3552 @[el2_lib.scala 327:30] - node _T_3553 = bits(_T_3522, 9, 9) @[el2_lib.scala 328:36] - _T_3527[5] <= _T_3553 @[el2_lib.scala 328:30] - node _T_3554 = bits(_T_3522, 10, 10) @[el2_lib.scala 325:36] - _T_3524[6] <= _T_3554 @[el2_lib.scala 325:30] - node _T_3555 = bits(_T_3522, 10, 10) @[el2_lib.scala 326:36] - _T_3525[6] <= _T_3555 @[el2_lib.scala 326:30] - node _T_3556 = bits(_T_3522, 10, 10) @[el2_lib.scala 327:36] - _T_3526[6] <= _T_3556 @[el2_lib.scala 327:30] - node _T_3557 = bits(_T_3522, 10, 10) @[el2_lib.scala 328:36] - _T_3527[6] <= _T_3557 @[el2_lib.scala 328:30] - node _T_3558 = bits(_T_3522, 11, 11) @[el2_lib.scala 325:36] - _T_3524[7] <= _T_3558 @[el2_lib.scala 325:30] - node _T_3559 = bits(_T_3522, 11, 11) @[el2_lib.scala 329:36] - _T_3528[0] <= _T_3559 @[el2_lib.scala 329:30] - node _T_3560 = bits(_T_3522, 12, 12) @[el2_lib.scala 326:36] - _T_3525[7] <= _T_3560 @[el2_lib.scala 326:30] - node _T_3561 = bits(_T_3522, 12, 12) @[el2_lib.scala 329:36] - _T_3528[1] <= _T_3561 @[el2_lib.scala 329:30] - node _T_3562 = bits(_T_3522, 13, 13) @[el2_lib.scala 325:36] - _T_3524[8] <= _T_3562 @[el2_lib.scala 325:30] - node _T_3563 = bits(_T_3522, 13, 13) @[el2_lib.scala 326:36] - _T_3525[8] <= _T_3563 @[el2_lib.scala 326:30] - node _T_3564 = bits(_T_3522, 13, 13) @[el2_lib.scala 329:36] - _T_3528[2] <= _T_3564 @[el2_lib.scala 329:30] - node _T_3565 = bits(_T_3522, 14, 14) @[el2_lib.scala 327:36] - _T_3526[7] <= _T_3565 @[el2_lib.scala 327:30] - node _T_3566 = bits(_T_3522, 14, 14) @[el2_lib.scala 329:36] - _T_3528[3] <= _T_3566 @[el2_lib.scala 329:30] - node _T_3567 = bits(_T_3522, 15, 15) @[el2_lib.scala 325:36] - _T_3524[9] <= _T_3567 @[el2_lib.scala 325:30] - node _T_3568 = bits(_T_3522, 15, 15) @[el2_lib.scala 327:36] - _T_3526[8] <= _T_3568 @[el2_lib.scala 327:30] - node _T_3569 = bits(_T_3522, 15, 15) @[el2_lib.scala 329:36] - _T_3528[4] <= _T_3569 @[el2_lib.scala 329:30] - node _T_3570 = bits(_T_3522, 16, 16) @[el2_lib.scala 326:36] - _T_3525[9] <= _T_3570 @[el2_lib.scala 326:30] - node _T_3571 = bits(_T_3522, 16, 16) @[el2_lib.scala 327:36] - _T_3526[9] <= _T_3571 @[el2_lib.scala 327:30] - node _T_3572 = bits(_T_3522, 16, 16) @[el2_lib.scala 329:36] - _T_3528[5] <= _T_3572 @[el2_lib.scala 329:30] - node _T_3573 = bits(_T_3522, 17, 17) @[el2_lib.scala 325:36] - _T_3524[10] <= _T_3573 @[el2_lib.scala 325:30] - node _T_3574 = bits(_T_3522, 17, 17) @[el2_lib.scala 326:36] - _T_3525[10] <= _T_3574 @[el2_lib.scala 326:30] - node _T_3575 = bits(_T_3522, 17, 17) @[el2_lib.scala 327:36] - _T_3526[10] <= _T_3575 @[el2_lib.scala 327:30] - node _T_3576 = bits(_T_3522, 17, 17) @[el2_lib.scala 329:36] - _T_3528[6] <= _T_3576 @[el2_lib.scala 329:30] - node _T_3577 = bits(_T_3522, 18, 18) @[el2_lib.scala 328:36] - _T_3527[7] <= _T_3577 @[el2_lib.scala 328:30] - node _T_3578 = bits(_T_3522, 18, 18) @[el2_lib.scala 329:36] - _T_3528[7] <= _T_3578 @[el2_lib.scala 329:30] - node _T_3579 = bits(_T_3522, 19, 19) @[el2_lib.scala 325:36] - _T_3524[11] <= _T_3579 @[el2_lib.scala 325:30] - node _T_3580 = bits(_T_3522, 19, 19) @[el2_lib.scala 328:36] - _T_3527[8] <= _T_3580 @[el2_lib.scala 328:30] - node _T_3581 = bits(_T_3522, 19, 19) @[el2_lib.scala 329:36] - _T_3528[8] <= _T_3581 @[el2_lib.scala 329:30] - node _T_3582 = bits(_T_3522, 20, 20) @[el2_lib.scala 326:36] - _T_3525[11] <= _T_3582 @[el2_lib.scala 326:30] - node _T_3583 = bits(_T_3522, 20, 20) @[el2_lib.scala 328:36] - _T_3527[9] <= _T_3583 @[el2_lib.scala 328:30] - node _T_3584 = bits(_T_3522, 20, 20) @[el2_lib.scala 329:36] - _T_3528[9] <= _T_3584 @[el2_lib.scala 329:30] - node _T_3585 = bits(_T_3522, 21, 21) @[el2_lib.scala 325:36] - _T_3524[12] <= _T_3585 @[el2_lib.scala 325:30] - node _T_3586 = bits(_T_3522, 21, 21) @[el2_lib.scala 326:36] - _T_3525[12] <= _T_3586 @[el2_lib.scala 326:30] - node _T_3587 = bits(_T_3522, 21, 21) @[el2_lib.scala 328:36] - _T_3527[10] <= _T_3587 @[el2_lib.scala 328:30] - node _T_3588 = bits(_T_3522, 21, 21) @[el2_lib.scala 329:36] - _T_3528[10] <= _T_3588 @[el2_lib.scala 329:30] - node _T_3589 = bits(_T_3522, 22, 22) @[el2_lib.scala 327:36] - _T_3526[11] <= _T_3589 @[el2_lib.scala 327:30] - node _T_3590 = bits(_T_3522, 22, 22) @[el2_lib.scala 328:36] - _T_3527[11] <= _T_3590 @[el2_lib.scala 328:30] - node _T_3591 = bits(_T_3522, 22, 22) @[el2_lib.scala 329:36] - _T_3528[11] <= _T_3591 @[el2_lib.scala 329:30] - node _T_3592 = bits(_T_3522, 23, 23) @[el2_lib.scala 325:36] - _T_3524[13] <= _T_3592 @[el2_lib.scala 325:30] - node _T_3593 = bits(_T_3522, 23, 23) @[el2_lib.scala 327:36] - _T_3526[12] <= _T_3593 @[el2_lib.scala 327:30] - node _T_3594 = bits(_T_3522, 23, 23) @[el2_lib.scala 328:36] - _T_3527[12] <= _T_3594 @[el2_lib.scala 328:30] - node _T_3595 = bits(_T_3522, 23, 23) @[el2_lib.scala 329:36] - _T_3528[12] <= _T_3595 @[el2_lib.scala 329:30] - node _T_3596 = bits(_T_3522, 24, 24) @[el2_lib.scala 326:36] - _T_3525[13] <= _T_3596 @[el2_lib.scala 326:30] - node _T_3597 = bits(_T_3522, 24, 24) @[el2_lib.scala 327:36] - _T_3526[13] <= _T_3597 @[el2_lib.scala 327:30] - node _T_3598 = bits(_T_3522, 24, 24) @[el2_lib.scala 328:36] - _T_3527[13] <= _T_3598 @[el2_lib.scala 328:30] - node _T_3599 = bits(_T_3522, 24, 24) @[el2_lib.scala 329:36] - _T_3528[13] <= _T_3599 @[el2_lib.scala 329:30] - node _T_3600 = bits(_T_3522, 25, 25) @[el2_lib.scala 325:36] - _T_3524[14] <= _T_3600 @[el2_lib.scala 325:30] - node _T_3601 = bits(_T_3522, 25, 25) @[el2_lib.scala 326:36] - _T_3525[14] <= _T_3601 @[el2_lib.scala 326:30] - node _T_3602 = bits(_T_3522, 25, 25) @[el2_lib.scala 327:36] - _T_3526[14] <= _T_3602 @[el2_lib.scala 327:30] - node _T_3603 = bits(_T_3522, 25, 25) @[el2_lib.scala 328:36] - _T_3527[14] <= _T_3603 @[el2_lib.scala 328:30] - node _T_3604 = bits(_T_3522, 25, 25) @[el2_lib.scala 329:36] - _T_3528[14] <= _T_3604 @[el2_lib.scala 329:30] - node _T_3605 = bits(_T_3522, 26, 26) @[el2_lib.scala 325:36] - _T_3524[15] <= _T_3605 @[el2_lib.scala 325:30] - node _T_3606 = bits(_T_3522, 26, 26) @[el2_lib.scala 330:36] - _T_3529[0] <= _T_3606 @[el2_lib.scala 330:30] - node _T_3607 = bits(_T_3522, 27, 27) @[el2_lib.scala 326:36] - _T_3525[15] <= _T_3607 @[el2_lib.scala 326:30] - node _T_3608 = bits(_T_3522, 27, 27) @[el2_lib.scala 330:36] - _T_3529[1] <= _T_3608 @[el2_lib.scala 330:30] - node _T_3609 = bits(_T_3522, 28, 28) @[el2_lib.scala 325:36] - _T_3524[16] <= _T_3609 @[el2_lib.scala 325:30] - node _T_3610 = bits(_T_3522, 28, 28) @[el2_lib.scala 326:36] - _T_3525[16] <= _T_3610 @[el2_lib.scala 326:30] - node _T_3611 = bits(_T_3522, 28, 28) @[el2_lib.scala 330:36] - _T_3529[2] <= _T_3611 @[el2_lib.scala 330:30] - node _T_3612 = bits(_T_3522, 29, 29) @[el2_lib.scala 327:36] - _T_3526[15] <= _T_3612 @[el2_lib.scala 327:30] - node _T_3613 = bits(_T_3522, 29, 29) @[el2_lib.scala 330:36] - _T_3529[3] <= _T_3613 @[el2_lib.scala 330:30] - node _T_3614 = bits(_T_3522, 30, 30) @[el2_lib.scala 325:36] - _T_3524[17] <= _T_3614 @[el2_lib.scala 325:30] - node _T_3615 = bits(_T_3522, 30, 30) @[el2_lib.scala 327:36] - _T_3526[16] <= _T_3615 @[el2_lib.scala 327:30] - node _T_3616 = bits(_T_3522, 30, 30) @[el2_lib.scala 330:36] - _T_3529[4] <= _T_3616 @[el2_lib.scala 330:30] - node _T_3617 = bits(_T_3522, 31, 31) @[el2_lib.scala 326:36] - _T_3525[17] <= _T_3617 @[el2_lib.scala 326:30] - node _T_3618 = bits(_T_3522, 31, 31) @[el2_lib.scala 327:36] - _T_3526[17] <= _T_3618 @[el2_lib.scala 327:30] - node _T_3619 = bits(_T_3522, 31, 31) @[el2_lib.scala 330:36] - _T_3529[5] <= _T_3619 @[el2_lib.scala 330:30] - node _T_3620 = xorr(_T_3522) @[el2_lib.scala 333:30] - node _T_3621 = xorr(_T_3523) @[el2_lib.scala 333:44] - node _T_3622 = xor(_T_3620, _T_3621) @[el2_lib.scala 333:35] - node _T_3623 = not(UInt<1>("h00")) @[el2_lib.scala 333:52] - node _T_3624 = and(_T_3622, _T_3623) @[el2_lib.scala 333:50] - node _T_3625 = bits(_T_3523, 5, 5) @[el2_lib.scala 333:68] - node _T_3626 = cat(_T_3529[2], _T_3529[1]) @[el2_lib.scala 333:76] - node _T_3627 = cat(_T_3626, _T_3529[0]) @[el2_lib.scala 333:76] - node _T_3628 = cat(_T_3529[5], _T_3529[4]) @[el2_lib.scala 333:76] - node _T_3629 = cat(_T_3628, _T_3529[3]) @[el2_lib.scala 333:76] - node _T_3630 = cat(_T_3629, _T_3627) @[el2_lib.scala 333:76] - node _T_3631 = xorr(_T_3630) @[el2_lib.scala 333:83] - node _T_3632 = xor(_T_3625, _T_3631) @[el2_lib.scala 333:71] - node _T_3633 = bits(_T_3523, 4, 4) @[el2_lib.scala 333:95] - node _T_3634 = cat(_T_3528[2], _T_3528[1]) @[el2_lib.scala 333:103] - node _T_3635 = cat(_T_3634, _T_3528[0]) @[el2_lib.scala 333:103] - node _T_3636 = cat(_T_3528[4], _T_3528[3]) @[el2_lib.scala 333:103] - node _T_3637 = cat(_T_3528[6], _T_3528[5]) @[el2_lib.scala 333:103] - node _T_3638 = cat(_T_3637, _T_3636) @[el2_lib.scala 333:103] - node _T_3639 = cat(_T_3638, _T_3635) @[el2_lib.scala 333:103] - node _T_3640 = cat(_T_3528[8], _T_3528[7]) @[el2_lib.scala 333:103] - node _T_3641 = cat(_T_3528[10], _T_3528[9]) @[el2_lib.scala 333:103] - node _T_3642 = cat(_T_3641, _T_3640) @[el2_lib.scala 333:103] - node _T_3643 = cat(_T_3528[12], _T_3528[11]) @[el2_lib.scala 333:103] - node _T_3644 = cat(_T_3528[14], _T_3528[13]) @[el2_lib.scala 333:103] - node _T_3645 = cat(_T_3644, _T_3643) @[el2_lib.scala 333:103] - node _T_3646 = cat(_T_3645, _T_3642) @[el2_lib.scala 333:103] - node _T_3647 = cat(_T_3646, _T_3639) @[el2_lib.scala 333:103] - node _T_3648 = xorr(_T_3647) @[el2_lib.scala 333:110] - node _T_3649 = xor(_T_3633, _T_3648) @[el2_lib.scala 333:98] - node _T_3650 = bits(_T_3523, 3, 3) @[el2_lib.scala 333:122] - node _T_3651 = cat(_T_3527[2], _T_3527[1]) @[el2_lib.scala 333:130] - node _T_3652 = cat(_T_3651, _T_3527[0]) @[el2_lib.scala 333:130] - node _T_3653 = cat(_T_3527[4], _T_3527[3]) @[el2_lib.scala 333:130] - node _T_3654 = cat(_T_3527[6], _T_3527[5]) @[el2_lib.scala 333:130] - node _T_3655 = cat(_T_3654, _T_3653) @[el2_lib.scala 333:130] - node _T_3656 = cat(_T_3655, _T_3652) @[el2_lib.scala 333:130] - node _T_3657 = cat(_T_3527[8], _T_3527[7]) @[el2_lib.scala 333:130] - node _T_3658 = cat(_T_3527[10], _T_3527[9]) @[el2_lib.scala 333:130] - node _T_3659 = cat(_T_3658, _T_3657) @[el2_lib.scala 333:130] - node _T_3660 = cat(_T_3527[12], _T_3527[11]) @[el2_lib.scala 333:130] - node _T_3661 = cat(_T_3527[14], _T_3527[13]) @[el2_lib.scala 333:130] - node _T_3662 = cat(_T_3661, _T_3660) @[el2_lib.scala 333:130] - node _T_3663 = cat(_T_3662, _T_3659) @[el2_lib.scala 333:130] - node _T_3664 = cat(_T_3663, _T_3656) @[el2_lib.scala 333:130] - node _T_3665 = xorr(_T_3664) @[el2_lib.scala 333:137] - node _T_3666 = xor(_T_3650, _T_3665) @[el2_lib.scala 333:125] - node _T_3667 = bits(_T_3523, 2, 2) @[el2_lib.scala 333:149] - node _T_3668 = cat(_T_3526[1], _T_3526[0]) @[el2_lib.scala 333:157] - node _T_3669 = cat(_T_3526[3], _T_3526[2]) @[el2_lib.scala 333:157] - node _T_3670 = cat(_T_3669, _T_3668) @[el2_lib.scala 333:157] - node _T_3671 = cat(_T_3526[5], _T_3526[4]) @[el2_lib.scala 333:157] - node _T_3672 = cat(_T_3526[8], _T_3526[7]) @[el2_lib.scala 333:157] - node _T_3673 = cat(_T_3672, _T_3526[6]) @[el2_lib.scala 333:157] - node _T_3674 = cat(_T_3673, _T_3671) @[el2_lib.scala 333:157] - node _T_3675 = cat(_T_3674, _T_3670) @[el2_lib.scala 333:157] - node _T_3676 = cat(_T_3526[10], _T_3526[9]) @[el2_lib.scala 333:157] - node _T_3677 = cat(_T_3526[12], _T_3526[11]) @[el2_lib.scala 333:157] - node _T_3678 = cat(_T_3677, _T_3676) @[el2_lib.scala 333:157] - node _T_3679 = cat(_T_3526[14], _T_3526[13]) @[el2_lib.scala 333:157] - node _T_3680 = cat(_T_3526[17], _T_3526[16]) @[el2_lib.scala 333:157] - node _T_3681 = cat(_T_3680, _T_3526[15]) @[el2_lib.scala 333:157] - node _T_3682 = cat(_T_3681, _T_3679) @[el2_lib.scala 333:157] - node _T_3683 = cat(_T_3682, _T_3678) @[el2_lib.scala 333:157] - node _T_3684 = cat(_T_3683, _T_3675) @[el2_lib.scala 333:157] - node _T_3685 = xorr(_T_3684) @[el2_lib.scala 333:164] - node _T_3686 = xor(_T_3667, _T_3685) @[el2_lib.scala 333:152] - node _T_3687 = bits(_T_3523, 1, 1) @[el2_lib.scala 333:176] - node _T_3688 = cat(_T_3525[1], _T_3525[0]) @[el2_lib.scala 333:184] - node _T_3689 = cat(_T_3525[3], _T_3525[2]) @[el2_lib.scala 333:184] - node _T_3690 = cat(_T_3689, _T_3688) @[el2_lib.scala 333:184] - node _T_3691 = cat(_T_3525[5], _T_3525[4]) @[el2_lib.scala 333:184] - node _T_3692 = cat(_T_3525[8], _T_3525[7]) @[el2_lib.scala 333:184] - node _T_3693 = cat(_T_3692, _T_3525[6]) @[el2_lib.scala 333:184] - node _T_3694 = cat(_T_3693, _T_3691) @[el2_lib.scala 333:184] - node _T_3695 = cat(_T_3694, _T_3690) @[el2_lib.scala 333:184] - node _T_3696 = cat(_T_3525[10], _T_3525[9]) @[el2_lib.scala 333:184] - node _T_3697 = cat(_T_3525[12], _T_3525[11]) @[el2_lib.scala 333:184] - node _T_3698 = cat(_T_3697, _T_3696) @[el2_lib.scala 333:184] - node _T_3699 = cat(_T_3525[14], _T_3525[13]) @[el2_lib.scala 333:184] - node _T_3700 = cat(_T_3525[17], _T_3525[16]) @[el2_lib.scala 333:184] - node _T_3701 = cat(_T_3700, _T_3525[15]) @[el2_lib.scala 333:184] - node _T_3702 = cat(_T_3701, _T_3699) @[el2_lib.scala 333:184] - node _T_3703 = cat(_T_3702, _T_3698) @[el2_lib.scala 333:184] - node _T_3704 = cat(_T_3703, _T_3695) @[el2_lib.scala 333:184] - node _T_3705 = xorr(_T_3704) @[el2_lib.scala 333:191] - node _T_3706 = xor(_T_3687, _T_3705) @[el2_lib.scala 333:179] - node _T_3707 = bits(_T_3523, 0, 0) @[el2_lib.scala 333:203] - node _T_3708 = cat(_T_3524[1], _T_3524[0]) @[el2_lib.scala 333:211] - node _T_3709 = cat(_T_3524[3], _T_3524[2]) @[el2_lib.scala 333:211] - node _T_3710 = cat(_T_3709, _T_3708) @[el2_lib.scala 333:211] - node _T_3711 = cat(_T_3524[5], _T_3524[4]) @[el2_lib.scala 333:211] - node _T_3712 = cat(_T_3524[8], _T_3524[7]) @[el2_lib.scala 333:211] - node _T_3713 = cat(_T_3712, _T_3524[6]) @[el2_lib.scala 333:211] - node _T_3714 = cat(_T_3713, _T_3711) @[el2_lib.scala 333:211] - node _T_3715 = cat(_T_3714, _T_3710) @[el2_lib.scala 333:211] - node _T_3716 = cat(_T_3524[10], _T_3524[9]) @[el2_lib.scala 333:211] - node _T_3717 = cat(_T_3524[12], _T_3524[11]) @[el2_lib.scala 333:211] - node _T_3718 = cat(_T_3717, _T_3716) @[el2_lib.scala 333:211] - node _T_3719 = cat(_T_3524[14], _T_3524[13]) @[el2_lib.scala 333:211] - node _T_3720 = cat(_T_3524[17], _T_3524[16]) @[el2_lib.scala 333:211] - node _T_3721 = cat(_T_3720, _T_3524[15]) @[el2_lib.scala 333:211] - node _T_3722 = cat(_T_3721, _T_3719) @[el2_lib.scala 333:211] - node _T_3723 = cat(_T_3722, _T_3718) @[el2_lib.scala 333:211] - node _T_3724 = cat(_T_3723, _T_3715) @[el2_lib.scala 333:211] - node _T_3725 = xorr(_T_3724) @[el2_lib.scala 333:218] - node _T_3726 = xor(_T_3707, _T_3725) @[el2_lib.scala 333:206] + wire _T_3524 : UInt<1>[18] @[lib.scala 173:18] + wire _T_3525 : UInt<1>[18] @[lib.scala 174:18] + wire _T_3526 : UInt<1>[18] @[lib.scala 175:18] + wire _T_3527 : UInt<1>[15] @[lib.scala 176:18] + wire _T_3528 : UInt<1>[15] @[lib.scala 177:18] + wire _T_3529 : UInt<1>[6] @[lib.scala 178:18] + node _T_3530 = bits(_T_3522, 0, 0) @[lib.scala 185:36] + _T_3524[0] <= _T_3530 @[lib.scala 185:30] + node _T_3531 = bits(_T_3522, 0, 0) @[lib.scala 186:36] + _T_3525[0] <= _T_3531 @[lib.scala 186:30] + node _T_3532 = bits(_T_3522, 1, 1) @[lib.scala 185:36] + _T_3524[1] <= _T_3532 @[lib.scala 185:30] + node _T_3533 = bits(_T_3522, 1, 1) @[lib.scala 187:36] + _T_3526[0] <= _T_3533 @[lib.scala 187:30] + node _T_3534 = bits(_T_3522, 2, 2) @[lib.scala 186:36] + _T_3525[1] <= _T_3534 @[lib.scala 186:30] + node _T_3535 = bits(_T_3522, 2, 2) @[lib.scala 187:36] + _T_3526[1] <= _T_3535 @[lib.scala 187:30] + node _T_3536 = bits(_T_3522, 3, 3) @[lib.scala 185:36] + _T_3524[2] <= _T_3536 @[lib.scala 185:30] + node _T_3537 = bits(_T_3522, 3, 3) @[lib.scala 186:36] + _T_3525[2] <= _T_3537 @[lib.scala 186:30] + node _T_3538 = bits(_T_3522, 3, 3) @[lib.scala 187:36] + _T_3526[2] <= _T_3538 @[lib.scala 187:30] + node _T_3539 = bits(_T_3522, 4, 4) @[lib.scala 185:36] + _T_3524[3] <= _T_3539 @[lib.scala 185:30] + node _T_3540 = bits(_T_3522, 4, 4) @[lib.scala 188:36] + _T_3527[0] <= _T_3540 @[lib.scala 188:30] + node _T_3541 = bits(_T_3522, 5, 5) @[lib.scala 186:36] + _T_3525[3] <= _T_3541 @[lib.scala 186:30] + node _T_3542 = bits(_T_3522, 5, 5) @[lib.scala 188:36] + _T_3527[1] <= _T_3542 @[lib.scala 188:30] + node _T_3543 = bits(_T_3522, 6, 6) @[lib.scala 185:36] + _T_3524[4] <= _T_3543 @[lib.scala 185:30] + node _T_3544 = bits(_T_3522, 6, 6) @[lib.scala 186:36] + _T_3525[4] <= _T_3544 @[lib.scala 186:30] + node _T_3545 = bits(_T_3522, 6, 6) @[lib.scala 188:36] + _T_3527[2] <= _T_3545 @[lib.scala 188:30] + node _T_3546 = bits(_T_3522, 7, 7) @[lib.scala 187:36] + _T_3526[3] <= _T_3546 @[lib.scala 187:30] + node _T_3547 = bits(_T_3522, 7, 7) @[lib.scala 188:36] + _T_3527[3] <= _T_3547 @[lib.scala 188:30] + node _T_3548 = bits(_T_3522, 8, 8) @[lib.scala 185:36] + _T_3524[5] <= _T_3548 @[lib.scala 185:30] + node _T_3549 = bits(_T_3522, 8, 8) @[lib.scala 187:36] + _T_3526[4] <= _T_3549 @[lib.scala 187:30] + node _T_3550 = bits(_T_3522, 8, 8) @[lib.scala 188:36] + _T_3527[4] <= _T_3550 @[lib.scala 188:30] + node _T_3551 = bits(_T_3522, 9, 9) @[lib.scala 186:36] + _T_3525[5] <= _T_3551 @[lib.scala 186:30] + node _T_3552 = bits(_T_3522, 9, 9) @[lib.scala 187:36] + _T_3526[5] <= _T_3552 @[lib.scala 187:30] + node _T_3553 = bits(_T_3522, 9, 9) @[lib.scala 188:36] + _T_3527[5] <= _T_3553 @[lib.scala 188:30] + node _T_3554 = bits(_T_3522, 10, 10) @[lib.scala 185:36] + _T_3524[6] <= _T_3554 @[lib.scala 185:30] + node _T_3555 = bits(_T_3522, 10, 10) @[lib.scala 186:36] + _T_3525[6] <= _T_3555 @[lib.scala 186:30] + node _T_3556 = bits(_T_3522, 10, 10) @[lib.scala 187:36] + _T_3526[6] <= _T_3556 @[lib.scala 187:30] + node _T_3557 = bits(_T_3522, 10, 10) @[lib.scala 188:36] + _T_3527[6] <= _T_3557 @[lib.scala 188:30] + node _T_3558 = bits(_T_3522, 11, 11) @[lib.scala 185:36] + _T_3524[7] <= _T_3558 @[lib.scala 185:30] + node _T_3559 = bits(_T_3522, 11, 11) @[lib.scala 189:36] + _T_3528[0] <= _T_3559 @[lib.scala 189:30] + node _T_3560 = bits(_T_3522, 12, 12) @[lib.scala 186:36] + _T_3525[7] <= _T_3560 @[lib.scala 186:30] + node _T_3561 = bits(_T_3522, 12, 12) @[lib.scala 189:36] + _T_3528[1] <= _T_3561 @[lib.scala 189:30] + node _T_3562 = bits(_T_3522, 13, 13) @[lib.scala 185:36] + _T_3524[8] <= _T_3562 @[lib.scala 185:30] + node _T_3563 = bits(_T_3522, 13, 13) @[lib.scala 186:36] + _T_3525[8] <= _T_3563 @[lib.scala 186:30] + node _T_3564 = bits(_T_3522, 13, 13) @[lib.scala 189:36] + _T_3528[2] <= _T_3564 @[lib.scala 189:30] + node _T_3565 = bits(_T_3522, 14, 14) @[lib.scala 187:36] + _T_3526[7] <= _T_3565 @[lib.scala 187:30] + node _T_3566 = bits(_T_3522, 14, 14) @[lib.scala 189:36] + _T_3528[3] <= _T_3566 @[lib.scala 189:30] + node _T_3567 = bits(_T_3522, 15, 15) @[lib.scala 185:36] + _T_3524[9] <= _T_3567 @[lib.scala 185:30] + node _T_3568 = bits(_T_3522, 15, 15) @[lib.scala 187:36] + _T_3526[8] <= _T_3568 @[lib.scala 187:30] + node _T_3569 = bits(_T_3522, 15, 15) @[lib.scala 189:36] + _T_3528[4] <= _T_3569 @[lib.scala 189:30] + node _T_3570 = bits(_T_3522, 16, 16) @[lib.scala 186:36] + _T_3525[9] <= _T_3570 @[lib.scala 186:30] + node _T_3571 = bits(_T_3522, 16, 16) @[lib.scala 187:36] + _T_3526[9] <= _T_3571 @[lib.scala 187:30] + node _T_3572 = bits(_T_3522, 16, 16) @[lib.scala 189:36] + _T_3528[5] <= _T_3572 @[lib.scala 189:30] + node _T_3573 = bits(_T_3522, 17, 17) @[lib.scala 185:36] + _T_3524[10] <= _T_3573 @[lib.scala 185:30] + node _T_3574 = bits(_T_3522, 17, 17) @[lib.scala 186:36] + _T_3525[10] <= _T_3574 @[lib.scala 186:30] + node _T_3575 = bits(_T_3522, 17, 17) @[lib.scala 187:36] + _T_3526[10] <= _T_3575 @[lib.scala 187:30] + node _T_3576 = bits(_T_3522, 17, 17) @[lib.scala 189:36] + _T_3528[6] <= _T_3576 @[lib.scala 189:30] + node _T_3577 = bits(_T_3522, 18, 18) @[lib.scala 188:36] + _T_3527[7] <= _T_3577 @[lib.scala 188:30] + node _T_3578 = bits(_T_3522, 18, 18) @[lib.scala 189:36] + _T_3528[7] <= _T_3578 @[lib.scala 189:30] + node _T_3579 = bits(_T_3522, 19, 19) @[lib.scala 185:36] + _T_3524[11] <= _T_3579 @[lib.scala 185:30] + node _T_3580 = bits(_T_3522, 19, 19) @[lib.scala 188:36] + _T_3527[8] <= _T_3580 @[lib.scala 188:30] + node _T_3581 = bits(_T_3522, 19, 19) @[lib.scala 189:36] + _T_3528[8] <= _T_3581 @[lib.scala 189:30] + node _T_3582 = bits(_T_3522, 20, 20) @[lib.scala 186:36] + _T_3525[11] <= _T_3582 @[lib.scala 186:30] + node _T_3583 = bits(_T_3522, 20, 20) @[lib.scala 188:36] + _T_3527[9] <= _T_3583 @[lib.scala 188:30] + node _T_3584 = bits(_T_3522, 20, 20) @[lib.scala 189:36] + _T_3528[9] <= _T_3584 @[lib.scala 189:30] + node _T_3585 = bits(_T_3522, 21, 21) @[lib.scala 185:36] + _T_3524[12] <= _T_3585 @[lib.scala 185:30] + node _T_3586 = bits(_T_3522, 21, 21) @[lib.scala 186:36] + _T_3525[12] <= _T_3586 @[lib.scala 186:30] + node _T_3587 = bits(_T_3522, 21, 21) @[lib.scala 188:36] + _T_3527[10] <= _T_3587 @[lib.scala 188:30] + node _T_3588 = bits(_T_3522, 21, 21) @[lib.scala 189:36] + _T_3528[10] <= _T_3588 @[lib.scala 189:30] + node _T_3589 = bits(_T_3522, 22, 22) @[lib.scala 187:36] + _T_3526[11] <= _T_3589 @[lib.scala 187:30] + node _T_3590 = bits(_T_3522, 22, 22) @[lib.scala 188:36] + _T_3527[11] <= _T_3590 @[lib.scala 188:30] + node _T_3591 = bits(_T_3522, 22, 22) @[lib.scala 189:36] + _T_3528[11] <= _T_3591 @[lib.scala 189:30] + node _T_3592 = bits(_T_3522, 23, 23) @[lib.scala 185:36] + _T_3524[13] <= _T_3592 @[lib.scala 185:30] + node _T_3593 = bits(_T_3522, 23, 23) @[lib.scala 187:36] + _T_3526[12] <= _T_3593 @[lib.scala 187:30] + node _T_3594 = bits(_T_3522, 23, 23) @[lib.scala 188:36] + _T_3527[12] <= _T_3594 @[lib.scala 188:30] + node _T_3595 = bits(_T_3522, 23, 23) @[lib.scala 189:36] + _T_3528[12] <= _T_3595 @[lib.scala 189:30] + node _T_3596 = bits(_T_3522, 24, 24) @[lib.scala 186:36] + _T_3525[13] <= _T_3596 @[lib.scala 186:30] + node _T_3597 = bits(_T_3522, 24, 24) @[lib.scala 187:36] + _T_3526[13] <= _T_3597 @[lib.scala 187:30] + node _T_3598 = bits(_T_3522, 24, 24) @[lib.scala 188:36] + _T_3527[13] <= _T_3598 @[lib.scala 188:30] + node _T_3599 = bits(_T_3522, 24, 24) @[lib.scala 189:36] + _T_3528[13] <= _T_3599 @[lib.scala 189:30] + node _T_3600 = bits(_T_3522, 25, 25) @[lib.scala 185:36] + _T_3524[14] <= _T_3600 @[lib.scala 185:30] + node _T_3601 = bits(_T_3522, 25, 25) @[lib.scala 186:36] + _T_3525[14] <= _T_3601 @[lib.scala 186:30] + node _T_3602 = bits(_T_3522, 25, 25) @[lib.scala 187:36] + _T_3526[14] <= _T_3602 @[lib.scala 187:30] + node _T_3603 = bits(_T_3522, 25, 25) @[lib.scala 188:36] + _T_3527[14] <= _T_3603 @[lib.scala 188:30] + node _T_3604 = bits(_T_3522, 25, 25) @[lib.scala 189:36] + _T_3528[14] <= _T_3604 @[lib.scala 189:30] + node _T_3605 = bits(_T_3522, 26, 26) @[lib.scala 185:36] + _T_3524[15] <= _T_3605 @[lib.scala 185:30] + node _T_3606 = bits(_T_3522, 26, 26) @[lib.scala 190:36] + _T_3529[0] <= _T_3606 @[lib.scala 190:30] + node _T_3607 = bits(_T_3522, 27, 27) @[lib.scala 186:36] + _T_3525[15] <= _T_3607 @[lib.scala 186:30] + node _T_3608 = bits(_T_3522, 27, 27) @[lib.scala 190:36] + _T_3529[1] <= _T_3608 @[lib.scala 190:30] + node _T_3609 = bits(_T_3522, 28, 28) @[lib.scala 185:36] + _T_3524[16] <= _T_3609 @[lib.scala 185:30] + node _T_3610 = bits(_T_3522, 28, 28) @[lib.scala 186:36] + _T_3525[16] <= _T_3610 @[lib.scala 186:30] + node _T_3611 = bits(_T_3522, 28, 28) @[lib.scala 190:36] + _T_3529[2] <= _T_3611 @[lib.scala 190:30] + node _T_3612 = bits(_T_3522, 29, 29) @[lib.scala 187:36] + _T_3526[15] <= _T_3612 @[lib.scala 187:30] + node _T_3613 = bits(_T_3522, 29, 29) @[lib.scala 190:36] + _T_3529[3] <= _T_3613 @[lib.scala 190:30] + node _T_3614 = bits(_T_3522, 30, 30) @[lib.scala 185:36] + _T_3524[17] <= _T_3614 @[lib.scala 185:30] + node _T_3615 = bits(_T_3522, 30, 30) @[lib.scala 187:36] + _T_3526[16] <= _T_3615 @[lib.scala 187:30] + node _T_3616 = bits(_T_3522, 30, 30) @[lib.scala 190:36] + _T_3529[4] <= _T_3616 @[lib.scala 190:30] + node _T_3617 = bits(_T_3522, 31, 31) @[lib.scala 186:36] + _T_3525[17] <= _T_3617 @[lib.scala 186:30] + node _T_3618 = bits(_T_3522, 31, 31) @[lib.scala 187:36] + _T_3526[17] <= _T_3618 @[lib.scala 187:30] + node _T_3619 = bits(_T_3522, 31, 31) @[lib.scala 190:36] + _T_3529[5] <= _T_3619 @[lib.scala 190:30] + node _T_3620 = xorr(_T_3522) @[lib.scala 193:30] + node _T_3621 = xorr(_T_3523) @[lib.scala 193:44] + node _T_3622 = xor(_T_3620, _T_3621) @[lib.scala 193:35] + node _T_3623 = not(UInt<1>("h00")) @[lib.scala 193:52] + node _T_3624 = and(_T_3622, _T_3623) @[lib.scala 193:50] + node _T_3625 = bits(_T_3523, 5, 5) @[lib.scala 193:68] + node _T_3626 = cat(_T_3529[2], _T_3529[1]) @[lib.scala 193:76] + node _T_3627 = cat(_T_3626, _T_3529[0]) @[lib.scala 193:76] + node _T_3628 = cat(_T_3529[5], _T_3529[4]) @[lib.scala 193:76] + node _T_3629 = cat(_T_3628, _T_3529[3]) @[lib.scala 193:76] + node _T_3630 = cat(_T_3629, _T_3627) @[lib.scala 193:76] + node _T_3631 = xorr(_T_3630) @[lib.scala 193:83] + node _T_3632 = xor(_T_3625, _T_3631) @[lib.scala 193:71] + node _T_3633 = bits(_T_3523, 4, 4) @[lib.scala 193:95] + node _T_3634 = cat(_T_3528[2], _T_3528[1]) @[lib.scala 193:103] + node _T_3635 = cat(_T_3634, _T_3528[0]) @[lib.scala 193:103] + node _T_3636 = cat(_T_3528[4], _T_3528[3]) @[lib.scala 193:103] + node _T_3637 = cat(_T_3528[6], _T_3528[5]) @[lib.scala 193:103] + node _T_3638 = cat(_T_3637, _T_3636) @[lib.scala 193:103] + node _T_3639 = cat(_T_3638, _T_3635) @[lib.scala 193:103] + node _T_3640 = cat(_T_3528[8], _T_3528[7]) @[lib.scala 193:103] + node _T_3641 = cat(_T_3528[10], _T_3528[9]) @[lib.scala 193:103] + node _T_3642 = cat(_T_3641, _T_3640) @[lib.scala 193:103] + node _T_3643 = cat(_T_3528[12], _T_3528[11]) @[lib.scala 193:103] + node _T_3644 = cat(_T_3528[14], _T_3528[13]) @[lib.scala 193:103] + node _T_3645 = cat(_T_3644, _T_3643) @[lib.scala 193:103] + node _T_3646 = cat(_T_3645, _T_3642) @[lib.scala 193:103] + node _T_3647 = cat(_T_3646, _T_3639) @[lib.scala 193:103] + node _T_3648 = xorr(_T_3647) @[lib.scala 193:110] + node _T_3649 = xor(_T_3633, _T_3648) @[lib.scala 193:98] + node _T_3650 = bits(_T_3523, 3, 3) @[lib.scala 193:122] + node _T_3651 = cat(_T_3527[2], _T_3527[1]) @[lib.scala 193:130] + node _T_3652 = cat(_T_3651, _T_3527[0]) @[lib.scala 193:130] + node _T_3653 = cat(_T_3527[4], _T_3527[3]) @[lib.scala 193:130] + node _T_3654 = cat(_T_3527[6], _T_3527[5]) @[lib.scala 193:130] + node _T_3655 = cat(_T_3654, _T_3653) @[lib.scala 193:130] + node _T_3656 = cat(_T_3655, _T_3652) @[lib.scala 193:130] + node _T_3657 = cat(_T_3527[8], _T_3527[7]) @[lib.scala 193:130] + node _T_3658 = cat(_T_3527[10], _T_3527[9]) @[lib.scala 193:130] + node _T_3659 = cat(_T_3658, _T_3657) @[lib.scala 193:130] + node _T_3660 = cat(_T_3527[12], _T_3527[11]) @[lib.scala 193:130] + node _T_3661 = cat(_T_3527[14], _T_3527[13]) @[lib.scala 193:130] + node _T_3662 = cat(_T_3661, _T_3660) @[lib.scala 193:130] + node _T_3663 = cat(_T_3662, _T_3659) @[lib.scala 193:130] + node _T_3664 = cat(_T_3663, _T_3656) @[lib.scala 193:130] + node _T_3665 = xorr(_T_3664) @[lib.scala 193:137] + node _T_3666 = xor(_T_3650, _T_3665) @[lib.scala 193:125] + node _T_3667 = bits(_T_3523, 2, 2) @[lib.scala 193:149] + node _T_3668 = cat(_T_3526[1], _T_3526[0]) @[lib.scala 193:157] + node _T_3669 = cat(_T_3526[3], _T_3526[2]) @[lib.scala 193:157] + node _T_3670 = cat(_T_3669, _T_3668) @[lib.scala 193:157] + node _T_3671 = cat(_T_3526[5], _T_3526[4]) @[lib.scala 193:157] + node _T_3672 = cat(_T_3526[8], _T_3526[7]) @[lib.scala 193:157] + node _T_3673 = cat(_T_3672, _T_3526[6]) @[lib.scala 193:157] + node _T_3674 = cat(_T_3673, _T_3671) @[lib.scala 193:157] + node _T_3675 = cat(_T_3674, _T_3670) @[lib.scala 193:157] + node _T_3676 = cat(_T_3526[10], _T_3526[9]) @[lib.scala 193:157] + node _T_3677 = cat(_T_3526[12], _T_3526[11]) @[lib.scala 193:157] + node _T_3678 = cat(_T_3677, _T_3676) @[lib.scala 193:157] + node _T_3679 = cat(_T_3526[14], _T_3526[13]) @[lib.scala 193:157] + node _T_3680 = cat(_T_3526[17], _T_3526[16]) @[lib.scala 193:157] + node _T_3681 = cat(_T_3680, _T_3526[15]) @[lib.scala 193:157] + node _T_3682 = cat(_T_3681, _T_3679) @[lib.scala 193:157] + node _T_3683 = cat(_T_3682, _T_3678) @[lib.scala 193:157] + node _T_3684 = cat(_T_3683, _T_3675) @[lib.scala 193:157] + node _T_3685 = xorr(_T_3684) @[lib.scala 193:164] + node _T_3686 = xor(_T_3667, _T_3685) @[lib.scala 193:152] + node _T_3687 = bits(_T_3523, 1, 1) @[lib.scala 193:176] + node _T_3688 = cat(_T_3525[1], _T_3525[0]) @[lib.scala 193:184] + node _T_3689 = cat(_T_3525[3], _T_3525[2]) @[lib.scala 193:184] + node _T_3690 = cat(_T_3689, _T_3688) @[lib.scala 193:184] + node _T_3691 = cat(_T_3525[5], _T_3525[4]) @[lib.scala 193:184] + node _T_3692 = cat(_T_3525[8], _T_3525[7]) @[lib.scala 193:184] + node _T_3693 = cat(_T_3692, _T_3525[6]) @[lib.scala 193:184] + node _T_3694 = cat(_T_3693, _T_3691) @[lib.scala 193:184] + node _T_3695 = cat(_T_3694, _T_3690) @[lib.scala 193:184] + node _T_3696 = cat(_T_3525[10], _T_3525[9]) @[lib.scala 193:184] + node _T_3697 = cat(_T_3525[12], _T_3525[11]) @[lib.scala 193:184] + node _T_3698 = cat(_T_3697, _T_3696) @[lib.scala 193:184] + node _T_3699 = cat(_T_3525[14], _T_3525[13]) @[lib.scala 193:184] + node _T_3700 = cat(_T_3525[17], _T_3525[16]) @[lib.scala 193:184] + node _T_3701 = cat(_T_3700, _T_3525[15]) @[lib.scala 193:184] + node _T_3702 = cat(_T_3701, _T_3699) @[lib.scala 193:184] + node _T_3703 = cat(_T_3702, _T_3698) @[lib.scala 193:184] + node _T_3704 = cat(_T_3703, _T_3695) @[lib.scala 193:184] + node _T_3705 = xorr(_T_3704) @[lib.scala 193:191] + node _T_3706 = xor(_T_3687, _T_3705) @[lib.scala 193:179] + node _T_3707 = bits(_T_3523, 0, 0) @[lib.scala 193:203] + node _T_3708 = cat(_T_3524[1], _T_3524[0]) @[lib.scala 193:211] + node _T_3709 = cat(_T_3524[3], _T_3524[2]) @[lib.scala 193:211] + node _T_3710 = cat(_T_3709, _T_3708) @[lib.scala 193:211] + node _T_3711 = cat(_T_3524[5], _T_3524[4]) @[lib.scala 193:211] + node _T_3712 = cat(_T_3524[8], _T_3524[7]) @[lib.scala 193:211] + node _T_3713 = cat(_T_3712, _T_3524[6]) @[lib.scala 193:211] + node _T_3714 = cat(_T_3713, _T_3711) @[lib.scala 193:211] + node _T_3715 = cat(_T_3714, _T_3710) @[lib.scala 193:211] + node _T_3716 = cat(_T_3524[10], _T_3524[9]) @[lib.scala 193:211] + node _T_3717 = cat(_T_3524[12], _T_3524[11]) @[lib.scala 193:211] + node _T_3718 = cat(_T_3717, _T_3716) @[lib.scala 193:211] + node _T_3719 = cat(_T_3524[14], _T_3524[13]) @[lib.scala 193:211] + node _T_3720 = cat(_T_3524[17], _T_3524[16]) @[lib.scala 193:211] + node _T_3721 = cat(_T_3720, _T_3524[15]) @[lib.scala 193:211] + node _T_3722 = cat(_T_3721, _T_3719) @[lib.scala 193:211] + node _T_3723 = cat(_T_3722, _T_3718) @[lib.scala 193:211] + node _T_3724 = cat(_T_3723, _T_3715) @[lib.scala 193:211] + node _T_3725 = xorr(_T_3724) @[lib.scala 193:218] + node _T_3726 = xor(_T_3707, _T_3725) @[lib.scala 193:206] node _T_3727 = cat(_T_3686, _T_3706) @[Cat.scala 29:58] node _T_3728 = cat(_T_3727, _T_3726) @[Cat.scala 29:58] node _T_3729 = cat(_T_3649, _T_3666) @[Cat.scala 29:58] node _T_3730 = cat(_T_3624, _T_3632) @[Cat.scala 29:58] node _T_3731 = cat(_T_3730, _T_3729) @[Cat.scala 29:58] node _T_3732 = cat(_T_3731, _T_3728) @[Cat.scala 29:58] - node _T_3733 = neq(_T_3732, UInt<1>("h00")) @[el2_lib.scala 334:44] - node _T_3734 = and(_T_3521, _T_3733) @[el2_lib.scala 334:32] - node _T_3735 = bits(_T_3732, 6, 6) @[el2_lib.scala 334:64] - node _T_3736 = and(_T_3734, _T_3735) @[el2_lib.scala 334:53] - node _T_3737 = neq(_T_3732, UInt<1>("h00")) @[el2_lib.scala 335:44] - node _T_3738 = and(_T_3521, _T_3737) @[el2_lib.scala 335:32] - node _T_3739 = bits(_T_3732, 6, 6) @[el2_lib.scala 335:65] - node _T_3740 = not(_T_3739) @[el2_lib.scala 335:55] - node _T_3741 = and(_T_3738, _T_3740) @[el2_lib.scala 335:53] - wire _T_3742 : UInt<1>[39] @[el2_lib.scala 336:26] - node _T_3743 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3744 = eq(_T_3743, UInt<1>("h01")) @[el2_lib.scala 339:41] - _T_3742[0] <= _T_3744 @[el2_lib.scala 339:23] - node _T_3745 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3746 = eq(_T_3745, UInt<2>("h02")) @[el2_lib.scala 339:41] - _T_3742[1] <= _T_3746 @[el2_lib.scala 339:23] - node _T_3747 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3748 = eq(_T_3747, UInt<2>("h03")) @[el2_lib.scala 339:41] - _T_3742[2] <= _T_3748 @[el2_lib.scala 339:23] - node _T_3749 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3750 = eq(_T_3749, UInt<3>("h04")) @[el2_lib.scala 339:41] - _T_3742[3] <= _T_3750 @[el2_lib.scala 339:23] - node _T_3751 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3752 = eq(_T_3751, UInt<3>("h05")) @[el2_lib.scala 339:41] - _T_3742[4] <= _T_3752 @[el2_lib.scala 339:23] - node _T_3753 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3754 = eq(_T_3753, UInt<3>("h06")) @[el2_lib.scala 339:41] - _T_3742[5] <= _T_3754 @[el2_lib.scala 339:23] - node _T_3755 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3756 = eq(_T_3755, UInt<3>("h07")) @[el2_lib.scala 339:41] - _T_3742[6] <= _T_3756 @[el2_lib.scala 339:23] - node _T_3757 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3758 = eq(_T_3757, UInt<4>("h08")) @[el2_lib.scala 339:41] - _T_3742[7] <= _T_3758 @[el2_lib.scala 339:23] - node _T_3759 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3760 = eq(_T_3759, UInt<4>("h09")) @[el2_lib.scala 339:41] - _T_3742[8] <= _T_3760 @[el2_lib.scala 339:23] - node _T_3761 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3762 = eq(_T_3761, UInt<4>("h0a")) @[el2_lib.scala 339:41] - _T_3742[9] <= _T_3762 @[el2_lib.scala 339:23] - node _T_3763 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3764 = eq(_T_3763, UInt<4>("h0b")) @[el2_lib.scala 339:41] - _T_3742[10] <= _T_3764 @[el2_lib.scala 339:23] - node _T_3765 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3766 = eq(_T_3765, UInt<4>("h0c")) @[el2_lib.scala 339:41] - _T_3742[11] <= _T_3766 @[el2_lib.scala 339:23] - node _T_3767 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3768 = eq(_T_3767, UInt<4>("h0d")) @[el2_lib.scala 339:41] - _T_3742[12] <= _T_3768 @[el2_lib.scala 339:23] - node _T_3769 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3770 = eq(_T_3769, UInt<4>("h0e")) @[el2_lib.scala 339:41] - _T_3742[13] <= _T_3770 @[el2_lib.scala 339:23] - node _T_3771 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3772 = eq(_T_3771, UInt<4>("h0f")) @[el2_lib.scala 339:41] - _T_3742[14] <= _T_3772 @[el2_lib.scala 339:23] - node _T_3773 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3774 = eq(_T_3773, UInt<5>("h010")) @[el2_lib.scala 339:41] - _T_3742[15] <= _T_3774 @[el2_lib.scala 339:23] - node _T_3775 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3776 = eq(_T_3775, UInt<5>("h011")) @[el2_lib.scala 339:41] - _T_3742[16] <= _T_3776 @[el2_lib.scala 339:23] - node _T_3777 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3778 = eq(_T_3777, UInt<5>("h012")) @[el2_lib.scala 339:41] - _T_3742[17] <= _T_3778 @[el2_lib.scala 339:23] - node _T_3779 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3780 = eq(_T_3779, UInt<5>("h013")) @[el2_lib.scala 339:41] - _T_3742[18] <= _T_3780 @[el2_lib.scala 339:23] - node _T_3781 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3782 = eq(_T_3781, UInt<5>("h014")) @[el2_lib.scala 339:41] - _T_3742[19] <= _T_3782 @[el2_lib.scala 339:23] - node _T_3783 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3784 = eq(_T_3783, UInt<5>("h015")) @[el2_lib.scala 339:41] - _T_3742[20] <= _T_3784 @[el2_lib.scala 339:23] - node _T_3785 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3786 = eq(_T_3785, UInt<5>("h016")) @[el2_lib.scala 339:41] - _T_3742[21] <= _T_3786 @[el2_lib.scala 339:23] - node _T_3787 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3788 = eq(_T_3787, UInt<5>("h017")) @[el2_lib.scala 339:41] - _T_3742[22] <= _T_3788 @[el2_lib.scala 339:23] - node _T_3789 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3790 = eq(_T_3789, UInt<5>("h018")) @[el2_lib.scala 339:41] - _T_3742[23] <= _T_3790 @[el2_lib.scala 339:23] - node _T_3791 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3792 = eq(_T_3791, UInt<5>("h019")) @[el2_lib.scala 339:41] - _T_3742[24] <= _T_3792 @[el2_lib.scala 339:23] - node _T_3793 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3794 = eq(_T_3793, UInt<5>("h01a")) @[el2_lib.scala 339:41] - _T_3742[25] <= _T_3794 @[el2_lib.scala 339:23] - node _T_3795 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3796 = eq(_T_3795, UInt<5>("h01b")) @[el2_lib.scala 339:41] - _T_3742[26] <= _T_3796 @[el2_lib.scala 339:23] - node _T_3797 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3798 = eq(_T_3797, UInt<5>("h01c")) @[el2_lib.scala 339:41] - _T_3742[27] <= _T_3798 @[el2_lib.scala 339:23] - node _T_3799 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3800 = eq(_T_3799, UInt<5>("h01d")) @[el2_lib.scala 339:41] - _T_3742[28] <= _T_3800 @[el2_lib.scala 339:23] - node _T_3801 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3802 = eq(_T_3801, UInt<5>("h01e")) @[el2_lib.scala 339:41] - _T_3742[29] <= _T_3802 @[el2_lib.scala 339:23] - node _T_3803 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3804 = eq(_T_3803, UInt<5>("h01f")) @[el2_lib.scala 339:41] - _T_3742[30] <= _T_3804 @[el2_lib.scala 339:23] - node _T_3805 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3806 = eq(_T_3805, UInt<6>("h020")) @[el2_lib.scala 339:41] - _T_3742[31] <= _T_3806 @[el2_lib.scala 339:23] - node _T_3807 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3808 = eq(_T_3807, UInt<6>("h021")) @[el2_lib.scala 339:41] - _T_3742[32] <= _T_3808 @[el2_lib.scala 339:23] - node _T_3809 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3810 = eq(_T_3809, UInt<6>("h022")) @[el2_lib.scala 339:41] - _T_3742[33] <= _T_3810 @[el2_lib.scala 339:23] - node _T_3811 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3812 = eq(_T_3811, UInt<6>("h023")) @[el2_lib.scala 339:41] - _T_3742[34] <= _T_3812 @[el2_lib.scala 339:23] - node _T_3813 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3814 = eq(_T_3813, UInt<6>("h024")) @[el2_lib.scala 339:41] - _T_3742[35] <= _T_3814 @[el2_lib.scala 339:23] - node _T_3815 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3816 = eq(_T_3815, UInt<6>("h025")) @[el2_lib.scala 339:41] - _T_3742[36] <= _T_3816 @[el2_lib.scala 339:23] - node _T_3817 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3818 = eq(_T_3817, UInt<6>("h026")) @[el2_lib.scala 339:41] - _T_3742[37] <= _T_3818 @[el2_lib.scala 339:23] - node _T_3819 = bits(_T_3732, 5, 0) @[el2_lib.scala 339:35] - node _T_3820 = eq(_T_3819, UInt<6>("h027")) @[el2_lib.scala 339:41] - _T_3742[38] <= _T_3820 @[el2_lib.scala 339:23] - node _T_3821 = bits(_T_3523, 6, 6) @[el2_lib.scala 341:37] - node _T_3822 = bits(_T_3522, 31, 26) @[el2_lib.scala 341:45] - node _T_3823 = bits(_T_3523, 5, 5) @[el2_lib.scala 341:60] - node _T_3824 = bits(_T_3522, 25, 11) @[el2_lib.scala 341:68] - node _T_3825 = bits(_T_3523, 4, 4) @[el2_lib.scala 341:83] - node _T_3826 = bits(_T_3522, 10, 4) @[el2_lib.scala 341:91] - node _T_3827 = bits(_T_3523, 3, 3) @[el2_lib.scala 341:105] - node _T_3828 = bits(_T_3522, 3, 1) @[el2_lib.scala 341:113] - node _T_3829 = bits(_T_3523, 2, 2) @[el2_lib.scala 341:126] - node _T_3830 = bits(_T_3522, 0, 0) @[el2_lib.scala 341:134] - node _T_3831 = bits(_T_3523, 1, 0) @[el2_lib.scala 341:145] + node _T_3733 = neq(_T_3732, UInt<1>("h00")) @[lib.scala 194:44] + node _T_3734 = and(_T_3521, _T_3733) @[lib.scala 194:32] + node _T_3735 = bits(_T_3732, 6, 6) @[lib.scala 194:64] + node _T_3736 = and(_T_3734, _T_3735) @[lib.scala 194:53] + node _T_3737 = neq(_T_3732, UInt<1>("h00")) @[lib.scala 195:44] + node _T_3738 = and(_T_3521, _T_3737) @[lib.scala 195:32] + node _T_3739 = bits(_T_3732, 6, 6) @[lib.scala 195:65] + node _T_3740 = not(_T_3739) @[lib.scala 195:55] + node _T_3741 = and(_T_3738, _T_3740) @[lib.scala 195:53] + wire _T_3742 : UInt<1>[39] @[lib.scala 196:26] + node _T_3743 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3744 = eq(_T_3743, UInt<1>("h01")) @[lib.scala 199:41] + _T_3742[0] <= _T_3744 @[lib.scala 199:23] + node _T_3745 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3746 = eq(_T_3745, UInt<2>("h02")) @[lib.scala 199:41] + _T_3742[1] <= _T_3746 @[lib.scala 199:23] + node _T_3747 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3748 = eq(_T_3747, UInt<2>("h03")) @[lib.scala 199:41] + _T_3742[2] <= _T_3748 @[lib.scala 199:23] + node _T_3749 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3750 = eq(_T_3749, UInt<3>("h04")) @[lib.scala 199:41] + _T_3742[3] <= _T_3750 @[lib.scala 199:23] + node _T_3751 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3752 = eq(_T_3751, UInt<3>("h05")) @[lib.scala 199:41] + _T_3742[4] <= _T_3752 @[lib.scala 199:23] + node _T_3753 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3754 = eq(_T_3753, UInt<3>("h06")) @[lib.scala 199:41] + _T_3742[5] <= _T_3754 @[lib.scala 199:23] + node _T_3755 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3756 = eq(_T_3755, UInt<3>("h07")) @[lib.scala 199:41] + _T_3742[6] <= _T_3756 @[lib.scala 199:23] + node _T_3757 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3758 = eq(_T_3757, UInt<4>("h08")) @[lib.scala 199:41] + _T_3742[7] <= _T_3758 @[lib.scala 199:23] + node _T_3759 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3760 = eq(_T_3759, UInt<4>("h09")) @[lib.scala 199:41] + _T_3742[8] <= _T_3760 @[lib.scala 199:23] + node _T_3761 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3762 = eq(_T_3761, UInt<4>("h0a")) @[lib.scala 199:41] + _T_3742[9] <= _T_3762 @[lib.scala 199:23] + node _T_3763 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3764 = eq(_T_3763, UInt<4>("h0b")) @[lib.scala 199:41] + _T_3742[10] <= _T_3764 @[lib.scala 199:23] + node _T_3765 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3766 = eq(_T_3765, UInt<4>("h0c")) @[lib.scala 199:41] + _T_3742[11] <= _T_3766 @[lib.scala 199:23] + node _T_3767 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3768 = eq(_T_3767, UInt<4>("h0d")) @[lib.scala 199:41] + _T_3742[12] <= _T_3768 @[lib.scala 199:23] + node _T_3769 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3770 = eq(_T_3769, UInt<4>("h0e")) @[lib.scala 199:41] + _T_3742[13] <= _T_3770 @[lib.scala 199:23] + node _T_3771 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3772 = eq(_T_3771, UInt<4>("h0f")) @[lib.scala 199:41] + _T_3742[14] <= _T_3772 @[lib.scala 199:23] + node _T_3773 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3774 = eq(_T_3773, UInt<5>("h010")) @[lib.scala 199:41] + _T_3742[15] <= _T_3774 @[lib.scala 199:23] + node _T_3775 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3776 = eq(_T_3775, UInt<5>("h011")) @[lib.scala 199:41] + _T_3742[16] <= _T_3776 @[lib.scala 199:23] + node _T_3777 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3778 = eq(_T_3777, UInt<5>("h012")) @[lib.scala 199:41] + _T_3742[17] <= _T_3778 @[lib.scala 199:23] + node _T_3779 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3780 = eq(_T_3779, UInt<5>("h013")) @[lib.scala 199:41] + _T_3742[18] <= _T_3780 @[lib.scala 199:23] + node _T_3781 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3782 = eq(_T_3781, UInt<5>("h014")) @[lib.scala 199:41] + _T_3742[19] <= _T_3782 @[lib.scala 199:23] + node _T_3783 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3784 = eq(_T_3783, UInt<5>("h015")) @[lib.scala 199:41] + _T_3742[20] <= _T_3784 @[lib.scala 199:23] + node _T_3785 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3786 = eq(_T_3785, UInt<5>("h016")) @[lib.scala 199:41] + _T_3742[21] <= _T_3786 @[lib.scala 199:23] + node _T_3787 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3788 = eq(_T_3787, UInt<5>("h017")) @[lib.scala 199:41] + _T_3742[22] <= _T_3788 @[lib.scala 199:23] + node _T_3789 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3790 = eq(_T_3789, UInt<5>("h018")) @[lib.scala 199:41] + _T_3742[23] <= _T_3790 @[lib.scala 199:23] + node _T_3791 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3792 = eq(_T_3791, UInt<5>("h019")) @[lib.scala 199:41] + _T_3742[24] <= _T_3792 @[lib.scala 199:23] + node _T_3793 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3794 = eq(_T_3793, UInt<5>("h01a")) @[lib.scala 199:41] + _T_3742[25] <= _T_3794 @[lib.scala 199:23] + node _T_3795 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3796 = eq(_T_3795, UInt<5>("h01b")) @[lib.scala 199:41] + _T_3742[26] <= _T_3796 @[lib.scala 199:23] + node _T_3797 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3798 = eq(_T_3797, UInt<5>("h01c")) @[lib.scala 199:41] + _T_3742[27] <= _T_3798 @[lib.scala 199:23] + node _T_3799 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3800 = eq(_T_3799, UInt<5>("h01d")) @[lib.scala 199:41] + _T_3742[28] <= _T_3800 @[lib.scala 199:23] + node _T_3801 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3802 = eq(_T_3801, UInt<5>("h01e")) @[lib.scala 199:41] + _T_3742[29] <= _T_3802 @[lib.scala 199:23] + node _T_3803 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3804 = eq(_T_3803, UInt<5>("h01f")) @[lib.scala 199:41] + _T_3742[30] <= _T_3804 @[lib.scala 199:23] + node _T_3805 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3806 = eq(_T_3805, UInt<6>("h020")) @[lib.scala 199:41] + _T_3742[31] <= _T_3806 @[lib.scala 199:23] + node _T_3807 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3808 = eq(_T_3807, UInt<6>("h021")) @[lib.scala 199:41] + _T_3742[32] <= _T_3808 @[lib.scala 199:23] + node _T_3809 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3810 = eq(_T_3809, UInt<6>("h022")) @[lib.scala 199:41] + _T_3742[33] <= _T_3810 @[lib.scala 199:23] + node _T_3811 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3812 = eq(_T_3811, UInt<6>("h023")) @[lib.scala 199:41] + _T_3742[34] <= _T_3812 @[lib.scala 199:23] + node _T_3813 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3814 = eq(_T_3813, UInt<6>("h024")) @[lib.scala 199:41] + _T_3742[35] <= _T_3814 @[lib.scala 199:23] + node _T_3815 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3816 = eq(_T_3815, UInt<6>("h025")) @[lib.scala 199:41] + _T_3742[36] <= _T_3816 @[lib.scala 199:23] + node _T_3817 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3818 = eq(_T_3817, UInt<6>("h026")) @[lib.scala 199:41] + _T_3742[37] <= _T_3818 @[lib.scala 199:23] + node _T_3819 = bits(_T_3732, 5, 0) @[lib.scala 199:35] + node _T_3820 = eq(_T_3819, UInt<6>("h027")) @[lib.scala 199:41] + _T_3742[38] <= _T_3820 @[lib.scala 199:23] + node _T_3821 = bits(_T_3523, 6, 6) @[lib.scala 201:37] + node _T_3822 = bits(_T_3522, 31, 26) @[lib.scala 201:45] + node _T_3823 = bits(_T_3523, 5, 5) @[lib.scala 201:60] + node _T_3824 = bits(_T_3522, 25, 11) @[lib.scala 201:68] + node _T_3825 = bits(_T_3523, 4, 4) @[lib.scala 201:83] + node _T_3826 = bits(_T_3522, 10, 4) @[lib.scala 201:91] + node _T_3827 = bits(_T_3523, 3, 3) @[lib.scala 201:105] + node _T_3828 = bits(_T_3522, 3, 1) @[lib.scala 201:113] + node _T_3829 = bits(_T_3523, 2, 2) @[lib.scala 201:126] + node _T_3830 = bits(_T_3522, 0, 0) @[lib.scala 201:134] + node _T_3831 = bits(_T_3523, 1, 0) @[lib.scala 201:145] node _T_3832 = cat(_T_3830, _T_3831) @[Cat.scala 29:58] node _T_3833 = cat(_T_3827, _T_3828) @[Cat.scala 29:58] node _T_3834 = cat(_T_3833, _T_3829) @[Cat.scala 29:58] @@ -7934,65 +7934,65 @@ circuit quasar_wrapper : node _T_3839 = cat(_T_3838, _T_3823) @[Cat.scala 29:58] node _T_3840 = cat(_T_3839, _T_3837) @[Cat.scala 29:58] node _T_3841 = cat(_T_3840, _T_3835) @[Cat.scala 29:58] - node _T_3842 = bits(_T_3736, 0, 0) @[el2_lib.scala 342:49] - node _T_3843 = cat(_T_3742[1], _T_3742[0]) @[el2_lib.scala 342:69] - node _T_3844 = cat(_T_3742[3], _T_3742[2]) @[el2_lib.scala 342:69] - node _T_3845 = cat(_T_3844, _T_3843) @[el2_lib.scala 342:69] - node _T_3846 = cat(_T_3742[5], _T_3742[4]) @[el2_lib.scala 342:69] - node _T_3847 = cat(_T_3742[8], _T_3742[7]) @[el2_lib.scala 342:69] - node _T_3848 = cat(_T_3847, _T_3742[6]) @[el2_lib.scala 342:69] - node _T_3849 = cat(_T_3848, _T_3846) @[el2_lib.scala 342:69] - node _T_3850 = cat(_T_3849, _T_3845) @[el2_lib.scala 342:69] - node _T_3851 = cat(_T_3742[10], _T_3742[9]) @[el2_lib.scala 342:69] - node _T_3852 = cat(_T_3742[13], _T_3742[12]) @[el2_lib.scala 342:69] - node _T_3853 = cat(_T_3852, _T_3742[11]) @[el2_lib.scala 342:69] - node _T_3854 = cat(_T_3853, _T_3851) @[el2_lib.scala 342:69] - node _T_3855 = cat(_T_3742[15], _T_3742[14]) @[el2_lib.scala 342:69] - node _T_3856 = cat(_T_3742[18], _T_3742[17]) @[el2_lib.scala 342:69] - node _T_3857 = cat(_T_3856, _T_3742[16]) @[el2_lib.scala 342:69] - node _T_3858 = cat(_T_3857, _T_3855) @[el2_lib.scala 342:69] - node _T_3859 = cat(_T_3858, _T_3854) @[el2_lib.scala 342:69] - node _T_3860 = cat(_T_3859, _T_3850) @[el2_lib.scala 342:69] - node _T_3861 = cat(_T_3742[20], _T_3742[19]) @[el2_lib.scala 342:69] - node _T_3862 = cat(_T_3742[23], _T_3742[22]) @[el2_lib.scala 342:69] - node _T_3863 = cat(_T_3862, _T_3742[21]) @[el2_lib.scala 342:69] - node _T_3864 = cat(_T_3863, _T_3861) @[el2_lib.scala 342:69] - node _T_3865 = cat(_T_3742[25], _T_3742[24]) @[el2_lib.scala 342:69] - node _T_3866 = cat(_T_3742[28], _T_3742[27]) @[el2_lib.scala 342:69] - node _T_3867 = cat(_T_3866, _T_3742[26]) @[el2_lib.scala 342:69] - node _T_3868 = cat(_T_3867, _T_3865) @[el2_lib.scala 342:69] - node _T_3869 = cat(_T_3868, _T_3864) @[el2_lib.scala 342:69] - node _T_3870 = cat(_T_3742[30], _T_3742[29]) @[el2_lib.scala 342:69] - node _T_3871 = cat(_T_3742[33], _T_3742[32]) @[el2_lib.scala 342:69] - node _T_3872 = cat(_T_3871, _T_3742[31]) @[el2_lib.scala 342:69] - node _T_3873 = cat(_T_3872, _T_3870) @[el2_lib.scala 342:69] - node _T_3874 = cat(_T_3742[35], _T_3742[34]) @[el2_lib.scala 342:69] - node _T_3875 = cat(_T_3742[38], _T_3742[37]) @[el2_lib.scala 342:69] - node _T_3876 = cat(_T_3875, _T_3742[36]) @[el2_lib.scala 342:69] - node _T_3877 = cat(_T_3876, _T_3874) @[el2_lib.scala 342:69] - node _T_3878 = cat(_T_3877, _T_3873) @[el2_lib.scala 342:69] - node _T_3879 = cat(_T_3878, _T_3869) @[el2_lib.scala 342:69] - node _T_3880 = cat(_T_3879, _T_3860) @[el2_lib.scala 342:69] - node _T_3881 = xor(_T_3880, _T_3841) @[el2_lib.scala 342:76] - node _T_3882 = mux(_T_3842, _T_3881, _T_3841) @[el2_lib.scala 342:31] - node _T_3883 = bits(_T_3882, 37, 32) @[el2_lib.scala 344:37] - node _T_3884 = bits(_T_3882, 30, 16) @[el2_lib.scala 344:61] - node _T_3885 = bits(_T_3882, 14, 8) @[el2_lib.scala 344:86] - node _T_3886 = bits(_T_3882, 6, 4) @[el2_lib.scala 344:110] - node _T_3887 = bits(_T_3882, 2, 2) @[el2_lib.scala 344:133] + node _T_3842 = bits(_T_3736, 0, 0) @[lib.scala 202:49] + node _T_3843 = cat(_T_3742[1], _T_3742[0]) @[lib.scala 202:69] + node _T_3844 = cat(_T_3742[3], _T_3742[2]) @[lib.scala 202:69] + node _T_3845 = cat(_T_3844, _T_3843) @[lib.scala 202:69] + node _T_3846 = cat(_T_3742[5], _T_3742[4]) @[lib.scala 202:69] + node _T_3847 = cat(_T_3742[8], _T_3742[7]) @[lib.scala 202:69] + node _T_3848 = cat(_T_3847, _T_3742[6]) @[lib.scala 202:69] + node _T_3849 = cat(_T_3848, _T_3846) @[lib.scala 202:69] + node _T_3850 = cat(_T_3849, _T_3845) @[lib.scala 202:69] + node _T_3851 = cat(_T_3742[10], _T_3742[9]) @[lib.scala 202:69] + node _T_3852 = cat(_T_3742[13], _T_3742[12]) @[lib.scala 202:69] + node _T_3853 = cat(_T_3852, _T_3742[11]) @[lib.scala 202:69] + node _T_3854 = cat(_T_3853, _T_3851) @[lib.scala 202:69] + node _T_3855 = cat(_T_3742[15], _T_3742[14]) @[lib.scala 202:69] + node _T_3856 = cat(_T_3742[18], _T_3742[17]) @[lib.scala 202:69] + node _T_3857 = cat(_T_3856, _T_3742[16]) @[lib.scala 202:69] + node _T_3858 = cat(_T_3857, _T_3855) @[lib.scala 202:69] + node _T_3859 = cat(_T_3858, _T_3854) @[lib.scala 202:69] + node _T_3860 = cat(_T_3859, _T_3850) @[lib.scala 202:69] + node _T_3861 = cat(_T_3742[20], _T_3742[19]) @[lib.scala 202:69] + node _T_3862 = cat(_T_3742[23], _T_3742[22]) @[lib.scala 202:69] + node _T_3863 = cat(_T_3862, _T_3742[21]) @[lib.scala 202:69] + node _T_3864 = cat(_T_3863, _T_3861) @[lib.scala 202:69] + node _T_3865 = cat(_T_3742[25], _T_3742[24]) @[lib.scala 202:69] + node _T_3866 = cat(_T_3742[28], _T_3742[27]) @[lib.scala 202:69] + node _T_3867 = cat(_T_3866, _T_3742[26]) @[lib.scala 202:69] + node _T_3868 = cat(_T_3867, _T_3865) @[lib.scala 202:69] + node _T_3869 = cat(_T_3868, _T_3864) @[lib.scala 202:69] + node _T_3870 = cat(_T_3742[30], _T_3742[29]) @[lib.scala 202:69] + node _T_3871 = cat(_T_3742[33], _T_3742[32]) @[lib.scala 202:69] + node _T_3872 = cat(_T_3871, _T_3742[31]) @[lib.scala 202:69] + node _T_3873 = cat(_T_3872, _T_3870) @[lib.scala 202:69] + node _T_3874 = cat(_T_3742[35], _T_3742[34]) @[lib.scala 202:69] + node _T_3875 = cat(_T_3742[38], _T_3742[37]) @[lib.scala 202:69] + node _T_3876 = cat(_T_3875, _T_3742[36]) @[lib.scala 202:69] + node _T_3877 = cat(_T_3876, _T_3874) @[lib.scala 202:69] + node _T_3878 = cat(_T_3877, _T_3873) @[lib.scala 202:69] + node _T_3879 = cat(_T_3878, _T_3869) @[lib.scala 202:69] + node _T_3880 = cat(_T_3879, _T_3860) @[lib.scala 202:69] + node _T_3881 = xor(_T_3880, _T_3841) @[lib.scala 202:76] + node _T_3882 = mux(_T_3842, _T_3881, _T_3841) @[lib.scala 202:31] + node _T_3883 = bits(_T_3882, 37, 32) @[lib.scala 204:37] + node _T_3884 = bits(_T_3882, 30, 16) @[lib.scala 204:61] + node _T_3885 = bits(_T_3882, 14, 8) @[lib.scala 204:86] + node _T_3886 = bits(_T_3882, 6, 4) @[lib.scala 204:110] + node _T_3887 = bits(_T_3882, 2, 2) @[lib.scala 204:133] node _T_3888 = cat(_T_3886, _T_3887) @[Cat.scala 29:58] node _T_3889 = cat(_T_3883, _T_3884) @[Cat.scala 29:58] node _T_3890 = cat(_T_3889, _T_3885) @[Cat.scala 29:58] node _T_3891 = cat(_T_3890, _T_3888) @[Cat.scala 29:58] - node _T_3892 = bits(_T_3882, 38, 38) @[el2_lib.scala 345:39] - node _T_3893 = bits(_T_3732, 6, 0) @[el2_lib.scala 345:56] - node _T_3894 = eq(_T_3893, UInt<7>("h040")) @[el2_lib.scala 345:62] - node _T_3895 = xor(_T_3892, _T_3894) @[el2_lib.scala 345:44] - node _T_3896 = bits(_T_3882, 31, 31) @[el2_lib.scala 345:102] - node _T_3897 = bits(_T_3882, 15, 15) @[el2_lib.scala 345:124] - node _T_3898 = bits(_T_3882, 7, 7) @[el2_lib.scala 345:146] - node _T_3899 = bits(_T_3882, 3, 3) @[el2_lib.scala 345:167] - node _T_3900 = bits(_T_3882, 1, 0) @[el2_lib.scala 345:188] + node _T_3892 = bits(_T_3882, 38, 38) @[lib.scala 205:39] + node _T_3893 = bits(_T_3732, 6, 0) @[lib.scala 205:56] + node _T_3894 = eq(_T_3893, UInt<7>("h040")) @[lib.scala 205:62] + node _T_3895 = xor(_T_3892, _T_3894) @[lib.scala 205:44] + node _T_3896 = bits(_T_3882, 31, 31) @[lib.scala 205:102] + node _T_3897 = bits(_T_3882, 15, 15) @[lib.scala 205:124] + node _T_3898 = bits(_T_3882, 7, 7) @[lib.scala 205:146] + node _T_3899 = bits(_T_3882, 3, 3) @[lib.scala 205:167] + node _T_3900 = bits(_T_3882, 1, 0) @[lib.scala 205:188] node _T_3901 = cat(_T_3898, _T_3899) @[Cat.scala 29:58] node _T_3902 = cat(_T_3901, _T_3900) @[Cat.scala 29:58] node _T_3903 = cat(_T_3895, _T_3896) @[Cat.scala 29:58] @@ -8183,102 +8183,102 @@ circuit quasar_wrapper : node way_status_clken_14 = eq(_T_4017, UInt<4>("h0e")) @[ifu_mem_ctl.scala 656:132] node _T_4018 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 656:89] node way_status_clken_15 = eq(_T_4018, UInt<4>("h0f")) @[ifu_mem_ctl.scala 656:132] - inst rvclkhdr_70 of rvclkhdr_70 @[el2_lib.scala 483:22] + inst rvclkhdr_70 of rvclkhdr_70 @[lib.scala 343:22] rvclkhdr_70.clock <= clock rvclkhdr_70.reset <= reset - rvclkhdr_70.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_70.io.en <= way_status_clken_0 @[el2_lib.scala 485:16] - rvclkhdr_70.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_71 of rvclkhdr_71 @[el2_lib.scala 483:22] + rvclkhdr_70.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_70.io.en <= way_status_clken_0 @[lib.scala 345:16] + rvclkhdr_70.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_71 of rvclkhdr_71 @[lib.scala 343:22] rvclkhdr_71.clock <= clock rvclkhdr_71.reset <= reset - rvclkhdr_71.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_71.io.en <= way_status_clken_1 @[el2_lib.scala 485:16] - rvclkhdr_71.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_72 of rvclkhdr_72 @[el2_lib.scala 483:22] + rvclkhdr_71.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_71.io.en <= way_status_clken_1 @[lib.scala 345:16] + rvclkhdr_71.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_72 of rvclkhdr_72 @[lib.scala 343:22] rvclkhdr_72.clock <= clock rvclkhdr_72.reset <= reset - rvclkhdr_72.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_72.io.en <= way_status_clken_2 @[el2_lib.scala 485:16] - rvclkhdr_72.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_73 of rvclkhdr_73 @[el2_lib.scala 483:22] + rvclkhdr_72.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_72.io.en <= way_status_clken_2 @[lib.scala 345:16] + rvclkhdr_72.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_73 of rvclkhdr_73 @[lib.scala 343:22] rvclkhdr_73.clock <= clock rvclkhdr_73.reset <= reset - rvclkhdr_73.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_73.io.en <= way_status_clken_3 @[el2_lib.scala 485:16] - rvclkhdr_73.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_74 of rvclkhdr_74 @[el2_lib.scala 483:22] + rvclkhdr_73.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_73.io.en <= way_status_clken_3 @[lib.scala 345:16] + rvclkhdr_73.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_74 of rvclkhdr_74 @[lib.scala 343:22] rvclkhdr_74.clock <= clock rvclkhdr_74.reset <= reset - rvclkhdr_74.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_74.io.en <= way_status_clken_4 @[el2_lib.scala 485:16] - rvclkhdr_74.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_75 of rvclkhdr_75 @[el2_lib.scala 483:22] + rvclkhdr_74.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_74.io.en <= way_status_clken_4 @[lib.scala 345:16] + rvclkhdr_74.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_75 of rvclkhdr_75 @[lib.scala 343:22] rvclkhdr_75.clock <= clock rvclkhdr_75.reset <= reset - rvclkhdr_75.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_75.io.en <= way_status_clken_5 @[el2_lib.scala 485:16] - rvclkhdr_75.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_76 of rvclkhdr_76 @[el2_lib.scala 483:22] + rvclkhdr_75.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_75.io.en <= way_status_clken_5 @[lib.scala 345:16] + rvclkhdr_75.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_76 of rvclkhdr_76 @[lib.scala 343:22] rvclkhdr_76.clock <= clock rvclkhdr_76.reset <= reset - rvclkhdr_76.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_76.io.en <= way_status_clken_6 @[el2_lib.scala 485:16] - rvclkhdr_76.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_77 of rvclkhdr_77 @[el2_lib.scala 483:22] + rvclkhdr_76.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_76.io.en <= way_status_clken_6 @[lib.scala 345:16] + rvclkhdr_76.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_77 of rvclkhdr_77 @[lib.scala 343:22] rvclkhdr_77.clock <= clock rvclkhdr_77.reset <= reset - rvclkhdr_77.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_77.io.en <= way_status_clken_7 @[el2_lib.scala 485:16] - rvclkhdr_77.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_78 of rvclkhdr_78 @[el2_lib.scala 483:22] + rvclkhdr_77.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_77.io.en <= way_status_clken_7 @[lib.scala 345:16] + rvclkhdr_77.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_78 of rvclkhdr_78 @[lib.scala 343:22] rvclkhdr_78.clock <= clock rvclkhdr_78.reset <= reset - rvclkhdr_78.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_78.io.en <= way_status_clken_8 @[el2_lib.scala 485:16] - rvclkhdr_78.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_79 of rvclkhdr_79 @[el2_lib.scala 483:22] + rvclkhdr_78.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_78.io.en <= way_status_clken_8 @[lib.scala 345:16] + rvclkhdr_78.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_79 of rvclkhdr_79 @[lib.scala 343:22] rvclkhdr_79.clock <= clock rvclkhdr_79.reset <= reset - rvclkhdr_79.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_79.io.en <= way_status_clken_9 @[el2_lib.scala 485:16] - rvclkhdr_79.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_80 of rvclkhdr_80 @[el2_lib.scala 483:22] + rvclkhdr_79.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_79.io.en <= way_status_clken_9 @[lib.scala 345:16] + rvclkhdr_79.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_80 of rvclkhdr_80 @[lib.scala 343:22] rvclkhdr_80.clock <= clock rvclkhdr_80.reset <= reset - rvclkhdr_80.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_80.io.en <= way_status_clken_10 @[el2_lib.scala 485:16] - rvclkhdr_80.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_81 of rvclkhdr_81 @[el2_lib.scala 483:22] + rvclkhdr_80.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_80.io.en <= way_status_clken_10 @[lib.scala 345:16] + rvclkhdr_80.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_81 of rvclkhdr_81 @[lib.scala 343:22] rvclkhdr_81.clock <= clock rvclkhdr_81.reset <= reset - rvclkhdr_81.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_81.io.en <= way_status_clken_11 @[el2_lib.scala 485:16] - rvclkhdr_81.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_82 of rvclkhdr_82 @[el2_lib.scala 483:22] + rvclkhdr_81.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_81.io.en <= way_status_clken_11 @[lib.scala 345:16] + rvclkhdr_81.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_82 of rvclkhdr_82 @[lib.scala 343:22] rvclkhdr_82.clock <= clock rvclkhdr_82.reset <= reset - rvclkhdr_82.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_82.io.en <= way_status_clken_12 @[el2_lib.scala 485:16] - rvclkhdr_82.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_83 of rvclkhdr_83 @[el2_lib.scala 483:22] + rvclkhdr_82.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_82.io.en <= way_status_clken_12 @[lib.scala 345:16] + rvclkhdr_82.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_83 of rvclkhdr_83 @[lib.scala 343:22] rvclkhdr_83.clock <= clock rvclkhdr_83.reset <= reset - rvclkhdr_83.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_83.io.en <= way_status_clken_13 @[el2_lib.scala 485:16] - rvclkhdr_83.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_84 of rvclkhdr_84 @[el2_lib.scala 483:22] + rvclkhdr_83.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_83.io.en <= way_status_clken_13 @[lib.scala 345:16] + rvclkhdr_83.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_84 of rvclkhdr_84 @[lib.scala 343:22] rvclkhdr_84.clock <= clock rvclkhdr_84.reset <= reset - rvclkhdr_84.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_84.io.en <= way_status_clken_14 @[el2_lib.scala 485:16] - rvclkhdr_84.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_85 of rvclkhdr_85 @[el2_lib.scala 483:22] + rvclkhdr_84.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_84.io.en <= way_status_clken_14 @[lib.scala 345:16] + rvclkhdr_84.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_85 of rvclkhdr_85 @[lib.scala 343:22] rvclkhdr_85.clock <= clock rvclkhdr_85.reset <= reset - rvclkhdr_85.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_85.io.en <= way_status_clken_15 @[el2_lib.scala 485:16] - rvclkhdr_85.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_85.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_85.io.en <= way_status_clken_15 @[lib.scala 345:16] + rvclkhdr_85.io.scan_mode <= io.scan_mode @[lib.scala 346:23] wire way_status_out : UInt<1>[128] @[ifu_mem_ctl.scala 658:30] node _T_4019 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] node _T_4020 = eq(_T_4019, UInt<1>("h00")) @[ifu_mem_ctl.scala 660:128] @@ -9937,61 +9937,61 @@ circuit quasar_wrapper : node _T_5141 = or(_T_5140, reset_all_tags) @[ifu_mem_ctl.scala 684:102] node tag_valid_clken_3 = cat(_T_5141, _T_5131) @[Cat.scala 29:58] node _T_5142 = bits(tag_valid_clken_0, 0, 0) @[ifu_mem_ctl.scala 686:135] - inst rvclkhdr_86 of rvclkhdr_86 @[el2_lib.scala 483:22] + inst rvclkhdr_86 of rvclkhdr_86 @[lib.scala 343:22] rvclkhdr_86.clock <= clock rvclkhdr_86.reset <= reset - rvclkhdr_86.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_86.io.en <= _T_5142 @[el2_lib.scala 485:16] - rvclkhdr_86.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_86.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_86.io.en <= _T_5142 @[lib.scala 345:16] + rvclkhdr_86.io.scan_mode <= io.scan_mode @[lib.scala 346:23] node _T_5143 = bits(tag_valid_clken_0, 1, 1) @[ifu_mem_ctl.scala 686:135] - inst rvclkhdr_87 of rvclkhdr_87 @[el2_lib.scala 483:22] + inst rvclkhdr_87 of rvclkhdr_87 @[lib.scala 343:22] rvclkhdr_87.clock <= clock rvclkhdr_87.reset <= reset - rvclkhdr_87.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_87.io.en <= _T_5143 @[el2_lib.scala 485:16] - rvclkhdr_87.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_87.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_87.io.en <= _T_5143 @[lib.scala 345:16] + rvclkhdr_87.io.scan_mode <= io.scan_mode @[lib.scala 346:23] node _T_5144 = bits(tag_valid_clken_1, 0, 0) @[ifu_mem_ctl.scala 686:135] - inst rvclkhdr_88 of rvclkhdr_88 @[el2_lib.scala 483:22] + inst rvclkhdr_88 of rvclkhdr_88 @[lib.scala 343:22] rvclkhdr_88.clock <= clock rvclkhdr_88.reset <= reset - rvclkhdr_88.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_88.io.en <= _T_5144 @[el2_lib.scala 485:16] - rvclkhdr_88.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_88.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_88.io.en <= _T_5144 @[lib.scala 345:16] + rvclkhdr_88.io.scan_mode <= io.scan_mode @[lib.scala 346:23] node _T_5145 = bits(tag_valid_clken_1, 1, 1) @[ifu_mem_ctl.scala 686:135] - inst rvclkhdr_89 of rvclkhdr_89 @[el2_lib.scala 483:22] + inst rvclkhdr_89 of rvclkhdr_89 @[lib.scala 343:22] rvclkhdr_89.clock <= clock rvclkhdr_89.reset <= reset - rvclkhdr_89.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_89.io.en <= _T_5145 @[el2_lib.scala 485:16] - rvclkhdr_89.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_89.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_89.io.en <= _T_5145 @[lib.scala 345:16] + rvclkhdr_89.io.scan_mode <= io.scan_mode @[lib.scala 346:23] node _T_5146 = bits(tag_valid_clken_2, 0, 0) @[ifu_mem_ctl.scala 686:135] - inst rvclkhdr_90 of rvclkhdr_90 @[el2_lib.scala 483:22] + inst rvclkhdr_90 of rvclkhdr_90 @[lib.scala 343:22] rvclkhdr_90.clock <= clock rvclkhdr_90.reset <= reset - rvclkhdr_90.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_90.io.en <= _T_5146 @[el2_lib.scala 485:16] - rvclkhdr_90.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_90.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_90.io.en <= _T_5146 @[lib.scala 345:16] + rvclkhdr_90.io.scan_mode <= io.scan_mode @[lib.scala 346:23] node _T_5147 = bits(tag_valid_clken_2, 1, 1) @[ifu_mem_ctl.scala 686:135] - inst rvclkhdr_91 of rvclkhdr_91 @[el2_lib.scala 483:22] + inst rvclkhdr_91 of rvclkhdr_91 @[lib.scala 343:22] rvclkhdr_91.clock <= clock rvclkhdr_91.reset <= reset - rvclkhdr_91.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_91.io.en <= _T_5147 @[el2_lib.scala 485:16] - rvclkhdr_91.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_91.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_91.io.en <= _T_5147 @[lib.scala 345:16] + rvclkhdr_91.io.scan_mode <= io.scan_mode @[lib.scala 346:23] node _T_5148 = bits(tag_valid_clken_3, 0, 0) @[ifu_mem_ctl.scala 686:135] - inst rvclkhdr_92 of rvclkhdr_92 @[el2_lib.scala 483:22] + inst rvclkhdr_92 of rvclkhdr_92 @[lib.scala 343:22] rvclkhdr_92.clock <= clock rvclkhdr_92.reset <= reset - rvclkhdr_92.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_92.io.en <= _T_5148 @[el2_lib.scala 485:16] - rvclkhdr_92.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_92.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_92.io.en <= _T_5148 @[lib.scala 345:16] + rvclkhdr_92.io.scan_mode <= io.scan_mode @[lib.scala 346:23] node _T_5149 = bits(tag_valid_clken_3, 1, 1) @[ifu_mem_ctl.scala 686:135] - inst rvclkhdr_93 of rvclkhdr_93 @[el2_lib.scala 483:22] + inst rvclkhdr_93 of rvclkhdr_93 @[lib.scala 343:22] rvclkhdr_93.clock <= clock rvclkhdr_93.reset <= reset - rvclkhdr_93.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_93.io.en <= _T_5149 @[el2_lib.scala 485:16] - rvclkhdr_93.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_93.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_93.io.en <= _T_5149 @[lib.scala 345:16] + rvclkhdr_93.io.scan_mode <= io.scan_mode @[lib.scala 346:23] wire ic_tag_valid_out : UInt<1>[128][2] @[ifu_mem_ctl.scala 687:32] node _T_5150 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] node _T_5151 = eq(_T_5150, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] @@ -15821,15 +15821,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_94 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_94 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_95 : output Q : Clock @@ -15845,15 +15845,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_95 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_95 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_96 : output Q : Clock @@ -15869,15 +15869,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_96 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_96 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_97 : output Q : Clock @@ -15893,15 +15893,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_97 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_97 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_98 : output Q : Clock @@ -15917,15 +15917,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_98 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_98 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_99 : output Q : Clock @@ -15941,15 +15941,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_99 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_99 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_100 : output Q : Clock @@ -15965,15 +15965,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_100 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_100 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_101 : output Q : Clock @@ -15989,15 +15989,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_101 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_101 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_102 : output Q : Clock @@ -16013,15 +16013,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_102 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_102 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_103 : output Q : Clock @@ -16037,15 +16037,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_103 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_103 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_104 : output Q : Clock @@ -16061,15 +16061,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_104 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_104 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_105 : output Q : Clock @@ -16085,15 +16085,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_105 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_105 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_106 : output Q : Clock @@ -16109,15 +16109,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_106 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_106 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_107 : output Q : Clock @@ -16133,15 +16133,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_107 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_107 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_108 : output Q : Clock @@ -16157,15 +16157,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_108 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_108 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_109 : output Q : Clock @@ -16181,15 +16181,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_109 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_109 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_110 : output Q : Clock @@ -16205,15 +16205,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_110 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_110 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_111 : output Q : Clock @@ -16229,15 +16229,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_111 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_111 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_112 : output Q : Clock @@ -16253,15 +16253,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_112 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_112 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_113 : output Q : Clock @@ -16277,15 +16277,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_113 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_113 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_114 : output Q : Clock @@ -16301,15 +16301,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_114 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_114 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_115 : output Q : Clock @@ -16325,15 +16325,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_115 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_115 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_116 : output Q : Clock @@ -16349,15 +16349,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_116 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_116 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_117 : output Q : Clock @@ -16373,15 +16373,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_117 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_117 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_118 : output Q : Clock @@ -16397,15 +16397,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_118 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_118 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_119 : output Q : Clock @@ -16421,15 +16421,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_119 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_119 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_120 : output Q : Clock @@ -16445,15 +16445,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_120 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_120 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_121 : output Q : Clock @@ -16469,15 +16469,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_121 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_121 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_122 : output Q : Clock @@ -16493,15 +16493,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_122 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_122 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_123 : output Q : Clock @@ -16517,15 +16517,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_123 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_123 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_124 : output Q : Clock @@ -16541,15 +16541,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_124 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_124 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_125 : output Q : Clock @@ -16565,15 +16565,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_125 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_125 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_126 : output Q : Clock @@ -16589,15 +16589,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_126 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_126 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_127 : output Q : Clock @@ -16613,15 +16613,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_127 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_127 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_128 : output Q : Clock @@ -16637,15 +16637,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_128 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_128 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_129 : output Q : Clock @@ -16661,15 +16661,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_129 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_129 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_130 : output Q : Clock @@ -16685,15 +16685,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_130 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_130 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_131 : output Q : Clock @@ -16709,15 +16709,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_131 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_131 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_132 : output Q : Clock @@ -16733,15 +16733,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_132 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_132 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_133 : output Q : Clock @@ -16757,15 +16757,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_133 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_133 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_134 : output Q : Clock @@ -16781,15 +16781,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_134 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_134 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_135 : output Q : Clock @@ -16805,15 +16805,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_135 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_135 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_136 : output Q : Clock @@ -16829,15 +16829,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_136 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_136 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_137 : output Q : Clock @@ -16853,15 +16853,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_137 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_137 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_138 : output Q : Clock @@ -16877,15 +16877,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_138 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_138 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_139 : output Q : Clock @@ -16901,15 +16901,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_139 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_139 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_140 : output Q : Clock @@ -16925,15 +16925,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_140 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_140 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_141 : output Q : Clock @@ -16949,15 +16949,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_141 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_141 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_142 : output Q : Clock @@ -16973,15 +16973,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_142 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_142 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_143 : output Q : Clock @@ -16997,15 +16997,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_143 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_143 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_144 : output Q : Clock @@ -17021,15 +17021,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_144 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_144 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_145 : output Q : Clock @@ -17045,15 +17045,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_145 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_145 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_146 : output Q : Clock @@ -17069,15 +17069,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_146 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_146 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_147 : output Q : Clock @@ -17093,15 +17093,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_147 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_147 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_148 : output Q : Clock @@ -17117,15 +17117,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_148 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_148 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_149 : output Q : Clock @@ -17141,15 +17141,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_149 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_149 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_150 : output Q : Clock @@ -17165,15 +17165,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_150 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_150 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_151 : output Q : Clock @@ -17189,15 +17189,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_151 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_151 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_152 : output Q : Clock @@ -17213,15 +17213,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_152 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_152 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_153 : output Q : Clock @@ -17237,15 +17237,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_153 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_153 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_154 : output Q : Clock @@ -17261,15 +17261,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_154 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_154 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_155 : output Q : Clock @@ -17285,15 +17285,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_155 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_155 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_156 : output Q : Clock @@ -17309,15 +17309,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_156 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_156 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_157 : output Q : Clock @@ -17333,15 +17333,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_157 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_157 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_158 : output Q : Clock @@ -17357,15 +17357,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_158 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_158 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_159 : output Q : Clock @@ -17381,15 +17381,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_159 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_159 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_160 : output Q : Clock @@ -17405,15 +17405,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_160 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_160 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_161 : output Q : Clock @@ -17429,15 +17429,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_161 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_161 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_162 : output Q : Clock @@ -17453,15 +17453,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_162 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_162 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_163 : output Q : Clock @@ -17477,15 +17477,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_163 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_163 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_164 : output Q : Clock @@ -17501,15 +17501,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_164 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_164 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_165 : output Q : Clock @@ -17525,15 +17525,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_165 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_165 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_166 : output Q : Clock @@ -17549,15 +17549,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_166 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_166 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_167 : output Q : Clock @@ -17573,15 +17573,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_167 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_167 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_168 : output Q : Clock @@ -17597,15 +17597,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_168 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_168 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_169 : output Q : Clock @@ -17621,15 +17621,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_169 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_169 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_170 : output Q : Clock @@ -17645,15 +17645,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_170 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_170 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_171 : output Q : Clock @@ -17669,15 +17669,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_171 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_171 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_172 : output Q : Clock @@ -17693,15 +17693,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_172 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_172 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_173 : output Q : Clock @@ -17717,15 +17717,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_173 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_173 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_174 : output Q : Clock @@ -17741,15 +17741,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_174 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_174 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_175 : output Q : Clock @@ -17765,15 +17765,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_175 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_175 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_176 : output Q : Clock @@ -17789,15 +17789,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_176 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_176 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_177 : output Q : Clock @@ -17813,15 +17813,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_177 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_177 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_178 : output Q : Clock @@ -17837,15 +17837,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_178 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_178 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_179 : output Q : Clock @@ -17861,15 +17861,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_179 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_179 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_180 : output Q : Clock @@ -17885,15 +17885,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_180 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_180 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_181 : output Q : Clock @@ -17909,15 +17909,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_181 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_181 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_182 : output Q : Clock @@ -17933,15 +17933,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_182 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_182 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_183 : output Q : Clock @@ -17957,15 +17957,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_183 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_183 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_184 : output Q : Clock @@ -17981,15 +17981,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_184 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_184 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_185 : output Q : Clock @@ -18005,15 +18005,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_185 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_185 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_186 : output Q : Clock @@ -18029,15 +18029,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_186 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_186 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_187 : output Q : Clock @@ -18053,15 +18053,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_187 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_187 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_188 : output Q : Clock @@ -18077,15 +18077,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_188 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_188 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_189 : output Q : Clock @@ -18101,15 +18101,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_189 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_189 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_190 : output Q : Clock @@ -18125,15 +18125,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_190 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_190 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_191 : output Q : Clock @@ -18149,15 +18149,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_191 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_191 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_192 : output Q : Clock @@ -18173,15 +18173,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_192 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_192 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_193 : output Q : Clock @@ -18197,15 +18197,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_193 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_193 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_194 : output Q : Clock @@ -18221,15 +18221,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_194 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_194 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_195 : output Q : Clock @@ -18245,15 +18245,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_195 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_195 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_196 : output Q : Clock @@ -18269,15 +18269,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_196 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_196 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_197 : output Q : Clock @@ -18293,15 +18293,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_197 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_197 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_198 : output Q : Clock @@ -18317,15 +18317,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_198 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_198 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_199 : output Q : Clock @@ -18341,15 +18341,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_199 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_199 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_200 : output Q : Clock @@ -18365,15 +18365,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_200 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_200 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_201 : output Q : Clock @@ -18389,15 +18389,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_201 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_201 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_202 : output Q : Clock @@ -18413,15 +18413,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_202 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_202 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_203 : output Q : Clock @@ -18437,15 +18437,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_203 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_203 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_204 : output Q : Clock @@ -18461,15 +18461,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_204 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_204 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_205 : output Q : Clock @@ -18485,15 +18485,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_205 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_205 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_206 : output Q : Clock @@ -18509,15 +18509,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_206 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_206 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_207 : output Q : Clock @@ -18533,15 +18533,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_207 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_207 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_208 : output Q : Clock @@ -18557,15 +18557,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_208 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_208 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_209 : output Q : Clock @@ -18581,15 +18581,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_209 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_209 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_210 : output Q : Clock @@ -18605,15 +18605,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_210 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_210 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_211 : output Q : Clock @@ -18629,15 +18629,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_211 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_211 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_212 : output Q : Clock @@ -18653,15 +18653,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_212 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_212 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_213 : output Q : Clock @@ -18677,15 +18677,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_213 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_213 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_214 : output Q : Clock @@ -18701,15 +18701,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_214 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_214 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_215 : output Q : Clock @@ -18725,15 +18725,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_215 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_215 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_216 : output Q : Clock @@ -18749,15 +18749,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_216 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_216 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_217 : output Q : Clock @@ -18773,15 +18773,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_217 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_217 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_218 : output Q : Clock @@ -18797,15 +18797,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_218 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_218 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_219 : output Q : Clock @@ -18821,15 +18821,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_219 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_219 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_220 : output Q : Clock @@ -18845,15 +18845,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_220 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_220 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_221 : output Q : Clock @@ -18869,15 +18869,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_221 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_221 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_222 : output Q : Clock @@ -18893,15 +18893,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_222 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_222 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_223 : output Q : Clock @@ -18917,15 +18917,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_223 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_223 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_224 : output Q : Clock @@ -18941,15 +18941,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_224 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_224 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_225 : output Q : Clock @@ -18965,15 +18965,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_225 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_225 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_226 : output Q : Clock @@ -18989,15 +18989,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_226 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_226 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_227 : output Q : Clock @@ -19013,15 +19013,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_227 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_227 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_228 : output Q : Clock @@ -19037,15 +19037,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_228 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_228 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_229 : output Q : Clock @@ -19061,15 +19061,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_229 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_229 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_230 : output Q : Clock @@ -19085,15 +19085,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_230 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_230 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_231 : output Q : Clock @@ -19109,15 +19109,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_231 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_231 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_232 : output Q : Clock @@ -19133,15 +19133,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_232 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_232 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_233 : output Q : Clock @@ -19157,15 +19157,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_233 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_233 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_234 : output Q : Clock @@ -19181,15 +19181,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_234 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_234 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_235 : output Q : Clock @@ -19205,15 +19205,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_235 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_235 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_236 : output Q : Clock @@ -19229,15 +19229,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_236 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_236 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_237 : output Q : Clock @@ -19253,15 +19253,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_237 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_237 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_238 : output Q : Clock @@ -19277,15 +19277,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_238 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_238 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_239 : output Q : Clock @@ -19301,15 +19301,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_239 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_239 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_240 : output Q : Clock @@ -19325,15 +19325,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_240 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_240 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_241 : output Q : Clock @@ -19349,15 +19349,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_241 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_241 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_242 : output Q : Clock @@ -19373,15 +19373,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_242 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_242 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_243 : output Q : Clock @@ -19397,15 +19397,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_243 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_243 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_244 : output Q : Clock @@ -19421,15 +19421,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_244 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_244 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_245 : output Q : Clock @@ -19445,15 +19445,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_245 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_245 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_246 : output Q : Clock @@ -19469,15 +19469,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_246 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_246 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_247 : output Q : Clock @@ -19493,15 +19493,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_247 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_247 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_248 : output Q : Clock @@ -19517,15 +19517,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_248 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_248 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_249 : output Q : Clock @@ -19541,15 +19541,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_249 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_249 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_250 : output Q : Clock @@ -19565,15 +19565,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_250 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_250 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_251 : output Q : Clock @@ -19589,15 +19589,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_251 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_251 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_252 : output Q : Clock @@ -19613,15 +19613,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_252 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_252 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_253 : output Q : Clock @@ -19637,15 +19637,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_253 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_253 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_254 : output Q : Clock @@ -19661,15 +19661,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_254 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_254 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_255 : output Q : Clock @@ -19685,15 +19685,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_255 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_255 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_256 : output Q : Clock @@ -19709,15 +19709,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_256 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_256 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_257 : output Q : Clock @@ -19733,15 +19733,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_257 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_257 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_258 : output Q : Clock @@ -19757,15 +19757,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_258 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_258 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_259 : output Q : Clock @@ -19781,15 +19781,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_259 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_259 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_260 : output Q : Clock @@ -19805,15 +19805,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_260 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_260 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_261 : output Q : Clock @@ -19829,15 +19829,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_261 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_261 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_262 : output Q : Clock @@ -19853,15 +19853,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_262 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_262 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_263 : output Q : Clock @@ -19877,15 +19877,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_263 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_263 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_264 : output Q : Clock @@ -19901,15 +19901,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_264 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_264 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_265 : output Q : Clock @@ -19925,15 +19925,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_265 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_265 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_266 : output Q : Clock @@ -19949,15 +19949,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_266 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_266 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_267 : output Q : Clock @@ -19973,15 +19973,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_267 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_267 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_268 : output Q : Clock @@ -19997,15 +19997,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_268 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_268 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_269 : output Q : Clock @@ -20021,15 +20021,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_269 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_269 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_270 : output Q : Clock @@ -20045,15 +20045,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_270 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_270 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_271 : output Q : Clock @@ -20069,15 +20069,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_271 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_271 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_272 : output Q : Clock @@ -20093,15 +20093,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_272 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_272 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_273 : output Q : Clock @@ -20117,15 +20117,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_273 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_273 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_274 : output Q : Clock @@ -20141,15 +20141,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_274 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_274 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_275 : output Q : Clock @@ -20165,15 +20165,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_275 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_275 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_276 : output Q : Clock @@ -20189,15 +20189,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_276 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_276 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_277 : output Q : Clock @@ -20213,15 +20213,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_277 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_277 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_278 : output Q : Clock @@ -20237,15 +20237,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_278 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_278 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_279 : output Q : Clock @@ -20261,15 +20261,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_279 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_279 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_280 : output Q : Clock @@ -20285,15 +20285,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_280 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_280 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_281 : output Q : Clock @@ -20309,15 +20309,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_281 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_281 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_282 : output Q : Clock @@ -20333,15 +20333,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_282 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_282 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_283 : output Q : Clock @@ -20357,15 +20357,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_283 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_283 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_284 : output Q : Clock @@ -20381,15 +20381,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_284 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_284 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_285 : output Q : Clock @@ -20405,15 +20405,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_285 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_285 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_286 : output Q : Clock @@ -20429,15 +20429,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_286 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_286 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_287 : output Q : Clock @@ -20453,15 +20453,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_287 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_287 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_288 : output Q : Clock @@ -20477,15 +20477,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_288 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_288 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_289 : output Q : Clock @@ -20501,15 +20501,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_289 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_289 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_290 : output Q : Clock @@ -20525,15 +20525,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_290 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_290 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_291 : output Q : Clock @@ -20549,15 +20549,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_291 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_291 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_292 : output Q : Clock @@ -20573,15 +20573,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_292 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_292 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_293 : output Q : Clock @@ -20597,15 +20597,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_293 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_293 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_294 : output Q : Clock @@ -20621,15 +20621,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_294 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_294 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_295 : output Q : Clock @@ -20645,15 +20645,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_295 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_295 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_296 : output Q : Clock @@ -20669,15 +20669,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_296 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_296 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_297 : output Q : Clock @@ -20693,15 +20693,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_297 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_297 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_298 : output Q : Clock @@ -20717,15 +20717,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_298 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_298 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_299 : output Q : Clock @@ -20741,15 +20741,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_299 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_299 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_300 : output Q : Clock @@ -20765,15 +20765,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_300 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_300 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_301 : output Q : Clock @@ -20789,15 +20789,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_301 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_301 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_302 : output Q : Clock @@ -20813,15 +20813,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_302 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_302 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_303 : output Q : Clock @@ -20837,15 +20837,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_303 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_303 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_304 : output Q : Clock @@ -20861,15 +20861,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_304 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_304 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_305 : output Q : Clock @@ -20885,15 +20885,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_305 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_305 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_306 : output Q : Clock @@ -20909,15 +20909,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_306 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_306 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_307 : output Q : Clock @@ -20933,15 +20933,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_307 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_307 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_308 : output Q : Clock @@ -20957,15 +20957,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_308 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_308 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_309 : output Q : Clock @@ -20981,15 +20981,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_309 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_309 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_310 : output Q : Clock @@ -21005,15 +21005,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_310 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_310 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_311 : output Q : Clock @@ -21029,15 +21029,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_311 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_311 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_312 : output Q : Clock @@ -21053,15 +21053,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_312 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_312 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_313 : output Q : Clock @@ -21077,15 +21077,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_313 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_313 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_314 : output Q : Clock @@ -21101,15 +21101,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_314 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_314 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_315 : output Q : Clock @@ -21125,15 +21125,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_315 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_315 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_316 : output Q : Clock @@ -21149,15 +21149,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_316 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_316 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_317 : output Q : Clock @@ -21173,15 +21173,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_317 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_317 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_318 : output Q : Clock @@ -21197,15 +21197,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_318 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_318 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_319 : output Q : Clock @@ -21221,15 +21221,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_319 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_319 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_320 : output Q : Clock @@ -21245,15 +21245,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_320 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_320 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_321 : output Q : Clock @@ -21269,15 +21269,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_321 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_321 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_322 : output Q : Clock @@ -21293,15 +21293,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_322 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_322 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_323 : output Q : Clock @@ -21317,15 +21317,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_323 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_323 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_324 : output Q : Clock @@ -21341,15 +21341,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_324 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_324 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_325 : output Q : Clock @@ -21365,15 +21365,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_325 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_325 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_326 : output Q : Clock @@ -21389,15 +21389,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_326 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_326 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_327 : output Q : Clock @@ -21413,15 +21413,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_327 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_327 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_328 : output Q : Clock @@ -21437,15 +21437,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_328 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_328 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_329 : output Q : Clock @@ -21461,15 +21461,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_329 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_329 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_330 : output Q : Clock @@ -21485,15 +21485,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_330 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_330 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_331 : output Q : Clock @@ -21509,15 +21509,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_331 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_331 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_332 : output Q : Clock @@ -21533,15 +21533,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_332 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_332 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_333 : output Q : Clock @@ -21557,15 +21557,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_333 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_333 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_334 : output Q : Clock @@ -21581,15 +21581,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_334 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_334 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_335 : output Q : Clock @@ -21605,15 +21605,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_335 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_335 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_336 : output Q : Clock @@ -21629,15 +21629,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_336 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_336 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_337 : output Q : Clock @@ -21653,15 +21653,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_337 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_337 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_338 : output Q : Clock @@ -21677,15 +21677,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_338 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_338 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_339 : output Q : Clock @@ -21701,15 +21701,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_339 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_339 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_340 : output Q : Clock @@ -21725,15 +21725,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_340 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_340 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_341 : output Q : Clock @@ -21749,15 +21749,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_341 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_341 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_342 : output Q : Clock @@ -21773,15 +21773,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_342 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_342 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_343 : output Q : Clock @@ -21797,15 +21797,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_343 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_343 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_344 : output Q : Clock @@ -21821,15 +21821,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_344 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_344 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_345 : output Q : Clock @@ -21845,15 +21845,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_345 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_345 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_346 : output Q : Clock @@ -21869,15 +21869,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_346 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_346 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_347 : output Q : Clock @@ -21893,15 +21893,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_347 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_347 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_348 : output Q : Clock @@ -21917,15 +21917,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_348 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_348 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_349 : output Q : Clock @@ -21941,15 +21941,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_349 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_349 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_350 : output Q : Clock @@ -21965,15 +21965,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_350 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_350 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_351 : output Q : Clock @@ -21989,15 +21989,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_351 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_351 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_352 : output Q : Clock @@ -22013,15 +22013,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_352 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_352 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_353 : output Q : Clock @@ -22037,15 +22037,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_353 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_353 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_354 : output Q : Clock @@ -22061,15 +22061,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_354 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_354 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_355 : output Q : Clock @@ -22085,15 +22085,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_355 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_355 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_356 : output Q : Clock @@ -22109,15 +22109,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_356 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_356 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_357 : output Q : Clock @@ -22133,15 +22133,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_357 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_357 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_358 : output Q : Clock @@ -22157,15 +22157,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_358 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_358 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_359 : output Q : Clock @@ -22181,15 +22181,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_359 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_359 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_360 : output Q : Clock @@ -22205,15 +22205,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_360 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_360 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_361 : output Q : Clock @@ -22229,15 +22229,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_361 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_361 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_362 : output Q : Clock @@ -22253,15 +22253,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_362 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_362 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_363 : output Q : Clock @@ -22277,15 +22277,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_363 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_363 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_364 : output Q : Clock @@ -22301,15 +22301,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_364 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_364 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_365 : output Q : Clock @@ -22325,15 +22325,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_365 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_365 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_366 : output Q : Clock @@ -22349,15 +22349,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_366 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_366 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_367 : output Q : Clock @@ -22373,15 +22373,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_367 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_367 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_368 : output Q : Clock @@ -22397,15 +22397,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_368 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_368 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_369 : output Q : Clock @@ -22421,15 +22421,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_369 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_369 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_370 : output Q : Clock @@ -22445,15 +22445,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_370 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_370 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_371 : output Q : Clock @@ -22469,15 +22469,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_371 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_371 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_372 : output Q : Clock @@ -22493,15 +22493,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_372 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_372 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_373 : output Q : Clock @@ -22517,15 +22517,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_373 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_373 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_374 : output Q : Clock @@ -22541,15 +22541,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_374 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_374 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_375 : output Q : Clock @@ -22565,15 +22565,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_375 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_375 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_376 : output Q : Clock @@ -22589,15 +22589,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_376 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_376 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_377 : output Q : Clock @@ -22613,15 +22613,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_377 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_377 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_378 : output Q : Clock @@ -22637,15 +22637,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_378 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_378 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_379 : output Q : Clock @@ -22661,15 +22661,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_379 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_379 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_380 : output Q : Clock @@ -22685,15 +22685,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_380 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_380 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_381 : output Q : Clock @@ -22709,15 +22709,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_381 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_381 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_382 : output Q : Clock @@ -22733,15 +22733,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_382 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_382 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_383 : output Q : Clock @@ -22757,15 +22757,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_383 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_383 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_384 : output Q : Clock @@ -22781,15 +22781,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_384 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_384 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_385 : output Q : Clock @@ -22805,15 +22805,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_385 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_385 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_386 : output Q : Clock @@ -22829,15 +22829,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_386 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_386 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_387 : output Q : Clock @@ -22853,15 +22853,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_387 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_387 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_388 : output Q : Clock @@ -22877,15 +22877,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_388 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_388 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_389 : output Q : Clock @@ -22901,15 +22901,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_389 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_389 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_390 : output Q : Clock @@ -22925,15 +22925,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_390 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_390 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_391 : output Q : Clock @@ -22949,15 +22949,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_391 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_391 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_392 : output Q : Clock @@ -22973,15 +22973,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_392 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_392 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_393 : output Q : Clock @@ -22997,15 +22997,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_393 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_393 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_394 : output Q : Clock @@ -23021,15 +23021,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_394 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_394 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_395 : output Q : Clock @@ -23045,15 +23045,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_395 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_395 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_396 : output Q : Clock @@ -23069,15 +23069,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_396 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_396 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_397 : output Q : Clock @@ -23093,15 +23093,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_397 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_397 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_398 : output Q : Clock @@ -23117,15 +23117,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_398 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_398 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_399 : output Q : Clock @@ -23141,15 +23141,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_399 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_399 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_400 : output Q : Clock @@ -23165,15 +23165,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_400 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_400 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_401 : output Q : Clock @@ -23189,15 +23189,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_401 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_401 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_402 : output Q : Clock @@ -23213,15 +23213,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_402 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_402 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_403 : output Q : Clock @@ -23237,15 +23237,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_403 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_403 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_404 : output Q : Clock @@ -23261,15 +23261,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_404 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_404 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_405 : output Q : Clock @@ -23285,15 +23285,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_405 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_405 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_406 : output Q : Clock @@ -23309,15 +23309,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_406 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_406 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_407 : output Q : Clock @@ -23333,15 +23333,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_407 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_407 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_408 : output Q : Clock @@ -23357,15 +23357,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_408 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_408 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_409 : output Q : Clock @@ -23381,15 +23381,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_409 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_409 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_410 : output Q : Clock @@ -23405,15 +23405,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_410 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_410 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_411 : output Q : Clock @@ -23429,15 +23429,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_411 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_411 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_412 : output Q : Clock @@ -23453,15 +23453,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_412 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_412 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_413 : output Q : Clock @@ -23477,15 +23477,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_413 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_413 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_414 : output Q : Clock @@ -23501,15 +23501,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_414 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_414 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_415 : output Q : Clock @@ -23525,15 +23525,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_415 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_415 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_416 : output Q : Clock @@ -23549,15 +23549,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_416 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_416 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_417 : output Q : Clock @@ -23573,15 +23573,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_417 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_417 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_418 : output Q : Clock @@ -23597,15 +23597,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_418 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_418 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_419 : output Q : Clock @@ -23621,15 +23621,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_419 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_419 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_420 : output Q : Clock @@ -23645,15 +23645,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_420 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_420 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_421 : output Q : Clock @@ -23669,15 +23669,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_421 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_421 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_422 : output Q : Clock @@ -23693,15 +23693,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_422 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_422 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_423 : output Q : Clock @@ -23717,15 +23717,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_423 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_423 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_424 : output Q : Clock @@ -23741,15 +23741,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_424 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_424 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_425 : output Q : Clock @@ -23765,15 +23765,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_425 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_425 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_426 : output Q : Clock @@ -23789,15 +23789,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_426 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_426 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_427 : output Q : Clock @@ -23813,15 +23813,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_427 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_427 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_428 : output Q : Clock @@ -23837,15 +23837,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_428 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_428 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_429 : output Q : Clock @@ -23861,15 +23861,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_429 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_429 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_430 : output Q : Clock @@ -23885,15 +23885,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_430 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_430 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_431 : output Q : Clock @@ -23909,15 +23909,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_431 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_431 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_432 : output Q : Clock @@ -23933,15 +23933,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_432 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_432 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_433 : output Q : Clock @@ -23957,15 +23957,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_433 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_433 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_434 : output Q : Clock @@ -23981,15 +23981,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_434 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_434 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_435 : output Q : Clock @@ -24005,15 +24005,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_435 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_435 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_436 : output Q : Clock @@ -24029,15 +24029,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_436 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_436 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_437 : output Q : Clock @@ -24053,15 +24053,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_437 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_437 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_438 : output Q : Clock @@ -24077,15 +24077,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_438 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_438 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_439 : output Q : Clock @@ -24101,15 +24101,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_439 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_439 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_440 : output Q : Clock @@ -24125,15 +24125,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_440 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_440 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_441 : output Q : Clock @@ -24149,15 +24149,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_441 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_441 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_442 : output Q : Clock @@ -24173,15 +24173,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_442 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_442 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_443 : output Q : Clock @@ -24197,15 +24197,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_443 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_443 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_444 : output Q : Clock @@ -24221,15 +24221,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_444 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_444 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_445 : output Q : Clock @@ -24245,15 +24245,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_445 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_445 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_446 : output Q : Clock @@ -24269,15 +24269,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_446 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_446 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_447 : output Q : Clock @@ -24293,15 +24293,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_447 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_447 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_448 : output Q : Clock @@ -24317,15 +24317,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_448 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_448 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_449 : output Q : Clock @@ -24341,15 +24341,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_449 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_449 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_450 : output Q : Clock @@ -24365,15 +24365,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_450 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_450 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_451 : output Q : Clock @@ -24389,15 +24389,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_451 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_451 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_452 : output Q : Clock @@ -24413,15 +24413,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_452 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_452 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_453 : output Q : Clock @@ -24437,15 +24437,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_453 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_453 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_454 : output Q : Clock @@ -24461,15 +24461,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_454 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_454 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_455 : output Q : Clock @@ -24485,15 +24485,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_455 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_455 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_456 : output Q : Clock @@ -24509,15 +24509,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_456 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_456 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_457 : output Q : Clock @@ -24533,15 +24533,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_457 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_457 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_458 : output Q : Clock @@ -24557,15 +24557,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_458 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_458 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_459 : output Q : Clock @@ -24581,15 +24581,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_459 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_459 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_460 : output Q : Clock @@ -24605,15 +24605,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_460 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_460 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_461 : output Q : Clock @@ -24629,15 +24629,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_461 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_461 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_462 : output Q : Clock @@ -24653,15 +24653,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_462 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_462 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_463 : output Q : Clock @@ -24677,15 +24677,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_463 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_463 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_464 : output Q : Clock @@ -24701,15 +24701,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_464 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_464 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_465 : output Q : Clock @@ -24725,15 +24725,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_465 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_465 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_466 : output Q : Clock @@ -24749,15 +24749,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_466 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_466 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_467 : output Q : Clock @@ -24773,15 +24773,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_467 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_467 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_468 : output Q : Clock @@ -24797,15 +24797,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_468 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_468 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_469 : output Q : Clock @@ -24821,15 +24821,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_469 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_469 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_470 : output Q : Clock @@ -24845,15 +24845,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_470 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_470 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_471 : output Q : Clock @@ -24869,15 +24869,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_471 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_471 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_472 : output Q : Clock @@ -24893,15 +24893,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_472 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_472 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_473 : output Q : Clock @@ -24917,15 +24917,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_473 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_473 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_474 : output Q : Clock @@ -24941,15 +24941,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_474 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_474 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_475 : output Q : Clock @@ -24965,15 +24965,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_475 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_475 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_476 : output Q : Clock @@ -24989,15 +24989,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_476 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_476 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_477 : output Q : Clock @@ -25013,15 +25013,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_477 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_477 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_478 : output Q : Clock @@ -25037,15 +25037,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_478 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_478 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_479 : output Q : Clock @@ -25061,15 +25061,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_479 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_479 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_480 : output Q : Clock @@ -25085,15 +25085,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_480 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_480 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_481 : output Q : Clock @@ -25109,15 +25109,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_481 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_481 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_482 : output Q : Clock @@ -25133,15 +25133,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_482 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_482 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_483 : output Q : Clock @@ -25157,15 +25157,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_483 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_483 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_484 : output Q : Clock @@ -25181,15 +25181,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_484 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_484 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_485 : output Q : Clock @@ -25205,15 +25205,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_485 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_485 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_486 : output Q : Clock @@ -25229,15 +25229,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_486 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_486 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_487 : output Q : Clock @@ -25253,15 +25253,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_487 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_487 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_488 : output Q : Clock @@ -25277,15 +25277,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_488 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_488 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_489 : output Q : Clock @@ -25301,15 +25301,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_489 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_489 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_490 : output Q : Clock @@ -25325,15 +25325,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_490 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_490 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_491 : output Q : Clock @@ -25349,15 +25349,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_491 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_491 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_492 : output Q : Clock @@ -25373,15 +25373,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_492 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_492 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_493 : output Q : Clock @@ -25397,15 +25397,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_493 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_493 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_494 : output Q : Clock @@ -25421,15 +25421,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_494 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_494 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_495 : output Q : Clock @@ -25445,15 +25445,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_495 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_495 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_496 : output Q : Clock @@ -25469,15 +25469,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_496 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_496 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_497 : output Q : Clock @@ -25493,15 +25493,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_497 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_497 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_498 : output Q : Clock @@ -25517,15 +25517,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_498 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_498 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_499 : output Q : Clock @@ -25541,15 +25541,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_499 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_499 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_500 : output Q : Clock @@ -25565,15 +25565,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_500 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_500 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_501 : output Q : Clock @@ -25589,15 +25589,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_501 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_501 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_502 : output Q : Clock @@ -25613,15 +25613,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_502 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_502 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_503 : output Q : Clock @@ -25637,15 +25637,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_503 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_503 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_504 : output Q : Clock @@ -25661,15 +25661,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_504 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_504 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_505 : output Q : Clock @@ -25685,15 +25685,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_505 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_505 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_506 : output Q : Clock @@ -25709,15 +25709,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_506 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_506 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_507 : output Q : Clock @@ -25733,15 +25733,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_507 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_507 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_508 : output Q : Clock @@ -25757,15 +25757,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_508 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_508 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_509 : output Q : Clock @@ -25781,15 +25781,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_509 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_509 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_510 : output Q : Clock @@ -25805,15 +25805,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_510 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_510 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_511 : output Q : Clock @@ -25829,15 +25829,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_511 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_511 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_512 : output Q : Clock @@ -25853,15 +25853,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_512 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_512 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_513 : output Q : Clock @@ -25877,15 +25877,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_513 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_513 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_514 : output Q : Clock @@ -25901,15 +25901,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_514 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_514 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_515 : output Q : Clock @@ -25925,15 +25925,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_515 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_515 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_516 : output Q : Clock @@ -25949,15 +25949,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_516 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_516 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_517 : output Q : Clock @@ -25973,15 +25973,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_517 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_517 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_518 : output Q : Clock @@ -25997,15 +25997,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_518 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_518 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_519 : output Q : Clock @@ -26021,15 +26021,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_519 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_519 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_520 : output Q : Clock @@ -26045,15 +26045,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_520 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_520 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_521 : output Q : Clock @@ -26069,15 +26069,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_521 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_521 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_522 : output Q : Clock @@ -26093,15 +26093,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_522 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_522 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_523 : output Q : Clock @@ -26117,15 +26117,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_523 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_523 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_524 : output Q : Clock @@ -26141,15 +26141,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_524 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_524 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_525 : output Q : Clock @@ -26165,15 +26165,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_525 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_525 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_526 : output Q : Clock @@ -26189,15 +26189,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_526 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_526 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_527 : output Q : Clock @@ -26213,15 +26213,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_527 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_527 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_528 : output Q : Clock @@ -26237,15 +26237,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_528 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_528 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_529 : output Q : Clock @@ -26261,15 +26261,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_529 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_529 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_530 : output Q : Clock @@ -26285,15 +26285,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_530 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_530 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_531 : output Q : Clock @@ -26309,15 +26309,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_531 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_531 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_532 : output Q : Clock @@ -26333,15 +26333,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_532 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_532 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_533 : output Q : Clock @@ -26357,15 +26357,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_533 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_533 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_534 : output Q : Clock @@ -26381,15 +26381,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_534 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_534 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_535 : output Q : Clock @@ -26405,15 +26405,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_535 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_535 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_536 : output Q : Clock @@ -26429,15 +26429,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_536 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_536 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_537 : output Q : Clock @@ -26453,15 +26453,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_537 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_537 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_538 : output Q : Clock @@ -26477,15 +26477,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_538 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_538 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_539 : output Q : Clock @@ -26501,15 +26501,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_539 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_539 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_540 : output Q : Clock @@ -26525,15 +26525,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_540 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_540 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_541 : output Q : Clock @@ -26549,15 +26549,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_541 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_541 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_542 : output Q : Clock @@ -26573,15 +26573,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_542 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_542 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_543 : output Q : Clock @@ -26597,15 +26597,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_543 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_543 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_544 : output Q : Clock @@ -26621,15 +26621,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_544 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_544 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_545 : output Q : Clock @@ -26645,15 +26645,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_545 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_545 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_546 : output Q : Clock @@ -26669,15 +26669,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_546 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_546 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_547 : output Q : Clock @@ -26693,15 +26693,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_547 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_547 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_548 : output Q : Clock @@ -26717,15 +26717,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_548 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_548 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_549 : output Q : Clock @@ -26741,15 +26741,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_549 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_549 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_550 : output Q : Clock @@ -26765,15 +26765,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_550 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_550 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_551 : output Q : Clock @@ -26789,15 +26789,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_551 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_551 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_552 : output Q : Clock @@ -26813,15 +26813,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_552 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_552 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_553 : output Q : Clock @@ -26837,15 +26837,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_553 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_553 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_554 : output Q : Clock @@ -26861,15 +26861,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_554 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_554 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_555 : output Q : Clock @@ -26885,15 +26885,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_555 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_555 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_556 : output Q : Clock @@ -26909,15 +26909,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_556 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_556 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_557 : output Q : Clock @@ -26933,15 +26933,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_557 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_557 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_558 : output Q : Clock @@ -26957,15 +26957,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_558 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_558 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_559 : output Q : Clock @@ -26981,15 +26981,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_559 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_559 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_560 : output Q : Clock @@ -27005,15 +27005,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_560 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_560 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_561 : output Q : Clock @@ -27029,15 +27029,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_561 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_561 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_562 : output Q : Clock @@ -27053,15 +27053,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_562 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_562 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_563 : output Q : Clock @@ -27077,15 +27077,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_563 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_563 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_564 : output Q : Clock @@ -27101,15 +27101,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_564 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_564 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_565 : output Q : Clock @@ -27125,15 +27125,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_565 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_565 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_566 : output Q : Clock @@ -27149,15 +27149,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_566 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_566 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_567 : output Q : Clock @@ -27173,15 +27173,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_567 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_567 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_568 : output Q : Clock @@ -27197,15 +27197,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_568 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_568 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_569 : output Q : Clock @@ -27221,15 +27221,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_569 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_569 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_570 : output Q : Clock @@ -27245,15 +27245,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_570 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_570 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_571 : output Q : Clock @@ -27269,15 +27269,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_571 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_571 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_572 : output Q : Clock @@ -27293,15 +27293,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_572 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_572 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_573 : output Q : Clock @@ -27317,15 +27317,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_573 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_573 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_574 : output Q : Clock @@ -27341,15 +27341,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_574 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_574 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_575 : output Q : Clock @@ -27365,15 +27365,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_575 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_575 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_576 : output Q : Clock @@ -27389,15 +27389,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_576 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_576 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_577 : output Q : Clock @@ -27413,15 +27413,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_577 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_577 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_578 : output Q : Clock @@ -27437,15 +27437,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_578 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_578 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_579 : output Q : Clock @@ -27461,15 +27461,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_579 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_579 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_580 : output Q : Clock @@ -27485,15 +27485,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_580 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_580 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_581 : output Q : Clock @@ -27509,15 +27509,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_581 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_581 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_582 : output Q : Clock @@ -27533,15 +27533,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_582 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_582 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_583 : output Q : Clock @@ -27557,15 +27557,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_583 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_583 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_584 : output Q : Clock @@ -27581,15 +27581,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_584 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_584 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_585 : output Q : Clock @@ -27605,15 +27605,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_585 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_585 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_586 : output Q : Clock @@ -27629,15 +27629,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_586 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_586 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_587 : output Q : Clock @@ -27653,15 +27653,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_587 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_587 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_588 : output Q : Clock @@ -27677,15 +27677,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_588 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_588 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_589 : output Q : Clock @@ -27701,15 +27701,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_589 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_589 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_590 : output Q : Clock @@ -27725,15 +27725,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_590 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_590 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_591 : output Q : Clock @@ -27749,15 +27749,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_591 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_591 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_592 : output Q : Clock @@ -27773,15 +27773,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_592 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_592 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_593 : output Q : Clock @@ -27797,15 +27797,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_593 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_593 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_594 : output Q : Clock @@ -27821,15 +27821,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_594 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_594 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_595 : output Q : Clock @@ -27845,15 +27845,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_595 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_595 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_596 : output Q : Clock @@ -27869,15 +27869,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_596 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_596 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_597 : output Q : Clock @@ -27893,15 +27893,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_597 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_597 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_598 : output Q : Clock @@ -27917,15 +27917,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_598 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_598 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_599 : output Q : Clock @@ -27941,15 +27941,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_599 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_599 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_600 : output Q : Clock @@ -27965,15 +27965,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_600 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_600 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_601 : output Q : Clock @@ -27989,15 +27989,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_601 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_601 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_602 : output Q : Clock @@ -28013,15 +28013,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_602 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_602 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_603 : output Q : Clock @@ -28037,15 +28037,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_603 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_603 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_604 : output Q : Clock @@ -28061,15 +28061,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_604 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_604 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_605 : output Q : Clock @@ -28085,15 +28085,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_605 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_605 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_606 : output Q : Clock @@ -28109,15 +28109,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_606 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_606 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_607 : output Q : Clock @@ -28133,15 +28133,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_607 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_607 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_608 : output Q : Clock @@ -28157,15 +28157,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_608 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_608 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_609 : output Q : Clock @@ -28181,15 +28181,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_609 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_609 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_610 : output Q : Clock @@ -28205,15 +28205,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_610 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_610 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_611 : output Q : Clock @@ -28229,15 +28229,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_611 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_611 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_612 : output Q : Clock @@ -28253,15 +28253,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_612 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_612 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_613 : output Q : Clock @@ -28277,15 +28277,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_613 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_613 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_614 : output Q : Clock @@ -28301,15 +28301,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_614 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_614 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_615 : output Q : Clock @@ -28325,15 +28325,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_615 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_615 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_616 : output Q : Clock @@ -28349,15 +28349,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_616 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_616 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_617 : output Q : Clock @@ -28373,15 +28373,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_617 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_617 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_618 : output Q : Clock @@ -28397,15 +28397,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_618 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_618 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_619 : output Q : Clock @@ -28421,15 +28421,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_619 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_619 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_620 : output Q : Clock @@ -28445,15 +28445,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_620 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_620 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_621 : output Q : Clock @@ -28469,15 +28469,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_621 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_621 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_622 : output Q : Clock @@ -28493,15 +28493,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_622 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_622 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_623 : output Q : Clock @@ -28517,15 +28517,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_623 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_623 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_624 : output Q : Clock @@ -28541,15 +28541,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_624 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_624 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_625 : output Q : Clock @@ -28565,15 +28565,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_625 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_625 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_626 : output Q : Clock @@ -28589,15 +28589,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_626 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_626 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_627 : output Q : Clock @@ -28613,15 +28613,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_627 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_627 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_628 : output Q : Clock @@ -28637,15 +28637,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_628 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_628 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_629 : output Q : Clock @@ -28661,15 +28661,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_629 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_629 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_630 : output Q : Clock @@ -28685,15 +28685,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_630 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_630 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_631 : output Q : Clock @@ -28709,15 +28709,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_631 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_631 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_632 : output Q : Clock @@ -28733,15 +28733,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_632 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_632 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_633 : output Q : Clock @@ -28757,15 +28757,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_633 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_633 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_634 : output Q : Clock @@ -28781,15 +28781,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_634 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_634 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_635 : output Q : Clock @@ -28805,15 +28805,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_635 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_635 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_636 : output Q : Clock @@ -28829,15 +28829,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_636 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_636 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_637 : output Q : Clock @@ -28853,15 +28853,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_637 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_637 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_638 : output Q : Clock @@ -28877,15 +28877,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_638 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_638 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_639 : output Q : Clock @@ -28901,15 +28901,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_639 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_639 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_640 : output Q : Clock @@ -28925,15 +28925,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_640 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_640 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_641 : output Q : Clock @@ -28949,15 +28949,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_641 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_641 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_642 : output Q : Clock @@ -28973,15 +28973,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_642 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_642 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_643 : output Q : Clock @@ -28997,15 +28997,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_643 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_643 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_644 : output Q : Clock @@ -29021,15 +29021,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_644 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_644 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_645 : output Q : Clock @@ -29045,15 +29045,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_645 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_645 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_646 : output Q : Clock @@ -29069,15 +29069,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_646 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_646 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_647 : output Q : Clock @@ -29093,15 +29093,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_647 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_647 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] module ifu_bp_ctl : input clock : Clock @@ -29136,20 +29136,20 @@ circuit quasar_wrapper : dec_tlu_error_wb <= _T_1 @[ifu_bp_ctl.scala 82:20] btb_error_addr_wb <= io.exu_bp.exu_i0_br_index_r @[ifu_bp_ctl.scala 83:21] dec_tlu_way_wb <= io.dec_bp.dec_tlu_br0_r_pkt.bits.way @[ifu_bp_ctl.scala 84:18] - node _T_2 = bits(io.ifc_fetch_addr_f, 8, 1) @[el2_lib.scala 191:13] - node _T_3 = bits(io.ifc_fetch_addr_f, 16, 9) @[el2_lib.scala 191:51] - node _T_4 = xor(_T_2, _T_3) @[el2_lib.scala 191:47] - node _T_5 = bits(io.ifc_fetch_addr_f, 24, 17) @[el2_lib.scala 191:89] - node btb_rd_addr_f = xor(_T_4, _T_5) @[el2_lib.scala 191:85] + node _T_2 = bits(io.ifc_fetch_addr_f, 8, 1) @[lib.scala 51:13] + node _T_3 = bits(io.ifc_fetch_addr_f, 16, 9) @[lib.scala 51:51] + node _T_4 = xor(_T_2, _T_3) @[lib.scala 51:47] + node _T_5 = bits(io.ifc_fetch_addr_f, 24, 17) @[lib.scala 51:89] + node btb_rd_addr_f = xor(_T_4, _T_5) @[lib.scala 51:85] node _T_6 = bits(io.ifc_fetch_addr_f, 30, 1) @[ifu_bp_ctl.scala 90:44] node _T_7 = add(_T_6, UInt<1>("h01")) @[ifu_bp_ctl.scala 90:51] node fetch_addr_p1_f = tail(_T_7, 1) @[ifu_bp_ctl.scala 90:51] node _T_8 = cat(fetch_addr_p1_f, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_9 = bits(_T_8, 8, 1) @[el2_lib.scala 191:13] - node _T_10 = bits(_T_8, 16, 9) @[el2_lib.scala 191:51] - node _T_11 = xor(_T_9, _T_10) @[el2_lib.scala 191:47] - node _T_12 = bits(_T_8, 24, 17) @[el2_lib.scala 191:89] - node btb_rd_addr_p1_f = xor(_T_11, _T_12) @[el2_lib.scala 191:85] + node _T_9 = bits(_T_8, 8, 1) @[lib.scala 51:13] + node _T_10 = bits(_T_8, 16, 9) @[lib.scala 51:51] + node _T_11 = xor(_T_9, _T_10) @[lib.scala 51:47] + node _T_12 = bits(_T_8, 24, 17) @[lib.scala 51:89] + node btb_rd_addr_p1_f = xor(_T_11, _T_12) @[lib.scala 51:85] node _T_13 = bits(bht_dir_f, 0, 0) @[ifu_bp_ctl.scala 96:33] node _T_14 = not(_T_13) @[ifu_bp_ctl.scala 96:23] node _T_15 = bits(bht_dir_f, 0, 0) @[ifu_bp_ctl.scala 96:46] @@ -29164,25 +29164,25 @@ circuit quasar_wrapper : node branch_error_collision_p1_f = and(dec_tlu_error_wb, _T_20) @[ifu_bp_ctl.scala 103:54] node branch_error_bank_conflict_f = and(branch_error_collision_f, dec_tlu_error_wb) @[ifu_bp_ctl.scala 106:63] node branch_error_bank_conflict_p1_f = and(branch_error_collision_p1_f, dec_tlu_error_wb) @[ifu_bp_ctl.scala 107:69] - node _T_21 = bits(io.ifc_fetch_addr_f, 13, 9) @[el2_lib.scala 182:32] - node _T_22 = bits(io.ifc_fetch_addr_f, 18, 14) @[el2_lib.scala 182:32] - node _T_23 = bits(io.ifc_fetch_addr_f, 23, 19) @[el2_lib.scala 182:32] - wire _T_24 : UInt<5>[3] @[el2_lib.scala 182:24] - _T_24[0] <= _T_21 @[el2_lib.scala 182:24] - _T_24[1] <= _T_22 @[el2_lib.scala 182:24] - _T_24[2] <= _T_23 @[el2_lib.scala 182:24] - node _T_25 = xor(_T_24[0], _T_24[1]) @[el2_lib.scala 182:111] - node fetch_rd_tag_f = xor(_T_25, _T_24[2]) @[el2_lib.scala 182:111] + node _T_21 = bits(io.ifc_fetch_addr_f, 13, 9) @[lib.scala 42:32] + node _T_22 = bits(io.ifc_fetch_addr_f, 18, 14) @[lib.scala 42:32] + node _T_23 = bits(io.ifc_fetch_addr_f, 23, 19) @[lib.scala 42:32] + wire _T_24 : UInt<5>[3] @[lib.scala 42:24] + _T_24[0] <= _T_21 @[lib.scala 42:24] + _T_24[1] <= _T_22 @[lib.scala 42:24] + _T_24[2] <= _T_23 @[lib.scala 42:24] + node _T_25 = xor(_T_24[0], _T_24[1]) @[lib.scala 42:111] + node fetch_rd_tag_f = xor(_T_25, _T_24[2]) @[lib.scala 42:111] node _T_26 = cat(fetch_addr_p1_f, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_27 = bits(_T_26, 13, 9) @[el2_lib.scala 182:32] - node _T_28 = bits(_T_26, 18, 14) @[el2_lib.scala 182:32] - node _T_29 = bits(_T_26, 23, 19) @[el2_lib.scala 182:32] - wire _T_30 : UInt<5>[3] @[el2_lib.scala 182:24] - _T_30[0] <= _T_27 @[el2_lib.scala 182:24] - _T_30[1] <= _T_28 @[el2_lib.scala 182:24] - _T_30[2] <= _T_29 @[el2_lib.scala 182:24] - node _T_31 = xor(_T_30[0], _T_30[1]) @[el2_lib.scala 182:111] - node fetch_rd_tag_p1_f = xor(_T_31, _T_30[2]) @[el2_lib.scala 182:111] + node _T_27 = bits(_T_26, 13, 9) @[lib.scala 42:32] + node _T_28 = bits(_T_26, 18, 14) @[lib.scala 42:32] + node _T_29 = bits(_T_26, 23, 19) @[lib.scala 42:32] + wire _T_30 : UInt<5>[3] @[lib.scala 42:24] + _T_30[0] <= _T_27 @[lib.scala 42:24] + _T_30[1] <= _T_28 @[lib.scala 42:24] + _T_30[2] <= _T_29 @[lib.scala 42:24] + node _T_31 = xor(_T_30[0], _T_30[1]) @[lib.scala 42:111] + node fetch_rd_tag_p1_f = xor(_T_31, _T_30[2]) @[lib.scala 42:111] node _T_32 = eq(io.exu_bp.exu_mp_btag, fetch_rd_tag_f) @[ifu_bp_ctl.scala 114:53] node _T_33 = and(_T_32, exu_mp_valid) @[ifu_bp_ctl.scala 114:73] node _T_34 = and(_T_33, io.ifc_fetch_req_f) @[ifu_bp_ctl.scala 114:88] @@ -29418,14 +29418,14 @@ circuit quasar_wrapper : io.ifu_bp_way_f <= _T_214 @[ifu_bp_ctl.scala 235:19] node _T_215 = or(io.ifc_fetch_req_f, exu_mp_valid) @[ifu_bp_ctl.scala 238:60] node _T_216 = bits(_T_215, 0, 0) @[ifu_bp_ctl.scala 238:75] - inst rvclkhdr of rvclkhdr_94 @[el2_lib.scala 508:23] + inst rvclkhdr of rvclkhdr_94 @[lib.scala 368:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr.io.en <= _T_216 @[el2_lib.scala 511:17] - rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_217 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_217 <= btb_lru_b0_ns @[el2_lib.scala 514:16] + rvclkhdr.io.clk <= clock @[lib.scala 370:18] + rvclkhdr.io.en <= _T_216 @[lib.scala 371:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_217 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_217 <= btb_lru_b0_ns @[lib.scala 374:16] btb_lru_b0_f <= _T_217 @[ifu_bp_ctl.scala 238:16] node _T_218 = bits(io.ifc_fetch_addr_f, 4, 2) @[ifu_bp_ctl.scala 241:37] node eoc_near = andr(_T_218) @[ifu_bp_ctl.scala 241:64] @@ -29639,14 +29639,14 @@ circuit quasar_wrapper : node _T_376 = and(io.ifc_fetch_req_f, _T_375) @[ifu_bp_ctl.scala 342:85] node _T_377 = and(_T_376, io.ic_hit_f) @[ifu_bp_ctl.scala 342:110] node _T_378 = bits(_T_377, 0, 0) @[ifu_bp_ctl.scala 342:125] - inst rvclkhdr_1 of rvclkhdr_95 @[el2_lib.scala 508:23] + inst rvclkhdr_1 of rvclkhdr_95 @[lib.scala 368:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_1.io.en <= _T_378 @[el2_lib.scala 511:17] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg ifc_fetch_adder_prior : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - ifc_fetch_adder_prior <= _T_374 @[el2_lib.scala 514:16] + rvclkhdr_1.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_1.io.en <= _T_378 @[lib.scala 371:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg ifc_fetch_adder_prior : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + ifc_fetch_adder_prior <= _T_374 @[lib.scala 374:16] io.ifu_bp_poffset_f <= btb_rd_tgt_f @[ifu_bp_ctl.scala 344:23] node _T_379 = bits(use_fa_plus, 0, 0) @[ifu_bp_ctl.scala 346:45] node _T_380 = bits(btb_fg_crossing_f, 0, 0) @[ifu_bp_ctl.scala 347:51] @@ -29666,29 +29666,29 @@ circuit quasar_wrapper : node _T_392 = cat(_T_391, bp_total_branch_offset_f) @[Cat.scala 29:58] node _T_393 = cat(_T_392, UInt<1>("h00")) @[Cat.scala 29:58] node _T_394 = cat(btb_rd_tgt_f, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_395 = bits(_T_393, 12, 1) @[el2_lib.scala 208:24] - node _T_396 = bits(_T_394, 12, 1) @[el2_lib.scala 208:40] - node _T_397 = add(_T_395, _T_396) @[el2_lib.scala 208:31] - node _T_398 = bits(_T_393, 31, 13) @[el2_lib.scala 209:20] - node _T_399 = add(_T_398, UInt<1>("h01")) @[el2_lib.scala 209:27] - node _T_400 = tail(_T_399, 1) @[el2_lib.scala 209:27] - node _T_401 = bits(_T_393, 31, 13) @[el2_lib.scala 210:20] - node _T_402 = sub(_T_401, UInt<1>("h01")) @[el2_lib.scala 210:27] - node _T_403 = tail(_T_402, 1) @[el2_lib.scala 210:27] - node _T_404 = bits(_T_394, 12, 12) @[el2_lib.scala 211:22] - node _T_405 = bits(_T_397, 12, 12) @[el2_lib.scala 212:39] - node _T_406 = eq(_T_405, UInt<1>("h00")) @[el2_lib.scala 212:28] - node _T_407 = xor(_T_404, _T_406) @[el2_lib.scala 212:26] - node _T_408 = bits(_T_407, 0, 0) @[el2_lib.scala 212:64] - node _T_409 = bits(_T_393, 31, 13) @[el2_lib.scala 212:76] - node _T_410 = eq(_T_404, UInt<1>("h00")) @[el2_lib.scala 213:20] - node _T_411 = bits(_T_397, 12, 12) @[el2_lib.scala 213:39] - node _T_412 = and(_T_410, _T_411) @[el2_lib.scala 213:26] - node _T_413 = bits(_T_412, 0, 0) @[el2_lib.scala 213:64] - node _T_414 = bits(_T_397, 12, 12) @[el2_lib.scala 214:39] - node _T_415 = eq(_T_414, UInt<1>("h00")) @[el2_lib.scala 214:28] - node _T_416 = and(_T_404, _T_415) @[el2_lib.scala 214:26] - node _T_417 = bits(_T_416, 0, 0) @[el2_lib.scala 214:64] + node _T_395 = bits(_T_393, 12, 1) @[lib.scala 68:24] + node _T_396 = bits(_T_394, 12, 1) @[lib.scala 68:40] + node _T_397 = add(_T_395, _T_396) @[lib.scala 68:31] + node _T_398 = bits(_T_393, 31, 13) @[lib.scala 69:20] + node _T_399 = add(_T_398, UInt<1>("h01")) @[lib.scala 69:27] + node _T_400 = tail(_T_399, 1) @[lib.scala 69:27] + node _T_401 = bits(_T_393, 31, 13) @[lib.scala 70:20] + node _T_402 = sub(_T_401, UInt<1>("h01")) @[lib.scala 70:27] + node _T_403 = tail(_T_402, 1) @[lib.scala 70:27] + node _T_404 = bits(_T_394, 12, 12) @[lib.scala 71:22] + node _T_405 = bits(_T_397, 12, 12) @[lib.scala 72:39] + node _T_406 = eq(_T_405, UInt<1>("h00")) @[lib.scala 72:28] + node _T_407 = xor(_T_404, _T_406) @[lib.scala 72:26] + node _T_408 = bits(_T_407, 0, 0) @[lib.scala 72:64] + node _T_409 = bits(_T_393, 31, 13) @[lib.scala 72:76] + node _T_410 = eq(_T_404, UInt<1>("h00")) @[lib.scala 73:20] + node _T_411 = bits(_T_397, 12, 12) @[lib.scala 73:39] + node _T_412 = and(_T_410, _T_411) @[lib.scala 73:26] + node _T_413 = bits(_T_412, 0, 0) @[lib.scala 73:64] + node _T_414 = bits(_T_397, 12, 12) @[lib.scala 74:39] + node _T_415 = eq(_T_414, UInt<1>("h00")) @[lib.scala 74:28] + node _T_416 = and(_T_404, _T_415) @[lib.scala 74:26] + node _T_417 = bits(_T_416, 0, 0) @[lib.scala 74:64] node _T_418 = mux(_T_408, _T_409, UInt<1>("h00")) @[Mux.scala 27:72] node _T_419 = mux(_T_413, _T_400, UInt<1>("h00")) @[Mux.scala 27:72] node _T_420 = mux(_T_417, _T_403, UInt<1>("h00")) @[Mux.scala 27:72] @@ -29696,7 +29696,7 @@ circuit quasar_wrapper : node _T_422 = or(_T_421, _T_420) @[Mux.scala 27:72] wire _T_423 : UInt<19> @[Mux.scala 27:72] _T_423 <= _T_422 @[Mux.scala 27:72] - node _T_424 = bits(_T_397, 11, 0) @[el2_lib.scala 214:94] + node _T_424 = bits(_T_397, 11, 0) @[lib.scala 74:94] node _T_425 = cat(_T_423, _T_424) @[Cat.scala 29:58] node bp_btb_target_adder_f = cat(_T_425, UInt<1>("h00")) @[Cat.scala 29:58] wire rets_out : UInt<32>[8] @[ifu_bp_ctl.scala 353:22] @@ -29724,29 +29724,29 @@ circuit quasar_wrapper : node _T_438 = not(btb_rd_pc4_f) @[ifu_bp_ctl.scala 361:113] node _T_439 = cat(_T_437, _T_438) @[Cat.scala 29:58] node _T_440 = cat(_T_439, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_441 = bits(_T_436, 12, 1) @[el2_lib.scala 208:24] - node _T_442 = bits(_T_440, 12, 1) @[el2_lib.scala 208:40] - node _T_443 = add(_T_441, _T_442) @[el2_lib.scala 208:31] - node _T_444 = bits(_T_436, 31, 13) @[el2_lib.scala 209:20] - node _T_445 = add(_T_444, UInt<1>("h01")) @[el2_lib.scala 209:27] - node _T_446 = tail(_T_445, 1) @[el2_lib.scala 209:27] - node _T_447 = bits(_T_436, 31, 13) @[el2_lib.scala 210:20] - node _T_448 = sub(_T_447, UInt<1>("h01")) @[el2_lib.scala 210:27] - node _T_449 = tail(_T_448, 1) @[el2_lib.scala 210:27] - node _T_450 = bits(_T_440, 12, 12) @[el2_lib.scala 211:22] - node _T_451 = bits(_T_443, 12, 12) @[el2_lib.scala 212:39] - node _T_452 = eq(_T_451, UInt<1>("h00")) @[el2_lib.scala 212:28] - node _T_453 = xor(_T_450, _T_452) @[el2_lib.scala 212:26] - node _T_454 = bits(_T_453, 0, 0) @[el2_lib.scala 212:64] - node _T_455 = bits(_T_436, 31, 13) @[el2_lib.scala 212:76] - node _T_456 = eq(_T_450, UInt<1>("h00")) @[el2_lib.scala 213:20] - node _T_457 = bits(_T_443, 12, 12) @[el2_lib.scala 213:39] - node _T_458 = and(_T_456, _T_457) @[el2_lib.scala 213:26] - node _T_459 = bits(_T_458, 0, 0) @[el2_lib.scala 213:64] - node _T_460 = bits(_T_443, 12, 12) @[el2_lib.scala 214:39] - node _T_461 = eq(_T_460, UInt<1>("h00")) @[el2_lib.scala 214:28] - node _T_462 = and(_T_450, _T_461) @[el2_lib.scala 214:26] - node _T_463 = bits(_T_462, 0, 0) @[el2_lib.scala 214:64] + node _T_441 = bits(_T_436, 12, 1) @[lib.scala 68:24] + node _T_442 = bits(_T_440, 12, 1) @[lib.scala 68:40] + node _T_443 = add(_T_441, _T_442) @[lib.scala 68:31] + node _T_444 = bits(_T_436, 31, 13) @[lib.scala 69:20] + node _T_445 = add(_T_444, UInt<1>("h01")) @[lib.scala 69:27] + node _T_446 = tail(_T_445, 1) @[lib.scala 69:27] + node _T_447 = bits(_T_436, 31, 13) @[lib.scala 70:20] + node _T_448 = sub(_T_447, UInt<1>("h01")) @[lib.scala 70:27] + node _T_449 = tail(_T_448, 1) @[lib.scala 70:27] + node _T_450 = bits(_T_440, 12, 12) @[lib.scala 71:22] + node _T_451 = bits(_T_443, 12, 12) @[lib.scala 72:39] + node _T_452 = eq(_T_451, UInt<1>("h00")) @[lib.scala 72:28] + node _T_453 = xor(_T_450, _T_452) @[lib.scala 72:26] + node _T_454 = bits(_T_453, 0, 0) @[lib.scala 72:64] + node _T_455 = bits(_T_436, 31, 13) @[lib.scala 72:76] + node _T_456 = eq(_T_450, UInt<1>("h00")) @[lib.scala 73:20] + node _T_457 = bits(_T_443, 12, 12) @[lib.scala 73:39] + node _T_458 = and(_T_456, _T_457) @[lib.scala 73:26] + node _T_459 = bits(_T_458, 0, 0) @[lib.scala 73:64] + node _T_460 = bits(_T_443, 12, 12) @[lib.scala 74:39] + node _T_461 = eq(_T_460, UInt<1>("h00")) @[lib.scala 74:28] + node _T_462 = and(_T_450, _T_461) @[lib.scala 74:26] + node _T_463 = bits(_T_462, 0, 0) @[lib.scala 74:64] node _T_464 = mux(_T_454, _T_455, UInt<1>("h00")) @[Mux.scala 27:72] node _T_465 = mux(_T_459, _T_446, UInt<1>("h00")) @[Mux.scala 27:72] node _T_466 = mux(_T_463, _T_449, UInt<1>("h00")) @[Mux.scala 27:72] @@ -29754,7 +29754,7 @@ circuit quasar_wrapper : node _T_468 = or(_T_467, _T_466) @[Mux.scala 27:72] wire _T_469 : UInt<19> @[Mux.scala 27:72] _T_469 <= _T_468 @[Mux.scala 27:72] - node _T_470 = bits(_T_443, 11, 0) @[el2_lib.scala 214:94] + node _T_470 = bits(_T_443, 11, 0) @[lib.scala 74:94] node _T_471 = cat(_T_469, _T_470) @[Cat.scala 29:58] node bp_rs_call_target_f = cat(_T_471, UInt<1>("h00")) @[Cat.scala 29:58] node _T_472 = eq(btb_rd_ret_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 363:33] @@ -29825,77 +29825,77 @@ circuit quasar_wrapper : wire rets_in_6 : UInt<32> @[Mux.scala 27:72] rets_in_6 <= _T_514 @[Mux.scala 27:72] node _T_515 = bits(rsenable_0, 0, 0) @[ifu_bp_ctl.scala 378:78] - inst rvclkhdr_2 of rvclkhdr_96 @[el2_lib.scala 508:23] + inst rvclkhdr_2 of rvclkhdr_96 @[lib.scala 368:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_2.io.en <= _T_515 @[el2_lib.scala 511:17] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_516 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_516 <= rets_in_0 @[el2_lib.scala 514:16] + rvclkhdr_2.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_2.io.en <= _T_515 @[lib.scala 371:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_516 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_516 <= rets_in_0 @[lib.scala 374:16] node _T_517 = bits(rsenable_1, 0, 0) @[ifu_bp_ctl.scala 378:78] - inst rvclkhdr_3 of rvclkhdr_97 @[el2_lib.scala 508:23] + inst rvclkhdr_3 of rvclkhdr_97 @[lib.scala 368:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_3.io.en <= _T_517 @[el2_lib.scala 511:17] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_518 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_518 <= rets_in_1 @[el2_lib.scala 514:16] + rvclkhdr_3.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_3.io.en <= _T_517 @[lib.scala 371:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_518 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_518 <= rets_in_1 @[lib.scala 374:16] node _T_519 = bits(rsenable_2, 0, 0) @[ifu_bp_ctl.scala 378:78] - inst rvclkhdr_4 of rvclkhdr_98 @[el2_lib.scala 508:23] + inst rvclkhdr_4 of rvclkhdr_98 @[lib.scala 368:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_4.io.en <= _T_519 @[el2_lib.scala 511:17] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_520 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_520 <= rets_in_2 @[el2_lib.scala 514:16] + rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_4.io.en <= _T_519 @[lib.scala 371:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_520 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_520 <= rets_in_2 @[lib.scala 374:16] node _T_521 = bits(rsenable_3, 0, 0) @[ifu_bp_ctl.scala 378:78] - inst rvclkhdr_5 of rvclkhdr_99 @[el2_lib.scala 508:23] + inst rvclkhdr_5 of rvclkhdr_99 @[lib.scala 368:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_5.io.en <= _T_521 @[el2_lib.scala 511:17] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_522 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_522 <= rets_in_3 @[el2_lib.scala 514:16] + rvclkhdr_5.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_5.io.en <= _T_521 @[lib.scala 371:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_522 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_522 <= rets_in_3 @[lib.scala 374:16] node _T_523 = bits(rsenable_4, 0, 0) @[ifu_bp_ctl.scala 378:78] - inst rvclkhdr_6 of rvclkhdr_100 @[el2_lib.scala 508:23] + inst rvclkhdr_6 of rvclkhdr_100 @[lib.scala 368:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset - rvclkhdr_6.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_6.io.en <= _T_523 @[el2_lib.scala 511:17] - rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_524 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_524 <= rets_in_4 @[el2_lib.scala 514:16] + rvclkhdr_6.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_6.io.en <= _T_523 @[lib.scala 371:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_524 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_524 <= rets_in_4 @[lib.scala 374:16] node _T_525 = bits(rsenable_5, 0, 0) @[ifu_bp_ctl.scala 378:78] - inst rvclkhdr_7 of rvclkhdr_101 @[el2_lib.scala 508:23] + inst rvclkhdr_7 of rvclkhdr_101 @[lib.scala 368:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset - rvclkhdr_7.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_7.io.en <= _T_525 @[el2_lib.scala 511:17] - rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_526 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_526 <= rets_in_5 @[el2_lib.scala 514:16] + rvclkhdr_7.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_7.io.en <= _T_525 @[lib.scala 371:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_526 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_526 <= rets_in_5 @[lib.scala 374:16] node _T_527 = bits(rsenable_6, 0, 0) @[ifu_bp_ctl.scala 378:78] - inst rvclkhdr_8 of rvclkhdr_102 @[el2_lib.scala 508:23] + inst rvclkhdr_8 of rvclkhdr_102 @[lib.scala 368:23] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset - rvclkhdr_8.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_8.io.en <= _T_527 @[el2_lib.scala 511:17] - rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_528 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_528 <= rets_in_6 @[el2_lib.scala 514:16] + rvclkhdr_8.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_8.io.en <= _T_527 @[lib.scala 371:17] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_528 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_528 <= rets_in_6 @[lib.scala 374:16] node _T_529 = bits(rs_push, 0, 0) @[ifu_bp_ctl.scala 378:78] - inst rvclkhdr_9 of rvclkhdr_103 @[el2_lib.scala 508:23] + inst rvclkhdr_9 of rvclkhdr_103 @[lib.scala 368:23] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset - rvclkhdr_9.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_9.io.en <= _T_529 @[el2_lib.scala 511:17] - rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_530 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_530 <= rets_out[6] @[el2_lib.scala 514:16] + rvclkhdr_9.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_9.io.en <= _T_529 @[lib.scala 371:17] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_530 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_530 <= rets_out[6] @[lib.scala 374:16] rets_out[0] <= _T_516 @[ifu_bp_ctl.scala 378:12] rets_out[1] <= _T_518 @[ifu_bp_ctl.scala 378:12] rets_out[2] <= _T_520 @[ifu_bp_ctl.scala 378:12] @@ -29947,5653 +29947,5653 @@ circuit quasar_wrapper : node _T_563 = cat(io.dec_bp.dec_tlu_br0_r_pkt.bits.middle, _T_562) @[Cat.scala 29:58] node bht_wr_en2 = and(_T_561, _T_563) @[ifu_bp_ctl.scala 397:46] node _T_564 = cat(io.exu_bp.exu_mp_index, UInt<2>("h00")) @[Cat.scala 29:58] - node _T_565 = bits(_T_564, 9, 2) @[el2_lib.scala 196:16] - node _T_566 = bits(io.exu_bp.exu_mp_eghr, 7, 0) @[el2_lib.scala 196:40] - node bht_wr_addr0 = xor(_T_565, _T_566) @[el2_lib.scala 196:35] + node _T_565 = bits(_T_564, 9, 2) @[lib.scala 56:16] + node _T_566 = bits(io.exu_bp.exu_mp_eghr, 7, 0) @[lib.scala 56:40] + node bht_wr_addr0 = xor(_T_565, _T_566) @[lib.scala 56:35] node _T_567 = cat(io.exu_bp.exu_i0_br_index_r, UInt<2>("h00")) @[Cat.scala 29:58] - node _T_568 = bits(_T_567, 9, 2) @[el2_lib.scala 196:16] - node _T_569 = bits(io.exu_bp.exu_i0_br_fghr_r, 7, 0) @[el2_lib.scala 196:40] - node bht_wr_addr2 = xor(_T_568, _T_569) @[el2_lib.scala 196:35] + node _T_568 = bits(_T_567, 9, 2) @[lib.scala 56:16] + node _T_569 = bits(io.exu_bp.exu_i0_br_fghr_r, 7, 0) @[lib.scala 56:40] + node bht_wr_addr2 = xor(_T_568, _T_569) @[lib.scala 56:35] node _T_570 = cat(btb_rd_addr_f, UInt<2>("h00")) @[Cat.scala 29:58] - node _T_571 = bits(_T_570, 9, 2) @[el2_lib.scala 196:16] - node _T_572 = bits(fghr, 7, 0) @[el2_lib.scala 196:40] - node bht_rd_addr_f = xor(_T_571, _T_572) @[el2_lib.scala 196:35] + node _T_571 = bits(_T_570, 9, 2) @[lib.scala 56:16] + node _T_572 = bits(fghr, 7, 0) @[lib.scala 56:40] + node bht_rd_addr_f = xor(_T_571, _T_572) @[lib.scala 56:35] node _T_573 = cat(btb_rd_addr_p1_f, UInt<2>("h00")) @[Cat.scala 29:58] - node _T_574 = bits(_T_573, 9, 2) @[el2_lib.scala 196:16] - node _T_575 = bits(fghr, 7, 0) @[el2_lib.scala 196:40] - node bht_rd_addr_hashed_p1_f = xor(_T_574, _T_575) @[el2_lib.scala 196:35] + node _T_574 = bits(_T_573, 9, 2) @[lib.scala 56:16] + node _T_575 = bits(fghr, 7, 0) @[lib.scala 56:40] + node bht_rd_addr_hashed_p1_f = xor(_T_574, _T_575) @[lib.scala 56:35] node _T_576 = eq(btb_wr_addr, UInt<1>("h00")) @[ifu_bp_ctl.scala 415:95] node _T_577 = and(_T_576, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_578 = bits(_T_577, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_10 of rvclkhdr_104 @[el2_lib.scala 508:23] + inst rvclkhdr_10 of rvclkhdr_104 @[lib.scala 368:23] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset - rvclkhdr_10.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_10.io.en <= _T_578 @[el2_lib.scala 511:17] - rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_0 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_0 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_10.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_10.io.en <= _T_578 @[lib.scala 371:17] + rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_0 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_0 <= btb_wr_data @[lib.scala 374:16] node _T_579 = eq(btb_wr_addr, UInt<1>("h01")) @[ifu_bp_ctl.scala 415:95] node _T_580 = and(_T_579, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_581 = bits(_T_580, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_11 of rvclkhdr_105 @[el2_lib.scala 508:23] + inst rvclkhdr_11 of rvclkhdr_105 @[lib.scala 368:23] rvclkhdr_11.clock <= clock rvclkhdr_11.reset <= reset - rvclkhdr_11.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_11.io.en <= _T_581 @[el2_lib.scala 511:17] - rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_1 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_1 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_11.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_11.io.en <= _T_581 @[lib.scala 371:17] + rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_1 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_1 <= btb_wr_data @[lib.scala 374:16] node _T_582 = eq(btb_wr_addr, UInt<2>("h02")) @[ifu_bp_ctl.scala 415:95] node _T_583 = and(_T_582, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_584 = bits(_T_583, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_12 of rvclkhdr_106 @[el2_lib.scala 508:23] + inst rvclkhdr_12 of rvclkhdr_106 @[lib.scala 368:23] rvclkhdr_12.clock <= clock rvclkhdr_12.reset <= reset - rvclkhdr_12.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_12.io.en <= _T_584 @[el2_lib.scala 511:17] - rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_2 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_2 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_12.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_12.io.en <= _T_584 @[lib.scala 371:17] + rvclkhdr_12.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_2 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_2 <= btb_wr_data @[lib.scala 374:16] node _T_585 = eq(btb_wr_addr, UInt<2>("h03")) @[ifu_bp_ctl.scala 415:95] node _T_586 = and(_T_585, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_587 = bits(_T_586, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_13 of rvclkhdr_107 @[el2_lib.scala 508:23] + inst rvclkhdr_13 of rvclkhdr_107 @[lib.scala 368:23] rvclkhdr_13.clock <= clock rvclkhdr_13.reset <= reset - rvclkhdr_13.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_13.io.en <= _T_587 @[el2_lib.scala 511:17] - rvclkhdr_13.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_3 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_3 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_13.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_13.io.en <= _T_587 @[lib.scala 371:17] + rvclkhdr_13.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_3 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_3 <= btb_wr_data @[lib.scala 374:16] node _T_588 = eq(btb_wr_addr, UInt<3>("h04")) @[ifu_bp_ctl.scala 415:95] node _T_589 = and(_T_588, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_590 = bits(_T_589, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_14 of rvclkhdr_108 @[el2_lib.scala 508:23] + inst rvclkhdr_14 of rvclkhdr_108 @[lib.scala 368:23] rvclkhdr_14.clock <= clock rvclkhdr_14.reset <= reset - rvclkhdr_14.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_14.io.en <= _T_590 @[el2_lib.scala 511:17] - rvclkhdr_14.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_4 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_4 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_14.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_14.io.en <= _T_590 @[lib.scala 371:17] + rvclkhdr_14.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_4 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_4 <= btb_wr_data @[lib.scala 374:16] node _T_591 = eq(btb_wr_addr, UInt<3>("h05")) @[ifu_bp_ctl.scala 415:95] node _T_592 = and(_T_591, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_593 = bits(_T_592, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_15 of rvclkhdr_109 @[el2_lib.scala 508:23] + inst rvclkhdr_15 of rvclkhdr_109 @[lib.scala 368:23] rvclkhdr_15.clock <= clock rvclkhdr_15.reset <= reset - rvclkhdr_15.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_15.io.en <= _T_593 @[el2_lib.scala 511:17] - rvclkhdr_15.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_5 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_5 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_15.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_15.io.en <= _T_593 @[lib.scala 371:17] + rvclkhdr_15.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_5 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_5 <= btb_wr_data @[lib.scala 374:16] node _T_594 = eq(btb_wr_addr, UInt<3>("h06")) @[ifu_bp_ctl.scala 415:95] node _T_595 = and(_T_594, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_596 = bits(_T_595, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_16 of rvclkhdr_110 @[el2_lib.scala 508:23] + inst rvclkhdr_16 of rvclkhdr_110 @[lib.scala 368:23] rvclkhdr_16.clock <= clock rvclkhdr_16.reset <= reset - rvclkhdr_16.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_16.io.en <= _T_596 @[el2_lib.scala 511:17] - rvclkhdr_16.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_6 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_6 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_16.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_16.io.en <= _T_596 @[lib.scala 371:17] + rvclkhdr_16.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_6 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_6 <= btb_wr_data @[lib.scala 374:16] node _T_597 = eq(btb_wr_addr, UInt<3>("h07")) @[ifu_bp_ctl.scala 415:95] node _T_598 = and(_T_597, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_599 = bits(_T_598, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_17 of rvclkhdr_111 @[el2_lib.scala 508:23] + inst rvclkhdr_17 of rvclkhdr_111 @[lib.scala 368:23] rvclkhdr_17.clock <= clock rvclkhdr_17.reset <= reset - rvclkhdr_17.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_17.io.en <= _T_599 @[el2_lib.scala 511:17] - rvclkhdr_17.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_7 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_7 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_17.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_17.io.en <= _T_599 @[lib.scala 371:17] + rvclkhdr_17.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_7 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_7 <= btb_wr_data @[lib.scala 374:16] node _T_600 = eq(btb_wr_addr, UInt<4>("h08")) @[ifu_bp_ctl.scala 415:95] node _T_601 = and(_T_600, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_602 = bits(_T_601, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_18 of rvclkhdr_112 @[el2_lib.scala 508:23] + inst rvclkhdr_18 of rvclkhdr_112 @[lib.scala 368:23] rvclkhdr_18.clock <= clock rvclkhdr_18.reset <= reset - rvclkhdr_18.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_18.io.en <= _T_602 @[el2_lib.scala 511:17] - rvclkhdr_18.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_8 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_8 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_18.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_18.io.en <= _T_602 @[lib.scala 371:17] + rvclkhdr_18.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_8 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_8 <= btb_wr_data @[lib.scala 374:16] node _T_603 = eq(btb_wr_addr, UInt<4>("h09")) @[ifu_bp_ctl.scala 415:95] node _T_604 = and(_T_603, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_605 = bits(_T_604, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_19 of rvclkhdr_113 @[el2_lib.scala 508:23] + inst rvclkhdr_19 of rvclkhdr_113 @[lib.scala 368:23] rvclkhdr_19.clock <= clock rvclkhdr_19.reset <= reset - rvclkhdr_19.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_19.io.en <= _T_605 @[el2_lib.scala 511:17] - rvclkhdr_19.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_9 : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_9 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_19.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_19.io.en <= _T_605 @[lib.scala 371:17] + rvclkhdr_19.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_9 : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_9 <= btb_wr_data @[lib.scala 374:16] node _T_606 = eq(btb_wr_addr, UInt<4>("h0a")) @[ifu_bp_ctl.scala 415:95] node _T_607 = and(_T_606, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_608 = bits(_T_607, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_20 of rvclkhdr_114 @[el2_lib.scala 508:23] + inst rvclkhdr_20 of rvclkhdr_114 @[lib.scala 368:23] rvclkhdr_20.clock <= clock rvclkhdr_20.reset <= reset - rvclkhdr_20.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_20.io.en <= _T_608 @[el2_lib.scala 511:17] - rvclkhdr_20.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_10 : UInt, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_10 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_20.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_20.io.en <= _T_608 @[lib.scala 371:17] + rvclkhdr_20.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_10 : UInt, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_10 <= btb_wr_data @[lib.scala 374:16] node _T_609 = eq(btb_wr_addr, UInt<4>("h0b")) @[ifu_bp_ctl.scala 415:95] node _T_610 = and(_T_609, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_611 = bits(_T_610, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_21 of rvclkhdr_115 @[el2_lib.scala 508:23] + inst rvclkhdr_21 of rvclkhdr_115 @[lib.scala 368:23] rvclkhdr_21.clock <= clock rvclkhdr_21.reset <= reset - rvclkhdr_21.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_21.io.en <= _T_611 @[el2_lib.scala 511:17] - rvclkhdr_21.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_11 : UInt, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_11 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_21.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_21.io.en <= _T_611 @[lib.scala 371:17] + rvclkhdr_21.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_11 : UInt, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_11 <= btb_wr_data @[lib.scala 374:16] node _T_612 = eq(btb_wr_addr, UInt<4>("h0c")) @[ifu_bp_ctl.scala 415:95] node _T_613 = and(_T_612, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_614 = bits(_T_613, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_22 of rvclkhdr_116 @[el2_lib.scala 508:23] + inst rvclkhdr_22 of rvclkhdr_116 @[lib.scala 368:23] rvclkhdr_22.clock <= clock rvclkhdr_22.reset <= reset - rvclkhdr_22.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_22.io.en <= _T_614 @[el2_lib.scala 511:17] - rvclkhdr_22.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_12 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_12 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_22.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_22.io.en <= _T_614 @[lib.scala 371:17] + rvclkhdr_22.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_12 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_12 <= btb_wr_data @[lib.scala 374:16] node _T_615 = eq(btb_wr_addr, UInt<4>("h0d")) @[ifu_bp_ctl.scala 415:95] node _T_616 = and(_T_615, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_617 = bits(_T_616, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_23 of rvclkhdr_117 @[el2_lib.scala 508:23] + inst rvclkhdr_23 of rvclkhdr_117 @[lib.scala 368:23] rvclkhdr_23.clock <= clock rvclkhdr_23.reset <= reset - rvclkhdr_23.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_23.io.en <= _T_617 @[el2_lib.scala 511:17] - rvclkhdr_23.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_13 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_13 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_23.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_23.io.en <= _T_617 @[lib.scala 371:17] + rvclkhdr_23.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_13 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_13 <= btb_wr_data @[lib.scala 374:16] node _T_618 = eq(btb_wr_addr, UInt<4>("h0e")) @[ifu_bp_ctl.scala 415:95] node _T_619 = and(_T_618, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_620 = bits(_T_619, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_24 of rvclkhdr_118 @[el2_lib.scala 508:23] + inst rvclkhdr_24 of rvclkhdr_118 @[lib.scala 368:23] rvclkhdr_24.clock <= clock rvclkhdr_24.reset <= reset - rvclkhdr_24.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_24.io.en <= _T_620 @[el2_lib.scala 511:17] - rvclkhdr_24.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_14 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_14 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_24.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_24.io.en <= _T_620 @[lib.scala 371:17] + rvclkhdr_24.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_14 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_14 <= btb_wr_data @[lib.scala 374:16] node _T_621 = eq(btb_wr_addr, UInt<4>("h0f")) @[ifu_bp_ctl.scala 415:95] node _T_622 = and(_T_621, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_623 = bits(_T_622, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_25 of rvclkhdr_119 @[el2_lib.scala 508:23] + inst rvclkhdr_25 of rvclkhdr_119 @[lib.scala 368:23] rvclkhdr_25.clock <= clock rvclkhdr_25.reset <= reset - rvclkhdr_25.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_25.io.en <= _T_623 @[el2_lib.scala 511:17] - rvclkhdr_25.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_15 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_15 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_25.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_25.io.en <= _T_623 @[lib.scala 371:17] + rvclkhdr_25.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_15 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_15 <= btb_wr_data @[lib.scala 374:16] node _T_624 = eq(btb_wr_addr, UInt<5>("h010")) @[ifu_bp_ctl.scala 415:95] node _T_625 = and(_T_624, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_626 = bits(_T_625, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_26 of rvclkhdr_120 @[el2_lib.scala 508:23] + inst rvclkhdr_26 of rvclkhdr_120 @[lib.scala 368:23] rvclkhdr_26.clock <= clock rvclkhdr_26.reset <= reset - rvclkhdr_26.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_26.io.en <= _T_626 @[el2_lib.scala 511:17] - rvclkhdr_26.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_16 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_16 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_26.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_26.io.en <= _T_626 @[lib.scala 371:17] + rvclkhdr_26.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_16 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_16 <= btb_wr_data @[lib.scala 374:16] node _T_627 = eq(btb_wr_addr, UInt<5>("h011")) @[ifu_bp_ctl.scala 415:95] node _T_628 = and(_T_627, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_629 = bits(_T_628, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_27 of rvclkhdr_121 @[el2_lib.scala 508:23] + inst rvclkhdr_27 of rvclkhdr_121 @[lib.scala 368:23] rvclkhdr_27.clock <= clock rvclkhdr_27.reset <= reset - rvclkhdr_27.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_27.io.en <= _T_629 @[el2_lib.scala 511:17] - rvclkhdr_27.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_17 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_17 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_27.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_27.io.en <= _T_629 @[lib.scala 371:17] + rvclkhdr_27.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_17 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_17 <= btb_wr_data @[lib.scala 374:16] node _T_630 = eq(btb_wr_addr, UInt<5>("h012")) @[ifu_bp_ctl.scala 415:95] node _T_631 = and(_T_630, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_632 = bits(_T_631, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_28 of rvclkhdr_122 @[el2_lib.scala 508:23] + inst rvclkhdr_28 of rvclkhdr_122 @[lib.scala 368:23] rvclkhdr_28.clock <= clock rvclkhdr_28.reset <= reset - rvclkhdr_28.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_28.io.en <= _T_632 @[el2_lib.scala 511:17] - rvclkhdr_28.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_18 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_18 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_28.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_28.io.en <= _T_632 @[lib.scala 371:17] + rvclkhdr_28.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_18 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_18 <= btb_wr_data @[lib.scala 374:16] node _T_633 = eq(btb_wr_addr, UInt<5>("h013")) @[ifu_bp_ctl.scala 415:95] node _T_634 = and(_T_633, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_635 = bits(_T_634, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_29 of rvclkhdr_123 @[el2_lib.scala 508:23] + inst rvclkhdr_29 of rvclkhdr_123 @[lib.scala 368:23] rvclkhdr_29.clock <= clock rvclkhdr_29.reset <= reset - rvclkhdr_29.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_29.io.en <= _T_635 @[el2_lib.scala 511:17] - rvclkhdr_29.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_19 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_19 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_29.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_29.io.en <= _T_635 @[lib.scala 371:17] + rvclkhdr_29.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_19 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_19 <= btb_wr_data @[lib.scala 374:16] node _T_636 = eq(btb_wr_addr, UInt<5>("h014")) @[ifu_bp_ctl.scala 415:95] node _T_637 = and(_T_636, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_638 = bits(_T_637, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_30 of rvclkhdr_124 @[el2_lib.scala 508:23] + inst rvclkhdr_30 of rvclkhdr_124 @[lib.scala 368:23] rvclkhdr_30.clock <= clock rvclkhdr_30.reset <= reset - rvclkhdr_30.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_30.io.en <= _T_638 @[el2_lib.scala 511:17] - rvclkhdr_30.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_20 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_20 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_30.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_30.io.en <= _T_638 @[lib.scala 371:17] + rvclkhdr_30.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_20 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_20 <= btb_wr_data @[lib.scala 374:16] node _T_639 = eq(btb_wr_addr, UInt<5>("h015")) @[ifu_bp_ctl.scala 415:95] node _T_640 = and(_T_639, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_641 = bits(_T_640, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_31 of rvclkhdr_125 @[el2_lib.scala 508:23] + inst rvclkhdr_31 of rvclkhdr_125 @[lib.scala 368:23] rvclkhdr_31.clock <= clock rvclkhdr_31.reset <= reset - rvclkhdr_31.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_31.io.en <= _T_641 @[el2_lib.scala 511:17] - rvclkhdr_31.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_21 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_21 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_31.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_31.io.en <= _T_641 @[lib.scala 371:17] + rvclkhdr_31.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_21 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_21 <= btb_wr_data @[lib.scala 374:16] node _T_642 = eq(btb_wr_addr, UInt<5>("h016")) @[ifu_bp_ctl.scala 415:95] node _T_643 = and(_T_642, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_644 = bits(_T_643, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_32 of rvclkhdr_126 @[el2_lib.scala 508:23] + inst rvclkhdr_32 of rvclkhdr_126 @[lib.scala 368:23] rvclkhdr_32.clock <= clock rvclkhdr_32.reset <= reset - rvclkhdr_32.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_32.io.en <= _T_644 @[el2_lib.scala 511:17] - rvclkhdr_32.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_22 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_22 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_32.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_32.io.en <= _T_644 @[lib.scala 371:17] + rvclkhdr_32.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_22 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_22 <= btb_wr_data @[lib.scala 374:16] node _T_645 = eq(btb_wr_addr, UInt<5>("h017")) @[ifu_bp_ctl.scala 415:95] node _T_646 = and(_T_645, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_647 = bits(_T_646, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_33 of rvclkhdr_127 @[el2_lib.scala 508:23] + inst rvclkhdr_33 of rvclkhdr_127 @[lib.scala 368:23] rvclkhdr_33.clock <= clock rvclkhdr_33.reset <= reset - rvclkhdr_33.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_33.io.en <= _T_647 @[el2_lib.scala 511:17] - rvclkhdr_33.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_23 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_23 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_33.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_33.io.en <= _T_647 @[lib.scala 371:17] + rvclkhdr_33.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_23 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_23 <= btb_wr_data @[lib.scala 374:16] node _T_648 = eq(btb_wr_addr, UInt<5>("h018")) @[ifu_bp_ctl.scala 415:95] node _T_649 = and(_T_648, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_650 = bits(_T_649, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_34 of rvclkhdr_128 @[el2_lib.scala 508:23] + inst rvclkhdr_34 of rvclkhdr_128 @[lib.scala 368:23] rvclkhdr_34.clock <= clock rvclkhdr_34.reset <= reset - rvclkhdr_34.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_34.io.en <= _T_650 @[el2_lib.scala 511:17] - rvclkhdr_34.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_24 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_24 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_34.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_34.io.en <= _T_650 @[lib.scala 371:17] + rvclkhdr_34.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_24 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_24 <= btb_wr_data @[lib.scala 374:16] node _T_651 = eq(btb_wr_addr, UInt<5>("h019")) @[ifu_bp_ctl.scala 415:95] node _T_652 = and(_T_651, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_653 = bits(_T_652, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_35 of rvclkhdr_129 @[el2_lib.scala 508:23] + inst rvclkhdr_35 of rvclkhdr_129 @[lib.scala 368:23] rvclkhdr_35.clock <= clock rvclkhdr_35.reset <= reset - rvclkhdr_35.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_35.io.en <= _T_653 @[el2_lib.scala 511:17] - rvclkhdr_35.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_25 : UInt, rvclkhdr_35.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_25 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_35.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_35.io.en <= _T_653 @[lib.scala 371:17] + rvclkhdr_35.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_25 : UInt, rvclkhdr_35.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_25 <= btb_wr_data @[lib.scala 374:16] node _T_654 = eq(btb_wr_addr, UInt<5>("h01a")) @[ifu_bp_ctl.scala 415:95] node _T_655 = and(_T_654, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_656 = bits(_T_655, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_36 of rvclkhdr_130 @[el2_lib.scala 508:23] + inst rvclkhdr_36 of rvclkhdr_130 @[lib.scala 368:23] rvclkhdr_36.clock <= clock rvclkhdr_36.reset <= reset - rvclkhdr_36.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_36.io.en <= _T_656 @[el2_lib.scala 511:17] - rvclkhdr_36.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_26 : UInt, rvclkhdr_36.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_26 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_36.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_36.io.en <= _T_656 @[lib.scala 371:17] + rvclkhdr_36.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_26 : UInt, rvclkhdr_36.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_26 <= btb_wr_data @[lib.scala 374:16] node _T_657 = eq(btb_wr_addr, UInt<5>("h01b")) @[ifu_bp_ctl.scala 415:95] node _T_658 = and(_T_657, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_659 = bits(_T_658, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_37 of rvclkhdr_131 @[el2_lib.scala 508:23] + inst rvclkhdr_37 of rvclkhdr_131 @[lib.scala 368:23] rvclkhdr_37.clock <= clock rvclkhdr_37.reset <= reset - rvclkhdr_37.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_37.io.en <= _T_659 @[el2_lib.scala 511:17] - rvclkhdr_37.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_27 : UInt, rvclkhdr_37.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_27 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_37.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_37.io.en <= _T_659 @[lib.scala 371:17] + rvclkhdr_37.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_27 : UInt, rvclkhdr_37.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_27 <= btb_wr_data @[lib.scala 374:16] node _T_660 = eq(btb_wr_addr, UInt<5>("h01c")) @[ifu_bp_ctl.scala 415:95] node _T_661 = and(_T_660, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_662 = bits(_T_661, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_38 of rvclkhdr_132 @[el2_lib.scala 508:23] + inst rvclkhdr_38 of rvclkhdr_132 @[lib.scala 368:23] rvclkhdr_38.clock <= clock rvclkhdr_38.reset <= reset - rvclkhdr_38.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_38.io.en <= _T_662 @[el2_lib.scala 511:17] - rvclkhdr_38.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_28 : UInt, rvclkhdr_38.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_28 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_38.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_38.io.en <= _T_662 @[lib.scala 371:17] + rvclkhdr_38.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_28 : UInt, rvclkhdr_38.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_28 <= btb_wr_data @[lib.scala 374:16] node _T_663 = eq(btb_wr_addr, UInt<5>("h01d")) @[ifu_bp_ctl.scala 415:95] node _T_664 = and(_T_663, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_665 = bits(_T_664, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_39 of rvclkhdr_133 @[el2_lib.scala 508:23] + inst rvclkhdr_39 of rvclkhdr_133 @[lib.scala 368:23] rvclkhdr_39.clock <= clock rvclkhdr_39.reset <= reset - rvclkhdr_39.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_39.io.en <= _T_665 @[el2_lib.scala 511:17] - rvclkhdr_39.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_29 : UInt, rvclkhdr_39.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_29 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_39.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_39.io.en <= _T_665 @[lib.scala 371:17] + rvclkhdr_39.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_29 : UInt, rvclkhdr_39.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_29 <= btb_wr_data @[lib.scala 374:16] node _T_666 = eq(btb_wr_addr, UInt<5>("h01e")) @[ifu_bp_ctl.scala 415:95] node _T_667 = and(_T_666, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_668 = bits(_T_667, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_40 of rvclkhdr_134 @[el2_lib.scala 508:23] + inst rvclkhdr_40 of rvclkhdr_134 @[lib.scala 368:23] rvclkhdr_40.clock <= clock rvclkhdr_40.reset <= reset - rvclkhdr_40.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_40.io.en <= _T_668 @[el2_lib.scala 511:17] - rvclkhdr_40.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_30 : UInt, rvclkhdr_40.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_30 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_40.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_40.io.en <= _T_668 @[lib.scala 371:17] + rvclkhdr_40.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_30 : UInt, rvclkhdr_40.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_30 <= btb_wr_data @[lib.scala 374:16] node _T_669 = eq(btb_wr_addr, UInt<5>("h01f")) @[ifu_bp_ctl.scala 415:95] node _T_670 = and(_T_669, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_671 = bits(_T_670, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_41 of rvclkhdr_135 @[el2_lib.scala 508:23] + inst rvclkhdr_41 of rvclkhdr_135 @[lib.scala 368:23] rvclkhdr_41.clock <= clock rvclkhdr_41.reset <= reset - rvclkhdr_41.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_41.io.en <= _T_671 @[el2_lib.scala 511:17] - rvclkhdr_41.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_31 : UInt, rvclkhdr_41.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_31 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_41.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_41.io.en <= _T_671 @[lib.scala 371:17] + rvclkhdr_41.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_31 : UInt, rvclkhdr_41.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_31 <= btb_wr_data @[lib.scala 374:16] node _T_672 = eq(btb_wr_addr, UInt<6>("h020")) @[ifu_bp_ctl.scala 415:95] node _T_673 = and(_T_672, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_674 = bits(_T_673, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_42 of rvclkhdr_136 @[el2_lib.scala 508:23] + inst rvclkhdr_42 of rvclkhdr_136 @[lib.scala 368:23] rvclkhdr_42.clock <= clock rvclkhdr_42.reset <= reset - rvclkhdr_42.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_42.io.en <= _T_674 @[el2_lib.scala 511:17] - rvclkhdr_42.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_32 : UInt, rvclkhdr_42.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_32 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_42.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_42.io.en <= _T_674 @[lib.scala 371:17] + rvclkhdr_42.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_32 : UInt, rvclkhdr_42.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_32 <= btb_wr_data @[lib.scala 374:16] node _T_675 = eq(btb_wr_addr, UInt<6>("h021")) @[ifu_bp_ctl.scala 415:95] node _T_676 = and(_T_675, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_677 = bits(_T_676, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_43 of rvclkhdr_137 @[el2_lib.scala 508:23] + inst rvclkhdr_43 of rvclkhdr_137 @[lib.scala 368:23] rvclkhdr_43.clock <= clock rvclkhdr_43.reset <= reset - rvclkhdr_43.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_43.io.en <= _T_677 @[el2_lib.scala 511:17] - rvclkhdr_43.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_33 : UInt, rvclkhdr_43.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_33 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_43.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_43.io.en <= _T_677 @[lib.scala 371:17] + rvclkhdr_43.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_33 : UInt, rvclkhdr_43.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_33 <= btb_wr_data @[lib.scala 374:16] node _T_678 = eq(btb_wr_addr, UInt<6>("h022")) @[ifu_bp_ctl.scala 415:95] node _T_679 = and(_T_678, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_680 = bits(_T_679, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_44 of rvclkhdr_138 @[el2_lib.scala 508:23] + inst rvclkhdr_44 of rvclkhdr_138 @[lib.scala 368:23] rvclkhdr_44.clock <= clock rvclkhdr_44.reset <= reset - rvclkhdr_44.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_44.io.en <= _T_680 @[el2_lib.scala 511:17] - rvclkhdr_44.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_34 : UInt, rvclkhdr_44.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_34 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_44.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_44.io.en <= _T_680 @[lib.scala 371:17] + rvclkhdr_44.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_34 : UInt, rvclkhdr_44.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_34 <= btb_wr_data @[lib.scala 374:16] node _T_681 = eq(btb_wr_addr, UInt<6>("h023")) @[ifu_bp_ctl.scala 415:95] node _T_682 = and(_T_681, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_683 = bits(_T_682, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_45 of rvclkhdr_139 @[el2_lib.scala 508:23] + inst rvclkhdr_45 of rvclkhdr_139 @[lib.scala 368:23] rvclkhdr_45.clock <= clock rvclkhdr_45.reset <= reset - rvclkhdr_45.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_45.io.en <= _T_683 @[el2_lib.scala 511:17] - rvclkhdr_45.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_35 : UInt, rvclkhdr_45.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_35 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_45.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_45.io.en <= _T_683 @[lib.scala 371:17] + rvclkhdr_45.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_35 : UInt, rvclkhdr_45.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_35 <= btb_wr_data @[lib.scala 374:16] node _T_684 = eq(btb_wr_addr, UInt<6>("h024")) @[ifu_bp_ctl.scala 415:95] node _T_685 = and(_T_684, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_686 = bits(_T_685, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_46 of rvclkhdr_140 @[el2_lib.scala 508:23] + inst rvclkhdr_46 of rvclkhdr_140 @[lib.scala 368:23] rvclkhdr_46.clock <= clock rvclkhdr_46.reset <= reset - rvclkhdr_46.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_46.io.en <= _T_686 @[el2_lib.scala 511:17] - rvclkhdr_46.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_36 : UInt, rvclkhdr_46.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_36 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_46.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_46.io.en <= _T_686 @[lib.scala 371:17] + rvclkhdr_46.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_36 : UInt, rvclkhdr_46.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_36 <= btb_wr_data @[lib.scala 374:16] node _T_687 = eq(btb_wr_addr, UInt<6>("h025")) @[ifu_bp_ctl.scala 415:95] node _T_688 = and(_T_687, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_689 = bits(_T_688, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_47 of rvclkhdr_141 @[el2_lib.scala 508:23] + inst rvclkhdr_47 of rvclkhdr_141 @[lib.scala 368:23] rvclkhdr_47.clock <= clock rvclkhdr_47.reset <= reset - rvclkhdr_47.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_47.io.en <= _T_689 @[el2_lib.scala 511:17] - rvclkhdr_47.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_37 : UInt, rvclkhdr_47.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_37 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_47.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_47.io.en <= _T_689 @[lib.scala 371:17] + rvclkhdr_47.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_37 : UInt, rvclkhdr_47.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_37 <= btb_wr_data @[lib.scala 374:16] node _T_690 = eq(btb_wr_addr, UInt<6>("h026")) @[ifu_bp_ctl.scala 415:95] node _T_691 = and(_T_690, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_692 = bits(_T_691, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_48 of rvclkhdr_142 @[el2_lib.scala 508:23] + inst rvclkhdr_48 of rvclkhdr_142 @[lib.scala 368:23] rvclkhdr_48.clock <= clock rvclkhdr_48.reset <= reset - rvclkhdr_48.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_48.io.en <= _T_692 @[el2_lib.scala 511:17] - rvclkhdr_48.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_38 : UInt, rvclkhdr_48.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_38 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_48.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_48.io.en <= _T_692 @[lib.scala 371:17] + rvclkhdr_48.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_38 : UInt, rvclkhdr_48.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_38 <= btb_wr_data @[lib.scala 374:16] node _T_693 = eq(btb_wr_addr, UInt<6>("h027")) @[ifu_bp_ctl.scala 415:95] node _T_694 = and(_T_693, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_695 = bits(_T_694, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_49 of rvclkhdr_143 @[el2_lib.scala 508:23] + inst rvclkhdr_49 of rvclkhdr_143 @[lib.scala 368:23] rvclkhdr_49.clock <= clock rvclkhdr_49.reset <= reset - rvclkhdr_49.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_49.io.en <= _T_695 @[el2_lib.scala 511:17] - rvclkhdr_49.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_39 : UInt, rvclkhdr_49.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_39 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_49.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_49.io.en <= _T_695 @[lib.scala 371:17] + rvclkhdr_49.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_39 : UInt, rvclkhdr_49.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_39 <= btb_wr_data @[lib.scala 374:16] node _T_696 = eq(btb_wr_addr, UInt<6>("h028")) @[ifu_bp_ctl.scala 415:95] node _T_697 = and(_T_696, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_698 = bits(_T_697, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_50 of rvclkhdr_144 @[el2_lib.scala 508:23] + inst rvclkhdr_50 of rvclkhdr_144 @[lib.scala 368:23] rvclkhdr_50.clock <= clock rvclkhdr_50.reset <= reset - rvclkhdr_50.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_50.io.en <= _T_698 @[el2_lib.scala 511:17] - rvclkhdr_50.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_40 : UInt, rvclkhdr_50.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_40 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_50.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_50.io.en <= _T_698 @[lib.scala 371:17] + rvclkhdr_50.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_40 : UInt, rvclkhdr_50.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_40 <= btb_wr_data @[lib.scala 374:16] node _T_699 = eq(btb_wr_addr, UInt<6>("h029")) @[ifu_bp_ctl.scala 415:95] node _T_700 = and(_T_699, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_701 = bits(_T_700, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_51 of rvclkhdr_145 @[el2_lib.scala 508:23] + inst rvclkhdr_51 of rvclkhdr_145 @[lib.scala 368:23] rvclkhdr_51.clock <= clock rvclkhdr_51.reset <= reset - rvclkhdr_51.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_51.io.en <= _T_701 @[el2_lib.scala 511:17] - rvclkhdr_51.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_41 : UInt, rvclkhdr_51.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_41 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_51.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_51.io.en <= _T_701 @[lib.scala 371:17] + rvclkhdr_51.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_41 : UInt, rvclkhdr_51.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_41 <= btb_wr_data @[lib.scala 374:16] node _T_702 = eq(btb_wr_addr, UInt<6>("h02a")) @[ifu_bp_ctl.scala 415:95] node _T_703 = and(_T_702, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_704 = bits(_T_703, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_52 of rvclkhdr_146 @[el2_lib.scala 508:23] + inst rvclkhdr_52 of rvclkhdr_146 @[lib.scala 368:23] rvclkhdr_52.clock <= clock rvclkhdr_52.reset <= reset - rvclkhdr_52.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_52.io.en <= _T_704 @[el2_lib.scala 511:17] - rvclkhdr_52.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_42 : UInt, rvclkhdr_52.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_42 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_52.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_52.io.en <= _T_704 @[lib.scala 371:17] + rvclkhdr_52.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_42 : UInt, rvclkhdr_52.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_42 <= btb_wr_data @[lib.scala 374:16] node _T_705 = eq(btb_wr_addr, UInt<6>("h02b")) @[ifu_bp_ctl.scala 415:95] node _T_706 = and(_T_705, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_707 = bits(_T_706, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_53 of rvclkhdr_147 @[el2_lib.scala 508:23] + inst rvclkhdr_53 of rvclkhdr_147 @[lib.scala 368:23] rvclkhdr_53.clock <= clock rvclkhdr_53.reset <= reset - rvclkhdr_53.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_53.io.en <= _T_707 @[el2_lib.scala 511:17] - rvclkhdr_53.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_43 : UInt, rvclkhdr_53.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_43 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_53.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_53.io.en <= _T_707 @[lib.scala 371:17] + rvclkhdr_53.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_43 : UInt, rvclkhdr_53.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_43 <= btb_wr_data @[lib.scala 374:16] node _T_708 = eq(btb_wr_addr, UInt<6>("h02c")) @[ifu_bp_ctl.scala 415:95] node _T_709 = and(_T_708, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_710 = bits(_T_709, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_54 of rvclkhdr_148 @[el2_lib.scala 508:23] + inst rvclkhdr_54 of rvclkhdr_148 @[lib.scala 368:23] rvclkhdr_54.clock <= clock rvclkhdr_54.reset <= reset - rvclkhdr_54.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_54.io.en <= _T_710 @[el2_lib.scala 511:17] - rvclkhdr_54.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_44 : UInt, rvclkhdr_54.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_44 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_54.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_54.io.en <= _T_710 @[lib.scala 371:17] + rvclkhdr_54.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_44 : UInt, rvclkhdr_54.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_44 <= btb_wr_data @[lib.scala 374:16] node _T_711 = eq(btb_wr_addr, UInt<6>("h02d")) @[ifu_bp_ctl.scala 415:95] node _T_712 = and(_T_711, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_713 = bits(_T_712, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_55 of rvclkhdr_149 @[el2_lib.scala 508:23] + inst rvclkhdr_55 of rvclkhdr_149 @[lib.scala 368:23] rvclkhdr_55.clock <= clock rvclkhdr_55.reset <= reset - rvclkhdr_55.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_55.io.en <= _T_713 @[el2_lib.scala 511:17] - rvclkhdr_55.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_45 : UInt, rvclkhdr_55.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_45 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_55.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_55.io.en <= _T_713 @[lib.scala 371:17] + rvclkhdr_55.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_45 : UInt, rvclkhdr_55.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_45 <= btb_wr_data @[lib.scala 374:16] node _T_714 = eq(btb_wr_addr, UInt<6>("h02e")) @[ifu_bp_ctl.scala 415:95] node _T_715 = and(_T_714, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_716 = bits(_T_715, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_56 of rvclkhdr_150 @[el2_lib.scala 508:23] + inst rvclkhdr_56 of rvclkhdr_150 @[lib.scala 368:23] rvclkhdr_56.clock <= clock rvclkhdr_56.reset <= reset - rvclkhdr_56.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_56.io.en <= _T_716 @[el2_lib.scala 511:17] - rvclkhdr_56.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_46 : UInt, rvclkhdr_56.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_46 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_56.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_56.io.en <= _T_716 @[lib.scala 371:17] + rvclkhdr_56.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_46 : UInt, rvclkhdr_56.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_46 <= btb_wr_data @[lib.scala 374:16] node _T_717 = eq(btb_wr_addr, UInt<6>("h02f")) @[ifu_bp_ctl.scala 415:95] node _T_718 = and(_T_717, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_719 = bits(_T_718, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_57 of rvclkhdr_151 @[el2_lib.scala 508:23] + inst rvclkhdr_57 of rvclkhdr_151 @[lib.scala 368:23] rvclkhdr_57.clock <= clock rvclkhdr_57.reset <= reset - rvclkhdr_57.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_57.io.en <= _T_719 @[el2_lib.scala 511:17] - rvclkhdr_57.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_47 : UInt, rvclkhdr_57.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_47 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_57.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_57.io.en <= _T_719 @[lib.scala 371:17] + rvclkhdr_57.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_47 : UInt, rvclkhdr_57.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_47 <= btb_wr_data @[lib.scala 374:16] node _T_720 = eq(btb_wr_addr, UInt<6>("h030")) @[ifu_bp_ctl.scala 415:95] node _T_721 = and(_T_720, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_722 = bits(_T_721, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_58 of rvclkhdr_152 @[el2_lib.scala 508:23] + inst rvclkhdr_58 of rvclkhdr_152 @[lib.scala 368:23] rvclkhdr_58.clock <= clock rvclkhdr_58.reset <= reset - rvclkhdr_58.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_58.io.en <= _T_722 @[el2_lib.scala 511:17] - rvclkhdr_58.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_48 : UInt, rvclkhdr_58.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_48 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_58.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_58.io.en <= _T_722 @[lib.scala 371:17] + rvclkhdr_58.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_48 : UInt, rvclkhdr_58.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_48 <= btb_wr_data @[lib.scala 374:16] node _T_723 = eq(btb_wr_addr, UInt<6>("h031")) @[ifu_bp_ctl.scala 415:95] node _T_724 = and(_T_723, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_725 = bits(_T_724, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_59 of rvclkhdr_153 @[el2_lib.scala 508:23] + inst rvclkhdr_59 of rvclkhdr_153 @[lib.scala 368:23] rvclkhdr_59.clock <= clock rvclkhdr_59.reset <= reset - rvclkhdr_59.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_59.io.en <= _T_725 @[el2_lib.scala 511:17] - rvclkhdr_59.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_49 : UInt, rvclkhdr_59.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_49 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_59.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_59.io.en <= _T_725 @[lib.scala 371:17] + rvclkhdr_59.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_49 : UInt, rvclkhdr_59.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_49 <= btb_wr_data @[lib.scala 374:16] node _T_726 = eq(btb_wr_addr, UInt<6>("h032")) @[ifu_bp_ctl.scala 415:95] node _T_727 = and(_T_726, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_728 = bits(_T_727, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_60 of rvclkhdr_154 @[el2_lib.scala 508:23] + inst rvclkhdr_60 of rvclkhdr_154 @[lib.scala 368:23] rvclkhdr_60.clock <= clock rvclkhdr_60.reset <= reset - rvclkhdr_60.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_60.io.en <= _T_728 @[el2_lib.scala 511:17] - rvclkhdr_60.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_50 : UInt, rvclkhdr_60.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_50 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_60.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_60.io.en <= _T_728 @[lib.scala 371:17] + rvclkhdr_60.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_50 : UInt, rvclkhdr_60.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_50 <= btb_wr_data @[lib.scala 374:16] node _T_729 = eq(btb_wr_addr, UInt<6>("h033")) @[ifu_bp_ctl.scala 415:95] node _T_730 = and(_T_729, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_731 = bits(_T_730, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_61 of rvclkhdr_155 @[el2_lib.scala 508:23] + inst rvclkhdr_61 of rvclkhdr_155 @[lib.scala 368:23] rvclkhdr_61.clock <= clock rvclkhdr_61.reset <= reset - rvclkhdr_61.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_61.io.en <= _T_731 @[el2_lib.scala 511:17] - rvclkhdr_61.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_51 : UInt, rvclkhdr_61.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_51 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_61.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_61.io.en <= _T_731 @[lib.scala 371:17] + rvclkhdr_61.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_51 : UInt, rvclkhdr_61.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_51 <= btb_wr_data @[lib.scala 374:16] node _T_732 = eq(btb_wr_addr, UInt<6>("h034")) @[ifu_bp_ctl.scala 415:95] node _T_733 = and(_T_732, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_734 = bits(_T_733, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_62 of rvclkhdr_156 @[el2_lib.scala 508:23] + inst rvclkhdr_62 of rvclkhdr_156 @[lib.scala 368:23] rvclkhdr_62.clock <= clock rvclkhdr_62.reset <= reset - rvclkhdr_62.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_62.io.en <= _T_734 @[el2_lib.scala 511:17] - rvclkhdr_62.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_52 : UInt, rvclkhdr_62.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_52 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_62.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_62.io.en <= _T_734 @[lib.scala 371:17] + rvclkhdr_62.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_52 : UInt, rvclkhdr_62.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_52 <= btb_wr_data @[lib.scala 374:16] node _T_735 = eq(btb_wr_addr, UInt<6>("h035")) @[ifu_bp_ctl.scala 415:95] node _T_736 = and(_T_735, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_737 = bits(_T_736, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_63 of rvclkhdr_157 @[el2_lib.scala 508:23] + inst rvclkhdr_63 of rvclkhdr_157 @[lib.scala 368:23] rvclkhdr_63.clock <= clock rvclkhdr_63.reset <= reset - rvclkhdr_63.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_63.io.en <= _T_737 @[el2_lib.scala 511:17] - rvclkhdr_63.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_53 : UInt, rvclkhdr_63.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_53 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_63.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_63.io.en <= _T_737 @[lib.scala 371:17] + rvclkhdr_63.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_53 : UInt, rvclkhdr_63.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_53 <= btb_wr_data @[lib.scala 374:16] node _T_738 = eq(btb_wr_addr, UInt<6>("h036")) @[ifu_bp_ctl.scala 415:95] node _T_739 = and(_T_738, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_740 = bits(_T_739, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_64 of rvclkhdr_158 @[el2_lib.scala 508:23] + inst rvclkhdr_64 of rvclkhdr_158 @[lib.scala 368:23] rvclkhdr_64.clock <= clock rvclkhdr_64.reset <= reset - rvclkhdr_64.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_64.io.en <= _T_740 @[el2_lib.scala 511:17] - rvclkhdr_64.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_54 : UInt, rvclkhdr_64.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_54 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_64.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_64.io.en <= _T_740 @[lib.scala 371:17] + rvclkhdr_64.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_54 : UInt, rvclkhdr_64.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_54 <= btb_wr_data @[lib.scala 374:16] node _T_741 = eq(btb_wr_addr, UInt<6>("h037")) @[ifu_bp_ctl.scala 415:95] node _T_742 = and(_T_741, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_743 = bits(_T_742, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_65 of rvclkhdr_159 @[el2_lib.scala 508:23] + inst rvclkhdr_65 of rvclkhdr_159 @[lib.scala 368:23] rvclkhdr_65.clock <= clock rvclkhdr_65.reset <= reset - rvclkhdr_65.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_65.io.en <= _T_743 @[el2_lib.scala 511:17] - rvclkhdr_65.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_55 : UInt, rvclkhdr_65.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_55 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_65.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_65.io.en <= _T_743 @[lib.scala 371:17] + rvclkhdr_65.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_55 : UInt, rvclkhdr_65.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_55 <= btb_wr_data @[lib.scala 374:16] node _T_744 = eq(btb_wr_addr, UInt<6>("h038")) @[ifu_bp_ctl.scala 415:95] node _T_745 = and(_T_744, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_746 = bits(_T_745, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_66 of rvclkhdr_160 @[el2_lib.scala 508:23] + inst rvclkhdr_66 of rvclkhdr_160 @[lib.scala 368:23] rvclkhdr_66.clock <= clock rvclkhdr_66.reset <= reset - rvclkhdr_66.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_66.io.en <= _T_746 @[el2_lib.scala 511:17] - rvclkhdr_66.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_56 : UInt, rvclkhdr_66.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_56 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_66.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_66.io.en <= _T_746 @[lib.scala 371:17] + rvclkhdr_66.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_56 : UInt, rvclkhdr_66.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_56 <= btb_wr_data @[lib.scala 374:16] node _T_747 = eq(btb_wr_addr, UInt<6>("h039")) @[ifu_bp_ctl.scala 415:95] node _T_748 = and(_T_747, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_749 = bits(_T_748, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_67 of rvclkhdr_161 @[el2_lib.scala 508:23] + inst rvclkhdr_67 of rvclkhdr_161 @[lib.scala 368:23] rvclkhdr_67.clock <= clock rvclkhdr_67.reset <= reset - rvclkhdr_67.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_67.io.en <= _T_749 @[el2_lib.scala 511:17] - rvclkhdr_67.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_57 : UInt, rvclkhdr_67.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_57 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_67.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_67.io.en <= _T_749 @[lib.scala 371:17] + rvclkhdr_67.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_57 : UInt, rvclkhdr_67.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_57 <= btb_wr_data @[lib.scala 374:16] node _T_750 = eq(btb_wr_addr, UInt<6>("h03a")) @[ifu_bp_ctl.scala 415:95] node _T_751 = and(_T_750, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_752 = bits(_T_751, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_68 of rvclkhdr_162 @[el2_lib.scala 508:23] + inst rvclkhdr_68 of rvclkhdr_162 @[lib.scala 368:23] rvclkhdr_68.clock <= clock rvclkhdr_68.reset <= reset - rvclkhdr_68.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_68.io.en <= _T_752 @[el2_lib.scala 511:17] - rvclkhdr_68.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_58 : UInt, rvclkhdr_68.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_58 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_68.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_68.io.en <= _T_752 @[lib.scala 371:17] + rvclkhdr_68.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_58 : UInt, rvclkhdr_68.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_58 <= btb_wr_data @[lib.scala 374:16] node _T_753 = eq(btb_wr_addr, UInt<6>("h03b")) @[ifu_bp_ctl.scala 415:95] node _T_754 = and(_T_753, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_755 = bits(_T_754, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_69 of rvclkhdr_163 @[el2_lib.scala 508:23] + inst rvclkhdr_69 of rvclkhdr_163 @[lib.scala 368:23] rvclkhdr_69.clock <= clock rvclkhdr_69.reset <= reset - rvclkhdr_69.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_69.io.en <= _T_755 @[el2_lib.scala 511:17] - rvclkhdr_69.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_59 : UInt, rvclkhdr_69.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_59 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_69.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_69.io.en <= _T_755 @[lib.scala 371:17] + rvclkhdr_69.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_59 : UInt, rvclkhdr_69.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_59 <= btb_wr_data @[lib.scala 374:16] node _T_756 = eq(btb_wr_addr, UInt<6>("h03c")) @[ifu_bp_ctl.scala 415:95] node _T_757 = and(_T_756, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_758 = bits(_T_757, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_70 of rvclkhdr_164 @[el2_lib.scala 508:23] + inst rvclkhdr_70 of rvclkhdr_164 @[lib.scala 368:23] rvclkhdr_70.clock <= clock rvclkhdr_70.reset <= reset - rvclkhdr_70.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_70.io.en <= _T_758 @[el2_lib.scala 511:17] - rvclkhdr_70.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_60 : UInt, rvclkhdr_70.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_60 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_70.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_70.io.en <= _T_758 @[lib.scala 371:17] + rvclkhdr_70.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_60 : UInt, rvclkhdr_70.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_60 <= btb_wr_data @[lib.scala 374:16] node _T_759 = eq(btb_wr_addr, UInt<6>("h03d")) @[ifu_bp_ctl.scala 415:95] node _T_760 = and(_T_759, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_761 = bits(_T_760, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_71 of rvclkhdr_165 @[el2_lib.scala 508:23] + inst rvclkhdr_71 of rvclkhdr_165 @[lib.scala 368:23] rvclkhdr_71.clock <= clock rvclkhdr_71.reset <= reset - rvclkhdr_71.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_71.io.en <= _T_761 @[el2_lib.scala 511:17] - rvclkhdr_71.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_61 : UInt, rvclkhdr_71.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_61 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_71.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_71.io.en <= _T_761 @[lib.scala 371:17] + rvclkhdr_71.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_61 : UInt, rvclkhdr_71.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_61 <= btb_wr_data @[lib.scala 374:16] node _T_762 = eq(btb_wr_addr, UInt<6>("h03e")) @[ifu_bp_ctl.scala 415:95] node _T_763 = and(_T_762, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_764 = bits(_T_763, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_72 of rvclkhdr_166 @[el2_lib.scala 508:23] + inst rvclkhdr_72 of rvclkhdr_166 @[lib.scala 368:23] rvclkhdr_72.clock <= clock rvclkhdr_72.reset <= reset - rvclkhdr_72.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_72.io.en <= _T_764 @[el2_lib.scala 511:17] - rvclkhdr_72.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_62 : UInt, rvclkhdr_72.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_62 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_72.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_72.io.en <= _T_764 @[lib.scala 371:17] + rvclkhdr_72.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_62 : UInt, rvclkhdr_72.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_62 <= btb_wr_data @[lib.scala 374:16] node _T_765 = eq(btb_wr_addr, UInt<6>("h03f")) @[ifu_bp_ctl.scala 415:95] node _T_766 = and(_T_765, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_767 = bits(_T_766, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_73 of rvclkhdr_167 @[el2_lib.scala 508:23] + inst rvclkhdr_73 of rvclkhdr_167 @[lib.scala 368:23] rvclkhdr_73.clock <= clock rvclkhdr_73.reset <= reset - rvclkhdr_73.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_73.io.en <= _T_767 @[el2_lib.scala 511:17] - rvclkhdr_73.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_63 : UInt, rvclkhdr_73.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_63 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_73.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_73.io.en <= _T_767 @[lib.scala 371:17] + rvclkhdr_73.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_63 : UInt, rvclkhdr_73.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_63 <= btb_wr_data @[lib.scala 374:16] node _T_768 = eq(btb_wr_addr, UInt<7>("h040")) @[ifu_bp_ctl.scala 415:95] node _T_769 = and(_T_768, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_770 = bits(_T_769, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_74 of rvclkhdr_168 @[el2_lib.scala 508:23] + inst rvclkhdr_74 of rvclkhdr_168 @[lib.scala 368:23] rvclkhdr_74.clock <= clock rvclkhdr_74.reset <= reset - rvclkhdr_74.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_74.io.en <= _T_770 @[el2_lib.scala 511:17] - rvclkhdr_74.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_64 : UInt, rvclkhdr_74.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_64 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_74.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_74.io.en <= _T_770 @[lib.scala 371:17] + rvclkhdr_74.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_64 : UInt, rvclkhdr_74.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_64 <= btb_wr_data @[lib.scala 374:16] node _T_771 = eq(btb_wr_addr, UInt<7>("h041")) @[ifu_bp_ctl.scala 415:95] node _T_772 = and(_T_771, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_773 = bits(_T_772, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_75 of rvclkhdr_169 @[el2_lib.scala 508:23] + inst rvclkhdr_75 of rvclkhdr_169 @[lib.scala 368:23] rvclkhdr_75.clock <= clock rvclkhdr_75.reset <= reset - rvclkhdr_75.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_75.io.en <= _T_773 @[el2_lib.scala 511:17] - rvclkhdr_75.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_65 : UInt, rvclkhdr_75.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_65 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_75.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_75.io.en <= _T_773 @[lib.scala 371:17] + rvclkhdr_75.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_65 : UInt, rvclkhdr_75.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_65 <= btb_wr_data @[lib.scala 374:16] node _T_774 = eq(btb_wr_addr, UInt<7>("h042")) @[ifu_bp_ctl.scala 415:95] node _T_775 = and(_T_774, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_776 = bits(_T_775, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_76 of rvclkhdr_170 @[el2_lib.scala 508:23] + inst rvclkhdr_76 of rvclkhdr_170 @[lib.scala 368:23] rvclkhdr_76.clock <= clock rvclkhdr_76.reset <= reset - rvclkhdr_76.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_76.io.en <= _T_776 @[el2_lib.scala 511:17] - rvclkhdr_76.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_66 : UInt, rvclkhdr_76.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_66 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_76.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_76.io.en <= _T_776 @[lib.scala 371:17] + rvclkhdr_76.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_66 : UInt, rvclkhdr_76.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_66 <= btb_wr_data @[lib.scala 374:16] node _T_777 = eq(btb_wr_addr, UInt<7>("h043")) @[ifu_bp_ctl.scala 415:95] node _T_778 = and(_T_777, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_779 = bits(_T_778, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_77 of rvclkhdr_171 @[el2_lib.scala 508:23] + inst rvclkhdr_77 of rvclkhdr_171 @[lib.scala 368:23] rvclkhdr_77.clock <= clock rvclkhdr_77.reset <= reset - rvclkhdr_77.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_77.io.en <= _T_779 @[el2_lib.scala 511:17] - rvclkhdr_77.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_67 : UInt, rvclkhdr_77.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_67 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_77.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_77.io.en <= _T_779 @[lib.scala 371:17] + rvclkhdr_77.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_67 : UInt, rvclkhdr_77.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_67 <= btb_wr_data @[lib.scala 374:16] node _T_780 = eq(btb_wr_addr, UInt<7>("h044")) @[ifu_bp_ctl.scala 415:95] node _T_781 = and(_T_780, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_782 = bits(_T_781, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_78 of rvclkhdr_172 @[el2_lib.scala 508:23] + inst rvclkhdr_78 of rvclkhdr_172 @[lib.scala 368:23] rvclkhdr_78.clock <= clock rvclkhdr_78.reset <= reset - rvclkhdr_78.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_78.io.en <= _T_782 @[el2_lib.scala 511:17] - rvclkhdr_78.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_68 : UInt, rvclkhdr_78.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_68 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_78.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_78.io.en <= _T_782 @[lib.scala 371:17] + rvclkhdr_78.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_68 : UInt, rvclkhdr_78.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_68 <= btb_wr_data @[lib.scala 374:16] node _T_783 = eq(btb_wr_addr, UInt<7>("h045")) @[ifu_bp_ctl.scala 415:95] node _T_784 = and(_T_783, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_785 = bits(_T_784, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_79 of rvclkhdr_173 @[el2_lib.scala 508:23] + inst rvclkhdr_79 of rvclkhdr_173 @[lib.scala 368:23] rvclkhdr_79.clock <= clock rvclkhdr_79.reset <= reset - rvclkhdr_79.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_79.io.en <= _T_785 @[el2_lib.scala 511:17] - rvclkhdr_79.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_69 : UInt, rvclkhdr_79.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_69 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_79.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_79.io.en <= _T_785 @[lib.scala 371:17] + rvclkhdr_79.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_69 : UInt, rvclkhdr_79.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_69 <= btb_wr_data @[lib.scala 374:16] node _T_786 = eq(btb_wr_addr, UInt<7>("h046")) @[ifu_bp_ctl.scala 415:95] node _T_787 = and(_T_786, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_788 = bits(_T_787, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_80 of rvclkhdr_174 @[el2_lib.scala 508:23] + inst rvclkhdr_80 of rvclkhdr_174 @[lib.scala 368:23] rvclkhdr_80.clock <= clock rvclkhdr_80.reset <= reset - rvclkhdr_80.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_80.io.en <= _T_788 @[el2_lib.scala 511:17] - rvclkhdr_80.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_70 : UInt, rvclkhdr_80.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_70 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_80.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_80.io.en <= _T_788 @[lib.scala 371:17] + rvclkhdr_80.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_70 : UInt, rvclkhdr_80.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_70 <= btb_wr_data @[lib.scala 374:16] node _T_789 = eq(btb_wr_addr, UInt<7>("h047")) @[ifu_bp_ctl.scala 415:95] node _T_790 = and(_T_789, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_791 = bits(_T_790, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_81 of rvclkhdr_175 @[el2_lib.scala 508:23] + inst rvclkhdr_81 of rvclkhdr_175 @[lib.scala 368:23] rvclkhdr_81.clock <= clock rvclkhdr_81.reset <= reset - rvclkhdr_81.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_81.io.en <= _T_791 @[el2_lib.scala 511:17] - rvclkhdr_81.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_71 : UInt, rvclkhdr_81.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_71 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_81.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_81.io.en <= _T_791 @[lib.scala 371:17] + rvclkhdr_81.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_71 : UInt, rvclkhdr_81.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_71 <= btb_wr_data @[lib.scala 374:16] node _T_792 = eq(btb_wr_addr, UInt<7>("h048")) @[ifu_bp_ctl.scala 415:95] node _T_793 = and(_T_792, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_794 = bits(_T_793, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_82 of rvclkhdr_176 @[el2_lib.scala 508:23] + inst rvclkhdr_82 of rvclkhdr_176 @[lib.scala 368:23] rvclkhdr_82.clock <= clock rvclkhdr_82.reset <= reset - rvclkhdr_82.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_82.io.en <= _T_794 @[el2_lib.scala 511:17] - rvclkhdr_82.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_72 : UInt, rvclkhdr_82.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_72 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_82.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_82.io.en <= _T_794 @[lib.scala 371:17] + rvclkhdr_82.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_72 : UInt, rvclkhdr_82.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_72 <= btb_wr_data @[lib.scala 374:16] node _T_795 = eq(btb_wr_addr, UInt<7>("h049")) @[ifu_bp_ctl.scala 415:95] node _T_796 = and(_T_795, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_797 = bits(_T_796, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_83 of rvclkhdr_177 @[el2_lib.scala 508:23] + inst rvclkhdr_83 of rvclkhdr_177 @[lib.scala 368:23] rvclkhdr_83.clock <= clock rvclkhdr_83.reset <= reset - rvclkhdr_83.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_83.io.en <= _T_797 @[el2_lib.scala 511:17] - rvclkhdr_83.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_73 : UInt, rvclkhdr_83.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_73 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_83.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_83.io.en <= _T_797 @[lib.scala 371:17] + rvclkhdr_83.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_73 : UInt, rvclkhdr_83.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_73 <= btb_wr_data @[lib.scala 374:16] node _T_798 = eq(btb_wr_addr, UInt<7>("h04a")) @[ifu_bp_ctl.scala 415:95] node _T_799 = and(_T_798, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_800 = bits(_T_799, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_84 of rvclkhdr_178 @[el2_lib.scala 508:23] + inst rvclkhdr_84 of rvclkhdr_178 @[lib.scala 368:23] rvclkhdr_84.clock <= clock rvclkhdr_84.reset <= reset - rvclkhdr_84.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_84.io.en <= _T_800 @[el2_lib.scala 511:17] - rvclkhdr_84.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_74 : UInt, rvclkhdr_84.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_74 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_84.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_84.io.en <= _T_800 @[lib.scala 371:17] + rvclkhdr_84.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_74 : UInt, rvclkhdr_84.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_74 <= btb_wr_data @[lib.scala 374:16] node _T_801 = eq(btb_wr_addr, UInt<7>("h04b")) @[ifu_bp_ctl.scala 415:95] node _T_802 = and(_T_801, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_803 = bits(_T_802, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_85 of rvclkhdr_179 @[el2_lib.scala 508:23] + inst rvclkhdr_85 of rvclkhdr_179 @[lib.scala 368:23] rvclkhdr_85.clock <= clock rvclkhdr_85.reset <= reset - rvclkhdr_85.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_85.io.en <= _T_803 @[el2_lib.scala 511:17] - rvclkhdr_85.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_75 : UInt, rvclkhdr_85.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_75 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_85.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_85.io.en <= _T_803 @[lib.scala 371:17] + rvclkhdr_85.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_75 : UInt, rvclkhdr_85.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_75 <= btb_wr_data @[lib.scala 374:16] node _T_804 = eq(btb_wr_addr, UInt<7>("h04c")) @[ifu_bp_ctl.scala 415:95] node _T_805 = and(_T_804, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_806 = bits(_T_805, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_86 of rvclkhdr_180 @[el2_lib.scala 508:23] + inst rvclkhdr_86 of rvclkhdr_180 @[lib.scala 368:23] rvclkhdr_86.clock <= clock rvclkhdr_86.reset <= reset - rvclkhdr_86.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_86.io.en <= _T_806 @[el2_lib.scala 511:17] - rvclkhdr_86.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_76 : UInt, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_76 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_86.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_86.io.en <= _T_806 @[lib.scala 371:17] + rvclkhdr_86.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_76 : UInt, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_76 <= btb_wr_data @[lib.scala 374:16] node _T_807 = eq(btb_wr_addr, UInt<7>("h04d")) @[ifu_bp_ctl.scala 415:95] node _T_808 = and(_T_807, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_809 = bits(_T_808, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_87 of rvclkhdr_181 @[el2_lib.scala 508:23] + inst rvclkhdr_87 of rvclkhdr_181 @[lib.scala 368:23] rvclkhdr_87.clock <= clock rvclkhdr_87.reset <= reset - rvclkhdr_87.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_87.io.en <= _T_809 @[el2_lib.scala 511:17] - rvclkhdr_87.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_77 : UInt, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_77 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_87.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_87.io.en <= _T_809 @[lib.scala 371:17] + rvclkhdr_87.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_77 : UInt, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_77 <= btb_wr_data @[lib.scala 374:16] node _T_810 = eq(btb_wr_addr, UInt<7>("h04e")) @[ifu_bp_ctl.scala 415:95] node _T_811 = and(_T_810, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_812 = bits(_T_811, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_88 of rvclkhdr_182 @[el2_lib.scala 508:23] + inst rvclkhdr_88 of rvclkhdr_182 @[lib.scala 368:23] rvclkhdr_88.clock <= clock rvclkhdr_88.reset <= reset - rvclkhdr_88.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_88.io.en <= _T_812 @[el2_lib.scala 511:17] - rvclkhdr_88.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_78 : UInt, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_78 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_88.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_88.io.en <= _T_812 @[lib.scala 371:17] + rvclkhdr_88.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_78 : UInt, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_78 <= btb_wr_data @[lib.scala 374:16] node _T_813 = eq(btb_wr_addr, UInt<7>("h04f")) @[ifu_bp_ctl.scala 415:95] node _T_814 = and(_T_813, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_815 = bits(_T_814, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_89 of rvclkhdr_183 @[el2_lib.scala 508:23] + inst rvclkhdr_89 of rvclkhdr_183 @[lib.scala 368:23] rvclkhdr_89.clock <= clock rvclkhdr_89.reset <= reset - rvclkhdr_89.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_89.io.en <= _T_815 @[el2_lib.scala 511:17] - rvclkhdr_89.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_79 : UInt, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_79 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_89.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_89.io.en <= _T_815 @[lib.scala 371:17] + rvclkhdr_89.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_79 : UInt, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_79 <= btb_wr_data @[lib.scala 374:16] node _T_816 = eq(btb_wr_addr, UInt<7>("h050")) @[ifu_bp_ctl.scala 415:95] node _T_817 = and(_T_816, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_818 = bits(_T_817, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_90 of rvclkhdr_184 @[el2_lib.scala 508:23] + inst rvclkhdr_90 of rvclkhdr_184 @[lib.scala 368:23] rvclkhdr_90.clock <= clock rvclkhdr_90.reset <= reset - rvclkhdr_90.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_90.io.en <= _T_818 @[el2_lib.scala 511:17] - rvclkhdr_90.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_80 : UInt, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_80 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_90.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_90.io.en <= _T_818 @[lib.scala 371:17] + rvclkhdr_90.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_80 : UInt, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_80 <= btb_wr_data @[lib.scala 374:16] node _T_819 = eq(btb_wr_addr, UInt<7>("h051")) @[ifu_bp_ctl.scala 415:95] node _T_820 = and(_T_819, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_821 = bits(_T_820, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_91 of rvclkhdr_185 @[el2_lib.scala 508:23] + inst rvclkhdr_91 of rvclkhdr_185 @[lib.scala 368:23] rvclkhdr_91.clock <= clock rvclkhdr_91.reset <= reset - rvclkhdr_91.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_91.io.en <= _T_821 @[el2_lib.scala 511:17] - rvclkhdr_91.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_81 : UInt, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_81 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_91.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_91.io.en <= _T_821 @[lib.scala 371:17] + rvclkhdr_91.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_81 : UInt, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_81 <= btb_wr_data @[lib.scala 374:16] node _T_822 = eq(btb_wr_addr, UInt<7>("h052")) @[ifu_bp_ctl.scala 415:95] node _T_823 = and(_T_822, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_824 = bits(_T_823, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_92 of rvclkhdr_186 @[el2_lib.scala 508:23] + inst rvclkhdr_92 of rvclkhdr_186 @[lib.scala 368:23] rvclkhdr_92.clock <= clock rvclkhdr_92.reset <= reset - rvclkhdr_92.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_92.io.en <= _T_824 @[el2_lib.scala 511:17] - rvclkhdr_92.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_82 : UInt, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_82 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_92.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_92.io.en <= _T_824 @[lib.scala 371:17] + rvclkhdr_92.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_82 : UInt, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_82 <= btb_wr_data @[lib.scala 374:16] node _T_825 = eq(btb_wr_addr, UInt<7>("h053")) @[ifu_bp_ctl.scala 415:95] node _T_826 = and(_T_825, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_827 = bits(_T_826, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_93 of rvclkhdr_187 @[el2_lib.scala 508:23] + inst rvclkhdr_93 of rvclkhdr_187 @[lib.scala 368:23] rvclkhdr_93.clock <= clock rvclkhdr_93.reset <= reset - rvclkhdr_93.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_93.io.en <= _T_827 @[el2_lib.scala 511:17] - rvclkhdr_93.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_83 : UInt, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_83 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_93.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_93.io.en <= _T_827 @[lib.scala 371:17] + rvclkhdr_93.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_83 : UInt, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_83 <= btb_wr_data @[lib.scala 374:16] node _T_828 = eq(btb_wr_addr, UInt<7>("h054")) @[ifu_bp_ctl.scala 415:95] node _T_829 = and(_T_828, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_830 = bits(_T_829, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_94 of rvclkhdr_188 @[el2_lib.scala 508:23] + inst rvclkhdr_94 of rvclkhdr_188 @[lib.scala 368:23] rvclkhdr_94.clock <= clock rvclkhdr_94.reset <= reset - rvclkhdr_94.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_94.io.en <= _T_830 @[el2_lib.scala 511:17] - rvclkhdr_94.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_84 : UInt, rvclkhdr_94.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_84 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_94.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_94.io.en <= _T_830 @[lib.scala 371:17] + rvclkhdr_94.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_84 : UInt, rvclkhdr_94.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_84 <= btb_wr_data @[lib.scala 374:16] node _T_831 = eq(btb_wr_addr, UInt<7>("h055")) @[ifu_bp_ctl.scala 415:95] node _T_832 = and(_T_831, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_833 = bits(_T_832, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_95 of rvclkhdr_189 @[el2_lib.scala 508:23] + inst rvclkhdr_95 of rvclkhdr_189 @[lib.scala 368:23] rvclkhdr_95.clock <= clock rvclkhdr_95.reset <= reset - rvclkhdr_95.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_95.io.en <= _T_833 @[el2_lib.scala 511:17] - rvclkhdr_95.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_85 : UInt, rvclkhdr_95.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_85 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_95.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_95.io.en <= _T_833 @[lib.scala 371:17] + rvclkhdr_95.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_85 : UInt, rvclkhdr_95.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_85 <= btb_wr_data @[lib.scala 374:16] node _T_834 = eq(btb_wr_addr, UInt<7>("h056")) @[ifu_bp_ctl.scala 415:95] node _T_835 = and(_T_834, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_836 = bits(_T_835, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_96 of rvclkhdr_190 @[el2_lib.scala 508:23] + inst rvclkhdr_96 of rvclkhdr_190 @[lib.scala 368:23] rvclkhdr_96.clock <= clock rvclkhdr_96.reset <= reset - rvclkhdr_96.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_96.io.en <= _T_836 @[el2_lib.scala 511:17] - rvclkhdr_96.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_86 : UInt, rvclkhdr_96.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_86 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_96.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_96.io.en <= _T_836 @[lib.scala 371:17] + rvclkhdr_96.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_86 : UInt, rvclkhdr_96.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_86 <= btb_wr_data @[lib.scala 374:16] node _T_837 = eq(btb_wr_addr, UInt<7>("h057")) @[ifu_bp_ctl.scala 415:95] node _T_838 = and(_T_837, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_839 = bits(_T_838, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_97 of rvclkhdr_191 @[el2_lib.scala 508:23] + inst rvclkhdr_97 of rvclkhdr_191 @[lib.scala 368:23] rvclkhdr_97.clock <= clock rvclkhdr_97.reset <= reset - rvclkhdr_97.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_97.io.en <= _T_839 @[el2_lib.scala 511:17] - rvclkhdr_97.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_87 : UInt, rvclkhdr_97.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_87 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_97.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_97.io.en <= _T_839 @[lib.scala 371:17] + rvclkhdr_97.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_87 : UInt, rvclkhdr_97.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_87 <= btb_wr_data @[lib.scala 374:16] node _T_840 = eq(btb_wr_addr, UInt<7>("h058")) @[ifu_bp_ctl.scala 415:95] node _T_841 = and(_T_840, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_842 = bits(_T_841, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_98 of rvclkhdr_192 @[el2_lib.scala 508:23] + inst rvclkhdr_98 of rvclkhdr_192 @[lib.scala 368:23] rvclkhdr_98.clock <= clock rvclkhdr_98.reset <= reset - rvclkhdr_98.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_98.io.en <= _T_842 @[el2_lib.scala 511:17] - rvclkhdr_98.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_88 : UInt, rvclkhdr_98.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_88 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_98.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_98.io.en <= _T_842 @[lib.scala 371:17] + rvclkhdr_98.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_88 : UInt, rvclkhdr_98.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_88 <= btb_wr_data @[lib.scala 374:16] node _T_843 = eq(btb_wr_addr, UInt<7>("h059")) @[ifu_bp_ctl.scala 415:95] node _T_844 = and(_T_843, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_845 = bits(_T_844, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_99 of rvclkhdr_193 @[el2_lib.scala 508:23] + inst rvclkhdr_99 of rvclkhdr_193 @[lib.scala 368:23] rvclkhdr_99.clock <= clock rvclkhdr_99.reset <= reset - rvclkhdr_99.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_99.io.en <= _T_845 @[el2_lib.scala 511:17] - rvclkhdr_99.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_89 : UInt, rvclkhdr_99.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_89 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_99.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_99.io.en <= _T_845 @[lib.scala 371:17] + rvclkhdr_99.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_89 : UInt, rvclkhdr_99.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_89 <= btb_wr_data @[lib.scala 374:16] node _T_846 = eq(btb_wr_addr, UInt<7>("h05a")) @[ifu_bp_ctl.scala 415:95] node _T_847 = and(_T_846, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_848 = bits(_T_847, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_100 of rvclkhdr_194 @[el2_lib.scala 508:23] + inst rvclkhdr_100 of rvclkhdr_194 @[lib.scala 368:23] rvclkhdr_100.clock <= clock rvclkhdr_100.reset <= reset - rvclkhdr_100.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_100.io.en <= _T_848 @[el2_lib.scala 511:17] - rvclkhdr_100.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_90 : UInt, rvclkhdr_100.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_90 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_100.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_100.io.en <= _T_848 @[lib.scala 371:17] + rvclkhdr_100.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_90 : UInt, rvclkhdr_100.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_90 <= btb_wr_data @[lib.scala 374:16] node _T_849 = eq(btb_wr_addr, UInt<7>("h05b")) @[ifu_bp_ctl.scala 415:95] node _T_850 = and(_T_849, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_851 = bits(_T_850, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_101 of rvclkhdr_195 @[el2_lib.scala 508:23] + inst rvclkhdr_101 of rvclkhdr_195 @[lib.scala 368:23] rvclkhdr_101.clock <= clock rvclkhdr_101.reset <= reset - rvclkhdr_101.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_101.io.en <= _T_851 @[el2_lib.scala 511:17] - rvclkhdr_101.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_91 : UInt, rvclkhdr_101.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_91 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_101.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_101.io.en <= _T_851 @[lib.scala 371:17] + rvclkhdr_101.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_91 : UInt, rvclkhdr_101.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_91 <= btb_wr_data @[lib.scala 374:16] node _T_852 = eq(btb_wr_addr, UInt<7>("h05c")) @[ifu_bp_ctl.scala 415:95] node _T_853 = and(_T_852, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_854 = bits(_T_853, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_102 of rvclkhdr_196 @[el2_lib.scala 508:23] + inst rvclkhdr_102 of rvclkhdr_196 @[lib.scala 368:23] rvclkhdr_102.clock <= clock rvclkhdr_102.reset <= reset - rvclkhdr_102.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_102.io.en <= _T_854 @[el2_lib.scala 511:17] - rvclkhdr_102.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_92 : UInt, rvclkhdr_102.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_92 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_102.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_102.io.en <= _T_854 @[lib.scala 371:17] + rvclkhdr_102.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_92 : UInt, rvclkhdr_102.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_92 <= btb_wr_data @[lib.scala 374:16] node _T_855 = eq(btb_wr_addr, UInt<7>("h05d")) @[ifu_bp_ctl.scala 415:95] node _T_856 = and(_T_855, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_857 = bits(_T_856, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_103 of rvclkhdr_197 @[el2_lib.scala 508:23] + inst rvclkhdr_103 of rvclkhdr_197 @[lib.scala 368:23] rvclkhdr_103.clock <= clock rvclkhdr_103.reset <= reset - rvclkhdr_103.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_103.io.en <= _T_857 @[el2_lib.scala 511:17] - rvclkhdr_103.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_93 : UInt, rvclkhdr_103.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_93 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_103.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_103.io.en <= _T_857 @[lib.scala 371:17] + rvclkhdr_103.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_93 : UInt, rvclkhdr_103.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_93 <= btb_wr_data @[lib.scala 374:16] node _T_858 = eq(btb_wr_addr, UInt<7>("h05e")) @[ifu_bp_ctl.scala 415:95] node _T_859 = and(_T_858, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_860 = bits(_T_859, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_104 of rvclkhdr_198 @[el2_lib.scala 508:23] + inst rvclkhdr_104 of rvclkhdr_198 @[lib.scala 368:23] rvclkhdr_104.clock <= clock rvclkhdr_104.reset <= reset - rvclkhdr_104.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_104.io.en <= _T_860 @[el2_lib.scala 511:17] - rvclkhdr_104.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_94 : UInt, rvclkhdr_104.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_94 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_104.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_104.io.en <= _T_860 @[lib.scala 371:17] + rvclkhdr_104.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_94 : UInt, rvclkhdr_104.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_94 <= btb_wr_data @[lib.scala 374:16] node _T_861 = eq(btb_wr_addr, UInt<7>("h05f")) @[ifu_bp_ctl.scala 415:95] node _T_862 = and(_T_861, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_863 = bits(_T_862, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_105 of rvclkhdr_199 @[el2_lib.scala 508:23] + inst rvclkhdr_105 of rvclkhdr_199 @[lib.scala 368:23] rvclkhdr_105.clock <= clock rvclkhdr_105.reset <= reset - rvclkhdr_105.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_105.io.en <= _T_863 @[el2_lib.scala 511:17] - rvclkhdr_105.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_95 : UInt, rvclkhdr_105.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_95 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_105.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_105.io.en <= _T_863 @[lib.scala 371:17] + rvclkhdr_105.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_95 : UInt, rvclkhdr_105.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_95 <= btb_wr_data @[lib.scala 374:16] node _T_864 = eq(btb_wr_addr, UInt<7>("h060")) @[ifu_bp_ctl.scala 415:95] node _T_865 = and(_T_864, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_866 = bits(_T_865, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_106 of rvclkhdr_200 @[el2_lib.scala 508:23] + inst rvclkhdr_106 of rvclkhdr_200 @[lib.scala 368:23] rvclkhdr_106.clock <= clock rvclkhdr_106.reset <= reset - rvclkhdr_106.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_106.io.en <= _T_866 @[el2_lib.scala 511:17] - rvclkhdr_106.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_96 : UInt, rvclkhdr_106.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_96 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_106.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_106.io.en <= _T_866 @[lib.scala 371:17] + rvclkhdr_106.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_96 : UInt, rvclkhdr_106.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_96 <= btb_wr_data @[lib.scala 374:16] node _T_867 = eq(btb_wr_addr, UInt<7>("h061")) @[ifu_bp_ctl.scala 415:95] node _T_868 = and(_T_867, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_869 = bits(_T_868, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_107 of rvclkhdr_201 @[el2_lib.scala 508:23] + inst rvclkhdr_107 of rvclkhdr_201 @[lib.scala 368:23] rvclkhdr_107.clock <= clock rvclkhdr_107.reset <= reset - rvclkhdr_107.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_107.io.en <= _T_869 @[el2_lib.scala 511:17] - rvclkhdr_107.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_97 : UInt, rvclkhdr_107.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_97 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_107.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_107.io.en <= _T_869 @[lib.scala 371:17] + rvclkhdr_107.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_97 : UInt, rvclkhdr_107.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_97 <= btb_wr_data @[lib.scala 374:16] node _T_870 = eq(btb_wr_addr, UInt<7>("h062")) @[ifu_bp_ctl.scala 415:95] node _T_871 = and(_T_870, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_872 = bits(_T_871, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_108 of rvclkhdr_202 @[el2_lib.scala 508:23] + inst rvclkhdr_108 of rvclkhdr_202 @[lib.scala 368:23] rvclkhdr_108.clock <= clock rvclkhdr_108.reset <= reset - rvclkhdr_108.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_108.io.en <= _T_872 @[el2_lib.scala 511:17] - rvclkhdr_108.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_98 : UInt, rvclkhdr_108.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_98 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_108.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_108.io.en <= _T_872 @[lib.scala 371:17] + rvclkhdr_108.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_98 : UInt, rvclkhdr_108.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_98 <= btb_wr_data @[lib.scala 374:16] node _T_873 = eq(btb_wr_addr, UInt<7>("h063")) @[ifu_bp_ctl.scala 415:95] node _T_874 = and(_T_873, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_875 = bits(_T_874, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_109 of rvclkhdr_203 @[el2_lib.scala 508:23] + inst rvclkhdr_109 of rvclkhdr_203 @[lib.scala 368:23] rvclkhdr_109.clock <= clock rvclkhdr_109.reset <= reset - rvclkhdr_109.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_109.io.en <= _T_875 @[el2_lib.scala 511:17] - rvclkhdr_109.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_99 : UInt, rvclkhdr_109.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_99 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_109.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_109.io.en <= _T_875 @[lib.scala 371:17] + rvclkhdr_109.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_99 : UInt, rvclkhdr_109.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_99 <= btb_wr_data @[lib.scala 374:16] node _T_876 = eq(btb_wr_addr, UInt<7>("h064")) @[ifu_bp_ctl.scala 415:95] node _T_877 = and(_T_876, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_878 = bits(_T_877, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_110 of rvclkhdr_204 @[el2_lib.scala 508:23] + inst rvclkhdr_110 of rvclkhdr_204 @[lib.scala 368:23] rvclkhdr_110.clock <= clock rvclkhdr_110.reset <= reset - rvclkhdr_110.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_110.io.en <= _T_878 @[el2_lib.scala 511:17] - rvclkhdr_110.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_100 : UInt, rvclkhdr_110.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_100 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_110.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_110.io.en <= _T_878 @[lib.scala 371:17] + rvclkhdr_110.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_100 : UInt, rvclkhdr_110.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_100 <= btb_wr_data @[lib.scala 374:16] node _T_879 = eq(btb_wr_addr, UInt<7>("h065")) @[ifu_bp_ctl.scala 415:95] node _T_880 = and(_T_879, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_881 = bits(_T_880, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_111 of rvclkhdr_205 @[el2_lib.scala 508:23] + inst rvclkhdr_111 of rvclkhdr_205 @[lib.scala 368:23] rvclkhdr_111.clock <= clock rvclkhdr_111.reset <= reset - rvclkhdr_111.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_111.io.en <= _T_881 @[el2_lib.scala 511:17] - rvclkhdr_111.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_101 : UInt, rvclkhdr_111.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_101 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_111.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_111.io.en <= _T_881 @[lib.scala 371:17] + rvclkhdr_111.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_101 : UInt, rvclkhdr_111.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_101 <= btb_wr_data @[lib.scala 374:16] node _T_882 = eq(btb_wr_addr, UInt<7>("h066")) @[ifu_bp_ctl.scala 415:95] node _T_883 = and(_T_882, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_884 = bits(_T_883, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_112 of rvclkhdr_206 @[el2_lib.scala 508:23] + inst rvclkhdr_112 of rvclkhdr_206 @[lib.scala 368:23] rvclkhdr_112.clock <= clock rvclkhdr_112.reset <= reset - rvclkhdr_112.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_112.io.en <= _T_884 @[el2_lib.scala 511:17] - rvclkhdr_112.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_102 : UInt, rvclkhdr_112.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_102 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_112.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_112.io.en <= _T_884 @[lib.scala 371:17] + rvclkhdr_112.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_102 : UInt, rvclkhdr_112.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_102 <= btb_wr_data @[lib.scala 374:16] node _T_885 = eq(btb_wr_addr, UInt<7>("h067")) @[ifu_bp_ctl.scala 415:95] node _T_886 = and(_T_885, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_887 = bits(_T_886, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_113 of rvclkhdr_207 @[el2_lib.scala 508:23] + inst rvclkhdr_113 of rvclkhdr_207 @[lib.scala 368:23] rvclkhdr_113.clock <= clock rvclkhdr_113.reset <= reset - rvclkhdr_113.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_113.io.en <= _T_887 @[el2_lib.scala 511:17] - rvclkhdr_113.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_103 : UInt, rvclkhdr_113.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_103 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_113.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_113.io.en <= _T_887 @[lib.scala 371:17] + rvclkhdr_113.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_103 : UInt, rvclkhdr_113.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_103 <= btb_wr_data @[lib.scala 374:16] node _T_888 = eq(btb_wr_addr, UInt<7>("h068")) @[ifu_bp_ctl.scala 415:95] node _T_889 = and(_T_888, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_890 = bits(_T_889, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_114 of rvclkhdr_208 @[el2_lib.scala 508:23] + inst rvclkhdr_114 of rvclkhdr_208 @[lib.scala 368:23] rvclkhdr_114.clock <= clock rvclkhdr_114.reset <= reset - rvclkhdr_114.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_114.io.en <= _T_890 @[el2_lib.scala 511:17] - rvclkhdr_114.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_104 : UInt, rvclkhdr_114.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_104 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_114.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_114.io.en <= _T_890 @[lib.scala 371:17] + rvclkhdr_114.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_104 : UInt, rvclkhdr_114.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_104 <= btb_wr_data @[lib.scala 374:16] node _T_891 = eq(btb_wr_addr, UInt<7>("h069")) @[ifu_bp_ctl.scala 415:95] node _T_892 = and(_T_891, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_893 = bits(_T_892, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_115 of rvclkhdr_209 @[el2_lib.scala 508:23] + inst rvclkhdr_115 of rvclkhdr_209 @[lib.scala 368:23] rvclkhdr_115.clock <= clock rvclkhdr_115.reset <= reset - rvclkhdr_115.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_115.io.en <= _T_893 @[el2_lib.scala 511:17] - rvclkhdr_115.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_105 : UInt, rvclkhdr_115.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_105 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_115.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_115.io.en <= _T_893 @[lib.scala 371:17] + rvclkhdr_115.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_105 : UInt, rvclkhdr_115.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_105 <= btb_wr_data @[lib.scala 374:16] node _T_894 = eq(btb_wr_addr, UInt<7>("h06a")) @[ifu_bp_ctl.scala 415:95] node _T_895 = and(_T_894, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_896 = bits(_T_895, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_116 of rvclkhdr_210 @[el2_lib.scala 508:23] + inst rvclkhdr_116 of rvclkhdr_210 @[lib.scala 368:23] rvclkhdr_116.clock <= clock rvclkhdr_116.reset <= reset - rvclkhdr_116.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_116.io.en <= _T_896 @[el2_lib.scala 511:17] - rvclkhdr_116.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_106 : UInt, rvclkhdr_116.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_106 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_116.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_116.io.en <= _T_896 @[lib.scala 371:17] + rvclkhdr_116.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_106 : UInt, rvclkhdr_116.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_106 <= btb_wr_data @[lib.scala 374:16] node _T_897 = eq(btb_wr_addr, UInt<7>("h06b")) @[ifu_bp_ctl.scala 415:95] node _T_898 = and(_T_897, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_899 = bits(_T_898, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_117 of rvclkhdr_211 @[el2_lib.scala 508:23] + inst rvclkhdr_117 of rvclkhdr_211 @[lib.scala 368:23] rvclkhdr_117.clock <= clock rvclkhdr_117.reset <= reset - rvclkhdr_117.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_117.io.en <= _T_899 @[el2_lib.scala 511:17] - rvclkhdr_117.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_107 : UInt, rvclkhdr_117.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_107 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_117.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_117.io.en <= _T_899 @[lib.scala 371:17] + rvclkhdr_117.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_107 : UInt, rvclkhdr_117.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_107 <= btb_wr_data @[lib.scala 374:16] node _T_900 = eq(btb_wr_addr, UInt<7>("h06c")) @[ifu_bp_ctl.scala 415:95] node _T_901 = and(_T_900, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_902 = bits(_T_901, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_118 of rvclkhdr_212 @[el2_lib.scala 508:23] + inst rvclkhdr_118 of rvclkhdr_212 @[lib.scala 368:23] rvclkhdr_118.clock <= clock rvclkhdr_118.reset <= reset - rvclkhdr_118.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_118.io.en <= _T_902 @[el2_lib.scala 511:17] - rvclkhdr_118.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_108 : UInt, rvclkhdr_118.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_108 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_118.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_118.io.en <= _T_902 @[lib.scala 371:17] + rvclkhdr_118.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_108 : UInt, rvclkhdr_118.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_108 <= btb_wr_data @[lib.scala 374:16] node _T_903 = eq(btb_wr_addr, UInt<7>("h06d")) @[ifu_bp_ctl.scala 415:95] node _T_904 = and(_T_903, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_905 = bits(_T_904, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_119 of rvclkhdr_213 @[el2_lib.scala 508:23] + inst rvclkhdr_119 of rvclkhdr_213 @[lib.scala 368:23] rvclkhdr_119.clock <= clock rvclkhdr_119.reset <= reset - rvclkhdr_119.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_119.io.en <= _T_905 @[el2_lib.scala 511:17] - rvclkhdr_119.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_109 : UInt, rvclkhdr_119.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_109 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_119.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_119.io.en <= _T_905 @[lib.scala 371:17] + rvclkhdr_119.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_109 : UInt, rvclkhdr_119.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_109 <= btb_wr_data @[lib.scala 374:16] node _T_906 = eq(btb_wr_addr, UInt<7>("h06e")) @[ifu_bp_ctl.scala 415:95] node _T_907 = and(_T_906, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_908 = bits(_T_907, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_120 of rvclkhdr_214 @[el2_lib.scala 508:23] + inst rvclkhdr_120 of rvclkhdr_214 @[lib.scala 368:23] rvclkhdr_120.clock <= clock rvclkhdr_120.reset <= reset - rvclkhdr_120.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_120.io.en <= _T_908 @[el2_lib.scala 511:17] - rvclkhdr_120.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_110 : UInt, rvclkhdr_120.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_110 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_120.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_120.io.en <= _T_908 @[lib.scala 371:17] + rvclkhdr_120.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_110 : UInt, rvclkhdr_120.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_110 <= btb_wr_data @[lib.scala 374:16] node _T_909 = eq(btb_wr_addr, UInt<7>("h06f")) @[ifu_bp_ctl.scala 415:95] node _T_910 = and(_T_909, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_911 = bits(_T_910, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_121 of rvclkhdr_215 @[el2_lib.scala 508:23] + inst rvclkhdr_121 of rvclkhdr_215 @[lib.scala 368:23] rvclkhdr_121.clock <= clock rvclkhdr_121.reset <= reset - rvclkhdr_121.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_121.io.en <= _T_911 @[el2_lib.scala 511:17] - rvclkhdr_121.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_111 : UInt, rvclkhdr_121.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_111 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_121.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_121.io.en <= _T_911 @[lib.scala 371:17] + rvclkhdr_121.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_111 : UInt, rvclkhdr_121.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_111 <= btb_wr_data @[lib.scala 374:16] node _T_912 = eq(btb_wr_addr, UInt<7>("h070")) @[ifu_bp_ctl.scala 415:95] node _T_913 = and(_T_912, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_914 = bits(_T_913, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_122 of rvclkhdr_216 @[el2_lib.scala 508:23] + inst rvclkhdr_122 of rvclkhdr_216 @[lib.scala 368:23] rvclkhdr_122.clock <= clock rvclkhdr_122.reset <= reset - rvclkhdr_122.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_122.io.en <= _T_914 @[el2_lib.scala 511:17] - rvclkhdr_122.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_112 : UInt, rvclkhdr_122.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_112 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_122.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_122.io.en <= _T_914 @[lib.scala 371:17] + rvclkhdr_122.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_112 : UInt, rvclkhdr_122.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_112 <= btb_wr_data @[lib.scala 374:16] node _T_915 = eq(btb_wr_addr, UInt<7>("h071")) @[ifu_bp_ctl.scala 415:95] node _T_916 = and(_T_915, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_917 = bits(_T_916, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_123 of rvclkhdr_217 @[el2_lib.scala 508:23] + inst rvclkhdr_123 of rvclkhdr_217 @[lib.scala 368:23] rvclkhdr_123.clock <= clock rvclkhdr_123.reset <= reset - rvclkhdr_123.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_123.io.en <= _T_917 @[el2_lib.scala 511:17] - rvclkhdr_123.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_113 : UInt, rvclkhdr_123.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_113 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_123.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_123.io.en <= _T_917 @[lib.scala 371:17] + rvclkhdr_123.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_113 : UInt, rvclkhdr_123.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_113 <= btb_wr_data @[lib.scala 374:16] node _T_918 = eq(btb_wr_addr, UInt<7>("h072")) @[ifu_bp_ctl.scala 415:95] node _T_919 = and(_T_918, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_920 = bits(_T_919, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_124 of rvclkhdr_218 @[el2_lib.scala 508:23] + inst rvclkhdr_124 of rvclkhdr_218 @[lib.scala 368:23] rvclkhdr_124.clock <= clock rvclkhdr_124.reset <= reset - rvclkhdr_124.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_124.io.en <= _T_920 @[el2_lib.scala 511:17] - rvclkhdr_124.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_114 : UInt, rvclkhdr_124.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_114 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_124.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_124.io.en <= _T_920 @[lib.scala 371:17] + rvclkhdr_124.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_114 : UInt, rvclkhdr_124.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_114 <= btb_wr_data @[lib.scala 374:16] node _T_921 = eq(btb_wr_addr, UInt<7>("h073")) @[ifu_bp_ctl.scala 415:95] node _T_922 = and(_T_921, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_923 = bits(_T_922, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_125 of rvclkhdr_219 @[el2_lib.scala 508:23] + inst rvclkhdr_125 of rvclkhdr_219 @[lib.scala 368:23] rvclkhdr_125.clock <= clock rvclkhdr_125.reset <= reset - rvclkhdr_125.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_125.io.en <= _T_923 @[el2_lib.scala 511:17] - rvclkhdr_125.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_115 : UInt, rvclkhdr_125.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_115 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_125.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_125.io.en <= _T_923 @[lib.scala 371:17] + rvclkhdr_125.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_115 : UInt, rvclkhdr_125.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_115 <= btb_wr_data @[lib.scala 374:16] node _T_924 = eq(btb_wr_addr, UInt<7>("h074")) @[ifu_bp_ctl.scala 415:95] node _T_925 = and(_T_924, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_926 = bits(_T_925, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_126 of rvclkhdr_220 @[el2_lib.scala 508:23] + inst rvclkhdr_126 of rvclkhdr_220 @[lib.scala 368:23] rvclkhdr_126.clock <= clock rvclkhdr_126.reset <= reset - rvclkhdr_126.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_126.io.en <= _T_926 @[el2_lib.scala 511:17] - rvclkhdr_126.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_116 : UInt, rvclkhdr_126.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_116 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_126.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_126.io.en <= _T_926 @[lib.scala 371:17] + rvclkhdr_126.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_116 : UInt, rvclkhdr_126.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_116 <= btb_wr_data @[lib.scala 374:16] node _T_927 = eq(btb_wr_addr, UInt<7>("h075")) @[ifu_bp_ctl.scala 415:95] node _T_928 = and(_T_927, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_929 = bits(_T_928, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_127 of rvclkhdr_221 @[el2_lib.scala 508:23] + inst rvclkhdr_127 of rvclkhdr_221 @[lib.scala 368:23] rvclkhdr_127.clock <= clock rvclkhdr_127.reset <= reset - rvclkhdr_127.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_127.io.en <= _T_929 @[el2_lib.scala 511:17] - rvclkhdr_127.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_117 : UInt, rvclkhdr_127.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_117 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_127.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_127.io.en <= _T_929 @[lib.scala 371:17] + rvclkhdr_127.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_117 : UInt, rvclkhdr_127.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_117 <= btb_wr_data @[lib.scala 374:16] node _T_930 = eq(btb_wr_addr, UInt<7>("h076")) @[ifu_bp_ctl.scala 415:95] node _T_931 = and(_T_930, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_932 = bits(_T_931, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_128 of rvclkhdr_222 @[el2_lib.scala 508:23] + inst rvclkhdr_128 of rvclkhdr_222 @[lib.scala 368:23] rvclkhdr_128.clock <= clock rvclkhdr_128.reset <= reset - rvclkhdr_128.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_128.io.en <= _T_932 @[el2_lib.scala 511:17] - rvclkhdr_128.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_118 : UInt, rvclkhdr_128.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_118 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_128.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_128.io.en <= _T_932 @[lib.scala 371:17] + rvclkhdr_128.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_118 : UInt, rvclkhdr_128.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_118 <= btb_wr_data @[lib.scala 374:16] node _T_933 = eq(btb_wr_addr, UInt<7>("h077")) @[ifu_bp_ctl.scala 415:95] node _T_934 = and(_T_933, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_935 = bits(_T_934, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_129 of rvclkhdr_223 @[el2_lib.scala 508:23] + inst rvclkhdr_129 of rvclkhdr_223 @[lib.scala 368:23] rvclkhdr_129.clock <= clock rvclkhdr_129.reset <= reset - rvclkhdr_129.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_129.io.en <= _T_935 @[el2_lib.scala 511:17] - rvclkhdr_129.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_119 : UInt, rvclkhdr_129.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_119 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_129.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_129.io.en <= _T_935 @[lib.scala 371:17] + rvclkhdr_129.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_119 : UInt, rvclkhdr_129.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_119 <= btb_wr_data @[lib.scala 374:16] node _T_936 = eq(btb_wr_addr, UInt<7>("h078")) @[ifu_bp_ctl.scala 415:95] node _T_937 = and(_T_936, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_938 = bits(_T_937, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_130 of rvclkhdr_224 @[el2_lib.scala 508:23] + inst rvclkhdr_130 of rvclkhdr_224 @[lib.scala 368:23] rvclkhdr_130.clock <= clock rvclkhdr_130.reset <= reset - rvclkhdr_130.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_130.io.en <= _T_938 @[el2_lib.scala 511:17] - rvclkhdr_130.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_120 : UInt, rvclkhdr_130.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_120 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_130.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_130.io.en <= _T_938 @[lib.scala 371:17] + rvclkhdr_130.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_120 : UInt, rvclkhdr_130.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_120 <= btb_wr_data @[lib.scala 374:16] node _T_939 = eq(btb_wr_addr, UInt<7>("h079")) @[ifu_bp_ctl.scala 415:95] node _T_940 = and(_T_939, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_941 = bits(_T_940, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_131 of rvclkhdr_225 @[el2_lib.scala 508:23] + inst rvclkhdr_131 of rvclkhdr_225 @[lib.scala 368:23] rvclkhdr_131.clock <= clock rvclkhdr_131.reset <= reset - rvclkhdr_131.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_131.io.en <= _T_941 @[el2_lib.scala 511:17] - rvclkhdr_131.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_121 : UInt, rvclkhdr_131.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_121 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_131.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_131.io.en <= _T_941 @[lib.scala 371:17] + rvclkhdr_131.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_121 : UInt, rvclkhdr_131.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_121 <= btb_wr_data @[lib.scala 374:16] node _T_942 = eq(btb_wr_addr, UInt<7>("h07a")) @[ifu_bp_ctl.scala 415:95] node _T_943 = and(_T_942, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_944 = bits(_T_943, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_132 of rvclkhdr_226 @[el2_lib.scala 508:23] + inst rvclkhdr_132 of rvclkhdr_226 @[lib.scala 368:23] rvclkhdr_132.clock <= clock rvclkhdr_132.reset <= reset - rvclkhdr_132.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_132.io.en <= _T_944 @[el2_lib.scala 511:17] - rvclkhdr_132.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_122 : UInt, rvclkhdr_132.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_122 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_132.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_132.io.en <= _T_944 @[lib.scala 371:17] + rvclkhdr_132.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_122 : UInt, rvclkhdr_132.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_122 <= btb_wr_data @[lib.scala 374:16] node _T_945 = eq(btb_wr_addr, UInt<7>("h07b")) @[ifu_bp_ctl.scala 415:95] node _T_946 = and(_T_945, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_947 = bits(_T_946, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_133 of rvclkhdr_227 @[el2_lib.scala 508:23] + inst rvclkhdr_133 of rvclkhdr_227 @[lib.scala 368:23] rvclkhdr_133.clock <= clock rvclkhdr_133.reset <= reset - rvclkhdr_133.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_133.io.en <= _T_947 @[el2_lib.scala 511:17] - rvclkhdr_133.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_123 : UInt, rvclkhdr_133.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_123 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_133.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_133.io.en <= _T_947 @[lib.scala 371:17] + rvclkhdr_133.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_123 : UInt, rvclkhdr_133.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_123 <= btb_wr_data @[lib.scala 374:16] node _T_948 = eq(btb_wr_addr, UInt<7>("h07c")) @[ifu_bp_ctl.scala 415:95] node _T_949 = and(_T_948, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_950 = bits(_T_949, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_134 of rvclkhdr_228 @[el2_lib.scala 508:23] + inst rvclkhdr_134 of rvclkhdr_228 @[lib.scala 368:23] rvclkhdr_134.clock <= clock rvclkhdr_134.reset <= reset - rvclkhdr_134.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_134.io.en <= _T_950 @[el2_lib.scala 511:17] - rvclkhdr_134.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_124 : UInt, rvclkhdr_134.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_124 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_134.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_134.io.en <= _T_950 @[lib.scala 371:17] + rvclkhdr_134.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_124 : UInt, rvclkhdr_134.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_124 <= btb_wr_data @[lib.scala 374:16] node _T_951 = eq(btb_wr_addr, UInt<7>("h07d")) @[ifu_bp_ctl.scala 415:95] node _T_952 = and(_T_951, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_953 = bits(_T_952, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_135 of rvclkhdr_229 @[el2_lib.scala 508:23] + inst rvclkhdr_135 of rvclkhdr_229 @[lib.scala 368:23] rvclkhdr_135.clock <= clock rvclkhdr_135.reset <= reset - rvclkhdr_135.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_135.io.en <= _T_953 @[el2_lib.scala 511:17] - rvclkhdr_135.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_125 : UInt, rvclkhdr_135.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_125 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_135.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_135.io.en <= _T_953 @[lib.scala 371:17] + rvclkhdr_135.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_125 : UInt, rvclkhdr_135.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_125 <= btb_wr_data @[lib.scala 374:16] node _T_954 = eq(btb_wr_addr, UInt<7>("h07e")) @[ifu_bp_ctl.scala 415:95] node _T_955 = and(_T_954, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_956 = bits(_T_955, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_136 of rvclkhdr_230 @[el2_lib.scala 508:23] + inst rvclkhdr_136 of rvclkhdr_230 @[lib.scala 368:23] rvclkhdr_136.clock <= clock rvclkhdr_136.reset <= reset - rvclkhdr_136.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_136.io.en <= _T_956 @[el2_lib.scala 511:17] - rvclkhdr_136.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_126 : UInt, rvclkhdr_136.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_126 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_136.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_136.io.en <= _T_956 @[lib.scala 371:17] + rvclkhdr_136.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_126 : UInt, rvclkhdr_136.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_126 <= btb_wr_data @[lib.scala 374:16] node _T_957 = eq(btb_wr_addr, UInt<7>("h07f")) @[ifu_bp_ctl.scala 415:95] node _T_958 = and(_T_957, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_959 = bits(_T_958, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_137 of rvclkhdr_231 @[el2_lib.scala 508:23] + inst rvclkhdr_137 of rvclkhdr_231 @[lib.scala 368:23] rvclkhdr_137.clock <= clock rvclkhdr_137.reset <= reset - rvclkhdr_137.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_137.io.en <= _T_959 @[el2_lib.scala 511:17] - rvclkhdr_137.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_127 : UInt, rvclkhdr_137.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_127 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_137.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_137.io.en <= _T_959 @[lib.scala 371:17] + rvclkhdr_137.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_127 : UInt, rvclkhdr_137.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_127 <= btb_wr_data @[lib.scala 374:16] node _T_960 = eq(btb_wr_addr, UInt<8>("h080")) @[ifu_bp_ctl.scala 415:95] node _T_961 = and(_T_960, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_962 = bits(_T_961, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_138 of rvclkhdr_232 @[el2_lib.scala 508:23] + inst rvclkhdr_138 of rvclkhdr_232 @[lib.scala 368:23] rvclkhdr_138.clock <= clock rvclkhdr_138.reset <= reset - rvclkhdr_138.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_138.io.en <= _T_962 @[el2_lib.scala 511:17] - rvclkhdr_138.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_128 : UInt, rvclkhdr_138.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_128 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_138.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_138.io.en <= _T_962 @[lib.scala 371:17] + rvclkhdr_138.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_128 : UInt, rvclkhdr_138.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_128 <= btb_wr_data @[lib.scala 374:16] node _T_963 = eq(btb_wr_addr, UInt<8>("h081")) @[ifu_bp_ctl.scala 415:95] node _T_964 = and(_T_963, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_965 = bits(_T_964, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_139 of rvclkhdr_233 @[el2_lib.scala 508:23] + inst rvclkhdr_139 of rvclkhdr_233 @[lib.scala 368:23] rvclkhdr_139.clock <= clock rvclkhdr_139.reset <= reset - rvclkhdr_139.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_139.io.en <= _T_965 @[el2_lib.scala 511:17] - rvclkhdr_139.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_129 : UInt, rvclkhdr_139.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_129 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_139.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_139.io.en <= _T_965 @[lib.scala 371:17] + rvclkhdr_139.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_129 : UInt, rvclkhdr_139.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_129 <= btb_wr_data @[lib.scala 374:16] node _T_966 = eq(btb_wr_addr, UInt<8>("h082")) @[ifu_bp_ctl.scala 415:95] node _T_967 = and(_T_966, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_968 = bits(_T_967, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_140 of rvclkhdr_234 @[el2_lib.scala 508:23] + inst rvclkhdr_140 of rvclkhdr_234 @[lib.scala 368:23] rvclkhdr_140.clock <= clock rvclkhdr_140.reset <= reset - rvclkhdr_140.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_140.io.en <= _T_968 @[el2_lib.scala 511:17] - rvclkhdr_140.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_130 : UInt, rvclkhdr_140.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_130 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_140.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_140.io.en <= _T_968 @[lib.scala 371:17] + rvclkhdr_140.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_130 : UInt, rvclkhdr_140.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_130 <= btb_wr_data @[lib.scala 374:16] node _T_969 = eq(btb_wr_addr, UInt<8>("h083")) @[ifu_bp_ctl.scala 415:95] node _T_970 = and(_T_969, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_971 = bits(_T_970, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_141 of rvclkhdr_235 @[el2_lib.scala 508:23] + inst rvclkhdr_141 of rvclkhdr_235 @[lib.scala 368:23] rvclkhdr_141.clock <= clock rvclkhdr_141.reset <= reset - rvclkhdr_141.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_141.io.en <= _T_971 @[el2_lib.scala 511:17] - rvclkhdr_141.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_131 : UInt, rvclkhdr_141.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_131 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_141.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_141.io.en <= _T_971 @[lib.scala 371:17] + rvclkhdr_141.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_131 : UInt, rvclkhdr_141.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_131 <= btb_wr_data @[lib.scala 374:16] node _T_972 = eq(btb_wr_addr, UInt<8>("h084")) @[ifu_bp_ctl.scala 415:95] node _T_973 = and(_T_972, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_974 = bits(_T_973, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_142 of rvclkhdr_236 @[el2_lib.scala 508:23] + inst rvclkhdr_142 of rvclkhdr_236 @[lib.scala 368:23] rvclkhdr_142.clock <= clock rvclkhdr_142.reset <= reset - rvclkhdr_142.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_142.io.en <= _T_974 @[el2_lib.scala 511:17] - rvclkhdr_142.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_132 : UInt, rvclkhdr_142.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_132 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_142.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_142.io.en <= _T_974 @[lib.scala 371:17] + rvclkhdr_142.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_132 : UInt, rvclkhdr_142.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_132 <= btb_wr_data @[lib.scala 374:16] node _T_975 = eq(btb_wr_addr, UInt<8>("h085")) @[ifu_bp_ctl.scala 415:95] node _T_976 = and(_T_975, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_977 = bits(_T_976, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_143 of rvclkhdr_237 @[el2_lib.scala 508:23] + inst rvclkhdr_143 of rvclkhdr_237 @[lib.scala 368:23] rvclkhdr_143.clock <= clock rvclkhdr_143.reset <= reset - rvclkhdr_143.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_143.io.en <= _T_977 @[el2_lib.scala 511:17] - rvclkhdr_143.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_133 : UInt, rvclkhdr_143.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_133 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_143.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_143.io.en <= _T_977 @[lib.scala 371:17] + rvclkhdr_143.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_133 : UInt, rvclkhdr_143.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_133 <= btb_wr_data @[lib.scala 374:16] node _T_978 = eq(btb_wr_addr, UInt<8>("h086")) @[ifu_bp_ctl.scala 415:95] node _T_979 = and(_T_978, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_980 = bits(_T_979, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_144 of rvclkhdr_238 @[el2_lib.scala 508:23] + inst rvclkhdr_144 of rvclkhdr_238 @[lib.scala 368:23] rvclkhdr_144.clock <= clock rvclkhdr_144.reset <= reset - rvclkhdr_144.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_144.io.en <= _T_980 @[el2_lib.scala 511:17] - rvclkhdr_144.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_134 : UInt, rvclkhdr_144.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_134 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_144.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_144.io.en <= _T_980 @[lib.scala 371:17] + rvclkhdr_144.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_134 : UInt, rvclkhdr_144.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_134 <= btb_wr_data @[lib.scala 374:16] node _T_981 = eq(btb_wr_addr, UInt<8>("h087")) @[ifu_bp_ctl.scala 415:95] node _T_982 = and(_T_981, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_983 = bits(_T_982, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_145 of rvclkhdr_239 @[el2_lib.scala 508:23] + inst rvclkhdr_145 of rvclkhdr_239 @[lib.scala 368:23] rvclkhdr_145.clock <= clock rvclkhdr_145.reset <= reset - rvclkhdr_145.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_145.io.en <= _T_983 @[el2_lib.scala 511:17] - rvclkhdr_145.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_135 : UInt, rvclkhdr_145.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_135 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_145.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_145.io.en <= _T_983 @[lib.scala 371:17] + rvclkhdr_145.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_135 : UInt, rvclkhdr_145.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_135 <= btb_wr_data @[lib.scala 374:16] node _T_984 = eq(btb_wr_addr, UInt<8>("h088")) @[ifu_bp_ctl.scala 415:95] node _T_985 = and(_T_984, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_986 = bits(_T_985, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_146 of rvclkhdr_240 @[el2_lib.scala 508:23] + inst rvclkhdr_146 of rvclkhdr_240 @[lib.scala 368:23] rvclkhdr_146.clock <= clock rvclkhdr_146.reset <= reset - rvclkhdr_146.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_146.io.en <= _T_986 @[el2_lib.scala 511:17] - rvclkhdr_146.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_136 : UInt, rvclkhdr_146.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_136 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_146.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_146.io.en <= _T_986 @[lib.scala 371:17] + rvclkhdr_146.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_136 : UInt, rvclkhdr_146.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_136 <= btb_wr_data @[lib.scala 374:16] node _T_987 = eq(btb_wr_addr, UInt<8>("h089")) @[ifu_bp_ctl.scala 415:95] node _T_988 = and(_T_987, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_989 = bits(_T_988, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_147 of rvclkhdr_241 @[el2_lib.scala 508:23] + inst rvclkhdr_147 of rvclkhdr_241 @[lib.scala 368:23] rvclkhdr_147.clock <= clock rvclkhdr_147.reset <= reset - rvclkhdr_147.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_147.io.en <= _T_989 @[el2_lib.scala 511:17] - rvclkhdr_147.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_137 : UInt, rvclkhdr_147.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_137 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_147.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_147.io.en <= _T_989 @[lib.scala 371:17] + rvclkhdr_147.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_137 : UInt, rvclkhdr_147.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_137 <= btb_wr_data @[lib.scala 374:16] node _T_990 = eq(btb_wr_addr, UInt<8>("h08a")) @[ifu_bp_ctl.scala 415:95] node _T_991 = and(_T_990, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_992 = bits(_T_991, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_148 of rvclkhdr_242 @[el2_lib.scala 508:23] + inst rvclkhdr_148 of rvclkhdr_242 @[lib.scala 368:23] rvclkhdr_148.clock <= clock rvclkhdr_148.reset <= reset - rvclkhdr_148.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_148.io.en <= _T_992 @[el2_lib.scala 511:17] - rvclkhdr_148.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_138 : UInt, rvclkhdr_148.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_138 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_148.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_148.io.en <= _T_992 @[lib.scala 371:17] + rvclkhdr_148.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_138 : UInt, rvclkhdr_148.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_138 <= btb_wr_data @[lib.scala 374:16] node _T_993 = eq(btb_wr_addr, UInt<8>("h08b")) @[ifu_bp_ctl.scala 415:95] node _T_994 = and(_T_993, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_995 = bits(_T_994, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_149 of rvclkhdr_243 @[el2_lib.scala 508:23] + inst rvclkhdr_149 of rvclkhdr_243 @[lib.scala 368:23] rvclkhdr_149.clock <= clock rvclkhdr_149.reset <= reset - rvclkhdr_149.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_149.io.en <= _T_995 @[el2_lib.scala 511:17] - rvclkhdr_149.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_139 : UInt, rvclkhdr_149.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_139 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_149.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_149.io.en <= _T_995 @[lib.scala 371:17] + rvclkhdr_149.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_139 : UInt, rvclkhdr_149.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_139 <= btb_wr_data @[lib.scala 374:16] node _T_996 = eq(btb_wr_addr, UInt<8>("h08c")) @[ifu_bp_ctl.scala 415:95] node _T_997 = and(_T_996, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_998 = bits(_T_997, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_150 of rvclkhdr_244 @[el2_lib.scala 508:23] + inst rvclkhdr_150 of rvclkhdr_244 @[lib.scala 368:23] rvclkhdr_150.clock <= clock rvclkhdr_150.reset <= reset - rvclkhdr_150.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_150.io.en <= _T_998 @[el2_lib.scala 511:17] - rvclkhdr_150.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_140 : UInt, rvclkhdr_150.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_140 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_150.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_150.io.en <= _T_998 @[lib.scala 371:17] + rvclkhdr_150.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_140 : UInt, rvclkhdr_150.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_140 <= btb_wr_data @[lib.scala 374:16] node _T_999 = eq(btb_wr_addr, UInt<8>("h08d")) @[ifu_bp_ctl.scala 415:95] node _T_1000 = and(_T_999, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1001 = bits(_T_1000, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_151 of rvclkhdr_245 @[el2_lib.scala 508:23] + inst rvclkhdr_151 of rvclkhdr_245 @[lib.scala 368:23] rvclkhdr_151.clock <= clock rvclkhdr_151.reset <= reset - rvclkhdr_151.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_151.io.en <= _T_1001 @[el2_lib.scala 511:17] - rvclkhdr_151.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_141 : UInt, rvclkhdr_151.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_141 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_151.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_151.io.en <= _T_1001 @[lib.scala 371:17] + rvclkhdr_151.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_141 : UInt, rvclkhdr_151.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_141 <= btb_wr_data @[lib.scala 374:16] node _T_1002 = eq(btb_wr_addr, UInt<8>("h08e")) @[ifu_bp_ctl.scala 415:95] node _T_1003 = and(_T_1002, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1004 = bits(_T_1003, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_152 of rvclkhdr_246 @[el2_lib.scala 508:23] + inst rvclkhdr_152 of rvclkhdr_246 @[lib.scala 368:23] rvclkhdr_152.clock <= clock rvclkhdr_152.reset <= reset - rvclkhdr_152.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_152.io.en <= _T_1004 @[el2_lib.scala 511:17] - rvclkhdr_152.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_142 : UInt, rvclkhdr_152.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_142 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_152.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_152.io.en <= _T_1004 @[lib.scala 371:17] + rvclkhdr_152.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_142 : UInt, rvclkhdr_152.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_142 <= btb_wr_data @[lib.scala 374:16] node _T_1005 = eq(btb_wr_addr, UInt<8>("h08f")) @[ifu_bp_ctl.scala 415:95] node _T_1006 = and(_T_1005, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1007 = bits(_T_1006, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_153 of rvclkhdr_247 @[el2_lib.scala 508:23] + inst rvclkhdr_153 of rvclkhdr_247 @[lib.scala 368:23] rvclkhdr_153.clock <= clock rvclkhdr_153.reset <= reset - rvclkhdr_153.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_153.io.en <= _T_1007 @[el2_lib.scala 511:17] - rvclkhdr_153.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_143 : UInt, rvclkhdr_153.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_143 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_153.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_153.io.en <= _T_1007 @[lib.scala 371:17] + rvclkhdr_153.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_143 : UInt, rvclkhdr_153.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_143 <= btb_wr_data @[lib.scala 374:16] node _T_1008 = eq(btb_wr_addr, UInt<8>("h090")) @[ifu_bp_ctl.scala 415:95] node _T_1009 = and(_T_1008, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1010 = bits(_T_1009, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_154 of rvclkhdr_248 @[el2_lib.scala 508:23] + inst rvclkhdr_154 of rvclkhdr_248 @[lib.scala 368:23] rvclkhdr_154.clock <= clock rvclkhdr_154.reset <= reset - rvclkhdr_154.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_154.io.en <= _T_1010 @[el2_lib.scala 511:17] - rvclkhdr_154.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_144 : UInt, rvclkhdr_154.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_144 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_154.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_154.io.en <= _T_1010 @[lib.scala 371:17] + rvclkhdr_154.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_144 : UInt, rvclkhdr_154.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_144 <= btb_wr_data @[lib.scala 374:16] node _T_1011 = eq(btb_wr_addr, UInt<8>("h091")) @[ifu_bp_ctl.scala 415:95] node _T_1012 = and(_T_1011, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1013 = bits(_T_1012, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_155 of rvclkhdr_249 @[el2_lib.scala 508:23] + inst rvclkhdr_155 of rvclkhdr_249 @[lib.scala 368:23] rvclkhdr_155.clock <= clock rvclkhdr_155.reset <= reset - rvclkhdr_155.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_155.io.en <= _T_1013 @[el2_lib.scala 511:17] - rvclkhdr_155.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_145 : UInt, rvclkhdr_155.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_145 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_155.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_155.io.en <= _T_1013 @[lib.scala 371:17] + rvclkhdr_155.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_145 : UInt, rvclkhdr_155.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_145 <= btb_wr_data @[lib.scala 374:16] node _T_1014 = eq(btb_wr_addr, UInt<8>("h092")) @[ifu_bp_ctl.scala 415:95] node _T_1015 = and(_T_1014, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1016 = bits(_T_1015, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_156 of rvclkhdr_250 @[el2_lib.scala 508:23] + inst rvclkhdr_156 of rvclkhdr_250 @[lib.scala 368:23] rvclkhdr_156.clock <= clock rvclkhdr_156.reset <= reset - rvclkhdr_156.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_156.io.en <= _T_1016 @[el2_lib.scala 511:17] - rvclkhdr_156.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_146 : UInt, rvclkhdr_156.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_146 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_156.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_156.io.en <= _T_1016 @[lib.scala 371:17] + rvclkhdr_156.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_146 : UInt, rvclkhdr_156.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_146 <= btb_wr_data @[lib.scala 374:16] node _T_1017 = eq(btb_wr_addr, UInt<8>("h093")) @[ifu_bp_ctl.scala 415:95] node _T_1018 = and(_T_1017, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1019 = bits(_T_1018, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_157 of rvclkhdr_251 @[el2_lib.scala 508:23] + inst rvclkhdr_157 of rvclkhdr_251 @[lib.scala 368:23] rvclkhdr_157.clock <= clock rvclkhdr_157.reset <= reset - rvclkhdr_157.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_157.io.en <= _T_1019 @[el2_lib.scala 511:17] - rvclkhdr_157.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_147 : UInt, rvclkhdr_157.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_147 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_157.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_157.io.en <= _T_1019 @[lib.scala 371:17] + rvclkhdr_157.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_147 : UInt, rvclkhdr_157.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_147 <= btb_wr_data @[lib.scala 374:16] node _T_1020 = eq(btb_wr_addr, UInt<8>("h094")) @[ifu_bp_ctl.scala 415:95] node _T_1021 = and(_T_1020, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1022 = bits(_T_1021, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_158 of rvclkhdr_252 @[el2_lib.scala 508:23] + inst rvclkhdr_158 of rvclkhdr_252 @[lib.scala 368:23] rvclkhdr_158.clock <= clock rvclkhdr_158.reset <= reset - rvclkhdr_158.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_158.io.en <= _T_1022 @[el2_lib.scala 511:17] - rvclkhdr_158.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_148 : UInt, rvclkhdr_158.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_148 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_158.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_158.io.en <= _T_1022 @[lib.scala 371:17] + rvclkhdr_158.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_148 : UInt, rvclkhdr_158.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_148 <= btb_wr_data @[lib.scala 374:16] node _T_1023 = eq(btb_wr_addr, UInt<8>("h095")) @[ifu_bp_ctl.scala 415:95] node _T_1024 = and(_T_1023, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1025 = bits(_T_1024, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_159 of rvclkhdr_253 @[el2_lib.scala 508:23] + inst rvclkhdr_159 of rvclkhdr_253 @[lib.scala 368:23] rvclkhdr_159.clock <= clock rvclkhdr_159.reset <= reset - rvclkhdr_159.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_159.io.en <= _T_1025 @[el2_lib.scala 511:17] - rvclkhdr_159.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_149 : UInt, rvclkhdr_159.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_149 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_159.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_159.io.en <= _T_1025 @[lib.scala 371:17] + rvclkhdr_159.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_149 : UInt, rvclkhdr_159.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_149 <= btb_wr_data @[lib.scala 374:16] node _T_1026 = eq(btb_wr_addr, UInt<8>("h096")) @[ifu_bp_ctl.scala 415:95] node _T_1027 = and(_T_1026, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1028 = bits(_T_1027, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_160 of rvclkhdr_254 @[el2_lib.scala 508:23] + inst rvclkhdr_160 of rvclkhdr_254 @[lib.scala 368:23] rvclkhdr_160.clock <= clock rvclkhdr_160.reset <= reset - rvclkhdr_160.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_160.io.en <= _T_1028 @[el2_lib.scala 511:17] - rvclkhdr_160.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_150 : UInt, rvclkhdr_160.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_150 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_160.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_160.io.en <= _T_1028 @[lib.scala 371:17] + rvclkhdr_160.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_150 : UInt, rvclkhdr_160.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_150 <= btb_wr_data @[lib.scala 374:16] node _T_1029 = eq(btb_wr_addr, UInt<8>("h097")) @[ifu_bp_ctl.scala 415:95] node _T_1030 = and(_T_1029, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1031 = bits(_T_1030, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_161 of rvclkhdr_255 @[el2_lib.scala 508:23] + inst rvclkhdr_161 of rvclkhdr_255 @[lib.scala 368:23] rvclkhdr_161.clock <= clock rvclkhdr_161.reset <= reset - rvclkhdr_161.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_161.io.en <= _T_1031 @[el2_lib.scala 511:17] - rvclkhdr_161.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_151 : UInt, rvclkhdr_161.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_151 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_161.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_161.io.en <= _T_1031 @[lib.scala 371:17] + rvclkhdr_161.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_151 : UInt, rvclkhdr_161.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_151 <= btb_wr_data @[lib.scala 374:16] node _T_1032 = eq(btb_wr_addr, UInt<8>("h098")) @[ifu_bp_ctl.scala 415:95] node _T_1033 = and(_T_1032, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1034 = bits(_T_1033, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_162 of rvclkhdr_256 @[el2_lib.scala 508:23] + inst rvclkhdr_162 of rvclkhdr_256 @[lib.scala 368:23] rvclkhdr_162.clock <= clock rvclkhdr_162.reset <= reset - rvclkhdr_162.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_162.io.en <= _T_1034 @[el2_lib.scala 511:17] - rvclkhdr_162.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_152 : UInt, rvclkhdr_162.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_152 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_162.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_162.io.en <= _T_1034 @[lib.scala 371:17] + rvclkhdr_162.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_152 : UInt, rvclkhdr_162.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_152 <= btb_wr_data @[lib.scala 374:16] node _T_1035 = eq(btb_wr_addr, UInt<8>("h099")) @[ifu_bp_ctl.scala 415:95] node _T_1036 = and(_T_1035, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1037 = bits(_T_1036, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_163 of rvclkhdr_257 @[el2_lib.scala 508:23] + inst rvclkhdr_163 of rvclkhdr_257 @[lib.scala 368:23] rvclkhdr_163.clock <= clock rvclkhdr_163.reset <= reset - rvclkhdr_163.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_163.io.en <= _T_1037 @[el2_lib.scala 511:17] - rvclkhdr_163.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_153 : UInt, rvclkhdr_163.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_153 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_163.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_163.io.en <= _T_1037 @[lib.scala 371:17] + rvclkhdr_163.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_153 : UInt, rvclkhdr_163.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_153 <= btb_wr_data @[lib.scala 374:16] node _T_1038 = eq(btb_wr_addr, UInt<8>("h09a")) @[ifu_bp_ctl.scala 415:95] node _T_1039 = and(_T_1038, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1040 = bits(_T_1039, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_164 of rvclkhdr_258 @[el2_lib.scala 508:23] + inst rvclkhdr_164 of rvclkhdr_258 @[lib.scala 368:23] rvclkhdr_164.clock <= clock rvclkhdr_164.reset <= reset - rvclkhdr_164.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_164.io.en <= _T_1040 @[el2_lib.scala 511:17] - rvclkhdr_164.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_154 : UInt, rvclkhdr_164.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_154 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_164.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_164.io.en <= _T_1040 @[lib.scala 371:17] + rvclkhdr_164.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_154 : UInt, rvclkhdr_164.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_154 <= btb_wr_data @[lib.scala 374:16] node _T_1041 = eq(btb_wr_addr, UInt<8>("h09b")) @[ifu_bp_ctl.scala 415:95] node _T_1042 = and(_T_1041, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1043 = bits(_T_1042, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_165 of rvclkhdr_259 @[el2_lib.scala 508:23] + inst rvclkhdr_165 of rvclkhdr_259 @[lib.scala 368:23] rvclkhdr_165.clock <= clock rvclkhdr_165.reset <= reset - rvclkhdr_165.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_165.io.en <= _T_1043 @[el2_lib.scala 511:17] - rvclkhdr_165.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_155 : UInt, rvclkhdr_165.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_155 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_165.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_165.io.en <= _T_1043 @[lib.scala 371:17] + rvclkhdr_165.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_155 : UInt, rvclkhdr_165.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_155 <= btb_wr_data @[lib.scala 374:16] node _T_1044 = eq(btb_wr_addr, UInt<8>("h09c")) @[ifu_bp_ctl.scala 415:95] node _T_1045 = and(_T_1044, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1046 = bits(_T_1045, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_166 of rvclkhdr_260 @[el2_lib.scala 508:23] + inst rvclkhdr_166 of rvclkhdr_260 @[lib.scala 368:23] rvclkhdr_166.clock <= clock rvclkhdr_166.reset <= reset - rvclkhdr_166.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_166.io.en <= _T_1046 @[el2_lib.scala 511:17] - rvclkhdr_166.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_156 : UInt, rvclkhdr_166.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_156 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_166.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_166.io.en <= _T_1046 @[lib.scala 371:17] + rvclkhdr_166.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_156 : UInt, rvclkhdr_166.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_156 <= btb_wr_data @[lib.scala 374:16] node _T_1047 = eq(btb_wr_addr, UInt<8>("h09d")) @[ifu_bp_ctl.scala 415:95] node _T_1048 = and(_T_1047, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1049 = bits(_T_1048, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_167 of rvclkhdr_261 @[el2_lib.scala 508:23] + inst rvclkhdr_167 of rvclkhdr_261 @[lib.scala 368:23] rvclkhdr_167.clock <= clock rvclkhdr_167.reset <= reset - rvclkhdr_167.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_167.io.en <= _T_1049 @[el2_lib.scala 511:17] - rvclkhdr_167.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_157 : UInt, rvclkhdr_167.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_157 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_167.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_167.io.en <= _T_1049 @[lib.scala 371:17] + rvclkhdr_167.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_157 : UInt, rvclkhdr_167.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_157 <= btb_wr_data @[lib.scala 374:16] node _T_1050 = eq(btb_wr_addr, UInt<8>("h09e")) @[ifu_bp_ctl.scala 415:95] node _T_1051 = and(_T_1050, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1052 = bits(_T_1051, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_168 of rvclkhdr_262 @[el2_lib.scala 508:23] + inst rvclkhdr_168 of rvclkhdr_262 @[lib.scala 368:23] rvclkhdr_168.clock <= clock rvclkhdr_168.reset <= reset - rvclkhdr_168.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_168.io.en <= _T_1052 @[el2_lib.scala 511:17] - rvclkhdr_168.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_158 : UInt, rvclkhdr_168.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_158 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_168.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_168.io.en <= _T_1052 @[lib.scala 371:17] + rvclkhdr_168.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_158 : UInt, rvclkhdr_168.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_158 <= btb_wr_data @[lib.scala 374:16] node _T_1053 = eq(btb_wr_addr, UInt<8>("h09f")) @[ifu_bp_ctl.scala 415:95] node _T_1054 = and(_T_1053, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1055 = bits(_T_1054, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_169 of rvclkhdr_263 @[el2_lib.scala 508:23] + inst rvclkhdr_169 of rvclkhdr_263 @[lib.scala 368:23] rvclkhdr_169.clock <= clock rvclkhdr_169.reset <= reset - rvclkhdr_169.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_169.io.en <= _T_1055 @[el2_lib.scala 511:17] - rvclkhdr_169.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_159 : UInt, rvclkhdr_169.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_159 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_169.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_169.io.en <= _T_1055 @[lib.scala 371:17] + rvclkhdr_169.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_159 : UInt, rvclkhdr_169.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_159 <= btb_wr_data @[lib.scala 374:16] node _T_1056 = eq(btb_wr_addr, UInt<8>("h0a0")) @[ifu_bp_ctl.scala 415:95] node _T_1057 = and(_T_1056, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1058 = bits(_T_1057, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_170 of rvclkhdr_264 @[el2_lib.scala 508:23] + inst rvclkhdr_170 of rvclkhdr_264 @[lib.scala 368:23] rvclkhdr_170.clock <= clock rvclkhdr_170.reset <= reset - rvclkhdr_170.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_170.io.en <= _T_1058 @[el2_lib.scala 511:17] - rvclkhdr_170.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_160 : UInt, rvclkhdr_170.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_160 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_170.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_170.io.en <= _T_1058 @[lib.scala 371:17] + rvclkhdr_170.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_160 : UInt, rvclkhdr_170.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_160 <= btb_wr_data @[lib.scala 374:16] node _T_1059 = eq(btb_wr_addr, UInt<8>("h0a1")) @[ifu_bp_ctl.scala 415:95] node _T_1060 = and(_T_1059, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1061 = bits(_T_1060, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_171 of rvclkhdr_265 @[el2_lib.scala 508:23] + inst rvclkhdr_171 of rvclkhdr_265 @[lib.scala 368:23] rvclkhdr_171.clock <= clock rvclkhdr_171.reset <= reset - rvclkhdr_171.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_171.io.en <= _T_1061 @[el2_lib.scala 511:17] - rvclkhdr_171.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_161 : UInt, rvclkhdr_171.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_161 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_171.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_171.io.en <= _T_1061 @[lib.scala 371:17] + rvclkhdr_171.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_161 : UInt, rvclkhdr_171.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_161 <= btb_wr_data @[lib.scala 374:16] node _T_1062 = eq(btb_wr_addr, UInt<8>("h0a2")) @[ifu_bp_ctl.scala 415:95] node _T_1063 = and(_T_1062, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1064 = bits(_T_1063, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_172 of rvclkhdr_266 @[el2_lib.scala 508:23] + inst rvclkhdr_172 of rvclkhdr_266 @[lib.scala 368:23] rvclkhdr_172.clock <= clock rvclkhdr_172.reset <= reset - rvclkhdr_172.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_172.io.en <= _T_1064 @[el2_lib.scala 511:17] - rvclkhdr_172.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_162 : UInt, rvclkhdr_172.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_162 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_172.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_172.io.en <= _T_1064 @[lib.scala 371:17] + rvclkhdr_172.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_162 : UInt, rvclkhdr_172.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_162 <= btb_wr_data @[lib.scala 374:16] node _T_1065 = eq(btb_wr_addr, UInt<8>("h0a3")) @[ifu_bp_ctl.scala 415:95] node _T_1066 = and(_T_1065, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1067 = bits(_T_1066, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_173 of rvclkhdr_267 @[el2_lib.scala 508:23] + inst rvclkhdr_173 of rvclkhdr_267 @[lib.scala 368:23] rvclkhdr_173.clock <= clock rvclkhdr_173.reset <= reset - rvclkhdr_173.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_173.io.en <= _T_1067 @[el2_lib.scala 511:17] - rvclkhdr_173.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_163 : UInt, rvclkhdr_173.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_163 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_173.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_173.io.en <= _T_1067 @[lib.scala 371:17] + rvclkhdr_173.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_163 : UInt, rvclkhdr_173.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_163 <= btb_wr_data @[lib.scala 374:16] node _T_1068 = eq(btb_wr_addr, UInt<8>("h0a4")) @[ifu_bp_ctl.scala 415:95] node _T_1069 = and(_T_1068, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1070 = bits(_T_1069, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_174 of rvclkhdr_268 @[el2_lib.scala 508:23] + inst rvclkhdr_174 of rvclkhdr_268 @[lib.scala 368:23] rvclkhdr_174.clock <= clock rvclkhdr_174.reset <= reset - rvclkhdr_174.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_174.io.en <= _T_1070 @[el2_lib.scala 511:17] - rvclkhdr_174.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_164 : UInt, rvclkhdr_174.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_164 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_174.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_174.io.en <= _T_1070 @[lib.scala 371:17] + rvclkhdr_174.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_164 : UInt, rvclkhdr_174.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_164 <= btb_wr_data @[lib.scala 374:16] node _T_1071 = eq(btb_wr_addr, UInt<8>("h0a5")) @[ifu_bp_ctl.scala 415:95] node _T_1072 = and(_T_1071, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1073 = bits(_T_1072, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_175 of rvclkhdr_269 @[el2_lib.scala 508:23] + inst rvclkhdr_175 of rvclkhdr_269 @[lib.scala 368:23] rvclkhdr_175.clock <= clock rvclkhdr_175.reset <= reset - rvclkhdr_175.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_175.io.en <= _T_1073 @[el2_lib.scala 511:17] - rvclkhdr_175.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_165 : UInt, rvclkhdr_175.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_165 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_175.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_175.io.en <= _T_1073 @[lib.scala 371:17] + rvclkhdr_175.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_165 : UInt, rvclkhdr_175.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_165 <= btb_wr_data @[lib.scala 374:16] node _T_1074 = eq(btb_wr_addr, UInt<8>("h0a6")) @[ifu_bp_ctl.scala 415:95] node _T_1075 = and(_T_1074, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1076 = bits(_T_1075, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_176 of rvclkhdr_270 @[el2_lib.scala 508:23] + inst rvclkhdr_176 of rvclkhdr_270 @[lib.scala 368:23] rvclkhdr_176.clock <= clock rvclkhdr_176.reset <= reset - rvclkhdr_176.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_176.io.en <= _T_1076 @[el2_lib.scala 511:17] - rvclkhdr_176.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_166 : UInt, rvclkhdr_176.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_166 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_176.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_176.io.en <= _T_1076 @[lib.scala 371:17] + rvclkhdr_176.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_166 : UInt, rvclkhdr_176.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_166 <= btb_wr_data @[lib.scala 374:16] node _T_1077 = eq(btb_wr_addr, UInt<8>("h0a7")) @[ifu_bp_ctl.scala 415:95] node _T_1078 = and(_T_1077, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1079 = bits(_T_1078, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_177 of rvclkhdr_271 @[el2_lib.scala 508:23] + inst rvclkhdr_177 of rvclkhdr_271 @[lib.scala 368:23] rvclkhdr_177.clock <= clock rvclkhdr_177.reset <= reset - rvclkhdr_177.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_177.io.en <= _T_1079 @[el2_lib.scala 511:17] - rvclkhdr_177.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_167 : UInt, rvclkhdr_177.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_167 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_177.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_177.io.en <= _T_1079 @[lib.scala 371:17] + rvclkhdr_177.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_167 : UInt, rvclkhdr_177.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_167 <= btb_wr_data @[lib.scala 374:16] node _T_1080 = eq(btb_wr_addr, UInt<8>("h0a8")) @[ifu_bp_ctl.scala 415:95] node _T_1081 = and(_T_1080, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1082 = bits(_T_1081, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_178 of rvclkhdr_272 @[el2_lib.scala 508:23] + inst rvclkhdr_178 of rvclkhdr_272 @[lib.scala 368:23] rvclkhdr_178.clock <= clock rvclkhdr_178.reset <= reset - rvclkhdr_178.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_178.io.en <= _T_1082 @[el2_lib.scala 511:17] - rvclkhdr_178.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_168 : UInt, rvclkhdr_178.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_168 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_178.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_178.io.en <= _T_1082 @[lib.scala 371:17] + rvclkhdr_178.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_168 : UInt, rvclkhdr_178.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_168 <= btb_wr_data @[lib.scala 374:16] node _T_1083 = eq(btb_wr_addr, UInt<8>("h0a9")) @[ifu_bp_ctl.scala 415:95] node _T_1084 = and(_T_1083, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1085 = bits(_T_1084, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_179 of rvclkhdr_273 @[el2_lib.scala 508:23] + inst rvclkhdr_179 of rvclkhdr_273 @[lib.scala 368:23] rvclkhdr_179.clock <= clock rvclkhdr_179.reset <= reset - rvclkhdr_179.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_179.io.en <= _T_1085 @[el2_lib.scala 511:17] - rvclkhdr_179.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_169 : UInt, rvclkhdr_179.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_169 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_179.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_179.io.en <= _T_1085 @[lib.scala 371:17] + rvclkhdr_179.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_169 : UInt, rvclkhdr_179.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_169 <= btb_wr_data @[lib.scala 374:16] node _T_1086 = eq(btb_wr_addr, UInt<8>("h0aa")) @[ifu_bp_ctl.scala 415:95] node _T_1087 = and(_T_1086, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1088 = bits(_T_1087, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_180 of rvclkhdr_274 @[el2_lib.scala 508:23] + inst rvclkhdr_180 of rvclkhdr_274 @[lib.scala 368:23] rvclkhdr_180.clock <= clock rvclkhdr_180.reset <= reset - rvclkhdr_180.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_180.io.en <= _T_1088 @[el2_lib.scala 511:17] - rvclkhdr_180.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_170 : UInt, rvclkhdr_180.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_170 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_180.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_180.io.en <= _T_1088 @[lib.scala 371:17] + rvclkhdr_180.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_170 : UInt, rvclkhdr_180.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_170 <= btb_wr_data @[lib.scala 374:16] node _T_1089 = eq(btb_wr_addr, UInt<8>("h0ab")) @[ifu_bp_ctl.scala 415:95] node _T_1090 = and(_T_1089, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1091 = bits(_T_1090, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_181 of rvclkhdr_275 @[el2_lib.scala 508:23] + inst rvclkhdr_181 of rvclkhdr_275 @[lib.scala 368:23] rvclkhdr_181.clock <= clock rvclkhdr_181.reset <= reset - rvclkhdr_181.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_181.io.en <= _T_1091 @[el2_lib.scala 511:17] - rvclkhdr_181.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_171 : UInt, rvclkhdr_181.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_171 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_181.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_181.io.en <= _T_1091 @[lib.scala 371:17] + rvclkhdr_181.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_171 : UInt, rvclkhdr_181.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_171 <= btb_wr_data @[lib.scala 374:16] node _T_1092 = eq(btb_wr_addr, UInt<8>("h0ac")) @[ifu_bp_ctl.scala 415:95] node _T_1093 = and(_T_1092, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1094 = bits(_T_1093, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_182 of rvclkhdr_276 @[el2_lib.scala 508:23] + inst rvclkhdr_182 of rvclkhdr_276 @[lib.scala 368:23] rvclkhdr_182.clock <= clock rvclkhdr_182.reset <= reset - rvclkhdr_182.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_182.io.en <= _T_1094 @[el2_lib.scala 511:17] - rvclkhdr_182.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_172 : UInt, rvclkhdr_182.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_172 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_182.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_182.io.en <= _T_1094 @[lib.scala 371:17] + rvclkhdr_182.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_172 : UInt, rvclkhdr_182.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_172 <= btb_wr_data @[lib.scala 374:16] node _T_1095 = eq(btb_wr_addr, UInt<8>("h0ad")) @[ifu_bp_ctl.scala 415:95] node _T_1096 = and(_T_1095, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1097 = bits(_T_1096, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_183 of rvclkhdr_277 @[el2_lib.scala 508:23] + inst rvclkhdr_183 of rvclkhdr_277 @[lib.scala 368:23] rvclkhdr_183.clock <= clock rvclkhdr_183.reset <= reset - rvclkhdr_183.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_183.io.en <= _T_1097 @[el2_lib.scala 511:17] - rvclkhdr_183.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_173 : UInt, rvclkhdr_183.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_173 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_183.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_183.io.en <= _T_1097 @[lib.scala 371:17] + rvclkhdr_183.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_173 : UInt, rvclkhdr_183.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_173 <= btb_wr_data @[lib.scala 374:16] node _T_1098 = eq(btb_wr_addr, UInt<8>("h0ae")) @[ifu_bp_ctl.scala 415:95] node _T_1099 = and(_T_1098, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1100 = bits(_T_1099, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_184 of rvclkhdr_278 @[el2_lib.scala 508:23] + inst rvclkhdr_184 of rvclkhdr_278 @[lib.scala 368:23] rvclkhdr_184.clock <= clock rvclkhdr_184.reset <= reset - rvclkhdr_184.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_184.io.en <= _T_1100 @[el2_lib.scala 511:17] - rvclkhdr_184.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_174 : UInt, rvclkhdr_184.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_174 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_184.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_184.io.en <= _T_1100 @[lib.scala 371:17] + rvclkhdr_184.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_174 : UInt, rvclkhdr_184.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_174 <= btb_wr_data @[lib.scala 374:16] node _T_1101 = eq(btb_wr_addr, UInt<8>("h0af")) @[ifu_bp_ctl.scala 415:95] node _T_1102 = and(_T_1101, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1103 = bits(_T_1102, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_185 of rvclkhdr_279 @[el2_lib.scala 508:23] + inst rvclkhdr_185 of rvclkhdr_279 @[lib.scala 368:23] rvclkhdr_185.clock <= clock rvclkhdr_185.reset <= reset - rvclkhdr_185.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_185.io.en <= _T_1103 @[el2_lib.scala 511:17] - rvclkhdr_185.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_175 : UInt, rvclkhdr_185.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_175 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_185.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_185.io.en <= _T_1103 @[lib.scala 371:17] + rvclkhdr_185.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_175 : UInt, rvclkhdr_185.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_175 <= btb_wr_data @[lib.scala 374:16] node _T_1104 = eq(btb_wr_addr, UInt<8>("h0b0")) @[ifu_bp_ctl.scala 415:95] node _T_1105 = and(_T_1104, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1106 = bits(_T_1105, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_186 of rvclkhdr_280 @[el2_lib.scala 508:23] + inst rvclkhdr_186 of rvclkhdr_280 @[lib.scala 368:23] rvclkhdr_186.clock <= clock rvclkhdr_186.reset <= reset - rvclkhdr_186.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_186.io.en <= _T_1106 @[el2_lib.scala 511:17] - rvclkhdr_186.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_176 : UInt, rvclkhdr_186.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_176 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_186.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_186.io.en <= _T_1106 @[lib.scala 371:17] + rvclkhdr_186.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_176 : UInt, rvclkhdr_186.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_176 <= btb_wr_data @[lib.scala 374:16] node _T_1107 = eq(btb_wr_addr, UInt<8>("h0b1")) @[ifu_bp_ctl.scala 415:95] node _T_1108 = and(_T_1107, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1109 = bits(_T_1108, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_187 of rvclkhdr_281 @[el2_lib.scala 508:23] + inst rvclkhdr_187 of rvclkhdr_281 @[lib.scala 368:23] rvclkhdr_187.clock <= clock rvclkhdr_187.reset <= reset - rvclkhdr_187.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_187.io.en <= _T_1109 @[el2_lib.scala 511:17] - rvclkhdr_187.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_177 : UInt, rvclkhdr_187.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_177 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_187.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_187.io.en <= _T_1109 @[lib.scala 371:17] + rvclkhdr_187.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_177 : UInt, rvclkhdr_187.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_177 <= btb_wr_data @[lib.scala 374:16] node _T_1110 = eq(btb_wr_addr, UInt<8>("h0b2")) @[ifu_bp_ctl.scala 415:95] node _T_1111 = and(_T_1110, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1112 = bits(_T_1111, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_188 of rvclkhdr_282 @[el2_lib.scala 508:23] + inst rvclkhdr_188 of rvclkhdr_282 @[lib.scala 368:23] rvclkhdr_188.clock <= clock rvclkhdr_188.reset <= reset - rvclkhdr_188.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_188.io.en <= _T_1112 @[el2_lib.scala 511:17] - rvclkhdr_188.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_178 : UInt, rvclkhdr_188.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_178 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_188.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_188.io.en <= _T_1112 @[lib.scala 371:17] + rvclkhdr_188.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_178 : UInt, rvclkhdr_188.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_178 <= btb_wr_data @[lib.scala 374:16] node _T_1113 = eq(btb_wr_addr, UInt<8>("h0b3")) @[ifu_bp_ctl.scala 415:95] node _T_1114 = and(_T_1113, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1115 = bits(_T_1114, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_189 of rvclkhdr_283 @[el2_lib.scala 508:23] + inst rvclkhdr_189 of rvclkhdr_283 @[lib.scala 368:23] rvclkhdr_189.clock <= clock rvclkhdr_189.reset <= reset - rvclkhdr_189.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_189.io.en <= _T_1115 @[el2_lib.scala 511:17] - rvclkhdr_189.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_179 : UInt, rvclkhdr_189.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_179 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_189.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_189.io.en <= _T_1115 @[lib.scala 371:17] + rvclkhdr_189.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_179 : UInt, rvclkhdr_189.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_179 <= btb_wr_data @[lib.scala 374:16] node _T_1116 = eq(btb_wr_addr, UInt<8>("h0b4")) @[ifu_bp_ctl.scala 415:95] node _T_1117 = and(_T_1116, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1118 = bits(_T_1117, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_190 of rvclkhdr_284 @[el2_lib.scala 508:23] + inst rvclkhdr_190 of rvclkhdr_284 @[lib.scala 368:23] rvclkhdr_190.clock <= clock rvclkhdr_190.reset <= reset - rvclkhdr_190.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_190.io.en <= _T_1118 @[el2_lib.scala 511:17] - rvclkhdr_190.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_180 : UInt, rvclkhdr_190.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_180 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_190.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_190.io.en <= _T_1118 @[lib.scala 371:17] + rvclkhdr_190.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_180 : UInt, rvclkhdr_190.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_180 <= btb_wr_data @[lib.scala 374:16] node _T_1119 = eq(btb_wr_addr, UInt<8>("h0b5")) @[ifu_bp_ctl.scala 415:95] node _T_1120 = and(_T_1119, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1121 = bits(_T_1120, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_191 of rvclkhdr_285 @[el2_lib.scala 508:23] + inst rvclkhdr_191 of rvclkhdr_285 @[lib.scala 368:23] rvclkhdr_191.clock <= clock rvclkhdr_191.reset <= reset - rvclkhdr_191.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_191.io.en <= _T_1121 @[el2_lib.scala 511:17] - rvclkhdr_191.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_181 : UInt, rvclkhdr_191.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_181 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_191.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_191.io.en <= _T_1121 @[lib.scala 371:17] + rvclkhdr_191.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_181 : UInt, rvclkhdr_191.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_181 <= btb_wr_data @[lib.scala 374:16] node _T_1122 = eq(btb_wr_addr, UInt<8>("h0b6")) @[ifu_bp_ctl.scala 415:95] node _T_1123 = and(_T_1122, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1124 = bits(_T_1123, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_192 of rvclkhdr_286 @[el2_lib.scala 508:23] + inst rvclkhdr_192 of rvclkhdr_286 @[lib.scala 368:23] rvclkhdr_192.clock <= clock rvclkhdr_192.reset <= reset - rvclkhdr_192.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_192.io.en <= _T_1124 @[el2_lib.scala 511:17] - rvclkhdr_192.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_182 : UInt, rvclkhdr_192.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_182 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_192.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_192.io.en <= _T_1124 @[lib.scala 371:17] + rvclkhdr_192.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_182 : UInt, rvclkhdr_192.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_182 <= btb_wr_data @[lib.scala 374:16] node _T_1125 = eq(btb_wr_addr, UInt<8>("h0b7")) @[ifu_bp_ctl.scala 415:95] node _T_1126 = and(_T_1125, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1127 = bits(_T_1126, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_193 of rvclkhdr_287 @[el2_lib.scala 508:23] + inst rvclkhdr_193 of rvclkhdr_287 @[lib.scala 368:23] rvclkhdr_193.clock <= clock rvclkhdr_193.reset <= reset - rvclkhdr_193.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_193.io.en <= _T_1127 @[el2_lib.scala 511:17] - rvclkhdr_193.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_183 : UInt, rvclkhdr_193.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_183 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_193.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_193.io.en <= _T_1127 @[lib.scala 371:17] + rvclkhdr_193.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_183 : UInt, rvclkhdr_193.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_183 <= btb_wr_data @[lib.scala 374:16] node _T_1128 = eq(btb_wr_addr, UInt<8>("h0b8")) @[ifu_bp_ctl.scala 415:95] node _T_1129 = and(_T_1128, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1130 = bits(_T_1129, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_194 of rvclkhdr_288 @[el2_lib.scala 508:23] + inst rvclkhdr_194 of rvclkhdr_288 @[lib.scala 368:23] rvclkhdr_194.clock <= clock rvclkhdr_194.reset <= reset - rvclkhdr_194.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_194.io.en <= _T_1130 @[el2_lib.scala 511:17] - rvclkhdr_194.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_184 : UInt, rvclkhdr_194.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_184 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_194.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_194.io.en <= _T_1130 @[lib.scala 371:17] + rvclkhdr_194.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_184 : UInt, rvclkhdr_194.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_184 <= btb_wr_data @[lib.scala 374:16] node _T_1131 = eq(btb_wr_addr, UInt<8>("h0b9")) @[ifu_bp_ctl.scala 415:95] node _T_1132 = and(_T_1131, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1133 = bits(_T_1132, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_195 of rvclkhdr_289 @[el2_lib.scala 508:23] + inst rvclkhdr_195 of rvclkhdr_289 @[lib.scala 368:23] rvclkhdr_195.clock <= clock rvclkhdr_195.reset <= reset - rvclkhdr_195.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_195.io.en <= _T_1133 @[el2_lib.scala 511:17] - rvclkhdr_195.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_185 : UInt, rvclkhdr_195.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_185 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_195.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_195.io.en <= _T_1133 @[lib.scala 371:17] + rvclkhdr_195.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_185 : UInt, rvclkhdr_195.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_185 <= btb_wr_data @[lib.scala 374:16] node _T_1134 = eq(btb_wr_addr, UInt<8>("h0ba")) @[ifu_bp_ctl.scala 415:95] node _T_1135 = and(_T_1134, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1136 = bits(_T_1135, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_196 of rvclkhdr_290 @[el2_lib.scala 508:23] + inst rvclkhdr_196 of rvclkhdr_290 @[lib.scala 368:23] rvclkhdr_196.clock <= clock rvclkhdr_196.reset <= reset - rvclkhdr_196.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_196.io.en <= _T_1136 @[el2_lib.scala 511:17] - rvclkhdr_196.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_186 : UInt, rvclkhdr_196.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_186 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_196.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_196.io.en <= _T_1136 @[lib.scala 371:17] + rvclkhdr_196.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_186 : UInt, rvclkhdr_196.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_186 <= btb_wr_data @[lib.scala 374:16] node _T_1137 = eq(btb_wr_addr, UInt<8>("h0bb")) @[ifu_bp_ctl.scala 415:95] node _T_1138 = and(_T_1137, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1139 = bits(_T_1138, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_197 of rvclkhdr_291 @[el2_lib.scala 508:23] + inst rvclkhdr_197 of rvclkhdr_291 @[lib.scala 368:23] rvclkhdr_197.clock <= clock rvclkhdr_197.reset <= reset - rvclkhdr_197.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_197.io.en <= _T_1139 @[el2_lib.scala 511:17] - rvclkhdr_197.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_187 : UInt, rvclkhdr_197.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_187 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_197.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_197.io.en <= _T_1139 @[lib.scala 371:17] + rvclkhdr_197.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_187 : UInt, rvclkhdr_197.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_187 <= btb_wr_data @[lib.scala 374:16] node _T_1140 = eq(btb_wr_addr, UInt<8>("h0bc")) @[ifu_bp_ctl.scala 415:95] node _T_1141 = and(_T_1140, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1142 = bits(_T_1141, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_198 of rvclkhdr_292 @[el2_lib.scala 508:23] + inst rvclkhdr_198 of rvclkhdr_292 @[lib.scala 368:23] rvclkhdr_198.clock <= clock rvclkhdr_198.reset <= reset - rvclkhdr_198.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_198.io.en <= _T_1142 @[el2_lib.scala 511:17] - rvclkhdr_198.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_188 : UInt, rvclkhdr_198.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_188 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_198.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_198.io.en <= _T_1142 @[lib.scala 371:17] + rvclkhdr_198.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_188 : UInt, rvclkhdr_198.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_188 <= btb_wr_data @[lib.scala 374:16] node _T_1143 = eq(btb_wr_addr, UInt<8>("h0bd")) @[ifu_bp_ctl.scala 415:95] node _T_1144 = and(_T_1143, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1145 = bits(_T_1144, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_199 of rvclkhdr_293 @[el2_lib.scala 508:23] + inst rvclkhdr_199 of rvclkhdr_293 @[lib.scala 368:23] rvclkhdr_199.clock <= clock rvclkhdr_199.reset <= reset - rvclkhdr_199.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_199.io.en <= _T_1145 @[el2_lib.scala 511:17] - rvclkhdr_199.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_189 : UInt, rvclkhdr_199.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_189 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_199.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_199.io.en <= _T_1145 @[lib.scala 371:17] + rvclkhdr_199.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_189 : UInt, rvclkhdr_199.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_189 <= btb_wr_data @[lib.scala 374:16] node _T_1146 = eq(btb_wr_addr, UInt<8>("h0be")) @[ifu_bp_ctl.scala 415:95] node _T_1147 = and(_T_1146, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1148 = bits(_T_1147, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_200 of rvclkhdr_294 @[el2_lib.scala 508:23] + inst rvclkhdr_200 of rvclkhdr_294 @[lib.scala 368:23] rvclkhdr_200.clock <= clock rvclkhdr_200.reset <= reset - rvclkhdr_200.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_200.io.en <= _T_1148 @[el2_lib.scala 511:17] - rvclkhdr_200.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_190 : UInt, rvclkhdr_200.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_190 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_200.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_200.io.en <= _T_1148 @[lib.scala 371:17] + rvclkhdr_200.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_190 : UInt, rvclkhdr_200.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_190 <= btb_wr_data @[lib.scala 374:16] node _T_1149 = eq(btb_wr_addr, UInt<8>("h0bf")) @[ifu_bp_ctl.scala 415:95] node _T_1150 = and(_T_1149, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1151 = bits(_T_1150, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_201 of rvclkhdr_295 @[el2_lib.scala 508:23] + inst rvclkhdr_201 of rvclkhdr_295 @[lib.scala 368:23] rvclkhdr_201.clock <= clock rvclkhdr_201.reset <= reset - rvclkhdr_201.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_201.io.en <= _T_1151 @[el2_lib.scala 511:17] - rvclkhdr_201.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_191 : UInt, rvclkhdr_201.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_191 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_201.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_201.io.en <= _T_1151 @[lib.scala 371:17] + rvclkhdr_201.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_191 : UInt, rvclkhdr_201.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_191 <= btb_wr_data @[lib.scala 374:16] node _T_1152 = eq(btb_wr_addr, UInt<8>("h0c0")) @[ifu_bp_ctl.scala 415:95] node _T_1153 = and(_T_1152, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1154 = bits(_T_1153, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_202 of rvclkhdr_296 @[el2_lib.scala 508:23] + inst rvclkhdr_202 of rvclkhdr_296 @[lib.scala 368:23] rvclkhdr_202.clock <= clock rvclkhdr_202.reset <= reset - rvclkhdr_202.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_202.io.en <= _T_1154 @[el2_lib.scala 511:17] - rvclkhdr_202.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_192 : UInt, rvclkhdr_202.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_192 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_202.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_202.io.en <= _T_1154 @[lib.scala 371:17] + rvclkhdr_202.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_192 : UInt, rvclkhdr_202.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_192 <= btb_wr_data @[lib.scala 374:16] node _T_1155 = eq(btb_wr_addr, UInt<8>("h0c1")) @[ifu_bp_ctl.scala 415:95] node _T_1156 = and(_T_1155, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1157 = bits(_T_1156, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_203 of rvclkhdr_297 @[el2_lib.scala 508:23] + inst rvclkhdr_203 of rvclkhdr_297 @[lib.scala 368:23] rvclkhdr_203.clock <= clock rvclkhdr_203.reset <= reset - rvclkhdr_203.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_203.io.en <= _T_1157 @[el2_lib.scala 511:17] - rvclkhdr_203.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_193 : UInt, rvclkhdr_203.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_193 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_203.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_203.io.en <= _T_1157 @[lib.scala 371:17] + rvclkhdr_203.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_193 : UInt, rvclkhdr_203.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_193 <= btb_wr_data @[lib.scala 374:16] node _T_1158 = eq(btb_wr_addr, UInt<8>("h0c2")) @[ifu_bp_ctl.scala 415:95] node _T_1159 = and(_T_1158, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1160 = bits(_T_1159, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_204 of rvclkhdr_298 @[el2_lib.scala 508:23] + inst rvclkhdr_204 of rvclkhdr_298 @[lib.scala 368:23] rvclkhdr_204.clock <= clock rvclkhdr_204.reset <= reset - rvclkhdr_204.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_204.io.en <= _T_1160 @[el2_lib.scala 511:17] - rvclkhdr_204.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_194 : UInt, rvclkhdr_204.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_194 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_204.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_204.io.en <= _T_1160 @[lib.scala 371:17] + rvclkhdr_204.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_194 : UInt, rvclkhdr_204.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_194 <= btb_wr_data @[lib.scala 374:16] node _T_1161 = eq(btb_wr_addr, UInt<8>("h0c3")) @[ifu_bp_ctl.scala 415:95] node _T_1162 = and(_T_1161, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1163 = bits(_T_1162, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_205 of rvclkhdr_299 @[el2_lib.scala 508:23] + inst rvclkhdr_205 of rvclkhdr_299 @[lib.scala 368:23] rvclkhdr_205.clock <= clock rvclkhdr_205.reset <= reset - rvclkhdr_205.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_205.io.en <= _T_1163 @[el2_lib.scala 511:17] - rvclkhdr_205.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_195 : UInt, rvclkhdr_205.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_195 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_205.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_205.io.en <= _T_1163 @[lib.scala 371:17] + rvclkhdr_205.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_195 : UInt, rvclkhdr_205.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_195 <= btb_wr_data @[lib.scala 374:16] node _T_1164 = eq(btb_wr_addr, UInt<8>("h0c4")) @[ifu_bp_ctl.scala 415:95] node _T_1165 = and(_T_1164, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1166 = bits(_T_1165, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_206 of rvclkhdr_300 @[el2_lib.scala 508:23] + inst rvclkhdr_206 of rvclkhdr_300 @[lib.scala 368:23] rvclkhdr_206.clock <= clock rvclkhdr_206.reset <= reset - rvclkhdr_206.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_206.io.en <= _T_1166 @[el2_lib.scala 511:17] - rvclkhdr_206.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_196 : UInt, rvclkhdr_206.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_196 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_206.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_206.io.en <= _T_1166 @[lib.scala 371:17] + rvclkhdr_206.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_196 : UInt, rvclkhdr_206.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_196 <= btb_wr_data @[lib.scala 374:16] node _T_1167 = eq(btb_wr_addr, UInt<8>("h0c5")) @[ifu_bp_ctl.scala 415:95] node _T_1168 = and(_T_1167, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1169 = bits(_T_1168, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_207 of rvclkhdr_301 @[el2_lib.scala 508:23] + inst rvclkhdr_207 of rvclkhdr_301 @[lib.scala 368:23] rvclkhdr_207.clock <= clock rvclkhdr_207.reset <= reset - rvclkhdr_207.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_207.io.en <= _T_1169 @[el2_lib.scala 511:17] - rvclkhdr_207.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_197 : UInt, rvclkhdr_207.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_197 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_207.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_207.io.en <= _T_1169 @[lib.scala 371:17] + rvclkhdr_207.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_197 : UInt, rvclkhdr_207.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_197 <= btb_wr_data @[lib.scala 374:16] node _T_1170 = eq(btb_wr_addr, UInt<8>("h0c6")) @[ifu_bp_ctl.scala 415:95] node _T_1171 = and(_T_1170, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1172 = bits(_T_1171, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_208 of rvclkhdr_302 @[el2_lib.scala 508:23] + inst rvclkhdr_208 of rvclkhdr_302 @[lib.scala 368:23] rvclkhdr_208.clock <= clock rvclkhdr_208.reset <= reset - rvclkhdr_208.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_208.io.en <= _T_1172 @[el2_lib.scala 511:17] - rvclkhdr_208.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_198 : UInt, rvclkhdr_208.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_198 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_208.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_208.io.en <= _T_1172 @[lib.scala 371:17] + rvclkhdr_208.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_198 : UInt, rvclkhdr_208.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_198 <= btb_wr_data @[lib.scala 374:16] node _T_1173 = eq(btb_wr_addr, UInt<8>("h0c7")) @[ifu_bp_ctl.scala 415:95] node _T_1174 = and(_T_1173, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1175 = bits(_T_1174, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_209 of rvclkhdr_303 @[el2_lib.scala 508:23] + inst rvclkhdr_209 of rvclkhdr_303 @[lib.scala 368:23] rvclkhdr_209.clock <= clock rvclkhdr_209.reset <= reset - rvclkhdr_209.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_209.io.en <= _T_1175 @[el2_lib.scala 511:17] - rvclkhdr_209.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_199 : UInt, rvclkhdr_209.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_199 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_209.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_209.io.en <= _T_1175 @[lib.scala 371:17] + rvclkhdr_209.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_199 : UInt, rvclkhdr_209.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_199 <= btb_wr_data @[lib.scala 374:16] node _T_1176 = eq(btb_wr_addr, UInt<8>("h0c8")) @[ifu_bp_ctl.scala 415:95] node _T_1177 = and(_T_1176, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1178 = bits(_T_1177, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_210 of rvclkhdr_304 @[el2_lib.scala 508:23] + inst rvclkhdr_210 of rvclkhdr_304 @[lib.scala 368:23] rvclkhdr_210.clock <= clock rvclkhdr_210.reset <= reset - rvclkhdr_210.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_210.io.en <= _T_1178 @[el2_lib.scala 511:17] - rvclkhdr_210.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_200 : UInt, rvclkhdr_210.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_200 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_210.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_210.io.en <= _T_1178 @[lib.scala 371:17] + rvclkhdr_210.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_200 : UInt, rvclkhdr_210.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_200 <= btb_wr_data @[lib.scala 374:16] node _T_1179 = eq(btb_wr_addr, UInt<8>("h0c9")) @[ifu_bp_ctl.scala 415:95] node _T_1180 = and(_T_1179, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1181 = bits(_T_1180, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_211 of rvclkhdr_305 @[el2_lib.scala 508:23] + inst rvclkhdr_211 of rvclkhdr_305 @[lib.scala 368:23] rvclkhdr_211.clock <= clock rvclkhdr_211.reset <= reset - rvclkhdr_211.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_211.io.en <= _T_1181 @[el2_lib.scala 511:17] - rvclkhdr_211.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_201 : UInt, rvclkhdr_211.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_201 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_211.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_211.io.en <= _T_1181 @[lib.scala 371:17] + rvclkhdr_211.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_201 : UInt, rvclkhdr_211.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_201 <= btb_wr_data @[lib.scala 374:16] node _T_1182 = eq(btb_wr_addr, UInt<8>("h0ca")) @[ifu_bp_ctl.scala 415:95] node _T_1183 = and(_T_1182, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1184 = bits(_T_1183, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_212 of rvclkhdr_306 @[el2_lib.scala 508:23] + inst rvclkhdr_212 of rvclkhdr_306 @[lib.scala 368:23] rvclkhdr_212.clock <= clock rvclkhdr_212.reset <= reset - rvclkhdr_212.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_212.io.en <= _T_1184 @[el2_lib.scala 511:17] - rvclkhdr_212.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_202 : UInt, rvclkhdr_212.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_202 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_212.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_212.io.en <= _T_1184 @[lib.scala 371:17] + rvclkhdr_212.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_202 : UInt, rvclkhdr_212.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_202 <= btb_wr_data @[lib.scala 374:16] node _T_1185 = eq(btb_wr_addr, UInt<8>("h0cb")) @[ifu_bp_ctl.scala 415:95] node _T_1186 = and(_T_1185, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1187 = bits(_T_1186, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_213 of rvclkhdr_307 @[el2_lib.scala 508:23] + inst rvclkhdr_213 of rvclkhdr_307 @[lib.scala 368:23] rvclkhdr_213.clock <= clock rvclkhdr_213.reset <= reset - rvclkhdr_213.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_213.io.en <= _T_1187 @[el2_lib.scala 511:17] - rvclkhdr_213.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_203 : UInt, rvclkhdr_213.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_203 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_213.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_213.io.en <= _T_1187 @[lib.scala 371:17] + rvclkhdr_213.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_203 : UInt, rvclkhdr_213.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_203 <= btb_wr_data @[lib.scala 374:16] node _T_1188 = eq(btb_wr_addr, UInt<8>("h0cc")) @[ifu_bp_ctl.scala 415:95] node _T_1189 = and(_T_1188, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1190 = bits(_T_1189, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_214 of rvclkhdr_308 @[el2_lib.scala 508:23] + inst rvclkhdr_214 of rvclkhdr_308 @[lib.scala 368:23] rvclkhdr_214.clock <= clock rvclkhdr_214.reset <= reset - rvclkhdr_214.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_214.io.en <= _T_1190 @[el2_lib.scala 511:17] - rvclkhdr_214.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_204 : UInt, rvclkhdr_214.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_204 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_214.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_214.io.en <= _T_1190 @[lib.scala 371:17] + rvclkhdr_214.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_204 : UInt, rvclkhdr_214.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_204 <= btb_wr_data @[lib.scala 374:16] node _T_1191 = eq(btb_wr_addr, UInt<8>("h0cd")) @[ifu_bp_ctl.scala 415:95] node _T_1192 = and(_T_1191, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1193 = bits(_T_1192, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_215 of rvclkhdr_309 @[el2_lib.scala 508:23] + inst rvclkhdr_215 of rvclkhdr_309 @[lib.scala 368:23] rvclkhdr_215.clock <= clock rvclkhdr_215.reset <= reset - rvclkhdr_215.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_215.io.en <= _T_1193 @[el2_lib.scala 511:17] - rvclkhdr_215.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_205 : UInt, rvclkhdr_215.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_205 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_215.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_215.io.en <= _T_1193 @[lib.scala 371:17] + rvclkhdr_215.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_205 : UInt, rvclkhdr_215.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_205 <= btb_wr_data @[lib.scala 374:16] node _T_1194 = eq(btb_wr_addr, UInt<8>("h0ce")) @[ifu_bp_ctl.scala 415:95] node _T_1195 = and(_T_1194, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1196 = bits(_T_1195, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_216 of rvclkhdr_310 @[el2_lib.scala 508:23] + inst rvclkhdr_216 of rvclkhdr_310 @[lib.scala 368:23] rvclkhdr_216.clock <= clock rvclkhdr_216.reset <= reset - rvclkhdr_216.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_216.io.en <= _T_1196 @[el2_lib.scala 511:17] - rvclkhdr_216.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_206 : UInt, rvclkhdr_216.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_206 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_216.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_216.io.en <= _T_1196 @[lib.scala 371:17] + rvclkhdr_216.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_206 : UInt, rvclkhdr_216.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_206 <= btb_wr_data @[lib.scala 374:16] node _T_1197 = eq(btb_wr_addr, UInt<8>("h0cf")) @[ifu_bp_ctl.scala 415:95] node _T_1198 = and(_T_1197, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1199 = bits(_T_1198, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_217 of rvclkhdr_311 @[el2_lib.scala 508:23] + inst rvclkhdr_217 of rvclkhdr_311 @[lib.scala 368:23] rvclkhdr_217.clock <= clock rvclkhdr_217.reset <= reset - rvclkhdr_217.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_217.io.en <= _T_1199 @[el2_lib.scala 511:17] - rvclkhdr_217.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_207 : UInt, rvclkhdr_217.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_207 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_217.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_217.io.en <= _T_1199 @[lib.scala 371:17] + rvclkhdr_217.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_207 : UInt, rvclkhdr_217.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_207 <= btb_wr_data @[lib.scala 374:16] node _T_1200 = eq(btb_wr_addr, UInt<8>("h0d0")) @[ifu_bp_ctl.scala 415:95] node _T_1201 = and(_T_1200, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1202 = bits(_T_1201, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_218 of rvclkhdr_312 @[el2_lib.scala 508:23] + inst rvclkhdr_218 of rvclkhdr_312 @[lib.scala 368:23] rvclkhdr_218.clock <= clock rvclkhdr_218.reset <= reset - rvclkhdr_218.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_218.io.en <= _T_1202 @[el2_lib.scala 511:17] - rvclkhdr_218.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_208 : UInt, rvclkhdr_218.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_208 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_218.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_218.io.en <= _T_1202 @[lib.scala 371:17] + rvclkhdr_218.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_208 : UInt, rvclkhdr_218.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_208 <= btb_wr_data @[lib.scala 374:16] node _T_1203 = eq(btb_wr_addr, UInt<8>("h0d1")) @[ifu_bp_ctl.scala 415:95] node _T_1204 = and(_T_1203, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1205 = bits(_T_1204, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_219 of rvclkhdr_313 @[el2_lib.scala 508:23] + inst rvclkhdr_219 of rvclkhdr_313 @[lib.scala 368:23] rvclkhdr_219.clock <= clock rvclkhdr_219.reset <= reset - rvclkhdr_219.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_219.io.en <= _T_1205 @[el2_lib.scala 511:17] - rvclkhdr_219.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_209 : UInt, rvclkhdr_219.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_209 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_219.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_219.io.en <= _T_1205 @[lib.scala 371:17] + rvclkhdr_219.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_209 : UInt, rvclkhdr_219.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_209 <= btb_wr_data @[lib.scala 374:16] node _T_1206 = eq(btb_wr_addr, UInt<8>("h0d2")) @[ifu_bp_ctl.scala 415:95] node _T_1207 = and(_T_1206, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1208 = bits(_T_1207, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_220 of rvclkhdr_314 @[el2_lib.scala 508:23] + inst rvclkhdr_220 of rvclkhdr_314 @[lib.scala 368:23] rvclkhdr_220.clock <= clock rvclkhdr_220.reset <= reset - rvclkhdr_220.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_220.io.en <= _T_1208 @[el2_lib.scala 511:17] - rvclkhdr_220.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_210 : UInt, rvclkhdr_220.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_210 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_220.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_220.io.en <= _T_1208 @[lib.scala 371:17] + rvclkhdr_220.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_210 : UInt, rvclkhdr_220.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_210 <= btb_wr_data @[lib.scala 374:16] node _T_1209 = eq(btb_wr_addr, UInt<8>("h0d3")) @[ifu_bp_ctl.scala 415:95] node _T_1210 = and(_T_1209, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1211 = bits(_T_1210, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_221 of rvclkhdr_315 @[el2_lib.scala 508:23] + inst rvclkhdr_221 of rvclkhdr_315 @[lib.scala 368:23] rvclkhdr_221.clock <= clock rvclkhdr_221.reset <= reset - rvclkhdr_221.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_221.io.en <= _T_1211 @[el2_lib.scala 511:17] - rvclkhdr_221.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_211 : UInt, rvclkhdr_221.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_211 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_221.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_221.io.en <= _T_1211 @[lib.scala 371:17] + rvclkhdr_221.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_211 : UInt, rvclkhdr_221.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_211 <= btb_wr_data @[lib.scala 374:16] node _T_1212 = eq(btb_wr_addr, UInt<8>("h0d4")) @[ifu_bp_ctl.scala 415:95] node _T_1213 = and(_T_1212, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1214 = bits(_T_1213, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_222 of rvclkhdr_316 @[el2_lib.scala 508:23] + inst rvclkhdr_222 of rvclkhdr_316 @[lib.scala 368:23] rvclkhdr_222.clock <= clock rvclkhdr_222.reset <= reset - rvclkhdr_222.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_222.io.en <= _T_1214 @[el2_lib.scala 511:17] - rvclkhdr_222.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_212 : UInt, rvclkhdr_222.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_212 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_222.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_222.io.en <= _T_1214 @[lib.scala 371:17] + rvclkhdr_222.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_212 : UInt, rvclkhdr_222.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_212 <= btb_wr_data @[lib.scala 374:16] node _T_1215 = eq(btb_wr_addr, UInt<8>("h0d5")) @[ifu_bp_ctl.scala 415:95] node _T_1216 = and(_T_1215, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1217 = bits(_T_1216, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_223 of rvclkhdr_317 @[el2_lib.scala 508:23] + inst rvclkhdr_223 of rvclkhdr_317 @[lib.scala 368:23] rvclkhdr_223.clock <= clock rvclkhdr_223.reset <= reset - rvclkhdr_223.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_223.io.en <= _T_1217 @[el2_lib.scala 511:17] - rvclkhdr_223.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_213 : UInt, rvclkhdr_223.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_213 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_223.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_223.io.en <= _T_1217 @[lib.scala 371:17] + rvclkhdr_223.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_213 : UInt, rvclkhdr_223.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_213 <= btb_wr_data @[lib.scala 374:16] node _T_1218 = eq(btb_wr_addr, UInt<8>("h0d6")) @[ifu_bp_ctl.scala 415:95] node _T_1219 = and(_T_1218, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1220 = bits(_T_1219, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_224 of rvclkhdr_318 @[el2_lib.scala 508:23] + inst rvclkhdr_224 of rvclkhdr_318 @[lib.scala 368:23] rvclkhdr_224.clock <= clock rvclkhdr_224.reset <= reset - rvclkhdr_224.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_224.io.en <= _T_1220 @[el2_lib.scala 511:17] - rvclkhdr_224.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_214 : UInt, rvclkhdr_224.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_214 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_224.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_224.io.en <= _T_1220 @[lib.scala 371:17] + rvclkhdr_224.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_214 : UInt, rvclkhdr_224.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_214 <= btb_wr_data @[lib.scala 374:16] node _T_1221 = eq(btb_wr_addr, UInt<8>("h0d7")) @[ifu_bp_ctl.scala 415:95] node _T_1222 = and(_T_1221, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1223 = bits(_T_1222, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_225 of rvclkhdr_319 @[el2_lib.scala 508:23] + inst rvclkhdr_225 of rvclkhdr_319 @[lib.scala 368:23] rvclkhdr_225.clock <= clock rvclkhdr_225.reset <= reset - rvclkhdr_225.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_225.io.en <= _T_1223 @[el2_lib.scala 511:17] - rvclkhdr_225.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_215 : UInt, rvclkhdr_225.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_215 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_225.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_225.io.en <= _T_1223 @[lib.scala 371:17] + rvclkhdr_225.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_215 : UInt, rvclkhdr_225.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_215 <= btb_wr_data @[lib.scala 374:16] node _T_1224 = eq(btb_wr_addr, UInt<8>("h0d8")) @[ifu_bp_ctl.scala 415:95] node _T_1225 = and(_T_1224, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1226 = bits(_T_1225, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_226 of rvclkhdr_320 @[el2_lib.scala 508:23] + inst rvclkhdr_226 of rvclkhdr_320 @[lib.scala 368:23] rvclkhdr_226.clock <= clock rvclkhdr_226.reset <= reset - rvclkhdr_226.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_226.io.en <= _T_1226 @[el2_lib.scala 511:17] - rvclkhdr_226.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_216 : UInt, rvclkhdr_226.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_216 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_226.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_226.io.en <= _T_1226 @[lib.scala 371:17] + rvclkhdr_226.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_216 : UInt, rvclkhdr_226.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_216 <= btb_wr_data @[lib.scala 374:16] node _T_1227 = eq(btb_wr_addr, UInt<8>("h0d9")) @[ifu_bp_ctl.scala 415:95] node _T_1228 = and(_T_1227, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1229 = bits(_T_1228, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_227 of rvclkhdr_321 @[el2_lib.scala 508:23] + inst rvclkhdr_227 of rvclkhdr_321 @[lib.scala 368:23] rvclkhdr_227.clock <= clock rvclkhdr_227.reset <= reset - rvclkhdr_227.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_227.io.en <= _T_1229 @[el2_lib.scala 511:17] - rvclkhdr_227.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_217 : UInt, rvclkhdr_227.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_217 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_227.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_227.io.en <= _T_1229 @[lib.scala 371:17] + rvclkhdr_227.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_217 : UInt, rvclkhdr_227.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_217 <= btb_wr_data @[lib.scala 374:16] node _T_1230 = eq(btb_wr_addr, UInt<8>("h0da")) @[ifu_bp_ctl.scala 415:95] node _T_1231 = and(_T_1230, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1232 = bits(_T_1231, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_228 of rvclkhdr_322 @[el2_lib.scala 508:23] + inst rvclkhdr_228 of rvclkhdr_322 @[lib.scala 368:23] rvclkhdr_228.clock <= clock rvclkhdr_228.reset <= reset - rvclkhdr_228.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_228.io.en <= _T_1232 @[el2_lib.scala 511:17] - rvclkhdr_228.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_218 : UInt, rvclkhdr_228.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_218 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_228.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_228.io.en <= _T_1232 @[lib.scala 371:17] + rvclkhdr_228.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_218 : UInt, rvclkhdr_228.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_218 <= btb_wr_data @[lib.scala 374:16] node _T_1233 = eq(btb_wr_addr, UInt<8>("h0db")) @[ifu_bp_ctl.scala 415:95] node _T_1234 = and(_T_1233, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1235 = bits(_T_1234, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_229 of rvclkhdr_323 @[el2_lib.scala 508:23] + inst rvclkhdr_229 of rvclkhdr_323 @[lib.scala 368:23] rvclkhdr_229.clock <= clock rvclkhdr_229.reset <= reset - rvclkhdr_229.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_229.io.en <= _T_1235 @[el2_lib.scala 511:17] - rvclkhdr_229.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_219 : UInt, rvclkhdr_229.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_219 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_229.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_229.io.en <= _T_1235 @[lib.scala 371:17] + rvclkhdr_229.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_219 : UInt, rvclkhdr_229.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_219 <= btb_wr_data @[lib.scala 374:16] node _T_1236 = eq(btb_wr_addr, UInt<8>("h0dc")) @[ifu_bp_ctl.scala 415:95] node _T_1237 = and(_T_1236, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1238 = bits(_T_1237, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_230 of rvclkhdr_324 @[el2_lib.scala 508:23] + inst rvclkhdr_230 of rvclkhdr_324 @[lib.scala 368:23] rvclkhdr_230.clock <= clock rvclkhdr_230.reset <= reset - rvclkhdr_230.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_230.io.en <= _T_1238 @[el2_lib.scala 511:17] - rvclkhdr_230.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_220 : UInt, rvclkhdr_230.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_220 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_230.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_230.io.en <= _T_1238 @[lib.scala 371:17] + rvclkhdr_230.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_220 : UInt, rvclkhdr_230.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_220 <= btb_wr_data @[lib.scala 374:16] node _T_1239 = eq(btb_wr_addr, UInt<8>("h0dd")) @[ifu_bp_ctl.scala 415:95] node _T_1240 = and(_T_1239, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1241 = bits(_T_1240, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_231 of rvclkhdr_325 @[el2_lib.scala 508:23] + inst rvclkhdr_231 of rvclkhdr_325 @[lib.scala 368:23] rvclkhdr_231.clock <= clock rvclkhdr_231.reset <= reset - rvclkhdr_231.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_231.io.en <= _T_1241 @[el2_lib.scala 511:17] - rvclkhdr_231.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_221 : UInt, rvclkhdr_231.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_221 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_231.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_231.io.en <= _T_1241 @[lib.scala 371:17] + rvclkhdr_231.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_221 : UInt, rvclkhdr_231.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_221 <= btb_wr_data @[lib.scala 374:16] node _T_1242 = eq(btb_wr_addr, UInt<8>("h0de")) @[ifu_bp_ctl.scala 415:95] node _T_1243 = and(_T_1242, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1244 = bits(_T_1243, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_232 of rvclkhdr_326 @[el2_lib.scala 508:23] + inst rvclkhdr_232 of rvclkhdr_326 @[lib.scala 368:23] rvclkhdr_232.clock <= clock rvclkhdr_232.reset <= reset - rvclkhdr_232.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_232.io.en <= _T_1244 @[el2_lib.scala 511:17] - rvclkhdr_232.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_222 : UInt, rvclkhdr_232.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_222 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_232.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_232.io.en <= _T_1244 @[lib.scala 371:17] + rvclkhdr_232.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_222 : UInt, rvclkhdr_232.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_222 <= btb_wr_data @[lib.scala 374:16] node _T_1245 = eq(btb_wr_addr, UInt<8>("h0df")) @[ifu_bp_ctl.scala 415:95] node _T_1246 = and(_T_1245, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1247 = bits(_T_1246, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_233 of rvclkhdr_327 @[el2_lib.scala 508:23] + inst rvclkhdr_233 of rvclkhdr_327 @[lib.scala 368:23] rvclkhdr_233.clock <= clock rvclkhdr_233.reset <= reset - rvclkhdr_233.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_233.io.en <= _T_1247 @[el2_lib.scala 511:17] - rvclkhdr_233.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_223 : UInt, rvclkhdr_233.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_223 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_233.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_233.io.en <= _T_1247 @[lib.scala 371:17] + rvclkhdr_233.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_223 : UInt, rvclkhdr_233.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_223 <= btb_wr_data @[lib.scala 374:16] node _T_1248 = eq(btb_wr_addr, UInt<8>("h0e0")) @[ifu_bp_ctl.scala 415:95] node _T_1249 = and(_T_1248, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1250 = bits(_T_1249, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_234 of rvclkhdr_328 @[el2_lib.scala 508:23] + inst rvclkhdr_234 of rvclkhdr_328 @[lib.scala 368:23] rvclkhdr_234.clock <= clock rvclkhdr_234.reset <= reset - rvclkhdr_234.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_234.io.en <= _T_1250 @[el2_lib.scala 511:17] - rvclkhdr_234.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_224 : UInt, rvclkhdr_234.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_224 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_234.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_234.io.en <= _T_1250 @[lib.scala 371:17] + rvclkhdr_234.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_224 : UInt, rvclkhdr_234.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_224 <= btb_wr_data @[lib.scala 374:16] node _T_1251 = eq(btb_wr_addr, UInt<8>("h0e1")) @[ifu_bp_ctl.scala 415:95] node _T_1252 = and(_T_1251, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1253 = bits(_T_1252, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_235 of rvclkhdr_329 @[el2_lib.scala 508:23] + inst rvclkhdr_235 of rvclkhdr_329 @[lib.scala 368:23] rvclkhdr_235.clock <= clock rvclkhdr_235.reset <= reset - rvclkhdr_235.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_235.io.en <= _T_1253 @[el2_lib.scala 511:17] - rvclkhdr_235.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_225 : UInt, rvclkhdr_235.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_225 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_235.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_235.io.en <= _T_1253 @[lib.scala 371:17] + rvclkhdr_235.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_225 : UInt, rvclkhdr_235.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_225 <= btb_wr_data @[lib.scala 374:16] node _T_1254 = eq(btb_wr_addr, UInt<8>("h0e2")) @[ifu_bp_ctl.scala 415:95] node _T_1255 = and(_T_1254, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1256 = bits(_T_1255, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_236 of rvclkhdr_330 @[el2_lib.scala 508:23] + inst rvclkhdr_236 of rvclkhdr_330 @[lib.scala 368:23] rvclkhdr_236.clock <= clock rvclkhdr_236.reset <= reset - rvclkhdr_236.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_236.io.en <= _T_1256 @[el2_lib.scala 511:17] - rvclkhdr_236.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_226 : UInt, rvclkhdr_236.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_226 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_236.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_236.io.en <= _T_1256 @[lib.scala 371:17] + rvclkhdr_236.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_226 : UInt, rvclkhdr_236.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_226 <= btb_wr_data @[lib.scala 374:16] node _T_1257 = eq(btb_wr_addr, UInt<8>("h0e3")) @[ifu_bp_ctl.scala 415:95] node _T_1258 = and(_T_1257, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1259 = bits(_T_1258, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_237 of rvclkhdr_331 @[el2_lib.scala 508:23] + inst rvclkhdr_237 of rvclkhdr_331 @[lib.scala 368:23] rvclkhdr_237.clock <= clock rvclkhdr_237.reset <= reset - rvclkhdr_237.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_237.io.en <= _T_1259 @[el2_lib.scala 511:17] - rvclkhdr_237.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_227 : UInt, rvclkhdr_237.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_227 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_237.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_237.io.en <= _T_1259 @[lib.scala 371:17] + rvclkhdr_237.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_227 : UInt, rvclkhdr_237.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_227 <= btb_wr_data @[lib.scala 374:16] node _T_1260 = eq(btb_wr_addr, UInt<8>("h0e4")) @[ifu_bp_ctl.scala 415:95] node _T_1261 = and(_T_1260, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1262 = bits(_T_1261, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_238 of rvclkhdr_332 @[el2_lib.scala 508:23] + inst rvclkhdr_238 of rvclkhdr_332 @[lib.scala 368:23] rvclkhdr_238.clock <= clock rvclkhdr_238.reset <= reset - rvclkhdr_238.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_238.io.en <= _T_1262 @[el2_lib.scala 511:17] - rvclkhdr_238.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_228 : UInt, rvclkhdr_238.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_228 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_238.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_238.io.en <= _T_1262 @[lib.scala 371:17] + rvclkhdr_238.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_228 : UInt, rvclkhdr_238.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_228 <= btb_wr_data @[lib.scala 374:16] node _T_1263 = eq(btb_wr_addr, UInt<8>("h0e5")) @[ifu_bp_ctl.scala 415:95] node _T_1264 = and(_T_1263, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1265 = bits(_T_1264, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_239 of rvclkhdr_333 @[el2_lib.scala 508:23] + inst rvclkhdr_239 of rvclkhdr_333 @[lib.scala 368:23] rvclkhdr_239.clock <= clock rvclkhdr_239.reset <= reset - rvclkhdr_239.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_239.io.en <= _T_1265 @[el2_lib.scala 511:17] - rvclkhdr_239.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_229 : UInt, rvclkhdr_239.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_229 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_239.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_239.io.en <= _T_1265 @[lib.scala 371:17] + rvclkhdr_239.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_229 : UInt, rvclkhdr_239.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_229 <= btb_wr_data @[lib.scala 374:16] node _T_1266 = eq(btb_wr_addr, UInt<8>("h0e6")) @[ifu_bp_ctl.scala 415:95] node _T_1267 = and(_T_1266, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1268 = bits(_T_1267, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_240 of rvclkhdr_334 @[el2_lib.scala 508:23] + inst rvclkhdr_240 of rvclkhdr_334 @[lib.scala 368:23] rvclkhdr_240.clock <= clock rvclkhdr_240.reset <= reset - rvclkhdr_240.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_240.io.en <= _T_1268 @[el2_lib.scala 511:17] - rvclkhdr_240.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_230 : UInt, rvclkhdr_240.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_230 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_240.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_240.io.en <= _T_1268 @[lib.scala 371:17] + rvclkhdr_240.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_230 : UInt, rvclkhdr_240.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_230 <= btb_wr_data @[lib.scala 374:16] node _T_1269 = eq(btb_wr_addr, UInt<8>("h0e7")) @[ifu_bp_ctl.scala 415:95] node _T_1270 = and(_T_1269, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1271 = bits(_T_1270, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_241 of rvclkhdr_335 @[el2_lib.scala 508:23] + inst rvclkhdr_241 of rvclkhdr_335 @[lib.scala 368:23] rvclkhdr_241.clock <= clock rvclkhdr_241.reset <= reset - rvclkhdr_241.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_241.io.en <= _T_1271 @[el2_lib.scala 511:17] - rvclkhdr_241.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_231 : UInt, rvclkhdr_241.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_231 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_241.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_241.io.en <= _T_1271 @[lib.scala 371:17] + rvclkhdr_241.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_231 : UInt, rvclkhdr_241.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_231 <= btb_wr_data @[lib.scala 374:16] node _T_1272 = eq(btb_wr_addr, UInt<8>("h0e8")) @[ifu_bp_ctl.scala 415:95] node _T_1273 = and(_T_1272, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1274 = bits(_T_1273, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_242 of rvclkhdr_336 @[el2_lib.scala 508:23] + inst rvclkhdr_242 of rvclkhdr_336 @[lib.scala 368:23] rvclkhdr_242.clock <= clock rvclkhdr_242.reset <= reset - rvclkhdr_242.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_242.io.en <= _T_1274 @[el2_lib.scala 511:17] - rvclkhdr_242.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_232 : UInt, rvclkhdr_242.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_232 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_242.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_242.io.en <= _T_1274 @[lib.scala 371:17] + rvclkhdr_242.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_232 : UInt, rvclkhdr_242.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_232 <= btb_wr_data @[lib.scala 374:16] node _T_1275 = eq(btb_wr_addr, UInt<8>("h0e9")) @[ifu_bp_ctl.scala 415:95] node _T_1276 = and(_T_1275, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1277 = bits(_T_1276, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_243 of rvclkhdr_337 @[el2_lib.scala 508:23] + inst rvclkhdr_243 of rvclkhdr_337 @[lib.scala 368:23] rvclkhdr_243.clock <= clock rvclkhdr_243.reset <= reset - rvclkhdr_243.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_243.io.en <= _T_1277 @[el2_lib.scala 511:17] - rvclkhdr_243.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_233 : UInt, rvclkhdr_243.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_233 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_243.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_243.io.en <= _T_1277 @[lib.scala 371:17] + rvclkhdr_243.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_233 : UInt, rvclkhdr_243.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_233 <= btb_wr_data @[lib.scala 374:16] node _T_1278 = eq(btb_wr_addr, UInt<8>("h0ea")) @[ifu_bp_ctl.scala 415:95] node _T_1279 = and(_T_1278, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1280 = bits(_T_1279, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_244 of rvclkhdr_338 @[el2_lib.scala 508:23] + inst rvclkhdr_244 of rvclkhdr_338 @[lib.scala 368:23] rvclkhdr_244.clock <= clock rvclkhdr_244.reset <= reset - rvclkhdr_244.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_244.io.en <= _T_1280 @[el2_lib.scala 511:17] - rvclkhdr_244.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_234 : UInt, rvclkhdr_244.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_234 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_244.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_244.io.en <= _T_1280 @[lib.scala 371:17] + rvclkhdr_244.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_234 : UInt, rvclkhdr_244.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_234 <= btb_wr_data @[lib.scala 374:16] node _T_1281 = eq(btb_wr_addr, UInt<8>("h0eb")) @[ifu_bp_ctl.scala 415:95] node _T_1282 = and(_T_1281, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1283 = bits(_T_1282, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_245 of rvclkhdr_339 @[el2_lib.scala 508:23] + inst rvclkhdr_245 of rvclkhdr_339 @[lib.scala 368:23] rvclkhdr_245.clock <= clock rvclkhdr_245.reset <= reset - rvclkhdr_245.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_245.io.en <= _T_1283 @[el2_lib.scala 511:17] - rvclkhdr_245.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_235 : UInt, rvclkhdr_245.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_235 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_245.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_245.io.en <= _T_1283 @[lib.scala 371:17] + rvclkhdr_245.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_235 : UInt, rvclkhdr_245.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_235 <= btb_wr_data @[lib.scala 374:16] node _T_1284 = eq(btb_wr_addr, UInt<8>("h0ec")) @[ifu_bp_ctl.scala 415:95] node _T_1285 = and(_T_1284, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1286 = bits(_T_1285, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_246 of rvclkhdr_340 @[el2_lib.scala 508:23] + inst rvclkhdr_246 of rvclkhdr_340 @[lib.scala 368:23] rvclkhdr_246.clock <= clock rvclkhdr_246.reset <= reset - rvclkhdr_246.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_246.io.en <= _T_1286 @[el2_lib.scala 511:17] - rvclkhdr_246.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_236 : UInt, rvclkhdr_246.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_236 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_246.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_246.io.en <= _T_1286 @[lib.scala 371:17] + rvclkhdr_246.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_236 : UInt, rvclkhdr_246.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_236 <= btb_wr_data @[lib.scala 374:16] node _T_1287 = eq(btb_wr_addr, UInt<8>("h0ed")) @[ifu_bp_ctl.scala 415:95] node _T_1288 = and(_T_1287, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1289 = bits(_T_1288, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_247 of rvclkhdr_341 @[el2_lib.scala 508:23] + inst rvclkhdr_247 of rvclkhdr_341 @[lib.scala 368:23] rvclkhdr_247.clock <= clock rvclkhdr_247.reset <= reset - rvclkhdr_247.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_247.io.en <= _T_1289 @[el2_lib.scala 511:17] - rvclkhdr_247.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_237 : UInt, rvclkhdr_247.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_237 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_247.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_247.io.en <= _T_1289 @[lib.scala 371:17] + rvclkhdr_247.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_237 : UInt, rvclkhdr_247.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_237 <= btb_wr_data @[lib.scala 374:16] node _T_1290 = eq(btb_wr_addr, UInt<8>("h0ee")) @[ifu_bp_ctl.scala 415:95] node _T_1291 = and(_T_1290, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1292 = bits(_T_1291, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_248 of rvclkhdr_342 @[el2_lib.scala 508:23] + inst rvclkhdr_248 of rvclkhdr_342 @[lib.scala 368:23] rvclkhdr_248.clock <= clock rvclkhdr_248.reset <= reset - rvclkhdr_248.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_248.io.en <= _T_1292 @[el2_lib.scala 511:17] - rvclkhdr_248.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_238 : UInt, rvclkhdr_248.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_238 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_248.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_248.io.en <= _T_1292 @[lib.scala 371:17] + rvclkhdr_248.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_238 : UInt, rvclkhdr_248.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_238 <= btb_wr_data @[lib.scala 374:16] node _T_1293 = eq(btb_wr_addr, UInt<8>("h0ef")) @[ifu_bp_ctl.scala 415:95] node _T_1294 = and(_T_1293, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1295 = bits(_T_1294, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_249 of rvclkhdr_343 @[el2_lib.scala 508:23] + inst rvclkhdr_249 of rvclkhdr_343 @[lib.scala 368:23] rvclkhdr_249.clock <= clock rvclkhdr_249.reset <= reset - rvclkhdr_249.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_249.io.en <= _T_1295 @[el2_lib.scala 511:17] - rvclkhdr_249.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_239 : UInt, rvclkhdr_249.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_239 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_249.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_249.io.en <= _T_1295 @[lib.scala 371:17] + rvclkhdr_249.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_239 : UInt, rvclkhdr_249.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_239 <= btb_wr_data @[lib.scala 374:16] node _T_1296 = eq(btb_wr_addr, UInt<8>("h0f0")) @[ifu_bp_ctl.scala 415:95] node _T_1297 = and(_T_1296, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1298 = bits(_T_1297, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_250 of rvclkhdr_344 @[el2_lib.scala 508:23] + inst rvclkhdr_250 of rvclkhdr_344 @[lib.scala 368:23] rvclkhdr_250.clock <= clock rvclkhdr_250.reset <= reset - rvclkhdr_250.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_250.io.en <= _T_1298 @[el2_lib.scala 511:17] - rvclkhdr_250.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_240 : UInt, rvclkhdr_250.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_240 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_250.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_250.io.en <= _T_1298 @[lib.scala 371:17] + rvclkhdr_250.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_240 : UInt, rvclkhdr_250.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_240 <= btb_wr_data @[lib.scala 374:16] node _T_1299 = eq(btb_wr_addr, UInt<8>("h0f1")) @[ifu_bp_ctl.scala 415:95] node _T_1300 = and(_T_1299, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1301 = bits(_T_1300, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_251 of rvclkhdr_345 @[el2_lib.scala 508:23] + inst rvclkhdr_251 of rvclkhdr_345 @[lib.scala 368:23] rvclkhdr_251.clock <= clock rvclkhdr_251.reset <= reset - rvclkhdr_251.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_251.io.en <= _T_1301 @[el2_lib.scala 511:17] - rvclkhdr_251.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_241 : UInt, rvclkhdr_251.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_241 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_251.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_251.io.en <= _T_1301 @[lib.scala 371:17] + rvclkhdr_251.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_241 : UInt, rvclkhdr_251.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_241 <= btb_wr_data @[lib.scala 374:16] node _T_1302 = eq(btb_wr_addr, UInt<8>("h0f2")) @[ifu_bp_ctl.scala 415:95] node _T_1303 = and(_T_1302, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1304 = bits(_T_1303, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_252 of rvclkhdr_346 @[el2_lib.scala 508:23] + inst rvclkhdr_252 of rvclkhdr_346 @[lib.scala 368:23] rvclkhdr_252.clock <= clock rvclkhdr_252.reset <= reset - rvclkhdr_252.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_252.io.en <= _T_1304 @[el2_lib.scala 511:17] - rvclkhdr_252.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_242 : UInt, rvclkhdr_252.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_242 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_252.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_252.io.en <= _T_1304 @[lib.scala 371:17] + rvclkhdr_252.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_242 : UInt, rvclkhdr_252.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_242 <= btb_wr_data @[lib.scala 374:16] node _T_1305 = eq(btb_wr_addr, UInt<8>("h0f3")) @[ifu_bp_ctl.scala 415:95] node _T_1306 = and(_T_1305, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1307 = bits(_T_1306, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_253 of rvclkhdr_347 @[el2_lib.scala 508:23] + inst rvclkhdr_253 of rvclkhdr_347 @[lib.scala 368:23] rvclkhdr_253.clock <= clock rvclkhdr_253.reset <= reset - rvclkhdr_253.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_253.io.en <= _T_1307 @[el2_lib.scala 511:17] - rvclkhdr_253.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_243 : UInt, rvclkhdr_253.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_243 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_253.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_253.io.en <= _T_1307 @[lib.scala 371:17] + rvclkhdr_253.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_243 : UInt, rvclkhdr_253.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_243 <= btb_wr_data @[lib.scala 374:16] node _T_1308 = eq(btb_wr_addr, UInt<8>("h0f4")) @[ifu_bp_ctl.scala 415:95] node _T_1309 = and(_T_1308, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1310 = bits(_T_1309, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_254 of rvclkhdr_348 @[el2_lib.scala 508:23] + inst rvclkhdr_254 of rvclkhdr_348 @[lib.scala 368:23] rvclkhdr_254.clock <= clock rvclkhdr_254.reset <= reset - rvclkhdr_254.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_254.io.en <= _T_1310 @[el2_lib.scala 511:17] - rvclkhdr_254.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_244 : UInt, rvclkhdr_254.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_244 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_254.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_254.io.en <= _T_1310 @[lib.scala 371:17] + rvclkhdr_254.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_244 : UInt, rvclkhdr_254.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_244 <= btb_wr_data @[lib.scala 374:16] node _T_1311 = eq(btb_wr_addr, UInt<8>("h0f5")) @[ifu_bp_ctl.scala 415:95] node _T_1312 = and(_T_1311, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1313 = bits(_T_1312, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_255 of rvclkhdr_349 @[el2_lib.scala 508:23] + inst rvclkhdr_255 of rvclkhdr_349 @[lib.scala 368:23] rvclkhdr_255.clock <= clock rvclkhdr_255.reset <= reset - rvclkhdr_255.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_255.io.en <= _T_1313 @[el2_lib.scala 511:17] - rvclkhdr_255.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_245 : UInt, rvclkhdr_255.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_245 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_255.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_255.io.en <= _T_1313 @[lib.scala 371:17] + rvclkhdr_255.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_245 : UInt, rvclkhdr_255.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_245 <= btb_wr_data @[lib.scala 374:16] node _T_1314 = eq(btb_wr_addr, UInt<8>("h0f6")) @[ifu_bp_ctl.scala 415:95] node _T_1315 = and(_T_1314, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1316 = bits(_T_1315, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_256 of rvclkhdr_350 @[el2_lib.scala 508:23] + inst rvclkhdr_256 of rvclkhdr_350 @[lib.scala 368:23] rvclkhdr_256.clock <= clock rvclkhdr_256.reset <= reset - rvclkhdr_256.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_256.io.en <= _T_1316 @[el2_lib.scala 511:17] - rvclkhdr_256.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_246 : UInt, rvclkhdr_256.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_246 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_256.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_256.io.en <= _T_1316 @[lib.scala 371:17] + rvclkhdr_256.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_246 : UInt, rvclkhdr_256.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_246 <= btb_wr_data @[lib.scala 374:16] node _T_1317 = eq(btb_wr_addr, UInt<8>("h0f7")) @[ifu_bp_ctl.scala 415:95] node _T_1318 = and(_T_1317, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1319 = bits(_T_1318, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_257 of rvclkhdr_351 @[el2_lib.scala 508:23] + inst rvclkhdr_257 of rvclkhdr_351 @[lib.scala 368:23] rvclkhdr_257.clock <= clock rvclkhdr_257.reset <= reset - rvclkhdr_257.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_257.io.en <= _T_1319 @[el2_lib.scala 511:17] - rvclkhdr_257.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_247 : UInt, rvclkhdr_257.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_247 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_257.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_257.io.en <= _T_1319 @[lib.scala 371:17] + rvclkhdr_257.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_247 : UInt, rvclkhdr_257.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_247 <= btb_wr_data @[lib.scala 374:16] node _T_1320 = eq(btb_wr_addr, UInt<8>("h0f8")) @[ifu_bp_ctl.scala 415:95] node _T_1321 = and(_T_1320, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1322 = bits(_T_1321, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_258 of rvclkhdr_352 @[el2_lib.scala 508:23] + inst rvclkhdr_258 of rvclkhdr_352 @[lib.scala 368:23] rvclkhdr_258.clock <= clock rvclkhdr_258.reset <= reset - rvclkhdr_258.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_258.io.en <= _T_1322 @[el2_lib.scala 511:17] - rvclkhdr_258.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_248 : UInt, rvclkhdr_258.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_248 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_258.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_258.io.en <= _T_1322 @[lib.scala 371:17] + rvclkhdr_258.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_248 : UInt, rvclkhdr_258.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_248 <= btb_wr_data @[lib.scala 374:16] node _T_1323 = eq(btb_wr_addr, UInt<8>("h0f9")) @[ifu_bp_ctl.scala 415:95] node _T_1324 = and(_T_1323, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1325 = bits(_T_1324, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_259 of rvclkhdr_353 @[el2_lib.scala 508:23] + inst rvclkhdr_259 of rvclkhdr_353 @[lib.scala 368:23] rvclkhdr_259.clock <= clock rvclkhdr_259.reset <= reset - rvclkhdr_259.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_259.io.en <= _T_1325 @[el2_lib.scala 511:17] - rvclkhdr_259.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_249 : UInt, rvclkhdr_259.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_249 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_259.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_259.io.en <= _T_1325 @[lib.scala 371:17] + rvclkhdr_259.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_249 : UInt, rvclkhdr_259.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_249 <= btb_wr_data @[lib.scala 374:16] node _T_1326 = eq(btb_wr_addr, UInt<8>("h0fa")) @[ifu_bp_ctl.scala 415:95] node _T_1327 = and(_T_1326, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1328 = bits(_T_1327, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_260 of rvclkhdr_354 @[el2_lib.scala 508:23] + inst rvclkhdr_260 of rvclkhdr_354 @[lib.scala 368:23] rvclkhdr_260.clock <= clock rvclkhdr_260.reset <= reset - rvclkhdr_260.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_260.io.en <= _T_1328 @[el2_lib.scala 511:17] - rvclkhdr_260.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_250 : UInt, rvclkhdr_260.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_250 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_260.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_260.io.en <= _T_1328 @[lib.scala 371:17] + rvclkhdr_260.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_250 : UInt, rvclkhdr_260.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_250 <= btb_wr_data @[lib.scala 374:16] node _T_1329 = eq(btb_wr_addr, UInt<8>("h0fb")) @[ifu_bp_ctl.scala 415:95] node _T_1330 = and(_T_1329, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1331 = bits(_T_1330, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_261 of rvclkhdr_355 @[el2_lib.scala 508:23] + inst rvclkhdr_261 of rvclkhdr_355 @[lib.scala 368:23] rvclkhdr_261.clock <= clock rvclkhdr_261.reset <= reset - rvclkhdr_261.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_261.io.en <= _T_1331 @[el2_lib.scala 511:17] - rvclkhdr_261.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_251 : UInt, rvclkhdr_261.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_251 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_261.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_261.io.en <= _T_1331 @[lib.scala 371:17] + rvclkhdr_261.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_251 : UInt, rvclkhdr_261.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_251 <= btb_wr_data @[lib.scala 374:16] node _T_1332 = eq(btb_wr_addr, UInt<8>("h0fc")) @[ifu_bp_ctl.scala 415:95] node _T_1333 = and(_T_1332, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1334 = bits(_T_1333, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_262 of rvclkhdr_356 @[el2_lib.scala 508:23] + inst rvclkhdr_262 of rvclkhdr_356 @[lib.scala 368:23] rvclkhdr_262.clock <= clock rvclkhdr_262.reset <= reset - rvclkhdr_262.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_262.io.en <= _T_1334 @[el2_lib.scala 511:17] - rvclkhdr_262.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_252 : UInt, rvclkhdr_262.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_252 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_262.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_262.io.en <= _T_1334 @[lib.scala 371:17] + rvclkhdr_262.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_252 : UInt, rvclkhdr_262.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_252 <= btb_wr_data @[lib.scala 374:16] node _T_1335 = eq(btb_wr_addr, UInt<8>("h0fd")) @[ifu_bp_ctl.scala 415:95] node _T_1336 = and(_T_1335, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1337 = bits(_T_1336, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_263 of rvclkhdr_357 @[el2_lib.scala 508:23] + inst rvclkhdr_263 of rvclkhdr_357 @[lib.scala 368:23] rvclkhdr_263.clock <= clock rvclkhdr_263.reset <= reset - rvclkhdr_263.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_263.io.en <= _T_1337 @[el2_lib.scala 511:17] - rvclkhdr_263.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_253 : UInt, rvclkhdr_263.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_253 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_263.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_263.io.en <= _T_1337 @[lib.scala 371:17] + rvclkhdr_263.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_253 : UInt, rvclkhdr_263.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_253 <= btb_wr_data @[lib.scala 374:16] node _T_1338 = eq(btb_wr_addr, UInt<8>("h0fe")) @[ifu_bp_ctl.scala 415:95] node _T_1339 = and(_T_1338, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1340 = bits(_T_1339, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_264 of rvclkhdr_358 @[el2_lib.scala 508:23] + inst rvclkhdr_264 of rvclkhdr_358 @[lib.scala 368:23] rvclkhdr_264.clock <= clock rvclkhdr_264.reset <= reset - rvclkhdr_264.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_264.io.en <= _T_1340 @[el2_lib.scala 511:17] - rvclkhdr_264.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_254 : UInt, rvclkhdr_264.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_254 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_264.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_264.io.en <= _T_1340 @[lib.scala 371:17] + rvclkhdr_264.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_254 : UInt, rvclkhdr_264.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_254 <= btb_wr_data @[lib.scala 374:16] node _T_1341 = eq(btb_wr_addr, UInt<8>("h0ff")) @[ifu_bp_ctl.scala 415:95] node _T_1342 = and(_T_1341, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] node _T_1343 = bits(_T_1342, 0, 0) @[ifu_bp_ctl.scala 415:121] - inst rvclkhdr_265 of rvclkhdr_359 @[el2_lib.scala 508:23] + inst rvclkhdr_265 of rvclkhdr_359 @[lib.scala 368:23] rvclkhdr_265.clock <= clock rvclkhdr_265.reset <= reset - rvclkhdr_265.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_265.io.en <= _T_1343 @[el2_lib.scala 511:17] - rvclkhdr_265.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way0_out_255 : UInt, rvclkhdr_265.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way0_out_255 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_265.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_265.io.en <= _T_1343 @[lib.scala 371:17] + rvclkhdr_265.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way0_out_255 : UInt, rvclkhdr_265.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way0_out_255 <= btb_wr_data @[lib.scala 374:16] node _T_1344 = eq(btb_wr_addr, UInt<1>("h00")) @[ifu_bp_ctl.scala 416:95] node _T_1345 = and(_T_1344, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1346 = bits(_T_1345, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_266 of rvclkhdr_360 @[el2_lib.scala 508:23] + inst rvclkhdr_266 of rvclkhdr_360 @[lib.scala 368:23] rvclkhdr_266.clock <= clock rvclkhdr_266.reset <= reset - rvclkhdr_266.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_266.io.en <= _T_1346 @[el2_lib.scala 511:17] - rvclkhdr_266.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_0 : UInt, rvclkhdr_266.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_0 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_266.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_266.io.en <= _T_1346 @[lib.scala 371:17] + rvclkhdr_266.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_0 : UInt, rvclkhdr_266.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_0 <= btb_wr_data @[lib.scala 374:16] node _T_1347 = eq(btb_wr_addr, UInt<1>("h01")) @[ifu_bp_ctl.scala 416:95] node _T_1348 = and(_T_1347, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1349 = bits(_T_1348, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_267 of rvclkhdr_361 @[el2_lib.scala 508:23] + inst rvclkhdr_267 of rvclkhdr_361 @[lib.scala 368:23] rvclkhdr_267.clock <= clock rvclkhdr_267.reset <= reset - rvclkhdr_267.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_267.io.en <= _T_1349 @[el2_lib.scala 511:17] - rvclkhdr_267.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_1 : UInt, rvclkhdr_267.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_1 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_267.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_267.io.en <= _T_1349 @[lib.scala 371:17] + rvclkhdr_267.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_1 : UInt, rvclkhdr_267.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_1 <= btb_wr_data @[lib.scala 374:16] node _T_1350 = eq(btb_wr_addr, UInt<2>("h02")) @[ifu_bp_ctl.scala 416:95] node _T_1351 = and(_T_1350, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1352 = bits(_T_1351, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_268 of rvclkhdr_362 @[el2_lib.scala 508:23] + inst rvclkhdr_268 of rvclkhdr_362 @[lib.scala 368:23] rvclkhdr_268.clock <= clock rvclkhdr_268.reset <= reset - rvclkhdr_268.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_268.io.en <= _T_1352 @[el2_lib.scala 511:17] - rvclkhdr_268.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_2 : UInt, rvclkhdr_268.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_2 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_268.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_268.io.en <= _T_1352 @[lib.scala 371:17] + rvclkhdr_268.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_2 : UInt, rvclkhdr_268.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_2 <= btb_wr_data @[lib.scala 374:16] node _T_1353 = eq(btb_wr_addr, UInt<2>("h03")) @[ifu_bp_ctl.scala 416:95] node _T_1354 = and(_T_1353, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1355 = bits(_T_1354, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_269 of rvclkhdr_363 @[el2_lib.scala 508:23] + inst rvclkhdr_269 of rvclkhdr_363 @[lib.scala 368:23] rvclkhdr_269.clock <= clock rvclkhdr_269.reset <= reset - rvclkhdr_269.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_269.io.en <= _T_1355 @[el2_lib.scala 511:17] - rvclkhdr_269.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_3 : UInt, rvclkhdr_269.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_3 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_269.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_269.io.en <= _T_1355 @[lib.scala 371:17] + rvclkhdr_269.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_3 : UInt, rvclkhdr_269.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_3 <= btb_wr_data @[lib.scala 374:16] node _T_1356 = eq(btb_wr_addr, UInt<3>("h04")) @[ifu_bp_ctl.scala 416:95] node _T_1357 = and(_T_1356, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1358 = bits(_T_1357, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_270 of rvclkhdr_364 @[el2_lib.scala 508:23] + inst rvclkhdr_270 of rvclkhdr_364 @[lib.scala 368:23] rvclkhdr_270.clock <= clock rvclkhdr_270.reset <= reset - rvclkhdr_270.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_270.io.en <= _T_1358 @[el2_lib.scala 511:17] - rvclkhdr_270.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_4 : UInt, rvclkhdr_270.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_4 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_270.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_270.io.en <= _T_1358 @[lib.scala 371:17] + rvclkhdr_270.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_4 : UInt, rvclkhdr_270.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_4 <= btb_wr_data @[lib.scala 374:16] node _T_1359 = eq(btb_wr_addr, UInt<3>("h05")) @[ifu_bp_ctl.scala 416:95] node _T_1360 = and(_T_1359, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1361 = bits(_T_1360, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_271 of rvclkhdr_365 @[el2_lib.scala 508:23] + inst rvclkhdr_271 of rvclkhdr_365 @[lib.scala 368:23] rvclkhdr_271.clock <= clock rvclkhdr_271.reset <= reset - rvclkhdr_271.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_271.io.en <= _T_1361 @[el2_lib.scala 511:17] - rvclkhdr_271.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_5 : UInt, rvclkhdr_271.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_5 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_271.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_271.io.en <= _T_1361 @[lib.scala 371:17] + rvclkhdr_271.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_5 : UInt, rvclkhdr_271.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_5 <= btb_wr_data @[lib.scala 374:16] node _T_1362 = eq(btb_wr_addr, UInt<3>("h06")) @[ifu_bp_ctl.scala 416:95] node _T_1363 = and(_T_1362, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1364 = bits(_T_1363, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_272 of rvclkhdr_366 @[el2_lib.scala 508:23] + inst rvclkhdr_272 of rvclkhdr_366 @[lib.scala 368:23] rvclkhdr_272.clock <= clock rvclkhdr_272.reset <= reset - rvclkhdr_272.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_272.io.en <= _T_1364 @[el2_lib.scala 511:17] - rvclkhdr_272.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_6 : UInt, rvclkhdr_272.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_6 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_272.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_272.io.en <= _T_1364 @[lib.scala 371:17] + rvclkhdr_272.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_6 : UInt, rvclkhdr_272.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_6 <= btb_wr_data @[lib.scala 374:16] node _T_1365 = eq(btb_wr_addr, UInt<3>("h07")) @[ifu_bp_ctl.scala 416:95] node _T_1366 = and(_T_1365, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1367 = bits(_T_1366, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_273 of rvclkhdr_367 @[el2_lib.scala 508:23] + inst rvclkhdr_273 of rvclkhdr_367 @[lib.scala 368:23] rvclkhdr_273.clock <= clock rvclkhdr_273.reset <= reset - rvclkhdr_273.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_273.io.en <= _T_1367 @[el2_lib.scala 511:17] - rvclkhdr_273.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_7 : UInt, rvclkhdr_273.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_7 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_273.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_273.io.en <= _T_1367 @[lib.scala 371:17] + rvclkhdr_273.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_7 : UInt, rvclkhdr_273.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_7 <= btb_wr_data @[lib.scala 374:16] node _T_1368 = eq(btb_wr_addr, UInt<4>("h08")) @[ifu_bp_ctl.scala 416:95] node _T_1369 = and(_T_1368, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1370 = bits(_T_1369, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_274 of rvclkhdr_368 @[el2_lib.scala 508:23] + inst rvclkhdr_274 of rvclkhdr_368 @[lib.scala 368:23] rvclkhdr_274.clock <= clock rvclkhdr_274.reset <= reset - rvclkhdr_274.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_274.io.en <= _T_1370 @[el2_lib.scala 511:17] - rvclkhdr_274.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_8 : UInt, rvclkhdr_274.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_8 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_274.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_274.io.en <= _T_1370 @[lib.scala 371:17] + rvclkhdr_274.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_8 : UInt, rvclkhdr_274.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_8 <= btb_wr_data @[lib.scala 374:16] node _T_1371 = eq(btb_wr_addr, UInt<4>("h09")) @[ifu_bp_ctl.scala 416:95] node _T_1372 = and(_T_1371, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1373 = bits(_T_1372, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_275 of rvclkhdr_369 @[el2_lib.scala 508:23] + inst rvclkhdr_275 of rvclkhdr_369 @[lib.scala 368:23] rvclkhdr_275.clock <= clock rvclkhdr_275.reset <= reset - rvclkhdr_275.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_275.io.en <= _T_1373 @[el2_lib.scala 511:17] - rvclkhdr_275.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_9 : UInt, rvclkhdr_275.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_9 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_275.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_275.io.en <= _T_1373 @[lib.scala 371:17] + rvclkhdr_275.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_9 : UInt, rvclkhdr_275.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_9 <= btb_wr_data @[lib.scala 374:16] node _T_1374 = eq(btb_wr_addr, UInt<4>("h0a")) @[ifu_bp_ctl.scala 416:95] node _T_1375 = and(_T_1374, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1376 = bits(_T_1375, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_276 of rvclkhdr_370 @[el2_lib.scala 508:23] + inst rvclkhdr_276 of rvclkhdr_370 @[lib.scala 368:23] rvclkhdr_276.clock <= clock rvclkhdr_276.reset <= reset - rvclkhdr_276.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_276.io.en <= _T_1376 @[el2_lib.scala 511:17] - rvclkhdr_276.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_10 : UInt, rvclkhdr_276.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_10 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_276.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_276.io.en <= _T_1376 @[lib.scala 371:17] + rvclkhdr_276.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_10 : UInt, rvclkhdr_276.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_10 <= btb_wr_data @[lib.scala 374:16] node _T_1377 = eq(btb_wr_addr, UInt<4>("h0b")) @[ifu_bp_ctl.scala 416:95] node _T_1378 = and(_T_1377, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1379 = bits(_T_1378, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_277 of rvclkhdr_371 @[el2_lib.scala 508:23] + inst rvclkhdr_277 of rvclkhdr_371 @[lib.scala 368:23] rvclkhdr_277.clock <= clock rvclkhdr_277.reset <= reset - rvclkhdr_277.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_277.io.en <= _T_1379 @[el2_lib.scala 511:17] - rvclkhdr_277.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_11 : UInt, rvclkhdr_277.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_11 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_277.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_277.io.en <= _T_1379 @[lib.scala 371:17] + rvclkhdr_277.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_11 : UInt, rvclkhdr_277.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_11 <= btb_wr_data @[lib.scala 374:16] node _T_1380 = eq(btb_wr_addr, UInt<4>("h0c")) @[ifu_bp_ctl.scala 416:95] node _T_1381 = and(_T_1380, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1382 = bits(_T_1381, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_278 of rvclkhdr_372 @[el2_lib.scala 508:23] + inst rvclkhdr_278 of rvclkhdr_372 @[lib.scala 368:23] rvclkhdr_278.clock <= clock rvclkhdr_278.reset <= reset - rvclkhdr_278.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_278.io.en <= _T_1382 @[el2_lib.scala 511:17] - rvclkhdr_278.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_12 : UInt, rvclkhdr_278.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_12 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_278.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_278.io.en <= _T_1382 @[lib.scala 371:17] + rvclkhdr_278.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_12 : UInt, rvclkhdr_278.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_12 <= btb_wr_data @[lib.scala 374:16] node _T_1383 = eq(btb_wr_addr, UInt<4>("h0d")) @[ifu_bp_ctl.scala 416:95] node _T_1384 = and(_T_1383, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1385 = bits(_T_1384, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_279 of rvclkhdr_373 @[el2_lib.scala 508:23] + inst rvclkhdr_279 of rvclkhdr_373 @[lib.scala 368:23] rvclkhdr_279.clock <= clock rvclkhdr_279.reset <= reset - rvclkhdr_279.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_279.io.en <= _T_1385 @[el2_lib.scala 511:17] - rvclkhdr_279.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_13 : UInt, rvclkhdr_279.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_13 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_279.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_279.io.en <= _T_1385 @[lib.scala 371:17] + rvclkhdr_279.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_13 : UInt, rvclkhdr_279.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_13 <= btb_wr_data @[lib.scala 374:16] node _T_1386 = eq(btb_wr_addr, UInt<4>("h0e")) @[ifu_bp_ctl.scala 416:95] node _T_1387 = and(_T_1386, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1388 = bits(_T_1387, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_280 of rvclkhdr_374 @[el2_lib.scala 508:23] + inst rvclkhdr_280 of rvclkhdr_374 @[lib.scala 368:23] rvclkhdr_280.clock <= clock rvclkhdr_280.reset <= reset - rvclkhdr_280.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_280.io.en <= _T_1388 @[el2_lib.scala 511:17] - rvclkhdr_280.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_14 : UInt, rvclkhdr_280.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_14 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_280.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_280.io.en <= _T_1388 @[lib.scala 371:17] + rvclkhdr_280.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_14 : UInt, rvclkhdr_280.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_14 <= btb_wr_data @[lib.scala 374:16] node _T_1389 = eq(btb_wr_addr, UInt<4>("h0f")) @[ifu_bp_ctl.scala 416:95] node _T_1390 = and(_T_1389, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1391 = bits(_T_1390, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_281 of rvclkhdr_375 @[el2_lib.scala 508:23] + inst rvclkhdr_281 of rvclkhdr_375 @[lib.scala 368:23] rvclkhdr_281.clock <= clock rvclkhdr_281.reset <= reset - rvclkhdr_281.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_281.io.en <= _T_1391 @[el2_lib.scala 511:17] - rvclkhdr_281.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_15 : UInt, rvclkhdr_281.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_15 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_281.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_281.io.en <= _T_1391 @[lib.scala 371:17] + rvclkhdr_281.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_15 : UInt, rvclkhdr_281.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_15 <= btb_wr_data @[lib.scala 374:16] node _T_1392 = eq(btb_wr_addr, UInt<5>("h010")) @[ifu_bp_ctl.scala 416:95] node _T_1393 = and(_T_1392, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1394 = bits(_T_1393, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_282 of rvclkhdr_376 @[el2_lib.scala 508:23] + inst rvclkhdr_282 of rvclkhdr_376 @[lib.scala 368:23] rvclkhdr_282.clock <= clock rvclkhdr_282.reset <= reset - rvclkhdr_282.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_282.io.en <= _T_1394 @[el2_lib.scala 511:17] - rvclkhdr_282.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_16 : UInt, rvclkhdr_282.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_16 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_282.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_282.io.en <= _T_1394 @[lib.scala 371:17] + rvclkhdr_282.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_16 : UInt, rvclkhdr_282.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_16 <= btb_wr_data @[lib.scala 374:16] node _T_1395 = eq(btb_wr_addr, UInt<5>("h011")) @[ifu_bp_ctl.scala 416:95] node _T_1396 = and(_T_1395, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1397 = bits(_T_1396, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_283 of rvclkhdr_377 @[el2_lib.scala 508:23] + inst rvclkhdr_283 of rvclkhdr_377 @[lib.scala 368:23] rvclkhdr_283.clock <= clock rvclkhdr_283.reset <= reset - rvclkhdr_283.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_283.io.en <= _T_1397 @[el2_lib.scala 511:17] - rvclkhdr_283.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_17 : UInt, rvclkhdr_283.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_17 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_283.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_283.io.en <= _T_1397 @[lib.scala 371:17] + rvclkhdr_283.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_17 : UInt, rvclkhdr_283.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_17 <= btb_wr_data @[lib.scala 374:16] node _T_1398 = eq(btb_wr_addr, UInt<5>("h012")) @[ifu_bp_ctl.scala 416:95] node _T_1399 = and(_T_1398, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1400 = bits(_T_1399, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_284 of rvclkhdr_378 @[el2_lib.scala 508:23] + inst rvclkhdr_284 of rvclkhdr_378 @[lib.scala 368:23] rvclkhdr_284.clock <= clock rvclkhdr_284.reset <= reset - rvclkhdr_284.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_284.io.en <= _T_1400 @[el2_lib.scala 511:17] - rvclkhdr_284.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_18 : UInt, rvclkhdr_284.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_18 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_284.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_284.io.en <= _T_1400 @[lib.scala 371:17] + rvclkhdr_284.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_18 : UInt, rvclkhdr_284.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_18 <= btb_wr_data @[lib.scala 374:16] node _T_1401 = eq(btb_wr_addr, UInt<5>("h013")) @[ifu_bp_ctl.scala 416:95] node _T_1402 = and(_T_1401, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1403 = bits(_T_1402, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_285 of rvclkhdr_379 @[el2_lib.scala 508:23] + inst rvclkhdr_285 of rvclkhdr_379 @[lib.scala 368:23] rvclkhdr_285.clock <= clock rvclkhdr_285.reset <= reset - rvclkhdr_285.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_285.io.en <= _T_1403 @[el2_lib.scala 511:17] - rvclkhdr_285.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_19 : UInt, rvclkhdr_285.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_19 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_285.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_285.io.en <= _T_1403 @[lib.scala 371:17] + rvclkhdr_285.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_19 : UInt, rvclkhdr_285.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_19 <= btb_wr_data @[lib.scala 374:16] node _T_1404 = eq(btb_wr_addr, UInt<5>("h014")) @[ifu_bp_ctl.scala 416:95] node _T_1405 = and(_T_1404, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1406 = bits(_T_1405, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_286 of rvclkhdr_380 @[el2_lib.scala 508:23] + inst rvclkhdr_286 of rvclkhdr_380 @[lib.scala 368:23] rvclkhdr_286.clock <= clock rvclkhdr_286.reset <= reset - rvclkhdr_286.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_286.io.en <= _T_1406 @[el2_lib.scala 511:17] - rvclkhdr_286.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_20 : UInt, rvclkhdr_286.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_20 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_286.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_286.io.en <= _T_1406 @[lib.scala 371:17] + rvclkhdr_286.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_20 : UInt, rvclkhdr_286.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_20 <= btb_wr_data @[lib.scala 374:16] node _T_1407 = eq(btb_wr_addr, UInt<5>("h015")) @[ifu_bp_ctl.scala 416:95] node _T_1408 = and(_T_1407, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1409 = bits(_T_1408, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_287 of rvclkhdr_381 @[el2_lib.scala 508:23] + inst rvclkhdr_287 of rvclkhdr_381 @[lib.scala 368:23] rvclkhdr_287.clock <= clock rvclkhdr_287.reset <= reset - rvclkhdr_287.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_287.io.en <= _T_1409 @[el2_lib.scala 511:17] - rvclkhdr_287.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_21 : UInt, rvclkhdr_287.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_21 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_287.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_287.io.en <= _T_1409 @[lib.scala 371:17] + rvclkhdr_287.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_21 : UInt, rvclkhdr_287.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_21 <= btb_wr_data @[lib.scala 374:16] node _T_1410 = eq(btb_wr_addr, UInt<5>("h016")) @[ifu_bp_ctl.scala 416:95] node _T_1411 = and(_T_1410, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1412 = bits(_T_1411, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_288 of rvclkhdr_382 @[el2_lib.scala 508:23] + inst rvclkhdr_288 of rvclkhdr_382 @[lib.scala 368:23] rvclkhdr_288.clock <= clock rvclkhdr_288.reset <= reset - rvclkhdr_288.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_288.io.en <= _T_1412 @[el2_lib.scala 511:17] - rvclkhdr_288.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_22 : UInt, rvclkhdr_288.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_22 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_288.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_288.io.en <= _T_1412 @[lib.scala 371:17] + rvclkhdr_288.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_22 : UInt, rvclkhdr_288.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_22 <= btb_wr_data @[lib.scala 374:16] node _T_1413 = eq(btb_wr_addr, UInt<5>("h017")) @[ifu_bp_ctl.scala 416:95] node _T_1414 = and(_T_1413, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1415 = bits(_T_1414, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_289 of rvclkhdr_383 @[el2_lib.scala 508:23] + inst rvclkhdr_289 of rvclkhdr_383 @[lib.scala 368:23] rvclkhdr_289.clock <= clock rvclkhdr_289.reset <= reset - rvclkhdr_289.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_289.io.en <= _T_1415 @[el2_lib.scala 511:17] - rvclkhdr_289.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_23 : UInt, rvclkhdr_289.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_23 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_289.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_289.io.en <= _T_1415 @[lib.scala 371:17] + rvclkhdr_289.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_23 : UInt, rvclkhdr_289.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_23 <= btb_wr_data @[lib.scala 374:16] node _T_1416 = eq(btb_wr_addr, UInt<5>("h018")) @[ifu_bp_ctl.scala 416:95] node _T_1417 = and(_T_1416, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1418 = bits(_T_1417, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_290 of rvclkhdr_384 @[el2_lib.scala 508:23] + inst rvclkhdr_290 of rvclkhdr_384 @[lib.scala 368:23] rvclkhdr_290.clock <= clock rvclkhdr_290.reset <= reset - rvclkhdr_290.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_290.io.en <= _T_1418 @[el2_lib.scala 511:17] - rvclkhdr_290.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_24 : UInt, rvclkhdr_290.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_24 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_290.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_290.io.en <= _T_1418 @[lib.scala 371:17] + rvclkhdr_290.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_24 : UInt, rvclkhdr_290.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_24 <= btb_wr_data @[lib.scala 374:16] node _T_1419 = eq(btb_wr_addr, UInt<5>("h019")) @[ifu_bp_ctl.scala 416:95] node _T_1420 = and(_T_1419, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1421 = bits(_T_1420, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_291 of rvclkhdr_385 @[el2_lib.scala 508:23] + inst rvclkhdr_291 of rvclkhdr_385 @[lib.scala 368:23] rvclkhdr_291.clock <= clock rvclkhdr_291.reset <= reset - rvclkhdr_291.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_291.io.en <= _T_1421 @[el2_lib.scala 511:17] - rvclkhdr_291.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_25 : UInt, rvclkhdr_291.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_25 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_291.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_291.io.en <= _T_1421 @[lib.scala 371:17] + rvclkhdr_291.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_25 : UInt, rvclkhdr_291.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_25 <= btb_wr_data @[lib.scala 374:16] node _T_1422 = eq(btb_wr_addr, UInt<5>("h01a")) @[ifu_bp_ctl.scala 416:95] node _T_1423 = and(_T_1422, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1424 = bits(_T_1423, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_292 of rvclkhdr_386 @[el2_lib.scala 508:23] + inst rvclkhdr_292 of rvclkhdr_386 @[lib.scala 368:23] rvclkhdr_292.clock <= clock rvclkhdr_292.reset <= reset - rvclkhdr_292.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_292.io.en <= _T_1424 @[el2_lib.scala 511:17] - rvclkhdr_292.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_26 : UInt, rvclkhdr_292.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_26 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_292.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_292.io.en <= _T_1424 @[lib.scala 371:17] + rvclkhdr_292.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_26 : UInt, rvclkhdr_292.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_26 <= btb_wr_data @[lib.scala 374:16] node _T_1425 = eq(btb_wr_addr, UInt<5>("h01b")) @[ifu_bp_ctl.scala 416:95] node _T_1426 = and(_T_1425, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1427 = bits(_T_1426, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_293 of rvclkhdr_387 @[el2_lib.scala 508:23] + inst rvclkhdr_293 of rvclkhdr_387 @[lib.scala 368:23] rvclkhdr_293.clock <= clock rvclkhdr_293.reset <= reset - rvclkhdr_293.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_293.io.en <= _T_1427 @[el2_lib.scala 511:17] - rvclkhdr_293.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_27 : UInt, rvclkhdr_293.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_27 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_293.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_293.io.en <= _T_1427 @[lib.scala 371:17] + rvclkhdr_293.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_27 : UInt, rvclkhdr_293.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_27 <= btb_wr_data @[lib.scala 374:16] node _T_1428 = eq(btb_wr_addr, UInt<5>("h01c")) @[ifu_bp_ctl.scala 416:95] node _T_1429 = and(_T_1428, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1430 = bits(_T_1429, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_294 of rvclkhdr_388 @[el2_lib.scala 508:23] + inst rvclkhdr_294 of rvclkhdr_388 @[lib.scala 368:23] rvclkhdr_294.clock <= clock rvclkhdr_294.reset <= reset - rvclkhdr_294.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_294.io.en <= _T_1430 @[el2_lib.scala 511:17] - rvclkhdr_294.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_28 : UInt, rvclkhdr_294.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_28 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_294.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_294.io.en <= _T_1430 @[lib.scala 371:17] + rvclkhdr_294.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_28 : UInt, rvclkhdr_294.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_28 <= btb_wr_data @[lib.scala 374:16] node _T_1431 = eq(btb_wr_addr, UInt<5>("h01d")) @[ifu_bp_ctl.scala 416:95] node _T_1432 = and(_T_1431, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1433 = bits(_T_1432, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_295 of rvclkhdr_389 @[el2_lib.scala 508:23] + inst rvclkhdr_295 of rvclkhdr_389 @[lib.scala 368:23] rvclkhdr_295.clock <= clock rvclkhdr_295.reset <= reset - rvclkhdr_295.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_295.io.en <= _T_1433 @[el2_lib.scala 511:17] - rvclkhdr_295.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_29 : UInt, rvclkhdr_295.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_29 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_295.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_295.io.en <= _T_1433 @[lib.scala 371:17] + rvclkhdr_295.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_29 : UInt, rvclkhdr_295.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_29 <= btb_wr_data @[lib.scala 374:16] node _T_1434 = eq(btb_wr_addr, UInt<5>("h01e")) @[ifu_bp_ctl.scala 416:95] node _T_1435 = and(_T_1434, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1436 = bits(_T_1435, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_296 of rvclkhdr_390 @[el2_lib.scala 508:23] + inst rvclkhdr_296 of rvclkhdr_390 @[lib.scala 368:23] rvclkhdr_296.clock <= clock rvclkhdr_296.reset <= reset - rvclkhdr_296.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_296.io.en <= _T_1436 @[el2_lib.scala 511:17] - rvclkhdr_296.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_30 : UInt, rvclkhdr_296.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_30 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_296.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_296.io.en <= _T_1436 @[lib.scala 371:17] + rvclkhdr_296.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_30 : UInt, rvclkhdr_296.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_30 <= btb_wr_data @[lib.scala 374:16] node _T_1437 = eq(btb_wr_addr, UInt<5>("h01f")) @[ifu_bp_ctl.scala 416:95] node _T_1438 = and(_T_1437, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1439 = bits(_T_1438, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_297 of rvclkhdr_391 @[el2_lib.scala 508:23] + inst rvclkhdr_297 of rvclkhdr_391 @[lib.scala 368:23] rvclkhdr_297.clock <= clock rvclkhdr_297.reset <= reset - rvclkhdr_297.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_297.io.en <= _T_1439 @[el2_lib.scala 511:17] - rvclkhdr_297.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_31 : UInt, rvclkhdr_297.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_31 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_297.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_297.io.en <= _T_1439 @[lib.scala 371:17] + rvclkhdr_297.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_31 : UInt, rvclkhdr_297.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_31 <= btb_wr_data @[lib.scala 374:16] node _T_1440 = eq(btb_wr_addr, UInt<6>("h020")) @[ifu_bp_ctl.scala 416:95] node _T_1441 = and(_T_1440, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1442 = bits(_T_1441, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_298 of rvclkhdr_392 @[el2_lib.scala 508:23] + inst rvclkhdr_298 of rvclkhdr_392 @[lib.scala 368:23] rvclkhdr_298.clock <= clock rvclkhdr_298.reset <= reset - rvclkhdr_298.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_298.io.en <= _T_1442 @[el2_lib.scala 511:17] - rvclkhdr_298.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_32 : UInt, rvclkhdr_298.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_32 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_298.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_298.io.en <= _T_1442 @[lib.scala 371:17] + rvclkhdr_298.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_32 : UInt, rvclkhdr_298.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_32 <= btb_wr_data @[lib.scala 374:16] node _T_1443 = eq(btb_wr_addr, UInt<6>("h021")) @[ifu_bp_ctl.scala 416:95] node _T_1444 = and(_T_1443, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1445 = bits(_T_1444, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_299 of rvclkhdr_393 @[el2_lib.scala 508:23] + inst rvclkhdr_299 of rvclkhdr_393 @[lib.scala 368:23] rvclkhdr_299.clock <= clock rvclkhdr_299.reset <= reset - rvclkhdr_299.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_299.io.en <= _T_1445 @[el2_lib.scala 511:17] - rvclkhdr_299.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_33 : UInt, rvclkhdr_299.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_33 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_299.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_299.io.en <= _T_1445 @[lib.scala 371:17] + rvclkhdr_299.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_33 : UInt, rvclkhdr_299.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_33 <= btb_wr_data @[lib.scala 374:16] node _T_1446 = eq(btb_wr_addr, UInt<6>("h022")) @[ifu_bp_ctl.scala 416:95] node _T_1447 = and(_T_1446, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1448 = bits(_T_1447, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_300 of rvclkhdr_394 @[el2_lib.scala 508:23] + inst rvclkhdr_300 of rvclkhdr_394 @[lib.scala 368:23] rvclkhdr_300.clock <= clock rvclkhdr_300.reset <= reset - rvclkhdr_300.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_300.io.en <= _T_1448 @[el2_lib.scala 511:17] - rvclkhdr_300.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_34 : UInt, rvclkhdr_300.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_34 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_300.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_300.io.en <= _T_1448 @[lib.scala 371:17] + rvclkhdr_300.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_34 : UInt, rvclkhdr_300.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_34 <= btb_wr_data @[lib.scala 374:16] node _T_1449 = eq(btb_wr_addr, UInt<6>("h023")) @[ifu_bp_ctl.scala 416:95] node _T_1450 = and(_T_1449, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1451 = bits(_T_1450, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_301 of rvclkhdr_395 @[el2_lib.scala 508:23] + inst rvclkhdr_301 of rvclkhdr_395 @[lib.scala 368:23] rvclkhdr_301.clock <= clock rvclkhdr_301.reset <= reset - rvclkhdr_301.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_301.io.en <= _T_1451 @[el2_lib.scala 511:17] - rvclkhdr_301.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_35 : UInt, rvclkhdr_301.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_35 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_301.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_301.io.en <= _T_1451 @[lib.scala 371:17] + rvclkhdr_301.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_35 : UInt, rvclkhdr_301.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_35 <= btb_wr_data @[lib.scala 374:16] node _T_1452 = eq(btb_wr_addr, UInt<6>("h024")) @[ifu_bp_ctl.scala 416:95] node _T_1453 = and(_T_1452, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1454 = bits(_T_1453, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_302 of rvclkhdr_396 @[el2_lib.scala 508:23] + inst rvclkhdr_302 of rvclkhdr_396 @[lib.scala 368:23] rvclkhdr_302.clock <= clock rvclkhdr_302.reset <= reset - rvclkhdr_302.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_302.io.en <= _T_1454 @[el2_lib.scala 511:17] - rvclkhdr_302.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_36 : UInt, rvclkhdr_302.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_36 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_302.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_302.io.en <= _T_1454 @[lib.scala 371:17] + rvclkhdr_302.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_36 : UInt, rvclkhdr_302.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_36 <= btb_wr_data @[lib.scala 374:16] node _T_1455 = eq(btb_wr_addr, UInt<6>("h025")) @[ifu_bp_ctl.scala 416:95] node _T_1456 = and(_T_1455, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1457 = bits(_T_1456, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_303 of rvclkhdr_397 @[el2_lib.scala 508:23] + inst rvclkhdr_303 of rvclkhdr_397 @[lib.scala 368:23] rvclkhdr_303.clock <= clock rvclkhdr_303.reset <= reset - rvclkhdr_303.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_303.io.en <= _T_1457 @[el2_lib.scala 511:17] - rvclkhdr_303.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_37 : UInt, rvclkhdr_303.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_37 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_303.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_303.io.en <= _T_1457 @[lib.scala 371:17] + rvclkhdr_303.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_37 : UInt, rvclkhdr_303.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_37 <= btb_wr_data @[lib.scala 374:16] node _T_1458 = eq(btb_wr_addr, UInt<6>("h026")) @[ifu_bp_ctl.scala 416:95] node _T_1459 = and(_T_1458, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1460 = bits(_T_1459, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_304 of rvclkhdr_398 @[el2_lib.scala 508:23] + inst rvclkhdr_304 of rvclkhdr_398 @[lib.scala 368:23] rvclkhdr_304.clock <= clock rvclkhdr_304.reset <= reset - rvclkhdr_304.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_304.io.en <= _T_1460 @[el2_lib.scala 511:17] - rvclkhdr_304.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_38 : UInt, rvclkhdr_304.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_38 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_304.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_304.io.en <= _T_1460 @[lib.scala 371:17] + rvclkhdr_304.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_38 : UInt, rvclkhdr_304.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_38 <= btb_wr_data @[lib.scala 374:16] node _T_1461 = eq(btb_wr_addr, UInt<6>("h027")) @[ifu_bp_ctl.scala 416:95] node _T_1462 = and(_T_1461, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1463 = bits(_T_1462, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_305 of rvclkhdr_399 @[el2_lib.scala 508:23] + inst rvclkhdr_305 of rvclkhdr_399 @[lib.scala 368:23] rvclkhdr_305.clock <= clock rvclkhdr_305.reset <= reset - rvclkhdr_305.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_305.io.en <= _T_1463 @[el2_lib.scala 511:17] - rvclkhdr_305.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_39 : UInt, rvclkhdr_305.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_39 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_305.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_305.io.en <= _T_1463 @[lib.scala 371:17] + rvclkhdr_305.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_39 : UInt, rvclkhdr_305.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_39 <= btb_wr_data @[lib.scala 374:16] node _T_1464 = eq(btb_wr_addr, UInt<6>("h028")) @[ifu_bp_ctl.scala 416:95] node _T_1465 = and(_T_1464, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1466 = bits(_T_1465, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_306 of rvclkhdr_400 @[el2_lib.scala 508:23] + inst rvclkhdr_306 of rvclkhdr_400 @[lib.scala 368:23] rvclkhdr_306.clock <= clock rvclkhdr_306.reset <= reset - rvclkhdr_306.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_306.io.en <= _T_1466 @[el2_lib.scala 511:17] - rvclkhdr_306.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_40 : UInt, rvclkhdr_306.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_40 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_306.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_306.io.en <= _T_1466 @[lib.scala 371:17] + rvclkhdr_306.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_40 : UInt, rvclkhdr_306.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_40 <= btb_wr_data @[lib.scala 374:16] node _T_1467 = eq(btb_wr_addr, UInt<6>("h029")) @[ifu_bp_ctl.scala 416:95] node _T_1468 = and(_T_1467, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1469 = bits(_T_1468, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_307 of rvclkhdr_401 @[el2_lib.scala 508:23] + inst rvclkhdr_307 of rvclkhdr_401 @[lib.scala 368:23] rvclkhdr_307.clock <= clock rvclkhdr_307.reset <= reset - rvclkhdr_307.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_307.io.en <= _T_1469 @[el2_lib.scala 511:17] - rvclkhdr_307.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_41 : UInt, rvclkhdr_307.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_41 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_307.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_307.io.en <= _T_1469 @[lib.scala 371:17] + rvclkhdr_307.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_41 : UInt, rvclkhdr_307.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_41 <= btb_wr_data @[lib.scala 374:16] node _T_1470 = eq(btb_wr_addr, UInt<6>("h02a")) @[ifu_bp_ctl.scala 416:95] node _T_1471 = and(_T_1470, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1472 = bits(_T_1471, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_308 of rvclkhdr_402 @[el2_lib.scala 508:23] + inst rvclkhdr_308 of rvclkhdr_402 @[lib.scala 368:23] rvclkhdr_308.clock <= clock rvclkhdr_308.reset <= reset - rvclkhdr_308.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_308.io.en <= _T_1472 @[el2_lib.scala 511:17] - rvclkhdr_308.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_42 : UInt, rvclkhdr_308.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_42 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_308.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_308.io.en <= _T_1472 @[lib.scala 371:17] + rvclkhdr_308.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_42 : UInt, rvclkhdr_308.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_42 <= btb_wr_data @[lib.scala 374:16] node _T_1473 = eq(btb_wr_addr, UInt<6>("h02b")) @[ifu_bp_ctl.scala 416:95] node _T_1474 = and(_T_1473, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1475 = bits(_T_1474, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_309 of rvclkhdr_403 @[el2_lib.scala 508:23] + inst rvclkhdr_309 of rvclkhdr_403 @[lib.scala 368:23] rvclkhdr_309.clock <= clock rvclkhdr_309.reset <= reset - rvclkhdr_309.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_309.io.en <= _T_1475 @[el2_lib.scala 511:17] - rvclkhdr_309.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_43 : UInt, rvclkhdr_309.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_43 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_309.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_309.io.en <= _T_1475 @[lib.scala 371:17] + rvclkhdr_309.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_43 : UInt, rvclkhdr_309.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_43 <= btb_wr_data @[lib.scala 374:16] node _T_1476 = eq(btb_wr_addr, UInt<6>("h02c")) @[ifu_bp_ctl.scala 416:95] node _T_1477 = and(_T_1476, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1478 = bits(_T_1477, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_310 of rvclkhdr_404 @[el2_lib.scala 508:23] + inst rvclkhdr_310 of rvclkhdr_404 @[lib.scala 368:23] rvclkhdr_310.clock <= clock rvclkhdr_310.reset <= reset - rvclkhdr_310.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_310.io.en <= _T_1478 @[el2_lib.scala 511:17] - rvclkhdr_310.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_44 : UInt, rvclkhdr_310.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_44 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_310.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_310.io.en <= _T_1478 @[lib.scala 371:17] + rvclkhdr_310.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_44 : UInt, rvclkhdr_310.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_44 <= btb_wr_data @[lib.scala 374:16] node _T_1479 = eq(btb_wr_addr, UInt<6>("h02d")) @[ifu_bp_ctl.scala 416:95] node _T_1480 = and(_T_1479, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1481 = bits(_T_1480, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_311 of rvclkhdr_405 @[el2_lib.scala 508:23] + inst rvclkhdr_311 of rvclkhdr_405 @[lib.scala 368:23] rvclkhdr_311.clock <= clock rvclkhdr_311.reset <= reset - rvclkhdr_311.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_311.io.en <= _T_1481 @[el2_lib.scala 511:17] - rvclkhdr_311.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_45 : UInt, rvclkhdr_311.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_45 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_311.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_311.io.en <= _T_1481 @[lib.scala 371:17] + rvclkhdr_311.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_45 : UInt, rvclkhdr_311.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_45 <= btb_wr_data @[lib.scala 374:16] node _T_1482 = eq(btb_wr_addr, UInt<6>("h02e")) @[ifu_bp_ctl.scala 416:95] node _T_1483 = and(_T_1482, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1484 = bits(_T_1483, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_312 of rvclkhdr_406 @[el2_lib.scala 508:23] + inst rvclkhdr_312 of rvclkhdr_406 @[lib.scala 368:23] rvclkhdr_312.clock <= clock rvclkhdr_312.reset <= reset - rvclkhdr_312.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_312.io.en <= _T_1484 @[el2_lib.scala 511:17] - rvclkhdr_312.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_46 : UInt, rvclkhdr_312.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_46 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_312.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_312.io.en <= _T_1484 @[lib.scala 371:17] + rvclkhdr_312.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_46 : UInt, rvclkhdr_312.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_46 <= btb_wr_data @[lib.scala 374:16] node _T_1485 = eq(btb_wr_addr, UInt<6>("h02f")) @[ifu_bp_ctl.scala 416:95] node _T_1486 = and(_T_1485, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1487 = bits(_T_1486, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_313 of rvclkhdr_407 @[el2_lib.scala 508:23] + inst rvclkhdr_313 of rvclkhdr_407 @[lib.scala 368:23] rvclkhdr_313.clock <= clock rvclkhdr_313.reset <= reset - rvclkhdr_313.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_313.io.en <= _T_1487 @[el2_lib.scala 511:17] - rvclkhdr_313.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_47 : UInt, rvclkhdr_313.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_47 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_313.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_313.io.en <= _T_1487 @[lib.scala 371:17] + rvclkhdr_313.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_47 : UInt, rvclkhdr_313.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_47 <= btb_wr_data @[lib.scala 374:16] node _T_1488 = eq(btb_wr_addr, UInt<6>("h030")) @[ifu_bp_ctl.scala 416:95] node _T_1489 = and(_T_1488, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1490 = bits(_T_1489, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_314 of rvclkhdr_408 @[el2_lib.scala 508:23] + inst rvclkhdr_314 of rvclkhdr_408 @[lib.scala 368:23] rvclkhdr_314.clock <= clock rvclkhdr_314.reset <= reset - rvclkhdr_314.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_314.io.en <= _T_1490 @[el2_lib.scala 511:17] - rvclkhdr_314.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_48 : UInt, rvclkhdr_314.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_48 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_314.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_314.io.en <= _T_1490 @[lib.scala 371:17] + rvclkhdr_314.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_48 : UInt, rvclkhdr_314.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_48 <= btb_wr_data @[lib.scala 374:16] node _T_1491 = eq(btb_wr_addr, UInt<6>("h031")) @[ifu_bp_ctl.scala 416:95] node _T_1492 = and(_T_1491, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1493 = bits(_T_1492, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_315 of rvclkhdr_409 @[el2_lib.scala 508:23] + inst rvclkhdr_315 of rvclkhdr_409 @[lib.scala 368:23] rvclkhdr_315.clock <= clock rvclkhdr_315.reset <= reset - rvclkhdr_315.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_315.io.en <= _T_1493 @[el2_lib.scala 511:17] - rvclkhdr_315.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_49 : UInt, rvclkhdr_315.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_49 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_315.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_315.io.en <= _T_1493 @[lib.scala 371:17] + rvclkhdr_315.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_49 : UInt, rvclkhdr_315.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_49 <= btb_wr_data @[lib.scala 374:16] node _T_1494 = eq(btb_wr_addr, UInt<6>("h032")) @[ifu_bp_ctl.scala 416:95] node _T_1495 = and(_T_1494, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1496 = bits(_T_1495, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_316 of rvclkhdr_410 @[el2_lib.scala 508:23] + inst rvclkhdr_316 of rvclkhdr_410 @[lib.scala 368:23] rvclkhdr_316.clock <= clock rvclkhdr_316.reset <= reset - rvclkhdr_316.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_316.io.en <= _T_1496 @[el2_lib.scala 511:17] - rvclkhdr_316.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_50 : UInt, rvclkhdr_316.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_50 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_316.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_316.io.en <= _T_1496 @[lib.scala 371:17] + rvclkhdr_316.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_50 : UInt, rvclkhdr_316.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_50 <= btb_wr_data @[lib.scala 374:16] node _T_1497 = eq(btb_wr_addr, UInt<6>("h033")) @[ifu_bp_ctl.scala 416:95] node _T_1498 = and(_T_1497, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1499 = bits(_T_1498, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_317 of rvclkhdr_411 @[el2_lib.scala 508:23] + inst rvclkhdr_317 of rvclkhdr_411 @[lib.scala 368:23] rvclkhdr_317.clock <= clock rvclkhdr_317.reset <= reset - rvclkhdr_317.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_317.io.en <= _T_1499 @[el2_lib.scala 511:17] - rvclkhdr_317.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_51 : UInt, rvclkhdr_317.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_51 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_317.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_317.io.en <= _T_1499 @[lib.scala 371:17] + rvclkhdr_317.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_51 : UInt, rvclkhdr_317.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_51 <= btb_wr_data @[lib.scala 374:16] node _T_1500 = eq(btb_wr_addr, UInt<6>("h034")) @[ifu_bp_ctl.scala 416:95] node _T_1501 = and(_T_1500, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1502 = bits(_T_1501, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_318 of rvclkhdr_412 @[el2_lib.scala 508:23] + inst rvclkhdr_318 of rvclkhdr_412 @[lib.scala 368:23] rvclkhdr_318.clock <= clock rvclkhdr_318.reset <= reset - rvclkhdr_318.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_318.io.en <= _T_1502 @[el2_lib.scala 511:17] - rvclkhdr_318.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_52 : UInt, rvclkhdr_318.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_52 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_318.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_318.io.en <= _T_1502 @[lib.scala 371:17] + rvclkhdr_318.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_52 : UInt, rvclkhdr_318.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_52 <= btb_wr_data @[lib.scala 374:16] node _T_1503 = eq(btb_wr_addr, UInt<6>("h035")) @[ifu_bp_ctl.scala 416:95] node _T_1504 = and(_T_1503, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1505 = bits(_T_1504, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_319 of rvclkhdr_413 @[el2_lib.scala 508:23] + inst rvclkhdr_319 of rvclkhdr_413 @[lib.scala 368:23] rvclkhdr_319.clock <= clock rvclkhdr_319.reset <= reset - rvclkhdr_319.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_319.io.en <= _T_1505 @[el2_lib.scala 511:17] - rvclkhdr_319.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_53 : UInt, rvclkhdr_319.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_53 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_319.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_319.io.en <= _T_1505 @[lib.scala 371:17] + rvclkhdr_319.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_53 : UInt, rvclkhdr_319.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_53 <= btb_wr_data @[lib.scala 374:16] node _T_1506 = eq(btb_wr_addr, UInt<6>("h036")) @[ifu_bp_ctl.scala 416:95] node _T_1507 = and(_T_1506, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1508 = bits(_T_1507, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_320 of rvclkhdr_414 @[el2_lib.scala 508:23] + inst rvclkhdr_320 of rvclkhdr_414 @[lib.scala 368:23] rvclkhdr_320.clock <= clock rvclkhdr_320.reset <= reset - rvclkhdr_320.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_320.io.en <= _T_1508 @[el2_lib.scala 511:17] - rvclkhdr_320.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_54 : UInt, rvclkhdr_320.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_54 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_320.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_320.io.en <= _T_1508 @[lib.scala 371:17] + rvclkhdr_320.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_54 : UInt, rvclkhdr_320.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_54 <= btb_wr_data @[lib.scala 374:16] node _T_1509 = eq(btb_wr_addr, UInt<6>("h037")) @[ifu_bp_ctl.scala 416:95] node _T_1510 = and(_T_1509, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1511 = bits(_T_1510, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_321 of rvclkhdr_415 @[el2_lib.scala 508:23] + inst rvclkhdr_321 of rvclkhdr_415 @[lib.scala 368:23] rvclkhdr_321.clock <= clock rvclkhdr_321.reset <= reset - rvclkhdr_321.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_321.io.en <= _T_1511 @[el2_lib.scala 511:17] - rvclkhdr_321.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_55 : UInt, rvclkhdr_321.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_55 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_321.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_321.io.en <= _T_1511 @[lib.scala 371:17] + rvclkhdr_321.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_55 : UInt, rvclkhdr_321.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_55 <= btb_wr_data @[lib.scala 374:16] node _T_1512 = eq(btb_wr_addr, UInt<6>("h038")) @[ifu_bp_ctl.scala 416:95] node _T_1513 = and(_T_1512, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1514 = bits(_T_1513, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_322 of rvclkhdr_416 @[el2_lib.scala 508:23] + inst rvclkhdr_322 of rvclkhdr_416 @[lib.scala 368:23] rvclkhdr_322.clock <= clock rvclkhdr_322.reset <= reset - rvclkhdr_322.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_322.io.en <= _T_1514 @[el2_lib.scala 511:17] - rvclkhdr_322.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_56 : UInt, rvclkhdr_322.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_56 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_322.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_322.io.en <= _T_1514 @[lib.scala 371:17] + rvclkhdr_322.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_56 : UInt, rvclkhdr_322.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_56 <= btb_wr_data @[lib.scala 374:16] node _T_1515 = eq(btb_wr_addr, UInt<6>("h039")) @[ifu_bp_ctl.scala 416:95] node _T_1516 = and(_T_1515, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1517 = bits(_T_1516, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_323 of rvclkhdr_417 @[el2_lib.scala 508:23] + inst rvclkhdr_323 of rvclkhdr_417 @[lib.scala 368:23] rvclkhdr_323.clock <= clock rvclkhdr_323.reset <= reset - rvclkhdr_323.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_323.io.en <= _T_1517 @[el2_lib.scala 511:17] - rvclkhdr_323.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_57 : UInt, rvclkhdr_323.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_57 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_323.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_323.io.en <= _T_1517 @[lib.scala 371:17] + rvclkhdr_323.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_57 : UInt, rvclkhdr_323.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_57 <= btb_wr_data @[lib.scala 374:16] node _T_1518 = eq(btb_wr_addr, UInt<6>("h03a")) @[ifu_bp_ctl.scala 416:95] node _T_1519 = and(_T_1518, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1520 = bits(_T_1519, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_324 of rvclkhdr_418 @[el2_lib.scala 508:23] + inst rvclkhdr_324 of rvclkhdr_418 @[lib.scala 368:23] rvclkhdr_324.clock <= clock rvclkhdr_324.reset <= reset - rvclkhdr_324.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_324.io.en <= _T_1520 @[el2_lib.scala 511:17] - rvclkhdr_324.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_58 : UInt, rvclkhdr_324.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_58 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_324.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_324.io.en <= _T_1520 @[lib.scala 371:17] + rvclkhdr_324.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_58 : UInt, rvclkhdr_324.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_58 <= btb_wr_data @[lib.scala 374:16] node _T_1521 = eq(btb_wr_addr, UInt<6>("h03b")) @[ifu_bp_ctl.scala 416:95] node _T_1522 = and(_T_1521, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1523 = bits(_T_1522, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_325 of rvclkhdr_419 @[el2_lib.scala 508:23] + inst rvclkhdr_325 of rvclkhdr_419 @[lib.scala 368:23] rvclkhdr_325.clock <= clock rvclkhdr_325.reset <= reset - rvclkhdr_325.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_325.io.en <= _T_1523 @[el2_lib.scala 511:17] - rvclkhdr_325.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_59 : UInt, rvclkhdr_325.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_59 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_325.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_325.io.en <= _T_1523 @[lib.scala 371:17] + rvclkhdr_325.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_59 : UInt, rvclkhdr_325.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_59 <= btb_wr_data @[lib.scala 374:16] node _T_1524 = eq(btb_wr_addr, UInt<6>("h03c")) @[ifu_bp_ctl.scala 416:95] node _T_1525 = and(_T_1524, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1526 = bits(_T_1525, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_326 of rvclkhdr_420 @[el2_lib.scala 508:23] + inst rvclkhdr_326 of rvclkhdr_420 @[lib.scala 368:23] rvclkhdr_326.clock <= clock rvclkhdr_326.reset <= reset - rvclkhdr_326.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_326.io.en <= _T_1526 @[el2_lib.scala 511:17] - rvclkhdr_326.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_60 : UInt, rvclkhdr_326.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_60 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_326.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_326.io.en <= _T_1526 @[lib.scala 371:17] + rvclkhdr_326.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_60 : UInt, rvclkhdr_326.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_60 <= btb_wr_data @[lib.scala 374:16] node _T_1527 = eq(btb_wr_addr, UInt<6>("h03d")) @[ifu_bp_ctl.scala 416:95] node _T_1528 = and(_T_1527, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1529 = bits(_T_1528, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_327 of rvclkhdr_421 @[el2_lib.scala 508:23] + inst rvclkhdr_327 of rvclkhdr_421 @[lib.scala 368:23] rvclkhdr_327.clock <= clock rvclkhdr_327.reset <= reset - rvclkhdr_327.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_327.io.en <= _T_1529 @[el2_lib.scala 511:17] - rvclkhdr_327.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_61 : UInt, rvclkhdr_327.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_61 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_327.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_327.io.en <= _T_1529 @[lib.scala 371:17] + rvclkhdr_327.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_61 : UInt, rvclkhdr_327.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_61 <= btb_wr_data @[lib.scala 374:16] node _T_1530 = eq(btb_wr_addr, UInt<6>("h03e")) @[ifu_bp_ctl.scala 416:95] node _T_1531 = and(_T_1530, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1532 = bits(_T_1531, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_328 of rvclkhdr_422 @[el2_lib.scala 508:23] + inst rvclkhdr_328 of rvclkhdr_422 @[lib.scala 368:23] rvclkhdr_328.clock <= clock rvclkhdr_328.reset <= reset - rvclkhdr_328.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_328.io.en <= _T_1532 @[el2_lib.scala 511:17] - rvclkhdr_328.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_62 : UInt, rvclkhdr_328.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_62 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_328.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_328.io.en <= _T_1532 @[lib.scala 371:17] + rvclkhdr_328.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_62 : UInt, rvclkhdr_328.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_62 <= btb_wr_data @[lib.scala 374:16] node _T_1533 = eq(btb_wr_addr, UInt<6>("h03f")) @[ifu_bp_ctl.scala 416:95] node _T_1534 = and(_T_1533, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1535 = bits(_T_1534, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_329 of rvclkhdr_423 @[el2_lib.scala 508:23] + inst rvclkhdr_329 of rvclkhdr_423 @[lib.scala 368:23] rvclkhdr_329.clock <= clock rvclkhdr_329.reset <= reset - rvclkhdr_329.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_329.io.en <= _T_1535 @[el2_lib.scala 511:17] - rvclkhdr_329.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_63 : UInt, rvclkhdr_329.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_63 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_329.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_329.io.en <= _T_1535 @[lib.scala 371:17] + rvclkhdr_329.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_63 : UInt, rvclkhdr_329.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_63 <= btb_wr_data @[lib.scala 374:16] node _T_1536 = eq(btb_wr_addr, UInt<7>("h040")) @[ifu_bp_ctl.scala 416:95] node _T_1537 = and(_T_1536, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1538 = bits(_T_1537, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_330 of rvclkhdr_424 @[el2_lib.scala 508:23] + inst rvclkhdr_330 of rvclkhdr_424 @[lib.scala 368:23] rvclkhdr_330.clock <= clock rvclkhdr_330.reset <= reset - rvclkhdr_330.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_330.io.en <= _T_1538 @[el2_lib.scala 511:17] - rvclkhdr_330.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_64 : UInt, rvclkhdr_330.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_64 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_330.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_330.io.en <= _T_1538 @[lib.scala 371:17] + rvclkhdr_330.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_64 : UInt, rvclkhdr_330.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_64 <= btb_wr_data @[lib.scala 374:16] node _T_1539 = eq(btb_wr_addr, UInt<7>("h041")) @[ifu_bp_ctl.scala 416:95] node _T_1540 = and(_T_1539, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1541 = bits(_T_1540, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_331 of rvclkhdr_425 @[el2_lib.scala 508:23] + inst rvclkhdr_331 of rvclkhdr_425 @[lib.scala 368:23] rvclkhdr_331.clock <= clock rvclkhdr_331.reset <= reset - rvclkhdr_331.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_331.io.en <= _T_1541 @[el2_lib.scala 511:17] - rvclkhdr_331.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_65 : UInt, rvclkhdr_331.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_65 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_331.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_331.io.en <= _T_1541 @[lib.scala 371:17] + rvclkhdr_331.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_65 : UInt, rvclkhdr_331.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_65 <= btb_wr_data @[lib.scala 374:16] node _T_1542 = eq(btb_wr_addr, UInt<7>("h042")) @[ifu_bp_ctl.scala 416:95] node _T_1543 = and(_T_1542, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1544 = bits(_T_1543, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_332 of rvclkhdr_426 @[el2_lib.scala 508:23] + inst rvclkhdr_332 of rvclkhdr_426 @[lib.scala 368:23] rvclkhdr_332.clock <= clock rvclkhdr_332.reset <= reset - rvclkhdr_332.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_332.io.en <= _T_1544 @[el2_lib.scala 511:17] - rvclkhdr_332.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_66 : UInt, rvclkhdr_332.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_66 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_332.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_332.io.en <= _T_1544 @[lib.scala 371:17] + rvclkhdr_332.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_66 : UInt, rvclkhdr_332.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_66 <= btb_wr_data @[lib.scala 374:16] node _T_1545 = eq(btb_wr_addr, UInt<7>("h043")) @[ifu_bp_ctl.scala 416:95] node _T_1546 = and(_T_1545, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1547 = bits(_T_1546, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_333 of rvclkhdr_427 @[el2_lib.scala 508:23] + inst rvclkhdr_333 of rvclkhdr_427 @[lib.scala 368:23] rvclkhdr_333.clock <= clock rvclkhdr_333.reset <= reset - rvclkhdr_333.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_333.io.en <= _T_1547 @[el2_lib.scala 511:17] - rvclkhdr_333.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_67 : UInt, rvclkhdr_333.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_67 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_333.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_333.io.en <= _T_1547 @[lib.scala 371:17] + rvclkhdr_333.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_67 : UInt, rvclkhdr_333.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_67 <= btb_wr_data @[lib.scala 374:16] node _T_1548 = eq(btb_wr_addr, UInt<7>("h044")) @[ifu_bp_ctl.scala 416:95] node _T_1549 = and(_T_1548, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1550 = bits(_T_1549, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_334 of rvclkhdr_428 @[el2_lib.scala 508:23] + inst rvclkhdr_334 of rvclkhdr_428 @[lib.scala 368:23] rvclkhdr_334.clock <= clock rvclkhdr_334.reset <= reset - rvclkhdr_334.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_334.io.en <= _T_1550 @[el2_lib.scala 511:17] - rvclkhdr_334.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_68 : UInt, rvclkhdr_334.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_68 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_334.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_334.io.en <= _T_1550 @[lib.scala 371:17] + rvclkhdr_334.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_68 : UInt, rvclkhdr_334.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_68 <= btb_wr_data @[lib.scala 374:16] node _T_1551 = eq(btb_wr_addr, UInt<7>("h045")) @[ifu_bp_ctl.scala 416:95] node _T_1552 = and(_T_1551, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1553 = bits(_T_1552, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_335 of rvclkhdr_429 @[el2_lib.scala 508:23] + inst rvclkhdr_335 of rvclkhdr_429 @[lib.scala 368:23] rvclkhdr_335.clock <= clock rvclkhdr_335.reset <= reset - rvclkhdr_335.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_335.io.en <= _T_1553 @[el2_lib.scala 511:17] - rvclkhdr_335.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_69 : UInt, rvclkhdr_335.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_69 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_335.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_335.io.en <= _T_1553 @[lib.scala 371:17] + rvclkhdr_335.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_69 : UInt, rvclkhdr_335.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_69 <= btb_wr_data @[lib.scala 374:16] node _T_1554 = eq(btb_wr_addr, UInt<7>("h046")) @[ifu_bp_ctl.scala 416:95] node _T_1555 = and(_T_1554, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1556 = bits(_T_1555, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_336 of rvclkhdr_430 @[el2_lib.scala 508:23] + inst rvclkhdr_336 of rvclkhdr_430 @[lib.scala 368:23] rvclkhdr_336.clock <= clock rvclkhdr_336.reset <= reset - rvclkhdr_336.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_336.io.en <= _T_1556 @[el2_lib.scala 511:17] - rvclkhdr_336.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_70 : UInt, rvclkhdr_336.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_70 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_336.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_336.io.en <= _T_1556 @[lib.scala 371:17] + rvclkhdr_336.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_70 : UInt, rvclkhdr_336.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_70 <= btb_wr_data @[lib.scala 374:16] node _T_1557 = eq(btb_wr_addr, UInt<7>("h047")) @[ifu_bp_ctl.scala 416:95] node _T_1558 = and(_T_1557, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1559 = bits(_T_1558, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_337 of rvclkhdr_431 @[el2_lib.scala 508:23] + inst rvclkhdr_337 of rvclkhdr_431 @[lib.scala 368:23] rvclkhdr_337.clock <= clock rvclkhdr_337.reset <= reset - rvclkhdr_337.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_337.io.en <= _T_1559 @[el2_lib.scala 511:17] - rvclkhdr_337.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_71 : UInt, rvclkhdr_337.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_71 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_337.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_337.io.en <= _T_1559 @[lib.scala 371:17] + rvclkhdr_337.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_71 : UInt, rvclkhdr_337.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_71 <= btb_wr_data @[lib.scala 374:16] node _T_1560 = eq(btb_wr_addr, UInt<7>("h048")) @[ifu_bp_ctl.scala 416:95] node _T_1561 = and(_T_1560, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1562 = bits(_T_1561, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_338 of rvclkhdr_432 @[el2_lib.scala 508:23] + inst rvclkhdr_338 of rvclkhdr_432 @[lib.scala 368:23] rvclkhdr_338.clock <= clock rvclkhdr_338.reset <= reset - rvclkhdr_338.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_338.io.en <= _T_1562 @[el2_lib.scala 511:17] - rvclkhdr_338.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_72 : UInt, rvclkhdr_338.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_72 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_338.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_338.io.en <= _T_1562 @[lib.scala 371:17] + rvclkhdr_338.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_72 : UInt, rvclkhdr_338.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_72 <= btb_wr_data @[lib.scala 374:16] node _T_1563 = eq(btb_wr_addr, UInt<7>("h049")) @[ifu_bp_ctl.scala 416:95] node _T_1564 = and(_T_1563, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1565 = bits(_T_1564, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_339 of rvclkhdr_433 @[el2_lib.scala 508:23] + inst rvclkhdr_339 of rvclkhdr_433 @[lib.scala 368:23] rvclkhdr_339.clock <= clock rvclkhdr_339.reset <= reset - rvclkhdr_339.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_339.io.en <= _T_1565 @[el2_lib.scala 511:17] - rvclkhdr_339.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_73 : UInt, rvclkhdr_339.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_73 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_339.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_339.io.en <= _T_1565 @[lib.scala 371:17] + rvclkhdr_339.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_73 : UInt, rvclkhdr_339.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_73 <= btb_wr_data @[lib.scala 374:16] node _T_1566 = eq(btb_wr_addr, UInt<7>("h04a")) @[ifu_bp_ctl.scala 416:95] node _T_1567 = and(_T_1566, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1568 = bits(_T_1567, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_340 of rvclkhdr_434 @[el2_lib.scala 508:23] + inst rvclkhdr_340 of rvclkhdr_434 @[lib.scala 368:23] rvclkhdr_340.clock <= clock rvclkhdr_340.reset <= reset - rvclkhdr_340.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_340.io.en <= _T_1568 @[el2_lib.scala 511:17] - rvclkhdr_340.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_74 : UInt, rvclkhdr_340.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_74 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_340.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_340.io.en <= _T_1568 @[lib.scala 371:17] + rvclkhdr_340.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_74 : UInt, rvclkhdr_340.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_74 <= btb_wr_data @[lib.scala 374:16] node _T_1569 = eq(btb_wr_addr, UInt<7>("h04b")) @[ifu_bp_ctl.scala 416:95] node _T_1570 = and(_T_1569, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1571 = bits(_T_1570, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_341 of rvclkhdr_435 @[el2_lib.scala 508:23] + inst rvclkhdr_341 of rvclkhdr_435 @[lib.scala 368:23] rvclkhdr_341.clock <= clock rvclkhdr_341.reset <= reset - rvclkhdr_341.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_341.io.en <= _T_1571 @[el2_lib.scala 511:17] - rvclkhdr_341.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_75 : UInt, rvclkhdr_341.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_75 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_341.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_341.io.en <= _T_1571 @[lib.scala 371:17] + rvclkhdr_341.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_75 : UInt, rvclkhdr_341.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_75 <= btb_wr_data @[lib.scala 374:16] node _T_1572 = eq(btb_wr_addr, UInt<7>("h04c")) @[ifu_bp_ctl.scala 416:95] node _T_1573 = and(_T_1572, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1574 = bits(_T_1573, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_342 of rvclkhdr_436 @[el2_lib.scala 508:23] + inst rvclkhdr_342 of rvclkhdr_436 @[lib.scala 368:23] rvclkhdr_342.clock <= clock rvclkhdr_342.reset <= reset - rvclkhdr_342.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_342.io.en <= _T_1574 @[el2_lib.scala 511:17] - rvclkhdr_342.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_76 : UInt, rvclkhdr_342.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_76 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_342.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_342.io.en <= _T_1574 @[lib.scala 371:17] + rvclkhdr_342.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_76 : UInt, rvclkhdr_342.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_76 <= btb_wr_data @[lib.scala 374:16] node _T_1575 = eq(btb_wr_addr, UInt<7>("h04d")) @[ifu_bp_ctl.scala 416:95] node _T_1576 = and(_T_1575, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1577 = bits(_T_1576, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_343 of rvclkhdr_437 @[el2_lib.scala 508:23] + inst rvclkhdr_343 of rvclkhdr_437 @[lib.scala 368:23] rvclkhdr_343.clock <= clock rvclkhdr_343.reset <= reset - rvclkhdr_343.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_343.io.en <= _T_1577 @[el2_lib.scala 511:17] - rvclkhdr_343.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_77 : UInt, rvclkhdr_343.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_77 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_343.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_343.io.en <= _T_1577 @[lib.scala 371:17] + rvclkhdr_343.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_77 : UInt, rvclkhdr_343.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_77 <= btb_wr_data @[lib.scala 374:16] node _T_1578 = eq(btb_wr_addr, UInt<7>("h04e")) @[ifu_bp_ctl.scala 416:95] node _T_1579 = and(_T_1578, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1580 = bits(_T_1579, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_344 of rvclkhdr_438 @[el2_lib.scala 508:23] + inst rvclkhdr_344 of rvclkhdr_438 @[lib.scala 368:23] rvclkhdr_344.clock <= clock rvclkhdr_344.reset <= reset - rvclkhdr_344.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_344.io.en <= _T_1580 @[el2_lib.scala 511:17] - rvclkhdr_344.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_78 : UInt, rvclkhdr_344.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_78 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_344.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_344.io.en <= _T_1580 @[lib.scala 371:17] + rvclkhdr_344.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_78 : UInt, rvclkhdr_344.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_78 <= btb_wr_data @[lib.scala 374:16] node _T_1581 = eq(btb_wr_addr, UInt<7>("h04f")) @[ifu_bp_ctl.scala 416:95] node _T_1582 = and(_T_1581, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1583 = bits(_T_1582, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_345 of rvclkhdr_439 @[el2_lib.scala 508:23] + inst rvclkhdr_345 of rvclkhdr_439 @[lib.scala 368:23] rvclkhdr_345.clock <= clock rvclkhdr_345.reset <= reset - rvclkhdr_345.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_345.io.en <= _T_1583 @[el2_lib.scala 511:17] - rvclkhdr_345.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_79 : UInt, rvclkhdr_345.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_79 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_345.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_345.io.en <= _T_1583 @[lib.scala 371:17] + rvclkhdr_345.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_79 : UInt, rvclkhdr_345.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_79 <= btb_wr_data @[lib.scala 374:16] node _T_1584 = eq(btb_wr_addr, UInt<7>("h050")) @[ifu_bp_ctl.scala 416:95] node _T_1585 = and(_T_1584, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1586 = bits(_T_1585, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_346 of rvclkhdr_440 @[el2_lib.scala 508:23] + inst rvclkhdr_346 of rvclkhdr_440 @[lib.scala 368:23] rvclkhdr_346.clock <= clock rvclkhdr_346.reset <= reset - rvclkhdr_346.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_346.io.en <= _T_1586 @[el2_lib.scala 511:17] - rvclkhdr_346.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_80 : UInt, rvclkhdr_346.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_80 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_346.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_346.io.en <= _T_1586 @[lib.scala 371:17] + rvclkhdr_346.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_80 : UInt, rvclkhdr_346.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_80 <= btb_wr_data @[lib.scala 374:16] node _T_1587 = eq(btb_wr_addr, UInt<7>("h051")) @[ifu_bp_ctl.scala 416:95] node _T_1588 = and(_T_1587, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1589 = bits(_T_1588, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_347 of rvclkhdr_441 @[el2_lib.scala 508:23] + inst rvclkhdr_347 of rvclkhdr_441 @[lib.scala 368:23] rvclkhdr_347.clock <= clock rvclkhdr_347.reset <= reset - rvclkhdr_347.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_347.io.en <= _T_1589 @[el2_lib.scala 511:17] - rvclkhdr_347.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_81 : UInt, rvclkhdr_347.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_81 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_347.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_347.io.en <= _T_1589 @[lib.scala 371:17] + rvclkhdr_347.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_81 : UInt, rvclkhdr_347.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_81 <= btb_wr_data @[lib.scala 374:16] node _T_1590 = eq(btb_wr_addr, UInt<7>("h052")) @[ifu_bp_ctl.scala 416:95] node _T_1591 = and(_T_1590, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1592 = bits(_T_1591, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_348 of rvclkhdr_442 @[el2_lib.scala 508:23] + inst rvclkhdr_348 of rvclkhdr_442 @[lib.scala 368:23] rvclkhdr_348.clock <= clock rvclkhdr_348.reset <= reset - rvclkhdr_348.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_348.io.en <= _T_1592 @[el2_lib.scala 511:17] - rvclkhdr_348.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_82 : UInt, rvclkhdr_348.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_82 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_348.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_348.io.en <= _T_1592 @[lib.scala 371:17] + rvclkhdr_348.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_82 : UInt, rvclkhdr_348.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_82 <= btb_wr_data @[lib.scala 374:16] node _T_1593 = eq(btb_wr_addr, UInt<7>("h053")) @[ifu_bp_ctl.scala 416:95] node _T_1594 = and(_T_1593, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1595 = bits(_T_1594, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_349 of rvclkhdr_443 @[el2_lib.scala 508:23] + inst rvclkhdr_349 of rvclkhdr_443 @[lib.scala 368:23] rvclkhdr_349.clock <= clock rvclkhdr_349.reset <= reset - rvclkhdr_349.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_349.io.en <= _T_1595 @[el2_lib.scala 511:17] - rvclkhdr_349.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_83 : UInt, rvclkhdr_349.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_83 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_349.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_349.io.en <= _T_1595 @[lib.scala 371:17] + rvclkhdr_349.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_83 : UInt, rvclkhdr_349.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_83 <= btb_wr_data @[lib.scala 374:16] node _T_1596 = eq(btb_wr_addr, UInt<7>("h054")) @[ifu_bp_ctl.scala 416:95] node _T_1597 = and(_T_1596, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1598 = bits(_T_1597, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_350 of rvclkhdr_444 @[el2_lib.scala 508:23] + inst rvclkhdr_350 of rvclkhdr_444 @[lib.scala 368:23] rvclkhdr_350.clock <= clock rvclkhdr_350.reset <= reset - rvclkhdr_350.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_350.io.en <= _T_1598 @[el2_lib.scala 511:17] - rvclkhdr_350.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_84 : UInt, rvclkhdr_350.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_84 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_350.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_350.io.en <= _T_1598 @[lib.scala 371:17] + rvclkhdr_350.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_84 : UInt, rvclkhdr_350.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_84 <= btb_wr_data @[lib.scala 374:16] node _T_1599 = eq(btb_wr_addr, UInt<7>("h055")) @[ifu_bp_ctl.scala 416:95] node _T_1600 = and(_T_1599, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1601 = bits(_T_1600, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_351 of rvclkhdr_445 @[el2_lib.scala 508:23] + inst rvclkhdr_351 of rvclkhdr_445 @[lib.scala 368:23] rvclkhdr_351.clock <= clock rvclkhdr_351.reset <= reset - rvclkhdr_351.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_351.io.en <= _T_1601 @[el2_lib.scala 511:17] - rvclkhdr_351.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_85 : UInt, rvclkhdr_351.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_85 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_351.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_351.io.en <= _T_1601 @[lib.scala 371:17] + rvclkhdr_351.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_85 : UInt, rvclkhdr_351.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_85 <= btb_wr_data @[lib.scala 374:16] node _T_1602 = eq(btb_wr_addr, UInt<7>("h056")) @[ifu_bp_ctl.scala 416:95] node _T_1603 = and(_T_1602, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1604 = bits(_T_1603, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_352 of rvclkhdr_446 @[el2_lib.scala 508:23] + inst rvclkhdr_352 of rvclkhdr_446 @[lib.scala 368:23] rvclkhdr_352.clock <= clock rvclkhdr_352.reset <= reset - rvclkhdr_352.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_352.io.en <= _T_1604 @[el2_lib.scala 511:17] - rvclkhdr_352.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_86 : UInt, rvclkhdr_352.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_86 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_352.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_352.io.en <= _T_1604 @[lib.scala 371:17] + rvclkhdr_352.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_86 : UInt, rvclkhdr_352.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_86 <= btb_wr_data @[lib.scala 374:16] node _T_1605 = eq(btb_wr_addr, UInt<7>("h057")) @[ifu_bp_ctl.scala 416:95] node _T_1606 = and(_T_1605, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1607 = bits(_T_1606, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_353 of rvclkhdr_447 @[el2_lib.scala 508:23] + inst rvclkhdr_353 of rvclkhdr_447 @[lib.scala 368:23] rvclkhdr_353.clock <= clock rvclkhdr_353.reset <= reset - rvclkhdr_353.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_353.io.en <= _T_1607 @[el2_lib.scala 511:17] - rvclkhdr_353.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_87 : UInt, rvclkhdr_353.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_87 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_353.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_353.io.en <= _T_1607 @[lib.scala 371:17] + rvclkhdr_353.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_87 : UInt, rvclkhdr_353.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_87 <= btb_wr_data @[lib.scala 374:16] node _T_1608 = eq(btb_wr_addr, UInt<7>("h058")) @[ifu_bp_ctl.scala 416:95] node _T_1609 = and(_T_1608, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1610 = bits(_T_1609, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_354 of rvclkhdr_448 @[el2_lib.scala 508:23] + inst rvclkhdr_354 of rvclkhdr_448 @[lib.scala 368:23] rvclkhdr_354.clock <= clock rvclkhdr_354.reset <= reset - rvclkhdr_354.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_354.io.en <= _T_1610 @[el2_lib.scala 511:17] - rvclkhdr_354.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_88 : UInt, rvclkhdr_354.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_88 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_354.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_354.io.en <= _T_1610 @[lib.scala 371:17] + rvclkhdr_354.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_88 : UInt, rvclkhdr_354.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_88 <= btb_wr_data @[lib.scala 374:16] node _T_1611 = eq(btb_wr_addr, UInt<7>("h059")) @[ifu_bp_ctl.scala 416:95] node _T_1612 = and(_T_1611, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1613 = bits(_T_1612, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_355 of rvclkhdr_449 @[el2_lib.scala 508:23] + inst rvclkhdr_355 of rvclkhdr_449 @[lib.scala 368:23] rvclkhdr_355.clock <= clock rvclkhdr_355.reset <= reset - rvclkhdr_355.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_355.io.en <= _T_1613 @[el2_lib.scala 511:17] - rvclkhdr_355.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_89 : UInt, rvclkhdr_355.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_89 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_355.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_355.io.en <= _T_1613 @[lib.scala 371:17] + rvclkhdr_355.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_89 : UInt, rvclkhdr_355.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_89 <= btb_wr_data @[lib.scala 374:16] node _T_1614 = eq(btb_wr_addr, UInt<7>("h05a")) @[ifu_bp_ctl.scala 416:95] node _T_1615 = and(_T_1614, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1616 = bits(_T_1615, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_356 of rvclkhdr_450 @[el2_lib.scala 508:23] + inst rvclkhdr_356 of rvclkhdr_450 @[lib.scala 368:23] rvclkhdr_356.clock <= clock rvclkhdr_356.reset <= reset - rvclkhdr_356.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_356.io.en <= _T_1616 @[el2_lib.scala 511:17] - rvclkhdr_356.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_90 : UInt, rvclkhdr_356.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_90 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_356.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_356.io.en <= _T_1616 @[lib.scala 371:17] + rvclkhdr_356.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_90 : UInt, rvclkhdr_356.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_90 <= btb_wr_data @[lib.scala 374:16] node _T_1617 = eq(btb_wr_addr, UInt<7>("h05b")) @[ifu_bp_ctl.scala 416:95] node _T_1618 = and(_T_1617, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1619 = bits(_T_1618, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_357 of rvclkhdr_451 @[el2_lib.scala 508:23] + inst rvclkhdr_357 of rvclkhdr_451 @[lib.scala 368:23] rvclkhdr_357.clock <= clock rvclkhdr_357.reset <= reset - rvclkhdr_357.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_357.io.en <= _T_1619 @[el2_lib.scala 511:17] - rvclkhdr_357.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_91 : UInt, rvclkhdr_357.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_91 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_357.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_357.io.en <= _T_1619 @[lib.scala 371:17] + rvclkhdr_357.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_91 : UInt, rvclkhdr_357.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_91 <= btb_wr_data @[lib.scala 374:16] node _T_1620 = eq(btb_wr_addr, UInt<7>("h05c")) @[ifu_bp_ctl.scala 416:95] node _T_1621 = and(_T_1620, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1622 = bits(_T_1621, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_358 of rvclkhdr_452 @[el2_lib.scala 508:23] + inst rvclkhdr_358 of rvclkhdr_452 @[lib.scala 368:23] rvclkhdr_358.clock <= clock rvclkhdr_358.reset <= reset - rvclkhdr_358.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_358.io.en <= _T_1622 @[el2_lib.scala 511:17] - rvclkhdr_358.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_92 : UInt, rvclkhdr_358.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_92 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_358.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_358.io.en <= _T_1622 @[lib.scala 371:17] + rvclkhdr_358.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_92 : UInt, rvclkhdr_358.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_92 <= btb_wr_data @[lib.scala 374:16] node _T_1623 = eq(btb_wr_addr, UInt<7>("h05d")) @[ifu_bp_ctl.scala 416:95] node _T_1624 = and(_T_1623, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1625 = bits(_T_1624, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_359 of rvclkhdr_453 @[el2_lib.scala 508:23] + inst rvclkhdr_359 of rvclkhdr_453 @[lib.scala 368:23] rvclkhdr_359.clock <= clock rvclkhdr_359.reset <= reset - rvclkhdr_359.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_359.io.en <= _T_1625 @[el2_lib.scala 511:17] - rvclkhdr_359.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_93 : UInt, rvclkhdr_359.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_93 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_359.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_359.io.en <= _T_1625 @[lib.scala 371:17] + rvclkhdr_359.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_93 : UInt, rvclkhdr_359.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_93 <= btb_wr_data @[lib.scala 374:16] node _T_1626 = eq(btb_wr_addr, UInt<7>("h05e")) @[ifu_bp_ctl.scala 416:95] node _T_1627 = and(_T_1626, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1628 = bits(_T_1627, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_360 of rvclkhdr_454 @[el2_lib.scala 508:23] + inst rvclkhdr_360 of rvclkhdr_454 @[lib.scala 368:23] rvclkhdr_360.clock <= clock rvclkhdr_360.reset <= reset - rvclkhdr_360.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_360.io.en <= _T_1628 @[el2_lib.scala 511:17] - rvclkhdr_360.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_94 : UInt, rvclkhdr_360.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_94 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_360.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_360.io.en <= _T_1628 @[lib.scala 371:17] + rvclkhdr_360.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_94 : UInt, rvclkhdr_360.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_94 <= btb_wr_data @[lib.scala 374:16] node _T_1629 = eq(btb_wr_addr, UInt<7>("h05f")) @[ifu_bp_ctl.scala 416:95] node _T_1630 = and(_T_1629, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1631 = bits(_T_1630, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_361 of rvclkhdr_455 @[el2_lib.scala 508:23] + inst rvclkhdr_361 of rvclkhdr_455 @[lib.scala 368:23] rvclkhdr_361.clock <= clock rvclkhdr_361.reset <= reset - rvclkhdr_361.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_361.io.en <= _T_1631 @[el2_lib.scala 511:17] - rvclkhdr_361.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_95 : UInt, rvclkhdr_361.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_95 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_361.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_361.io.en <= _T_1631 @[lib.scala 371:17] + rvclkhdr_361.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_95 : UInt, rvclkhdr_361.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_95 <= btb_wr_data @[lib.scala 374:16] node _T_1632 = eq(btb_wr_addr, UInt<7>("h060")) @[ifu_bp_ctl.scala 416:95] node _T_1633 = and(_T_1632, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1634 = bits(_T_1633, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_362 of rvclkhdr_456 @[el2_lib.scala 508:23] + inst rvclkhdr_362 of rvclkhdr_456 @[lib.scala 368:23] rvclkhdr_362.clock <= clock rvclkhdr_362.reset <= reset - rvclkhdr_362.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_362.io.en <= _T_1634 @[el2_lib.scala 511:17] - rvclkhdr_362.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_96 : UInt, rvclkhdr_362.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_96 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_362.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_362.io.en <= _T_1634 @[lib.scala 371:17] + rvclkhdr_362.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_96 : UInt, rvclkhdr_362.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_96 <= btb_wr_data @[lib.scala 374:16] node _T_1635 = eq(btb_wr_addr, UInt<7>("h061")) @[ifu_bp_ctl.scala 416:95] node _T_1636 = and(_T_1635, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1637 = bits(_T_1636, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_363 of rvclkhdr_457 @[el2_lib.scala 508:23] + inst rvclkhdr_363 of rvclkhdr_457 @[lib.scala 368:23] rvclkhdr_363.clock <= clock rvclkhdr_363.reset <= reset - rvclkhdr_363.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_363.io.en <= _T_1637 @[el2_lib.scala 511:17] - rvclkhdr_363.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_97 : UInt, rvclkhdr_363.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_97 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_363.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_363.io.en <= _T_1637 @[lib.scala 371:17] + rvclkhdr_363.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_97 : UInt, rvclkhdr_363.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_97 <= btb_wr_data @[lib.scala 374:16] node _T_1638 = eq(btb_wr_addr, UInt<7>("h062")) @[ifu_bp_ctl.scala 416:95] node _T_1639 = and(_T_1638, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1640 = bits(_T_1639, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_364 of rvclkhdr_458 @[el2_lib.scala 508:23] + inst rvclkhdr_364 of rvclkhdr_458 @[lib.scala 368:23] rvclkhdr_364.clock <= clock rvclkhdr_364.reset <= reset - rvclkhdr_364.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_364.io.en <= _T_1640 @[el2_lib.scala 511:17] - rvclkhdr_364.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_98 : UInt, rvclkhdr_364.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_98 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_364.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_364.io.en <= _T_1640 @[lib.scala 371:17] + rvclkhdr_364.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_98 : UInt, rvclkhdr_364.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_98 <= btb_wr_data @[lib.scala 374:16] node _T_1641 = eq(btb_wr_addr, UInt<7>("h063")) @[ifu_bp_ctl.scala 416:95] node _T_1642 = and(_T_1641, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1643 = bits(_T_1642, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_365 of rvclkhdr_459 @[el2_lib.scala 508:23] + inst rvclkhdr_365 of rvclkhdr_459 @[lib.scala 368:23] rvclkhdr_365.clock <= clock rvclkhdr_365.reset <= reset - rvclkhdr_365.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_365.io.en <= _T_1643 @[el2_lib.scala 511:17] - rvclkhdr_365.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_99 : UInt, rvclkhdr_365.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_99 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_365.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_365.io.en <= _T_1643 @[lib.scala 371:17] + rvclkhdr_365.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_99 : UInt, rvclkhdr_365.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_99 <= btb_wr_data @[lib.scala 374:16] node _T_1644 = eq(btb_wr_addr, UInt<7>("h064")) @[ifu_bp_ctl.scala 416:95] node _T_1645 = and(_T_1644, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1646 = bits(_T_1645, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_366 of rvclkhdr_460 @[el2_lib.scala 508:23] + inst rvclkhdr_366 of rvclkhdr_460 @[lib.scala 368:23] rvclkhdr_366.clock <= clock rvclkhdr_366.reset <= reset - rvclkhdr_366.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_366.io.en <= _T_1646 @[el2_lib.scala 511:17] - rvclkhdr_366.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_100 : UInt, rvclkhdr_366.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_100 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_366.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_366.io.en <= _T_1646 @[lib.scala 371:17] + rvclkhdr_366.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_100 : UInt, rvclkhdr_366.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_100 <= btb_wr_data @[lib.scala 374:16] node _T_1647 = eq(btb_wr_addr, UInt<7>("h065")) @[ifu_bp_ctl.scala 416:95] node _T_1648 = and(_T_1647, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1649 = bits(_T_1648, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_367 of rvclkhdr_461 @[el2_lib.scala 508:23] + inst rvclkhdr_367 of rvclkhdr_461 @[lib.scala 368:23] rvclkhdr_367.clock <= clock rvclkhdr_367.reset <= reset - rvclkhdr_367.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_367.io.en <= _T_1649 @[el2_lib.scala 511:17] - rvclkhdr_367.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_101 : UInt, rvclkhdr_367.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_101 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_367.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_367.io.en <= _T_1649 @[lib.scala 371:17] + rvclkhdr_367.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_101 : UInt, rvclkhdr_367.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_101 <= btb_wr_data @[lib.scala 374:16] node _T_1650 = eq(btb_wr_addr, UInt<7>("h066")) @[ifu_bp_ctl.scala 416:95] node _T_1651 = and(_T_1650, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1652 = bits(_T_1651, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_368 of rvclkhdr_462 @[el2_lib.scala 508:23] + inst rvclkhdr_368 of rvclkhdr_462 @[lib.scala 368:23] rvclkhdr_368.clock <= clock rvclkhdr_368.reset <= reset - rvclkhdr_368.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_368.io.en <= _T_1652 @[el2_lib.scala 511:17] - rvclkhdr_368.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_102 : UInt, rvclkhdr_368.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_102 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_368.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_368.io.en <= _T_1652 @[lib.scala 371:17] + rvclkhdr_368.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_102 : UInt, rvclkhdr_368.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_102 <= btb_wr_data @[lib.scala 374:16] node _T_1653 = eq(btb_wr_addr, UInt<7>("h067")) @[ifu_bp_ctl.scala 416:95] node _T_1654 = and(_T_1653, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1655 = bits(_T_1654, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_369 of rvclkhdr_463 @[el2_lib.scala 508:23] + inst rvclkhdr_369 of rvclkhdr_463 @[lib.scala 368:23] rvclkhdr_369.clock <= clock rvclkhdr_369.reset <= reset - rvclkhdr_369.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_369.io.en <= _T_1655 @[el2_lib.scala 511:17] - rvclkhdr_369.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_103 : UInt, rvclkhdr_369.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_103 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_369.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_369.io.en <= _T_1655 @[lib.scala 371:17] + rvclkhdr_369.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_103 : UInt, rvclkhdr_369.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_103 <= btb_wr_data @[lib.scala 374:16] node _T_1656 = eq(btb_wr_addr, UInt<7>("h068")) @[ifu_bp_ctl.scala 416:95] node _T_1657 = and(_T_1656, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1658 = bits(_T_1657, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_370 of rvclkhdr_464 @[el2_lib.scala 508:23] + inst rvclkhdr_370 of rvclkhdr_464 @[lib.scala 368:23] rvclkhdr_370.clock <= clock rvclkhdr_370.reset <= reset - rvclkhdr_370.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_370.io.en <= _T_1658 @[el2_lib.scala 511:17] - rvclkhdr_370.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_104 : UInt, rvclkhdr_370.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_104 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_370.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_370.io.en <= _T_1658 @[lib.scala 371:17] + rvclkhdr_370.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_104 : UInt, rvclkhdr_370.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_104 <= btb_wr_data @[lib.scala 374:16] node _T_1659 = eq(btb_wr_addr, UInt<7>("h069")) @[ifu_bp_ctl.scala 416:95] node _T_1660 = and(_T_1659, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1661 = bits(_T_1660, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_371 of rvclkhdr_465 @[el2_lib.scala 508:23] + inst rvclkhdr_371 of rvclkhdr_465 @[lib.scala 368:23] rvclkhdr_371.clock <= clock rvclkhdr_371.reset <= reset - rvclkhdr_371.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_371.io.en <= _T_1661 @[el2_lib.scala 511:17] - rvclkhdr_371.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_105 : UInt, rvclkhdr_371.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_105 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_371.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_371.io.en <= _T_1661 @[lib.scala 371:17] + rvclkhdr_371.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_105 : UInt, rvclkhdr_371.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_105 <= btb_wr_data @[lib.scala 374:16] node _T_1662 = eq(btb_wr_addr, UInt<7>("h06a")) @[ifu_bp_ctl.scala 416:95] node _T_1663 = and(_T_1662, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1664 = bits(_T_1663, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_372 of rvclkhdr_466 @[el2_lib.scala 508:23] + inst rvclkhdr_372 of rvclkhdr_466 @[lib.scala 368:23] rvclkhdr_372.clock <= clock rvclkhdr_372.reset <= reset - rvclkhdr_372.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_372.io.en <= _T_1664 @[el2_lib.scala 511:17] - rvclkhdr_372.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_106 : UInt, rvclkhdr_372.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_106 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_372.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_372.io.en <= _T_1664 @[lib.scala 371:17] + rvclkhdr_372.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_106 : UInt, rvclkhdr_372.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_106 <= btb_wr_data @[lib.scala 374:16] node _T_1665 = eq(btb_wr_addr, UInt<7>("h06b")) @[ifu_bp_ctl.scala 416:95] node _T_1666 = and(_T_1665, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1667 = bits(_T_1666, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_373 of rvclkhdr_467 @[el2_lib.scala 508:23] + inst rvclkhdr_373 of rvclkhdr_467 @[lib.scala 368:23] rvclkhdr_373.clock <= clock rvclkhdr_373.reset <= reset - rvclkhdr_373.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_373.io.en <= _T_1667 @[el2_lib.scala 511:17] - rvclkhdr_373.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_107 : UInt, rvclkhdr_373.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_107 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_373.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_373.io.en <= _T_1667 @[lib.scala 371:17] + rvclkhdr_373.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_107 : UInt, rvclkhdr_373.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_107 <= btb_wr_data @[lib.scala 374:16] node _T_1668 = eq(btb_wr_addr, UInt<7>("h06c")) @[ifu_bp_ctl.scala 416:95] node _T_1669 = and(_T_1668, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1670 = bits(_T_1669, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_374 of rvclkhdr_468 @[el2_lib.scala 508:23] + inst rvclkhdr_374 of rvclkhdr_468 @[lib.scala 368:23] rvclkhdr_374.clock <= clock rvclkhdr_374.reset <= reset - rvclkhdr_374.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_374.io.en <= _T_1670 @[el2_lib.scala 511:17] - rvclkhdr_374.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_108 : UInt, rvclkhdr_374.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_108 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_374.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_374.io.en <= _T_1670 @[lib.scala 371:17] + rvclkhdr_374.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_108 : UInt, rvclkhdr_374.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_108 <= btb_wr_data @[lib.scala 374:16] node _T_1671 = eq(btb_wr_addr, UInt<7>("h06d")) @[ifu_bp_ctl.scala 416:95] node _T_1672 = and(_T_1671, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1673 = bits(_T_1672, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_375 of rvclkhdr_469 @[el2_lib.scala 508:23] + inst rvclkhdr_375 of rvclkhdr_469 @[lib.scala 368:23] rvclkhdr_375.clock <= clock rvclkhdr_375.reset <= reset - rvclkhdr_375.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_375.io.en <= _T_1673 @[el2_lib.scala 511:17] - rvclkhdr_375.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_109 : UInt, rvclkhdr_375.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_109 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_375.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_375.io.en <= _T_1673 @[lib.scala 371:17] + rvclkhdr_375.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_109 : UInt, rvclkhdr_375.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_109 <= btb_wr_data @[lib.scala 374:16] node _T_1674 = eq(btb_wr_addr, UInt<7>("h06e")) @[ifu_bp_ctl.scala 416:95] node _T_1675 = and(_T_1674, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1676 = bits(_T_1675, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_376 of rvclkhdr_470 @[el2_lib.scala 508:23] + inst rvclkhdr_376 of rvclkhdr_470 @[lib.scala 368:23] rvclkhdr_376.clock <= clock rvclkhdr_376.reset <= reset - rvclkhdr_376.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_376.io.en <= _T_1676 @[el2_lib.scala 511:17] - rvclkhdr_376.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_110 : UInt, rvclkhdr_376.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_110 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_376.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_376.io.en <= _T_1676 @[lib.scala 371:17] + rvclkhdr_376.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_110 : UInt, rvclkhdr_376.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_110 <= btb_wr_data @[lib.scala 374:16] node _T_1677 = eq(btb_wr_addr, UInt<7>("h06f")) @[ifu_bp_ctl.scala 416:95] node _T_1678 = and(_T_1677, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1679 = bits(_T_1678, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_377 of rvclkhdr_471 @[el2_lib.scala 508:23] + inst rvclkhdr_377 of rvclkhdr_471 @[lib.scala 368:23] rvclkhdr_377.clock <= clock rvclkhdr_377.reset <= reset - rvclkhdr_377.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_377.io.en <= _T_1679 @[el2_lib.scala 511:17] - rvclkhdr_377.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_111 : UInt, rvclkhdr_377.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_111 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_377.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_377.io.en <= _T_1679 @[lib.scala 371:17] + rvclkhdr_377.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_111 : UInt, rvclkhdr_377.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_111 <= btb_wr_data @[lib.scala 374:16] node _T_1680 = eq(btb_wr_addr, UInt<7>("h070")) @[ifu_bp_ctl.scala 416:95] node _T_1681 = and(_T_1680, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1682 = bits(_T_1681, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_378 of rvclkhdr_472 @[el2_lib.scala 508:23] + inst rvclkhdr_378 of rvclkhdr_472 @[lib.scala 368:23] rvclkhdr_378.clock <= clock rvclkhdr_378.reset <= reset - rvclkhdr_378.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_378.io.en <= _T_1682 @[el2_lib.scala 511:17] - rvclkhdr_378.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_112 : UInt, rvclkhdr_378.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_112 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_378.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_378.io.en <= _T_1682 @[lib.scala 371:17] + rvclkhdr_378.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_112 : UInt, rvclkhdr_378.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_112 <= btb_wr_data @[lib.scala 374:16] node _T_1683 = eq(btb_wr_addr, UInt<7>("h071")) @[ifu_bp_ctl.scala 416:95] node _T_1684 = and(_T_1683, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1685 = bits(_T_1684, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_379 of rvclkhdr_473 @[el2_lib.scala 508:23] + inst rvclkhdr_379 of rvclkhdr_473 @[lib.scala 368:23] rvclkhdr_379.clock <= clock rvclkhdr_379.reset <= reset - rvclkhdr_379.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_379.io.en <= _T_1685 @[el2_lib.scala 511:17] - rvclkhdr_379.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_113 : UInt, rvclkhdr_379.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_113 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_379.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_379.io.en <= _T_1685 @[lib.scala 371:17] + rvclkhdr_379.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_113 : UInt, rvclkhdr_379.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_113 <= btb_wr_data @[lib.scala 374:16] node _T_1686 = eq(btb_wr_addr, UInt<7>("h072")) @[ifu_bp_ctl.scala 416:95] node _T_1687 = and(_T_1686, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1688 = bits(_T_1687, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_380 of rvclkhdr_474 @[el2_lib.scala 508:23] + inst rvclkhdr_380 of rvclkhdr_474 @[lib.scala 368:23] rvclkhdr_380.clock <= clock rvclkhdr_380.reset <= reset - rvclkhdr_380.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_380.io.en <= _T_1688 @[el2_lib.scala 511:17] - rvclkhdr_380.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_114 : UInt, rvclkhdr_380.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_114 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_380.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_380.io.en <= _T_1688 @[lib.scala 371:17] + rvclkhdr_380.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_114 : UInt, rvclkhdr_380.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_114 <= btb_wr_data @[lib.scala 374:16] node _T_1689 = eq(btb_wr_addr, UInt<7>("h073")) @[ifu_bp_ctl.scala 416:95] node _T_1690 = and(_T_1689, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1691 = bits(_T_1690, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_381 of rvclkhdr_475 @[el2_lib.scala 508:23] + inst rvclkhdr_381 of rvclkhdr_475 @[lib.scala 368:23] rvclkhdr_381.clock <= clock rvclkhdr_381.reset <= reset - rvclkhdr_381.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_381.io.en <= _T_1691 @[el2_lib.scala 511:17] - rvclkhdr_381.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_115 : UInt, rvclkhdr_381.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_115 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_381.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_381.io.en <= _T_1691 @[lib.scala 371:17] + rvclkhdr_381.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_115 : UInt, rvclkhdr_381.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_115 <= btb_wr_data @[lib.scala 374:16] node _T_1692 = eq(btb_wr_addr, UInt<7>("h074")) @[ifu_bp_ctl.scala 416:95] node _T_1693 = and(_T_1692, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1694 = bits(_T_1693, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_382 of rvclkhdr_476 @[el2_lib.scala 508:23] + inst rvclkhdr_382 of rvclkhdr_476 @[lib.scala 368:23] rvclkhdr_382.clock <= clock rvclkhdr_382.reset <= reset - rvclkhdr_382.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_382.io.en <= _T_1694 @[el2_lib.scala 511:17] - rvclkhdr_382.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_116 : UInt, rvclkhdr_382.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_116 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_382.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_382.io.en <= _T_1694 @[lib.scala 371:17] + rvclkhdr_382.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_116 : UInt, rvclkhdr_382.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_116 <= btb_wr_data @[lib.scala 374:16] node _T_1695 = eq(btb_wr_addr, UInt<7>("h075")) @[ifu_bp_ctl.scala 416:95] node _T_1696 = and(_T_1695, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1697 = bits(_T_1696, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_383 of rvclkhdr_477 @[el2_lib.scala 508:23] + inst rvclkhdr_383 of rvclkhdr_477 @[lib.scala 368:23] rvclkhdr_383.clock <= clock rvclkhdr_383.reset <= reset - rvclkhdr_383.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_383.io.en <= _T_1697 @[el2_lib.scala 511:17] - rvclkhdr_383.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_117 : UInt, rvclkhdr_383.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_117 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_383.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_383.io.en <= _T_1697 @[lib.scala 371:17] + rvclkhdr_383.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_117 : UInt, rvclkhdr_383.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_117 <= btb_wr_data @[lib.scala 374:16] node _T_1698 = eq(btb_wr_addr, UInt<7>("h076")) @[ifu_bp_ctl.scala 416:95] node _T_1699 = and(_T_1698, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1700 = bits(_T_1699, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_384 of rvclkhdr_478 @[el2_lib.scala 508:23] + inst rvclkhdr_384 of rvclkhdr_478 @[lib.scala 368:23] rvclkhdr_384.clock <= clock rvclkhdr_384.reset <= reset - rvclkhdr_384.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_384.io.en <= _T_1700 @[el2_lib.scala 511:17] - rvclkhdr_384.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_118 : UInt, rvclkhdr_384.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_118 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_384.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_384.io.en <= _T_1700 @[lib.scala 371:17] + rvclkhdr_384.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_118 : UInt, rvclkhdr_384.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_118 <= btb_wr_data @[lib.scala 374:16] node _T_1701 = eq(btb_wr_addr, UInt<7>("h077")) @[ifu_bp_ctl.scala 416:95] node _T_1702 = and(_T_1701, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1703 = bits(_T_1702, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_385 of rvclkhdr_479 @[el2_lib.scala 508:23] + inst rvclkhdr_385 of rvclkhdr_479 @[lib.scala 368:23] rvclkhdr_385.clock <= clock rvclkhdr_385.reset <= reset - rvclkhdr_385.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_385.io.en <= _T_1703 @[el2_lib.scala 511:17] - rvclkhdr_385.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_119 : UInt, rvclkhdr_385.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_119 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_385.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_385.io.en <= _T_1703 @[lib.scala 371:17] + rvclkhdr_385.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_119 : UInt, rvclkhdr_385.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_119 <= btb_wr_data @[lib.scala 374:16] node _T_1704 = eq(btb_wr_addr, UInt<7>("h078")) @[ifu_bp_ctl.scala 416:95] node _T_1705 = and(_T_1704, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1706 = bits(_T_1705, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_386 of rvclkhdr_480 @[el2_lib.scala 508:23] + inst rvclkhdr_386 of rvclkhdr_480 @[lib.scala 368:23] rvclkhdr_386.clock <= clock rvclkhdr_386.reset <= reset - rvclkhdr_386.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_386.io.en <= _T_1706 @[el2_lib.scala 511:17] - rvclkhdr_386.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_120 : UInt, rvclkhdr_386.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_120 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_386.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_386.io.en <= _T_1706 @[lib.scala 371:17] + rvclkhdr_386.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_120 : UInt, rvclkhdr_386.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_120 <= btb_wr_data @[lib.scala 374:16] node _T_1707 = eq(btb_wr_addr, UInt<7>("h079")) @[ifu_bp_ctl.scala 416:95] node _T_1708 = and(_T_1707, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1709 = bits(_T_1708, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_387 of rvclkhdr_481 @[el2_lib.scala 508:23] + inst rvclkhdr_387 of rvclkhdr_481 @[lib.scala 368:23] rvclkhdr_387.clock <= clock rvclkhdr_387.reset <= reset - rvclkhdr_387.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_387.io.en <= _T_1709 @[el2_lib.scala 511:17] - rvclkhdr_387.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_121 : UInt, rvclkhdr_387.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_121 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_387.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_387.io.en <= _T_1709 @[lib.scala 371:17] + rvclkhdr_387.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_121 : UInt, rvclkhdr_387.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_121 <= btb_wr_data @[lib.scala 374:16] node _T_1710 = eq(btb_wr_addr, UInt<7>("h07a")) @[ifu_bp_ctl.scala 416:95] node _T_1711 = and(_T_1710, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1712 = bits(_T_1711, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_388 of rvclkhdr_482 @[el2_lib.scala 508:23] + inst rvclkhdr_388 of rvclkhdr_482 @[lib.scala 368:23] rvclkhdr_388.clock <= clock rvclkhdr_388.reset <= reset - rvclkhdr_388.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_388.io.en <= _T_1712 @[el2_lib.scala 511:17] - rvclkhdr_388.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_122 : UInt, rvclkhdr_388.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_122 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_388.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_388.io.en <= _T_1712 @[lib.scala 371:17] + rvclkhdr_388.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_122 : UInt, rvclkhdr_388.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_122 <= btb_wr_data @[lib.scala 374:16] node _T_1713 = eq(btb_wr_addr, UInt<7>("h07b")) @[ifu_bp_ctl.scala 416:95] node _T_1714 = and(_T_1713, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1715 = bits(_T_1714, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_389 of rvclkhdr_483 @[el2_lib.scala 508:23] + inst rvclkhdr_389 of rvclkhdr_483 @[lib.scala 368:23] rvclkhdr_389.clock <= clock rvclkhdr_389.reset <= reset - rvclkhdr_389.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_389.io.en <= _T_1715 @[el2_lib.scala 511:17] - rvclkhdr_389.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_123 : UInt, rvclkhdr_389.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_123 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_389.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_389.io.en <= _T_1715 @[lib.scala 371:17] + rvclkhdr_389.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_123 : UInt, rvclkhdr_389.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_123 <= btb_wr_data @[lib.scala 374:16] node _T_1716 = eq(btb_wr_addr, UInt<7>("h07c")) @[ifu_bp_ctl.scala 416:95] node _T_1717 = and(_T_1716, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1718 = bits(_T_1717, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_390 of rvclkhdr_484 @[el2_lib.scala 508:23] + inst rvclkhdr_390 of rvclkhdr_484 @[lib.scala 368:23] rvclkhdr_390.clock <= clock rvclkhdr_390.reset <= reset - rvclkhdr_390.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_390.io.en <= _T_1718 @[el2_lib.scala 511:17] - rvclkhdr_390.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_124 : UInt, rvclkhdr_390.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_124 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_390.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_390.io.en <= _T_1718 @[lib.scala 371:17] + rvclkhdr_390.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_124 : UInt, rvclkhdr_390.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_124 <= btb_wr_data @[lib.scala 374:16] node _T_1719 = eq(btb_wr_addr, UInt<7>("h07d")) @[ifu_bp_ctl.scala 416:95] node _T_1720 = and(_T_1719, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1721 = bits(_T_1720, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_391 of rvclkhdr_485 @[el2_lib.scala 508:23] + inst rvclkhdr_391 of rvclkhdr_485 @[lib.scala 368:23] rvclkhdr_391.clock <= clock rvclkhdr_391.reset <= reset - rvclkhdr_391.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_391.io.en <= _T_1721 @[el2_lib.scala 511:17] - rvclkhdr_391.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_125 : UInt, rvclkhdr_391.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_125 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_391.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_391.io.en <= _T_1721 @[lib.scala 371:17] + rvclkhdr_391.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_125 : UInt, rvclkhdr_391.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_125 <= btb_wr_data @[lib.scala 374:16] node _T_1722 = eq(btb_wr_addr, UInt<7>("h07e")) @[ifu_bp_ctl.scala 416:95] node _T_1723 = and(_T_1722, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1724 = bits(_T_1723, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_392 of rvclkhdr_486 @[el2_lib.scala 508:23] + inst rvclkhdr_392 of rvclkhdr_486 @[lib.scala 368:23] rvclkhdr_392.clock <= clock rvclkhdr_392.reset <= reset - rvclkhdr_392.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_392.io.en <= _T_1724 @[el2_lib.scala 511:17] - rvclkhdr_392.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_126 : UInt, rvclkhdr_392.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_126 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_392.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_392.io.en <= _T_1724 @[lib.scala 371:17] + rvclkhdr_392.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_126 : UInt, rvclkhdr_392.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_126 <= btb_wr_data @[lib.scala 374:16] node _T_1725 = eq(btb_wr_addr, UInt<7>("h07f")) @[ifu_bp_ctl.scala 416:95] node _T_1726 = and(_T_1725, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1727 = bits(_T_1726, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_393 of rvclkhdr_487 @[el2_lib.scala 508:23] + inst rvclkhdr_393 of rvclkhdr_487 @[lib.scala 368:23] rvclkhdr_393.clock <= clock rvclkhdr_393.reset <= reset - rvclkhdr_393.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_393.io.en <= _T_1727 @[el2_lib.scala 511:17] - rvclkhdr_393.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_127 : UInt, rvclkhdr_393.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_127 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_393.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_393.io.en <= _T_1727 @[lib.scala 371:17] + rvclkhdr_393.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_127 : UInt, rvclkhdr_393.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_127 <= btb_wr_data @[lib.scala 374:16] node _T_1728 = eq(btb_wr_addr, UInt<8>("h080")) @[ifu_bp_ctl.scala 416:95] node _T_1729 = and(_T_1728, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1730 = bits(_T_1729, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_394 of rvclkhdr_488 @[el2_lib.scala 508:23] + inst rvclkhdr_394 of rvclkhdr_488 @[lib.scala 368:23] rvclkhdr_394.clock <= clock rvclkhdr_394.reset <= reset - rvclkhdr_394.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_394.io.en <= _T_1730 @[el2_lib.scala 511:17] - rvclkhdr_394.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_128 : UInt, rvclkhdr_394.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_128 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_394.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_394.io.en <= _T_1730 @[lib.scala 371:17] + rvclkhdr_394.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_128 : UInt, rvclkhdr_394.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_128 <= btb_wr_data @[lib.scala 374:16] node _T_1731 = eq(btb_wr_addr, UInt<8>("h081")) @[ifu_bp_ctl.scala 416:95] node _T_1732 = and(_T_1731, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1733 = bits(_T_1732, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_395 of rvclkhdr_489 @[el2_lib.scala 508:23] + inst rvclkhdr_395 of rvclkhdr_489 @[lib.scala 368:23] rvclkhdr_395.clock <= clock rvclkhdr_395.reset <= reset - rvclkhdr_395.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_395.io.en <= _T_1733 @[el2_lib.scala 511:17] - rvclkhdr_395.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_129 : UInt, rvclkhdr_395.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_129 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_395.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_395.io.en <= _T_1733 @[lib.scala 371:17] + rvclkhdr_395.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_129 : UInt, rvclkhdr_395.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_129 <= btb_wr_data @[lib.scala 374:16] node _T_1734 = eq(btb_wr_addr, UInt<8>("h082")) @[ifu_bp_ctl.scala 416:95] node _T_1735 = and(_T_1734, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1736 = bits(_T_1735, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_396 of rvclkhdr_490 @[el2_lib.scala 508:23] + inst rvclkhdr_396 of rvclkhdr_490 @[lib.scala 368:23] rvclkhdr_396.clock <= clock rvclkhdr_396.reset <= reset - rvclkhdr_396.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_396.io.en <= _T_1736 @[el2_lib.scala 511:17] - rvclkhdr_396.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_130 : UInt, rvclkhdr_396.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_130 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_396.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_396.io.en <= _T_1736 @[lib.scala 371:17] + rvclkhdr_396.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_130 : UInt, rvclkhdr_396.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_130 <= btb_wr_data @[lib.scala 374:16] node _T_1737 = eq(btb_wr_addr, UInt<8>("h083")) @[ifu_bp_ctl.scala 416:95] node _T_1738 = and(_T_1737, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1739 = bits(_T_1738, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_397 of rvclkhdr_491 @[el2_lib.scala 508:23] + inst rvclkhdr_397 of rvclkhdr_491 @[lib.scala 368:23] rvclkhdr_397.clock <= clock rvclkhdr_397.reset <= reset - rvclkhdr_397.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_397.io.en <= _T_1739 @[el2_lib.scala 511:17] - rvclkhdr_397.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_131 : UInt, rvclkhdr_397.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_131 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_397.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_397.io.en <= _T_1739 @[lib.scala 371:17] + rvclkhdr_397.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_131 : UInt, rvclkhdr_397.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_131 <= btb_wr_data @[lib.scala 374:16] node _T_1740 = eq(btb_wr_addr, UInt<8>("h084")) @[ifu_bp_ctl.scala 416:95] node _T_1741 = and(_T_1740, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1742 = bits(_T_1741, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_398 of rvclkhdr_492 @[el2_lib.scala 508:23] + inst rvclkhdr_398 of rvclkhdr_492 @[lib.scala 368:23] rvclkhdr_398.clock <= clock rvclkhdr_398.reset <= reset - rvclkhdr_398.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_398.io.en <= _T_1742 @[el2_lib.scala 511:17] - rvclkhdr_398.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_132 : UInt, rvclkhdr_398.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_132 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_398.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_398.io.en <= _T_1742 @[lib.scala 371:17] + rvclkhdr_398.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_132 : UInt, rvclkhdr_398.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_132 <= btb_wr_data @[lib.scala 374:16] node _T_1743 = eq(btb_wr_addr, UInt<8>("h085")) @[ifu_bp_ctl.scala 416:95] node _T_1744 = and(_T_1743, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1745 = bits(_T_1744, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_399 of rvclkhdr_493 @[el2_lib.scala 508:23] + inst rvclkhdr_399 of rvclkhdr_493 @[lib.scala 368:23] rvclkhdr_399.clock <= clock rvclkhdr_399.reset <= reset - rvclkhdr_399.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_399.io.en <= _T_1745 @[el2_lib.scala 511:17] - rvclkhdr_399.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_133 : UInt, rvclkhdr_399.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_133 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_399.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_399.io.en <= _T_1745 @[lib.scala 371:17] + rvclkhdr_399.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_133 : UInt, rvclkhdr_399.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_133 <= btb_wr_data @[lib.scala 374:16] node _T_1746 = eq(btb_wr_addr, UInt<8>("h086")) @[ifu_bp_ctl.scala 416:95] node _T_1747 = and(_T_1746, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1748 = bits(_T_1747, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_400 of rvclkhdr_494 @[el2_lib.scala 508:23] + inst rvclkhdr_400 of rvclkhdr_494 @[lib.scala 368:23] rvclkhdr_400.clock <= clock rvclkhdr_400.reset <= reset - rvclkhdr_400.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_400.io.en <= _T_1748 @[el2_lib.scala 511:17] - rvclkhdr_400.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_134 : UInt, rvclkhdr_400.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_134 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_400.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_400.io.en <= _T_1748 @[lib.scala 371:17] + rvclkhdr_400.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_134 : UInt, rvclkhdr_400.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_134 <= btb_wr_data @[lib.scala 374:16] node _T_1749 = eq(btb_wr_addr, UInt<8>("h087")) @[ifu_bp_ctl.scala 416:95] node _T_1750 = and(_T_1749, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1751 = bits(_T_1750, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_401 of rvclkhdr_495 @[el2_lib.scala 508:23] + inst rvclkhdr_401 of rvclkhdr_495 @[lib.scala 368:23] rvclkhdr_401.clock <= clock rvclkhdr_401.reset <= reset - rvclkhdr_401.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_401.io.en <= _T_1751 @[el2_lib.scala 511:17] - rvclkhdr_401.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_135 : UInt, rvclkhdr_401.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_135 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_401.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_401.io.en <= _T_1751 @[lib.scala 371:17] + rvclkhdr_401.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_135 : UInt, rvclkhdr_401.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_135 <= btb_wr_data @[lib.scala 374:16] node _T_1752 = eq(btb_wr_addr, UInt<8>("h088")) @[ifu_bp_ctl.scala 416:95] node _T_1753 = and(_T_1752, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1754 = bits(_T_1753, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_402 of rvclkhdr_496 @[el2_lib.scala 508:23] + inst rvclkhdr_402 of rvclkhdr_496 @[lib.scala 368:23] rvclkhdr_402.clock <= clock rvclkhdr_402.reset <= reset - rvclkhdr_402.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_402.io.en <= _T_1754 @[el2_lib.scala 511:17] - rvclkhdr_402.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_136 : UInt, rvclkhdr_402.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_136 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_402.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_402.io.en <= _T_1754 @[lib.scala 371:17] + rvclkhdr_402.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_136 : UInt, rvclkhdr_402.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_136 <= btb_wr_data @[lib.scala 374:16] node _T_1755 = eq(btb_wr_addr, UInt<8>("h089")) @[ifu_bp_ctl.scala 416:95] node _T_1756 = and(_T_1755, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1757 = bits(_T_1756, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_403 of rvclkhdr_497 @[el2_lib.scala 508:23] + inst rvclkhdr_403 of rvclkhdr_497 @[lib.scala 368:23] rvclkhdr_403.clock <= clock rvclkhdr_403.reset <= reset - rvclkhdr_403.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_403.io.en <= _T_1757 @[el2_lib.scala 511:17] - rvclkhdr_403.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_137 : UInt, rvclkhdr_403.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_137 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_403.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_403.io.en <= _T_1757 @[lib.scala 371:17] + rvclkhdr_403.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_137 : UInt, rvclkhdr_403.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_137 <= btb_wr_data @[lib.scala 374:16] node _T_1758 = eq(btb_wr_addr, UInt<8>("h08a")) @[ifu_bp_ctl.scala 416:95] node _T_1759 = and(_T_1758, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1760 = bits(_T_1759, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_404 of rvclkhdr_498 @[el2_lib.scala 508:23] + inst rvclkhdr_404 of rvclkhdr_498 @[lib.scala 368:23] rvclkhdr_404.clock <= clock rvclkhdr_404.reset <= reset - rvclkhdr_404.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_404.io.en <= _T_1760 @[el2_lib.scala 511:17] - rvclkhdr_404.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_138 : UInt, rvclkhdr_404.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_138 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_404.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_404.io.en <= _T_1760 @[lib.scala 371:17] + rvclkhdr_404.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_138 : UInt, rvclkhdr_404.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_138 <= btb_wr_data @[lib.scala 374:16] node _T_1761 = eq(btb_wr_addr, UInt<8>("h08b")) @[ifu_bp_ctl.scala 416:95] node _T_1762 = and(_T_1761, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1763 = bits(_T_1762, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_405 of rvclkhdr_499 @[el2_lib.scala 508:23] + inst rvclkhdr_405 of rvclkhdr_499 @[lib.scala 368:23] rvclkhdr_405.clock <= clock rvclkhdr_405.reset <= reset - rvclkhdr_405.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_405.io.en <= _T_1763 @[el2_lib.scala 511:17] - rvclkhdr_405.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_139 : UInt, rvclkhdr_405.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_139 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_405.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_405.io.en <= _T_1763 @[lib.scala 371:17] + rvclkhdr_405.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_139 : UInt, rvclkhdr_405.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_139 <= btb_wr_data @[lib.scala 374:16] node _T_1764 = eq(btb_wr_addr, UInt<8>("h08c")) @[ifu_bp_ctl.scala 416:95] node _T_1765 = and(_T_1764, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1766 = bits(_T_1765, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_406 of rvclkhdr_500 @[el2_lib.scala 508:23] + inst rvclkhdr_406 of rvclkhdr_500 @[lib.scala 368:23] rvclkhdr_406.clock <= clock rvclkhdr_406.reset <= reset - rvclkhdr_406.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_406.io.en <= _T_1766 @[el2_lib.scala 511:17] - rvclkhdr_406.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_140 : UInt, rvclkhdr_406.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_140 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_406.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_406.io.en <= _T_1766 @[lib.scala 371:17] + rvclkhdr_406.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_140 : UInt, rvclkhdr_406.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_140 <= btb_wr_data @[lib.scala 374:16] node _T_1767 = eq(btb_wr_addr, UInt<8>("h08d")) @[ifu_bp_ctl.scala 416:95] node _T_1768 = and(_T_1767, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1769 = bits(_T_1768, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_407 of rvclkhdr_501 @[el2_lib.scala 508:23] + inst rvclkhdr_407 of rvclkhdr_501 @[lib.scala 368:23] rvclkhdr_407.clock <= clock rvclkhdr_407.reset <= reset - rvclkhdr_407.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_407.io.en <= _T_1769 @[el2_lib.scala 511:17] - rvclkhdr_407.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_141 : UInt, rvclkhdr_407.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_141 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_407.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_407.io.en <= _T_1769 @[lib.scala 371:17] + rvclkhdr_407.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_141 : UInt, rvclkhdr_407.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_141 <= btb_wr_data @[lib.scala 374:16] node _T_1770 = eq(btb_wr_addr, UInt<8>("h08e")) @[ifu_bp_ctl.scala 416:95] node _T_1771 = and(_T_1770, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1772 = bits(_T_1771, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_408 of rvclkhdr_502 @[el2_lib.scala 508:23] + inst rvclkhdr_408 of rvclkhdr_502 @[lib.scala 368:23] rvclkhdr_408.clock <= clock rvclkhdr_408.reset <= reset - rvclkhdr_408.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_408.io.en <= _T_1772 @[el2_lib.scala 511:17] - rvclkhdr_408.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_142 : UInt, rvclkhdr_408.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_142 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_408.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_408.io.en <= _T_1772 @[lib.scala 371:17] + rvclkhdr_408.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_142 : UInt, rvclkhdr_408.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_142 <= btb_wr_data @[lib.scala 374:16] node _T_1773 = eq(btb_wr_addr, UInt<8>("h08f")) @[ifu_bp_ctl.scala 416:95] node _T_1774 = and(_T_1773, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1775 = bits(_T_1774, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_409 of rvclkhdr_503 @[el2_lib.scala 508:23] + inst rvclkhdr_409 of rvclkhdr_503 @[lib.scala 368:23] rvclkhdr_409.clock <= clock rvclkhdr_409.reset <= reset - rvclkhdr_409.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_409.io.en <= _T_1775 @[el2_lib.scala 511:17] - rvclkhdr_409.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_143 : UInt, rvclkhdr_409.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_143 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_409.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_409.io.en <= _T_1775 @[lib.scala 371:17] + rvclkhdr_409.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_143 : UInt, rvclkhdr_409.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_143 <= btb_wr_data @[lib.scala 374:16] node _T_1776 = eq(btb_wr_addr, UInt<8>("h090")) @[ifu_bp_ctl.scala 416:95] node _T_1777 = and(_T_1776, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1778 = bits(_T_1777, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_410 of rvclkhdr_504 @[el2_lib.scala 508:23] + inst rvclkhdr_410 of rvclkhdr_504 @[lib.scala 368:23] rvclkhdr_410.clock <= clock rvclkhdr_410.reset <= reset - rvclkhdr_410.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_410.io.en <= _T_1778 @[el2_lib.scala 511:17] - rvclkhdr_410.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_144 : UInt, rvclkhdr_410.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_144 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_410.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_410.io.en <= _T_1778 @[lib.scala 371:17] + rvclkhdr_410.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_144 : UInt, rvclkhdr_410.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_144 <= btb_wr_data @[lib.scala 374:16] node _T_1779 = eq(btb_wr_addr, UInt<8>("h091")) @[ifu_bp_ctl.scala 416:95] node _T_1780 = and(_T_1779, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1781 = bits(_T_1780, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_411 of rvclkhdr_505 @[el2_lib.scala 508:23] + inst rvclkhdr_411 of rvclkhdr_505 @[lib.scala 368:23] rvclkhdr_411.clock <= clock rvclkhdr_411.reset <= reset - rvclkhdr_411.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_411.io.en <= _T_1781 @[el2_lib.scala 511:17] - rvclkhdr_411.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_145 : UInt, rvclkhdr_411.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_145 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_411.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_411.io.en <= _T_1781 @[lib.scala 371:17] + rvclkhdr_411.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_145 : UInt, rvclkhdr_411.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_145 <= btb_wr_data @[lib.scala 374:16] node _T_1782 = eq(btb_wr_addr, UInt<8>("h092")) @[ifu_bp_ctl.scala 416:95] node _T_1783 = and(_T_1782, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1784 = bits(_T_1783, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_412 of rvclkhdr_506 @[el2_lib.scala 508:23] + inst rvclkhdr_412 of rvclkhdr_506 @[lib.scala 368:23] rvclkhdr_412.clock <= clock rvclkhdr_412.reset <= reset - rvclkhdr_412.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_412.io.en <= _T_1784 @[el2_lib.scala 511:17] - rvclkhdr_412.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_146 : UInt, rvclkhdr_412.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_146 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_412.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_412.io.en <= _T_1784 @[lib.scala 371:17] + rvclkhdr_412.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_146 : UInt, rvclkhdr_412.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_146 <= btb_wr_data @[lib.scala 374:16] node _T_1785 = eq(btb_wr_addr, UInt<8>("h093")) @[ifu_bp_ctl.scala 416:95] node _T_1786 = and(_T_1785, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1787 = bits(_T_1786, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_413 of rvclkhdr_507 @[el2_lib.scala 508:23] + inst rvclkhdr_413 of rvclkhdr_507 @[lib.scala 368:23] rvclkhdr_413.clock <= clock rvclkhdr_413.reset <= reset - rvclkhdr_413.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_413.io.en <= _T_1787 @[el2_lib.scala 511:17] - rvclkhdr_413.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_147 : UInt, rvclkhdr_413.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_147 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_413.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_413.io.en <= _T_1787 @[lib.scala 371:17] + rvclkhdr_413.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_147 : UInt, rvclkhdr_413.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_147 <= btb_wr_data @[lib.scala 374:16] node _T_1788 = eq(btb_wr_addr, UInt<8>("h094")) @[ifu_bp_ctl.scala 416:95] node _T_1789 = and(_T_1788, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1790 = bits(_T_1789, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_414 of rvclkhdr_508 @[el2_lib.scala 508:23] + inst rvclkhdr_414 of rvclkhdr_508 @[lib.scala 368:23] rvclkhdr_414.clock <= clock rvclkhdr_414.reset <= reset - rvclkhdr_414.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_414.io.en <= _T_1790 @[el2_lib.scala 511:17] - rvclkhdr_414.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_148 : UInt, rvclkhdr_414.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_148 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_414.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_414.io.en <= _T_1790 @[lib.scala 371:17] + rvclkhdr_414.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_148 : UInt, rvclkhdr_414.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_148 <= btb_wr_data @[lib.scala 374:16] node _T_1791 = eq(btb_wr_addr, UInt<8>("h095")) @[ifu_bp_ctl.scala 416:95] node _T_1792 = and(_T_1791, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1793 = bits(_T_1792, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_415 of rvclkhdr_509 @[el2_lib.scala 508:23] + inst rvclkhdr_415 of rvclkhdr_509 @[lib.scala 368:23] rvclkhdr_415.clock <= clock rvclkhdr_415.reset <= reset - rvclkhdr_415.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_415.io.en <= _T_1793 @[el2_lib.scala 511:17] - rvclkhdr_415.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_149 : UInt, rvclkhdr_415.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_149 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_415.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_415.io.en <= _T_1793 @[lib.scala 371:17] + rvclkhdr_415.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_149 : UInt, rvclkhdr_415.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_149 <= btb_wr_data @[lib.scala 374:16] node _T_1794 = eq(btb_wr_addr, UInt<8>("h096")) @[ifu_bp_ctl.scala 416:95] node _T_1795 = and(_T_1794, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1796 = bits(_T_1795, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_416 of rvclkhdr_510 @[el2_lib.scala 508:23] + inst rvclkhdr_416 of rvclkhdr_510 @[lib.scala 368:23] rvclkhdr_416.clock <= clock rvclkhdr_416.reset <= reset - rvclkhdr_416.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_416.io.en <= _T_1796 @[el2_lib.scala 511:17] - rvclkhdr_416.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_150 : UInt, rvclkhdr_416.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_150 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_416.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_416.io.en <= _T_1796 @[lib.scala 371:17] + rvclkhdr_416.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_150 : UInt, rvclkhdr_416.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_150 <= btb_wr_data @[lib.scala 374:16] node _T_1797 = eq(btb_wr_addr, UInt<8>("h097")) @[ifu_bp_ctl.scala 416:95] node _T_1798 = and(_T_1797, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1799 = bits(_T_1798, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_417 of rvclkhdr_511 @[el2_lib.scala 508:23] + inst rvclkhdr_417 of rvclkhdr_511 @[lib.scala 368:23] rvclkhdr_417.clock <= clock rvclkhdr_417.reset <= reset - rvclkhdr_417.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_417.io.en <= _T_1799 @[el2_lib.scala 511:17] - rvclkhdr_417.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_151 : UInt, rvclkhdr_417.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_151 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_417.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_417.io.en <= _T_1799 @[lib.scala 371:17] + rvclkhdr_417.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_151 : UInt, rvclkhdr_417.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_151 <= btb_wr_data @[lib.scala 374:16] node _T_1800 = eq(btb_wr_addr, UInt<8>("h098")) @[ifu_bp_ctl.scala 416:95] node _T_1801 = and(_T_1800, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1802 = bits(_T_1801, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_418 of rvclkhdr_512 @[el2_lib.scala 508:23] + inst rvclkhdr_418 of rvclkhdr_512 @[lib.scala 368:23] rvclkhdr_418.clock <= clock rvclkhdr_418.reset <= reset - rvclkhdr_418.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_418.io.en <= _T_1802 @[el2_lib.scala 511:17] - rvclkhdr_418.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_152 : UInt, rvclkhdr_418.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_152 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_418.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_418.io.en <= _T_1802 @[lib.scala 371:17] + rvclkhdr_418.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_152 : UInt, rvclkhdr_418.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_152 <= btb_wr_data @[lib.scala 374:16] node _T_1803 = eq(btb_wr_addr, UInt<8>("h099")) @[ifu_bp_ctl.scala 416:95] node _T_1804 = and(_T_1803, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1805 = bits(_T_1804, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_419 of rvclkhdr_513 @[el2_lib.scala 508:23] + inst rvclkhdr_419 of rvclkhdr_513 @[lib.scala 368:23] rvclkhdr_419.clock <= clock rvclkhdr_419.reset <= reset - rvclkhdr_419.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_419.io.en <= _T_1805 @[el2_lib.scala 511:17] - rvclkhdr_419.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_153 : UInt, rvclkhdr_419.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_153 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_419.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_419.io.en <= _T_1805 @[lib.scala 371:17] + rvclkhdr_419.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_153 : UInt, rvclkhdr_419.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_153 <= btb_wr_data @[lib.scala 374:16] node _T_1806 = eq(btb_wr_addr, UInt<8>("h09a")) @[ifu_bp_ctl.scala 416:95] node _T_1807 = and(_T_1806, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1808 = bits(_T_1807, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_420 of rvclkhdr_514 @[el2_lib.scala 508:23] + inst rvclkhdr_420 of rvclkhdr_514 @[lib.scala 368:23] rvclkhdr_420.clock <= clock rvclkhdr_420.reset <= reset - rvclkhdr_420.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_420.io.en <= _T_1808 @[el2_lib.scala 511:17] - rvclkhdr_420.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_154 : UInt, rvclkhdr_420.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_154 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_420.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_420.io.en <= _T_1808 @[lib.scala 371:17] + rvclkhdr_420.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_154 : UInt, rvclkhdr_420.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_154 <= btb_wr_data @[lib.scala 374:16] node _T_1809 = eq(btb_wr_addr, UInt<8>("h09b")) @[ifu_bp_ctl.scala 416:95] node _T_1810 = and(_T_1809, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1811 = bits(_T_1810, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_421 of rvclkhdr_515 @[el2_lib.scala 508:23] + inst rvclkhdr_421 of rvclkhdr_515 @[lib.scala 368:23] rvclkhdr_421.clock <= clock rvclkhdr_421.reset <= reset - rvclkhdr_421.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_421.io.en <= _T_1811 @[el2_lib.scala 511:17] - rvclkhdr_421.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_155 : UInt, rvclkhdr_421.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_155 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_421.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_421.io.en <= _T_1811 @[lib.scala 371:17] + rvclkhdr_421.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_155 : UInt, rvclkhdr_421.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_155 <= btb_wr_data @[lib.scala 374:16] node _T_1812 = eq(btb_wr_addr, UInt<8>("h09c")) @[ifu_bp_ctl.scala 416:95] node _T_1813 = and(_T_1812, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1814 = bits(_T_1813, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_422 of rvclkhdr_516 @[el2_lib.scala 508:23] + inst rvclkhdr_422 of rvclkhdr_516 @[lib.scala 368:23] rvclkhdr_422.clock <= clock rvclkhdr_422.reset <= reset - rvclkhdr_422.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_422.io.en <= _T_1814 @[el2_lib.scala 511:17] - rvclkhdr_422.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_156 : UInt, rvclkhdr_422.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_156 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_422.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_422.io.en <= _T_1814 @[lib.scala 371:17] + rvclkhdr_422.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_156 : UInt, rvclkhdr_422.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_156 <= btb_wr_data @[lib.scala 374:16] node _T_1815 = eq(btb_wr_addr, UInt<8>("h09d")) @[ifu_bp_ctl.scala 416:95] node _T_1816 = and(_T_1815, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1817 = bits(_T_1816, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_423 of rvclkhdr_517 @[el2_lib.scala 508:23] + inst rvclkhdr_423 of rvclkhdr_517 @[lib.scala 368:23] rvclkhdr_423.clock <= clock rvclkhdr_423.reset <= reset - rvclkhdr_423.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_423.io.en <= _T_1817 @[el2_lib.scala 511:17] - rvclkhdr_423.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_157 : UInt, rvclkhdr_423.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_157 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_423.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_423.io.en <= _T_1817 @[lib.scala 371:17] + rvclkhdr_423.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_157 : UInt, rvclkhdr_423.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_157 <= btb_wr_data @[lib.scala 374:16] node _T_1818 = eq(btb_wr_addr, UInt<8>("h09e")) @[ifu_bp_ctl.scala 416:95] node _T_1819 = and(_T_1818, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1820 = bits(_T_1819, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_424 of rvclkhdr_518 @[el2_lib.scala 508:23] + inst rvclkhdr_424 of rvclkhdr_518 @[lib.scala 368:23] rvclkhdr_424.clock <= clock rvclkhdr_424.reset <= reset - rvclkhdr_424.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_424.io.en <= _T_1820 @[el2_lib.scala 511:17] - rvclkhdr_424.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_158 : UInt, rvclkhdr_424.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_158 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_424.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_424.io.en <= _T_1820 @[lib.scala 371:17] + rvclkhdr_424.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_158 : UInt, rvclkhdr_424.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_158 <= btb_wr_data @[lib.scala 374:16] node _T_1821 = eq(btb_wr_addr, UInt<8>("h09f")) @[ifu_bp_ctl.scala 416:95] node _T_1822 = and(_T_1821, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1823 = bits(_T_1822, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_425 of rvclkhdr_519 @[el2_lib.scala 508:23] + inst rvclkhdr_425 of rvclkhdr_519 @[lib.scala 368:23] rvclkhdr_425.clock <= clock rvclkhdr_425.reset <= reset - rvclkhdr_425.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_425.io.en <= _T_1823 @[el2_lib.scala 511:17] - rvclkhdr_425.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_159 : UInt, rvclkhdr_425.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_159 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_425.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_425.io.en <= _T_1823 @[lib.scala 371:17] + rvclkhdr_425.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_159 : UInt, rvclkhdr_425.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_159 <= btb_wr_data @[lib.scala 374:16] node _T_1824 = eq(btb_wr_addr, UInt<8>("h0a0")) @[ifu_bp_ctl.scala 416:95] node _T_1825 = and(_T_1824, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1826 = bits(_T_1825, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_426 of rvclkhdr_520 @[el2_lib.scala 508:23] + inst rvclkhdr_426 of rvclkhdr_520 @[lib.scala 368:23] rvclkhdr_426.clock <= clock rvclkhdr_426.reset <= reset - rvclkhdr_426.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_426.io.en <= _T_1826 @[el2_lib.scala 511:17] - rvclkhdr_426.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_160 : UInt, rvclkhdr_426.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_160 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_426.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_426.io.en <= _T_1826 @[lib.scala 371:17] + rvclkhdr_426.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_160 : UInt, rvclkhdr_426.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_160 <= btb_wr_data @[lib.scala 374:16] node _T_1827 = eq(btb_wr_addr, UInt<8>("h0a1")) @[ifu_bp_ctl.scala 416:95] node _T_1828 = and(_T_1827, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1829 = bits(_T_1828, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_427 of rvclkhdr_521 @[el2_lib.scala 508:23] + inst rvclkhdr_427 of rvclkhdr_521 @[lib.scala 368:23] rvclkhdr_427.clock <= clock rvclkhdr_427.reset <= reset - rvclkhdr_427.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_427.io.en <= _T_1829 @[el2_lib.scala 511:17] - rvclkhdr_427.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_161 : UInt, rvclkhdr_427.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_161 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_427.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_427.io.en <= _T_1829 @[lib.scala 371:17] + rvclkhdr_427.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_161 : UInt, rvclkhdr_427.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_161 <= btb_wr_data @[lib.scala 374:16] node _T_1830 = eq(btb_wr_addr, UInt<8>("h0a2")) @[ifu_bp_ctl.scala 416:95] node _T_1831 = and(_T_1830, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1832 = bits(_T_1831, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_428 of rvclkhdr_522 @[el2_lib.scala 508:23] + inst rvclkhdr_428 of rvclkhdr_522 @[lib.scala 368:23] rvclkhdr_428.clock <= clock rvclkhdr_428.reset <= reset - rvclkhdr_428.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_428.io.en <= _T_1832 @[el2_lib.scala 511:17] - rvclkhdr_428.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_162 : UInt, rvclkhdr_428.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_162 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_428.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_428.io.en <= _T_1832 @[lib.scala 371:17] + rvclkhdr_428.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_162 : UInt, rvclkhdr_428.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_162 <= btb_wr_data @[lib.scala 374:16] node _T_1833 = eq(btb_wr_addr, UInt<8>("h0a3")) @[ifu_bp_ctl.scala 416:95] node _T_1834 = and(_T_1833, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1835 = bits(_T_1834, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_429 of rvclkhdr_523 @[el2_lib.scala 508:23] + inst rvclkhdr_429 of rvclkhdr_523 @[lib.scala 368:23] rvclkhdr_429.clock <= clock rvclkhdr_429.reset <= reset - rvclkhdr_429.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_429.io.en <= _T_1835 @[el2_lib.scala 511:17] - rvclkhdr_429.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_163 : UInt, rvclkhdr_429.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_163 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_429.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_429.io.en <= _T_1835 @[lib.scala 371:17] + rvclkhdr_429.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_163 : UInt, rvclkhdr_429.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_163 <= btb_wr_data @[lib.scala 374:16] node _T_1836 = eq(btb_wr_addr, UInt<8>("h0a4")) @[ifu_bp_ctl.scala 416:95] node _T_1837 = and(_T_1836, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1838 = bits(_T_1837, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_430 of rvclkhdr_524 @[el2_lib.scala 508:23] + inst rvclkhdr_430 of rvclkhdr_524 @[lib.scala 368:23] rvclkhdr_430.clock <= clock rvclkhdr_430.reset <= reset - rvclkhdr_430.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_430.io.en <= _T_1838 @[el2_lib.scala 511:17] - rvclkhdr_430.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_164 : UInt, rvclkhdr_430.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_164 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_430.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_430.io.en <= _T_1838 @[lib.scala 371:17] + rvclkhdr_430.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_164 : UInt, rvclkhdr_430.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_164 <= btb_wr_data @[lib.scala 374:16] node _T_1839 = eq(btb_wr_addr, UInt<8>("h0a5")) @[ifu_bp_ctl.scala 416:95] node _T_1840 = and(_T_1839, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1841 = bits(_T_1840, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_431 of rvclkhdr_525 @[el2_lib.scala 508:23] + inst rvclkhdr_431 of rvclkhdr_525 @[lib.scala 368:23] rvclkhdr_431.clock <= clock rvclkhdr_431.reset <= reset - rvclkhdr_431.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_431.io.en <= _T_1841 @[el2_lib.scala 511:17] - rvclkhdr_431.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_165 : UInt, rvclkhdr_431.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_165 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_431.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_431.io.en <= _T_1841 @[lib.scala 371:17] + rvclkhdr_431.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_165 : UInt, rvclkhdr_431.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_165 <= btb_wr_data @[lib.scala 374:16] node _T_1842 = eq(btb_wr_addr, UInt<8>("h0a6")) @[ifu_bp_ctl.scala 416:95] node _T_1843 = and(_T_1842, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1844 = bits(_T_1843, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_432 of rvclkhdr_526 @[el2_lib.scala 508:23] + inst rvclkhdr_432 of rvclkhdr_526 @[lib.scala 368:23] rvclkhdr_432.clock <= clock rvclkhdr_432.reset <= reset - rvclkhdr_432.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_432.io.en <= _T_1844 @[el2_lib.scala 511:17] - rvclkhdr_432.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_166 : UInt, rvclkhdr_432.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_166 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_432.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_432.io.en <= _T_1844 @[lib.scala 371:17] + rvclkhdr_432.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_166 : UInt, rvclkhdr_432.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_166 <= btb_wr_data @[lib.scala 374:16] node _T_1845 = eq(btb_wr_addr, UInt<8>("h0a7")) @[ifu_bp_ctl.scala 416:95] node _T_1846 = and(_T_1845, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1847 = bits(_T_1846, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_433 of rvclkhdr_527 @[el2_lib.scala 508:23] + inst rvclkhdr_433 of rvclkhdr_527 @[lib.scala 368:23] rvclkhdr_433.clock <= clock rvclkhdr_433.reset <= reset - rvclkhdr_433.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_433.io.en <= _T_1847 @[el2_lib.scala 511:17] - rvclkhdr_433.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_167 : UInt, rvclkhdr_433.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_167 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_433.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_433.io.en <= _T_1847 @[lib.scala 371:17] + rvclkhdr_433.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_167 : UInt, rvclkhdr_433.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_167 <= btb_wr_data @[lib.scala 374:16] node _T_1848 = eq(btb_wr_addr, UInt<8>("h0a8")) @[ifu_bp_ctl.scala 416:95] node _T_1849 = and(_T_1848, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1850 = bits(_T_1849, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_434 of rvclkhdr_528 @[el2_lib.scala 508:23] + inst rvclkhdr_434 of rvclkhdr_528 @[lib.scala 368:23] rvclkhdr_434.clock <= clock rvclkhdr_434.reset <= reset - rvclkhdr_434.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_434.io.en <= _T_1850 @[el2_lib.scala 511:17] - rvclkhdr_434.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_168 : UInt, rvclkhdr_434.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_168 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_434.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_434.io.en <= _T_1850 @[lib.scala 371:17] + rvclkhdr_434.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_168 : UInt, rvclkhdr_434.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_168 <= btb_wr_data @[lib.scala 374:16] node _T_1851 = eq(btb_wr_addr, UInt<8>("h0a9")) @[ifu_bp_ctl.scala 416:95] node _T_1852 = and(_T_1851, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1853 = bits(_T_1852, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_435 of rvclkhdr_529 @[el2_lib.scala 508:23] + inst rvclkhdr_435 of rvclkhdr_529 @[lib.scala 368:23] rvclkhdr_435.clock <= clock rvclkhdr_435.reset <= reset - rvclkhdr_435.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_435.io.en <= _T_1853 @[el2_lib.scala 511:17] - rvclkhdr_435.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_169 : UInt, rvclkhdr_435.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_169 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_435.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_435.io.en <= _T_1853 @[lib.scala 371:17] + rvclkhdr_435.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_169 : UInt, rvclkhdr_435.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_169 <= btb_wr_data @[lib.scala 374:16] node _T_1854 = eq(btb_wr_addr, UInt<8>("h0aa")) @[ifu_bp_ctl.scala 416:95] node _T_1855 = and(_T_1854, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1856 = bits(_T_1855, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_436 of rvclkhdr_530 @[el2_lib.scala 508:23] + inst rvclkhdr_436 of rvclkhdr_530 @[lib.scala 368:23] rvclkhdr_436.clock <= clock rvclkhdr_436.reset <= reset - rvclkhdr_436.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_436.io.en <= _T_1856 @[el2_lib.scala 511:17] - rvclkhdr_436.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_170 : UInt, rvclkhdr_436.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_170 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_436.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_436.io.en <= _T_1856 @[lib.scala 371:17] + rvclkhdr_436.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_170 : UInt, rvclkhdr_436.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_170 <= btb_wr_data @[lib.scala 374:16] node _T_1857 = eq(btb_wr_addr, UInt<8>("h0ab")) @[ifu_bp_ctl.scala 416:95] node _T_1858 = and(_T_1857, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1859 = bits(_T_1858, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_437 of rvclkhdr_531 @[el2_lib.scala 508:23] + inst rvclkhdr_437 of rvclkhdr_531 @[lib.scala 368:23] rvclkhdr_437.clock <= clock rvclkhdr_437.reset <= reset - rvclkhdr_437.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_437.io.en <= _T_1859 @[el2_lib.scala 511:17] - rvclkhdr_437.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_171 : UInt, rvclkhdr_437.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_171 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_437.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_437.io.en <= _T_1859 @[lib.scala 371:17] + rvclkhdr_437.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_171 : UInt, rvclkhdr_437.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_171 <= btb_wr_data @[lib.scala 374:16] node _T_1860 = eq(btb_wr_addr, UInt<8>("h0ac")) @[ifu_bp_ctl.scala 416:95] node _T_1861 = and(_T_1860, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1862 = bits(_T_1861, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_438 of rvclkhdr_532 @[el2_lib.scala 508:23] + inst rvclkhdr_438 of rvclkhdr_532 @[lib.scala 368:23] rvclkhdr_438.clock <= clock rvclkhdr_438.reset <= reset - rvclkhdr_438.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_438.io.en <= _T_1862 @[el2_lib.scala 511:17] - rvclkhdr_438.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_172 : UInt, rvclkhdr_438.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_172 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_438.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_438.io.en <= _T_1862 @[lib.scala 371:17] + rvclkhdr_438.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_172 : UInt, rvclkhdr_438.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_172 <= btb_wr_data @[lib.scala 374:16] node _T_1863 = eq(btb_wr_addr, UInt<8>("h0ad")) @[ifu_bp_ctl.scala 416:95] node _T_1864 = and(_T_1863, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1865 = bits(_T_1864, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_439 of rvclkhdr_533 @[el2_lib.scala 508:23] + inst rvclkhdr_439 of rvclkhdr_533 @[lib.scala 368:23] rvclkhdr_439.clock <= clock rvclkhdr_439.reset <= reset - rvclkhdr_439.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_439.io.en <= _T_1865 @[el2_lib.scala 511:17] - rvclkhdr_439.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_173 : UInt, rvclkhdr_439.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_173 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_439.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_439.io.en <= _T_1865 @[lib.scala 371:17] + rvclkhdr_439.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_173 : UInt, rvclkhdr_439.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_173 <= btb_wr_data @[lib.scala 374:16] node _T_1866 = eq(btb_wr_addr, UInt<8>("h0ae")) @[ifu_bp_ctl.scala 416:95] node _T_1867 = and(_T_1866, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1868 = bits(_T_1867, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_440 of rvclkhdr_534 @[el2_lib.scala 508:23] + inst rvclkhdr_440 of rvclkhdr_534 @[lib.scala 368:23] rvclkhdr_440.clock <= clock rvclkhdr_440.reset <= reset - rvclkhdr_440.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_440.io.en <= _T_1868 @[el2_lib.scala 511:17] - rvclkhdr_440.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_174 : UInt, rvclkhdr_440.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_174 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_440.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_440.io.en <= _T_1868 @[lib.scala 371:17] + rvclkhdr_440.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_174 : UInt, rvclkhdr_440.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_174 <= btb_wr_data @[lib.scala 374:16] node _T_1869 = eq(btb_wr_addr, UInt<8>("h0af")) @[ifu_bp_ctl.scala 416:95] node _T_1870 = and(_T_1869, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1871 = bits(_T_1870, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_441 of rvclkhdr_535 @[el2_lib.scala 508:23] + inst rvclkhdr_441 of rvclkhdr_535 @[lib.scala 368:23] rvclkhdr_441.clock <= clock rvclkhdr_441.reset <= reset - rvclkhdr_441.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_441.io.en <= _T_1871 @[el2_lib.scala 511:17] - rvclkhdr_441.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_175 : UInt, rvclkhdr_441.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_175 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_441.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_441.io.en <= _T_1871 @[lib.scala 371:17] + rvclkhdr_441.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_175 : UInt, rvclkhdr_441.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_175 <= btb_wr_data @[lib.scala 374:16] node _T_1872 = eq(btb_wr_addr, UInt<8>("h0b0")) @[ifu_bp_ctl.scala 416:95] node _T_1873 = and(_T_1872, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1874 = bits(_T_1873, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_442 of rvclkhdr_536 @[el2_lib.scala 508:23] + inst rvclkhdr_442 of rvclkhdr_536 @[lib.scala 368:23] rvclkhdr_442.clock <= clock rvclkhdr_442.reset <= reset - rvclkhdr_442.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_442.io.en <= _T_1874 @[el2_lib.scala 511:17] - rvclkhdr_442.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_176 : UInt, rvclkhdr_442.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_176 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_442.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_442.io.en <= _T_1874 @[lib.scala 371:17] + rvclkhdr_442.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_176 : UInt, rvclkhdr_442.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_176 <= btb_wr_data @[lib.scala 374:16] node _T_1875 = eq(btb_wr_addr, UInt<8>("h0b1")) @[ifu_bp_ctl.scala 416:95] node _T_1876 = and(_T_1875, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1877 = bits(_T_1876, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_443 of rvclkhdr_537 @[el2_lib.scala 508:23] + inst rvclkhdr_443 of rvclkhdr_537 @[lib.scala 368:23] rvclkhdr_443.clock <= clock rvclkhdr_443.reset <= reset - rvclkhdr_443.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_443.io.en <= _T_1877 @[el2_lib.scala 511:17] - rvclkhdr_443.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_177 : UInt, rvclkhdr_443.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_177 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_443.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_443.io.en <= _T_1877 @[lib.scala 371:17] + rvclkhdr_443.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_177 : UInt, rvclkhdr_443.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_177 <= btb_wr_data @[lib.scala 374:16] node _T_1878 = eq(btb_wr_addr, UInt<8>("h0b2")) @[ifu_bp_ctl.scala 416:95] node _T_1879 = and(_T_1878, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1880 = bits(_T_1879, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_444 of rvclkhdr_538 @[el2_lib.scala 508:23] + inst rvclkhdr_444 of rvclkhdr_538 @[lib.scala 368:23] rvclkhdr_444.clock <= clock rvclkhdr_444.reset <= reset - rvclkhdr_444.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_444.io.en <= _T_1880 @[el2_lib.scala 511:17] - rvclkhdr_444.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_178 : UInt, rvclkhdr_444.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_178 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_444.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_444.io.en <= _T_1880 @[lib.scala 371:17] + rvclkhdr_444.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_178 : UInt, rvclkhdr_444.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_178 <= btb_wr_data @[lib.scala 374:16] node _T_1881 = eq(btb_wr_addr, UInt<8>("h0b3")) @[ifu_bp_ctl.scala 416:95] node _T_1882 = and(_T_1881, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1883 = bits(_T_1882, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_445 of rvclkhdr_539 @[el2_lib.scala 508:23] + inst rvclkhdr_445 of rvclkhdr_539 @[lib.scala 368:23] rvclkhdr_445.clock <= clock rvclkhdr_445.reset <= reset - rvclkhdr_445.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_445.io.en <= _T_1883 @[el2_lib.scala 511:17] - rvclkhdr_445.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_179 : UInt, rvclkhdr_445.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_179 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_445.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_445.io.en <= _T_1883 @[lib.scala 371:17] + rvclkhdr_445.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_179 : UInt, rvclkhdr_445.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_179 <= btb_wr_data @[lib.scala 374:16] node _T_1884 = eq(btb_wr_addr, UInt<8>("h0b4")) @[ifu_bp_ctl.scala 416:95] node _T_1885 = and(_T_1884, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1886 = bits(_T_1885, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_446 of rvclkhdr_540 @[el2_lib.scala 508:23] + inst rvclkhdr_446 of rvclkhdr_540 @[lib.scala 368:23] rvclkhdr_446.clock <= clock rvclkhdr_446.reset <= reset - rvclkhdr_446.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_446.io.en <= _T_1886 @[el2_lib.scala 511:17] - rvclkhdr_446.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_180 : UInt, rvclkhdr_446.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_180 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_446.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_446.io.en <= _T_1886 @[lib.scala 371:17] + rvclkhdr_446.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_180 : UInt, rvclkhdr_446.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_180 <= btb_wr_data @[lib.scala 374:16] node _T_1887 = eq(btb_wr_addr, UInt<8>("h0b5")) @[ifu_bp_ctl.scala 416:95] node _T_1888 = and(_T_1887, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1889 = bits(_T_1888, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_447 of rvclkhdr_541 @[el2_lib.scala 508:23] + inst rvclkhdr_447 of rvclkhdr_541 @[lib.scala 368:23] rvclkhdr_447.clock <= clock rvclkhdr_447.reset <= reset - rvclkhdr_447.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_447.io.en <= _T_1889 @[el2_lib.scala 511:17] - rvclkhdr_447.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_181 : UInt, rvclkhdr_447.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_181 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_447.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_447.io.en <= _T_1889 @[lib.scala 371:17] + rvclkhdr_447.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_181 : UInt, rvclkhdr_447.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_181 <= btb_wr_data @[lib.scala 374:16] node _T_1890 = eq(btb_wr_addr, UInt<8>("h0b6")) @[ifu_bp_ctl.scala 416:95] node _T_1891 = and(_T_1890, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1892 = bits(_T_1891, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_448 of rvclkhdr_542 @[el2_lib.scala 508:23] + inst rvclkhdr_448 of rvclkhdr_542 @[lib.scala 368:23] rvclkhdr_448.clock <= clock rvclkhdr_448.reset <= reset - rvclkhdr_448.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_448.io.en <= _T_1892 @[el2_lib.scala 511:17] - rvclkhdr_448.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_182 : UInt, rvclkhdr_448.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_182 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_448.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_448.io.en <= _T_1892 @[lib.scala 371:17] + rvclkhdr_448.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_182 : UInt, rvclkhdr_448.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_182 <= btb_wr_data @[lib.scala 374:16] node _T_1893 = eq(btb_wr_addr, UInt<8>("h0b7")) @[ifu_bp_ctl.scala 416:95] node _T_1894 = and(_T_1893, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1895 = bits(_T_1894, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_449 of rvclkhdr_543 @[el2_lib.scala 508:23] + inst rvclkhdr_449 of rvclkhdr_543 @[lib.scala 368:23] rvclkhdr_449.clock <= clock rvclkhdr_449.reset <= reset - rvclkhdr_449.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_449.io.en <= _T_1895 @[el2_lib.scala 511:17] - rvclkhdr_449.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_183 : UInt, rvclkhdr_449.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_183 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_449.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_449.io.en <= _T_1895 @[lib.scala 371:17] + rvclkhdr_449.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_183 : UInt, rvclkhdr_449.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_183 <= btb_wr_data @[lib.scala 374:16] node _T_1896 = eq(btb_wr_addr, UInt<8>("h0b8")) @[ifu_bp_ctl.scala 416:95] node _T_1897 = and(_T_1896, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1898 = bits(_T_1897, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_450 of rvclkhdr_544 @[el2_lib.scala 508:23] + inst rvclkhdr_450 of rvclkhdr_544 @[lib.scala 368:23] rvclkhdr_450.clock <= clock rvclkhdr_450.reset <= reset - rvclkhdr_450.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_450.io.en <= _T_1898 @[el2_lib.scala 511:17] - rvclkhdr_450.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_184 : UInt, rvclkhdr_450.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_184 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_450.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_450.io.en <= _T_1898 @[lib.scala 371:17] + rvclkhdr_450.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_184 : UInt, rvclkhdr_450.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_184 <= btb_wr_data @[lib.scala 374:16] node _T_1899 = eq(btb_wr_addr, UInt<8>("h0b9")) @[ifu_bp_ctl.scala 416:95] node _T_1900 = and(_T_1899, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1901 = bits(_T_1900, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_451 of rvclkhdr_545 @[el2_lib.scala 508:23] + inst rvclkhdr_451 of rvclkhdr_545 @[lib.scala 368:23] rvclkhdr_451.clock <= clock rvclkhdr_451.reset <= reset - rvclkhdr_451.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_451.io.en <= _T_1901 @[el2_lib.scala 511:17] - rvclkhdr_451.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_185 : UInt, rvclkhdr_451.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_185 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_451.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_451.io.en <= _T_1901 @[lib.scala 371:17] + rvclkhdr_451.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_185 : UInt, rvclkhdr_451.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_185 <= btb_wr_data @[lib.scala 374:16] node _T_1902 = eq(btb_wr_addr, UInt<8>("h0ba")) @[ifu_bp_ctl.scala 416:95] node _T_1903 = and(_T_1902, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1904 = bits(_T_1903, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_452 of rvclkhdr_546 @[el2_lib.scala 508:23] + inst rvclkhdr_452 of rvclkhdr_546 @[lib.scala 368:23] rvclkhdr_452.clock <= clock rvclkhdr_452.reset <= reset - rvclkhdr_452.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_452.io.en <= _T_1904 @[el2_lib.scala 511:17] - rvclkhdr_452.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_186 : UInt, rvclkhdr_452.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_186 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_452.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_452.io.en <= _T_1904 @[lib.scala 371:17] + rvclkhdr_452.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_186 : UInt, rvclkhdr_452.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_186 <= btb_wr_data @[lib.scala 374:16] node _T_1905 = eq(btb_wr_addr, UInt<8>("h0bb")) @[ifu_bp_ctl.scala 416:95] node _T_1906 = and(_T_1905, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1907 = bits(_T_1906, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_453 of rvclkhdr_547 @[el2_lib.scala 508:23] + inst rvclkhdr_453 of rvclkhdr_547 @[lib.scala 368:23] rvclkhdr_453.clock <= clock rvclkhdr_453.reset <= reset - rvclkhdr_453.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_453.io.en <= _T_1907 @[el2_lib.scala 511:17] - rvclkhdr_453.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_187 : UInt, rvclkhdr_453.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_187 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_453.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_453.io.en <= _T_1907 @[lib.scala 371:17] + rvclkhdr_453.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_187 : UInt, rvclkhdr_453.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_187 <= btb_wr_data @[lib.scala 374:16] node _T_1908 = eq(btb_wr_addr, UInt<8>("h0bc")) @[ifu_bp_ctl.scala 416:95] node _T_1909 = and(_T_1908, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1910 = bits(_T_1909, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_454 of rvclkhdr_548 @[el2_lib.scala 508:23] + inst rvclkhdr_454 of rvclkhdr_548 @[lib.scala 368:23] rvclkhdr_454.clock <= clock rvclkhdr_454.reset <= reset - rvclkhdr_454.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_454.io.en <= _T_1910 @[el2_lib.scala 511:17] - rvclkhdr_454.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_188 : UInt, rvclkhdr_454.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_188 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_454.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_454.io.en <= _T_1910 @[lib.scala 371:17] + rvclkhdr_454.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_188 : UInt, rvclkhdr_454.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_188 <= btb_wr_data @[lib.scala 374:16] node _T_1911 = eq(btb_wr_addr, UInt<8>("h0bd")) @[ifu_bp_ctl.scala 416:95] node _T_1912 = and(_T_1911, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1913 = bits(_T_1912, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_455 of rvclkhdr_549 @[el2_lib.scala 508:23] + inst rvclkhdr_455 of rvclkhdr_549 @[lib.scala 368:23] rvclkhdr_455.clock <= clock rvclkhdr_455.reset <= reset - rvclkhdr_455.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_455.io.en <= _T_1913 @[el2_lib.scala 511:17] - rvclkhdr_455.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_189 : UInt, rvclkhdr_455.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_189 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_455.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_455.io.en <= _T_1913 @[lib.scala 371:17] + rvclkhdr_455.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_189 : UInt, rvclkhdr_455.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_189 <= btb_wr_data @[lib.scala 374:16] node _T_1914 = eq(btb_wr_addr, UInt<8>("h0be")) @[ifu_bp_ctl.scala 416:95] node _T_1915 = and(_T_1914, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1916 = bits(_T_1915, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_456 of rvclkhdr_550 @[el2_lib.scala 508:23] + inst rvclkhdr_456 of rvclkhdr_550 @[lib.scala 368:23] rvclkhdr_456.clock <= clock rvclkhdr_456.reset <= reset - rvclkhdr_456.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_456.io.en <= _T_1916 @[el2_lib.scala 511:17] - rvclkhdr_456.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_190 : UInt, rvclkhdr_456.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_190 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_456.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_456.io.en <= _T_1916 @[lib.scala 371:17] + rvclkhdr_456.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_190 : UInt, rvclkhdr_456.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_190 <= btb_wr_data @[lib.scala 374:16] node _T_1917 = eq(btb_wr_addr, UInt<8>("h0bf")) @[ifu_bp_ctl.scala 416:95] node _T_1918 = and(_T_1917, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1919 = bits(_T_1918, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_457 of rvclkhdr_551 @[el2_lib.scala 508:23] + inst rvclkhdr_457 of rvclkhdr_551 @[lib.scala 368:23] rvclkhdr_457.clock <= clock rvclkhdr_457.reset <= reset - rvclkhdr_457.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_457.io.en <= _T_1919 @[el2_lib.scala 511:17] - rvclkhdr_457.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_191 : UInt, rvclkhdr_457.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_191 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_457.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_457.io.en <= _T_1919 @[lib.scala 371:17] + rvclkhdr_457.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_191 : UInt, rvclkhdr_457.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_191 <= btb_wr_data @[lib.scala 374:16] node _T_1920 = eq(btb_wr_addr, UInt<8>("h0c0")) @[ifu_bp_ctl.scala 416:95] node _T_1921 = and(_T_1920, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1922 = bits(_T_1921, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_458 of rvclkhdr_552 @[el2_lib.scala 508:23] + inst rvclkhdr_458 of rvclkhdr_552 @[lib.scala 368:23] rvclkhdr_458.clock <= clock rvclkhdr_458.reset <= reset - rvclkhdr_458.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_458.io.en <= _T_1922 @[el2_lib.scala 511:17] - rvclkhdr_458.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_192 : UInt, rvclkhdr_458.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_192 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_458.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_458.io.en <= _T_1922 @[lib.scala 371:17] + rvclkhdr_458.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_192 : UInt, rvclkhdr_458.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_192 <= btb_wr_data @[lib.scala 374:16] node _T_1923 = eq(btb_wr_addr, UInt<8>("h0c1")) @[ifu_bp_ctl.scala 416:95] node _T_1924 = and(_T_1923, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1925 = bits(_T_1924, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_459 of rvclkhdr_553 @[el2_lib.scala 508:23] + inst rvclkhdr_459 of rvclkhdr_553 @[lib.scala 368:23] rvclkhdr_459.clock <= clock rvclkhdr_459.reset <= reset - rvclkhdr_459.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_459.io.en <= _T_1925 @[el2_lib.scala 511:17] - rvclkhdr_459.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_193 : UInt, rvclkhdr_459.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_193 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_459.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_459.io.en <= _T_1925 @[lib.scala 371:17] + rvclkhdr_459.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_193 : UInt, rvclkhdr_459.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_193 <= btb_wr_data @[lib.scala 374:16] node _T_1926 = eq(btb_wr_addr, UInt<8>("h0c2")) @[ifu_bp_ctl.scala 416:95] node _T_1927 = and(_T_1926, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1928 = bits(_T_1927, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_460 of rvclkhdr_554 @[el2_lib.scala 508:23] + inst rvclkhdr_460 of rvclkhdr_554 @[lib.scala 368:23] rvclkhdr_460.clock <= clock rvclkhdr_460.reset <= reset - rvclkhdr_460.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_460.io.en <= _T_1928 @[el2_lib.scala 511:17] - rvclkhdr_460.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_194 : UInt, rvclkhdr_460.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_194 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_460.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_460.io.en <= _T_1928 @[lib.scala 371:17] + rvclkhdr_460.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_194 : UInt, rvclkhdr_460.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_194 <= btb_wr_data @[lib.scala 374:16] node _T_1929 = eq(btb_wr_addr, UInt<8>("h0c3")) @[ifu_bp_ctl.scala 416:95] node _T_1930 = and(_T_1929, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1931 = bits(_T_1930, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_461 of rvclkhdr_555 @[el2_lib.scala 508:23] + inst rvclkhdr_461 of rvclkhdr_555 @[lib.scala 368:23] rvclkhdr_461.clock <= clock rvclkhdr_461.reset <= reset - rvclkhdr_461.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_461.io.en <= _T_1931 @[el2_lib.scala 511:17] - rvclkhdr_461.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_195 : UInt, rvclkhdr_461.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_195 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_461.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_461.io.en <= _T_1931 @[lib.scala 371:17] + rvclkhdr_461.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_195 : UInt, rvclkhdr_461.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_195 <= btb_wr_data @[lib.scala 374:16] node _T_1932 = eq(btb_wr_addr, UInt<8>("h0c4")) @[ifu_bp_ctl.scala 416:95] node _T_1933 = and(_T_1932, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1934 = bits(_T_1933, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_462 of rvclkhdr_556 @[el2_lib.scala 508:23] + inst rvclkhdr_462 of rvclkhdr_556 @[lib.scala 368:23] rvclkhdr_462.clock <= clock rvclkhdr_462.reset <= reset - rvclkhdr_462.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_462.io.en <= _T_1934 @[el2_lib.scala 511:17] - rvclkhdr_462.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_196 : UInt, rvclkhdr_462.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_196 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_462.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_462.io.en <= _T_1934 @[lib.scala 371:17] + rvclkhdr_462.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_196 : UInt, rvclkhdr_462.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_196 <= btb_wr_data @[lib.scala 374:16] node _T_1935 = eq(btb_wr_addr, UInt<8>("h0c5")) @[ifu_bp_ctl.scala 416:95] node _T_1936 = and(_T_1935, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1937 = bits(_T_1936, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_463 of rvclkhdr_557 @[el2_lib.scala 508:23] + inst rvclkhdr_463 of rvclkhdr_557 @[lib.scala 368:23] rvclkhdr_463.clock <= clock rvclkhdr_463.reset <= reset - rvclkhdr_463.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_463.io.en <= _T_1937 @[el2_lib.scala 511:17] - rvclkhdr_463.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_197 : UInt, rvclkhdr_463.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_197 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_463.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_463.io.en <= _T_1937 @[lib.scala 371:17] + rvclkhdr_463.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_197 : UInt, rvclkhdr_463.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_197 <= btb_wr_data @[lib.scala 374:16] node _T_1938 = eq(btb_wr_addr, UInt<8>("h0c6")) @[ifu_bp_ctl.scala 416:95] node _T_1939 = and(_T_1938, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1940 = bits(_T_1939, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_464 of rvclkhdr_558 @[el2_lib.scala 508:23] + inst rvclkhdr_464 of rvclkhdr_558 @[lib.scala 368:23] rvclkhdr_464.clock <= clock rvclkhdr_464.reset <= reset - rvclkhdr_464.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_464.io.en <= _T_1940 @[el2_lib.scala 511:17] - rvclkhdr_464.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_198 : UInt, rvclkhdr_464.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_198 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_464.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_464.io.en <= _T_1940 @[lib.scala 371:17] + rvclkhdr_464.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_198 : UInt, rvclkhdr_464.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_198 <= btb_wr_data @[lib.scala 374:16] node _T_1941 = eq(btb_wr_addr, UInt<8>("h0c7")) @[ifu_bp_ctl.scala 416:95] node _T_1942 = and(_T_1941, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1943 = bits(_T_1942, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_465 of rvclkhdr_559 @[el2_lib.scala 508:23] + inst rvclkhdr_465 of rvclkhdr_559 @[lib.scala 368:23] rvclkhdr_465.clock <= clock rvclkhdr_465.reset <= reset - rvclkhdr_465.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_465.io.en <= _T_1943 @[el2_lib.scala 511:17] - rvclkhdr_465.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_199 : UInt, rvclkhdr_465.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_199 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_465.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_465.io.en <= _T_1943 @[lib.scala 371:17] + rvclkhdr_465.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_199 : UInt, rvclkhdr_465.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_199 <= btb_wr_data @[lib.scala 374:16] node _T_1944 = eq(btb_wr_addr, UInt<8>("h0c8")) @[ifu_bp_ctl.scala 416:95] node _T_1945 = and(_T_1944, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1946 = bits(_T_1945, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_466 of rvclkhdr_560 @[el2_lib.scala 508:23] + inst rvclkhdr_466 of rvclkhdr_560 @[lib.scala 368:23] rvclkhdr_466.clock <= clock rvclkhdr_466.reset <= reset - rvclkhdr_466.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_466.io.en <= _T_1946 @[el2_lib.scala 511:17] - rvclkhdr_466.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_200 : UInt, rvclkhdr_466.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_200 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_466.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_466.io.en <= _T_1946 @[lib.scala 371:17] + rvclkhdr_466.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_200 : UInt, rvclkhdr_466.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_200 <= btb_wr_data @[lib.scala 374:16] node _T_1947 = eq(btb_wr_addr, UInt<8>("h0c9")) @[ifu_bp_ctl.scala 416:95] node _T_1948 = and(_T_1947, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1949 = bits(_T_1948, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_467 of rvclkhdr_561 @[el2_lib.scala 508:23] + inst rvclkhdr_467 of rvclkhdr_561 @[lib.scala 368:23] rvclkhdr_467.clock <= clock rvclkhdr_467.reset <= reset - rvclkhdr_467.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_467.io.en <= _T_1949 @[el2_lib.scala 511:17] - rvclkhdr_467.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_201 : UInt, rvclkhdr_467.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_201 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_467.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_467.io.en <= _T_1949 @[lib.scala 371:17] + rvclkhdr_467.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_201 : UInt, rvclkhdr_467.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_201 <= btb_wr_data @[lib.scala 374:16] node _T_1950 = eq(btb_wr_addr, UInt<8>("h0ca")) @[ifu_bp_ctl.scala 416:95] node _T_1951 = and(_T_1950, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1952 = bits(_T_1951, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_468 of rvclkhdr_562 @[el2_lib.scala 508:23] + inst rvclkhdr_468 of rvclkhdr_562 @[lib.scala 368:23] rvclkhdr_468.clock <= clock rvclkhdr_468.reset <= reset - rvclkhdr_468.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_468.io.en <= _T_1952 @[el2_lib.scala 511:17] - rvclkhdr_468.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_202 : UInt, rvclkhdr_468.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_202 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_468.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_468.io.en <= _T_1952 @[lib.scala 371:17] + rvclkhdr_468.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_202 : UInt, rvclkhdr_468.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_202 <= btb_wr_data @[lib.scala 374:16] node _T_1953 = eq(btb_wr_addr, UInt<8>("h0cb")) @[ifu_bp_ctl.scala 416:95] node _T_1954 = and(_T_1953, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1955 = bits(_T_1954, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_469 of rvclkhdr_563 @[el2_lib.scala 508:23] + inst rvclkhdr_469 of rvclkhdr_563 @[lib.scala 368:23] rvclkhdr_469.clock <= clock rvclkhdr_469.reset <= reset - rvclkhdr_469.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_469.io.en <= _T_1955 @[el2_lib.scala 511:17] - rvclkhdr_469.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_203 : UInt, rvclkhdr_469.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_203 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_469.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_469.io.en <= _T_1955 @[lib.scala 371:17] + rvclkhdr_469.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_203 : UInt, rvclkhdr_469.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_203 <= btb_wr_data @[lib.scala 374:16] node _T_1956 = eq(btb_wr_addr, UInt<8>("h0cc")) @[ifu_bp_ctl.scala 416:95] node _T_1957 = and(_T_1956, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1958 = bits(_T_1957, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_470 of rvclkhdr_564 @[el2_lib.scala 508:23] + inst rvclkhdr_470 of rvclkhdr_564 @[lib.scala 368:23] rvclkhdr_470.clock <= clock rvclkhdr_470.reset <= reset - rvclkhdr_470.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_470.io.en <= _T_1958 @[el2_lib.scala 511:17] - rvclkhdr_470.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_204 : UInt, rvclkhdr_470.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_204 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_470.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_470.io.en <= _T_1958 @[lib.scala 371:17] + rvclkhdr_470.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_204 : UInt, rvclkhdr_470.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_204 <= btb_wr_data @[lib.scala 374:16] node _T_1959 = eq(btb_wr_addr, UInt<8>("h0cd")) @[ifu_bp_ctl.scala 416:95] node _T_1960 = and(_T_1959, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1961 = bits(_T_1960, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_471 of rvclkhdr_565 @[el2_lib.scala 508:23] + inst rvclkhdr_471 of rvclkhdr_565 @[lib.scala 368:23] rvclkhdr_471.clock <= clock rvclkhdr_471.reset <= reset - rvclkhdr_471.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_471.io.en <= _T_1961 @[el2_lib.scala 511:17] - rvclkhdr_471.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_205 : UInt, rvclkhdr_471.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_205 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_471.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_471.io.en <= _T_1961 @[lib.scala 371:17] + rvclkhdr_471.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_205 : UInt, rvclkhdr_471.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_205 <= btb_wr_data @[lib.scala 374:16] node _T_1962 = eq(btb_wr_addr, UInt<8>("h0ce")) @[ifu_bp_ctl.scala 416:95] node _T_1963 = and(_T_1962, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1964 = bits(_T_1963, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_472 of rvclkhdr_566 @[el2_lib.scala 508:23] + inst rvclkhdr_472 of rvclkhdr_566 @[lib.scala 368:23] rvclkhdr_472.clock <= clock rvclkhdr_472.reset <= reset - rvclkhdr_472.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_472.io.en <= _T_1964 @[el2_lib.scala 511:17] - rvclkhdr_472.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_206 : UInt, rvclkhdr_472.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_206 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_472.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_472.io.en <= _T_1964 @[lib.scala 371:17] + rvclkhdr_472.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_206 : UInt, rvclkhdr_472.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_206 <= btb_wr_data @[lib.scala 374:16] node _T_1965 = eq(btb_wr_addr, UInt<8>("h0cf")) @[ifu_bp_ctl.scala 416:95] node _T_1966 = and(_T_1965, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1967 = bits(_T_1966, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_473 of rvclkhdr_567 @[el2_lib.scala 508:23] + inst rvclkhdr_473 of rvclkhdr_567 @[lib.scala 368:23] rvclkhdr_473.clock <= clock rvclkhdr_473.reset <= reset - rvclkhdr_473.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_473.io.en <= _T_1967 @[el2_lib.scala 511:17] - rvclkhdr_473.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_207 : UInt, rvclkhdr_473.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_207 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_473.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_473.io.en <= _T_1967 @[lib.scala 371:17] + rvclkhdr_473.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_207 : UInt, rvclkhdr_473.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_207 <= btb_wr_data @[lib.scala 374:16] node _T_1968 = eq(btb_wr_addr, UInt<8>("h0d0")) @[ifu_bp_ctl.scala 416:95] node _T_1969 = and(_T_1968, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1970 = bits(_T_1969, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_474 of rvclkhdr_568 @[el2_lib.scala 508:23] + inst rvclkhdr_474 of rvclkhdr_568 @[lib.scala 368:23] rvclkhdr_474.clock <= clock rvclkhdr_474.reset <= reset - rvclkhdr_474.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_474.io.en <= _T_1970 @[el2_lib.scala 511:17] - rvclkhdr_474.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_208 : UInt, rvclkhdr_474.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_208 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_474.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_474.io.en <= _T_1970 @[lib.scala 371:17] + rvclkhdr_474.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_208 : UInt, rvclkhdr_474.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_208 <= btb_wr_data @[lib.scala 374:16] node _T_1971 = eq(btb_wr_addr, UInt<8>("h0d1")) @[ifu_bp_ctl.scala 416:95] node _T_1972 = and(_T_1971, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1973 = bits(_T_1972, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_475 of rvclkhdr_569 @[el2_lib.scala 508:23] + inst rvclkhdr_475 of rvclkhdr_569 @[lib.scala 368:23] rvclkhdr_475.clock <= clock rvclkhdr_475.reset <= reset - rvclkhdr_475.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_475.io.en <= _T_1973 @[el2_lib.scala 511:17] - rvclkhdr_475.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_209 : UInt, rvclkhdr_475.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_209 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_475.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_475.io.en <= _T_1973 @[lib.scala 371:17] + rvclkhdr_475.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_209 : UInt, rvclkhdr_475.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_209 <= btb_wr_data @[lib.scala 374:16] node _T_1974 = eq(btb_wr_addr, UInt<8>("h0d2")) @[ifu_bp_ctl.scala 416:95] node _T_1975 = and(_T_1974, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1976 = bits(_T_1975, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_476 of rvclkhdr_570 @[el2_lib.scala 508:23] + inst rvclkhdr_476 of rvclkhdr_570 @[lib.scala 368:23] rvclkhdr_476.clock <= clock rvclkhdr_476.reset <= reset - rvclkhdr_476.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_476.io.en <= _T_1976 @[el2_lib.scala 511:17] - rvclkhdr_476.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_210 : UInt, rvclkhdr_476.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_210 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_476.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_476.io.en <= _T_1976 @[lib.scala 371:17] + rvclkhdr_476.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_210 : UInt, rvclkhdr_476.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_210 <= btb_wr_data @[lib.scala 374:16] node _T_1977 = eq(btb_wr_addr, UInt<8>("h0d3")) @[ifu_bp_ctl.scala 416:95] node _T_1978 = and(_T_1977, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1979 = bits(_T_1978, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_477 of rvclkhdr_571 @[el2_lib.scala 508:23] + inst rvclkhdr_477 of rvclkhdr_571 @[lib.scala 368:23] rvclkhdr_477.clock <= clock rvclkhdr_477.reset <= reset - rvclkhdr_477.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_477.io.en <= _T_1979 @[el2_lib.scala 511:17] - rvclkhdr_477.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_211 : UInt, rvclkhdr_477.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_211 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_477.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_477.io.en <= _T_1979 @[lib.scala 371:17] + rvclkhdr_477.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_211 : UInt, rvclkhdr_477.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_211 <= btb_wr_data @[lib.scala 374:16] node _T_1980 = eq(btb_wr_addr, UInt<8>("h0d4")) @[ifu_bp_ctl.scala 416:95] node _T_1981 = and(_T_1980, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1982 = bits(_T_1981, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_478 of rvclkhdr_572 @[el2_lib.scala 508:23] + inst rvclkhdr_478 of rvclkhdr_572 @[lib.scala 368:23] rvclkhdr_478.clock <= clock rvclkhdr_478.reset <= reset - rvclkhdr_478.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_478.io.en <= _T_1982 @[el2_lib.scala 511:17] - rvclkhdr_478.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_212 : UInt, rvclkhdr_478.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_212 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_478.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_478.io.en <= _T_1982 @[lib.scala 371:17] + rvclkhdr_478.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_212 : UInt, rvclkhdr_478.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_212 <= btb_wr_data @[lib.scala 374:16] node _T_1983 = eq(btb_wr_addr, UInt<8>("h0d5")) @[ifu_bp_ctl.scala 416:95] node _T_1984 = and(_T_1983, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1985 = bits(_T_1984, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_479 of rvclkhdr_573 @[el2_lib.scala 508:23] + inst rvclkhdr_479 of rvclkhdr_573 @[lib.scala 368:23] rvclkhdr_479.clock <= clock rvclkhdr_479.reset <= reset - rvclkhdr_479.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_479.io.en <= _T_1985 @[el2_lib.scala 511:17] - rvclkhdr_479.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_213 : UInt, rvclkhdr_479.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_213 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_479.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_479.io.en <= _T_1985 @[lib.scala 371:17] + rvclkhdr_479.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_213 : UInt, rvclkhdr_479.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_213 <= btb_wr_data @[lib.scala 374:16] node _T_1986 = eq(btb_wr_addr, UInt<8>("h0d6")) @[ifu_bp_ctl.scala 416:95] node _T_1987 = and(_T_1986, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1988 = bits(_T_1987, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_480 of rvclkhdr_574 @[el2_lib.scala 508:23] + inst rvclkhdr_480 of rvclkhdr_574 @[lib.scala 368:23] rvclkhdr_480.clock <= clock rvclkhdr_480.reset <= reset - rvclkhdr_480.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_480.io.en <= _T_1988 @[el2_lib.scala 511:17] - rvclkhdr_480.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_214 : UInt, rvclkhdr_480.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_214 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_480.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_480.io.en <= _T_1988 @[lib.scala 371:17] + rvclkhdr_480.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_214 : UInt, rvclkhdr_480.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_214 <= btb_wr_data @[lib.scala 374:16] node _T_1989 = eq(btb_wr_addr, UInt<8>("h0d7")) @[ifu_bp_ctl.scala 416:95] node _T_1990 = and(_T_1989, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1991 = bits(_T_1990, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_481 of rvclkhdr_575 @[el2_lib.scala 508:23] + inst rvclkhdr_481 of rvclkhdr_575 @[lib.scala 368:23] rvclkhdr_481.clock <= clock rvclkhdr_481.reset <= reset - rvclkhdr_481.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_481.io.en <= _T_1991 @[el2_lib.scala 511:17] - rvclkhdr_481.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_215 : UInt, rvclkhdr_481.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_215 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_481.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_481.io.en <= _T_1991 @[lib.scala 371:17] + rvclkhdr_481.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_215 : UInt, rvclkhdr_481.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_215 <= btb_wr_data @[lib.scala 374:16] node _T_1992 = eq(btb_wr_addr, UInt<8>("h0d8")) @[ifu_bp_ctl.scala 416:95] node _T_1993 = and(_T_1992, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1994 = bits(_T_1993, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_482 of rvclkhdr_576 @[el2_lib.scala 508:23] + inst rvclkhdr_482 of rvclkhdr_576 @[lib.scala 368:23] rvclkhdr_482.clock <= clock rvclkhdr_482.reset <= reset - rvclkhdr_482.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_482.io.en <= _T_1994 @[el2_lib.scala 511:17] - rvclkhdr_482.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_216 : UInt, rvclkhdr_482.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_216 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_482.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_482.io.en <= _T_1994 @[lib.scala 371:17] + rvclkhdr_482.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_216 : UInt, rvclkhdr_482.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_216 <= btb_wr_data @[lib.scala 374:16] node _T_1995 = eq(btb_wr_addr, UInt<8>("h0d9")) @[ifu_bp_ctl.scala 416:95] node _T_1996 = and(_T_1995, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_1997 = bits(_T_1996, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_483 of rvclkhdr_577 @[el2_lib.scala 508:23] + inst rvclkhdr_483 of rvclkhdr_577 @[lib.scala 368:23] rvclkhdr_483.clock <= clock rvclkhdr_483.reset <= reset - rvclkhdr_483.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_483.io.en <= _T_1997 @[el2_lib.scala 511:17] - rvclkhdr_483.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_217 : UInt, rvclkhdr_483.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_217 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_483.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_483.io.en <= _T_1997 @[lib.scala 371:17] + rvclkhdr_483.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_217 : UInt, rvclkhdr_483.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_217 <= btb_wr_data @[lib.scala 374:16] node _T_1998 = eq(btb_wr_addr, UInt<8>("h0da")) @[ifu_bp_ctl.scala 416:95] node _T_1999 = and(_T_1998, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2000 = bits(_T_1999, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_484 of rvclkhdr_578 @[el2_lib.scala 508:23] + inst rvclkhdr_484 of rvclkhdr_578 @[lib.scala 368:23] rvclkhdr_484.clock <= clock rvclkhdr_484.reset <= reset - rvclkhdr_484.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_484.io.en <= _T_2000 @[el2_lib.scala 511:17] - rvclkhdr_484.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_218 : UInt, rvclkhdr_484.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_218 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_484.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_484.io.en <= _T_2000 @[lib.scala 371:17] + rvclkhdr_484.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_218 : UInt, rvclkhdr_484.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_218 <= btb_wr_data @[lib.scala 374:16] node _T_2001 = eq(btb_wr_addr, UInt<8>("h0db")) @[ifu_bp_ctl.scala 416:95] node _T_2002 = and(_T_2001, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2003 = bits(_T_2002, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_485 of rvclkhdr_579 @[el2_lib.scala 508:23] + inst rvclkhdr_485 of rvclkhdr_579 @[lib.scala 368:23] rvclkhdr_485.clock <= clock rvclkhdr_485.reset <= reset - rvclkhdr_485.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_485.io.en <= _T_2003 @[el2_lib.scala 511:17] - rvclkhdr_485.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_219 : UInt, rvclkhdr_485.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_219 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_485.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_485.io.en <= _T_2003 @[lib.scala 371:17] + rvclkhdr_485.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_219 : UInt, rvclkhdr_485.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_219 <= btb_wr_data @[lib.scala 374:16] node _T_2004 = eq(btb_wr_addr, UInt<8>("h0dc")) @[ifu_bp_ctl.scala 416:95] node _T_2005 = and(_T_2004, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2006 = bits(_T_2005, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_486 of rvclkhdr_580 @[el2_lib.scala 508:23] + inst rvclkhdr_486 of rvclkhdr_580 @[lib.scala 368:23] rvclkhdr_486.clock <= clock rvclkhdr_486.reset <= reset - rvclkhdr_486.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_486.io.en <= _T_2006 @[el2_lib.scala 511:17] - rvclkhdr_486.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_220 : UInt, rvclkhdr_486.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_220 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_486.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_486.io.en <= _T_2006 @[lib.scala 371:17] + rvclkhdr_486.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_220 : UInt, rvclkhdr_486.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_220 <= btb_wr_data @[lib.scala 374:16] node _T_2007 = eq(btb_wr_addr, UInt<8>("h0dd")) @[ifu_bp_ctl.scala 416:95] node _T_2008 = and(_T_2007, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2009 = bits(_T_2008, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_487 of rvclkhdr_581 @[el2_lib.scala 508:23] + inst rvclkhdr_487 of rvclkhdr_581 @[lib.scala 368:23] rvclkhdr_487.clock <= clock rvclkhdr_487.reset <= reset - rvclkhdr_487.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_487.io.en <= _T_2009 @[el2_lib.scala 511:17] - rvclkhdr_487.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_221 : UInt, rvclkhdr_487.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_221 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_487.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_487.io.en <= _T_2009 @[lib.scala 371:17] + rvclkhdr_487.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_221 : UInt, rvclkhdr_487.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_221 <= btb_wr_data @[lib.scala 374:16] node _T_2010 = eq(btb_wr_addr, UInt<8>("h0de")) @[ifu_bp_ctl.scala 416:95] node _T_2011 = and(_T_2010, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2012 = bits(_T_2011, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_488 of rvclkhdr_582 @[el2_lib.scala 508:23] + inst rvclkhdr_488 of rvclkhdr_582 @[lib.scala 368:23] rvclkhdr_488.clock <= clock rvclkhdr_488.reset <= reset - rvclkhdr_488.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_488.io.en <= _T_2012 @[el2_lib.scala 511:17] - rvclkhdr_488.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_222 : UInt, rvclkhdr_488.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_222 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_488.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_488.io.en <= _T_2012 @[lib.scala 371:17] + rvclkhdr_488.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_222 : UInt, rvclkhdr_488.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_222 <= btb_wr_data @[lib.scala 374:16] node _T_2013 = eq(btb_wr_addr, UInt<8>("h0df")) @[ifu_bp_ctl.scala 416:95] node _T_2014 = and(_T_2013, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2015 = bits(_T_2014, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_489 of rvclkhdr_583 @[el2_lib.scala 508:23] + inst rvclkhdr_489 of rvclkhdr_583 @[lib.scala 368:23] rvclkhdr_489.clock <= clock rvclkhdr_489.reset <= reset - rvclkhdr_489.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_489.io.en <= _T_2015 @[el2_lib.scala 511:17] - rvclkhdr_489.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_223 : UInt, rvclkhdr_489.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_223 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_489.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_489.io.en <= _T_2015 @[lib.scala 371:17] + rvclkhdr_489.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_223 : UInt, rvclkhdr_489.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_223 <= btb_wr_data @[lib.scala 374:16] node _T_2016 = eq(btb_wr_addr, UInt<8>("h0e0")) @[ifu_bp_ctl.scala 416:95] node _T_2017 = and(_T_2016, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2018 = bits(_T_2017, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_490 of rvclkhdr_584 @[el2_lib.scala 508:23] + inst rvclkhdr_490 of rvclkhdr_584 @[lib.scala 368:23] rvclkhdr_490.clock <= clock rvclkhdr_490.reset <= reset - rvclkhdr_490.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_490.io.en <= _T_2018 @[el2_lib.scala 511:17] - rvclkhdr_490.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_224 : UInt, rvclkhdr_490.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_224 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_490.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_490.io.en <= _T_2018 @[lib.scala 371:17] + rvclkhdr_490.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_224 : UInt, rvclkhdr_490.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_224 <= btb_wr_data @[lib.scala 374:16] node _T_2019 = eq(btb_wr_addr, UInt<8>("h0e1")) @[ifu_bp_ctl.scala 416:95] node _T_2020 = and(_T_2019, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2021 = bits(_T_2020, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_491 of rvclkhdr_585 @[el2_lib.scala 508:23] + inst rvclkhdr_491 of rvclkhdr_585 @[lib.scala 368:23] rvclkhdr_491.clock <= clock rvclkhdr_491.reset <= reset - rvclkhdr_491.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_491.io.en <= _T_2021 @[el2_lib.scala 511:17] - rvclkhdr_491.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_225 : UInt, rvclkhdr_491.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_225 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_491.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_491.io.en <= _T_2021 @[lib.scala 371:17] + rvclkhdr_491.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_225 : UInt, rvclkhdr_491.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_225 <= btb_wr_data @[lib.scala 374:16] node _T_2022 = eq(btb_wr_addr, UInt<8>("h0e2")) @[ifu_bp_ctl.scala 416:95] node _T_2023 = and(_T_2022, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2024 = bits(_T_2023, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_492 of rvclkhdr_586 @[el2_lib.scala 508:23] + inst rvclkhdr_492 of rvclkhdr_586 @[lib.scala 368:23] rvclkhdr_492.clock <= clock rvclkhdr_492.reset <= reset - rvclkhdr_492.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_492.io.en <= _T_2024 @[el2_lib.scala 511:17] - rvclkhdr_492.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_226 : UInt, rvclkhdr_492.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_226 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_492.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_492.io.en <= _T_2024 @[lib.scala 371:17] + rvclkhdr_492.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_226 : UInt, rvclkhdr_492.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_226 <= btb_wr_data @[lib.scala 374:16] node _T_2025 = eq(btb_wr_addr, UInt<8>("h0e3")) @[ifu_bp_ctl.scala 416:95] node _T_2026 = and(_T_2025, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2027 = bits(_T_2026, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_493 of rvclkhdr_587 @[el2_lib.scala 508:23] + inst rvclkhdr_493 of rvclkhdr_587 @[lib.scala 368:23] rvclkhdr_493.clock <= clock rvclkhdr_493.reset <= reset - rvclkhdr_493.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_493.io.en <= _T_2027 @[el2_lib.scala 511:17] - rvclkhdr_493.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_227 : UInt, rvclkhdr_493.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_227 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_493.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_493.io.en <= _T_2027 @[lib.scala 371:17] + rvclkhdr_493.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_227 : UInt, rvclkhdr_493.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_227 <= btb_wr_data @[lib.scala 374:16] node _T_2028 = eq(btb_wr_addr, UInt<8>("h0e4")) @[ifu_bp_ctl.scala 416:95] node _T_2029 = and(_T_2028, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2030 = bits(_T_2029, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_494 of rvclkhdr_588 @[el2_lib.scala 508:23] + inst rvclkhdr_494 of rvclkhdr_588 @[lib.scala 368:23] rvclkhdr_494.clock <= clock rvclkhdr_494.reset <= reset - rvclkhdr_494.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_494.io.en <= _T_2030 @[el2_lib.scala 511:17] - rvclkhdr_494.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_228 : UInt, rvclkhdr_494.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_228 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_494.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_494.io.en <= _T_2030 @[lib.scala 371:17] + rvclkhdr_494.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_228 : UInt, rvclkhdr_494.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_228 <= btb_wr_data @[lib.scala 374:16] node _T_2031 = eq(btb_wr_addr, UInt<8>("h0e5")) @[ifu_bp_ctl.scala 416:95] node _T_2032 = and(_T_2031, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2033 = bits(_T_2032, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_495 of rvclkhdr_589 @[el2_lib.scala 508:23] + inst rvclkhdr_495 of rvclkhdr_589 @[lib.scala 368:23] rvclkhdr_495.clock <= clock rvclkhdr_495.reset <= reset - rvclkhdr_495.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_495.io.en <= _T_2033 @[el2_lib.scala 511:17] - rvclkhdr_495.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_229 : UInt, rvclkhdr_495.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_229 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_495.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_495.io.en <= _T_2033 @[lib.scala 371:17] + rvclkhdr_495.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_229 : UInt, rvclkhdr_495.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_229 <= btb_wr_data @[lib.scala 374:16] node _T_2034 = eq(btb_wr_addr, UInt<8>("h0e6")) @[ifu_bp_ctl.scala 416:95] node _T_2035 = and(_T_2034, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2036 = bits(_T_2035, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_496 of rvclkhdr_590 @[el2_lib.scala 508:23] + inst rvclkhdr_496 of rvclkhdr_590 @[lib.scala 368:23] rvclkhdr_496.clock <= clock rvclkhdr_496.reset <= reset - rvclkhdr_496.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_496.io.en <= _T_2036 @[el2_lib.scala 511:17] - rvclkhdr_496.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_230 : UInt, rvclkhdr_496.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_230 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_496.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_496.io.en <= _T_2036 @[lib.scala 371:17] + rvclkhdr_496.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_230 : UInt, rvclkhdr_496.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_230 <= btb_wr_data @[lib.scala 374:16] node _T_2037 = eq(btb_wr_addr, UInt<8>("h0e7")) @[ifu_bp_ctl.scala 416:95] node _T_2038 = and(_T_2037, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2039 = bits(_T_2038, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_497 of rvclkhdr_591 @[el2_lib.scala 508:23] + inst rvclkhdr_497 of rvclkhdr_591 @[lib.scala 368:23] rvclkhdr_497.clock <= clock rvclkhdr_497.reset <= reset - rvclkhdr_497.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_497.io.en <= _T_2039 @[el2_lib.scala 511:17] - rvclkhdr_497.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_231 : UInt, rvclkhdr_497.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_231 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_497.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_497.io.en <= _T_2039 @[lib.scala 371:17] + rvclkhdr_497.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_231 : UInt, rvclkhdr_497.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_231 <= btb_wr_data @[lib.scala 374:16] node _T_2040 = eq(btb_wr_addr, UInt<8>("h0e8")) @[ifu_bp_ctl.scala 416:95] node _T_2041 = and(_T_2040, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2042 = bits(_T_2041, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_498 of rvclkhdr_592 @[el2_lib.scala 508:23] + inst rvclkhdr_498 of rvclkhdr_592 @[lib.scala 368:23] rvclkhdr_498.clock <= clock rvclkhdr_498.reset <= reset - rvclkhdr_498.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_498.io.en <= _T_2042 @[el2_lib.scala 511:17] - rvclkhdr_498.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_232 : UInt, rvclkhdr_498.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_232 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_498.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_498.io.en <= _T_2042 @[lib.scala 371:17] + rvclkhdr_498.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_232 : UInt, rvclkhdr_498.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_232 <= btb_wr_data @[lib.scala 374:16] node _T_2043 = eq(btb_wr_addr, UInt<8>("h0e9")) @[ifu_bp_ctl.scala 416:95] node _T_2044 = and(_T_2043, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2045 = bits(_T_2044, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_499 of rvclkhdr_593 @[el2_lib.scala 508:23] + inst rvclkhdr_499 of rvclkhdr_593 @[lib.scala 368:23] rvclkhdr_499.clock <= clock rvclkhdr_499.reset <= reset - rvclkhdr_499.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_499.io.en <= _T_2045 @[el2_lib.scala 511:17] - rvclkhdr_499.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_233 : UInt, rvclkhdr_499.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_233 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_499.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_499.io.en <= _T_2045 @[lib.scala 371:17] + rvclkhdr_499.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_233 : UInt, rvclkhdr_499.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_233 <= btb_wr_data @[lib.scala 374:16] node _T_2046 = eq(btb_wr_addr, UInt<8>("h0ea")) @[ifu_bp_ctl.scala 416:95] node _T_2047 = and(_T_2046, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2048 = bits(_T_2047, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_500 of rvclkhdr_594 @[el2_lib.scala 508:23] + inst rvclkhdr_500 of rvclkhdr_594 @[lib.scala 368:23] rvclkhdr_500.clock <= clock rvclkhdr_500.reset <= reset - rvclkhdr_500.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_500.io.en <= _T_2048 @[el2_lib.scala 511:17] - rvclkhdr_500.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_234 : UInt, rvclkhdr_500.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_234 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_500.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_500.io.en <= _T_2048 @[lib.scala 371:17] + rvclkhdr_500.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_234 : UInt, rvclkhdr_500.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_234 <= btb_wr_data @[lib.scala 374:16] node _T_2049 = eq(btb_wr_addr, UInt<8>("h0eb")) @[ifu_bp_ctl.scala 416:95] node _T_2050 = and(_T_2049, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2051 = bits(_T_2050, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_501 of rvclkhdr_595 @[el2_lib.scala 508:23] + inst rvclkhdr_501 of rvclkhdr_595 @[lib.scala 368:23] rvclkhdr_501.clock <= clock rvclkhdr_501.reset <= reset - rvclkhdr_501.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_501.io.en <= _T_2051 @[el2_lib.scala 511:17] - rvclkhdr_501.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_235 : UInt, rvclkhdr_501.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_235 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_501.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_501.io.en <= _T_2051 @[lib.scala 371:17] + rvclkhdr_501.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_235 : UInt, rvclkhdr_501.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_235 <= btb_wr_data @[lib.scala 374:16] node _T_2052 = eq(btb_wr_addr, UInt<8>("h0ec")) @[ifu_bp_ctl.scala 416:95] node _T_2053 = and(_T_2052, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2054 = bits(_T_2053, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_502 of rvclkhdr_596 @[el2_lib.scala 508:23] + inst rvclkhdr_502 of rvclkhdr_596 @[lib.scala 368:23] rvclkhdr_502.clock <= clock rvclkhdr_502.reset <= reset - rvclkhdr_502.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_502.io.en <= _T_2054 @[el2_lib.scala 511:17] - rvclkhdr_502.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_236 : UInt, rvclkhdr_502.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_236 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_502.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_502.io.en <= _T_2054 @[lib.scala 371:17] + rvclkhdr_502.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_236 : UInt, rvclkhdr_502.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_236 <= btb_wr_data @[lib.scala 374:16] node _T_2055 = eq(btb_wr_addr, UInt<8>("h0ed")) @[ifu_bp_ctl.scala 416:95] node _T_2056 = and(_T_2055, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2057 = bits(_T_2056, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_503 of rvclkhdr_597 @[el2_lib.scala 508:23] + inst rvclkhdr_503 of rvclkhdr_597 @[lib.scala 368:23] rvclkhdr_503.clock <= clock rvclkhdr_503.reset <= reset - rvclkhdr_503.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_503.io.en <= _T_2057 @[el2_lib.scala 511:17] - rvclkhdr_503.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_237 : UInt, rvclkhdr_503.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_237 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_503.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_503.io.en <= _T_2057 @[lib.scala 371:17] + rvclkhdr_503.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_237 : UInt, rvclkhdr_503.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_237 <= btb_wr_data @[lib.scala 374:16] node _T_2058 = eq(btb_wr_addr, UInt<8>("h0ee")) @[ifu_bp_ctl.scala 416:95] node _T_2059 = and(_T_2058, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2060 = bits(_T_2059, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_504 of rvclkhdr_598 @[el2_lib.scala 508:23] + inst rvclkhdr_504 of rvclkhdr_598 @[lib.scala 368:23] rvclkhdr_504.clock <= clock rvclkhdr_504.reset <= reset - rvclkhdr_504.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_504.io.en <= _T_2060 @[el2_lib.scala 511:17] - rvclkhdr_504.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_238 : UInt, rvclkhdr_504.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_238 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_504.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_504.io.en <= _T_2060 @[lib.scala 371:17] + rvclkhdr_504.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_238 : UInt, rvclkhdr_504.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_238 <= btb_wr_data @[lib.scala 374:16] node _T_2061 = eq(btb_wr_addr, UInt<8>("h0ef")) @[ifu_bp_ctl.scala 416:95] node _T_2062 = and(_T_2061, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2063 = bits(_T_2062, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_505 of rvclkhdr_599 @[el2_lib.scala 508:23] + inst rvclkhdr_505 of rvclkhdr_599 @[lib.scala 368:23] rvclkhdr_505.clock <= clock rvclkhdr_505.reset <= reset - rvclkhdr_505.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_505.io.en <= _T_2063 @[el2_lib.scala 511:17] - rvclkhdr_505.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_239 : UInt, rvclkhdr_505.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_239 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_505.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_505.io.en <= _T_2063 @[lib.scala 371:17] + rvclkhdr_505.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_239 : UInt, rvclkhdr_505.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_239 <= btb_wr_data @[lib.scala 374:16] node _T_2064 = eq(btb_wr_addr, UInt<8>("h0f0")) @[ifu_bp_ctl.scala 416:95] node _T_2065 = and(_T_2064, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2066 = bits(_T_2065, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_506 of rvclkhdr_600 @[el2_lib.scala 508:23] + inst rvclkhdr_506 of rvclkhdr_600 @[lib.scala 368:23] rvclkhdr_506.clock <= clock rvclkhdr_506.reset <= reset - rvclkhdr_506.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_506.io.en <= _T_2066 @[el2_lib.scala 511:17] - rvclkhdr_506.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_240 : UInt, rvclkhdr_506.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_240 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_506.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_506.io.en <= _T_2066 @[lib.scala 371:17] + rvclkhdr_506.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_240 : UInt, rvclkhdr_506.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_240 <= btb_wr_data @[lib.scala 374:16] node _T_2067 = eq(btb_wr_addr, UInt<8>("h0f1")) @[ifu_bp_ctl.scala 416:95] node _T_2068 = and(_T_2067, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2069 = bits(_T_2068, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_507 of rvclkhdr_601 @[el2_lib.scala 508:23] + inst rvclkhdr_507 of rvclkhdr_601 @[lib.scala 368:23] rvclkhdr_507.clock <= clock rvclkhdr_507.reset <= reset - rvclkhdr_507.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_507.io.en <= _T_2069 @[el2_lib.scala 511:17] - rvclkhdr_507.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_241 : UInt, rvclkhdr_507.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_241 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_507.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_507.io.en <= _T_2069 @[lib.scala 371:17] + rvclkhdr_507.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_241 : UInt, rvclkhdr_507.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_241 <= btb_wr_data @[lib.scala 374:16] node _T_2070 = eq(btb_wr_addr, UInt<8>("h0f2")) @[ifu_bp_ctl.scala 416:95] node _T_2071 = and(_T_2070, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2072 = bits(_T_2071, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_508 of rvclkhdr_602 @[el2_lib.scala 508:23] + inst rvclkhdr_508 of rvclkhdr_602 @[lib.scala 368:23] rvclkhdr_508.clock <= clock rvclkhdr_508.reset <= reset - rvclkhdr_508.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_508.io.en <= _T_2072 @[el2_lib.scala 511:17] - rvclkhdr_508.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_242 : UInt, rvclkhdr_508.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_242 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_508.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_508.io.en <= _T_2072 @[lib.scala 371:17] + rvclkhdr_508.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_242 : UInt, rvclkhdr_508.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_242 <= btb_wr_data @[lib.scala 374:16] node _T_2073 = eq(btb_wr_addr, UInt<8>("h0f3")) @[ifu_bp_ctl.scala 416:95] node _T_2074 = and(_T_2073, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2075 = bits(_T_2074, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_509 of rvclkhdr_603 @[el2_lib.scala 508:23] + inst rvclkhdr_509 of rvclkhdr_603 @[lib.scala 368:23] rvclkhdr_509.clock <= clock rvclkhdr_509.reset <= reset - rvclkhdr_509.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_509.io.en <= _T_2075 @[el2_lib.scala 511:17] - rvclkhdr_509.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_243 : UInt, rvclkhdr_509.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_243 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_509.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_509.io.en <= _T_2075 @[lib.scala 371:17] + rvclkhdr_509.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_243 : UInt, rvclkhdr_509.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_243 <= btb_wr_data @[lib.scala 374:16] node _T_2076 = eq(btb_wr_addr, UInt<8>("h0f4")) @[ifu_bp_ctl.scala 416:95] node _T_2077 = and(_T_2076, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2078 = bits(_T_2077, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_510 of rvclkhdr_604 @[el2_lib.scala 508:23] + inst rvclkhdr_510 of rvclkhdr_604 @[lib.scala 368:23] rvclkhdr_510.clock <= clock rvclkhdr_510.reset <= reset - rvclkhdr_510.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_510.io.en <= _T_2078 @[el2_lib.scala 511:17] - rvclkhdr_510.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_244 : UInt, rvclkhdr_510.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_244 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_510.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_510.io.en <= _T_2078 @[lib.scala 371:17] + rvclkhdr_510.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_244 : UInt, rvclkhdr_510.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_244 <= btb_wr_data @[lib.scala 374:16] node _T_2079 = eq(btb_wr_addr, UInt<8>("h0f5")) @[ifu_bp_ctl.scala 416:95] node _T_2080 = and(_T_2079, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2081 = bits(_T_2080, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_511 of rvclkhdr_605 @[el2_lib.scala 508:23] + inst rvclkhdr_511 of rvclkhdr_605 @[lib.scala 368:23] rvclkhdr_511.clock <= clock rvclkhdr_511.reset <= reset - rvclkhdr_511.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_511.io.en <= _T_2081 @[el2_lib.scala 511:17] - rvclkhdr_511.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_245 : UInt, rvclkhdr_511.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_245 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_511.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_511.io.en <= _T_2081 @[lib.scala 371:17] + rvclkhdr_511.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_245 : UInt, rvclkhdr_511.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_245 <= btb_wr_data @[lib.scala 374:16] node _T_2082 = eq(btb_wr_addr, UInt<8>("h0f6")) @[ifu_bp_ctl.scala 416:95] node _T_2083 = and(_T_2082, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2084 = bits(_T_2083, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_512 of rvclkhdr_606 @[el2_lib.scala 508:23] + inst rvclkhdr_512 of rvclkhdr_606 @[lib.scala 368:23] rvclkhdr_512.clock <= clock rvclkhdr_512.reset <= reset - rvclkhdr_512.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_512.io.en <= _T_2084 @[el2_lib.scala 511:17] - rvclkhdr_512.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_246 : UInt, rvclkhdr_512.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_246 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_512.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_512.io.en <= _T_2084 @[lib.scala 371:17] + rvclkhdr_512.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_246 : UInt, rvclkhdr_512.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_246 <= btb_wr_data @[lib.scala 374:16] node _T_2085 = eq(btb_wr_addr, UInt<8>("h0f7")) @[ifu_bp_ctl.scala 416:95] node _T_2086 = and(_T_2085, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2087 = bits(_T_2086, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_513 of rvclkhdr_607 @[el2_lib.scala 508:23] + inst rvclkhdr_513 of rvclkhdr_607 @[lib.scala 368:23] rvclkhdr_513.clock <= clock rvclkhdr_513.reset <= reset - rvclkhdr_513.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_513.io.en <= _T_2087 @[el2_lib.scala 511:17] - rvclkhdr_513.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_247 : UInt, rvclkhdr_513.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_247 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_513.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_513.io.en <= _T_2087 @[lib.scala 371:17] + rvclkhdr_513.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_247 : UInt, rvclkhdr_513.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_247 <= btb_wr_data @[lib.scala 374:16] node _T_2088 = eq(btb_wr_addr, UInt<8>("h0f8")) @[ifu_bp_ctl.scala 416:95] node _T_2089 = and(_T_2088, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2090 = bits(_T_2089, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_514 of rvclkhdr_608 @[el2_lib.scala 508:23] + inst rvclkhdr_514 of rvclkhdr_608 @[lib.scala 368:23] rvclkhdr_514.clock <= clock rvclkhdr_514.reset <= reset - rvclkhdr_514.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_514.io.en <= _T_2090 @[el2_lib.scala 511:17] - rvclkhdr_514.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_248 : UInt, rvclkhdr_514.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_248 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_514.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_514.io.en <= _T_2090 @[lib.scala 371:17] + rvclkhdr_514.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_248 : UInt, rvclkhdr_514.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_248 <= btb_wr_data @[lib.scala 374:16] node _T_2091 = eq(btb_wr_addr, UInt<8>("h0f9")) @[ifu_bp_ctl.scala 416:95] node _T_2092 = and(_T_2091, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2093 = bits(_T_2092, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_515 of rvclkhdr_609 @[el2_lib.scala 508:23] + inst rvclkhdr_515 of rvclkhdr_609 @[lib.scala 368:23] rvclkhdr_515.clock <= clock rvclkhdr_515.reset <= reset - rvclkhdr_515.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_515.io.en <= _T_2093 @[el2_lib.scala 511:17] - rvclkhdr_515.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_249 : UInt, rvclkhdr_515.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_249 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_515.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_515.io.en <= _T_2093 @[lib.scala 371:17] + rvclkhdr_515.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_249 : UInt, rvclkhdr_515.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_249 <= btb_wr_data @[lib.scala 374:16] node _T_2094 = eq(btb_wr_addr, UInt<8>("h0fa")) @[ifu_bp_ctl.scala 416:95] node _T_2095 = and(_T_2094, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2096 = bits(_T_2095, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_516 of rvclkhdr_610 @[el2_lib.scala 508:23] + inst rvclkhdr_516 of rvclkhdr_610 @[lib.scala 368:23] rvclkhdr_516.clock <= clock rvclkhdr_516.reset <= reset - rvclkhdr_516.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_516.io.en <= _T_2096 @[el2_lib.scala 511:17] - rvclkhdr_516.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_250 : UInt, rvclkhdr_516.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_250 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_516.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_516.io.en <= _T_2096 @[lib.scala 371:17] + rvclkhdr_516.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_250 : UInt, rvclkhdr_516.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_250 <= btb_wr_data @[lib.scala 374:16] node _T_2097 = eq(btb_wr_addr, UInt<8>("h0fb")) @[ifu_bp_ctl.scala 416:95] node _T_2098 = and(_T_2097, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2099 = bits(_T_2098, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_517 of rvclkhdr_611 @[el2_lib.scala 508:23] + inst rvclkhdr_517 of rvclkhdr_611 @[lib.scala 368:23] rvclkhdr_517.clock <= clock rvclkhdr_517.reset <= reset - rvclkhdr_517.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_517.io.en <= _T_2099 @[el2_lib.scala 511:17] - rvclkhdr_517.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_251 : UInt, rvclkhdr_517.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_251 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_517.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_517.io.en <= _T_2099 @[lib.scala 371:17] + rvclkhdr_517.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_251 : UInt, rvclkhdr_517.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_251 <= btb_wr_data @[lib.scala 374:16] node _T_2100 = eq(btb_wr_addr, UInt<8>("h0fc")) @[ifu_bp_ctl.scala 416:95] node _T_2101 = and(_T_2100, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2102 = bits(_T_2101, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_518 of rvclkhdr_612 @[el2_lib.scala 508:23] + inst rvclkhdr_518 of rvclkhdr_612 @[lib.scala 368:23] rvclkhdr_518.clock <= clock rvclkhdr_518.reset <= reset - rvclkhdr_518.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_518.io.en <= _T_2102 @[el2_lib.scala 511:17] - rvclkhdr_518.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_252 : UInt, rvclkhdr_518.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_252 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_518.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_518.io.en <= _T_2102 @[lib.scala 371:17] + rvclkhdr_518.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_252 : UInt, rvclkhdr_518.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_252 <= btb_wr_data @[lib.scala 374:16] node _T_2103 = eq(btb_wr_addr, UInt<8>("h0fd")) @[ifu_bp_ctl.scala 416:95] node _T_2104 = and(_T_2103, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2105 = bits(_T_2104, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_519 of rvclkhdr_613 @[el2_lib.scala 508:23] + inst rvclkhdr_519 of rvclkhdr_613 @[lib.scala 368:23] rvclkhdr_519.clock <= clock rvclkhdr_519.reset <= reset - rvclkhdr_519.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_519.io.en <= _T_2105 @[el2_lib.scala 511:17] - rvclkhdr_519.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_253 : UInt, rvclkhdr_519.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_253 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_519.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_519.io.en <= _T_2105 @[lib.scala 371:17] + rvclkhdr_519.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_253 : UInt, rvclkhdr_519.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_253 <= btb_wr_data @[lib.scala 374:16] node _T_2106 = eq(btb_wr_addr, UInt<8>("h0fe")) @[ifu_bp_ctl.scala 416:95] node _T_2107 = and(_T_2106, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2108 = bits(_T_2107, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_520 of rvclkhdr_614 @[el2_lib.scala 508:23] + inst rvclkhdr_520 of rvclkhdr_614 @[lib.scala 368:23] rvclkhdr_520.clock <= clock rvclkhdr_520.reset <= reset - rvclkhdr_520.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_520.io.en <= _T_2108 @[el2_lib.scala 511:17] - rvclkhdr_520.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_254 : UInt, rvclkhdr_520.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_254 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_520.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_520.io.en <= _T_2108 @[lib.scala 371:17] + rvclkhdr_520.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_254 : UInt, rvclkhdr_520.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_254 <= btb_wr_data @[lib.scala 374:16] node _T_2109 = eq(btb_wr_addr, UInt<8>("h0ff")) @[ifu_bp_ctl.scala 416:95] node _T_2110 = and(_T_2109, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] node _T_2111 = bits(_T_2110, 0, 0) @[ifu_bp_ctl.scala 416:121] - inst rvclkhdr_521 of rvclkhdr_615 @[el2_lib.scala 508:23] + inst rvclkhdr_521 of rvclkhdr_615 @[lib.scala 368:23] rvclkhdr_521.clock <= clock rvclkhdr_521.reset <= reset - rvclkhdr_521.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_521.io.en <= _T_2111 @[el2_lib.scala 511:17] - rvclkhdr_521.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg btb_bank0_rd_data_way1_out_255 : UInt, rvclkhdr_521.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - btb_bank0_rd_data_way1_out_255 <= btb_wr_data @[el2_lib.scala 514:16] + rvclkhdr_521.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_521.io.en <= _T_2111 @[lib.scala 371:17] + rvclkhdr_521.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg btb_bank0_rd_data_way1_out_255 : UInt, rvclkhdr_521.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + btb_bank0_rd_data_way1_out_255 <= btb_wr_data @[lib.scala 374:16] node _T_2112 = eq(btb_rd_addr_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 418:77] node _T_2113 = bits(_T_2112, 0, 0) @[ifu_bp_ctl.scala 418:85] node _T_2114 = eq(btb_rd_addr_f, UInt<1>("h01")) @[ifu_bp_ctl.scala 418:77] @@ -39699,198 +39699,198 @@ circuit quasar_wrapper : _T_6207 <= _T_6206 @[Mux.scala 27:72] btb_bank0_rd_data_way1_p1_f <= _T_6207 @[ifu_bp_ctl.scala 423:31] wire bht_bank_clken : UInt<1>[16][2] @[ifu_bp_ctl.scala 425:28] - inst rvclkhdr_522 of rvclkhdr_616 @[el2_lib.scala 483:22] + inst rvclkhdr_522 of rvclkhdr_616 @[lib.scala 343:22] rvclkhdr_522.clock <= clock rvclkhdr_522.reset <= reset - rvclkhdr_522.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_522.io.en <= bht_bank_clken[0][0] @[el2_lib.scala 485:16] - rvclkhdr_522.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_523 of rvclkhdr_617 @[el2_lib.scala 483:22] + rvclkhdr_522.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_522.io.en <= bht_bank_clken[0][0] @[lib.scala 345:16] + rvclkhdr_522.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_523 of rvclkhdr_617 @[lib.scala 343:22] rvclkhdr_523.clock <= clock rvclkhdr_523.reset <= reset - rvclkhdr_523.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_523.io.en <= bht_bank_clken[0][1] @[el2_lib.scala 485:16] - rvclkhdr_523.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_524 of rvclkhdr_618 @[el2_lib.scala 483:22] + rvclkhdr_523.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_523.io.en <= bht_bank_clken[0][1] @[lib.scala 345:16] + rvclkhdr_523.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_524 of rvclkhdr_618 @[lib.scala 343:22] rvclkhdr_524.clock <= clock rvclkhdr_524.reset <= reset - rvclkhdr_524.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_524.io.en <= bht_bank_clken[0][2] @[el2_lib.scala 485:16] - rvclkhdr_524.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_525 of rvclkhdr_619 @[el2_lib.scala 483:22] + rvclkhdr_524.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_524.io.en <= bht_bank_clken[0][2] @[lib.scala 345:16] + rvclkhdr_524.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_525 of rvclkhdr_619 @[lib.scala 343:22] rvclkhdr_525.clock <= clock rvclkhdr_525.reset <= reset - rvclkhdr_525.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_525.io.en <= bht_bank_clken[0][3] @[el2_lib.scala 485:16] - rvclkhdr_525.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_526 of rvclkhdr_620 @[el2_lib.scala 483:22] + rvclkhdr_525.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_525.io.en <= bht_bank_clken[0][3] @[lib.scala 345:16] + rvclkhdr_525.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_526 of rvclkhdr_620 @[lib.scala 343:22] rvclkhdr_526.clock <= clock rvclkhdr_526.reset <= reset - rvclkhdr_526.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_526.io.en <= bht_bank_clken[0][4] @[el2_lib.scala 485:16] - rvclkhdr_526.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_527 of rvclkhdr_621 @[el2_lib.scala 483:22] + rvclkhdr_526.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_526.io.en <= bht_bank_clken[0][4] @[lib.scala 345:16] + rvclkhdr_526.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_527 of rvclkhdr_621 @[lib.scala 343:22] rvclkhdr_527.clock <= clock rvclkhdr_527.reset <= reset - rvclkhdr_527.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_527.io.en <= bht_bank_clken[0][5] @[el2_lib.scala 485:16] - rvclkhdr_527.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_528 of rvclkhdr_622 @[el2_lib.scala 483:22] + rvclkhdr_527.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_527.io.en <= bht_bank_clken[0][5] @[lib.scala 345:16] + rvclkhdr_527.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_528 of rvclkhdr_622 @[lib.scala 343:22] rvclkhdr_528.clock <= clock rvclkhdr_528.reset <= reset - rvclkhdr_528.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_528.io.en <= bht_bank_clken[0][6] @[el2_lib.scala 485:16] - rvclkhdr_528.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_529 of rvclkhdr_623 @[el2_lib.scala 483:22] + rvclkhdr_528.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_528.io.en <= bht_bank_clken[0][6] @[lib.scala 345:16] + rvclkhdr_528.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_529 of rvclkhdr_623 @[lib.scala 343:22] rvclkhdr_529.clock <= clock rvclkhdr_529.reset <= reset - rvclkhdr_529.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_529.io.en <= bht_bank_clken[0][7] @[el2_lib.scala 485:16] - rvclkhdr_529.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_530 of rvclkhdr_624 @[el2_lib.scala 483:22] + rvclkhdr_529.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_529.io.en <= bht_bank_clken[0][7] @[lib.scala 345:16] + rvclkhdr_529.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_530 of rvclkhdr_624 @[lib.scala 343:22] rvclkhdr_530.clock <= clock rvclkhdr_530.reset <= reset - rvclkhdr_530.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_530.io.en <= bht_bank_clken[0][8] @[el2_lib.scala 485:16] - rvclkhdr_530.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_531 of rvclkhdr_625 @[el2_lib.scala 483:22] + rvclkhdr_530.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_530.io.en <= bht_bank_clken[0][8] @[lib.scala 345:16] + rvclkhdr_530.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_531 of rvclkhdr_625 @[lib.scala 343:22] rvclkhdr_531.clock <= clock rvclkhdr_531.reset <= reset - rvclkhdr_531.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_531.io.en <= bht_bank_clken[0][9] @[el2_lib.scala 485:16] - rvclkhdr_531.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_532 of rvclkhdr_626 @[el2_lib.scala 483:22] + rvclkhdr_531.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_531.io.en <= bht_bank_clken[0][9] @[lib.scala 345:16] + rvclkhdr_531.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_532 of rvclkhdr_626 @[lib.scala 343:22] rvclkhdr_532.clock <= clock rvclkhdr_532.reset <= reset - rvclkhdr_532.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_532.io.en <= bht_bank_clken[0][10] @[el2_lib.scala 485:16] - rvclkhdr_532.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_533 of rvclkhdr_627 @[el2_lib.scala 483:22] + rvclkhdr_532.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_532.io.en <= bht_bank_clken[0][10] @[lib.scala 345:16] + rvclkhdr_532.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_533 of rvclkhdr_627 @[lib.scala 343:22] rvclkhdr_533.clock <= clock rvclkhdr_533.reset <= reset - rvclkhdr_533.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_533.io.en <= bht_bank_clken[0][11] @[el2_lib.scala 485:16] - rvclkhdr_533.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_534 of rvclkhdr_628 @[el2_lib.scala 483:22] + rvclkhdr_533.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_533.io.en <= bht_bank_clken[0][11] @[lib.scala 345:16] + rvclkhdr_533.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_534 of rvclkhdr_628 @[lib.scala 343:22] rvclkhdr_534.clock <= clock rvclkhdr_534.reset <= reset - rvclkhdr_534.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_534.io.en <= bht_bank_clken[0][12] @[el2_lib.scala 485:16] - rvclkhdr_534.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_535 of rvclkhdr_629 @[el2_lib.scala 483:22] + rvclkhdr_534.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_534.io.en <= bht_bank_clken[0][12] @[lib.scala 345:16] + rvclkhdr_534.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_535 of rvclkhdr_629 @[lib.scala 343:22] rvclkhdr_535.clock <= clock rvclkhdr_535.reset <= reset - rvclkhdr_535.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_535.io.en <= bht_bank_clken[0][13] @[el2_lib.scala 485:16] - rvclkhdr_535.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_536 of rvclkhdr_630 @[el2_lib.scala 483:22] + rvclkhdr_535.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_535.io.en <= bht_bank_clken[0][13] @[lib.scala 345:16] + rvclkhdr_535.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_536 of rvclkhdr_630 @[lib.scala 343:22] rvclkhdr_536.clock <= clock rvclkhdr_536.reset <= reset - rvclkhdr_536.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_536.io.en <= bht_bank_clken[0][14] @[el2_lib.scala 485:16] - rvclkhdr_536.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_537 of rvclkhdr_631 @[el2_lib.scala 483:22] + rvclkhdr_536.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_536.io.en <= bht_bank_clken[0][14] @[lib.scala 345:16] + rvclkhdr_536.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_537 of rvclkhdr_631 @[lib.scala 343:22] rvclkhdr_537.clock <= clock rvclkhdr_537.reset <= reset - rvclkhdr_537.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_537.io.en <= bht_bank_clken[0][15] @[el2_lib.scala 485:16] - rvclkhdr_537.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_538 of rvclkhdr_632 @[el2_lib.scala 483:22] + rvclkhdr_537.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_537.io.en <= bht_bank_clken[0][15] @[lib.scala 345:16] + rvclkhdr_537.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_538 of rvclkhdr_632 @[lib.scala 343:22] rvclkhdr_538.clock <= clock rvclkhdr_538.reset <= reset - rvclkhdr_538.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_538.io.en <= bht_bank_clken[1][0] @[el2_lib.scala 485:16] - rvclkhdr_538.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_539 of rvclkhdr_633 @[el2_lib.scala 483:22] + rvclkhdr_538.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_538.io.en <= bht_bank_clken[1][0] @[lib.scala 345:16] + rvclkhdr_538.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_539 of rvclkhdr_633 @[lib.scala 343:22] rvclkhdr_539.clock <= clock rvclkhdr_539.reset <= reset - rvclkhdr_539.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_539.io.en <= bht_bank_clken[1][1] @[el2_lib.scala 485:16] - rvclkhdr_539.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_540 of rvclkhdr_634 @[el2_lib.scala 483:22] + rvclkhdr_539.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_539.io.en <= bht_bank_clken[1][1] @[lib.scala 345:16] + rvclkhdr_539.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_540 of rvclkhdr_634 @[lib.scala 343:22] rvclkhdr_540.clock <= clock rvclkhdr_540.reset <= reset - rvclkhdr_540.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_540.io.en <= bht_bank_clken[1][2] @[el2_lib.scala 485:16] - rvclkhdr_540.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_541 of rvclkhdr_635 @[el2_lib.scala 483:22] + rvclkhdr_540.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_540.io.en <= bht_bank_clken[1][2] @[lib.scala 345:16] + rvclkhdr_540.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_541 of rvclkhdr_635 @[lib.scala 343:22] rvclkhdr_541.clock <= clock rvclkhdr_541.reset <= reset - rvclkhdr_541.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_541.io.en <= bht_bank_clken[1][3] @[el2_lib.scala 485:16] - rvclkhdr_541.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_542 of rvclkhdr_636 @[el2_lib.scala 483:22] + rvclkhdr_541.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_541.io.en <= bht_bank_clken[1][3] @[lib.scala 345:16] + rvclkhdr_541.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_542 of rvclkhdr_636 @[lib.scala 343:22] rvclkhdr_542.clock <= clock rvclkhdr_542.reset <= reset - rvclkhdr_542.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_542.io.en <= bht_bank_clken[1][4] @[el2_lib.scala 485:16] - rvclkhdr_542.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_543 of rvclkhdr_637 @[el2_lib.scala 483:22] + rvclkhdr_542.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_542.io.en <= bht_bank_clken[1][4] @[lib.scala 345:16] + rvclkhdr_542.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_543 of rvclkhdr_637 @[lib.scala 343:22] rvclkhdr_543.clock <= clock rvclkhdr_543.reset <= reset - rvclkhdr_543.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_543.io.en <= bht_bank_clken[1][5] @[el2_lib.scala 485:16] - rvclkhdr_543.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_544 of rvclkhdr_638 @[el2_lib.scala 483:22] + rvclkhdr_543.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_543.io.en <= bht_bank_clken[1][5] @[lib.scala 345:16] + rvclkhdr_543.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_544 of rvclkhdr_638 @[lib.scala 343:22] rvclkhdr_544.clock <= clock rvclkhdr_544.reset <= reset - rvclkhdr_544.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_544.io.en <= bht_bank_clken[1][6] @[el2_lib.scala 485:16] - rvclkhdr_544.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_545 of rvclkhdr_639 @[el2_lib.scala 483:22] + rvclkhdr_544.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_544.io.en <= bht_bank_clken[1][6] @[lib.scala 345:16] + rvclkhdr_544.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_545 of rvclkhdr_639 @[lib.scala 343:22] rvclkhdr_545.clock <= clock rvclkhdr_545.reset <= reset - rvclkhdr_545.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_545.io.en <= bht_bank_clken[1][7] @[el2_lib.scala 485:16] - rvclkhdr_545.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_546 of rvclkhdr_640 @[el2_lib.scala 483:22] + rvclkhdr_545.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_545.io.en <= bht_bank_clken[1][7] @[lib.scala 345:16] + rvclkhdr_545.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_546 of rvclkhdr_640 @[lib.scala 343:22] rvclkhdr_546.clock <= clock rvclkhdr_546.reset <= reset - rvclkhdr_546.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_546.io.en <= bht_bank_clken[1][8] @[el2_lib.scala 485:16] - rvclkhdr_546.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_547 of rvclkhdr_641 @[el2_lib.scala 483:22] + rvclkhdr_546.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_546.io.en <= bht_bank_clken[1][8] @[lib.scala 345:16] + rvclkhdr_546.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_547 of rvclkhdr_641 @[lib.scala 343:22] rvclkhdr_547.clock <= clock rvclkhdr_547.reset <= reset - rvclkhdr_547.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_547.io.en <= bht_bank_clken[1][9] @[el2_lib.scala 485:16] - rvclkhdr_547.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_548 of rvclkhdr_642 @[el2_lib.scala 483:22] + rvclkhdr_547.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_547.io.en <= bht_bank_clken[1][9] @[lib.scala 345:16] + rvclkhdr_547.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_548 of rvclkhdr_642 @[lib.scala 343:22] rvclkhdr_548.clock <= clock rvclkhdr_548.reset <= reset - rvclkhdr_548.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_548.io.en <= bht_bank_clken[1][10] @[el2_lib.scala 485:16] - rvclkhdr_548.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_549 of rvclkhdr_643 @[el2_lib.scala 483:22] + rvclkhdr_548.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_548.io.en <= bht_bank_clken[1][10] @[lib.scala 345:16] + rvclkhdr_548.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_549 of rvclkhdr_643 @[lib.scala 343:22] rvclkhdr_549.clock <= clock rvclkhdr_549.reset <= reset - rvclkhdr_549.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_549.io.en <= bht_bank_clken[1][11] @[el2_lib.scala 485:16] - rvclkhdr_549.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_550 of rvclkhdr_644 @[el2_lib.scala 483:22] + rvclkhdr_549.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_549.io.en <= bht_bank_clken[1][11] @[lib.scala 345:16] + rvclkhdr_549.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_550 of rvclkhdr_644 @[lib.scala 343:22] rvclkhdr_550.clock <= clock rvclkhdr_550.reset <= reset - rvclkhdr_550.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_550.io.en <= bht_bank_clken[1][12] @[el2_lib.scala 485:16] - rvclkhdr_550.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_551 of rvclkhdr_645 @[el2_lib.scala 483:22] + rvclkhdr_550.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_550.io.en <= bht_bank_clken[1][12] @[lib.scala 345:16] + rvclkhdr_550.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_551 of rvclkhdr_645 @[lib.scala 343:22] rvclkhdr_551.clock <= clock rvclkhdr_551.reset <= reset - rvclkhdr_551.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_551.io.en <= bht_bank_clken[1][13] @[el2_lib.scala 485:16] - rvclkhdr_551.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_552 of rvclkhdr_646 @[el2_lib.scala 483:22] + rvclkhdr_551.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_551.io.en <= bht_bank_clken[1][13] @[lib.scala 345:16] + rvclkhdr_551.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_552 of rvclkhdr_646 @[lib.scala 343:22] rvclkhdr_552.clock <= clock rvclkhdr_552.reset <= reset - rvclkhdr_552.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_552.io.en <= bht_bank_clken[1][14] @[el2_lib.scala 485:16] - rvclkhdr_552.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_553 of rvclkhdr_647 @[el2_lib.scala 483:22] + rvclkhdr_552.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_552.io.en <= bht_bank_clken[1][14] @[lib.scala 345:16] + rvclkhdr_552.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_553 of rvclkhdr_647 @[lib.scala 343:22] rvclkhdr_553.clock <= clock rvclkhdr_553.reset <= reset - rvclkhdr_553.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_553.io.en <= bht_bank_clken[1][15] @[el2_lib.scala 485:16] - rvclkhdr_553.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_553.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_553.io.en <= bht_bank_clken[1][15] @[lib.scala 345:16] + rvclkhdr_553.io.scan_mode <= io.scan_mode @[lib.scala 346:23] node _T_6208 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 429:40] node _T_6209 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 429:60] node _T_6210 = eq(_T_6209, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:109] @@ -60266,15 +60266,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_648 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_648 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_649 : output Q : Clock @@ -60290,15 +60290,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_649 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_649 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_650 : output Q : Clock @@ -60314,15 +60314,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_650 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_650 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_651 : output Q : Clock @@ -60338,15 +60338,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_651 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_651 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_652 : output Q : Clock @@ -60362,15 +60362,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_652 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_652 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_653 : output Q : Clock @@ -60386,15 +60386,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_653 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_653 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_654 : output Q : Clock @@ -60410,15 +60410,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_654 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_654 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_655 : output Q : Clock @@ -60434,15 +60434,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_655 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_655 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_656 : output Q : Clock @@ -60458,15 +60458,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_656 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_656 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_657 : output Q : Clock @@ -60482,15 +60482,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_657 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_657 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_658 : output Q : Clock @@ -60506,15 +60506,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_658 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_658 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_659 : output Q : Clock @@ -60530,15 +60530,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_659 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_659 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] module ifu_compress_ctl : input clock : Clock @@ -61910,16 +61910,16 @@ circuit quasar_wrapper : node _T_1276 = cat(_T_1275, _T_1273) @[Cat.scala 29:58] node sjald_1 = cat(_T_1276, _T_1272) @[Cat.scala 29:58] node _T_1277 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 129:32] - wire _T_1278 : UInt<1>[9] @[el2_lib.scala 162:48] - _T_1278[0] <= _T_1277 @[el2_lib.scala 162:48] - _T_1278[1] <= _T_1277 @[el2_lib.scala 162:48] - _T_1278[2] <= _T_1277 @[el2_lib.scala 162:48] - _T_1278[3] <= _T_1277 @[el2_lib.scala 162:48] - _T_1278[4] <= _T_1277 @[el2_lib.scala 162:48] - _T_1278[5] <= _T_1277 @[el2_lib.scala 162:48] - _T_1278[6] <= _T_1277 @[el2_lib.scala 162:48] - _T_1278[7] <= _T_1277 @[el2_lib.scala 162:48] - _T_1278[8] <= _T_1277 @[el2_lib.scala 162:48] + wire _T_1278 : UInt<1>[9] @[lib.scala 12:48] + _T_1278[0] <= _T_1277 @[lib.scala 12:48] + _T_1278[1] <= _T_1277 @[lib.scala 12:48] + _T_1278[2] <= _T_1277 @[lib.scala 12:48] + _T_1278[3] <= _T_1277 @[lib.scala 12:48] + _T_1278[4] <= _T_1277 @[lib.scala 12:48] + _T_1278[5] <= _T_1277 @[lib.scala 12:48] + _T_1278[6] <= _T_1277 @[lib.scala 12:48] + _T_1278[7] <= _T_1277 @[lib.scala 12:48] + _T_1278[8] <= _T_1277 @[lib.scala 12:48] node _T_1279 = cat(_T_1278[0], _T_1278[1]) @[Cat.scala 29:58] node _T_1280 = cat(_T_1279, _T_1278[2]) @[Cat.scala 29:58] node _T_1281 = cat(_T_1280, _T_1278[3]) @[Cat.scala 29:58] @@ -61930,22 +61930,22 @@ circuit quasar_wrapper : node sjald_12 = cat(_T_1285, _T_1278[8]) @[Cat.scala 29:58] node sjald = cat(sjald_12, sjald_1) @[Cat.scala 29:58] node _T_1286 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 131:36] - wire _T_1287 : UInt<1>[15] @[el2_lib.scala 162:48] - _T_1287[0] <= _T_1286 @[el2_lib.scala 162:48] - _T_1287[1] <= _T_1286 @[el2_lib.scala 162:48] - _T_1287[2] <= _T_1286 @[el2_lib.scala 162:48] - _T_1287[3] <= _T_1286 @[el2_lib.scala 162:48] - _T_1287[4] <= _T_1286 @[el2_lib.scala 162:48] - _T_1287[5] <= _T_1286 @[el2_lib.scala 162:48] - _T_1287[6] <= _T_1286 @[el2_lib.scala 162:48] - _T_1287[7] <= _T_1286 @[el2_lib.scala 162:48] - _T_1287[8] <= _T_1286 @[el2_lib.scala 162:48] - _T_1287[9] <= _T_1286 @[el2_lib.scala 162:48] - _T_1287[10] <= _T_1286 @[el2_lib.scala 162:48] - _T_1287[11] <= _T_1286 @[el2_lib.scala 162:48] - _T_1287[12] <= _T_1286 @[el2_lib.scala 162:48] - _T_1287[13] <= _T_1286 @[el2_lib.scala 162:48] - _T_1287[14] <= _T_1286 @[el2_lib.scala 162:48] + wire _T_1287 : UInt<1>[15] @[lib.scala 12:48] + _T_1287[0] <= _T_1286 @[lib.scala 12:48] + _T_1287[1] <= _T_1286 @[lib.scala 12:48] + _T_1287[2] <= _T_1286 @[lib.scala 12:48] + _T_1287[3] <= _T_1286 @[lib.scala 12:48] + _T_1287[4] <= _T_1286 @[lib.scala 12:48] + _T_1287[5] <= _T_1286 @[lib.scala 12:48] + _T_1287[6] <= _T_1286 @[lib.scala 12:48] + _T_1287[7] <= _T_1286 @[lib.scala 12:48] + _T_1287[8] <= _T_1286 @[lib.scala 12:48] + _T_1287[9] <= _T_1286 @[lib.scala 12:48] + _T_1287[10] <= _T_1286 @[lib.scala 12:48] + _T_1287[11] <= _T_1286 @[lib.scala 12:48] + _T_1287[12] <= _T_1286 @[lib.scala 12:48] + _T_1287[13] <= _T_1286 @[lib.scala 12:48] + _T_1287[14] <= _T_1286 @[lib.scala 12:48] node _T_1288 = cat(_T_1287[0], _T_1287[1]) @[Cat.scala 29:58] node _T_1289 = cat(_T_1288, _T_1287[2]) @[Cat.scala 29:58] node _T_1290 = cat(_T_1289, _T_1287[3]) @[Cat.scala 29:58] @@ -61965,14 +61965,14 @@ circuit quasar_wrapper : node _T_1303 = bits(l1, 31, 20) @[ifu_compress_ctl.scala 133:17] node _T_1304 = bits(simm5_0, 0, 0) @[ifu_compress_ctl.scala 134:23] node _T_1305 = bits(simm5d, 5, 5) @[ifu_compress_ctl.scala 134:49] - wire _T_1306 : UInt<1>[7] @[el2_lib.scala 162:48] - _T_1306[0] <= _T_1305 @[el2_lib.scala 162:48] - _T_1306[1] <= _T_1305 @[el2_lib.scala 162:48] - _T_1306[2] <= _T_1305 @[el2_lib.scala 162:48] - _T_1306[3] <= _T_1305 @[el2_lib.scala 162:48] - _T_1306[4] <= _T_1305 @[el2_lib.scala 162:48] - _T_1306[5] <= _T_1305 @[el2_lib.scala 162:48] - _T_1306[6] <= _T_1305 @[el2_lib.scala 162:48] + wire _T_1306 : UInt<1>[7] @[lib.scala 12:48] + _T_1306[0] <= _T_1305 @[lib.scala 12:48] + _T_1306[1] <= _T_1305 @[lib.scala 12:48] + _T_1306[2] <= _T_1305 @[lib.scala 12:48] + _T_1306[3] <= _T_1305 @[lib.scala 12:48] + _T_1306[4] <= _T_1305 @[lib.scala 12:48] + _T_1306[5] <= _T_1305 @[lib.scala 12:48] + _T_1306[6] <= _T_1305 @[lib.scala 12:48] node _T_1307 = cat(_T_1306[0], _T_1306[1]) @[Cat.scala 29:58] node _T_1308 = cat(_T_1307, _T_1306[2]) @[Cat.scala 29:58] node _T_1309 = cat(_T_1308, _T_1306[3]) @[Cat.scala 29:58] @@ -61986,10 +61986,10 @@ circuit quasar_wrapper : node _T_1317 = cat(_T_1316, UInt<2>("h00")) @[Cat.scala 29:58] node _T_1318 = bits(simm9_4, 0, 0) @[ifu_compress_ctl.scala 136:23] node _T_1319 = bits(simm9d, 5, 5) @[ifu_compress_ctl.scala 136:49] - wire _T_1320 : UInt<1>[3] @[el2_lib.scala 162:48] - _T_1320[0] <= _T_1319 @[el2_lib.scala 162:48] - _T_1320[1] <= _T_1319 @[el2_lib.scala 162:48] - _T_1320[2] <= _T_1319 @[el2_lib.scala 162:48] + wire _T_1320 : UInt<1>[3] @[lib.scala 12:48] + _T_1320[0] <= _T_1319 @[lib.scala 12:48] + _T_1320[1] <= _T_1319 @[lib.scala 12:48] + _T_1320[2] <= _T_1319 @[lib.scala 12:48] node _T_1321 = cat(_T_1320[0], _T_1320[1]) @[Cat.scala 29:58] node _T_1322 = cat(_T_1321, _T_1320[2]) @[Cat.scala 29:58] node _T_1323 = bits(simm9d, 4, 0) @[ifu_compress_ctl.scala 136:61] @@ -62072,11 +62072,11 @@ circuit quasar_wrapper : node _T_1392 = bits(l2, 31, 25) @[ifu_compress_ctl.scala 151:17] node _T_1393 = bits(sbroffset8_1, 0, 0) @[ifu_compress_ctl.scala 151:50] node _T_1394 = bits(sbr8d, 8, 8) @[ifu_compress_ctl.scala 151:74] - wire _T_1395 : UInt<1>[4] @[el2_lib.scala 162:48] - _T_1395[0] <= _T_1394 @[el2_lib.scala 162:48] - _T_1395[1] <= _T_1394 @[el2_lib.scala 162:48] - _T_1395[2] <= _T_1394 @[el2_lib.scala 162:48] - _T_1395[3] <= _T_1394 @[el2_lib.scala 162:48] + wire _T_1395 : UInt<1>[4] @[lib.scala 12:48] + _T_1395[0] <= _T_1394 @[lib.scala 12:48] + _T_1395[1] <= _T_1394 @[lib.scala 12:48] + _T_1395[2] <= _T_1394 @[lib.scala 12:48] + _T_1395[3] <= _T_1394 @[lib.scala 12:48] node _T_1396 = cat(_T_1395[0], _T_1395[1]) @[Cat.scala 29:58] node _T_1397 = cat(_T_1396, _T_1395[2]) @[Cat.scala 29:58] node _T_1398 = cat(_T_1397, _T_1395[3]) @[Cat.scala 29:58] @@ -62466,39 +62466,39 @@ circuit quasar_wrapper : node _T_1776 = eq(_T_1775, UInt<1>("h00")) @[ifu_compress_ctl.scala 171:52] node _T_1777 = and(_T_1774, _T_1776) @[ifu_compress_ctl.scala 171:50] node legal = or(_T_1770, _T_1777) @[ifu_compress_ctl.scala 171:30] - wire _T_1778 : UInt<1>[32] @[el2_lib.scala 162:48] - _T_1778[0] <= legal @[el2_lib.scala 162:48] - _T_1778[1] <= legal @[el2_lib.scala 162:48] - _T_1778[2] <= legal @[el2_lib.scala 162:48] - _T_1778[3] <= legal @[el2_lib.scala 162:48] - _T_1778[4] <= legal @[el2_lib.scala 162:48] - _T_1778[5] <= legal @[el2_lib.scala 162:48] - _T_1778[6] <= legal @[el2_lib.scala 162:48] - _T_1778[7] <= legal @[el2_lib.scala 162:48] - _T_1778[8] <= legal @[el2_lib.scala 162:48] - _T_1778[9] <= legal @[el2_lib.scala 162:48] - _T_1778[10] <= legal @[el2_lib.scala 162:48] - _T_1778[11] <= legal @[el2_lib.scala 162:48] - _T_1778[12] <= legal @[el2_lib.scala 162:48] - _T_1778[13] <= legal @[el2_lib.scala 162:48] - _T_1778[14] <= legal @[el2_lib.scala 162:48] - _T_1778[15] <= legal @[el2_lib.scala 162:48] - _T_1778[16] <= legal @[el2_lib.scala 162:48] - _T_1778[17] <= legal @[el2_lib.scala 162:48] - _T_1778[18] <= legal @[el2_lib.scala 162:48] - _T_1778[19] <= legal @[el2_lib.scala 162:48] - _T_1778[20] <= legal @[el2_lib.scala 162:48] - _T_1778[21] <= legal @[el2_lib.scala 162:48] - _T_1778[22] <= legal @[el2_lib.scala 162:48] - _T_1778[23] <= legal @[el2_lib.scala 162:48] - _T_1778[24] <= legal @[el2_lib.scala 162:48] - _T_1778[25] <= legal @[el2_lib.scala 162:48] - _T_1778[26] <= legal @[el2_lib.scala 162:48] - _T_1778[27] <= legal @[el2_lib.scala 162:48] - _T_1778[28] <= legal @[el2_lib.scala 162:48] - _T_1778[29] <= legal @[el2_lib.scala 162:48] - _T_1778[30] <= legal @[el2_lib.scala 162:48] - _T_1778[31] <= legal @[el2_lib.scala 162:48] + wire _T_1778 : UInt<1>[32] @[lib.scala 12:48] + _T_1778[0] <= legal @[lib.scala 12:48] + _T_1778[1] <= legal @[lib.scala 12:48] + _T_1778[2] <= legal @[lib.scala 12:48] + _T_1778[3] <= legal @[lib.scala 12:48] + _T_1778[4] <= legal @[lib.scala 12:48] + _T_1778[5] <= legal @[lib.scala 12:48] + _T_1778[6] <= legal @[lib.scala 12:48] + _T_1778[7] <= legal @[lib.scala 12:48] + _T_1778[8] <= legal @[lib.scala 12:48] + _T_1778[9] <= legal @[lib.scala 12:48] + _T_1778[10] <= legal @[lib.scala 12:48] + _T_1778[11] <= legal @[lib.scala 12:48] + _T_1778[12] <= legal @[lib.scala 12:48] + _T_1778[13] <= legal @[lib.scala 12:48] + _T_1778[14] <= legal @[lib.scala 12:48] + _T_1778[15] <= legal @[lib.scala 12:48] + _T_1778[16] <= legal @[lib.scala 12:48] + _T_1778[17] <= legal @[lib.scala 12:48] + _T_1778[18] <= legal @[lib.scala 12:48] + _T_1778[19] <= legal @[lib.scala 12:48] + _T_1778[20] <= legal @[lib.scala 12:48] + _T_1778[21] <= legal @[lib.scala 12:48] + _T_1778[22] <= legal @[lib.scala 12:48] + _T_1778[23] <= legal @[lib.scala 12:48] + _T_1778[24] <= legal @[lib.scala 12:48] + _T_1778[25] <= legal @[lib.scala 12:48] + _T_1778[26] <= legal @[lib.scala 12:48] + _T_1778[27] <= legal @[lib.scala 12:48] + _T_1778[28] <= legal @[lib.scala 12:48] + _T_1778[29] <= legal @[lib.scala 12:48] + _T_1778[30] <= legal @[lib.scala 12:48] + _T_1778[31] <= legal @[lib.scala 12:48] node _T_1779 = cat(_T_1778[0], _T_1778[1]) @[Cat.scala 29:58] node _T_1780 = cat(_T_1779, _T_1778[2]) @[Cat.scala 29:58] node _T_1781 = cat(_T_1780, _T_1778[3]) @[Cat.scala 29:58] @@ -62660,121 +62660,121 @@ circuit quasar_wrapper : reg q0off : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_aln_ctl.scala 114:48] q0off <= q0off_in @[ifu_aln_ctl.scala 114:48] node _T_4 = bits(f2_wr_en, 0, 0) @[ifu_aln_ctl.scala 116:47] - inst rvclkhdr of rvclkhdr_648 @[el2_lib.scala 508:23] + inst rvclkhdr of rvclkhdr_648 @[lib.scala 368:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr.io.en <= _T_4 @[el2_lib.scala 511:17] - rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg f2pc : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - f2pc <= io.ifu_fetch_pc @[el2_lib.scala 514:16] + rvclkhdr.io.clk <= clock @[lib.scala 370:18] + rvclkhdr.io.en <= _T_4 @[lib.scala 371:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg f2pc : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + f2pc <= io.ifu_fetch_pc @[lib.scala 374:16] node _T_5 = bits(f1_shift_wr_en, 0, 0) @[ifu_aln_ctl.scala 117:45] - inst rvclkhdr_1 of rvclkhdr_649 @[el2_lib.scala 508:23] + inst rvclkhdr_1 of rvclkhdr_649 @[lib.scala 368:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_1.io.en <= _T_5 @[el2_lib.scala 511:17] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg f1pc : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - f1pc <= f1pc_in @[el2_lib.scala 514:16] + rvclkhdr_1.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_1.io.en <= _T_5 @[lib.scala 371:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg f1pc : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + f1pc <= f1pc_in @[lib.scala 374:16] node _T_6 = bits(f0_shift_wr_en, 0, 0) @[ifu_aln_ctl.scala 118:45] - inst rvclkhdr_2 of rvclkhdr_650 @[el2_lib.scala 508:23] + inst rvclkhdr_2 of rvclkhdr_650 @[lib.scala 368:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_2.io.en <= _T_6 @[el2_lib.scala 511:17] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg f0pc : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - f0pc <= f0pc_in @[el2_lib.scala 514:16] + rvclkhdr_2.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_2.io.en <= _T_6 @[lib.scala 371:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg f0pc : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + f0pc <= f0pc_in @[lib.scala 374:16] node _T_7 = bits(qwen, 2, 2) @[ifu_aln_ctl.scala 120:36] - inst rvclkhdr_3 of rvclkhdr_651 @[el2_lib.scala 508:23] + inst rvclkhdr_3 of rvclkhdr_651 @[lib.scala 368:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_3.io.en <= _T_7 @[el2_lib.scala 511:17] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_8 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_8 <= brdata_in @[el2_lib.scala 514:16] + rvclkhdr_3.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_3.io.en <= _T_7 @[lib.scala 371:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_8 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_8 <= brdata_in @[lib.scala 374:16] brdata2 <= _T_8 @[ifu_aln_ctl.scala 120:11] node _T_9 = bits(qwen, 1, 1) @[ifu_aln_ctl.scala 121:36] - inst rvclkhdr_4 of rvclkhdr_652 @[el2_lib.scala 508:23] + inst rvclkhdr_4 of rvclkhdr_652 @[lib.scala 368:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_4.io.en <= _T_9 @[el2_lib.scala 511:17] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_10 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_10 <= brdata_in @[el2_lib.scala 514:16] + rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_4.io.en <= _T_9 @[lib.scala 371:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_10 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_10 <= brdata_in @[lib.scala 374:16] brdata1 <= _T_10 @[ifu_aln_ctl.scala 121:11] node _T_11 = bits(qwen, 0, 0) @[ifu_aln_ctl.scala 122:36] - inst rvclkhdr_5 of rvclkhdr_653 @[el2_lib.scala 508:23] + inst rvclkhdr_5 of rvclkhdr_653 @[lib.scala 368:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_5.io.en <= _T_11 @[el2_lib.scala 511:17] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_12 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_12 <= brdata_in @[el2_lib.scala 514:16] + rvclkhdr_5.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_5.io.en <= _T_11 @[lib.scala 371:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_12 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_12 <= brdata_in @[lib.scala 374:16] brdata0 <= _T_12 @[ifu_aln_ctl.scala 122:11] node _T_13 = bits(qwen, 2, 2) @[ifu_aln_ctl.scala 124:37] - inst rvclkhdr_6 of rvclkhdr_654 @[el2_lib.scala 508:23] + inst rvclkhdr_6 of rvclkhdr_654 @[lib.scala 368:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset - rvclkhdr_6.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_6.io.en <= _T_13 @[el2_lib.scala 511:17] - rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_14 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_14 <= misc_data_in @[el2_lib.scala 514:16] + rvclkhdr_6.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_6.io.en <= _T_13 @[lib.scala 371:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_14 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_14 <= misc_data_in @[lib.scala 374:16] misc2 <= _T_14 @[ifu_aln_ctl.scala 124:9] node _T_15 = bits(qwen, 1, 1) @[ifu_aln_ctl.scala 125:37] - inst rvclkhdr_7 of rvclkhdr_655 @[el2_lib.scala 508:23] + inst rvclkhdr_7 of rvclkhdr_655 @[lib.scala 368:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset - rvclkhdr_7.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_7.io.en <= _T_15 @[el2_lib.scala 511:17] - rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_16 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_16 <= misc_data_in @[el2_lib.scala 514:16] + rvclkhdr_7.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_7.io.en <= _T_15 @[lib.scala 371:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_16 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_16 <= misc_data_in @[lib.scala 374:16] misc1 <= _T_16 @[ifu_aln_ctl.scala 125:9] node _T_17 = bits(qwen, 0, 0) @[ifu_aln_ctl.scala 126:37] - inst rvclkhdr_8 of rvclkhdr_656 @[el2_lib.scala 508:23] + inst rvclkhdr_8 of rvclkhdr_656 @[lib.scala 368:23] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset - rvclkhdr_8.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_8.io.en <= _T_17 @[el2_lib.scala 511:17] - rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_18 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_18 <= misc_data_in @[el2_lib.scala 514:16] + rvclkhdr_8.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_8.io.en <= _T_17 @[lib.scala 371:17] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_18 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_18 <= misc_data_in @[lib.scala 374:16] misc0 <= _T_18 @[ifu_aln_ctl.scala 126:9] node _T_19 = bits(qwen, 2, 2) @[ifu_aln_ctl.scala 128:41] - inst rvclkhdr_9 of rvclkhdr_657 @[el2_lib.scala 508:23] + inst rvclkhdr_9 of rvclkhdr_657 @[lib.scala 368:23] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset - rvclkhdr_9.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_9.io.en <= _T_19 @[el2_lib.scala 511:17] - rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_20 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_20 <= io.ifu_fetch_data_f @[el2_lib.scala 514:16] + rvclkhdr_9.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_9.io.en <= _T_19 @[lib.scala 371:17] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_20 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_20 <= io.ifu_fetch_data_f @[lib.scala 374:16] q2 <= _T_20 @[ifu_aln_ctl.scala 128:6] node _T_21 = bits(qwen, 1, 1) @[ifu_aln_ctl.scala 129:41] - inst rvclkhdr_10 of rvclkhdr_658 @[el2_lib.scala 508:23] + inst rvclkhdr_10 of rvclkhdr_658 @[lib.scala 368:23] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset - rvclkhdr_10.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_10.io.en <= _T_21 @[el2_lib.scala 511:17] - rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_22 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_22 <= io.ifu_fetch_data_f @[el2_lib.scala 514:16] + rvclkhdr_10.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_10.io.en <= _T_21 @[lib.scala 371:17] + rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_22 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_22 <= io.ifu_fetch_data_f @[lib.scala 374:16] q1 <= _T_22 @[ifu_aln_ctl.scala 129:6] node _T_23 = bits(qwen, 0, 0) @[ifu_aln_ctl.scala 130:41] - inst rvclkhdr_11 of rvclkhdr_659 @[el2_lib.scala 508:23] + inst rvclkhdr_11 of rvclkhdr_659 @[lib.scala 368:23] rvclkhdr_11.clock <= clock rvclkhdr_11.reset <= reset - rvclkhdr_11.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_11.io.en <= _T_23 @[el2_lib.scala 511:17] - rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_24 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_24 <= io.ifu_fetch_data_f @[el2_lib.scala 514:16] + rvclkhdr_11.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_11.io.en <= _T_23 @[lib.scala 371:17] + rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_24 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_24 <= io.ifu_fetch_data_f @[lib.scala 374:16] q0 <= _T_24 @[ifu_aln_ctl.scala 130:6] f2_wr_en <= fetch_to_f2 @[ifu_aln_ctl.scala 133:18] node _T_25 = or(fetch_to_f1, shift_f2_f1) @[ifu_aln_ctl.scala 134:33] @@ -63591,34 +63591,34 @@ circuit quasar_wrapper : wire _T_699 : UInt<32> @[Mux.scala 27:72] _T_699 <= _T_698 @[Mux.scala 27:72] io.dec_aln.aln_ib.ifu_i0_instr <= _T_699 @[ifu_aln_ctl.scala 354:34] - node _T_700 = bits(f0pc, 8, 1) @[el2_lib.scala 191:13] - node _T_701 = bits(f0pc, 16, 9) @[el2_lib.scala 191:51] - node _T_702 = xor(_T_700, _T_701) @[el2_lib.scala 191:47] - node _T_703 = bits(f0pc, 24, 17) @[el2_lib.scala 191:89] - node firstpc_hash = xor(_T_702, _T_703) @[el2_lib.scala 191:85] - node _T_704 = bits(secondpc, 8, 1) @[el2_lib.scala 191:13] - node _T_705 = bits(secondpc, 16, 9) @[el2_lib.scala 191:51] - node _T_706 = xor(_T_704, _T_705) @[el2_lib.scala 191:47] - node _T_707 = bits(secondpc, 24, 17) @[el2_lib.scala 191:89] - node secondpc_hash = xor(_T_706, _T_707) @[el2_lib.scala 191:85] - node _T_708 = bits(f0pc, 13, 9) @[el2_lib.scala 182:32] - node _T_709 = bits(f0pc, 18, 14) @[el2_lib.scala 182:32] - node _T_710 = bits(f0pc, 23, 19) @[el2_lib.scala 182:32] - wire _T_711 : UInt<5>[3] @[el2_lib.scala 182:24] - _T_711[0] <= _T_708 @[el2_lib.scala 182:24] - _T_711[1] <= _T_709 @[el2_lib.scala 182:24] - _T_711[2] <= _T_710 @[el2_lib.scala 182:24] - node _T_712 = xor(_T_711[0], _T_711[1]) @[el2_lib.scala 182:111] - node firstbrtag_hash = xor(_T_712, _T_711[2]) @[el2_lib.scala 182:111] - node _T_713 = bits(secondpc, 13, 9) @[el2_lib.scala 182:32] - node _T_714 = bits(secondpc, 18, 14) @[el2_lib.scala 182:32] - node _T_715 = bits(secondpc, 23, 19) @[el2_lib.scala 182:32] - wire _T_716 : UInt<5>[3] @[el2_lib.scala 182:24] - _T_716[0] <= _T_713 @[el2_lib.scala 182:24] - _T_716[1] <= _T_714 @[el2_lib.scala 182:24] - _T_716[2] <= _T_715 @[el2_lib.scala 182:24] - node _T_717 = xor(_T_716[0], _T_716[1]) @[el2_lib.scala 182:111] - node secondbrtag_hash = xor(_T_717, _T_716[2]) @[el2_lib.scala 182:111] + node _T_700 = bits(f0pc, 8, 1) @[lib.scala 51:13] + node _T_701 = bits(f0pc, 16, 9) @[lib.scala 51:51] + node _T_702 = xor(_T_700, _T_701) @[lib.scala 51:47] + node _T_703 = bits(f0pc, 24, 17) @[lib.scala 51:89] + node firstpc_hash = xor(_T_702, _T_703) @[lib.scala 51:85] + node _T_704 = bits(secondpc, 8, 1) @[lib.scala 51:13] + node _T_705 = bits(secondpc, 16, 9) @[lib.scala 51:51] + node _T_706 = xor(_T_704, _T_705) @[lib.scala 51:47] + node _T_707 = bits(secondpc, 24, 17) @[lib.scala 51:89] + node secondpc_hash = xor(_T_706, _T_707) @[lib.scala 51:85] + node _T_708 = bits(f0pc, 13, 9) @[lib.scala 42:32] + node _T_709 = bits(f0pc, 18, 14) @[lib.scala 42:32] + node _T_710 = bits(f0pc, 23, 19) @[lib.scala 42:32] + wire _T_711 : UInt<5>[3] @[lib.scala 42:24] + _T_711[0] <= _T_708 @[lib.scala 42:24] + _T_711[1] <= _T_709 @[lib.scala 42:24] + _T_711[2] <= _T_710 @[lib.scala 42:24] + node _T_712 = xor(_T_711[0], _T_711[1]) @[lib.scala 42:111] + node firstbrtag_hash = xor(_T_712, _T_711[2]) @[lib.scala 42:111] + node _T_713 = bits(secondpc, 13, 9) @[lib.scala 42:32] + node _T_714 = bits(secondpc, 18, 14) @[lib.scala 42:32] + node _T_715 = bits(secondpc, 23, 19) @[lib.scala 42:32] + wire _T_716 : UInt<5>[3] @[lib.scala 42:24] + _T_716[0] <= _T_713 @[lib.scala 42:24] + _T_716[1] <= _T_714 @[lib.scala 42:24] + _T_716[2] <= _T_715 @[lib.scala 42:24] + node _T_717 = xor(_T_716[0], _T_716[1]) @[lib.scala 42:111] + node secondbrtag_hash = xor(_T_717, _T_716[2]) @[lib.scala 42:111] node _T_718 = bits(alignbrend, 0, 0) @[ifu_aln_ctl.scala 365:57] node _T_719 = and(first2B, _T_718) @[ifu_aln_ctl.scala 365:45] node _T_720 = bits(alignbrend, 1, 1) @[ifu_aln_ctl.scala 365:85] @@ -63742,15 +63742,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_660 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_660 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] module ifu_ifc_ctl : input clock : Clock @@ -63980,10 +63980,10 @@ circuit quasar_wrapper : node _T_141 = or(wfm, _T_140) @[ifu_ifc_ctl.scala 130:41] io.dec_ifc.ifu_pmu_fetch_stall <= _T_141 @[ifu_ifc_ctl.scala 130:34] node _T_142 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_143 = bits(_T_142, 31, 28) @[el2_lib.scala 224:25] - node iccm_acc_in_region_bf = eq(_T_143, UInt<4>("h0e")) @[el2_lib.scala 224:47] - node _T_144 = bits(_T_142, 31, 16) @[el2_lib.scala 227:14] - node iccm_acc_in_range_bf = eq(_T_144, UInt<16>("h0ee00")) @[el2_lib.scala 227:29] + node _T_143 = bits(_T_142, 31, 28) @[lib.scala 84:25] + node iccm_acc_in_region_bf = eq(_T_143, UInt<4>("h0e")) @[lib.scala 84:47] + node _T_144 = bits(_T_142, 31, 16) @[lib.scala 87:14] + node iccm_acc_in_range_bf = eq(_T_144, UInt<16>("h0ee00")) @[lib.scala 87:29] io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[ifu_ifc_ctl.scala 137:25] node _T_145 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[ifu_ifc_ctl.scala 138:30] node _T_146 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[ifu_ifc_ctl.scala 139:39] @@ -64011,14 +64011,14 @@ circuit quasar_wrapper : _T_164 <= io.ifc_fetch_req_bf @[ifu_ifc_ctl.scala 145:57] io.ifc_fetch_req_f <= _T_164 @[ifu_ifc_ctl.scala 145:22] node _T_165 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[ifu_ifc_ctl.scala 147:73] - inst rvclkhdr of rvclkhdr_660 @[el2_lib.scala 508:23] + inst rvclkhdr of rvclkhdr_660 @[lib.scala 368:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr.io.en <= _T_165 @[el2_lib.scala 511:17] - rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_166 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_166 <= io.ifc_fetch_addr_bf @[el2_lib.scala 514:16] + rvclkhdr.io.clk <= clock @[lib.scala 370:18] + rvclkhdr.io.en <= _T_165 @[lib.scala 371:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_166 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_166 <= io.ifc_fetch_addr_bf @[lib.scala 374:16] io.ifc_fetch_addr_f <= _T_166 @[ifu_ifc_ctl.scala 147:23] module ifu : @@ -64335,15 +64335,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_661 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_661 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] module dec_dec_ctl : input clock : Clock @@ -66383,15 +66383,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_662 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_662 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_663 : output Q : Clock @@ -66407,15 +66407,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_663 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_663 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_664 : output Q : Clock @@ -66431,15 +66431,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_664 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_664 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_665 : output Q : Clock @@ -66455,15 +66455,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_665 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_665 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_666 : output Q : Clock @@ -66479,15 +66479,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_666 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_666 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_667 : output Q : Clock @@ -66503,15 +66503,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_667 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_667 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_668 : output Q : Clock @@ -66527,15 +66527,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_668 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_668 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_669 : output Q : Clock @@ -66551,15 +66551,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_669 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_669 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_670 : output Q : Clock @@ -66575,15 +66575,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_670 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_670 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_671 : output Q : Clock @@ -66599,15 +66599,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_671 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_671 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_672 : output Q : Clock @@ -66623,15 +66623,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_672 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_672 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_673 : output Q : Clock @@ -66647,15 +66647,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_673 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_673 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_674 : output Q : Clock @@ -66671,15 +66671,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_674 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_674 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_675 : output Q : Clock @@ -66695,15 +66695,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_675 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_675 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_676 : output Q : Clock @@ -66719,15 +66719,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_676 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_676 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_677 : output Q : Clock @@ -66743,15 +66743,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_677 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_677 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_678 : output Q : Clock @@ -66767,15 +66767,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_678 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_678 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_679 : output Q : Clock @@ -66791,15 +66791,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_679 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_679 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_680 : output Q : Clock @@ -66815,15 +66815,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_680 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_680 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] module dec_decode_ctl : input clock : Clock @@ -67023,12 +67023,12 @@ circuit quasar_wrapper : node _T_16 = xor(illegal_lockout_in, illegal_lockout) @[dec_decode_ctl.scala 189:32] node data_gate_en = or(_T_15, _T_16) @[dec_decode_ctl.scala 188:56] node _T_17 = bits(data_gate_en, 0, 0) @[dec_decode_ctl.scala 192:56] - inst rvclkhdr of rvclkhdr_661 @[el2_lib.scala 483:22] + inst rvclkhdr of rvclkhdr_661 @[lib.scala 343:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr.io.en <= _T_17 @[el2_lib.scala 485:16] - rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr.io.clk <= clock @[lib.scala 344:17] + rvclkhdr.io.en <= _T_17 @[lib.scala 345:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] node _T_18 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 196:62] node i0_brp_valid = and(io.dec_i0_brp.valid, _T_18) @[dec_decode_ctl.scala 196:60] io.decode_exu.dec_i0_predict_p_d.bits.misp <= UInt<1>("h00") @[dec_decode_ctl.scala 197:54] @@ -67963,52 +67963,52 @@ circuit quasar_wrapper : csr_imm_x <= i0_dp.csr_imm @[dec_decode_ctl.scala 450:51] node _T_362 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 453:27] node _T_363 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 453:48] - inst rvclkhdr_1 of rvclkhdr_662 @[el2_lib.scala 508:23] + inst rvclkhdr_1 of rvclkhdr_662 @[lib.scala 368:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_1.io.en <= _T_363 @[el2_lib.scala 511:17] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg csrimm_x : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - csrimm_x <= _T_362 @[el2_lib.scala 514:16] + rvclkhdr_1.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_1.io.en <= _T_363 @[lib.scala 371:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg csrimm_x : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + csrimm_x <= _T_362 @[lib.scala 374:16] node _T_364 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 454:62] - inst rvclkhdr_2 of rvclkhdr_663 @[el2_lib.scala 508:23] + inst rvclkhdr_2 of rvclkhdr_663 @[lib.scala 368:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_2.io.en <= _T_364 @[el2_lib.scala 511:17] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg csr_rddata_x : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - csr_rddata_x <= io.dec_csr_rddata_d @[el2_lib.scala 514:16] + rvclkhdr_2.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_2.io.en <= _T_364 @[lib.scala 371:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg csr_rddata_x : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + csr_rddata_x <= io.dec_csr_rddata_d @[lib.scala 374:16] node _T_365 = bits(csr_imm_x, 0, 0) @[dec_decode_ctl.scala 457:15] - wire _T_366 : UInt<1>[27] @[el2_lib.scala 162:48] - _T_366[0] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_366[1] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_366[2] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_366[3] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_366[4] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_366[5] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_366[6] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_366[7] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_366[8] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_366[9] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_366[10] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_366[11] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_366[12] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_366[13] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_366[14] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_366[15] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_366[16] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_366[17] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_366[18] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_366[19] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_366[20] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_366[21] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_366[22] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_366[23] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_366[24] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_366[25] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_366[26] <= UInt<1>("h00") @[el2_lib.scala 162:48] + wire _T_366 : UInt<1>[27] @[lib.scala 12:48] + _T_366[0] <= UInt<1>("h00") @[lib.scala 12:48] + _T_366[1] <= UInt<1>("h00") @[lib.scala 12:48] + _T_366[2] <= UInt<1>("h00") @[lib.scala 12:48] + _T_366[3] <= UInt<1>("h00") @[lib.scala 12:48] + _T_366[4] <= UInt<1>("h00") @[lib.scala 12:48] + _T_366[5] <= UInt<1>("h00") @[lib.scala 12:48] + _T_366[6] <= UInt<1>("h00") @[lib.scala 12:48] + _T_366[7] <= UInt<1>("h00") @[lib.scala 12:48] + _T_366[8] <= UInt<1>("h00") @[lib.scala 12:48] + _T_366[9] <= UInt<1>("h00") @[lib.scala 12:48] + _T_366[10] <= UInt<1>("h00") @[lib.scala 12:48] + _T_366[11] <= UInt<1>("h00") @[lib.scala 12:48] + _T_366[12] <= UInt<1>("h00") @[lib.scala 12:48] + _T_366[13] <= UInt<1>("h00") @[lib.scala 12:48] + _T_366[14] <= UInt<1>("h00") @[lib.scala 12:48] + _T_366[15] <= UInt<1>("h00") @[lib.scala 12:48] + _T_366[16] <= UInt<1>("h00") @[lib.scala 12:48] + _T_366[17] <= UInt<1>("h00") @[lib.scala 12:48] + _T_366[18] <= UInt<1>("h00") @[lib.scala 12:48] + _T_366[19] <= UInt<1>("h00") @[lib.scala 12:48] + _T_366[20] <= UInt<1>("h00") @[lib.scala 12:48] + _T_366[21] <= UInt<1>("h00") @[lib.scala 12:48] + _T_366[22] <= UInt<1>("h00") @[lib.scala 12:48] + _T_366[23] <= UInt<1>("h00") @[lib.scala 12:48] + _T_366[24] <= UInt<1>("h00") @[lib.scala 12:48] + _T_366[25] <= UInt<1>("h00") @[lib.scala 12:48] + _T_366[26] <= UInt<1>("h00") @[lib.scala 12:48] node _T_367 = cat(_T_366[0], _T_366[1]) @[Cat.scala 29:58] node _T_368 = cat(_T_367, _T_366[2]) @[Cat.scala 29:58] node _T_369 = cat(_T_368, _T_366[3]) @[Cat.scala 29:58] @@ -68090,14 +68090,14 @@ circuit quasar_wrapper : node _T_430 = and(_T_429, csr_read_x) @[dec_decode_ctl.scala 477:61] node _T_431 = or(_T_430, io.dec_tlu_wr_pause_r) @[dec_decode_ctl.scala 477:75] node csr_data_wen = or(_T_431, pause_stall) @[dec_decode_ctl.scala 477:99] - inst rvclkhdr_3 of rvclkhdr_664 @[el2_lib.scala 508:23] + inst rvclkhdr_3 of rvclkhdr_664 @[lib.scala 368:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_3.io.en <= csr_data_wen @[el2_lib.scala 511:17] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_432 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_432 <= write_csr_data_in @[el2_lib.scala 514:16] + rvclkhdr_3.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_3.io.en <= csr_data_wen @[lib.scala 371:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_432 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_432 <= write_csr_data_in @[lib.scala 374:16] write_csr_data <= _T_432 @[dec_decode_ctl.scala 478:18] node _T_433 = bits(r_d.bits.csrwonly, 0, 0) @[dec_decode_ctl.scala 484:49] node _T_434 = mux(_T_433, i0_result_corr_r, write_csr_data) @[dec_decode_ctl.scala 484:30] @@ -68125,23 +68125,23 @@ circuit quasar_wrapper : node _T_447 = eq(any_csr_d, UInt<1>("h00")) @[dec_decode_ctl.scala 500:40] node _T_448 = or(_T_447, io.dec_csr_legal_d) @[dec_decode_ctl.scala 500:51] node i0_legal = and(i0_dp.legal, _T_448) @[dec_decode_ctl.scala 500:37] - wire _T_449 : UInt<1>[16] @[el2_lib.scala 162:48] - _T_449[0] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_449[1] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_449[2] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_449[3] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_449[4] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_449[5] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_449[6] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_449[7] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_449[8] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_449[9] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_449[10] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_449[11] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_449[12] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_449[13] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_449[14] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_449[15] <= UInt<1>("h00") @[el2_lib.scala 162:48] + wire _T_449 : UInt<1>[16] @[lib.scala 12:48] + _T_449[0] <= UInt<1>("h00") @[lib.scala 12:48] + _T_449[1] <= UInt<1>("h00") @[lib.scala 12:48] + _T_449[2] <= UInt<1>("h00") @[lib.scala 12:48] + _T_449[3] <= UInt<1>("h00") @[lib.scala 12:48] + _T_449[4] <= UInt<1>("h00") @[lib.scala 12:48] + _T_449[5] <= UInt<1>("h00") @[lib.scala 12:48] + _T_449[6] <= UInt<1>("h00") @[lib.scala 12:48] + _T_449[7] <= UInt<1>("h00") @[lib.scala 12:48] + _T_449[8] <= UInt<1>("h00") @[lib.scala 12:48] + _T_449[9] <= UInt<1>("h00") @[lib.scala 12:48] + _T_449[10] <= UInt<1>("h00") @[lib.scala 12:48] + _T_449[11] <= UInt<1>("h00") @[lib.scala 12:48] + _T_449[12] <= UInt<1>("h00") @[lib.scala 12:48] + _T_449[13] <= UInt<1>("h00") @[lib.scala 12:48] + _T_449[14] <= UInt<1>("h00") @[lib.scala 12:48] + _T_449[15] <= UInt<1>("h00") @[lib.scala 12:48] node _T_450 = cat(_T_449[0], _T_449[1]) @[Cat.scala 29:58] node _T_451 = cat(_T_450, _T_449[2]) @[Cat.scala 29:58] node _T_452 = cat(_T_451, _T_449[3]) @[Cat.scala 29:58] @@ -68163,14 +68163,14 @@ circuit quasar_wrapper : node shift_illegal = and(io.dec_aln.dec_i0_decode_d, _T_466) @[dec_decode_ctl.scala 504:55] node _T_467 = eq(illegal_lockout, UInt<1>("h00")) @[dec_decode_ctl.scala 505:44] node illegal_inst_en = and(shift_illegal, _T_467) @[dec_decode_ctl.scala 505:42] - inst rvclkhdr_4 of rvclkhdr_665 @[el2_lib.scala 508:23] + inst rvclkhdr_4 of rvclkhdr_665 @[lib.scala 368:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_4.io.en <= illegal_inst_en @[el2_lib.scala 511:17] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_468 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_468 <= i0_inst_d @[el2_lib.scala 514:16] + rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_4.io.en <= illegal_inst_en @[lib.scala 371:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_468 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_468 <= i0_inst_d @[lib.scala 374:16] io.dec_illegal_inst <= _T_468 @[dec_decode_ctl.scala 506:23] node _T_469 = or(shift_illegal, illegal_lockout) @[dec_decode_ctl.scala 507:40] node _T_470 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 507:61] @@ -68259,45 +68259,45 @@ circuit quasar_wrapper : d_t.pmu_i0_br_unpred <= i0_br_unpred @[dec_decode_ctl.scala 559:26] d_t.pmu_divide <= UInt<1>("h00") @[dec_decode_ctl.scala 560:26] d_t.pmu_lsu_misaligned <= UInt<1>("h00") @[dec_decode_ctl.scala 561:26] - wire _T_522 : UInt<1>[4] @[el2_lib.scala 162:48] - _T_522[0] <= io.dec_aln.dec_i0_decode_d @[el2_lib.scala 162:48] - _T_522[1] <= io.dec_aln.dec_i0_decode_d @[el2_lib.scala 162:48] - _T_522[2] <= io.dec_aln.dec_i0_decode_d @[el2_lib.scala 162:48] - _T_522[3] <= io.dec_aln.dec_i0_decode_d @[el2_lib.scala 162:48] + wire _T_522 : UInt<1>[4] @[lib.scala 12:48] + _T_522[0] <= io.dec_aln.dec_i0_decode_d @[lib.scala 12:48] + _T_522[1] <= io.dec_aln.dec_i0_decode_d @[lib.scala 12:48] + _T_522[2] <= io.dec_aln.dec_i0_decode_d @[lib.scala 12:48] + _T_522[3] <= io.dec_aln.dec_i0_decode_d @[lib.scala 12:48] node _T_523 = cat(_T_522[0], _T_522[1]) @[Cat.scala 29:58] node _T_524 = cat(_T_523, _T_522[2]) @[Cat.scala 29:58] node _T_525 = cat(_T_524, _T_522[3]) @[Cat.scala 29:58] node _T_526 = and(io.dec_i0_trigger_match_d, _T_525) @[dec_decode_ctl.scala 563:56] d_t.i0trigger <= _T_526 @[dec_decode_ctl.scala 563:26] node _T_527 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 566:33] - inst rvclkhdr_5 of rvclkhdr_666 @[el2_lib.scala 518:23] + inst rvclkhdr_5 of rvclkhdr_666 @[lib.scala 378:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[el2_lib.scala 520:18] - rvclkhdr_5.io.en <= _T_527 @[el2_lib.scala 521:17] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] - wire _T_528 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_lib.scala 524:33] - _T_528.pmu_lsu_misaligned <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_528.pmu_divide <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_528.pmu_i0_br_unpred <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_528.pmu_i0_itype <= UInt<4>("h00") @[el2_lib.scala 524:33] - _T_528.i0trigger <= UInt<4>("h00") @[el2_lib.scala 524:33] - _T_528.fence_i <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_528.icaf_type <= UInt<2>("h00") @[el2_lib.scala 524:33] - _T_528.icaf_f1 <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_528.icaf <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_528.legal <= UInt<1>("h00") @[el2_lib.scala 524:33] - reg _T_529 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, rvclkhdr_5.io.l1clk with : (reset => (reset, _T_528)) @[el2_lib.scala 524:16] - _T_529.pmu_lsu_misaligned <= d_t.pmu_lsu_misaligned @[el2_lib.scala 524:16] - _T_529.pmu_divide <= d_t.pmu_divide @[el2_lib.scala 524:16] - _T_529.pmu_i0_br_unpred <= d_t.pmu_i0_br_unpred @[el2_lib.scala 524:16] - _T_529.pmu_i0_itype <= d_t.pmu_i0_itype @[el2_lib.scala 524:16] - _T_529.i0trigger <= d_t.i0trigger @[el2_lib.scala 524:16] - _T_529.fence_i <= d_t.fence_i @[el2_lib.scala 524:16] - _T_529.icaf_type <= d_t.icaf_type @[el2_lib.scala 524:16] - _T_529.icaf_f1 <= d_t.icaf_f1 @[el2_lib.scala 524:16] - _T_529.icaf <= d_t.icaf @[el2_lib.scala 524:16] - _T_529.legal <= d_t.legal @[el2_lib.scala 524:16] + rvclkhdr_5.io.clk <= clock @[lib.scala 380:18] + rvclkhdr_5.io.en <= _T_527 @[lib.scala 381:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 382:24] + wire _T_528 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[lib.scala 384:33] + _T_528.pmu_lsu_misaligned <= UInt<1>("h00") @[lib.scala 384:33] + _T_528.pmu_divide <= UInt<1>("h00") @[lib.scala 384:33] + _T_528.pmu_i0_br_unpred <= UInt<1>("h00") @[lib.scala 384:33] + _T_528.pmu_i0_itype <= UInt<4>("h00") @[lib.scala 384:33] + _T_528.i0trigger <= UInt<4>("h00") @[lib.scala 384:33] + _T_528.fence_i <= UInt<1>("h00") @[lib.scala 384:33] + _T_528.icaf_type <= UInt<2>("h00") @[lib.scala 384:33] + _T_528.icaf_f1 <= UInt<1>("h00") @[lib.scala 384:33] + _T_528.icaf <= UInt<1>("h00") @[lib.scala 384:33] + _T_528.legal <= UInt<1>("h00") @[lib.scala 384:33] + reg _T_529 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, rvclkhdr_5.io.l1clk with : (reset => (reset, _T_528)) @[lib.scala 384:16] + _T_529.pmu_lsu_misaligned <= d_t.pmu_lsu_misaligned @[lib.scala 384:16] + _T_529.pmu_divide <= d_t.pmu_divide @[lib.scala 384:16] + _T_529.pmu_i0_br_unpred <= d_t.pmu_i0_br_unpred @[lib.scala 384:16] + _T_529.pmu_i0_itype <= d_t.pmu_i0_itype @[lib.scala 384:16] + _T_529.i0trigger <= d_t.i0trigger @[lib.scala 384:16] + _T_529.fence_i <= d_t.fence_i @[lib.scala 384:16] + _T_529.icaf_type <= d_t.icaf_type @[lib.scala 384:16] + _T_529.icaf_f1 <= d_t.icaf_f1 @[lib.scala 384:16] + _T_529.icaf <= d_t.icaf @[lib.scala 384:16] + _T_529.legal <= d_t.legal @[lib.scala 384:16] x_t.pmu_lsu_misaligned <= _T_529.pmu_lsu_misaligned @[dec_decode_ctl.scala 566:7] x_t.pmu_divide <= _T_529.pmu_divide @[dec_decode_ctl.scala 566:7] x_t.pmu_i0_br_unpred <= _T_529.pmu_i0_br_unpred @[dec_decode_ctl.scala 566:7] @@ -68318,11 +68318,11 @@ circuit quasar_wrapper : x_t_in.icaf_f1 <= x_t.icaf_f1 @[dec_decode_ctl.scala 568:10] x_t_in.icaf <= x_t.icaf @[dec_decode_ctl.scala 568:10] x_t_in.legal <= x_t.legal @[dec_decode_ctl.scala 568:10] - wire _T_530 : UInt<1>[4] @[el2_lib.scala 162:48] - _T_530[0] <= io.dec_tlu_flush_lower_wb @[el2_lib.scala 162:48] - _T_530[1] <= io.dec_tlu_flush_lower_wb @[el2_lib.scala 162:48] - _T_530[2] <= io.dec_tlu_flush_lower_wb @[el2_lib.scala 162:48] - _T_530[3] <= io.dec_tlu_flush_lower_wb @[el2_lib.scala 162:48] + wire _T_530 : UInt<1>[4] @[lib.scala 12:48] + _T_530[0] <= io.dec_tlu_flush_lower_wb @[lib.scala 12:48] + _T_530[1] <= io.dec_tlu_flush_lower_wb @[lib.scala 12:48] + _T_530[2] <= io.dec_tlu_flush_lower_wb @[lib.scala 12:48] + _T_530[3] <= io.dec_tlu_flush_lower_wb @[lib.scala 12:48] node _T_531 = cat(_T_530[0], _T_530[1]) @[Cat.scala 29:58] node _T_532 = cat(_T_531, _T_530[2]) @[Cat.scala 29:58] node _T_533 = cat(_T_532, _T_530[3]) @[Cat.scala 29:58] @@ -68330,34 +68330,34 @@ circuit quasar_wrapper : node _T_535 = and(x_t.i0trigger, _T_534) @[dec_decode_ctl.scala 569:37] x_t_in.i0trigger <= _T_535 @[dec_decode_ctl.scala 569:20] node _T_536 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 571:36] - inst rvclkhdr_6 of rvclkhdr_667 @[el2_lib.scala 518:23] + inst rvclkhdr_6 of rvclkhdr_667 @[lib.scala 378:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset - rvclkhdr_6.io.clk <= clock @[el2_lib.scala 520:18] - rvclkhdr_6.io.en <= _T_536 @[el2_lib.scala 521:17] - rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] - wire _T_537 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_lib.scala 524:33] - _T_537.pmu_lsu_misaligned <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_537.pmu_divide <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_537.pmu_i0_br_unpred <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_537.pmu_i0_itype <= UInt<4>("h00") @[el2_lib.scala 524:33] - _T_537.i0trigger <= UInt<4>("h00") @[el2_lib.scala 524:33] - _T_537.fence_i <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_537.icaf_type <= UInt<2>("h00") @[el2_lib.scala 524:33] - _T_537.icaf_f1 <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_537.icaf <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_537.legal <= UInt<1>("h00") @[el2_lib.scala 524:33] - reg _T_538 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, rvclkhdr_6.io.l1clk with : (reset => (reset, _T_537)) @[el2_lib.scala 524:16] - _T_538.pmu_lsu_misaligned <= x_t_in.pmu_lsu_misaligned @[el2_lib.scala 524:16] - _T_538.pmu_divide <= x_t_in.pmu_divide @[el2_lib.scala 524:16] - _T_538.pmu_i0_br_unpred <= x_t_in.pmu_i0_br_unpred @[el2_lib.scala 524:16] - _T_538.pmu_i0_itype <= x_t_in.pmu_i0_itype @[el2_lib.scala 524:16] - _T_538.i0trigger <= x_t_in.i0trigger @[el2_lib.scala 524:16] - _T_538.fence_i <= x_t_in.fence_i @[el2_lib.scala 524:16] - _T_538.icaf_type <= x_t_in.icaf_type @[el2_lib.scala 524:16] - _T_538.icaf_f1 <= x_t_in.icaf_f1 @[el2_lib.scala 524:16] - _T_538.icaf <= x_t_in.icaf @[el2_lib.scala 524:16] - _T_538.legal <= x_t_in.legal @[el2_lib.scala 524:16] + rvclkhdr_6.io.clk <= clock @[lib.scala 380:18] + rvclkhdr_6.io.en <= _T_536 @[lib.scala 381:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 382:24] + wire _T_537 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[lib.scala 384:33] + _T_537.pmu_lsu_misaligned <= UInt<1>("h00") @[lib.scala 384:33] + _T_537.pmu_divide <= UInt<1>("h00") @[lib.scala 384:33] + _T_537.pmu_i0_br_unpred <= UInt<1>("h00") @[lib.scala 384:33] + _T_537.pmu_i0_itype <= UInt<4>("h00") @[lib.scala 384:33] + _T_537.i0trigger <= UInt<4>("h00") @[lib.scala 384:33] + _T_537.fence_i <= UInt<1>("h00") @[lib.scala 384:33] + _T_537.icaf_type <= UInt<2>("h00") @[lib.scala 384:33] + _T_537.icaf_f1 <= UInt<1>("h00") @[lib.scala 384:33] + _T_537.icaf <= UInt<1>("h00") @[lib.scala 384:33] + _T_537.legal <= UInt<1>("h00") @[lib.scala 384:33] + reg _T_538 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, rvclkhdr_6.io.l1clk with : (reset => (reset, _T_537)) @[lib.scala 384:16] + _T_538.pmu_lsu_misaligned <= x_t_in.pmu_lsu_misaligned @[lib.scala 384:16] + _T_538.pmu_divide <= x_t_in.pmu_divide @[lib.scala 384:16] + _T_538.pmu_i0_br_unpred <= x_t_in.pmu_i0_br_unpred @[lib.scala 384:16] + _T_538.pmu_i0_itype <= x_t_in.pmu_i0_itype @[lib.scala 384:16] + _T_538.i0trigger <= x_t_in.i0trigger @[lib.scala 384:16] + _T_538.fence_i <= x_t_in.fence_i @[lib.scala 384:16] + _T_538.icaf_type <= x_t_in.icaf_type @[lib.scala 384:16] + _T_538.icaf_f1 <= x_t_in.icaf_f1 @[lib.scala 384:16] + _T_538.icaf <= x_t_in.icaf @[lib.scala 384:16] + _T_538.legal <= x_t_in.legal @[lib.scala 384:16] r_t.pmu_lsu_misaligned <= _T_538.pmu_lsu_misaligned @[dec_decode_ctl.scala 571:7] r_t.pmu_divide <= _T_538.pmu_divide @[dec_decode_ctl.scala 571:7] r_t.pmu_i0_br_unpred <= _T_538.pmu_i0_br_unpred @[dec_decode_ctl.scala 571:7] @@ -68383,11 +68383,11 @@ circuit quasar_wrapper : r_t_in.icaf <= r_t.icaf @[dec_decode_ctl.scala 575:10] r_t_in.legal <= r_t.legal @[dec_decode_ctl.scala 575:10] node _T_539 = or(r_d.bits.i0load, r_d.bits.i0store) @[dec_decode_ctl.scala 577:61] - wire _T_540 : UInt<1>[4] @[el2_lib.scala 162:48] - _T_540[0] <= _T_539 @[el2_lib.scala 162:48] - _T_540[1] <= _T_539 @[el2_lib.scala 162:48] - _T_540[2] <= _T_539 @[el2_lib.scala 162:48] - _T_540[3] <= _T_539 @[el2_lib.scala 162:48] + wire _T_540 : UInt<1>[4] @[lib.scala 12:48] + _T_540[0] <= _T_539 @[lib.scala 12:48] + _T_540[1] <= _T_539 @[lib.scala 12:48] + _T_540[2] <= _T_539 @[lib.scala 12:48] + _T_540[3] <= _T_539 @[lib.scala 12:48] node _T_541 = cat(_T_540[0], _T_540[1]) @[Cat.scala 29:58] node _T_542 = cat(_T_541, _T_540[2]) @[Cat.scala 29:58] node _T_543 = cat(_T_542, _T_540[3]) @[Cat.scala 29:58] @@ -68468,27 +68468,27 @@ circuit quasar_wrapper : _T_569 <= _T_568 @[Mux.scala 27:72] io.decode_exu.dec_i0_immed_d <= _T_569 @[dec_decode_ctl.scala 603:32] node _T_570 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 608:38] - wire _T_571 : UInt<1>[20] @[el2_lib.scala 162:48] - _T_571[0] <= _T_570 @[el2_lib.scala 162:48] - _T_571[1] <= _T_570 @[el2_lib.scala 162:48] - _T_571[2] <= _T_570 @[el2_lib.scala 162:48] - _T_571[3] <= _T_570 @[el2_lib.scala 162:48] - _T_571[4] <= _T_570 @[el2_lib.scala 162:48] - _T_571[5] <= _T_570 @[el2_lib.scala 162:48] - _T_571[6] <= _T_570 @[el2_lib.scala 162:48] - _T_571[7] <= _T_570 @[el2_lib.scala 162:48] - _T_571[8] <= _T_570 @[el2_lib.scala 162:48] - _T_571[9] <= _T_570 @[el2_lib.scala 162:48] - _T_571[10] <= _T_570 @[el2_lib.scala 162:48] - _T_571[11] <= _T_570 @[el2_lib.scala 162:48] - _T_571[12] <= _T_570 @[el2_lib.scala 162:48] - _T_571[13] <= _T_570 @[el2_lib.scala 162:48] - _T_571[14] <= _T_570 @[el2_lib.scala 162:48] - _T_571[15] <= _T_570 @[el2_lib.scala 162:48] - _T_571[16] <= _T_570 @[el2_lib.scala 162:48] - _T_571[17] <= _T_570 @[el2_lib.scala 162:48] - _T_571[18] <= _T_570 @[el2_lib.scala 162:48] - _T_571[19] <= _T_570 @[el2_lib.scala 162:48] + wire _T_571 : UInt<1>[20] @[lib.scala 12:48] + _T_571[0] <= _T_570 @[lib.scala 12:48] + _T_571[1] <= _T_570 @[lib.scala 12:48] + _T_571[2] <= _T_570 @[lib.scala 12:48] + _T_571[3] <= _T_570 @[lib.scala 12:48] + _T_571[4] <= _T_570 @[lib.scala 12:48] + _T_571[5] <= _T_570 @[lib.scala 12:48] + _T_571[6] <= _T_570 @[lib.scala 12:48] + _T_571[7] <= _T_570 @[lib.scala 12:48] + _T_571[8] <= _T_570 @[lib.scala 12:48] + _T_571[9] <= _T_570 @[lib.scala 12:48] + _T_571[10] <= _T_570 @[lib.scala 12:48] + _T_571[11] <= _T_570 @[lib.scala 12:48] + _T_571[12] <= _T_570 @[lib.scala 12:48] + _T_571[13] <= _T_570 @[lib.scala 12:48] + _T_571[14] <= _T_570 @[lib.scala 12:48] + _T_571[15] <= _T_570 @[lib.scala 12:48] + _T_571[16] <= _T_570 @[lib.scala 12:48] + _T_571[17] <= _T_570 @[lib.scala 12:48] + _T_571[18] <= _T_570 @[lib.scala 12:48] + _T_571[19] <= _T_570 @[lib.scala 12:48] node _T_572 = cat(_T_571[0], _T_571[1]) @[Cat.scala 29:58] node _T_573 = cat(_T_572, _T_571[2]) @[Cat.scala 29:58] node _T_574 = cat(_T_573, _T_571[3]) @[Cat.scala 29:58] @@ -68510,34 +68510,34 @@ circuit quasar_wrapper : node _T_590 = cat(_T_589, _T_571[19]) @[Cat.scala 29:58] node _T_591 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 608:46] node _T_592 = cat(_T_590, _T_591) @[Cat.scala 29:58] - wire _T_593 : UInt<1>[27] @[el2_lib.scala 162:48] - _T_593[0] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_593[1] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_593[2] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_593[3] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_593[4] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_593[5] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_593[6] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_593[7] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_593[8] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_593[9] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_593[10] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_593[11] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_593[12] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_593[13] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_593[14] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_593[15] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_593[16] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_593[17] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_593[18] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_593[19] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_593[20] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_593[21] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_593[22] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_593[23] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_593[24] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_593[25] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_593[26] <= UInt<1>("h00") @[el2_lib.scala 162:48] + wire _T_593 : UInt<1>[27] @[lib.scala 12:48] + _T_593[0] <= UInt<1>("h00") @[lib.scala 12:48] + _T_593[1] <= UInt<1>("h00") @[lib.scala 12:48] + _T_593[2] <= UInt<1>("h00") @[lib.scala 12:48] + _T_593[3] <= UInt<1>("h00") @[lib.scala 12:48] + _T_593[4] <= UInt<1>("h00") @[lib.scala 12:48] + _T_593[5] <= UInt<1>("h00") @[lib.scala 12:48] + _T_593[6] <= UInt<1>("h00") @[lib.scala 12:48] + _T_593[7] <= UInt<1>("h00") @[lib.scala 12:48] + _T_593[8] <= UInt<1>("h00") @[lib.scala 12:48] + _T_593[9] <= UInt<1>("h00") @[lib.scala 12:48] + _T_593[10] <= UInt<1>("h00") @[lib.scala 12:48] + _T_593[11] <= UInt<1>("h00") @[lib.scala 12:48] + _T_593[12] <= UInt<1>("h00") @[lib.scala 12:48] + _T_593[13] <= UInt<1>("h00") @[lib.scala 12:48] + _T_593[14] <= UInt<1>("h00") @[lib.scala 12:48] + _T_593[15] <= UInt<1>("h00") @[lib.scala 12:48] + _T_593[16] <= UInt<1>("h00") @[lib.scala 12:48] + _T_593[17] <= UInt<1>("h00") @[lib.scala 12:48] + _T_593[18] <= UInt<1>("h00") @[lib.scala 12:48] + _T_593[19] <= UInt<1>("h00") @[lib.scala 12:48] + _T_593[20] <= UInt<1>("h00") @[lib.scala 12:48] + _T_593[21] <= UInt<1>("h00") @[lib.scala 12:48] + _T_593[22] <= UInt<1>("h00") @[lib.scala 12:48] + _T_593[23] <= UInt<1>("h00") @[lib.scala 12:48] + _T_593[24] <= UInt<1>("h00") @[lib.scala 12:48] + _T_593[25] <= UInt<1>("h00") @[lib.scala 12:48] + _T_593[26] <= UInt<1>("h00") @[lib.scala 12:48] node _T_594 = cat(_T_593[0], _T_593[1]) @[Cat.scala 29:58] node _T_595 = cat(_T_594, _T_593[2]) @[Cat.scala 29:58] node _T_596 = cat(_T_595, _T_593[3]) @[Cat.scala 29:58] @@ -68567,19 +68567,19 @@ circuit quasar_wrapper : node _T_620 = bits(io.dec_i0_instr_d, 24, 20) @[dec_decode_ctl.scala 609:43] node _T_621 = cat(_T_619, _T_620) @[Cat.scala 29:58] node _T_622 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 610:38] - wire _T_623 : UInt<1>[12] @[el2_lib.scala 162:48] - _T_623[0] <= _T_622 @[el2_lib.scala 162:48] - _T_623[1] <= _T_622 @[el2_lib.scala 162:48] - _T_623[2] <= _T_622 @[el2_lib.scala 162:48] - _T_623[3] <= _T_622 @[el2_lib.scala 162:48] - _T_623[4] <= _T_622 @[el2_lib.scala 162:48] - _T_623[5] <= _T_622 @[el2_lib.scala 162:48] - _T_623[6] <= _T_622 @[el2_lib.scala 162:48] - _T_623[7] <= _T_622 @[el2_lib.scala 162:48] - _T_623[8] <= _T_622 @[el2_lib.scala 162:48] - _T_623[9] <= _T_622 @[el2_lib.scala 162:48] - _T_623[10] <= _T_622 @[el2_lib.scala 162:48] - _T_623[11] <= _T_622 @[el2_lib.scala 162:48] + wire _T_623 : UInt<1>[12] @[lib.scala 12:48] + _T_623[0] <= _T_622 @[lib.scala 12:48] + _T_623[1] <= _T_622 @[lib.scala 12:48] + _T_623[2] <= _T_622 @[lib.scala 12:48] + _T_623[3] <= _T_622 @[lib.scala 12:48] + _T_623[4] <= _T_622 @[lib.scala 12:48] + _T_623[5] <= _T_622 @[lib.scala 12:48] + _T_623[6] <= _T_622 @[lib.scala 12:48] + _T_623[7] <= _T_622 @[lib.scala 12:48] + _T_623[8] <= _T_622 @[lib.scala 12:48] + _T_623[9] <= _T_622 @[lib.scala 12:48] + _T_623[10] <= _T_622 @[lib.scala 12:48] + _T_623[11] <= _T_622 @[lib.scala 12:48] node _T_624 = cat(_T_623[0], _T_623[1]) @[Cat.scala 29:58] node _T_625 = cat(_T_624, _T_623[2]) @[Cat.scala 29:58] node _T_626 = cat(_T_625, _T_623[3]) @[Cat.scala 29:58] @@ -68599,19 +68599,19 @@ circuit quasar_wrapper : node _T_640 = cat(_T_639, _T_636) @[Cat.scala 29:58] node _T_641 = cat(_T_640, _T_638) @[Cat.scala 29:58] node _T_642 = bits(io.dec_i0_instr_d, 31, 12) @[dec_decode_ctl.scala 611:30] - wire _T_643 : UInt<1>[12] @[el2_lib.scala 162:48] - _T_643[0] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_643[1] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_643[2] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_643[3] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_643[4] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_643[5] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_643[6] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_643[7] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_643[8] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_643[9] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_643[10] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_643[11] <= UInt<1>("h00") @[el2_lib.scala 162:48] + wire _T_643 : UInt<1>[12] @[lib.scala 12:48] + _T_643[0] <= UInt<1>("h00") @[lib.scala 12:48] + _T_643[1] <= UInt<1>("h00") @[lib.scala 12:48] + _T_643[2] <= UInt<1>("h00") @[lib.scala 12:48] + _T_643[3] <= UInt<1>("h00") @[lib.scala 12:48] + _T_643[4] <= UInt<1>("h00") @[lib.scala 12:48] + _T_643[5] <= UInt<1>("h00") @[lib.scala 12:48] + _T_643[6] <= UInt<1>("h00") @[lib.scala 12:48] + _T_643[7] <= UInt<1>("h00") @[lib.scala 12:48] + _T_643[8] <= UInt<1>("h00") @[lib.scala 12:48] + _T_643[9] <= UInt<1>("h00") @[lib.scala 12:48] + _T_643[10] <= UInt<1>("h00") @[lib.scala 12:48] + _T_643[11] <= UInt<1>("h00") @[lib.scala 12:48] node _T_644 = cat(_T_643[0], _T_643[1]) @[Cat.scala 29:58] node _T_645 = cat(_T_644, _T_643[2]) @[Cat.scala 29:58] node _T_646 = cat(_T_645, _T_643[3]) @[Cat.scala 29:58] @@ -68626,34 +68626,34 @@ circuit quasar_wrapper : node _T_655 = cat(_T_642, _T_654) @[Cat.scala 29:58] node _T_656 = and(i0_csr_write_only_d, i0_dp.csr_imm) @[dec_decode_ctl.scala 612:26] node _T_657 = bits(_T_656, 0, 0) @[dec_decode_ctl.scala 612:43] - wire _T_658 : UInt<1>[27] @[el2_lib.scala 162:48] - _T_658[0] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_658[1] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_658[2] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_658[3] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_658[4] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_658[5] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_658[6] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_658[7] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_658[8] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_658[9] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_658[10] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_658[11] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_658[12] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_658[13] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_658[14] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_658[15] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_658[16] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_658[17] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_658[18] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_658[19] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_658[20] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_658[21] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_658[22] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_658[23] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_658[24] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_658[25] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_658[26] <= UInt<1>("h00") @[el2_lib.scala 162:48] + wire _T_658 : UInt<1>[27] @[lib.scala 12:48] + _T_658[0] <= UInt<1>("h00") @[lib.scala 12:48] + _T_658[1] <= UInt<1>("h00") @[lib.scala 12:48] + _T_658[2] <= UInt<1>("h00") @[lib.scala 12:48] + _T_658[3] <= UInt<1>("h00") @[lib.scala 12:48] + _T_658[4] <= UInt<1>("h00") @[lib.scala 12:48] + _T_658[5] <= UInt<1>("h00") @[lib.scala 12:48] + _T_658[6] <= UInt<1>("h00") @[lib.scala 12:48] + _T_658[7] <= UInt<1>("h00") @[lib.scala 12:48] + _T_658[8] <= UInt<1>("h00") @[lib.scala 12:48] + _T_658[9] <= UInt<1>("h00") @[lib.scala 12:48] + _T_658[10] <= UInt<1>("h00") @[lib.scala 12:48] + _T_658[11] <= UInt<1>("h00") @[lib.scala 12:48] + _T_658[12] <= UInt<1>("h00") @[lib.scala 12:48] + _T_658[13] <= UInt<1>("h00") @[lib.scala 12:48] + _T_658[14] <= UInt<1>("h00") @[lib.scala 12:48] + _T_658[15] <= UInt<1>("h00") @[lib.scala 12:48] + _T_658[16] <= UInt<1>("h00") @[lib.scala 12:48] + _T_658[17] <= UInt<1>("h00") @[lib.scala 12:48] + _T_658[18] <= UInt<1>("h00") @[lib.scala 12:48] + _T_658[19] <= UInt<1>("h00") @[lib.scala 12:48] + _T_658[20] <= UInt<1>("h00") @[lib.scala 12:48] + _T_658[21] <= UInt<1>("h00") @[lib.scala 12:48] + _T_658[22] <= UInt<1>("h00") @[lib.scala 12:48] + _T_658[23] <= UInt<1>("h00") @[lib.scala 12:48] + _T_658[24] <= UInt<1>("h00") @[lib.scala 12:48] + _T_658[25] <= UInt<1>("h00") @[lib.scala 12:48] + _T_658[26] <= UInt<1>("h00") @[lib.scala 12:48] node _T_659 = cat(_T_658[0], _T_658[1]) @[Cat.scala 29:58] node _T_660 = cat(_T_659, _T_658[2]) @[Cat.scala 29:58] node _T_661 = cat(_T_660, _T_658[3]) @[Cat.scala 29:58] @@ -68766,32 +68766,32 @@ circuit quasar_wrapper : node _T_731 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 645:40] d_d.bits.csrwaddr <= _T_731 @[dec_decode_ctl.scala 645:34] node _T_732 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 647:34] - inst rvclkhdr_7 of rvclkhdr_668 @[el2_lib.scala 518:23] + inst rvclkhdr_7 of rvclkhdr_668 @[lib.scala 378:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset - rvclkhdr_7.io.clk <= clock @[el2_lib.scala 520:18] - rvclkhdr_7.io.en <= _T_732 @[el2_lib.scala 521:17] - rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] - wire _T_733 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_lib.scala 524:33] - _T_733.bits.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] - _T_733.bits.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_733.bits.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_733.bits.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_733.bits.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_733.bits.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_733.bits.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_733.bits.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] - _T_733.valid <= UInt<1>("h00") @[el2_lib.scala 524:33] - reg _T_734 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_7.io.l1clk with : (reset => (reset, _T_733)) @[el2_lib.scala 524:16] - _T_734.bits.csrwaddr <= d_d.bits.csrwaddr @[el2_lib.scala 524:16] - _T_734.bits.csrwonly <= d_d.bits.csrwonly @[el2_lib.scala 524:16] - _T_734.bits.csrwen <= d_d.bits.csrwen @[el2_lib.scala 524:16] - _T_734.bits.i0v <= d_d.bits.i0v @[el2_lib.scala 524:16] - _T_734.bits.i0div <= d_d.bits.i0div @[el2_lib.scala 524:16] - _T_734.bits.i0store <= d_d.bits.i0store @[el2_lib.scala 524:16] - _T_734.bits.i0load <= d_d.bits.i0load @[el2_lib.scala 524:16] - _T_734.bits.i0rd <= d_d.bits.i0rd @[el2_lib.scala 524:16] - _T_734.valid <= d_d.valid @[el2_lib.scala 524:16] + rvclkhdr_7.io.clk <= clock @[lib.scala 380:18] + rvclkhdr_7.io.en <= _T_732 @[lib.scala 381:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 382:24] + wire _T_733 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 384:33] + _T_733.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 384:33] + _T_733.bits.csrwonly <= UInt<1>("h00") @[lib.scala 384:33] + _T_733.bits.csrwen <= UInt<1>("h00") @[lib.scala 384:33] + _T_733.bits.i0v <= UInt<1>("h00") @[lib.scala 384:33] + _T_733.bits.i0div <= UInt<1>("h00") @[lib.scala 384:33] + _T_733.bits.i0store <= UInt<1>("h00") @[lib.scala 384:33] + _T_733.bits.i0load <= UInt<1>("h00") @[lib.scala 384:33] + _T_733.bits.i0rd <= UInt<5>("h00") @[lib.scala 384:33] + _T_733.valid <= UInt<1>("h00") @[lib.scala 384:33] + reg _T_734 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_7.io.l1clk with : (reset => (reset, _T_733)) @[lib.scala 384:16] + _T_734.bits.csrwaddr <= d_d.bits.csrwaddr @[lib.scala 384:16] + _T_734.bits.csrwonly <= d_d.bits.csrwonly @[lib.scala 384:16] + _T_734.bits.csrwen <= d_d.bits.csrwen @[lib.scala 384:16] + _T_734.bits.i0v <= d_d.bits.i0v @[lib.scala 384:16] + _T_734.bits.i0div <= d_d.bits.i0div @[lib.scala 384:16] + _T_734.bits.i0store <= d_d.bits.i0store @[lib.scala 384:16] + _T_734.bits.i0load <= d_d.bits.i0load @[lib.scala 384:16] + _T_734.bits.i0rd <= d_d.bits.i0rd @[lib.scala 384:16] + _T_734.valid <= d_d.valid @[lib.scala 384:16] x_d.bits.csrwaddr <= _T_734.bits.csrwaddr @[dec_decode_ctl.scala 647:7] x_d.bits.csrwonly <= _T_734.bits.csrwonly @[dec_decode_ctl.scala 647:7] x_d.bits.csrwen <= _T_734.bits.csrwen @[dec_decode_ctl.scala 647:7] @@ -68822,32 +68822,32 @@ circuit quasar_wrapper : node _T_742 = and(_T_740, _T_741) @[dec_decode_ctl.scala 651:62] x_d_in.valid <= _T_742 @[dec_decode_ctl.scala 651:20] node _T_743 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 653:36] - inst rvclkhdr_8 of rvclkhdr_669 @[el2_lib.scala 518:23] + inst rvclkhdr_8 of rvclkhdr_669 @[lib.scala 378:23] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset - rvclkhdr_8.io.clk <= clock @[el2_lib.scala 520:18] - rvclkhdr_8.io.en <= _T_743 @[el2_lib.scala 521:17] - rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] - wire _T_744 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_lib.scala 524:33] - _T_744.bits.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] - _T_744.bits.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_744.bits.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_744.bits.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_744.bits.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_744.bits.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_744.bits.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_744.bits.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] - _T_744.valid <= UInt<1>("h00") @[el2_lib.scala 524:33] - reg _T_745 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_8.io.l1clk with : (reset => (reset, _T_744)) @[el2_lib.scala 524:16] - _T_745.bits.csrwaddr <= x_d_in.bits.csrwaddr @[el2_lib.scala 524:16] - _T_745.bits.csrwonly <= x_d_in.bits.csrwonly @[el2_lib.scala 524:16] - _T_745.bits.csrwen <= x_d_in.bits.csrwen @[el2_lib.scala 524:16] - _T_745.bits.i0v <= x_d_in.bits.i0v @[el2_lib.scala 524:16] - _T_745.bits.i0div <= x_d_in.bits.i0div @[el2_lib.scala 524:16] - _T_745.bits.i0store <= x_d_in.bits.i0store @[el2_lib.scala 524:16] - _T_745.bits.i0load <= x_d_in.bits.i0load @[el2_lib.scala 524:16] - _T_745.bits.i0rd <= x_d_in.bits.i0rd @[el2_lib.scala 524:16] - _T_745.valid <= x_d_in.valid @[el2_lib.scala 524:16] + rvclkhdr_8.io.clk <= clock @[lib.scala 380:18] + rvclkhdr_8.io.en <= _T_743 @[lib.scala 381:17] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 382:24] + wire _T_744 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 384:33] + _T_744.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 384:33] + _T_744.bits.csrwonly <= UInt<1>("h00") @[lib.scala 384:33] + _T_744.bits.csrwen <= UInt<1>("h00") @[lib.scala 384:33] + _T_744.bits.i0v <= UInt<1>("h00") @[lib.scala 384:33] + _T_744.bits.i0div <= UInt<1>("h00") @[lib.scala 384:33] + _T_744.bits.i0store <= UInt<1>("h00") @[lib.scala 384:33] + _T_744.bits.i0load <= UInt<1>("h00") @[lib.scala 384:33] + _T_744.bits.i0rd <= UInt<5>("h00") @[lib.scala 384:33] + _T_744.valid <= UInt<1>("h00") @[lib.scala 384:33] + reg _T_745 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_8.io.l1clk with : (reset => (reset, _T_744)) @[lib.scala 384:16] + _T_745.bits.csrwaddr <= x_d_in.bits.csrwaddr @[lib.scala 384:16] + _T_745.bits.csrwonly <= x_d_in.bits.csrwonly @[lib.scala 384:16] + _T_745.bits.csrwen <= x_d_in.bits.csrwen @[lib.scala 384:16] + _T_745.bits.i0v <= x_d_in.bits.i0v @[lib.scala 384:16] + _T_745.bits.i0div <= x_d_in.bits.i0div @[lib.scala 384:16] + _T_745.bits.i0store <= x_d_in.bits.i0store @[lib.scala 384:16] + _T_745.bits.i0load <= x_d_in.bits.i0load @[lib.scala 384:16] + _T_745.bits.i0rd <= x_d_in.bits.i0rd @[lib.scala 384:16] + _T_745.valid <= x_d_in.valid @[lib.scala 384:16] r_d.bits.csrwaddr <= _T_745.bits.csrwaddr @[dec_decode_ctl.scala 653:7] r_d.bits.csrwonly <= _T_745.bits.csrwonly @[dec_decode_ctl.scala 653:7] r_d.bits.csrwen <= _T_745.bits.csrwen @[dec_decode_ctl.scala 653:7] @@ -68880,32 +68880,32 @@ circuit quasar_wrapper : node _T_753 = and(r_d.bits.i0store, _T_752) @[dec_decode_ctl.scala 660:49] r_d_in.bits.i0store <= _T_753 @[dec_decode_ctl.scala 660:27] node _T_754 = bits(i0_wb_ctl_en, 0, 0) @[dec_decode_ctl.scala 662:37] - inst rvclkhdr_9 of rvclkhdr_670 @[el2_lib.scala 518:23] + inst rvclkhdr_9 of rvclkhdr_670 @[lib.scala 378:23] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset - rvclkhdr_9.io.clk <= clock @[el2_lib.scala 520:18] - rvclkhdr_9.io.en <= _T_754 @[el2_lib.scala 521:17] - rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] - wire _T_755 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[el2_lib.scala 524:33] - _T_755.bits.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] - _T_755.bits.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_755.bits.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_755.bits.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_755.bits.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_755.bits.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_755.bits.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_755.bits.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] - _T_755.valid <= UInt<1>("h00") @[el2_lib.scala 524:33] - reg _T_756 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_9.io.l1clk with : (reset => (reset, _T_755)) @[el2_lib.scala 524:16] - _T_756.bits.csrwaddr <= r_d_in.bits.csrwaddr @[el2_lib.scala 524:16] - _T_756.bits.csrwonly <= r_d_in.bits.csrwonly @[el2_lib.scala 524:16] - _T_756.bits.csrwen <= r_d_in.bits.csrwen @[el2_lib.scala 524:16] - _T_756.bits.i0v <= r_d_in.bits.i0v @[el2_lib.scala 524:16] - _T_756.bits.i0div <= r_d_in.bits.i0div @[el2_lib.scala 524:16] - _T_756.bits.i0store <= r_d_in.bits.i0store @[el2_lib.scala 524:16] - _T_756.bits.i0load <= r_d_in.bits.i0load @[el2_lib.scala 524:16] - _T_756.bits.i0rd <= r_d_in.bits.i0rd @[el2_lib.scala 524:16] - _T_756.valid <= r_d_in.valid @[el2_lib.scala 524:16] + rvclkhdr_9.io.clk <= clock @[lib.scala 380:18] + rvclkhdr_9.io.en <= _T_754 @[lib.scala 381:17] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 382:24] + wire _T_755 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 384:33] + _T_755.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 384:33] + _T_755.bits.csrwonly <= UInt<1>("h00") @[lib.scala 384:33] + _T_755.bits.csrwen <= UInt<1>("h00") @[lib.scala 384:33] + _T_755.bits.i0v <= UInt<1>("h00") @[lib.scala 384:33] + _T_755.bits.i0div <= UInt<1>("h00") @[lib.scala 384:33] + _T_755.bits.i0store <= UInt<1>("h00") @[lib.scala 384:33] + _T_755.bits.i0load <= UInt<1>("h00") @[lib.scala 384:33] + _T_755.bits.i0rd <= UInt<5>("h00") @[lib.scala 384:33] + _T_755.valid <= UInt<1>("h00") @[lib.scala 384:33] + reg _T_756 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_9.io.l1clk with : (reset => (reset, _T_755)) @[lib.scala 384:16] + _T_756.bits.csrwaddr <= r_d_in.bits.csrwaddr @[lib.scala 384:16] + _T_756.bits.csrwonly <= r_d_in.bits.csrwonly @[lib.scala 384:16] + _T_756.bits.csrwen <= r_d_in.bits.csrwen @[lib.scala 384:16] + _T_756.bits.i0v <= r_d_in.bits.i0v @[lib.scala 384:16] + _T_756.bits.i0div <= r_d_in.bits.i0div @[lib.scala 384:16] + _T_756.bits.i0store <= r_d_in.bits.i0store @[lib.scala 384:16] + _T_756.bits.i0load <= r_d_in.bits.i0load @[lib.scala 384:16] + _T_756.bits.i0rd <= r_d_in.bits.i0rd @[lib.scala 384:16] + _T_756.valid <= r_d_in.valid @[lib.scala 384:16] wbd.bits.csrwaddr <= _T_756.bits.csrwaddr @[dec_decode_ctl.scala 662:7] wbd.bits.csrwonly <= _T_756.bits.csrwonly @[dec_decode_ctl.scala 662:7] wbd.bits.csrwen <= _T_756.bits.csrwen @[dec_decode_ctl.scala 662:7] @@ -68926,14 +68926,14 @@ circuit quasar_wrapper : io.dec_i0_wen_r <= _T_762 @[dec_decode_ctl.scala 666:32] io.dec_i0_wdata_r <= i0_result_corr_r @[dec_decode_ctl.scala 667:26] node _T_763 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 669:57] - inst rvclkhdr_10 of rvclkhdr_671 @[el2_lib.scala 508:23] + inst rvclkhdr_10 of rvclkhdr_671 @[lib.scala 368:23] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset - rvclkhdr_10.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_10.io.en <= _T_763 @[el2_lib.scala 511:17] - rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg i0_result_r_raw : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - i0_result_r_raw <= i0_result_x @[el2_lib.scala 514:16] + rvclkhdr_10.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_10.io.en <= _T_763 @[lib.scala 371:17] + rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg i0_result_r_raw : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + i0_result_r_raw <= i0_result_x @[lib.scala 374:16] node _T_764 = and(x_d.bits.i0v, x_d.bits.i0load) @[dec_decode_ctl.scala 675:47] node _T_765 = bits(_T_764, 0, 0) @[dec_decode_ctl.scala 675:66] node _T_766 = mux(_T_765, io.lsu_result_m, io.decode_exu.exu_i0_result_x) @[dec_decode_ctl.scala 675:32] @@ -68946,17 +68946,17 @@ circuit quasar_wrapper : node _T_770 = eq(i0_dp.jal, UInt<1>("h00")) @[dec_decode_ctl.scala 681:73] node _T_771 = and(io.decode_exu.i0_ap.predict_nt, _T_770) @[dec_decode_ctl.scala 681:71] node _T_772 = bits(_T_771, 0, 0) @[dec_decode_ctl.scala 681:85] - wire _T_773 : UInt<1>[10] @[el2_lib.scala 162:48] - _T_773[0] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_773[1] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_773[2] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_773[3] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_773[4] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_773[5] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_773[6] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_773[7] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_773[8] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_773[9] <= UInt<1>("h00") @[el2_lib.scala 162:48] + wire _T_773 : UInt<1>[10] @[lib.scala 12:48] + _T_773[0] <= UInt<1>("h00") @[lib.scala 12:48] + _T_773[1] <= UInt<1>("h00") @[lib.scala 12:48] + _T_773[2] <= UInt<1>("h00") @[lib.scala 12:48] + _T_773[3] <= UInt<1>("h00") @[lib.scala 12:48] + _T_773[4] <= UInt<1>("h00") @[lib.scala 12:48] + _T_773[5] <= UInt<1>("h00") @[lib.scala 12:48] + _T_773[6] <= UInt<1>("h00") @[lib.scala 12:48] + _T_773[7] <= UInt<1>("h00") @[lib.scala 12:48] + _T_773[8] <= UInt<1>("h00") @[lib.scala 12:48] + _T_773[9] <= UInt<1>("h00") @[lib.scala 12:48] node _T_774 = cat(_T_773[0], _T_773[1]) @[Cat.scala 29:58] node _T_775 = cat(_T_774, _T_773[2]) @[Cat.scala 29:58] node _T_776 = cat(_T_775, _T_773[3]) @[Cat.scala 29:58] @@ -68973,17 +68973,17 @@ circuit quasar_wrapper : wire last_br_immed_d : UInt<12> last_br_immed_d <= UInt<1>("h00") node _T_786 = bits(io.decode_exu.i0_ap.predict_nt, 0, 0) @[dec_decode_ctl.scala 683:59] - wire _T_787 : UInt<1>[10] @[el2_lib.scala 162:48] - _T_787[0] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_787[1] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_787[2] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_787[3] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_787[4] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_787[5] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_787[6] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_787[7] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_787[8] <= UInt<1>("h00") @[el2_lib.scala 162:48] - _T_787[9] <= UInt<1>("h00") @[el2_lib.scala 162:48] + wire _T_787 : UInt<1>[10] @[lib.scala 12:48] + _T_787[0] <= UInt<1>("h00") @[lib.scala 12:48] + _T_787[1] <= UInt<1>("h00") @[lib.scala 12:48] + _T_787[2] <= UInt<1>("h00") @[lib.scala 12:48] + _T_787[3] <= UInt<1>("h00") @[lib.scala 12:48] + _T_787[4] <= UInt<1>("h00") @[lib.scala 12:48] + _T_787[5] <= UInt<1>("h00") @[lib.scala 12:48] + _T_787[6] <= UInt<1>("h00") @[lib.scala 12:48] + _T_787[7] <= UInt<1>("h00") @[lib.scala 12:48] + _T_787[8] <= UInt<1>("h00") @[lib.scala 12:48] + _T_787[9] <= UInt<1>("h00") @[lib.scala 12:48] node _T_788 = cat(_T_787[0], _T_787[1]) @[Cat.scala 29:58] node _T_789 = cat(_T_788, _T_787[2]) @[Cat.scala 29:58] node _T_790 = cat(_T_789, _T_787[3]) @[Cat.scala 29:58] @@ -69000,14 +69000,14 @@ circuit quasar_wrapper : wire last_br_immed_x : UInt<12> last_br_immed_x <= UInt<1>("h00") node _T_800 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 685:58] - inst rvclkhdr_11 of rvclkhdr_672 @[el2_lib.scala 508:23] + inst rvclkhdr_11 of rvclkhdr_672 @[lib.scala 368:23] rvclkhdr_11.clock <= clock rvclkhdr_11.reset <= reset - rvclkhdr_11.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_11.io.en <= _T_800 @[el2_lib.scala 511:17] - rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_801 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_801 <= last_br_immed_d @[el2_lib.scala 514:16] + rvclkhdr_11.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_11.io.en <= _T_800 @[lib.scala 371:17] + rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_801 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_801 <= last_br_immed_d @[lib.scala 374:16] last_br_immed_x <= _T_801 @[dec_decode_ctl.scala 685:19] node _T_802 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 689:45] node _T_803 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 689:76] @@ -69056,105 +69056,105 @@ circuit quasar_wrapper : io.div_waddr_wb <= _T_833 @[dec_decode_ctl.scala 711:19] node _T_834 = bits(i0_inst_d, 24, 7) @[dec_decode_ctl.scala 718:34] node _T_835 = bits(i0_div_decode_d, 0, 0) @[dec_decode_ctl.scala 718:57] - inst rvclkhdr_12 of rvclkhdr_673 @[el2_lib.scala 508:23] + inst rvclkhdr_12 of rvclkhdr_673 @[lib.scala 368:23] rvclkhdr_12.clock <= clock rvclkhdr_12.reset <= reset - rvclkhdr_12.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_12.io.en <= _T_835 @[el2_lib.scala 511:17] - rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg div_inst : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - div_inst <= _T_834 @[el2_lib.scala 514:16] + rvclkhdr_12.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_12.io.en <= _T_835 @[lib.scala 371:17] + rvclkhdr_12.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg div_inst : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + div_inst <= _T_834 @[lib.scala 374:16] node _T_836 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 719:49] - inst rvclkhdr_13 of rvclkhdr_674 @[el2_lib.scala 508:23] + inst rvclkhdr_13 of rvclkhdr_674 @[lib.scala 368:23] rvclkhdr_13.clock <= clock rvclkhdr_13.reset <= reset - rvclkhdr_13.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_13.io.en <= _T_836 @[el2_lib.scala 511:17] - rvclkhdr_13.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg i0_inst_x : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - i0_inst_x <= i0_inst_d @[el2_lib.scala 514:16] + rvclkhdr_13.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_13.io.en <= _T_836 @[lib.scala 371:17] + rvclkhdr_13.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg i0_inst_x : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + i0_inst_x <= i0_inst_d @[lib.scala 374:16] node _T_837 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 720:49] - inst rvclkhdr_14 of rvclkhdr_675 @[el2_lib.scala 508:23] + inst rvclkhdr_14 of rvclkhdr_675 @[lib.scala 368:23] rvclkhdr_14.clock <= clock rvclkhdr_14.reset <= reset - rvclkhdr_14.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_14.io.en <= _T_837 @[el2_lib.scala 511:17] - rvclkhdr_14.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg i0_inst_r : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - i0_inst_r <= i0_inst_x @[el2_lib.scala 514:16] + rvclkhdr_14.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_14.io.en <= _T_837 @[lib.scala 371:17] + rvclkhdr_14.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg i0_inst_r : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + i0_inst_r <= i0_inst_x @[lib.scala 374:16] node _T_838 = bits(i0_wb_data_en, 0, 0) @[dec_decode_ctl.scala 722:50] - inst rvclkhdr_15 of rvclkhdr_676 @[el2_lib.scala 508:23] + inst rvclkhdr_15 of rvclkhdr_676 @[lib.scala 368:23] rvclkhdr_15.clock <= clock rvclkhdr_15.reset <= reset - rvclkhdr_15.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_15.io.en <= _T_838 @[el2_lib.scala 511:17] - rvclkhdr_15.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg i0_inst_wb : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - i0_inst_wb <= i0_inst_r @[el2_lib.scala 514:16] + rvclkhdr_15.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_15.io.en <= _T_838 @[lib.scala 371:17] + rvclkhdr_15.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg i0_inst_wb : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + i0_inst_wb <= i0_inst_r @[lib.scala 374:16] node _T_839 = bits(i0_wb1_data_en, 0, 0) @[dec_decode_ctl.scala 723:53] - inst rvclkhdr_16 of rvclkhdr_677 @[el2_lib.scala 508:23] + inst rvclkhdr_16 of rvclkhdr_677 @[lib.scala 368:23] rvclkhdr_16.clock <= clock rvclkhdr_16.reset <= reset - rvclkhdr_16.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_16.io.en <= _T_839 @[el2_lib.scala 511:17] - rvclkhdr_16.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_840 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_840 <= i0_inst_wb @[el2_lib.scala 514:16] + rvclkhdr_16.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_16.io.en <= _T_839 @[lib.scala 371:17] + rvclkhdr_16.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_840 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_840 <= i0_inst_wb @[lib.scala 374:16] io.dec_i0_inst_wb1 <= _T_840 @[dec_decode_ctl.scala 723:22] node _T_841 = bits(i0_wb_data_en, 0, 0) @[dec_decode_ctl.scala 724:53] - inst rvclkhdr_17 of rvclkhdr_678 @[el2_lib.scala 508:23] + inst rvclkhdr_17 of rvclkhdr_678 @[lib.scala 368:23] rvclkhdr_17.clock <= clock rvclkhdr_17.reset <= reset - rvclkhdr_17.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_17.io.en <= _T_841 @[el2_lib.scala 511:17] - rvclkhdr_17.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg i0_pc_wb : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - i0_pc_wb <= io.dec_tlu_i0_pc_r @[el2_lib.scala 514:16] + rvclkhdr_17.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_17.io.en <= _T_841 @[lib.scala 371:17] + rvclkhdr_17.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg i0_pc_wb : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + i0_pc_wb <= io.dec_tlu_i0_pc_r @[lib.scala 374:16] node _T_842 = bits(i0_wb1_data_en, 0, 0) @[dec_decode_ctl.scala 726:49] - inst rvclkhdr_18 of rvclkhdr_679 @[el2_lib.scala 508:23] + inst rvclkhdr_18 of rvclkhdr_679 @[lib.scala 368:23] rvclkhdr_18.clock <= clock rvclkhdr_18.reset <= reset - rvclkhdr_18.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_18.io.en <= _T_842 @[el2_lib.scala 511:17] - rvclkhdr_18.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_843 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_843 <= i0_pc_wb @[el2_lib.scala 514:16] + rvclkhdr_18.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_18.io.en <= _T_842 @[lib.scala 371:17] + rvclkhdr_18.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_843 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_843 <= i0_pc_wb @[lib.scala 374:16] io.dec_i0_pc_wb1 <= _T_843 @[dec_decode_ctl.scala 726:20] node _T_844 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 727:64] - inst rvclkhdr_19 of rvclkhdr_680 @[el2_lib.scala 508:23] + inst rvclkhdr_19 of rvclkhdr_680 @[lib.scala 368:23] rvclkhdr_19.clock <= clock rvclkhdr_19.reset <= reset - rvclkhdr_19.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_19.io.en <= _T_844 @[el2_lib.scala 511:17] - rvclkhdr_19.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg dec_i0_pc_r : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - dec_i0_pc_r <= io.dec_alu.exu_i0_pc_x @[el2_lib.scala 514:16] + rvclkhdr_19.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_19.io.en <= _T_844 @[lib.scala 371:17] + rvclkhdr_19.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg dec_i0_pc_r : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + dec_i0_pc_r <= io.dec_alu.exu_i0_pc_x @[lib.scala 374:16] io.dec_tlu_i0_pc_r <= dec_i0_pc_r @[dec_decode_ctl.scala 729:27] node _T_845 = cat(io.dec_alu.exu_i0_pc_x, UInt<1>("h00")) @[Cat.scala 29:58] node _T_846 = cat(last_br_immed_x, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_847 = bits(_T_845, 12, 1) @[el2_lib.scala 208:24] - node _T_848 = bits(_T_846, 12, 1) @[el2_lib.scala 208:40] - node _T_849 = add(_T_847, _T_848) @[el2_lib.scala 208:31] - node _T_850 = bits(_T_845, 31, 13) @[el2_lib.scala 209:20] - node _T_851 = add(_T_850, UInt<1>("h01")) @[el2_lib.scala 209:27] - node _T_852 = tail(_T_851, 1) @[el2_lib.scala 209:27] - node _T_853 = bits(_T_845, 31, 13) @[el2_lib.scala 210:20] - node _T_854 = sub(_T_853, UInt<1>("h01")) @[el2_lib.scala 210:27] - node _T_855 = tail(_T_854, 1) @[el2_lib.scala 210:27] - node _T_856 = bits(_T_846, 12, 12) @[el2_lib.scala 211:22] - node _T_857 = bits(_T_849, 12, 12) @[el2_lib.scala 212:39] - node _T_858 = eq(_T_857, UInt<1>("h00")) @[el2_lib.scala 212:28] - node _T_859 = xor(_T_856, _T_858) @[el2_lib.scala 212:26] - node _T_860 = bits(_T_859, 0, 0) @[el2_lib.scala 212:64] - node _T_861 = bits(_T_845, 31, 13) @[el2_lib.scala 212:76] - node _T_862 = eq(_T_856, UInt<1>("h00")) @[el2_lib.scala 213:20] - node _T_863 = bits(_T_849, 12, 12) @[el2_lib.scala 213:39] - node _T_864 = and(_T_862, _T_863) @[el2_lib.scala 213:26] - node _T_865 = bits(_T_864, 0, 0) @[el2_lib.scala 213:64] - node _T_866 = bits(_T_849, 12, 12) @[el2_lib.scala 214:39] - node _T_867 = eq(_T_866, UInt<1>("h00")) @[el2_lib.scala 214:28] - node _T_868 = and(_T_856, _T_867) @[el2_lib.scala 214:26] - node _T_869 = bits(_T_868, 0, 0) @[el2_lib.scala 214:64] + node _T_847 = bits(_T_845, 12, 1) @[lib.scala 68:24] + node _T_848 = bits(_T_846, 12, 1) @[lib.scala 68:40] + node _T_849 = add(_T_847, _T_848) @[lib.scala 68:31] + node _T_850 = bits(_T_845, 31, 13) @[lib.scala 69:20] + node _T_851 = add(_T_850, UInt<1>("h01")) @[lib.scala 69:27] + node _T_852 = tail(_T_851, 1) @[lib.scala 69:27] + node _T_853 = bits(_T_845, 31, 13) @[lib.scala 70:20] + node _T_854 = sub(_T_853, UInt<1>("h01")) @[lib.scala 70:27] + node _T_855 = tail(_T_854, 1) @[lib.scala 70:27] + node _T_856 = bits(_T_846, 12, 12) @[lib.scala 71:22] + node _T_857 = bits(_T_849, 12, 12) @[lib.scala 72:39] + node _T_858 = eq(_T_857, UInt<1>("h00")) @[lib.scala 72:28] + node _T_859 = xor(_T_856, _T_858) @[lib.scala 72:26] + node _T_860 = bits(_T_859, 0, 0) @[lib.scala 72:64] + node _T_861 = bits(_T_845, 31, 13) @[lib.scala 72:76] + node _T_862 = eq(_T_856, UInt<1>("h00")) @[lib.scala 73:20] + node _T_863 = bits(_T_849, 12, 12) @[lib.scala 73:39] + node _T_864 = and(_T_862, _T_863) @[lib.scala 73:26] + node _T_865 = bits(_T_864, 0, 0) @[lib.scala 73:64] + node _T_866 = bits(_T_849, 12, 12) @[lib.scala 74:39] + node _T_867 = eq(_T_866, UInt<1>("h00")) @[lib.scala 74:28] + node _T_868 = and(_T_856, _T_867) @[lib.scala 74:26] + node _T_869 = bits(_T_868, 0, 0) @[lib.scala 74:64] node _T_870 = mux(_T_860, _T_861, UInt<1>("h00")) @[Mux.scala 27:72] node _T_871 = mux(_T_865, _T_852, UInt<1>("h00")) @[Mux.scala 27:72] node _T_872 = mux(_T_869, _T_855, UInt<1>("h00")) @[Mux.scala 27:72] @@ -69162,7 +69162,7 @@ circuit quasar_wrapper : node _T_874 = or(_T_873, _T_872) @[Mux.scala 27:72] wire _T_875 : UInt<19> @[Mux.scala 27:72] _T_875 <= _T_874 @[Mux.scala 27:72] - node _T_876 = bits(_T_849, 11, 0) @[el2_lib.scala 214:94] + node _T_876 = bits(_T_849, 11, 0) @[lib.scala 74:94] node _T_877 = cat(_T_875, _T_876) @[Cat.scala 29:58] node temp_pred_correct_npc_x = cat(_T_877, UInt<1>("h00")) @[Cat.scala 29:58] node _T_878 = bits(temp_pred_correct_npc_x, 31, 1) @[dec_decode_ctl.scala 734:62] @@ -69351,15 +69351,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_681 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_681 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_682 : output Q : Clock @@ -69375,15 +69375,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_682 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_682 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_683 : output Q : Clock @@ -69399,15 +69399,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_683 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_683 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_684 : output Q : Clock @@ -69423,15 +69423,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_684 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_684 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_685 : output Q : Clock @@ -69447,15 +69447,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_685 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_685 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_686 : output Q : Clock @@ -69471,15 +69471,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_686 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_686 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_687 : output Q : Clock @@ -69495,15 +69495,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_687 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_687 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_688 : output Q : Clock @@ -69519,15 +69519,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_688 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_688 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_689 : output Q : Clock @@ -69543,15 +69543,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_689 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_689 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_690 : output Q : Clock @@ -69567,15 +69567,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_690 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_690 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_691 : output Q : Clock @@ -69591,15 +69591,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_691 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_691 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_692 : output Q : Clock @@ -69615,15 +69615,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_692 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_692 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_693 : output Q : Clock @@ -69639,15 +69639,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_693 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_693 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_694 : output Q : Clock @@ -69663,15 +69663,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_694 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_694 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_695 : output Q : Clock @@ -69687,15 +69687,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_695 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_695 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_696 : output Q : Clock @@ -69711,15 +69711,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_696 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_696 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_697 : output Q : Clock @@ -69735,15 +69735,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_697 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_697 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_698 : output Q : Clock @@ -69759,15 +69759,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_698 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_698 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_699 : output Q : Clock @@ -69783,15 +69783,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_699 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_699 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_700 : output Q : Clock @@ -69807,15 +69807,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_700 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_700 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_701 : output Q : Clock @@ -69831,15 +69831,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_701 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_701 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_702 : output Q : Clock @@ -69855,15 +69855,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_702 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_702 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_703 : output Q : Clock @@ -69879,15 +69879,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_703 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_703 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_704 : output Q : Clock @@ -69903,15 +69903,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_704 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_704 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_705 : output Q : Clock @@ -69927,15 +69927,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_705 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_705 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_706 : output Q : Clock @@ -69951,15 +69951,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_706 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_706 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_707 : output Q : Clock @@ -69975,15 +69975,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_707 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_707 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_708 : output Q : Clock @@ -69999,15 +69999,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_708 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_708 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_709 : output Q : Clock @@ -70023,15 +70023,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_709 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_709 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_710 : output Q : Clock @@ -70047,15 +70047,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_710 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_710 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_711 : output Q : Clock @@ -70071,15 +70071,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_711 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_711 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] module dec_gpr_ctl : input clock : Clock @@ -71008,314 +71008,314 @@ circuit quasar_wrapper : node _T_621 = or(_T_589, _T_620) @[dec_gpr_ctl.scala 57:95] gpr_wr_en <= _T_621 @[dec_gpr_ctl.scala 57:18] node _T_622 = bits(gpr_wr_en, 1, 1) @[dec_gpr_ctl.scala 61:49] - inst rvclkhdr of rvclkhdr_681 @[el2_lib.scala 508:23] + inst rvclkhdr of rvclkhdr_681 @[lib.scala 368:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr.io.en <= _T_622 @[el2_lib.scala 511:17] - rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_623 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_623 <= gpr_in[1] @[el2_lib.scala 514:16] + rvclkhdr.io.clk <= clock @[lib.scala 370:18] + rvclkhdr.io.en <= _T_622 @[lib.scala 371:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_623 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_623 <= gpr_in[1] @[lib.scala 374:16] gpr_out[1] <= _T_623 @[dec_gpr_ctl.scala 61:21] node _T_624 = bits(gpr_wr_en, 2, 2) @[dec_gpr_ctl.scala 61:49] - inst rvclkhdr_1 of rvclkhdr_682 @[el2_lib.scala 508:23] + inst rvclkhdr_1 of rvclkhdr_682 @[lib.scala 368:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_1.io.en <= _T_624 @[el2_lib.scala 511:17] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_625 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_625 <= gpr_in[2] @[el2_lib.scala 514:16] + rvclkhdr_1.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_1.io.en <= _T_624 @[lib.scala 371:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_625 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_625 <= gpr_in[2] @[lib.scala 374:16] gpr_out[2] <= _T_625 @[dec_gpr_ctl.scala 61:21] node _T_626 = bits(gpr_wr_en, 3, 3) @[dec_gpr_ctl.scala 61:49] - inst rvclkhdr_2 of rvclkhdr_683 @[el2_lib.scala 508:23] + inst rvclkhdr_2 of rvclkhdr_683 @[lib.scala 368:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_2.io.en <= _T_626 @[el2_lib.scala 511:17] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_627 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_627 <= gpr_in[3] @[el2_lib.scala 514:16] + rvclkhdr_2.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_2.io.en <= _T_626 @[lib.scala 371:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_627 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_627 <= gpr_in[3] @[lib.scala 374:16] gpr_out[3] <= _T_627 @[dec_gpr_ctl.scala 61:21] node _T_628 = bits(gpr_wr_en, 4, 4) @[dec_gpr_ctl.scala 61:49] - inst rvclkhdr_3 of rvclkhdr_684 @[el2_lib.scala 508:23] + inst rvclkhdr_3 of rvclkhdr_684 @[lib.scala 368:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_3.io.en <= _T_628 @[el2_lib.scala 511:17] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_629 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_629 <= gpr_in[4] @[el2_lib.scala 514:16] + rvclkhdr_3.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_3.io.en <= _T_628 @[lib.scala 371:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_629 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_629 <= gpr_in[4] @[lib.scala 374:16] gpr_out[4] <= _T_629 @[dec_gpr_ctl.scala 61:21] node _T_630 = bits(gpr_wr_en, 5, 5) @[dec_gpr_ctl.scala 61:49] - inst rvclkhdr_4 of rvclkhdr_685 @[el2_lib.scala 508:23] + inst rvclkhdr_4 of rvclkhdr_685 @[lib.scala 368:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_4.io.en <= _T_630 @[el2_lib.scala 511:17] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_631 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_631 <= gpr_in[5] @[el2_lib.scala 514:16] + rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_4.io.en <= _T_630 @[lib.scala 371:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_631 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_631 <= gpr_in[5] @[lib.scala 374:16] gpr_out[5] <= _T_631 @[dec_gpr_ctl.scala 61:21] node _T_632 = bits(gpr_wr_en, 6, 6) @[dec_gpr_ctl.scala 61:49] - inst rvclkhdr_5 of rvclkhdr_686 @[el2_lib.scala 508:23] + inst rvclkhdr_5 of rvclkhdr_686 @[lib.scala 368:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_5.io.en <= _T_632 @[el2_lib.scala 511:17] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_633 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_633 <= gpr_in[6] @[el2_lib.scala 514:16] + rvclkhdr_5.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_5.io.en <= _T_632 @[lib.scala 371:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_633 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_633 <= gpr_in[6] @[lib.scala 374:16] gpr_out[6] <= _T_633 @[dec_gpr_ctl.scala 61:21] node _T_634 = bits(gpr_wr_en, 7, 7) @[dec_gpr_ctl.scala 61:49] - inst rvclkhdr_6 of rvclkhdr_687 @[el2_lib.scala 508:23] + inst rvclkhdr_6 of rvclkhdr_687 @[lib.scala 368:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset - rvclkhdr_6.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_6.io.en <= _T_634 @[el2_lib.scala 511:17] - rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_635 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_635 <= gpr_in[7] @[el2_lib.scala 514:16] + rvclkhdr_6.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_6.io.en <= _T_634 @[lib.scala 371:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_635 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_635 <= gpr_in[7] @[lib.scala 374:16] gpr_out[7] <= _T_635 @[dec_gpr_ctl.scala 61:21] node _T_636 = bits(gpr_wr_en, 8, 8) @[dec_gpr_ctl.scala 61:49] - inst rvclkhdr_7 of rvclkhdr_688 @[el2_lib.scala 508:23] + inst rvclkhdr_7 of rvclkhdr_688 @[lib.scala 368:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset - rvclkhdr_7.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_7.io.en <= _T_636 @[el2_lib.scala 511:17] - rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_637 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_637 <= gpr_in[8] @[el2_lib.scala 514:16] + rvclkhdr_7.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_7.io.en <= _T_636 @[lib.scala 371:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_637 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_637 <= gpr_in[8] @[lib.scala 374:16] gpr_out[8] <= _T_637 @[dec_gpr_ctl.scala 61:21] node _T_638 = bits(gpr_wr_en, 9, 9) @[dec_gpr_ctl.scala 61:49] - inst rvclkhdr_8 of rvclkhdr_689 @[el2_lib.scala 508:23] + inst rvclkhdr_8 of rvclkhdr_689 @[lib.scala 368:23] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset - rvclkhdr_8.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_8.io.en <= _T_638 @[el2_lib.scala 511:17] - rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_639 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_639 <= gpr_in[9] @[el2_lib.scala 514:16] + rvclkhdr_8.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_8.io.en <= _T_638 @[lib.scala 371:17] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_639 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_639 <= gpr_in[9] @[lib.scala 374:16] gpr_out[9] <= _T_639 @[dec_gpr_ctl.scala 61:21] node _T_640 = bits(gpr_wr_en, 10, 10) @[dec_gpr_ctl.scala 61:49] - inst rvclkhdr_9 of rvclkhdr_690 @[el2_lib.scala 508:23] + inst rvclkhdr_9 of rvclkhdr_690 @[lib.scala 368:23] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset - rvclkhdr_9.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_9.io.en <= _T_640 @[el2_lib.scala 511:17] - rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_641 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_641 <= gpr_in[10] @[el2_lib.scala 514:16] + rvclkhdr_9.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_9.io.en <= _T_640 @[lib.scala 371:17] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_641 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_641 <= gpr_in[10] @[lib.scala 374:16] gpr_out[10] <= _T_641 @[dec_gpr_ctl.scala 61:21] node _T_642 = bits(gpr_wr_en, 11, 11) @[dec_gpr_ctl.scala 61:49] - inst rvclkhdr_10 of rvclkhdr_691 @[el2_lib.scala 508:23] + inst rvclkhdr_10 of rvclkhdr_691 @[lib.scala 368:23] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset - rvclkhdr_10.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_10.io.en <= _T_642 @[el2_lib.scala 511:17] - rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_643 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_643 <= gpr_in[11] @[el2_lib.scala 514:16] + rvclkhdr_10.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_10.io.en <= _T_642 @[lib.scala 371:17] + rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_643 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_643 <= gpr_in[11] @[lib.scala 374:16] gpr_out[11] <= _T_643 @[dec_gpr_ctl.scala 61:21] node _T_644 = bits(gpr_wr_en, 12, 12) @[dec_gpr_ctl.scala 61:49] - inst rvclkhdr_11 of rvclkhdr_692 @[el2_lib.scala 508:23] + inst rvclkhdr_11 of rvclkhdr_692 @[lib.scala 368:23] rvclkhdr_11.clock <= clock rvclkhdr_11.reset <= reset - rvclkhdr_11.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_11.io.en <= _T_644 @[el2_lib.scala 511:17] - rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_645 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_645 <= gpr_in[12] @[el2_lib.scala 514:16] + rvclkhdr_11.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_11.io.en <= _T_644 @[lib.scala 371:17] + rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_645 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_645 <= gpr_in[12] @[lib.scala 374:16] gpr_out[12] <= _T_645 @[dec_gpr_ctl.scala 61:21] node _T_646 = bits(gpr_wr_en, 13, 13) @[dec_gpr_ctl.scala 61:49] - inst rvclkhdr_12 of rvclkhdr_693 @[el2_lib.scala 508:23] + inst rvclkhdr_12 of rvclkhdr_693 @[lib.scala 368:23] rvclkhdr_12.clock <= clock rvclkhdr_12.reset <= reset - rvclkhdr_12.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_12.io.en <= _T_646 @[el2_lib.scala 511:17] - rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_647 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_647 <= gpr_in[13] @[el2_lib.scala 514:16] + rvclkhdr_12.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_12.io.en <= _T_646 @[lib.scala 371:17] + rvclkhdr_12.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_647 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_647 <= gpr_in[13] @[lib.scala 374:16] gpr_out[13] <= _T_647 @[dec_gpr_ctl.scala 61:21] node _T_648 = bits(gpr_wr_en, 14, 14) @[dec_gpr_ctl.scala 61:49] - inst rvclkhdr_13 of rvclkhdr_694 @[el2_lib.scala 508:23] + inst rvclkhdr_13 of rvclkhdr_694 @[lib.scala 368:23] rvclkhdr_13.clock <= clock rvclkhdr_13.reset <= reset - rvclkhdr_13.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_13.io.en <= _T_648 @[el2_lib.scala 511:17] - rvclkhdr_13.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_649 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_649 <= gpr_in[14] @[el2_lib.scala 514:16] + rvclkhdr_13.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_13.io.en <= _T_648 @[lib.scala 371:17] + rvclkhdr_13.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_649 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_649 <= gpr_in[14] @[lib.scala 374:16] gpr_out[14] <= _T_649 @[dec_gpr_ctl.scala 61:21] node _T_650 = bits(gpr_wr_en, 15, 15) @[dec_gpr_ctl.scala 61:49] - inst rvclkhdr_14 of rvclkhdr_695 @[el2_lib.scala 508:23] + inst rvclkhdr_14 of rvclkhdr_695 @[lib.scala 368:23] rvclkhdr_14.clock <= clock rvclkhdr_14.reset <= reset - rvclkhdr_14.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_14.io.en <= _T_650 @[el2_lib.scala 511:17] - rvclkhdr_14.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_651 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_651 <= gpr_in[15] @[el2_lib.scala 514:16] + rvclkhdr_14.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_14.io.en <= _T_650 @[lib.scala 371:17] + rvclkhdr_14.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_651 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_651 <= gpr_in[15] @[lib.scala 374:16] gpr_out[15] <= _T_651 @[dec_gpr_ctl.scala 61:21] node _T_652 = bits(gpr_wr_en, 16, 16) @[dec_gpr_ctl.scala 61:49] - inst rvclkhdr_15 of rvclkhdr_696 @[el2_lib.scala 508:23] + inst rvclkhdr_15 of rvclkhdr_696 @[lib.scala 368:23] rvclkhdr_15.clock <= clock rvclkhdr_15.reset <= reset - rvclkhdr_15.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_15.io.en <= _T_652 @[el2_lib.scala 511:17] - rvclkhdr_15.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_653 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_653 <= gpr_in[16] @[el2_lib.scala 514:16] + rvclkhdr_15.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_15.io.en <= _T_652 @[lib.scala 371:17] + rvclkhdr_15.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_653 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_653 <= gpr_in[16] @[lib.scala 374:16] gpr_out[16] <= _T_653 @[dec_gpr_ctl.scala 61:21] node _T_654 = bits(gpr_wr_en, 17, 17) @[dec_gpr_ctl.scala 61:49] - inst rvclkhdr_16 of rvclkhdr_697 @[el2_lib.scala 508:23] + inst rvclkhdr_16 of rvclkhdr_697 @[lib.scala 368:23] rvclkhdr_16.clock <= clock rvclkhdr_16.reset <= reset - rvclkhdr_16.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_16.io.en <= _T_654 @[el2_lib.scala 511:17] - rvclkhdr_16.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_655 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_655 <= gpr_in[17] @[el2_lib.scala 514:16] + rvclkhdr_16.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_16.io.en <= _T_654 @[lib.scala 371:17] + rvclkhdr_16.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_655 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_655 <= gpr_in[17] @[lib.scala 374:16] gpr_out[17] <= _T_655 @[dec_gpr_ctl.scala 61:21] node _T_656 = bits(gpr_wr_en, 18, 18) @[dec_gpr_ctl.scala 61:49] - inst rvclkhdr_17 of rvclkhdr_698 @[el2_lib.scala 508:23] + inst rvclkhdr_17 of rvclkhdr_698 @[lib.scala 368:23] rvclkhdr_17.clock <= clock rvclkhdr_17.reset <= reset - rvclkhdr_17.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_17.io.en <= _T_656 @[el2_lib.scala 511:17] - rvclkhdr_17.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_657 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_657 <= gpr_in[18] @[el2_lib.scala 514:16] + rvclkhdr_17.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_17.io.en <= _T_656 @[lib.scala 371:17] + rvclkhdr_17.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_657 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_657 <= gpr_in[18] @[lib.scala 374:16] gpr_out[18] <= _T_657 @[dec_gpr_ctl.scala 61:21] node _T_658 = bits(gpr_wr_en, 19, 19) @[dec_gpr_ctl.scala 61:49] - inst rvclkhdr_18 of rvclkhdr_699 @[el2_lib.scala 508:23] + inst rvclkhdr_18 of rvclkhdr_699 @[lib.scala 368:23] rvclkhdr_18.clock <= clock rvclkhdr_18.reset <= reset - rvclkhdr_18.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_18.io.en <= _T_658 @[el2_lib.scala 511:17] - rvclkhdr_18.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_659 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_659 <= gpr_in[19] @[el2_lib.scala 514:16] + rvclkhdr_18.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_18.io.en <= _T_658 @[lib.scala 371:17] + rvclkhdr_18.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_659 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_659 <= gpr_in[19] @[lib.scala 374:16] gpr_out[19] <= _T_659 @[dec_gpr_ctl.scala 61:21] node _T_660 = bits(gpr_wr_en, 20, 20) @[dec_gpr_ctl.scala 61:49] - inst rvclkhdr_19 of rvclkhdr_700 @[el2_lib.scala 508:23] + inst rvclkhdr_19 of rvclkhdr_700 @[lib.scala 368:23] rvclkhdr_19.clock <= clock rvclkhdr_19.reset <= reset - rvclkhdr_19.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_19.io.en <= _T_660 @[el2_lib.scala 511:17] - rvclkhdr_19.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_661 : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_661 <= gpr_in[20] @[el2_lib.scala 514:16] + rvclkhdr_19.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_19.io.en <= _T_660 @[lib.scala 371:17] + rvclkhdr_19.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_661 : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_661 <= gpr_in[20] @[lib.scala 374:16] gpr_out[20] <= _T_661 @[dec_gpr_ctl.scala 61:21] node _T_662 = bits(gpr_wr_en, 21, 21) @[dec_gpr_ctl.scala 61:49] - inst rvclkhdr_20 of rvclkhdr_701 @[el2_lib.scala 508:23] + inst rvclkhdr_20 of rvclkhdr_701 @[lib.scala 368:23] rvclkhdr_20.clock <= clock rvclkhdr_20.reset <= reset - rvclkhdr_20.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_20.io.en <= _T_662 @[el2_lib.scala 511:17] - rvclkhdr_20.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_663 : UInt, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_663 <= gpr_in[21] @[el2_lib.scala 514:16] + rvclkhdr_20.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_20.io.en <= _T_662 @[lib.scala 371:17] + rvclkhdr_20.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_663 : UInt, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_663 <= gpr_in[21] @[lib.scala 374:16] gpr_out[21] <= _T_663 @[dec_gpr_ctl.scala 61:21] node _T_664 = bits(gpr_wr_en, 22, 22) @[dec_gpr_ctl.scala 61:49] - inst rvclkhdr_21 of rvclkhdr_702 @[el2_lib.scala 508:23] + inst rvclkhdr_21 of rvclkhdr_702 @[lib.scala 368:23] rvclkhdr_21.clock <= clock rvclkhdr_21.reset <= reset - rvclkhdr_21.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_21.io.en <= _T_664 @[el2_lib.scala 511:17] - rvclkhdr_21.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_665 : UInt, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_665 <= gpr_in[22] @[el2_lib.scala 514:16] + rvclkhdr_21.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_21.io.en <= _T_664 @[lib.scala 371:17] + rvclkhdr_21.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_665 : UInt, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_665 <= gpr_in[22] @[lib.scala 374:16] gpr_out[22] <= _T_665 @[dec_gpr_ctl.scala 61:21] node _T_666 = bits(gpr_wr_en, 23, 23) @[dec_gpr_ctl.scala 61:49] - inst rvclkhdr_22 of rvclkhdr_703 @[el2_lib.scala 508:23] + inst rvclkhdr_22 of rvclkhdr_703 @[lib.scala 368:23] rvclkhdr_22.clock <= clock rvclkhdr_22.reset <= reset - rvclkhdr_22.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_22.io.en <= _T_666 @[el2_lib.scala 511:17] - rvclkhdr_22.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_667 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_667 <= gpr_in[23] @[el2_lib.scala 514:16] + rvclkhdr_22.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_22.io.en <= _T_666 @[lib.scala 371:17] + rvclkhdr_22.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_667 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_667 <= gpr_in[23] @[lib.scala 374:16] gpr_out[23] <= _T_667 @[dec_gpr_ctl.scala 61:21] node _T_668 = bits(gpr_wr_en, 24, 24) @[dec_gpr_ctl.scala 61:49] - inst rvclkhdr_23 of rvclkhdr_704 @[el2_lib.scala 508:23] + inst rvclkhdr_23 of rvclkhdr_704 @[lib.scala 368:23] rvclkhdr_23.clock <= clock rvclkhdr_23.reset <= reset - rvclkhdr_23.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_23.io.en <= _T_668 @[el2_lib.scala 511:17] - rvclkhdr_23.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_669 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_669 <= gpr_in[24] @[el2_lib.scala 514:16] + rvclkhdr_23.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_23.io.en <= _T_668 @[lib.scala 371:17] + rvclkhdr_23.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_669 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_669 <= gpr_in[24] @[lib.scala 374:16] gpr_out[24] <= _T_669 @[dec_gpr_ctl.scala 61:21] node _T_670 = bits(gpr_wr_en, 25, 25) @[dec_gpr_ctl.scala 61:49] - inst rvclkhdr_24 of rvclkhdr_705 @[el2_lib.scala 508:23] + inst rvclkhdr_24 of rvclkhdr_705 @[lib.scala 368:23] rvclkhdr_24.clock <= clock rvclkhdr_24.reset <= reset - rvclkhdr_24.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_24.io.en <= _T_670 @[el2_lib.scala 511:17] - rvclkhdr_24.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_671 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_671 <= gpr_in[25] @[el2_lib.scala 514:16] + rvclkhdr_24.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_24.io.en <= _T_670 @[lib.scala 371:17] + rvclkhdr_24.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_671 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_671 <= gpr_in[25] @[lib.scala 374:16] gpr_out[25] <= _T_671 @[dec_gpr_ctl.scala 61:21] node _T_672 = bits(gpr_wr_en, 26, 26) @[dec_gpr_ctl.scala 61:49] - inst rvclkhdr_25 of rvclkhdr_706 @[el2_lib.scala 508:23] + inst rvclkhdr_25 of rvclkhdr_706 @[lib.scala 368:23] rvclkhdr_25.clock <= clock rvclkhdr_25.reset <= reset - rvclkhdr_25.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_25.io.en <= _T_672 @[el2_lib.scala 511:17] - rvclkhdr_25.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_673 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_673 <= gpr_in[26] @[el2_lib.scala 514:16] + rvclkhdr_25.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_25.io.en <= _T_672 @[lib.scala 371:17] + rvclkhdr_25.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_673 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_673 <= gpr_in[26] @[lib.scala 374:16] gpr_out[26] <= _T_673 @[dec_gpr_ctl.scala 61:21] node _T_674 = bits(gpr_wr_en, 27, 27) @[dec_gpr_ctl.scala 61:49] - inst rvclkhdr_26 of rvclkhdr_707 @[el2_lib.scala 508:23] + inst rvclkhdr_26 of rvclkhdr_707 @[lib.scala 368:23] rvclkhdr_26.clock <= clock rvclkhdr_26.reset <= reset - rvclkhdr_26.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_26.io.en <= _T_674 @[el2_lib.scala 511:17] - rvclkhdr_26.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_675 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_675 <= gpr_in[27] @[el2_lib.scala 514:16] + rvclkhdr_26.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_26.io.en <= _T_674 @[lib.scala 371:17] + rvclkhdr_26.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_675 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_675 <= gpr_in[27] @[lib.scala 374:16] gpr_out[27] <= _T_675 @[dec_gpr_ctl.scala 61:21] node _T_676 = bits(gpr_wr_en, 28, 28) @[dec_gpr_ctl.scala 61:49] - inst rvclkhdr_27 of rvclkhdr_708 @[el2_lib.scala 508:23] + inst rvclkhdr_27 of rvclkhdr_708 @[lib.scala 368:23] rvclkhdr_27.clock <= clock rvclkhdr_27.reset <= reset - rvclkhdr_27.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_27.io.en <= _T_676 @[el2_lib.scala 511:17] - rvclkhdr_27.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_677 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_677 <= gpr_in[28] @[el2_lib.scala 514:16] + rvclkhdr_27.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_27.io.en <= _T_676 @[lib.scala 371:17] + rvclkhdr_27.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_677 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_677 <= gpr_in[28] @[lib.scala 374:16] gpr_out[28] <= _T_677 @[dec_gpr_ctl.scala 61:21] node _T_678 = bits(gpr_wr_en, 29, 29) @[dec_gpr_ctl.scala 61:49] - inst rvclkhdr_28 of rvclkhdr_709 @[el2_lib.scala 508:23] + inst rvclkhdr_28 of rvclkhdr_709 @[lib.scala 368:23] rvclkhdr_28.clock <= clock rvclkhdr_28.reset <= reset - rvclkhdr_28.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_28.io.en <= _T_678 @[el2_lib.scala 511:17] - rvclkhdr_28.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_679 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_679 <= gpr_in[29] @[el2_lib.scala 514:16] + rvclkhdr_28.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_28.io.en <= _T_678 @[lib.scala 371:17] + rvclkhdr_28.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_679 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_679 <= gpr_in[29] @[lib.scala 374:16] gpr_out[29] <= _T_679 @[dec_gpr_ctl.scala 61:21] node _T_680 = bits(gpr_wr_en, 30, 30) @[dec_gpr_ctl.scala 61:49] - inst rvclkhdr_29 of rvclkhdr_710 @[el2_lib.scala 508:23] + inst rvclkhdr_29 of rvclkhdr_710 @[lib.scala 368:23] rvclkhdr_29.clock <= clock rvclkhdr_29.reset <= reset - rvclkhdr_29.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_29.io.en <= _T_680 @[el2_lib.scala 511:17] - rvclkhdr_29.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_681 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_681 <= gpr_in[30] @[el2_lib.scala 514:16] + rvclkhdr_29.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_29.io.en <= _T_680 @[lib.scala 371:17] + rvclkhdr_29.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_681 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_681 <= gpr_in[30] @[lib.scala 374:16] gpr_out[30] <= _T_681 @[dec_gpr_ctl.scala 61:21] node _T_682 = bits(gpr_wr_en, 31, 31) @[dec_gpr_ctl.scala 61:49] - inst rvclkhdr_30 of rvclkhdr_711 @[el2_lib.scala 508:23] + inst rvclkhdr_30 of rvclkhdr_711 @[lib.scala 368:23] rvclkhdr_30.clock <= clock rvclkhdr_30.reset <= reset - rvclkhdr_30.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_30.io.en <= _T_682 @[el2_lib.scala 511:17] - rvclkhdr_30.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_683 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_683 <= gpr_in[31] @[el2_lib.scala 514:16] + rvclkhdr_30.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_30.io.en <= _T_682 @[lib.scala 371:17] + rvclkhdr_30.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_683 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_683 <= gpr_in[31] @[lib.scala 374:16] gpr_out[31] <= _T_683 @[dec_gpr_ctl.scala 61:21] node _T_684 = eq(io.raddr0, UInt<1>("h01")) @[dec_gpr_ctl.scala 64:72] node _T_685 = bits(_T_684, 0, 0) @[dec_gpr_ctl.scala 64:80] @@ -71584,15 +71584,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_712 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_712 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_713 : output Q : Clock @@ -71608,15 +71608,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_713 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_713 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_714 : output Q : Clock @@ -71632,15 +71632,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_714 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_714 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_715 : output Q : Clock @@ -71656,15 +71656,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_715 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_715 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] module dec_timer_ctl : input clock : Clock @@ -71709,14 +71709,14 @@ circuit quasar_wrapper : node _T_15 = or(wr_mitcnt0_r, mitcnt0_inc_ok) @[dec_tlu_ctl.scala 2689:59] node _T_16 = or(_T_15, mit0_match_ns) @[dec_tlu_ctl.scala 2689:76] node _T_17 = bits(_T_16, 0, 0) @[dec_tlu_ctl.scala 2689:93] - inst rvclkhdr of rvclkhdr_712 @[el2_lib.scala 508:23] + inst rvclkhdr of rvclkhdr_712 @[lib.scala 368:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr.io.en <= _T_17 @[el2_lib.scala 511:17] - rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_18 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_18 <= mitcnt0_ns @[el2_lib.scala 514:16] + rvclkhdr.io.clk <= clock @[lib.scala 370:18] + rvclkhdr.io.en <= _T_17 @[lib.scala 371:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_18 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_18 <= mitcnt0_ns @[lib.scala 374:16] mitcnt0 <= _T_18 @[dec_tlu_ctl.scala 2689:25] node _T_19 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d5")) @[dec_tlu_ctl.scala 2696:72] node wr_mitcnt1_r = and(io.dec_csr_wen_r_mod, _T_19) @[dec_tlu_ctl.scala 2696:49] @@ -71745,41 +71745,41 @@ circuit quasar_wrapper : node _T_39 = or(wr_mitcnt1_r, mitcnt1_inc_ok) @[dec_tlu_ctl.scala 2703:60] node _T_40 = or(_T_39, mit1_match_ns) @[dec_tlu_ctl.scala 2703:77] node _T_41 = bits(_T_40, 0, 0) @[dec_tlu_ctl.scala 2703:94] - inst rvclkhdr_1 of rvclkhdr_713 @[el2_lib.scala 508:23] + inst rvclkhdr_1 of rvclkhdr_713 @[lib.scala 368:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_1.io.en <= _T_41 @[el2_lib.scala 511:17] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_42 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_42 <= mitcnt1_ns @[el2_lib.scala 514:16] + rvclkhdr_1.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_1.io.en <= _T_41 @[lib.scala 371:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_42 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_42 <= mitcnt1_ns @[lib.scala 374:16] mitcnt1 <= _T_42 @[dec_tlu_ctl.scala 2703:25] node _T_43 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d3")) @[dec_tlu_ctl.scala 2710:70] node wr_mitb0_r = and(io.dec_csr_wen_r_mod, _T_43) @[dec_tlu_ctl.scala 2710:47] node _T_44 = not(io.dec_csr_wrdata_r) @[dec_tlu_ctl.scala 2711:38] node _T_45 = bits(wr_mitb0_r, 0, 0) @[dec_tlu_ctl.scala 2711:71] - inst rvclkhdr_2 of rvclkhdr_714 @[el2_lib.scala 508:23] + inst rvclkhdr_2 of rvclkhdr_714 @[lib.scala 368:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_2.io.en <= _T_45 @[el2_lib.scala 511:17] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg mitb0_b : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - mitb0_b <= _T_44 @[el2_lib.scala 514:16] + rvclkhdr_2.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_2.io.en <= _T_45 @[lib.scala 371:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg mitb0_b : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + mitb0_b <= _T_44 @[lib.scala 374:16] node _T_46 = not(mitb0_b) @[dec_tlu_ctl.scala 2712:22] mitb0 <= _T_46 @[dec_tlu_ctl.scala 2712:19] node _T_47 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d6")) @[dec_tlu_ctl.scala 2719:69] node wr_mitb1_r = and(io.dec_csr_wen_r_mod, _T_47) @[dec_tlu_ctl.scala 2719:47] node _T_48 = not(io.dec_csr_wrdata_r) @[dec_tlu_ctl.scala 2720:29] node _T_49 = bits(wr_mitb1_r, 0, 0) @[dec_tlu_ctl.scala 2720:62] - inst rvclkhdr_3 of rvclkhdr_715 @[el2_lib.scala 508:23] + inst rvclkhdr_3 of rvclkhdr_715 @[lib.scala 368:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_3.io.en <= _T_49 @[el2_lib.scala 511:17] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg mitb1_b : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - mitb1_b <= _T_48 @[el2_lib.scala 514:16] + rvclkhdr_3.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_3.io.en <= _T_49 @[lib.scala 371:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg mitb1_b : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + mitb1_b <= _T_48 @[lib.scala 374:16] node _T_50 = not(mitb1_b) @[dec_tlu_ctl.scala 2721:18] mitb1 <= _T_50 @[dec_tlu_ctl.scala 2721:15] node _T_51 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d4")) @[dec_tlu_ctl.scala 2732:72] @@ -71860,15 +71860,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_716 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_716 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_717 : output Q : Clock @@ -71884,15 +71884,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_717 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_717 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_718 : output Q : Clock @@ -71908,15 +71908,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_718 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_718 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_719 : output Q : Clock @@ -71932,15 +71932,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_719 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_719 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_720 : output Q : Clock @@ -71956,15 +71956,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_720 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_720 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_721 : output Q : Clock @@ -71980,15 +71980,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_721 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_721 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_722 : output Q : Clock @@ -72004,15 +72004,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_722 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_722 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_723 : output Q : Clock @@ -72028,15 +72028,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_723 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_723 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_724 : output Q : Clock @@ -72052,15 +72052,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_724 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_724 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_725 : output Q : Clock @@ -72076,15 +72076,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_725 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_725 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_726 : output Q : Clock @@ -72100,15 +72100,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_726 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_726 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_727 : output Q : Clock @@ -72124,15 +72124,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_727 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_727 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_728 : output Q : Clock @@ -72148,15 +72148,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_728 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_728 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_729 : output Q : Clock @@ -72172,15 +72172,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_729 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_729 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_730 : output Q : Clock @@ -72196,15 +72196,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_730 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_730 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_731 : output Q : Clock @@ -72220,15 +72220,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_731 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_731 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_732 : output Q : Clock @@ -72244,15 +72244,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_732 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_732 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_733 : output Q : Clock @@ -72268,15 +72268,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_733 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_733 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_734 : output Q : Clock @@ -72292,15 +72292,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_734 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_734 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_735 : output Q : Clock @@ -72316,15 +72316,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_735 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_735 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_736 : output Q : Clock @@ -72340,15 +72340,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_736 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_736 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_737 : output Q : Clock @@ -72364,15 +72364,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_737 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_737 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_738 : output Q : Clock @@ -72388,15 +72388,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_738 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_738 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_739 : output Q : Clock @@ -72412,15 +72412,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_739 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_739 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_740 : output Q : Clock @@ -72436,15 +72436,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_740 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_740 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_741 : output Q : Clock @@ -72460,15 +72460,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_741 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_741 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_742 : output Q : Clock @@ -72484,15 +72484,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_742 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_742 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_743 : output Q : Clock @@ -72508,15 +72508,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_743 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_743 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_744 : output Q : Clock @@ -72532,15 +72532,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_744 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_744 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_745 : output Q : Clock @@ -72556,15 +72556,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_745 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_745 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_746 : output Q : Clock @@ -72580,15 +72580,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_746 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_746 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_747 : output Q : Clock @@ -72604,15 +72604,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_747 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_747 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_748 : output Q : Clock @@ -72628,15 +72628,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_748 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_748 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_749 : output Q : Clock @@ -72652,15 +72652,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_749 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_749 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_750 : output Q : Clock @@ -72676,15 +72676,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_750 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_750 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_751 : output Q : Clock @@ -72700,15 +72700,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_751 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_751 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_752 : output Q : Clock @@ -72724,15 +72724,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_752 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_752 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_753 : output Q : Clock @@ -72748,15 +72748,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_753 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_753 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_754 : output Q : Clock @@ -72772,15 +72772,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_754 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_754 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] module csr_tlu : input clock : Clock @@ -72975,14 +72975,14 @@ circuit quasar_wrapper : node _T_60 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1477:68] node mtvec_ns = cat(_T_59, _T_60) @[Cat.scala 29:58] node _T_61 = bits(wr_mtvec_r, 0, 0) @[dec_tlu_ctl.scala 1478:42] - inst rvclkhdr of rvclkhdr_720 @[el2_lib.scala 508:23] + inst rvclkhdr of rvclkhdr_720 @[lib.scala 368:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr.io.en <= _T_61 @[el2_lib.scala 511:17] - rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_62 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_62 <= mtvec_ns @[el2_lib.scala 514:16] + rvclkhdr.io.clk <= clock @[lib.scala 370:18] + rvclkhdr.io.en <= _T_61 @[lib.scala 371:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_62 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_62 <= mtvec_ns @[lib.scala 374:16] io.mtvec <= _T_62 @[dec_tlu_ctl.scala 1478:11] node _T_63 = or(mdccme_ce_req, miccme_ce_req) @[dec_tlu_ctl.scala 1490:30] node ce_int = or(_T_63, mice_ce_req) @[dec_tlu_ctl.scala 1490:46] @@ -73034,14 +73034,14 @@ circuit quasar_wrapper : node mcyclel_cout = bits(_T_94, 0, 0) @[dec_tlu_ctl.scala 1526:37] node _T_95 = or(wr_mcyclel_r, mcyclel_cout_in) @[dec_tlu_ctl.scala 1527:46] node _T_96 = bits(_T_95, 0, 0) @[dec_tlu_ctl.scala 1527:72] - inst rvclkhdr_1 of rvclkhdr_721 @[el2_lib.scala 508:23] + inst rvclkhdr_1 of rvclkhdr_721 @[lib.scala 368:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_1.io.en <= _T_96 @[el2_lib.scala 511:17] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_97 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_97 <= mcyclel_ns @[el2_lib.scala 514:16] + rvclkhdr_1.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_1.io.en <= _T_96 @[lib.scala 371:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_97 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_97 <= mcyclel_ns @[lib.scala 374:16] mcyclel <= _T_97 @[dec_tlu_ctl.scala 1527:10] node _T_98 = eq(wr_mcycleh_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1528:71] node _T_99 = and(mcyclel_cout, _T_98) @[dec_tlu_ctl.scala 1528:69] @@ -73058,14 +73058,14 @@ circuit quasar_wrapper : node mcycleh_ns = mux(_T_105, io.dec_csr_wrdata_r, mcycleh_inc) @[dec_tlu_ctl.scala 1537:22] node _T_106 = or(wr_mcycleh_r, mcyclel_cout_f) @[dec_tlu_ctl.scala 1539:46] node _T_107 = bits(_T_106, 0, 0) @[dec_tlu_ctl.scala 1539:64] - inst rvclkhdr_2 of rvclkhdr_722 @[el2_lib.scala 508:23] + inst rvclkhdr_2 of rvclkhdr_722 @[lib.scala 368:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_2.io.en <= _T_107 @[el2_lib.scala 511:17] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_108 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_108 <= mcycleh_ns @[el2_lib.scala 514:16] + rvclkhdr_2.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_2.io.en <= _T_107 @[lib.scala 371:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_108 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_108 <= mcycleh_ns @[lib.scala 374:16] mcycleh <= _T_108 @[dec_tlu_ctl.scala 1539:10] node _T_109 = or(io.ebreak_r, io.ecall_r) @[dec_tlu_ctl.scala 1553:72] node _T_110 = or(_T_109, io.ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 1553:85] @@ -73088,14 +73088,14 @@ circuit quasar_wrapper : node _T_122 = bits(minstretl_inc, 31, 0) @[dec_tlu_ctl.scala 1561:83] node minstretl_ns = mux(_T_121, io.dec_csr_wrdata_r, _T_122) @[dec_tlu_ctl.scala 1561:24] node _T_123 = bits(minstret_enable, 0, 0) @[dec_tlu_ctl.scala 1562:51] - inst rvclkhdr_3 of rvclkhdr_723 @[el2_lib.scala 508:23] + inst rvclkhdr_3 of rvclkhdr_723 @[lib.scala 368:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_3.io.en <= _T_123 @[el2_lib.scala 511:17] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_124 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_124 <= minstretl_ns @[el2_lib.scala 514:16] + rvclkhdr_3.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_3.io.en <= _T_123 @[lib.scala 371:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_124 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_124 <= minstretl_ns @[lib.scala 374:16] minstretl <= _T_124 @[dec_tlu_ctl.scala 1562:12] reg minstret_enable_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1563:56] minstret_enable_f <= minstret_enable @[dec_tlu_ctl.scala 1563:56] @@ -73116,27 +73116,27 @@ circuit quasar_wrapper : node minstreth_ns = mux(_T_134, io.dec_csr_wrdata_r, minstreth_inc) @[dec_tlu_ctl.scala 1576:25] node _T_135 = or(minstret_enable_f, wr_minstreth_r) @[dec_tlu_ctl.scala 1578:55] node _T_136 = bits(_T_135, 0, 0) @[dec_tlu_ctl.scala 1578:73] - inst rvclkhdr_4 of rvclkhdr_724 @[el2_lib.scala 508:23] + inst rvclkhdr_4 of rvclkhdr_724 @[lib.scala 368:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_4.io.en <= _T_136 @[el2_lib.scala 511:17] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_137 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_137 <= minstreth_ns @[el2_lib.scala 514:16] + rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_4.io.en <= _T_136 @[lib.scala 371:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_137 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_137 <= minstreth_ns @[lib.scala 374:16] minstreth <= _T_137 @[dec_tlu_ctl.scala 1578:12] node _T_138 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1586:65] node _T_139 = eq(_T_138, UInt<12>("h0340")) @[dec_tlu_ctl.scala 1586:72] node wr_mscratch_r = and(io.dec_csr_wen_r_mod, _T_139) @[dec_tlu_ctl.scala 1586:43] node _T_140 = bits(wr_mscratch_r, 0, 0) @[dec_tlu_ctl.scala 1588:55] - inst rvclkhdr_5 of rvclkhdr_725 @[el2_lib.scala 508:23] + inst rvclkhdr_5 of rvclkhdr_725 @[lib.scala 368:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_5.io.en <= _T_140 @[el2_lib.scala 511:17] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_141 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_141 <= io.dec_csr_wrdata_r @[el2_lib.scala 514:16] + rvclkhdr_5.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_5.io.en <= _T_140 @[lib.scala 371:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_141 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_141 <= io.dec_csr_wrdata_r @[lib.scala 374:16] mscratch <= _T_141 @[dec_tlu_ctl.scala 1588:11] node _T_142 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1597:22] node _T_143 = eq(io.tlu_flush_lower_r_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 1597:47] @@ -73168,14 +73168,14 @@ circuit quasar_wrapper : node _T_164 = or(sel_exu_npc_r, sel_flush_npc_r) @[dec_tlu_ctl.scala 1607:48] node _T_165 = or(_T_164, io.reset_delayed) @[dec_tlu_ctl.scala 1607:66] node _T_166 = bits(_T_165, 0, 0) @[dec_tlu_ctl.scala 1607:86] - inst rvclkhdr_6 of rvclkhdr_726 @[el2_lib.scala 508:23] + inst rvclkhdr_6 of rvclkhdr_726 @[lib.scala 368:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset - rvclkhdr_6.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_6.io.en <= _T_166 @[el2_lib.scala 511:17] - rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_167 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_167 <= io.npc_r @[el2_lib.scala 514:16] + rvclkhdr_6.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_6.io.en <= _T_166 @[lib.scala 371:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_167 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_167 <= io.npc_r @[lib.scala 374:16] io.npc_r_d1 <= _T_167 @[dec_tlu_ctl.scala 1607:14] node _T_168 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1610:21] node _T_169 = and(_T_168, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 1610:44] @@ -73186,14 +73186,14 @@ circuit quasar_wrapper : node _T_173 = or(_T_171, _T_172) @[Mux.scala 27:72] wire pc_r : UInt<31> @[Mux.scala 27:72] pc_r <= _T_173 @[Mux.scala 27:72] - inst rvclkhdr_7 of rvclkhdr_727 @[el2_lib.scala 508:23] + inst rvclkhdr_7 of rvclkhdr_727 @[lib.scala 368:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset - rvclkhdr_7.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_7.io.en <= pc0_valid_r @[el2_lib.scala 511:17] - rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_174 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_174 <= pc_r @[el2_lib.scala 514:16] + rvclkhdr_7.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_7.io.en <= pc0_valid_r @[lib.scala 371:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_174 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_174 <= pc_r @[lib.scala 374:16] pc_r_d1 <= _T_174 @[dec_tlu_ctl.scala 1616:10] node _T_175 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1618:61] node _T_176 = eq(_T_175, UInt<12>("h0341")) @[dec_tlu_ctl.scala 1618:68] @@ -73381,14 +73381,14 @@ circuit quasar_wrapper : node wr_mcgc_r = and(io.dec_csr_wen_r_mod, _T_325) @[dec_tlu_ctl.scala 1713:39] node _T_326 = bits(io.dec_csr_wrdata_r, 8, 0) @[dec_tlu_ctl.scala 1715:39] node _T_327 = bits(wr_mcgc_r, 0, 0) @[dec_tlu_ctl.scala 1715:55] - inst rvclkhdr_8 of rvclkhdr_728 @[el2_lib.scala 508:23] + inst rvclkhdr_8 of rvclkhdr_728 @[lib.scala 368:23] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset - rvclkhdr_8.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_8.io.en <= _T_327 @[el2_lib.scala 511:17] - rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg mcgc : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - mcgc <= _T_326 @[el2_lib.scala 514:16] + rvclkhdr_8.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_8.io.en <= _T_327 @[lib.scala 371:17] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg mcgc : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + mcgc <= _T_326 @[lib.scala 374:16] node _T_328 = bits(mcgc, 8, 8) @[dec_tlu_ctl.scala 1717:38] io.dec_tlu_misc_clk_override <= _T_328 @[dec_tlu_ctl.scala 1717:31] node _T_329 = bits(mcgc, 7, 7) @[dec_tlu_ctl.scala 1718:38] @@ -73409,991 +73409,983 @@ circuit quasar_wrapper : node _T_337 = eq(_T_336, UInt<12>("h07f9")) @[dec_tlu_ctl.scala 1743:68] node wr_mfdc_r = and(io.dec_csr_wen_r_mod, _T_337) @[dec_tlu_ctl.scala 1743:39] node _T_338 = bits(wr_mfdc_r, 0, 0) @[dec_tlu_ctl.scala 1747:39] - inst rvclkhdr_9 of rvclkhdr_729 @[el2_lib.scala 508:23] + inst rvclkhdr_9 of rvclkhdr_729 @[lib.scala 368:23] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset - rvclkhdr_9.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_9.io.en <= _T_338 @[el2_lib.scala 511:17] - rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_339 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_339 <= mfdc_ns @[el2_lib.scala 514:16] + rvclkhdr_9.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_9.io.en <= _T_338 @[lib.scala 371:17] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_339 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_339 <= mfdc_ns @[lib.scala 374:16] mfdc_int <= _T_339 @[dec_tlu_ctl.scala 1747:11] - node _T_340 = bits(io.dec_csr_wrdata_r, 18, 16) @[dec_tlu_ctl.scala 1752:40] - node _T_341 = not(_T_340) @[dec_tlu_ctl.scala 1752:20] - node _T_342 = bits(io.dec_csr_wrdata_r, 11, 7) @[dec_tlu_ctl.scala 1752:67] - node _T_343 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1752:95] - node _T_344 = not(_T_343) @[dec_tlu_ctl.scala 1752:75] - node _T_345 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1752:119] - node _T_346 = cat(_T_344, _T_345) @[Cat.scala 29:58] - node _T_347 = cat(_T_341, _T_342) @[Cat.scala 29:58] + node _T_340 = bits(io.dec_csr_wrdata_r, 18, 16) @[dec_tlu_ctl.scala 1756:39] + node _T_341 = not(_T_340) @[dec_tlu_ctl.scala 1756:19] + node _T_342 = bits(io.dec_csr_wrdata_r, 11, 0) @[dec_tlu_ctl.scala 1756:66] + node _T_343 = cat(_T_341, _T_342) @[Cat.scala 29:58] + mfdc_ns <= _T_343 @[dec_tlu_ctl.scala 1756:12] + node _T_344 = bits(mfdc_int, 14, 12) @[dec_tlu_ctl.scala 1757:28] + node _T_345 = not(_T_344) @[dec_tlu_ctl.scala 1757:19] + node _T_346 = bits(mfdc_int, 11, 0) @[dec_tlu_ctl.scala 1757:54] + node _T_347 = cat(_T_345, UInt<4>("h00")) @[Cat.scala 29:58] node _T_348 = cat(_T_347, _T_346) @[Cat.scala 29:58] - mfdc_ns <= _T_348 @[dec_tlu_ctl.scala 1752:13] - node _T_349 = bits(mfdc_int, 14, 12) @[dec_tlu_ctl.scala 1753:29] - node _T_350 = not(_T_349) @[dec_tlu_ctl.scala 1753:20] - node _T_351 = bits(mfdc_int, 11, 7) @[dec_tlu_ctl.scala 1753:55] - node _T_352 = bits(mfdc_int, 6, 6) @[dec_tlu_ctl.scala 1753:72] - node _T_353 = not(_T_352) @[dec_tlu_ctl.scala 1753:63] - node _T_354 = bits(mfdc_int, 5, 0) @[dec_tlu_ctl.scala 1753:85] - node _T_355 = cat(_T_353, _T_354) @[Cat.scala 29:58] - node _T_356 = cat(_T_350, UInt<4>("h00")) @[Cat.scala 29:58] - node _T_357 = cat(_T_356, _T_351) @[Cat.scala 29:58] - node _T_358 = cat(_T_357, _T_355) @[Cat.scala 29:58] - mfdc <= _T_358 @[dec_tlu_ctl.scala 1753:13] - node _T_359 = bits(mfdc, 18, 16) @[dec_tlu_ctl.scala 1761:46] - io.dec_tlu_dma_qos_prty <= _T_359 @[dec_tlu_ctl.scala 1761:39] - node _T_360 = bits(mfdc, 11, 11) @[dec_tlu_ctl.scala 1762:46] - io.dec_tlu_external_ldfwd_disable <= _T_360 @[dec_tlu_ctl.scala 1762:39] - node _T_361 = bits(mfdc, 8, 8) @[dec_tlu_ctl.scala 1763:46] - io.dec_tlu_core_ecc_disable <= _T_361 @[dec_tlu_ctl.scala 1763:39] - node _T_362 = bits(mfdc, 6, 6) @[dec_tlu_ctl.scala 1764:46] - io.dec_tlu_sideeffect_posted_disable <= _T_362 @[dec_tlu_ctl.scala 1764:39] - node _T_363 = bits(mfdc, 3, 3) @[dec_tlu_ctl.scala 1765:46] - io.dec_tlu_bpred_disable <= _T_363 @[dec_tlu_ctl.scala 1765:39] - node _T_364 = bits(mfdc, 2, 2) @[dec_tlu_ctl.scala 1766:46] - io.dec_tlu_wb_coalescing_disable <= _T_364 @[dec_tlu_ctl.scala 1766:39] - node _T_365 = bits(mfdc, 0, 0) @[dec_tlu_ctl.scala 1767:46] - io.dec_tlu_pipelining_disable <= _T_365 @[dec_tlu_ctl.scala 1767:39] - node _T_366 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1776:70] - node _T_367 = eq(_T_366, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 1776:77] - node _T_368 = and(io.dec_csr_wen_r_mod, _T_367) @[dec_tlu_ctl.scala 1776:48] - node _T_369 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1776:89] - node _T_370 = and(_T_368, _T_369) @[dec_tlu_ctl.scala 1776:87] - node _T_371 = not(io.take_ext_int_start) @[dec_tlu_ctl.scala 1776:113] - node _T_372 = and(_T_370, _T_371) @[dec_tlu_ctl.scala 1776:111] - io.dec_tlu_wr_pause_r <= _T_372 @[dec_tlu_ctl.scala 1776:24] - node _T_373 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1783:61] - node _T_374 = eq(_T_373, UInt<12>("h07c0")) @[dec_tlu_ctl.scala 1783:68] - node wr_mrac_r = and(io.dec_csr_wen_r_mod, _T_374) @[dec_tlu_ctl.scala 1783:39] - node _T_375 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1786:39] - node _T_376 = bits(io.dec_csr_wrdata_r, 30, 30) @[dec_tlu_ctl.scala 1786:64] - node _T_377 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1786:91] - node _T_378 = not(_T_377) @[dec_tlu_ctl.scala 1786:71] - node _T_379 = and(_T_376, _T_378) @[dec_tlu_ctl.scala 1786:69] - node _T_380 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1787:41] - node _T_381 = bits(io.dec_csr_wrdata_r, 28, 28) @[dec_tlu_ctl.scala 1787:66] - node _T_382 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1787:93] - node _T_383 = not(_T_382) @[dec_tlu_ctl.scala 1787:73] - node _T_384 = and(_T_381, _T_383) @[dec_tlu_ctl.scala 1787:71] - node _T_385 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1788:41] - node _T_386 = bits(io.dec_csr_wrdata_r, 26, 26) @[dec_tlu_ctl.scala 1788:66] - node _T_387 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1788:93] - node _T_388 = not(_T_387) @[dec_tlu_ctl.scala 1788:73] - node _T_389 = and(_T_386, _T_388) @[dec_tlu_ctl.scala 1788:71] - node _T_390 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1789:41] - node _T_391 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 1789:66] - node _T_392 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1789:93] - node _T_393 = not(_T_392) @[dec_tlu_ctl.scala 1789:73] - node _T_394 = and(_T_391, _T_393) @[dec_tlu_ctl.scala 1789:71] - node _T_395 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1790:41] - node _T_396 = bits(io.dec_csr_wrdata_r, 22, 22) @[dec_tlu_ctl.scala 1790:66] - node _T_397 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1790:93] - node _T_398 = not(_T_397) @[dec_tlu_ctl.scala 1790:73] - node _T_399 = and(_T_396, _T_398) @[dec_tlu_ctl.scala 1790:71] - node _T_400 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1791:41] - node _T_401 = bits(io.dec_csr_wrdata_r, 20, 20) @[dec_tlu_ctl.scala 1791:66] - node _T_402 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1791:93] - node _T_403 = not(_T_402) @[dec_tlu_ctl.scala 1791:73] - node _T_404 = and(_T_401, _T_403) @[dec_tlu_ctl.scala 1791:71] - node _T_405 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1792:41] - node _T_406 = bits(io.dec_csr_wrdata_r, 18, 18) @[dec_tlu_ctl.scala 1792:66] - node _T_407 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1792:93] - node _T_408 = not(_T_407) @[dec_tlu_ctl.scala 1792:73] - node _T_409 = and(_T_406, _T_408) @[dec_tlu_ctl.scala 1792:71] - node _T_410 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1793:41] - node _T_411 = bits(io.dec_csr_wrdata_r, 16, 16) @[dec_tlu_ctl.scala 1793:66] - node _T_412 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1793:93] - node _T_413 = not(_T_412) @[dec_tlu_ctl.scala 1793:73] - node _T_414 = and(_T_411, _T_413) @[dec_tlu_ctl.scala 1793:71] - node _T_415 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1794:41] - node _T_416 = bits(io.dec_csr_wrdata_r, 14, 14) @[dec_tlu_ctl.scala 1794:66] - node _T_417 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1794:93] - node _T_418 = not(_T_417) @[dec_tlu_ctl.scala 1794:73] - node _T_419 = and(_T_416, _T_418) @[dec_tlu_ctl.scala 1794:71] - node _T_420 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1795:41] - node _T_421 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 1795:66] - node _T_422 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1795:93] - node _T_423 = not(_T_422) @[dec_tlu_ctl.scala 1795:73] - node _T_424 = and(_T_421, _T_423) @[dec_tlu_ctl.scala 1795:71] - node _T_425 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1796:41] - node _T_426 = bits(io.dec_csr_wrdata_r, 10, 10) @[dec_tlu_ctl.scala 1796:66] - node _T_427 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1796:93] - node _T_428 = not(_T_427) @[dec_tlu_ctl.scala 1796:73] - node _T_429 = and(_T_426, _T_428) @[dec_tlu_ctl.scala 1796:71] - node _T_430 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1797:41] - node _T_431 = bits(io.dec_csr_wrdata_r, 8, 8) @[dec_tlu_ctl.scala 1797:66] - node _T_432 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1797:93] - node _T_433 = not(_T_432) @[dec_tlu_ctl.scala 1797:73] - node _T_434 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 1797:70] - node _T_435 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1798:41] - node _T_436 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1798:66] - node _T_437 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1798:93] - node _T_438 = not(_T_437) @[dec_tlu_ctl.scala 1798:73] - node _T_439 = and(_T_436, _T_438) @[dec_tlu_ctl.scala 1798:70] - node _T_440 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1799:41] - node _T_441 = bits(io.dec_csr_wrdata_r, 4, 4) @[dec_tlu_ctl.scala 1799:66] - node _T_442 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1799:93] - node _T_443 = not(_T_442) @[dec_tlu_ctl.scala 1799:73] - node _T_444 = and(_T_441, _T_443) @[dec_tlu_ctl.scala 1799:70] - node _T_445 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1800:41] - node _T_446 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 1800:66] - node _T_447 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1800:93] - node _T_448 = not(_T_447) @[dec_tlu_ctl.scala 1800:73] - node _T_449 = and(_T_446, _T_448) @[dec_tlu_ctl.scala 1800:70] - node _T_450 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1801:41] - node _T_451 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1801:66] - node _T_452 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1801:93] - node _T_453 = not(_T_452) @[dec_tlu_ctl.scala 1801:73] - node _T_454 = and(_T_451, _T_453) @[dec_tlu_ctl.scala 1801:70] - node _T_455 = cat(_T_450, _T_454) @[Cat.scala 29:58] - node _T_456 = cat(_T_445, _T_449) @[Cat.scala 29:58] + mfdc <= _T_348 @[dec_tlu_ctl.scala 1757:12] + node _T_349 = bits(mfdc, 18, 16) @[dec_tlu_ctl.scala 1761:46] + io.dec_tlu_dma_qos_prty <= _T_349 @[dec_tlu_ctl.scala 1761:39] + node _T_350 = bits(mfdc, 11, 11) @[dec_tlu_ctl.scala 1762:46] + io.dec_tlu_external_ldfwd_disable <= _T_350 @[dec_tlu_ctl.scala 1762:39] + node _T_351 = bits(mfdc, 8, 8) @[dec_tlu_ctl.scala 1763:46] + io.dec_tlu_core_ecc_disable <= _T_351 @[dec_tlu_ctl.scala 1763:39] + node _T_352 = bits(mfdc, 6, 6) @[dec_tlu_ctl.scala 1764:46] + io.dec_tlu_sideeffect_posted_disable <= _T_352 @[dec_tlu_ctl.scala 1764:39] + node _T_353 = bits(mfdc, 3, 3) @[dec_tlu_ctl.scala 1765:46] + io.dec_tlu_bpred_disable <= _T_353 @[dec_tlu_ctl.scala 1765:39] + node _T_354 = bits(mfdc, 2, 2) @[dec_tlu_ctl.scala 1766:46] + io.dec_tlu_wb_coalescing_disable <= _T_354 @[dec_tlu_ctl.scala 1766:39] + node _T_355 = bits(mfdc, 0, 0) @[dec_tlu_ctl.scala 1767:46] + io.dec_tlu_pipelining_disable <= _T_355 @[dec_tlu_ctl.scala 1767:39] + node _T_356 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1776:70] + node _T_357 = eq(_T_356, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 1776:77] + node _T_358 = and(io.dec_csr_wen_r_mod, _T_357) @[dec_tlu_ctl.scala 1776:48] + node _T_359 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1776:89] + node _T_360 = and(_T_358, _T_359) @[dec_tlu_ctl.scala 1776:87] + node _T_361 = not(io.take_ext_int_start) @[dec_tlu_ctl.scala 1776:113] + node _T_362 = and(_T_360, _T_361) @[dec_tlu_ctl.scala 1776:111] + io.dec_tlu_wr_pause_r <= _T_362 @[dec_tlu_ctl.scala 1776:24] + node _T_363 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1783:61] + node _T_364 = eq(_T_363, UInt<12>("h07c0")) @[dec_tlu_ctl.scala 1783:68] + node wr_mrac_r = and(io.dec_csr_wen_r_mod, _T_364) @[dec_tlu_ctl.scala 1783:39] + node _T_365 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1786:39] + node _T_366 = bits(io.dec_csr_wrdata_r, 30, 30) @[dec_tlu_ctl.scala 1786:64] + node _T_367 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1786:91] + node _T_368 = not(_T_367) @[dec_tlu_ctl.scala 1786:71] + node _T_369 = and(_T_366, _T_368) @[dec_tlu_ctl.scala 1786:69] + node _T_370 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1787:41] + node _T_371 = bits(io.dec_csr_wrdata_r, 28, 28) @[dec_tlu_ctl.scala 1787:66] + node _T_372 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1787:93] + node _T_373 = not(_T_372) @[dec_tlu_ctl.scala 1787:73] + node _T_374 = and(_T_371, _T_373) @[dec_tlu_ctl.scala 1787:71] + node _T_375 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1788:41] + node _T_376 = bits(io.dec_csr_wrdata_r, 26, 26) @[dec_tlu_ctl.scala 1788:66] + node _T_377 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1788:93] + node _T_378 = not(_T_377) @[dec_tlu_ctl.scala 1788:73] + node _T_379 = and(_T_376, _T_378) @[dec_tlu_ctl.scala 1788:71] + node _T_380 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1789:41] + node _T_381 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 1789:66] + node _T_382 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1789:93] + node _T_383 = not(_T_382) @[dec_tlu_ctl.scala 1789:73] + node _T_384 = and(_T_381, _T_383) @[dec_tlu_ctl.scala 1789:71] + node _T_385 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1790:41] + node _T_386 = bits(io.dec_csr_wrdata_r, 22, 22) @[dec_tlu_ctl.scala 1790:66] + node _T_387 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1790:93] + node _T_388 = not(_T_387) @[dec_tlu_ctl.scala 1790:73] + node _T_389 = and(_T_386, _T_388) @[dec_tlu_ctl.scala 1790:71] + node _T_390 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1791:41] + node _T_391 = bits(io.dec_csr_wrdata_r, 20, 20) @[dec_tlu_ctl.scala 1791:66] + node _T_392 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1791:93] + node _T_393 = not(_T_392) @[dec_tlu_ctl.scala 1791:73] + node _T_394 = and(_T_391, _T_393) @[dec_tlu_ctl.scala 1791:71] + node _T_395 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1792:41] + node _T_396 = bits(io.dec_csr_wrdata_r, 18, 18) @[dec_tlu_ctl.scala 1792:66] + node _T_397 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1792:93] + node _T_398 = not(_T_397) @[dec_tlu_ctl.scala 1792:73] + node _T_399 = and(_T_396, _T_398) @[dec_tlu_ctl.scala 1792:71] + node _T_400 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1793:41] + node _T_401 = bits(io.dec_csr_wrdata_r, 16, 16) @[dec_tlu_ctl.scala 1793:66] + node _T_402 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1793:93] + node _T_403 = not(_T_402) @[dec_tlu_ctl.scala 1793:73] + node _T_404 = and(_T_401, _T_403) @[dec_tlu_ctl.scala 1793:71] + node _T_405 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1794:41] + node _T_406 = bits(io.dec_csr_wrdata_r, 14, 14) @[dec_tlu_ctl.scala 1794:66] + node _T_407 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1794:93] + node _T_408 = not(_T_407) @[dec_tlu_ctl.scala 1794:73] + node _T_409 = and(_T_406, _T_408) @[dec_tlu_ctl.scala 1794:71] + node _T_410 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1795:41] + node _T_411 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 1795:66] + node _T_412 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1795:93] + node _T_413 = not(_T_412) @[dec_tlu_ctl.scala 1795:73] + node _T_414 = and(_T_411, _T_413) @[dec_tlu_ctl.scala 1795:71] + node _T_415 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1796:41] + node _T_416 = bits(io.dec_csr_wrdata_r, 10, 10) @[dec_tlu_ctl.scala 1796:66] + node _T_417 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1796:93] + node _T_418 = not(_T_417) @[dec_tlu_ctl.scala 1796:73] + node _T_419 = and(_T_416, _T_418) @[dec_tlu_ctl.scala 1796:71] + node _T_420 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1797:41] + node _T_421 = bits(io.dec_csr_wrdata_r, 8, 8) @[dec_tlu_ctl.scala 1797:66] + node _T_422 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1797:93] + node _T_423 = not(_T_422) @[dec_tlu_ctl.scala 1797:73] + node _T_424 = and(_T_421, _T_423) @[dec_tlu_ctl.scala 1797:70] + node _T_425 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1798:41] + node _T_426 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1798:66] + node _T_427 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1798:93] + node _T_428 = not(_T_427) @[dec_tlu_ctl.scala 1798:73] + node _T_429 = and(_T_426, _T_428) @[dec_tlu_ctl.scala 1798:70] + node _T_430 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1799:41] + node _T_431 = bits(io.dec_csr_wrdata_r, 4, 4) @[dec_tlu_ctl.scala 1799:66] + node _T_432 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1799:93] + node _T_433 = not(_T_432) @[dec_tlu_ctl.scala 1799:73] + node _T_434 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 1799:70] + node _T_435 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1800:41] + node _T_436 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 1800:66] + node _T_437 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1800:93] + node _T_438 = not(_T_437) @[dec_tlu_ctl.scala 1800:73] + node _T_439 = and(_T_436, _T_438) @[dec_tlu_ctl.scala 1800:70] + node _T_440 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1801:41] + node _T_441 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1801:66] + node _T_442 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1801:93] + node _T_443 = not(_T_442) @[dec_tlu_ctl.scala 1801:73] + node _T_444 = and(_T_441, _T_443) @[dec_tlu_ctl.scala 1801:70] + node _T_445 = cat(_T_440, _T_444) @[Cat.scala 29:58] + node _T_446 = cat(_T_435, _T_439) @[Cat.scala 29:58] + node _T_447 = cat(_T_446, _T_445) @[Cat.scala 29:58] + node _T_448 = cat(_T_430, _T_434) @[Cat.scala 29:58] + node _T_449 = cat(_T_425, _T_429) @[Cat.scala 29:58] + node _T_450 = cat(_T_449, _T_448) @[Cat.scala 29:58] + node _T_451 = cat(_T_450, _T_447) @[Cat.scala 29:58] + node _T_452 = cat(_T_420, _T_424) @[Cat.scala 29:58] + node _T_453 = cat(_T_415, _T_419) @[Cat.scala 29:58] + node _T_454 = cat(_T_453, _T_452) @[Cat.scala 29:58] + node _T_455 = cat(_T_410, _T_414) @[Cat.scala 29:58] + node _T_456 = cat(_T_405, _T_409) @[Cat.scala 29:58] node _T_457 = cat(_T_456, _T_455) @[Cat.scala 29:58] - node _T_458 = cat(_T_440, _T_444) @[Cat.scala 29:58] - node _T_459 = cat(_T_435, _T_439) @[Cat.scala 29:58] - node _T_460 = cat(_T_459, _T_458) @[Cat.scala 29:58] - node _T_461 = cat(_T_460, _T_457) @[Cat.scala 29:58] - node _T_462 = cat(_T_430, _T_434) @[Cat.scala 29:58] - node _T_463 = cat(_T_425, _T_429) @[Cat.scala 29:58] - node _T_464 = cat(_T_463, _T_462) @[Cat.scala 29:58] - node _T_465 = cat(_T_420, _T_424) @[Cat.scala 29:58] - node _T_466 = cat(_T_415, _T_419) @[Cat.scala 29:58] - node _T_467 = cat(_T_466, _T_465) @[Cat.scala 29:58] - node _T_468 = cat(_T_467, _T_464) @[Cat.scala 29:58] - node _T_469 = cat(_T_468, _T_461) @[Cat.scala 29:58] - node _T_470 = cat(_T_410, _T_414) @[Cat.scala 29:58] - node _T_471 = cat(_T_405, _T_409) @[Cat.scala 29:58] + node _T_458 = cat(_T_457, _T_454) @[Cat.scala 29:58] + node _T_459 = cat(_T_458, _T_451) @[Cat.scala 29:58] + node _T_460 = cat(_T_400, _T_404) @[Cat.scala 29:58] + node _T_461 = cat(_T_395, _T_399) @[Cat.scala 29:58] + node _T_462 = cat(_T_461, _T_460) @[Cat.scala 29:58] + node _T_463 = cat(_T_390, _T_394) @[Cat.scala 29:58] + node _T_464 = cat(_T_385, _T_389) @[Cat.scala 29:58] + node _T_465 = cat(_T_464, _T_463) @[Cat.scala 29:58] + node _T_466 = cat(_T_465, _T_462) @[Cat.scala 29:58] + node _T_467 = cat(_T_380, _T_384) @[Cat.scala 29:58] + node _T_468 = cat(_T_375, _T_379) @[Cat.scala 29:58] + node _T_469 = cat(_T_468, _T_467) @[Cat.scala 29:58] + node _T_470 = cat(_T_370, _T_374) @[Cat.scala 29:58] + node _T_471 = cat(_T_365, _T_369) @[Cat.scala 29:58] node _T_472 = cat(_T_471, _T_470) @[Cat.scala 29:58] - node _T_473 = cat(_T_400, _T_404) @[Cat.scala 29:58] - node _T_474 = cat(_T_395, _T_399) @[Cat.scala 29:58] - node _T_475 = cat(_T_474, _T_473) @[Cat.scala 29:58] - node _T_476 = cat(_T_475, _T_472) @[Cat.scala 29:58] - node _T_477 = cat(_T_390, _T_394) @[Cat.scala 29:58] - node _T_478 = cat(_T_385, _T_389) @[Cat.scala 29:58] - node _T_479 = cat(_T_478, _T_477) @[Cat.scala 29:58] - node _T_480 = cat(_T_380, _T_384) @[Cat.scala 29:58] - node _T_481 = cat(_T_375, _T_379) @[Cat.scala 29:58] - node _T_482 = cat(_T_481, _T_480) @[Cat.scala 29:58] - node _T_483 = cat(_T_482, _T_479) @[Cat.scala 29:58] - node _T_484 = cat(_T_483, _T_476) @[Cat.scala 29:58] - node mrac_in = cat(_T_484, _T_469) @[Cat.scala 29:58] - node _T_485 = bits(wr_mrac_r, 0, 0) @[dec_tlu_ctl.scala 1804:38] - inst rvclkhdr_10 of rvclkhdr_730 @[el2_lib.scala 508:23] + node _T_473 = cat(_T_472, _T_469) @[Cat.scala 29:58] + node _T_474 = cat(_T_473, _T_466) @[Cat.scala 29:58] + node mrac_in = cat(_T_474, _T_459) @[Cat.scala 29:58] + node _T_475 = bits(wr_mrac_r, 0, 0) @[dec_tlu_ctl.scala 1804:38] + inst rvclkhdr_10 of rvclkhdr_730 @[lib.scala 368:23] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset - rvclkhdr_10.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_10.io.en <= _T_485 @[el2_lib.scala 511:17] - rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg mrac : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - mrac <= mrac_in @[el2_lib.scala 514:16] + rvclkhdr_10.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_10.io.en <= _T_475 @[lib.scala 371:17] + rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg mrac : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + mrac <= mrac_in @[lib.scala 374:16] io.dec_tlu_mrac_ff <= mrac @[dec_tlu_ctl.scala 1806:21] - node _T_486 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1814:62] - node _T_487 = eq(_T_486, UInt<12>("h0bc0")) @[dec_tlu_ctl.scala 1814:69] - node wr_mdeau_r = and(io.dec_csr_wen_r_mod, _T_487) @[dec_tlu_ctl.scala 1814:40] - node _T_488 = not(wr_mdeau_r) @[dec_tlu_ctl.scala 1824:59] - node _T_489 = and(io.mdseac_locked_f, _T_488) @[dec_tlu_ctl.scala 1824:57] - node _T_490 = or(mdseac_en, _T_489) @[dec_tlu_ctl.scala 1824:35] - io.mdseac_locked_ns <= _T_490 @[dec_tlu_ctl.scala 1824:22] - node _T_491 = or(io.lsu_imprecise_error_store_any, io.lsu_imprecise_error_load_any) @[dec_tlu_ctl.scala 1826:49] - node _T_492 = not(io.nmi_int_detected_f) @[dec_tlu_ctl.scala 1826:86] - node _T_493 = and(_T_491, _T_492) @[dec_tlu_ctl.scala 1826:84] - node _T_494 = not(io.mdseac_locked_f) @[dec_tlu_ctl.scala 1826:111] - node _T_495 = and(_T_493, _T_494) @[dec_tlu_ctl.scala 1826:109] - mdseac_en <= _T_495 @[dec_tlu_ctl.scala 1826:12] - node _T_496 = bits(mdseac_en, 0, 0) @[dec_tlu_ctl.scala 1828:64] - inst rvclkhdr_11 of rvclkhdr_731 @[el2_lib.scala 508:23] + node _T_476 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1814:62] + node _T_477 = eq(_T_476, UInt<12>("h0bc0")) @[dec_tlu_ctl.scala 1814:69] + node wr_mdeau_r = and(io.dec_csr_wen_r_mod, _T_477) @[dec_tlu_ctl.scala 1814:40] + node _T_478 = not(wr_mdeau_r) @[dec_tlu_ctl.scala 1824:59] + node _T_479 = and(io.mdseac_locked_f, _T_478) @[dec_tlu_ctl.scala 1824:57] + node _T_480 = or(mdseac_en, _T_479) @[dec_tlu_ctl.scala 1824:35] + io.mdseac_locked_ns <= _T_480 @[dec_tlu_ctl.scala 1824:22] + node _T_481 = or(io.lsu_imprecise_error_store_any, io.lsu_imprecise_error_load_any) @[dec_tlu_ctl.scala 1826:49] + node _T_482 = not(io.nmi_int_detected_f) @[dec_tlu_ctl.scala 1826:86] + node _T_483 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 1826:84] + node _T_484 = not(io.mdseac_locked_f) @[dec_tlu_ctl.scala 1826:111] + node _T_485 = and(_T_483, _T_484) @[dec_tlu_ctl.scala 1826:109] + mdseac_en <= _T_485 @[dec_tlu_ctl.scala 1826:12] + node _T_486 = bits(mdseac_en, 0, 0) @[dec_tlu_ctl.scala 1828:64] + inst rvclkhdr_11 of rvclkhdr_731 @[lib.scala 368:23] rvclkhdr_11.clock <= clock rvclkhdr_11.reset <= reset - rvclkhdr_11.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_11.io.en <= _T_496 @[el2_lib.scala 511:17] - rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg mdseac : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - mdseac <= io.lsu_imprecise_error_addr_any @[el2_lib.scala 514:16] - node _T_497 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1837:61] - node _T_498 = eq(_T_497, UInt<12>("h07c6")) @[dec_tlu_ctl.scala 1837:68] - node wr_mpmc_r = and(io.dec_csr_wen_r_mod, _T_498) @[dec_tlu_ctl.scala 1837:39] - node _T_499 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1841:51] - node _T_500 = and(wr_mpmc_r, _T_499) @[dec_tlu_ctl.scala 1841:30] - node _T_501 = not(io.internal_dbg_halt_mode_f2) @[dec_tlu_ctl.scala 1841:57] - node _T_502 = and(_T_500, _T_501) @[dec_tlu_ctl.scala 1841:55] - node _T_503 = not(io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 1841:89] - node _T_504 = and(_T_502, _T_503) @[dec_tlu_ctl.scala 1841:87] - io.fw_halt_req <= _T_504 @[dec_tlu_ctl.scala 1841:17] + rvclkhdr_11.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_11.io.en <= _T_486 @[lib.scala 371:17] + rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg mdseac : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + mdseac <= io.lsu_imprecise_error_addr_any @[lib.scala 374:16] + node _T_487 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1837:61] + node _T_488 = eq(_T_487, UInt<12>("h07c6")) @[dec_tlu_ctl.scala 1837:68] + node wr_mpmc_r = and(io.dec_csr_wen_r_mod, _T_488) @[dec_tlu_ctl.scala 1837:39] + node _T_489 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1841:51] + node _T_490 = and(wr_mpmc_r, _T_489) @[dec_tlu_ctl.scala 1841:30] + node _T_491 = not(io.internal_dbg_halt_mode_f2) @[dec_tlu_ctl.scala 1841:57] + node _T_492 = and(_T_490, _T_491) @[dec_tlu_ctl.scala 1841:55] + node _T_493 = not(io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 1841:89] + node _T_494 = and(_T_492, _T_493) @[dec_tlu_ctl.scala 1841:87] + io.fw_halt_req <= _T_494 @[dec_tlu_ctl.scala 1841:17] wire fw_halted_ns : UInt<1> fw_halted_ns <= UInt<1>("h00") reg fw_halted : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1843:48] fw_halted <= fw_halted_ns @[dec_tlu_ctl.scala 1843:48] - node _T_505 = or(io.fw_halt_req, fw_halted) @[dec_tlu_ctl.scala 1844:34] - node _T_506 = not(set_mie_pmu_fw_halt) @[dec_tlu_ctl.scala 1844:49] - node _T_507 = and(_T_505, _T_506) @[dec_tlu_ctl.scala 1844:47] - fw_halted_ns <= _T_507 @[dec_tlu_ctl.scala 1844:15] - node _T_508 = bits(wr_mpmc_r, 0, 0) @[dec_tlu_ctl.scala 1845:29] - node _T_509 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1845:57] - node _T_510 = not(_T_509) @[dec_tlu_ctl.scala 1845:37] - node _T_511 = not(mpmc) @[dec_tlu_ctl.scala 1845:62] - node _T_512 = mux(_T_508, _T_510, _T_511) @[dec_tlu_ctl.scala 1845:18] - mpmc_b_ns <= _T_512 @[dec_tlu_ctl.scala 1845:12] - reg _T_513 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1847:44] - _T_513 <= mpmc_b_ns @[dec_tlu_ctl.scala 1847:44] - mpmc_b <= _T_513 @[dec_tlu_ctl.scala 1847:9] - node _T_514 = not(mpmc_b) @[dec_tlu_ctl.scala 1850:10] - mpmc <= _T_514 @[dec_tlu_ctl.scala 1850:7] - node _T_515 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1859:40] - node _T_516 = gt(_T_515, UInt<5>("h01a")) @[dec_tlu_ctl.scala 1859:48] - node _T_517 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1859:92] - node csr_sat = mux(_T_516, UInt<5>("h01a"), _T_517) @[dec_tlu_ctl.scala 1859:19] - node _T_518 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1861:63] - node _T_519 = eq(_T_518, UInt<12>("h07f0")) @[dec_tlu_ctl.scala 1861:70] - node wr_micect_r = and(io.dec_csr_wen_r_mod, _T_519) @[dec_tlu_ctl.scala 1861:41] - node _T_520 = cat(UInt<26>("h00"), io.ic_perr_r_d1) @[Cat.scala 29:58] - node _T_521 = add(micect, _T_520) @[dec_tlu_ctl.scala 1862:23] - node _T_522 = tail(_T_521, 1) @[dec_tlu_ctl.scala 1862:23] - micect_inc <= _T_522 @[dec_tlu_ctl.scala 1862:13] - node _T_523 = bits(wr_micect_r, 0, 0) @[dec_tlu_ctl.scala 1863:35] - node _T_524 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1863:75] - node _T_525 = cat(csr_sat, _T_524) @[Cat.scala 29:58] - node _T_526 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1863:95] - node _T_527 = cat(_T_526, micect_inc) @[Cat.scala 29:58] - node micect_ns = mux(_T_523, _T_525, _T_527) @[dec_tlu_ctl.scala 1863:22] - node _T_528 = or(wr_micect_r, io.ic_perr_r_d1) @[dec_tlu_ctl.scala 1865:42] - node _T_529 = bits(_T_528, 0, 0) @[dec_tlu_ctl.scala 1865:61] - inst rvclkhdr_12 of rvclkhdr_732 @[el2_lib.scala 508:23] + node _T_495 = or(io.fw_halt_req, fw_halted) @[dec_tlu_ctl.scala 1844:34] + node _T_496 = not(set_mie_pmu_fw_halt) @[dec_tlu_ctl.scala 1844:49] + node _T_497 = and(_T_495, _T_496) @[dec_tlu_ctl.scala 1844:47] + fw_halted_ns <= _T_497 @[dec_tlu_ctl.scala 1844:15] + node _T_498 = bits(wr_mpmc_r, 0, 0) @[dec_tlu_ctl.scala 1845:29] + node _T_499 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1845:57] + node _T_500 = not(_T_499) @[dec_tlu_ctl.scala 1845:37] + node _T_501 = not(mpmc) @[dec_tlu_ctl.scala 1845:62] + node _T_502 = mux(_T_498, _T_500, _T_501) @[dec_tlu_ctl.scala 1845:18] + mpmc_b_ns <= _T_502 @[dec_tlu_ctl.scala 1845:12] + reg _T_503 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1847:44] + _T_503 <= mpmc_b_ns @[dec_tlu_ctl.scala 1847:44] + mpmc_b <= _T_503 @[dec_tlu_ctl.scala 1847:9] + node _T_504 = not(mpmc_b) @[dec_tlu_ctl.scala 1850:10] + mpmc <= _T_504 @[dec_tlu_ctl.scala 1850:7] + node _T_505 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1859:40] + node _T_506 = gt(_T_505, UInt<5>("h01a")) @[dec_tlu_ctl.scala 1859:48] + node _T_507 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1859:92] + node csr_sat = mux(_T_506, UInt<5>("h01a"), _T_507) @[dec_tlu_ctl.scala 1859:19] + node _T_508 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1861:63] + node _T_509 = eq(_T_508, UInt<12>("h07f0")) @[dec_tlu_ctl.scala 1861:70] + node wr_micect_r = and(io.dec_csr_wen_r_mod, _T_509) @[dec_tlu_ctl.scala 1861:41] + node _T_510 = cat(UInt<26>("h00"), io.ic_perr_r_d1) @[Cat.scala 29:58] + node _T_511 = add(micect, _T_510) @[dec_tlu_ctl.scala 1862:23] + node _T_512 = tail(_T_511, 1) @[dec_tlu_ctl.scala 1862:23] + micect_inc <= _T_512 @[dec_tlu_ctl.scala 1862:13] + node _T_513 = bits(wr_micect_r, 0, 0) @[dec_tlu_ctl.scala 1863:35] + node _T_514 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1863:75] + node _T_515 = cat(csr_sat, _T_514) @[Cat.scala 29:58] + node _T_516 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1863:95] + node _T_517 = cat(_T_516, micect_inc) @[Cat.scala 29:58] + node micect_ns = mux(_T_513, _T_515, _T_517) @[dec_tlu_ctl.scala 1863:22] + node _T_518 = or(wr_micect_r, io.ic_perr_r_d1) @[dec_tlu_ctl.scala 1865:42] + node _T_519 = bits(_T_518, 0, 0) @[dec_tlu_ctl.scala 1865:61] + inst rvclkhdr_12 of rvclkhdr_732 @[lib.scala 368:23] rvclkhdr_12.clock <= clock rvclkhdr_12.reset <= reset - rvclkhdr_12.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_12.io.en <= _T_529 @[el2_lib.scala 511:17] - rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_530 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_530 <= micect_ns @[el2_lib.scala 514:16] - micect <= _T_530 @[dec_tlu_ctl.scala 1865:9] - node _T_531 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1867:48] - node _T_532 = dshl(UInt<32>("h0ffffffff"), _T_531) @[dec_tlu_ctl.scala 1867:39] - node _T_533 = bits(micect, 26, 0) @[dec_tlu_ctl.scala 1867:79] - node _T_534 = cat(UInt<5>("h00"), _T_533) @[Cat.scala 29:58] - node _T_535 = and(_T_532, _T_534) @[dec_tlu_ctl.scala 1867:57] - node _T_536 = orr(_T_535) @[dec_tlu_ctl.scala 1867:88] - mice_ce_req <= _T_536 @[dec_tlu_ctl.scala 1867:14] - node _T_537 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1876:69] - node _T_538 = eq(_T_537, UInt<12>("h07f1")) @[dec_tlu_ctl.scala 1876:76] - node wr_miccmect_r = and(io.dec_csr_wen_r_mod, _T_538) @[dec_tlu_ctl.scala 1876:47] - node _T_539 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1877:26] - node _T_540 = or(io.iccm_sbecc_r_d1, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1877:70] - node _T_541 = cat(UInt<26>("h00"), _T_540) @[Cat.scala 29:58] - node _T_542 = add(_T_539, _T_541) @[dec_tlu_ctl.scala 1877:33] - node _T_543 = tail(_T_542, 1) @[dec_tlu_ctl.scala 1877:33] - miccmect_inc <= _T_543 @[dec_tlu_ctl.scala 1877:15] - node _T_544 = bits(wr_miccmect_r, 0, 0) @[dec_tlu_ctl.scala 1878:45] - node _T_545 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1878:85] - node _T_546 = cat(csr_sat, _T_545) @[Cat.scala 29:58] - node _T_547 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1878:107] - node _T_548 = cat(_T_547, miccmect_inc) @[Cat.scala 29:58] - node miccmect_ns = mux(_T_544, _T_546, _T_548) @[dec_tlu_ctl.scala 1878:30] - node _T_549 = or(wr_miccmect_r, io.iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 1880:48] - node _T_550 = or(_T_549, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1880:69] - node _T_551 = bits(_T_550, 0, 0) @[dec_tlu_ctl.scala 1880:93] - inst rvclkhdr_13 of rvclkhdr_733 @[el2_lib.scala 508:23] + rvclkhdr_12.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_12.io.en <= _T_519 @[lib.scala 371:17] + rvclkhdr_12.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_520 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_520 <= micect_ns @[lib.scala 374:16] + micect <= _T_520 @[dec_tlu_ctl.scala 1865:9] + node _T_521 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1867:48] + node _T_522 = dshl(UInt<32>("h0ffffffff"), _T_521) @[dec_tlu_ctl.scala 1867:39] + node _T_523 = bits(micect, 26, 0) @[dec_tlu_ctl.scala 1867:79] + node _T_524 = cat(UInt<5>("h00"), _T_523) @[Cat.scala 29:58] + node _T_525 = and(_T_522, _T_524) @[dec_tlu_ctl.scala 1867:57] + node _T_526 = orr(_T_525) @[dec_tlu_ctl.scala 1867:88] + mice_ce_req <= _T_526 @[dec_tlu_ctl.scala 1867:14] + node _T_527 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1876:69] + node _T_528 = eq(_T_527, UInt<12>("h07f1")) @[dec_tlu_ctl.scala 1876:76] + node wr_miccmect_r = and(io.dec_csr_wen_r_mod, _T_528) @[dec_tlu_ctl.scala 1876:47] + node _T_529 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1877:26] + node _T_530 = or(io.iccm_sbecc_r_d1, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1877:70] + node _T_531 = cat(UInt<26>("h00"), _T_530) @[Cat.scala 29:58] + node _T_532 = add(_T_529, _T_531) @[dec_tlu_ctl.scala 1877:33] + node _T_533 = tail(_T_532, 1) @[dec_tlu_ctl.scala 1877:33] + miccmect_inc <= _T_533 @[dec_tlu_ctl.scala 1877:15] + node _T_534 = bits(wr_miccmect_r, 0, 0) @[dec_tlu_ctl.scala 1878:45] + node _T_535 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1878:85] + node _T_536 = cat(csr_sat, _T_535) @[Cat.scala 29:58] + node _T_537 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1878:107] + node _T_538 = cat(_T_537, miccmect_inc) @[Cat.scala 29:58] + node miccmect_ns = mux(_T_534, _T_536, _T_538) @[dec_tlu_ctl.scala 1878:30] + node _T_539 = or(wr_miccmect_r, io.iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 1880:48] + node _T_540 = or(_T_539, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1880:69] + node _T_541 = bits(_T_540, 0, 0) @[dec_tlu_ctl.scala 1880:93] + inst rvclkhdr_13 of rvclkhdr_733 @[lib.scala 368:23] rvclkhdr_13.clock <= clock rvclkhdr_13.reset <= reset - rvclkhdr_13.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_13.io.en <= _T_551 @[el2_lib.scala 511:17] - rvclkhdr_13.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_552 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_552 <= miccmect_ns @[el2_lib.scala 514:16] - miccmect <= _T_552 @[dec_tlu_ctl.scala 1880:11] - node _T_553 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1882:51] - node _T_554 = dshl(UInt<32>("h0ffffffff"), _T_553) @[dec_tlu_ctl.scala 1882:40] - node _T_555 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1882:84] - node _T_556 = cat(UInt<5>("h00"), _T_555) @[Cat.scala 29:58] - node _T_557 = and(_T_554, _T_556) @[dec_tlu_ctl.scala 1882:60] - node _T_558 = orr(_T_557) @[dec_tlu_ctl.scala 1882:93] - miccme_ce_req <= _T_558 @[dec_tlu_ctl.scala 1882:15] - node _T_559 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1891:69] - node _T_560 = eq(_T_559, UInt<12>("h07f2")) @[dec_tlu_ctl.scala 1891:76] - node wr_mdccmect_r = and(io.dec_csr_wen_r_mod, _T_560) @[dec_tlu_ctl.scala 1891:47] - node _T_561 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1892:26] - node _T_562 = cat(UInt<26>("h00"), io.lsu_single_ecc_error_r_d1) @[Cat.scala 29:58] - node _T_563 = add(_T_561, _T_562) @[dec_tlu_ctl.scala 1892:33] - node _T_564 = tail(_T_563, 1) @[dec_tlu_ctl.scala 1892:33] - mdccmect_inc <= _T_564 @[dec_tlu_ctl.scala 1892:15] - node _T_565 = bits(wr_mdccmect_r, 0, 0) @[dec_tlu_ctl.scala 1893:45] - node _T_566 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1893:85] - node _T_567 = cat(csr_sat, _T_566) @[Cat.scala 29:58] - node _T_568 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1893:107] - node _T_569 = cat(_T_568, mdccmect_inc) @[Cat.scala 29:58] - node mdccmect_ns = mux(_T_565, _T_567, _T_569) @[dec_tlu_ctl.scala 1893:30] - node _T_570 = or(wr_mdccmect_r, io.lsu_single_ecc_error_r_d1) @[dec_tlu_ctl.scala 1895:49] - node _T_571 = bits(_T_570, 0, 0) @[dec_tlu_ctl.scala 1895:81] - inst rvclkhdr_14 of rvclkhdr_734 @[el2_lib.scala 508:23] + rvclkhdr_13.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_13.io.en <= _T_541 @[lib.scala 371:17] + rvclkhdr_13.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_542 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_542 <= miccmect_ns @[lib.scala 374:16] + miccmect <= _T_542 @[dec_tlu_ctl.scala 1880:11] + node _T_543 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1882:51] + node _T_544 = dshl(UInt<32>("h0ffffffff"), _T_543) @[dec_tlu_ctl.scala 1882:40] + node _T_545 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1882:84] + node _T_546 = cat(UInt<5>("h00"), _T_545) @[Cat.scala 29:58] + node _T_547 = and(_T_544, _T_546) @[dec_tlu_ctl.scala 1882:60] + node _T_548 = orr(_T_547) @[dec_tlu_ctl.scala 1882:93] + miccme_ce_req <= _T_548 @[dec_tlu_ctl.scala 1882:15] + node _T_549 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1891:69] + node _T_550 = eq(_T_549, UInt<12>("h07f2")) @[dec_tlu_ctl.scala 1891:76] + node wr_mdccmect_r = and(io.dec_csr_wen_r_mod, _T_550) @[dec_tlu_ctl.scala 1891:47] + node _T_551 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1892:26] + node _T_552 = cat(UInt<26>("h00"), io.lsu_single_ecc_error_r_d1) @[Cat.scala 29:58] + node _T_553 = add(_T_551, _T_552) @[dec_tlu_ctl.scala 1892:33] + node _T_554 = tail(_T_553, 1) @[dec_tlu_ctl.scala 1892:33] + mdccmect_inc <= _T_554 @[dec_tlu_ctl.scala 1892:15] + node _T_555 = bits(wr_mdccmect_r, 0, 0) @[dec_tlu_ctl.scala 1893:45] + node _T_556 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1893:85] + node _T_557 = cat(csr_sat, _T_556) @[Cat.scala 29:58] + node _T_558 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1893:107] + node _T_559 = cat(_T_558, mdccmect_inc) @[Cat.scala 29:58] + node mdccmect_ns = mux(_T_555, _T_557, _T_559) @[dec_tlu_ctl.scala 1893:30] + node _T_560 = or(wr_mdccmect_r, io.lsu_single_ecc_error_r_d1) @[dec_tlu_ctl.scala 1895:49] + node _T_561 = bits(_T_560, 0, 0) @[dec_tlu_ctl.scala 1895:81] + inst rvclkhdr_14 of rvclkhdr_734 @[lib.scala 368:23] rvclkhdr_14.clock <= clock rvclkhdr_14.reset <= reset - rvclkhdr_14.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_14.io.en <= _T_571 @[el2_lib.scala 511:17] - rvclkhdr_14.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_572 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_572 <= mdccmect_ns @[el2_lib.scala 514:16] - mdccmect <= _T_572 @[dec_tlu_ctl.scala 1895:11] - node _T_573 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1897:52] - node _T_574 = dshl(UInt<32>("h0ffffffff"), _T_573) @[dec_tlu_ctl.scala 1897:41] - node _T_575 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1897:85] - node _T_576 = cat(UInt<5>("h00"), _T_575) @[Cat.scala 29:58] - node _T_577 = and(_T_574, _T_576) @[dec_tlu_ctl.scala 1897:61] - node _T_578 = orr(_T_577) @[dec_tlu_ctl.scala 1897:94] - mdccme_ce_req <= _T_578 @[dec_tlu_ctl.scala 1897:16] - node _T_579 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1907:62] - node _T_580 = eq(_T_579, UInt<12>("h07ce")) @[dec_tlu_ctl.scala 1907:69] - node wr_mfdht_r = and(io.dec_csr_wen_r_mod, _T_580) @[dec_tlu_ctl.scala 1907:40] - node _T_581 = bits(wr_mfdht_r, 0, 0) @[dec_tlu_ctl.scala 1909:32] - node _T_582 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1909:59] - node mfdht_ns = mux(_T_581, _T_582, mfdht) @[dec_tlu_ctl.scala 1909:20] - reg _T_583 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1911:43] - _T_583 <= mfdht_ns @[dec_tlu_ctl.scala 1911:43] - mfdht <= _T_583 @[dec_tlu_ctl.scala 1911:8] - node _T_584 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1920:62] - node _T_585 = eq(_T_584, UInt<12>("h07cf")) @[dec_tlu_ctl.scala 1920:69] - node wr_mfdhs_r = and(io.dec_csr_wen_r_mod, _T_585) @[dec_tlu_ctl.scala 1920:40] - node _T_586 = bits(wr_mfdhs_r, 0, 0) @[dec_tlu_ctl.scala 1922:32] - node _T_587 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 1922:60] - node _T_588 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1923:43] - node _T_589 = and(io.dbg_tlu_halted, _T_588) @[dec_tlu_ctl.scala 1923:41] - node _T_590 = bits(_T_589, 0, 0) @[dec_tlu_ctl.scala 1923:65] - node _T_591 = not(io.lsu_idle_any_f) @[dec_tlu_ctl.scala 1923:78] - node _T_592 = not(io.ifu_miss_state_idle_f) @[dec_tlu_ctl.scala 1923:98] - node _T_593 = cat(_T_591, _T_592) @[Cat.scala 29:58] - node _T_594 = mux(_T_590, _T_593, mfdhs) @[dec_tlu_ctl.scala 1923:21] - node mfdhs_ns = mux(_T_586, _T_587, _T_594) @[dec_tlu_ctl.scala 1922:20] - node _T_595 = or(wr_mfdhs_r, io.dbg_tlu_halted) @[dec_tlu_ctl.scala 1925:71] - node _T_596 = bits(_T_595, 0, 0) @[dec_tlu_ctl.scala 1925:92] - reg _T_597 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_596 : @[Reg.scala 28:19] - _T_597 <= mfdhs_ns @[Reg.scala 28:23] + rvclkhdr_14.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_14.io.en <= _T_561 @[lib.scala 371:17] + rvclkhdr_14.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_562 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_562 <= mdccmect_ns @[lib.scala 374:16] + mdccmect <= _T_562 @[dec_tlu_ctl.scala 1895:11] + node _T_563 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1897:52] + node _T_564 = dshl(UInt<32>("h0ffffffff"), _T_563) @[dec_tlu_ctl.scala 1897:41] + node _T_565 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1897:85] + node _T_566 = cat(UInt<5>("h00"), _T_565) @[Cat.scala 29:58] + node _T_567 = and(_T_564, _T_566) @[dec_tlu_ctl.scala 1897:61] + node _T_568 = orr(_T_567) @[dec_tlu_ctl.scala 1897:94] + mdccme_ce_req <= _T_568 @[dec_tlu_ctl.scala 1897:16] + node _T_569 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1907:62] + node _T_570 = eq(_T_569, UInt<12>("h07ce")) @[dec_tlu_ctl.scala 1907:69] + node wr_mfdht_r = and(io.dec_csr_wen_r_mod, _T_570) @[dec_tlu_ctl.scala 1907:40] + node _T_571 = bits(wr_mfdht_r, 0, 0) @[dec_tlu_ctl.scala 1909:32] + node _T_572 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1909:59] + node mfdht_ns = mux(_T_571, _T_572, mfdht) @[dec_tlu_ctl.scala 1909:20] + reg _T_573 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1911:43] + _T_573 <= mfdht_ns @[dec_tlu_ctl.scala 1911:43] + mfdht <= _T_573 @[dec_tlu_ctl.scala 1911:8] + node _T_574 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1920:62] + node _T_575 = eq(_T_574, UInt<12>("h07cf")) @[dec_tlu_ctl.scala 1920:69] + node wr_mfdhs_r = and(io.dec_csr_wen_r_mod, _T_575) @[dec_tlu_ctl.scala 1920:40] + node _T_576 = bits(wr_mfdhs_r, 0, 0) @[dec_tlu_ctl.scala 1922:32] + node _T_577 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 1922:60] + node _T_578 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1923:43] + node _T_579 = and(io.dbg_tlu_halted, _T_578) @[dec_tlu_ctl.scala 1923:41] + node _T_580 = bits(_T_579, 0, 0) @[dec_tlu_ctl.scala 1923:65] + node _T_581 = not(io.lsu_idle_any_f) @[dec_tlu_ctl.scala 1923:78] + node _T_582 = not(io.ifu_miss_state_idle_f) @[dec_tlu_ctl.scala 1923:98] + node _T_583 = cat(_T_581, _T_582) @[Cat.scala 29:58] + node _T_584 = mux(_T_580, _T_583, mfdhs) @[dec_tlu_ctl.scala 1923:21] + node mfdhs_ns = mux(_T_576, _T_577, _T_584) @[dec_tlu_ctl.scala 1922:20] + node _T_585 = or(wr_mfdhs_r, io.dbg_tlu_halted) @[dec_tlu_ctl.scala 1925:71] + node _T_586 = bits(_T_585, 0, 0) @[dec_tlu_ctl.scala 1925:92] + reg _T_587 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_586 : @[Reg.scala 28:19] + _T_587 <= mfdhs_ns @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mfdhs <= _T_597 @[dec_tlu_ctl.scala 1925:8] - node _T_598 = bits(io.debug_halt_req_f, 0, 0) @[dec_tlu_ctl.scala 1927:47] - node _T_599 = add(force_halt_ctr_f, UInt<32>("h01")) @[dec_tlu_ctl.scala 1927:74] - node _T_600 = tail(_T_599, 1) @[dec_tlu_ctl.scala 1927:74] - node _T_601 = bits(io.dbg_tlu_halted_f, 0, 0) @[dec_tlu_ctl.scala 1928:48] - node _T_602 = mux(_T_601, UInt<32>("h00"), force_halt_ctr_f) @[dec_tlu_ctl.scala 1928:27] - node force_halt_ctr = mux(_T_598, _T_600, _T_602) @[dec_tlu_ctl.scala 1927:26] - node _T_603 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1930:81] - reg _T_604 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_603 : @[Reg.scala 28:19] - _T_604 <= force_halt_ctr @[Reg.scala 28:23] + mfdhs <= _T_587 @[dec_tlu_ctl.scala 1925:8] + node _T_588 = bits(io.debug_halt_req_f, 0, 0) @[dec_tlu_ctl.scala 1927:47] + node _T_589 = add(force_halt_ctr_f, UInt<32>("h01")) @[dec_tlu_ctl.scala 1927:74] + node _T_590 = tail(_T_589, 1) @[dec_tlu_ctl.scala 1927:74] + node _T_591 = bits(io.dbg_tlu_halted_f, 0, 0) @[dec_tlu_ctl.scala 1928:48] + node _T_592 = mux(_T_591, UInt<32>("h00"), force_halt_ctr_f) @[dec_tlu_ctl.scala 1928:27] + node force_halt_ctr = mux(_T_588, _T_590, _T_592) @[dec_tlu_ctl.scala 1927:26] + node _T_593 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1930:81] + reg _T_594 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_593 : @[Reg.scala 28:19] + _T_594 <= force_halt_ctr @[Reg.scala 28:23] skip @[Reg.scala 28:19] - force_halt_ctr_f <= _T_604 @[dec_tlu_ctl.scala 1930:19] - node _T_605 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1932:24] - node _T_606 = bits(mfdht, 5, 1) @[dec_tlu_ctl.scala 1932:79] - node _T_607 = dshl(UInt<32>("h0ffffffff"), _T_606) @[dec_tlu_ctl.scala 1932:71] - node _T_608 = and(force_halt_ctr_f, _T_607) @[dec_tlu_ctl.scala 1932:48] - node _T_609 = orr(_T_608) @[dec_tlu_ctl.scala 1932:87] - node _T_610 = and(_T_605, _T_609) @[dec_tlu_ctl.scala 1932:28] - io.force_halt <= _T_610 @[dec_tlu_ctl.scala 1932:16] - node _T_611 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1940:62] - node _T_612 = eq(_T_611, UInt<12>("h0bc8")) @[dec_tlu_ctl.scala 1940:69] - node wr_meivt_r = and(io.dec_csr_wen_r_mod, _T_612) @[dec_tlu_ctl.scala 1940:40] - node _T_613 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 1942:40] - node _T_614 = bits(wr_meivt_r, 0, 0) @[dec_tlu_ctl.scala 1942:59] - inst rvclkhdr_15 of rvclkhdr_735 @[el2_lib.scala 508:23] + force_halt_ctr_f <= _T_594 @[dec_tlu_ctl.scala 1930:19] + node _T_595 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1932:24] + node _T_596 = bits(mfdht, 5, 1) @[dec_tlu_ctl.scala 1932:79] + node _T_597 = dshl(UInt<32>("h0ffffffff"), _T_596) @[dec_tlu_ctl.scala 1932:71] + node _T_598 = and(force_halt_ctr_f, _T_597) @[dec_tlu_ctl.scala 1932:48] + node _T_599 = orr(_T_598) @[dec_tlu_ctl.scala 1932:87] + node _T_600 = and(_T_595, _T_599) @[dec_tlu_ctl.scala 1932:28] + io.force_halt <= _T_600 @[dec_tlu_ctl.scala 1932:16] + node _T_601 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1940:62] + node _T_602 = eq(_T_601, UInt<12>("h0bc8")) @[dec_tlu_ctl.scala 1940:69] + node wr_meivt_r = and(io.dec_csr_wen_r_mod, _T_602) @[dec_tlu_ctl.scala 1940:40] + node _T_603 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 1942:40] + node _T_604 = bits(wr_meivt_r, 0, 0) @[dec_tlu_ctl.scala 1942:59] + inst rvclkhdr_15 of rvclkhdr_735 @[lib.scala 368:23] rvclkhdr_15.clock <= clock rvclkhdr_15.reset <= reset - rvclkhdr_15.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_15.io.en <= _T_614 @[el2_lib.scala 511:17] - rvclkhdr_15.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg meivt : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - meivt <= _T_613 @[el2_lib.scala 514:16] - node _T_615 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1954:49] - inst rvclkhdr_16 of rvclkhdr_736 @[el2_lib.scala 508:23] + rvclkhdr_15.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_15.io.en <= _T_604 @[lib.scala 371:17] + rvclkhdr_15.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg meivt : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + meivt <= _T_603 @[lib.scala 374:16] + node _T_605 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1954:49] + inst rvclkhdr_16 of rvclkhdr_736 @[lib.scala 368:23] rvclkhdr_16.clock <= clock rvclkhdr_16.reset <= reset - rvclkhdr_16.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_16.io.en <= _T_615 @[el2_lib.scala 511:17] - rvclkhdr_16.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg meihap : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - meihap <= io.pic_claimid @[el2_lib.scala 514:16] - node _T_616 = cat(meivt, meihap) @[Cat.scala 29:58] - io.dec_tlu_meihap <= _T_616 @[dec_tlu_ctl.scala 1955:20] - node _T_617 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1964:65] - node _T_618 = eq(_T_617, UInt<12>("h0bcc")) @[dec_tlu_ctl.scala 1964:72] - node wr_meicurpl_r = and(io.dec_csr_wen_r_mod, _T_618) @[dec_tlu_ctl.scala 1964:43] - node _T_619 = bits(wr_meicurpl_r, 0, 0) @[dec_tlu_ctl.scala 1965:38] - node _T_620 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1965:65] - node meicurpl_ns = mux(_T_619, _T_620, meicurpl) @[dec_tlu_ctl.scala 1965:23] - reg _T_621 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1967:46] - _T_621 <= meicurpl_ns @[dec_tlu_ctl.scala 1967:46] - meicurpl <= _T_621 @[dec_tlu_ctl.scala 1967:11] + rvclkhdr_16.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_16.io.en <= _T_605 @[lib.scala 371:17] + rvclkhdr_16.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg meihap : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + meihap <= io.pic_claimid @[lib.scala 374:16] + node _T_606 = cat(meivt, meihap) @[Cat.scala 29:58] + io.dec_tlu_meihap <= _T_606 @[dec_tlu_ctl.scala 1955:20] + node _T_607 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1964:65] + node _T_608 = eq(_T_607, UInt<12>("h0bcc")) @[dec_tlu_ctl.scala 1964:72] + node wr_meicurpl_r = and(io.dec_csr_wen_r_mod, _T_608) @[dec_tlu_ctl.scala 1964:43] + node _T_609 = bits(wr_meicurpl_r, 0, 0) @[dec_tlu_ctl.scala 1965:38] + node _T_610 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1965:65] + node meicurpl_ns = mux(_T_609, _T_610, meicurpl) @[dec_tlu_ctl.scala 1965:23] + reg _T_611 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1967:46] + _T_611 <= meicurpl_ns @[dec_tlu_ctl.scala 1967:46] + meicurpl <= _T_611 @[dec_tlu_ctl.scala 1967:11] io.dec_tlu_meicurpl <= meicurpl @[dec_tlu_ctl.scala 1969:22] - node _T_622 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1979:66] - node _T_623 = eq(_T_622, UInt<12>("h0bcb")) @[dec_tlu_ctl.scala 1979:73] - node _T_624 = and(io.dec_csr_wen_r_mod, _T_623) @[dec_tlu_ctl.scala 1979:44] - node wr_meicidpl_r = or(_T_624, io.take_ext_int_start) @[dec_tlu_ctl.scala 1979:88] - node _T_625 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1981:37] - node _T_626 = bits(wr_meicidpl_r, 0, 0) @[dec_tlu_ctl.scala 1982:38] - node _T_627 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1982:65] - node _T_628 = mux(_T_626, _T_627, meicidpl) @[dec_tlu_ctl.scala 1982:23] - node meicidpl_ns = mux(_T_625, io.pic_pl, _T_628) @[dec_tlu_ctl.scala 1981:23] - reg _T_629 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1984:44] - _T_629 <= meicidpl_ns @[dec_tlu_ctl.scala 1984:44] - meicidpl <= _T_629 @[dec_tlu_ctl.scala 1984:11] - node _T_630 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1991:62] - node _T_631 = eq(_T_630, UInt<12>("h0bca")) @[dec_tlu_ctl.scala 1991:69] - node _T_632 = and(io.dec_csr_wen_r_mod, _T_631) @[dec_tlu_ctl.scala 1991:40] - node _T_633 = or(_T_632, io.take_ext_int_start) @[dec_tlu_ctl.scala 1991:83] - wr_meicpct_r <= _T_633 @[dec_tlu_ctl.scala 1991:15] - node _T_634 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2000:62] - node _T_635 = eq(_T_634, UInt<12>("h0bc9")) @[dec_tlu_ctl.scala 2000:69] - node wr_meipt_r = and(io.dec_csr_wen_r_mod, _T_635) @[dec_tlu_ctl.scala 2000:40] - node _T_636 = bits(wr_meipt_r, 0, 0) @[dec_tlu_ctl.scala 2001:32] - node _T_637 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2001:59] - node meipt_ns = mux(_T_636, _T_637, meipt) @[dec_tlu_ctl.scala 2001:20] - reg _T_638 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2003:43] - _T_638 <= meipt_ns @[dec_tlu_ctl.scala 2003:43] - meipt <= _T_638 @[dec_tlu_ctl.scala 2003:8] + node _T_612 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1979:66] + node _T_613 = eq(_T_612, UInt<12>("h0bcb")) @[dec_tlu_ctl.scala 1979:73] + node _T_614 = and(io.dec_csr_wen_r_mod, _T_613) @[dec_tlu_ctl.scala 1979:44] + node wr_meicidpl_r = or(_T_614, io.take_ext_int_start) @[dec_tlu_ctl.scala 1979:88] + node _T_615 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1981:37] + node _T_616 = bits(wr_meicidpl_r, 0, 0) @[dec_tlu_ctl.scala 1982:38] + node _T_617 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1982:65] + node _T_618 = mux(_T_616, _T_617, meicidpl) @[dec_tlu_ctl.scala 1982:23] + node meicidpl_ns = mux(_T_615, io.pic_pl, _T_618) @[dec_tlu_ctl.scala 1981:23] + reg _T_619 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1984:44] + _T_619 <= meicidpl_ns @[dec_tlu_ctl.scala 1984:44] + meicidpl <= _T_619 @[dec_tlu_ctl.scala 1984:11] + node _T_620 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1991:62] + node _T_621 = eq(_T_620, UInt<12>("h0bca")) @[dec_tlu_ctl.scala 1991:69] + node _T_622 = and(io.dec_csr_wen_r_mod, _T_621) @[dec_tlu_ctl.scala 1991:40] + node _T_623 = or(_T_622, io.take_ext_int_start) @[dec_tlu_ctl.scala 1991:83] + wr_meicpct_r <= _T_623 @[dec_tlu_ctl.scala 1991:15] + node _T_624 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2000:62] + node _T_625 = eq(_T_624, UInt<12>("h0bc9")) @[dec_tlu_ctl.scala 2000:69] + node wr_meipt_r = and(io.dec_csr_wen_r_mod, _T_625) @[dec_tlu_ctl.scala 2000:40] + node _T_626 = bits(wr_meipt_r, 0, 0) @[dec_tlu_ctl.scala 2001:32] + node _T_627 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2001:59] + node meipt_ns = mux(_T_626, _T_627, meipt) @[dec_tlu_ctl.scala 2001:20] + reg _T_628 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2003:43] + _T_628 <= meipt_ns @[dec_tlu_ctl.scala 2003:43] + meipt <= _T_628 @[dec_tlu_ctl.scala 2003:8] io.dec_tlu_meipt <= meipt @[dec_tlu_ctl.scala 2005:19] - node _T_639 = and(io.trigger_hit_r_d1, io.dcsr_single_step_done_f) @[dec_tlu_ctl.scala 2031:89] - node trigger_hit_for_dscr_cause_r_d1 = or(io.trigger_hit_dmode_r_d1, _T_639) @[dec_tlu_ctl.scala 2031:66] - node _T_640 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2034:31] - node _T_641 = and(io.dcsr_single_step_done_f, _T_640) @[dec_tlu_ctl.scala 2034:29] - node _T_642 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2034:63] - node _T_643 = and(_T_641, _T_642) @[dec_tlu_ctl.scala 2034:61] - node _T_644 = not(io.debug_halt_req) @[dec_tlu_ctl.scala 2034:98] - node _T_645 = and(_T_643, _T_644) @[dec_tlu_ctl.scala 2034:96] - node _T_646 = bits(_T_645, 0, 0) @[dec_tlu_ctl.scala 2034:118] - node _T_647 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2035:48] - node _T_648 = and(io.debug_halt_req, _T_647) @[dec_tlu_ctl.scala 2035:46] - node _T_649 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2035:80] - node _T_650 = and(_T_648, _T_649) @[dec_tlu_ctl.scala 2035:78] - node _T_651 = bits(_T_650, 0, 0) @[dec_tlu_ctl.scala 2035:114] - node _T_652 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2036:77] - node _T_653 = and(io.ebreak_to_debug_mode_r_d1, _T_652) @[dec_tlu_ctl.scala 2036:75] - node _T_654 = bits(_T_653, 0, 0) @[dec_tlu_ctl.scala 2036:111] - node _T_655 = bits(trigger_hit_for_dscr_cause_r_d1, 0, 0) @[dec_tlu_ctl.scala 2037:108] - node _T_656 = mux(_T_646, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_657 = mux(_T_651, UInt<3>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_658 = mux(_T_654, UInt<3>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_659 = mux(_T_655, UInt<3>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_660 = or(_T_656, _T_657) @[Mux.scala 27:72] - node _T_661 = or(_T_660, _T_658) @[Mux.scala 27:72] - node _T_662 = or(_T_661, _T_659) @[Mux.scala 27:72] + node _T_629 = and(io.trigger_hit_r_d1, io.dcsr_single_step_done_f) @[dec_tlu_ctl.scala 2031:89] + node trigger_hit_for_dscr_cause_r_d1 = or(io.trigger_hit_dmode_r_d1, _T_629) @[dec_tlu_ctl.scala 2031:66] + node _T_630 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2034:31] + node _T_631 = and(io.dcsr_single_step_done_f, _T_630) @[dec_tlu_ctl.scala 2034:29] + node _T_632 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2034:63] + node _T_633 = and(_T_631, _T_632) @[dec_tlu_ctl.scala 2034:61] + node _T_634 = not(io.debug_halt_req) @[dec_tlu_ctl.scala 2034:98] + node _T_635 = and(_T_633, _T_634) @[dec_tlu_ctl.scala 2034:96] + node _T_636 = bits(_T_635, 0, 0) @[dec_tlu_ctl.scala 2034:118] + node _T_637 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2035:48] + node _T_638 = and(io.debug_halt_req, _T_637) @[dec_tlu_ctl.scala 2035:46] + node _T_639 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2035:80] + node _T_640 = and(_T_638, _T_639) @[dec_tlu_ctl.scala 2035:78] + node _T_641 = bits(_T_640, 0, 0) @[dec_tlu_ctl.scala 2035:114] + node _T_642 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2036:77] + node _T_643 = and(io.ebreak_to_debug_mode_r_d1, _T_642) @[dec_tlu_ctl.scala 2036:75] + node _T_644 = bits(_T_643, 0, 0) @[dec_tlu_ctl.scala 2036:111] + node _T_645 = bits(trigger_hit_for_dscr_cause_r_d1, 0, 0) @[dec_tlu_ctl.scala 2037:108] + node _T_646 = mux(_T_636, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_647 = mux(_T_641, UInt<3>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_648 = mux(_T_644, UInt<3>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_649 = mux(_T_645, UInt<3>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_650 = or(_T_646, _T_647) @[Mux.scala 27:72] + node _T_651 = or(_T_650, _T_648) @[Mux.scala 27:72] + node _T_652 = or(_T_651, _T_649) @[Mux.scala 27:72] wire dcsr_cause : UInt<3> @[Mux.scala 27:72] - dcsr_cause <= _T_662 @[Mux.scala 27:72] - node _T_663 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2039:46] - node _T_664 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2039:91] - node _T_665 = eq(_T_664, UInt<12>("h07b0")) @[dec_tlu_ctl.scala 2039:98] - node wr_dcsr_r = and(_T_663, _T_665) @[dec_tlu_ctl.scala 2039:69] - node _T_666 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2045:69] - node _T_667 = eq(_T_666, UInt<3>("h03")) @[dec_tlu_ctl.scala 2045:75] - node dcsr_cause_upgradeable = and(io.internal_dbg_halt_mode_f, _T_667) @[dec_tlu_ctl.scala 2045:59] - node _T_668 = not(io.dbg_tlu_halted) @[dec_tlu_ctl.scala 2046:59] - node _T_669 = or(_T_668, dcsr_cause_upgradeable) @[dec_tlu_ctl.scala 2046:78] - node enter_debug_halt_req_le = and(io.enter_debug_halt_req, _T_669) @[dec_tlu_ctl.scala 2046:56] + dcsr_cause <= _T_652 @[Mux.scala 27:72] + node _T_653 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2039:46] + node _T_654 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2039:91] + node _T_655 = eq(_T_654, UInt<12>("h07b0")) @[dec_tlu_ctl.scala 2039:98] + node wr_dcsr_r = and(_T_653, _T_655) @[dec_tlu_ctl.scala 2039:69] + node _T_656 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2045:69] + node _T_657 = eq(_T_656, UInt<3>("h03")) @[dec_tlu_ctl.scala 2045:75] + node dcsr_cause_upgradeable = and(io.internal_dbg_halt_mode_f, _T_657) @[dec_tlu_ctl.scala 2045:59] + node _T_658 = not(io.dbg_tlu_halted) @[dec_tlu_ctl.scala 2046:59] + node _T_659 = or(_T_658, dcsr_cause_upgradeable) @[dec_tlu_ctl.scala 2046:78] + node enter_debug_halt_req_le = and(io.enter_debug_halt_req, _T_659) @[dec_tlu_ctl.scala 2046:56] node nmi_in_debug_mode = and(io.nmi_int_detected_f, io.internal_dbg_halt_mode_f) @[dec_tlu_ctl.scala 2048:48] - node _T_670 = bits(enter_debug_halt_req_le, 0, 0) @[dec_tlu_ctl.scala 2049:44] - node _T_671 = bits(io.dcsr, 15, 9) @[dec_tlu_ctl.scala 2049:64] - node _T_672 = bits(io.dcsr, 5, 2) @[dec_tlu_ctl.scala 2049:91] + node _T_660 = bits(enter_debug_halt_req_le, 0, 0) @[dec_tlu_ctl.scala 2049:44] + node _T_661 = bits(io.dcsr, 15, 9) @[dec_tlu_ctl.scala 2049:64] + node _T_662 = bits(io.dcsr, 5, 2) @[dec_tlu_ctl.scala 2049:91] + node _T_663 = cat(_T_662, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_664 = cat(_T_661, dcsr_cause) @[Cat.scala 29:58] + node _T_665 = cat(_T_664, _T_663) @[Cat.scala 29:58] + node _T_666 = bits(wr_dcsr_r, 0, 0) @[dec_tlu_ctl.scala 2050:18] + node _T_667 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 2050:49] + node _T_668 = bits(io.dec_csr_wrdata_r, 11, 10) @[dec_tlu_ctl.scala 2050:84] + node _T_669 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2050:110] + node _T_670 = bits(io.dcsr, 3, 3) @[dec_tlu_ctl.scala 2050:154] + node _T_671 = or(nmi_in_debug_mode, _T_670) @[dec_tlu_ctl.scala 2050:145] + node _T_672 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2050:178] node _T_673 = cat(_T_672, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_674 = cat(_T_671, dcsr_cause) @[Cat.scala 29:58] + node _T_674 = cat(UInt<2>("h00"), _T_671) @[Cat.scala 29:58] node _T_675 = cat(_T_674, _T_673) @[Cat.scala 29:58] - node _T_676 = bits(wr_dcsr_r, 0, 0) @[dec_tlu_ctl.scala 2050:18] - node _T_677 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 2050:49] - node _T_678 = bits(io.dec_csr_wrdata_r, 11, 10) @[dec_tlu_ctl.scala 2050:84] - node _T_679 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2050:110] - node _T_680 = bits(io.dcsr, 3, 3) @[dec_tlu_ctl.scala 2050:154] - node _T_681 = or(nmi_in_debug_mode, _T_680) @[dec_tlu_ctl.scala 2050:145] - node _T_682 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2050:178] + node _T_676 = cat(UInt<1>("h00"), _T_669) @[Cat.scala 29:58] + node _T_677 = cat(_T_667, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_678 = cat(_T_677, _T_668) @[Cat.scala 29:58] + node _T_679 = cat(_T_678, _T_676) @[Cat.scala 29:58] + node _T_680 = cat(_T_679, _T_675) @[Cat.scala 29:58] + node _T_681 = bits(io.dcsr, 15, 4) @[dec_tlu_ctl.scala 2050:211] + node _T_682 = bits(io.dcsr, 2, 2) @[dec_tlu_ctl.scala 2050:245] node _T_683 = cat(_T_682, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_684 = cat(UInt<2>("h00"), _T_681) @[Cat.scala 29:58] + node _T_684 = cat(_T_681, nmi_in_debug_mode) @[Cat.scala 29:58] node _T_685 = cat(_T_684, _T_683) @[Cat.scala 29:58] - node _T_686 = cat(UInt<1>("h00"), _T_679) @[Cat.scala 29:58] - node _T_687 = cat(_T_677, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_688 = cat(_T_687, _T_678) @[Cat.scala 29:58] - node _T_689 = cat(_T_688, _T_686) @[Cat.scala 29:58] - node _T_690 = cat(_T_689, _T_685) @[Cat.scala 29:58] - node _T_691 = bits(io.dcsr, 15, 4) @[dec_tlu_ctl.scala 2050:211] - node _T_692 = bits(io.dcsr, 2, 2) @[dec_tlu_ctl.scala 2050:245] - node _T_693 = cat(_T_692, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_694 = cat(_T_691, nmi_in_debug_mode) @[Cat.scala 29:58] - node _T_695 = cat(_T_694, _T_693) @[Cat.scala 29:58] - node _T_696 = mux(_T_676, _T_690, _T_695) @[dec_tlu_ctl.scala 2050:7] - node dcsr_ns = mux(_T_670, _T_675, _T_696) @[dec_tlu_ctl.scala 2049:19] - node _T_697 = or(enter_debug_halt_req_le, wr_dcsr_r) @[dec_tlu_ctl.scala 2052:54] - node _T_698 = or(_T_697, io.internal_dbg_halt_mode) @[dec_tlu_ctl.scala 2052:66] - node _T_699 = or(_T_698, io.take_nmi) @[dec_tlu_ctl.scala 2052:94] - node _T_700 = bits(_T_699, 0, 0) @[dec_tlu_ctl.scala 2052:109] - inst rvclkhdr_17 of rvclkhdr_737 @[el2_lib.scala 508:23] + node _T_686 = mux(_T_666, _T_680, _T_685) @[dec_tlu_ctl.scala 2050:7] + node dcsr_ns = mux(_T_660, _T_665, _T_686) @[dec_tlu_ctl.scala 2049:19] + node _T_687 = or(enter_debug_halt_req_le, wr_dcsr_r) @[dec_tlu_ctl.scala 2052:54] + node _T_688 = or(_T_687, io.internal_dbg_halt_mode) @[dec_tlu_ctl.scala 2052:66] + node _T_689 = or(_T_688, io.take_nmi) @[dec_tlu_ctl.scala 2052:94] + node _T_690 = bits(_T_689, 0, 0) @[dec_tlu_ctl.scala 2052:109] + inst rvclkhdr_17 of rvclkhdr_737 @[lib.scala 368:23] rvclkhdr_17.clock <= clock rvclkhdr_17.reset <= reset - rvclkhdr_17.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_17.io.en <= _T_700 @[el2_lib.scala 511:17] - rvclkhdr_17.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_701 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_701 <= dcsr_ns @[el2_lib.scala 514:16] - io.dcsr <= _T_701 @[dec_tlu_ctl.scala 2052:10] - node _T_702 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2060:45] - node _T_703 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2060:90] - node _T_704 = eq(_T_703, UInt<12>("h07b1")) @[dec_tlu_ctl.scala 2060:97] - node wr_dpc_r = and(_T_702, _T_704) @[dec_tlu_ctl.scala 2060:68] - node _T_705 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2061:44] - node _T_706 = and(io.dbg_tlu_halted, _T_705) @[dec_tlu_ctl.scala 2061:42] - node _T_707 = not(io.request_debug_mode_done) @[dec_tlu_ctl.scala 2061:67] - node dpc_capture_npc = and(_T_706, _T_707) @[dec_tlu_ctl.scala 2061:65] - node _T_708 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2065:21] - node _T_709 = not(dpc_capture_npc) @[dec_tlu_ctl.scala 2065:39] - node _T_710 = and(_T_708, _T_709) @[dec_tlu_ctl.scala 2065:37] - node _T_711 = and(_T_710, wr_dpc_r) @[dec_tlu_ctl.scala 2065:56] - node _T_712 = bits(_T_711, 0, 0) @[dec_tlu_ctl.scala 2065:68] - node _T_713 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 2065:97] - node _T_714 = bits(io.request_debug_mode_r, 0, 0) @[dec_tlu_ctl.scala 2066:68] - node _T_715 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2067:33] - node _T_716 = and(_T_715, dpc_capture_npc) @[dec_tlu_ctl.scala 2067:49] - node _T_717 = bits(_T_716, 0, 0) @[dec_tlu_ctl.scala 2067:68] - node _T_718 = mux(_T_712, _T_713, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_719 = mux(_T_714, pc_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_720 = mux(_T_717, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_721 = or(_T_718, _T_719) @[Mux.scala 27:72] - node _T_722 = or(_T_721, _T_720) @[Mux.scala 27:72] + rvclkhdr_17.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_17.io.en <= _T_690 @[lib.scala 371:17] + rvclkhdr_17.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_691 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_691 <= dcsr_ns @[lib.scala 374:16] + io.dcsr <= _T_691 @[dec_tlu_ctl.scala 2052:10] + node _T_692 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2060:45] + node _T_693 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2060:90] + node _T_694 = eq(_T_693, UInt<12>("h07b1")) @[dec_tlu_ctl.scala 2060:97] + node wr_dpc_r = and(_T_692, _T_694) @[dec_tlu_ctl.scala 2060:68] + node _T_695 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2061:44] + node _T_696 = and(io.dbg_tlu_halted, _T_695) @[dec_tlu_ctl.scala 2061:42] + node _T_697 = not(io.request_debug_mode_done) @[dec_tlu_ctl.scala 2061:67] + node dpc_capture_npc = and(_T_696, _T_697) @[dec_tlu_ctl.scala 2061:65] + node _T_698 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2065:21] + node _T_699 = not(dpc_capture_npc) @[dec_tlu_ctl.scala 2065:39] + node _T_700 = and(_T_698, _T_699) @[dec_tlu_ctl.scala 2065:37] + node _T_701 = and(_T_700, wr_dpc_r) @[dec_tlu_ctl.scala 2065:56] + node _T_702 = bits(_T_701, 0, 0) @[dec_tlu_ctl.scala 2065:68] + node _T_703 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 2065:97] + node _T_704 = bits(io.request_debug_mode_r, 0, 0) @[dec_tlu_ctl.scala 2066:68] + node _T_705 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2067:33] + node _T_706 = and(_T_705, dpc_capture_npc) @[dec_tlu_ctl.scala 2067:49] + node _T_707 = bits(_T_706, 0, 0) @[dec_tlu_ctl.scala 2067:68] + node _T_708 = mux(_T_702, _T_703, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_709 = mux(_T_704, pc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_710 = mux(_T_707, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_711 = or(_T_708, _T_709) @[Mux.scala 27:72] + node _T_712 = or(_T_711, _T_710) @[Mux.scala 27:72] wire dpc_ns : UInt<31> @[Mux.scala 27:72] - dpc_ns <= _T_722 @[Mux.scala 27:72] - node _T_723 = or(wr_dpc_r, io.request_debug_mode_r) @[dec_tlu_ctl.scala 2069:36] - node _T_724 = or(_T_723, dpc_capture_npc) @[dec_tlu_ctl.scala 2069:53] - node _T_725 = bits(_T_724, 0, 0) @[dec_tlu_ctl.scala 2069:72] - inst rvclkhdr_18 of rvclkhdr_738 @[el2_lib.scala 508:23] + dpc_ns <= _T_712 @[Mux.scala 27:72] + node _T_713 = or(wr_dpc_r, io.request_debug_mode_r) @[dec_tlu_ctl.scala 2069:36] + node _T_714 = or(_T_713, dpc_capture_npc) @[dec_tlu_ctl.scala 2069:53] + node _T_715 = bits(_T_714, 0, 0) @[dec_tlu_ctl.scala 2069:72] + inst rvclkhdr_18 of rvclkhdr_738 @[lib.scala 368:23] rvclkhdr_18.clock <= clock rvclkhdr_18.reset <= reset - rvclkhdr_18.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_18.io.en <= _T_725 @[el2_lib.scala 511:17] - rvclkhdr_18.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_726 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_726 <= dpc_ns @[el2_lib.scala 514:16] - io.dpc <= _T_726 @[dec_tlu_ctl.scala 2069:9] - node _T_727 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 2083:43] - node _T_728 = bits(io.dec_csr_wrdata_r, 21, 20) @[dec_tlu_ctl.scala 2083:68] - node _T_729 = bits(io.dec_csr_wrdata_r, 16, 3) @[dec_tlu_ctl.scala 2083:96] - node _T_730 = cat(_T_727, _T_728) @[Cat.scala 29:58] - node dicawics_ns = cat(_T_730, _T_729) @[Cat.scala 29:58] - node _T_731 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2084:50] - node _T_732 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2084:95] - node _T_733 = eq(_T_732, UInt<12>("h07c8")) @[dec_tlu_ctl.scala 2084:102] - node wr_dicawics_r = and(_T_731, _T_733) @[dec_tlu_ctl.scala 2084:73] - node _T_734 = bits(wr_dicawics_r, 0, 0) @[dec_tlu_ctl.scala 2086:50] - inst rvclkhdr_19 of rvclkhdr_739 @[el2_lib.scala 508:23] + rvclkhdr_18.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_18.io.en <= _T_715 @[lib.scala 371:17] + rvclkhdr_18.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_716 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_716 <= dpc_ns @[lib.scala 374:16] + io.dpc <= _T_716 @[dec_tlu_ctl.scala 2069:9] + node _T_717 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 2083:43] + node _T_718 = bits(io.dec_csr_wrdata_r, 21, 20) @[dec_tlu_ctl.scala 2083:68] + node _T_719 = bits(io.dec_csr_wrdata_r, 16, 3) @[dec_tlu_ctl.scala 2083:96] + node _T_720 = cat(_T_717, _T_718) @[Cat.scala 29:58] + node dicawics_ns = cat(_T_720, _T_719) @[Cat.scala 29:58] + node _T_721 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2084:50] + node _T_722 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2084:95] + node _T_723 = eq(_T_722, UInt<12>("h07c8")) @[dec_tlu_ctl.scala 2084:102] + node wr_dicawics_r = and(_T_721, _T_723) @[dec_tlu_ctl.scala 2084:73] + node _T_724 = bits(wr_dicawics_r, 0, 0) @[dec_tlu_ctl.scala 2086:50] + inst rvclkhdr_19 of rvclkhdr_739 @[lib.scala 368:23] rvclkhdr_19.clock <= clock rvclkhdr_19.reset <= reset - rvclkhdr_19.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_19.io.en <= _T_734 @[el2_lib.scala 511:17] - rvclkhdr_19.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg dicawics : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - dicawics <= dicawics_ns @[el2_lib.scala 514:16] - node _T_735 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2102:48] - node _T_736 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2102:93] - node _T_737 = eq(_T_736, UInt<12>("h07c9")) @[dec_tlu_ctl.scala 2102:100] - node wr_dicad0_r = and(_T_735, _T_737) @[dec_tlu_ctl.scala 2102:71] - node _T_738 = bits(wr_dicad0_r, 0, 0) @[dec_tlu_ctl.scala 2103:34] - node dicad0_ns = mux(_T_738, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data) @[dec_tlu_ctl.scala 2103:21] - node _T_739 = or(wr_dicad0_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2105:46] - node _T_740 = bits(_T_739, 0, 0) @[dec_tlu_ctl.scala 2105:79] - inst rvclkhdr_20 of rvclkhdr_740 @[el2_lib.scala 508:23] + rvclkhdr_19.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_19.io.en <= _T_724 @[lib.scala 371:17] + rvclkhdr_19.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg dicawics : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + dicawics <= dicawics_ns @[lib.scala 374:16] + node _T_725 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2102:48] + node _T_726 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2102:93] + node _T_727 = eq(_T_726, UInt<12>("h07c9")) @[dec_tlu_ctl.scala 2102:100] + node wr_dicad0_r = and(_T_725, _T_727) @[dec_tlu_ctl.scala 2102:71] + node _T_728 = bits(wr_dicad0_r, 0, 0) @[dec_tlu_ctl.scala 2103:34] + node dicad0_ns = mux(_T_728, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data) @[dec_tlu_ctl.scala 2103:21] + node _T_729 = or(wr_dicad0_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2105:46] + node _T_730 = bits(_T_729, 0, 0) @[dec_tlu_ctl.scala 2105:79] + inst rvclkhdr_20 of rvclkhdr_740 @[lib.scala 368:23] rvclkhdr_20.clock <= clock rvclkhdr_20.reset <= reset - rvclkhdr_20.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_20.io.en <= _T_740 @[el2_lib.scala 511:17] - rvclkhdr_20.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg dicad0 : UInt, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - dicad0 <= dicad0_ns @[el2_lib.scala 514:16] - node _T_741 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2115:49] - node _T_742 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2115:94] - node _T_743 = eq(_T_742, UInt<12>("h07cc")) @[dec_tlu_ctl.scala 2115:101] - node wr_dicad0h_r = and(_T_741, _T_743) @[dec_tlu_ctl.scala 2115:72] - node _T_744 = bits(wr_dicad0h_r, 0, 0) @[dec_tlu_ctl.scala 2117:36] - node _T_745 = bits(io.ifu_ic_debug_rd_data, 63, 32) @[dec_tlu_ctl.scala 2117:88] - node dicad0h_ns = mux(_T_744, io.dec_csr_wrdata_r, _T_745) @[dec_tlu_ctl.scala 2117:22] - node _T_746 = or(wr_dicad0h_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2119:48] - node _T_747 = bits(_T_746, 0, 0) @[dec_tlu_ctl.scala 2119:81] - inst rvclkhdr_21 of rvclkhdr_741 @[el2_lib.scala 508:23] + rvclkhdr_20.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_20.io.en <= _T_730 @[lib.scala 371:17] + rvclkhdr_20.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg dicad0 : UInt, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + dicad0 <= dicad0_ns @[lib.scala 374:16] + node _T_731 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2115:49] + node _T_732 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2115:94] + node _T_733 = eq(_T_732, UInt<12>("h07cc")) @[dec_tlu_ctl.scala 2115:101] + node wr_dicad0h_r = and(_T_731, _T_733) @[dec_tlu_ctl.scala 2115:72] + node _T_734 = bits(wr_dicad0h_r, 0, 0) @[dec_tlu_ctl.scala 2117:36] + node _T_735 = bits(io.ifu_ic_debug_rd_data, 63, 32) @[dec_tlu_ctl.scala 2117:88] + node dicad0h_ns = mux(_T_734, io.dec_csr_wrdata_r, _T_735) @[dec_tlu_ctl.scala 2117:22] + node _T_736 = or(wr_dicad0h_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2119:48] + node _T_737 = bits(_T_736, 0, 0) @[dec_tlu_ctl.scala 2119:81] + inst rvclkhdr_21 of rvclkhdr_741 @[lib.scala 368:23] rvclkhdr_21.clock <= clock rvclkhdr_21.reset <= reset - rvclkhdr_21.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_21.io.en <= _T_747 @[el2_lib.scala 511:17] - rvclkhdr_21.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg dicad0h : UInt, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - dicad0h <= dicad0h_ns @[el2_lib.scala 514:16] - wire _T_748 : UInt<7> - _T_748 <= UInt<1>("h00") - node _T_749 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2127:48] - node _T_750 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2127:93] - node _T_751 = eq(_T_750, UInt<12>("h07ca")) @[dec_tlu_ctl.scala 2127:100] - node _T_752 = and(_T_749, _T_751) @[dec_tlu_ctl.scala 2127:71] - node _T_753 = bits(_T_752, 0, 0) @[dec_tlu_ctl.scala 2129:34] - node _T_754 = bits(io.ifu_ic_debug_rd_data, 70, 64) @[dec_tlu_ctl.scala 2129:86] - node _T_755 = mux(_T_753, io.dec_csr_wrdata_r, _T_754) @[dec_tlu_ctl.scala 2129:21] - node _T_756 = or(_T_752, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2131:78] - node _T_757 = bits(_T_756, 0, 0) @[dec_tlu_ctl.scala 2131:111] - reg _T_758 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_757 : @[Reg.scala 28:19] - _T_758 <= _T_755 @[Reg.scala 28:23] + rvclkhdr_21.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_21.io.en <= _T_737 @[lib.scala 371:17] + rvclkhdr_21.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg dicad0h : UInt, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + dicad0h <= dicad0h_ns @[lib.scala 374:16] + wire _T_738 : UInt<4> + _T_738 <= UInt<1>("h00") + node _T_739 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2142:48] + node _T_740 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2142:93] + node _T_741 = eq(_T_740, UInt<12>("h07ca")) @[dec_tlu_ctl.scala 2142:100] + node _T_742 = and(_T_739, _T_741) @[dec_tlu_ctl.scala 2142:71] + node _T_743 = bits(_T_742, 0, 0) @[dec_tlu_ctl.scala 2144:34] + node _T_744 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2144:61] + node _T_745 = bits(io.ifu_ic_debug_rd_data, 67, 64) @[dec_tlu_ctl.scala 2144:91] + node _T_746 = mux(_T_743, _T_744, _T_745) @[dec_tlu_ctl.scala 2144:21] + node _T_747 = or(_T_742, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2146:77] + node _T_748 = bits(_T_747, 0, 0) @[dec_tlu_ctl.scala 2146:110] + reg _T_749 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_748 : @[Reg.scala 28:19] + _T_749 <= _T_746 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - _T_748 <= _T_758 @[dec_tlu_ctl.scala 2131:13] - node _T_759 = cat(UInt<25>("h00"), _T_748) @[Cat.scala 29:58] - dicad1 <= _T_759 @[dec_tlu_ctl.scala 2132:9] - node _T_760 = bits(dicad1, 6, 0) @[dec_tlu_ctl.scala 2154:77] - node _T_761 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2154:91] - node _T_762 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2154:105] - node _T_763 = cat(_T_760, _T_761) @[Cat.scala 29:58] - node _T_764 = cat(_T_763, _T_762) @[Cat.scala 29:58] - io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_764 @[dec_tlu_ctl.scala 2154:64] + _T_738 <= _T_749 @[dec_tlu_ctl.scala 2146:13] + node _T_750 = cat(UInt<28>("h00"), _T_738) @[Cat.scala 29:58] + dicad1 <= _T_750 @[dec_tlu_ctl.scala 2147:9] + node _T_751 = bits(dicad1, 3, 0) @[dec_tlu_ctl.scala 2155:69] + node _T_752 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2155:83] + node _T_753 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2155:97] + node _T_754 = cat(_T_752, _T_753) @[Cat.scala 29:58] + node _T_755 = cat(UInt<2>("h00"), _T_751) @[Cat.scala 29:58] + node _T_756 = cat(_T_755, _T_754) @[Cat.scala 29:58] + io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_756 @[dec_tlu_ctl.scala 2155:47] io.dec_tlu_ic_diag_pkt.icache_dicawics <= dicawics @[dec_tlu_ctl.scala 2157:41] - node _T_765 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 2159:52] - node _T_766 = and(_T_765, io.dec_i0_decode_d) @[dec_tlu_ctl.scala 2159:75] - node _T_767 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 2159:98] - node _T_768 = and(_T_766, _T_767) @[dec_tlu_ctl.scala 2159:96] - node _T_769 = bits(io.dec_csr_rdaddr_d, 11, 0) @[dec_tlu_ctl.scala 2159:142] - node _T_770 = eq(_T_769, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2159:149] - node icache_rd_valid = and(_T_768, _T_770) @[dec_tlu_ctl.scala 2159:120] - node _T_771 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2160:52] - node _T_772 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2160:97] - node _T_773 = eq(_T_772, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2160:104] - node icache_wr_valid = and(_T_771, _T_773) @[dec_tlu_ctl.scala 2160:75] + node _T_757 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 2159:52] + node _T_758 = and(_T_757, io.dec_i0_decode_d) @[dec_tlu_ctl.scala 2159:75] + node _T_759 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 2159:98] + node _T_760 = and(_T_758, _T_759) @[dec_tlu_ctl.scala 2159:96] + node _T_761 = bits(io.dec_csr_rdaddr_d, 11, 0) @[dec_tlu_ctl.scala 2159:142] + node _T_762 = eq(_T_761, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2159:149] + node icache_rd_valid = and(_T_760, _T_762) @[dec_tlu_ctl.scala 2159:120] + node _T_763 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2160:52] + node _T_764 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2160:97] + node _T_765 = eq(_T_764, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2160:104] + node icache_wr_valid = and(_T_763, _T_765) @[dec_tlu_ctl.scala 2160:75] reg icache_rd_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2162:58] icache_rd_valid_f <= icache_rd_valid @[dec_tlu_ctl.scala 2162:58] reg icache_wr_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2163:58] icache_wr_valid_f <= icache_wr_valid @[dec_tlu_ctl.scala 2163:58] io.dec_tlu_ic_diag_pkt.icache_rd_valid <= icache_rd_valid_f @[dec_tlu_ctl.scala 2165:41] io.dec_tlu_ic_diag_pkt.icache_wr_valid <= icache_wr_valid_f @[dec_tlu_ctl.scala 2166:41] - node _T_774 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2174:62] - node _T_775 = eq(_T_774, UInt<12>("h07a0")) @[dec_tlu_ctl.scala 2174:69] - node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_775) @[dec_tlu_ctl.scala 2174:40] - node _T_776 = bits(wr_mtsel_r, 0, 0) @[dec_tlu_ctl.scala 2175:32] - node _T_777 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 2175:59] - node mtsel_ns = mux(_T_776, _T_777, mtsel) @[dec_tlu_ctl.scala 2175:20] - reg _T_778 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2177:43] - _T_778 <= mtsel_ns @[dec_tlu_ctl.scala 2177:43] - mtsel <= _T_778 @[dec_tlu_ctl.scala 2177:8] - node _T_779 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2212:38] - node _T_780 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2212:64] - node _T_781 = not(_T_780) @[dec_tlu_ctl.scala 2212:44] - node tdata_load = and(_T_779, _T_781) @[dec_tlu_ctl.scala 2212:42] - node _T_782 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2214:40] - node _T_783 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2214:66] - node _T_784 = not(_T_783) @[dec_tlu_ctl.scala 2214:46] - node tdata_opcode = and(_T_782, _T_784) @[dec_tlu_ctl.scala 2214:44] - node _T_785 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2216:41] - node _T_786 = and(_T_785, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2216:46] - node _T_787 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 2216:90] - node tdata_action = and(_T_786, _T_787) @[dec_tlu_ctl.scala 2216:69] - node _T_788 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2218:47] - node _T_789 = and(_T_788, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2218:52] - node _T_790 = bits(io.dec_csr_wrdata_r, 20, 19) @[dec_tlu_ctl.scala 2218:94] - node _T_791 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2218:136] - node _T_792 = bits(io.dec_csr_wrdata_r, 7, 6) @[dec_tlu_ctl.scala 2219:43] - node _T_793 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 2219:83] - node _T_794 = cat(_T_793, tdata_load) @[Cat.scala 29:58] - node _T_795 = cat(_T_792, tdata_opcode) @[Cat.scala 29:58] - node _T_796 = cat(_T_795, _T_794) @[Cat.scala 29:58] - node _T_797 = cat(tdata_action, _T_791) @[Cat.scala 29:58] - node _T_798 = cat(_T_789, _T_790) @[Cat.scala 29:58] - node _T_799 = cat(_T_798, _T_797) @[Cat.scala 29:58] - node tdata_wrdata_r = cat(_T_799, _T_796) @[Cat.scala 29:58] - node _T_800 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] - node _T_801 = eq(_T_800, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] - node _T_802 = and(io.dec_csr_wen_r_mod, _T_801) @[dec_tlu_ctl.scala 2222:70] - node _T_803 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2222:121] - node _T_804 = and(_T_802, _T_803) @[dec_tlu_ctl.scala 2222:112] - node _T_805 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2222:154] - node _T_806 = not(_T_805) @[dec_tlu_ctl.scala 2222:138] - node _T_807 = or(_T_806, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] - node _T_808 = and(_T_804, _T_807) @[dec_tlu_ctl.scala 2222:135] - node _T_809 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] - node _T_810 = eq(_T_809, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] - node _T_811 = and(io.dec_csr_wen_r_mod, _T_810) @[dec_tlu_ctl.scala 2222:70] - node _T_812 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2222:121] - node _T_813 = and(_T_811, _T_812) @[dec_tlu_ctl.scala 2222:112] - node _T_814 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2222:154] - node _T_815 = not(_T_814) @[dec_tlu_ctl.scala 2222:138] - node _T_816 = or(_T_815, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] - node _T_817 = and(_T_813, _T_816) @[dec_tlu_ctl.scala 2222:135] - node _T_818 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] - node _T_819 = eq(_T_818, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] - node _T_820 = and(io.dec_csr_wen_r_mod, _T_819) @[dec_tlu_ctl.scala 2222:70] - node _T_821 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2222:121] - node _T_822 = and(_T_820, _T_821) @[dec_tlu_ctl.scala 2222:112] - node _T_823 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2222:154] - node _T_824 = not(_T_823) @[dec_tlu_ctl.scala 2222:138] - node _T_825 = or(_T_824, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] - node _T_826 = and(_T_822, _T_825) @[dec_tlu_ctl.scala 2222:135] - node _T_827 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] - node _T_828 = eq(_T_827, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] - node _T_829 = and(io.dec_csr_wen_r_mod, _T_828) @[dec_tlu_ctl.scala 2222:70] - node _T_830 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2222:121] - node _T_831 = and(_T_829, _T_830) @[dec_tlu_ctl.scala 2222:112] - node _T_832 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2222:154] - node _T_833 = not(_T_832) @[dec_tlu_ctl.scala 2222:138] - node _T_834 = or(_T_833, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] - node _T_835 = and(_T_831, _T_834) @[dec_tlu_ctl.scala 2222:135] + node _T_766 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2174:62] + node _T_767 = eq(_T_766, UInt<12>("h07a0")) @[dec_tlu_ctl.scala 2174:69] + node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_767) @[dec_tlu_ctl.scala 2174:40] + node _T_768 = bits(wr_mtsel_r, 0, 0) @[dec_tlu_ctl.scala 2175:32] + node _T_769 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 2175:59] + node mtsel_ns = mux(_T_768, _T_769, mtsel) @[dec_tlu_ctl.scala 2175:20] + reg _T_770 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2177:43] + _T_770 <= mtsel_ns @[dec_tlu_ctl.scala 2177:43] + mtsel <= _T_770 @[dec_tlu_ctl.scala 2177:8] + node _T_771 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2212:38] + node _T_772 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2212:64] + node _T_773 = not(_T_772) @[dec_tlu_ctl.scala 2212:44] + node tdata_load = and(_T_771, _T_773) @[dec_tlu_ctl.scala 2212:42] + node _T_774 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2214:40] + node _T_775 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2214:66] + node _T_776 = not(_T_775) @[dec_tlu_ctl.scala 2214:46] + node tdata_opcode = and(_T_774, _T_776) @[dec_tlu_ctl.scala 2214:44] + node _T_777 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2216:41] + node _T_778 = and(_T_777, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2216:46] + node _T_779 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 2216:90] + node tdata_action = and(_T_778, _T_779) @[dec_tlu_ctl.scala 2216:69] + node _T_780 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2218:47] + node _T_781 = and(_T_780, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2218:52] + node _T_782 = bits(io.dec_csr_wrdata_r, 20, 19) @[dec_tlu_ctl.scala 2218:94] + node _T_783 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2218:136] + node _T_784 = bits(io.dec_csr_wrdata_r, 7, 6) @[dec_tlu_ctl.scala 2219:43] + node _T_785 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 2219:83] + node _T_786 = cat(_T_785, tdata_load) @[Cat.scala 29:58] + node _T_787 = cat(_T_784, tdata_opcode) @[Cat.scala 29:58] + node _T_788 = cat(_T_787, _T_786) @[Cat.scala 29:58] + node _T_789 = cat(tdata_action, _T_783) @[Cat.scala 29:58] + node _T_790 = cat(_T_781, _T_782) @[Cat.scala 29:58] + node _T_791 = cat(_T_790, _T_789) @[Cat.scala 29:58] + node tdata_wrdata_r = cat(_T_791, _T_788) @[Cat.scala 29:58] + node _T_792 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] + node _T_793 = eq(_T_792, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] + node _T_794 = and(io.dec_csr_wen_r_mod, _T_793) @[dec_tlu_ctl.scala 2222:70] + node _T_795 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2222:121] + node _T_796 = and(_T_794, _T_795) @[dec_tlu_ctl.scala 2222:112] + node _T_797 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2222:154] + node _T_798 = not(_T_797) @[dec_tlu_ctl.scala 2222:138] + node _T_799 = or(_T_798, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] + node _T_800 = and(_T_796, _T_799) @[dec_tlu_ctl.scala 2222:135] + node _T_801 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] + node _T_802 = eq(_T_801, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] + node _T_803 = and(io.dec_csr_wen_r_mod, _T_802) @[dec_tlu_ctl.scala 2222:70] + node _T_804 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2222:121] + node _T_805 = and(_T_803, _T_804) @[dec_tlu_ctl.scala 2222:112] + node _T_806 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2222:154] + node _T_807 = not(_T_806) @[dec_tlu_ctl.scala 2222:138] + node _T_808 = or(_T_807, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] + node _T_809 = and(_T_805, _T_808) @[dec_tlu_ctl.scala 2222:135] + node _T_810 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] + node _T_811 = eq(_T_810, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] + node _T_812 = and(io.dec_csr_wen_r_mod, _T_811) @[dec_tlu_ctl.scala 2222:70] + node _T_813 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2222:121] + node _T_814 = and(_T_812, _T_813) @[dec_tlu_ctl.scala 2222:112] + node _T_815 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2222:154] + node _T_816 = not(_T_815) @[dec_tlu_ctl.scala 2222:138] + node _T_817 = or(_T_816, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] + node _T_818 = and(_T_814, _T_817) @[dec_tlu_ctl.scala 2222:135] + node _T_819 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] + node _T_820 = eq(_T_819, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] + node _T_821 = and(io.dec_csr_wen_r_mod, _T_820) @[dec_tlu_ctl.scala 2222:70] + node _T_822 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2222:121] + node _T_823 = and(_T_821, _T_822) @[dec_tlu_ctl.scala 2222:112] + node _T_824 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2222:154] + node _T_825 = not(_T_824) @[dec_tlu_ctl.scala 2222:138] + node _T_826 = or(_T_825, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] + node _T_827 = and(_T_823, _T_826) @[dec_tlu_ctl.scala 2222:135] wire wr_mtdata1_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2222:42] - wr_mtdata1_t_r[0] <= _T_808 @[dec_tlu_ctl.scala 2222:42] - wr_mtdata1_t_r[1] <= _T_817 @[dec_tlu_ctl.scala 2222:42] - wr_mtdata1_t_r[2] <= _T_826 @[dec_tlu_ctl.scala 2222:42] - wr_mtdata1_t_r[3] <= _T_835 @[dec_tlu_ctl.scala 2222:42] - node _T_836 = bits(wr_mtdata1_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2223:68] - node _T_837 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2223:111] - node _T_838 = bits(io.update_hit_bit_r, 0, 0) @[dec_tlu_ctl.scala 2223:135] - node _T_839 = bits(io.mtdata1_t[0], 8, 8) @[dec_tlu_ctl.scala 2223:156] - node _T_840 = or(_T_838, _T_839) @[dec_tlu_ctl.scala 2223:139] - node _T_841 = bits(io.mtdata1_t[0], 7, 0) @[dec_tlu_ctl.scala 2223:176] - node _T_842 = cat(_T_837, _T_840) @[Cat.scala 29:58] - node _T_843 = cat(_T_842, _T_841) @[Cat.scala 29:58] - node _T_844 = mux(_T_836, tdata_wrdata_r, _T_843) @[dec_tlu_ctl.scala 2223:49] - node _T_845 = bits(wr_mtdata1_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2223:68] - node _T_846 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2223:111] - node _T_847 = bits(io.update_hit_bit_r, 1, 1) @[dec_tlu_ctl.scala 2223:135] - node _T_848 = bits(io.mtdata1_t[1], 8, 8) @[dec_tlu_ctl.scala 2223:156] - node _T_849 = or(_T_847, _T_848) @[dec_tlu_ctl.scala 2223:139] - node _T_850 = bits(io.mtdata1_t[1], 7, 0) @[dec_tlu_ctl.scala 2223:176] - node _T_851 = cat(_T_846, _T_849) @[Cat.scala 29:58] - node _T_852 = cat(_T_851, _T_850) @[Cat.scala 29:58] - node _T_853 = mux(_T_845, tdata_wrdata_r, _T_852) @[dec_tlu_ctl.scala 2223:49] - node _T_854 = bits(wr_mtdata1_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2223:68] - node _T_855 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2223:111] - node _T_856 = bits(io.update_hit_bit_r, 2, 2) @[dec_tlu_ctl.scala 2223:135] - node _T_857 = bits(io.mtdata1_t[2], 8, 8) @[dec_tlu_ctl.scala 2223:156] - node _T_858 = or(_T_856, _T_857) @[dec_tlu_ctl.scala 2223:139] - node _T_859 = bits(io.mtdata1_t[2], 7, 0) @[dec_tlu_ctl.scala 2223:176] - node _T_860 = cat(_T_855, _T_858) @[Cat.scala 29:58] - node _T_861 = cat(_T_860, _T_859) @[Cat.scala 29:58] - node _T_862 = mux(_T_854, tdata_wrdata_r, _T_861) @[dec_tlu_ctl.scala 2223:49] - node _T_863 = bits(wr_mtdata1_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2223:68] - node _T_864 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2223:111] - node _T_865 = bits(io.update_hit_bit_r, 3, 3) @[dec_tlu_ctl.scala 2223:135] - node _T_866 = bits(io.mtdata1_t[3], 8, 8) @[dec_tlu_ctl.scala 2223:156] - node _T_867 = or(_T_865, _T_866) @[dec_tlu_ctl.scala 2223:139] - node _T_868 = bits(io.mtdata1_t[3], 7, 0) @[dec_tlu_ctl.scala 2223:176] - node _T_869 = cat(_T_864, _T_867) @[Cat.scala 29:58] - node _T_870 = cat(_T_869, _T_868) @[Cat.scala 29:58] - node _T_871 = mux(_T_863, tdata_wrdata_r, _T_870) @[dec_tlu_ctl.scala 2223:49] + wr_mtdata1_t_r[0] <= _T_800 @[dec_tlu_ctl.scala 2222:42] + wr_mtdata1_t_r[1] <= _T_809 @[dec_tlu_ctl.scala 2222:42] + wr_mtdata1_t_r[2] <= _T_818 @[dec_tlu_ctl.scala 2222:42] + wr_mtdata1_t_r[3] <= _T_827 @[dec_tlu_ctl.scala 2222:42] + node _T_828 = bits(wr_mtdata1_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2223:68] + node _T_829 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2223:111] + node _T_830 = bits(io.update_hit_bit_r, 0, 0) @[dec_tlu_ctl.scala 2223:135] + node _T_831 = bits(io.mtdata1_t[0], 8, 8) @[dec_tlu_ctl.scala 2223:156] + node _T_832 = or(_T_830, _T_831) @[dec_tlu_ctl.scala 2223:139] + node _T_833 = bits(io.mtdata1_t[0], 7, 0) @[dec_tlu_ctl.scala 2223:176] + node _T_834 = cat(_T_829, _T_832) @[Cat.scala 29:58] + node _T_835 = cat(_T_834, _T_833) @[Cat.scala 29:58] + node _T_836 = mux(_T_828, tdata_wrdata_r, _T_835) @[dec_tlu_ctl.scala 2223:49] + node _T_837 = bits(wr_mtdata1_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2223:68] + node _T_838 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2223:111] + node _T_839 = bits(io.update_hit_bit_r, 1, 1) @[dec_tlu_ctl.scala 2223:135] + node _T_840 = bits(io.mtdata1_t[1], 8, 8) @[dec_tlu_ctl.scala 2223:156] + node _T_841 = or(_T_839, _T_840) @[dec_tlu_ctl.scala 2223:139] + node _T_842 = bits(io.mtdata1_t[1], 7, 0) @[dec_tlu_ctl.scala 2223:176] + node _T_843 = cat(_T_838, _T_841) @[Cat.scala 29:58] + node _T_844 = cat(_T_843, _T_842) @[Cat.scala 29:58] + node _T_845 = mux(_T_837, tdata_wrdata_r, _T_844) @[dec_tlu_ctl.scala 2223:49] + node _T_846 = bits(wr_mtdata1_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2223:68] + node _T_847 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2223:111] + node _T_848 = bits(io.update_hit_bit_r, 2, 2) @[dec_tlu_ctl.scala 2223:135] + node _T_849 = bits(io.mtdata1_t[2], 8, 8) @[dec_tlu_ctl.scala 2223:156] + node _T_850 = or(_T_848, _T_849) @[dec_tlu_ctl.scala 2223:139] + node _T_851 = bits(io.mtdata1_t[2], 7, 0) @[dec_tlu_ctl.scala 2223:176] + node _T_852 = cat(_T_847, _T_850) @[Cat.scala 29:58] + node _T_853 = cat(_T_852, _T_851) @[Cat.scala 29:58] + node _T_854 = mux(_T_846, tdata_wrdata_r, _T_853) @[dec_tlu_ctl.scala 2223:49] + node _T_855 = bits(wr_mtdata1_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2223:68] + node _T_856 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2223:111] + node _T_857 = bits(io.update_hit_bit_r, 3, 3) @[dec_tlu_ctl.scala 2223:135] + node _T_858 = bits(io.mtdata1_t[3], 8, 8) @[dec_tlu_ctl.scala 2223:156] + node _T_859 = or(_T_857, _T_858) @[dec_tlu_ctl.scala 2223:139] + node _T_860 = bits(io.mtdata1_t[3], 7, 0) @[dec_tlu_ctl.scala 2223:176] + node _T_861 = cat(_T_856, _T_859) @[Cat.scala 29:58] + node _T_862 = cat(_T_861, _T_860) @[Cat.scala 29:58] + node _T_863 = mux(_T_855, tdata_wrdata_r, _T_862) @[dec_tlu_ctl.scala 2223:49] wire mtdata1_t_ns : UInt<10>[4] @[dec_tlu_ctl.scala 2223:40] - mtdata1_t_ns[0] <= _T_844 @[dec_tlu_ctl.scala 2223:40] - mtdata1_t_ns[1] <= _T_853 @[dec_tlu_ctl.scala 2223:40] - mtdata1_t_ns[2] <= _T_862 @[dec_tlu_ctl.scala 2223:40] - mtdata1_t_ns[3] <= _T_871 @[dec_tlu_ctl.scala 2223:40] - reg _T_872 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2225:74] - _T_872 <= mtdata1_t_ns[0] @[dec_tlu_ctl.scala 2225:74] - io.mtdata1_t[0] <= _T_872 @[dec_tlu_ctl.scala 2225:39] - reg _T_873 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2225:74] - _T_873 <= mtdata1_t_ns[1] @[dec_tlu_ctl.scala 2225:74] - io.mtdata1_t[1] <= _T_873 @[dec_tlu_ctl.scala 2225:39] - reg _T_874 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2225:74] - _T_874 <= mtdata1_t_ns[2] @[dec_tlu_ctl.scala 2225:74] - io.mtdata1_t[2] <= _T_874 @[dec_tlu_ctl.scala 2225:39] - reg _T_875 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2225:74] - _T_875 <= mtdata1_t_ns[3] @[dec_tlu_ctl.scala 2225:74] - io.mtdata1_t[3] <= _T_875 @[dec_tlu_ctl.scala 2225:39] - node _T_876 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2228:58] - node _T_877 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2228:104] - node _T_878 = bits(io.mtdata1_t[0], 8, 7) @[dec_tlu_ctl.scala 2228:142] - node _T_879 = bits(io.mtdata1_t[0], 6, 5) @[dec_tlu_ctl.scala 2228:174] - node _T_880 = bits(io.mtdata1_t[0], 4, 3) @[dec_tlu_ctl.scala 2228:206] - node _T_881 = bits(io.mtdata1_t[0], 2, 0) @[dec_tlu_ctl.scala 2228:238] - node _T_882 = cat(UInt<3>("h00"), _T_881) @[Cat.scala 29:58] - node _T_883 = cat(_T_879, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_884 = cat(_T_883, _T_880) @[Cat.scala 29:58] - node _T_885 = cat(_T_884, _T_882) @[Cat.scala 29:58] - node _T_886 = cat(_T_878, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_887 = cat(UInt<4>("h02"), _T_877) @[Cat.scala 29:58] - node _T_888 = cat(_T_887, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_889 = cat(_T_888, _T_886) @[Cat.scala 29:58] - node _T_890 = cat(_T_889, _T_885) @[Cat.scala 29:58] - node _T_891 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2228:58] - node _T_892 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2228:104] - node _T_893 = bits(io.mtdata1_t[1], 8, 7) @[dec_tlu_ctl.scala 2228:142] - node _T_894 = bits(io.mtdata1_t[1], 6, 5) @[dec_tlu_ctl.scala 2228:174] - node _T_895 = bits(io.mtdata1_t[1], 4, 3) @[dec_tlu_ctl.scala 2228:206] - node _T_896 = bits(io.mtdata1_t[1], 2, 0) @[dec_tlu_ctl.scala 2228:238] - node _T_897 = cat(UInt<3>("h00"), _T_896) @[Cat.scala 29:58] - node _T_898 = cat(_T_894, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_899 = cat(_T_898, _T_895) @[Cat.scala 29:58] - node _T_900 = cat(_T_899, _T_897) @[Cat.scala 29:58] - node _T_901 = cat(_T_893, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_902 = cat(UInt<4>("h02"), _T_892) @[Cat.scala 29:58] - node _T_903 = cat(_T_902, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_904 = cat(_T_903, _T_901) @[Cat.scala 29:58] - node _T_905 = cat(_T_904, _T_900) @[Cat.scala 29:58] - node _T_906 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2228:58] - node _T_907 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2228:104] - node _T_908 = bits(io.mtdata1_t[2], 8, 7) @[dec_tlu_ctl.scala 2228:142] - node _T_909 = bits(io.mtdata1_t[2], 6, 5) @[dec_tlu_ctl.scala 2228:174] - node _T_910 = bits(io.mtdata1_t[2], 4, 3) @[dec_tlu_ctl.scala 2228:206] - node _T_911 = bits(io.mtdata1_t[2], 2, 0) @[dec_tlu_ctl.scala 2228:238] - node _T_912 = cat(UInt<3>("h00"), _T_911) @[Cat.scala 29:58] - node _T_913 = cat(_T_909, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_914 = cat(_T_913, _T_910) @[Cat.scala 29:58] - node _T_915 = cat(_T_914, _T_912) @[Cat.scala 29:58] - node _T_916 = cat(_T_908, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_917 = cat(UInt<4>("h02"), _T_907) @[Cat.scala 29:58] - node _T_918 = cat(_T_917, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_919 = cat(_T_918, _T_916) @[Cat.scala 29:58] - node _T_920 = cat(_T_919, _T_915) @[Cat.scala 29:58] - node _T_921 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2228:58] - node _T_922 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2228:104] - node _T_923 = bits(io.mtdata1_t[3], 8, 7) @[dec_tlu_ctl.scala 2228:142] - node _T_924 = bits(io.mtdata1_t[3], 6, 5) @[dec_tlu_ctl.scala 2228:174] - node _T_925 = bits(io.mtdata1_t[3], 4, 3) @[dec_tlu_ctl.scala 2228:206] - node _T_926 = bits(io.mtdata1_t[3], 2, 0) @[dec_tlu_ctl.scala 2228:238] - node _T_927 = cat(UInt<3>("h00"), _T_926) @[Cat.scala 29:58] - node _T_928 = cat(_T_924, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_929 = cat(_T_928, _T_925) @[Cat.scala 29:58] - node _T_930 = cat(_T_929, _T_927) @[Cat.scala 29:58] - node _T_931 = cat(_T_923, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_932 = cat(UInt<4>("h02"), _T_922) @[Cat.scala 29:58] - node _T_933 = cat(_T_932, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_934 = cat(_T_933, _T_931) @[Cat.scala 29:58] - node _T_935 = cat(_T_934, _T_930) @[Cat.scala 29:58] - node _T_936 = mux(_T_876, _T_890, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_937 = mux(_T_891, _T_905, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_938 = mux(_T_906, _T_920, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_939 = mux(_T_921, _T_935, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_940 = or(_T_936, _T_937) @[Mux.scala 27:72] - node _T_941 = or(_T_940, _T_938) @[Mux.scala 27:72] - node _T_942 = or(_T_941, _T_939) @[Mux.scala 27:72] + mtdata1_t_ns[0] <= _T_836 @[dec_tlu_ctl.scala 2223:40] + mtdata1_t_ns[1] <= _T_845 @[dec_tlu_ctl.scala 2223:40] + mtdata1_t_ns[2] <= _T_854 @[dec_tlu_ctl.scala 2223:40] + mtdata1_t_ns[3] <= _T_863 @[dec_tlu_ctl.scala 2223:40] + reg _T_864 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2225:74] + _T_864 <= mtdata1_t_ns[0] @[dec_tlu_ctl.scala 2225:74] + io.mtdata1_t[0] <= _T_864 @[dec_tlu_ctl.scala 2225:39] + reg _T_865 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2225:74] + _T_865 <= mtdata1_t_ns[1] @[dec_tlu_ctl.scala 2225:74] + io.mtdata1_t[1] <= _T_865 @[dec_tlu_ctl.scala 2225:39] + reg _T_866 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2225:74] + _T_866 <= mtdata1_t_ns[2] @[dec_tlu_ctl.scala 2225:74] + io.mtdata1_t[2] <= _T_866 @[dec_tlu_ctl.scala 2225:39] + reg _T_867 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2225:74] + _T_867 <= mtdata1_t_ns[3] @[dec_tlu_ctl.scala 2225:74] + io.mtdata1_t[3] <= _T_867 @[dec_tlu_ctl.scala 2225:39] + node _T_868 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2228:58] + node _T_869 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2228:104] + node _T_870 = bits(io.mtdata1_t[0], 8, 7) @[dec_tlu_ctl.scala 2228:142] + node _T_871 = bits(io.mtdata1_t[0], 6, 5) @[dec_tlu_ctl.scala 2228:174] + node _T_872 = bits(io.mtdata1_t[0], 4, 3) @[dec_tlu_ctl.scala 2228:206] + node _T_873 = bits(io.mtdata1_t[0], 2, 0) @[dec_tlu_ctl.scala 2228:238] + node _T_874 = cat(UInt<3>("h00"), _T_873) @[Cat.scala 29:58] + node _T_875 = cat(_T_871, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_876 = cat(_T_875, _T_872) @[Cat.scala 29:58] + node _T_877 = cat(_T_876, _T_874) @[Cat.scala 29:58] + node _T_878 = cat(_T_870, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_879 = cat(UInt<4>("h02"), _T_869) @[Cat.scala 29:58] + node _T_880 = cat(_T_879, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_881 = cat(_T_880, _T_878) @[Cat.scala 29:58] + node _T_882 = cat(_T_881, _T_877) @[Cat.scala 29:58] + node _T_883 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2228:58] + node _T_884 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2228:104] + node _T_885 = bits(io.mtdata1_t[1], 8, 7) @[dec_tlu_ctl.scala 2228:142] + node _T_886 = bits(io.mtdata1_t[1], 6, 5) @[dec_tlu_ctl.scala 2228:174] + node _T_887 = bits(io.mtdata1_t[1], 4, 3) @[dec_tlu_ctl.scala 2228:206] + node _T_888 = bits(io.mtdata1_t[1], 2, 0) @[dec_tlu_ctl.scala 2228:238] + node _T_889 = cat(UInt<3>("h00"), _T_888) @[Cat.scala 29:58] + node _T_890 = cat(_T_886, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_891 = cat(_T_890, _T_887) @[Cat.scala 29:58] + node _T_892 = cat(_T_891, _T_889) @[Cat.scala 29:58] + node _T_893 = cat(_T_885, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_894 = cat(UInt<4>("h02"), _T_884) @[Cat.scala 29:58] + node _T_895 = cat(_T_894, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_896 = cat(_T_895, _T_893) @[Cat.scala 29:58] + node _T_897 = cat(_T_896, _T_892) @[Cat.scala 29:58] + node _T_898 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2228:58] + node _T_899 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2228:104] + node _T_900 = bits(io.mtdata1_t[2], 8, 7) @[dec_tlu_ctl.scala 2228:142] + node _T_901 = bits(io.mtdata1_t[2], 6, 5) @[dec_tlu_ctl.scala 2228:174] + node _T_902 = bits(io.mtdata1_t[2], 4, 3) @[dec_tlu_ctl.scala 2228:206] + node _T_903 = bits(io.mtdata1_t[2], 2, 0) @[dec_tlu_ctl.scala 2228:238] + node _T_904 = cat(UInt<3>("h00"), _T_903) @[Cat.scala 29:58] + node _T_905 = cat(_T_901, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_906 = cat(_T_905, _T_902) @[Cat.scala 29:58] + node _T_907 = cat(_T_906, _T_904) @[Cat.scala 29:58] + node _T_908 = cat(_T_900, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_909 = cat(UInt<4>("h02"), _T_899) @[Cat.scala 29:58] + node _T_910 = cat(_T_909, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_911 = cat(_T_910, _T_908) @[Cat.scala 29:58] + node _T_912 = cat(_T_911, _T_907) @[Cat.scala 29:58] + node _T_913 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2228:58] + node _T_914 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2228:104] + node _T_915 = bits(io.mtdata1_t[3], 8, 7) @[dec_tlu_ctl.scala 2228:142] + node _T_916 = bits(io.mtdata1_t[3], 6, 5) @[dec_tlu_ctl.scala 2228:174] + node _T_917 = bits(io.mtdata1_t[3], 4, 3) @[dec_tlu_ctl.scala 2228:206] + node _T_918 = bits(io.mtdata1_t[3], 2, 0) @[dec_tlu_ctl.scala 2228:238] + node _T_919 = cat(UInt<3>("h00"), _T_918) @[Cat.scala 29:58] + node _T_920 = cat(_T_916, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_921 = cat(_T_920, _T_917) @[Cat.scala 29:58] + node _T_922 = cat(_T_921, _T_919) @[Cat.scala 29:58] + node _T_923 = cat(_T_915, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_924 = cat(UInt<4>("h02"), _T_914) @[Cat.scala 29:58] + node _T_925 = cat(_T_924, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_926 = cat(_T_925, _T_923) @[Cat.scala 29:58] + node _T_927 = cat(_T_926, _T_922) @[Cat.scala 29:58] + node _T_928 = mux(_T_868, _T_882, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_929 = mux(_T_883, _T_897, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_930 = mux(_T_898, _T_912, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_931 = mux(_T_913, _T_927, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_932 = or(_T_928, _T_929) @[Mux.scala 27:72] + node _T_933 = or(_T_932, _T_930) @[Mux.scala 27:72] + node _T_934 = or(_T_933, _T_931) @[Mux.scala 27:72] wire mtdata1_tsel_out : UInt<32> @[Mux.scala 27:72] - mtdata1_tsel_out <= _T_942 @[Mux.scala 27:72] - node _T_943 = bits(io.mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 2230:58] - io.trigger_pkt_any[0].select <= _T_943 @[dec_tlu_ctl.scala 2230:40] - node _T_944 = bits(io.mtdata1_t[0], 4, 4) @[dec_tlu_ctl.scala 2231:61] - io.trigger_pkt_any[0].match_pkt <= _T_944 @[dec_tlu_ctl.scala 2231:43] - node _T_945 = bits(io.mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 2232:58] - io.trigger_pkt_any[0].store <= _T_945 @[dec_tlu_ctl.scala 2232:40] - node _T_946 = bits(io.mtdata1_t[0], 0, 0) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[0].load <= _T_946 @[dec_tlu_ctl.scala 2233:40] - node _T_947 = bits(io.mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[0].execute <= _T_947 @[dec_tlu_ctl.scala 2234:40] - node _T_948 = bits(io.mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 2235:58] - io.trigger_pkt_any[0].m <= _T_948 @[dec_tlu_ctl.scala 2235:40] - node _T_949 = bits(io.mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 2230:58] - io.trigger_pkt_any[1].select <= _T_949 @[dec_tlu_ctl.scala 2230:40] - node _T_950 = bits(io.mtdata1_t[1], 4, 4) @[dec_tlu_ctl.scala 2231:61] - io.trigger_pkt_any[1].match_pkt <= _T_950 @[dec_tlu_ctl.scala 2231:43] - node _T_951 = bits(io.mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 2232:58] - io.trigger_pkt_any[1].store <= _T_951 @[dec_tlu_ctl.scala 2232:40] - node _T_952 = bits(io.mtdata1_t[1], 0, 0) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[1].load <= _T_952 @[dec_tlu_ctl.scala 2233:40] - node _T_953 = bits(io.mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[1].execute <= _T_953 @[dec_tlu_ctl.scala 2234:40] - node _T_954 = bits(io.mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 2235:58] - io.trigger_pkt_any[1].m <= _T_954 @[dec_tlu_ctl.scala 2235:40] - node _T_955 = bits(io.mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 2230:58] - io.trigger_pkt_any[2].select <= _T_955 @[dec_tlu_ctl.scala 2230:40] - node _T_956 = bits(io.mtdata1_t[2], 4, 4) @[dec_tlu_ctl.scala 2231:61] - io.trigger_pkt_any[2].match_pkt <= _T_956 @[dec_tlu_ctl.scala 2231:43] - node _T_957 = bits(io.mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 2232:58] - io.trigger_pkt_any[2].store <= _T_957 @[dec_tlu_ctl.scala 2232:40] - node _T_958 = bits(io.mtdata1_t[2], 0, 0) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[2].load <= _T_958 @[dec_tlu_ctl.scala 2233:40] - node _T_959 = bits(io.mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[2].execute <= _T_959 @[dec_tlu_ctl.scala 2234:40] - node _T_960 = bits(io.mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 2235:58] - io.trigger_pkt_any[2].m <= _T_960 @[dec_tlu_ctl.scala 2235:40] - node _T_961 = bits(io.mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 2230:58] - io.trigger_pkt_any[3].select <= _T_961 @[dec_tlu_ctl.scala 2230:40] - node _T_962 = bits(io.mtdata1_t[3], 4, 4) @[dec_tlu_ctl.scala 2231:61] - io.trigger_pkt_any[3].match_pkt <= _T_962 @[dec_tlu_ctl.scala 2231:43] - node _T_963 = bits(io.mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 2232:58] - io.trigger_pkt_any[3].store <= _T_963 @[dec_tlu_ctl.scala 2232:40] - node _T_964 = bits(io.mtdata1_t[3], 0, 0) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[3].load <= _T_964 @[dec_tlu_ctl.scala 2233:40] - node _T_965 = bits(io.mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[3].execute <= _T_965 @[dec_tlu_ctl.scala 2234:40] - node _T_966 = bits(io.mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 2235:58] - io.trigger_pkt_any[3].m <= _T_966 @[dec_tlu_ctl.scala 2235:40] - node _T_967 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] - node _T_968 = eq(_T_967, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] - node _T_969 = and(io.dec_csr_wen_r_mod, _T_968) @[dec_tlu_ctl.scala 2242:69] - node _T_970 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2242:120] - node _T_971 = and(_T_969, _T_970) @[dec_tlu_ctl.scala 2242:111] - node _T_972 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2242:153] - node _T_973 = not(_T_972) @[dec_tlu_ctl.scala 2242:137] - node _T_974 = or(_T_973, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] - node _T_975 = and(_T_971, _T_974) @[dec_tlu_ctl.scala 2242:134] - node _T_976 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] - node _T_977 = eq(_T_976, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] - node _T_978 = and(io.dec_csr_wen_r_mod, _T_977) @[dec_tlu_ctl.scala 2242:69] - node _T_979 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2242:120] - node _T_980 = and(_T_978, _T_979) @[dec_tlu_ctl.scala 2242:111] - node _T_981 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2242:153] - node _T_982 = not(_T_981) @[dec_tlu_ctl.scala 2242:137] - node _T_983 = or(_T_982, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] - node _T_984 = and(_T_980, _T_983) @[dec_tlu_ctl.scala 2242:134] - node _T_985 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] - node _T_986 = eq(_T_985, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] - node _T_987 = and(io.dec_csr_wen_r_mod, _T_986) @[dec_tlu_ctl.scala 2242:69] - node _T_988 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2242:120] - node _T_989 = and(_T_987, _T_988) @[dec_tlu_ctl.scala 2242:111] - node _T_990 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2242:153] - node _T_991 = not(_T_990) @[dec_tlu_ctl.scala 2242:137] - node _T_992 = or(_T_991, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] - node _T_993 = and(_T_989, _T_992) @[dec_tlu_ctl.scala 2242:134] - node _T_994 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] - node _T_995 = eq(_T_994, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] - node _T_996 = and(io.dec_csr_wen_r_mod, _T_995) @[dec_tlu_ctl.scala 2242:69] - node _T_997 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2242:120] - node _T_998 = and(_T_996, _T_997) @[dec_tlu_ctl.scala 2242:111] - node _T_999 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2242:153] - node _T_1000 = not(_T_999) @[dec_tlu_ctl.scala 2242:137] - node _T_1001 = or(_T_1000, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] - node _T_1002 = and(_T_998, _T_1001) @[dec_tlu_ctl.scala 2242:134] + mtdata1_tsel_out <= _T_934 @[Mux.scala 27:72] + node _T_935 = bits(io.mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 2230:58] + io.trigger_pkt_any[0].select <= _T_935 @[dec_tlu_ctl.scala 2230:40] + node _T_936 = bits(io.mtdata1_t[0], 4, 4) @[dec_tlu_ctl.scala 2231:61] + io.trigger_pkt_any[0].match_pkt <= _T_936 @[dec_tlu_ctl.scala 2231:43] + node _T_937 = bits(io.mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 2232:58] + io.trigger_pkt_any[0].store <= _T_937 @[dec_tlu_ctl.scala 2232:40] + node _T_938 = bits(io.mtdata1_t[0], 0, 0) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[0].load <= _T_938 @[dec_tlu_ctl.scala 2233:40] + node _T_939 = bits(io.mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[0].execute <= _T_939 @[dec_tlu_ctl.scala 2234:40] + node _T_940 = bits(io.mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 2235:58] + io.trigger_pkt_any[0].m <= _T_940 @[dec_tlu_ctl.scala 2235:40] + node _T_941 = bits(io.mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 2230:58] + io.trigger_pkt_any[1].select <= _T_941 @[dec_tlu_ctl.scala 2230:40] + node _T_942 = bits(io.mtdata1_t[1], 4, 4) @[dec_tlu_ctl.scala 2231:61] + io.trigger_pkt_any[1].match_pkt <= _T_942 @[dec_tlu_ctl.scala 2231:43] + node _T_943 = bits(io.mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 2232:58] + io.trigger_pkt_any[1].store <= _T_943 @[dec_tlu_ctl.scala 2232:40] + node _T_944 = bits(io.mtdata1_t[1], 0, 0) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[1].load <= _T_944 @[dec_tlu_ctl.scala 2233:40] + node _T_945 = bits(io.mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[1].execute <= _T_945 @[dec_tlu_ctl.scala 2234:40] + node _T_946 = bits(io.mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 2235:58] + io.trigger_pkt_any[1].m <= _T_946 @[dec_tlu_ctl.scala 2235:40] + node _T_947 = bits(io.mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 2230:58] + io.trigger_pkt_any[2].select <= _T_947 @[dec_tlu_ctl.scala 2230:40] + node _T_948 = bits(io.mtdata1_t[2], 4, 4) @[dec_tlu_ctl.scala 2231:61] + io.trigger_pkt_any[2].match_pkt <= _T_948 @[dec_tlu_ctl.scala 2231:43] + node _T_949 = bits(io.mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 2232:58] + io.trigger_pkt_any[2].store <= _T_949 @[dec_tlu_ctl.scala 2232:40] + node _T_950 = bits(io.mtdata1_t[2], 0, 0) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[2].load <= _T_950 @[dec_tlu_ctl.scala 2233:40] + node _T_951 = bits(io.mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[2].execute <= _T_951 @[dec_tlu_ctl.scala 2234:40] + node _T_952 = bits(io.mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 2235:58] + io.trigger_pkt_any[2].m <= _T_952 @[dec_tlu_ctl.scala 2235:40] + node _T_953 = bits(io.mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 2230:58] + io.trigger_pkt_any[3].select <= _T_953 @[dec_tlu_ctl.scala 2230:40] + node _T_954 = bits(io.mtdata1_t[3], 4, 4) @[dec_tlu_ctl.scala 2231:61] + io.trigger_pkt_any[3].match_pkt <= _T_954 @[dec_tlu_ctl.scala 2231:43] + node _T_955 = bits(io.mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 2232:58] + io.trigger_pkt_any[3].store <= _T_955 @[dec_tlu_ctl.scala 2232:40] + node _T_956 = bits(io.mtdata1_t[3], 0, 0) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[3].load <= _T_956 @[dec_tlu_ctl.scala 2233:40] + node _T_957 = bits(io.mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[3].execute <= _T_957 @[dec_tlu_ctl.scala 2234:40] + node _T_958 = bits(io.mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 2235:58] + io.trigger_pkt_any[3].m <= _T_958 @[dec_tlu_ctl.scala 2235:40] + node _T_959 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] + node _T_960 = eq(_T_959, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] + node _T_961 = and(io.dec_csr_wen_r_mod, _T_960) @[dec_tlu_ctl.scala 2242:69] + node _T_962 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2242:120] + node _T_963 = and(_T_961, _T_962) @[dec_tlu_ctl.scala 2242:111] + node _T_964 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2242:153] + node _T_965 = not(_T_964) @[dec_tlu_ctl.scala 2242:137] + node _T_966 = or(_T_965, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] + node _T_967 = and(_T_963, _T_966) @[dec_tlu_ctl.scala 2242:134] + node _T_968 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] + node _T_969 = eq(_T_968, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] + node _T_970 = and(io.dec_csr_wen_r_mod, _T_969) @[dec_tlu_ctl.scala 2242:69] + node _T_971 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2242:120] + node _T_972 = and(_T_970, _T_971) @[dec_tlu_ctl.scala 2242:111] + node _T_973 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2242:153] + node _T_974 = not(_T_973) @[dec_tlu_ctl.scala 2242:137] + node _T_975 = or(_T_974, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] + node _T_976 = and(_T_972, _T_975) @[dec_tlu_ctl.scala 2242:134] + node _T_977 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] + node _T_978 = eq(_T_977, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] + node _T_979 = and(io.dec_csr_wen_r_mod, _T_978) @[dec_tlu_ctl.scala 2242:69] + node _T_980 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2242:120] + node _T_981 = and(_T_979, _T_980) @[dec_tlu_ctl.scala 2242:111] + node _T_982 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2242:153] + node _T_983 = not(_T_982) @[dec_tlu_ctl.scala 2242:137] + node _T_984 = or(_T_983, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] + node _T_985 = and(_T_981, _T_984) @[dec_tlu_ctl.scala 2242:134] + node _T_986 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] + node _T_987 = eq(_T_986, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] + node _T_988 = and(io.dec_csr_wen_r_mod, _T_987) @[dec_tlu_ctl.scala 2242:69] + node _T_989 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2242:120] + node _T_990 = and(_T_988, _T_989) @[dec_tlu_ctl.scala 2242:111] + node _T_991 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2242:153] + node _T_992 = not(_T_991) @[dec_tlu_ctl.scala 2242:137] + node _T_993 = or(_T_992, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] + node _T_994 = and(_T_990, _T_993) @[dec_tlu_ctl.scala 2242:134] wire wr_mtdata2_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2242:42] - wr_mtdata2_t_r[0] <= _T_975 @[dec_tlu_ctl.scala 2242:42] - wr_mtdata2_t_r[1] <= _T_984 @[dec_tlu_ctl.scala 2242:42] - wr_mtdata2_t_r[2] <= _T_993 @[dec_tlu_ctl.scala 2242:42] - wr_mtdata2_t_r[3] <= _T_1002 @[dec_tlu_ctl.scala 2242:42] - node _T_1003 = bits(wr_mtdata2_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2243:84] - inst rvclkhdr_22 of rvclkhdr_742 @[el2_lib.scala 508:23] + wr_mtdata2_t_r[0] <= _T_967 @[dec_tlu_ctl.scala 2242:42] + wr_mtdata2_t_r[1] <= _T_976 @[dec_tlu_ctl.scala 2242:42] + wr_mtdata2_t_r[2] <= _T_985 @[dec_tlu_ctl.scala 2242:42] + wr_mtdata2_t_r[3] <= _T_994 @[dec_tlu_ctl.scala 2242:42] + node _T_995 = bits(wr_mtdata2_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2243:84] + inst rvclkhdr_22 of rvclkhdr_742 @[lib.scala 368:23] rvclkhdr_22.clock <= clock rvclkhdr_22.reset <= reset - rvclkhdr_22.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_22.io.en <= _T_1003 @[el2_lib.scala 511:17] - rvclkhdr_22.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_1004 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_1004 <= io.dec_csr_wrdata_r @[el2_lib.scala 514:16] - mtdata2_t[0] <= _T_1004 @[dec_tlu_ctl.scala 2243:36] - node _T_1005 = bits(wr_mtdata2_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2243:84] - inst rvclkhdr_23 of rvclkhdr_743 @[el2_lib.scala 508:23] + rvclkhdr_22.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_22.io.en <= _T_995 @[lib.scala 371:17] + rvclkhdr_22.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_996 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_996 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[0] <= _T_996 @[dec_tlu_ctl.scala 2243:36] + node _T_997 = bits(wr_mtdata2_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2243:84] + inst rvclkhdr_23 of rvclkhdr_743 @[lib.scala 368:23] rvclkhdr_23.clock <= clock rvclkhdr_23.reset <= reset - rvclkhdr_23.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_23.io.en <= _T_1005 @[el2_lib.scala 511:17] - rvclkhdr_23.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_1006 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_1006 <= io.dec_csr_wrdata_r @[el2_lib.scala 514:16] - mtdata2_t[1] <= _T_1006 @[dec_tlu_ctl.scala 2243:36] - node _T_1007 = bits(wr_mtdata2_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2243:84] - inst rvclkhdr_24 of rvclkhdr_744 @[el2_lib.scala 508:23] + rvclkhdr_23.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_23.io.en <= _T_997 @[lib.scala 371:17] + rvclkhdr_23.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_998 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_998 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[1] <= _T_998 @[dec_tlu_ctl.scala 2243:36] + node _T_999 = bits(wr_mtdata2_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2243:84] + inst rvclkhdr_24 of rvclkhdr_744 @[lib.scala 368:23] rvclkhdr_24.clock <= clock rvclkhdr_24.reset <= reset - rvclkhdr_24.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_24.io.en <= _T_1007 @[el2_lib.scala 511:17] - rvclkhdr_24.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_1008 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_1008 <= io.dec_csr_wrdata_r @[el2_lib.scala 514:16] - mtdata2_t[2] <= _T_1008 @[dec_tlu_ctl.scala 2243:36] - node _T_1009 = bits(wr_mtdata2_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2243:84] - inst rvclkhdr_25 of rvclkhdr_745 @[el2_lib.scala 508:23] + rvclkhdr_24.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_24.io.en <= _T_999 @[lib.scala 371:17] + rvclkhdr_24.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_1000 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1000 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[2] <= _T_1000 @[dec_tlu_ctl.scala 2243:36] + node _T_1001 = bits(wr_mtdata2_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2243:84] + inst rvclkhdr_25 of rvclkhdr_745 @[lib.scala 368:23] rvclkhdr_25.clock <= clock rvclkhdr_25.reset <= reset - rvclkhdr_25.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_25.io.en <= _T_1009 @[el2_lib.scala 511:17] - rvclkhdr_25.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_1010 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_1010 <= io.dec_csr_wrdata_r @[el2_lib.scala 514:16] - mtdata2_t[3] <= _T_1010 @[dec_tlu_ctl.scala 2243:36] - node _T_1011 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2247:57] - node _T_1012 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2247:57] - node _T_1013 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2247:57] - node _T_1014 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2247:57] - node _T_1015 = mux(_T_1011, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1016 = mux(_T_1012, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1017 = mux(_T_1013, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1018 = mux(_T_1014, mtdata2_t[3], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1019 = or(_T_1015, _T_1016) @[Mux.scala 27:72] - node _T_1020 = or(_T_1019, _T_1017) @[Mux.scala 27:72] - node _T_1021 = or(_T_1020, _T_1018) @[Mux.scala 27:72] + rvclkhdr_25.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_25.io.en <= _T_1001 @[lib.scala 371:17] + rvclkhdr_25.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_1002 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1002 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[3] <= _T_1002 @[dec_tlu_ctl.scala 2243:36] + node _T_1003 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2247:57] + node _T_1004 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2247:57] + node _T_1005 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2247:57] + node _T_1006 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2247:57] + node _T_1007 = mux(_T_1003, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1008 = mux(_T_1004, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1009 = mux(_T_1005, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1010 = mux(_T_1006, mtdata2_t[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1011 = or(_T_1007, _T_1008) @[Mux.scala 27:72] + node _T_1012 = or(_T_1011, _T_1009) @[Mux.scala 27:72] + node _T_1013 = or(_T_1012, _T_1010) @[Mux.scala 27:72] wire mtdata2_tsel_out : UInt<32> @[Mux.scala 27:72] - mtdata2_tsel_out <= _T_1021 @[Mux.scala 27:72] + mtdata2_tsel_out <= _T_1013 @[Mux.scala 27:72] io.trigger_pkt_any[0].tdata2 <= mtdata2_t[0] @[dec_tlu_ctl.scala 2248:51] io.trigger_pkt_any[1].tdata2 <= mtdata2_t[1] @[dec_tlu_ctl.scala 2248:51] io.trigger_pkt_any[2].tdata2 <= mtdata2_t[2] @[dec_tlu_ctl.scala 2248:51] @@ -74402,238 +74394,246 @@ circuit quasar_wrapper : mhpme_vec[1] <= mhpme4 @[dec_tlu_ctl.scala 2259:15] mhpme_vec[2] <= mhpme5 @[dec_tlu_ctl.scala 2260:15] mhpme_vec[3] <= mhpme6 @[dec_tlu_ctl.scala 2261:15] - node _T_1022 = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15] - node _T_1023 = mux(_T_1022, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1023) @[dec_tlu_ctl.scala 2267:59] + node _T_1014 = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15] + node _T_1015 = mux(_T_1014, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1015) @[dec_tlu_ctl.scala 2267:59] wire mhpmc_inc_r : UInt<1>[4] @[dec_tlu_ctl.scala 2268:24] wire mhpmc_inc_r_d1 : UInt<1>[4] @[dec_tlu_ctl.scala 2269:27] - node _T_1024 = bits(mcountinhibit, 3, 3) @[dec_tlu_ctl.scala 2273:38] - node _T_1025 = not(_T_1024) @[dec_tlu_ctl.scala 2273:24] - node _T_1026 = eq(mhpme_vec[0], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] - node _T_1027 = bits(_T_1026, 0, 0) @[dec_tlu_ctl.scala 2274:62] - node _T_1028 = eq(mhpme_vec[0], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] - node _T_1029 = bits(_T_1028, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1030 = eq(mhpme_vec[0], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] - node _T_1031 = bits(_T_1030, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1032 = eq(mhpme_vec[0], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] - node _T_1033 = bits(_T_1032, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1034 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] - node _T_1035 = and(io.tlu_i0_commit_cmt, _T_1034) @[dec_tlu_ctl.scala 2277:94] - node _T_1036 = eq(mhpme_vec[0], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] - node _T_1037 = bits(_T_1036, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1038 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] - node _T_1039 = and(io.tlu_i0_commit_cmt, _T_1038) @[dec_tlu_ctl.scala 2278:94] - node _T_1040 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] - node _T_1041 = and(_T_1039, _T_1040) @[dec_tlu_ctl.scala 2278:115] - node _T_1042 = eq(mhpme_vec[0], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] - node _T_1043 = bits(_T_1042, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1044 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] - node _T_1045 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] - node _T_1046 = and(_T_1044, _T_1045) @[dec_tlu_ctl.scala 2279:115] - node _T_1047 = eq(mhpme_vec[0], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] - node _T_1048 = bits(_T_1047, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1049 = eq(mhpme_vec[0], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] - node _T_1050 = bits(_T_1049, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1051 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] - node _T_1052 = bits(_T_1051, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1053 = eq(mhpme_vec[0], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] - node _T_1054 = bits(_T_1053, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1055 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] - node _T_1056 = eq(mhpme_vec[0], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] - node _T_1057 = bits(_T_1056, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1058 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] - node _T_1059 = eq(mhpme_vec[0], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] - node _T_1060 = bits(_T_1059, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1061 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] - node _T_1062 = eq(mhpme_vec[0], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] - node _T_1063 = bits(_T_1062, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1064 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] - node _T_1065 = eq(mhpme_vec[0], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] - node _T_1066 = bits(_T_1065, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1067 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] - node _T_1068 = and(_T_1067, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] - node _T_1069 = eq(mhpme_vec[0], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] - node _T_1070 = bits(_T_1069, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1071 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] - node _T_1072 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] - node _T_1073 = and(_T_1071, _T_1072) @[dec_tlu_ctl.scala 2288:101] - node _T_1074 = eq(mhpme_vec[0], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] - node _T_1075 = bits(_T_1074, 0, 0) @[dec_tlu_ctl.scala 2289:59] - node _T_1076 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] - node _T_1077 = eq(mhpme_vec[0], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] - node _T_1078 = bits(_T_1077, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1079 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] - node _T_1080 = eq(mhpme_vec[0], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] - node _T_1081 = bits(_T_1080, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1082 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] - node _T_1083 = eq(mhpme_vec[0], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] - node _T_1084 = bits(_T_1083, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1085 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] - node _T_1086 = eq(mhpme_vec[0], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] - node _T_1087 = bits(_T_1086, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1088 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] - node _T_1089 = eq(mhpme_vec[0], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] - node _T_1090 = bits(_T_1089, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1091 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] - node _T_1092 = eq(mhpme_vec[0], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] - node _T_1093 = bits(_T_1092, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1094 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] - node _T_1095 = eq(mhpme_vec[0], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] - node _T_1096 = bits(_T_1095, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1097 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] - node _T_1098 = eq(mhpme_vec[0], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] - node _T_1099 = bits(_T_1098, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1100 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] - node _T_1101 = eq(mhpme_vec[0], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] - node _T_1102 = bits(_T_1101, 0, 0) @[dec_tlu_ctl.scala 2298:59] - node _T_1103 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] - node _T_1104 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] - node _T_1105 = or(_T_1103, _T_1104) @[dec_tlu_ctl.scala 2298:101] - node _T_1106 = eq(mhpme_vec[0], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] - node _T_1107 = bits(_T_1106, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1108 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] - node _T_1109 = eq(mhpme_vec[0], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] - node _T_1110 = bits(_T_1109, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1111 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] - node _T_1112 = eq(mhpme_vec[0], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] - node _T_1113 = bits(_T_1112, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1114 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] - node _T_1115 = eq(mhpme_vec[0], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] - node _T_1116 = bits(_T_1115, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1117 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] - node _T_1118 = bits(_T_1117, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1119 = eq(mhpme_vec[0], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] - node _T_1120 = bits(_T_1119, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1121 = eq(mhpme_vec[0], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] - node _T_1122 = bits(_T_1121, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1123 = eq(mhpme_vec[0], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] - node _T_1124 = bits(_T_1123, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1125 = eq(mhpme_vec[0], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] - node _T_1126 = bits(_T_1125, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1127 = eq(mhpme_vec[0], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] - node _T_1128 = bits(_T_1127, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1129 = eq(mhpme_vec[0], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] - node _T_1130 = bits(_T_1129, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1131 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] - node _T_1132 = or(_T_1131, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] - node _T_1133 = eq(mhpme_vec[0], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] - node _T_1134 = bits(_T_1133, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1135 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] - node _T_1136 = or(_T_1135, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] - node _T_1137 = eq(mhpme_vec[0], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] - node _T_1138 = bits(_T_1137, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1139 = eq(mhpme_vec[0], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] - node _T_1140 = bits(_T_1139, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1141 = eq(mhpme_vec[0], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] - node _T_1142 = bits(_T_1141, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1143 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] - node _T_1144 = and(_T_1143, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] - node _T_1145 = eq(mhpme_vec[0], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] - node _T_1146 = bits(_T_1145, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1147 = eq(mhpme_vec[0], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] - node _T_1148 = bits(_T_1147, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_1149 = eq(mhpme_vec[0], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] - node _T_1150 = bits(_T_1149, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_1151 = eq(mhpme_vec[0], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] - node _T_1152 = bits(_T_1151, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_1153 = eq(mhpme_vec[0], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] - node _T_1154 = bits(_T_1153, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_1155 = eq(mhpme_vec[0], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] - node _T_1156 = bits(_T_1155, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_1157 = eq(mhpme_vec[0], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] - node _T_1158 = bits(_T_1157, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_1159 = eq(mhpme_vec[0], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] - node _T_1160 = bits(_T_1159, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_1161 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] - node _T_1162 = bits(_T_1161, 0, 0) @[dec_tlu_ctl.scala 2321:84] - node _T_1163 = not(_T_1162) @[dec_tlu_ctl.scala 2321:73] - node _T_1164 = eq(mhpme_vec[0], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] - node _T_1165 = bits(_T_1164, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_1166 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] - node _T_1167 = bits(_T_1166, 0, 0) @[dec_tlu_ctl.scala 2322:84] - node _T_1168 = not(_T_1167) @[dec_tlu_ctl.scala 2322:73] - node _T_1169 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] - node _T_1170 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] - node _T_1171 = and(_T_1169, _T_1170) @[dec_tlu_ctl.scala 2322:113] - node _T_1172 = orr(_T_1171) @[dec_tlu_ctl.scala 2322:125] - node _T_1173 = and(_T_1168, _T_1172) @[dec_tlu_ctl.scala 2322:98] - node _T_1174 = eq(mhpme_vec[0], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] - node _T_1175 = bits(_T_1174, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_1176 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] - node _T_1177 = eq(mhpme_vec[0], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] - node _T_1178 = bits(_T_1177, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_1179 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] - node _T_1180 = eq(mhpme_vec[0], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] - node _T_1181 = bits(_T_1180, 0, 0) @[dec_tlu_ctl.scala 2325:62] - node _T_1182 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] - node _T_1183 = eq(mhpme_vec[0], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] - node _T_1184 = bits(_T_1183, 0, 0) @[dec_tlu_ctl.scala 2327:62] - node _T_1185 = eq(mhpme_vec[0], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] - node _T_1186 = bits(_T_1185, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_1187 = eq(mhpme_vec[0], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] - node _T_1188 = bits(_T_1187, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_1189 = eq(mhpme_vec[0], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] - node _T_1190 = bits(_T_1189, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_1191 = eq(mhpme_vec[0], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] - node _T_1192 = bits(_T_1191, 0, 0) @[dec_tlu_ctl.scala 2331:62] - node _T_1193 = mux(_T_1027, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1194 = mux(_T_1029, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1195 = mux(_T_1031, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1196 = mux(_T_1033, _T_1035, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1197 = mux(_T_1037, _T_1041, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1198 = mux(_T_1043, _T_1046, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1199 = mux(_T_1048, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1200 = mux(_T_1050, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1201 = mux(_T_1052, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1202 = mux(_T_1054, _T_1055, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1203 = mux(_T_1057, _T_1058, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1204 = mux(_T_1060, _T_1061, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1205 = mux(_T_1063, _T_1064, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1206 = mux(_T_1066, _T_1068, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1207 = mux(_T_1070, _T_1073, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1208 = mux(_T_1075, _T_1076, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1209 = mux(_T_1078, _T_1079, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1210 = mux(_T_1081, _T_1082, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1211 = mux(_T_1084, _T_1085, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1212 = mux(_T_1087, _T_1088, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1213 = mux(_T_1090, _T_1091, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1214 = mux(_T_1093, _T_1094, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1215 = mux(_T_1096, _T_1097, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1216 = mux(_T_1099, _T_1100, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1217 = mux(_T_1102, _T_1105, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1218 = mux(_T_1107, _T_1108, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1219 = mux(_T_1110, _T_1111, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1220 = mux(_T_1113, _T_1114, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1221 = mux(_T_1116, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1222 = mux(_T_1118, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1223 = mux(_T_1120, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1224 = mux(_T_1122, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1225 = mux(_T_1124, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1226 = mux(_T_1126, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1227 = mux(_T_1128, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1228 = mux(_T_1130, _T_1132, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1229 = mux(_T_1134, _T_1136, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1230 = mux(_T_1138, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1231 = mux(_T_1140, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1232 = mux(_T_1142, _T_1144, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1233 = mux(_T_1146, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1234 = mux(_T_1148, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1235 = mux(_T_1150, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1236 = mux(_T_1152, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1237 = mux(_T_1154, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1238 = mux(_T_1156, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1239 = mux(_T_1158, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1240 = mux(_T_1160, _T_1163, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1241 = mux(_T_1165, _T_1173, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1242 = mux(_T_1175, _T_1176, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1243 = mux(_T_1178, _T_1179, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1244 = mux(_T_1181, _T_1182, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1245 = mux(_T_1184, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1246 = mux(_T_1186, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1247 = mux(_T_1188, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1248 = mux(_T_1190, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1249 = mux(_T_1192, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1250 = or(_T_1193, _T_1194) @[Mux.scala 27:72] + node _T_1016 = bits(mcountinhibit, 3, 3) @[dec_tlu_ctl.scala 2273:38] + node _T_1017 = not(_T_1016) @[dec_tlu_ctl.scala 2273:24] + node _T_1018 = eq(mhpme_vec[0], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] + node _T_1019 = bits(_T_1018, 0, 0) @[dec_tlu_ctl.scala 2274:62] + node _T_1020 = eq(mhpme_vec[0], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] + node _T_1021 = bits(_T_1020, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1022 = eq(mhpme_vec[0], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] + node _T_1023 = bits(_T_1022, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1024 = eq(mhpme_vec[0], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] + node _T_1025 = bits(_T_1024, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1026 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] + node _T_1027 = and(io.tlu_i0_commit_cmt, _T_1026) @[dec_tlu_ctl.scala 2277:94] + node _T_1028 = eq(mhpme_vec[0], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] + node _T_1029 = bits(_T_1028, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1030 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] + node _T_1031 = and(io.tlu_i0_commit_cmt, _T_1030) @[dec_tlu_ctl.scala 2278:94] + node _T_1032 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] + node _T_1033 = and(_T_1031, _T_1032) @[dec_tlu_ctl.scala 2278:115] + node _T_1034 = eq(mhpme_vec[0], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] + node _T_1035 = bits(_T_1034, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1036 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] + node _T_1037 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] + node _T_1038 = and(_T_1036, _T_1037) @[dec_tlu_ctl.scala 2279:115] + node _T_1039 = eq(mhpme_vec[0], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] + node _T_1040 = bits(_T_1039, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1041 = eq(mhpme_vec[0], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] + node _T_1042 = bits(_T_1041, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1043 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] + node _T_1044 = bits(_T_1043, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1045 = eq(mhpme_vec[0], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] + node _T_1046 = bits(_T_1045, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1047 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] + node _T_1048 = eq(mhpme_vec[0], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] + node _T_1049 = bits(_T_1048, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1050 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] + node _T_1051 = eq(mhpme_vec[0], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] + node _T_1052 = bits(_T_1051, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1053 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] + node _T_1054 = eq(mhpme_vec[0], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] + node _T_1055 = bits(_T_1054, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1056 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] + node _T_1057 = eq(mhpme_vec[0], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] + node _T_1058 = bits(_T_1057, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1059 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] + node _T_1060 = and(_T_1059, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] + node _T_1061 = eq(mhpme_vec[0], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] + node _T_1062 = bits(_T_1061, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1063 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] + node _T_1064 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] + node _T_1065 = and(_T_1063, _T_1064) @[dec_tlu_ctl.scala 2288:101] + node _T_1066 = eq(mhpme_vec[0], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] + node _T_1067 = bits(_T_1066, 0, 0) @[dec_tlu_ctl.scala 2289:59] + node _T_1068 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] + node _T_1069 = eq(mhpme_vec[0], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] + node _T_1070 = bits(_T_1069, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1071 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] + node _T_1072 = eq(mhpme_vec[0], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] + node _T_1073 = bits(_T_1072, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1074 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] + node _T_1075 = eq(mhpme_vec[0], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] + node _T_1076 = bits(_T_1075, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1077 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] + node _T_1078 = eq(mhpme_vec[0], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] + node _T_1079 = bits(_T_1078, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1080 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] + node _T_1081 = eq(mhpme_vec[0], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] + node _T_1082 = bits(_T_1081, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1083 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] + node _T_1084 = eq(mhpme_vec[0], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] + node _T_1085 = bits(_T_1084, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1086 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] + node _T_1087 = eq(mhpme_vec[0], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] + node _T_1088 = bits(_T_1087, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1089 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] + node _T_1090 = eq(mhpme_vec[0], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] + node _T_1091 = bits(_T_1090, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1092 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] + node _T_1093 = eq(mhpme_vec[0], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] + node _T_1094 = bits(_T_1093, 0, 0) @[dec_tlu_ctl.scala 2298:59] + node _T_1095 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] + node _T_1096 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] + node _T_1097 = or(_T_1095, _T_1096) @[dec_tlu_ctl.scala 2298:101] + node _T_1098 = eq(mhpme_vec[0], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] + node _T_1099 = bits(_T_1098, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1100 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] + node _T_1101 = eq(mhpme_vec[0], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] + node _T_1102 = bits(_T_1101, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1103 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] + node _T_1104 = eq(mhpme_vec[0], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] + node _T_1105 = bits(_T_1104, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1106 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] + node _T_1107 = eq(mhpme_vec[0], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] + node _T_1108 = bits(_T_1107, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1109 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] + node _T_1110 = bits(_T_1109, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1111 = eq(mhpme_vec[0], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] + node _T_1112 = bits(_T_1111, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1113 = eq(mhpme_vec[0], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] + node _T_1114 = bits(_T_1113, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1115 = eq(mhpme_vec[0], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] + node _T_1116 = bits(_T_1115, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1117 = eq(mhpme_vec[0], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] + node _T_1118 = bits(_T_1117, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1119 = eq(mhpme_vec[0], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] + node _T_1120 = bits(_T_1119, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1121 = eq(mhpme_vec[0], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] + node _T_1122 = bits(_T_1121, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1123 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] + node _T_1124 = or(_T_1123, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] + node _T_1125 = eq(mhpme_vec[0], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] + node _T_1126 = bits(_T_1125, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1127 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] + node _T_1128 = or(_T_1127, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] + node _T_1129 = eq(mhpme_vec[0], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] + node _T_1130 = bits(_T_1129, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1131 = eq(mhpme_vec[0], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] + node _T_1132 = bits(_T_1131, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1133 = eq(mhpme_vec[0], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] + node _T_1134 = bits(_T_1133, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1135 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] + node _T_1136 = and(_T_1135, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] + node _T_1137 = eq(mhpme_vec[0], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] + node _T_1138 = bits(_T_1137, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_1139 = eq(mhpme_vec[0], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] + node _T_1140 = bits(_T_1139, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_1141 = eq(mhpme_vec[0], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] + node _T_1142 = bits(_T_1141, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_1143 = eq(mhpme_vec[0], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] + node _T_1144 = bits(_T_1143, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_1145 = eq(mhpme_vec[0], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] + node _T_1146 = bits(_T_1145, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_1147 = eq(mhpme_vec[0], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] + node _T_1148 = bits(_T_1147, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_1149 = eq(mhpme_vec[0], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] + node _T_1150 = bits(_T_1149, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_1151 = eq(mhpme_vec[0], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] + node _T_1152 = bits(_T_1151, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_1153 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] + node _T_1154 = bits(_T_1153, 0, 0) @[dec_tlu_ctl.scala 2321:84] + node _T_1155 = not(_T_1154) @[dec_tlu_ctl.scala 2321:73] + node _T_1156 = eq(mhpme_vec[0], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] + node _T_1157 = bits(_T_1156, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_1158 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] + node _T_1159 = bits(_T_1158, 0, 0) @[dec_tlu_ctl.scala 2322:84] + node _T_1160 = not(_T_1159) @[dec_tlu_ctl.scala 2322:73] + node _T_1161 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] + node _T_1162 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] + node _T_1163 = and(_T_1161, _T_1162) @[dec_tlu_ctl.scala 2322:113] + node _T_1164 = orr(_T_1163) @[dec_tlu_ctl.scala 2322:125] + node _T_1165 = and(_T_1160, _T_1164) @[dec_tlu_ctl.scala 2322:98] + node _T_1166 = eq(mhpme_vec[0], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] + node _T_1167 = bits(_T_1166, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_1168 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] + node _T_1169 = eq(mhpme_vec[0], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] + node _T_1170 = bits(_T_1169, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_1171 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] + node _T_1172 = eq(mhpme_vec[0], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] + node _T_1173 = bits(_T_1172, 0, 0) @[dec_tlu_ctl.scala 2325:62] + node _T_1174 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] + node _T_1175 = eq(mhpme_vec[0], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] + node _T_1176 = bits(_T_1175, 0, 0) @[dec_tlu_ctl.scala 2327:62] + node _T_1177 = eq(mhpme_vec[0], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] + node _T_1178 = bits(_T_1177, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_1179 = eq(mhpme_vec[0], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] + node _T_1180 = bits(_T_1179, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_1181 = eq(mhpme_vec[0], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] + node _T_1182 = bits(_T_1181, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_1183 = eq(mhpme_vec[0], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] + node _T_1184 = bits(_T_1183, 0, 0) @[dec_tlu_ctl.scala 2331:62] + node _T_1185 = mux(_T_1019, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1186 = mux(_T_1021, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1187 = mux(_T_1023, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1188 = mux(_T_1025, _T_1027, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1189 = mux(_T_1029, _T_1033, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1190 = mux(_T_1035, _T_1038, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1191 = mux(_T_1040, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1192 = mux(_T_1042, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1193 = mux(_T_1044, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1194 = mux(_T_1046, _T_1047, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1195 = mux(_T_1049, _T_1050, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1196 = mux(_T_1052, _T_1053, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1197 = mux(_T_1055, _T_1056, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1198 = mux(_T_1058, _T_1060, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1199 = mux(_T_1062, _T_1065, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1200 = mux(_T_1067, _T_1068, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1201 = mux(_T_1070, _T_1071, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1202 = mux(_T_1073, _T_1074, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1203 = mux(_T_1076, _T_1077, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1204 = mux(_T_1079, _T_1080, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1205 = mux(_T_1082, _T_1083, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1206 = mux(_T_1085, _T_1086, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1207 = mux(_T_1088, _T_1089, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1208 = mux(_T_1091, _T_1092, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1209 = mux(_T_1094, _T_1097, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1210 = mux(_T_1099, _T_1100, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1211 = mux(_T_1102, _T_1103, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1212 = mux(_T_1105, _T_1106, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1213 = mux(_T_1108, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1214 = mux(_T_1110, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1215 = mux(_T_1112, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1216 = mux(_T_1114, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1217 = mux(_T_1116, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1218 = mux(_T_1118, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1219 = mux(_T_1120, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1220 = mux(_T_1122, _T_1124, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1221 = mux(_T_1126, _T_1128, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1222 = mux(_T_1130, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1223 = mux(_T_1132, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1224 = mux(_T_1134, _T_1136, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1225 = mux(_T_1138, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1226 = mux(_T_1140, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1227 = mux(_T_1142, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1228 = mux(_T_1144, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1229 = mux(_T_1146, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1230 = mux(_T_1148, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1231 = mux(_T_1150, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1232 = mux(_T_1152, _T_1155, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1233 = mux(_T_1157, _T_1165, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1234 = mux(_T_1167, _T_1168, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1235 = mux(_T_1170, _T_1171, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1236 = mux(_T_1173, _T_1174, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1237 = mux(_T_1176, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1238 = mux(_T_1178, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1239 = mux(_T_1180, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1240 = mux(_T_1182, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1241 = mux(_T_1184, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1242 = or(_T_1185, _T_1186) @[Mux.scala 27:72] + node _T_1243 = or(_T_1242, _T_1187) @[Mux.scala 27:72] + node _T_1244 = or(_T_1243, _T_1188) @[Mux.scala 27:72] + node _T_1245 = or(_T_1244, _T_1189) @[Mux.scala 27:72] + node _T_1246 = or(_T_1245, _T_1190) @[Mux.scala 27:72] + node _T_1247 = or(_T_1246, _T_1191) @[Mux.scala 27:72] + node _T_1248 = or(_T_1247, _T_1192) @[Mux.scala 27:72] + node _T_1249 = or(_T_1248, _T_1193) @[Mux.scala 27:72] + node _T_1250 = or(_T_1249, _T_1194) @[Mux.scala 27:72] node _T_1251 = or(_T_1250, _T_1195) @[Mux.scala 27:72] node _T_1252 = or(_T_1251, _T_1196) @[Mux.scala 27:72] node _T_1253 = or(_T_1252, _T_1197) @[Mux.scala 27:72] @@ -74681,245 +74681,245 @@ circuit quasar_wrapper : node _T_1295 = or(_T_1294, _T_1239) @[Mux.scala 27:72] node _T_1296 = or(_T_1295, _T_1240) @[Mux.scala 27:72] node _T_1297 = or(_T_1296, _T_1241) @[Mux.scala 27:72] - node _T_1298 = or(_T_1297, _T_1242) @[Mux.scala 27:72] - node _T_1299 = or(_T_1298, _T_1243) @[Mux.scala 27:72] - node _T_1300 = or(_T_1299, _T_1244) @[Mux.scala 27:72] - node _T_1301 = or(_T_1300, _T_1245) @[Mux.scala 27:72] - node _T_1302 = or(_T_1301, _T_1246) @[Mux.scala 27:72] - node _T_1303 = or(_T_1302, _T_1247) @[Mux.scala 27:72] - node _T_1304 = or(_T_1303, _T_1248) @[Mux.scala 27:72] - node _T_1305 = or(_T_1304, _T_1249) @[Mux.scala 27:72] - wire _T_1306 : UInt<1> @[Mux.scala 27:72] - _T_1306 <= _T_1305 @[Mux.scala 27:72] - node _T_1307 = and(_T_1025, _T_1306) @[dec_tlu_ctl.scala 2273:44] - mhpmc_inc_r[0] <= _T_1307 @[dec_tlu_ctl.scala 2273:19] - node _T_1308 = bits(mcountinhibit, 4, 4) @[dec_tlu_ctl.scala 2273:38] - node _T_1309 = not(_T_1308) @[dec_tlu_ctl.scala 2273:24] - node _T_1310 = eq(mhpme_vec[1], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] - node _T_1311 = bits(_T_1310, 0, 0) @[dec_tlu_ctl.scala 2274:62] - node _T_1312 = eq(mhpme_vec[1], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] - node _T_1313 = bits(_T_1312, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1314 = eq(mhpme_vec[1], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] - node _T_1315 = bits(_T_1314, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1316 = eq(mhpme_vec[1], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] - node _T_1317 = bits(_T_1316, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1318 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] - node _T_1319 = and(io.tlu_i0_commit_cmt, _T_1318) @[dec_tlu_ctl.scala 2277:94] - node _T_1320 = eq(mhpme_vec[1], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] - node _T_1321 = bits(_T_1320, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1322 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] - node _T_1323 = and(io.tlu_i0_commit_cmt, _T_1322) @[dec_tlu_ctl.scala 2278:94] - node _T_1324 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] - node _T_1325 = and(_T_1323, _T_1324) @[dec_tlu_ctl.scala 2278:115] - node _T_1326 = eq(mhpme_vec[1], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] - node _T_1327 = bits(_T_1326, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1328 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] - node _T_1329 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] - node _T_1330 = and(_T_1328, _T_1329) @[dec_tlu_ctl.scala 2279:115] - node _T_1331 = eq(mhpme_vec[1], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] - node _T_1332 = bits(_T_1331, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1333 = eq(mhpme_vec[1], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] - node _T_1334 = bits(_T_1333, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1335 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] - node _T_1336 = bits(_T_1335, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1337 = eq(mhpme_vec[1], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] - node _T_1338 = bits(_T_1337, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1339 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] - node _T_1340 = eq(mhpme_vec[1], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] - node _T_1341 = bits(_T_1340, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1342 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] - node _T_1343 = eq(mhpme_vec[1], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] - node _T_1344 = bits(_T_1343, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1345 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] - node _T_1346 = eq(mhpme_vec[1], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] - node _T_1347 = bits(_T_1346, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1348 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] - node _T_1349 = eq(mhpme_vec[1], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] - node _T_1350 = bits(_T_1349, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1351 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] - node _T_1352 = and(_T_1351, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] - node _T_1353 = eq(mhpme_vec[1], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] - node _T_1354 = bits(_T_1353, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1355 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] - node _T_1356 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] - node _T_1357 = and(_T_1355, _T_1356) @[dec_tlu_ctl.scala 2288:101] - node _T_1358 = eq(mhpme_vec[1], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] - node _T_1359 = bits(_T_1358, 0, 0) @[dec_tlu_ctl.scala 2289:59] - node _T_1360 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] - node _T_1361 = eq(mhpme_vec[1], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] - node _T_1362 = bits(_T_1361, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1363 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] - node _T_1364 = eq(mhpme_vec[1], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] - node _T_1365 = bits(_T_1364, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1366 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] - node _T_1367 = eq(mhpme_vec[1], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] - node _T_1368 = bits(_T_1367, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1369 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] - node _T_1370 = eq(mhpme_vec[1], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] - node _T_1371 = bits(_T_1370, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1372 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] - node _T_1373 = eq(mhpme_vec[1], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] - node _T_1374 = bits(_T_1373, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1375 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] - node _T_1376 = eq(mhpme_vec[1], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] - node _T_1377 = bits(_T_1376, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1378 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] - node _T_1379 = eq(mhpme_vec[1], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] - node _T_1380 = bits(_T_1379, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1381 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] - node _T_1382 = eq(mhpme_vec[1], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] - node _T_1383 = bits(_T_1382, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1384 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] - node _T_1385 = eq(mhpme_vec[1], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] - node _T_1386 = bits(_T_1385, 0, 0) @[dec_tlu_ctl.scala 2298:59] - node _T_1387 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] - node _T_1388 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] - node _T_1389 = or(_T_1387, _T_1388) @[dec_tlu_ctl.scala 2298:101] - node _T_1390 = eq(mhpme_vec[1], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] - node _T_1391 = bits(_T_1390, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1392 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] - node _T_1393 = eq(mhpme_vec[1], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] - node _T_1394 = bits(_T_1393, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1395 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] - node _T_1396 = eq(mhpme_vec[1], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] - node _T_1397 = bits(_T_1396, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1398 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] - node _T_1399 = eq(mhpme_vec[1], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] - node _T_1400 = bits(_T_1399, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1401 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] - node _T_1402 = bits(_T_1401, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1403 = eq(mhpme_vec[1], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] - node _T_1404 = bits(_T_1403, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1405 = eq(mhpme_vec[1], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] - node _T_1406 = bits(_T_1405, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1407 = eq(mhpme_vec[1], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] - node _T_1408 = bits(_T_1407, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1409 = eq(mhpme_vec[1], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] - node _T_1410 = bits(_T_1409, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1411 = eq(mhpme_vec[1], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] - node _T_1412 = bits(_T_1411, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1413 = eq(mhpme_vec[1], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] - node _T_1414 = bits(_T_1413, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1415 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] - node _T_1416 = or(_T_1415, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] - node _T_1417 = eq(mhpme_vec[1], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] - node _T_1418 = bits(_T_1417, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1419 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] - node _T_1420 = or(_T_1419, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] - node _T_1421 = eq(mhpme_vec[1], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] - node _T_1422 = bits(_T_1421, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1423 = eq(mhpme_vec[1], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] - node _T_1424 = bits(_T_1423, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1425 = eq(mhpme_vec[1], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] - node _T_1426 = bits(_T_1425, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1427 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] - node _T_1428 = and(_T_1427, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] - node _T_1429 = eq(mhpme_vec[1], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] - node _T_1430 = bits(_T_1429, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1431 = eq(mhpme_vec[1], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] - node _T_1432 = bits(_T_1431, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_1433 = eq(mhpme_vec[1], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] - node _T_1434 = bits(_T_1433, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_1435 = eq(mhpme_vec[1], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] - node _T_1436 = bits(_T_1435, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_1437 = eq(mhpme_vec[1], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] - node _T_1438 = bits(_T_1437, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_1439 = eq(mhpme_vec[1], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] - node _T_1440 = bits(_T_1439, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_1441 = eq(mhpme_vec[1], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] - node _T_1442 = bits(_T_1441, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_1443 = eq(mhpme_vec[1], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] - node _T_1444 = bits(_T_1443, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_1445 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] - node _T_1446 = bits(_T_1445, 0, 0) @[dec_tlu_ctl.scala 2321:84] - node _T_1447 = not(_T_1446) @[dec_tlu_ctl.scala 2321:73] - node _T_1448 = eq(mhpme_vec[1], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] - node _T_1449 = bits(_T_1448, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_1450 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] - node _T_1451 = bits(_T_1450, 0, 0) @[dec_tlu_ctl.scala 2322:84] - node _T_1452 = not(_T_1451) @[dec_tlu_ctl.scala 2322:73] - node _T_1453 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] - node _T_1454 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] - node _T_1455 = and(_T_1453, _T_1454) @[dec_tlu_ctl.scala 2322:113] - node _T_1456 = orr(_T_1455) @[dec_tlu_ctl.scala 2322:125] - node _T_1457 = and(_T_1452, _T_1456) @[dec_tlu_ctl.scala 2322:98] - node _T_1458 = eq(mhpme_vec[1], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] - node _T_1459 = bits(_T_1458, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_1460 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] - node _T_1461 = eq(mhpme_vec[1], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] - node _T_1462 = bits(_T_1461, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_1463 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] - node _T_1464 = eq(mhpme_vec[1], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] - node _T_1465 = bits(_T_1464, 0, 0) @[dec_tlu_ctl.scala 2325:62] - node _T_1466 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] - node _T_1467 = eq(mhpme_vec[1], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] - node _T_1468 = bits(_T_1467, 0, 0) @[dec_tlu_ctl.scala 2327:62] - node _T_1469 = eq(mhpme_vec[1], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] - node _T_1470 = bits(_T_1469, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_1471 = eq(mhpme_vec[1], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] - node _T_1472 = bits(_T_1471, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_1473 = eq(mhpme_vec[1], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] - node _T_1474 = bits(_T_1473, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_1475 = eq(mhpme_vec[1], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] - node _T_1476 = bits(_T_1475, 0, 0) @[dec_tlu_ctl.scala 2331:62] - node _T_1477 = mux(_T_1311, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1478 = mux(_T_1313, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1479 = mux(_T_1315, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1480 = mux(_T_1317, _T_1319, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1481 = mux(_T_1321, _T_1325, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1482 = mux(_T_1327, _T_1330, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1483 = mux(_T_1332, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1484 = mux(_T_1334, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1485 = mux(_T_1336, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1486 = mux(_T_1338, _T_1339, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1487 = mux(_T_1341, _T_1342, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1488 = mux(_T_1344, _T_1345, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1489 = mux(_T_1347, _T_1348, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1490 = mux(_T_1350, _T_1352, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1491 = mux(_T_1354, _T_1357, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1492 = mux(_T_1359, _T_1360, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1493 = mux(_T_1362, _T_1363, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1494 = mux(_T_1365, _T_1366, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1495 = mux(_T_1368, _T_1369, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1496 = mux(_T_1371, _T_1372, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1497 = mux(_T_1374, _T_1375, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1498 = mux(_T_1377, _T_1378, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1499 = mux(_T_1380, _T_1381, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1500 = mux(_T_1383, _T_1384, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1501 = mux(_T_1386, _T_1389, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1502 = mux(_T_1391, _T_1392, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1503 = mux(_T_1394, _T_1395, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1504 = mux(_T_1397, _T_1398, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1505 = mux(_T_1400, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1506 = mux(_T_1402, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1507 = mux(_T_1404, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1508 = mux(_T_1406, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1509 = mux(_T_1408, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1510 = mux(_T_1410, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1511 = mux(_T_1412, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1512 = mux(_T_1414, _T_1416, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1513 = mux(_T_1418, _T_1420, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1514 = mux(_T_1422, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1515 = mux(_T_1424, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1516 = mux(_T_1426, _T_1428, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1517 = mux(_T_1430, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1518 = mux(_T_1432, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1519 = mux(_T_1434, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1520 = mux(_T_1436, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1521 = mux(_T_1438, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1522 = mux(_T_1440, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1523 = mux(_T_1442, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1524 = mux(_T_1444, _T_1447, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1525 = mux(_T_1449, _T_1457, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1526 = mux(_T_1459, _T_1460, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1527 = mux(_T_1462, _T_1463, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1528 = mux(_T_1465, _T_1466, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1529 = mux(_T_1468, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1530 = mux(_T_1470, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1531 = mux(_T_1472, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1532 = mux(_T_1474, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1533 = mux(_T_1476, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1534 = or(_T_1477, _T_1478) @[Mux.scala 27:72] + wire _T_1298 : UInt<1> @[Mux.scala 27:72] + _T_1298 <= _T_1297 @[Mux.scala 27:72] + node _T_1299 = and(_T_1017, _T_1298) @[dec_tlu_ctl.scala 2273:44] + mhpmc_inc_r[0] <= _T_1299 @[dec_tlu_ctl.scala 2273:19] + node _T_1300 = bits(mcountinhibit, 4, 4) @[dec_tlu_ctl.scala 2273:38] + node _T_1301 = not(_T_1300) @[dec_tlu_ctl.scala 2273:24] + node _T_1302 = eq(mhpme_vec[1], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] + node _T_1303 = bits(_T_1302, 0, 0) @[dec_tlu_ctl.scala 2274:62] + node _T_1304 = eq(mhpme_vec[1], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] + node _T_1305 = bits(_T_1304, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1306 = eq(mhpme_vec[1], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] + node _T_1307 = bits(_T_1306, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1308 = eq(mhpme_vec[1], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] + node _T_1309 = bits(_T_1308, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1310 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] + node _T_1311 = and(io.tlu_i0_commit_cmt, _T_1310) @[dec_tlu_ctl.scala 2277:94] + node _T_1312 = eq(mhpme_vec[1], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] + node _T_1313 = bits(_T_1312, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1314 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] + node _T_1315 = and(io.tlu_i0_commit_cmt, _T_1314) @[dec_tlu_ctl.scala 2278:94] + node _T_1316 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] + node _T_1317 = and(_T_1315, _T_1316) @[dec_tlu_ctl.scala 2278:115] + node _T_1318 = eq(mhpme_vec[1], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] + node _T_1319 = bits(_T_1318, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1320 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] + node _T_1321 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] + node _T_1322 = and(_T_1320, _T_1321) @[dec_tlu_ctl.scala 2279:115] + node _T_1323 = eq(mhpme_vec[1], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] + node _T_1324 = bits(_T_1323, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1325 = eq(mhpme_vec[1], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] + node _T_1326 = bits(_T_1325, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1327 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] + node _T_1328 = bits(_T_1327, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1329 = eq(mhpme_vec[1], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] + node _T_1330 = bits(_T_1329, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1331 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] + node _T_1332 = eq(mhpme_vec[1], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] + node _T_1333 = bits(_T_1332, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1334 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] + node _T_1335 = eq(mhpme_vec[1], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] + node _T_1336 = bits(_T_1335, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1337 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] + node _T_1338 = eq(mhpme_vec[1], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] + node _T_1339 = bits(_T_1338, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1340 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] + node _T_1341 = eq(mhpme_vec[1], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] + node _T_1342 = bits(_T_1341, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1343 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] + node _T_1344 = and(_T_1343, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] + node _T_1345 = eq(mhpme_vec[1], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] + node _T_1346 = bits(_T_1345, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1347 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] + node _T_1348 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] + node _T_1349 = and(_T_1347, _T_1348) @[dec_tlu_ctl.scala 2288:101] + node _T_1350 = eq(mhpme_vec[1], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] + node _T_1351 = bits(_T_1350, 0, 0) @[dec_tlu_ctl.scala 2289:59] + node _T_1352 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] + node _T_1353 = eq(mhpme_vec[1], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] + node _T_1354 = bits(_T_1353, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1355 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] + node _T_1356 = eq(mhpme_vec[1], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] + node _T_1357 = bits(_T_1356, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1358 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] + node _T_1359 = eq(mhpme_vec[1], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] + node _T_1360 = bits(_T_1359, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1361 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] + node _T_1362 = eq(mhpme_vec[1], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] + node _T_1363 = bits(_T_1362, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1364 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] + node _T_1365 = eq(mhpme_vec[1], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] + node _T_1366 = bits(_T_1365, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1367 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] + node _T_1368 = eq(mhpme_vec[1], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] + node _T_1369 = bits(_T_1368, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1370 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] + node _T_1371 = eq(mhpme_vec[1], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] + node _T_1372 = bits(_T_1371, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1373 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] + node _T_1374 = eq(mhpme_vec[1], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] + node _T_1375 = bits(_T_1374, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1376 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] + node _T_1377 = eq(mhpme_vec[1], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] + node _T_1378 = bits(_T_1377, 0, 0) @[dec_tlu_ctl.scala 2298:59] + node _T_1379 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] + node _T_1380 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] + node _T_1381 = or(_T_1379, _T_1380) @[dec_tlu_ctl.scala 2298:101] + node _T_1382 = eq(mhpme_vec[1], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] + node _T_1383 = bits(_T_1382, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1384 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] + node _T_1385 = eq(mhpme_vec[1], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] + node _T_1386 = bits(_T_1385, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1387 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] + node _T_1388 = eq(mhpme_vec[1], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] + node _T_1389 = bits(_T_1388, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1390 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] + node _T_1391 = eq(mhpme_vec[1], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] + node _T_1392 = bits(_T_1391, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1393 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] + node _T_1394 = bits(_T_1393, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1395 = eq(mhpme_vec[1], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] + node _T_1396 = bits(_T_1395, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1397 = eq(mhpme_vec[1], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] + node _T_1398 = bits(_T_1397, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1399 = eq(mhpme_vec[1], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] + node _T_1400 = bits(_T_1399, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1401 = eq(mhpme_vec[1], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] + node _T_1402 = bits(_T_1401, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1403 = eq(mhpme_vec[1], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] + node _T_1404 = bits(_T_1403, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1405 = eq(mhpme_vec[1], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] + node _T_1406 = bits(_T_1405, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1407 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] + node _T_1408 = or(_T_1407, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] + node _T_1409 = eq(mhpme_vec[1], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] + node _T_1410 = bits(_T_1409, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1411 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] + node _T_1412 = or(_T_1411, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] + node _T_1413 = eq(mhpme_vec[1], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] + node _T_1414 = bits(_T_1413, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1415 = eq(mhpme_vec[1], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] + node _T_1416 = bits(_T_1415, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1417 = eq(mhpme_vec[1], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] + node _T_1418 = bits(_T_1417, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1419 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] + node _T_1420 = and(_T_1419, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] + node _T_1421 = eq(mhpme_vec[1], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] + node _T_1422 = bits(_T_1421, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_1423 = eq(mhpme_vec[1], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] + node _T_1424 = bits(_T_1423, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_1425 = eq(mhpme_vec[1], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] + node _T_1426 = bits(_T_1425, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_1427 = eq(mhpme_vec[1], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] + node _T_1428 = bits(_T_1427, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_1429 = eq(mhpme_vec[1], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] + node _T_1430 = bits(_T_1429, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_1431 = eq(mhpme_vec[1], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] + node _T_1432 = bits(_T_1431, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_1433 = eq(mhpme_vec[1], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] + node _T_1434 = bits(_T_1433, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_1435 = eq(mhpme_vec[1], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] + node _T_1436 = bits(_T_1435, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_1437 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] + node _T_1438 = bits(_T_1437, 0, 0) @[dec_tlu_ctl.scala 2321:84] + node _T_1439 = not(_T_1438) @[dec_tlu_ctl.scala 2321:73] + node _T_1440 = eq(mhpme_vec[1], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] + node _T_1441 = bits(_T_1440, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_1442 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] + node _T_1443 = bits(_T_1442, 0, 0) @[dec_tlu_ctl.scala 2322:84] + node _T_1444 = not(_T_1443) @[dec_tlu_ctl.scala 2322:73] + node _T_1445 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] + node _T_1446 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] + node _T_1447 = and(_T_1445, _T_1446) @[dec_tlu_ctl.scala 2322:113] + node _T_1448 = orr(_T_1447) @[dec_tlu_ctl.scala 2322:125] + node _T_1449 = and(_T_1444, _T_1448) @[dec_tlu_ctl.scala 2322:98] + node _T_1450 = eq(mhpme_vec[1], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] + node _T_1451 = bits(_T_1450, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_1452 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] + node _T_1453 = eq(mhpme_vec[1], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] + node _T_1454 = bits(_T_1453, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_1455 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] + node _T_1456 = eq(mhpme_vec[1], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] + node _T_1457 = bits(_T_1456, 0, 0) @[dec_tlu_ctl.scala 2325:62] + node _T_1458 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] + node _T_1459 = eq(mhpme_vec[1], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] + node _T_1460 = bits(_T_1459, 0, 0) @[dec_tlu_ctl.scala 2327:62] + node _T_1461 = eq(mhpme_vec[1], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] + node _T_1462 = bits(_T_1461, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_1463 = eq(mhpme_vec[1], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] + node _T_1464 = bits(_T_1463, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_1465 = eq(mhpme_vec[1], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] + node _T_1466 = bits(_T_1465, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_1467 = eq(mhpme_vec[1], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] + node _T_1468 = bits(_T_1467, 0, 0) @[dec_tlu_ctl.scala 2331:62] + node _T_1469 = mux(_T_1303, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1470 = mux(_T_1305, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1471 = mux(_T_1307, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1472 = mux(_T_1309, _T_1311, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1473 = mux(_T_1313, _T_1317, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1474 = mux(_T_1319, _T_1322, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1475 = mux(_T_1324, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1476 = mux(_T_1326, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1477 = mux(_T_1328, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1478 = mux(_T_1330, _T_1331, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1479 = mux(_T_1333, _T_1334, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1480 = mux(_T_1336, _T_1337, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1481 = mux(_T_1339, _T_1340, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1482 = mux(_T_1342, _T_1344, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1483 = mux(_T_1346, _T_1349, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1484 = mux(_T_1351, _T_1352, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1485 = mux(_T_1354, _T_1355, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1486 = mux(_T_1357, _T_1358, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1487 = mux(_T_1360, _T_1361, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1488 = mux(_T_1363, _T_1364, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1489 = mux(_T_1366, _T_1367, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1490 = mux(_T_1369, _T_1370, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1491 = mux(_T_1372, _T_1373, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1492 = mux(_T_1375, _T_1376, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1493 = mux(_T_1378, _T_1381, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1494 = mux(_T_1383, _T_1384, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1495 = mux(_T_1386, _T_1387, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1496 = mux(_T_1389, _T_1390, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1497 = mux(_T_1392, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1498 = mux(_T_1394, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1499 = mux(_T_1396, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1500 = mux(_T_1398, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1501 = mux(_T_1400, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1502 = mux(_T_1402, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1503 = mux(_T_1404, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1504 = mux(_T_1406, _T_1408, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1505 = mux(_T_1410, _T_1412, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1506 = mux(_T_1414, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1507 = mux(_T_1416, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1508 = mux(_T_1418, _T_1420, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1509 = mux(_T_1422, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1510 = mux(_T_1424, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1511 = mux(_T_1426, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1512 = mux(_T_1428, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1513 = mux(_T_1430, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1514 = mux(_T_1432, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1515 = mux(_T_1434, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1516 = mux(_T_1436, _T_1439, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1517 = mux(_T_1441, _T_1449, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1518 = mux(_T_1451, _T_1452, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1519 = mux(_T_1454, _T_1455, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1520 = mux(_T_1457, _T_1458, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1521 = mux(_T_1460, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1522 = mux(_T_1462, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1523 = mux(_T_1464, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1524 = mux(_T_1466, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1525 = mux(_T_1468, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1526 = or(_T_1469, _T_1470) @[Mux.scala 27:72] + node _T_1527 = or(_T_1526, _T_1471) @[Mux.scala 27:72] + node _T_1528 = or(_T_1527, _T_1472) @[Mux.scala 27:72] + node _T_1529 = or(_T_1528, _T_1473) @[Mux.scala 27:72] + node _T_1530 = or(_T_1529, _T_1474) @[Mux.scala 27:72] + node _T_1531 = or(_T_1530, _T_1475) @[Mux.scala 27:72] + node _T_1532 = or(_T_1531, _T_1476) @[Mux.scala 27:72] + node _T_1533 = or(_T_1532, _T_1477) @[Mux.scala 27:72] + node _T_1534 = or(_T_1533, _T_1478) @[Mux.scala 27:72] node _T_1535 = or(_T_1534, _T_1479) @[Mux.scala 27:72] node _T_1536 = or(_T_1535, _T_1480) @[Mux.scala 27:72] node _T_1537 = or(_T_1536, _T_1481) @[Mux.scala 27:72] @@ -74967,245 +74967,245 @@ circuit quasar_wrapper : node _T_1579 = or(_T_1578, _T_1523) @[Mux.scala 27:72] node _T_1580 = or(_T_1579, _T_1524) @[Mux.scala 27:72] node _T_1581 = or(_T_1580, _T_1525) @[Mux.scala 27:72] - node _T_1582 = or(_T_1581, _T_1526) @[Mux.scala 27:72] - node _T_1583 = or(_T_1582, _T_1527) @[Mux.scala 27:72] - node _T_1584 = or(_T_1583, _T_1528) @[Mux.scala 27:72] - node _T_1585 = or(_T_1584, _T_1529) @[Mux.scala 27:72] - node _T_1586 = or(_T_1585, _T_1530) @[Mux.scala 27:72] - node _T_1587 = or(_T_1586, _T_1531) @[Mux.scala 27:72] - node _T_1588 = or(_T_1587, _T_1532) @[Mux.scala 27:72] - node _T_1589 = or(_T_1588, _T_1533) @[Mux.scala 27:72] - wire _T_1590 : UInt<1> @[Mux.scala 27:72] - _T_1590 <= _T_1589 @[Mux.scala 27:72] - node _T_1591 = and(_T_1309, _T_1590) @[dec_tlu_ctl.scala 2273:44] - mhpmc_inc_r[1] <= _T_1591 @[dec_tlu_ctl.scala 2273:19] - node _T_1592 = bits(mcountinhibit, 5, 5) @[dec_tlu_ctl.scala 2273:38] - node _T_1593 = not(_T_1592) @[dec_tlu_ctl.scala 2273:24] - node _T_1594 = eq(mhpme_vec[2], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] - node _T_1595 = bits(_T_1594, 0, 0) @[dec_tlu_ctl.scala 2274:62] - node _T_1596 = eq(mhpme_vec[2], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] - node _T_1597 = bits(_T_1596, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1598 = eq(mhpme_vec[2], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] - node _T_1599 = bits(_T_1598, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1600 = eq(mhpme_vec[2], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] - node _T_1601 = bits(_T_1600, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1602 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] - node _T_1603 = and(io.tlu_i0_commit_cmt, _T_1602) @[dec_tlu_ctl.scala 2277:94] - node _T_1604 = eq(mhpme_vec[2], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] - node _T_1605 = bits(_T_1604, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1606 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] - node _T_1607 = and(io.tlu_i0_commit_cmt, _T_1606) @[dec_tlu_ctl.scala 2278:94] - node _T_1608 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] - node _T_1609 = and(_T_1607, _T_1608) @[dec_tlu_ctl.scala 2278:115] - node _T_1610 = eq(mhpme_vec[2], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] - node _T_1611 = bits(_T_1610, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1612 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] - node _T_1613 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] - node _T_1614 = and(_T_1612, _T_1613) @[dec_tlu_ctl.scala 2279:115] - node _T_1615 = eq(mhpme_vec[2], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] - node _T_1616 = bits(_T_1615, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1617 = eq(mhpme_vec[2], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] - node _T_1618 = bits(_T_1617, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1619 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] - node _T_1620 = bits(_T_1619, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1621 = eq(mhpme_vec[2], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] - node _T_1622 = bits(_T_1621, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1623 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] - node _T_1624 = eq(mhpme_vec[2], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] - node _T_1625 = bits(_T_1624, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1626 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] - node _T_1627 = eq(mhpme_vec[2], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] - node _T_1628 = bits(_T_1627, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1629 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] - node _T_1630 = eq(mhpme_vec[2], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] - node _T_1631 = bits(_T_1630, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1632 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] - node _T_1633 = eq(mhpme_vec[2], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] - node _T_1634 = bits(_T_1633, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1635 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] - node _T_1636 = and(_T_1635, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] - node _T_1637 = eq(mhpme_vec[2], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] - node _T_1638 = bits(_T_1637, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1639 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] - node _T_1640 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] - node _T_1641 = and(_T_1639, _T_1640) @[dec_tlu_ctl.scala 2288:101] - node _T_1642 = eq(mhpme_vec[2], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] - node _T_1643 = bits(_T_1642, 0, 0) @[dec_tlu_ctl.scala 2289:59] - node _T_1644 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] - node _T_1645 = eq(mhpme_vec[2], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] - node _T_1646 = bits(_T_1645, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1647 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] - node _T_1648 = eq(mhpme_vec[2], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] - node _T_1649 = bits(_T_1648, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1650 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] - node _T_1651 = eq(mhpme_vec[2], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] - node _T_1652 = bits(_T_1651, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1653 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] - node _T_1654 = eq(mhpme_vec[2], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] - node _T_1655 = bits(_T_1654, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1656 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] - node _T_1657 = eq(mhpme_vec[2], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] - node _T_1658 = bits(_T_1657, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1659 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] - node _T_1660 = eq(mhpme_vec[2], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] - node _T_1661 = bits(_T_1660, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1662 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] - node _T_1663 = eq(mhpme_vec[2], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] - node _T_1664 = bits(_T_1663, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1665 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] - node _T_1666 = eq(mhpme_vec[2], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] - node _T_1667 = bits(_T_1666, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1668 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] - node _T_1669 = eq(mhpme_vec[2], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] - node _T_1670 = bits(_T_1669, 0, 0) @[dec_tlu_ctl.scala 2298:59] - node _T_1671 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] - node _T_1672 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] - node _T_1673 = or(_T_1671, _T_1672) @[dec_tlu_ctl.scala 2298:101] - node _T_1674 = eq(mhpme_vec[2], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] - node _T_1675 = bits(_T_1674, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1676 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] - node _T_1677 = eq(mhpme_vec[2], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] - node _T_1678 = bits(_T_1677, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1679 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] - node _T_1680 = eq(mhpme_vec[2], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] - node _T_1681 = bits(_T_1680, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1682 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] - node _T_1683 = eq(mhpme_vec[2], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] - node _T_1684 = bits(_T_1683, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1685 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] - node _T_1686 = bits(_T_1685, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1687 = eq(mhpme_vec[2], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] - node _T_1688 = bits(_T_1687, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1689 = eq(mhpme_vec[2], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] - node _T_1690 = bits(_T_1689, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1691 = eq(mhpme_vec[2], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] - node _T_1692 = bits(_T_1691, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1693 = eq(mhpme_vec[2], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] - node _T_1694 = bits(_T_1693, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1695 = eq(mhpme_vec[2], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] - node _T_1696 = bits(_T_1695, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1697 = eq(mhpme_vec[2], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] - node _T_1698 = bits(_T_1697, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1699 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] - node _T_1700 = or(_T_1699, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] - node _T_1701 = eq(mhpme_vec[2], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] - node _T_1702 = bits(_T_1701, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1703 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] - node _T_1704 = or(_T_1703, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] - node _T_1705 = eq(mhpme_vec[2], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] - node _T_1706 = bits(_T_1705, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1707 = eq(mhpme_vec[2], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] - node _T_1708 = bits(_T_1707, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1709 = eq(mhpme_vec[2], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] - node _T_1710 = bits(_T_1709, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1711 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] - node _T_1712 = and(_T_1711, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] - node _T_1713 = eq(mhpme_vec[2], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] - node _T_1714 = bits(_T_1713, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1715 = eq(mhpme_vec[2], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] - node _T_1716 = bits(_T_1715, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_1717 = eq(mhpme_vec[2], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] - node _T_1718 = bits(_T_1717, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_1719 = eq(mhpme_vec[2], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] - node _T_1720 = bits(_T_1719, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_1721 = eq(mhpme_vec[2], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] - node _T_1722 = bits(_T_1721, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_1723 = eq(mhpme_vec[2], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] - node _T_1724 = bits(_T_1723, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_1725 = eq(mhpme_vec[2], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] - node _T_1726 = bits(_T_1725, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_1727 = eq(mhpme_vec[2], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] - node _T_1728 = bits(_T_1727, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_1729 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] - node _T_1730 = bits(_T_1729, 0, 0) @[dec_tlu_ctl.scala 2321:84] - node _T_1731 = not(_T_1730) @[dec_tlu_ctl.scala 2321:73] - node _T_1732 = eq(mhpme_vec[2], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] - node _T_1733 = bits(_T_1732, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_1734 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] - node _T_1735 = bits(_T_1734, 0, 0) @[dec_tlu_ctl.scala 2322:84] - node _T_1736 = not(_T_1735) @[dec_tlu_ctl.scala 2322:73] - node _T_1737 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] - node _T_1738 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] - node _T_1739 = and(_T_1737, _T_1738) @[dec_tlu_ctl.scala 2322:113] - node _T_1740 = orr(_T_1739) @[dec_tlu_ctl.scala 2322:125] - node _T_1741 = and(_T_1736, _T_1740) @[dec_tlu_ctl.scala 2322:98] - node _T_1742 = eq(mhpme_vec[2], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] - node _T_1743 = bits(_T_1742, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_1744 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] - node _T_1745 = eq(mhpme_vec[2], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] - node _T_1746 = bits(_T_1745, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_1747 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] - node _T_1748 = eq(mhpme_vec[2], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] - node _T_1749 = bits(_T_1748, 0, 0) @[dec_tlu_ctl.scala 2325:62] - node _T_1750 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] - node _T_1751 = eq(mhpme_vec[2], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] - node _T_1752 = bits(_T_1751, 0, 0) @[dec_tlu_ctl.scala 2327:62] - node _T_1753 = eq(mhpme_vec[2], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] - node _T_1754 = bits(_T_1753, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_1755 = eq(mhpme_vec[2], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] - node _T_1756 = bits(_T_1755, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_1757 = eq(mhpme_vec[2], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] - node _T_1758 = bits(_T_1757, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_1759 = eq(mhpme_vec[2], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] - node _T_1760 = bits(_T_1759, 0, 0) @[dec_tlu_ctl.scala 2331:62] - node _T_1761 = mux(_T_1595, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1762 = mux(_T_1597, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1763 = mux(_T_1599, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1764 = mux(_T_1601, _T_1603, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1765 = mux(_T_1605, _T_1609, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1766 = mux(_T_1611, _T_1614, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1767 = mux(_T_1616, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1768 = mux(_T_1618, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1769 = mux(_T_1620, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1770 = mux(_T_1622, _T_1623, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1771 = mux(_T_1625, _T_1626, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1772 = mux(_T_1628, _T_1629, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1773 = mux(_T_1631, _T_1632, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1774 = mux(_T_1634, _T_1636, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1775 = mux(_T_1638, _T_1641, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1776 = mux(_T_1643, _T_1644, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1777 = mux(_T_1646, _T_1647, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1778 = mux(_T_1649, _T_1650, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1779 = mux(_T_1652, _T_1653, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1780 = mux(_T_1655, _T_1656, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1781 = mux(_T_1658, _T_1659, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1782 = mux(_T_1661, _T_1662, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1783 = mux(_T_1664, _T_1665, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1784 = mux(_T_1667, _T_1668, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1785 = mux(_T_1670, _T_1673, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1786 = mux(_T_1675, _T_1676, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1787 = mux(_T_1678, _T_1679, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1788 = mux(_T_1681, _T_1682, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1789 = mux(_T_1684, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1790 = mux(_T_1686, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1791 = mux(_T_1688, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1792 = mux(_T_1690, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1793 = mux(_T_1692, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1794 = mux(_T_1694, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1795 = mux(_T_1696, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1796 = mux(_T_1698, _T_1700, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1797 = mux(_T_1702, _T_1704, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1798 = mux(_T_1706, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1799 = mux(_T_1708, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1800 = mux(_T_1710, _T_1712, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1801 = mux(_T_1714, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1802 = mux(_T_1716, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1803 = mux(_T_1718, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1804 = mux(_T_1720, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1805 = mux(_T_1722, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1806 = mux(_T_1724, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1807 = mux(_T_1726, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1808 = mux(_T_1728, _T_1731, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1809 = mux(_T_1733, _T_1741, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1810 = mux(_T_1743, _T_1744, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1811 = mux(_T_1746, _T_1747, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1812 = mux(_T_1749, _T_1750, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1813 = mux(_T_1752, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1814 = mux(_T_1754, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1815 = mux(_T_1756, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1816 = mux(_T_1758, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1817 = mux(_T_1760, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1818 = or(_T_1761, _T_1762) @[Mux.scala 27:72] + wire _T_1582 : UInt<1> @[Mux.scala 27:72] + _T_1582 <= _T_1581 @[Mux.scala 27:72] + node _T_1583 = and(_T_1301, _T_1582) @[dec_tlu_ctl.scala 2273:44] + mhpmc_inc_r[1] <= _T_1583 @[dec_tlu_ctl.scala 2273:19] + node _T_1584 = bits(mcountinhibit, 5, 5) @[dec_tlu_ctl.scala 2273:38] + node _T_1585 = not(_T_1584) @[dec_tlu_ctl.scala 2273:24] + node _T_1586 = eq(mhpme_vec[2], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] + node _T_1587 = bits(_T_1586, 0, 0) @[dec_tlu_ctl.scala 2274:62] + node _T_1588 = eq(mhpme_vec[2], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] + node _T_1589 = bits(_T_1588, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1590 = eq(mhpme_vec[2], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] + node _T_1591 = bits(_T_1590, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1592 = eq(mhpme_vec[2], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] + node _T_1593 = bits(_T_1592, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1594 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] + node _T_1595 = and(io.tlu_i0_commit_cmt, _T_1594) @[dec_tlu_ctl.scala 2277:94] + node _T_1596 = eq(mhpme_vec[2], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] + node _T_1597 = bits(_T_1596, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1598 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] + node _T_1599 = and(io.tlu_i0_commit_cmt, _T_1598) @[dec_tlu_ctl.scala 2278:94] + node _T_1600 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] + node _T_1601 = and(_T_1599, _T_1600) @[dec_tlu_ctl.scala 2278:115] + node _T_1602 = eq(mhpme_vec[2], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] + node _T_1603 = bits(_T_1602, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1604 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] + node _T_1605 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] + node _T_1606 = and(_T_1604, _T_1605) @[dec_tlu_ctl.scala 2279:115] + node _T_1607 = eq(mhpme_vec[2], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] + node _T_1608 = bits(_T_1607, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1609 = eq(mhpme_vec[2], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] + node _T_1610 = bits(_T_1609, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1611 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] + node _T_1612 = bits(_T_1611, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1613 = eq(mhpme_vec[2], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] + node _T_1614 = bits(_T_1613, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1615 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] + node _T_1616 = eq(mhpme_vec[2], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] + node _T_1617 = bits(_T_1616, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1618 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] + node _T_1619 = eq(mhpme_vec[2], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] + node _T_1620 = bits(_T_1619, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1621 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] + node _T_1622 = eq(mhpme_vec[2], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] + node _T_1623 = bits(_T_1622, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1624 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] + node _T_1625 = eq(mhpme_vec[2], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] + node _T_1626 = bits(_T_1625, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1627 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] + node _T_1628 = and(_T_1627, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] + node _T_1629 = eq(mhpme_vec[2], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] + node _T_1630 = bits(_T_1629, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1631 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] + node _T_1632 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] + node _T_1633 = and(_T_1631, _T_1632) @[dec_tlu_ctl.scala 2288:101] + node _T_1634 = eq(mhpme_vec[2], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] + node _T_1635 = bits(_T_1634, 0, 0) @[dec_tlu_ctl.scala 2289:59] + node _T_1636 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] + node _T_1637 = eq(mhpme_vec[2], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] + node _T_1638 = bits(_T_1637, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1639 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] + node _T_1640 = eq(mhpme_vec[2], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] + node _T_1641 = bits(_T_1640, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1642 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] + node _T_1643 = eq(mhpme_vec[2], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] + node _T_1644 = bits(_T_1643, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1645 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] + node _T_1646 = eq(mhpme_vec[2], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] + node _T_1647 = bits(_T_1646, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1648 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] + node _T_1649 = eq(mhpme_vec[2], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] + node _T_1650 = bits(_T_1649, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1651 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] + node _T_1652 = eq(mhpme_vec[2], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] + node _T_1653 = bits(_T_1652, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1654 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] + node _T_1655 = eq(mhpme_vec[2], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] + node _T_1656 = bits(_T_1655, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1657 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] + node _T_1658 = eq(mhpme_vec[2], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] + node _T_1659 = bits(_T_1658, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1660 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] + node _T_1661 = eq(mhpme_vec[2], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] + node _T_1662 = bits(_T_1661, 0, 0) @[dec_tlu_ctl.scala 2298:59] + node _T_1663 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] + node _T_1664 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] + node _T_1665 = or(_T_1663, _T_1664) @[dec_tlu_ctl.scala 2298:101] + node _T_1666 = eq(mhpme_vec[2], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] + node _T_1667 = bits(_T_1666, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1668 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] + node _T_1669 = eq(mhpme_vec[2], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] + node _T_1670 = bits(_T_1669, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1671 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] + node _T_1672 = eq(mhpme_vec[2], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] + node _T_1673 = bits(_T_1672, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1674 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] + node _T_1675 = eq(mhpme_vec[2], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] + node _T_1676 = bits(_T_1675, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1677 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] + node _T_1678 = bits(_T_1677, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1679 = eq(mhpme_vec[2], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] + node _T_1680 = bits(_T_1679, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1681 = eq(mhpme_vec[2], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] + node _T_1682 = bits(_T_1681, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1683 = eq(mhpme_vec[2], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] + node _T_1684 = bits(_T_1683, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1685 = eq(mhpme_vec[2], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] + node _T_1686 = bits(_T_1685, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1687 = eq(mhpme_vec[2], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] + node _T_1688 = bits(_T_1687, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1689 = eq(mhpme_vec[2], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] + node _T_1690 = bits(_T_1689, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1691 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] + node _T_1692 = or(_T_1691, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] + node _T_1693 = eq(mhpme_vec[2], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] + node _T_1694 = bits(_T_1693, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1695 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] + node _T_1696 = or(_T_1695, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] + node _T_1697 = eq(mhpme_vec[2], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] + node _T_1698 = bits(_T_1697, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1699 = eq(mhpme_vec[2], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] + node _T_1700 = bits(_T_1699, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1701 = eq(mhpme_vec[2], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] + node _T_1702 = bits(_T_1701, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1703 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] + node _T_1704 = and(_T_1703, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] + node _T_1705 = eq(mhpme_vec[2], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] + node _T_1706 = bits(_T_1705, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_1707 = eq(mhpme_vec[2], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] + node _T_1708 = bits(_T_1707, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_1709 = eq(mhpme_vec[2], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] + node _T_1710 = bits(_T_1709, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_1711 = eq(mhpme_vec[2], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] + node _T_1712 = bits(_T_1711, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_1713 = eq(mhpme_vec[2], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] + node _T_1714 = bits(_T_1713, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_1715 = eq(mhpme_vec[2], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] + node _T_1716 = bits(_T_1715, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_1717 = eq(mhpme_vec[2], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] + node _T_1718 = bits(_T_1717, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_1719 = eq(mhpme_vec[2], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] + node _T_1720 = bits(_T_1719, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_1721 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] + node _T_1722 = bits(_T_1721, 0, 0) @[dec_tlu_ctl.scala 2321:84] + node _T_1723 = not(_T_1722) @[dec_tlu_ctl.scala 2321:73] + node _T_1724 = eq(mhpme_vec[2], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] + node _T_1725 = bits(_T_1724, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_1726 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] + node _T_1727 = bits(_T_1726, 0, 0) @[dec_tlu_ctl.scala 2322:84] + node _T_1728 = not(_T_1727) @[dec_tlu_ctl.scala 2322:73] + node _T_1729 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] + node _T_1730 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] + node _T_1731 = and(_T_1729, _T_1730) @[dec_tlu_ctl.scala 2322:113] + node _T_1732 = orr(_T_1731) @[dec_tlu_ctl.scala 2322:125] + node _T_1733 = and(_T_1728, _T_1732) @[dec_tlu_ctl.scala 2322:98] + node _T_1734 = eq(mhpme_vec[2], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] + node _T_1735 = bits(_T_1734, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_1736 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] + node _T_1737 = eq(mhpme_vec[2], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] + node _T_1738 = bits(_T_1737, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_1739 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] + node _T_1740 = eq(mhpme_vec[2], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] + node _T_1741 = bits(_T_1740, 0, 0) @[dec_tlu_ctl.scala 2325:62] + node _T_1742 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] + node _T_1743 = eq(mhpme_vec[2], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] + node _T_1744 = bits(_T_1743, 0, 0) @[dec_tlu_ctl.scala 2327:62] + node _T_1745 = eq(mhpme_vec[2], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] + node _T_1746 = bits(_T_1745, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_1747 = eq(mhpme_vec[2], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] + node _T_1748 = bits(_T_1747, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_1749 = eq(mhpme_vec[2], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] + node _T_1750 = bits(_T_1749, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_1751 = eq(mhpme_vec[2], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] + node _T_1752 = bits(_T_1751, 0, 0) @[dec_tlu_ctl.scala 2331:62] + node _T_1753 = mux(_T_1587, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1754 = mux(_T_1589, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1755 = mux(_T_1591, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1756 = mux(_T_1593, _T_1595, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1757 = mux(_T_1597, _T_1601, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1758 = mux(_T_1603, _T_1606, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1759 = mux(_T_1608, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1760 = mux(_T_1610, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1761 = mux(_T_1612, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1762 = mux(_T_1614, _T_1615, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1763 = mux(_T_1617, _T_1618, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1764 = mux(_T_1620, _T_1621, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1765 = mux(_T_1623, _T_1624, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1766 = mux(_T_1626, _T_1628, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1767 = mux(_T_1630, _T_1633, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1768 = mux(_T_1635, _T_1636, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1769 = mux(_T_1638, _T_1639, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1770 = mux(_T_1641, _T_1642, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1771 = mux(_T_1644, _T_1645, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1772 = mux(_T_1647, _T_1648, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1773 = mux(_T_1650, _T_1651, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1774 = mux(_T_1653, _T_1654, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1775 = mux(_T_1656, _T_1657, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1776 = mux(_T_1659, _T_1660, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1777 = mux(_T_1662, _T_1665, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1778 = mux(_T_1667, _T_1668, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1779 = mux(_T_1670, _T_1671, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1780 = mux(_T_1673, _T_1674, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1781 = mux(_T_1676, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1782 = mux(_T_1678, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1783 = mux(_T_1680, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1784 = mux(_T_1682, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1785 = mux(_T_1684, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1786 = mux(_T_1686, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1787 = mux(_T_1688, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1788 = mux(_T_1690, _T_1692, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1789 = mux(_T_1694, _T_1696, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1790 = mux(_T_1698, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1791 = mux(_T_1700, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1792 = mux(_T_1702, _T_1704, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1793 = mux(_T_1706, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1794 = mux(_T_1708, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1795 = mux(_T_1710, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1796 = mux(_T_1712, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1797 = mux(_T_1714, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1798 = mux(_T_1716, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1799 = mux(_T_1718, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1800 = mux(_T_1720, _T_1723, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1801 = mux(_T_1725, _T_1733, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1802 = mux(_T_1735, _T_1736, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1803 = mux(_T_1738, _T_1739, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1804 = mux(_T_1741, _T_1742, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1805 = mux(_T_1744, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1806 = mux(_T_1746, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1807 = mux(_T_1748, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1808 = mux(_T_1750, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1809 = mux(_T_1752, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1810 = or(_T_1753, _T_1754) @[Mux.scala 27:72] + node _T_1811 = or(_T_1810, _T_1755) @[Mux.scala 27:72] + node _T_1812 = or(_T_1811, _T_1756) @[Mux.scala 27:72] + node _T_1813 = or(_T_1812, _T_1757) @[Mux.scala 27:72] + node _T_1814 = or(_T_1813, _T_1758) @[Mux.scala 27:72] + node _T_1815 = or(_T_1814, _T_1759) @[Mux.scala 27:72] + node _T_1816 = or(_T_1815, _T_1760) @[Mux.scala 27:72] + node _T_1817 = or(_T_1816, _T_1761) @[Mux.scala 27:72] + node _T_1818 = or(_T_1817, _T_1762) @[Mux.scala 27:72] node _T_1819 = or(_T_1818, _T_1763) @[Mux.scala 27:72] node _T_1820 = or(_T_1819, _T_1764) @[Mux.scala 27:72] node _T_1821 = or(_T_1820, _T_1765) @[Mux.scala 27:72] @@ -75253,245 +75253,245 @@ circuit quasar_wrapper : node _T_1863 = or(_T_1862, _T_1807) @[Mux.scala 27:72] node _T_1864 = or(_T_1863, _T_1808) @[Mux.scala 27:72] node _T_1865 = or(_T_1864, _T_1809) @[Mux.scala 27:72] - node _T_1866 = or(_T_1865, _T_1810) @[Mux.scala 27:72] - node _T_1867 = or(_T_1866, _T_1811) @[Mux.scala 27:72] - node _T_1868 = or(_T_1867, _T_1812) @[Mux.scala 27:72] - node _T_1869 = or(_T_1868, _T_1813) @[Mux.scala 27:72] - node _T_1870 = or(_T_1869, _T_1814) @[Mux.scala 27:72] - node _T_1871 = or(_T_1870, _T_1815) @[Mux.scala 27:72] - node _T_1872 = or(_T_1871, _T_1816) @[Mux.scala 27:72] - node _T_1873 = or(_T_1872, _T_1817) @[Mux.scala 27:72] - wire _T_1874 : UInt<1> @[Mux.scala 27:72] - _T_1874 <= _T_1873 @[Mux.scala 27:72] - node _T_1875 = and(_T_1593, _T_1874) @[dec_tlu_ctl.scala 2273:44] - mhpmc_inc_r[2] <= _T_1875 @[dec_tlu_ctl.scala 2273:19] - node _T_1876 = bits(mcountinhibit, 6, 6) @[dec_tlu_ctl.scala 2273:38] - node _T_1877 = not(_T_1876) @[dec_tlu_ctl.scala 2273:24] - node _T_1878 = eq(mhpme_vec[3], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] - node _T_1879 = bits(_T_1878, 0, 0) @[dec_tlu_ctl.scala 2274:62] - node _T_1880 = eq(mhpme_vec[3], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] - node _T_1881 = bits(_T_1880, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1882 = eq(mhpme_vec[3], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] - node _T_1883 = bits(_T_1882, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1884 = eq(mhpme_vec[3], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] - node _T_1885 = bits(_T_1884, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1886 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] - node _T_1887 = and(io.tlu_i0_commit_cmt, _T_1886) @[dec_tlu_ctl.scala 2277:94] - node _T_1888 = eq(mhpme_vec[3], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] - node _T_1889 = bits(_T_1888, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1890 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] - node _T_1891 = and(io.tlu_i0_commit_cmt, _T_1890) @[dec_tlu_ctl.scala 2278:94] - node _T_1892 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] - node _T_1893 = and(_T_1891, _T_1892) @[dec_tlu_ctl.scala 2278:115] - node _T_1894 = eq(mhpme_vec[3], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] - node _T_1895 = bits(_T_1894, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1896 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] - node _T_1897 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] - node _T_1898 = and(_T_1896, _T_1897) @[dec_tlu_ctl.scala 2279:115] - node _T_1899 = eq(mhpme_vec[3], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] - node _T_1900 = bits(_T_1899, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1901 = eq(mhpme_vec[3], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] - node _T_1902 = bits(_T_1901, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1903 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] - node _T_1904 = bits(_T_1903, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1905 = eq(mhpme_vec[3], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] - node _T_1906 = bits(_T_1905, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1907 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] - node _T_1908 = eq(mhpme_vec[3], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] - node _T_1909 = bits(_T_1908, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1910 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] - node _T_1911 = eq(mhpme_vec[3], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] - node _T_1912 = bits(_T_1911, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1913 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] - node _T_1914 = eq(mhpme_vec[3], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] - node _T_1915 = bits(_T_1914, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1916 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] - node _T_1917 = eq(mhpme_vec[3], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] - node _T_1918 = bits(_T_1917, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1919 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] - node _T_1920 = and(_T_1919, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] - node _T_1921 = eq(mhpme_vec[3], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] - node _T_1922 = bits(_T_1921, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1923 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] - node _T_1924 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] - node _T_1925 = and(_T_1923, _T_1924) @[dec_tlu_ctl.scala 2288:101] - node _T_1926 = eq(mhpme_vec[3], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] - node _T_1927 = bits(_T_1926, 0, 0) @[dec_tlu_ctl.scala 2289:59] - node _T_1928 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] - node _T_1929 = eq(mhpme_vec[3], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] - node _T_1930 = bits(_T_1929, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1931 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] - node _T_1932 = eq(mhpme_vec[3], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] - node _T_1933 = bits(_T_1932, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1934 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] - node _T_1935 = eq(mhpme_vec[3], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] - node _T_1936 = bits(_T_1935, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1937 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] - node _T_1938 = eq(mhpme_vec[3], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] - node _T_1939 = bits(_T_1938, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1940 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] - node _T_1941 = eq(mhpme_vec[3], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] - node _T_1942 = bits(_T_1941, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1943 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] - node _T_1944 = eq(mhpme_vec[3], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] - node _T_1945 = bits(_T_1944, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1946 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] - node _T_1947 = eq(mhpme_vec[3], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] - node _T_1948 = bits(_T_1947, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1949 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] - node _T_1950 = eq(mhpme_vec[3], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] - node _T_1951 = bits(_T_1950, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1952 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] - node _T_1953 = eq(mhpme_vec[3], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] - node _T_1954 = bits(_T_1953, 0, 0) @[dec_tlu_ctl.scala 2298:59] - node _T_1955 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] - node _T_1956 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] - node _T_1957 = or(_T_1955, _T_1956) @[dec_tlu_ctl.scala 2298:101] - node _T_1958 = eq(mhpme_vec[3], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] - node _T_1959 = bits(_T_1958, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1960 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] - node _T_1961 = eq(mhpme_vec[3], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] - node _T_1962 = bits(_T_1961, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1963 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] - node _T_1964 = eq(mhpme_vec[3], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] - node _T_1965 = bits(_T_1964, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1966 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] - node _T_1967 = eq(mhpme_vec[3], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] - node _T_1968 = bits(_T_1967, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1969 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] - node _T_1970 = bits(_T_1969, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1971 = eq(mhpme_vec[3], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] - node _T_1972 = bits(_T_1971, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1973 = eq(mhpme_vec[3], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] - node _T_1974 = bits(_T_1973, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1975 = eq(mhpme_vec[3], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] - node _T_1976 = bits(_T_1975, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1977 = eq(mhpme_vec[3], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] - node _T_1978 = bits(_T_1977, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1979 = eq(mhpme_vec[3], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] - node _T_1980 = bits(_T_1979, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1981 = eq(mhpme_vec[3], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] - node _T_1982 = bits(_T_1981, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1983 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] - node _T_1984 = or(_T_1983, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] - node _T_1985 = eq(mhpme_vec[3], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] - node _T_1986 = bits(_T_1985, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1987 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] - node _T_1988 = or(_T_1987, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] - node _T_1989 = eq(mhpme_vec[3], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] - node _T_1990 = bits(_T_1989, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1991 = eq(mhpme_vec[3], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] - node _T_1992 = bits(_T_1991, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1993 = eq(mhpme_vec[3], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] - node _T_1994 = bits(_T_1993, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1995 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] - node _T_1996 = and(_T_1995, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] - node _T_1997 = eq(mhpme_vec[3], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] - node _T_1998 = bits(_T_1997, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1999 = eq(mhpme_vec[3], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] - node _T_2000 = bits(_T_1999, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_2001 = eq(mhpme_vec[3], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] - node _T_2002 = bits(_T_2001, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_2003 = eq(mhpme_vec[3], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] - node _T_2004 = bits(_T_2003, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_2005 = eq(mhpme_vec[3], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] - node _T_2006 = bits(_T_2005, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_2007 = eq(mhpme_vec[3], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] - node _T_2008 = bits(_T_2007, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_2009 = eq(mhpme_vec[3], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] - node _T_2010 = bits(_T_2009, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_2011 = eq(mhpme_vec[3], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] - node _T_2012 = bits(_T_2011, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_2013 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] - node _T_2014 = bits(_T_2013, 0, 0) @[dec_tlu_ctl.scala 2321:84] - node _T_2015 = not(_T_2014) @[dec_tlu_ctl.scala 2321:73] - node _T_2016 = eq(mhpme_vec[3], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] - node _T_2017 = bits(_T_2016, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_2018 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] - node _T_2019 = bits(_T_2018, 0, 0) @[dec_tlu_ctl.scala 2322:84] - node _T_2020 = not(_T_2019) @[dec_tlu_ctl.scala 2322:73] - node _T_2021 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] - node _T_2022 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] - node _T_2023 = and(_T_2021, _T_2022) @[dec_tlu_ctl.scala 2322:113] - node _T_2024 = orr(_T_2023) @[dec_tlu_ctl.scala 2322:125] - node _T_2025 = and(_T_2020, _T_2024) @[dec_tlu_ctl.scala 2322:98] - node _T_2026 = eq(mhpme_vec[3], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] - node _T_2027 = bits(_T_2026, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_2028 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] - node _T_2029 = eq(mhpme_vec[3], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] - node _T_2030 = bits(_T_2029, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_2031 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] - node _T_2032 = eq(mhpme_vec[3], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] - node _T_2033 = bits(_T_2032, 0, 0) @[dec_tlu_ctl.scala 2325:62] - node _T_2034 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] - node _T_2035 = eq(mhpme_vec[3], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] - node _T_2036 = bits(_T_2035, 0, 0) @[dec_tlu_ctl.scala 2327:62] - node _T_2037 = eq(mhpme_vec[3], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] - node _T_2038 = bits(_T_2037, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_2039 = eq(mhpme_vec[3], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] - node _T_2040 = bits(_T_2039, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_2041 = eq(mhpme_vec[3], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] - node _T_2042 = bits(_T_2041, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_2043 = eq(mhpme_vec[3], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] - node _T_2044 = bits(_T_2043, 0, 0) @[dec_tlu_ctl.scala 2331:62] - node _T_2045 = mux(_T_1879, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2046 = mux(_T_1881, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2047 = mux(_T_1883, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2048 = mux(_T_1885, _T_1887, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2049 = mux(_T_1889, _T_1893, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2050 = mux(_T_1895, _T_1898, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2051 = mux(_T_1900, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2052 = mux(_T_1902, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2053 = mux(_T_1904, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2054 = mux(_T_1906, _T_1907, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2055 = mux(_T_1909, _T_1910, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2056 = mux(_T_1912, _T_1913, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2057 = mux(_T_1915, _T_1916, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2058 = mux(_T_1918, _T_1920, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2059 = mux(_T_1922, _T_1925, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2060 = mux(_T_1927, _T_1928, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2061 = mux(_T_1930, _T_1931, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2062 = mux(_T_1933, _T_1934, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2063 = mux(_T_1936, _T_1937, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2064 = mux(_T_1939, _T_1940, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2065 = mux(_T_1942, _T_1943, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2066 = mux(_T_1945, _T_1946, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2067 = mux(_T_1948, _T_1949, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2068 = mux(_T_1951, _T_1952, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2069 = mux(_T_1954, _T_1957, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2070 = mux(_T_1959, _T_1960, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2071 = mux(_T_1962, _T_1963, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2072 = mux(_T_1965, _T_1966, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2073 = mux(_T_1968, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2074 = mux(_T_1970, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2075 = mux(_T_1972, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2076 = mux(_T_1974, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2077 = mux(_T_1976, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2078 = mux(_T_1978, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2079 = mux(_T_1980, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2080 = mux(_T_1982, _T_1984, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2081 = mux(_T_1986, _T_1988, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2082 = mux(_T_1990, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2083 = mux(_T_1992, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2084 = mux(_T_1994, _T_1996, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2085 = mux(_T_1998, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2086 = mux(_T_2000, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2087 = mux(_T_2002, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2088 = mux(_T_2004, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2089 = mux(_T_2006, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2090 = mux(_T_2008, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2091 = mux(_T_2010, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2092 = mux(_T_2012, _T_2015, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2093 = mux(_T_2017, _T_2025, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2094 = mux(_T_2027, _T_2028, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2095 = mux(_T_2030, _T_2031, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2096 = mux(_T_2033, _T_2034, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2097 = mux(_T_2036, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2098 = mux(_T_2038, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2099 = mux(_T_2040, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2100 = mux(_T_2042, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2101 = mux(_T_2044, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2102 = or(_T_2045, _T_2046) @[Mux.scala 27:72] + wire _T_1866 : UInt<1> @[Mux.scala 27:72] + _T_1866 <= _T_1865 @[Mux.scala 27:72] + node _T_1867 = and(_T_1585, _T_1866) @[dec_tlu_ctl.scala 2273:44] + mhpmc_inc_r[2] <= _T_1867 @[dec_tlu_ctl.scala 2273:19] + node _T_1868 = bits(mcountinhibit, 6, 6) @[dec_tlu_ctl.scala 2273:38] + node _T_1869 = not(_T_1868) @[dec_tlu_ctl.scala 2273:24] + node _T_1870 = eq(mhpme_vec[3], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] + node _T_1871 = bits(_T_1870, 0, 0) @[dec_tlu_ctl.scala 2274:62] + node _T_1872 = eq(mhpme_vec[3], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] + node _T_1873 = bits(_T_1872, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1874 = eq(mhpme_vec[3], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] + node _T_1875 = bits(_T_1874, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1876 = eq(mhpme_vec[3], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] + node _T_1877 = bits(_T_1876, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1878 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] + node _T_1879 = and(io.tlu_i0_commit_cmt, _T_1878) @[dec_tlu_ctl.scala 2277:94] + node _T_1880 = eq(mhpme_vec[3], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] + node _T_1881 = bits(_T_1880, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1882 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] + node _T_1883 = and(io.tlu_i0_commit_cmt, _T_1882) @[dec_tlu_ctl.scala 2278:94] + node _T_1884 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] + node _T_1885 = and(_T_1883, _T_1884) @[dec_tlu_ctl.scala 2278:115] + node _T_1886 = eq(mhpme_vec[3], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] + node _T_1887 = bits(_T_1886, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1888 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] + node _T_1889 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] + node _T_1890 = and(_T_1888, _T_1889) @[dec_tlu_ctl.scala 2279:115] + node _T_1891 = eq(mhpme_vec[3], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] + node _T_1892 = bits(_T_1891, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1893 = eq(mhpme_vec[3], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] + node _T_1894 = bits(_T_1893, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1895 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] + node _T_1896 = bits(_T_1895, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1897 = eq(mhpme_vec[3], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] + node _T_1898 = bits(_T_1897, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1899 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] + node _T_1900 = eq(mhpme_vec[3], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] + node _T_1901 = bits(_T_1900, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1902 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] + node _T_1903 = eq(mhpme_vec[3], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] + node _T_1904 = bits(_T_1903, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1905 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] + node _T_1906 = eq(mhpme_vec[3], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] + node _T_1907 = bits(_T_1906, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1908 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] + node _T_1909 = eq(mhpme_vec[3], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] + node _T_1910 = bits(_T_1909, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1911 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] + node _T_1912 = and(_T_1911, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] + node _T_1913 = eq(mhpme_vec[3], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] + node _T_1914 = bits(_T_1913, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1915 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] + node _T_1916 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] + node _T_1917 = and(_T_1915, _T_1916) @[dec_tlu_ctl.scala 2288:101] + node _T_1918 = eq(mhpme_vec[3], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] + node _T_1919 = bits(_T_1918, 0, 0) @[dec_tlu_ctl.scala 2289:59] + node _T_1920 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] + node _T_1921 = eq(mhpme_vec[3], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] + node _T_1922 = bits(_T_1921, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1923 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] + node _T_1924 = eq(mhpme_vec[3], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] + node _T_1925 = bits(_T_1924, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1926 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] + node _T_1927 = eq(mhpme_vec[3], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] + node _T_1928 = bits(_T_1927, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1929 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] + node _T_1930 = eq(mhpme_vec[3], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] + node _T_1931 = bits(_T_1930, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1932 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] + node _T_1933 = eq(mhpme_vec[3], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] + node _T_1934 = bits(_T_1933, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1935 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] + node _T_1936 = eq(mhpme_vec[3], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] + node _T_1937 = bits(_T_1936, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1938 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] + node _T_1939 = eq(mhpme_vec[3], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] + node _T_1940 = bits(_T_1939, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1941 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] + node _T_1942 = eq(mhpme_vec[3], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] + node _T_1943 = bits(_T_1942, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1944 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] + node _T_1945 = eq(mhpme_vec[3], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] + node _T_1946 = bits(_T_1945, 0, 0) @[dec_tlu_ctl.scala 2298:59] + node _T_1947 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] + node _T_1948 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] + node _T_1949 = or(_T_1947, _T_1948) @[dec_tlu_ctl.scala 2298:101] + node _T_1950 = eq(mhpme_vec[3], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] + node _T_1951 = bits(_T_1950, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1952 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] + node _T_1953 = eq(mhpme_vec[3], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] + node _T_1954 = bits(_T_1953, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1955 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] + node _T_1956 = eq(mhpme_vec[3], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] + node _T_1957 = bits(_T_1956, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1958 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] + node _T_1959 = eq(mhpme_vec[3], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] + node _T_1960 = bits(_T_1959, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1961 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] + node _T_1962 = bits(_T_1961, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1963 = eq(mhpme_vec[3], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] + node _T_1964 = bits(_T_1963, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1965 = eq(mhpme_vec[3], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] + node _T_1966 = bits(_T_1965, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1967 = eq(mhpme_vec[3], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] + node _T_1968 = bits(_T_1967, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1969 = eq(mhpme_vec[3], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] + node _T_1970 = bits(_T_1969, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1971 = eq(mhpme_vec[3], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] + node _T_1972 = bits(_T_1971, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1973 = eq(mhpme_vec[3], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] + node _T_1974 = bits(_T_1973, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1975 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] + node _T_1976 = or(_T_1975, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] + node _T_1977 = eq(mhpme_vec[3], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] + node _T_1978 = bits(_T_1977, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1979 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] + node _T_1980 = or(_T_1979, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] + node _T_1981 = eq(mhpme_vec[3], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] + node _T_1982 = bits(_T_1981, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1983 = eq(mhpme_vec[3], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] + node _T_1984 = bits(_T_1983, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1985 = eq(mhpme_vec[3], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] + node _T_1986 = bits(_T_1985, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1987 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] + node _T_1988 = and(_T_1987, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] + node _T_1989 = eq(mhpme_vec[3], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] + node _T_1990 = bits(_T_1989, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_1991 = eq(mhpme_vec[3], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] + node _T_1992 = bits(_T_1991, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_1993 = eq(mhpme_vec[3], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] + node _T_1994 = bits(_T_1993, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_1995 = eq(mhpme_vec[3], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] + node _T_1996 = bits(_T_1995, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_1997 = eq(mhpme_vec[3], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] + node _T_1998 = bits(_T_1997, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_1999 = eq(mhpme_vec[3], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] + node _T_2000 = bits(_T_1999, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_2001 = eq(mhpme_vec[3], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] + node _T_2002 = bits(_T_2001, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_2003 = eq(mhpme_vec[3], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] + node _T_2004 = bits(_T_2003, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_2005 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] + node _T_2006 = bits(_T_2005, 0, 0) @[dec_tlu_ctl.scala 2321:84] + node _T_2007 = not(_T_2006) @[dec_tlu_ctl.scala 2321:73] + node _T_2008 = eq(mhpme_vec[3], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] + node _T_2009 = bits(_T_2008, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_2010 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] + node _T_2011 = bits(_T_2010, 0, 0) @[dec_tlu_ctl.scala 2322:84] + node _T_2012 = not(_T_2011) @[dec_tlu_ctl.scala 2322:73] + node _T_2013 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] + node _T_2014 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] + node _T_2015 = and(_T_2013, _T_2014) @[dec_tlu_ctl.scala 2322:113] + node _T_2016 = orr(_T_2015) @[dec_tlu_ctl.scala 2322:125] + node _T_2017 = and(_T_2012, _T_2016) @[dec_tlu_ctl.scala 2322:98] + node _T_2018 = eq(mhpme_vec[3], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] + node _T_2019 = bits(_T_2018, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_2020 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] + node _T_2021 = eq(mhpme_vec[3], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] + node _T_2022 = bits(_T_2021, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_2023 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] + node _T_2024 = eq(mhpme_vec[3], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] + node _T_2025 = bits(_T_2024, 0, 0) @[dec_tlu_ctl.scala 2325:62] + node _T_2026 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] + node _T_2027 = eq(mhpme_vec[3], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] + node _T_2028 = bits(_T_2027, 0, 0) @[dec_tlu_ctl.scala 2327:62] + node _T_2029 = eq(mhpme_vec[3], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] + node _T_2030 = bits(_T_2029, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_2031 = eq(mhpme_vec[3], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] + node _T_2032 = bits(_T_2031, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_2033 = eq(mhpme_vec[3], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] + node _T_2034 = bits(_T_2033, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_2035 = eq(mhpme_vec[3], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] + node _T_2036 = bits(_T_2035, 0, 0) @[dec_tlu_ctl.scala 2331:62] + node _T_2037 = mux(_T_1871, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2038 = mux(_T_1873, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2039 = mux(_T_1875, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2040 = mux(_T_1877, _T_1879, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2041 = mux(_T_1881, _T_1885, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2042 = mux(_T_1887, _T_1890, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2043 = mux(_T_1892, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2044 = mux(_T_1894, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2045 = mux(_T_1896, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2046 = mux(_T_1898, _T_1899, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2047 = mux(_T_1901, _T_1902, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2048 = mux(_T_1904, _T_1905, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2049 = mux(_T_1907, _T_1908, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2050 = mux(_T_1910, _T_1912, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2051 = mux(_T_1914, _T_1917, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2052 = mux(_T_1919, _T_1920, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2053 = mux(_T_1922, _T_1923, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2054 = mux(_T_1925, _T_1926, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2055 = mux(_T_1928, _T_1929, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2056 = mux(_T_1931, _T_1932, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2057 = mux(_T_1934, _T_1935, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2058 = mux(_T_1937, _T_1938, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2059 = mux(_T_1940, _T_1941, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2060 = mux(_T_1943, _T_1944, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2061 = mux(_T_1946, _T_1949, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2062 = mux(_T_1951, _T_1952, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2063 = mux(_T_1954, _T_1955, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2064 = mux(_T_1957, _T_1958, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2065 = mux(_T_1960, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2066 = mux(_T_1962, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2067 = mux(_T_1964, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2068 = mux(_T_1966, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2069 = mux(_T_1968, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2070 = mux(_T_1970, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2071 = mux(_T_1972, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2072 = mux(_T_1974, _T_1976, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2073 = mux(_T_1978, _T_1980, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2074 = mux(_T_1982, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2075 = mux(_T_1984, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2076 = mux(_T_1986, _T_1988, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2077 = mux(_T_1990, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2078 = mux(_T_1992, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2079 = mux(_T_1994, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2080 = mux(_T_1996, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2081 = mux(_T_1998, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2082 = mux(_T_2000, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2083 = mux(_T_2002, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2084 = mux(_T_2004, _T_2007, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2085 = mux(_T_2009, _T_2017, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2086 = mux(_T_2019, _T_2020, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2087 = mux(_T_2022, _T_2023, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2088 = mux(_T_2025, _T_2026, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2089 = mux(_T_2028, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2090 = mux(_T_2030, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2091 = mux(_T_2032, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2092 = mux(_T_2034, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2093 = mux(_T_2036, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2094 = or(_T_2037, _T_2038) @[Mux.scala 27:72] + node _T_2095 = or(_T_2094, _T_2039) @[Mux.scala 27:72] + node _T_2096 = or(_T_2095, _T_2040) @[Mux.scala 27:72] + node _T_2097 = or(_T_2096, _T_2041) @[Mux.scala 27:72] + node _T_2098 = or(_T_2097, _T_2042) @[Mux.scala 27:72] + node _T_2099 = or(_T_2098, _T_2043) @[Mux.scala 27:72] + node _T_2100 = or(_T_2099, _T_2044) @[Mux.scala 27:72] + node _T_2101 = or(_T_2100, _T_2045) @[Mux.scala 27:72] + node _T_2102 = or(_T_2101, _T_2046) @[Mux.scala 27:72] node _T_2103 = or(_T_2102, _T_2047) @[Mux.scala 27:72] node _T_2104 = or(_T_2103, _T_2048) @[Mux.scala 27:72] node _T_2105 = or(_T_2104, _T_2049) @[Mux.scala 27:72] @@ -75539,583 +75539,583 @@ circuit quasar_wrapper : node _T_2147 = or(_T_2146, _T_2091) @[Mux.scala 27:72] node _T_2148 = or(_T_2147, _T_2092) @[Mux.scala 27:72] node _T_2149 = or(_T_2148, _T_2093) @[Mux.scala 27:72] - node _T_2150 = or(_T_2149, _T_2094) @[Mux.scala 27:72] - node _T_2151 = or(_T_2150, _T_2095) @[Mux.scala 27:72] - node _T_2152 = or(_T_2151, _T_2096) @[Mux.scala 27:72] - node _T_2153 = or(_T_2152, _T_2097) @[Mux.scala 27:72] - node _T_2154 = or(_T_2153, _T_2098) @[Mux.scala 27:72] - node _T_2155 = or(_T_2154, _T_2099) @[Mux.scala 27:72] - node _T_2156 = or(_T_2155, _T_2100) @[Mux.scala 27:72] - node _T_2157 = or(_T_2156, _T_2101) @[Mux.scala 27:72] - wire _T_2158 : UInt<1> @[Mux.scala 27:72] - _T_2158 <= _T_2157 @[Mux.scala 27:72] - node _T_2159 = and(_T_1877, _T_2158) @[dec_tlu_ctl.scala 2273:44] - mhpmc_inc_r[3] <= _T_2159 @[dec_tlu_ctl.scala 2273:19] - reg _T_2160 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2334:53] - _T_2160 <= mhpmc_inc_r[0] @[dec_tlu_ctl.scala 2334:53] - mhpmc_inc_r_d1[0] <= _T_2160 @[dec_tlu_ctl.scala 2334:20] - reg _T_2161 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2335:53] - _T_2161 <= mhpmc_inc_r[1] @[dec_tlu_ctl.scala 2335:53] - mhpmc_inc_r_d1[1] <= _T_2161 @[dec_tlu_ctl.scala 2335:20] - reg _T_2162 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2336:53] - _T_2162 <= mhpmc_inc_r[2] @[dec_tlu_ctl.scala 2336:53] - mhpmc_inc_r_d1[2] <= _T_2162 @[dec_tlu_ctl.scala 2336:20] - reg _T_2163 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2337:53] - _T_2163 <= mhpmc_inc_r[3] @[dec_tlu_ctl.scala 2337:53] - mhpmc_inc_r_d1[3] <= _T_2163 @[dec_tlu_ctl.scala 2337:20] + wire _T_2150 : UInt<1> @[Mux.scala 27:72] + _T_2150 <= _T_2149 @[Mux.scala 27:72] + node _T_2151 = and(_T_1869, _T_2150) @[dec_tlu_ctl.scala 2273:44] + mhpmc_inc_r[3] <= _T_2151 @[dec_tlu_ctl.scala 2273:19] + reg _T_2152 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2334:53] + _T_2152 <= mhpmc_inc_r[0] @[dec_tlu_ctl.scala 2334:53] + mhpmc_inc_r_d1[0] <= _T_2152 @[dec_tlu_ctl.scala 2334:20] + reg _T_2153 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2335:53] + _T_2153 <= mhpmc_inc_r[1] @[dec_tlu_ctl.scala 2335:53] + mhpmc_inc_r_d1[1] <= _T_2153 @[dec_tlu_ctl.scala 2335:20] + reg _T_2154 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2336:53] + _T_2154 <= mhpmc_inc_r[2] @[dec_tlu_ctl.scala 2336:53] + mhpmc_inc_r_d1[2] <= _T_2154 @[dec_tlu_ctl.scala 2336:20] + reg _T_2155 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2337:53] + _T_2155 <= mhpmc_inc_r[3] @[dec_tlu_ctl.scala 2337:53] + mhpmc_inc_r_d1[3] <= _T_2155 @[dec_tlu_ctl.scala 2337:20] reg perfcnt_halted_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2338:56] perfcnt_halted_d1 <= perfcnt_halted @[dec_tlu_ctl.scala 2338:56] - node _T_2164 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2341:53] - node _T_2165 = and(io.dec_tlu_dbg_halted, _T_2164) @[dec_tlu_ctl.scala 2341:44] - node _T_2166 = or(_T_2165, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2341:67] - perfcnt_halted <= _T_2166 @[dec_tlu_ctl.scala 2341:17] - node _T_2167 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2342:70] - node _T_2168 = and(io.dec_tlu_dbg_halted, _T_2167) @[dec_tlu_ctl.scala 2342:61] - node _T_2169 = not(_T_2168) @[dec_tlu_ctl.scala 2342:37] - node _T_2170 = bits(_T_2169, 0, 0) @[Bitwise.scala 72:15] - node _T_2171 = mux(_T_2170, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_2172 = bits(mhpme_vec[3], 9, 9) @[dec_tlu_ctl.scala 2342:104] - node _T_2173 = bits(mhpme_vec[2], 9, 9) @[dec_tlu_ctl.scala 2342:120] - node _T_2174 = bits(mhpme_vec[1], 9, 9) @[dec_tlu_ctl.scala 2342:136] - node _T_2175 = bits(mhpme_vec[0], 9, 9) @[dec_tlu_ctl.scala 2342:152] - node _T_2176 = cat(_T_2174, _T_2175) @[Cat.scala 29:58] - node _T_2177 = cat(_T_2172, _T_2173) @[Cat.scala 29:58] - node _T_2178 = cat(_T_2177, _T_2176) @[Cat.scala 29:58] - node perfcnt_during_sleep = and(_T_2171, _T_2178) @[dec_tlu_ctl.scala 2342:86] - node _T_2179 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2344:88] - node _T_2180 = not(_T_2179) @[dec_tlu_ctl.scala 2344:67] - node _T_2181 = and(perfcnt_halted_d1, _T_2180) @[dec_tlu_ctl.scala 2344:65] - node _T_2182 = not(_T_2181) @[dec_tlu_ctl.scala 2344:45] - node _T_2183 = and(mhpmc_inc_r_d1[0], _T_2182) @[dec_tlu_ctl.scala 2344:43] - io.dec_tlu_perfcnt0 <= _T_2183 @[dec_tlu_ctl.scala 2344:22] - node _T_2184 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2345:88] - node _T_2185 = not(_T_2184) @[dec_tlu_ctl.scala 2345:67] - node _T_2186 = and(perfcnt_halted_d1, _T_2185) @[dec_tlu_ctl.scala 2345:65] - node _T_2187 = not(_T_2186) @[dec_tlu_ctl.scala 2345:45] - node _T_2188 = and(mhpmc_inc_r_d1[1], _T_2187) @[dec_tlu_ctl.scala 2345:43] - io.dec_tlu_perfcnt1 <= _T_2188 @[dec_tlu_ctl.scala 2345:22] - node _T_2189 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2346:88] - node _T_2190 = not(_T_2189) @[dec_tlu_ctl.scala 2346:67] - node _T_2191 = and(perfcnt_halted_d1, _T_2190) @[dec_tlu_ctl.scala 2346:65] - node _T_2192 = not(_T_2191) @[dec_tlu_ctl.scala 2346:45] - node _T_2193 = and(mhpmc_inc_r_d1[2], _T_2192) @[dec_tlu_ctl.scala 2346:43] - io.dec_tlu_perfcnt2 <= _T_2193 @[dec_tlu_ctl.scala 2346:22] - node _T_2194 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2347:88] - node _T_2195 = not(_T_2194) @[dec_tlu_ctl.scala 2347:67] - node _T_2196 = and(perfcnt_halted_d1, _T_2195) @[dec_tlu_ctl.scala 2347:65] - node _T_2197 = not(_T_2196) @[dec_tlu_ctl.scala 2347:45] - node _T_2198 = and(mhpmc_inc_r_d1[3], _T_2197) @[dec_tlu_ctl.scala 2347:43] - io.dec_tlu_perfcnt3 <= _T_2198 @[dec_tlu_ctl.scala 2347:22] - node _T_2199 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2353:65] - node _T_2200 = eq(_T_2199, UInt<12>("h0b03")) @[dec_tlu_ctl.scala 2353:72] - node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2200) @[dec_tlu_ctl.scala 2353:43] - node _T_2201 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2354:23] - node _T_2202 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2354:61] - node _T_2203 = or(_T_2201, _T_2202) @[dec_tlu_ctl.scala 2354:39] - node _T_2204 = orr(mhpmc_inc_r[0]) @[dec_tlu_ctl.scala 2354:86] - node mhpmc3_wr_en1 = and(_T_2203, _T_2204) @[dec_tlu_ctl.scala 2354:66] + node _T_2156 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2341:53] + node _T_2157 = and(io.dec_tlu_dbg_halted, _T_2156) @[dec_tlu_ctl.scala 2341:44] + node _T_2158 = or(_T_2157, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2341:67] + perfcnt_halted <= _T_2158 @[dec_tlu_ctl.scala 2341:17] + node _T_2159 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2342:70] + node _T_2160 = and(io.dec_tlu_dbg_halted, _T_2159) @[dec_tlu_ctl.scala 2342:61] + node _T_2161 = not(_T_2160) @[dec_tlu_ctl.scala 2342:37] + node _T_2162 = bits(_T_2161, 0, 0) @[Bitwise.scala 72:15] + node _T_2163 = mux(_T_2162, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2164 = bits(mhpme_vec[3], 9, 9) @[dec_tlu_ctl.scala 2342:104] + node _T_2165 = bits(mhpme_vec[2], 9, 9) @[dec_tlu_ctl.scala 2342:120] + node _T_2166 = bits(mhpme_vec[1], 9, 9) @[dec_tlu_ctl.scala 2342:136] + node _T_2167 = bits(mhpme_vec[0], 9, 9) @[dec_tlu_ctl.scala 2342:152] + node _T_2168 = cat(_T_2166, _T_2167) @[Cat.scala 29:58] + node _T_2169 = cat(_T_2164, _T_2165) @[Cat.scala 29:58] + node _T_2170 = cat(_T_2169, _T_2168) @[Cat.scala 29:58] + node perfcnt_during_sleep = and(_T_2163, _T_2170) @[dec_tlu_ctl.scala 2342:86] + node _T_2171 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2344:88] + node _T_2172 = not(_T_2171) @[dec_tlu_ctl.scala 2344:67] + node _T_2173 = and(perfcnt_halted_d1, _T_2172) @[dec_tlu_ctl.scala 2344:65] + node _T_2174 = not(_T_2173) @[dec_tlu_ctl.scala 2344:45] + node _T_2175 = and(mhpmc_inc_r_d1[0], _T_2174) @[dec_tlu_ctl.scala 2344:43] + io.dec_tlu_perfcnt0 <= _T_2175 @[dec_tlu_ctl.scala 2344:22] + node _T_2176 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2345:88] + node _T_2177 = not(_T_2176) @[dec_tlu_ctl.scala 2345:67] + node _T_2178 = and(perfcnt_halted_d1, _T_2177) @[dec_tlu_ctl.scala 2345:65] + node _T_2179 = not(_T_2178) @[dec_tlu_ctl.scala 2345:45] + node _T_2180 = and(mhpmc_inc_r_d1[1], _T_2179) @[dec_tlu_ctl.scala 2345:43] + io.dec_tlu_perfcnt1 <= _T_2180 @[dec_tlu_ctl.scala 2345:22] + node _T_2181 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2346:88] + node _T_2182 = not(_T_2181) @[dec_tlu_ctl.scala 2346:67] + node _T_2183 = and(perfcnt_halted_d1, _T_2182) @[dec_tlu_ctl.scala 2346:65] + node _T_2184 = not(_T_2183) @[dec_tlu_ctl.scala 2346:45] + node _T_2185 = and(mhpmc_inc_r_d1[2], _T_2184) @[dec_tlu_ctl.scala 2346:43] + io.dec_tlu_perfcnt2 <= _T_2185 @[dec_tlu_ctl.scala 2346:22] + node _T_2186 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2347:88] + node _T_2187 = not(_T_2186) @[dec_tlu_ctl.scala 2347:67] + node _T_2188 = and(perfcnt_halted_d1, _T_2187) @[dec_tlu_ctl.scala 2347:65] + node _T_2189 = not(_T_2188) @[dec_tlu_ctl.scala 2347:45] + node _T_2190 = and(mhpmc_inc_r_d1[3], _T_2189) @[dec_tlu_ctl.scala 2347:43] + io.dec_tlu_perfcnt3 <= _T_2190 @[dec_tlu_ctl.scala 2347:22] + node _T_2191 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2353:65] + node _T_2192 = eq(_T_2191, UInt<12>("h0b03")) @[dec_tlu_ctl.scala 2353:72] + node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2192) @[dec_tlu_ctl.scala 2353:43] + node _T_2193 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2354:23] + node _T_2194 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2354:61] + node _T_2195 = or(_T_2193, _T_2194) @[dec_tlu_ctl.scala 2354:39] + node _T_2196 = orr(mhpmc_inc_r[0]) @[dec_tlu_ctl.scala 2354:86] + node mhpmc3_wr_en1 = and(_T_2195, _T_2196) @[dec_tlu_ctl.scala 2354:66] node mhpmc3_wr_en = or(mhpmc3_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2355:36] - node _T_2205 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2358:28] - node _T_2206 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2358:41] - node _T_2207 = cat(_T_2205, _T_2206) @[Cat.scala 29:58] - node _T_2208 = cat(UInt<63>("h00"), mhpmc_inc_r[0]) @[Cat.scala 29:58] - node _T_2209 = add(_T_2207, _T_2208) @[dec_tlu_ctl.scala 2358:49] - node _T_2210 = tail(_T_2209, 1) @[dec_tlu_ctl.scala 2358:49] - mhpmc3_incr <= _T_2210 @[dec_tlu_ctl.scala 2358:14] - node _T_2211 = bits(mhpmc3_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2359:36] - node _T_2212 = bits(mhpmc3_incr, 31, 0) @[dec_tlu_ctl.scala 2359:76] - node mhpmc3_ns = mux(_T_2211, io.dec_csr_wrdata_r, _T_2212) @[dec_tlu_ctl.scala 2359:21] - node _T_2213 = bits(mhpmc3_wr_en, 0, 0) @[dec_tlu_ctl.scala 2361:42] - inst rvclkhdr_26 of rvclkhdr_746 @[el2_lib.scala 508:23] + node _T_2197 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2358:28] + node _T_2198 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2358:41] + node _T_2199 = cat(_T_2197, _T_2198) @[Cat.scala 29:58] + node _T_2200 = cat(UInt<63>("h00"), mhpmc_inc_r[0]) @[Cat.scala 29:58] + node _T_2201 = add(_T_2199, _T_2200) @[dec_tlu_ctl.scala 2358:49] + node _T_2202 = tail(_T_2201, 1) @[dec_tlu_ctl.scala 2358:49] + mhpmc3_incr <= _T_2202 @[dec_tlu_ctl.scala 2358:14] + node _T_2203 = bits(mhpmc3_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2359:36] + node _T_2204 = bits(mhpmc3_incr, 31, 0) @[dec_tlu_ctl.scala 2359:76] + node mhpmc3_ns = mux(_T_2203, io.dec_csr_wrdata_r, _T_2204) @[dec_tlu_ctl.scala 2359:21] + node _T_2205 = bits(mhpmc3_wr_en, 0, 0) @[dec_tlu_ctl.scala 2361:42] + inst rvclkhdr_26 of rvclkhdr_746 @[lib.scala 368:23] rvclkhdr_26.clock <= clock rvclkhdr_26.reset <= reset - rvclkhdr_26.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_26.io.en <= _T_2213 @[el2_lib.scala 511:17] - rvclkhdr_26.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_2214 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_2214 <= mhpmc3_ns @[el2_lib.scala 514:16] - mhpmc3 <= _T_2214 @[dec_tlu_ctl.scala 2361:9] - node _T_2215 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2363:66] - node _T_2216 = eq(_T_2215, UInt<12>("h0b83")) @[dec_tlu_ctl.scala 2363:73] - node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2216) @[dec_tlu_ctl.scala 2363:44] + rvclkhdr_26.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_26.io.en <= _T_2205 @[lib.scala 371:17] + rvclkhdr_26.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_2206 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2206 <= mhpmc3_ns @[lib.scala 374:16] + mhpmc3 <= _T_2206 @[dec_tlu_ctl.scala 2361:9] + node _T_2207 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2363:66] + node _T_2208 = eq(_T_2207, UInt<12>("h0b83")) @[dec_tlu_ctl.scala 2363:73] + node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2208) @[dec_tlu_ctl.scala 2363:44] node mhpmc3h_wr_en = or(mhpmc3h_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2364:38] - node _T_2217 = bits(mhpmc3h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2365:38] - node _T_2218 = bits(mhpmc3_incr, 63, 32) @[dec_tlu_ctl.scala 2365:78] - node mhpmc3h_ns = mux(_T_2217, io.dec_csr_wrdata_r, _T_2218) @[dec_tlu_ctl.scala 2365:22] - node _T_2219 = bits(mhpmc3h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2367:46] - inst rvclkhdr_27 of rvclkhdr_747 @[el2_lib.scala 508:23] + node _T_2209 = bits(mhpmc3h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2365:38] + node _T_2210 = bits(mhpmc3_incr, 63, 32) @[dec_tlu_ctl.scala 2365:78] + node mhpmc3h_ns = mux(_T_2209, io.dec_csr_wrdata_r, _T_2210) @[dec_tlu_ctl.scala 2365:22] + node _T_2211 = bits(mhpmc3h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2367:46] + inst rvclkhdr_27 of rvclkhdr_747 @[lib.scala 368:23] rvclkhdr_27.clock <= clock rvclkhdr_27.reset <= reset - rvclkhdr_27.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_27.io.en <= _T_2219 @[el2_lib.scala 511:17] - rvclkhdr_27.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_2220 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_2220 <= mhpmc3h_ns @[el2_lib.scala 514:16] - mhpmc3h <= _T_2220 @[dec_tlu_ctl.scala 2367:10] - node _T_2221 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2372:65] - node _T_2222 = eq(_T_2221, UInt<12>("h0b04")) @[dec_tlu_ctl.scala 2372:72] - node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2222) @[dec_tlu_ctl.scala 2372:43] - node _T_2223 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2373:23] - node _T_2224 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2373:61] - node _T_2225 = or(_T_2223, _T_2224) @[dec_tlu_ctl.scala 2373:39] - node _T_2226 = orr(mhpmc_inc_r[1]) @[dec_tlu_ctl.scala 2373:86] - node mhpmc4_wr_en1 = and(_T_2225, _T_2226) @[dec_tlu_ctl.scala 2373:66] + rvclkhdr_27.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_27.io.en <= _T_2211 @[lib.scala 371:17] + rvclkhdr_27.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_2212 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2212 <= mhpmc3h_ns @[lib.scala 374:16] + mhpmc3h <= _T_2212 @[dec_tlu_ctl.scala 2367:10] + node _T_2213 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2372:65] + node _T_2214 = eq(_T_2213, UInt<12>("h0b04")) @[dec_tlu_ctl.scala 2372:72] + node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2214) @[dec_tlu_ctl.scala 2372:43] + node _T_2215 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2373:23] + node _T_2216 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2373:61] + node _T_2217 = or(_T_2215, _T_2216) @[dec_tlu_ctl.scala 2373:39] + node _T_2218 = orr(mhpmc_inc_r[1]) @[dec_tlu_ctl.scala 2373:86] + node mhpmc4_wr_en1 = and(_T_2217, _T_2218) @[dec_tlu_ctl.scala 2373:66] node mhpmc4_wr_en = or(mhpmc4_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2374:36] - node _T_2227 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2378:28] - node _T_2228 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2378:41] - node _T_2229 = cat(_T_2227, _T_2228) @[Cat.scala 29:58] - node _T_2230 = cat(UInt<63>("h00"), mhpmc_inc_r[1]) @[Cat.scala 29:58] - node _T_2231 = add(_T_2229, _T_2230) @[dec_tlu_ctl.scala 2378:49] - node _T_2232 = tail(_T_2231, 1) @[dec_tlu_ctl.scala 2378:49] - mhpmc4_incr <= _T_2232 @[dec_tlu_ctl.scala 2378:14] - node _T_2233 = bits(mhpmc4_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2379:36] - node _T_2234 = bits(io.dec_csr_wrdata_r, 31, 0) @[dec_tlu_ctl.scala 2379:63] - node _T_2235 = bits(mhpmc4_incr, 31, 0) @[dec_tlu_ctl.scala 2379:82] - node mhpmc4_ns = mux(_T_2233, _T_2234, _T_2235) @[dec_tlu_ctl.scala 2379:21] - node _T_2236 = bits(mhpmc4_wr_en, 0, 0) @[dec_tlu_ctl.scala 2380:43] - inst rvclkhdr_28 of rvclkhdr_748 @[el2_lib.scala 508:23] + node _T_2219 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2378:28] + node _T_2220 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2378:41] + node _T_2221 = cat(_T_2219, _T_2220) @[Cat.scala 29:58] + node _T_2222 = cat(UInt<63>("h00"), mhpmc_inc_r[1]) @[Cat.scala 29:58] + node _T_2223 = add(_T_2221, _T_2222) @[dec_tlu_ctl.scala 2378:49] + node _T_2224 = tail(_T_2223, 1) @[dec_tlu_ctl.scala 2378:49] + mhpmc4_incr <= _T_2224 @[dec_tlu_ctl.scala 2378:14] + node _T_2225 = bits(mhpmc4_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2379:36] + node _T_2226 = bits(io.dec_csr_wrdata_r, 31, 0) @[dec_tlu_ctl.scala 2379:63] + node _T_2227 = bits(mhpmc4_incr, 31, 0) @[dec_tlu_ctl.scala 2379:82] + node mhpmc4_ns = mux(_T_2225, _T_2226, _T_2227) @[dec_tlu_ctl.scala 2379:21] + node _T_2228 = bits(mhpmc4_wr_en, 0, 0) @[dec_tlu_ctl.scala 2380:43] + inst rvclkhdr_28 of rvclkhdr_748 @[lib.scala 368:23] rvclkhdr_28.clock <= clock rvclkhdr_28.reset <= reset - rvclkhdr_28.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_28.io.en <= _T_2236 @[el2_lib.scala 511:17] - rvclkhdr_28.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_2237 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_2237 <= mhpmc4_ns @[el2_lib.scala 514:16] - mhpmc4 <= _T_2237 @[dec_tlu_ctl.scala 2380:9] - node _T_2238 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2382:66] - node _T_2239 = eq(_T_2238, UInt<12>("h0b84")) @[dec_tlu_ctl.scala 2382:73] - node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2239) @[dec_tlu_ctl.scala 2382:44] + rvclkhdr_28.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_28.io.en <= _T_2228 @[lib.scala 371:17] + rvclkhdr_28.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_2229 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2229 <= mhpmc4_ns @[lib.scala 374:16] + mhpmc4 <= _T_2229 @[dec_tlu_ctl.scala 2380:9] + node _T_2230 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2382:66] + node _T_2231 = eq(_T_2230, UInt<12>("h0b84")) @[dec_tlu_ctl.scala 2382:73] + node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2231) @[dec_tlu_ctl.scala 2382:44] node mhpmc4h_wr_en = or(mhpmc4h_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2383:38] - node _T_2240 = bits(mhpmc4h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2384:38] - node _T_2241 = bits(mhpmc4_incr, 63, 32) @[dec_tlu_ctl.scala 2384:78] - node mhpmc4h_ns = mux(_T_2240, io.dec_csr_wrdata_r, _T_2241) @[dec_tlu_ctl.scala 2384:22] - node _T_2242 = bits(mhpmc4h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2385:46] - inst rvclkhdr_29 of rvclkhdr_749 @[el2_lib.scala 508:23] + node _T_2232 = bits(mhpmc4h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2384:38] + node _T_2233 = bits(mhpmc4_incr, 63, 32) @[dec_tlu_ctl.scala 2384:78] + node mhpmc4h_ns = mux(_T_2232, io.dec_csr_wrdata_r, _T_2233) @[dec_tlu_ctl.scala 2384:22] + node _T_2234 = bits(mhpmc4h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2385:46] + inst rvclkhdr_29 of rvclkhdr_749 @[lib.scala 368:23] rvclkhdr_29.clock <= clock rvclkhdr_29.reset <= reset - rvclkhdr_29.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_29.io.en <= _T_2242 @[el2_lib.scala 511:17] - rvclkhdr_29.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_2243 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_2243 <= mhpmc4h_ns @[el2_lib.scala 514:16] - mhpmc4h <= _T_2243 @[dec_tlu_ctl.scala 2385:10] - node _T_2244 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2391:65] - node _T_2245 = eq(_T_2244, UInt<12>("h0b05")) @[dec_tlu_ctl.scala 2391:72] - node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2245) @[dec_tlu_ctl.scala 2391:43] - node _T_2246 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2392:23] - node _T_2247 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2392:61] - node _T_2248 = or(_T_2246, _T_2247) @[dec_tlu_ctl.scala 2392:39] - node _T_2249 = orr(mhpmc_inc_r[2]) @[dec_tlu_ctl.scala 2392:86] - node mhpmc5_wr_en1 = and(_T_2248, _T_2249) @[dec_tlu_ctl.scala 2392:66] + rvclkhdr_29.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_29.io.en <= _T_2234 @[lib.scala 371:17] + rvclkhdr_29.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_2235 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2235 <= mhpmc4h_ns @[lib.scala 374:16] + mhpmc4h <= _T_2235 @[dec_tlu_ctl.scala 2385:10] + node _T_2236 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2391:65] + node _T_2237 = eq(_T_2236, UInt<12>("h0b05")) @[dec_tlu_ctl.scala 2391:72] + node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2237) @[dec_tlu_ctl.scala 2391:43] + node _T_2238 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2392:23] + node _T_2239 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2392:61] + node _T_2240 = or(_T_2238, _T_2239) @[dec_tlu_ctl.scala 2392:39] + node _T_2241 = orr(mhpmc_inc_r[2]) @[dec_tlu_ctl.scala 2392:86] + node mhpmc5_wr_en1 = and(_T_2240, _T_2241) @[dec_tlu_ctl.scala 2392:66] node mhpmc5_wr_en = or(mhpmc5_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2393:36] - node _T_2250 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2395:28] - node _T_2251 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2395:41] - node _T_2252 = cat(_T_2250, _T_2251) @[Cat.scala 29:58] - node _T_2253 = cat(UInt<63>("h00"), mhpmc_inc_r[2]) @[Cat.scala 29:58] - node _T_2254 = add(_T_2252, _T_2253) @[dec_tlu_ctl.scala 2395:49] - node _T_2255 = tail(_T_2254, 1) @[dec_tlu_ctl.scala 2395:49] - mhpmc5_incr <= _T_2255 @[dec_tlu_ctl.scala 2395:14] - node _T_2256 = bits(mhpmc5_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2396:36] - node _T_2257 = bits(mhpmc5_incr, 31, 0) @[dec_tlu_ctl.scala 2396:76] - node mhpmc5_ns = mux(_T_2256, io.dec_csr_wrdata_r, _T_2257) @[dec_tlu_ctl.scala 2396:21] - node _T_2258 = bits(mhpmc5_wr_en, 0, 0) @[dec_tlu_ctl.scala 2398:43] - inst rvclkhdr_30 of rvclkhdr_750 @[el2_lib.scala 508:23] + node _T_2242 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2395:28] + node _T_2243 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2395:41] + node _T_2244 = cat(_T_2242, _T_2243) @[Cat.scala 29:58] + node _T_2245 = cat(UInt<63>("h00"), mhpmc_inc_r[2]) @[Cat.scala 29:58] + node _T_2246 = add(_T_2244, _T_2245) @[dec_tlu_ctl.scala 2395:49] + node _T_2247 = tail(_T_2246, 1) @[dec_tlu_ctl.scala 2395:49] + mhpmc5_incr <= _T_2247 @[dec_tlu_ctl.scala 2395:14] + node _T_2248 = bits(mhpmc5_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2396:36] + node _T_2249 = bits(mhpmc5_incr, 31, 0) @[dec_tlu_ctl.scala 2396:76] + node mhpmc5_ns = mux(_T_2248, io.dec_csr_wrdata_r, _T_2249) @[dec_tlu_ctl.scala 2396:21] + node _T_2250 = bits(mhpmc5_wr_en, 0, 0) @[dec_tlu_ctl.scala 2398:43] + inst rvclkhdr_30 of rvclkhdr_750 @[lib.scala 368:23] rvclkhdr_30.clock <= clock rvclkhdr_30.reset <= reset - rvclkhdr_30.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_30.io.en <= _T_2258 @[el2_lib.scala 511:17] - rvclkhdr_30.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_2259 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_2259 <= mhpmc5_ns @[el2_lib.scala 514:16] - mhpmc5 <= _T_2259 @[dec_tlu_ctl.scala 2398:9] - node _T_2260 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2400:66] - node _T_2261 = eq(_T_2260, UInt<12>("h0b85")) @[dec_tlu_ctl.scala 2400:73] - node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2261) @[dec_tlu_ctl.scala 2400:44] + rvclkhdr_30.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_30.io.en <= _T_2250 @[lib.scala 371:17] + rvclkhdr_30.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_2251 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2251 <= mhpmc5_ns @[lib.scala 374:16] + mhpmc5 <= _T_2251 @[dec_tlu_ctl.scala 2398:9] + node _T_2252 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2400:66] + node _T_2253 = eq(_T_2252, UInt<12>("h0b85")) @[dec_tlu_ctl.scala 2400:73] + node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2253) @[dec_tlu_ctl.scala 2400:44] node mhpmc5h_wr_en = or(mhpmc5h_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2401:38] - node _T_2262 = bits(mhpmc5h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2402:38] - node _T_2263 = bits(mhpmc5_incr, 63, 32) @[dec_tlu_ctl.scala 2402:78] - node mhpmc5h_ns = mux(_T_2262, io.dec_csr_wrdata_r, _T_2263) @[dec_tlu_ctl.scala 2402:22] - node _T_2264 = bits(mhpmc5h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2404:46] - inst rvclkhdr_31 of rvclkhdr_751 @[el2_lib.scala 508:23] + node _T_2254 = bits(mhpmc5h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2402:38] + node _T_2255 = bits(mhpmc5_incr, 63, 32) @[dec_tlu_ctl.scala 2402:78] + node mhpmc5h_ns = mux(_T_2254, io.dec_csr_wrdata_r, _T_2255) @[dec_tlu_ctl.scala 2402:22] + node _T_2256 = bits(mhpmc5h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2404:46] + inst rvclkhdr_31 of rvclkhdr_751 @[lib.scala 368:23] rvclkhdr_31.clock <= clock rvclkhdr_31.reset <= reset - rvclkhdr_31.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_31.io.en <= _T_2264 @[el2_lib.scala 511:17] - rvclkhdr_31.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_2265 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_2265 <= mhpmc5h_ns @[el2_lib.scala 514:16] - mhpmc5h <= _T_2265 @[dec_tlu_ctl.scala 2404:10] - node _T_2266 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2409:65] - node _T_2267 = eq(_T_2266, UInt<12>("h0b06")) @[dec_tlu_ctl.scala 2409:72] - node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2267) @[dec_tlu_ctl.scala 2409:43] - node _T_2268 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2410:23] - node _T_2269 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2410:61] - node _T_2270 = or(_T_2268, _T_2269) @[dec_tlu_ctl.scala 2410:39] - node _T_2271 = orr(mhpmc_inc_r[3]) @[dec_tlu_ctl.scala 2410:86] - node mhpmc6_wr_en1 = and(_T_2270, _T_2271) @[dec_tlu_ctl.scala 2410:66] + rvclkhdr_31.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_31.io.en <= _T_2256 @[lib.scala 371:17] + rvclkhdr_31.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_2257 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2257 <= mhpmc5h_ns @[lib.scala 374:16] + mhpmc5h <= _T_2257 @[dec_tlu_ctl.scala 2404:10] + node _T_2258 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2409:65] + node _T_2259 = eq(_T_2258, UInt<12>("h0b06")) @[dec_tlu_ctl.scala 2409:72] + node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2259) @[dec_tlu_ctl.scala 2409:43] + node _T_2260 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2410:23] + node _T_2261 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2410:61] + node _T_2262 = or(_T_2260, _T_2261) @[dec_tlu_ctl.scala 2410:39] + node _T_2263 = orr(mhpmc_inc_r[3]) @[dec_tlu_ctl.scala 2410:86] + node mhpmc6_wr_en1 = and(_T_2262, _T_2263) @[dec_tlu_ctl.scala 2410:66] node mhpmc6_wr_en = or(mhpmc6_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2411:36] - node _T_2272 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2413:28] - node _T_2273 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2413:41] - node _T_2274 = cat(_T_2272, _T_2273) @[Cat.scala 29:58] - node _T_2275 = cat(UInt<63>("h00"), mhpmc_inc_r[3]) @[Cat.scala 29:58] - node _T_2276 = add(_T_2274, _T_2275) @[dec_tlu_ctl.scala 2413:49] - node _T_2277 = tail(_T_2276, 1) @[dec_tlu_ctl.scala 2413:49] - mhpmc6_incr <= _T_2277 @[dec_tlu_ctl.scala 2413:14] - node _T_2278 = bits(mhpmc6_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2414:36] - node _T_2279 = bits(mhpmc6_incr, 31, 0) @[dec_tlu_ctl.scala 2414:76] - node mhpmc6_ns = mux(_T_2278, io.dec_csr_wrdata_r, _T_2279) @[dec_tlu_ctl.scala 2414:21] - node _T_2280 = bits(mhpmc6_wr_en, 0, 0) @[dec_tlu_ctl.scala 2416:43] - inst rvclkhdr_32 of rvclkhdr_752 @[el2_lib.scala 508:23] + node _T_2264 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2413:28] + node _T_2265 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2413:41] + node _T_2266 = cat(_T_2264, _T_2265) @[Cat.scala 29:58] + node _T_2267 = cat(UInt<63>("h00"), mhpmc_inc_r[3]) @[Cat.scala 29:58] + node _T_2268 = add(_T_2266, _T_2267) @[dec_tlu_ctl.scala 2413:49] + node _T_2269 = tail(_T_2268, 1) @[dec_tlu_ctl.scala 2413:49] + mhpmc6_incr <= _T_2269 @[dec_tlu_ctl.scala 2413:14] + node _T_2270 = bits(mhpmc6_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2414:36] + node _T_2271 = bits(mhpmc6_incr, 31, 0) @[dec_tlu_ctl.scala 2414:76] + node mhpmc6_ns = mux(_T_2270, io.dec_csr_wrdata_r, _T_2271) @[dec_tlu_ctl.scala 2414:21] + node _T_2272 = bits(mhpmc6_wr_en, 0, 0) @[dec_tlu_ctl.scala 2416:43] + inst rvclkhdr_32 of rvclkhdr_752 @[lib.scala 368:23] rvclkhdr_32.clock <= clock rvclkhdr_32.reset <= reset - rvclkhdr_32.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_32.io.en <= _T_2280 @[el2_lib.scala 511:17] - rvclkhdr_32.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_2281 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_2281 <= mhpmc6_ns @[el2_lib.scala 514:16] - mhpmc6 <= _T_2281 @[dec_tlu_ctl.scala 2416:9] - node _T_2282 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2418:66] - node _T_2283 = eq(_T_2282, UInt<12>("h0b86")) @[dec_tlu_ctl.scala 2418:73] - node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2283) @[dec_tlu_ctl.scala 2418:44] + rvclkhdr_32.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_32.io.en <= _T_2272 @[lib.scala 371:17] + rvclkhdr_32.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_2273 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2273 <= mhpmc6_ns @[lib.scala 374:16] + mhpmc6 <= _T_2273 @[dec_tlu_ctl.scala 2416:9] + node _T_2274 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2418:66] + node _T_2275 = eq(_T_2274, UInt<12>("h0b86")) @[dec_tlu_ctl.scala 2418:73] + node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2275) @[dec_tlu_ctl.scala 2418:44] node mhpmc6h_wr_en = or(mhpmc6h_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2419:38] - node _T_2284 = bits(mhpmc6h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2420:38] - node _T_2285 = bits(mhpmc6_incr, 63, 32) @[dec_tlu_ctl.scala 2420:78] - node mhpmc6h_ns = mux(_T_2284, io.dec_csr_wrdata_r, _T_2285) @[dec_tlu_ctl.scala 2420:22] - node _T_2286 = bits(mhpmc6h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2422:46] - inst rvclkhdr_33 of rvclkhdr_753 @[el2_lib.scala 508:23] + node _T_2276 = bits(mhpmc6h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2420:38] + node _T_2277 = bits(mhpmc6_incr, 63, 32) @[dec_tlu_ctl.scala 2420:78] + node mhpmc6h_ns = mux(_T_2276, io.dec_csr_wrdata_r, _T_2277) @[dec_tlu_ctl.scala 2420:22] + node _T_2278 = bits(mhpmc6h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2422:46] + inst rvclkhdr_33 of rvclkhdr_753 @[lib.scala 368:23] rvclkhdr_33.clock <= clock rvclkhdr_33.reset <= reset - rvclkhdr_33.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_33.io.en <= _T_2286 @[el2_lib.scala 511:17] - rvclkhdr_33.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_2287 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_2287 <= mhpmc6h_ns @[el2_lib.scala 514:16] - mhpmc6h <= _T_2287 @[dec_tlu_ctl.scala 2422:10] - node _T_2288 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2429:50] - node _T_2289 = gt(_T_2288, UInt<10>("h0204")) @[dec_tlu_ctl.scala 2429:56] - node _T_2290 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 2429:93] - node _T_2291 = orr(_T_2290) @[dec_tlu_ctl.scala 2429:102] - node _T_2292 = or(_T_2289, _T_2291) @[dec_tlu_ctl.scala 2429:71] - node _T_2293 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2429:141] - node event_saturate_r = mux(_T_2292, UInt<10>("h0204"), _T_2293) @[dec_tlu_ctl.scala 2429:28] - node _T_2294 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2431:63] - node _T_2295 = eq(_T_2294, UInt<12>("h0323")) @[dec_tlu_ctl.scala 2431:70] - node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_2295) @[dec_tlu_ctl.scala 2431:41] - node _T_2296 = bits(wr_mhpme3_r, 0, 0) @[dec_tlu_ctl.scala 2433:80] + rvclkhdr_33.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_33.io.en <= _T_2278 @[lib.scala 371:17] + rvclkhdr_33.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_2279 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2279 <= mhpmc6h_ns @[lib.scala 374:16] + mhpmc6h <= _T_2279 @[dec_tlu_ctl.scala 2422:10] + node _T_2280 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2429:50] + node _T_2281 = gt(_T_2280, UInt<10>("h0204")) @[dec_tlu_ctl.scala 2429:56] + node _T_2282 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 2429:93] + node _T_2283 = orr(_T_2282) @[dec_tlu_ctl.scala 2429:102] + node _T_2284 = or(_T_2281, _T_2283) @[dec_tlu_ctl.scala 2429:71] + node _T_2285 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2429:141] + node event_saturate_r = mux(_T_2284, UInt<10>("h0204"), _T_2285) @[dec_tlu_ctl.scala 2429:28] + node _T_2286 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2431:63] + node _T_2287 = eq(_T_2286, UInt<12>("h0323")) @[dec_tlu_ctl.scala 2431:70] + node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_2287) @[dec_tlu_ctl.scala 2431:41] + node _T_2288 = bits(wr_mhpme3_r, 0, 0) @[dec_tlu_ctl.scala 2433:80] + reg _T_2289 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2288 : @[Reg.scala 28:19] + _T_2289 <= event_saturate_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mhpme3 <= _T_2289 @[dec_tlu_ctl.scala 2433:9] + node _T_2290 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2438:63] + node _T_2291 = eq(_T_2290, UInt<12>("h0324")) @[dec_tlu_ctl.scala 2438:70] + node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_2291) @[dec_tlu_ctl.scala 2438:41] + node _T_2292 = bits(wr_mhpme4_r, 0, 0) @[dec_tlu_ctl.scala 2439:80] + reg _T_2293 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2292 : @[Reg.scala 28:19] + _T_2293 <= event_saturate_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mhpme4 <= _T_2293 @[dec_tlu_ctl.scala 2439:9] + node _T_2294 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2445:63] + node _T_2295 = eq(_T_2294, UInt<12>("h0325")) @[dec_tlu_ctl.scala 2445:70] + node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_2295) @[dec_tlu_ctl.scala 2445:41] + node _T_2296 = bits(wr_mhpme5_r, 0, 0) @[dec_tlu_ctl.scala 2446:80] reg _T_2297 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_2296 : @[Reg.scala 28:19] _T_2297 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme3 <= _T_2297 @[dec_tlu_ctl.scala 2433:9] - node _T_2298 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2438:63] - node _T_2299 = eq(_T_2298, UInt<12>("h0324")) @[dec_tlu_ctl.scala 2438:70] - node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_2299) @[dec_tlu_ctl.scala 2438:41] - node _T_2300 = bits(wr_mhpme4_r, 0, 0) @[dec_tlu_ctl.scala 2439:80] + mhpme5 <= _T_2297 @[dec_tlu_ctl.scala 2446:9] + node _T_2298 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2452:63] + node _T_2299 = eq(_T_2298, UInt<12>("h0326")) @[dec_tlu_ctl.scala 2452:70] + node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_2299) @[dec_tlu_ctl.scala 2452:41] + node _T_2300 = bits(wr_mhpme6_r, 0, 0) @[dec_tlu_ctl.scala 2453:80] reg _T_2301 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_2300 : @[Reg.scala 28:19] _T_2301 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme4 <= _T_2301 @[dec_tlu_ctl.scala 2439:9] - node _T_2302 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2445:63] - node _T_2303 = eq(_T_2302, UInt<12>("h0325")) @[dec_tlu_ctl.scala 2445:70] - node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_2303) @[dec_tlu_ctl.scala 2445:41] - node _T_2304 = bits(wr_mhpme5_r, 0, 0) @[dec_tlu_ctl.scala 2446:80] - reg _T_2305 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2304 : @[Reg.scala 28:19] - _T_2305 <= event_saturate_r @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - mhpme5 <= _T_2305 @[dec_tlu_ctl.scala 2446:9] - node _T_2306 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2452:63] - node _T_2307 = eq(_T_2306, UInt<12>("h0326")) @[dec_tlu_ctl.scala 2452:70] - node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_2307) @[dec_tlu_ctl.scala 2452:41] - node _T_2308 = bits(wr_mhpme6_r, 0, 0) @[dec_tlu_ctl.scala 2453:80] + mhpme6 <= _T_2301 @[dec_tlu_ctl.scala 2453:9] + node _T_2302 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2469:70] + node _T_2303 = eq(_T_2302, UInt<12>("h0320")) @[dec_tlu_ctl.scala 2469:77] + node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_2303) @[dec_tlu_ctl.scala 2469:48] + node _T_2304 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2471:54] + wire temp_ncount0 : UInt<1> + temp_ncount0 <= _T_2304 + node _T_2305 = bits(mcountinhibit, 1, 1) @[dec_tlu_ctl.scala 2472:54] + wire temp_ncount1 : UInt<1> + temp_ncount1 <= _T_2305 + node _T_2306 = bits(mcountinhibit, 6, 2) @[dec_tlu_ctl.scala 2473:55] + wire temp_ncount6_2 : UInt<5> + temp_ncount6_2 <= _T_2306 + node _T_2307 = bits(io.dec_csr_wrdata_r, 6, 2) @[dec_tlu_ctl.scala 2474:74] + node _T_2308 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2474:103] reg _T_2309 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_2308 : @[Reg.scala 28:19] - _T_2309 <= event_saturate_r @[Reg.scala 28:23] + _T_2309 <= _T_2307 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme6 <= _T_2309 @[dec_tlu_ctl.scala 2453:9] - node _T_2310 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2469:70] - node _T_2311 = eq(_T_2310, UInt<12>("h0320")) @[dec_tlu_ctl.scala 2469:77] - node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_2311) @[dec_tlu_ctl.scala 2469:48] - node _T_2312 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2471:54] - wire temp_ncount0 : UInt<1> - temp_ncount0 <= _T_2312 - node _T_2313 = bits(mcountinhibit, 1, 1) @[dec_tlu_ctl.scala 2472:54] - wire temp_ncount1 : UInt<1> - temp_ncount1 <= _T_2313 - node _T_2314 = bits(mcountinhibit, 6, 2) @[dec_tlu_ctl.scala 2473:55] - wire temp_ncount6_2 : UInt<5> - temp_ncount6_2 <= _T_2314 - node _T_2315 = bits(io.dec_csr_wrdata_r, 6, 2) @[dec_tlu_ctl.scala 2474:74] - node _T_2316 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2474:103] - reg _T_2317 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2316 : @[Reg.scala 28:19] - _T_2317 <= _T_2315 @[Reg.scala 28:23] + temp_ncount6_2 <= _T_2309 @[dec_tlu_ctl.scala 2474:17] + node _T_2310 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2476:72] + node _T_2311 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2476:99] + reg _T_2312 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2311 : @[Reg.scala 28:19] + _T_2312 <= _T_2310 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - temp_ncount6_2 <= _T_2317 @[dec_tlu_ctl.scala 2474:17] - node _T_2318 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2476:72] - node _T_2319 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2476:99] - reg _T_2320 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2319 : @[Reg.scala 28:19] - _T_2320 <= _T_2318 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - temp_ncount0 <= _T_2320 @[dec_tlu_ctl.scala 2476:15] - node _T_2321 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2322 = cat(_T_2321, temp_ncount0) @[Cat.scala 29:58] - mcountinhibit <= _T_2322 @[dec_tlu_ctl.scala 2477:16] - node _T_2323 = or(io.i0_valid_wb, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 2484:51] - node _T_2324 = or(_T_2323, io.interrupt_valid_r_d1) @[dec_tlu_ctl.scala 2484:78] - node _T_2325 = or(_T_2324, io.dec_tlu_i0_valid_wb1) @[dec_tlu_ctl.scala 2484:104] - node _T_2326 = or(_T_2325, io.dec_tlu_i0_exc_valid_wb1) @[dec_tlu_ctl.scala 2484:130] - node _T_2327 = or(_T_2326, io.dec_tlu_int_valid_wb1) @[dec_tlu_ctl.scala 2485:32] - node _T_2328 = or(_T_2327, io.clk_override) @[dec_tlu_ctl.scala 2485:59] - node _T_2329 = bits(_T_2328, 0, 0) @[dec_tlu_ctl.scala 2485:78] - inst rvclkhdr_34 of rvclkhdr_754 @[el2_lib.scala 483:22] + temp_ncount0 <= _T_2312 @[dec_tlu_ctl.scala 2476:15] + node _T_2313 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2314 = cat(_T_2313, temp_ncount0) @[Cat.scala 29:58] + mcountinhibit <= _T_2314 @[dec_tlu_ctl.scala 2477:16] + node _T_2315 = or(io.i0_valid_wb, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 2484:51] + node _T_2316 = or(_T_2315, io.interrupt_valid_r_d1) @[dec_tlu_ctl.scala 2484:78] + node _T_2317 = or(_T_2316, io.dec_tlu_i0_valid_wb1) @[dec_tlu_ctl.scala 2484:104] + node _T_2318 = or(_T_2317, io.dec_tlu_i0_exc_valid_wb1) @[dec_tlu_ctl.scala 2484:130] + node _T_2319 = or(_T_2318, io.dec_tlu_int_valid_wb1) @[dec_tlu_ctl.scala 2485:32] + node _T_2320 = or(_T_2319, io.clk_override) @[dec_tlu_ctl.scala 2485:59] + node _T_2321 = bits(_T_2320, 0, 0) @[dec_tlu_ctl.scala 2485:78] + inst rvclkhdr_34 of rvclkhdr_754 @[lib.scala 343:22] rvclkhdr_34.clock <= clock rvclkhdr_34.reset <= reset - rvclkhdr_34.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_34.io.en <= _T_2329 @[el2_lib.scala 485:16] - rvclkhdr_34.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - reg _T_2330 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2487:62] - _T_2330 <= io.i0_valid_wb @[dec_tlu_ctl.scala 2487:62] - io.dec_tlu_i0_valid_wb1 <= _T_2330 @[dec_tlu_ctl.scala 2487:30] - node _T_2331 = or(io.i0_exception_valid_r_d1, io.lsu_i0_exc_r_d1) @[dec_tlu_ctl.scala 2488:91] - node _T_2332 = not(io.trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 2488:137] - node _T_2333 = and(io.trigger_hit_r_d1, _T_2332) @[dec_tlu_ctl.scala 2488:135] - node _T_2334 = or(_T_2331, _T_2333) @[dec_tlu_ctl.scala 2488:112] - reg _T_2335 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2488:62] - _T_2335 <= _T_2334 @[dec_tlu_ctl.scala 2488:62] - io.dec_tlu_i0_exc_valid_wb1 <= _T_2335 @[dec_tlu_ctl.scala 2488:30] - reg _T_2336 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2489:62] - _T_2336 <= io.exc_cause_wb @[dec_tlu_ctl.scala 2489:62] - io.dec_tlu_exc_cause_wb1 <= _T_2336 @[dec_tlu_ctl.scala 2489:30] - reg _T_2337 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2490:62] - _T_2337 <= io.interrupt_valid_r_d1 @[dec_tlu_ctl.scala 2490:62] - io.dec_tlu_int_valid_wb1 <= _T_2337 @[dec_tlu_ctl.scala 2490:30] + rvclkhdr_34.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_34.io.en <= _T_2321 @[lib.scala 345:16] + rvclkhdr_34.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + reg _T_2322 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2487:62] + _T_2322 <= io.i0_valid_wb @[dec_tlu_ctl.scala 2487:62] + io.dec_tlu_i0_valid_wb1 <= _T_2322 @[dec_tlu_ctl.scala 2487:30] + node _T_2323 = or(io.i0_exception_valid_r_d1, io.lsu_i0_exc_r_d1) @[dec_tlu_ctl.scala 2488:91] + node _T_2324 = not(io.trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 2488:137] + node _T_2325 = and(io.trigger_hit_r_d1, _T_2324) @[dec_tlu_ctl.scala 2488:135] + node _T_2326 = or(_T_2323, _T_2325) @[dec_tlu_ctl.scala 2488:112] + reg _T_2327 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2488:62] + _T_2327 <= _T_2326 @[dec_tlu_ctl.scala 2488:62] + io.dec_tlu_i0_exc_valid_wb1 <= _T_2327 @[dec_tlu_ctl.scala 2488:30] + reg _T_2328 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2489:62] + _T_2328 <= io.exc_cause_wb @[dec_tlu_ctl.scala 2489:62] + io.dec_tlu_exc_cause_wb1 <= _T_2328 @[dec_tlu_ctl.scala 2489:30] + reg _T_2329 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2490:62] + _T_2329 <= io.interrupt_valid_r_d1 @[dec_tlu_ctl.scala 2490:62] + io.dec_tlu_int_valid_wb1 <= _T_2329 @[dec_tlu_ctl.scala 2490:30] io.dec_tlu_mtval_wb1 <= mtval @[dec_tlu_ctl.scala 2492:24] - node _T_2338 = bits(io.csr_pkt.csr_misa, 0, 0) @[dec_tlu_ctl.scala 2498:61] - node _T_2339 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[dec_tlu_ctl.scala 2499:42] - node _T_2340 = bits(io.csr_pkt.csr_marchid, 0, 0) @[dec_tlu_ctl.scala 2500:40] - node _T_2341 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[dec_tlu_ctl.scala 2501:39] - node _T_2342 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[dec_tlu_ctl.scala 2502:40] - node _T_2343 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58] - node _T_2344 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[dec_tlu_ctl.scala 2503:40] - node _T_2345 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 2503:103] - node _T_2346 = bits(io.mstatus, 0, 0) @[dec_tlu_ctl.scala 2503:128] - node _T_2347 = cat(UInt<3>("h00"), _T_2346) @[Cat.scala 29:58] - node _T_2348 = cat(_T_2347, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2349 = cat(UInt<3>("h00"), _T_2345) @[Cat.scala 29:58] - node _T_2350 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58] - node _T_2351 = cat(_T_2350, _T_2349) @[Cat.scala 29:58] - node _T_2352 = cat(_T_2351, _T_2348) @[Cat.scala 29:58] - node _T_2353 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[dec_tlu_ctl.scala 2504:38] - node _T_2354 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 2504:70] - node _T_2355 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 2504:96] - node _T_2356 = cat(_T_2354, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2330 = bits(io.csr_pkt.csr_misa, 0, 0) @[dec_tlu_ctl.scala 2498:61] + node _T_2331 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[dec_tlu_ctl.scala 2499:42] + node _T_2332 = bits(io.csr_pkt.csr_marchid, 0, 0) @[dec_tlu_ctl.scala 2500:40] + node _T_2333 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[dec_tlu_ctl.scala 2501:39] + node _T_2334 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[dec_tlu_ctl.scala 2502:40] + node _T_2335 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_2336 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[dec_tlu_ctl.scala 2503:40] + node _T_2337 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 2503:103] + node _T_2338 = bits(io.mstatus, 0, 0) @[dec_tlu_ctl.scala 2503:128] + node _T_2339 = cat(UInt<3>("h00"), _T_2338) @[Cat.scala 29:58] + node _T_2340 = cat(_T_2339, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2341 = cat(UInt<3>("h00"), _T_2337) @[Cat.scala 29:58] + node _T_2342 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58] + node _T_2343 = cat(_T_2342, _T_2341) @[Cat.scala 29:58] + node _T_2344 = cat(_T_2343, _T_2340) @[Cat.scala 29:58] + node _T_2345 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[dec_tlu_ctl.scala 2504:38] + node _T_2346 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 2504:70] + node _T_2347 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 2504:96] + node _T_2348 = cat(_T_2346, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2349 = cat(_T_2348, _T_2347) @[Cat.scala 29:58] + node _T_2350 = bits(io.csr_pkt.csr_mip, 0, 0) @[dec_tlu_ctl.scala 2505:36] + node _T_2351 = bits(io.mip, 5, 3) @[dec_tlu_ctl.scala 2505:78] + node _T_2352 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 2505:102] + node _T_2353 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 2505:123] + node _T_2354 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 2505:144] + node _T_2355 = cat(_T_2354, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2356 = cat(_T_2353, UInt<3>("h00")) @[Cat.scala 29:58] node _T_2357 = cat(_T_2356, _T_2355) @[Cat.scala 29:58] - node _T_2358 = bits(io.csr_pkt.csr_mip, 0, 0) @[dec_tlu_ctl.scala 2505:36] - node _T_2359 = bits(io.mip, 5, 3) @[dec_tlu_ctl.scala 2505:78] - node _T_2360 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 2505:102] - node _T_2361 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 2505:123] - node _T_2362 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 2505:144] - node _T_2363 = cat(_T_2362, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2364 = cat(_T_2361, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2365 = cat(_T_2364, _T_2363) @[Cat.scala 29:58] - node _T_2366 = cat(_T_2360, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2367 = cat(UInt<1>("h00"), _T_2359) @[Cat.scala 29:58] - node _T_2368 = cat(_T_2367, UInt<16>("h00")) @[Cat.scala 29:58] - node _T_2369 = cat(_T_2368, _T_2366) @[Cat.scala 29:58] - node _T_2370 = cat(_T_2369, _T_2365) @[Cat.scala 29:58] - node _T_2371 = bits(io.csr_pkt.csr_mie, 0, 0) @[dec_tlu_ctl.scala 2506:36] - node _T_2372 = bits(mie, 5, 3) @[dec_tlu_ctl.scala 2506:75] - node _T_2373 = bits(mie, 2, 2) @[dec_tlu_ctl.scala 2506:96] - node _T_2374 = bits(mie, 1, 1) @[dec_tlu_ctl.scala 2506:114] - node _T_2375 = bits(mie, 0, 0) @[dec_tlu_ctl.scala 2506:132] - node _T_2376 = cat(_T_2375, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2377 = cat(_T_2374, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2378 = cat(_T_2377, _T_2376) @[Cat.scala 29:58] - node _T_2379 = cat(_T_2373, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2380 = cat(UInt<1>("h00"), _T_2372) @[Cat.scala 29:58] - node _T_2381 = cat(_T_2380, UInt<16>("h00")) @[Cat.scala 29:58] - node _T_2382 = cat(_T_2381, _T_2379) @[Cat.scala 29:58] - node _T_2383 = cat(_T_2382, _T_2378) @[Cat.scala 29:58] - node _T_2384 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[dec_tlu_ctl.scala 2507:40] - node _T_2385 = bits(mcyclel, 31, 0) @[dec_tlu_ctl.scala 2507:65] - node _T_2386 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[dec_tlu_ctl.scala 2508:40] - node _T_2387 = bits(mcycleh_inc, 31, 0) @[dec_tlu_ctl.scala 2508:69] - node _T_2388 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[dec_tlu_ctl.scala 2509:42] - node _T_2389 = bits(minstretl, 31, 0) @[dec_tlu_ctl.scala 2509:72] - node _T_2390 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[dec_tlu_ctl.scala 2510:42] - node _T_2391 = bits(minstreth_inc, 31, 0) @[dec_tlu_ctl.scala 2510:72] - node _T_2392 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[dec_tlu_ctl.scala 2511:41] - node _T_2393 = bits(mscratch, 31, 0) @[dec_tlu_ctl.scala 2511:66] - node _T_2394 = bits(io.csr_pkt.csr_mepc, 0, 0) @[dec_tlu_ctl.scala 2512:37] - node _T_2395 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2396 = bits(io.csr_pkt.csr_mcause, 0, 0) @[dec_tlu_ctl.scala 2513:39] - node _T_2397 = bits(mcause, 31, 0) @[dec_tlu_ctl.scala 2513:64] - node _T_2398 = bits(io.csr_pkt.csr_mscause, 0, 0) @[dec_tlu_ctl.scala 2514:40] - node _T_2399 = bits(mscause, 3, 0) @[dec_tlu_ctl.scala 2514:80] - node _T_2400 = cat(UInt<28>("h00"), _T_2399) @[Cat.scala 29:58] - node _T_2401 = bits(io.csr_pkt.csr_mtval, 0, 0) @[dec_tlu_ctl.scala 2515:38] - node _T_2402 = bits(mtval, 31, 0) @[dec_tlu_ctl.scala 2515:63] - node _T_2403 = bits(io.csr_pkt.csr_mrac, 0, 0) @[dec_tlu_ctl.scala 2516:37] - node _T_2404 = bits(mrac, 31, 0) @[dec_tlu_ctl.scala 2516:62] - node _T_2405 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[dec_tlu_ctl.scala 2517:39] - node _T_2406 = bits(mdseac, 31, 0) @[dec_tlu_ctl.scala 2517:64] - node _T_2407 = bits(io.csr_pkt.csr_meivt, 0, 0) @[dec_tlu_ctl.scala 2518:38] - node _T_2408 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58] - node _T_2409 = bits(io.csr_pkt.csr_meihap, 0, 0) @[dec_tlu_ctl.scala 2519:39] - node _T_2410 = cat(meivt, meihap) @[Cat.scala 29:58] - node _T_2411 = cat(_T_2410, UInt<2>("h00")) @[Cat.scala 29:58] - node _T_2412 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[dec_tlu_ctl.scala 2520:41] - node _T_2413 = bits(meicurpl, 3, 0) @[dec_tlu_ctl.scala 2520:81] - node _T_2414 = cat(UInt<28>("h00"), _T_2413) @[Cat.scala 29:58] - node _T_2415 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[dec_tlu_ctl.scala 2521:41] - node _T_2416 = bits(meicidpl, 3, 0) @[dec_tlu_ctl.scala 2521:81] - node _T_2417 = cat(UInt<28>("h00"), _T_2416) @[Cat.scala 29:58] - node _T_2418 = bits(io.csr_pkt.csr_meipt, 0, 0) @[dec_tlu_ctl.scala 2522:38] - node _T_2419 = bits(meipt, 3, 0) @[dec_tlu_ctl.scala 2522:78] - node _T_2420 = cat(UInt<28>("h00"), _T_2419) @[Cat.scala 29:58] - node _T_2421 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[dec_tlu_ctl.scala 2523:37] - node _T_2422 = bits(mcgc, 8, 0) @[dec_tlu_ctl.scala 2523:77] - node _T_2423 = cat(UInt<23>("h00"), _T_2422) @[Cat.scala 29:58] - node _T_2424 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[dec_tlu_ctl.scala 2524:37] - node _T_2425 = bits(mfdc, 18, 0) @[dec_tlu_ctl.scala 2524:77] - node _T_2426 = cat(UInt<13>("h00"), _T_2425) @[Cat.scala 29:58] - node _T_2427 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[dec_tlu_ctl.scala 2525:37] - node _T_2428 = bits(io.dcsr, 15, 2) @[dec_tlu_ctl.scala 2525:85] - node _T_2429 = cat(UInt<16>("h04000"), _T_2428) @[Cat.scala 29:58] - node _T_2430 = cat(_T_2429, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_2431 = bits(io.csr_pkt.csr_dpc, 0, 0) @[dec_tlu_ctl.scala 2526:36] - node _T_2432 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2433 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[dec_tlu_ctl.scala 2527:39] - node _T_2434 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2527:64] - node _T_2435 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[dec_tlu_ctl.scala 2528:40] - node _T_2436 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2528:65] - node _T_2437 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[dec_tlu_ctl.scala 2529:39] - node _T_2438 = bits(dicad1, 31, 0) @[dec_tlu_ctl.scala 2529:64] - node _T_2439 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[dec_tlu_ctl.scala 2530:41] - node _T_2440 = bits(dicawics, 16, 16) @[dec_tlu_ctl.scala 2530:80] - node _T_2441 = bits(dicawics, 15, 14) @[dec_tlu_ctl.scala 2530:104] - node _T_2442 = bits(dicawics, 13, 0) @[dec_tlu_ctl.scala 2530:131] - node _T_2443 = cat(UInt<3>("h00"), _T_2442) @[Cat.scala 29:58] - node _T_2444 = cat(_T_2443, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2445 = cat(UInt<2>("h00"), _T_2441) @[Cat.scala 29:58] - node _T_2446 = cat(UInt<7>("h00"), _T_2440) @[Cat.scala 29:58] - node _T_2447 = cat(_T_2446, _T_2445) @[Cat.scala 29:58] - node _T_2448 = cat(_T_2447, _T_2444) @[Cat.scala 29:58] - node _T_2449 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[dec_tlu_ctl.scala 2531:38] - node _T_2450 = bits(mtsel, 1, 0) @[dec_tlu_ctl.scala 2531:78] - node _T_2451 = cat(UInt<30>("h00"), _T_2450) @[Cat.scala 29:58] - node _T_2452 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[dec_tlu_ctl.scala 2532:40] - node _T_2453 = bits(mtdata1_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2532:74] - node _T_2454 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[dec_tlu_ctl.scala 2533:40] - node _T_2455 = bits(mtdata2_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2533:74] - node _T_2456 = bits(io.csr_pkt.csr_micect, 0, 0) @[dec_tlu_ctl.scala 2534:39] - node _T_2457 = bits(micect, 31, 0) @[dec_tlu_ctl.scala 2534:64] - node _T_2458 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[dec_tlu_ctl.scala 2535:41] - node _T_2459 = bits(miccmect, 31, 0) @[dec_tlu_ctl.scala 2535:66] - node _T_2460 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[dec_tlu_ctl.scala 2536:41] - node _T_2461 = bits(mdccmect, 31, 0) @[dec_tlu_ctl.scala 2536:66] - node _T_2462 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[dec_tlu_ctl.scala 2537:39] - node _T_2463 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2537:64] - node _T_2464 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[dec_tlu_ctl.scala 2538:39] - node _T_2465 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2538:64] - node _T_2466 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[dec_tlu_ctl.scala 2539:39] - node _T_2467 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2539:64] - node _T_2468 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[dec_tlu_ctl.scala 2540:39] - node _T_2469 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2540:64] - node _T_2470 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[dec_tlu_ctl.scala 2541:40] - node _T_2471 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2541:65] - node _T_2472 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[dec_tlu_ctl.scala 2542:40] - node _T_2473 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2542:65] - node _T_2474 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[dec_tlu_ctl.scala 2543:40] - node _T_2475 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2543:65] - node _T_2476 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[dec_tlu_ctl.scala 2544:40] - node _T_2477 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2544:65] - node _T_2478 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[dec_tlu_ctl.scala 2545:38] - node _T_2479 = bits(mfdht, 5, 0) @[dec_tlu_ctl.scala 2545:78] - node _T_2480 = cat(UInt<26>("h00"), _T_2479) @[Cat.scala 29:58] - node _T_2481 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[dec_tlu_ctl.scala 2546:38] - node _T_2482 = bits(mfdhs, 1, 0) @[dec_tlu_ctl.scala 2546:78] - node _T_2483 = cat(UInt<30>("h00"), _T_2482) @[Cat.scala 29:58] - node _T_2484 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[dec_tlu_ctl.scala 2547:39] - node _T_2485 = bits(mhpme3, 9, 0) @[dec_tlu_ctl.scala 2547:79] - node _T_2486 = cat(UInt<22>("h00"), _T_2485) @[Cat.scala 29:58] - node _T_2487 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[dec_tlu_ctl.scala 2548:39] - node _T_2488 = bits(mhpme4, 9, 0) @[dec_tlu_ctl.scala 2548:79] - node _T_2489 = cat(UInt<22>("h00"), _T_2488) @[Cat.scala 29:58] - node _T_2490 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[dec_tlu_ctl.scala 2549:39] - node _T_2491 = bits(mhpme5, 9, 0) @[dec_tlu_ctl.scala 2549:78] - node _T_2492 = cat(UInt<22>("h00"), _T_2491) @[Cat.scala 29:58] - node _T_2493 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[dec_tlu_ctl.scala 2550:39] - node _T_2494 = bits(mhpme6, 9, 0) @[dec_tlu_ctl.scala 2550:78] - node _T_2495 = cat(UInt<22>("h00"), _T_2494) @[Cat.scala 29:58] - node _T_2496 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2551:46] - node _T_2497 = bits(mcountinhibit, 6, 0) @[dec_tlu_ctl.scala 2551:86] - node _T_2498 = cat(UInt<25>("h00"), _T_2497) @[Cat.scala 29:58] - node _T_2499 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[dec_tlu_ctl.scala 2552:37] - node _T_2500 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58] - node _T_2501 = cat(_T_2500, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2502 = bits(io.dec_timer_read_d, 0, 0) @[dec_tlu_ctl.scala 2553:37] - node _T_2503 = bits(io.dec_timer_rddata_d, 31, 0) @[dec_tlu_ctl.scala 2553:76] - node _T_2504 = mux(_T_2338, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2505 = mux(_T_2339, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2506 = mux(_T_2340, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2507 = mux(_T_2341, UInt<32>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2508 = mux(_T_2342, _T_2343, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2509 = mux(_T_2344, _T_2352, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2510 = mux(_T_2353, _T_2357, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2511 = mux(_T_2358, _T_2370, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2512 = mux(_T_2371, _T_2383, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2513 = mux(_T_2384, _T_2385, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2514 = mux(_T_2386, _T_2387, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2515 = mux(_T_2388, _T_2389, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2516 = mux(_T_2390, _T_2391, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2517 = mux(_T_2392, _T_2393, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2518 = mux(_T_2394, _T_2395, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2519 = mux(_T_2396, _T_2397, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2520 = mux(_T_2398, _T_2400, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2521 = mux(_T_2401, _T_2402, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2522 = mux(_T_2403, _T_2404, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2523 = mux(_T_2405, _T_2406, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2524 = mux(_T_2407, _T_2408, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2525 = mux(_T_2409, _T_2411, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2526 = mux(_T_2412, _T_2414, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2527 = mux(_T_2415, _T_2417, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2528 = mux(_T_2418, _T_2420, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2529 = mux(_T_2421, _T_2423, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2530 = mux(_T_2424, _T_2426, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2531 = mux(_T_2427, _T_2430, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2532 = mux(_T_2431, _T_2432, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2533 = mux(_T_2433, _T_2434, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2534 = mux(_T_2435, _T_2436, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2535 = mux(_T_2437, _T_2438, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2536 = mux(_T_2439, _T_2448, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2537 = mux(_T_2449, _T_2451, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2538 = mux(_T_2452, _T_2453, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2539 = mux(_T_2454, _T_2455, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2540 = mux(_T_2456, _T_2457, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2541 = mux(_T_2458, _T_2459, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2542 = mux(_T_2460, _T_2461, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2543 = mux(_T_2462, _T_2463, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2544 = mux(_T_2464, _T_2465, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2545 = mux(_T_2466, _T_2467, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2546 = mux(_T_2468, _T_2469, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2547 = mux(_T_2470, _T_2471, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2548 = mux(_T_2472, _T_2473, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2549 = mux(_T_2474, _T_2475, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2550 = mux(_T_2476, _T_2477, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2551 = mux(_T_2478, _T_2480, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2552 = mux(_T_2481, _T_2483, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2553 = mux(_T_2484, _T_2486, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2554 = mux(_T_2487, _T_2489, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2555 = mux(_T_2490, _T_2492, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2556 = mux(_T_2493, _T_2495, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2557 = mux(_T_2496, _T_2498, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2558 = mux(_T_2499, _T_2501, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2559 = mux(_T_2502, _T_2503, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2560 = or(_T_2504, _T_2505) @[Mux.scala 27:72] + node _T_2358 = cat(_T_2352, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2359 = cat(UInt<1>("h00"), _T_2351) @[Cat.scala 29:58] + node _T_2360 = cat(_T_2359, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_2361 = cat(_T_2360, _T_2358) @[Cat.scala 29:58] + node _T_2362 = cat(_T_2361, _T_2357) @[Cat.scala 29:58] + node _T_2363 = bits(io.csr_pkt.csr_mie, 0, 0) @[dec_tlu_ctl.scala 2506:36] + node _T_2364 = bits(mie, 5, 3) @[dec_tlu_ctl.scala 2506:75] + node _T_2365 = bits(mie, 2, 2) @[dec_tlu_ctl.scala 2506:96] + node _T_2366 = bits(mie, 1, 1) @[dec_tlu_ctl.scala 2506:114] + node _T_2367 = bits(mie, 0, 0) @[dec_tlu_ctl.scala 2506:132] + node _T_2368 = cat(_T_2367, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2369 = cat(_T_2366, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2370 = cat(_T_2369, _T_2368) @[Cat.scala 29:58] + node _T_2371 = cat(_T_2365, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2372 = cat(UInt<1>("h00"), _T_2364) @[Cat.scala 29:58] + node _T_2373 = cat(_T_2372, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_2374 = cat(_T_2373, _T_2371) @[Cat.scala 29:58] + node _T_2375 = cat(_T_2374, _T_2370) @[Cat.scala 29:58] + node _T_2376 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[dec_tlu_ctl.scala 2507:40] + node _T_2377 = bits(mcyclel, 31, 0) @[dec_tlu_ctl.scala 2507:65] + node _T_2378 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[dec_tlu_ctl.scala 2508:40] + node _T_2379 = bits(mcycleh_inc, 31, 0) @[dec_tlu_ctl.scala 2508:69] + node _T_2380 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[dec_tlu_ctl.scala 2509:42] + node _T_2381 = bits(minstretl, 31, 0) @[dec_tlu_ctl.scala 2509:72] + node _T_2382 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[dec_tlu_ctl.scala 2510:42] + node _T_2383 = bits(minstreth_inc, 31, 0) @[dec_tlu_ctl.scala 2510:72] + node _T_2384 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[dec_tlu_ctl.scala 2511:41] + node _T_2385 = bits(mscratch, 31, 0) @[dec_tlu_ctl.scala 2511:66] + node _T_2386 = bits(io.csr_pkt.csr_mepc, 0, 0) @[dec_tlu_ctl.scala 2512:37] + node _T_2387 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2388 = bits(io.csr_pkt.csr_mcause, 0, 0) @[dec_tlu_ctl.scala 2513:39] + node _T_2389 = bits(mcause, 31, 0) @[dec_tlu_ctl.scala 2513:64] + node _T_2390 = bits(io.csr_pkt.csr_mscause, 0, 0) @[dec_tlu_ctl.scala 2514:40] + node _T_2391 = bits(mscause, 3, 0) @[dec_tlu_ctl.scala 2514:80] + node _T_2392 = cat(UInt<28>("h00"), _T_2391) @[Cat.scala 29:58] + node _T_2393 = bits(io.csr_pkt.csr_mtval, 0, 0) @[dec_tlu_ctl.scala 2515:38] + node _T_2394 = bits(mtval, 31, 0) @[dec_tlu_ctl.scala 2515:63] + node _T_2395 = bits(io.csr_pkt.csr_mrac, 0, 0) @[dec_tlu_ctl.scala 2516:37] + node _T_2396 = bits(mrac, 31, 0) @[dec_tlu_ctl.scala 2516:62] + node _T_2397 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[dec_tlu_ctl.scala 2517:39] + node _T_2398 = bits(mdseac, 31, 0) @[dec_tlu_ctl.scala 2517:64] + node _T_2399 = bits(io.csr_pkt.csr_meivt, 0, 0) @[dec_tlu_ctl.scala 2518:38] + node _T_2400 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58] + node _T_2401 = bits(io.csr_pkt.csr_meihap, 0, 0) @[dec_tlu_ctl.scala 2519:39] + node _T_2402 = cat(meivt, meihap) @[Cat.scala 29:58] + node _T_2403 = cat(_T_2402, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_2404 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[dec_tlu_ctl.scala 2520:41] + node _T_2405 = bits(meicurpl, 3, 0) @[dec_tlu_ctl.scala 2520:81] + node _T_2406 = cat(UInt<28>("h00"), _T_2405) @[Cat.scala 29:58] + node _T_2407 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[dec_tlu_ctl.scala 2521:41] + node _T_2408 = bits(meicidpl, 3, 0) @[dec_tlu_ctl.scala 2521:81] + node _T_2409 = cat(UInt<28>("h00"), _T_2408) @[Cat.scala 29:58] + node _T_2410 = bits(io.csr_pkt.csr_meipt, 0, 0) @[dec_tlu_ctl.scala 2522:38] + node _T_2411 = bits(meipt, 3, 0) @[dec_tlu_ctl.scala 2522:78] + node _T_2412 = cat(UInt<28>("h00"), _T_2411) @[Cat.scala 29:58] + node _T_2413 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[dec_tlu_ctl.scala 2523:37] + node _T_2414 = bits(mcgc, 8, 0) @[dec_tlu_ctl.scala 2523:77] + node _T_2415 = cat(UInt<23>("h00"), _T_2414) @[Cat.scala 29:58] + node _T_2416 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[dec_tlu_ctl.scala 2524:37] + node _T_2417 = bits(mfdc, 18, 0) @[dec_tlu_ctl.scala 2524:77] + node _T_2418 = cat(UInt<13>("h00"), _T_2417) @[Cat.scala 29:58] + node _T_2419 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[dec_tlu_ctl.scala 2525:37] + node _T_2420 = bits(io.dcsr, 15, 2) @[dec_tlu_ctl.scala 2525:85] + node _T_2421 = cat(UInt<16>("h04000"), _T_2420) @[Cat.scala 29:58] + node _T_2422 = cat(_T_2421, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_2423 = bits(io.csr_pkt.csr_dpc, 0, 0) @[dec_tlu_ctl.scala 2526:36] + node _T_2424 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2425 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[dec_tlu_ctl.scala 2527:39] + node _T_2426 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2527:64] + node _T_2427 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[dec_tlu_ctl.scala 2528:40] + node _T_2428 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2528:65] + node _T_2429 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[dec_tlu_ctl.scala 2529:39] + node _T_2430 = bits(dicad1, 31, 0) @[dec_tlu_ctl.scala 2529:64] + node _T_2431 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[dec_tlu_ctl.scala 2530:41] + node _T_2432 = bits(dicawics, 16, 16) @[dec_tlu_ctl.scala 2530:80] + node _T_2433 = bits(dicawics, 15, 14) @[dec_tlu_ctl.scala 2530:104] + node _T_2434 = bits(dicawics, 13, 0) @[dec_tlu_ctl.scala 2530:131] + node _T_2435 = cat(UInt<3>("h00"), _T_2434) @[Cat.scala 29:58] + node _T_2436 = cat(_T_2435, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2437 = cat(UInt<2>("h00"), _T_2433) @[Cat.scala 29:58] + node _T_2438 = cat(UInt<7>("h00"), _T_2432) @[Cat.scala 29:58] + node _T_2439 = cat(_T_2438, _T_2437) @[Cat.scala 29:58] + node _T_2440 = cat(_T_2439, _T_2436) @[Cat.scala 29:58] + node _T_2441 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[dec_tlu_ctl.scala 2531:38] + node _T_2442 = bits(mtsel, 1, 0) @[dec_tlu_ctl.scala 2531:78] + node _T_2443 = cat(UInt<30>("h00"), _T_2442) @[Cat.scala 29:58] + node _T_2444 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[dec_tlu_ctl.scala 2532:40] + node _T_2445 = bits(mtdata1_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2532:74] + node _T_2446 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[dec_tlu_ctl.scala 2533:40] + node _T_2447 = bits(mtdata2_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2533:74] + node _T_2448 = bits(io.csr_pkt.csr_micect, 0, 0) @[dec_tlu_ctl.scala 2534:39] + node _T_2449 = bits(micect, 31, 0) @[dec_tlu_ctl.scala 2534:64] + node _T_2450 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[dec_tlu_ctl.scala 2535:41] + node _T_2451 = bits(miccmect, 31, 0) @[dec_tlu_ctl.scala 2535:66] + node _T_2452 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[dec_tlu_ctl.scala 2536:41] + node _T_2453 = bits(mdccmect, 31, 0) @[dec_tlu_ctl.scala 2536:66] + node _T_2454 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[dec_tlu_ctl.scala 2537:39] + node _T_2455 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2537:64] + node _T_2456 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[dec_tlu_ctl.scala 2538:39] + node _T_2457 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2538:64] + node _T_2458 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[dec_tlu_ctl.scala 2539:39] + node _T_2459 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2539:64] + node _T_2460 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[dec_tlu_ctl.scala 2540:39] + node _T_2461 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2540:64] + node _T_2462 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[dec_tlu_ctl.scala 2541:40] + node _T_2463 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2541:65] + node _T_2464 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[dec_tlu_ctl.scala 2542:40] + node _T_2465 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2542:65] + node _T_2466 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[dec_tlu_ctl.scala 2543:40] + node _T_2467 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2543:65] + node _T_2468 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[dec_tlu_ctl.scala 2544:40] + node _T_2469 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2544:65] + node _T_2470 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[dec_tlu_ctl.scala 2545:38] + node _T_2471 = bits(mfdht, 5, 0) @[dec_tlu_ctl.scala 2545:78] + node _T_2472 = cat(UInt<26>("h00"), _T_2471) @[Cat.scala 29:58] + node _T_2473 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[dec_tlu_ctl.scala 2546:38] + node _T_2474 = bits(mfdhs, 1, 0) @[dec_tlu_ctl.scala 2546:78] + node _T_2475 = cat(UInt<30>("h00"), _T_2474) @[Cat.scala 29:58] + node _T_2476 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[dec_tlu_ctl.scala 2547:39] + node _T_2477 = bits(mhpme3, 9, 0) @[dec_tlu_ctl.scala 2547:79] + node _T_2478 = cat(UInt<22>("h00"), _T_2477) @[Cat.scala 29:58] + node _T_2479 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[dec_tlu_ctl.scala 2548:39] + node _T_2480 = bits(mhpme4, 9, 0) @[dec_tlu_ctl.scala 2548:79] + node _T_2481 = cat(UInt<22>("h00"), _T_2480) @[Cat.scala 29:58] + node _T_2482 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[dec_tlu_ctl.scala 2549:39] + node _T_2483 = bits(mhpme5, 9, 0) @[dec_tlu_ctl.scala 2549:78] + node _T_2484 = cat(UInt<22>("h00"), _T_2483) @[Cat.scala 29:58] + node _T_2485 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[dec_tlu_ctl.scala 2550:39] + node _T_2486 = bits(mhpme6, 9, 0) @[dec_tlu_ctl.scala 2550:78] + node _T_2487 = cat(UInt<22>("h00"), _T_2486) @[Cat.scala 29:58] + node _T_2488 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2551:46] + node _T_2489 = bits(mcountinhibit, 6, 0) @[dec_tlu_ctl.scala 2551:86] + node _T_2490 = cat(UInt<25>("h00"), _T_2489) @[Cat.scala 29:58] + node _T_2491 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[dec_tlu_ctl.scala 2552:37] + node _T_2492 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58] + node _T_2493 = cat(_T_2492, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2494 = bits(io.dec_timer_read_d, 0, 0) @[dec_tlu_ctl.scala 2553:37] + node _T_2495 = bits(io.dec_timer_rddata_d, 31, 0) @[dec_tlu_ctl.scala 2553:76] + node _T_2496 = mux(_T_2330, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2497 = mux(_T_2331, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2498 = mux(_T_2332, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2499 = mux(_T_2333, UInt<32>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2500 = mux(_T_2334, _T_2335, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2501 = mux(_T_2336, _T_2344, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2502 = mux(_T_2345, _T_2349, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2503 = mux(_T_2350, _T_2362, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2504 = mux(_T_2363, _T_2375, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2505 = mux(_T_2376, _T_2377, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2506 = mux(_T_2378, _T_2379, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2507 = mux(_T_2380, _T_2381, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2508 = mux(_T_2382, _T_2383, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2509 = mux(_T_2384, _T_2385, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2510 = mux(_T_2386, _T_2387, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2511 = mux(_T_2388, _T_2389, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2512 = mux(_T_2390, _T_2392, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2513 = mux(_T_2393, _T_2394, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2514 = mux(_T_2395, _T_2396, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2515 = mux(_T_2397, _T_2398, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2516 = mux(_T_2399, _T_2400, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2517 = mux(_T_2401, _T_2403, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2518 = mux(_T_2404, _T_2406, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2519 = mux(_T_2407, _T_2409, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2520 = mux(_T_2410, _T_2412, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2521 = mux(_T_2413, _T_2415, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2522 = mux(_T_2416, _T_2418, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2523 = mux(_T_2419, _T_2422, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2524 = mux(_T_2423, _T_2424, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2525 = mux(_T_2425, _T_2426, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2526 = mux(_T_2427, _T_2428, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2527 = mux(_T_2429, _T_2430, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2528 = mux(_T_2431, _T_2440, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2529 = mux(_T_2441, _T_2443, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2530 = mux(_T_2444, _T_2445, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2531 = mux(_T_2446, _T_2447, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2532 = mux(_T_2448, _T_2449, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2533 = mux(_T_2450, _T_2451, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2534 = mux(_T_2452, _T_2453, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2535 = mux(_T_2454, _T_2455, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2536 = mux(_T_2456, _T_2457, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2537 = mux(_T_2458, _T_2459, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2538 = mux(_T_2460, _T_2461, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2539 = mux(_T_2462, _T_2463, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2540 = mux(_T_2464, _T_2465, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2541 = mux(_T_2466, _T_2467, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2542 = mux(_T_2468, _T_2469, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2543 = mux(_T_2470, _T_2472, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2544 = mux(_T_2473, _T_2475, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2545 = mux(_T_2476, _T_2478, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2546 = mux(_T_2479, _T_2481, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2547 = mux(_T_2482, _T_2484, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2548 = mux(_T_2485, _T_2487, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2549 = mux(_T_2488, _T_2490, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2550 = mux(_T_2491, _T_2493, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2551 = mux(_T_2494, _T_2495, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2552 = or(_T_2496, _T_2497) @[Mux.scala 27:72] + node _T_2553 = or(_T_2552, _T_2498) @[Mux.scala 27:72] + node _T_2554 = or(_T_2553, _T_2499) @[Mux.scala 27:72] + node _T_2555 = or(_T_2554, _T_2500) @[Mux.scala 27:72] + node _T_2556 = or(_T_2555, _T_2501) @[Mux.scala 27:72] + node _T_2557 = or(_T_2556, _T_2502) @[Mux.scala 27:72] + node _T_2558 = or(_T_2557, _T_2503) @[Mux.scala 27:72] + node _T_2559 = or(_T_2558, _T_2504) @[Mux.scala 27:72] + node _T_2560 = or(_T_2559, _T_2505) @[Mux.scala 27:72] node _T_2561 = or(_T_2560, _T_2506) @[Mux.scala 27:72] node _T_2562 = or(_T_2561, _T_2507) @[Mux.scala 27:72] node _T_2563 = or(_T_2562, _T_2508) @[Mux.scala 27:72] @@ -76162,17 +76162,9 @@ circuit quasar_wrapper : node _T_2604 = or(_T_2603, _T_2549) @[Mux.scala 27:72] node _T_2605 = or(_T_2604, _T_2550) @[Mux.scala 27:72] node _T_2606 = or(_T_2605, _T_2551) @[Mux.scala 27:72] - node _T_2607 = or(_T_2606, _T_2552) @[Mux.scala 27:72] - node _T_2608 = or(_T_2607, _T_2553) @[Mux.scala 27:72] - node _T_2609 = or(_T_2608, _T_2554) @[Mux.scala 27:72] - node _T_2610 = or(_T_2609, _T_2555) @[Mux.scala 27:72] - node _T_2611 = or(_T_2610, _T_2556) @[Mux.scala 27:72] - node _T_2612 = or(_T_2611, _T_2557) @[Mux.scala 27:72] - node _T_2613 = or(_T_2612, _T_2558) @[Mux.scala 27:72] - node _T_2614 = or(_T_2613, _T_2559) @[Mux.scala 27:72] - wire _T_2615 : UInt @[Mux.scala 27:72] - _T_2615 <= _T_2614 @[Mux.scala 27:72] - io.dec_csr_rddata_d <= _T_2615 @[dec_tlu_ctl.scala 2497:21] + wire _T_2607 : UInt @[Mux.scala 27:72] + _T_2607 <= _T_2606 @[Mux.scala 27:72] + io.dec_csr_rddata_d <= _T_2607 @[dec_tlu_ctl.scala 2497:21] module dec_decode_csr_read : input clock : Clock @@ -78117,10 +78109,10 @@ circuit quasar_wrapper : node _T_5 = cat(io.nmi_int, io.timer_int) @[Cat.scala 29:58] node _T_6 = cat(_T_5, _T_4) @[Cat.scala 29:58] node _T_7 = cat(_T_6, _T_3) @[Cat.scala 29:58] - reg _T_8 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 177:81] - _T_8 <= _T_7 @[el2_lib.scala 177:81] - reg syncro_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 177:58] - syncro_ff <= _T_8 @[el2_lib.scala 177:58] + reg _T_8 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 37:81] + _T_8 <= _T_7 @[lib.scala 37:81] + reg syncro_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 37:58] + syncro_ff <= _T_8 @[lib.scala 37:58] node nmi_int_sync = bits(syncro_ff, 6, 6) @[dec_tlu_ctl.scala 301:67] node timer_int_sync = bits(syncro_ff, 5, 5) @[dec_tlu_ctl.scala 302:59] node soft_int_sync = bits(syncro_ff, 4, 4) @[dec_tlu_ctl.scala 303:59] @@ -78130,21 +78122,21 @@ circuit quasar_wrapper : node mpc_debug_run_req_sync = bits(syncro_ff, 0, 0) @[dec_tlu_ctl.scala 307:51] node _T_9 = or(dec_csr_wen_r_mod, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 310:58] node _T_10 = bits(_T_9, 0, 0) @[dec_tlu_ctl.scala 310:74] - inst rvclkhdr of rvclkhdr_716 @[el2_lib.scala 483:22] + inst rvclkhdr of rvclkhdr_716 @[lib.scala 343:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr.io.en <= _T_10 @[el2_lib.scala 485:16] - rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr.io.clk <= clock @[lib.scala 344:17] + rvclkhdr.io.en <= _T_10 @[lib.scala 345:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] node _T_11 = or(io.lsu_error_pkt_r.valid, lsu_exc_valid_r_d1) @[dec_tlu_ctl.scala 311:67] node _T_12 = or(_T_11, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 311:88] node _T_13 = bits(_T_12, 0, 0) @[dec_tlu_ctl.scala 311:104] - inst rvclkhdr_1 of rvclkhdr_717 @[el2_lib.scala 483:22] + inst rvclkhdr_1 of rvclkhdr_717 @[lib.scala 343:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_1.io.en <= _T_13 @[el2_lib.scala 485:16] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_1.io.en <= _T_13 @[lib.scala 345:16] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] node e4e5_valid = or(io.dec_tlu_i0_valid_r, e5_valid) @[dec_tlu_ctl.scala 314:30] node _T_14 = or(debug_mode_status, i_cpu_run_req_d1) @[dec_tlu_ctl.scala 315:50] node _T_15 = or(_T_14, interrupt_valid_r) @[dec_tlu_ctl.scala 315:69] @@ -78159,20 +78151,20 @@ circuit quasar_wrapper : node flush_clkvalid = or(_T_23, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 315:225] node _T_24 = or(e4e5_valid, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 317:49] node _T_25 = bits(_T_24, 0, 0) @[dec_tlu_ctl.scala 317:65] - inst rvclkhdr_2 of rvclkhdr_718 @[el2_lib.scala 483:22] + inst rvclkhdr_2 of rvclkhdr_718 @[lib.scala 343:22] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_2.io.en <= _T_25 @[el2_lib.scala 485:16] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_2.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_2.io.en <= _T_25 @[lib.scala 345:16] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 346:23] node _T_26 = or(e4e5_valid, flush_clkvalid) @[dec_tlu_ctl.scala 318:53] node _T_27 = bits(_T_26, 0, 0) @[dec_tlu_ctl.scala 318:71] - inst rvclkhdr_3 of rvclkhdr_719 @[el2_lib.scala 483:22] + inst rvclkhdr_3 of rvclkhdr_719 @[lib.scala 343:22] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_3.io.en <= _T_27 @[el2_lib.scala 485:16] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_3.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_3.io.en <= _T_27 @[lib.scala 345:16] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 346:23] reg iccm_repair_state_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 320:80] iccm_repair_state_d1 <= iccm_repair_state_ns @[dec_tlu_ctl.scala 320:80] reg _T_28 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 321:89] @@ -79741,39 +79733,39 @@ circuit quasar_wrapper : node _T = eq(io.trigger_pkt_any[0].select, UInt<1>("h00")) @[dec_trigger.scala 14:63] node _T_1 = and(_T, io.trigger_pkt_any[0].execute) @[dec_trigger.scala 14:93] - wire _T_2 : UInt<1>[32] @[el2_lib.scala 162:48] - _T_2[0] <= _T_1 @[el2_lib.scala 162:48] - _T_2[1] <= _T_1 @[el2_lib.scala 162:48] - _T_2[2] <= _T_1 @[el2_lib.scala 162:48] - _T_2[3] <= _T_1 @[el2_lib.scala 162:48] - _T_2[4] <= _T_1 @[el2_lib.scala 162:48] - _T_2[5] <= _T_1 @[el2_lib.scala 162:48] - _T_2[6] <= _T_1 @[el2_lib.scala 162:48] - _T_2[7] <= _T_1 @[el2_lib.scala 162:48] - _T_2[8] <= _T_1 @[el2_lib.scala 162:48] - _T_2[9] <= _T_1 @[el2_lib.scala 162:48] - _T_2[10] <= _T_1 @[el2_lib.scala 162:48] - _T_2[11] <= _T_1 @[el2_lib.scala 162:48] - _T_2[12] <= _T_1 @[el2_lib.scala 162:48] - _T_2[13] <= _T_1 @[el2_lib.scala 162:48] - _T_2[14] <= _T_1 @[el2_lib.scala 162:48] - _T_2[15] <= _T_1 @[el2_lib.scala 162:48] - _T_2[16] <= _T_1 @[el2_lib.scala 162:48] - _T_2[17] <= _T_1 @[el2_lib.scala 162:48] - _T_2[18] <= _T_1 @[el2_lib.scala 162:48] - _T_2[19] <= _T_1 @[el2_lib.scala 162:48] - _T_2[20] <= _T_1 @[el2_lib.scala 162:48] - _T_2[21] <= _T_1 @[el2_lib.scala 162:48] - _T_2[22] <= _T_1 @[el2_lib.scala 162:48] - _T_2[23] <= _T_1 @[el2_lib.scala 162:48] - _T_2[24] <= _T_1 @[el2_lib.scala 162:48] - _T_2[25] <= _T_1 @[el2_lib.scala 162:48] - _T_2[26] <= _T_1 @[el2_lib.scala 162:48] - _T_2[27] <= _T_1 @[el2_lib.scala 162:48] - _T_2[28] <= _T_1 @[el2_lib.scala 162:48] - _T_2[29] <= _T_1 @[el2_lib.scala 162:48] - _T_2[30] <= _T_1 @[el2_lib.scala 162:48] - _T_2[31] <= _T_1 @[el2_lib.scala 162:48] + wire _T_2 : UInt<1>[32] @[lib.scala 12:48] + _T_2[0] <= _T_1 @[lib.scala 12:48] + _T_2[1] <= _T_1 @[lib.scala 12:48] + _T_2[2] <= _T_1 @[lib.scala 12:48] + _T_2[3] <= _T_1 @[lib.scala 12:48] + _T_2[4] <= _T_1 @[lib.scala 12:48] + _T_2[5] <= _T_1 @[lib.scala 12:48] + _T_2[6] <= _T_1 @[lib.scala 12:48] + _T_2[7] <= _T_1 @[lib.scala 12:48] + _T_2[8] <= _T_1 @[lib.scala 12:48] + _T_2[9] <= _T_1 @[lib.scala 12:48] + _T_2[10] <= _T_1 @[lib.scala 12:48] + _T_2[11] <= _T_1 @[lib.scala 12:48] + _T_2[12] <= _T_1 @[lib.scala 12:48] + _T_2[13] <= _T_1 @[lib.scala 12:48] + _T_2[14] <= _T_1 @[lib.scala 12:48] + _T_2[15] <= _T_1 @[lib.scala 12:48] + _T_2[16] <= _T_1 @[lib.scala 12:48] + _T_2[17] <= _T_1 @[lib.scala 12:48] + _T_2[18] <= _T_1 @[lib.scala 12:48] + _T_2[19] <= _T_1 @[lib.scala 12:48] + _T_2[20] <= _T_1 @[lib.scala 12:48] + _T_2[21] <= _T_1 @[lib.scala 12:48] + _T_2[22] <= _T_1 @[lib.scala 12:48] + _T_2[23] <= _T_1 @[lib.scala 12:48] + _T_2[24] <= _T_1 @[lib.scala 12:48] + _T_2[25] <= _T_1 @[lib.scala 12:48] + _T_2[26] <= _T_1 @[lib.scala 12:48] + _T_2[27] <= _T_1 @[lib.scala 12:48] + _T_2[28] <= _T_1 @[lib.scala 12:48] + _T_2[29] <= _T_1 @[lib.scala 12:48] + _T_2[30] <= _T_1 @[lib.scala 12:48] + _T_2[31] <= _T_1 @[lib.scala 12:48] node _T_3 = cat(_T_2[0], _T_2[1]) @[Cat.scala 29:58] node _T_4 = cat(_T_3, _T_2[2]) @[Cat.scala 29:58] node _T_5 = cat(_T_4, _T_2[3]) @[Cat.scala 29:58] @@ -79810,39 +79802,39 @@ circuit quasar_wrapper : node _T_36 = and(_T_33, _T_35) @[dec_trigger.scala 14:127] node _T_37 = eq(io.trigger_pkt_any[1].select, UInt<1>("h00")) @[dec_trigger.scala 14:63] node _T_38 = and(_T_37, io.trigger_pkt_any[1].execute) @[dec_trigger.scala 14:93] - wire _T_39 : UInt<1>[32] @[el2_lib.scala 162:48] - _T_39[0] <= _T_38 @[el2_lib.scala 162:48] - _T_39[1] <= _T_38 @[el2_lib.scala 162:48] - _T_39[2] <= _T_38 @[el2_lib.scala 162:48] - _T_39[3] <= _T_38 @[el2_lib.scala 162:48] - _T_39[4] <= _T_38 @[el2_lib.scala 162:48] - _T_39[5] <= _T_38 @[el2_lib.scala 162:48] - _T_39[6] <= _T_38 @[el2_lib.scala 162:48] - _T_39[7] <= _T_38 @[el2_lib.scala 162:48] - _T_39[8] <= _T_38 @[el2_lib.scala 162:48] - _T_39[9] <= _T_38 @[el2_lib.scala 162:48] - _T_39[10] <= _T_38 @[el2_lib.scala 162:48] - _T_39[11] <= _T_38 @[el2_lib.scala 162:48] - _T_39[12] <= _T_38 @[el2_lib.scala 162:48] - _T_39[13] <= _T_38 @[el2_lib.scala 162:48] - _T_39[14] <= _T_38 @[el2_lib.scala 162:48] - _T_39[15] <= _T_38 @[el2_lib.scala 162:48] - _T_39[16] <= _T_38 @[el2_lib.scala 162:48] - _T_39[17] <= _T_38 @[el2_lib.scala 162:48] - _T_39[18] <= _T_38 @[el2_lib.scala 162:48] - _T_39[19] <= _T_38 @[el2_lib.scala 162:48] - _T_39[20] <= _T_38 @[el2_lib.scala 162:48] - _T_39[21] <= _T_38 @[el2_lib.scala 162:48] - _T_39[22] <= _T_38 @[el2_lib.scala 162:48] - _T_39[23] <= _T_38 @[el2_lib.scala 162:48] - _T_39[24] <= _T_38 @[el2_lib.scala 162:48] - _T_39[25] <= _T_38 @[el2_lib.scala 162:48] - _T_39[26] <= _T_38 @[el2_lib.scala 162:48] - _T_39[27] <= _T_38 @[el2_lib.scala 162:48] - _T_39[28] <= _T_38 @[el2_lib.scala 162:48] - _T_39[29] <= _T_38 @[el2_lib.scala 162:48] - _T_39[30] <= _T_38 @[el2_lib.scala 162:48] - _T_39[31] <= _T_38 @[el2_lib.scala 162:48] + wire _T_39 : UInt<1>[32] @[lib.scala 12:48] + _T_39[0] <= _T_38 @[lib.scala 12:48] + _T_39[1] <= _T_38 @[lib.scala 12:48] + _T_39[2] <= _T_38 @[lib.scala 12:48] + _T_39[3] <= _T_38 @[lib.scala 12:48] + _T_39[4] <= _T_38 @[lib.scala 12:48] + _T_39[5] <= _T_38 @[lib.scala 12:48] + _T_39[6] <= _T_38 @[lib.scala 12:48] + _T_39[7] <= _T_38 @[lib.scala 12:48] + _T_39[8] <= _T_38 @[lib.scala 12:48] + _T_39[9] <= _T_38 @[lib.scala 12:48] + _T_39[10] <= _T_38 @[lib.scala 12:48] + _T_39[11] <= _T_38 @[lib.scala 12:48] + _T_39[12] <= _T_38 @[lib.scala 12:48] + _T_39[13] <= _T_38 @[lib.scala 12:48] + _T_39[14] <= _T_38 @[lib.scala 12:48] + _T_39[15] <= _T_38 @[lib.scala 12:48] + _T_39[16] <= _T_38 @[lib.scala 12:48] + _T_39[17] <= _T_38 @[lib.scala 12:48] + _T_39[18] <= _T_38 @[lib.scala 12:48] + _T_39[19] <= _T_38 @[lib.scala 12:48] + _T_39[20] <= _T_38 @[lib.scala 12:48] + _T_39[21] <= _T_38 @[lib.scala 12:48] + _T_39[22] <= _T_38 @[lib.scala 12:48] + _T_39[23] <= _T_38 @[lib.scala 12:48] + _T_39[24] <= _T_38 @[lib.scala 12:48] + _T_39[25] <= _T_38 @[lib.scala 12:48] + _T_39[26] <= _T_38 @[lib.scala 12:48] + _T_39[27] <= _T_38 @[lib.scala 12:48] + _T_39[28] <= _T_38 @[lib.scala 12:48] + _T_39[29] <= _T_38 @[lib.scala 12:48] + _T_39[30] <= _T_38 @[lib.scala 12:48] + _T_39[31] <= _T_38 @[lib.scala 12:48] node _T_40 = cat(_T_39[0], _T_39[1]) @[Cat.scala 29:58] node _T_41 = cat(_T_40, _T_39[2]) @[Cat.scala 29:58] node _T_42 = cat(_T_41, _T_39[3]) @[Cat.scala 29:58] @@ -79879,39 +79871,39 @@ circuit quasar_wrapper : node _T_73 = and(_T_70, _T_72) @[dec_trigger.scala 14:127] node _T_74 = eq(io.trigger_pkt_any[2].select, UInt<1>("h00")) @[dec_trigger.scala 14:63] node _T_75 = and(_T_74, io.trigger_pkt_any[2].execute) @[dec_trigger.scala 14:93] - wire _T_76 : UInt<1>[32] @[el2_lib.scala 162:48] - _T_76[0] <= _T_75 @[el2_lib.scala 162:48] - _T_76[1] <= _T_75 @[el2_lib.scala 162:48] - _T_76[2] <= _T_75 @[el2_lib.scala 162:48] - _T_76[3] <= _T_75 @[el2_lib.scala 162:48] - _T_76[4] <= _T_75 @[el2_lib.scala 162:48] - _T_76[5] <= _T_75 @[el2_lib.scala 162:48] - _T_76[6] <= _T_75 @[el2_lib.scala 162:48] - _T_76[7] <= _T_75 @[el2_lib.scala 162:48] - _T_76[8] <= _T_75 @[el2_lib.scala 162:48] - _T_76[9] <= _T_75 @[el2_lib.scala 162:48] - _T_76[10] <= _T_75 @[el2_lib.scala 162:48] - _T_76[11] <= _T_75 @[el2_lib.scala 162:48] - _T_76[12] <= _T_75 @[el2_lib.scala 162:48] - _T_76[13] <= _T_75 @[el2_lib.scala 162:48] - _T_76[14] <= _T_75 @[el2_lib.scala 162:48] - _T_76[15] <= _T_75 @[el2_lib.scala 162:48] - _T_76[16] <= _T_75 @[el2_lib.scala 162:48] - _T_76[17] <= _T_75 @[el2_lib.scala 162:48] - _T_76[18] <= _T_75 @[el2_lib.scala 162:48] - _T_76[19] <= _T_75 @[el2_lib.scala 162:48] - _T_76[20] <= _T_75 @[el2_lib.scala 162:48] - _T_76[21] <= _T_75 @[el2_lib.scala 162:48] - _T_76[22] <= _T_75 @[el2_lib.scala 162:48] - _T_76[23] <= _T_75 @[el2_lib.scala 162:48] - _T_76[24] <= _T_75 @[el2_lib.scala 162:48] - _T_76[25] <= _T_75 @[el2_lib.scala 162:48] - _T_76[26] <= _T_75 @[el2_lib.scala 162:48] - _T_76[27] <= _T_75 @[el2_lib.scala 162:48] - _T_76[28] <= _T_75 @[el2_lib.scala 162:48] - _T_76[29] <= _T_75 @[el2_lib.scala 162:48] - _T_76[30] <= _T_75 @[el2_lib.scala 162:48] - _T_76[31] <= _T_75 @[el2_lib.scala 162:48] + wire _T_76 : UInt<1>[32] @[lib.scala 12:48] + _T_76[0] <= _T_75 @[lib.scala 12:48] + _T_76[1] <= _T_75 @[lib.scala 12:48] + _T_76[2] <= _T_75 @[lib.scala 12:48] + _T_76[3] <= _T_75 @[lib.scala 12:48] + _T_76[4] <= _T_75 @[lib.scala 12:48] + _T_76[5] <= _T_75 @[lib.scala 12:48] + _T_76[6] <= _T_75 @[lib.scala 12:48] + _T_76[7] <= _T_75 @[lib.scala 12:48] + _T_76[8] <= _T_75 @[lib.scala 12:48] + _T_76[9] <= _T_75 @[lib.scala 12:48] + _T_76[10] <= _T_75 @[lib.scala 12:48] + _T_76[11] <= _T_75 @[lib.scala 12:48] + _T_76[12] <= _T_75 @[lib.scala 12:48] + _T_76[13] <= _T_75 @[lib.scala 12:48] + _T_76[14] <= _T_75 @[lib.scala 12:48] + _T_76[15] <= _T_75 @[lib.scala 12:48] + _T_76[16] <= _T_75 @[lib.scala 12:48] + _T_76[17] <= _T_75 @[lib.scala 12:48] + _T_76[18] <= _T_75 @[lib.scala 12:48] + _T_76[19] <= _T_75 @[lib.scala 12:48] + _T_76[20] <= _T_75 @[lib.scala 12:48] + _T_76[21] <= _T_75 @[lib.scala 12:48] + _T_76[22] <= _T_75 @[lib.scala 12:48] + _T_76[23] <= _T_75 @[lib.scala 12:48] + _T_76[24] <= _T_75 @[lib.scala 12:48] + _T_76[25] <= _T_75 @[lib.scala 12:48] + _T_76[26] <= _T_75 @[lib.scala 12:48] + _T_76[27] <= _T_75 @[lib.scala 12:48] + _T_76[28] <= _T_75 @[lib.scala 12:48] + _T_76[29] <= _T_75 @[lib.scala 12:48] + _T_76[30] <= _T_75 @[lib.scala 12:48] + _T_76[31] <= _T_75 @[lib.scala 12:48] node _T_77 = cat(_T_76[0], _T_76[1]) @[Cat.scala 29:58] node _T_78 = cat(_T_77, _T_76[2]) @[Cat.scala 29:58] node _T_79 = cat(_T_78, _T_76[3]) @[Cat.scala 29:58] @@ -79948,39 +79940,39 @@ circuit quasar_wrapper : node _T_110 = and(_T_107, _T_109) @[dec_trigger.scala 14:127] node _T_111 = eq(io.trigger_pkt_any[3].select, UInt<1>("h00")) @[dec_trigger.scala 14:63] node _T_112 = and(_T_111, io.trigger_pkt_any[3].execute) @[dec_trigger.scala 14:93] - wire _T_113 : UInt<1>[32] @[el2_lib.scala 162:48] - _T_113[0] <= _T_112 @[el2_lib.scala 162:48] - _T_113[1] <= _T_112 @[el2_lib.scala 162:48] - _T_113[2] <= _T_112 @[el2_lib.scala 162:48] - _T_113[3] <= _T_112 @[el2_lib.scala 162:48] - _T_113[4] <= _T_112 @[el2_lib.scala 162:48] - _T_113[5] <= _T_112 @[el2_lib.scala 162:48] - _T_113[6] <= _T_112 @[el2_lib.scala 162:48] - _T_113[7] <= _T_112 @[el2_lib.scala 162:48] - _T_113[8] <= _T_112 @[el2_lib.scala 162:48] - _T_113[9] <= _T_112 @[el2_lib.scala 162:48] - _T_113[10] <= _T_112 @[el2_lib.scala 162:48] - _T_113[11] <= _T_112 @[el2_lib.scala 162:48] - _T_113[12] <= _T_112 @[el2_lib.scala 162:48] - _T_113[13] <= _T_112 @[el2_lib.scala 162:48] - _T_113[14] <= _T_112 @[el2_lib.scala 162:48] - _T_113[15] <= _T_112 @[el2_lib.scala 162:48] - _T_113[16] <= _T_112 @[el2_lib.scala 162:48] - _T_113[17] <= _T_112 @[el2_lib.scala 162:48] - _T_113[18] <= _T_112 @[el2_lib.scala 162:48] - _T_113[19] <= _T_112 @[el2_lib.scala 162:48] - _T_113[20] <= _T_112 @[el2_lib.scala 162:48] - _T_113[21] <= _T_112 @[el2_lib.scala 162:48] - _T_113[22] <= _T_112 @[el2_lib.scala 162:48] - _T_113[23] <= _T_112 @[el2_lib.scala 162:48] - _T_113[24] <= _T_112 @[el2_lib.scala 162:48] - _T_113[25] <= _T_112 @[el2_lib.scala 162:48] - _T_113[26] <= _T_112 @[el2_lib.scala 162:48] - _T_113[27] <= _T_112 @[el2_lib.scala 162:48] - _T_113[28] <= _T_112 @[el2_lib.scala 162:48] - _T_113[29] <= _T_112 @[el2_lib.scala 162:48] - _T_113[30] <= _T_112 @[el2_lib.scala 162:48] - _T_113[31] <= _T_112 @[el2_lib.scala 162:48] + wire _T_113 : UInt<1>[32] @[lib.scala 12:48] + _T_113[0] <= _T_112 @[lib.scala 12:48] + _T_113[1] <= _T_112 @[lib.scala 12:48] + _T_113[2] <= _T_112 @[lib.scala 12:48] + _T_113[3] <= _T_112 @[lib.scala 12:48] + _T_113[4] <= _T_112 @[lib.scala 12:48] + _T_113[5] <= _T_112 @[lib.scala 12:48] + _T_113[6] <= _T_112 @[lib.scala 12:48] + _T_113[7] <= _T_112 @[lib.scala 12:48] + _T_113[8] <= _T_112 @[lib.scala 12:48] + _T_113[9] <= _T_112 @[lib.scala 12:48] + _T_113[10] <= _T_112 @[lib.scala 12:48] + _T_113[11] <= _T_112 @[lib.scala 12:48] + _T_113[12] <= _T_112 @[lib.scala 12:48] + _T_113[13] <= _T_112 @[lib.scala 12:48] + _T_113[14] <= _T_112 @[lib.scala 12:48] + _T_113[15] <= _T_112 @[lib.scala 12:48] + _T_113[16] <= _T_112 @[lib.scala 12:48] + _T_113[17] <= _T_112 @[lib.scala 12:48] + _T_113[18] <= _T_112 @[lib.scala 12:48] + _T_113[19] <= _T_112 @[lib.scala 12:48] + _T_113[20] <= _T_112 @[lib.scala 12:48] + _T_113[21] <= _T_112 @[lib.scala 12:48] + _T_113[22] <= _T_112 @[lib.scala 12:48] + _T_113[23] <= _T_112 @[lib.scala 12:48] + _T_113[24] <= _T_112 @[lib.scala 12:48] + _T_113[25] <= _T_112 @[lib.scala 12:48] + _T_113[26] <= _T_112 @[lib.scala 12:48] + _T_113[27] <= _T_112 @[lib.scala 12:48] + _T_113[28] <= _T_112 @[lib.scala 12:48] + _T_113[29] <= _T_112 @[lib.scala 12:48] + _T_113[30] <= _T_112 @[lib.scala 12:48] + _T_113[31] <= _T_112 @[lib.scala 12:48] node _T_114 = cat(_T_113[0], _T_113[1]) @[Cat.scala 29:58] node _T_115 = cat(_T_114, _T_113[2]) @[Cat.scala 29:58] node _T_116 = cat(_T_115, _T_113[3]) @[Cat.scala 29:58] @@ -80022,1171 +80014,1171 @@ circuit quasar_wrapper : dec_i0_match_data[3] <= _T_147 @[dec_trigger.scala 14:46] node _T_148 = and(io.trigger_pkt_any[0].execute, io.trigger_pkt_any[0].m) @[dec_trigger.scala 15:83] node _T_149 = bits(io.trigger_pkt_any[0].match_pkt, 0, 0) @[dec_trigger.scala 15:216] - wire _T_150 : UInt<1>[32] @[el2_lib.scala 240:24] - node _T_151 = andr(io.trigger_pkt_any[0].tdata2) @[el2_lib.scala 241:45] - node _T_152 = not(_T_151) @[el2_lib.scala 241:39] - node _T_153 = and(_T_149, _T_152) @[el2_lib.scala 241:37] - node _T_154 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[el2_lib.scala 242:48] - node _T_155 = bits(dec_i0_match_data[0], 0, 0) @[el2_lib.scala 242:60] - node _T_156 = eq(_T_154, _T_155) @[el2_lib.scala 242:52] - node _T_157 = or(_T_153, _T_156) @[el2_lib.scala 242:41] - _T_150[0] <= _T_157 @[el2_lib.scala 242:18] - node _T_158 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[el2_lib.scala 244:28] - node _T_159 = andr(_T_158) @[el2_lib.scala 244:36] - node _T_160 = and(_T_159, _T_153) @[el2_lib.scala 244:41] - node _T_161 = bits(io.trigger_pkt_any[0].tdata2, 1, 1) @[el2_lib.scala 244:74] - node _T_162 = bits(dec_i0_match_data[0], 1, 1) @[el2_lib.scala 244:86] - node _T_163 = eq(_T_161, _T_162) @[el2_lib.scala 244:78] - node _T_164 = mux(_T_160, UInt<1>("h01"), _T_163) @[el2_lib.scala 244:23] - _T_150[1] <= _T_164 @[el2_lib.scala 244:17] - node _T_165 = bits(io.trigger_pkt_any[0].tdata2, 1, 0) @[el2_lib.scala 244:28] - node _T_166 = andr(_T_165) @[el2_lib.scala 244:36] - node _T_167 = and(_T_166, _T_153) @[el2_lib.scala 244:41] - node _T_168 = bits(io.trigger_pkt_any[0].tdata2, 2, 2) @[el2_lib.scala 244:74] - node _T_169 = bits(dec_i0_match_data[0], 2, 2) @[el2_lib.scala 244:86] - node _T_170 = eq(_T_168, _T_169) @[el2_lib.scala 244:78] - node _T_171 = mux(_T_167, UInt<1>("h01"), _T_170) @[el2_lib.scala 244:23] - _T_150[2] <= _T_171 @[el2_lib.scala 244:17] - node _T_172 = bits(io.trigger_pkt_any[0].tdata2, 2, 0) @[el2_lib.scala 244:28] - node _T_173 = andr(_T_172) @[el2_lib.scala 244:36] - node _T_174 = and(_T_173, _T_153) @[el2_lib.scala 244:41] - node _T_175 = bits(io.trigger_pkt_any[0].tdata2, 3, 3) @[el2_lib.scala 244:74] - node _T_176 = bits(dec_i0_match_data[0], 3, 3) @[el2_lib.scala 244:86] - node _T_177 = eq(_T_175, _T_176) @[el2_lib.scala 244:78] - node _T_178 = mux(_T_174, UInt<1>("h01"), _T_177) @[el2_lib.scala 244:23] - _T_150[3] <= _T_178 @[el2_lib.scala 244:17] - node _T_179 = bits(io.trigger_pkt_any[0].tdata2, 3, 0) @[el2_lib.scala 244:28] - node _T_180 = andr(_T_179) @[el2_lib.scala 244:36] - node _T_181 = and(_T_180, _T_153) @[el2_lib.scala 244:41] - node _T_182 = bits(io.trigger_pkt_any[0].tdata2, 4, 4) @[el2_lib.scala 244:74] - node _T_183 = bits(dec_i0_match_data[0], 4, 4) @[el2_lib.scala 244:86] - node _T_184 = eq(_T_182, _T_183) @[el2_lib.scala 244:78] - node _T_185 = mux(_T_181, UInt<1>("h01"), _T_184) @[el2_lib.scala 244:23] - _T_150[4] <= _T_185 @[el2_lib.scala 244:17] - node _T_186 = bits(io.trigger_pkt_any[0].tdata2, 4, 0) @[el2_lib.scala 244:28] - node _T_187 = andr(_T_186) @[el2_lib.scala 244:36] - node _T_188 = and(_T_187, _T_153) @[el2_lib.scala 244:41] - node _T_189 = bits(io.trigger_pkt_any[0].tdata2, 5, 5) @[el2_lib.scala 244:74] - node _T_190 = bits(dec_i0_match_data[0], 5, 5) @[el2_lib.scala 244:86] - node _T_191 = eq(_T_189, _T_190) @[el2_lib.scala 244:78] - node _T_192 = mux(_T_188, UInt<1>("h01"), _T_191) @[el2_lib.scala 244:23] - _T_150[5] <= _T_192 @[el2_lib.scala 244:17] - node _T_193 = bits(io.trigger_pkt_any[0].tdata2, 5, 0) @[el2_lib.scala 244:28] - node _T_194 = andr(_T_193) @[el2_lib.scala 244:36] - node _T_195 = and(_T_194, _T_153) @[el2_lib.scala 244:41] - node _T_196 = bits(io.trigger_pkt_any[0].tdata2, 6, 6) @[el2_lib.scala 244:74] - node _T_197 = bits(dec_i0_match_data[0], 6, 6) @[el2_lib.scala 244:86] - node _T_198 = eq(_T_196, _T_197) @[el2_lib.scala 244:78] - node _T_199 = mux(_T_195, UInt<1>("h01"), _T_198) @[el2_lib.scala 244:23] - _T_150[6] <= _T_199 @[el2_lib.scala 244:17] - node _T_200 = bits(io.trigger_pkt_any[0].tdata2, 6, 0) @[el2_lib.scala 244:28] - node _T_201 = andr(_T_200) @[el2_lib.scala 244:36] - node _T_202 = and(_T_201, _T_153) @[el2_lib.scala 244:41] - node _T_203 = bits(io.trigger_pkt_any[0].tdata2, 7, 7) @[el2_lib.scala 244:74] - node _T_204 = bits(dec_i0_match_data[0], 7, 7) @[el2_lib.scala 244:86] - node _T_205 = eq(_T_203, _T_204) @[el2_lib.scala 244:78] - node _T_206 = mux(_T_202, UInt<1>("h01"), _T_205) @[el2_lib.scala 244:23] - _T_150[7] <= _T_206 @[el2_lib.scala 244:17] - node _T_207 = bits(io.trigger_pkt_any[0].tdata2, 7, 0) @[el2_lib.scala 244:28] - node _T_208 = andr(_T_207) @[el2_lib.scala 244:36] - node _T_209 = and(_T_208, _T_153) @[el2_lib.scala 244:41] - node _T_210 = bits(io.trigger_pkt_any[0].tdata2, 8, 8) @[el2_lib.scala 244:74] - node _T_211 = bits(dec_i0_match_data[0], 8, 8) @[el2_lib.scala 244:86] - node _T_212 = eq(_T_210, _T_211) @[el2_lib.scala 244:78] - node _T_213 = mux(_T_209, UInt<1>("h01"), _T_212) @[el2_lib.scala 244:23] - _T_150[8] <= _T_213 @[el2_lib.scala 244:17] - node _T_214 = bits(io.trigger_pkt_any[0].tdata2, 8, 0) @[el2_lib.scala 244:28] - node _T_215 = andr(_T_214) @[el2_lib.scala 244:36] - node _T_216 = and(_T_215, _T_153) @[el2_lib.scala 244:41] - node _T_217 = bits(io.trigger_pkt_any[0].tdata2, 9, 9) @[el2_lib.scala 244:74] - node _T_218 = bits(dec_i0_match_data[0], 9, 9) @[el2_lib.scala 244:86] - node _T_219 = eq(_T_217, _T_218) @[el2_lib.scala 244:78] - node _T_220 = mux(_T_216, UInt<1>("h01"), _T_219) @[el2_lib.scala 244:23] - _T_150[9] <= _T_220 @[el2_lib.scala 244:17] - node _T_221 = bits(io.trigger_pkt_any[0].tdata2, 9, 0) @[el2_lib.scala 244:28] - node _T_222 = andr(_T_221) @[el2_lib.scala 244:36] - node _T_223 = and(_T_222, _T_153) @[el2_lib.scala 244:41] - node _T_224 = bits(io.trigger_pkt_any[0].tdata2, 10, 10) @[el2_lib.scala 244:74] - node _T_225 = bits(dec_i0_match_data[0], 10, 10) @[el2_lib.scala 244:86] - node _T_226 = eq(_T_224, _T_225) @[el2_lib.scala 244:78] - node _T_227 = mux(_T_223, UInt<1>("h01"), _T_226) @[el2_lib.scala 244:23] - _T_150[10] <= _T_227 @[el2_lib.scala 244:17] - node _T_228 = bits(io.trigger_pkt_any[0].tdata2, 10, 0) @[el2_lib.scala 244:28] - node _T_229 = andr(_T_228) @[el2_lib.scala 244:36] - node _T_230 = and(_T_229, _T_153) @[el2_lib.scala 244:41] - node _T_231 = bits(io.trigger_pkt_any[0].tdata2, 11, 11) @[el2_lib.scala 244:74] - node _T_232 = bits(dec_i0_match_data[0], 11, 11) @[el2_lib.scala 244:86] - node _T_233 = eq(_T_231, _T_232) @[el2_lib.scala 244:78] - node _T_234 = mux(_T_230, UInt<1>("h01"), _T_233) @[el2_lib.scala 244:23] - _T_150[11] <= _T_234 @[el2_lib.scala 244:17] - node _T_235 = bits(io.trigger_pkt_any[0].tdata2, 11, 0) @[el2_lib.scala 244:28] - node _T_236 = andr(_T_235) @[el2_lib.scala 244:36] - node _T_237 = and(_T_236, _T_153) @[el2_lib.scala 244:41] - node _T_238 = bits(io.trigger_pkt_any[0].tdata2, 12, 12) @[el2_lib.scala 244:74] - node _T_239 = bits(dec_i0_match_data[0], 12, 12) @[el2_lib.scala 244:86] - node _T_240 = eq(_T_238, _T_239) @[el2_lib.scala 244:78] - node _T_241 = mux(_T_237, UInt<1>("h01"), _T_240) @[el2_lib.scala 244:23] - _T_150[12] <= _T_241 @[el2_lib.scala 244:17] - node _T_242 = bits(io.trigger_pkt_any[0].tdata2, 12, 0) @[el2_lib.scala 244:28] - node _T_243 = andr(_T_242) @[el2_lib.scala 244:36] - node _T_244 = and(_T_243, _T_153) @[el2_lib.scala 244:41] - node _T_245 = bits(io.trigger_pkt_any[0].tdata2, 13, 13) @[el2_lib.scala 244:74] - node _T_246 = bits(dec_i0_match_data[0], 13, 13) @[el2_lib.scala 244:86] - node _T_247 = eq(_T_245, _T_246) @[el2_lib.scala 244:78] - node _T_248 = mux(_T_244, UInt<1>("h01"), _T_247) @[el2_lib.scala 244:23] - _T_150[13] <= _T_248 @[el2_lib.scala 244:17] - node _T_249 = bits(io.trigger_pkt_any[0].tdata2, 13, 0) @[el2_lib.scala 244:28] - node _T_250 = andr(_T_249) @[el2_lib.scala 244:36] - node _T_251 = and(_T_250, _T_153) @[el2_lib.scala 244:41] - node _T_252 = bits(io.trigger_pkt_any[0].tdata2, 14, 14) @[el2_lib.scala 244:74] - node _T_253 = bits(dec_i0_match_data[0], 14, 14) @[el2_lib.scala 244:86] - node _T_254 = eq(_T_252, _T_253) @[el2_lib.scala 244:78] - node _T_255 = mux(_T_251, UInt<1>("h01"), _T_254) @[el2_lib.scala 244:23] - _T_150[14] <= _T_255 @[el2_lib.scala 244:17] - node _T_256 = bits(io.trigger_pkt_any[0].tdata2, 14, 0) @[el2_lib.scala 244:28] - node _T_257 = andr(_T_256) @[el2_lib.scala 244:36] - node _T_258 = and(_T_257, _T_153) @[el2_lib.scala 244:41] - node _T_259 = bits(io.trigger_pkt_any[0].tdata2, 15, 15) @[el2_lib.scala 244:74] - node _T_260 = bits(dec_i0_match_data[0], 15, 15) @[el2_lib.scala 244:86] - node _T_261 = eq(_T_259, _T_260) @[el2_lib.scala 244:78] - node _T_262 = mux(_T_258, UInt<1>("h01"), _T_261) @[el2_lib.scala 244:23] - _T_150[15] <= _T_262 @[el2_lib.scala 244:17] - node _T_263 = bits(io.trigger_pkt_any[0].tdata2, 15, 0) @[el2_lib.scala 244:28] - node _T_264 = andr(_T_263) @[el2_lib.scala 244:36] - node _T_265 = and(_T_264, _T_153) @[el2_lib.scala 244:41] - node _T_266 = bits(io.trigger_pkt_any[0].tdata2, 16, 16) @[el2_lib.scala 244:74] - node _T_267 = bits(dec_i0_match_data[0], 16, 16) @[el2_lib.scala 244:86] - node _T_268 = eq(_T_266, _T_267) @[el2_lib.scala 244:78] - node _T_269 = mux(_T_265, UInt<1>("h01"), _T_268) @[el2_lib.scala 244:23] - _T_150[16] <= _T_269 @[el2_lib.scala 244:17] - node _T_270 = bits(io.trigger_pkt_any[0].tdata2, 16, 0) @[el2_lib.scala 244:28] - node _T_271 = andr(_T_270) @[el2_lib.scala 244:36] - node _T_272 = and(_T_271, _T_153) @[el2_lib.scala 244:41] - node _T_273 = bits(io.trigger_pkt_any[0].tdata2, 17, 17) @[el2_lib.scala 244:74] - node _T_274 = bits(dec_i0_match_data[0], 17, 17) @[el2_lib.scala 244:86] - node _T_275 = eq(_T_273, _T_274) @[el2_lib.scala 244:78] - node _T_276 = mux(_T_272, UInt<1>("h01"), _T_275) @[el2_lib.scala 244:23] - _T_150[17] <= _T_276 @[el2_lib.scala 244:17] - node _T_277 = bits(io.trigger_pkt_any[0].tdata2, 17, 0) @[el2_lib.scala 244:28] - node _T_278 = andr(_T_277) @[el2_lib.scala 244:36] - node _T_279 = and(_T_278, _T_153) @[el2_lib.scala 244:41] - node _T_280 = bits(io.trigger_pkt_any[0].tdata2, 18, 18) @[el2_lib.scala 244:74] - node _T_281 = bits(dec_i0_match_data[0], 18, 18) @[el2_lib.scala 244:86] - node _T_282 = eq(_T_280, _T_281) @[el2_lib.scala 244:78] - node _T_283 = mux(_T_279, UInt<1>("h01"), _T_282) @[el2_lib.scala 244:23] - _T_150[18] <= _T_283 @[el2_lib.scala 244:17] - node _T_284 = bits(io.trigger_pkt_any[0].tdata2, 18, 0) @[el2_lib.scala 244:28] - node _T_285 = andr(_T_284) @[el2_lib.scala 244:36] - node _T_286 = and(_T_285, _T_153) @[el2_lib.scala 244:41] - node _T_287 = bits(io.trigger_pkt_any[0].tdata2, 19, 19) @[el2_lib.scala 244:74] - node _T_288 = bits(dec_i0_match_data[0], 19, 19) @[el2_lib.scala 244:86] - node _T_289 = eq(_T_287, _T_288) @[el2_lib.scala 244:78] - node _T_290 = mux(_T_286, UInt<1>("h01"), _T_289) @[el2_lib.scala 244:23] - _T_150[19] <= _T_290 @[el2_lib.scala 244:17] - node _T_291 = bits(io.trigger_pkt_any[0].tdata2, 19, 0) @[el2_lib.scala 244:28] - node _T_292 = andr(_T_291) @[el2_lib.scala 244:36] - node _T_293 = and(_T_292, _T_153) @[el2_lib.scala 244:41] - node _T_294 = bits(io.trigger_pkt_any[0].tdata2, 20, 20) @[el2_lib.scala 244:74] - node _T_295 = bits(dec_i0_match_data[0], 20, 20) @[el2_lib.scala 244:86] - node _T_296 = eq(_T_294, _T_295) @[el2_lib.scala 244:78] - node _T_297 = mux(_T_293, UInt<1>("h01"), _T_296) @[el2_lib.scala 244:23] - _T_150[20] <= _T_297 @[el2_lib.scala 244:17] - node _T_298 = bits(io.trigger_pkt_any[0].tdata2, 20, 0) @[el2_lib.scala 244:28] - node _T_299 = andr(_T_298) @[el2_lib.scala 244:36] - node _T_300 = and(_T_299, _T_153) @[el2_lib.scala 244:41] - node _T_301 = bits(io.trigger_pkt_any[0].tdata2, 21, 21) @[el2_lib.scala 244:74] - node _T_302 = bits(dec_i0_match_data[0], 21, 21) @[el2_lib.scala 244:86] - node _T_303 = eq(_T_301, _T_302) @[el2_lib.scala 244:78] - node _T_304 = mux(_T_300, UInt<1>("h01"), _T_303) @[el2_lib.scala 244:23] - _T_150[21] <= _T_304 @[el2_lib.scala 244:17] - node _T_305 = bits(io.trigger_pkt_any[0].tdata2, 21, 0) @[el2_lib.scala 244:28] - node _T_306 = andr(_T_305) @[el2_lib.scala 244:36] - node _T_307 = and(_T_306, _T_153) @[el2_lib.scala 244:41] - node _T_308 = bits(io.trigger_pkt_any[0].tdata2, 22, 22) @[el2_lib.scala 244:74] - node _T_309 = bits(dec_i0_match_data[0], 22, 22) @[el2_lib.scala 244:86] - node _T_310 = eq(_T_308, _T_309) @[el2_lib.scala 244:78] - node _T_311 = mux(_T_307, UInt<1>("h01"), _T_310) @[el2_lib.scala 244:23] - _T_150[22] <= _T_311 @[el2_lib.scala 244:17] - node _T_312 = bits(io.trigger_pkt_any[0].tdata2, 22, 0) @[el2_lib.scala 244:28] - node _T_313 = andr(_T_312) @[el2_lib.scala 244:36] - node _T_314 = and(_T_313, _T_153) @[el2_lib.scala 244:41] - node _T_315 = bits(io.trigger_pkt_any[0].tdata2, 23, 23) @[el2_lib.scala 244:74] - node _T_316 = bits(dec_i0_match_data[0], 23, 23) @[el2_lib.scala 244:86] - node _T_317 = eq(_T_315, _T_316) @[el2_lib.scala 244:78] - node _T_318 = mux(_T_314, UInt<1>("h01"), _T_317) @[el2_lib.scala 244:23] - _T_150[23] <= _T_318 @[el2_lib.scala 244:17] - node _T_319 = bits(io.trigger_pkt_any[0].tdata2, 23, 0) @[el2_lib.scala 244:28] - node _T_320 = andr(_T_319) @[el2_lib.scala 244:36] - node _T_321 = and(_T_320, _T_153) @[el2_lib.scala 244:41] - node _T_322 = bits(io.trigger_pkt_any[0].tdata2, 24, 24) @[el2_lib.scala 244:74] - node _T_323 = bits(dec_i0_match_data[0], 24, 24) @[el2_lib.scala 244:86] - node _T_324 = eq(_T_322, _T_323) @[el2_lib.scala 244:78] - node _T_325 = mux(_T_321, UInt<1>("h01"), _T_324) @[el2_lib.scala 244:23] - _T_150[24] <= _T_325 @[el2_lib.scala 244:17] - node _T_326 = bits(io.trigger_pkt_any[0].tdata2, 24, 0) @[el2_lib.scala 244:28] - node _T_327 = andr(_T_326) @[el2_lib.scala 244:36] - node _T_328 = and(_T_327, _T_153) @[el2_lib.scala 244:41] - node _T_329 = bits(io.trigger_pkt_any[0].tdata2, 25, 25) @[el2_lib.scala 244:74] - node _T_330 = bits(dec_i0_match_data[0], 25, 25) @[el2_lib.scala 244:86] - node _T_331 = eq(_T_329, _T_330) @[el2_lib.scala 244:78] - node _T_332 = mux(_T_328, UInt<1>("h01"), _T_331) @[el2_lib.scala 244:23] - _T_150[25] <= _T_332 @[el2_lib.scala 244:17] - node _T_333 = bits(io.trigger_pkt_any[0].tdata2, 25, 0) @[el2_lib.scala 244:28] - node _T_334 = andr(_T_333) @[el2_lib.scala 244:36] - node _T_335 = and(_T_334, _T_153) @[el2_lib.scala 244:41] - node _T_336 = bits(io.trigger_pkt_any[0].tdata2, 26, 26) @[el2_lib.scala 244:74] - node _T_337 = bits(dec_i0_match_data[0], 26, 26) @[el2_lib.scala 244:86] - node _T_338 = eq(_T_336, _T_337) @[el2_lib.scala 244:78] - node _T_339 = mux(_T_335, UInt<1>("h01"), _T_338) @[el2_lib.scala 244:23] - _T_150[26] <= _T_339 @[el2_lib.scala 244:17] - node _T_340 = bits(io.trigger_pkt_any[0].tdata2, 26, 0) @[el2_lib.scala 244:28] - node _T_341 = andr(_T_340) @[el2_lib.scala 244:36] - node _T_342 = and(_T_341, _T_153) @[el2_lib.scala 244:41] - node _T_343 = bits(io.trigger_pkt_any[0].tdata2, 27, 27) @[el2_lib.scala 244:74] - node _T_344 = bits(dec_i0_match_data[0], 27, 27) @[el2_lib.scala 244:86] - node _T_345 = eq(_T_343, _T_344) @[el2_lib.scala 244:78] - node _T_346 = mux(_T_342, UInt<1>("h01"), _T_345) @[el2_lib.scala 244:23] - _T_150[27] <= _T_346 @[el2_lib.scala 244:17] - node _T_347 = bits(io.trigger_pkt_any[0].tdata2, 27, 0) @[el2_lib.scala 244:28] - node _T_348 = andr(_T_347) @[el2_lib.scala 244:36] - node _T_349 = and(_T_348, _T_153) @[el2_lib.scala 244:41] - node _T_350 = bits(io.trigger_pkt_any[0].tdata2, 28, 28) @[el2_lib.scala 244:74] - node _T_351 = bits(dec_i0_match_data[0], 28, 28) @[el2_lib.scala 244:86] - node _T_352 = eq(_T_350, _T_351) @[el2_lib.scala 244:78] - node _T_353 = mux(_T_349, UInt<1>("h01"), _T_352) @[el2_lib.scala 244:23] - _T_150[28] <= _T_353 @[el2_lib.scala 244:17] - node _T_354 = bits(io.trigger_pkt_any[0].tdata2, 28, 0) @[el2_lib.scala 244:28] - node _T_355 = andr(_T_354) @[el2_lib.scala 244:36] - node _T_356 = and(_T_355, _T_153) @[el2_lib.scala 244:41] - node _T_357 = bits(io.trigger_pkt_any[0].tdata2, 29, 29) @[el2_lib.scala 244:74] - node _T_358 = bits(dec_i0_match_data[0], 29, 29) @[el2_lib.scala 244:86] - node _T_359 = eq(_T_357, _T_358) @[el2_lib.scala 244:78] - node _T_360 = mux(_T_356, UInt<1>("h01"), _T_359) @[el2_lib.scala 244:23] - _T_150[29] <= _T_360 @[el2_lib.scala 244:17] - node _T_361 = bits(io.trigger_pkt_any[0].tdata2, 29, 0) @[el2_lib.scala 244:28] - node _T_362 = andr(_T_361) @[el2_lib.scala 244:36] - node _T_363 = and(_T_362, _T_153) @[el2_lib.scala 244:41] - node _T_364 = bits(io.trigger_pkt_any[0].tdata2, 30, 30) @[el2_lib.scala 244:74] - node _T_365 = bits(dec_i0_match_data[0], 30, 30) @[el2_lib.scala 244:86] - node _T_366 = eq(_T_364, _T_365) @[el2_lib.scala 244:78] - node _T_367 = mux(_T_363, UInt<1>("h01"), _T_366) @[el2_lib.scala 244:23] - _T_150[30] <= _T_367 @[el2_lib.scala 244:17] - node _T_368 = bits(io.trigger_pkt_any[0].tdata2, 30, 0) @[el2_lib.scala 244:28] - node _T_369 = andr(_T_368) @[el2_lib.scala 244:36] - node _T_370 = and(_T_369, _T_153) @[el2_lib.scala 244:41] - node _T_371 = bits(io.trigger_pkt_any[0].tdata2, 31, 31) @[el2_lib.scala 244:74] - node _T_372 = bits(dec_i0_match_data[0], 31, 31) @[el2_lib.scala 244:86] - node _T_373 = eq(_T_371, _T_372) @[el2_lib.scala 244:78] - node _T_374 = mux(_T_370, UInt<1>("h01"), _T_373) @[el2_lib.scala 244:23] - _T_150[31] <= _T_374 @[el2_lib.scala 244:17] - node _T_375 = cat(_T_150[1], _T_150[0]) @[el2_lib.scala 245:14] - node _T_376 = cat(_T_150[3], _T_150[2]) @[el2_lib.scala 245:14] - node _T_377 = cat(_T_376, _T_375) @[el2_lib.scala 245:14] - node _T_378 = cat(_T_150[5], _T_150[4]) @[el2_lib.scala 245:14] - node _T_379 = cat(_T_150[7], _T_150[6]) @[el2_lib.scala 245:14] - node _T_380 = cat(_T_379, _T_378) @[el2_lib.scala 245:14] - node _T_381 = cat(_T_380, _T_377) @[el2_lib.scala 245:14] - node _T_382 = cat(_T_150[9], _T_150[8]) @[el2_lib.scala 245:14] - node _T_383 = cat(_T_150[11], _T_150[10]) @[el2_lib.scala 245:14] - node _T_384 = cat(_T_383, _T_382) @[el2_lib.scala 245:14] - node _T_385 = cat(_T_150[13], _T_150[12]) @[el2_lib.scala 245:14] - node _T_386 = cat(_T_150[15], _T_150[14]) @[el2_lib.scala 245:14] - node _T_387 = cat(_T_386, _T_385) @[el2_lib.scala 245:14] - node _T_388 = cat(_T_387, _T_384) @[el2_lib.scala 245:14] - node _T_389 = cat(_T_388, _T_381) @[el2_lib.scala 245:14] - node _T_390 = cat(_T_150[17], _T_150[16]) @[el2_lib.scala 245:14] - node _T_391 = cat(_T_150[19], _T_150[18]) @[el2_lib.scala 245:14] - node _T_392 = cat(_T_391, _T_390) @[el2_lib.scala 245:14] - node _T_393 = cat(_T_150[21], _T_150[20]) @[el2_lib.scala 245:14] - node _T_394 = cat(_T_150[23], _T_150[22]) @[el2_lib.scala 245:14] - node _T_395 = cat(_T_394, _T_393) @[el2_lib.scala 245:14] - node _T_396 = cat(_T_395, _T_392) @[el2_lib.scala 245:14] - node _T_397 = cat(_T_150[25], _T_150[24]) @[el2_lib.scala 245:14] - node _T_398 = cat(_T_150[27], _T_150[26]) @[el2_lib.scala 245:14] - node _T_399 = cat(_T_398, _T_397) @[el2_lib.scala 245:14] - node _T_400 = cat(_T_150[29], _T_150[28]) @[el2_lib.scala 245:14] - node _T_401 = cat(_T_150[31], _T_150[30]) @[el2_lib.scala 245:14] - node _T_402 = cat(_T_401, _T_400) @[el2_lib.scala 245:14] - node _T_403 = cat(_T_402, _T_399) @[el2_lib.scala 245:14] - node _T_404 = cat(_T_403, _T_396) @[el2_lib.scala 245:14] - node _T_405 = cat(_T_404, _T_389) @[el2_lib.scala 245:14] - node _T_406 = andr(_T_405) @[el2_lib.scala 245:25] + wire _T_150 : UInt<1>[32] @[lib.scala 100:24] + node _T_151 = andr(io.trigger_pkt_any[0].tdata2) @[lib.scala 101:45] + node _T_152 = not(_T_151) @[lib.scala 101:39] + node _T_153 = and(_T_149, _T_152) @[lib.scala 101:37] + node _T_154 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[lib.scala 102:48] + node _T_155 = bits(dec_i0_match_data[0], 0, 0) @[lib.scala 102:60] + node _T_156 = eq(_T_154, _T_155) @[lib.scala 102:52] + node _T_157 = or(_T_153, _T_156) @[lib.scala 102:41] + _T_150[0] <= _T_157 @[lib.scala 102:18] + node _T_158 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[lib.scala 104:28] + node _T_159 = andr(_T_158) @[lib.scala 104:36] + node _T_160 = and(_T_159, _T_153) @[lib.scala 104:41] + node _T_161 = bits(io.trigger_pkt_any[0].tdata2, 1, 1) @[lib.scala 104:74] + node _T_162 = bits(dec_i0_match_data[0], 1, 1) @[lib.scala 104:86] + node _T_163 = eq(_T_161, _T_162) @[lib.scala 104:78] + node _T_164 = mux(_T_160, UInt<1>("h01"), _T_163) @[lib.scala 104:23] + _T_150[1] <= _T_164 @[lib.scala 104:17] + node _T_165 = bits(io.trigger_pkt_any[0].tdata2, 1, 0) @[lib.scala 104:28] + node _T_166 = andr(_T_165) @[lib.scala 104:36] + node _T_167 = and(_T_166, _T_153) @[lib.scala 104:41] + node _T_168 = bits(io.trigger_pkt_any[0].tdata2, 2, 2) @[lib.scala 104:74] + node _T_169 = bits(dec_i0_match_data[0], 2, 2) @[lib.scala 104:86] + node _T_170 = eq(_T_168, _T_169) @[lib.scala 104:78] + node _T_171 = mux(_T_167, UInt<1>("h01"), _T_170) @[lib.scala 104:23] + _T_150[2] <= _T_171 @[lib.scala 104:17] + node _T_172 = bits(io.trigger_pkt_any[0].tdata2, 2, 0) @[lib.scala 104:28] + node _T_173 = andr(_T_172) @[lib.scala 104:36] + node _T_174 = and(_T_173, _T_153) @[lib.scala 104:41] + node _T_175 = bits(io.trigger_pkt_any[0].tdata2, 3, 3) @[lib.scala 104:74] + node _T_176 = bits(dec_i0_match_data[0], 3, 3) @[lib.scala 104:86] + node _T_177 = eq(_T_175, _T_176) @[lib.scala 104:78] + node _T_178 = mux(_T_174, UInt<1>("h01"), _T_177) @[lib.scala 104:23] + _T_150[3] <= _T_178 @[lib.scala 104:17] + node _T_179 = bits(io.trigger_pkt_any[0].tdata2, 3, 0) @[lib.scala 104:28] + node _T_180 = andr(_T_179) @[lib.scala 104:36] + node _T_181 = and(_T_180, _T_153) @[lib.scala 104:41] + node _T_182 = bits(io.trigger_pkt_any[0].tdata2, 4, 4) @[lib.scala 104:74] + node _T_183 = bits(dec_i0_match_data[0], 4, 4) @[lib.scala 104:86] + node _T_184 = eq(_T_182, _T_183) @[lib.scala 104:78] + node _T_185 = mux(_T_181, UInt<1>("h01"), _T_184) @[lib.scala 104:23] + _T_150[4] <= _T_185 @[lib.scala 104:17] + node _T_186 = bits(io.trigger_pkt_any[0].tdata2, 4, 0) @[lib.scala 104:28] + node _T_187 = andr(_T_186) @[lib.scala 104:36] + node _T_188 = and(_T_187, _T_153) @[lib.scala 104:41] + node _T_189 = bits(io.trigger_pkt_any[0].tdata2, 5, 5) @[lib.scala 104:74] + node _T_190 = bits(dec_i0_match_data[0], 5, 5) @[lib.scala 104:86] + node _T_191 = eq(_T_189, _T_190) @[lib.scala 104:78] + node _T_192 = mux(_T_188, UInt<1>("h01"), _T_191) @[lib.scala 104:23] + _T_150[5] <= _T_192 @[lib.scala 104:17] + node _T_193 = bits(io.trigger_pkt_any[0].tdata2, 5, 0) @[lib.scala 104:28] + node _T_194 = andr(_T_193) @[lib.scala 104:36] + node _T_195 = and(_T_194, _T_153) @[lib.scala 104:41] + node _T_196 = bits(io.trigger_pkt_any[0].tdata2, 6, 6) @[lib.scala 104:74] + node _T_197 = bits(dec_i0_match_data[0], 6, 6) @[lib.scala 104:86] + node _T_198 = eq(_T_196, _T_197) @[lib.scala 104:78] + node _T_199 = mux(_T_195, UInt<1>("h01"), _T_198) @[lib.scala 104:23] + _T_150[6] <= _T_199 @[lib.scala 104:17] + node _T_200 = bits(io.trigger_pkt_any[0].tdata2, 6, 0) @[lib.scala 104:28] + node _T_201 = andr(_T_200) @[lib.scala 104:36] + node _T_202 = and(_T_201, _T_153) @[lib.scala 104:41] + node _T_203 = bits(io.trigger_pkt_any[0].tdata2, 7, 7) @[lib.scala 104:74] + node _T_204 = bits(dec_i0_match_data[0], 7, 7) @[lib.scala 104:86] + node _T_205 = eq(_T_203, _T_204) @[lib.scala 104:78] + node _T_206 = mux(_T_202, UInt<1>("h01"), _T_205) @[lib.scala 104:23] + _T_150[7] <= _T_206 @[lib.scala 104:17] + node _T_207 = bits(io.trigger_pkt_any[0].tdata2, 7, 0) @[lib.scala 104:28] + node _T_208 = andr(_T_207) @[lib.scala 104:36] + node _T_209 = and(_T_208, _T_153) @[lib.scala 104:41] + node _T_210 = bits(io.trigger_pkt_any[0].tdata2, 8, 8) @[lib.scala 104:74] + node _T_211 = bits(dec_i0_match_data[0], 8, 8) @[lib.scala 104:86] + node _T_212 = eq(_T_210, _T_211) @[lib.scala 104:78] + node _T_213 = mux(_T_209, UInt<1>("h01"), _T_212) @[lib.scala 104:23] + _T_150[8] <= _T_213 @[lib.scala 104:17] + node _T_214 = bits(io.trigger_pkt_any[0].tdata2, 8, 0) @[lib.scala 104:28] + node _T_215 = andr(_T_214) @[lib.scala 104:36] + node _T_216 = and(_T_215, _T_153) @[lib.scala 104:41] + node _T_217 = bits(io.trigger_pkt_any[0].tdata2, 9, 9) @[lib.scala 104:74] + node _T_218 = bits(dec_i0_match_data[0], 9, 9) @[lib.scala 104:86] + node _T_219 = eq(_T_217, _T_218) @[lib.scala 104:78] + node _T_220 = mux(_T_216, UInt<1>("h01"), _T_219) @[lib.scala 104:23] + _T_150[9] <= _T_220 @[lib.scala 104:17] + node _T_221 = bits(io.trigger_pkt_any[0].tdata2, 9, 0) @[lib.scala 104:28] + node _T_222 = andr(_T_221) @[lib.scala 104:36] + node _T_223 = and(_T_222, _T_153) @[lib.scala 104:41] + node _T_224 = bits(io.trigger_pkt_any[0].tdata2, 10, 10) @[lib.scala 104:74] + node _T_225 = bits(dec_i0_match_data[0], 10, 10) @[lib.scala 104:86] + node _T_226 = eq(_T_224, _T_225) @[lib.scala 104:78] + node _T_227 = mux(_T_223, UInt<1>("h01"), _T_226) @[lib.scala 104:23] + _T_150[10] <= _T_227 @[lib.scala 104:17] + node _T_228 = bits(io.trigger_pkt_any[0].tdata2, 10, 0) @[lib.scala 104:28] + node _T_229 = andr(_T_228) @[lib.scala 104:36] + node _T_230 = and(_T_229, _T_153) @[lib.scala 104:41] + node _T_231 = bits(io.trigger_pkt_any[0].tdata2, 11, 11) @[lib.scala 104:74] + node _T_232 = bits(dec_i0_match_data[0], 11, 11) @[lib.scala 104:86] + node _T_233 = eq(_T_231, _T_232) @[lib.scala 104:78] + node _T_234 = mux(_T_230, UInt<1>("h01"), _T_233) @[lib.scala 104:23] + _T_150[11] <= _T_234 @[lib.scala 104:17] + node _T_235 = bits(io.trigger_pkt_any[0].tdata2, 11, 0) @[lib.scala 104:28] + node _T_236 = andr(_T_235) @[lib.scala 104:36] + node _T_237 = and(_T_236, _T_153) @[lib.scala 104:41] + node _T_238 = bits(io.trigger_pkt_any[0].tdata2, 12, 12) @[lib.scala 104:74] + node _T_239 = bits(dec_i0_match_data[0], 12, 12) @[lib.scala 104:86] + node _T_240 = eq(_T_238, _T_239) @[lib.scala 104:78] + node _T_241 = mux(_T_237, UInt<1>("h01"), _T_240) @[lib.scala 104:23] + _T_150[12] <= _T_241 @[lib.scala 104:17] + node _T_242 = bits(io.trigger_pkt_any[0].tdata2, 12, 0) @[lib.scala 104:28] + node _T_243 = andr(_T_242) @[lib.scala 104:36] + node _T_244 = and(_T_243, _T_153) @[lib.scala 104:41] + node _T_245 = bits(io.trigger_pkt_any[0].tdata2, 13, 13) @[lib.scala 104:74] + node _T_246 = bits(dec_i0_match_data[0], 13, 13) @[lib.scala 104:86] + node _T_247 = eq(_T_245, _T_246) @[lib.scala 104:78] + node _T_248 = mux(_T_244, UInt<1>("h01"), _T_247) @[lib.scala 104:23] + _T_150[13] <= _T_248 @[lib.scala 104:17] + node _T_249 = bits(io.trigger_pkt_any[0].tdata2, 13, 0) @[lib.scala 104:28] + node _T_250 = andr(_T_249) @[lib.scala 104:36] + node _T_251 = and(_T_250, _T_153) @[lib.scala 104:41] + node _T_252 = bits(io.trigger_pkt_any[0].tdata2, 14, 14) @[lib.scala 104:74] + node _T_253 = bits(dec_i0_match_data[0], 14, 14) @[lib.scala 104:86] + node _T_254 = eq(_T_252, _T_253) @[lib.scala 104:78] + node _T_255 = mux(_T_251, UInt<1>("h01"), _T_254) @[lib.scala 104:23] + _T_150[14] <= _T_255 @[lib.scala 104:17] + node _T_256 = bits(io.trigger_pkt_any[0].tdata2, 14, 0) @[lib.scala 104:28] + node _T_257 = andr(_T_256) @[lib.scala 104:36] + node _T_258 = and(_T_257, _T_153) @[lib.scala 104:41] + node _T_259 = bits(io.trigger_pkt_any[0].tdata2, 15, 15) @[lib.scala 104:74] + node _T_260 = bits(dec_i0_match_data[0], 15, 15) @[lib.scala 104:86] + node _T_261 = eq(_T_259, _T_260) @[lib.scala 104:78] + node _T_262 = mux(_T_258, UInt<1>("h01"), _T_261) @[lib.scala 104:23] + _T_150[15] <= _T_262 @[lib.scala 104:17] + node _T_263 = bits(io.trigger_pkt_any[0].tdata2, 15, 0) @[lib.scala 104:28] + node _T_264 = andr(_T_263) @[lib.scala 104:36] + node _T_265 = and(_T_264, _T_153) @[lib.scala 104:41] + node _T_266 = bits(io.trigger_pkt_any[0].tdata2, 16, 16) @[lib.scala 104:74] + node _T_267 = bits(dec_i0_match_data[0], 16, 16) @[lib.scala 104:86] + node _T_268 = eq(_T_266, _T_267) @[lib.scala 104:78] + node _T_269 = mux(_T_265, UInt<1>("h01"), _T_268) @[lib.scala 104:23] + _T_150[16] <= _T_269 @[lib.scala 104:17] + node _T_270 = bits(io.trigger_pkt_any[0].tdata2, 16, 0) @[lib.scala 104:28] + node _T_271 = andr(_T_270) @[lib.scala 104:36] + node _T_272 = and(_T_271, _T_153) @[lib.scala 104:41] + node _T_273 = bits(io.trigger_pkt_any[0].tdata2, 17, 17) @[lib.scala 104:74] + node _T_274 = bits(dec_i0_match_data[0], 17, 17) @[lib.scala 104:86] + node _T_275 = eq(_T_273, _T_274) @[lib.scala 104:78] + node _T_276 = mux(_T_272, UInt<1>("h01"), _T_275) @[lib.scala 104:23] + _T_150[17] <= _T_276 @[lib.scala 104:17] + node _T_277 = bits(io.trigger_pkt_any[0].tdata2, 17, 0) @[lib.scala 104:28] + node _T_278 = andr(_T_277) @[lib.scala 104:36] + node _T_279 = and(_T_278, _T_153) @[lib.scala 104:41] + node _T_280 = bits(io.trigger_pkt_any[0].tdata2, 18, 18) @[lib.scala 104:74] + node _T_281 = bits(dec_i0_match_data[0], 18, 18) @[lib.scala 104:86] + node _T_282 = eq(_T_280, _T_281) @[lib.scala 104:78] + node _T_283 = mux(_T_279, UInt<1>("h01"), _T_282) @[lib.scala 104:23] + _T_150[18] <= _T_283 @[lib.scala 104:17] + node _T_284 = bits(io.trigger_pkt_any[0].tdata2, 18, 0) @[lib.scala 104:28] + node _T_285 = andr(_T_284) @[lib.scala 104:36] + node _T_286 = and(_T_285, _T_153) @[lib.scala 104:41] + node _T_287 = bits(io.trigger_pkt_any[0].tdata2, 19, 19) @[lib.scala 104:74] + node _T_288 = bits(dec_i0_match_data[0], 19, 19) @[lib.scala 104:86] + node _T_289 = eq(_T_287, _T_288) @[lib.scala 104:78] + node _T_290 = mux(_T_286, UInt<1>("h01"), _T_289) @[lib.scala 104:23] + _T_150[19] <= _T_290 @[lib.scala 104:17] + node _T_291 = bits(io.trigger_pkt_any[0].tdata2, 19, 0) @[lib.scala 104:28] + node _T_292 = andr(_T_291) @[lib.scala 104:36] + node _T_293 = and(_T_292, _T_153) @[lib.scala 104:41] + node _T_294 = bits(io.trigger_pkt_any[0].tdata2, 20, 20) @[lib.scala 104:74] + node _T_295 = bits(dec_i0_match_data[0], 20, 20) @[lib.scala 104:86] + node _T_296 = eq(_T_294, _T_295) @[lib.scala 104:78] + node _T_297 = mux(_T_293, UInt<1>("h01"), _T_296) @[lib.scala 104:23] + _T_150[20] <= _T_297 @[lib.scala 104:17] + node _T_298 = bits(io.trigger_pkt_any[0].tdata2, 20, 0) @[lib.scala 104:28] + node _T_299 = andr(_T_298) @[lib.scala 104:36] + node _T_300 = and(_T_299, _T_153) @[lib.scala 104:41] + node _T_301 = bits(io.trigger_pkt_any[0].tdata2, 21, 21) @[lib.scala 104:74] + node _T_302 = bits(dec_i0_match_data[0], 21, 21) @[lib.scala 104:86] + node _T_303 = eq(_T_301, _T_302) @[lib.scala 104:78] + node _T_304 = mux(_T_300, UInt<1>("h01"), _T_303) @[lib.scala 104:23] + _T_150[21] <= _T_304 @[lib.scala 104:17] + node _T_305 = bits(io.trigger_pkt_any[0].tdata2, 21, 0) @[lib.scala 104:28] + node _T_306 = andr(_T_305) @[lib.scala 104:36] + node _T_307 = and(_T_306, _T_153) @[lib.scala 104:41] + node _T_308 = bits(io.trigger_pkt_any[0].tdata2, 22, 22) @[lib.scala 104:74] + node _T_309 = bits(dec_i0_match_data[0], 22, 22) @[lib.scala 104:86] + node _T_310 = eq(_T_308, _T_309) @[lib.scala 104:78] + node _T_311 = mux(_T_307, UInt<1>("h01"), _T_310) @[lib.scala 104:23] + _T_150[22] <= _T_311 @[lib.scala 104:17] + node _T_312 = bits(io.trigger_pkt_any[0].tdata2, 22, 0) @[lib.scala 104:28] + node _T_313 = andr(_T_312) @[lib.scala 104:36] + node _T_314 = and(_T_313, _T_153) @[lib.scala 104:41] + node _T_315 = bits(io.trigger_pkt_any[0].tdata2, 23, 23) @[lib.scala 104:74] + node _T_316 = bits(dec_i0_match_data[0], 23, 23) @[lib.scala 104:86] + node _T_317 = eq(_T_315, _T_316) @[lib.scala 104:78] + node _T_318 = mux(_T_314, UInt<1>("h01"), _T_317) @[lib.scala 104:23] + _T_150[23] <= _T_318 @[lib.scala 104:17] + node _T_319 = bits(io.trigger_pkt_any[0].tdata2, 23, 0) @[lib.scala 104:28] + node _T_320 = andr(_T_319) @[lib.scala 104:36] + node _T_321 = and(_T_320, _T_153) @[lib.scala 104:41] + node _T_322 = bits(io.trigger_pkt_any[0].tdata2, 24, 24) @[lib.scala 104:74] + node _T_323 = bits(dec_i0_match_data[0], 24, 24) @[lib.scala 104:86] + node _T_324 = eq(_T_322, _T_323) @[lib.scala 104:78] + node _T_325 = mux(_T_321, UInt<1>("h01"), _T_324) @[lib.scala 104:23] + _T_150[24] <= _T_325 @[lib.scala 104:17] + node _T_326 = bits(io.trigger_pkt_any[0].tdata2, 24, 0) @[lib.scala 104:28] + node _T_327 = andr(_T_326) @[lib.scala 104:36] + node _T_328 = and(_T_327, _T_153) @[lib.scala 104:41] + node _T_329 = bits(io.trigger_pkt_any[0].tdata2, 25, 25) @[lib.scala 104:74] + node _T_330 = bits(dec_i0_match_data[0], 25, 25) @[lib.scala 104:86] + node _T_331 = eq(_T_329, _T_330) @[lib.scala 104:78] + node _T_332 = mux(_T_328, UInt<1>("h01"), _T_331) @[lib.scala 104:23] + _T_150[25] <= _T_332 @[lib.scala 104:17] + node _T_333 = bits(io.trigger_pkt_any[0].tdata2, 25, 0) @[lib.scala 104:28] + node _T_334 = andr(_T_333) @[lib.scala 104:36] + node _T_335 = and(_T_334, _T_153) @[lib.scala 104:41] + node _T_336 = bits(io.trigger_pkt_any[0].tdata2, 26, 26) @[lib.scala 104:74] + node _T_337 = bits(dec_i0_match_data[0], 26, 26) @[lib.scala 104:86] + node _T_338 = eq(_T_336, _T_337) @[lib.scala 104:78] + node _T_339 = mux(_T_335, UInt<1>("h01"), _T_338) @[lib.scala 104:23] + _T_150[26] <= _T_339 @[lib.scala 104:17] + node _T_340 = bits(io.trigger_pkt_any[0].tdata2, 26, 0) @[lib.scala 104:28] + node _T_341 = andr(_T_340) @[lib.scala 104:36] + node _T_342 = and(_T_341, _T_153) @[lib.scala 104:41] + node _T_343 = bits(io.trigger_pkt_any[0].tdata2, 27, 27) @[lib.scala 104:74] + node _T_344 = bits(dec_i0_match_data[0], 27, 27) @[lib.scala 104:86] + node _T_345 = eq(_T_343, _T_344) @[lib.scala 104:78] + node _T_346 = mux(_T_342, UInt<1>("h01"), _T_345) @[lib.scala 104:23] + _T_150[27] <= _T_346 @[lib.scala 104:17] + node _T_347 = bits(io.trigger_pkt_any[0].tdata2, 27, 0) @[lib.scala 104:28] + node _T_348 = andr(_T_347) @[lib.scala 104:36] + node _T_349 = and(_T_348, _T_153) @[lib.scala 104:41] + node _T_350 = bits(io.trigger_pkt_any[0].tdata2, 28, 28) @[lib.scala 104:74] + node _T_351 = bits(dec_i0_match_data[0], 28, 28) @[lib.scala 104:86] + node _T_352 = eq(_T_350, _T_351) @[lib.scala 104:78] + node _T_353 = mux(_T_349, UInt<1>("h01"), _T_352) @[lib.scala 104:23] + _T_150[28] <= _T_353 @[lib.scala 104:17] + node _T_354 = bits(io.trigger_pkt_any[0].tdata2, 28, 0) @[lib.scala 104:28] + node _T_355 = andr(_T_354) @[lib.scala 104:36] + node _T_356 = and(_T_355, _T_153) @[lib.scala 104:41] + node _T_357 = bits(io.trigger_pkt_any[0].tdata2, 29, 29) @[lib.scala 104:74] + node _T_358 = bits(dec_i0_match_data[0], 29, 29) @[lib.scala 104:86] + node _T_359 = eq(_T_357, _T_358) @[lib.scala 104:78] + node _T_360 = mux(_T_356, UInt<1>("h01"), _T_359) @[lib.scala 104:23] + _T_150[29] <= _T_360 @[lib.scala 104:17] + node _T_361 = bits(io.trigger_pkt_any[0].tdata2, 29, 0) @[lib.scala 104:28] + node _T_362 = andr(_T_361) @[lib.scala 104:36] + node _T_363 = and(_T_362, _T_153) @[lib.scala 104:41] + node _T_364 = bits(io.trigger_pkt_any[0].tdata2, 30, 30) @[lib.scala 104:74] + node _T_365 = bits(dec_i0_match_data[0], 30, 30) @[lib.scala 104:86] + node _T_366 = eq(_T_364, _T_365) @[lib.scala 104:78] + node _T_367 = mux(_T_363, UInt<1>("h01"), _T_366) @[lib.scala 104:23] + _T_150[30] <= _T_367 @[lib.scala 104:17] + node _T_368 = bits(io.trigger_pkt_any[0].tdata2, 30, 0) @[lib.scala 104:28] + node _T_369 = andr(_T_368) @[lib.scala 104:36] + node _T_370 = and(_T_369, _T_153) @[lib.scala 104:41] + node _T_371 = bits(io.trigger_pkt_any[0].tdata2, 31, 31) @[lib.scala 104:74] + node _T_372 = bits(dec_i0_match_data[0], 31, 31) @[lib.scala 104:86] + node _T_373 = eq(_T_371, _T_372) @[lib.scala 104:78] + node _T_374 = mux(_T_370, UInt<1>("h01"), _T_373) @[lib.scala 104:23] + _T_150[31] <= _T_374 @[lib.scala 104:17] + node _T_375 = cat(_T_150[1], _T_150[0]) @[lib.scala 105:14] + node _T_376 = cat(_T_150[3], _T_150[2]) @[lib.scala 105:14] + node _T_377 = cat(_T_376, _T_375) @[lib.scala 105:14] + node _T_378 = cat(_T_150[5], _T_150[4]) @[lib.scala 105:14] + node _T_379 = cat(_T_150[7], _T_150[6]) @[lib.scala 105:14] + node _T_380 = cat(_T_379, _T_378) @[lib.scala 105:14] + node _T_381 = cat(_T_380, _T_377) @[lib.scala 105:14] + node _T_382 = cat(_T_150[9], _T_150[8]) @[lib.scala 105:14] + node _T_383 = cat(_T_150[11], _T_150[10]) @[lib.scala 105:14] + node _T_384 = cat(_T_383, _T_382) @[lib.scala 105:14] + node _T_385 = cat(_T_150[13], _T_150[12]) @[lib.scala 105:14] + node _T_386 = cat(_T_150[15], _T_150[14]) @[lib.scala 105:14] + node _T_387 = cat(_T_386, _T_385) @[lib.scala 105:14] + node _T_388 = cat(_T_387, _T_384) @[lib.scala 105:14] + node _T_389 = cat(_T_388, _T_381) @[lib.scala 105:14] + node _T_390 = cat(_T_150[17], _T_150[16]) @[lib.scala 105:14] + node _T_391 = cat(_T_150[19], _T_150[18]) @[lib.scala 105:14] + node _T_392 = cat(_T_391, _T_390) @[lib.scala 105:14] + node _T_393 = cat(_T_150[21], _T_150[20]) @[lib.scala 105:14] + node _T_394 = cat(_T_150[23], _T_150[22]) @[lib.scala 105:14] + node _T_395 = cat(_T_394, _T_393) @[lib.scala 105:14] + node _T_396 = cat(_T_395, _T_392) @[lib.scala 105:14] + node _T_397 = cat(_T_150[25], _T_150[24]) @[lib.scala 105:14] + node _T_398 = cat(_T_150[27], _T_150[26]) @[lib.scala 105:14] + node _T_399 = cat(_T_398, _T_397) @[lib.scala 105:14] + node _T_400 = cat(_T_150[29], _T_150[28]) @[lib.scala 105:14] + node _T_401 = cat(_T_150[31], _T_150[30]) @[lib.scala 105:14] + node _T_402 = cat(_T_401, _T_400) @[lib.scala 105:14] + node _T_403 = cat(_T_402, _T_399) @[lib.scala 105:14] + node _T_404 = cat(_T_403, _T_396) @[lib.scala 105:14] + node _T_405 = cat(_T_404, _T_389) @[lib.scala 105:14] + node _T_406 = andr(_T_405) @[lib.scala 105:25] node _T_407 = and(_T_148, _T_406) @[dec_trigger.scala 15:109] node _T_408 = and(io.trigger_pkt_any[1].execute, io.trigger_pkt_any[1].m) @[dec_trigger.scala 15:83] node _T_409 = bits(io.trigger_pkt_any[1].match_pkt, 0, 0) @[dec_trigger.scala 15:216] - wire _T_410 : UInt<1>[32] @[el2_lib.scala 240:24] - node _T_411 = andr(io.trigger_pkt_any[1].tdata2) @[el2_lib.scala 241:45] - node _T_412 = not(_T_411) @[el2_lib.scala 241:39] - node _T_413 = and(_T_409, _T_412) @[el2_lib.scala 241:37] - node _T_414 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[el2_lib.scala 242:48] - node _T_415 = bits(dec_i0_match_data[1], 0, 0) @[el2_lib.scala 242:60] - node _T_416 = eq(_T_414, _T_415) @[el2_lib.scala 242:52] - node _T_417 = or(_T_413, _T_416) @[el2_lib.scala 242:41] - _T_410[0] <= _T_417 @[el2_lib.scala 242:18] - node _T_418 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[el2_lib.scala 244:28] - node _T_419 = andr(_T_418) @[el2_lib.scala 244:36] - node _T_420 = and(_T_419, _T_413) @[el2_lib.scala 244:41] - node _T_421 = bits(io.trigger_pkt_any[1].tdata2, 1, 1) @[el2_lib.scala 244:74] - node _T_422 = bits(dec_i0_match_data[1], 1, 1) @[el2_lib.scala 244:86] - node _T_423 = eq(_T_421, _T_422) @[el2_lib.scala 244:78] - node _T_424 = mux(_T_420, UInt<1>("h01"), _T_423) @[el2_lib.scala 244:23] - _T_410[1] <= _T_424 @[el2_lib.scala 244:17] - node _T_425 = bits(io.trigger_pkt_any[1].tdata2, 1, 0) @[el2_lib.scala 244:28] - node _T_426 = andr(_T_425) @[el2_lib.scala 244:36] - node _T_427 = and(_T_426, _T_413) @[el2_lib.scala 244:41] - node _T_428 = bits(io.trigger_pkt_any[1].tdata2, 2, 2) @[el2_lib.scala 244:74] - node _T_429 = bits(dec_i0_match_data[1], 2, 2) @[el2_lib.scala 244:86] - node _T_430 = eq(_T_428, _T_429) @[el2_lib.scala 244:78] - node _T_431 = mux(_T_427, UInt<1>("h01"), _T_430) @[el2_lib.scala 244:23] - _T_410[2] <= _T_431 @[el2_lib.scala 244:17] - node _T_432 = bits(io.trigger_pkt_any[1].tdata2, 2, 0) @[el2_lib.scala 244:28] - node _T_433 = andr(_T_432) @[el2_lib.scala 244:36] - node _T_434 = and(_T_433, _T_413) @[el2_lib.scala 244:41] - node _T_435 = bits(io.trigger_pkt_any[1].tdata2, 3, 3) @[el2_lib.scala 244:74] - node _T_436 = bits(dec_i0_match_data[1], 3, 3) @[el2_lib.scala 244:86] - node _T_437 = eq(_T_435, _T_436) @[el2_lib.scala 244:78] - node _T_438 = mux(_T_434, UInt<1>("h01"), _T_437) @[el2_lib.scala 244:23] - _T_410[3] <= _T_438 @[el2_lib.scala 244:17] - node _T_439 = bits(io.trigger_pkt_any[1].tdata2, 3, 0) @[el2_lib.scala 244:28] - node _T_440 = andr(_T_439) @[el2_lib.scala 244:36] - node _T_441 = and(_T_440, _T_413) @[el2_lib.scala 244:41] - node _T_442 = bits(io.trigger_pkt_any[1].tdata2, 4, 4) @[el2_lib.scala 244:74] - node _T_443 = bits(dec_i0_match_data[1], 4, 4) @[el2_lib.scala 244:86] - node _T_444 = eq(_T_442, _T_443) @[el2_lib.scala 244:78] - node _T_445 = mux(_T_441, UInt<1>("h01"), _T_444) @[el2_lib.scala 244:23] - _T_410[4] <= _T_445 @[el2_lib.scala 244:17] - node _T_446 = bits(io.trigger_pkt_any[1].tdata2, 4, 0) @[el2_lib.scala 244:28] - node _T_447 = andr(_T_446) @[el2_lib.scala 244:36] - node _T_448 = and(_T_447, _T_413) @[el2_lib.scala 244:41] - node _T_449 = bits(io.trigger_pkt_any[1].tdata2, 5, 5) @[el2_lib.scala 244:74] - node _T_450 = bits(dec_i0_match_data[1], 5, 5) @[el2_lib.scala 244:86] - node _T_451 = eq(_T_449, _T_450) @[el2_lib.scala 244:78] - node _T_452 = mux(_T_448, UInt<1>("h01"), _T_451) @[el2_lib.scala 244:23] - _T_410[5] <= _T_452 @[el2_lib.scala 244:17] - node _T_453 = bits(io.trigger_pkt_any[1].tdata2, 5, 0) @[el2_lib.scala 244:28] - node _T_454 = andr(_T_453) @[el2_lib.scala 244:36] - node _T_455 = and(_T_454, _T_413) @[el2_lib.scala 244:41] - node _T_456 = bits(io.trigger_pkt_any[1].tdata2, 6, 6) @[el2_lib.scala 244:74] - node _T_457 = bits(dec_i0_match_data[1], 6, 6) @[el2_lib.scala 244:86] - node _T_458 = eq(_T_456, _T_457) @[el2_lib.scala 244:78] - node _T_459 = mux(_T_455, UInt<1>("h01"), _T_458) @[el2_lib.scala 244:23] - _T_410[6] <= _T_459 @[el2_lib.scala 244:17] - node _T_460 = bits(io.trigger_pkt_any[1].tdata2, 6, 0) @[el2_lib.scala 244:28] - node _T_461 = andr(_T_460) @[el2_lib.scala 244:36] - node _T_462 = and(_T_461, _T_413) @[el2_lib.scala 244:41] - node _T_463 = bits(io.trigger_pkt_any[1].tdata2, 7, 7) @[el2_lib.scala 244:74] - node _T_464 = bits(dec_i0_match_data[1], 7, 7) @[el2_lib.scala 244:86] - node _T_465 = eq(_T_463, _T_464) @[el2_lib.scala 244:78] - node _T_466 = mux(_T_462, UInt<1>("h01"), _T_465) @[el2_lib.scala 244:23] - _T_410[7] <= _T_466 @[el2_lib.scala 244:17] - node _T_467 = bits(io.trigger_pkt_any[1].tdata2, 7, 0) @[el2_lib.scala 244:28] - node _T_468 = andr(_T_467) @[el2_lib.scala 244:36] - node _T_469 = and(_T_468, _T_413) @[el2_lib.scala 244:41] - node _T_470 = bits(io.trigger_pkt_any[1].tdata2, 8, 8) @[el2_lib.scala 244:74] - node _T_471 = bits(dec_i0_match_data[1], 8, 8) @[el2_lib.scala 244:86] - node _T_472 = eq(_T_470, _T_471) @[el2_lib.scala 244:78] - node _T_473 = mux(_T_469, UInt<1>("h01"), _T_472) @[el2_lib.scala 244:23] - _T_410[8] <= _T_473 @[el2_lib.scala 244:17] - node _T_474 = bits(io.trigger_pkt_any[1].tdata2, 8, 0) @[el2_lib.scala 244:28] - node _T_475 = andr(_T_474) @[el2_lib.scala 244:36] - node _T_476 = and(_T_475, _T_413) @[el2_lib.scala 244:41] - node _T_477 = bits(io.trigger_pkt_any[1].tdata2, 9, 9) @[el2_lib.scala 244:74] - node _T_478 = bits(dec_i0_match_data[1], 9, 9) @[el2_lib.scala 244:86] - node _T_479 = eq(_T_477, _T_478) @[el2_lib.scala 244:78] - node _T_480 = mux(_T_476, UInt<1>("h01"), _T_479) @[el2_lib.scala 244:23] - _T_410[9] <= _T_480 @[el2_lib.scala 244:17] - node _T_481 = bits(io.trigger_pkt_any[1].tdata2, 9, 0) @[el2_lib.scala 244:28] - node _T_482 = andr(_T_481) @[el2_lib.scala 244:36] - node _T_483 = and(_T_482, _T_413) @[el2_lib.scala 244:41] - node _T_484 = bits(io.trigger_pkt_any[1].tdata2, 10, 10) @[el2_lib.scala 244:74] - node _T_485 = bits(dec_i0_match_data[1], 10, 10) @[el2_lib.scala 244:86] - node _T_486 = eq(_T_484, _T_485) @[el2_lib.scala 244:78] - node _T_487 = mux(_T_483, UInt<1>("h01"), _T_486) @[el2_lib.scala 244:23] - _T_410[10] <= _T_487 @[el2_lib.scala 244:17] - node _T_488 = bits(io.trigger_pkt_any[1].tdata2, 10, 0) @[el2_lib.scala 244:28] - node _T_489 = andr(_T_488) @[el2_lib.scala 244:36] - node _T_490 = and(_T_489, _T_413) @[el2_lib.scala 244:41] - node _T_491 = bits(io.trigger_pkt_any[1].tdata2, 11, 11) @[el2_lib.scala 244:74] - node _T_492 = bits(dec_i0_match_data[1], 11, 11) @[el2_lib.scala 244:86] - node _T_493 = eq(_T_491, _T_492) @[el2_lib.scala 244:78] - node _T_494 = mux(_T_490, UInt<1>("h01"), _T_493) @[el2_lib.scala 244:23] - _T_410[11] <= _T_494 @[el2_lib.scala 244:17] - node _T_495 = bits(io.trigger_pkt_any[1].tdata2, 11, 0) @[el2_lib.scala 244:28] - node _T_496 = andr(_T_495) @[el2_lib.scala 244:36] - node _T_497 = and(_T_496, _T_413) @[el2_lib.scala 244:41] - node _T_498 = bits(io.trigger_pkt_any[1].tdata2, 12, 12) @[el2_lib.scala 244:74] - node _T_499 = bits(dec_i0_match_data[1], 12, 12) @[el2_lib.scala 244:86] - node _T_500 = eq(_T_498, _T_499) @[el2_lib.scala 244:78] - node _T_501 = mux(_T_497, UInt<1>("h01"), _T_500) @[el2_lib.scala 244:23] - _T_410[12] <= _T_501 @[el2_lib.scala 244:17] - node _T_502 = bits(io.trigger_pkt_any[1].tdata2, 12, 0) @[el2_lib.scala 244:28] - node _T_503 = andr(_T_502) @[el2_lib.scala 244:36] - node _T_504 = and(_T_503, _T_413) @[el2_lib.scala 244:41] - node _T_505 = bits(io.trigger_pkt_any[1].tdata2, 13, 13) @[el2_lib.scala 244:74] - node _T_506 = bits(dec_i0_match_data[1], 13, 13) @[el2_lib.scala 244:86] - node _T_507 = eq(_T_505, _T_506) @[el2_lib.scala 244:78] - node _T_508 = mux(_T_504, UInt<1>("h01"), _T_507) @[el2_lib.scala 244:23] - _T_410[13] <= _T_508 @[el2_lib.scala 244:17] - node _T_509 = bits(io.trigger_pkt_any[1].tdata2, 13, 0) @[el2_lib.scala 244:28] - node _T_510 = andr(_T_509) @[el2_lib.scala 244:36] - node _T_511 = and(_T_510, _T_413) @[el2_lib.scala 244:41] - node _T_512 = bits(io.trigger_pkt_any[1].tdata2, 14, 14) @[el2_lib.scala 244:74] - node _T_513 = bits(dec_i0_match_data[1], 14, 14) @[el2_lib.scala 244:86] - node _T_514 = eq(_T_512, _T_513) @[el2_lib.scala 244:78] - node _T_515 = mux(_T_511, UInt<1>("h01"), _T_514) @[el2_lib.scala 244:23] - _T_410[14] <= _T_515 @[el2_lib.scala 244:17] - node _T_516 = bits(io.trigger_pkt_any[1].tdata2, 14, 0) @[el2_lib.scala 244:28] - node _T_517 = andr(_T_516) @[el2_lib.scala 244:36] - node _T_518 = and(_T_517, _T_413) @[el2_lib.scala 244:41] - node _T_519 = bits(io.trigger_pkt_any[1].tdata2, 15, 15) @[el2_lib.scala 244:74] - node _T_520 = bits(dec_i0_match_data[1], 15, 15) @[el2_lib.scala 244:86] - node _T_521 = eq(_T_519, _T_520) @[el2_lib.scala 244:78] - node _T_522 = mux(_T_518, UInt<1>("h01"), _T_521) @[el2_lib.scala 244:23] - _T_410[15] <= _T_522 @[el2_lib.scala 244:17] - node _T_523 = bits(io.trigger_pkt_any[1].tdata2, 15, 0) @[el2_lib.scala 244:28] - node _T_524 = andr(_T_523) @[el2_lib.scala 244:36] - node _T_525 = and(_T_524, _T_413) @[el2_lib.scala 244:41] - node _T_526 = bits(io.trigger_pkt_any[1].tdata2, 16, 16) @[el2_lib.scala 244:74] - node _T_527 = bits(dec_i0_match_data[1], 16, 16) @[el2_lib.scala 244:86] - node _T_528 = eq(_T_526, _T_527) @[el2_lib.scala 244:78] - node _T_529 = mux(_T_525, UInt<1>("h01"), _T_528) @[el2_lib.scala 244:23] - _T_410[16] <= _T_529 @[el2_lib.scala 244:17] - node _T_530 = bits(io.trigger_pkt_any[1].tdata2, 16, 0) @[el2_lib.scala 244:28] - node _T_531 = andr(_T_530) @[el2_lib.scala 244:36] - node _T_532 = and(_T_531, _T_413) @[el2_lib.scala 244:41] - node _T_533 = bits(io.trigger_pkt_any[1].tdata2, 17, 17) @[el2_lib.scala 244:74] - node _T_534 = bits(dec_i0_match_data[1], 17, 17) @[el2_lib.scala 244:86] - node _T_535 = eq(_T_533, _T_534) @[el2_lib.scala 244:78] - node _T_536 = mux(_T_532, UInt<1>("h01"), _T_535) @[el2_lib.scala 244:23] - _T_410[17] <= _T_536 @[el2_lib.scala 244:17] - node _T_537 = bits(io.trigger_pkt_any[1].tdata2, 17, 0) @[el2_lib.scala 244:28] - node _T_538 = andr(_T_537) @[el2_lib.scala 244:36] - node _T_539 = and(_T_538, _T_413) @[el2_lib.scala 244:41] - node _T_540 = bits(io.trigger_pkt_any[1].tdata2, 18, 18) @[el2_lib.scala 244:74] - node _T_541 = bits(dec_i0_match_data[1], 18, 18) @[el2_lib.scala 244:86] - node _T_542 = eq(_T_540, _T_541) @[el2_lib.scala 244:78] - node _T_543 = mux(_T_539, UInt<1>("h01"), _T_542) @[el2_lib.scala 244:23] - _T_410[18] <= _T_543 @[el2_lib.scala 244:17] - node _T_544 = bits(io.trigger_pkt_any[1].tdata2, 18, 0) @[el2_lib.scala 244:28] - node _T_545 = andr(_T_544) @[el2_lib.scala 244:36] - node _T_546 = and(_T_545, _T_413) @[el2_lib.scala 244:41] - node _T_547 = bits(io.trigger_pkt_any[1].tdata2, 19, 19) @[el2_lib.scala 244:74] - node _T_548 = bits(dec_i0_match_data[1], 19, 19) @[el2_lib.scala 244:86] - node _T_549 = eq(_T_547, _T_548) @[el2_lib.scala 244:78] - node _T_550 = mux(_T_546, UInt<1>("h01"), _T_549) @[el2_lib.scala 244:23] - _T_410[19] <= _T_550 @[el2_lib.scala 244:17] - node _T_551 = bits(io.trigger_pkt_any[1].tdata2, 19, 0) @[el2_lib.scala 244:28] - node _T_552 = andr(_T_551) @[el2_lib.scala 244:36] - node _T_553 = and(_T_552, _T_413) @[el2_lib.scala 244:41] - node _T_554 = bits(io.trigger_pkt_any[1].tdata2, 20, 20) @[el2_lib.scala 244:74] - node _T_555 = bits(dec_i0_match_data[1], 20, 20) @[el2_lib.scala 244:86] - node _T_556 = eq(_T_554, _T_555) @[el2_lib.scala 244:78] - node _T_557 = mux(_T_553, UInt<1>("h01"), _T_556) @[el2_lib.scala 244:23] - _T_410[20] <= _T_557 @[el2_lib.scala 244:17] - node _T_558 = bits(io.trigger_pkt_any[1].tdata2, 20, 0) @[el2_lib.scala 244:28] - node _T_559 = andr(_T_558) @[el2_lib.scala 244:36] - node _T_560 = and(_T_559, _T_413) @[el2_lib.scala 244:41] - node _T_561 = bits(io.trigger_pkt_any[1].tdata2, 21, 21) @[el2_lib.scala 244:74] - node _T_562 = bits(dec_i0_match_data[1], 21, 21) @[el2_lib.scala 244:86] - node _T_563 = eq(_T_561, _T_562) @[el2_lib.scala 244:78] - node _T_564 = mux(_T_560, UInt<1>("h01"), _T_563) @[el2_lib.scala 244:23] - _T_410[21] <= _T_564 @[el2_lib.scala 244:17] - node _T_565 = bits(io.trigger_pkt_any[1].tdata2, 21, 0) @[el2_lib.scala 244:28] - node _T_566 = andr(_T_565) @[el2_lib.scala 244:36] - node _T_567 = and(_T_566, _T_413) @[el2_lib.scala 244:41] - node _T_568 = bits(io.trigger_pkt_any[1].tdata2, 22, 22) @[el2_lib.scala 244:74] - node _T_569 = bits(dec_i0_match_data[1], 22, 22) @[el2_lib.scala 244:86] - node _T_570 = eq(_T_568, _T_569) @[el2_lib.scala 244:78] - node _T_571 = mux(_T_567, UInt<1>("h01"), _T_570) @[el2_lib.scala 244:23] - _T_410[22] <= _T_571 @[el2_lib.scala 244:17] - node _T_572 = bits(io.trigger_pkt_any[1].tdata2, 22, 0) @[el2_lib.scala 244:28] - node _T_573 = andr(_T_572) @[el2_lib.scala 244:36] - node _T_574 = and(_T_573, _T_413) @[el2_lib.scala 244:41] - node _T_575 = bits(io.trigger_pkt_any[1].tdata2, 23, 23) @[el2_lib.scala 244:74] - node _T_576 = bits(dec_i0_match_data[1], 23, 23) @[el2_lib.scala 244:86] - node _T_577 = eq(_T_575, _T_576) @[el2_lib.scala 244:78] - node _T_578 = mux(_T_574, UInt<1>("h01"), _T_577) @[el2_lib.scala 244:23] - _T_410[23] <= _T_578 @[el2_lib.scala 244:17] - node _T_579 = bits(io.trigger_pkt_any[1].tdata2, 23, 0) @[el2_lib.scala 244:28] - node _T_580 = andr(_T_579) @[el2_lib.scala 244:36] - node _T_581 = and(_T_580, _T_413) @[el2_lib.scala 244:41] - node _T_582 = bits(io.trigger_pkt_any[1].tdata2, 24, 24) @[el2_lib.scala 244:74] - node _T_583 = bits(dec_i0_match_data[1], 24, 24) @[el2_lib.scala 244:86] - node _T_584 = eq(_T_582, _T_583) @[el2_lib.scala 244:78] - node _T_585 = mux(_T_581, UInt<1>("h01"), _T_584) @[el2_lib.scala 244:23] - _T_410[24] <= _T_585 @[el2_lib.scala 244:17] - node _T_586 = bits(io.trigger_pkt_any[1].tdata2, 24, 0) @[el2_lib.scala 244:28] - node _T_587 = andr(_T_586) @[el2_lib.scala 244:36] - node _T_588 = and(_T_587, _T_413) @[el2_lib.scala 244:41] - node _T_589 = bits(io.trigger_pkt_any[1].tdata2, 25, 25) @[el2_lib.scala 244:74] - node _T_590 = bits(dec_i0_match_data[1], 25, 25) @[el2_lib.scala 244:86] - node _T_591 = eq(_T_589, _T_590) @[el2_lib.scala 244:78] - node _T_592 = mux(_T_588, UInt<1>("h01"), _T_591) @[el2_lib.scala 244:23] - _T_410[25] <= _T_592 @[el2_lib.scala 244:17] - node _T_593 = bits(io.trigger_pkt_any[1].tdata2, 25, 0) @[el2_lib.scala 244:28] - node _T_594 = andr(_T_593) @[el2_lib.scala 244:36] - node _T_595 = and(_T_594, _T_413) @[el2_lib.scala 244:41] - node _T_596 = bits(io.trigger_pkt_any[1].tdata2, 26, 26) @[el2_lib.scala 244:74] - node _T_597 = bits(dec_i0_match_data[1], 26, 26) @[el2_lib.scala 244:86] - node _T_598 = eq(_T_596, _T_597) @[el2_lib.scala 244:78] - node _T_599 = mux(_T_595, UInt<1>("h01"), _T_598) @[el2_lib.scala 244:23] - _T_410[26] <= _T_599 @[el2_lib.scala 244:17] - node _T_600 = bits(io.trigger_pkt_any[1].tdata2, 26, 0) @[el2_lib.scala 244:28] - node _T_601 = andr(_T_600) @[el2_lib.scala 244:36] - node _T_602 = and(_T_601, _T_413) @[el2_lib.scala 244:41] - node _T_603 = bits(io.trigger_pkt_any[1].tdata2, 27, 27) @[el2_lib.scala 244:74] - node _T_604 = bits(dec_i0_match_data[1], 27, 27) @[el2_lib.scala 244:86] - node _T_605 = eq(_T_603, _T_604) @[el2_lib.scala 244:78] - node _T_606 = mux(_T_602, UInt<1>("h01"), _T_605) @[el2_lib.scala 244:23] - _T_410[27] <= _T_606 @[el2_lib.scala 244:17] - node _T_607 = bits(io.trigger_pkt_any[1].tdata2, 27, 0) @[el2_lib.scala 244:28] - node _T_608 = andr(_T_607) @[el2_lib.scala 244:36] - node _T_609 = and(_T_608, _T_413) @[el2_lib.scala 244:41] - node _T_610 = bits(io.trigger_pkt_any[1].tdata2, 28, 28) @[el2_lib.scala 244:74] - node _T_611 = bits(dec_i0_match_data[1], 28, 28) @[el2_lib.scala 244:86] - node _T_612 = eq(_T_610, _T_611) @[el2_lib.scala 244:78] - node _T_613 = mux(_T_609, UInt<1>("h01"), _T_612) @[el2_lib.scala 244:23] - _T_410[28] <= _T_613 @[el2_lib.scala 244:17] - node _T_614 = bits(io.trigger_pkt_any[1].tdata2, 28, 0) @[el2_lib.scala 244:28] - node _T_615 = andr(_T_614) @[el2_lib.scala 244:36] - node _T_616 = and(_T_615, _T_413) @[el2_lib.scala 244:41] - node _T_617 = bits(io.trigger_pkt_any[1].tdata2, 29, 29) @[el2_lib.scala 244:74] - node _T_618 = bits(dec_i0_match_data[1], 29, 29) @[el2_lib.scala 244:86] - node _T_619 = eq(_T_617, _T_618) @[el2_lib.scala 244:78] - node _T_620 = mux(_T_616, UInt<1>("h01"), _T_619) @[el2_lib.scala 244:23] - _T_410[29] <= _T_620 @[el2_lib.scala 244:17] - node _T_621 = bits(io.trigger_pkt_any[1].tdata2, 29, 0) @[el2_lib.scala 244:28] - node _T_622 = andr(_T_621) @[el2_lib.scala 244:36] - node _T_623 = and(_T_622, _T_413) @[el2_lib.scala 244:41] - node _T_624 = bits(io.trigger_pkt_any[1].tdata2, 30, 30) @[el2_lib.scala 244:74] - node _T_625 = bits(dec_i0_match_data[1], 30, 30) @[el2_lib.scala 244:86] - node _T_626 = eq(_T_624, _T_625) @[el2_lib.scala 244:78] - node _T_627 = mux(_T_623, UInt<1>("h01"), _T_626) @[el2_lib.scala 244:23] - _T_410[30] <= _T_627 @[el2_lib.scala 244:17] - node _T_628 = bits(io.trigger_pkt_any[1].tdata2, 30, 0) @[el2_lib.scala 244:28] - node _T_629 = andr(_T_628) @[el2_lib.scala 244:36] - node _T_630 = and(_T_629, _T_413) @[el2_lib.scala 244:41] - node _T_631 = bits(io.trigger_pkt_any[1].tdata2, 31, 31) @[el2_lib.scala 244:74] - node _T_632 = bits(dec_i0_match_data[1], 31, 31) @[el2_lib.scala 244:86] - node _T_633 = eq(_T_631, _T_632) @[el2_lib.scala 244:78] - node _T_634 = mux(_T_630, UInt<1>("h01"), _T_633) @[el2_lib.scala 244:23] - _T_410[31] <= _T_634 @[el2_lib.scala 244:17] - node _T_635 = cat(_T_410[1], _T_410[0]) @[el2_lib.scala 245:14] - node _T_636 = cat(_T_410[3], _T_410[2]) @[el2_lib.scala 245:14] - node _T_637 = cat(_T_636, _T_635) @[el2_lib.scala 245:14] - node _T_638 = cat(_T_410[5], _T_410[4]) @[el2_lib.scala 245:14] - node _T_639 = cat(_T_410[7], _T_410[6]) @[el2_lib.scala 245:14] - node _T_640 = cat(_T_639, _T_638) @[el2_lib.scala 245:14] - node _T_641 = cat(_T_640, _T_637) @[el2_lib.scala 245:14] - node _T_642 = cat(_T_410[9], _T_410[8]) @[el2_lib.scala 245:14] - node _T_643 = cat(_T_410[11], _T_410[10]) @[el2_lib.scala 245:14] - node _T_644 = cat(_T_643, _T_642) @[el2_lib.scala 245:14] - node _T_645 = cat(_T_410[13], _T_410[12]) @[el2_lib.scala 245:14] - node _T_646 = cat(_T_410[15], _T_410[14]) @[el2_lib.scala 245:14] - node _T_647 = cat(_T_646, _T_645) @[el2_lib.scala 245:14] - node _T_648 = cat(_T_647, _T_644) @[el2_lib.scala 245:14] - node _T_649 = cat(_T_648, _T_641) @[el2_lib.scala 245:14] - node _T_650 = cat(_T_410[17], _T_410[16]) @[el2_lib.scala 245:14] - node _T_651 = cat(_T_410[19], _T_410[18]) @[el2_lib.scala 245:14] - node _T_652 = cat(_T_651, _T_650) @[el2_lib.scala 245:14] - node _T_653 = cat(_T_410[21], _T_410[20]) @[el2_lib.scala 245:14] - node _T_654 = cat(_T_410[23], _T_410[22]) @[el2_lib.scala 245:14] - node _T_655 = cat(_T_654, _T_653) @[el2_lib.scala 245:14] - node _T_656 = cat(_T_655, _T_652) @[el2_lib.scala 245:14] - node _T_657 = cat(_T_410[25], _T_410[24]) @[el2_lib.scala 245:14] - node _T_658 = cat(_T_410[27], _T_410[26]) @[el2_lib.scala 245:14] - node _T_659 = cat(_T_658, _T_657) @[el2_lib.scala 245:14] - node _T_660 = cat(_T_410[29], _T_410[28]) @[el2_lib.scala 245:14] - node _T_661 = cat(_T_410[31], _T_410[30]) @[el2_lib.scala 245:14] - node _T_662 = cat(_T_661, _T_660) @[el2_lib.scala 245:14] - node _T_663 = cat(_T_662, _T_659) @[el2_lib.scala 245:14] - node _T_664 = cat(_T_663, _T_656) @[el2_lib.scala 245:14] - node _T_665 = cat(_T_664, _T_649) @[el2_lib.scala 245:14] - node _T_666 = andr(_T_665) @[el2_lib.scala 245:25] + wire _T_410 : UInt<1>[32] @[lib.scala 100:24] + node _T_411 = andr(io.trigger_pkt_any[1].tdata2) @[lib.scala 101:45] + node _T_412 = not(_T_411) @[lib.scala 101:39] + node _T_413 = and(_T_409, _T_412) @[lib.scala 101:37] + node _T_414 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[lib.scala 102:48] + node _T_415 = bits(dec_i0_match_data[1], 0, 0) @[lib.scala 102:60] + node _T_416 = eq(_T_414, _T_415) @[lib.scala 102:52] + node _T_417 = or(_T_413, _T_416) @[lib.scala 102:41] + _T_410[0] <= _T_417 @[lib.scala 102:18] + node _T_418 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[lib.scala 104:28] + node _T_419 = andr(_T_418) @[lib.scala 104:36] + node _T_420 = and(_T_419, _T_413) @[lib.scala 104:41] + node _T_421 = bits(io.trigger_pkt_any[1].tdata2, 1, 1) @[lib.scala 104:74] + node _T_422 = bits(dec_i0_match_data[1], 1, 1) @[lib.scala 104:86] + node _T_423 = eq(_T_421, _T_422) @[lib.scala 104:78] + node _T_424 = mux(_T_420, UInt<1>("h01"), _T_423) @[lib.scala 104:23] + _T_410[1] <= _T_424 @[lib.scala 104:17] + node _T_425 = bits(io.trigger_pkt_any[1].tdata2, 1, 0) @[lib.scala 104:28] + node _T_426 = andr(_T_425) @[lib.scala 104:36] + node _T_427 = and(_T_426, _T_413) @[lib.scala 104:41] + node _T_428 = bits(io.trigger_pkt_any[1].tdata2, 2, 2) @[lib.scala 104:74] + node _T_429 = bits(dec_i0_match_data[1], 2, 2) @[lib.scala 104:86] + node _T_430 = eq(_T_428, _T_429) @[lib.scala 104:78] + node _T_431 = mux(_T_427, UInt<1>("h01"), _T_430) @[lib.scala 104:23] + _T_410[2] <= _T_431 @[lib.scala 104:17] + node _T_432 = bits(io.trigger_pkt_any[1].tdata2, 2, 0) @[lib.scala 104:28] + node _T_433 = andr(_T_432) @[lib.scala 104:36] + node _T_434 = and(_T_433, _T_413) @[lib.scala 104:41] + node _T_435 = bits(io.trigger_pkt_any[1].tdata2, 3, 3) @[lib.scala 104:74] + node _T_436 = bits(dec_i0_match_data[1], 3, 3) @[lib.scala 104:86] + node _T_437 = eq(_T_435, _T_436) @[lib.scala 104:78] + node _T_438 = mux(_T_434, UInt<1>("h01"), _T_437) @[lib.scala 104:23] + _T_410[3] <= _T_438 @[lib.scala 104:17] + node _T_439 = bits(io.trigger_pkt_any[1].tdata2, 3, 0) @[lib.scala 104:28] + node _T_440 = andr(_T_439) @[lib.scala 104:36] + node _T_441 = and(_T_440, _T_413) @[lib.scala 104:41] + node _T_442 = bits(io.trigger_pkt_any[1].tdata2, 4, 4) @[lib.scala 104:74] + node _T_443 = bits(dec_i0_match_data[1], 4, 4) @[lib.scala 104:86] + node _T_444 = eq(_T_442, _T_443) @[lib.scala 104:78] + node _T_445 = mux(_T_441, UInt<1>("h01"), _T_444) @[lib.scala 104:23] + _T_410[4] <= _T_445 @[lib.scala 104:17] + node _T_446 = bits(io.trigger_pkt_any[1].tdata2, 4, 0) @[lib.scala 104:28] + node _T_447 = andr(_T_446) @[lib.scala 104:36] + node _T_448 = and(_T_447, _T_413) @[lib.scala 104:41] + node _T_449 = bits(io.trigger_pkt_any[1].tdata2, 5, 5) @[lib.scala 104:74] + node _T_450 = bits(dec_i0_match_data[1], 5, 5) @[lib.scala 104:86] + node _T_451 = eq(_T_449, _T_450) @[lib.scala 104:78] + node _T_452 = mux(_T_448, UInt<1>("h01"), _T_451) @[lib.scala 104:23] + _T_410[5] <= _T_452 @[lib.scala 104:17] + node _T_453 = bits(io.trigger_pkt_any[1].tdata2, 5, 0) @[lib.scala 104:28] + node _T_454 = andr(_T_453) @[lib.scala 104:36] + node _T_455 = and(_T_454, _T_413) @[lib.scala 104:41] + node _T_456 = bits(io.trigger_pkt_any[1].tdata2, 6, 6) @[lib.scala 104:74] + node _T_457 = bits(dec_i0_match_data[1], 6, 6) @[lib.scala 104:86] + node _T_458 = eq(_T_456, _T_457) @[lib.scala 104:78] + node _T_459 = mux(_T_455, UInt<1>("h01"), _T_458) @[lib.scala 104:23] + _T_410[6] <= _T_459 @[lib.scala 104:17] + node _T_460 = bits(io.trigger_pkt_any[1].tdata2, 6, 0) @[lib.scala 104:28] + node _T_461 = andr(_T_460) @[lib.scala 104:36] + node _T_462 = and(_T_461, _T_413) @[lib.scala 104:41] + node _T_463 = bits(io.trigger_pkt_any[1].tdata2, 7, 7) @[lib.scala 104:74] + node _T_464 = bits(dec_i0_match_data[1], 7, 7) @[lib.scala 104:86] + node _T_465 = eq(_T_463, _T_464) @[lib.scala 104:78] + node _T_466 = mux(_T_462, UInt<1>("h01"), _T_465) @[lib.scala 104:23] + _T_410[7] <= _T_466 @[lib.scala 104:17] + node _T_467 = bits(io.trigger_pkt_any[1].tdata2, 7, 0) @[lib.scala 104:28] + node _T_468 = andr(_T_467) @[lib.scala 104:36] + node _T_469 = and(_T_468, _T_413) @[lib.scala 104:41] + node _T_470 = bits(io.trigger_pkt_any[1].tdata2, 8, 8) @[lib.scala 104:74] + node _T_471 = bits(dec_i0_match_data[1], 8, 8) @[lib.scala 104:86] + node _T_472 = eq(_T_470, _T_471) @[lib.scala 104:78] + node _T_473 = mux(_T_469, UInt<1>("h01"), _T_472) @[lib.scala 104:23] + _T_410[8] <= _T_473 @[lib.scala 104:17] + node _T_474 = bits(io.trigger_pkt_any[1].tdata2, 8, 0) @[lib.scala 104:28] + node _T_475 = andr(_T_474) @[lib.scala 104:36] + node _T_476 = and(_T_475, _T_413) @[lib.scala 104:41] + node _T_477 = bits(io.trigger_pkt_any[1].tdata2, 9, 9) @[lib.scala 104:74] + node _T_478 = bits(dec_i0_match_data[1], 9, 9) @[lib.scala 104:86] + node _T_479 = eq(_T_477, _T_478) @[lib.scala 104:78] + node _T_480 = mux(_T_476, UInt<1>("h01"), _T_479) @[lib.scala 104:23] + _T_410[9] <= _T_480 @[lib.scala 104:17] + node _T_481 = bits(io.trigger_pkt_any[1].tdata2, 9, 0) @[lib.scala 104:28] + node _T_482 = andr(_T_481) @[lib.scala 104:36] + node _T_483 = and(_T_482, _T_413) @[lib.scala 104:41] + node _T_484 = bits(io.trigger_pkt_any[1].tdata2, 10, 10) @[lib.scala 104:74] + node _T_485 = bits(dec_i0_match_data[1], 10, 10) @[lib.scala 104:86] + node _T_486 = eq(_T_484, _T_485) @[lib.scala 104:78] + node _T_487 = mux(_T_483, UInt<1>("h01"), _T_486) @[lib.scala 104:23] + _T_410[10] <= _T_487 @[lib.scala 104:17] + node _T_488 = bits(io.trigger_pkt_any[1].tdata2, 10, 0) @[lib.scala 104:28] + node _T_489 = andr(_T_488) @[lib.scala 104:36] + node _T_490 = and(_T_489, _T_413) @[lib.scala 104:41] + node _T_491 = bits(io.trigger_pkt_any[1].tdata2, 11, 11) @[lib.scala 104:74] + node _T_492 = bits(dec_i0_match_data[1], 11, 11) @[lib.scala 104:86] + node _T_493 = eq(_T_491, _T_492) @[lib.scala 104:78] + node _T_494 = mux(_T_490, UInt<1>("h01"), _T_493) @[lib.scala 104:23] + _T_410[11] <= _T_494 @[lib.scala 104:17] + node _T_495 = bits(io.trigger_pkt_any[1].tdata2, 11, 0) @[lib.scala 104:28] + node _T_496 = andr(_T_495) @[lib.scala 104:36] + node _T_497 = and(_T_496, _T_413) @[lib.scala 104:41] + node _T_498 = bits(io.trigger_pkt_any[1].tdata2, 12, 12) @[lib.scala 104:74] + node _T_499 = bits(dec_i0_match_data[1], 12, 12) @[lib.scala 104:86] + node _T_500 = eq(_T_498, _T_499) @[lib.scala 104:78] + node _T_501 = mux(_T_497, UInt<1>("h01"), _T_500) @[lib.scala 104:23] + _T_410[12] <= _T_501 @[lib.scala 104:17] + node _T_502 = bits(io.trigger_pkt_any[1].tdata2, 12, 0) @[lib.scala 104:28] + node _T_503 = andr(_T_502) @[lib.scala 104:36] + node _T_504 = and(_T_503, _T_413) @[lib.scala 104:41] + node _T_505 = bits(io.trigger_pkt_any[1].tdata2, 13, 13) @[lib.scala 104:74] + node _T_506 = bits(dec_i0_match_data[1], 13, 13) @[lib.scala 104:86] + node _T_507 = eq(_T_505, _T_506) @[lib.scala 104:78] + node _T_508 = mux(_T_504, UInt<1>("h01"), _T_507) @[lib.scala 104:23] + _T_410[13] <= _T_508 @[lib.scala 104:17] + node _T_509 = bits(io.trigger_pkt_any[1].tdata2, 13, 0) @[lib.scala 104:28] + node _T_510 = andr(_T_509) @[lib.scala 104:36] + node _T_511 = and(_T_510, _T_413) @[lib.scala 104:41] + node _T_512 = bits(io.trigger_pkt_any[1].tdata2, 14, 14) @[lib.scala 104:74] + node _T_513 = bits(dec_i0_match_data[1], 14, 14) @[lib.scala 104:86] + node _T_514 = eq(_T_512, _T_513) @[lib.scala 104:78] + node _T_515 = mux(_T_511, UInt<1>("h01"), _T_514) @[lib.scala 104:23] + _T_410[14] <= _T_515 @[lib.scala 104:17] + node _T_516 = bits(io.trigger_pkt_any[1].tdata2, 14, 0) @[lib.scala 104:28] + node _T_517 = andr(_T_516) @[lib.scala 104:36] + node _T_518 = and(_T_517, _T_413) @[lib.scala 104:41] + node _T_519 = bits(io.trigger_pkt_any[1].tdata2, 15, 15) @[lib.scala 104:74] + node _T_520 = bits(dec_i0_match_data[1], 15, 15) @[lib.scala 104:86] + node _T_521 = eq(_T_519, _T_520) @[lib.scala 104:78] + node _T_522 = mux(_T_518, UInt<1>("h01"), _T_521) @[lib.scala 104:23] + _T_410[15] <= _T_522 @[lib.scala 104:17] + node _T_523 = bits(io.trigger_pkt_any[1].tdata2, 15, 0) @[lib.scala 104:28] + node _T_524 = andr(_T_523) @[lib.scala 104:36] + node _T_525 = and(_T_524, _T_413) @[lib.scala 104:41] + node _T_526 = bits(io.trigger_pkt_any[1].tdata2, 16, 16) @[lib.scala 104:74] + node _T_527 = bits(dec_i0_match_data[1], 16, 16) @[lib.scala 104:86] + node _T_528 = eq(_T_526, _T_527) @[lib.scala 104:78] + node _T_529 = mux(_T_525, UInt<1>("h01"), _T_528) @[lib.scala 104:23] + _T_410[16] <= _T_529 @[lib.scala 104:17] + node _T_530 = bits(io.trigger_pkt_any[1].tdata2, 16, 0) @[lib.scala 104:28] + node _T_531 = andr(_T_530) @[lib.scala 104:36] + node _T_532 = and(_T_531, _T_413) @[lib.scala 104:41] + node _T_533 = bits(io.trigger_pkt_any[1].tdata2, 17, 17) @[lib.scala 104:74] + node _T_534 = bits(dec_i0_match_data[1], 17, 17) @[lib.scala 104:86] + node _T_535 = eq(_T_533, _T_534) @[lib.scala 104:78] + node _T_536 = mux(_T_532, UInt<1>("h01"), _T_535) @[lib.scala 104:23] + _T_410[17] <= _T_536 @[lib.scala 104:17] + node _T_537 = bits(io.trigger_pkt_any[1].tdata2, 17, 0) @[lib.scala 104:28] + node _T_538 = andr(_T_537) @[lib.scala 104:36] + node _T_539 = and(_T_538, _T_413) @[lib.scala 104:41] + node _T_540 = bits(io.trigger_pkt_any[1].tdata2, 18, 18) @[lib.scala 104:74] + node _T_541 = bits(dec_i0_match_data[1], 18, 18) @[lib.scala 104:86] + node _T_542 = eq(_T_540, _T_541) @[lib.scala 104:78] + node _T_543 = mux(_T_539, UInt<1>("h01"), _T_542) @[lib.scala 104:23] + _T_410[18] <= _T_543 @[lib.scala 104:17] + node _T_544 = bits(io.trigger_pkt_any[1].tdata2, 18, 0) @[lib.scala 104:28] + node _T_545 = andr(_T_544) @[lib.scala 104:36] + node _T_546 = and(_T_545, _T_413) @[lib.scala 104:41] + node _T_547 = bits(io.trigger_pkt_any[1].tdata2, 19, 19) @[lib.scala 104:74] + node _T_548 = bits(dec_i0_match_data[1], 19, 19) @[lib.scala 104:86] + node _T_549 = eq(_T_547, _T_548) @[lib.scala 104:78] + node _T_550 = mux(_T_546, UInt<1>("h01"), _T_549) @[lib.scala 104:23] + _T_410[19] <= _T_550 @[lib.scala 104:17] + node _T_551 = bits(io.trigger_pkt_any[1].tdata2, 19, 0) @[lib.scala 104:28] + node _T_552 = andr(_T_551) @[lib.scala 104:36] + node _T_553 = and(_T_552, _T_413) @[lib.scala 104:41] + node _T_554 = bits(io.trigger_pkt_any[1].tdata2, 20, 20) @[lib.scala 104:74] + node _T_555 = bits(dec_i0_match_data[1], 20, 20) @[lib.scala 104:86] + node _T_556 = eq(_T_554, _T_555) @[lib.scala 104:78] + node _T_557 = mux(_T_553, UInt<1>("h01"), _T_556) @[lib.scala 104:23] + _T_410[20] <= _T_557 @[lib.scala 104:17] + node _T_558 = bits(io.trigger_pkt_any[1].tdata2, 20, 0) @[lib.scala 104:28] + node _T_559 = andr(_T_558) @[lib.scala 104:36] + node _T_560 = and(_T_559, _T_413) @[lib.scala 104:41] + node _T_561 = bits(io.trigger_pkt_any[1].tdata2, 21, 21) @[lib.scala 104:74] + node _T_562 = bits(dec_i0_match_data[1], 21, 21) @[lib.scala 104:86] + node _T_563 = eq(_T_561, _T_562) @[lib.scala 104:78] + node _T_564 = mux(_T_560, UInt<1>("h01"), _T_563) @[lib.scala 104:23] + _T_410[21] <= _T_564 @[lib.scala 104:17] + node _T_565 = bits(io.trigger_pkt_any[1].tdata2, 21, 0) @[lib.scala 104:28] + node _T_566 = andr(_T_565) @[lib.scala 104:36] + node _T_567 = and(_T_566, _T_413) @[lib.scala 104:41] + node _T_568 = bits(io.trigger_pkt_any[1].tdata2, 22, 22) @[lib.scala 104:74] + node _T_569 = bits(dec_i0_match_data[1], 22, 22) @[lib.scala 104:86] + node _T_570 = eq(_T_568, _T_569) @[lib.scala 104:78] + node _T_571 = mux(_T_567, UInt<1>("h01"), _T_570) @[lib.scala 104:23] + _T_410[22] <= _T_571 @[lib.scala 104:17] + node _T_572 = bits(io.trigger_pkt_any[1].tdata2, 22, 0) @[lib.scala 104:28] + node _T_573 = andr(_T_572) @[lib.scala 104:36] + node _T_574 = and(_T_573, _T_413) @[lib.scala 104:41] + node _T_575 = bits(io.trigger_pkt_any[1].tdata2, 23, 23) @[lib.scala 104:74] + node _T_576 = bits(dec_i0_match_data[1], 23, 23) @[lib.scala 104:86] + node _T_577 = eq(_T_575, _T_576) @[lib.scala 104:78] + node _T_578 = mux(_T_574, UInt<1>("h01"), _T_577) @[lib.scala 104:23] + _T_410[23] <= _T_578 @[lib.scala 104:17] + node _T_579 = bits(io.trigger_pkt_any[1].tdata2, 23, 0) @[lib.scala 104:28] + node _T_580 = andr(_T_579) @[lib.scala 104:36] + node _T_581 = and(_T_580, _T_413) @[lib.scala 104:41] + node _T_582 = bits(io.trigger_pkt_any[1].tdata2, 24, 24) @[lib.scala 104:74] + node _T_583 = bits(dec_i0_match_data[1], 24, 24) @[lib.scala 104:86] + node _T_584 = eq(_T_582, _T_583) @[lib.scala 104:78] + node _T_585 = mux(_T_581, UInt<1>("h01"), _T_584) @[lib.scala 104:23] + _T_410[24] <= _T_585 @[lib.scala 104:17] + node _T_586 = bits(io.trigger_pkt_any[1].tdata2, 24, 0) @[lib.scala 104:28] + node _T_587 = andr(_T_586) @[lib.scala 104:36] + node _T_588 = and(_T_587, _T_413) @[lib.scala 104:41] + node _T_589 = bits(io.trigger_pkt_any[1].tdata2, 25, 25) @[lib.scala 104:74] + node _T_590 = bits(dec_i0_match_data[1], 25, 25) @[lib.scala 104:86] + node _T_591 = eq(_T_589, _T_590) @[lib.scala 104:78] + node _T_592 = mux(_T_588, UInt<1>("h01"), _T_591) @[lib.scala 104:23] + _T_410[25] <= _T_592 @[lib.scala 104:17] + node _T_593 = bits(io.trigger_pkt_any[1].tdata2, 25, 0) @[lib.scala 104:28] + node _T_594 = andr(_T_593) @[lib.scala 104:36] + node _T_595 = and(_T_594, _T_413) @[lib.scala 104:41] + node _T_596 = bits(io.trigger_pkt_any[1].tdata2, 26, 26) @[lib.scala 104:74] + node _T_597 = bits(dec_i0_match_data[1], 26, 26) @[lib.scala 104:86] + node _T_598 = eq(_T_596, _T_597) @[lib.scala 104:78] + node _T_599 = mux(_T_595, UInt<1>("h01"), _T_598) @[lib.scala 104:23] + _T_410[26] <= _T_599 @[lib.scala 104:17] + node _T_600 = bits(io.trigger_pkt_any[1].tdata2, 26, 0) @[lib.scala 104:28] + node _T_601 = andr(_T_600) @[lib.scala 104:36] + node _T_602 = and(_T_601, _T_413) @[lib.scala 104:41] + node _T_603 = bits(io.trigger_pkt_any[1].tdata2, 27, 27) @[lib.scala 104:74] + node _T_604 = bits(dec_i0_match_data[1], 27, 27) @[lib.scala 104:86] + node _T_605 = eq(_T_603, _T_604) @[lib.scala 104:78] + node _T_606 = mux(_T_602, UInt<1>("h01"), _T_605) @[lib.scala 104:23] + _T_410[27] <= _T_606 @[lib.scala 104:17] + node _T_607 = bits(io.trigger_pkt_any[1].tdata2, 27, 0) @[lib.scala 104:28] + node _T_608 = andr(_T_607) @[lib.scala 104:36] + node _T_609 = and(_T_608, _T_413) @[lib.scala 104:41] + node _T_610 = bits(io.trigger_pkt_any[1].tdata2, 28, 28) @[lib.scala 104:74] + node _T_611 = bits(dec_i0_match_data[1], 28, 28) @[lib.scala 104:86] + node _T_612 = eq(_T_610, _T_611) @[lib.scala 104:78] + node _T_613 = mux(_T_609, UInt<1>("h01"), _T_612) @[lib.scala 104:23] + _T_410[28] <= _T_613 @[lib.scala 104:17] + node _T_614 = bits(io.trigger_pkt_any[1].tdata2, 28, 0) @[lib.scala 104:28] + node _T_615 = andr(_T_614) @[lib.scala 104:36] + node _T_616 = and(_T_615, _T_413) @[lib.scala 104:41] + node _T_617 = bits(io.trigger_pkt_any[1].tdata2, 29, 29) @[lib.scala 104:74] + node _T_618 = bits(dec_i0_match_data[1], 29, 29) @[lib.scala 104:86] + node _T_619 = eq(_T_617, _T_618) @[lib.scala 104:78] + node _T_620 = mux(_T_616, UInt<1>("h01"), _T_619) @[lib.scala 104:23] + _T_410[29] <= _T_620 @[lib.scala 104:17] + node _T_621 = bits(io.trigger_pkt_any[1].tdata2, 29, 0) @[lib.scala 104:28] + node _T_622 = andr(_T_621) @[lib.scala 104:36] + node _T_623 = and(_T_622, _T_413) @[lib.scala 104:41] + node _T_624 = bits(io.trigger_pkt_any[1].tdata2, 30, 30) @[lib.scala 104:74] + node _T_625 = bits(dec_i0_match_data[1], 30, 30) @[lib.scala 104:86] + node _T_626 = eq(_T_624, _T_625) @[lib.scala 104:78] + node _T_627 = mux(_T_623, UInt<1>("h01"), _T_626) @[lib.scala 104:23] + _T_410[30] <= _T_627 @[lib.scala 104:17] + node _T_628 = bits(io.trigger_pkt_any[1].tdata2, 30, 0) @[lib.scala 104:28] + node _T_629 = andr(_T_628) @[lib.scala 104:36] + node _T_630 = and(_T_629, _T_413) @[lib.scala 104:41] + node _T_631 = bits(io.trigger_pkt_any[1].tdata2, 31, 31) @[lib.scala 104:74] + node _T_632 = bits(dec_i0_match_data[1], 31, 31) @[lib.scala 104:86] + node _T_633 = eq(_T_631, _T_632) @[lib.scala 104:78] + node _T_634 = mux(_T_630, UInt<1>("h01"), _T_633) @[lib.scala 104:23] + _T_410[31] <= _T_634 @[lib.scala 104:17] + node _T_635 = cat(_T_410[1], _T_410[0]) @[lib.scala 105:14] + node _T_636 = cat(_T_410[3], _T_410[2]) @[lib.scala 105:14] + node _T_637 = cat(_T_636, _T_635) @[lib.scala 105:14] + node _T_638 = cat(_T_410[5], _T_410[4]) @[lib.scala 105:14] + node _T_639 = cat(_T_410[7], _T_410[6]) @[lib.scala 105:14] + node _T_640 = cat(_T_639, _T_638) @[lib.scala 105:14] + node _T_641 = cat(_T_640, _T_637) @[lib.scala 105:14] + node _T_642 = cat(_T_410[9], _T_410[8]) @[lib.scala 105:14] + node _T_643 = cat(_T_410[11], _T_410[10]) @[lib.scala 105:14] + node _T_644 = cat(_T_643, _T_642) @[lib.scala 105:14] + node _T_645 = cat(_T_410[13], _T_410[12]) @[lib.scala 105:14] + node _T_646 = cat(_T_410[15], _T_410[14]) @[lib.scala 105:14] + node _T_647 = cat(_T_646, _T_645) @[lib.scala 105:14] + node _T_648 = cat(_T_647, _T_644) @[lib.scala 105:14] + node _T_649 = cat(_T_648, _T_641) @[lib.scala 105:14] + node _T_650 = cat(_T_410[17], _T_410[16]) @[lib.scala 105:14] + node _T_651 = cat(_T_410[19], _T_410[18]) @[lib.scala 105:14] + node _T_652 = cat(_T_651, _T_650) @[lib.scala 105:14] + node _T_653 = cat(_T_410[21], _T_410[20]) @[lib.scala 105:14] + node _T_654 = cat(_T_410[23], _T_410[22]) @[lib.scala 105:14] + node _T_655 = cat(_T_654, _T_653) @[lib.scala 105:14] + node _T_656 = cat(_T_655, _T_652) @[lib.scala 105:14] + node _T_657 = cat(_T_410[25], _T_410[24]) @[lib.scala 105:14] + node _T_658 = cat(_T_410[27], _T_410[26]) @[lib.scala 105:14] + node _T_659 = cat(_T_658, _T_657) @[lib.scala 105:14] + node _T_660 = cat(_T_410[29], _T_410[28]) @[lib.scala 105:14] + node _T_661 = cat(_T_410[31], _T_410[30]) @[lib.scala 105:14] + node _T_662 = cat(_T_661, _T_660) @[lib.scala 105:14] + node _T_663 = cat(_T_662, _T_659) @[lib.scala 105:14] + node _T_664 = cat(_T_663, _T_656) @[lib.scala 105:14] + node _T_665 = cat(_T_664, _T_649) @[lib.scala 105:14] + node _T_666 = andr(_T_665) @[lib.scala 105:25] node _T_667 = and(_T_408, _T_666) @[dec_trigger.scala 15:109] node _T_668 = and(io.trigger_pkt_any[2].execute, io.trigger_pkt_any[2].m) @[dec_trigger.scala 15:83] node _T_669 = bits(io.trigger_pkt_any[2].match_pkt, 0, 0) @[dec_trigger.scala 15:216] - wire _T_670 : UInt<1>[32] @[el2_lib.scala 240:24] - node _T_671 = andr(io.trigger_pkt_any[2].tdata2) @[el2_lib.scala 241:45] - node _T_672 = not(_T_671) @[el2_lib.scala 241:39] - node _T_673 = and(_T_669, _T_672) @[el2_lib.scala 241:37] - node _T_674 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[el2_lib.scala 242:48] - node _T_675 = bits(dec_i0_match_data[2], 0, 0) @[el2_lib.scala 242:60] - node _T_676 = eq(_T_674, _T_675) @[el2_lib.scala 242:52] - node _T_677 = or(_T_673, _T_676) @[el2_lib.scala 242:41] - _T_670[0] <= _T_677 @[el2_lib.scala 242:18] - node _T_678 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[el2_lib.scala 244:28] - node _T_679 = andr(_T_678) @[el2_lib.scala 244:36] - node _T_680 = and(_T_679, _T_673) @[el2_lib.scala 244:41] - node _T_681 = bits(io.trigger_pkt_any[2].tdata2, 1, 1) @[el2_lib.scala 244:74] - node _T_682 = bits(dec_i0_match_data[2], 1, 1) @[el2_lib.scala 244:86] - node _T_683 = eq(_T_681, _T_682) @[el2_lib.scala 244:78] - node _T_684 = mux(_T_680, UInt<1>("h01"), _T_683) @[el2_lib.scala 244:23] - _T_670[1] <= _T_684 @[el2_lib.scala 244:17] - node _T_685 = bits(io.trigger_pkt_any[2].tdata2, 1, 0) @[el2_lib.scala 244:28] - node _T_686 = andr(_T_685) @[el2_lib.scala 244:36] - node _T_687 = and(_T_686, _T_673) @[el2_lib.scala 244:41] - node _T_688 = bits(io.trigger_pkt_any[2].tdata2, 2, 2) @[el2_lib.scala 244:74] - node _T_689 = bits(dec_i0_match_data[2], 2, 2) @[el2_lib.scala 244:86] - node _T_690 = eq(_T_688, _T_689) @[el2_lib.scala 244:78] - node _T_691 = mux(_T_687, UInt<1>("h01"), _T_690) @[el2_lib.scala 244:23] - _T_670[2] <= _T_691 @[el2_lib.scala 244:17] - node _T_692 = bits(io.trigger_pkt_any[2].tdata2, 2, 0) @[el2_lib.scala 244:28] - node _T_693 = andr(_T_692) @[el2_lib.scala 244:36] - node _T_694 = and(_T_693, _T_673) @[el2_lib.scala 244:41] - node _T_695 = bits(io.trigger_pkt_any[2].tdata2, 3, 3) @[el2_lib.scala 244:74] - node _T_696 = bits(dec_i0_match_data[2], 3, 3) @[el2_lib.scala 244:86] - node _T_697 = eq(_T_695, _T_696) @[el2_lib.scala 244:78] - node _T_698 = mux(_T_694, UInt<1>("h01"), _T_697) @[el2_lib.scala 244:23] - _T_670[3] <= _T_698 @[el2_lib.scala 244:17] - node _T_699 = bits(io.trigger_pkt_any[2].tdata2, 3, 0) @[el2_lib.scala 244:28] - node _T_700 = andr(_T_699) @[el2_lib.scala 244:36] - node _T_701 = and(_T_700, _T_673) @[el2_lib.scala 244:41] - node _T_702 = bits(io.trigger_pkt_any[2].tdata2, 4, 4) @[el2_lib.scala 244:74] - node _T_703 = bits(dec_i0_match_data[2], 4, 4) @[el2_lib.scala 244:86] - node _T_704 = eq(_T_702, _T_703) @[el2_lib.scala 244:78] - node _T_705 = mux(_T_701, UInt<1>("h01"), _T_704) @[el2_lib.scala 244:23] - _T_670[4] <= _T_705 @[el2_lib.scala 244:17] - node _T_706 = bits(io.trigger_pkt_any[2].tdata2, 4, 0) @[el2_lib.scala 244:28] - node _T_707 = andr(_T_706) @[el2_lib.scala 244:36] - node _T_708 = and(_T_707, _T_673) @[el2_lib.scala 244:41] - node _T_709 = bits(io.trigger_pkt_any[2].tdata2, 5, 5) @[el2_lib.scala 244:74] - node _T_710 = bits(dec_i0_match_data[2], 5, 5) @[el2_lib.scala 244:86] - node _T_711 = eq(_T_709, _T_710) @[el2_lib.scala 244:78] - node _T_712 = mux(_T_708, UInt<1>("h01"), _T_711) @[el2_lib.scala 244:23] - _T_670[5] <= _T_712 @[el2_lib.scala 244:17] - node _T_713 = bits(io.trigger_pkt_any[2].tdata2, 5, 0) @[el2_lib.scala 244:28] - node _T_714 = andr(_T_713) @[el2_lib.scala 244:36] - node _T_715 = and(_T_714, _T_673) @[el2_lib.scala 244:41] - node _T_716 = bits(io.trigger_pkt_any[2].tdata2, 6, 6) @[el2_lib.scala 244:74] - node _T_717 = bits(dec_i0_match_data[2], 6, 6) @[el2_lib.scala 244:86] - node _T_718 = eq(_T_716, _T_717) @[el2_lib.scala 244:78] - node _T_719 = mux(_T_715, UInt<1>("h01"), _T_718) @[el2_lib.scala 244:23] - _T_670[6] <= _T_719 @[el2_lib.scala 244:17] - node _T_720 = bits(io.trigger_pkt_any[2].tdata2, 6, 0) @[el2_lib.scala 244:28] - node _T_721 = andr(_T_720) @[el2_lib.scala 244:36] - node _T_722 = and(_T_721, _T_673) @[el2_lib.scala 244:41] - node _T_723 = bits(io.trigger_pkt_any[2].tdata2, 7, 7) @[el2_lib.scala 244:74] - node _T_724 = bits(dec_i0_match_data[2], 7, 7) @[el2_lib.scala 244:86] - node _T_725 = eq(_T_723, _T_724) @[el2_lib.scala 244:78] - node _T_726 = mux(_T_722, UInt<1>("h01"), _T_725) @[el2_lib.scala 244:23] - _T_670[7] <= _T_726 @[el2_lib.scala 244:17] - node _T_727 = bits(io.trigger_pkt_any[2].tdata2, 7, 0) @[el2_lib.scala 244:28] - node _T_728 = andr(_T_727) @[el2_lib.scala 244:36] - node _T_729 = and(_T_728, _T_673) @[el2_lib.scala 244:41] - node _T_730 = bits(io.trigger_pkt_any[2].tdata2, 8, 8) @[el2_lib.scala 244:74] - node _T_731 = bits(dec_i0_match_data[2], 8, 8) @[el2_lib.scala 244:86] - node _T_732 = eq(_T_730, _T_731) @[el2_lib.scala 244:78] - node _T_733 = mux(_T_729, UInt<1>("h01"), _T_732) @[el2_lib.scala 244:23] - _T_670[8] <= _T_733 @[el2_lib.scala 244:17] - node _T_734 = bits(io.trigger_pkt_any[2].tdata2, 8, 0) @[el2_lib.scala 244:28] - node _T_735 = andr(_T_734) @[el2_lib.scala 244:36] - node _T_736 = and(_T_735, _T_673) @[el2_lib.scala 244:41] - node _T_737 = bits(io.trigger_pkt_any[2].tdata2, 9, 9) @[el2_lib.scala 244:74] - node _T_738 = bits(dec_i0_match_data[2], 9, 9) @[el2_lib.scala 244:86] - node _T_739 = eq(_T_737, _T_738) @[el2_lib.scala 244:78] - node _T_740 = mux(_T_736, UInt<1>("h01"), _T_739) @[el2_lib.scala 244:23] - _T_670[9] <= _T_740 @[el2_lib.scala 244:17] - node _T_741 = bits(io.trigger_pkt_any[2].tdata2, 9, 0) @[el2_lib.scala 244:28] - node _T_742 = andr(_T_741) @[el2_lib.scala 244:36] - node _T_743 = and(_T_742, _T_673) @[el2_lib.scala 244:41] - node _T_744 = bits(io.trigger_pkt_any[2].tdata2, 10, 10) @[el2_lib.scala 244:74] - node _T_745 = bits(dec_i0_match_data[2], 10, 10) @[el2_lib.scala 244:86] - node _T_746 = eq(_T_744, _T_745) @[el2_lib.scala 244:78] - node _T_747 = mux(_T_743, UInt<1>("h01"), _T_746) @[el2_lib.scala 244:23] - _T_670[10] <= _T_747 @[el2_lib.scala 244:17] - node _T_748 = bits(io.trigger_pkt_any[2].tdata2, 10, 0) @[el2_lib.scala 244:28] - node _T_749 = andr(_T_748) @[el2_lib.scala 244:36] - node _T_750 = and(_T_749, _T_673) @[el2_lib.scala 244:41] - node _T_751 = bits(io.trigger_pkt_any[2].tdata2, 11, 11) @[el2_lib.scala 244:74] - node _T_752 = bits(dec_i0_match_data[2], 11, 11) @[el2_lib.scala 244:86] - node _T_753 = eq(_T_751, _T_752) @[el2_lib.scala 244:78] - node _T_754 = mux(_T_750, UInt<1>("h01"), _T_753) @[el2_lib.scala 244:23] - _T_670[11] <= _T_754 @[el2_lib.scala 244:17] - node _T_755 = bits(io.trigger_pkt_any[2].tdata2, 11, 0) @[el2_lib.scala 244:28] - node _T_756 = andr(_T_755) @[el2_lib.scala 244:36] - node _T_757 = and(_T_756, _T_673) @[el2_lib.scala 244:41] - node _T_758 = bits(io.trigger_pkt_any[2].tdata2, 12, 12) @[el2_lib.scala 244:74] - node _T_759 = bits(dec_i0_match_data[2], 12, 12) @[el2_lib.scala 244:86] - node _T_760 = eq(_T_758, _T_759) @[el2_lib.scala 244:78] - node _T_761 = mux(_T_757, UInt<1>("h01"), _T_760) @[el2_lib.scala 244:23] - _T_670[12] <= _T_761 @[el2_lib.scala 244:17] - node _T_762 = bits(io.trigger_pkt_any[2].tdata2, 12, 0) @[el2_lib.scala 244:28] - node _T_763 = andr(_T_762) @[el2_lib.scala 244:36] - node _T_764 = and(_T_763, _T_673) @[el2_lib.scala 244:41] - node _T_765 = bits(io.trigger_pkt_any[2].tdata2, 13, 13) @[el2_lib.scala 244:74] - node _T_766 = bits(dec_i0_match_data[2], 13, 13) @[el2_lib.scala 244:86] - node _T_767 = eq(_T_765, _T_766) @[el2_lib.scala 244:78] - node _T_768 = mux(_T_764, UInt<1>("h01"), _T_767) @[el2_lib.scala 244:23] - _T_670[13] <= _T_768 @[el2_lib.scala 244:17] - node _T_769 = bits(io.trigger_pkt_any[2].tdata2, 13, 0) @[el2_lib.scala 244:28] - node _T_770 = andr(_T_769) @[el2_lib.scala 244:36] - node _T_771 = and(_T_770, _T_673) @[el2_lib.scala 244:41] - node _T_772 = bits(io.trigger_pkt_any[2].tdata2, 14, 14) @[el2_lib.scala 244:74] - node _T_773 = bits(dec_i0_match_data[2], 14, 14) @[el2_lib.scala 244:86] - node _T_774 = eq(_T_772, _T_773) @[el2_lib.scala 244:78] - node _T_775 = mux(_T_771, UInt<1>("h01"), _T_774) @[el2_lib.scala 244:23] - _T_670[14] <= _T_775 @[el2_lib.scala 244:17] - node _T_776 = bits(io.trigger_pkt_any[2].tdata2, 14, 0) @[el2_lib.scala 244:28] - node _T_777 = andr(_T_776) @[el2_lib.scala 244:36] - node _T_778 = and(_T_777, _T_673) @[el2_lib.scala 244:41] - node _T_779 = bits(io.trigger_pkt_any[2].tdata2, 15, 15) @[el2_lib.scala 244:74] - node _T_780 = bits(dec_i0_match_data[2], 15, 15) @[el2_lib.scala 244:86] - node _T_781 = eq(_T_779, _T_780) @[el2_lib.scala 244:78] - node _T_782 = mux(_T_778, UInt<1>("h01"), _T_781) @[el2_lib.scala 244:23] - _T_670[15] <= _T_782 @[el2_lib.scala 244:17] - node _T_783 = bits(io.trigger_pkt_any[2].tdata2, 15, 0) @[el2_lib.scala 244:28] - node _T_784 = andr(_T_783) @[el2_lib.scala 244:36] - node _T_785 = and(_T_784, _T_673) @[el2_lib.scala 244:41] - node _T_786 = bits(io.trigger_pkt_any[2].tdata2, 16, 16) @[el2_lib.scala 244:74] - node _T_787 = bits(dec_i0_match_data[2], 16, 16) @[el2_lib.scala 244:86] - node _T_788 = eq(_T_786, _T_787) @[el2_lib.scala 244:78] - node _T_789 = mux(_T_785, UInt<1>("h01"), _T_788) @[el2_lib.scala 244:23] - _T_670[16] <= _T_789 @[el2_lib.scala 244:17] - node _T_790 = bits(io.trigger_pkt_any[2].tdata2, 16, 0) @[el2_lib.scala 244:28] - node _T_791 = andr(_T_790) @[el2_lib.scala 244:36] - node _T_792 = and(_T_791, _T_673) @[el2_lib.scala 244:41] - node _T_793 = bits(io.trigger_pkt_any[2].tdata2, 17, 17) @[el2_lib.scala 244:74] - node _T_794 = bits(dec_i0_match_data[2], 17, 17) @[el2_lib.scala 244:86] - node _T_795 = eq(_T_793, _T_794) @[el2_lib.scala 244:78] - node _T_796 = mux(_T_792, UInt<1>("h01"), _T_795) @[el2_lib.scala 244:23] - _T_670[17] <= _T_796 @[el2_lib.scala 244:17] - node _T_797 = bits(io.trigger_pkt_any[2].tdata2, 17, 0) @[el2_lib.scala 244:28] - node _T_798 = andr(_T_797) @[el2_lib.scala 244:36] - node _T_799 = and(_T_798, _T_673) @[el2_lib.scala 244:41] - node _T_800 = bits(io.trigger_pkt_any[2].tdata2, 18, 18) @[el2_lib.scala 244:74] - node _T_801 = bits(dec_i0_match_data[2], 18, 18) @[el2_lib.scala 244:86] - node _T_802 = eq(_T_800, _T_801) @[el2_lib.scala 244:78] - node _T_803 = mux(_T_799, UInt<1>("h01"), _T_802) @[el2_lib.scala 244:23] - _T_670[18] <= _T_803 @[el2_lib.scala 244:17] - node _T_804 = bits(io.trigger_pkt_any[2].tdata2, 18, 0) @[el2_lib.scala 244:28] - node _T_805 = andr(_T_804) @[el2_lib.scala 244:36] - node _T_806 = and(_T_805, _T_673) @[el2_lib.scala 244:41] - node _T_807 = bits(io.trigger_pkt_any[2].tdata2, 19, 19) @[el2_lib.scala 244:74] - node _T_808 = bits(dec_i0_match_data[2], 19, 19) @[el2_lib.scala 244:86] - node _T_809 = eq(_T_807, _T_808) @[el2_lib.scala 244:78] - node _T_810 = mux(_T_806, UInt<1>("h01"), _T_809) @[el2_lib.scala 244:23] - _T_670[19] <= _T_810 @[el2_lib.scala 244:17] - node _T_811 = bits(io.trigger_pkt_any[2].tdata2, 19, 0) @[el2_lib.scala 244:28] - node _T_812 = andr(_T_811) @[el2_lib.scala 244:36] - node _T_813 = and(_T_812, _T_673) @[el2_lib.scala 244:41] - node _T_814 = bits(io.trigger_pkt_any[2].tdata2, 20, 20) @[el2_lib.scala 244:74] - node _T_815 = bits(dec_i0_match_data[2], 20, 20) @[el2_lib.scala 244:86] - node _T_816 = eq(_T_814, _T_815) @[el2_lib.scala 244:78] - node _T_817 = mux(_T_813, UInt<1>("h01"), _T_816) @[el2_lib.scala 244:23] - _T_670[20] <= _T_817 @[el2_lib.scala 244:17] - node _T_818 = bits(io.trigger_pkt_any[2].tdata2, 20, 0) @[el2_lib.scala 244:28] - node _T_819 = andr(_T_818) @[el2_lib.scala 244:36] - node _T_820 = and(_T_819, _T_673) @[el2_lib.scala 244:41] - node _T_821 = bits(io.trigger_pkt_any[2].tdata2, 21, 21) @[el2_lib.scala 244:74] - node _T_822 = bits(dec_i0_match_data[2], 21, 21) @[el2_lib.scala 244:86] - node _T_823 = eq(_T_821, _T_822) @[el2_lib.scala 244:78] - node _T_824 = mux(_T_820, UInt<1>("h01"), _T_823) @[el2_lib.scala 244:23] - _T_670[21] <= _T_824 @[el2_lib.scala 244:17] - node _T_825 = bits(io.trigger_pkt_any[2].tdata2, 21, 0) @[el2_lib.scala 244:28] - node _T_826 = andr(_T_825) @[el2_lib.scala 244:36] - node _T_827 = and(_T_826, _T_673) @[el2_lib.scala 244:41] - node _T_828 = bits(io.trigger_pkt_any[2].tdata2, 22, 22) @[el2_lib.scala 244:74] - node _T_829 = bits(dec_i0_match_data[2], 22, 22) @[el2_lib.scala 244:86] - node _T_830 = eq(_T_828, _T_829) @[el2_lib.scala 244:78] - node _T_831 = mux(_T_827, UInt<1>("h01"), _T_830) @[el2_lib.scala 244:23] - _T_670[22] <= _T_831 @[el2_lib.scala 244:17] - node _T_832 = bits(io.trigger_pkt_any[2].tdata2, 22, 0) @[el2_lib.scala 244:28] - node _T_833 = andr(_T_832) @[el2_lib.scala 244:36] - node _T_834 = and(_T_833, _T_673) @[el2_lib.scala 244:41] - node _T_835 = bits(io.trigger_pkt_any[2].tdata2, 23, 23) @[el2_lib.scala 244:74] - node _T_836 = bits(dec_i0_match_data[2], 23, 23) @[el2_lib.scala 244:86] - node _T_837 = eq(_T_835, _T_836) @[el2_lib.scala 244:78] - node _T_838 = mux(_T_834, UInt<1>("h01"), _T_837) @[el2_lib.scala 244:23] - _T_670[23] <= _T_838 @[el2_lib.scala 244:17] - node _T_839 = bits(io.trigger_pkt_any[2].tdata2, 23, 0) @[el2_lib.scala 244:28] - node _T_840 = andr(_T_839) @[el2_lib.scala 244:36] - node _T_841 = and(_T_840, _T_673) @[el2_lib.scala 244:41] - node _T_842 = bits(io.trigger_pkt_any[2].tdata2, 24, 24) @[el2_lib.scala 244:74] - node _T_843 = bits(dec_i0_match_data[2], 24, 24) @[el2_lib.scala 244:86] - node _T_844 = eq(_T_842, _T_843) @[el2_lib.scala 244:78] - node _T_845 = mux(_T_841, UInt<1>("h01"), _T_844) @[el2_lib.scala 244:23] - _T_670[24] <= _T_845 @[el2_lib.scala 244:17] - node _T_846 = bits(io.trigger_pkt_any[2].tdata2, 24, 0) @[el2_lib.scala 244:28] - node _T_847 = andr(_T_846) @[el2_lib.scala 244:36] - node _T_848 = and(_T_847, _T_673) @[el2_lib.scala 244:41] - node _T_849 = bits(io.trigger_pkt_any[2].tdata2, 25, 25) @[el2_lib.scala 244:74] - node _T_850 = bits(dec_i0_match_data[2], 25, 25) @[el2_lib.scala 244:86] - node _T_851 = eq(_T_849, _T_850) @[el2_lib.scala 244:78] - node _T_852 = mux(_T_848, UInt<1>("h01"), _T_851) @[el2_lib.scala 244:23] - _T_670[25] <= _T_852 @[el2_lib.scala 244:17] - node _T_853 = bits(io.trigger_pkt_any[2].tdata2, 25, 0) @[el2_lib.scala 244:28] - node _T_854 = andr(_T_853) @[el2_lib.scala 244:36] - node _T_855 = and(_T_854, _T_673) @[el2_lib.scala 244:41] - node _T_856 = bits(io.trigger_pkt_any[2].tdata2, 26, 26) @[el2_lib.scala 244:74] - node _T_857 = bits(dec_i0_match_data[2], 26, 26) @[el2_lib.scala 244:86] - node _T_858 = eq(_T_856, _T_857) @[el2_lib.scala 244:78] - node _T_859 = mux(_T_855, UInt<1>("h01"), _T_858) @[el2_lib.scala 244:23] - _T_670[26] <= _T_859 @[el2_lib.scala 244:17] - node _T_860 = bits(io.trigger_pkt_any[2].tdata2, 26, 0) @[el2_lib.scala 244:28] - node _T_861 = andr(_T_860) @[el2_lib.scala 244:36] - node _T_862 = and(_T_861, _T_673) @[el2_lib.scala 244:41] - node _T_863 = bits(io.trigger_pkt_any[2].tdata2, 27, 27) @[el2_lib.scala 244:74] - node _T_864 = bits(dec_i0_match_data[2], 27, 27) @[el2_lib.scala 244:86] - node _T_865 = eq(_T_863, _T_864) @[el2_lib.scala 244:78] - node _T_866 = mux(_T_862, UInt<1>("h01"), _T_865) @[el2_lib.scala 244:23] - _T_670[27] <= _T_866 @[el2_lib.scala 244:17] - node _T_867 = bits(io.trigger_pkt_any[2].tdata2, 27, 0) @[el2_lib.scala 244:28] - node _T_868 = andr(_T_867) @[el2_lib.scala 244:36] - node _T_869 = and(_T_868, _T_673) @[el2_lib.scala 244:41] - node _T_870 = bits(io.trigger_pkt_any[2].tdata2, 28, 28) @[el2_lib.scala 244:74] - node _T_871 = bits(dec_i0_match_data[2], 28, 28) @[el2_lib.scala 244:86] - node _T_872 = eq(_T_870, _T_871) @[el2_lib.scala 244:78] - node _T_873 = mux(_T_869, UInt<1>("h01"), _T_872) @[el2_lib.scala 244:23] - _T_670[28] <= _T_873 @[el2_lib.scala 244:17] - node _T_874 = bits(io.trigger_pkt_any[2].tdata2, 28, 0) @[el2_lib.scala 244:28] - node _T_875 = andr(_T_874) @[el2_lib.scala 244:36] - node _T_876 = and(_T_875, _T_673) @[el2_lib.scala 244:41] - node _T_877 = bits(io.trigger_pkt_any[2].tdata2, 29, 29) @[el2_lib.scala 244:74] - node _T_878 = bits(dec_i0_match_data[2], 29, 29) @[el2_lib.scala 244:86] - node _T_879 = eq(_T_877, _T_878) @[el2_lib.scala 244:78] - node _T_880 = mux(_T_876, UInt<1>("h01"), _T_879) @[el2_lib.scala 244:23] - _T_670[29] <= _T_880 @[el2_lib.scala 244:17] - node _T_881 = bits(io.trigger_pkt_any[2].tdata2, 29, 0) @[el2_lib.scala 244:28] - node _T_882 = andr(_T_881) @[el2_lib.scala 244:36] - node _T_883 = and(_T_882, _T_673) @[el2_lib.scala 244:41] - node _T_884 = bits(io.trigger_pkt_any[2].tdata2, 30, 30) @[el2_lib.scala 244:74] - node _T_885 = bits(dec_i0_match_data[2], 30, 30) @[el2_lib.scala 244:86] - node _T_886 = eq(_T_884, _T_885) @[el2_lib.scala 244:78] - node _T_887 = mux(_T_883, UInt<1>("h01"), _T_886) @[el2_lib.scala 244:23] - _T_670[30] <= _T_887 @[el2_lib.scala 244:17] - node _T_888 = bits(io.trigger_pkt_any[2].tdata2, 30, 0) @[el2_lib.scala 244:28] - node _T_889 = andr(_T_888) @[el2_lib.scala 244:36] - node _T_890 = and(_T_889, _T_673) @[el2_lib.scala 244:41] - node _T_891 = bits(io.trigger_pkt_any[2].tdata2, 31, 31) @[el2_lib.scala 244:74] - node _T_892 = bits(dec_i0_match_data[2], 31, 31) @[el2_lib.scala 244:86] - node _T_893 = eq(_T_891, _T_892) @[el2_lib.scala 244:78] - node _T_894 = mux(_T_890, UInt<1>("h01"), _T_893) @[el2_lib.scala 244:23] - _T_670[31] <= _T_894 @[el2_lib.scala 244:17] - node _T_895 = cat(_T_670[1], _T_670[0]) @[el2_lib.scala 245:14] - node _T_896 = cat(_T_670[3], _T_670[2]) @[el2_lib.scala 245:14] - node _T_897 = cat(_T_896, _T_895) @[el2_lib.scala 245:14] - node _T_898 = cat(_T_670[5], _T_670[4]) @[el2_lib.scala 245:14] - node _T_899 = cat(_T_670[7], _T_670[6]) @[el2_lib.scala 245:14] - node _T_900 = cat(_T_899, _T_898) @[el2_lib.scala 245:14] - node _T_901 = cat(_T_900, _T_897) @[el2_lib.scala 245:14] - node _T_902 = cat(_T_670[9], _T_670[8]) @[el2_lib.scala 245:14] - node _T_903 = cat(_T_670[11], _T_670[10]) @[el2_lib.scala 245:14] - node _T_904 = cat(_T_903, _T_902) @[el2_lib.scala 245:14] - node _T_905 = cat(_T_670[13], _T_670[12]) @[el2_lib.scala 245:14] - node _T_906 = cat(_T_670[15], _T_670[14]) @[el2_lib.scala 245:14] - node _T_907 = cat(_T_906, _T_905) @[el2_lib.scala 245:14] - node _T_908 = cat(_T_907, _T_904) @[el2_lib.scala 245:14] - node _T_909 = cat(_T_908, _T_901) @[el2_lib.scala 245:14] - node _T_910 = cat(_T_670[17], _T_670[16]) @[el2_lib.scala 245:14] - node _T_911 = cat(_T_670[19], _T_670[18]) @[el2_lib.scala 245:14] - node _T_912 = cat(_T_911, _T_910) @[el2_lib.scala 245:14] - node _T_913 = cat(_T_670[21], _T_670[20]) @[el2_lib.scala 245:14] - node _T_914 = cat(_T_670[23], _T_670[22]) @[el2_lib.scala 245:14] - node _T_915 = cat(_T_914, _T_913) @[el2_lib.scala 245:14] - node _T_916 = cat(_T_915, _T_912) @[el2_lib.scala 245:14] - node _T_917 = cat(_T_670[25], _T_670[24]) @[el2_lib.scala 245:14] - node _T_918 = cat(_T_670[27], _T_670[26]) @[el2_lib.scala 245:14] - node _T_919 = cat(_T_918, _T_917) @[el2_lib.scala 245:14] - node _T_920 = cat(_T_670[29], _T_670[28]) @[el2_lib.scala 245:14] - node _T_921 = cat(_T_670[31], _T_670[30]) @[el2_lib.scala 245:14] - node _T_922 = cat(_T_921, _T_920) @[el2_lib.scala 245:14] - node _T_923 = cat(_T_922, _T_919) @[el2_lib.scala 245:14] - node _T_924 = cat(_T_923, _T_916) @[el2_lib.scala 245:14] - node _T_925 = cat(_T_924, _T_909) @[el2_lib.scala 245:14] - node _T_926 = andr(_T_925) @[el2_lib.scala 245:25] + wire _T_670 : UInt<1>[32] @[lib.scala 100:24] + node _T_671 = andr(io.trigger_pkt_any[2].tdata2) @[lib.scala 101:45] + node _T_672 = not(_T_671) @[lib.scala 101:39] + node _T_673 = and(_T_669, _T_672) @[lib.scala 101:37] + node _T_674 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[lib.scala 102:48] + node _T_675 = bits(dec_i0_match_data[2], 0, 0) @[lib.scala 102:60] + node _T_676 = eq(_T_674, _T_675) @[lib.scala 102:52] + node _T_677 = or(_T_673, _T_676) @[lib.scala 102:41] + _T_670[0] <= _T_677 @[lib.scala 102:18] + node _T_678 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[lib.scala 104:28] + node _T_679 = andr(_T_678) @[lib.scala 104:36] + node _T_680 = and(_T_679, _T_673) @[lib.scala 104:41] + node _T_681 = bits(io.trigger_pkt_any[2].tdata2, 1, 1) @[lib.scala 104:74] + node _T_682 = bits(dec_i0_match_data[2], 1, 1) @[lib.scala 104:86] + node _T_683 = eq(_T_681, _T_682) @[lib.scala 104:78] + node _T_684 = mux(_T_680, UInt<1>("h01"), _T_683) @[lib.scala 104:23] + _T_670[1] <= _T_684 @[lib.scala 104:17] + node _T_685 = bits(io.trigger_pkt_any[2].tdata2, 1, 0) @[lib.scala 104:28] + node _T_686 = andr(_T_685) @[lib.scala 104:36] + node _T_687 = and(_T_686, _T_673) @[lib.scala 104:41] + node _T_688 = bits(io.trigger_pkt_any[2].tdata2, 2, 2) @[lib.scala 104:74] + node _T_689 = bits(dec_i0_match_data[2], 2, 2) @[lib.scala 104:86] + node _T_690 = eq(_T_688, _T_689) @[lib.scala 104:78] + node _T_691 = mux(_T_687, UInt<1>("h01"), _T_690) @[lib.scala 104:23] + _T_670[2] <= _T_691 @[lib.scala 104:17] + node _T_692 = bits(io.trigger_pkt_any[2].tdata2, 2, 0) @[lib.scala 104:28] + node _T_693 = andr(_T_692) @[lib.scala 104:36] + node _T_694 = and(_T_693, _T_673) @[lib.scala 104:41] + node _T_695 = bits(io.trigger_pkt_any[2].tdata2, 3, 3) @[lib.scala 104:74] + node _T_696 = bits(dec_i0_match_data[2], 3, 3) @[lib.scala 104:86] + node _T_697 = eq(_T_695, _T_696) @[lib.scala 104:78] + node _T_698 = mux(_T_694, UInt<1>("h01"), _T_697) @[lib.scala 104:23] + _T_670[3] <= _T_698 @[lib.scala 104:17] + node _T_699 = bits(io.trigger_pkt_any[2].tdata2, 3, 0) @[lib.scala 104:28] + node _T_700 = andr(_T_699) @[lib.scala 104:36] + node _T_701 = and(_T_700, _T_673) @[lib.scala 104:41] + node _T_702 = bits(io.trigger_pkt_any[2].tdata2, 4, 4) @[lib.scala 104:74] + node _T_703 = bits(dec_i0_match_data[2], 4, 4) @[lib.scala 104:86] + node _T_704 = eq(_T_702, _T_703) @[lib.scala 104:78] + node _T_705 = mux(_T_701, UInt<1>("h01"), _T_704) @[lib.scala 104:23] + _T_670[4] <= _T_705 @[lib.scala 104:17] + node _T_706 = bits(io.trigger_pkt_any[2].tdata2, 4, 0) @[lib.scala 104:28] + node _T_707 = andr(_T_706) @[lib.scala 104:36] + node _T_708 = and(_T_707, _T_673) @[lib.scala 104:41] + node _T_709 = bits(io.trigger_pkt_any[2].tdata2, 5, 5) @[lib.scala 104:74] + node _T_710 = bits(dec_i0_match_data[2], 5, 5) @[lib.scala 104:86] + node _T_711 = eq(_T_709, _T_710) @[lib.scala 104:78] + node _T_712 = mux(_T_708, UInt<1>("h01"), _T_711) @[lib.scala 104:23] + _T_670[5] <= _T_712 @[lib.scala 104:17] + node _T_713 = bits(io.trigger_pkt_any[2].tdata2, 5, 0) @[lib.scala 104:28] + node _T_714 = andr(_T_713) @[lib.scala 104:36] + node _T_715 = and(_T_714, _T_673) @[lib.scala 104:41] + node _T_716 = bits(io.trigger_pkt_any[2].tdata2, 6, 6) @[lib.scala 104:74] + node _T_717 = bits(dec_i0_match_data[2], 6, 6) @[lib.scala 104:86] + node _T_718 = eq(_T_716, _T_717) @[lib.scala 104:78] + node _T_719 = mux(_T_715, UInt<1>("h01"), _T_718) @[lib.scala 104:23] + _T_670[6] <= _T_719 @[lib.scala 104:17] + node _T_720 = bits(io.trigger_pkt_any[2].tdata2, 6, 0) @[lib.scala 104:28] + node _T_721 = andr(_T_720) @[lib.scala 104:36] + node _T_722 = and(_T_721, _T_673) @[lib.scala 104:41] + node _T_723 = bits(io.trigger_pkt_any[2].tdata2, 7, 7) @[lib.scala 104:74] + node _T_724 = bits(dec_i0_match_data[2], 7, 7) @[lib.scala 104:86] + node _T_725 = eq(_T_723, _T_724) @[lib.scala 104:78] + node _T_726 = mux(_T_722, UInt<1>("h01"), _T_725) @[lib.scala 104:23] + _T_670[7] <= _T_726 @[lib.scala 104:17] + node _T_727 = bits(io.trigger_pkt_any[2].tdata2, 7, 0) @[lib.scala 104:28] + node _T_728 = andr(_T_727) @[lib.scala 104:36] + node _T_729 = and(_T_728, _T_673) @[lib.scala 104:41] + node _T_730 = bits(io.trigger_pkt_any[2].tdata2, 8, 8) @[lib.scala 104:74] + node _T_731 = bits(dec_i0_match_data[2], 8, 8) @[lib.scala 104:86] + node _T_732 = eq(_T_730, _T_731) @[lib.scala 104:78] + node _T_733 = mux(_T_729, UInt<1>("h01"), _T_732) @[lib.scala 104:23] + _T_670[8] <= _T_733 @[lib.scala 104:17] + node _T_734 = bits(io.trigger_pkt_any[2].tdata2, 8, 0) @[lib.scala 104:28] + node _T_735 = andr(_T_734) @[lib.scala 104:36] + node _T_736 = and(_T_735, _T_673) @[lib.scala 104:41] + node _T_737 = bits(io.trigger_pkt_any[2].tdata2, 9, 9) @[lib.scala 104:74] + node _T_738 = bits(dec_i0_match_data[2], 9, 9) @[lib.scala 104:86] + node _T_739 = eq(_T_737, _T_738) @[lib.scala 104:78] + node _T_740 = mux(_T_736, UInt<1>("h01"), _T_739) @[lib.scala 104:23] + _T_670[9] <= _T_740 @[lib.scala 104:17] + node _T_741 = bits(io.trigger_pkt_any[2].tdata2, 9, 0) @[lib.scala 104:28] + node _T_742 = andr(_T_741) @[lib.scala 104:36] + node _T_743 = and(_T_742, _T_673) @[lib.scala 104:41] + node _T_744 = bits(io.trigger_pkt_any[2].tdata2, 10, 10) @[lib.scala 104:74] + node _T_745 = bits(dec_i0_match_data[2], 10, 10) @[lib.scala 104:86] + node _T_746 = eq(_T_744, _T_745) @[lib.scala 104:78] + node _T_747 = mux(_T_743, UInt<1>("h01"), _T_746) @[lib.scala 104:23] + _T_670[10] <= _T_747 @[lib.scala 104:17] + node _T_748 = bits(io.trigger_pkt_any[2].tdata2, 10, 0) @[lib.scala 104:28] + node _T_749 = andr(_T_748) @[lib.scala 104:36] + node _T_750 = and(_T_749, _T_673) @[lib.scala 104:41] + node _T_751 = bits(io.trigger_pkt_any[2].tdata2, 11, 11) @[lib.scala 104:74] + node _T_752 = bits(dec_i0_match_data[2], 11, 11) @[lib.scala 104:86] + node _T_753 = eq(_T_751, _T_752) @[lib.scala 104:78] + node _T_754 = mux(_T_750, UInt<1>("h01"), _T_753) @[lib.scala 104:23] + _T_670[11] <= _T_754 @[lib.scala 104:17] + node _T_755 = bits(io.trigger_pkt_any[2].tdata2, 11, 0) @[lib.scala 104:28] + node _T_756 = andr(_T_755) @[lib.scala 104:36] + node _T_757 = and(_T_756, _T_673) @[lib.scala 104:41] + node _T_758 = bits(io.trigger_pkt_any[2].tdata2, 12, 12) @[lib.scala 104:74] + node _T_759 = bits(dec_i0_match_data[2], 12, 12) @[lib.scala 104:86] + node _T_760 = eq(_T_758, _T_759) @[lib.scala 104:78] + node _T_761 = mux(_T_757, UInt<1>("h01"), _T_760) @[lib.scala 104:23] + _T_670[12] <= _T_761 @[lib.scala 104:17] + node _T_762 = bits(io.trigger_pkt_any[2].tdata2, 12, 0) @[lib.scala 104:28] + node _T_763 = andr(_T_762) @[lib.scala 104:36] + node _T_764 = and(_T_763, _T_673) @[lib.scala 104:41] + node _T_765 = bits(io.trigger_pkt_any[2].tdata2, 13, 13) @[lib.scala 104:74] + node _T_766 = bits(dec_i0_match_data[2], 13, 13) @[lib.scala 104:86] + node _T_767 = eq(_T_765, _T_766) @[lib.scala 104:78] + node _T_768 = mux(_T_764, UInt<1>("h01"), _T_767) @[lib.scala 104:23] + _T_670[13] <= _T_768 @[lib.scala 104:17] + node _T_769 = bits(io.trigger_pkt_any[2].tdata2, 13, 0) @[lib.scala 104:28] + node _T_770 = andr(_T_769) @[lib.scala 104:36] + node _T_771 = and(_T_770, _T_673) @[lib.scala 104:41] + node _T_772 = bits(io.trigger_pkt_any[2].tdata2, 14, 14) @[lib.scala 104:74] + node _T_773 = bits(dec_i0_match_data[2], 14, 14) @[lib.scala 104:86] + node _T_774 = eq(_T_772, _T_773) @[lib.scala 104:78] + node _T_775 = mux(_T_771, UInt<1>("h01"), _T_774) @[lib.scala 104:23] + _T_670[14] <= _T_775 @[lib.scala 104:17] + node _T_776 = bits(io.trigger_pkt_any[2].tdata2, 14, 0) @[lib.scala 104:28] + node _T_777 = andr(_T_776) @[lib.scala 104:36] + node _T_778 = and(_T_777, _T_673) @[lib.scala 104:41] + node _T_779 = bits(io.trigger_pkt_any[2].tdata2, 15, 15) @[lib.scala 104:74] + node _T_780 = bits(dec_i0_match_data[2], 15, 15) @[lib.scala 104:86] + node _T_781 = eq(_T_779, _T_780) @[lib.scala 104:78] + node _T_782 = mux(_T_778, UInt<1>("h01"), _T_781) @[lib.scala 104:23] + _T_670[15] <= _T_782 @[lib.scala 104:17] + node _T_783 = bits(io.trigger_pkt_any[2].tdata2, 15, 0) @[lib.scala 104:28] + node _T_784 = andr(_T_783) @[lib.scala 104:36] + node _T_785 = and(_T_784, _T_673) @[lib.scala 104:41] + node _T_786 = bits(io.trigger_pkt_any[2].tdata2, 16, 16) @[lib.scala 104:74] + node _T_787 = bits(dec_i0_match_data[2], 16, 16) @[lib.scala 104:86] + node _T_788 = eq(_T_786, _T_787) @[lib.scala 104:78] + node _T_789 = mux(_T_785, UInt<1>("h01"), _T_788) @[lib.scala 104:23] + _T_670[16] <= _T_789 @[lib.scala 104:17] + node _T_790 = bits(io.trigger_pkt_any[2].tdata2, 16, 0) @[lib.scala 104:28] + node _T_791 = andr(_T_790) @[lib.scala 104:36] + node _T_792 = and(_T_791, _T_673) @[lib.scala 104:41] + node _T_793 = bits(io.trigger_pkt_any[2].tdata2, 17, 17) @[lib.scala 104:74] + node _T_794 = bits(dec_i0_match_data[2], 17, 17) @[lib.scala 104:86] + node _T_795 = eq(_T_793, _T_794) @[lib.scala 104:78] + node _T_796 = mux(_T_792, UInt<1>("h01"), _T_795) @[lib.scala 104:23] + _T_670[17] <= _T_796 @[lib.scala 104:17] + node _T_797 = bits(io.trigger_pkt_any[2].tdata2, 17, 0) @[lib.scala 104:28] + node _T_798 = andr(_T_797) @[lib.scala 104:36] + node _T_799 = and(_T_798, _T_673) @[lib.scala 104:41] + node _T_800 = bits(io.trigger_pkt_any[2].tdata2, 18, 18) @[lib.scala 104:74] + node _T_801 = bits(dec_i0_match_data[2], 18, 18) @[lib.scala 104:86] + node _T_802 = eq(_T_800, _T_801) @[lib.scala 104:78] + node _T_803 = mux(_T_799, UInt<1>("h01"), _T_802) @[lib.scala 104:23] + _T_670[18] <= _T_803 @[lib.scala 104:17] + node _T_804 = bits(io.trigger_pkt_any[2].tdata2, 18, 0) @[lib.scala 104:28] + node _T_805 = andr(_T_804) @[lib.scala 104:36] + node _T_806 = and(_T_805, _T_673) @[lib.scala 104:41] + node _T_807 = bits(io.trigger_pkt_any[2].tdata2, 19, 19) @[lib.scala 104:74] + node _T_808 = bits(dec_i0_match_data[2], 19, 19) @[lib.scala 104:86] + node _T_809 = eq(_T_807, _T_808) @[lib.scala 104:78] + node _T_810 = mux(_T_806, UInt<1>("h01"), _T_809) @[lib.scala 104:23] + _T_670[19] <= _T_810 @[lib.scala 104:17] + node _T_811 = bits(io.trigger_pkt_any[2].tdata2, 19, 0) @[lib.scala 104:28] + node _T_812 = andr(_T_811) @[lib.scala 104:36] + node _T_813 = and(_T_812, _T_673) @[lib.scala 104:41] + node _T_814 = bits(io.trigger_pkt_any[2].tdata2, 20, 20) @[lib.scala 104:74] + node _T_815 = bits(dec_i0_match_data[2], 20, 20) @[lib.scala 104:86] + node _T_816 = eq(_T_814, _T_815) @[lib.scala 104:78] + node _T_817 = mux(_T_813, UInt<1>("h01"), _T_816) @[lib.scala 104:23] + _T_670[20] <= _T_817 @[lib.scala 104:17] + node _T_818 = bits(io.trigger_pkt_any[2].tdata2, 20, 0) @[lib.scala 104:28] + node _T_819 = andr(_T_818) @[lib.scala 104:36] + node _T_820 = and(_T_819, _T_673) @[lib.scala 104:41] + node _T_821 = bits(io.trigger_pkt_any[2].tdata2, 21, 21) @[lib.scala 104:74] + node _T_822 = bits(dec_i0_match_data[2], 21, 21) @[lib.scala 104:86] + node _T_823 = eq(_T_821, _T_822) @[lib.scala 104:78] + node _T_824 = mux(_T_820, UInt<1>("h01"), _T_823) @[lib.scala 104:23] + _T_670[21] <= _T_824 @[lib.scala 104:17] + node _T_825 = bits(io.trigger_pkt_any[2].tdata2, 21, 0) @[lib.scala 104:28] + node _T_826 = andr(_T_825) @[lib.scala 104:36] + node _T_827 = and(_T_826, _T_673) @[lib.scala 104:41] + node _T_828 = bits(io.trigger_pkt_any[2].tdata2, 22, 22) @[lib.scala 104:74] + node _T_829 = bits(dec_i0_match_data[2], 22, 22) @[lib.scala 104:86] + node _T_830 = eq(_T_828, _T_829) @[lib.scala 104:78] + node _T_831 = mux(_T_827, UInt<1>("h01"), _T_830) @[lib.scala 104:23] + _T_670[22] <= _T_831 @[lib.scala 104:17] + node _T_832 = bits(io.trigger_pkt_any[2].tdata2, 22, 0) @[lib.scala 104:28] + node _T_833 = andr(_T_832) @[lib.scala 104:36] + node _T_834 = and(_T_833, _T_673) @[lib.scala 104:41] + node _T_835 = bits(io.trigger_pkt_any[2].tdata2, 23, 23) @[lib.scala 104:74] + node _T_836 = bits(dec_i0_match_data[2], 23, 23) @[lib.scala 104:86] + node _T_837 = eq(_T_835, _T_836) @[lib.scala 104:78] + node _T_838 = mux(_T_834, UInt<1>("h01"), _T_837) @[lib.scala 104:23] + _T_670[23] <= _T_838 @[lib.scala 104:17] + node _T_839 = bits(io.trigger_pkt_any[2].tdata2, 23, 0) @[lib.scala 104:28] + node _T_840 = andr(_T_839) @[lib.scala 104:36] + node _T_841 = and(_T_840, _T_673) @[lib.scala 104:41] + node _T_842 = bits(io.trigger_pkt_any[2].tdata2, 24, 24) @[lib.scala 104:74] + node _T_843 = bits(dec_i0_match_data[2], 24, 24) @[lib.scala 104:86] + node _T_844 = eq(_T_842, _T_843) @[lib.scala 104:78] + node _T_845 = mux(_T_841, UInt<1>("h01"), _T_844) @[lib.scala 104:23] + _T_670[24] <= _T_845 @[lib.scala 104:17] + node _T_846 = bits(io.trigger_pkt_any[2].tdata2, 24, 0) @[lib.scala 104:28] + node _T_847 = andr(_T_846) @[lib.scala 104:36] + node _T_848 = and(_T_847, _T_673) @[lib.scala 104:41] + node _T_849 = bits(io.trigger_pkt_any[2].tdata2, 25, 25) @[lib.scala 104:74] + node _T_850 = bits(dec_i0_match_data[2], 25, 25) @[lib.scala 104:86] + node _T_851 = eq(_T_849, _T_850) @[lib.scala 104:78] + node _T_852 = mux(_T_848, UInt<1>("h01"), _T_851) @[lib.scala 104:23] + _T_670[25] <= _T_852 @[lib.scala 104:17] + node _T_853 = bits(io.trigger_pkt_any[2].tdata2, 25, 0) @[lib.scala 104:28] + node _T_854 = andr(_T_853) @[lib.scala 104:36] + node _T_855 = and(_T_854, _T_673) @[lib.scala 104:41] + node _T_856 = bits(io.trigger_pkt_any[2].tdata2, 26, 26) @[lib.scala 104:74] + node _T_857 = bits(dec_i0_match_data[2], 26, 26) @[lib.scala 104:86] + node _T_858 = eq(_T_856, _T_857) @[lib.scala 104:78] + node _T_859 = mux(_T_855, UInt<1>("h01"), _T_858) @[lib.scala 104:23] + _T_670[26] <= _T_859 @[lib.scala 104:17] + node _T_860 = bits(io.trigger_pkt_any[2].tdata2, 26, 0) @[lib.scala 104:28] + node _T_861 = andr(_T_860) @[lib.scala 104:36] + node _T_862 = and(_T_861, _T_673) @[lib.scala 104:41] + node _T_863 = bits(io.trigger_pkt_any[2].tdata2, 27, 27) @[lib.scala 104:74] + node _T_864 = bits(dec_i0_match_data[2], 27, 27) @[lib.scala 104:86] + node _T_865 = eq(_T_863, _T_864) @[lib.scala 104:78] + node _T_866 = mux(_T_862, UInt<1>("h01"), _T_865) @[lib.scala 104:23] + _T_670[27] <= _T_866 @[lib.scala 104:17] + node _T_867 = bits(io.trigger_pkt_any[2].tdata2, 27, 0) @[lib.scala 104:28] + node _T_868 = andr(_T_867) @[lib.scala 104:36] + node _T_869 = and(_T_868, _T_673) @[lib.scala 104:41] + node _T_870 = bits(io.trigger_pkt_any[2].tdata2, 28, 28) @[lib.scala 104:74] + node _T_871 = bits(dec_i0_match_data[2], 28, 28) @[lib.scala 104:86] + node _T_872 = eq(_T_870, _T_871) @[lib.scala 104:78] + node _T_873 = mux(_T_869, UInt<1>("h01"), _T_872) @[lib.scala 104:23] + _T_670[28] <= _T_873 @[lib.scala 104:17] + node _T_874 = bits(io.trigger_pkt_any[2].tdata2, 28, 0) @[lib.scala 104:28] + node _T_875 = andr(_T_874) @[lib.scala 104:36] + node _T_876 = and(_T_875, _T_673) @[lib.scala 104:41] + node _T_877 = bits(io.trigger_pkt_any[2].tdata2, 29, 29) @[lib.scala 104:74] + node _T_878 = bits(dec_i0_match_data[2], 29, 29) @[lib.scala 104:86] + node _T_879 = eq(_T_877, _T_878) @[lib.scala 104:78] + node _T_880 = mux(_T_876, UInt<1>("h01"), _T_879) @[lib.scala 104:23] + _T_670[29] <= _T_880 @[lib.scala 104:17] + node _T_881 = bits(io.trigger_pkt_any[2].tdata2, 29, 0) @[lib.scala 104:28] + node _T_882 = andr(_T_881) @[lib.scala 104:36] + node _T_883 = and(_T_882, _T_673) @[lib.scala 104:41] + node _T_884 = bits(io.trigger_pkt_any[2].tdata2, 30, 30) @[lib.scala 104:74] + node _T_885 = bits(dec_i0_match_data[2], 30, 30) @[lib.scala 104:86] + node _T_886 = eq(_T_884, _T_885) @[lib.scala 104:78] + node _T_887 = mux(_T_883, UInt<1>("h01"), _T_886) @[lib.scala 104:23] + _T_670[30] <= _T_887 @[lib.scala 104:17] + node _T_888 = bits(io.trigger_pkt_any[2].tdata2, 30, 0) @[lib.scala 104:28] + node _T_889 = andr(_T_888) @[lib.scala 104:36] + node _T_890 = and(_T_889, _T_673) @[lib.scala 104:41] + node _T_891 = bits(io.trigger_pkt_any[2].tdata2, 31, 31) @[lib.scala 104:74] + node _T_892 = bits(dec_i0_match_data[2], 31, 31) @[lib.scala 104:86] + node _T_893 = eq(_T_891, _T_892) @[lib.scala 104:78] + node _T_894 = mux(_T_890, UInt<1>("h01"), _T_893) @[lib.scala 104:23] + _T_670[31] <= _T_894 @[lib.scala 104:17] + node _T_895 = cat(_T_670[1], _T_670[0]) @[lib.scala 105:14] + node _T_896 = cat(_T_670[3], _T_670[2]) @[lib.scala 105:14] + node _T_897 = cat(_T_896, _T_895) @[lib.scala 105:14] + node _T_898 = cat(_T_670[5], _T_670[4]) @[lib.scala 105:14] + node _T_899 = cat(_T_670[7], _T_670[6]) @[lib.scala 105:14] + node _T_900 = cat(_T_899, _T_898) @[lib.scala 105:14] + node _T_901 = cat(_T_900, _T_897) @[lib.scala 105:14] + node _T_902 = cat(_T_670[9], _T_670[8]) @[lib.scala 105:14] + node _T_903 = cat(_T_670[11], _T_670[10]) @[lib.scala 105:14] + node _T_904 = cat(_T_903, _T_902) @[lib.scala 105:14] + node _T_905 = cat(_T_670[13], _T_670[12]) @[lib.scala 105:14] + node _T_906 = cat(_T_670[15], _T_670[14]) @[lib.scala 105:14] + node _T_907 = cat(_T_906, _T_905) @[lib.scala 105:14] + node _T_908 = cat(_T_907, _T_904) @[lib.scala 105:14] + node _T_909 = cat(_T_908, _T_901) @[lib.scala 105:14] + node _T_910 = cat(_T_670[17], _T_670[16]) @[lib.scala 105:14] + node _T_911 = cat(_T_670[19], _T_670[18]) @[lib.scala 105:14] + node _T_912 = cat(_T_911, _T_910) @[lib.scala 105:14] + node _T_913 = cat(_T_670[21], _T_670[20]) @[lib.scala 105:14] + node _T_914 = cat(_T_670[23], _T_670[22]) @[lib.scala 105:14] + node _T_915 = cat(_T_914, _T_913) @[lib.scala 105:14] + node _T_916 = cat(_T_915, _T_912) @[lib.scala 105:14] + node _T_917 = cat(_T_670[25], _T_670[24]) @[lib.scala 105:14] + node _T_918 = cat(_T_670[27], _T_670[26]) @[lib.scala 105:14] + node _T_919 = cat(_T_918, _T_917) @[lib.scala 105:14] + node _T_920 = cat(_T_670[29], _T_670[28]) @[lib.scala 105:14] + node _T_921 = cat(_T_670[31], _T_670[30]) @[lib.scala 105:14] + node _T_922 = cat(_T_921, _T_920) @[lib.scala 105:14] + node _T_923 = cat(_T_922, _T_919) @[lib.scala 105:14] + node _T_924 = cat(_T_923, _T_916) @[lib.scala 105:14] + node _T_925 = cat(_T_924, _T_909) @[lib.scala 105:14] + node _T_926 = andr(_T_925) @[lib.scala 105:25] node _T_927 = and(_T_668, _T_926) @[dec_trigger.scala 15:109] node _T_928 = and(io.trigger_pkt_any[3].execute, io.trigger_pkt_any[3].m) @[dec_trigger.scala 15:83] node _T_929 = bits(io.trigger_pkt_any[3].match_pkt, 0, 0) @[dec_trigger.scala 15:216] - wire _T_930 : UInt<1>[32] @[el2_lib.scala 240:24] - node _T_931 = andr(io.trigger_pkt_any[3].tdata2) @[el2_lib.scala 241:45] - node _T_932 = not(_T_931) @[el2_lib.scala 241:39] - node _T_933 = and(_T_929, _T_932) @[el2_lib.scala 241:37] - node _T_934 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[el2_lib.scala 242:48] - node _T_935 = bits(dec_i0_match_data[3], 0, 0) @[el2_lib.scala 242:60] - node _T_936 = eq(_T_934, _T_935) @[el2_lib.scala 242:52] - node _T_937 = or(_T_933, _T_936) @[el2_lib.scala 242:41] - _T_930[0] <= _T_937 @[el2_lib.scala 242:18] - node _T_938 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[el2_lib.scala 244:28] - node _T_939 = andr(_T_938) @[el2_lib.scala 244:36] - node _T_940 = and(_T_939, _T_933) @[el2_lib.scala 244:41] - node _T_941 = bits(io.trigger_pkt_any[3].tdata2, 1, 1) @[el2_lib.scala 244:74] - node _T_942 = bits(dec_i0_match_data[3], 1, 1) @[el2_lib.scala 244:86] - node _T_943 = eq(_T_941, _T_942) @[el2_lib.scala 244:78] - node _T_944 = mux(_T_940, UInt<1>("h01"), _T_943) @[el2_lib.scala 244:23] - _T_930[1] <= _T_944 @[el2_lib.scala 244:17] - node _T_945 = bits(io.trigger_pkt_any[3].tdata2, 1, 0) @[el2_lib.scala 244:28] - node _T_946 = andr(_T_945) @[el2_lib.scala 244:36] - node _T_947 = and(_T_946, _T_933) @[el2_lib.scala 244:41] - node _T_948 = bits(io.trigger_pkt_any[3].tdata2, 2, 2) @[el2_lib.scala 244:74] - node _T_949 = bits(dec_i0_match_data[3], 2, 2) @[el2_lib.scala 244:86] - node _T_950 = eq(_T_948, _T_949) @[el2_lib.scala 244:78] - node _T_951 = mux(_T_947, UInt<1>("h01"), _T_950) @[el2_lib.scala 244:23] - _T_930[2] <= _T_951 @[el2_lib.scala 244:17] - node _T_952 = bits(io.trigger_pkt_any[3].tdata2, 2, 0) @[el2_lib.scala 244:28] - node _T_953 = andr(_T_952) @[el2_lib.scala 244:36] - node _T_954 = and(_T_953, _T_933) @[el2_lib.scala 244:41] - node _T_955 = bits(io.trigger_pkt_any[3].tdata2, 3, 3) @[el2_lib.scala 244:74] - node _T_956 = bits(dec_i0_match_data[3], 3, 3) @[el2_lib.scala 244:86] - node _T_957 = eq(_T_955, _T_956) @[el2_lib.scala 244:78] - node _T_958 = mux(_T_954, UInt<1>("h01"), _T_957) @[el2_lib.scala 244:23] - _T_930[3] <= _T_958 @[el2_lib.scala 244:17] - node _T_959 = bits(io.trigger_pkt_any[3].tdata2, 3, 0) @[el2_lib.scala 244:28] - node _T_960 = andr(_T_959) @[el2_lib.scala 244:36] - node _T_961 = and(_T_960, _T_933) @[el2_lib.scala 244:41] - node _T_962 = bits(io.trigger_pkt_any[3].tdata2, 4, 4) @[el2_lib.scala 244:74] - node _T_963 = bits(dec_i0_match_data[3], 4, 4) @[el2_lib.scala 244:86] - node _T_964 = eq(_T_962, _T_963) @[el2_lib.scala 244:78] - node _T_965 = mux(_T_961, UInt<1>("h01"), _T_964) @[el2_lib.scala 244:23] - _T_930[4] <= _T_965 @[el2_lib.scala 244:17] - node _T_966 = bits(io.trigger_pkt_any[3].tdata2, 4, 0) @[el2_lib.scala 244:28] - node _T_967 = andr(_T_966) @[el2_lib.scala 244:36] - node _T_968 = and(_T_967, _T_933) @[el2_lib.scala 244:41] - node _T_969 = bits(io.trigger_pkt_any[3].tdata2, 5, 5) @[el2_lib.scala 244:74] - node _T_970 = bits(dec_i0_match_data[3], 5, 5) @[el2_lib.scala 244:86] - node _T_971 = eq(_T_969, _T_970) @[el2_lib.scala 244:78] - node _T_972 = mux(_T_968, UInt<1>("h01"), _T_971) @[el2_lib.scala 244:23] - _T_930[5] <= _T_972 @[el2_lib.scala 244:17] - node _T_973 = bits(io.trigger_pkt_any[3].tdata2, 5, 0) @[el2_lib.scala 244:28] - node _T_974 = andr(_T_973) @[el2_lib.scala 244:36] - node _T_975 = and(_T_974, _T_933) @[el2_lib.scala 244:41] - node _T_976 = bits(io.trigger_pkt_any[3].tdata2, 6, 6) @[el2_lib.scala 244:74] - node _T_977 = bits(dec_i0_match_data[3], 6, 6) @[el2_lib.scala 244:86] - node _T_978 = eq(_T_976, _T_977) @[el2_lib.scala 244:78] - node _T_979 = mux(_T_975, UInt<1>("h01"), _T_978) @[el2_lib.scala 244:23] - _T_930[6] <= _T_979 @[el2_lib.scala 244:17] - node _T_980 = bits(io.trigger_pkt_any[3].tdata2, 6, 0) @[el2_lib.scala 244:28] - node _T_981 = andr(_T_980) @[el2_lib.scala 244:36] - node _T_982 = and(_T_981, _T_933) @[el2_lib.scala 244:41] - node _T_983 = bits(io.trigger_pkt_any[3].tdata2, 7, 7) @[el2_lib.scala 244:74] - node _T_984 = bits(dec_i0_match_data[3], 7, 7) @[el2_lib.scala 244:86] - node _T_985 = eq(_T_983, _T_984) @[el2_lib.scala 244:78] - node _T_986 = mux(_T_982, UInt<1>("h01"), _T_985) @[el2_lib.scala 244:23] - _T_930[7] <= _T_986 @[el2_lib.scala 244:17] - node _T_987 = bits(io.trigger_pkt_any[3].tdata2, 7, 0) @[el2_lib.scala 244:28] - node _T_988 = andr(_T_987) @[el2_lib.scala 244:36] - node _T_989 = and(_T_988, _T_933) @[el2_lib.scala 244:41] - node _T_990 = bits(io.trigger_pkt_any[3].tdata2, 8, 8) @[el2_lib.scala 244:74] - node _T_991 = bits(dec_i0_match_data[3], 8, 8) @[el2_lib.scala 244:86] - node _T_992 = eq(_T_990, _T_991) @[el2_lib.scala 244:78] - node _T_993 = mux(_T_989, UInt<1>("h01"), _T_992) @[el2_lib.scala 244:23] - _T_930[8] <= _T_993 @[el2_lib.scala 244:17] - node _T_994 = bits(io.trigger_pkt_any[3].tdata2, 8, 0) @[el2_lib.scala 244:28] - node _T_995 = andr(_T_994) @[el2_lib.scala 244:36] - node _T_996 = and(_T_995, _T_933) @[el2_lib.scala 244:41] - node _T_997 = bits(io.trigger_pkt_any[3].tdata2, 9, 9) @[el2_lib.scala 244:74] - node _T_998 = bits(dec_i0_match_data[3], 9, 9) @[el2_lib.scala 244:86] - node _T_999 = eq(_T_997, _T_998) @[el2_lib.scala 244:78] - node _T_1000 = mux(_T_996, UInt<1>("h01"), _T_999) @[el2_lib.scala 244:23] - _T_930[9] <= _T_1000 @[el2_lib.scala 244:17] - node _T_1001 = bits(io.trigger_pkt_any[3].tdata2, 9, 0) @[el2_lib.scala 244:28] - node _T_1002 = andr(_T_1001) @[el2_lib.scala 244:36] - node _T_1003 = and(_T_1002, _T_933) @[el2_lib.scala 244:41] - node _T_1004 = bits(io.trigger_pkt_any[3].tdata2, 10, 10) @[el2_lib.scala 244:74] - node _T_1005 = bits(dec_i0_match_data[3], 10, 10) @[el2_lib.scala 244:86] - node _T_1006 = eq(_T_1004, _T_1005) @[el2_lib.scala 244:78] - node _T_1007 = mux(_T_1003, UInt<1>("h01"), _T_1006) @[el2_lib.scala 244:23] - _T_930[10] <= _T_1007 @[el2_lib.scala 244:17] - node _T_1008 = bits(io.trigger_pkt_any[3].tdata2, 10, 0) @[el2_lib.scala 244:28] - node _T_1009 = andr(_T_1008) @[el2_lib.scala 244:36] - node _T_1010 = and(_T_1009, _T_933) @[el2_lib.scala 244:41] - node _T_1011 = bits(io.trigger_pkt_any[3].tdata2, 11, 11) @[el2_lib.scala 244:74] - node _T_1012 = bits(dec_i0_match_data[3], 11, 11) @[el2_lib.scala 244:86] - node _T_1013 = eq(_T_1011, _T_1012) @[el2_lib.scala 244:78] - node _T_1014 = mux(_T_1010, UInt<1>("h01"), _T_1013) @[el2_lib.scala 244:23] - _T_930[11] <= _T_1014 @[el2_lib.scala 244:17] - node _T_1015 = bits(io.trigger_pkt_any[3].tdata2, 11, 0) @[el2_lib.scala 244:28] - node _T_1016 = andr(_T_1015) @[el2_lib.scala 244:36] - node _T_1017 = and(_T_1016, _T_933) @[el2_lib.scala 244:41] - node _T_1018 = bits(io.trigger_pkt_any[3].tdata2, 12, 12) @[el2_lib.scala 244:74] - node _T_1019 = bits(dec_i0_match_data[3], 12, 12) @[el2_lib.scala 244:86] - node _T_1020 = eq(_T_1018, _T_1019) @[el2_lib.scala 244:78] - node _T_1021 = mux(_T_1017, UInt<1>("h01"), _T_1020) @[el2_lib.scala 244:23] - _T_930[12] <= _T_1021 @[el2_lib.scala 244:17] - node _T_1022 = bits(io.trigger_pkt_any[3].tdata2, 12, 0) @[el2_lib.scala 244:28] - node _T_1023 = andr(_T_1022) @[el2_lib.scala 244:36] - node _T_1024 = and(_T_1023, _T_933) @[el2_lib.scala 244:41] - node _T_1025 = bits(io.trigger_pkt_any[3].tdata2, 13, 13) @[el2_lib.scala 244:74] - node _T_1026 = bits(dec_i0_match_data[3], 13, 13) @[el2_lib.scala 244:86] - node _T_1027 = eq(_T_1025, _T_1026) @[el2_lib.scala 244:78] - node _T_1028 = mux(_T_1024, UInt<1>("h01"), _T_1027) @[el2_lib.scala 244:23] - _T_930[13] <= _T_1028 @[el2_lib.scala 244:17] - node _T_1029 = bits(io.trigger_pkt_any[3].tdata2, 13, 0) @[el2_lib.scala 244:28] - node _T_1030 = andr(_T_1029) @[el2_lib.scala 244:36] - node _T_1031 = and(_T_1030, _T_933) @[el2_lib.scala 244:41] - node _T_1032 = bits(io.trigger_pkt_any[3].tdata2, 14, 14) @[el2_lib.scala 244:74] - node _T_1033 = bits(dec_i0_match_data[3], 14, 14) @[el2_lib.scala 244:86] - node _T_1034 = eq(_T_1032, _T_1033) @[el2_lib.scala 244:78] - node _T_1035 = mux(_T_1031, UInt<1>("h01"), _T_1034) @[el2_lib.scala 244:23] - _T_930[14] <= _T_1035 @[el2_lib.scala 244:17] - node _T_1036 = bits(io.trigger_pkt_any[3].tdata2, 14, 0) @[el2_lib.scala 244:28] - node _T_1037 = andr(_T_1036) @[el2_lib.scala 244:36] - node _T_1038 = and(_T_1037, _T_933) @[el2_lib.scala 244:41] - node _T_1039 = bits(io.trigger_pkt_any[3].tdata2, 15, 15) @[el2_lib.scala 244:74] - node _T_1040 = bits(dec_i0_match_data[3], 15, 15) @[el2_lib.scala 244:86] - node _T_1041 = eq(_T_1039, _T_1040) @[el2_lib.scala 244:78] - node _T_1042 = mux(_T_1038, UInt<1>("h01"), _T_1041) @[el2_lib.scala 244:23] - _T_930[15] <= _T_1042 @[el2_lib.scala 244:17] - node _T_1043 = bits(io.trigger_pkt_any[3].tdata2, 15, 0) @[el2_lib.scala 244:28] - node _T_1044 = andr(_T_1043) @[el2_lib.scala 244:36] - node _T_1045 = and(_T_1044, _T_933) @[el2_lib.scala 244:41] - node _T_1046 = bits(io.trigger_pkt_any[3].tdata2, 16, 16) @[el2_lib.scala 244:74] - node _T_1047 = bits(dec_i0_match_data[3], 16, 16) @[el2_lib.scala 244:86] - node _T_1048 = eq(_T_1046, _T_1047) @[el2_lib.scala 244:78] - node _T_1049 = mux(_T_1045, UInt<1>("h01"), _T_1048) @[el2_lib.scala 244:23] - _T_930[16] <= _T_1049 @[el2_lib.scala 244:17] - node _T_1050 = bits(io.trigger_pkt_any[3].tdata2, 16, 0) @[el2_lib.scala 244:28] - node _T_1051 = andr(_T_1050) @[el2_lib.scala 244:36] - node _T_1052 = and(_T_1051, _T_933) @[el2_lib.scala 244:41] - node _T_1053 = bits(io.trigger_pkt_any[3].tdata2, 17, 17) @[el2_lib.scala 244:74] - node _T_1054 = bits(dec_i0_match_data[3], 17, 17) @[el2_lib.scala 244:86] - node _T_1055 = eq(_T_1053, _T_1054) @[el2_lib.scala 244:78] - node _T_1056 = mux(_T_1052, UInt<1>("h01"), _T_1055) @[el2_lib.scala 244:23] - _T_930[17] <= _T_1056 @[el2_lib.scala 244:17] - node _T_1057 = bits(io.trigger_pkt_any[3].tdata2, 17, 0) @[el2_lib.scala 244:28] - node _T_1058 = andr(_T_1057) @[el2_lib.scala 244:36] - node _T_1059 = and(_T_1058, _T_933) @[el2_lib.scala 244:41] - node _T_1060 = bits(io.trigger_pkt_any[3].tdata2, 18, 18) @[el2_lib.scala 244:74] - node _T_1061 = bits(dec_i0_match_data[3], 18, 18) @[el2_lib.scala 244:86] - node _T_1062 = eq(_T_1060, _T_1061) @[el2_lib.scala 244:78] - node _T_1063 = mux(_T_1059, UInt<1>("h01"), _T_1062) @[el2_lib.scala 244:23] - _T_930[18] <= _T_1063 @[el2_lib.scala 244:17] - node _T_1064 = bits(io.trigger_pkt_any[3].tdata2, 18, 0) @[el2_lib.scala 244:28] - node _T_1065 = andr(_T_1064) @[el2_lib.scala 244:36] - node _T_1066 = and(_T_1065, _T_933) @[el2_lib.scala 244:41] - node _T_1067 = bits(io.trigger_pkt_any[3].tdata2, 19, 19) @[el2_lib.scala 244:74] - node _T_1068 = bits(dec_i0_match_data[3], 19, 19) @[el2_lib.scala 244:86] - node _T_1069 = eq(_T_1067, _T_1068) @[el2_lib.scala 244:78] - node _T_1070 = mux(_T_1066, UInt<1>("h01"), _T_1069) @[el2_lib.scala 244:23] - _T_930[19] <= _T_1070 @[el2_lib.scala 244:17] - node _T_1071 = bits(io.trigger_pkt_any[3].tdata2, 19, 0) @[el2_lib.scala 244:28] - node _T_1072 = andr(_T_1071) @[el2_lib.scala 244:36] - node _T_1073 = and(_T_1072, _T_933) @[el2_lib.scala 244:41] - node _T_1074 = bits(io.trigger_pkt_any[3].tdata2, 20, 20) @[el2_lib.scala 244:74] - node _T_1075 = bits(dec_i0_match_data[3], 20, 20) @[el2_lib.scala 244:86] - node _T_1076 = eq(_T_1074, _T_1075) @[el2_lib.scala 244:78] - node _T_1077 = mux(_T_1073, UInt<1>("h01"), _T_1076) @[el2_lib.scala 244:23] - _T_930[20] <= _T_1077 @[el2_lib.scala 244:17] - node _T_1078 = bits(io.trigger_pkt_any[3].tdata2, 20, 0) @[el2_lib.scala 244:28] - node _T_1079 = andr(_T_1078) @[el2_lib.scala 244:36] - node _T_1080 = and(_T_1079, _T_933) @[el2_lib.scala 244:41] - node _T_1081 = bits(io.trigger_pkt_any[3].tdata2, 21, 21) @[el2_lib.scala 244:74] - node _T_1082 = bits(dec_i0_match_data[3], 21, 21) @[el2_lib.scala 244:86] - node _T_1083 = eq(_T_1081, _T_1082) @[el2_lib.scala 244:78] - node _T_1084 = mux(_T_1080, UInt<1>("h01"), _T_1083) @[el2_lib.scala 244:23] - _T_930[21] <= _T_1084 @[el2_lib.scala 244:17] - node _T_1085 = bits(io.trigger_pkt_any[3].tdata2, 21, 0) @[el2_lib.scala 244:28] - node _T_1086 = andr(_T_1085) @[el2_lib.scala 244:36] - node _T_1087 = and(_T_1086, _T_933) @[el2_lib.scala 244:41] - node _T_1088 = bits(io.trigger_pkt_any[3].tdata2, 22, 22) @[el2_lib.scala 244:74] - node _T_1089 = bits(dec_i0_match_data[3], 22, 22) @[el2_lib.scala 244:86] - node _T_1090 = eq(_T_1088, _T_1089) @[el2_lib.scala 244:78] - node _T_1091 = mux(_T_1087, UInt<1>("h01"), _T_1090) @[el2_lib.scala 244:23] - _T_930[22] <= _T_1091 @[el2_lib.scala 244:17] - node _T_1092 = bits(io.trigger_pkt_any[3].tdata2, 22, 0) @[el2_lib.scala 244:28] - node _T_1093 = andr(_T_1092) @[el2_lib.scala 244:36] - node _T_1094 = and(_T_1093, _T_933) @[el2_lib.scala 244:41] - node _T_1095 = bits(io.trigger_pkt_any[3].tdata2, 23, 23) @[el2_lib.scala 244:74] - node _T_1096 = bits(dec_i0_match_data[3], 23, 23) @[el2_lib.scala 244:86] - node _T_1097 = eq(_T_1095, _T_1096) @[el2_lib.scala 244:78] - node _T_1098 = mux(_T_1094, UInt<1>("h01"), _T_1097) @[el2_lib.scala 244:23] - _T_930[23] <= _T_1098 @[el2_lib.scala 244:17] - node _T_1099 = bits(io.trigger_pkt_any[3].tdata2, 23, 0) @[el2_lib.scala 244:28] - node _T_1100 = andr(_T_1099) @[el2_lib.scala 244:36] - node _T_1101 = and(_T_1100, _T_933) @[el2_lib.scala 244:41] - node _T_1102 = bits(io.trigger_pkt_any[3].tdata2, 24, 24) @[el2_lib.scala 244:74] - node _T_1103 = bits(dec_i0_match_data[3], 24, 24) @[el2_lib.scala 244:86] - node _T_1104 = eq(_T_1102, _T_1103) @[el2_lib.scala 244:78] - node _T_1105 = mux(_T_1101, UInt<1>("h01"), _T_1104) @[el2_lib.scala 244:23] - _T_930[24] <= _T_1105 @[el2_lib.scala 244:17] - node _T_1106 = bits(io.trigger_pkt_any[3].tdata2, 24, 0) @[el2_lib.scala 244:28] - node _T_1107 = andr(_T_1106) @[el2_lib.scala 244:36] - node _T_1108 = and(_T_1107, _T_933) @[el2_lib.scala 244:41] - node _T_1109 = bits(io.trigger_pkt_any[3].tdata2, 25, 25) @[el2_lib.scala 244:74] - node _T_1110 = bits(dec_i0_match_data[3], 25, 25) @[el2_lib.scala 244:86] - node _T_1111 = eq(_T_1109, _T_1110) @[el2_lib.scala 244:78] - node _T_1112 = mux(_T_1108, UInt<1>("h01"), _T_1111) @[el2_lib.scala 244:23] - _T_930[25] <= _T_1112 @[el2_lib.scala 244:17] - node _T_1113 = bits(io.trigger_pkt_any[3].tdata2, 25, 0) @[el2_lib.scala 244:28] - node _T_1114 = andr(_T_1113) @[el2_lib.scala 244:36] - node _T_1115 = and(_T_1114, _T_933) @[el2_lib.scala 244:41] - node _T_1116 = bits(io.trigger_pkt_any[3].tdata2, 26, 26) @[el2_lib.scala 244:74] - node _T_1117 = bits(dec_i0_match_data[3], 26, 26) @[el2_lib.scala 244:86] - node _T_1118 = eq(_T_1116, _T_1117) @[el2_lib.scala 244:78] - node _T_1119 = mux(_T_1115, UInt<1>("h01"), _T_1118) @[el2_lib.scala 244:23] - _T_930[26] <= _T_1119 @[el2_lib.scala 244:17] - node _T_1120 = bits(io.trigger_pkt_any[3].tdata2, 26, 0) @[el2_lib.scala 244:28] - node _T_1121 = andr(_T_1120) @[el2_lib.scala 244:36] - node _T_1122 = and(_T_1121, _T_933) @[el2_lib.scala 244:41] - node _T_1123 = bits(io.trigger_pkt_any[3].tdata2, 27, 27) @[el2_lib.scala 244:74] - node _T_1124 = bits(dec_i0_match_data[3], 27, 27) @[el2_lib.scala 244:86] - node _T_1125 = eq(_T_1123, _T_1124) @[el2_lib.scala 244:78] - node _T_1126 = mux(_T_1122, UInt<1>("h01"), _T_1125) @[el2_lib.scala 244:23] - _T_930[27] <= _T_1126 @[el2_lib.scala 244:17] - node _T_1127 = bits(io.trigger_pkt_any[3].tdata2, 27, 0) @[el2_lib.scala 244:28] - node _T_1128 = andr(_T_1127) @[el2_lib.scala 244:36] - node _T_1129 = and(_T_1128, _T_933) @[el2_lib.scala 244:41] - node _T_1130 = bits(io.trigger_pkt_any[3].tdata2, 28, 28) @[el2_lib.scala 244:74] - node _T_1131 = bits(dec_i0_match_data[3], 28, 28) @[el2_lib.scala 244:86] - node _T_1132 = eq(_T_1130, _T_1131) @[el2_lib.scala 244:78] - node _T_1133 = mux(_T_1129, UInt<1>("h01"), _T_1132) @[el2_lib.scala 244:23] - _T_930[28] <= _T_1133 @[el2_lib.scala 244:17] - node _T_1134 = bits(io.trigger_pkt_any[3].tdata2, 28, 0) @[el2_lib.scala 244:28] - node _T_1135 = andr(_T_1134) @[el2_lib.scala 244:36] - node _T_1136 = and(_T_1135, _T_933) @[el2_lib.scala 244:41] - node _T_1137 = bits(io.trigger_pkt_any[3].tdata2, 29, 29) @[el2_lib.scala 244:74] - node _T_1138 = bits(dec_i0_match_data[3], 29, 29) @[el2_lib.scala 244:86] - node _T_1139 = eq(_T_1137, _T_1138) @[el2_lib.scala 244:78] - node _T_1140 = mux(_T_1136, UInt<1>("h01"), _T_1139) @[el2_lib.scala 244:23] - _T_930[29] <= _T_1140 @[el2_lib.scala 244:17] - node _T_1141 = bits(io.trigger_pkt_any[3].tdata2, 29, 0) @[el2_lib.scala 244:28] - node _T_1142 = andr(_T_1141) @[el2_lib.scala 244:36] - node _T_1143 = and(_T_1142, _T_933) @[el2_lib.scala 244:41] - node _T_1144 = bits(io.trigger_pkt_any[3].tdata2, 30, 30) @[el2_lib.scala 244:74] - node _T_1145 = bits(dec_i0_match_data[3], 30, 30) @[el2_lib.scala 244:86] - node _T_1146 = eq(_T_1144, _T_1145) @[el2_lib.scala 244:78] - node _T_1147 = mux(_T_1143, UInt<1>("h01"), _T_1146) @[el2_lib.scala 244:23] - _T_930[30] <= _T_1147 @[el2_lib.scala 244:17] - node _T_1148 = bits(io.trigger_pkt_any[3].tdata2, 30, 0) @[el2_lib.scala 244:28] - node _T_1149 = andr(_T_1148) @[el2_lib.scala 244:36] - node _T_1150 = and(_T_1149, _T_933) @[el2_lib.scala 244:41] - node _T_1151 = bits(io.trigger_pkt_any[3].tdata2, 31, 31) @[el2_lib.scala 244:74] - node _T_1152 = bits(dec_i0_match_data[3], 31, 31) @[el2_lib.scala 244:86] - node _T_1153 = eq(_T_1151, _T_1152) @[el2_lib.scala 244:78] - node _T_1154 = mux(_T_1150, UInt<1>("h01"), _T_1153) @[el2_lib.scala 244:23] - _T_930[31] <= _T_1154 @[el2_lib.scala 244:17] - node _T_1155 = cat(_T_930[1], _T_930[0]) @[el2_lib.scala 245:14] - node _T_1156 = cat(_T_930[3], _T_930[2]) @[el2_lib.scala 245:14] - node _T_1157 = cat(_T_1156, _T_1155) @[el2_lib.scala 245:14] - node _T_1158 = cat(_T_930[5], _T_930[4]) @[el2_lib.scala 245:14] - node _T_1159 = cat(_T_930[7], _T_930[6]) @[el2_lib.scala 245:14] - node _T_1160 = cat(_T_1159, _T_1158) @[el2_lib.scala 245:14] - node _T_1161 = cat(_T_1160, _T_1157) @[el2_lib.scala 245:14] - node _T_1162 = cat(_T_930[9], _T_930[8]) @[el2_lib.scala 245:14] - node _T_1163 = cat(_T_930[11], _T_930[10]) @[el2_lib.scala 245:14] - node _T_1164 = cat(_T_1163, _T_1162) @[el2_lib.scala 245:14] - node _T_1165 = cat(_T_930[13], _T_930[12]) @[el2_lib.scala 245:14] - node _T_1166 = cat(_T_930[15], _T_930[14]) @[el2_lib.scala 245:14] - node _T_1167 = cat(_T_1166, _T_1165) @[el2_lib.scala 245:14] - node _T_1168 = cat(_T_1167, _T_1164) @[el2_lib.scala 245:14] - node _T_1169 = cat(_T_1168, _T_1161) @[el2_lib.scala 245:14] - node _T_1170 = cat(_T_930[17], _T_930[16]) @[el2_lib.scala 245:14] - node _T_1171 = cat(_T_930[19], _T_930[18]) @[el2_lib.scala 245:14] - node _T_1172 = cat(_T_1171, _T_1170) @[el2_lib.scala 245:14] - node _T_1173 = cat(_T_930[21], _T_930[20]) @[el2_lib.scala 245:14] - node _T_1174 = cat(_T_930[23], _T_930[22]) @[el2_lib.scala 245:14] - node _T_1175 = cat(_T_1174, _T_1173) @[el2_lib.scala 245:14] - node _T_1176 = cat(_T_1175, _T_1172) @[el2_lib.scala 245:14] - node _T_1177 = cat(_T_930[25], _T_930[24]) @[el2_lib.scala 245:14] - node _T_1178 = cat(_T_930[27], _T_930[26]) @[el2_lib.scala 245:14] - node _T_1179 = cat(_T_1178, _T_1177) @[el2_lib.scala 245:14] - node _T_1180 = cat(_T_930[29], _T_930[28]) @[el2_lib.scala 245:14] - node _T_1181 = cat(_T_930[31], _T_930[30]) @[el2_lib.scala 245:14] - node _T_1182 = cat(_T_1181, _T_1180) @[el2_lib.scala 245:14] - node _T_1183 = cat(_T_1182, _T_1179) @[el2_lib.scala 245:14] - node _T_1184 = cat(_T_1183, _T_1176) @[el2_lib.scala 245:14] - node _T_1185 = cat(_T_1184, _T_1169) @[el2_lib.scala 245:14] - node _T_1186 = andr(_T_1185) @[el2_lib.scala 245:25] + wire _T_930 : UInt<1>[32] @[lib.scala 100:24] + node _T_931 = andr(io.trigger_pkt_any[3].tdata2) @[lib.scala 101:45] + node _T_932 = not(_T_931) @[lib.scala 101:39] + node _T_933 = and(_T_929, _T_932) @[lib.scala 101:37] + node _T_934 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[lib.scala 102:48] + node _T_935 = bits(dec_i0_match_data[3], 0, 0) @[lib.scala 102:60] + node _T_936 = eq(_T_934, _T_935) @[lib.scala 102:52] + node _T_937 = or(_T_933, _T_936) @[lib.scala 102:41] + _T_930[0] <= _T_937 @[lib.scala 102:18] + node _T_938 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[lib.scala 104:28] + node _T_939 = andr(_T_938) @[lib.scala 104:36] + node _T_940 = and(_T_939, _T_933) @[lib.scala 104:41] + node _T_941 = bits(io.trigger_pkt_any[3].tdata2, 1, 1) @[lib.scala 104:74] + node _T_942 = bits(dec_i0_match_data[3], 1, 1) @[lib.scala 104:86] + node _T_943 = eq(_T_941, _T_942) @[lib.scala 104:78] + node _T_944 = mux(_T_940, UInt<1>("h01"), _T_943) @[lib.scala 104:23] + _T_930[1] <= _T_944 @[lib.scala 104:17] + node _T_945 = bits(io.trigger_pkt_any[3].tdata2, 1, 0) @[lib.scala 104:28] + node _T_946 = andr(_T_945) @[lib.scala 104:36] + node _T_947 = and(_T_946, _T_933) @[lib.scala 104:41] + node _T_948 = bits(io.trigger_pkt_any[3].tdata2, 2, 2) @[lib.scala 104:74] + node _T_949 = bits(dec_i0_match_data[3], 2, 2) @[lib.scala 104:86] + node _T_950 = eq(_T_948, _T_949) @[lib.scala 104:78] + node _T_951 = mux(_T_947, UInt<1>("h01"), _T_950) @[lib.scala 104:23] + _T_930[2] <= _T_951 @[lib.scala 104:17] + node _T_952 = bits(io.trigger_pkt_any[3].tdata2, 2, 0) @[lib.scala 104:28] + node _T_953 = andr(_T_952) @[lib.scala 104:36] + node _T_954 = and(_T_953, _T_933) @[lib.scala 104:41] + node _T_955 = bits(io.trigger_pkt_any[3].tdata2, 3, 3) @[lib.scala 104:74] + node _T_956 = bits(dec_i0_match_data[3], 3, 3) @[lib.scala 104:86] + node _T_957 = eq(_T_955, _T_956) @[lib.scala 104:78] + node _T_958 = mux(_T_954, UInt<1>("h01"), _T_957) @[lib.scala 104:23] + _T_930[3] <= _T_958 @[lib.scala 104:17] + node _T_959 = bits(io.trigger_pkt_any[3].tdata2, 3, 0) @[lib.scala 104:28] + node _T_960 = andr(_T_959) @[lib.scala 104:36] + node _T_961 = and(_T_960, _T_933) @[lib.scala 104:41] + node _T_962 = bits(io.trigger_pkt_any[3].tdata2, 4, 4) @[lib.scala 104:74] + node _T_963 = bits(dec_i0_match_data[3], 4, 4) @[lib.scala 104:86] + node _T_964 = eq(_T_962, _T_963) @[lib.scala 104:78] + node _T_965 = mux(_T_961, UInt<1>("h01"), _T_964) @[lib.scala 104:23] + _T_930[4] <= _T_965 @[lib.scala 104:17] + node _T_966 = bits(io.trigger_pkt_any[3].tdata2, 4, 0) @[lib.scala 104:28] + node _T_967 = andr(_T_966) @[lib.scala 104:36] + node _T_968 = and(_T_967, _T_933) @[lib.scala 104:41] + node _T_969 = bits(io.trigger_pkt_any[3].tdata2, 5, 5) @[lib.scala 104:74] + node _T_970 = bits(dec_i0_match_data[3], 5, 5) @[lib.scala 104:86] + node _T_971 = eq(_T_969, _T_970) @[lib.scala 104:78] + node _T_972 = mux(_T_968, UInt<1>("h01"), _T_971) @[lib.scala 104:23] + _T_930[5] <= _T_972 @[lib.scala 104:17] + node _T_973 = bits(io.trigger_pkt_any[3].tdata2, 5, 0) @[lib.scala 104:28] + node _T_974 = andr(_T_973) @[lib.scala 104:36] + node _T_975 = and(_T_974, _T_933) @[lib.scala 104:41] + node _T_976 = bits(io.trigger_pkt_any[3].tdata2, 6, 6) @[lib.scala 104:74] + node _T_977 = bits(dec_i0_match_data[3], 6, 6) @[lib.scala 104:86] + node _T_978 = eq(_T_976, _T_977) @[lib.scala 104:78] + node _T_979 = mux(_T_975, UInt<1>("h01"), _T_978) @[lib.scala 104:23] + _T_930[6] <= _T_979 @[lib.scala 104:17] + node _T_980 = bits(io.trigger_pkt_any[3].tdata2, 6, 0) @[lib.scala 104:28] + node _T_981 = andr(_T_980) @[lib.scala 104:36] + node _T_982 = and(_T_981, _T_933) @[lib.scala 104:41] + node _T_983 = bits(io.trigger_pkt_any[3].tdata2, 7, 7) @[lib.scala 104:74] + node _T_984 = bits(dec_i0_match_data[3], 7, 7) @[lib.scala 104:86] + node _T_985 = eq(_T_983, _T_984) @[lib.scala 104:78] + node _T_986 = mux(_T_982, UInt<1>("h01"), _T_985) @[lib.scala 104:23] + _T_930[7] <= _T_986 @[lib.scala 104:17] + node _T_987 = bits(io.trigger_pkt_any[3].tdata2, 7, 0) @[lib.scala 104:28] + node _T_988 = andr(_T_987) @[lib.scala 104:36] + node _T_989 = and(_T_988, _T_933) @[lib.scala 104:41] + node _T_990 = bits(io.trigger_pkt_any[3].tdata2, 8, 8) @[lib.scala 104:74] + node _T_991 = bits(dec_i0_match_data[3], 8, 8) @[lib.scala 104:86] + node _T_992 = eq(_T_990, _T_991) @[lib.scala 104:78] + node _T_993 = mux(_T_989, UInt<1>("h01"), _T_992) @[lib.scala 104:23] + _T_930[8] <= _T_993 @[lib.scala 104:17] + node _T_994 = bits(io.trigger_pkt_any[3].tdata2, 8, 0) @[lib.scala 104:28] + node _T_995 = andr(_T_994) @[lib.scala 104:36] + node _T_996 = and(_T_995, _T_933) @[lib.scala 104:41] + node _T_997 = bits(io.trigger_pkt_any[3].tdata2, 9, 9) @[lib.scala 104:74] + node _T_998 = bits(dec_i0_match_data[3], 9, 9) @[lib.scala 104:86] + node _T_999 = eq(_T_997, _T_998) @[lib.scala 104:78] + node _T_1000 = mux(_T_996, UInt<1>("h01"), _T_999) @[lib.scala 104:23] + _T_930[9] <= _T_1000 @[lib.scala 104:17] + node _T_1001 = bits(io.trigger_pkt_any[3].tdata2, 9, 0) @[lib.scala 104:28] + node _T_1002 = andr(_T_1001) @[lib.scala 104:36] + node _T_1003 = and(_T_1002, _T_933) @[lib.scala 104:41] + node _T_1004 = bits(io.trigger_pkt_any[3].tdata2, 10, 10) @[lib.scala 104:74] + node _T_1005 = bits(dec_i0_match_data[3], 10, 10) @[lib.scala 104:86] + node _T_1006 = eq(_T_1004, _T_1005) @[lib.scala 104:78] + node _T_1007 = mux(_T_1003, UInt<1>("h01"), _T_1006) @[lib.scala 104:23] + _T_930[10] <= _T_1007 @[lib.scala 104:17] + node _T_1008 = bits(io.trigger_pkt_any[3].tdata2, 10, 0) @[lib.scala 104:28] + node _T_1009 = andr(_T_1008) @[lib.scala 104:36] + node _T_1010 = and(_T_1009, _T_933) @[lib.scala 104:41] + node _T_1011 = bits(io.trigger_pkt_any[3].tdata2, 11, 11) @[lib.scala 104:74] + node _T_1012 = bits(dec_i0_match_data[3], 11, 11) @[lib.scala 104:86] + node _T_1013 = eq(_T_1011, _T_1012) @[lib.scala 104:78] + node _T_1014 = mux(_T_1010, UInt<1>("h01"), _T_1013) @[lib.scala 104:23] + _T_930[11] <= _T_1014 @[lib.scala 104:17] + node _T_1015 = bits(io.trigger_pkt_any[3].tdata2, 11, 0) @[lib.scala 104:28] + node _T_1016 = andr(_T_1015) @[lib.scala 104:36] + node _T_1017 = and(_T_1016, _T_933) @[lib.scala 104:41] + node _T_1018 = bits(io.trigger_pkt_any[3].tdata2, 12, 12) @[lib.scala 104:74] + node _T_1019 = bits(dec_i0_match_data[3], 12, 12) @[lib.scala 104:86] + node _T_1020 = eq(_T_1018, _T_1019) @[lib.scala 104:78] + node _T_1021 = mux(_T_1017, UInt<1>("h01"), _T_1020) @[lib.scala 104:23] + _T_930[12] <= _T_1021 @[lib.scala 104:17] + node _T_1022 = bits(io.trigger_pkt_any[3].tdata2, 12, 0) @[lib.scala 104:28] + node _T_1023 = andr(_T_1022) @[lib.scala 104:36] + node _T_1024 = and(_T_1023, _T_933) @[lib.scala 104:41] + node _T_1025 = bits(io.trigger_pkt_any[3].tdata2, 13, 13) @[lib.scala 104:74] + node _T_1026 = bits(dec_i0_match_data[3], 13, 13) @[lib.scala 104:86] + node _T_1027 = eq(_T_1025, _T_1026) @[lib.scala 104:78] + node _T_1028 = mux(_T_1024, UInt<1>("h01"), _T_1027) @[lib.scala 104:23] + _T_930[13] <= _T_1028 @[lib.scala 104:17] + node _T_1029 = bits(io.trigger_pkt_any[3].tdata2, 13, 0) @[lib.scala 104:28] + node _T_1030 = andr(_T_1029) @[lib.scala 104:36] + node _T_1031 = and(_T_1030, _T_933) @[lib.scala 104:41] + node _T_1032 = bits(io.trigger_pkt_any[3].tdata2, 14, 14) @[lib.scala 104:74] + node _T_1033 = bits(dec_i0_match_data[3], 14, 14) @[lib.scala 104:86] + node _T_1034 = eq(_T_1032, _T_1033) @[lib.scala 104:78] + node _T_1035 = mux(_T_1031, UInt<1>("h01"), _T_1034) @[lib.scala 104:23] + _T_930[14] <= _T_1035 @[lib.scala 104:17] + node _T_1036 = bits(io.trigger_pkt_any[3].tdata2, 14, 0) @[lib.scala 104:28] + node _T_1037 = andr(_T_1036) @[lib.scala 104:36] + node _T_1038 = and(_T_1037, _T_933) @[lib.scala 104:41] + node _T_1039 = bits(io.trigger_pkt_any[3].tdata2, 15, 15) @[lib.scala 104:74] + node _T_1040 = bits(dec_i0_match_data[3], 15, 15) @[lib.scala 104:86] + node _T_1041 = eq(_T_1039, _T_1040) @[lib.scala 104:78] + node _T_1042 = mux(_T_1038, UInt<1>("h01"), _T_1041) @[lib.scala 104:23] + _T_930[15] <= _T_1042 @[lib.scala 104:17] + node _T_1043 = bits(io.trigger_pkt_any[3].tdata2, 15, 0) @[lib.scala 104:28] + node _T_1044 = andr(_T_1043) @[lib.scala 104:36] + node _T_1045 = and(_T_1044, _T_933) @[lib.scala 104:41] + node _T_1046 = bits(io.trigger_pkt_any[3].tdata2, 16, 16) @[lib.scala 104:74] + node _T_1047 = bits(dec_i0_match_data[3], 16, 16) @[lib.scala 104:86] + node _T_1048 = eq(_T_1046, _T_1047) @[lib.scala 104:78] + node _T_1049 = mux(_T_1045, UInt<1>("h01"), _T_1048) @[lib.scala 104:23] + _T_930[16] <= _T_1049 @[lib.scala 104:17] + node _T_1050 = bits(io.trigger_pkt_any[3].tdata2, 16, 0) @[lib.scala 104:28] + node _T_1051 = andr(_T_1050) @[lib.scala 104:36] + node _T_1052 = and(_T_1051, _T_933) @[lib.scala 104:41] + node _T_1053 = bits(io.trigger_pkt_any[3].tdata2, 17, 17) @[lib.scala 104:74] + node _T_1054 = bits(dec_i0_match_data[3], 17, 17) @[lib.scala 104:86] + node _T_1055 = eq(_T_1053, _T_1054) @[lib.scala 104:78] + node _T_1056 = mux(_T_1052, UInt<1>("h01"), _T_1055) @[lib.scala 104:23] + _T_930[17] <= _T_1056 @[lib.scala 104:17] + node _T_1057 = bits(io.trigger_pkt_any[3].tdata2, 17, 0) @[lib.scala 104:28] + node _T_1058 = andr(_T_1057) @[lib.scala 104:36] + node _T_1059 = and(_T_1058, _T_933) @[lib.scala 104:41] + node _T_1060 = bits(io.trigger_pkt_any[3].tdata2, 18, 18) @[lib.scala 104:74] + node _T_1061 = bits(dec_i0_match_data[3], 18, 18) @[lib.scala 104:86] + node _T_1062 = eq(_T_1060, _T_1061) @[lib.scala 104:78] + node _T_1063 = mux(_T_1059, UInt<1>("h01"), _T_1062) @[lib.scala 104:23] + _T_930[18] <= _T_1063 @[lib.scala 104:17] + node _T_1064 = bits(io.trigger_pkt_any[3].tdata2, 18, 0) @[lib.scala 104:28] + node _T_1065 = andr(_T_1064) @[lib.scala 104:36] + node _T_1066 = and(_T_1065, _T_933) @[lib.scala 104:41] + node _T_1067 = bits(io.trigger_pkt_any[3].tdata2, 19, 19) @[lib.scala 104:74] + node _T_1068 = bits(dec_i0_match_data[3], 19, 19) @[lib.scala 104:86] + node _T_1069 = eq(_T_1067, _T_1068) @[lib.scala 104:78] + node _T_1070 = mux(_T_1066, UInt<1>("h01"), _T_1069) @[lib.scala 104:23] + _T_930[19] <= _T_1070 @[lib.scala 104:17] + node _T_1071 = bits(io.trigger_pkt_any[3].tdata2, 19, 0) @[lib.scala 104:28] + node _T_1072 = andr(_T_1071) @[lib.scala 104:36] + node _T_1073 = and(_T_1072, _T_933) @[lib.scala 104:41] + node _T_1074 = bits(io.trigger_pkt_any[3].tdata2, 20, 20) @[lib.scala 104:74] + node _T_1075 = bits(dec_i0_match_data[3], 20, 20) @[lib.scala 104:86] + node _T_1076 = eq(_T_1074, _T_1075) @[lib.scala 104:78] + node _T_1077 = mux(_T_1073, UInt<1>("h01"), _T_1076) @[lib.scala 104:23] + _T_930[20] <= _T_1077 @[lib.scala 104:17] + node _T_1078 = bits(io.trigger_pkt_any[3].tdata2, 20, 0) @[lib.scala 104:28] + node _T_1079 = andr(_T_1078) @[lib.scala 104:36] + node _T_1080 = and(_T_1079, _T_933) @[lib.scala 104:41] + node _T_1081 = bits(io.trigger_pkt_any[3].tdata2, 21, 21) @[lib.scala 104:74] + node _T_1082 = bits(dec_i0_match_data[3], 21, 21) @[lib.scala 104:86] + node _T_1083 = eq(_T_1081, _T_1082) @[lib.scala 104:78] + node _T_1084 = mux(_T_1080, UInt<1>("h01"), _T_1083) @[lib.scala 104:23] + _T_930[21] <= _T_1084 @[lib.scala 104:17] + node _T_1085 = bits(io.trigger_pkt_any[3].tdata2, 21, 0) @[lib.scala 104:28] + node _T_1086 = andr(_T_1085) @[lib.scala 104:36] + node _T_1087 = and(_T_1086, _T_933) @[lib.scala 104:41] + node _T_1088 = bits(io.trigger_pkt_any[3].tdata2, 22, 22) @[lib.scala 104:74] + node _T_1089 = bits(dec_i0_match_data[3], 22, 22) @[lib.scala 104:86] + node _T_1090 = eq(_T_1088, _T_1089) @[lib.scala 104:78] + node _T_1091 = mux(_T_1087, UInt<1>("h01"), _T_1090) @[lib.scala 104:23] + _T_930[22] <= _T_1091 @[lib.scala 104:17] + node _T_1092 = bits(io.trigger_pkt_any[3].tdata2, 22, 0) @[lib.scala 104:28] + node _T_1093 = andr(_T_1092) @[lib.scala 104:36] + node _T_1094 = and(_T_1093, _T_933) @[lib.scala 104:41] + node _T_1095 = bits(io.trigger_pkt_any[3].tdata2, 23, 23) @[lib.scala 104:74] + node _T_1096 = bits(dec_i0_match_data[3], 23, 23) @[lib.scala 104:86] + node _T_1097 = eq(_T_1095, _T_1096) @[lib.scala 104:78] + node _T_1098 = mux(_T_1094, UInt<1>("h01"), _T_1097) @[lib.scala 104:23] + _T_930[23] <= _T_1098 @[lib.scala 104:17] + node _T_1099 = bits(io.trigger_pkt_any[3].tdata2, 23, 0) @[lib.scala 104:28] + node _T_1100 = andr(_T_1099) @[lib.scala 104:36] + node _T_1101 = and(_T_1100, _T_933) @[lib.scala 104:41] + node _T_1102 = bits(io.trigger_pkt_any[3].tdata2, 24, 24) @[lib.scala 104:74] + node _T_1103 = bits(dec_i0_match_data[3], 24, 24) @[lib.scala 104:86] + node _T_1104 = eq(_T_1102, _T_1103) @[lib.scala 104:78] + node _T_1105 = mux(_T_1101, UInt<1>("h01"), _T_1104) @[lib.scala 104:23] + _T_930[24] <= _T_1105 @[lib.scala 104:17] + node _T_1106 = bits(io.trigger_pkt_any[3].tdata2, 24, 0) @[lib.scala 104:28] + node _T_1107 = andr(_T_1106) @[lib.scala 104:36] + node _T_1108 = and(_T_1107, _T_933) @[lib.scala 104:41] + node _T_1109 = bits(io.trigger_pkt_any[3].tdata2, 25, 25) @[lib.scala 104:74] + node _T_1110 = bits(dec_i0_match_data[3], 25, 25) @[lib.scala 104:86] + node _T_1111 = eq(_T_1109, _T_1110) @[lib.scala 104:78] + node _T_1112 = mux(_T_1108, UInt<1>("h01"), _T_1111) @[lib.scala 104:23] + _T_930[25] <= _T_1112 @[lib.scala 104:17] + node _T_1113 = bits(io.trigger_pkt_any[3].tdata2, 25, 0) @[lib.scala 104:28] + node _T_1114 = andr(_T_1113) @[lib.scala 104:36] + node _T_1115 = and(_T_1114, _T_933) @[lib.scala 104:41] + node _T_1116 = bits(io.trigger_pkt_any[3].tdata2, 26, 26) @[lib.scala 104:74] + node _T_1117 = bits(dec_i0_match_data[3], 26, 26) @[lib.scala 104:86] + node _T_1118 = eq(_T_1116, _T_1117) @[lib.scala 104:78] + node _T_1119 = mux(_T_1115, UInt<1>("h01"), _T_1118) @[lib.scala 104:23] + _T_930[26] <= _T_1119 @[lib.scala 104:17] + node _T_1120 = bits(io.trigger_pkt_any[3].tdata2, 26, 0) @[lib.scala 104:28] + node _T_1121 = andr(_T_1120) @[lib.scala 104:36] + node _T_1122 = and(_T_1121, _T_933) @[lib.scala 104:41] + node _T_1123 = bits(io.trigger_pkt_any[3].tdata2, 27, 27) @[lib.scala 104:74] + node _T_1124 = bits(dec_i0_match_data[3], 27, 27) @[lib.scala 104:86] + node _T_1125 = eq(_T_1123, _T_1124) @[lib.scala 104:78] + node _T_1126 = mux(_T_1122, UInt<1>("h01"), _T_1125) @[lib.scala 104:23] + _T_930[27] <= _T_1126 @[lib.scala 104:17] + node _T_1127 = bits(io.trigger_pkt_any[3].tdata2, 27, 0) @[lib.scala 104:28] + node _T_1128 = andr(_T_1127) @[lib.scala 104:36] + node _T_1129 = and(_T_1128, _T_933) @[lib.scala 104:41] + node _T_1130 = bits(io.trigger_pkt_any[3].tdata2, 28, 28) @[lib.scala 104:74] + node _T_1131 = bits(dec_i0_match_data[3], 28, 28) @[lib.scala 104:86] + node _T_1132 = eq(_T_1130, _T_1131) @[lib.scala 104:78] + node _T_1133 = mux(_T_1129, UInt<1>("h01"), _T_1132) @[lib.scala 104:23] + _T_930[28] <= _T_1133 @[lib.scala 104:17] + node _T_1134 = bits(io.trigger_pkt_any[3].tdata2, 28, 0) @[lib.scala 104:28] + node _T_1135 = andr(_T_1134) @[lib.scala 104:36] + node _T_1136 = and(_T_1135, _T_933) @[lib.scala 104:41] + node _T_1137 = bits(io.trigger_pkt_any[3].tdata2, 29, 29) @[lib.scala 104:74] + node _T_1138 = bits(dec_i0_match_data[3], 29, 29) @[lib.scala 104:86] + node _T_1139 = eq(_T_1137, _T_1138) @[lib.scala 104:78] + node _T_1140 = mux(_T_1136, UInt<1>("h01"), _T_1139) @[lib.scala 104:23] + _T_930[29] <= _T_1140 @[lib.scala 104:17] + node _T_1141 = bits(io.trigger_pkt_any[3].tdata2, 29, 0) @[lib.scala 104:28] + node _T_1142 = andr(_T_1141) @[lib.scala 104:36] + node _T_1143 = and(_T_1142, _T_933) @[lib.scala 104:41] + node _T_1144 = bits(io.trigger_pkt_any[3].tdata2, 30, 30) @[lib.scala 104:74] + node _T_1145 = bits(dec_i0_match_data[3], 30, 30) @[lib.scala 104:86] + node _T_1146 = eq(_T_1144, _T_1145) @[lib.scala 104:78] + node _T_1147 = mux(_T_1143, UInt<1>("h01"), _T_1146) @[lib.scala 104:23] + _T_930[30] <= _T_1147 @[lib.scala 104:17] + node _T_1148 = bits(io.trigger_pkt_any[3].tdata2, 30, 0) @[lib.scala 104:28] + node _T_1149 = andr(_T_1148) @[lib.scala 104:36] + node _T_1150 = and(_T_1149, _T_933) @[lib.scala 104:41] + node _T_1151 = bits(io.trigger_pkt_any[3].tdata2, 31, 31) @[lib.scala 104:74] + node _T_1152 = bits(dec_i0_match_data[3], 31, 31) @[lib.scala 104:86] + node _T_1153 = eq(_T_1151, _T_1152) @[lib.scala 104:78] + node _T_1154 = mux(_T_1150, UInt<1>("h01"), _T_1153) @[lib.scala 104:23] + _T_930[31] <= _T_1154 @[lib.scala 104:17] + node _T_1155 = cat(_T_930[1], _T_930[0]) @[lib.scala 105:14] + node _T_1156 = cat(_T_930[3], _T_930[2]) @[lib.scala 105:14] + node _T_1157 = cat(_T_1156, _T_1155) @[lib.scala 105:14] + node _T_1158 = cat(_T_930[5], _T_930[4]) @[lib.scala 105:14] + node _T_1159 = cat(_T_930[7], _T_930[6]) @[lib.scala 105:14] + node _T_1160 = cat(_T_1159, _T_1158) @[lib.scala 105:14] + node _T_1161 = cat(_T_1160, _T_1157) @[lib.scala 105:14] + node _T_1162 = cat(_T_930[9], _T_930[8]) @[lib.scala 105:14] + node _T_1163 = cat(_T_930[11], _T_930[10]) @[lib.scala 105:14] + node _T_1164 = cat(_T_1163, _T_1162) @[lib.scala 105:14] + node _T_1165 = cat(_T_930[13], _T_930[12]) @[lib.scala 105:14] + node _T_1166 = cat(_T_930[15], _T_930[14]) @[lib.scala 105:14] + node _T_1167 = cat(_T_1166, _T_1165) @[lib.scala 105:14] + node _T_1168 = cat(_T_1167, _T_1164) @[lib.scala 105:14] + node _T_1169 = cat(_T_1168, _T_1161) @[lib.scala 105:14] + node _T_1170 = cat(_T_930[17], _T_930[16]) @[lib.scala 105:14] + node _T_1171 = cat(_T_930[19], _T_930[18]) @[lib.scala 105:14] + node _T_1172 = cat(_T_1171, _T_1170) @[lib.scala 105:14] + node _T_1173 = cat(_T_930[21], _T_930[20]) @[lib.scala 105:14] + node _T_1174 = cat(_T_930[23], _T_930[22]) @[lib.scala 105:14] + node _T_1175 = cat(_T_1174, _T_1173) @[lib.scala 105:14] + node _T_1176 = cat(_T_1175, _T_1172) @[lib.scala 105:14] + node _T_1177 = cat(_T_930[25], _T_930[24]) @[lib.scala 105:14] + node _T_1178 = cat(_T_930[27], _T_930[26]) @[lib.scala 105:14] + node _T_1179 = cat(_T_1178, _T_1177) @[lib.scala 105:14] + node _T_1180 = cat(_T_930[29], _T_930[28]) @[lib.scala 105:14] + node _T_1181 = cat(_T_930[31], _T_930[30]) @[lib.scala 105:14] + node _T_1182 = cat(_T_1181, _T_1180) @[lib.scala 105:14] + node _T_1183 = cat(_T_1182, _T_1179) @[lib.scala 105:14] + node _T_1184 = cat(_T_1183, _T_1176) @[lib.scala 105:14] + node _T_1185 = cat(_T_1184, _T_1169) @[lib.scala 105:14] + node _T_1186 = andr(_T_1185) @[lib.scala 105:25] node _T_1187 = and(_T_928, _T_1186) @[dec_trigger.scala 15:109] node _T_1188 = cat(_T_1187, _T_927) @[Cat.scala 29:58] node _T_1189 = cat(_T_1188, _T_667) @[Cat.scala 29:58] @@ -81669,15 +81661,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_755 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_755 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_756 : output Q : Clock @@ -81693,15 +81685,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_756 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_756 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_757 : output Q : Clock @@ -81717,15 +81709,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_757 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_757 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_758 : output Q : Clock @@ -81741,15 +81733,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_758 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_758 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_759 : output Q : Clock @@ -81765,15 +81757,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_759 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_759 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_760 : output Q : Clock @@ -81789,15 +81781,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_760 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_760 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_761 : output Q : Clock @@ -81813,15 +81805,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_761 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_761 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_762 : output Q : Clock @@ -81837,15 +81829,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_762 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_762 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] module dbg : input clock : Clock @@ -81917,18 +81909,18 @@ circuit quasar_wrapper : node _T_5 = neq(sb_state, UInt<4>("h00")) @[dbg.scala 96:63] node _T_6 = or(_T_4, _T_5) @[dbg.scala 96:51] node sb_free_clken = or(_T_6, io.clk_override) @[dbg.scala 96:86] - inst rvclkhdr of rvclkhdr_755 @[el2_lib.scala 483:22] + inst rvclkhdr of rvclkhdr_755 @[lib.scala 343:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr.io.en <= dbg_free_clken @[el2_lib.scala 485:16] - rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - inst rvclkhdr_1 of rvclkhdr_756 @[el2_lib.scala 483:22] + rvclkhdr.io.clk <= clock @[lib.scala 344:17] + rvclkhdr.io.en <= dbg_free_clken @[lib.scala 345:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + inst rvclkhdr_1 of rvclkhdr_756 @[lib.scala 343:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_1.io.en <= sb_free_clken @[el2_lib.scala 485:16] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_1.io.en <= sb_free_clken @[lib.scala 345:16] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] node _T_7 = bits(io.dbg_rst_l, 0, 0) @[dbg.scala 100:42] node _T_8 = bits(dmcontrol_reg, 0, 0) @[dbg.scala 100:61] node _T_9 = or(_T_8, io.scan_mode) @[dbg.scala 100:65] @@ -82065,22 +82057,22 @@ circuit quasar_wrapper : node _T_103 = bits(sb_bus_rdata, 63, 32) @[dbg.scala 150:47] node _T_104 = and(_T_102, _T_103) @[dbg.scala 150:33] node sbdata1_din = or(_T_100, _T_104) @[dbg.scala 149:68] - inst rvclkhdr_2 of rvclkhdr_757 @[el2_lib.scala 508:23] + inst rvclkhdr_2 of rvclkhdr_757 @[lib.scala 368:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= dbg_dm_rst_l - rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_2.io.en <= sbdata0_reg_wren @[el2_lib.scala 511:17] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg sbdata0_reg : UInt, rvclkhdr_2.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[el2_lib.scala 514:16] - sbdata0_reg <= sbdata0_din @[el2_lib.scala 514:16] - inst rvclkhdr_3 of rvclkhdr_758 @[el2_lib.scala 508:23] + rvclkhdr_2.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_2.io.en <= sbdata0_reg_wren @[lib.scala 371:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg sbdata0_reg : UInt, rvclkhdr_2.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[lib.scala 374:16] + sbdata0_reg <= sbdata0_din @[lib.scala 374:16] + inst rvclkhdr_3 of rvclkhdr_758 @[lib.scala 368:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= dbg_dm_rst_l - rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_3.io.en <= sbdata1_reg_wren @[el2_lib.scala 511:17] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg sbdata1_reg : UInt, rvclkhdr_3.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[el2_lib.scala 514:16] - sbdata1_reg <= sbdata1_din @[el2_lib.scala 514:16] + rvclkhdr_3.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_3.io.en <= sbdata1_reg_wren @[lib.scala 371:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg sbdata1_reg : UInt, rvclkhdr_3.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[lib.scala 374:16] + sbdata1_reg <= sbdata1_din @[lib.scala 374:16] node _T_105 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 160:44] node _T_106 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 160:82] node sbaddress0_reg_wren0 = and(_T_105, _T_106) @[dbg.scala 160:63] @@ -82095,14 +82087,14 @@ circuit quasar_wrapper : node _T_114 = tail(_T_113, 1) @[dbg.scala 163:54] node _T_115 = and(_T_111, _T_114) @[dbg.scala 163:36] node sbaddress0_reg_din = or(_T_109, _T_115) @[dbg.scala 162:78] - inst rvclkhdr_4 of rvclkhdr_759 @[el2_lib.scala 508:23] + inst rvclkhdr_4 of rvclkhdr_759 @[lib.scala 368:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= dbg_dm_rst_l - rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_4.io.en <= sbaddress0_reg_wren @[el2_lib.scala 511:17] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_116 : UInt, rvclkhdr_4.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_116 <= sbaddress0_reg_din @[el2_lib.scala 514:16] + rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_4.io.en <= sbaddress0_reg_wren @[lib.scala 371:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_116 : UInt, rvclkhdr_4.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[lib.scala 374:16] + _T_116 <= sbaddress0_reg_din @[lib.scala 374:16] sbaddress0_reg <= _T_116 @[dbg.scala 164:18] node _T_117 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 168:43] node _T_118 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 168:81] @@ -82316,14 +82308,14 @@ circuit quasar_wrapper : node _T_275 = cat(_T_271, UInt<1>("h00")) @[Cat.scala 29:58] node _T_276 = cat(_T_275, _T_272) @[Cat.scala 29:58] node command_din = cat(_T_276, _T_274) @[Cat.scala 29:58] - inst rvclkhdr_5 of rvclkhdr_760 @[el2_lib.scala 508:23] + inst rvclkhdr_5 of rvclkhdr_760 @[lib.scala 368:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= dbg_dm_rst_l - rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_5.io.en <= command_wren @[el2_lib.scala 511:17] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg command_reg : UInt, rvclkhdr_5.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[el2_lib.scala 514:16] - command_reg <= command_din @[el2_lib.scala 514:16] + rvclkhdr_5.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_5.io.en <= command_wren @[lib.scala 371:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg command_reg : UInt, rvclkhdr_5.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[lib.scala 374:16] + command_reg <= command_din @[lib.scala 374:16] node _T_277 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 246:39] node _T_278 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 246:77] node _T_279 = and(_T_277, _T_278) @[dbg.scala 246:58] @@ -82342,14 +82334,14 @@ circuit quasar_wrapper : node _T_289 = mux(_T_288, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] node _T_290 = and(_T_289, io.core_dbg_rddata) @[dbg.scala 250:92] node data0_din = or(_T_287, _T_290) @[dbg.scala 250:64] - inst rvclkhdr_6 of rvclkhdr_761 @[el2_lib.scala 508:23] + inst rvclkhdr_6 of rvclkhdr_761 @[lib.scala 368:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= dbg_dm_rst_l - rvclkhdr_6.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_6.io.en <= data0_reg_wren @[el2_lib.scala 511:17] - rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg data0_reg : UInt, rvclkhdr_6.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[el2_lib.scala 514:16] - data0_reg <= data0_din @[el2_lib.scala 514:16] + rvclkhdr_6.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_6.io.en <= data0_reg_wren @[lib.scala 371:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg data0_reg : UInt, rvclkhdr_6.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[lib.scala 374:16] + data0_reg <= data0_din @[lib.scala 374:16] node _T_291 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 255:39] node _T_292 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[dbg.scala 255:77] node _T_293 = and(_T_291, _T_292) @[dbg.scala 255:58] @@ -82358,14 +82350,14 @@ circuit quasar_wrapper : node _T_295 = bits(data1_reg_wren, 0, 0) @[Bitwise.scala 72:15] node _T_296 = mux(_T_295, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] node data1_din = and(_T_296, io.dmi_reg_wdata) @[dbg.scala 256:44] - inst rvclkhdr_7 of rvclkhdr_762 @[el2_lib.scala 508:23] + inst rvclkhdr_7 of rvclkhdr_762 @[lib.scala 368:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= dbg_dm_rst_l - rvclkhdr_7.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_7.io.en <= data1_reg_wren @[el2_lib.scala 511:17] - rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_297 : UInt, rvclkhdr_7.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_297 <= data1_din @[el2_lib.scala 514:16] + rvclkhdr_7.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_7.io.en <= data1_reg_wren @[lib.scala 371:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_297 : UInt, rvclkhdr_7.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[lib.scala 374:16] + _T_297 <= data1_din @[lib.scala 374:16] data1_reg <= _T_297 @[dbg.scala 257:13] wire dbg_nxtstate : UInt<3> dbg_nxtstate <= UInt<3>("h00") @@ -82947,15 +82939,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_763 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_763 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_764 : output Q : Clock @@ -82971,15 +82963,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_764 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_764 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_765 : output Q : Clock @@ -82995,15 +82987,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_765 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_765 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_766 : output Q : Clock @@ -83019,15 +83011,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_766 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_766 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_767 : output Q : Clock @@ -83043,15 +83035,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_767 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_767 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_768 : output Q : Clock @@ -83067,15 +83059,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_768 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_768 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_769 : output Q : Clock @@ -83091,15 +83083,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_769 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_769 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_770 : output Q : Clock @@ -83115,15 +83107,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_770 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_770 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_771 : output Q : Clock @@ -83139,15 +83131,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_771 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_771 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_772 : output Q : Clock @@ -83163,15 +83155,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_772 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_772 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_773 : output Q : Clock @@ -83187,15 +83179,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_773 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_773 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_774 : output Q : Clock @@ -83211,15 +83203,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_774 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_774 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_775 : output Q : Clock @@ -83235,15 +83227,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_775 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_775 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_776 : output Q : Clock @@ -83259,15 +83251,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_776 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_776 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_777 : output Q : Clock @@ -83283,15 +83275,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_777 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_777 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_778 : output Q : Clock @@ -83307,15 +83299,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_778 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_778 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_779 : output Q : Clock @@ -83331,15 +83323,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_779 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_779 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_780 : output Q : Clock @@ -83355,15 +83347,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_780 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_780 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_781 : output Q : Clock @@ -83379,15 +83371,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_781 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_781 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_782 : output Q : Clock @@ -83403,15 +83395,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_782 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_782 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] module exu_alu_ctl : input clock : Clock @@ -83419,26 +83411,26 @@ circuit quasar_wrapper : output io : {dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, flip dec_i0_pc_d : UInt<31>, flip scan_mode : UInt<1>, flip flush_upper_x : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip enable : UInt<1>, flip i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip a_in : SInt<32>, flip b_in : UInt<32>, flip pp_in : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, result_ff : UInt<32>, flush_upper_out : UInt<1>, flush_final_out : UInt<1>, flush_path_out : UInt<31>, pred_correct_out : UInt<1>, predict_p_out : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}} node _T = bits(io.scan_mode, 0, 0) @[exu_alu_ctl.scala 30:80] - inst rvclkhdr of rvclkhdr_781 @[el2_lib.scala 508:23] + inst rvclkhdr of rvclkhdr_781 @[lib.scala 368:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr.io.en <= io.enable @[el2_lib.scala 511:17] - rvclkhdr.io.scan_mode <= _T @[el2_lib.scala 512:24] - reg _T_1 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_1 <= io.dec_i0_pc_d @[el2_lib.scala 514:16] + rvclkhdr.io.clk <= clock @[lib.scala 370:18] + rvclkhdr.io.en <= io.enable @[lib.scala 371:17] + rvclkhdr.io.scan_mode <= _T @[lib.scala 372:24] + reg _T_1 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1 <= io.dec_i0_pc_d @[lib.scala 374:16] io.dec_alu.exu_i0_pc_x <= _T_1 @[exu_alu_ctl.scala 30:26] wire result : UInt<32> result <= UInt<1>("h00") node _T_2 = bits(io.scan_mode, 0, 0) @[exu_alu_ctl.scala 32:62] - inst rvclkhdr_1 of rvclkhdr_782 @[el2_lib.scala 508:23] + inst rvclkhdr_1 of rvclkhdr_782 @[lib.scala 368:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_1.io.en <= io.enable @[el2_lib.scala 511:17] - rvclkhdr_1.io.scan_mode <= _T_2 @[el2_lib.scala 512:24] - reg _T_3 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_3 <= result @[el2_lib.scala 514:16] + rvclkhdr_1.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_1.io.en <= io.enable @[lib.scala 371:17] + rvclkhdr_1.io.scan_mode <= _T_2 @[lib.scala 372:24] + reg _T_3 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_3 <= result @[lib.scala 374:16] io.result_ff <= _T_3 @[exu_alu_ctl.scala 32:16] node _T_4 = bits(io.i0_ap.sub, 0, 0) @[exu_alu_ctl.scala 34:32] node _T_5 = not(io.b_in) @[exu_alu_ctl.scala 34:40] @@ -83555,12 +83547,12 @@ circuit quasar_wrapper : shift_amount <= _T_97 @[Mux.scala 27:72] wire shift_mask : UInt<32> shift_mask <= UInt<1>("h00") - wire _T_98 : UInt<1>[5] @[el2_lib.scala 162:48] - _T_98[0] <= io.i0_ap.sll @[el2_lib.scala 162:48] - _T_98[1] <= io.i0_ap.sll @[el2_lib.scala 162:48] - _T_98[2] <= io.i0_ap.sll @[el2_lib.scala 162:48] - _T_98[3] <= io.i0_ap.sll @[el2_lib.scala 162:48] - _T_98[4] <= io.i0_ap.sll @[el2_lib.scala 162:48] + wire _T_98 : UInt<1>[5] @[lib.scala 12:48] + _T_98[0] <= io.i0_ap.sll @[lib.scala 12:48] + _T_98[1] <= io.i0_ap.sll @[lib.scala 12:48] + _T_98[2] <= io.i0_ap.sll @[lib.scala 12:48] + _T_98[3] <= io.i0_ap.sll @[lib.scala 12:48] + _T_98[4] <= io.i0_ap.sll @[lib.scala 12:48] node _T_99 = cat(_T_98[0], _T_98[1]) @[Cat.scala 29:58] node _T_100 = cat(_T_99, _T_98[2]) @[Cat.scala 29:58] node _T_101 = cat(_T_100, _T_98[3]) @[Cat.scala 29:58] @@ -83571,38 +83563,38 @@ circuit quasar_wrapper : shift_mask <= _T_105 @[exu_alu_ctl.scala 61:14] wire shift_extend : UInt<63> shift_extend <= UInt<1>("h00") - wire _T_106 : UInt<1>[31] @[el2_lib.scala 162:48] - _T_106[0] <= io.i0_ap.sra @[el2_lib.scala 162:48] - _T_106[1] <= io.i0_ap.sra @[el2_lib.scala 162:48] - _T_106[2] <= io.i0_ap.sra @[el2_lib.scala 162:48] - _T_106[3] <= io.i0_ap.sra @[el2_lib.scala 162:48] - _T_106[4] <= io.i0_ap.sra @[el2_lib.scala 162:48] - _T_106[5] <= io.i0_ap.sra @[el2_lib.scala 162:48] - _T_106[6] <= io.i0_ap.sra @[el2_lib.scala 162:48] - _T_106[7] <= io.i0_ap.sra @[el2_lib.scala 162:48] - _T_106[8] <= io.i0_ap.sra @[el2_lib.scala 162:48] - _T_106[9] <= io.i0_ap.sra @[el2_lib.scala 162:48] - _T_106[10] <= io.i0_ap.sra @[el2_lib.scala 162:48] - _T_106[11] <= io.i0_ap.sra @[el2_lib.scala 162:48] - _T_106[12] <= io.i0_ap.sra @[el2_lib.scala 162:48] - _T_106[13] <= io.i0_ap.sra @[el2_lib.scala 162:48] - _T_106[14] <= io.i0_ap.sra @[el2_lib.scala 162:48] - _T_106[15] <= io.i0_ap.sra @[el2_lib.scala 162:48] - _T_106[16] <= io.i0_ap.sra @[el2_lib.scala 162:48] - _T_106[17] <= io.i0_ap.sra @[el2_lib.scala 162:48] - _T_106[18] <= io.i0_ap.sra @[el2_lib.scala 162:48] - _T_106[19] <= io.i0_ap.sra @[el2_lib.scala 162:48] - _T_106[20] <= io.i0_ap.sra @[el2_lib.scala 162:48] - _T_106[21] <= io.i0_ap.sra @[el2_lib.scala 162:48] - _T_106[22] <= io.i0_ap.sra @[el2_lib.scala 162:48] - _T_106[23] <= io.i0_ap.sra @[el2_lib.scala 162:48] - _T_106[24] <= io.i0_ap.sra @[el2_lib.scala 162:48] - _T_106[25] <= io.i0_ap.sra @[el2_lib.scala 162:48] - _T_106[26] <= io.i0_ap.sra @[el2_lib.scala 162:48] - _T_106[27] <= io.i0_ap.sra @[el2_lib.scala 162:48] - _T_106[28] <= io.i0_ap.sra @[el2_lib.scala 162:48] - _T_106[29] <= io.i0_ap.sra @[el2_lib.scala 162:48] - _T_106[30] <= io.i0_ap.sra @[el2_lib.scala 162:48] + wire _T_106 : UInt<1>[31] @[lib.scala 12:48] + _T_106[0] <= io.i0_ap.sra @[lib.scala 12:48] + _T_106[1] <= io.i0_ap.sra @[lib.scala 12:48] + _T_106[2] <= io.i0_ap.sra @[lib.scala 12:48] + _T_106[3] <= io.i0_ap.sra @[lib.scala 12:48] + _T_106[4] <= io.i0_ap.sra @[lib.scala 12:48] + _T_106[5] <= io.i0_ap.sra @[lib.scala 12:48] + _T_106[6] <= io.i0_ap.sra @[lib.scala 12:48] + _T_106[7] <= io.i0_ap.sra @[lib.scala 12:48] + _T_106[8] <= io.i0_ap.sra @[lib.scala 12:48] + _T_106[9] <= io.i0_ap.sra @[lib.scala 12:48] + _T_106[10] <= io.i0_ap.sra @[lib.scala 12:48] + _T_106[11] <= io.i0_ap.sra @[lib.scala 12:48] + _T_106[12] <= io.i0_ap.sra @[lib.scala 12:48] + _T_106[13] <= io.i0_ap.sra @[lib.scala 12:48] + _T_106[14] <= io.i0_ap.sra @[lib.scala 12:48] + _T_106[15] <= io.i0_ap.sra @[lib.scala 12:48] + _T_106[16] <= io.i0_ap.sra @[lib.scala 12:48] + _T_106[17] <= io.i0_ap.sra @[lib.scala 12:48] + _T_106[18] <= io.i0_ap.sra @[lib.scala 12:48] + _T_106[19] <= io.i0_ap.sra @[lib.scala 12:48] + _T_106[20] <= io.i0_ap.sra @[lib.scala 12:48] + _T_106[21] <= io.i0_ap.sra @[lib.scala 12:48] + _T_106[22] <= io.i0_ap.sra @[lib.scala 12:48] + _T_106[23] <= io.i0_ap.sra @[lib.scala 12:48] + _T_106[24] <= io.i0_ap.sra @[lib.scala 12:48] + _T_106[25] <= io.i0_ap.sra @[lib.scala 12:48] + _T_106[26] <= io.i0_ap.sra @[lib.scala 12:48] + _T_106[27] <= io.i0_ap.sra @[lib.scala 12:48] + _T_106[28] <= io.i0_ap.sra @[lib.scala 12:48] + _T_106[29] <= io.i0_ap.sra @[lib.scala 12:48] + _T_106[30] <= io.i0_ap.sra @[lib.scala 12:48] node _T_107 = cat(_T_106[0], _T_106[1]) @[Cat.scala 29:58] node _T_108 = cat(_T_107, _T_106[2]) @[Cat.scala 29:58] node _T_109 = cat(_T_108, _T_106[3]) @[Cat.scala 29:58] @@ -83634,38 +83626,38 @@ circuit quasar_wrapper : node _T_135 = cat(_T_134, _T_106[29]) @[Cat.scala 29:58] node _T_136 = cat(_T_135, _T_106[30]) @[Cat.scala 29:58] node _T_137 = bits(io.a_in, 31, 31) @[exu_alu_ctl.scala 64:64] - wire _T_138 : UInt<1>[31] @[el2_lib.scala 162:48] - _T_138[0] <= _T_137 @[el2_lib.scala 162:48] - _T_138[1] <= _T_137 @[el2_lib.scala 162:48] - _T_138[2] <= _T_137 @[el2_lib.scala 162:48] - _T_138[3] <= _T_137 @[el2_lib.scala 162:48] - _T_138[4] <= _T_137 @[el2_lib.scala 162:48] - _T_138[5] <= _T_137 @[el2_lib.scala 162:48] - _T_138[6] <= _T_137 @[el2_lib.scala 162:48] - _T_138[7] <= _T_137 @[el2_lib.scala 162:48] - _T_138[8] <= _T_137 @[el2_lib.scala 162:48] - _T_138[9] <= _T_137 @[el2_lib.scala 162:48] - _T_138[10] <= _T_137 @[el2_lib.scala 162:48] - _T_138[11] <= _T_137 @[el2_lib.scala 162:48] - _T_138[12] <= _T_137 @[el2_lib.scala 162:48] - _T_138[13] <= _T_137 @[el2_lib.scala 162:48] - _T_138[14] <= _T_137 @[el2_lib.scala 162:48] - _T_138[15] <= _T_137 @[el2_lib.scala 162:48] - _T_138[16] <= _T_137 @[el2_lib.scala 162:48] - _T_138[17] <= _T_137 @[el2_lib.scala 162:48] - _T_138[18] <= _T_137 @[el2_lib.scala 162:48] - _T_138[19] <= _T_137 @[el2_lib.scala 162:48] - _T_138[20] <= _T_137 @[el2_lib.scala 162:48] - _T_138[21] <= _T_137 @[el2_lib.scala 162:48] - _T_138[22] <= _T_137 @[el2_lib.scala 162:48] - _T_138[23] <= _T_137 @[el2_lib.scala 162:48] - _T_138[24] <= _T_137 @[el2_lib.scala 162:48] - _T_138[25] <= _T_137 @[el2_lib.scala 162:48] - _T_138[26] <= _T_137 @[el2_lib.scala 162:48] - _T_138[27] <= _T_137 @[el2_lib.scala 162:48] - _T_138[28] <= _T_137 @[el2_lib.scala 162:48] - _T_138[29] <= _T_137 @[el2_lib.scala 162:48] - _T_138[30] <= _T_137 @[el2_lib.scala 162:48] + wire _T_138 : UInt<1>[31] @[lib.scala 12:48] + _T_138[0] <= _T_137 @[lib.scala 12:48] + _T_138[1] <= _T_137 @[lib.scala 12:48] + _T_138[2] <= _T_137 @[lib.scala 12:48] + _T_138[3] <= _T_137 @[lib.scala 12:48] + _T_138[4] <= _T_137 @[lib.scala 12:48] + _T_138[5] <= _T_137 @[lib.scala 12:48] + _T_138[6] <= _T_137 @[lib.scala 12:48] + _T_138[7] <= _T_137 @[lib.scala 12:48] + _T_138[8] <= _T_137 @[lib.scala 12:48] + _T_138[9] <= _T_137 @[lib.scala 12:48] + _T_138[10] <= _T_137 @[lib.scala 12:48] + _T_138[11] <= _T_137 @[lib.scala 12:48] + _T_138[12] <= _T_137 @[lib.scala 12:48] + _T_138[13] <= _T_137 @[lib.scala 12:48] + _T_138[14] <= _T_137 @[lib.scala 12:48] + _T_138[15] <= _T_137 @[lib.scala 12:48] + _T_138[16] <= _T_137 @[lib.scala 12:48] + _T_138[17] <= _T_137 @[lib.scala 12:48] + _T_138[18] <= _T_137 @[lib.scala 12:48] + _T_138[19] <= _T_137 @[lib.scala 12:48] + _T_138[20] <= _T_137 @[lib.scala 12:48] + _T_138[21] <= _T_137 @[lib.scala 12:48] + _T_138[22] <= _T_137 @[lib.scala 12:48] + _T_138[23] <= _T_137 @[lib.scala 12:48] + _T_138[24] <= _T_137 @[lib.scala 12:48] + _T_138[25] <= _T_137 @[lib.scala 12:48] + _T_138[26] <= _T_137 @[lib.scala 12:48] + _T_138[27] <= _T_137 @[lib.scala 12:48] + _T_138[28] <= _T_137 @[lib.scala 12:48] + _T_138[29] <= _T_137 @[lib.scala 12:48] + _T_138[30] <= _T_137 @[lib.scala 12:48] node _T_139 = cat(_T_138[0], _T_138[1]) @[Cat.scala 29:58] node _T_140 = cat(_T_139, _T_138[2]) @[Cat.scala 29:58] node _T_141 = cat(_T_140, _T_138[3]) @[Cat.scala 29:58] @@ -83697,38 +83689,38 @@ circuit quasar_wrapper : node _T_167 = cat(_T_166, _T_138[29]) @[Cat.scala 29:58] node _T_168 = cat(_T_167, _T_138[30]) @[Cat.scala 29:58] node _T_169 = and(_T_136, _T_168) @[exu_alu_ctl.scala 64:47] - wire _T_170 : UInt<1>[31] @[el2_lib.scala 162:48] - _T_170[0] <= io.i0_ap.sll @[el2_lib.scala 162:48] - _T_170[1] <= io.i0_ap.sll @[el2_lib.scala 162:48] - _T_170[2] <= io.i0_ap.sll @[el2_lib.scala 162:48] - _T_170[3] <= io.i0_ap.sll @[el2_lib.scala 162:48] - _T_170[4] <= io.i0_ap.sll @[el2_lib.scala 162:48] - _T_170[5] <= io.i0_ap.sll @[el2_lib.scala 162:48] - _T_170[6] <= io.i0_ap.sll @[el2_lib.scala 162:48] - _T_170[7] <= io.i0_ap.sll @[el2_lib.scala 162:48] - _T_170[8] <= io.i0_ap.sll @[el2_lib.scala 162:48] - _T_170[9] <= io.i0_ap.sll @[el2_lib.scala 162:48] - _T_170[10] <= io.i0_ap.sll @[el2_lib.scala 162:48] - _T_170[11] <= io.i0_ap.sll @[el2_lib.scala 162:48] - _T_170[12] <= io.i0_ap.sll @[el2_lib.scala 162:48] - _T_170[13] <= io.i0_ap.sll @[el2_lib.scala 162:48] - _T_170[14] <= io.i0_ap.sll @[el2_lib.scala 162:48] - _T_170[15] <= io.i0_ap.sll @[el2_lib.scala 162:48] - _T_170[16] <= io.i0_ap.sll @[el2_lib.scala 162:48] - _T_170[17] <= io.i0_ap.sll @[el2_lib.scala 162:48] - _T_170[18] <= io.i0_ap.sll @[el2_lib.scala 162:48] - _T_170[19] <= io.i0_ap.sll @[el2_lib.scala 162:48] - _T_170[20] <= io.i0_ap.sll @[el2_lib.scala 162:48] - _T_170[21] <= io.i0_ap.sll @[el2_lib.scala 162:48] - _T_170[22] <= io.i0_ap.sll @[el2_lib.scala 162:48] - _T_170[23] <= io.i0_ap.sll @[el2_lib.scala 162:48] - _T_170[24] <= io.i0_ap.sll @[el2_lib.scala 162:48] - _T_170[25] <= io.i0_ap.sll @[el2_lib.scala 162:48] - _T_170[26] <= io.i0_ap.sll @[el2_lib.scala 162:48] - _T_170[27] <= io.i0_ap.sll @[el2_lib.scala 162:48] - _T_170[28] <= io.i0_ap.sll @[el2_lib.scala 162:48] - _T_170[29] <= io.i0_ap.sll @[el2_lib.scala 162:48] - _T_170[30] <= io.i0_ap.sll @[el2_lib.scala 162:48] + wire _T_170 : UInt<1>[31] @[lib.scala 12:48] + _T_170[0] <= io.i0_ap.sll @[lib.scala 12:48] + _T_170[1] <= io.i0_ap.sll @[lib.scala 12:48] + _T_170[2] <= io.i0_ap.sll @[lib.scala 12:48] + _T_170[3] <= io.i0_ap.sll @[lib.scala 12:48] + _T_170[4] <= io.i0_ap.sll @[lib.scala 12:48] + _T_170[5] <= io.i0_ap.sll @[lib.scala 12:48] + _T_170[6] <= io.i0_ap.sll @[lib.scala 12:48] + _T_170[7] <= io.i0_ap.sll @[lib.scala 12:48] + _T_170[8] <= io.i0_ap.sll @[lib.scala 12:48] + _T_170[9] <= io.i0_ap.sll @[lib.scala 12:48] + _T_170[10] <= io.i0_ap.sll @[lib.scala 12:48] + _T_170[11] <= io.i0_ap.sll @[lib.scala 12:48] + _T_170[12] <= io.i0_ap.sll @[lib.scala 12:48] + _T_170[13] <= io.i0_ap.sll @[lib.scala 12:48] + _T_170[14] <= io.i0_ap.sll @[lib.scala 12:48] + _T_170[15] <= io.i0_ap.sll @[lib.scala 12:48] + _T_170[16] <= io.i0_ap.sll @[lib.scala 12:48] + _T_170[17] <= io.i0_ap.sll @[lib.scala 12:48] + _T_170[18] <= io.i0_ap.sll @[lib.scala 12:48] + _T_170[19] <= io.i0_ap.sll @[lib.scala 12:48] + _T_170[20] <= io.i0_ap.sll @[lib.scala 12:48] + _T_170[21] <= io.i0_ap.sll @[lib.scala 12:48] + _T_170[22] <= io.i0_ap.sll @[lib.scala 12:48] + _T_170[23] <= io.i0_ap.sll @[lib.scala 12:48] + _T_170[24] <= io.i0_ap.sll @[lib.scala 12:48] + _T_170[25] <= io.i0_ap.sll @[lib.scala 12:48] + _T_170[26] <= io.i0_ap.sll @[lib.scala 12:48] + _T_170[27] <= io.i0_ap.sll @[lib.scala 12:48] + _T_170[28] <= io.i0_ap.sll @[lib.scala 12:48] + _T_170[29] <= io.i0_ap.sll @[lib.scala 12:48] + _T_170[30] <= io.i0_ap.sll @[lib.scala 12:48] node _T_171 = cat(_T_170[0], _T_170[1]) @[Cat.scala 29:58] node _T_172 = cat(_T_171, _T_170[2]) @[Cat.scala 29:58] node _T_173 = cat(_T_172, _T_170[3]) @[Cat.scala 29:58] @@ -83787,29 +83779,29 @@ circuit quasar_wrapper : node slt_one = and(io.i0_ap.slt, lt) @[exu_alu_ctl.scala 77:43] node _T_217 = cat(io.dec_i0_pc_d, UInt<1>("h00")) @[Cat.scala 29:58] node _T_218 = cat(io.dec_alu.dec_i0_br_immed_d, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_219 = bits(_T_217, 12, 1) @[el2_lib.scala 208:24] - node _T_220 = bits(_T_218, 12, 1) @[el2_lib.scala 208:40] - node _T_221 = add(_T_219, _T_220) @[el2_lib.scala 208:31] - node _T_222 = bits(_T_217, 31, 13) @[el2_lib.scala 209:20] - node _T_223 = add(_T_222, UInt<1>("h01")) @[el2_lib.scala 209:27] - node _T_224 = tail(_T_223, 1) @[el2_lib.scala 209:27] - node _T_225 = bits(_T_217, 31, 13) @[el2_lib.scala 210:20] - node _T_226 = sub(_T_225, UInt<1>("h01")) @[el2_lib.scala 210:27] - node _T_227 = tail(_T_226, 1) @[el2_lib.scala 210:27] - node _T_228 = bits(_T_218, 12, 12) @[el2_lib.scala 211:22] - node _T_229 = bits(_T_221, 12, 12) @[el2_lib.scala 212:39] - node _T_230 = eq(_T_229, UInt<1>("h00")) @[el2_lib.scala 212:28] - node _T_231 = xor(_T_228, _T_230) @[el2_lib.scala 212:26] - node _T_232 = bits(_T_231, 0, 0) @[el2_lib.scala 212:64] - node _T_233 = bits(_T_217, 31, 13) @[el2_lib.scala 212:76] - node _T_234 = eq(_T_228, UInt<1>("h00")) @[el2_lib.scala 213:20] - node _T_235 = bits(_T_221, 12, 12) @[el2_lib.scala 213:39] - node _T_236 = and(_T_234, _T_235) @[el2_lib.scala 213:26] - node _T_237 = bits(_T_236, 0, 0) @[el2_lib.scala 213:64] - node _T_238 = bits(_T_221, 12, 12) @[el2_lib.scala 214:39] - node _T_239 = eq(_T_238, UInt<1>("h00")) @[el2_lib.scala 214:28] - node _T_240 = and(_T_228, _T_239) @[el2_lib.scala 214:26] - node _T_241 = bits(_T_240, 0, 0) @[el2_lib.scala 214:64] + node _T_219 = bits(_T_217, 12, 1) @[lib.scala 68:24] + node _T_220 = bits(_T_218, 12, 1) @[lib.scala 68:40] + node _T_221 = add(_T_219, _T_220) @[lib.scala 68:31] + node _T_222 = bits(_T_217, 31, 13) @[lib.scala 69:20] + node _T_223 = add(_T_222, UInt<1>("h01")) @[lib.scala 69:27] + node _T_224 = tail(_T_223, 1) @[lib.scala 69:27] + node _T_225 = bits(_T_217, 31, 13) @[lib.scala 70:20] + node _T_226 = sub(_T_225, UInt<1>("h01")) @[lib.scala 70:27] + node _T_227 = tail(_T_226, 1) @[lib.scala 70:27] + node _T_228 = bits(_T_218, 12, 12) @[lib.scala 71:22] + node _T_229 = bits(_T_221, 12, 12) @[lib.scala 72:39] + node _T_230 = eq(_T_229, UInt<1>("h00")) @[lib.scala 72:28] + node _T_231 = xor(_T_228, _T_230) @[lib.scala 72:26] + node _T_232 = bits(_T_231, 0, 0) @[lib.scala 72:64] + node _T_233 = bits(_T_217, 31, 13) @[lib.scala 72:76] + node _T_234 = eq(_T_228, UInt<1>("h00")) @[lib.scala 73:20] + node _T_235 = bits(_T_221, 12, 12) @[lib.scala 73:39] + node _T_236 = and(_T_234, _T_235) @[lib.scala 73:26] + node _T_237 = bits(_T_236, 0, 0) @[lib.scala 73:64] + node _T_238 = bits(_T_221, 12, 12) @[lib.scala 74:39] + node _T_239 = eq(_T_238, UInt<1>("h00")) @[lib.scala 74:28] + node _T_240 = and(_T_228, _T_239) @[lib.scala 74:26] + node _T_241 = bits(_T_240, 0, 0) @[lib.scala 74:64] node _T_242 = mux(_T_232, _T_233, UInt<1>("h00")) @[Mux.scala 27:72] node _T_243 = mux(_T_237, _T_224, UInt<1>("h00")) @[Mux.scala 27:72] node _T_244 = mux(_T_241, _T_227, UInt<1>("h00")) @[Mux.scala 27:72] @@ -83817,7 +83809,7 @@ circuit quasar_wrapper : node _T_246 = or(_T_245, _T_244) @[Mux.scala 27:72] wire _T_247 : UInt<19> @[Mux.scala 27:72] _T_247 <= _T_246 @[Mux.scala 27:72] - node _T_248 = bits(_T_221, 11, 0) @[el2_lib.scala 214:94] + node _T_248 = bits(_T_221, 11, 0) @[lib.scala 74:94] node _T_249 = cat(_T_247, _T_248) @[Cat.scala 29:58] node pcout = cat(_T_249, UInt<1>("h00")) @[Cat.scala 29:58] node _T_250 = bits(lout, 31, 0) @[exu_alu_ctl.scala 83:24] @@ -83945,15 +83937,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_783 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_783 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_784 : output Q : Clock @@ -83969,15 +83961,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_784 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_784 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_785 : output Q : Clock @@ -83993,15 +83985,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_785 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_785 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] module exu_mul_ctl : input clock : Clock @@ -84031,34 +84023,34 @@ circuit quasar_wrapper : node _T_7 = asSInt(_T_6) @[exu_mul_ctl.scala 27:71] rs2_ext_in <= _T_7 @[exu_mul_ctl.scala 27:14] node _T_8 = bits(io.mul_p.valid, 0, 0) @[exu_mul_ctl.scala 29:52] - inst rvclkhdr of rvclkhdr_783 @[el2_lib.scala 508:23] + inst rvclkhdr of rvclkhdr_783 @[lib.scala 368:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr.io.en <= _T_8 @[el2_lib.scala 511:17] - rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_9 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_9 <= io.mul_p.bits.low @[el2_lib.scala 514:16] + rvclkhdr.io.clk <= clock @[lib.scala 370:18] + rvclkhdr.io.en <= _T_8 @[lib.scala 371:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_9 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_9 <= io.mul_p.bits.low @[lib.scala 374:16] low_x <= _T_9 @[exu_mul_ctl.scala 29:9] node _T_10 = bits(io.mul_p.valid, 0, 0) @[exu_mul_ctl.scala 30:44] - inst rvclkhdr_1 of rvclkhdr_784 @[el2_lib.scala 528:23] + inst rvclkhdr_1 of rvclkhdr_784 @[lib.scala 388:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[el2_lib.scala 530:18] - rvclkhdr_1.io.en <= _T_10 @[el2_lib.scala 531:17] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 532:24] - reg _T_11 : SInt, rvclkhdr_1.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[el2_lib.scala 534:16] - _T_11 <= rs1_ext_in @[el2_lib.scala 534:16] + rvclkhdr_1.io.clk <= clock @[lib.scala 390:18] + rvclkhdr_1.io.en <= _T_10 @[lib.scala 391:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 392:24] + reg _T_11 : SInt, rvclkhdr_1.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[lib.scala 394:16] + _T_11 <= rs1_ext_in @[lib.scala 394:16] rs1_x <= _T_11 @[exu_mul_ctl.scala 30:9] node _T_12 = bits(io.mul_p.valid, 0, 0) @[exu_mul_ctl.scala 31:45] - inst rvclkhdr_2 of rvclkhdr_785 @[el2_lib.scala 528:23] + inst rvclkhdr_2 of rvclkhdr_785 @[lib.scala 388:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= clock @[el2_lib.scala 530:18] - rvclkhdr_2.io.en <= _T_12 @[el2_lib.scala 531:17] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 532:24] - reg _T_13 : SInt, rvclkhdr_2.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[el2_lib.scala 534:16] - _T_13 <= rs2_ext_in @[el2_lib.scala 534:16] + rvclkhdr_2.io.clk <= clock @[lib.scala 390:18] + rvclkhdr_2.io.en <= _T_12 @[lib.scala 391:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 392:24] + reg _T_13 : SInt, rvclkhdr_2.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[lib.scala 394:16] + _T_13 <= rs2_ext_in @[lib.scala 394:16] rs2_x <= _T_13 @[exu_mul_ctl.scala 31:9] node _T_14 = mul(rs1_x, rs2_x) @[exu_mul_ctl.scala 33:20] prod_x <= _T_14 @[exu_mul_ctl.scala 33:10] @@ -84088,15 +84080,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_786 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_786 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_787 : output Q : Clock @@ -84112,15 +84104,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_787 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_787 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_788 : output Q : Clock @@ -84136,15 +84128,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_788 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_788 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_789 : output Q : Clock @@ -84160,15 +84152,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_789 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_789 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] module exu_div_ctl : input clock : Clock @@ -85002,255 +84994,255 @@ circuit quasar_wrapper : node _T_738 = and(sign_ff, dividend_neg_ff) @[exu_div_ctl.scala 166:32] node _T_739 = bits(_T_738, 0, 0) @[exu_div_ctl.scala 166:51] node _T_740 = bits(q_ff, 31, 0) @[exu_div_ctl.scala 166:74] - wire _T_741 : UInt<1>[31] @[el2_lib.scala 541:20] - node _T_742 = bits(_T_740, 0, 0) @[el2_lib.scala 543:27] - node _T_743 = orr(_T_742) @[el2_lib.scala 543:35] - node _T_744 = bits(_T_740, 1, 1) @[el2_lib.scala 543:44] - node _T_745 = not(_T_744) @[el2_lib.scala 543:40] - node _T_746 = bits(_T_740, 1, 1) @[el2_lib.scala 543:51] - node _T_747 = mux(_T_743, _T_745, _T_746) @[el2_lib.scala 543:23] - _T_741[0] <= _T_747 @[el2_lib.scala 543:17] - node _T_748 = bits(_T_740, 1, 0) @[el2_lib.scala 543:27] - node _T_749 = orr(_T_748) @[el2_lib.scala 543:35] - node _T_750 = bits(_T_740, 2, 2) @[el2_lib.scala 543:44] - node _T_751 = not(_T_750) @[el2_lib.scala 543:40] - node _T_752 = bits(_T_740, 2, 2) @[el2_lib.scala 543:51] - node _T_753 = mux(_T_749, _T_751, _T_752) @[el2_lib.scala 543:23] - _T_741[1] <= _T_753 @[el2_lib.scala 543:17] - node _T_754 = bits(_T_740, 2, 0) @[el2_lib.scala 543:27] - node _T_755 = orr(_T_754) @[el2_lib.scala 543:35] - node _T_756 = bits(_T_740, 3, 3) @[el2_lib.scala 543:44] - node _T_757 = not(_T_756) @[el2_lib.scala 543:40] - node _T_758 = bits(_T_740, 3, 3) @[el2_lib.scala 543:51] - node _T_759 = mux(_T_755, _T_757, _T_758) @[el2_lib.scala 543:23] - _T_741[2] <= _T_759 @[el2_lib.scala 543:17] - node _T_760 = bits(_T_740, 3, 0) @[el2_lib.scala 543:27] - node _T_761 = orr(_T_760) @[el2_lib.scala 543:35] - node _T_762 = bits(_T_740, 4, 4) @[el2_lib.scala 543:44] - node _T_763 = not(_T_762) @[el2_lib.scala 543:40] - node _T_764 = bits(_T_740, 4, 4) @[el2_lib.scala 543:51] - node _T_765 = mux(_T_761, _T_763, _T_764) @[el2_lib.scala 543:23] - _T_741[3] <= _T_765 @[el2_lib.scala 543:17] - node _T_766 = bits(_T_740, 4, 0) @[el2_lib.scala 543:27] - node _T_767 = orr(_T_766) @[el2_lib.scala 543:35] - node _T_768 = bits(_T_740, 5, 5) @[el2_lib.scala 543:44] - node _T_769 = not(_T_768) @[el2_lib.scala 543:40] - node _T_770 = bits(_T_740, 5, 5) @[el2_lib.scala 543:51] - node _T_771 = mux(_T_767, _T_769, _T_770) @[el2_lib.scala 543:23] - _T_741[4] <= _T_771 @[el2_lib.scala 543:17] - node _T_772 = bits(_T_740, 5, 0) @[el2_lib.scala 543:27] - node _T_773 = orr(_T_772) @[el2_lib.scala 543:35] - node _T_774 = bits(_T_740, 6, 6) @[el2_lib.scala 543:44] - node _T_775 = not(_T_774) @[el2_lib.scala 543:40] - node _T_776 = bits(_T_740, 6, 6) @[el2_lib.scala 543:51] - node _T_777 = mux(_T_773, _T_775, _T_776) @[el2_lib.scala 543:23] - _T_741[5] <= _T_777 @[el2_lib.scala 543:17] - node _T_778 = bits(_T_740, 6, 0) @[el2_lib.scala 543:27] - node _T_779 = orr(_T_778) @[el2_lib.scala 543:35] - node _T_780 = bits(_T_740, 7, 7) @[el2_lib.scala 543:44] - node _T_781 = not(_T_780) @[el2_lib.scala 543:40] - node _T_782 = bits(_T_740, 7, 7) @[el2_lib.scala 543:51] - node _T_783 = mux(_T_779, _T_781, _T_782) @[el2_lib.scala 543:23] - _T_741[6] <= _T_783 @[el2_lib.scala 543:17] - node _T_784 = bits(_T_740, 7, 0) @[el2_lib.scala 543:27] - node _T_785 = orr(_T_784) @[el2_lib.scala 543:35] - node _T_786 = bits(_T_740, 8, 8) @[el2_lib.scala 543:44] - node _T_787 = not(_T_786) @[el2_lib.scala 543:40] - node _T_788 = bits(_T_740, 8, 8) @[el2_lib.scala 543:51] - node _T_789 = mux(_T_785, _T_787, _T_788) @[el2_lib.scala 543:23] - _T_741[7] <= _T_789 @[el2_lib.scala 543:17] - node _T_790 = bits(_T_740, 8, 0) @[el2_lib.scala 543:27] - node _T_791 = orr(_T_790) @[el2_lib.scala 543:35] - node _T_792 = bits(_T_740, 9, 9) @[el2_lib.scala 543:44] - node _T_793 = not(_T_792) @[el2_lib.scala 543:40] - node _T_794 = bits(_T_740, 9, 9) @[el2_lib.scala 543:51] - node _T_795 = mux(_T_791, _T_793, _T_794) @[el2_lib.scala 543:23] - _T_741[8] <= _T_795 @[el2_lib.scala 543:17] - node _T_796 = bits(_T_740, 9, 0) @[el2_lib.scala 543:27] - node _T_797 = orr(_T_796) @[el2_lib.scala 543:35] - node _T_798 = bits(_T_740, 10, 10) @[el2_lib.scala 543:44] - node _T_799 = not(_T_798) @[el2_lib.scala 543:40] - node _T_800 = bits(_T_740, 10, 10) @[el2_lib.scala 543:51] - node _T_801 = mux(_T_797, _T_799, _T_800) @[el2_lib.scala 543:23] - _T_741[9] <= _T_801 @[el2_lib.scala 543:17] - node _T_802 = bits(_T_740, 10, 0) @[el2_lib.scala 543:27] - node _T_803 = orr(_T_802) @[el2_lib.scala 543:35] - node _T_804 = bits(_T_740, 11, 11) @[el2_lib.scala 543:44] - node _T_805 = not(_T_804) @[el2_lib.scala 543:40] - node _T_806 = bits(_T_740, 11, 11) @[el2_lib.scala 543:51] - node _T_807 = mux(_T_803, _T_805, _T_806) @[el2_lib.scala 543:23] - _T_741[10] <= _T_807 @[el2_lib.scala 543:17] - node _T_808 = bits(_T_740, 11, 0) @[el2_lib.scala 543:27] - node _T_809 = orr(_T_808) @[el2_lib.scala 543:35] - node _T_810 = bits(_T_740, 12, 12) @[el2_lib.scala 543:44] - node _T_811 = not(_T_810) @[el2_lib.scala 543:40] - node _T_812 = bits(_T_740, 12, 12) @[el2_lib.scala 543:51] - node _T_813 = mux(_T_809, _T_811, _T_812) @[el2_lib.scala 543:23] - _T_741[11] <= _T_813 @[el2_lib.scala 543:17] - node _T_814 = bits(_T_740, 12, 0) @[el2_lib.scala 543:27] - node _T_815 = orr(_T_814) @[el2_lib.scala 543:35] - node _T_816 = bits(_T_740, 13, 13) @[el2_lib.scala 543:44] - node _T_817 = not(_T_816) @[el2_lib.scala 543:40] - node _T_818 = bits(_T_740, 13, 13) @[el2_lib.scala 543:51] - node _T_819 = mux(_T_815, _T_817, _T_818) @[el2_lib.scala 543:23] - _T_741[12] <= _T_819 @[el2_lib.scala 543:17] - node _T_820 = bits(_T_740, 13, 0) @[el2_lib.scala 543:27] - node _T_821 = orr(_T_820) @[el2_lib.scala 543:35] - node _T_822 = bits(_T_740, 14, 14) @[el2_lib.scala 543:44] - node _T_823 = not(_T_822) @[el2_lib.scala 543:40] - node _T_824 = bits(_T_740, 14, 14) @[el2_lib.scala 543:51] - node _T_825 = mux(_T_821, _T_823, _T_824) @[el2_lib.scala 543:23] - _T_741[13] <= _T_825 @[el2_lib.scala 543:17] - node _T_826 = bits(_T_740, 14, 0) @[el2_lib.scala 543:27] - node _T_827 = orr(_T_826) @[el2_lib.scala 543:35] - node _T_828 = bits(_T_740, 15, 15) @[el2_lib.scala 543:44] - node _T_829 = not(_T_828) @[el2_lib.scala 543:40] - node _T_830 = bits(_T_740, 15, 15) @[el2_lib.scala 543:51] - node _T_831 = mux(_T_827, _T_829, _T_830) @[el2_lib.scala 543:23] - _T_741[14] <= _T_831 @[el2_lib.scala 543:17] - node _T_832 = bits(_T_740, 15, 0) @[el2_lib.scala 543:27] - node _T_833 = orr(_T_832) @[el2_lib.scala 543:35] - node _T_834 = bits(_T_740, 16, 16) @[el2_lib.scala 543:44] - node _T_835 = not(_T_834) @[el2_lib.scala 543:40] - node _T_836 = bits(_T_740, 16, 16) @[el2_lib.scala 543:51] - node _T_837 = mux(_T_833, _T_835, _T_836) @[el2_lib.scala 543:23] - _T_741[15] <= _T_837 @[el2_lib.scala 543:17] - node _T_838 = bits(_T_740, 16, 0) @[el2_lib.scala 543:27] - node _T_839 = orr(_T_838) @[el2_lib.scala 543:35] - node _T_840 = bits(_T_740, 17, 17) @[el2_lib.scala 543:44] - node _T_841 = not(_T_840) @[el2_lib.scala 543:40] - node _T_842 = bits(_T_740, 17, 17) @[el2_lib.scala 543:51] - node _T_843 = mux(_T_839, _T_841, _T_842) @[el2_lib.scala 543:23] - _T_741[16] <= _T_843 @[el2_lib.scala 543:17] - node _T_844 = bits(_T_740, 17, 0) @[el2_lib.scala 543:27] - node _T_845 = orr(_T_844) @[el2_lib.scala 543:35] - node _T_846 = bits(_T_740, 18, 18) @[el2_lib.scala 543:44] - node _T_847 = not(_T_846) @[el2_lib.scala 543:40] - node _T_848 = bits(_T_740, 18, 18) @[el2_lib.scala 543:51] - node _T_849 = mux(_T_845, _T_847, _T_848) @[el2_lib.scala 543:23] - _T_741[17] <= _T_849 @[el2_lib.scala 543:17] - node _T_850 = bits(_T_740, 18, 0) @[el2_lib.scala 543:27] - node _T_851 = orr(_T_850) @[el2_lib.scala 543:35] - node _T_852 = bits(_T_740, 19, 19) @[el2_lib.scala 543:44] - node _T_853 = not(_T_852) @[el2_lib.scala 543:40] - node _T_854 = bits(_T_740, 19, 19) @[el2_lib.scala 543:51] - node _T_855 = mux(_T_851, _T_853, _T_854) @[el2_lib.scala 543:23] - _T_741[18] <= _T_855 @[el2_lib.scala 543:17] - node _T_856 = bits(_T_740, 19, 0) @[el2_lib.scala 543:27] - node _T_857 = orr(_T_856) @[el2_lib.scala 543:35] - node _T_858 = bits(_T_740, 20, 20) @[el2_lib.scala 543:44] - node _T_859 = not(_T_858) @[el2_lib.scala 543:40] - node _T_860 = bits(_T_740, 20, 20) @[el2_lib.scala 543:51] - node _T_861 = mux(_T_857, _T_859, _T_860) @[el2_lib.scala 543:23] - _T_741[19] <= _T_861 @[el2_lib.scala 543:17] - node _T_862 = bits(_T_740, 20, 0) @[el2_lib.scala 543:27] - node _T_863 = orr(_T_862) @[el2_lib.scala 543:35] - node _T_864 = bits(_T_740, 21, 21) @[el2_lib.scala 543:44] - node _T_865 = not(_T_864) @[el2_lib.scala 543:40] - node _T_866 = bits(_T_740, 21, 21) @[el2_lib.scala 543:51] - node _T_867 = mux(_T_863, _T_865, _T_866) @[el2_lib.scala 543:23] - _T_741[20] <= _T_867 @[el2_lib.scala 543:17] - node _T_868 = bits(_T_740, 21, 0) @[el2_lib.scala 543:27] - node _T_869 = orr(_T_868) @[el2_lib.scala 543:35] - node _T_870 = bits(_T_740, 22, 22) @[el2_lib.scala 543:44] - node _T_871 = not(_T_870) @[el2_lib.scala 543:40] - node _T_872 = bits(_T_740, 22, 22) @[el2_lib.scala 543:51] - node _T_873 = mux(_T_869, _T_871, _T_872) @[el2_lib.scala 543:23] - _T_741[21] <= _T_873 @[el2_lib.scala 543:17] - node _T_874 = bits(_T_740, 22, 0) @[el2_lib.scala 543:27] - node _T_875 = orr(_T_874) @[el2_lib.scala 543:35] - node _T_876 = bits(_T_740, 23, 23) @[el2_lib.scala 543:44] - node _T_877 = not(_T_876) @[el2_lib.scala 543:40] - node _T_878 = bits(_T_740, 23, 23) @[el2_lib.scala 543:51] - node _T_879 = mux(_T_875, _T_877, _T_878) @[el2_lib.scala 543:23] - _T_741[22] <= _T_879 @[el2_lib.scala 543:17] - node _T_880 = bits(_T_740, 23, 0) @[el2_lib.scala 543:27] - node _T_881 = orr(_T_880) @[el2_lib.scala 543:35] - node _T_882 = bits(_T_740, 24, 24) @[el2_lib.scala 543:44] - node _T_883 = not(_T_882) @[el2_lib.scala 543:40] - node _T_884 = bits(_T_740, 24, 24) @[el2_lib.scala 543:51] - node _T_885 = mux(_T_881, _T_883, _T_884) @[el2_lib.scala 543:23] - _T_741[23] <= _T_885 @[el2_lib.scala 543:17] - node _T_886 = bits(_T_740, 24, 0) @[el2_lib.scala 543:27] - node _T_887 = orr(_T_886) @[el2_lib.scala 543:35] - node _T_888 = bits(_T_740, 25, 25) @[el2_lib.scala 543:44] - node _T_889 = not(_T_888) @[el2_lib.scala 543:40] - node _T_890 = bits(_T_740, 25, 25) @[el2_lib.scala 543:51] - node _T_891 = mux(_T_887, _T_889, _T_890) @[el2_lib.scala 543:23] - _T_741[24] <= _T_891 @[el2_lib.scala 543:17] - node _T_892 = bits(_T_740, 25, 0) @[el2_lib.scala 543:27] - node _T_893 = orr(_T_892) @[el2_lib.scala 543:35] - node _T_894 = bits(_T_740, 26, 26) @[el2_lib.scala 543:44] - node _T_895 = not(_T_894) @[el2_lib.scala 543:40] - node _T_896 = bits(_T_740, 26, 26) @[el2_lib.scala 543:51] - node _T_897 = mux(_T_893, _T_895, _T_896) @[el2_lib.scala 543:23] - _T_741[25] <= _T_897 @[el2_lib.scala 543:17] - node _T_898 = bits(_T_740, 26, 0) @[el2_lib.scala 543:27] - node _T_899 = orr(_T_898) @[el2_lib.scala 543:35] - node _T_900 = bits(_T_740, 27, 27) @[el2_lib.scala 543:44] - node _T_901 = not(_T_900) @[el2_lib.scala 543:40] - node _T_902 = bits(_T_740, 27, 27) @[el2_lib.scala 543:51] - node _T_903 = mux(_T_899, _T_901, _T_902) @[el2_lib.scala 543:23] - _T_741[26] <= _T_903 @[el2_lib.scala 543:17] - node _T_904 = bits(_T_740, 27, 0) @[el2_lib.scala 543:27] - node _T_905 = orr(_T_904) @[el2_lib.scala 543:35] - node _T_906 = bits(_T_740, 28, 28) @[el2_lib.scala 543:44] - node _T_907 = not(_T_906) @[el2_lib.scala 543:40] - node _T_908 = bits(_T_740, 28, 28) @[el2_lib.scala 543:51] - node _T_909 = mux(_T_905, _T_907, _T_908) @[el2_lib.scala 543:23] - _T_741[27] <= _T_909 @[el2_lib.scala 543:17] - node _T_910 = bits(_T_740, 28, 0) @[el2_lib.scala 543:27] - node _T_911 = orr(_T_910) @[el2_lib.scala 543:35] - node _T_912 = bits(_T_740, 29, 29) @[el2_lib.scala 543:44] - node _T_913 = not(_T_912) @[el2_lib.scala 543:40] - node _T_914 = bits(_T_740, 29, 29) @[el2_lib.scala 543:51] - node _T_915 = mux(_T_911, _T_913, _T_914) @[el2_lib.scala 543:23] - _T_741[28] <= _T_915 @[el2_lib.scala 543:17] - node _T_916 = bits(_T_740, 29, 0) @[el2_lib.scala 543:27] - node _T_917 = orr(_T_916) @[el2_lib.scala 543:35] - node _T_918 = bits(_T_740, 30, 30) @[el2_lib.scala 543:44] - node _T_919 = not(_T_918) @[el2_lib.scala 543:40] - node _T_920 = bits(_T_740, 30, 30) @[el2_lib.scala 543:51] - node _T_921 = mux(_T_917, _T_919, _T_920) @[el2_lib.scala 543:23] - _T_741[29] <= _T_921 @[el2_lib.scala 543:17] - node _T_922 = bits(_T_740, 30, 0) @[el2_lib.scala 543:27] - node _T_923 = orr(_T_922) @[el2_lib.scala 543:35] - node _T_924 = bits(_T_740, 31, 31) @[el2_lib.scala 543:44] - node _T_925 = not(_T_924) @[el2_lib.scala 543:40] - node _T_926 = bits(_T_740, 31, 31) @[el2_lib.scala 543:51] - node _T_927 = mux(_T_923, _T_925, _T_926) @[el2_lib.scala 543:23] - _T_741[30] <= _T_927 @[el2_lib.scala 543:17] - node _T_928 = cat(_T_741[2], _T_741[1]) @[el2_lib.scala 545:14] - node _T_929 = cat(_T_928, _T_741[0]) @[el2_lib.scala 545:14] - node _T_930 = cat(_T_741[4], _T_741[3]) @[el2_lib.scala 545:14] - node _T_931 = cat(_T_741[6], _T_741[5]) @[el2_lib.scala 545:14] - node _T_932 = cat(_T_931, _T_930) @[el2_lib.scala 545:14] - node _T_933 = cat(_T_932, _T_929) @[el2_lib.scala 545:14] - node _T_934 = cat(_T_741[8], _T_741[7]) @[el2_lib.scala 545:14] - node _T_935 = cat(_T_741[10], _T_741[9]) @[el2_lib.scala 545:14] - node _T_936 = cat(_T_935, _T_934) @[el2_lib.scala 545:14] - node _T_937 = cat(_T_741[12], _T_741[11]) @[el2_lib.scala 545:14] - node _T_938 = cat(_T_741[14], _T_741[13]) @[el2_lib.scala 545:14] - node _T_939 = cat(_T_938, _T_937) @[el2_lib.scala 545:14] - node _T_940 = cat(_T_939, _T_936) @[el2_lib.scala 545:14] - node _T_941 = cat(_T_940, _T_933) @[el2_lib.scala 545:14] - node _T_942 = cat(_T_741[16], _T_741[15]) @[el2_lib.scala 545:14] - node _T_943 = cat(_T_741[18], _T_741[17]) @[el2_lib.scala 545:14] - node _T_944 = cat(_T_943, _T_942) @[el2_lib.scala 545:14] - node _T_945 = cat(_T_741[20], _T_741[19]) @[el2_lib.scala 545:14] - node _T_946 = cat(_T_741[22], _T_741[21]) @[el2_lib.scala 545:14] - node _T_947 = cat(_T_946, _T_945) @[el2_lib.scala 545:14] - node _T_948 = cat(_T_947, _T_944) @[el2_lib.scala 545:14] - node _T_949 = cat(_T_741[24], _T_741[23]) @[el2_lib.scala 545:14] - node _T_950 = cat(_T_741[26], _T_741[25]) @[el2_lib.scala 545:14] - node _T_951 = cat(_T_950, _T_949) @[el2_lib.scala 545:14] - node _T_952 = cat(_T_741[28], _T_741[27]) @[el2_lib.scala 545:14] - node _T_953 = cat(_T_741[30], _T_741[29]) @[el2_lib.scala 545:14] - node _T_954 = cat(_T_953, _T_952) @[el2_lib.scala 545:14] - node _T_955 = cat(_T_954, _T_951) @[el2_lib.scala 545:14] - node _T_956 = cat(_T_955, _T_948) @[el2_lib.scala 545:14] - node _T_957 = cat(_T_956, _T_941) @[el2_lib.scala 545:14] - node _T_958 = bits(_T_740, 0, 0) @[el2_lib.scala 545:24] + wire _T_741 : UInt<1>[31] @[lib.scala 401:20] + node _T_742 = bits(_T_740, 0, 0) @[lib.scala 403:27] + node _T_743 = orr(_T_742) @[lib.scala 403:35] + node _T_744 = bits(_T_740, 1, 1) @[lib.scala 403:44] + node _T_745 = not(_T_744) @[lib.scala 403:40] + node _T_746 = bits(_T_740, 1, 1) @[lib.scala 403:51] + node _T_747 = mux(_T_743, _T_745, _T_746) @[lib.scala 403:23] + _T_741[0] <= _T_747 @[lib.scala 403:17] + node _T_748 = bits(_T_740, 1, 0) @[lib.scala 403:27] + node _T_749 = orr(_T_748) @[lib.scala 403:35] + node _T_750 = bits(_T_740, 2, 2) @[lib.scala 403:44] + node _T_751 = not(_T_750) @[lib.scala 403:40] + node _T_752 = bits(_T_740, 2, 2) @[lib.scala 403:51] + node _T_753 = mux(_T_749, _T_751, _T_752) @[lib.scala 403:23] + _T_741[1] <= _T_753 @[lib.scala 403:17] + node _T_754 = bits(_T_740, 2, 0) @[lib.scala 403:27] + node _T_755 = orr(_T_754) @[lib.scala 403:35] + node _T_756 = bits(_T_740, 3, 3) @[lib.scala 403:44] + node _T_757 = not(_T_756) @[lib.scala 403:40] + node _T_758 = bits(_T_740, 3, 3) @[lib.scala 403:51] + node _T_759 = mux(_T_755, _T_757, _T_758) @[lib.scala 403:23] + _T_741[2] <= _T_759 @[lib.scala 403:17] + node _T_760 = bits(_T_740, 3, 0) @[lib.scala 403:27] + node _T_761 = orr(_T_760) @[lib.scala 403:35] + node _T_762 = bits(_T_740, 4, 4) @[lib.scala 403:44] + node _T_763 = not(_T_762) @[lib.scala 403:40] + node _T_764 = bits(_T_740, 4, 4) @[lib.scala 403:51] + node _T_765 = mux(_T_761, _T_763, _T_764) @[lib.scala 403:23] + _T_741[3] <= _T_765 @[lib.scala 403:17] + node _T_766 = bits(_T_740, 4, 0) @[lib.scala 403:27] + node _T_767 = orr(_T_766) @[lib.scala 403:35] + node _T_768 = bits(_T_740, 5, 5) @[lib.scala 403:44] + node _T_769 = not(_T_768) @[lib.scala 403:40] + node _T_770 = bits(_T_740, 5, 5) @[lib.scala 403:51] + node _T_771 = mux(_T_767, _T_769, _T_770) @[lib.scala 403:23] + _T_741[4] <= _T_771 @[lib.scala 403:17] + node _T_772 = bits(_T_740, 5, 0) @[lib.scala 403:27] + node _T_773 = orr(_T_772) @[lib.scala 403:35] + node _T_774 = bits(_T_740, 6, 6) @[lib.scala 403:44] + node _T_775 = not(_T_774) @[lib.scala 403:40] + node _T_776 = bits(_T_740, 6, 6) @[lib.scala 403:51] + node _T_777 = mux(_T_773, _T_775, _T_776) @[lib.scala 403:23] + _T_741[5] <= _T_777 @[lib.scala 403:17] + node _T_778 = bits(_T_740, 6, 0) @[lib.scala 403:27] + node _T_779 = orr(_T_778) @[lib.scala 403:35] + node _T_780 = bits(_T_740, 7, 7) @[lib.scala 403:44] + node _T_781 = not(_T_780) @[lib.scala 403:40] + node _T_782 = bits(_T_740, 7, 7) @[lib.scala 403:51] + node _T_783 = mux(_T_779, _T_781, _T_782) @[lib.scala 403:23] + _T_741[6] <= _T_783 @[lib.scala 403:17] + node _T_784 = bits(_T_740, 7, 0) @[lib.scala 403:27] + node _T_785 = orr(_T_784) @[lib.scala 403:35] + node _T_786 = bits(_T_740, 8, 8) @[lib.scala 403:44] + node _T_787 = not(_T_786) @[lib.scala 403:40] + node _T_788 = bits(_T_740, 8, 8) @[lib.scala 403:51] + node _T_789 = mux(_T_785, _T_787, _T_788) @[lib.scala 403:23] + _T_741[7] <= _T_789 @[lib.scala 403:17] + node _T_790 = bits(_T_740, 8, 0) @[lib.scala 403:27] + node _T_791 = orr(_T_790) @[lib.scala 403:35] + node _T_792 = bits(_T_740, 9, 9) @[lib.scala 403:44] + node _T_793 = not(_T_792) @[lib.scala 403:40] + node _T_794 = bits(_T_740, 9, 9) @[lib.scala 403:51] + node _T_795 = mux(_T_791, _T_793, _T_794) @[lib.scala 403:23] + _T_741[8] <= _T_795 @[lib.scala 403:17] + node _T_796 = bits(_T_740, 9, 0) @[lib.scala 403:27] + node _T_797 = orr(_T_796) @[lib.scala 403:35] + node _T_798 = bits(_T_740, 10, 10) @[lib.scala 403:44] + node _T_799 = not(_T_798) @[lib.scala 403:40] + node _T_800 = bits(_T_740, 10, 10) @[lib.scala 403:51] + node _T_801 = mux(_T_797, _T_799, _T_800) @[lib.scala 403:23] + _T_741[9] <= _T_801 @[lib.scala 403:17] + node _T_802 = bits(_T_740, 10, 0) @[lib.scala 403:27] + node _T_803 = orr(_T_802) @[lib.scala 403:35] + node _T_804 = bits(_T_740, 11, 11) @[lib.scala 403:44] + node _T_805 = not(_T_804) @[lib.scala 403:40] + node _T_806 = bits(_T_740, 11, 11) @[lib.scala 403:51] + node _T_807 = mux(_T_803, _T_805, _T_806) @[lib.scala 403:23] + _T_741[10] <= _T_807 @[lib.scala 403:17] + node _T_808 = bits(_T_740, 11, 0) @[lib.scala 403:27] + node _T_809 = orr(_T_808) @[lib.scala 403:35] + node _T_810 = bits(_T_740, 12, 12) @[lib.scala 403:44] + node _T_811 = not(_T_810) @[lib.scala 403:40] + node _T_812 = bits(_T_740, 12, 12) @[lib.scala 403:51] + node _T_813 = mux(_T_809, _T_811, _T_812) @[lib.scala 403:23] + _T_741[11] <= _T_813 @[lib.scala 403:17] + node _T_814 = bits(_T_740, 12, 0) @[lib.scala 403:27] + node _T_815 = orr(_T_814) @[lib.scala 403:35] + node _T_816 = bits(_T_740, 13, 13) @[lib.scala 403:44] + node _T_817 = not(_T_816) @[lib.scala 403:40] + node _T_818 = bits(_T_740, 13, 13) @[lib.scala 403:51] + node _T_819 = mux(_T_815, _T_817, _T_818) @[lib.scala 403:23] + _T_741[12] <= _T_819 @[lib.scala 403:17] + node _T_820 = bits(_T_740, 13, 0) @[lib.scala 403:27] + node _T_821 = orr(_T_820) @[lib.scala 403:35] + node _T_822 = bits(_T_740, 14, 14) @[lib.scala 403:44] + node _T_823 = not(_T_822) @[lib.scala 403:40] + node _T_824 = bits(_T_740, 14, 14) @[lib.scala 403:51] + node _T_825 = mux(_T_821, _T_823, _T_824) @[lib.scala 403:23] + _T_741[13] <= _T_825 @[lib.scala 403:17] + node _T_826 = bits(_T_740, 14, 0) @[lib.scala 403:27] + node _T_827 = orr(_T_826) @[lib.scala 403:35] + node _T_828 = bits(_T_740, 15, 15) @[lib.scala 403:44] + node _T_829 = not(_T_828) @[lib.scala 403:40] + node _T_830 = bits(_T_740, 15, 15) @[lib.scala 403:51] + node _T_831 = mux(_T_827, _T_829, _T_830) @[lib.scala 403:23] + _T_741[14] <= _T_831 @[lib.scala 403:17] + node _T_832 = bits(_T_740, 15, 0) @[lib.scala 403:27] + node _T_833 = orr(_T_832) @[lib.scala 403:35] + node _T_834 = bits(_T_740, 16, 16) @[lib.scala 403:44] + node _T_835 = not(_T_834) @[lib.scala 403:40] + node _T_836 = bits(_T_740, 16, 16) @[lib.scala 403:51] + node _T_837 = mux(_T_833, _T_835, _T_836) @[lib.scala 403:23] + _T_741[15] <= _T_837 @[lib.scala 403:17] + node _T_838 = bits(_T_740, 16, 0) @[lib.scala 403:27] + node _T_839 = orr(_T_838) @[lib.scala 403:35] + node _T_840 = bits(_T_740, 17, 17) @[lib.scala 403:44] + node _T_841 = not(_T_840) @[lib.scala 403:40] + node _T_842 = bits(_T_740, 17, 17) @[lib.scala 403:51] + node _T_843 = mux(_T_839, _T_841, _T_842) @[lib.scala 403:23] + _T_741[16] <= _T_843 @[lib.scala 403:17] + node _T_844 = bits(_T_740, 17, 0) @[lib.scala 403:27] + node _T_845 = orr(_T_844) @[lib.scala 403:35] + node _T_846 = bits(_T_740, 18, 18) @[lib.scala 403:44] + node _T_847 = not(_T_846) @[lib.scala 403:40] + node _T_848 = bits(_T_740, 18, 18) @[lib.scala 403:51] + node _T_849 = mux(_T_845, _T_847, _T_848) @[lib.scala 403:23] + _T_741[17] <= _T_849 @[lib.scala 403:17] + node _T_850 = bits(_T_740, 18, 0) @[lib.scala 403:27] + node _T_851 = orr(_T_850) @[lib.scala 403:35] + node _T_852 = bits(_T_740, 19, 19) @[lib.scala 403:44] + node _T_853 = not(_T_852) @[lib.scala 403:40] + node _T_854 = bits(_T_740, 19, 19) @[lib.scala 403:51] + node _T_855 = mux(_T_851, _T_853, _T_854) @[lib.scala 403:23] + _T_741[18] <= _T_855 @[lib.scala 403:17] + node _T_856 = bits(_T_740, 19, 0) @[lib.scala 403:27] + node _T_857 = orr(_T_856) @[lib.scala 403:35] + node _T_858 = bits(_T_740, 20, 20) @[lib.scala 403:44] + node _T_859 = not(_T_858) @[lib.scala 403:40] + node _T_860 = bits(_T_740, 20, 20) @[lib.scala 403:51] + node _T_861 = mux(_T_857, _T_859, _T_860) @[lib.scala 403:23] + _T_741[19] <= _T_861 @[lib.scala 403:17] + node _T_862 = bits(_T_740, 20, 0) @[lib.scala 403:27] + node _T_863 = orr(_T_862) @[lib.scala 403:35] + node _T_864 = bits(_T_740, 21, 21) @[lib.scala 403:44] + node _T_865 = not(_T_864) @[lib.scala 403:40] + node _T_866 = bits(_T_740, 21, 21) @[lib.scala 403:51] + node _T_867 = mux(_T_863, _T_865, _T_866) @[lib.scala 403:23] + _T_741[20] <= _T_867 @[lib.scala 403:17] + node _T_868 = bits(_T_740, 21, 0) @[lib.scala 403:27] + node _T_869 = orr(_T_868) @[lib.scala 403:35] + node _T_870 = bits(_T_740, 22, 22) @[lib.scala 403:44] + node _T_871 = not(_T_870) @[lib.scala 403:40] + node _T_872 = bits(_T_740, 22, 22) @[lib.scala 403:51] + node _T_873 = mux(_T_869, _T_871, _T_872) @[lib.scala 403:23] + _T_741[21] <= _T_873 @[lib.scala 403:17] + node _T_874 = bits(_T_740, 22, 0) @[lib.scala 403:27] + node _T_875 = orr(_T_874) @[lib.scala 403:35] + node _T_876 = bits(_T_740, 23, 23) @[lib.scala 403:44] + node _T_877 = not(_T_876) @[lib.scala 403:40] + node _T_878 = bits(_T_740, 23, 23) @[lib.scala 403:51] + node _T_879 = mux(_T_875, _T_877, _T_878) @[lib.scala 403:23] + _T_741[22] <= _T_879 @[lib.scala 403:17] + node _T_880 = bits(_T_740, 23, 0) @[lib.scala 403:27] + node _T_881 = orr(_T_880) @[lib.scala 403:35] + node _T_882 = bits(_T_740, 24, 24) @[lib.scala 403:44] + node _T_883 = not(_T_882) @[lib.scala 403:40] + node _T_884 = bits(_T_740, 24, 24) @[lib.scala 403:51] + node _T_885 = mux(_T_881, _T_883, _T_884) @[lib.scala 403:23] + _T_741[23] <= _T_885 @[lib.scala 403:17] + node _T_886 = bits(_T_740, 24, 0) @[lib.scala 403:27] + node _T_887 = orr(_T_886) @[lib.scala 403:35] + node _T_888 = bits(_T_740, 25, 25) @[lib.scala 403:44] + node _T_889 = not(_T_888) @[lib.scala 403:40] + node _T_890 = bits(_T_740, 25, 25) @[lib.scala 403:51] + node _T_891 = mux(_T_887, _T_889, _T_890) @[lib.scala 403:23] + _T_741[24] <= _T_891 @[lib.scala 403:17] + node _T_892 = bits(_T_740, 25, 0) @[lib.scala 403:27] + node _T_893 = orr(_T_892) @[lib.scala 403:35] + node _T_894 = bits(_T_740, 26, 26) @[lib.scala 403:44] + node _T_895 = not(_T_894) @[lib.scala 403:40] + node _T_896 = bits(_T_740, 26, 26) @[lib.scala 403:51] + node _T_897 = mux(_T_893, _T_895, _T_896) @[lib.scala 403:23] + _T_741[25] <= _T_897 @[lib.scala 403:17] + node _T_898 = bits(_T_740, 26, 0) @[lib.scala 403:27] + node _T_899 = orr(_T_898) @[lib.scala 403:35] + node _T_900 = bits(_T_740, 27, 27) @[lib.scala 403:44] + node _T_901 = not(_T_900) @[lib.scala 403:40] + node _T_902 = bits(_T_740, 27, 27) @[lib.scala 403:51] + node _T_903 = mux(_T_899, _T_901, _T_902) @[lib.scala 403:23] + _T_741[26] <= _T_903 @[lib.scala 403:17] + node _T_904 = bits(_T_740, 27, 0) @[lib.scala 403:27] + node _T_905 = orr(_T_904) @[lib.scala 403:35] + node _T_906 = bits(_T_740, 28, 28) @[lib.scala 403:44] + node _T_907 = not(_T_906) @[lib.scala 403:40] + node _T_908 = bits(_T_740, 28, 28) @[lib.scala 403:51] + node _T_909 = mux(_T_905, _T_907, _T_908) @[lib.scala 403:23] + _T_741[27] <= _T_909 @[lib.scala 403:17] + node _T_910 = bits(_T_740, 28, 0) @[lib.scala 403:27] + node _T_911 = orr(_T_910) @[lib.scala 403:35] + node _T_912 = bits(_T_740, 29, 29) @[lib.scala 403:44] + node _T_913 = not(_T_912) @[lib.scala 403:40] + node _T_914 = bits(_T_740, 29, 29) @[lib.scala 403:51] + node _T_915 = mux(_T_911, _T_913, _T_914) @[lib.scala 403:23] + _T_741[28] <= _T_915 @[lib.scala 403:17] + node _T_916 = bits(_T_740, 29, 0) @[lib.scala 403:27] + node _T_917 = orr(_T_916) @[lib.scala 403:35] + node _T_918 = bits(_T_740, 30, 30) @[lib.scala 403:44] + node _T_919 = not(_T_918) @[lib.scala 403:40] + node _T_920 = bits(_T_740, 30, 30) @[lib.scala 403:51] + node _T_921 = mux(_T_917, _T_919, _T_920) @[lib.scala 403:23] + _T_741[29] <= _T_921 @[lib.scala 403:17] + node _T_922 = bits(_T_740, 30, 0) @[lib.scala 403:27] + node _T_923 = orr(_T_922) @[lib.scala 403:35] + node _T_924 = bits(_T_740, 31, 31) @[lib.scala 403:44] + node _T_925 = not(_T_924) @[lib.scala 403:40] + node _T_926 = bits(_T_740, 31, 31) @[lib.scala 403:51] + node _T_927 = mux(_T_923, _T_925, _T_926) @[lib.scala 403:23] + _T_741[30] <= _T_927 @[lib.scala 403:17] + node _T_928 = cat(_T_741[2], _T_741[1]) @[lib.scala 405:14] + node _T_929 = cat(_T_928, _T_741[0]) @[lib.scala 405:14] + node _T_930 = cat(_T_741[4], _T_741[3]) @[lib.scala 405:14] + node _T_931 = cat(_T_741[6], _T_741[5]) @[lib.scala 405:14] + node _T_932 = cat(_T_931, _T_930) @[lib.scala 405:14] + node _T_933 = cat(_T_932, _T_929) @[lib.scala 405:14] + node _T_934 = cat(_T_741[8], _T_741[7]) @[lib.scala 405:14] + node _T_935 = cat(_T_741[10], _T_741[9]) @[lib.scala 405:14] + node _T_936 = cat(_T_935, _T_934) @[lib.scala 405:14] + node _T_937 = cat(_T_741[12], _T_741[11]) @[lib.scala 405:14] + node _T_938 = cat(_T_741[14], _T_741[13]) @[lib.scala 405:14] + node _T_939 = cat(_T_938, _T_937) @[lib.scala 405:14] + node _T_940 = cat(_T_939, _T_936) @[lib.scala 405:14] + node _T_941 = cat(_T_940, _T_933) @[lib.scala 405:14] + node _T_942 = cat(_T_741[16], _T_741[15]) @[lib.scala 405:14] + node _T_943 = cat(_T_741[18], _T_741[17]) @[lib.scala 405:14] + node _T_944 = cat(_T_943, _T_942) @[lib.scala 405:14] + node _T_945 = cat(_T_741[20], _T_741[19]) @[lib.scala 405:14] + node _T_946 = cat(_T_741[22], _T_741[21]) @[lib.scala 405:14] + node _T_947 = cat(_T_946, _T_945) @[lib.scala 405:14] + node _T_948 = cat(_T_947, _T_944) @[lib.scala 405:14] + node _T_949 = cat(_T_741[24], _T_741[23]) @[lib.scala 405:14] + node _T_950 = cat(_T_741[26], _T_741[25]) @[lib.scala 405:14] + node _T_951 = cat(_T_950, _T_949) @[lib.scala 405:14] + node _T_952 = cat(_T_741[28], _T_741[27]) @[lib.scala 405:14] + node _T_953 = cat(_T_741[30], _T_741[29]) @[lib.scala 405:14] + node _T_954 = cat(_T_953, _T_952) @[lib.scala 405:14] + node _T_955 = cat(_T_954, _T_951) @[lib.scala 405:14] + node _T_956 = cat(_T_955, _T_948) @[lib.scala 405:14] + node _T_957 = cat(_T_956, _T_941) @[lib.scala 405:14] + node _T_958 = bits(_T_740, 0, 0) @[lib.scala 405:24] node _T_959 = cat(_T_957, _T_958) @[Cat.scala 29:58] node _T_960 = bits(q_ff, 31, 0) @[exu_div_ctl.scala 166:86] node _T_961 = mux(_T_739, _T_959, _T_960) @[exu_div_ctl.scala 166:22] @@ -85317,510 +85309,510 @@ circuit quasar_wrapper : node _T_1011 = and(sign_ff, _T_1010) @[exu_div_ctl.scala 183:31] node _T_1012 = bits(_T_1011, 0, 0) @[exu_div_ctl.scala 183:69] node _T_1013 = bits(q_ff, 31, 0) @[exu_div_ctl.scala 183:91] - wire _T_1014 : UInt<1>[31] @[el2_lib.scala 541:20] - node _T_1015 = bits(_T_1013, 0, 0) @[el2_lib.scala 543:27] - node _T_1016 = orr(_T_1015) @[el2_lib.scala 543:35] - node _T_1017 = bits(_T_1013, 1, 1) @[el2_lib.scala 543:44] - node _T_1018 = not(_T_1017) @[el2_lib.scala 543:40] - node _T_1019 = bits(_T_1013, 1, 1) @[el2_lib.scala 543:51] - node _T_1020 = mux(_T_1016, _T_1018, _T_1019) @[el2_lib.scala 543:23] - _T_1014[0] <= _T_1020 @[el2_lib.scala 543:17] - node _T_1021 = bits(_T_1013, 1, 0) @[el2_lib.scala 543:27] - node _T_1022 = orr(_T_1021) @[el2_lib.scala 543:35] - node _T_1023 = bits(_T_1013, 2, 2) @[el2_lib.scala 543:44] - node _T_1024 = not(_T_1023) @[el2_lib.scala 543:40] - node _T_1025 = bits(_T_1013, 2, 2) @[el2_lib.scala 543:51] - node _T_1026 = mux(_T_1022, _T_1024, _T_1025) @[el2_lib.scala 543:23] - _T_1014[1] <= _T_1026 @[el2_lib.scala 543:17] - node _T_1027 = bits(_T_1013, 2, 0) @[el2_lib.scala 543:27] - node _T_1028 = orr(_T_1027) @[el2_lib.scala 543:35] - node _T_1029 = bits(_T_1013, 3, 3) @[el2_lib.scala 543:44] - node _T_1030 = not(_T_1029) @[el2_lib.scala 543:40] - node _T_1031 = bits(_T_1013, 3, 3) @[el2_lib.scala 543:51] - node _T_1032 = mux(_T_1028, _T_1030, _T_1031) @[el2_lib.scala 543:23] - _T_1014[2] <= _T_1032 @[el2_lib.scala 543:17] - node _T_1033 = bits(_T_1013, 3, 0) @[el2_lib.scala 543:27] - node _T_1034 = orr(_T_1033) @[el2_lib.scala 543:35] - node _T_1035 = bits(_T_1013, 4, 4) @[el2_lib.scala 543:44] - node _T_1036 = not(_T_1035) @[el2_lib.scala 543:40] - node _T_1037 = bits(_T_1013, 4, 4) @[el2_lib.scala 543:51] - node _T_1038 = mux(_T_1034, _T_1036, _T_1037) @[el2_lib.scala 543:23] - _T_1014[3] <= _T_1038 @[el2_lib.scala 543:17] - node _T_1039 = bits(_T_1013, 4, 0) @[el2_lib.scala 543:27] - node _T_1040 = orr(_T_1039) @[el2_lib.scala 543:35] - node _T_1041 = bits(_T_1013, 5, 5) @[el2_lib.scala 543:44] - node _T_1042 = not(_T_1041) @[el2_lib.scala 543:40] - node _T_1043 = bits(_T_1013, 5, 5) @[el2_lib.scala 543:51] - node _T_1044 = mux(_T_1040, _T_1042, _T_1043) @[el2_lib.scala 543:23] - _T_1014[4] <= _T_1044 @[el2_lib.scala 543:17] - node _T_1045 = bits(_T_1013, 5, 0) @[el2_lib.scala 543:27] - node _T_1046 = orr(_T_1045) @[el2_lib.scala 543:35] - node _T_1047 = bits(_T_1013, 6, 6) @[el2_lib.scala 543:44] - node _T_1048 = not(_T_1047) @[el2_lib.scala 543:40] - node _T_1049 = bits(_T_1013, 6, 6) @[el2_lib.scala 543:51] - node _T_1050 = mux(_T_1046, _T_1048, _T_1049) @[el2_lib.scala 543:23] - _T_1014[5] <= _T_1050 @[el2_lib.scala 543:17] - node _T_1051 = bits(_T_1013, 6, 0) @[el2_lib.scala 543:27] - node _T_1052 = orr(_T_1051) @[el2_lib.scala 543:35] - node _T_1053 = bits(_T_1013, 7, 7) @[el2_lib.scala 543:44] - node _T_1054 = not(_T_1053) @[el2_lib.scala 543:40] - node _T_1055 = bits(_T_1013, 7, 7) @[el2_lib.scala 543:51] - node _T_1056 = mux(_T_1052, _T_1054, _T_1055) @[el2_lib.scala 543:23] - _T_1014[6] <= _T_1056 @[el2_lib.scala 543:17] - node _T_1057 = bits(_T_1013, 7, 0) @[el2_lib.scala 543:27] - node _T_1058 = orr(_T_1057) @[el2_lib.scala 543:35] - node _T_1059 = bits(_T_1013, 8, 8) @[el2_lib.scala 543:44] - node _T_1060 = not(_T_1059) @[el2_lib.scala 543:40] - node _T_1061 = bits(_T_1013, 8, 8) @[el2_lib.scala 543:51] - node _T_1062 = mux(_T_1058, _T_1060, _T_1061) @[el2_lib.scala 543:23] - _T_1014[7] <= _T_1062 @[el2_lib.scala 543:17] - node _T_1063 = bits(_T_1013, 8, 0) @[el2_lib.scala 543:27] - node _T_1064 = orr(_T_1063) @[el2_lib.scala 543:35] - node _T_1065 = bits(_T_1013, 9, 9) @[el2_lib.scala 543:44] - node _T_1066 = not(_T_1065) @[el2_lib.scala 543:40] - node _T_1067 = bits(_T_1013, 9, 9) @[el2_lib.scala 543:51] - node _T_1068 = mux(_T_1064, _T_1066, _T_1067) @[el2_lib.scala 543:23] - _T_1014[8] <= _T_1068 @[el2_lib.scala 543:17] - node _T_1069 = bits(_T_1013, 9, 0) @[el2_lib.scala 543:27] - node _T_1070 = orr(_T_1069) @[el2_lib.scala 543:35] - node _T_1071 = bits(_T_1013, 10, 10) @[el2_lib.scala 543:44] - node _T_1072 = not(_T_1071) @[el2_lib.scala 543:40] - node _T_1073 = bits(_T_1013, 10, 10) @[el2_lib.scala 543:51] - node _T_1074 = mux(_T_1070, _T_1072, _T_1073) @[el2_lib.scala 543:23] - _T_1014[9] <= _T_1074 @[el2_lib.scala 543:17] - node _T_1075 = bits(_T_1013, 10, 0) @[el2_lib.scala 543:27] - node _T_1076 = orr(_T_1075) @[el2_lib.scala 543:35] - node _T_1077 = bits(_T_1013, 11, 11) @[el2_lib.scala 543:44] - node _T_1078 = not(_T_1077) @[el2_lib.scala 543:40] - node _T_1079 = bits(_T_1013, 11, 11) @[el2_lib.scala 543:51] - node _T_1080 = mux(_T_1076, _T_1078, _T_1079) @[el2_lib.scala 543:23] - _T_1014[10] <= _T_1080 @[el2_lib.scala 543:17] - node _T_1081 = bits(_T_1013, 11, 0) @[el2_lib.scala 543:27] - node _T_1082 = orr(_T_1081) @[el2_lib.scala 543:35] - node _T_1083 = bits(_T_1013, 12, 12) @[el2_lib.scala 543:44] - node _T_1084 = not(_T_1083) @[el2_lib.scala 543:40] - node _T_1085 = bits(_T_1013, 12, 12) @[el2_lib.scala 543:51] - node _T_1086 = mux(_T_1082, _T_1084, _T_1085) @[el2_lib.scala 543:23] - _T_1014[11] <= _T_1086 @[el2_lib.scala 543:17] - node _T_1087 = bits(_T_1013, 12, 0) @[el2_lib.scala 543:27] - node _T_1088 = orr(_T_1087) @[el2_lib.scala 543:35] - node _T_1089 = bits(_T_1013, 13, 13) @[el2_lib.scala 543:44] - node _T_1090 = not(_T_1089) @[el2_lib.scala 543:40] - node _T_1091 = bits(_T_1013, 13, 13) @[el2_lib.scala 543:51] - node _T_1092 = mux(_T_1088, _T_1090, _T_1091) @[el2_lib.scala 543:23] - _T_1014[12] <= _T_1092 @[el2_lib.scala 543:17] - node _T_1093 = bits(_T_1013, 13, 0) @[el2_lib.scala 543:27] - node _T_1094 = orr(_T_1093) @[el2_lib.scala 543:35] - node _T_1095 = bits(_T_1013, 14, 14) @[el2_lib.scala 543:44] - node _T_1096 = not(_T_1095) @[el2_lib.scala 543:40] - node _T_1097 = bits(_T_1013, 14, 14) @[el2_lib.scala 543:51] - node _T_1098 = mux(_T_1094, _T_1096, _T_1097) @[el2_lib.scala 543:23] - _T_1014[13] <= _T_1098 @[el2_lib.scala 543:17] - node _T_1099 = bits(_T_1013, 14, 0) @[el2_lib.scala 543:27] - node _T_1100 = orr(_T_1099) @[el2_lib.scala 543:35] - node _T_1101 = bits(_T_1013, 15, 15) @[el2_lib.scala 543:44] - node _T_1102 = not(_T_1101) @[el2_lib.scala 543:40] - node _T_1103 = bits(_T_1013, 15, 15) @[el2_lib.scala 543:51] - node _T_1104 = mux(_T_1100, _T_1102, _T_1103) @[el2_lib.scala 543:23] - _T_1014[14] <= _T_1104 @[el2_lib.scala 543:17] - node _T_1105 = bits(_T_1013, 15, 0) @[el2_lib.scala 543:27] - node _T_1106 = orr(_T_1105) @[el2_lib.scala 543:35] - node _T_1107 = bits(_T_1013, 16, 16) @[el2_lib.scala 543:44] - node _T_1108 = not(_T_1107) @[el2_lib.scala 543:40] - node _T_1109 = bits(_T_1013, 16, 16) @[el2_lib.scala 543:51] - node _T_1110 = mux(_T_1106, _T_1108, _T_1109) @[el2_lib.scala 543:23] - _T_1014[15] <= _T_1110 @[el2_lib.scala 543:17] - node _T_1111 = bits(_T_1013, 16, 0) @[el2_lib.scala 543:27] - node _T_1112 = orr(_T_1111) @[el2_lib.scala 543:35] - node _T_1113 = bits(_T_1013, 17, 17) @[el2_lib.scala 543:44] - node _T_1114 = not(_T_1113) @[el2_lib.scala 543:40] - node _T_1115 = bits(_T_1013, 17, 17) @[el2_lib.scala 543:51] - node _T_1116 = mux(_T_1112, _T_1114, _T_1115) @[el2_lib.scala 543:23] - _T_1014[16] <= _T_1116 @[el2_lib.scala 543:17] - node _T_1117 = bits(_T_1013, 17, 0) @[el2_lib.scala 543:27] - node _T_1118 = orr(_T_1117) @[el2_lib.scala 543:35] - node _T_1119 = bits(_T_1013, 18, 18) @[el2_lib.scala 543:44] - node _T_1120 = not(_T_1119) @[el2_lib.scala 543:40] - node _T_1121 = bits(_T_1013, 18, 18) @[el2_lib.scala 543:51] - node _T_1122 = mux(_T_1118, _T_1120, _T_1121) @[el2_lib.scala 543:23] - _T_1014[17] <= _T_1122 @[el2_lib.scala 543:17] - node _T_1123 = bits(_T_1013, 18, 0) @[el2_lib.scala 543:27] - node _T_1124 = orr(_T_1123) @[el2_lib.scala 543:35] - node _T_1125 = bits(_T_1013, 19, 19) @[el2_lib.scala 543:44] - node _T_1126 = not(_T_1125) @[el2_lib.scala 543:40] - node _T_1127 = bits(_T_1013, 19, 19) @[el2_lib.scala 543:51] - node _T_1128 = mux(_T_1124, _T_1126, _T_1127) @[el2_lib.scala 543:23] - _T_1014[18] <= _T_1128 @[el2_lib.scala 543:17] - node _T_1129 = bits(_T_1013, 19, 0) @[el2_lib.scala 543:27] - node _T_1130 = orr(_T_1129) @[el2_lib.scala 543:35] - node _T_1131 = bits(_T_1013, 20, 20) @[el2_lib.scala 543:44] - node _T_1132 = not(_T_1131) @[el2_lib.scala 543:40] - node _T_1133 = bits(_T_1013, 20, 20) @[el2_lib.scala 543:51] - node _T_1134 = mux(_T_1130, _T_1132, _T_1133) @[el2_lib.scala 543:23] - _T_1014[19] <= _T_1134 @[el2_lib.scala 543:17] - node _T_1135 = bits(_T_1013, 20, 0) @[el2_lib.scala 543:27] - node _T_1136 = orr(_T_1135) @[el2_lib.scala 543:35] - node _T_1137 = bits(_T_1013, 21, 21) @[el2_lib.scala 543:44] - node _T_1138 = not(_T_1137) @[el2_lib.scala 543:40] - node _T_1139 = bits(_T_1013, 21, 21) @[el2_lib.scala 543:51] - node _T_1140 = mux(_T_1136, _T_1138, _T_1139) @[el2_lib.scala 543:23] - _T_1014[20] <= _T_1140 @[el2_lib.scala 543:17] - node _T_1141 = bits(_T_1013, 21, 0) @[el2_lib.scala 543:27] - node _T_1142 = orr(_T_1141) @[el2_lib.scala 543:35] - node _T_1143 = bits(_T_1013, 22, 22) @[el2_lib.scala 543:44] - node _T_1144 = not(_T_1143) @[el2_lib.scala 543:40] - node _T_1145 = bits(_T_1013, 22, 22) @[el2_lib.scala 543:51] - node _T_1146 = mux(_T_1142, _T_1144, _T_1145) @[el2_lib.scala 543:23] - _T_1014[21] <= _T_1146 @[el2_lib.scala 543:17] - node _T_1147 = bits(_T_1013, 22, 0) @[el2_lib.scala 543:27] - node _T_1148 = orr(_T_1147) @[el2_lib.scala 543:35] - node _T_1149 = bits(_T_1013, 23, 23) @[el2_lib.scala 543:44] - node _T_1150 = not(_T_1149) @[el2_lib.scala 543:40] - node _T_1151 = bits(_T_1013, 23, 23) @[el2_lib.scala 543:51] - node _T_1152 = mux(_T_1148, _T_1150, _T_1151) @[el2_lib.scala 543:23] - _T_1014[22] <= _T_1152 @[el2_lib.scala 543:17] - node _T_1153 = bits(_T_1013, 23, 0) @[el2_lib.scala 543:27] - node _T_1154 = orr(_T_1153) @[el2_lib.scala 543:35] - node _T_1155 = bits(_T_1013, 24, 24) @[el2_lib.scala 543:44] - node _T_1156 = not(_T_1155) @[el2_lib.scala 543:40] - node _T_1157 = bits(_T_1013, 24, 24) @[el2_lib.scala 543:51] - node _T_1158 = mux(_T_1154, _T_1156, _T_1157) @[el2_lib.scala 543:23] - _T_1014[23] <= _T_1158 @[el2_lib.scala 543:17] - node _T_1159 = bits(_T_1013, 24, 0) @[el2_lib.scala 543:27] - node _T_1160 = orr(_T_1159) @[el2_lib.scala 543:35] - node _T_1161 = bits(_T_1013, 25, 25) @[el2_lib.scala 543:44] - node _T_1162 = not(_T_1161) @[el2_lib.scala 543:40] - node _T_1163 = bits(_T_1013, 25, 25) @[el2_lib.scala 543:51] - node _T_1164 = mux(_T_1160, _T_1162, _T_1163) @[el2_lib.scala 543:23] - _T_1014[24] <= _T_1164 @[el2_lib.scala 543:17] - node _T_1165 = bits(_T_1013, 25, 0) @[el2_lib.scala 543:27] - node _T_1166 = orr(_T_1165) @[el2_lib.scala 543:35] - node _T_1167 = bits(_T_1013, 26, 26) @[el2_lib.scala 543:44] - node _T_1168 = not(_T_1167) @[el2_lib.scala 543:40] - node _T_1169 = bits(_T_1013, 26, 26) @[el2_lib.scala 543:51] - node _T_1170 = mux(_T_1166, _T_1168, _T_1169) @[el2_lib.scala 543:23] - _T_1014[25] <= _T_1170 @[el2_lib.scala 543:17] - node _T_1171 = bits(_T_1013, 26, 0) @[el2_lib.scala 543:27] - node _T_1172 = orr(_T_1171) @[el2_lib.scala 543:35] - node _T_1173 = bits(_T_1013, 27, 27) @[el2_lib.scala 543:44] - node _T_1174 = not(_T_1173) @[el2_lib.scala 543:40] - node _T_1175 = bits(_T_1013, 27, 27) @[el2_lib.scala 543:51] - node _T_1176 = mux(_T_1172, _T_1174, _T_1175) @[el2_lib.scala 543:23] - _T_1014[26] <= _T_1176 @[el2_lib.scala 543:17] - node _T_1177 = bits(_T_1013, 27, 0) @[el2_lib.scala 543:27] - node _T_1178 = orr(_T_1177) @[el2_lib.scala 543:35] - node _T_1179 = bits(_T_1013, 28, 28) @[el2_lib.scala 543:44] - node _T_1180 = not(_T_1179) @[el2_lib.scala 543:40] - node _T_1181 = bits(_T_1013, 28, 28) @[el2_lib.scala 543:51] - node _T_1182 = mux(_T_1178, _T_1180, _T_1181) @[el2_lib.scala 543:23] - _T_1014[27] <= _T_1182 @[el2_lib.scala 543:17] - node _T_1183 = bits(_T_1013, 28, 0) @[el2_lib.scala 543:27] - node _T_1184 = orr(_T_1183) @[el2_lib.scala 543:35] - node _T_1185 = bits(_T_1013, 29, 29) @[el2_lib.scala 543:44] - node _T_1186 = not(_T_1185) @[el2_lib.scala 543:40] - node _T_1187 = bits(_T_1013, 29, 29) @[el2_lib.scala 543:51] - node _T_1188 = mux(_T_1184, _T_1186, _T_1187) @[el2_lib.scala 543:23] - _T_1014[28] <= _T_1188 @[el2_lib.scala 543:17] - node _T_1189 = bits(_T_1013, 29, 0) @[el2_lib.scala 543:27] - node _T_1190 = orr(_T_1189) @[el2_lib.scala 543:35] - node _T_1191 = bits(_T_1013, 30, 30) @[el2_lib.scala 543:44] - node _T_1192 = not(_T_1191) @[el2_lib.scala 543:40] - node _T_1193 = bits(_T_1013, 30, 30) @[el2_lib.scala 543:51] - node _T_1194 = mux(_T_1190, _T_1192, _T_1193) @[el2_lib.scala 543:23] - _T_1014[29] <= _T_1194 @[el2_lib.scala 543:17] - node _T_1195 = bits(_T_1013, 30, 0) @[el2_lib.scala 543:27] - node _T_1196 = orr(_T_1195) @[el2_lib.scala 543:35] - node _T_1197 = bits(_T_1013, 31, 31) @[el2_lib.scala 543:44] - node _T_1198 = not(_T_1197) @[el2_lib.scala 543:40] - node _T_1199 = bits(_T_1013, 31, 31) @[el2_lib.scala 543:51] - node _T_1200 = mux(_T_1196, _T_1198, _T_1199) @[el2_lib.scala 543:23] - _T_1014[30] <= _T_1200 @[el2_lib.scala 543:17] - node _T_1201 = cat(_T_1014[2], _T_1014[1]) @[el2_lib.scala 545:14] - node _T_1202 = cat(_T_1201, _T_1014[0]) @[el2_lib.scala 545:14] - node _T_1203 = cat(_T_1014[4], _T_1014[3]) @[el2_lib.scala 545:14] - node _T_1204 = cat(_T_1014[6], _T_1014[5]) @[el2_lib.scala 545:14] - node _T_1205 = cat(_T_1204, _T_1203) @[el2_lib.scala 545:14] - node _T_1206 = cat(_T_1205, _T_1202) @[el2_lib.scala 545:14] - node _T_1207 = cat(_T_1014[8], _T_1014[7]) @[el2_lib.scala 545:14] - node _T_1208 = cat(_T_1014[10], _T_1014[9]) @[el2_lib.scala 545:14] - node _T_1209 = cat(_T_1208, _T_1207) @[el2_lib.scala 545:14] - node _T_1210 = cat(_T_1014[12], _T_1014[11]) @[el2_lib.scala 545:14] - node _T_1211 = cat(_T_1014[14], _T_1014[13]) @[el2_lib.scala 545:14] - node _T_1212 = cat(_T_1211, _T_1210) @[el2_lib.scala 545:14] - node _T_1213 = cat(_T_1212, _T_1209) @[el2_lib.scala 545:14] - node _T_1214 = cat(_T_1213, _T_1206) @[el2_lib.scala 545:14] - node _T_1215 = cat(_T_1014[16], _T_1014[15]) @[el2_lib.scala 545:14] - node _T_1216 = cat(_T_1014[18], _T_1014[17]) @[el2_lib.scala 545:14] - node _T_1217 = cat(_T_1216, _T_1215) @[el2_lib.scala 545:14] - node _T_1218 = cat(_T_1014[20], _T_1014[19]) @[el2_lib.scala 545:14] - node _T_1219 = cat(_T_1014[22], _T_1014[21]) @[el2_lib.scala 545:14] - node _T_1220 = cat(_T_1219, _T_1218) @[el2_lib.scala 545:14] - node _T_1221 = cat(_T_1220, _T_1217) @[el2_lib.scala 545:14] - node _T_1222 = cat(_T_1014[24], _T_1014[23]) @[el2_lib.scala 545:14] - node _T_1223 = cat(_T_1014[26], _T_1014[25]) @[el2_lib.scala 545:14] - node _T_1224 = cat(_T_1223, _T_1222) @[el2_lib.scala 545:14] - node _T_1225 = cat(_T_1014[28], _T_1014[27]) @[el2_lib.scala 545:14] - node _T_1226 = cat(_T_1014[30], _T_1014[29]) @[el2_lib.scala 545:14] - node _T_1227 = cat(_T_1226, _T_1225) @[el2_lib.scala 545:14] - node _T_1228 = cat(_T_1227, _T_1224) @[el2_lib.scala 545:14] - node _T_1229 = cat(_T_1228, _T_1221) @[el2_lib.scala 545:14] - node _T_1230 = cat(_T_1229, _T_1214) @[el2_lib.scala 545:14] - node _T_1231 = bits(_T_1013, 0, 0) @[el2_lib.scala 545:24] + wire _T_1014 : UInt<1>[31] @[lib.scala 401:20] + node _T_1015 = bits(_T_1013, 0, 0) @[lib.scala 403:27] + node _T_1016 = orr(_T_1015) @[lib.scala 403:35] + node _T_1017 = bits(_T_1013, 1, 1) @[lib.scala 403:44] + node _T_1018 = not(_T_1017) @[lib.scala 403:40] + node _T_1019 = bits(_T_1013, 1, 1) @[lib.scala 403:51] + node _T_1020 = mux(_T_1016, _T_1018, _T_1019) @[lib.scala 403:23] + _T_1014[0] <= _T_1020 @[lib.scala 403:17] + node _T_1021 = bits(_T_1013, 1, 0) @[lib.scala 403:27] + node _T_1022 = orr(_T_1021) @[lib.scala 403:35] + node _T_1023 = bits(_T_1013, 2, 2) @[lib.scala 403:44] + node _T_1024 = not(_T_1023) @[lib.scala 403:40] + node _T_1025 = bits(_T_1013, 2, 2) @[lib.scala 403:51] + node _T_1026 = mux(_T_1022, _T_1024, _T_1025) @[lib.scala 403:23] + _T_1014[1] <= _T_1026 @[lib.scala 403:17] + node _T_1027 = bits(_T_1013, 2, 0) @[lib.scala 403:27] + node _T_1028 = orr(_T_1027) @[lib.scala 403:35] + node _T_1029 = bits(_T_1013, 3, 3) @[lib.scala 403:44] + node _T_1030 = not(_T_1029) @[lib.scala 403:40] + node _T_1031 = bits(_T_1013, 3, 3) @[lib.scala 403:51] + node _T_1032 = mux(_T_1028, _T_1030, _T_1031) @[lib.scala 403:23] + _T_1014[2] <= _T_1032 @[lib.scala 403:17] + node _T_1033 = bits(_T_1013, 3, 0) @[lib.scala 403:27] + node _T_1034 = orr(_T_1033) @[lib.scala 403:35] + node _T_1035 = bits(_T_1013, 4, 4) @[lib.scala 403:44] + node _T_1036 = not(_T_1035) @[lib.scala 403:40] + node _T_1037 = bits(_T_1013, 4, 4) @[lib.scala 403:51] + node _T_1038 = mux(_T_1034, _T_1036, _T_1037) @[lib.scala 403:23] + _T_1014[3] <= _T_1038 @[lib.scala 403:17] + node _T_1039 = bits(_T_1013, 4, 0) @[lib.scala 403:27] + node _T_1040 = orr(_T_1039) @[lib.scala 403:35] + node _T_1041 = bits(_T_1013, 5, 5) @[lib.scala 403:44] + node _T_1042 = not(_T_1041) @[lib.scala 403:40] + node _T_1043 = bits(_T_1013, 5, 5) @[lib.scala 403:51] + node _T_1044 = mux(_T_1040, _T_1042, _T_1043) @[lib.scala 403:23] + _T_1014[4] <= _T_1044 @[lib.scala 403:17] + node _T_1045 = bits(_T_1013, 5, 0) @[lib.scala 403:27] + node _T_1046 = orr(_T_1045) @[lib.scala 403:35] + node _T_1047 = bits(_T_1013, 6, 6) @[lib.scala 403:44] + node _T_1048 = not(_T_1047) @[lib.scala 403:40] + node _T_1049 = bits(_T_1013, 6, 6) @[lib.scala 403:51] + node _T_1050 = mux(_T_1046, _T_1048, _T_1049) @[lib.scala 403:23] + _T_1014[5] <= _T_1050 @[lib.scala 403:17] + node _T_1051 = bits(_T_1013, 6, 0) @[lib.scala 403:27] + node _T_1052 = orr(_T_1051) @[lib.scala 403:35] + node _T_1053 = bits(_T_1013, 7, 7) @[lib.scala 403:44] + node _T_1054 = not(_T_1053) @[lib.scala 403:40] + node _T_1055 = bits(_T_1013, 7, 7) @[lib.scala 403:51] + node _T_1056 = mux(_T_1052, _T_1054, _T_1055) @[lib.scala 403:23] + _T_1014[6] <= _T_1056 @[lib.scala 403:17] + node _T_1057 = bits(_T_1013, 7, 0) @[lib.scala 403:27] + node _T_1058 = orr(_T_1057) @[lib.scala 403:35] + node _T_1059 = bits(_T_1013, 8, 8) @[lib.scala 403:44] + node _T_1060 = not(_T_1059) @[lib.scala 403:40] + node _T_1061 = bits(_T_1013, 8, 8) @[lib.scala 403:51] + node _T_1062 = mux(_T_1058, _T_1060, _T_1061) @[lib.scala 403:23] + _T_1014[7] <= _T_1062 @[lib.scala 403:17] + node _T_1063 = bits(_T_1013, 8, 0) @[lib.scala 403:27] + node _T_1064 = orr(_T_1063) @[lib.scala 403:35] + node _T_1065 = bits(_T_1013, 9, 9) @[lib.scala 403:44] + node _T_1066 = not(_T_1065) @[lib.scala 403:40] + node _T_1067 = bits(_T_1013, 9, 9) @[lib.scala 403:51] + node _T_1068 = mux(_T_1064, _T_1066, _T_1067) @[lib.scala 403:23] + _T_1014[8] <= _T_1068 @[lib.scala 403:17] + node _T_1069 = bits(_T_1013, 9, 0) @[lib.scala 403:27] + node _T_1070 = orr(_T_1069) @[lib.scala 403:35] + node _T_1071 = bits(_T_1013, 10, 10) @[lib.scala 403:44] + node _T_1072 = not(_T_1071) @[lib.scala 403:40] + node _T_1073 = bits(_T_1013, 10, 10) @[lib.scala 403:51] + node _T_1074 = mux(_T_1070, _T_1072, _T_1073) @[lib.scala 403:23] + _T_1014[9] <= _T_1074 @[lib.scala 403:17] + node _T_1075 = bits(_T_1013, 10, 0) @[lib.scala 403:27] + node _T_1076 = orr(_T_1075) @[lib.scala 403:35] + node _T_1077 = bits(_T_1013, 11, 11) @[lib.scala 403:44] + node _T_1078 = not(_T_1077) @[lib.scala 403:40] + node _T_1079 = bits(_T_1013, 11, 11) @[lib.scala 403:51] + node _T_1080 = mux(_T_1076, _T_1078, _T_1079) @[lib.scala 403:23] + _T_1014[10] <= _T_1080 @[lib.scala 403:17] + node _T_1081 = bits(_T_1013, 11, 0) @[lib.scala 403:27] + node _T_1082 = orr(_T_1081) @[lib.scala 403:35] + node _T_1083 = bits(_T_1013, 12, 12) @[lib.scala 403:44] + node _T_1084 = not(_T_1083) @[lib.scala 403:40] + node _T_1085 = bits(_T_1013, 12, 12) @[lib.scala 403:51] + node _T_1086 = mux(_T_1082, _T_1084, _T_1085) @[lib.scala 403:23] + _T_1014[11] <= _T_1086 @[lib.scala 403:17] + node _T_1087 = bits(_T_1013, 12, 0) @[lib.scala 403:27] + node _T_1088 = orr(_T_1087) @[lib.scala 403:35] + node _T_1089 = bits(_T_1013, 13, 13) @[lib.scala 403:44] + node _T_1090 = not(_T_1089) @[lib.scala 403:40] + node _T_1091 = bits(_T_1013, 13, 13) @[lib.scala 403:51] + node _T_1092 = mux(_T_1088, _T_1090, _T_1091) @[lib.scala 403:23] + _T_1014[12] <= _T_1092 @[lib.scala 403:17] + node _T_1093 = bits(_T_1013, 13, 0) @[lib.scala 403:27] + node _T_1094 = orr(_T_1093) @[lib.scala 403:35] + node _T_1095 = bits(_T_1013, 14, 14) @[lib.scala 403:44] + node _T_1096 = not(_T_1095) @[lib.scala 403:40] + node _T_1097 = bits(_T_1013, 14, 14) @[lib.scala 403:51] + node _T_1098 = mux(_T_1094, _T_1096, _T_1097) @[lib.scala 403:23] + _T_1014[13] <= _T_1098 @[lib.scala 403:17] + node _T_1099 = bits(_T_1013, 14, 0) @[lib.scala 403:27] + node _T_1100 = orr(_T_1099) @[lib.scala 403:35] + node _T_1101 = bits(_T_1013, 15, 15) @[lib.scala 403:44] + node _T_1102 = not(_T_1101) @[lib.scala 403:40] + node _T_1103 = bits(_T_1013, 15, 15) @[lib.scala 403:51] + node _T_1104 = mux(_T_1100, _T_1102, _T_1103) @[lib.scala 403:23] + _T_1014[14] <= _T_1104 @[lib.scala 403:17] + node _T_1105 = bits(_T_1013, 15, 0) @[lib.scala 403:27] + node _T_1106 = orr(_T_1105) @[lib.scala 403:35] + node _T_1107 = bits(_T_1013, 16, 16) @[lib.scala 403:44] + node _T_1108 = not(_T_1107) @[lib.scala 403:40] + node _T_1109 = bits(_T_1013, 16, 16) @[lib.scala 403:51] + node _T_1110 = mux(_T_1106, _T_1108, _T_1109) @[lib.scala 403:23] + _T_1014[15] <= _T_1110 @[lib.scala 403:17] + node _T_1111 = bits(_T_1013, 16, 0) @[lib.scala 403:27] + node _T_1112 = orr(_T_1111) @[lib.scala 403:35] + node _T_1113 = bits(_T_1013, 17, 17) @[lib.scala 403:44] + node _T_1114 = not(_T_1113) @[lib.scala 403:40] + node _T_1115 = bits(_T_1013, 17, 17) @[lib.scala 403:51] + node _T_1116 = mux(_T_1112, _T_1114, _T_1115) @[lib.scala 403:23] + _T_1014[16] <= _T_1116 @[lib.scala 403:17] + node _T_1117 = bits(_T_1013, 17, 0) @[lib.scala 403:27] + node _T_1118 = orr(_T_1117) @[lib.scala 403:35] + node _T_1119 = bits(_T_1013, 18, 18) @[lib.scala 403:44] + node _T_1120 = not(_T_1119) @[lib.scala 403:40] + node _T_1121 = bits(_T_1013, 18, 18) @[lib.scala 403:51] + node _T_1122 = mux(_T_1118, _T_1120, _T_1121) @[lib.scala 403:23] + _T_1014[17] <= _T_1122 @[lib.scala 403:17] + node _T_1123 = bits(_T_1013, 18, 0) @[lib.scala 403:27] + node _T_1124 = orr(_T_1123) @[lib.scala 403:35] + node _T_1125 = bits(_T_1013, 19, 19) @[lib.scala 403:44] + node _T_1126 = not(_T_1125) @[lib.scala 403:40] + node _T_1127 = bits(_T_1013, 19, 19) @[lib.scala 403:51] + node _T_1128 = mux(_T_1124, _T_1126, _T_1127) @[lib.scala 403:23] + _T_1014[18] <= _T_1128 @[lib.scala 403:17] + node _T_1129 = bits(_T_1013, 19, 0) @[lib.scala 403:27] + node _T_1130 = orr(_T_1129) @[lib.scala 403:35] + node _T_1131 = bits(_T_1013, 20, 20) @[lib.scala 403:44] + node _T_1132 = not(_T_1131) @[lib.scala 403:40] + node _T_1133 = bits(_T_1013, 20, 20) @[lib.scala 403:51] + node _T_1134 = mux(_T_1130, _T_1132, _T_1133) @[lib.scala 403:23] + _T_1014[19] <= _T_1134 @[lib.scala 403:17] + node _T_1135 = bits(_T_1013, 20, 0) @[lib.scala 403:27] + node _T_1136 = orr(_T_1135) @[lib.scala 403:35] + node _T_1137 = bits(_T_1013, 21, 21) @[lib.scala 403:44] + node _T_1138 = not(_T_1137) @[lib.scala 403:40] + node _T_1139 = bits(_T_1013, 21, 21) @[lib.scala 403:51] + node _T_1140 = mux(_T_1136, _T_1138, _T_1139) @[lib.scala 403:23] + _T_1014[20] <= _T_1140 @[lib.scala 403:17] + node _T_1141 = bits(_T_1013, 21, 0) @[lib.scala 403:27] + node _T_1142 = orr(_T_1141) @[lib.scala 403:35] + node _T_1143 = bits(_T_1013, 22, 22) @[lib.scala 403:44] + node _T_1144 = not(_T_1143) @[lib.scala 403:40] + node _T_1145 = bits(_T_1013, 22, 22) @[lib.scala 403:51] + node _T_1146 = mux(_T_1142, _T_1144, _T_1145) @[lib.scala 403:23] + _T_1014[21] <= _T_1146 @[lib.scala 403:17] + node _T_1147 = bits(_T_1013, 22, 0) @[lib.scala 403:27] + node _T_1148 = orr(_T_1147) @[lib.scala 403:35] + node _T_1149 = bits(_T_1013, 23, 23) @[lib.scala 403:44] + node _T_1150 = not(_T_1149) @[lib.scala 403:40] + node _T_1151 = bits(_T_1013, 23, 23) @[lib.scala 403:51] + node _T_1152 = mux(_T_1148, _T_1150, _T_1151) @[lib.scala 403:23] + _T_1014[22] <= _T_1152 @[lib.scala 403:17] + node _T_1153 = bits(_T_1013, 23, 0) @[lib.scala 403:27] + node _T_1154 = orr(_T_1153) @[lib.scala 403:35] + node _T_1155 = bits(_T_1013, 24, 24) @[lib.scala 403:44] + node _T_1156 = not(_T_1155) @[lib.scala 403:40] + node _T_1157 = bits(_T_1013, 24, 24) @[lib.scala 403:51] + node _T_1158 = mux(_T_1154, _T_1156, _T_1157) @[lib.scala 403:23] + _T_1014[23] <= _T_1158 @[lib.scala 403:17] + node _T_1159 = bits(_T_1013, 24, 0) @[lib.scala 403:27] + node _T_1160 = orr(_T_1159) @[lib.scala 403:35] + node _T_1161 = bits(_T_1013, 25, 25) @[lib.scala 403:44] + node _T_1162 = not(_T_1161) @[lib.scala 403:40] + node _T_1163 = bits(_T_1013, 25, 25) @[lib.scala 403:51] + node _T_1164 = mux(_T_1160, _T_1162, _T_1163) @[lib.scala 403:23] + _T_1014[24] <= _T_1164 @[lib.scala 403:17] + node _T_1165 = bits(_T_1013, 25, 0) @[lib.scala 403:27] + node _T_1166 = orr(_T_1165) @[lib.scala 403:35] + node _T_1167 = bits(_T_1013, 26, 26) @[lib.scala 403:44] + node _T_1168 = not(_T_1167) @[lib.scala 403:40] + node _T_1169 = bits(_T_1013, 26, 26) @[lib.scala 403:51] + node _T_1170 = mux(_T_1166, _T_1168, _T_1169) @[lib.scala 403:23] + _T_1014[25] <= _T_1170 @[lib.scala 403:17] + node _T_1171 = bits(_T_1013, 26, 0) @[lib.scala 403:27] + node _T_1172 = orr(_T_1171) @[lib.scala 403:35] + node _T_1173 = bits(_T_1013, 27, 27) @[lib.scala 403:44] + node _T_1174 = not(_T_1173) @[lib.scala 403:40] + node _T_1175 = bits(_T_1013, 27, 27) @[lib.scala 403:51] + node _T_1176 = mux(_T_1172, _T_1174, _T_1175) @[lib.scala 403:23] + _T_1014[26] <= _T_1176 @[lib.scala 403:17] + node _T_1177 = bits(_T_1013, 27, 0) @[lib.scala 403:27] + node _T_1178 = orr(_T_1177) @[lib.scala 403:35] + node _T_1179 = bits(_T_1013, 28, 28) @[lib.scala 403:44] + node _T_1180 = not(_T_1179) @[lib.scala 403:40] + node _T_1181 = bits(_T_1013, 28, 28) @[lib.scala 403:51] + node _T_1182 = mux(_T_1178, _T_1180, _T_1181) @[lib.scala 403:23] + _T_1014[27] <= _T_1182 @[lib.scala 403:17] + node _T_1183 = bits(_T_1013, 28, 0) @[lib.scala 403:27] + node _T_1184 = orr(_T_1183) @[lib.scala 403:35] + node _T_1185 = bits(_T_1013, 29, 29) @[lib.scala 403:44] + node _T_1186 = not(_T_1185) @[lib.scala 403:40] + node _T_1187 = bits(_T_1013, 29, 29) @[lib.scala 403:51] + node _T_1188 = mux(_T_1184, _T_1186, _T_1187) @[lib.scala 403:23] + _T_1014[28] <= _T_1188 @[lib.scala 403:17] + node _T_1189 = bits(_T_1013, 29, 0) @[lib.scala 403:27] + node _T_1190 = orr(_T_1189) @[lib.scala 403:35] + node _T_1191 = bits(_T_1013, 30, 30) @[lib.scala 403:44] + node _T_1192 = not(_T_1191) @[lib.scala 403:40] + node _T_1193 = bits(_T_1013, 30, 30) @[lib.scala 403:51] + node _T_1194 = mux(_T_1190, _T_1192, _T_1193) @[lib.scala 403:23] + _T_1014[29] <= _T_1194 @[lib.scala 403:17] + node _T_1195 = bits(_T_1013, 30, 0) @[lib.scala 403:27] + node _T_1196 = orr(_T_1195) @[lib.scala 403:35] + node _T_1197 = bits(_T_1013, 31, 31) @[lib.scala 403:44] + node _T_1198 = not(_T_1197) @[lib.scala 403:40] + node _T_1199 = bits(_T_1013, 31, 31) @[lib.scala 403:51] + node _T_1200 = mux(_T_1196, _T_1198, _T_1199) @[lib.scala 403:23] + _T_1014[30] <= _T_1200 @[lib.scala 403:17] + node _T_1201 = cat(_T_1014[2], _T_1014[1]) @[lib.scala 405:14] + node _T_1202 = cat(_T_1201, _T_1014[0]) @[lib.scala 405:14] + node _T_1203 = cat(_T_1014[4], _T_1014[3]) @[lib.scala 405:14] + node _T_1204 = cat(_T_1014[6], _T_1014[5]) @[lib.scala 405:14] + node _T_1205 = cat(_T_1204, _T_1203) @[lib.scala 405:14] + node _T_1206 = cat(_T_1205, _T_1202) @[lib.scala 405:14] + node _T_1207 = cat(_T_1014[8], _T_1014[7]) @[lib.scala 405:14] + node _T_1208 = cat(_T_1014[10], _T_1014[9]) @[lib.scala 405:14] + node _T_1209 = cat(_T_1208, _T_1207) @[lib.scala 405:14] + node _T_1210 = cat(_T_1014[12], _T_1014[11]) @[lib.scala 405:14] + node _T_1211 = cat(_T_1014[14], _T_1014[13]) @[lib.scala 405:14] + node _T_1212 = cat(_T_1211, _T_1210) @[lib.scala 405:14] + node _T_1213 = cat(_T_1212, _T_1209) @[lib.scala 405:14] + node _T_1214 = cat(_T_1213, _T_1206) @[lib.scala 405:14] + node _T_1215 = cat(_T_1014[16], _T_1014[15]) @[lib.scala 405:14] + node _T_1216 = cat(_T_1014[18], _T_1014[17]) @[lib.scala 405:14] + node _T_1217 = cat(_T_1216, _T_1215) @[lib.scala 405:14] + node _T_1218 = cat(_T_1014[20], _T_1014[19]) @[lib.scala 405:14] + node _T_1219 = cat(_T_1014[22], _T_1014[21]) @[lib.scala 405:14] + node _T_1220 = cat(_T_1219, _T_1218) @[lib.scala 405:14] + node _T_1221 = cat(_T_1220, _T_1217) @[lib.scala 405:14] + node _T_1222 = cat(_T_1014[24], _T_1014[23]) @[lib.scala 405:14] + node _T_1223 = cat(_T_1014[26], _T_1014[25]) @[lib.scala 405:14] + node _T_1224 = cat(_T_1223, _T_1222) @[lib.scala 405:14] + node _T_1225 = cat(_T_1014[28], _T_1014[27]) @[lib.scala 405:14] + node _T_1226 = cat(_T_1014[30], _T_1014[29]) @[lib.scala 405:14] + node _T_1227 = cat(_T_1226, _T_1225) @[lib.scala 405:14] + node _T_1228 = cat(_T_1227, _T_1224) @[lib.scala 405:14] + node _T_1229 = cat(_T_1228, _T_1221) @[lib.scala 405:14] + node _T_1230 = cat(_T_1229, _T_1214) @[lib.scala 405:14] + node _T_1231 = bits(_T_1013, 0, 0) @[lib.scala 405:24] node _T_1232 = cat(_T_1230, _T_1231) @[Cat.scala 29:58] node _T_1233 = bits(q_ff, 31, 0) @[exu_div_ctl.scala 183:104] node q_ff_eff = mux(_T_1012, _T_1232, _T_1233) @[exu_div_ctl.scala 183:21] node _T_1234 = and(sign_ff, dividend_neg_ff) @[exu_div_ctl.scala 184:31] node _T_1235 = bits(_T_1234, 0, 0) @[exu_div_ctl.scala 184:51] node _T_1236 = bits(a_ff, 31, 0) @[exu_div_ctl.scala 184:74] - wire _T_1237 : UInt<1>[31] @[el2_lib.scala 541:20] - node _T_1238 = bits(_T_1236, 0, 0) @[el2_lib.scala 543:27] - node _T_1239 = orr(_T_1238) @[el2_lib.scala 543:35] - node _T_1240 = bits(_T_1236, 1, 1) @[el2_lib.scala 543:44] - node _T_1241 = not(_T_1240) @[el2_lib.scala 543:40] - node _T_1242 = bits(_T_1236, 1, 1) @[el2_lib.scala 543:51] - node _T_1243 = mux(_T_1239, _T_1241, _T_1242) @[el2_lib.scala 543:23] - _T_1237[0] <= _T_1243 @[el2_lib.scala 543:17] - node _T_1244 = bits(_T_1236, 1, 0) @[el2_lib.scala 543:27] - node _T_1245 = orr(_T_1244) @[el2_lib.scala 543:35] - node _T_1246 = bits(_T_1236, 2, 2) @[el2_lib.scala 543:44] - node _T_1247 = not(_T_1246) @[el2_lib.scala 543:40] - node _T_1248 = bits(_T_1236, 2, 2) @[el2_lib.scala 543:51] - node _T_1249 = mux(_T_1245, _T_1247, _T_1248) @[el2_lib.scala 543:23] - _T_1237[1] <= _T_1249 @[el2_lib.scala 543:17] - node _T_1250 = bits(_T_1236, 2, 0) @[el2_lib.scala 543:27] - node _T_1251 = orr(_T_1250) @[el2_lib.scala 543:35] - node _T_1252 = bits(_T_1236, 3, 3) @[el2_lib.scala 543:44] - node _T_1253 = not(_T_1252) @[el2_lib.scala 543:40] - node _T_1254 = bits(_T_1236, 3, 3) @[el2_lib.scala 543:51] - node _T_1255 = mux(_T_1251, _T_1253, _T_1254) @[el2_lib.scala 543:23] - _T_1237[2] <= _T_1255 @[el2_lib.scala 543:17] - node _T_1256 = bits(_T_1236, 3, 0) @[el2_lib.scala 543:27] - node _T_1257 = orr(_T_1256) @[el2_lib.scala 543:35] - node _T_1258 = bits(_T_1236, 4, 4) @[el2_lib.scala 543:44] - node _T_1259 = not(_T_1258) @[el2_lib.scala 543:40] - node _T_1260 = bits(_T_1236, 4, 4) @[el2_lib.scala 543:51] - node _T_1261 = mux(_T_1257, _T_1259, _T_1260) @[el2_lib.scala 543:23] - _T_1237[3] <= _T_1261 @[el2_lib.scala 543:17] - node _T_1262 = bits(_T_1236, 4, 0) @[el2_lib.scala 543:27] - node _T_1263 = orr(_T_1262) @[el2_lib.scala 543:35] - node _T_1264 = bits(_T_1236, 5, 5) @[el2_lib.scala 543:44] - node _T_1265 = not(_T_1264) @[el2_lib.scala 543:40] - node _T_1266 = bits(_T_1236, 5, 5) @[el2_lib.scala 543:51] - node _T_1267 = mux(_T_1263, _T_1265, _T_1266) @[el2_lib.scala 543:23] - _T_1237[4] <= _T_1267 @[el2_lib.scala 543:17] - node _T_1268 = bits(_T_1236, 5, 0) @[el2_lib.scala 543:27] - node _T_1269 = orr(_T_1268) @[el2_lib.scala 543:35] - node _T_1270 = bits(_T_1236, 6, 6) @[el2_lib.scala 543:44] - node _T_1271 = not(_T_1270) @[el2_lib.scala 543:40] - node _T_1272 = bits(_T_1236, 6, 6) @[el2_lib.scala 543:51] - node _T_1273 = mux(_T_1269, _T_1271, _T_1272) @[el2_lib.scala 543:23] - _T_1237[5] <= _T_1273 @[el2_lib.scala 543:17] - node _T_1274 = bits(_T_1236, 6, 0) @[el2_lib.scala 543:27] - node _T_1275 = orr(_T_1274) @[el2_lib.scala 543:35] - node _T_1276 = bits(_T_1236, 7, 7) @[el2_lib.scala 543:44] - node _T_1277 = not(_T_1276) @[el2_lib.scala 543:40] - node _T_1278 = bits(_T_1236, 7, 7) @[el2_lib.scala 543:51] - node _T_1279 = mux(_T_1275, _T_1277, _T_1278) @[el2_lib.scala 543:23] - _T_1237[6] <= _T_1279 @[el2_lib.scala 543:17] - node _T_1280 = bits(_T_1236, 7, 0) @[el2_lib.scala 543:27] - node _T_1281 = orr(_T_1280) @[el2_lib.scala 543:35] - node _T_1282 = bits(_T_1236, 8, 8) @[el2_lib.scala 543:44] - node _T_1283 = not(_T_1282) @[el2_lib.scala 543:40] - node _T_1284 = bits(_T_1236, 8, 8) @[el2_lib.scala 543:51] - node _T_1285 = mux(_T_1281, _T_1283, _T_1284) @[el2_lib.scala 543:23] - _T_1237[7] <= _T_1285 @[el2_lib.scala 543:17] - node _T_1286 = bits(_T_1236, 8, 0) @[el2_lib.scala 543:27] - node _T_1287 = orr(_T_1286) @[el2_lib.scala 543:35] - node _T_1288 = bits(_T_1236, 9, 9) @[el2_lib.scala 543:44] - node _T_1289 = not(_T_1288) @[el2_lib.scala 543:40] - node _T_1290 = bits(_T_1236, 9, 9) @[el2_lib.scala 543:51] - node _T_1291 = mux(_T_1287, _T_1289, _T_1290) @[el2_lib.scala 543:23] - _T_1237[8] <= _T_1291 @[el2_lib.scala 543:17] - node _T_1292 = bits(_T_1236, 9, 0) @[el2_lib.scala 543:27] - node _T_1293 = orr(_T_1292) @[el2_lib.scala 543:35] - node _T_1294 = bits(_T_1236, 10, 10) @[el2_lib.scala 543:44] - node _T_1295 = not(_T_1294) @[el2_lib.scala 543:40] - node _T_1296 = bits(_T_1236, 10, 10) @[el2_lib.scala 543:51] - node _T_1297 = mux(_T_1293, _T_1295, _T_1296) @[el2_lib.scala 543:23] - _T_1237[9] <= _T_1297 @[el2_lib.scala 543:17] - node _T_1298 = bits(_T_1236, 10, 0) @[el2_lib.scala 543:27] - node _T_1299 = orr(_T_1298) @[el2_lib.scala 543:35] - node _T_1300 = bits(_T_1236, 11, 11) @[el2_lib.scala 543:44] - node _T_1301 = not(_T_1300) @[el2_lib.scala 543:40] - node _T_1302 = bits(_T_1236, 11, 11) @[el2_lib.scala 543:51] - node _T_1303 = mux(_T_1299, _T_1301, _T_1302) @[el2_lib.scala 543:23] - _T_1237[10] <= _T_1303 @[el2_lib.scala 543:17] - node _T_1304 = bits(_T_1236, 11, 0) @[el2_lib.scala 543:27] - node _T_1305 = orr(_T_1304) @[el2_lib.scala 543:35] - node _T_1306 = bits(_T_1236, 12, 12) @[el2_lib.scala 543:44] - node _T_1307 = not(_T_1306) @[el2_lib.scala 543:40] - node _T_1308 = bits(_T_1236, 12, 12) @[el2_lib.scala 543:51] - node _T_1309 = mux(_T_1305, _T_1307, _T_1308) @[el2_lib.scala 543:23] - _T_1237[11] <= _T_1309 @[el2_lib.scala 543:17] - node _T_1310 = bits(_T_1236, 12, 0) @[el2_lib.scala 543:27] - node _T_1311 = orr(_T_1310) @[el2_lib.scala 543:35] - node _T_1312 = bits(_T_1236, 13, 13) @[el2_lib.scala 543:44] - node _T_1313 = not(_T_1312) @[el2_lib.scala 543:40] - node _T_1314 = bits(_T_1236, 13, 13) @[el2_lib.scala 543:51] - node _T_1315 = mux(_T_1311, _T_1313, _T_1314) @[el2_lib.scala 543:23] - _T_1237[12] <= _T_1315 @[el2_lib.scala 543:17] - node _T_1316 = bits(_T_1236, 13, 0) @[el2_lib.scala 543:27] - node _T_1317 = orr(_T_1316) @[el2_lib.scala 543:35] - node _T_1318 = bits(_T_1236, 14, 14) @[el2_lib.scala 543:44] - node _T_1319 = not(_T_1318) @[el2_lib.scala 543:40] - node _T_1320 = bits(_T_1236, 14, 14) @[el2_lib.scala 543:51] - node _T_1321 = mux(_T_1317, _T_1319, _T_1320) @[el2_lib.scala 543:23] - _T_1237[13] <= _T_1321 @[el2_lib.scala 543:17] - node _T_1322 = bits(_T_1236, 14, 0) @[el2_lib.scala 543:27] - node _T_1323 = orr(_T_1322) @[el2_lib.scala 543:35] - node _T_1324 = bits(_T_1236, 15, 15) @[el2_lib.scala 543:44] - node _T_1325 = not(_T_1324) @[el2_lib.scala 543:40] - node _T_1326 = bits(_T_1236, 15, 15) @[el2_lib.scala 543:51] - node _T_1327 = mux(_T_1323, _T_1325, _T_1326) @[el2_lib.scala 543:23] - _T_1237[14] <= _T_1327 @[el2_lib.scala 543:17] - node _T_1328 = bits(_T_1236, 15, 0) @[el2_lib.scala 543:27] - node _T_1329 = orr(_T_1328) @[el2_lib.scala 543:35] - node _T_1330 = bits(_T_1236, 16, 16) @[el2_lib.scala 543:44] - node _T_1331 = not(_T_1330) @[el2_lib.scala 543:40] - node _T_1332 = bits(_T_1236, 16, 16) @[el2_lib.scala 543:51] - node _T_1333 = mux(_T_1329, _T_1331, _T_1332) @[el2_lib.scala 543:23] - _T_1237[15] <= _T_1333 @[el2_lib.scala 543:17] - node _T_1334 = bits(_T_1236, 16, 0) @[el2_lib.scala 543:27] - node _T_1335 = orr(_T_1334) @[el2_lib.scala 543:35] - node _T_1336 = bits(_T_1236, 17, 17) @[el2_lib.scala 543:44] - node _T_1337 = not(_T_1336) @[el2_lib.scala 543:40] - node _T_1338 = bits(_T_1236, 17, 17) @[el2_lib.scala 543:51] - node _T_1339 = mux(_T_1335, _T_1337, _T_1338) @[el2_lib.scala 543:23] - _T_1237[16] <= _T_1339 @[el2_lib.scala 543:17] - node _T_1340 = bits(_T_1236, 17, 0) @[el2_lib.scala 543:27] - node _T_1341 = orr(_T_1340) @[el2_lib.scala 543:35] - node _T_1342 = bits(_T_1236, 18, 18) @[el2_lib.scala 543:44] - node _T_1343 = not(_T_1342) @[el2_lib.scala 543:40] - node _T_1344 = bits(_T_1236, 18, 18) @[el2_lib.scala 543:51] - node _T_1345 = mux(_T_1341, _T_1343, _T_1344) @[el2_lib.scala 543:23] - _T_1237[17] <= _T_1345 @[el2_lib.scala 543:17] - node _T_1346 = bits(_T_1236, 18, 0) @[el2_lib.scala 543:27] - node _T_1347 = orr(_T_1346) @[el2_lib.scala 543:35] - node _T_1348 = bits(_T_1236, 19, 19) @[el2_lib.scala 543:44] - node _T_1349 = not(_T_1348) @[el2_lib.scala 543:40] - node _T_1350 = bits(_T_1236, 19, 19) @[el2_lib.scala 543:51] - node _T_1351 = mux(_T_1347, _T_1349, _T_1350) @[el2_lib.scala 543:23] - _T_1237[18] <= _T_1351 @[el2_lib.scala 543:17] - node _T_1352 = bits(_T_1236, 19, 0) @[el2_lib.scala 543:27] - node _T_1353 = orr(_T_1352) @[el2_lib.scala 543:35] - node _T_1354 = bits(_T_1236, 20, 20) @[el2_lib.scala 543:44] - node _T_1355 = not(_T_1354) @[el2_lib.scala 543:40] - node _T_1356 = bits(_T_1236, 20, 20) @[el2_lib.scala 543:51] - node _T_1357 = mux(_T_1353, _T_1355, _T_1356) @[el2_lib.scala 543:23] - _T_1237[19] <= _T_1357 @[el2_lib.scala 543:17] - node _T_1358 = bits(_T_1236, 20, 0) @[el2_lib.scala 543:27] - node _T_1359 = orr(_T_1358) @[el2_lib.scala 543:35] - node _T_1360 = bits(_T_1236, 21, 21) @[el2_lib.scala 543:44] - node _T_1361 = not(_T_1360) @[el2_lib.scala 543:40] - node _T_1362 = bits(_T_1236, 21, 21) @[el2_lib.scala 543:51] - node _T_1363 = mux(_T_1359, _T_1361, _T_1362) @[el2_lib.scala 543:23] - _T_1237[20] <= _T_1363 @[el2_lib.scala 543:17] - node _T_1364 = bits(_T_1236, 21, 0) @[el2_lib.scala 543:27] - node _T_1365 = orr(_T_1364) @[el2_lib.scala 543:35] - node _T_1366 = bits(_T_1236, 22, 22) @[el2_lib.scala 543:44] - node _T_1367 = not(_T_1366) @[el2_lib.scala 543:40] - node _T_1368 = bits(_T_1236, 22, 22) @[el2_lib.scala 543:51] - node _T_1369 = mux(_T_1365, _T_1367, _T_1368) @[el2_lib.scala 543:23] - _T_1237[21] <= _T_1369 @[el2_lib.scala 543:17] - node _T_1370 = bits(_T_1236, 22, 0) @[el2_lib.scala 543:27] - node _T_1371 = orr(_T_1370) @[el2_lib.scala 543:35] - node _T_1372 = bits(_T_1236, 23, 23) @[el2_lib.scala 543:44] - node _T_1373 = not(_T_1372) @[el2_lib.scala 543:40] - node _T_1374 = bits(_T_1236, 23, 23) @[el2_lib.scala 543:51] - node _T_1375 = mux(_T_1371, _T_1373, _T_1374) @[el2_lib.scala 543:23] - _T_1237[22] <= _T_1375 @[el2_lib.scala 543:17] - node _T_1376 = bits(_T_1236, 23, 0) @[el2_lib.scala 543:27] - node _T_1377 = orr(_T_1376) @[el2_lib.scala 543:35] - node _T_1378 = bits(_T_1236, 24, 24) @[el2_lib.scala 543:44] - node _T_1379 = not(_T_1378) @[el2_lib.scala 543:40] - node _T_1380 = bits(_T_1236, 24, 24) @[el2_lib.scala 543:51] - node _T_1381 = mux(_T_1377, _T_1379, _T_1380) @[el2_lib.scala 543:23] - _T_1237[23] <= _T_1381 @[el2_lib.scala 543:17] - node _T_1382 = bits(_T_1236, 24, 0) @[el2_lib.scala 543:27] - node _T_1383 = orr(_T_1382) @[el2_lib.scala 543:35] - node _T_1384 = bits(_T_1236, 25, 25) @[el2_lib.scala 543:44] - node _T_1385 = not(_T_1384) @[el2_lib.scala 543:40] - node _T_1386 = bits(_T_1236, 25, 25) @[el2_lib.scala 543:51] - node _T_1387 = mux(_T_1383, _T_1385, _T_1386) @[el2_lib.scala 543:23] - _T_1237[24] <= _T_1387 @[el2_lib.scala 543:17] - node _T_1388 = bits(_T_1236, 25, 0) @[el2_lib.scala 543:27] - node _T_1389 = orr(_T_1388) @[el2_lib.scala 543:35] - node _T_1390 = bits(_T_1236, 26, 26) @[el2_lib.scala 543:44] - node _T_1391 = not(_T_1390) @[el2_lib.scala 543:40] - node _T_1392 = bits(_T_1236, 26, 26) @[el2_lib.scala 543:51] - node _T_1393 = mux(_T_1389, _T_1391, _T_1392) @[el2_lib.scala 543:23] - _T_1237[25] <= _T_1393 @[el2_lib.scala 543:17] - node _T_1394 = bits(_T_1236, 26, 0) @[el2_lib.scala 543:27] - node _T_1395 = orr(_T_1394) @[el2_lib.scala 543:35] - node _T_1396 = bits(_T_1236, 27, 27) @[el2_lib.scala 543:44] - node _T_1397 = not(_T_1396) @[el2_lib.scala 543:40] - node _T_1398 = bits(_T_1236, 27, 27) @[el2_lib.scala 543:51] - node _T_1399 = mux(_T_1395, _T_1397, _T_1398) @[el2_lib.scala 543:23] - _T_1237[26] <= _T_1399 @[el2_lib.scala 543:17] - node _T_1400 = bits(_T_1236, 27, 0) @[el2_lib.scala 543:27] - node _T_1401 = orr(_T_1400) @[el2_lib.scala 543:35] - node _T_1402 = bits(_T_1236, 28, 28) @[el2_lib.scala 543:44] - node _T_1403 = not(_T_1402) @[el2_lib.scala 543:40] - node _T_1404 = bits(_T_1236, 28, 28) @[el2_lib.scala 543:51] - node _T_1405 = mux(_T_1401, _T_1403, _T_1404) @[el2_lib.scala 543:23] - _T_1237[27] <= _T_1405 @[el2_lib.scala 543:17] - node _T_1406 = bits(_T_1236, 28, 0) @[el2_lib.scala 543:27] - node _T_1407 = orr(_T_1406) @[el2_lib.scala 543:35] - node _T_1408 = bits(_T_1236, 29, 29) @[el2_lib.scala 543:44] - node _T_1409 = not(_T_1408) @[el2_lib.scala 543:40] - node _T_1410 = bits(_T_1236, 29, 29) @[el2_lib.scala 543:51] - node _T_1411 = mux(_T_1407, _T_1409, _T_1410) @[el2_lib.scala 543:23] - _T_1237[28] <= _T_1411 @[el2_lib.scala 543:17] - node _T_1412 = bits(_T_1236, 29, 0) @[el2_lib.scala 543:27] - node _T_1413 = orr(_T_1412) @[el2_lib.scala 543:35] - node _T_1414 = bits(_T_1236, 30, 30) @[el2_lib.scala 543:44] - node _T_1415 = not(_T_1414) @[el2_lib.scala 543:40] - node _T_1416 = bits(_T_1236, 30, 30) @[el2_lib.scala 543:51] - node _T_1417 = mux(_T_1413, _T_1415, _T_1416) @[el2_lib.scala 543:23] - _T_1237[29] <= _T_1417 @[el2_lib.scala 543:17] - node _T_1418 = bits(_T_1236, 30, 0) @[el2_lib.scala 543:27] - node _T_1419 = orr(_T_1418) @[el2_lib.scala 543:35] - node _T_1420 = bits(_T_1236, 31, 31) @[el2_lib.scala 543:44] - node _T_1421 = not(_T_1420) @[el2_lib.scala 543:40] - node _T_1422 = bits(_T_1236, 31, 31) @[el2_lib.scala 543:51] - node _T_1423 = mux(_T_1419, _T_1421, _T_1422) @[el2_lib.scala 543:23] - _T_1237[30] <= _T_1423 @[el2_lib.scala 543:17] - node _T_1424 = cat(_T_1237[2], _T_1237[1]) @[el2_lib.scala 545:14] - node _T_1425 = cat(_T_1424, _T_1237[0]) @[el2_lib.scala 545:14] - node _T_1426 = cat(_T_1237[4], _T_1237[3]) @[el2_lib.scala 545:14] - node _T_1427 = cat(_T_1237[6], _T_1237[5]) @[el2_lib.scala 545:14] - node _T_1428 = cat(_T_1427, _T_1426) @[el2_lib.scala 545:14] - node _T_1429 = cat(_T_1428, _T_1425) @[el2_lib.scala 545:14] - node _T_1430 = cat(_T_1237[8], _T_1237[7]) @[el2_lib.scala 545:14] - node _T_1431 = cat(_T_1237[10], _T_1237[9]) @[el2_lib.scala 545:14] - node _T_1432 = cat(_T_1431, _T_1430) @[el2_lib.scala 545:14] - node _T_1433 = cat(_T_1237[12], _T_1237[11]) @[el2_lib.scala 545:14] - node _T_1434 = cat(_T_1237[14], _T_1237[13]) @[el2_lib.scala 545:14] - node _T_1435 = cat(_T_1434, _T_1433) @[el2_lib.scala 545:14] - node _T_1436 = cat(_T_1435, _T_1432) @[el2_lib.scala 545:14] - node _T_1437 = cat(_T_1436, _T_1429) @[el2_lib.scala 545:14] - node _T_1438 = cat(_T_1237[16], _T_1237[15]) @[el2_lib.scala 545:14] - node _T_1439 = cat(_T_1237[18], _T_1237[17]) @[el2_lib.scala 545:14] - node _T_1440 = cat(_T_1439, _T_1438) @[el2_lib.scala 545:14] - node _T_1441 = cat(_T_1237[20], _T_1237[19]) @[el2_lib.scala 545:14] - node _T_1442 = cat(_T_1237[22], _T_1237[21]) @[el2_lib.scala 545:14] - node _T_1443 = cat(_T_1442, _T_1441) @[el2_lib.scala 545:14] - node _T_1444 = cat(_T_1443, _T_1440) @[el2_lib.scala 545:14] - node _T_1445 = cat(_T_1237[24], _T_1237[23]) @[el2_lib.scala 545:14] - node _T_1446 = cat(_T_1237[26], _T_1237[25]) @[el2_lib.scala 545:14] - node _T_1447 = cat(_T_1446, _T_1445) @[el2_lib.scala 545:14] - node _T_1448 = cat(_T_1237[28], _T_1237[27]) @[el2_lib.scala 545:14] - node _T_1449 = cat(_T_1237[30], _T_1237[29]) @[el2_lib.scala 545:14] - node _T_1450 = cat(_T_1449, _T_1448) @[el2_lib.scala 545:14] - node _T_1451 = cat(_T_1450, _T_1447) @[el2_lib.scala 545:14] - node _T_1452 = cat(_T_1451, _T_1444) @[el2_lib.scala 545:14] - node _T_1453 = cat(_T_1452, _T_1437) @[el2_lib.scala 545:14] - node _T_1454 = bits(_T_1236, 0, 0) @[el2_lib.scala 545:24] + wire _T_1237 : UInt<1>[31] @[lib.scala 401:20] + node _T_1238 = bits(_T_1236, 0, 0) @[lib.scala 403:27] + node _T_1239 = orr(_T_1238) @[lib.scala 403:35] + node _T_1240 = bits(_T_1236, 1, 1) @[lib.scala 403:44] + node _T_1241 = not(_T_1240) @[lib.scala 403:40] + node _T_1242 = bits(_T_1236, 1, 1) @[lib.scala 403:51] + node _T_1243 = mux(_T_1239, _T_1241, _T_1242) @[lib.scala 403:23] + _T_1237[0] <= _T_1243 @[lib.scala 403:17] + node _T_1244 = bits(_T_1236, 1, 0) @[lib.scala 403:27] + node _T_1245 = orr(_T_1244) @[lib.scala 403:35] + node _T_1246 = bits(_T_1236, 2, 2) @[lib.scala 403:44] + node _T_1247 = not(_T_1246) @[lib.scala 403:40] + node _T_1248 = bits(_T_1236, 2, 2) @[lib.scala 403:51] + node _T_1249 = mux(_T_1245, _T_1247, _T_1248) @[lib.scala 403:23] + _T_1237[1] <= _T_1249 @[lib.scala 403:17] + node _T_1250 = bits(_T_1236, 2, 0) @[lib.scala 403:27] + node _T_1251 = orr(_T_1250) @[lib.scala 403:35] + node _T_1252 = bits(_T_1236, 3, 3) @[lib.scala 403:44] + node _T_1253 = not(_T_1252) @[lib.scala 403:40] + node _T_1254 = bits(_T_1236, 3, 3) @[lib.scala 403:51] + node _T_1255 = mux(_T_1251, _T_1253, _T_1254) @[lib.scala 403:23] + _T_1237[2] <= _T_1255 @[lib.scala 403:17] + node _T_1256 = bits(_T_1236, 3, 0) @[lib.scala 403:27] + node _T_1257 = orr(_T_1256) @[lib.scala 403:35] + node _T_1258 = bits(_T_1236, 4, 4) @[lib.scala 403:44] + node _T_1259 = not(_T_1258) @[lib.scala 403:40] + node _T_1260 = bits(_T_1236, 4, 4) @[lib.scala 403:51] + node _T_1261 = mux(_T_1257, _T_1259, _T_1260) @[lib.scala 403:23] + _T_1237[3] <= _T_1261 @[lib.scala 403:17] + node _T_1262 = bits(_T_1236, 4, 0) @[lib.scala 403:27] + node _T_1263 = orr(_T_1262) @[lib.scala 403:35] + node _T_1264 = bits(_T_1236, 5, 5) @[lib.scala 403:44] + node _T_1265 = not(_T_1264) @[lib.scala 403:40] + node _T_1266 = bits(_T_1236, 5, 5) @[lib.scala 403:51] + node _T_1267 = mux(_T_1263, _T_1265, _T_1266) @[lib.scala 403:23] + _T_1237[4] <= _T_1267 @[lib.scala 403:17] + node _T_1268 = bits(_T_1236, 5, 0) @[lib.scala 403:27] + node _T_1269 = orr(_T_1268) @[lib.scala 403:35] + node _T_1270 = bits(_T_1236, 6, 6) @[lib.scala 403:44] + node _T_1271 = not(_T_1270) @[lib.scala 403:40] + node _T_1272 = bits(_T_1236, 6, 6) @[lib.scala 403:51] + node _T_1273 = mux(_T_1269, _T_1271, _T_1272) @[lib.scala 403:23] + _T_1237[5] <= _T_1273 @[lib.scala 403:17] + node _T_1274 = bits(_T_1236, 6, 0) @[lib.scala 403:27] + node _T_1275 = orr(_T_1274) @[lib.scala 403:35] + node _T_1276 = bits(_T_1236, 7, 7) @[lib.scala 403:44] + node _T_1277 = not(_T_1276) @[lib.scala 403:40] + node _T_1278 = bits(_T_1236, 7, 7) @[lib.scala 403:51] + node _T_1279 = mux(_T_1275, _T_1277, _T_1278) @[lib.scala 403:23] + _T_1237[6] <= _T_1279 @[lib.scala 403:17] + node _T_1280 = bits(_T_1236, 7, 0) @[lib.scala 403:27] + node _T_1281 = orr(_T_1280) @[lib.scala 403:35] + node _T_1282 = bits(_T_1236, 8, 8) @[lib.scala 403:44] + node _T_1283 = not(_T_1282) @[lib.scala 403:40] + node _T_1284 = bits(_T_1236, 8, 8) @[lib.scala 403:51] + node _T_1285 = mux(_T_1281, _T_1283, _T_1284) @[lib.scala 403:23] + _T_1237[7] <= _T_1285 @[lib.scala 403:17] + node _T_1286 = bits(_T_1236, 8, 0) @[lib.scala 403:27] + node _T_1287 = orr(_T_1286) @[lib.scala 403:35] + node _T_1288 = bits(_T_1236, 9, 9) @[lib.scala 403:44] + node _T_1289 = not(_T_1288) @[lib.scala 403:40] + node _T_1290 = bits(_T_1236, 9, 9) @[lib.scala 403:51] + node _T_1291 = mux(_T_1287, _T_1289, _T_1290) @[lib.scala 403:23] + _T_1237[8] <= _T_1291 @[lib.scala 403:17] + node _T_1292 = bits(_T_1236, 9, 0) @[lib.scala 403:27] + node _T_1293 = orr(_T_1292) @[lib.scala 403:35] + node _T_1294 = bits(_T_1236, 10, 10) @[lib.scala 403:44] + node _T_1295 = not(_T_1294) @[lib.scala 403:40] + node _T_1296 = bits(_T_1236, 10, 10) @[lib.scala 403:51] + node _T_1297 = mux(_T_1293, _T_1295, _T_1296) @[lib.scala 403:23] + _T_1237[9] <= _T_1297 @[lib.scala 403:17] + node _T_1298 = bits(_T_1236, 10, 0) @[lib.scala 403:27] + node _T_1299 = orr(_T_1298) @[lib.scala 403:35] + node _T_1300 = bits(_T_1236, 11, 11) @[lib.scala 403:44] + node _T_1301 = not(_T_1300) @[lib.scala 403:40] + node _T_1302 = bits(_T_1236, 11, 11) @[lib.scala 403:51] + node _T_1303 = mux(_T_1299, _T_1301, _T_1302) @[lib.scala 403:23] + _T_1237[10] <= _T_1303 @[lib.scala 403:17] + node _T_1304 = bits(_T_1236, 11, 0) @[lib.scala 403:27] + node _T_1305 = orr(_T_1304) @[lib.scala 403:35] + node _T_1306 = bits(_T_1236, 12, 12) @[lib.scala 403:44] + node _T_1307 = not(_T_1306) @[lib.scala 403:40] + node _T_1308 = bits(_T_1236, 12, 12) @[lib.scala 403:51] + node _T_1309 = mux(_T_1305, _T_1307, _T_1308) @[lib.scala 403:23] + _T_1237[11] <= _T_1309 @[lib.scala 403:17] + node _T_1310 = bits(_T_1236, 12, 0) @[lib.scala 403:27] + node _T_1311 = orr(_T_1310) @[lib.scala 403:35] + node _T_1312 = bits(_T_1236, 13, 13) @[lib.scala 403:44] + node _T_1313 = not(_T_1312) @[lib.scala 403:40] + node _T_1314 = bits(_T_1236, 13, 13) @[lib.scala 403:51] + node _T_1315 = mux(_T_1311, _T_1313, _T_1314) @[lib.scala 403:23] + _T_1237[12] <= _T_1315 @[lib.scala 403:17] + node _T_1316 = bits(_T_1236, 13, 0) @[lib.scala 403:27] + node _T_1317 = orr(_T_1316) @[lib.scala 403:35] + node _T_1318 = bits(_T_1236, 14, 14) @[lib.scala 403:44] + node _T_1319 = not(_T_1318) @[lib.scala 403:40] + node _T_1320 = bits(_T_1236, 14, 14) @[lib.scala 403:51] + node _T_1321 = mux(_T_1317, _T_1319, _T_1320) @[lib.scala 403:23] + _T_1237[13] <= _T_1321 @[lib.scala 403:17] + node _T_1322 = bits(_T_1236, 14, 0) @[lib.scala 403:27] + node _T_1323 = orr(_T_1322) @[lib.scala 403:35] + node _T_1324 = bits(_T_1236, 15, 15) @[lib.scala 403:44] + node _T_1325 = not(_T_1324) @[lib.scala 403:40] + node _T_1326 = bits(_T_1236, 15, 15) @[lib.scala 403:51] + node _T_1327 = mux(_T_1323, _T_1325, _T_1326) @[lib.scala 403:23] + _T_1237[14] <= _T_1327 @[lib.scala 403:17] + node _T_1328 = bits(_T_1236, 15, 0) @[lib.scala 403:27] + node _T_1329 = orr(_T_1328) @[lib.scala 403:35] + node _T_1330 = bits(_T_1236, 16, 16) @[lib.scala 403:44] + node _T_1331 = not(_T_1330) @[lib.scala 403:40] + node _T_1332 = bits(_T_1236, 16, 16) @[lib.scala 403:51] + node _T_1333 = mux(_T_1329, _T_1331, _T_1332) @[lib.scala 403:23] + _T_1237[15] <= _T_1333 @[lib.scala 403:17] + node _T_1334 = bits(_T_1236, 16, 0) @[lib.scala 403:27] + node _T_1335 = orr(_T_1334) @[lib.scala 403:35] + node _T_1336 = bits(_T_1236, 17, 17) @[lib.scala 403:44] + node _T_1337 = not(_T_1336) @[lib.scala 403:40] + node _T_1338 = bits(_T_1236, 17, 17) @[lib.scala 403:51] + node _T_1339 = mux(_T_1335, _T_1337, _T_1338) @[lib.scala 403:23] + _T_1237[16] <= _T_1339 @[lib.scala 403:17] + node _T_1340 = bits(_T_1236, 17, 0) @[lib.scala 403:27] + node _T_1341 = orr(_T_1340) @[lib.scala 403:35] + node _T_1342 = bits(_T_1236, 18, 18) @[lib.scala 403:44] + node _T_1343 = not(_T_1342) @[lib.scala 403:40] + node _T_1344 = bits(_T_1236, 18, 18) @[lib.scala 403:51] + node _T_1345 = mux(_T_1341, _T_1343, _T_1344) @[lib.scala 403:23] + _T_1237[17] <= _T_1345 @[lib.scala 403:17] + node _T_1346 = bits(_T_1236, 18, 0) @[lib.scala 403:27] + node _T_1347 = orr(_T_1346) @[lib.scala 403:35] + node _T_1348 = bits(_T_1236, 19, 19) @[lib.scala 403:44] + node _T_1349 = not(_T_1348) @[lib.scala 403:40] + node _T_1350 = bits(_T_1236, 19, 19) @[lib.scala 403:51] + node _T_1351 = mux(_T_1347, _T_1349, _T_1350) @[lib.scala 403:23] + _T_1237[18] <= _T_1351 @[lib.scala 403:17] + node _T_1352 = bits(_T_1236, 19, 0) @[lib.scala 403:27] + node _T_1353 = orr(_T_1352) @[lib.scala 403:35] + node _T_1354 = bits(_T_1236, 20, 20) @[lib.scala 403:44] + node _T_1355 = not(_T_1354) @[lib.scala 403:40] + node _T_1356 = bits(_T_1236, 20, 20) @[lib.scala 403:51] + node _T_1357 = mux(_T_1353, _T_1355, _T_1356) @[lib.scala 403:23] + _T_1237[19] <= _T_1357 @[lib.scala 403:17] + node _T_1358 = bits(_T_1236, 20, 0) @[lib.scala 403:27] + node _T_1359 = orr(_T_1358) @[lib.scala 403:35] + node _T_1360 = bits(_T_1236, 21, 21) @[lib.scala 403:44] + node _T_1361 = not(_T_1360) @[lib.scala 403:40] + node _T_1362 = bits(_T_1236, 21, 21) @[lib.scala 403:51] + node _T_1363 = mux(_T_1359, _T_1361, _T_1362) @[lib.scala 403:23] + _T_1237[20] <= _T_1363 @[lib.scala 403:17] + node _T_1364 = bits(_T_1236, 21, 0) @[lib.scala 403:27] + node _T_1365 = orr(_T_1364) @[lib.scala 403:35] + node _T_1366 = bits(_T_1236, 22, 22) @[lib.scala 403:44] + node _T_1367 = not(_T_1366) @[lib.scala 403:40] + node _T_1368 = bits(_T_1236, 22, 22) @[lib.scala 403:51] + node _T_1369 = mux(_T_1365, _T_1367, _T_1368) @[lib.scala 403:23] + _T_1237[21] <= _T_1369 @[lib.scala 403:17] + node _T_1370 = bits(_T_1236, 22, 0) @[lib.scala 403:27] + node _T_1371 = orr(_T_1370) @[lib.scala 403:35] + node _T_1372 = bits(_T_1236, 23, 23) @[lib.scala 403:44] + node _T_1373 = not(_T_1372) @[lib.scala 403:40] + node _T_1374 = bits(_T_1236, 23, 23) @[lib.scala 403:51] + node _T_1375 = mux(_T_1371, _T_1373, _T_1374) @[lib.scala 403:23] + _T_1237[22] <= _T_1375 @[lib.scala 403:17] + node _T_1376 = bits(_T_1236, 23, 0) @[lib.scala 403:27] + node _T_1377 = orr(_T_1376) @[lib.scala 403:35] + node _T_1378 = bits(_T_1236, 24, 24) @[lib.scala 403:44] + node _T_1379 = not(_T_1378) @[lib.scala 403:40] + node _T_1380 = bits(_T_1236, 24, 24) @[lib.scala 403:51] + node _T_1381 = mux(_T_1377, _T_1379, _T_1380) @[lib.scala 403:23] + _T_1237[23] <= _T_1381 @[lib.scala 403:17] + node _T_1382 = bits(_T_1236, 24, 0) @[lib.scala 403:27] + node _T_1383 = orr(_T_1382) @[lib.scala 403:35] + node _T_1384 = bits(_T_1236, 25, 25) @[lib.scala 403:44] + node _T_1385 = not(_T_1384) @[lib.scala 403:40] + node _T_1386 = bits(_T_1236, 25, 25) @[lib.scala 403:51] + node _T_1387 = mux(_T_1383, _T_1385, _T_1386) @[lib.scala 403:23] + _T_1237[24] <= _T_1387 @[lib.scala 403:17] + node _T_1388 = bits(_T_1236, 25, 0) @[lib.scala 403:27] + node _T_1389 = orr(_T_1388) @[lib.scala 403:35] + node _T_1390 = bits(_T_1236, 26, 26) @[lib.scala 403:44] + node _T_1391 = not(_T_1390) @[lib.scala 403:40] + node _T_1392 = bits(_T_1236, 26, 26) @[lib.scala 403:51] + node _T_1393 = mux(_T_1389, _T_1391, _T_1392) @[lib.scala 403:23] + _T_1237[25] <= _T_1393 @[lib.scala 403:17] + node _T_1394 = bits(_T_1236, 26, 0) @[lib.scala 403:27] + node _T_1395 = orr(_T_1394) @[lib.scala 403:35] + node _T_1396 = bits(_T_1236, 27, 27) @[lib.scala 403:44] + node _T_1397 = not(_T_1396) @[lib.scala 403:40] + node _T_1398 = bits(_T_1236, 27, 27) @[lib.scala 403:51] + node _T_1399 = mux(_T_1395, _T_1397, _T_1398) @[lib.scala 403:23] + _T_1237[26] <= _T_1399 @[lib.scala 403:17] + node _T_1400 = bits(_T_1236, 27, 0) @[lib.scala 403:27] + node _T_1401 = orr(_T_1400) @[lib.scala 403:35] + node _T_1402 = bits(_T_1236, 28, 28) @[lib.scala 403:44] + node _T_1403 = not(_T_1402) @[lib.scala 403:40] + node _T_1404 = bits(_T_1236, 28, 28) @[lib.scala 403:51] + node _T_1405 = mux(_T_1401, _T_1403, _T_1404) @[lib.scala 403:23] + _T_1237[27] <= _T_1405 @[lib.scala 403:17] + node _T_1406 = bits(_T_1236, 28, 0) @[lib.scala 403:27] + node _T_1407 = orr(_T_1406) @[lib.scala 403:35] + node _T_1408 = bits(_T_1236, 29, 29) @[lib.scala 403:44] + node _T_1409 = not(_T_1408) @[lib.scala 403:40] + node _T_1410 = bits(_T_1236, 29, 29) @[lib.scala 403:51] + node _T_1411 = mux(_T_1407, _T_1409, _T_1410) @[lib.scala 403:23] + _T_1237[28] <= _T_1411 @[lib.scala 403:17] + node _T_1412 = bits(_T_1236, 29, 0) @[lib.scala 403:27] + node _T_1413 = orr(_T_1412) @[lib.scala 403:35] + node _T_1414 = bits(_T_1236, 30, 30) @[lib.scala 403:44] + node _T_1415 = not(_T_1414) @[lib.scala 403:40] + node _T_1416 = bits(_T_1236, 30, 30) @[lib.scala 403:51] + node _T_1417 = mux(_T_1413, _T_1415, _T_1416) @[lib.scala 403:23] + _T_1237[29] <= _T_1417 @[lib.scala 403:17] + node _T_1418 = bits(_T_1236, 30, 0) @[lib.scala 403:27] + node _T_1419 = orr(_T_1418) @[lib.scala 403:35] + node _T_1420 = bits(_T_1236, 31, 31) @[lib.scala 403:44] + node _T_1421 = not(_T_1420) @[lib.scala 403:40] + node _T_1422 = bits(_T_1236, 31, 31) @[lib.scala 403:51] + node _T_1423 = mux(_T_1419, _T_1421, _T_1422) @[lib.scala 403:23] + _T_1237[30] <= _T_1423 @[lib.scala 403:17] + node _T_1424 = cat(_T_1237[2], _T_1237[1]) @[lib.scala 405:14] + node _T_1425 = cat(_T_1424, _T_1237[0]) @[lib.scala 405:14] + node _T_1426 = cat(_T_1237[4], _T_1237[3]) @[lib.scala 405:14] + node _T_1427 = cat(_T_1237[6], _T_1237[5]) @[lib.scala 405:14] + node _T_1428 = cat(_T_1427, _T_1426) @[lib.scala 405:14] + node _T_1429 = cat(_T_1428, _T_1425) @[lib.scala 405:14] + node _T_1430 = cat(_T_1237[8], _T_1237[7]) @[lib.scala 405:14] + node _T_1431 = cat(_T_1237[10], _T_1237[9]) @[lib.scala 405:14] + node _T_1432 = cat(_T_1431, _T_1430) @[lib.scala 405:14] + node _T_1433 = cat(_T_1237[12], _T_1237[11]) @[lib.scala 405:14] + node _T_1434 = cat(_T_1237[14], _T_1237[13]) @[lib.scala 405:14] + node _T_1435 = cat(_T_1434, _T_1433) @[lib.scala 405:14] + node _T_1436 = cat(_T_1435, _T_1432) @[lib.scala 405:14] + node _T_1437 = cat(_T_1436, _T_1429) @[lib.scala 405:14] + node _T_1438 = cat(_T_1237[16], _T_1237[15]) @[lib.scala 405:14] + node _T_1439 = cat(_T_1237[18], _T_1237[17]) @[lib.scala 405:14] + node _T_1440 = cat(_T_1439, _T_1438) @[lib.scala 405:14] + node _T_1441 = cat(_T_1237[20], _T_1237[19]) @[lib.scala 405:14] + node _T_1442 = cat(_T_1237[22], _T_1237[21]) @[lib.scala 405:14] + node _T_1443 = cat(_T_1442, _T_1441) @[lib.scala 405:14] + node _T_1444 = cat(_T_1443, _T_1440) @[lib.scala 405:14] + node _T_1445 = cat(_T_1237[24], _T_1237[23]) @[lib.scala 405:14] + node _T_1446 = cat(_T_1237[26], _T_1237[25]) @[lib.scala 405:14] + node _T_1447 = cat(_T_1446, _T_1445) @[lib.scala 405:14] + node _T_1448 = cat(_T_1237[28], _T_1237[27]) @[lib.scala 405:14] + node _T_1449 = cat(_T_1237[30], _T_1237[29]) @[lib.scala 405:14] + node _T_1450 = cat(_T_1449, _T_1448) @[lib.scala 405:14] + node _T_1451 = cat(_T_1450, _T_1447) @[lib.scala 405:14] + node _T_1452 = cat(_T_1451, _T_1444) @[lib.scala 405:14] + node _T_1453 = cat(_T_1452, _T_1437) @[lib.scala 405:14] + node _T_1454 = bits(_T_1236, 0, 0) @[lib.scala 405:24] node _T_1455 = cat(_T_1453, _T_1454) @[Cat.scala 29:58] node _T_1456 = bits(a_ff, 31, 0) @[exu_div_ctl.scala 184:87] node a_ff_eff = mux(_T_1235, _T_1455, _T_1456) @[exu_div_ctl.scala 184:21] @@ -85840,12 +85832,12 @@ circuit quasar_wrapper : _T_1469 <= _T_1468 @[Mux.scala 27:72] io.exu_div_result <= _T_1469 @[exu_div_ctl.scala 186:21] node _T_1470 = bits(div_clken, 0, 0) @[exu_div_ctl.scala 192:46] - inst rvclkhdr of rvclkhdr_786 @[el2_lib.scala 483:22] + inst rvclkhdr of rvclkhdr_786 @[lib.scala 343:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr.io.en <= _T_1470 @[el2_lib.scala 485:16] - rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr.io.clk <= clock @[lib.scala 344:17] + rvclkhdr.io.en <= _T_1470 @[lib.scala 345:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] node _T_1471 = eq(io.dec_div.dec_div_cancel, UInt<1>("h00")) @[exu_div_ctl.scala 195:52] node _T_1472 = and(io.dec_div.div_p.valid, _T_1471) @[exu_div_ctl.scala 195:50] reg _T_1473 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[exu_div_ctl.scala 195:26] @@ -85901,38 +85893,38 @@ circuit quasar_wrapper : _T_1492 <= shortq_shift @[exu_div_ctl.scala 206:31] shortq_shift_xx <= _T_1492 @[exu_div_ctl.scala 206:21] node _T_1493 = bits(qff_enable, 0, 0) @[exu_div_ctl.scala 208:35] - inst rvclkhdr_1 of rvclkhdr_787 @[el2_lib.scala 508:23] + inst rvclkhdr_1 of rvclkhdr_787 @[lib.scala 368:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_1.io.en <= _T_1493 @[el2_lib.scala 511:17] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_1494 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_1494 <= q_in @[el2_lib.scala 514:16] + rvclkhdr_1.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_1.io.en <= _T_1493 @[lib.scala 371:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_1494 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1494 <= q_in @[lib.scala 374:16] q_ff <= _T_1494 @[exu_div_ctl.scala 208:8] node _T_1495 = bits(aff_enable, 0, 0) @[exu_div_ctl.scala 209:35] - inst rvclkhdr_2 of rvclkhdr_788 @[el2_lib.scala 508:23] + inst rvclkhdr_2 of rvclkhdr_788 @[lib.scala 368:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_2.io.en <= _T_1495 @[el2_lib.scala 511:17] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_1496 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_1496 <= a_in @[el2_lib.scala 514:16] + rvclkhdr_2.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_2.io.en <= _T_1495 @[lib.scala 371:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_1496 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1496 <= a_in @[lib.scala 374:16] a_ff <= _T_1496 @[exu_div_ctl.scala 209:8] node _T_1497 = eq(io.dec_div.div_p.bits.unsign, UInt<1>("h00")) @[exu_div_ctl.scala 210:22] node _T_1498 = bits(io.divisor, 31, 31) @[exu_div_ctl.scala 210:64] node _T_1499 = and(_T_1497, _T_1498) @[exu_div_ctl.scala 210:52] node _T_1500 = cat(_T_1499, io.divisor) @[Cat.scala 29:58] node _T_1501 = bits(io.dec_div.div_p.valid, 0, 0) @[exu_div_ctl.scala 210:106] - inst rvclkhdr_3 of rvclkhdr_789 @[el2_lib.scala 508:23] + inst rvclkhdr_3 of rvclkhdr_789 @[lib.scala 368:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_3.io.en <= _T_1501 @[el2_lib.scala 511:17] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_1502 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_1502 <= _T_1500 @[el2_lib.scala 514:16] + rvclkhdr_3.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_3.io.en <= _T_1501 @[lib.scala 371:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_1502 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1502 <= _T_1500 @[lib.scala 374:16] m_ff <= _T_1502 @[exu_div_ctl.scala 210:8] module exu : @@ -85970,61 +85962,61 @@ circuit quasar_wrapper : node _T = cat(io.dec_exu.decode_exu.i0_predict_fghr_d, io.dec_exu.decode_exu.i0_predict_index_d) @[Cat.scala 29:58] node predpipe_d = cat(_T, io.dec_exu.decode_exu.i0_predict_btag_d) @[Cat.scala 29:58] node _T_1 = bits(x_data_en, 0, 0) @[exu.scala 63:59] - inst rvclkhdr of rvclkhdr_763 @[el2_lib.scala 508:23] + inst rvclkhdr of rvclkhdr_763 @[lib.scala 368:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr.io.en <= _T_1 @[el2_lib.scala 511:17] - rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg i0_flush_path_x : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - i0_flush_path_x <= i0_flush_path_d @[el2_lib.scala 514:16] + rvclkhdr.io.clk <= clock @[lib.scala 370:18] + rvclkhdr.io.en <= _T_1 @[lib.scala 371:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg i0_flush_path_x : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + i0_flush_path_x <= i0_flush_path_d @[lib.scala 374:16] node _T_2 = bits(x_data_en, 0, 0) @[exu.scala 64:89] - inst rvclkhdr_1 of rvclkhdr_764 @[el2_lib.scala 508:23] + inst rvclkhdr_1 of rvclkhdr_764 @[lib.scala 368:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_1.io.en <= _T_2 @[el2_lib.scala 511:17] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_3 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_3 <= csr_rs1_in_d @[el2_lib.scala 514:16] + rvclkhdr_1.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_1.io.en <= _T_2 @[lib.scala 371:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_3 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_3 <= csr_rs1_in_d @[lib.scala 374:16] io.dec_exu.decode_exu.exu_csr_rs1_x <= _T_3 @[exu.scala 64:57] node _T_4 = bits(x_data_en, 0, 0) @[exu.scala 65:83] - inst rvclkhdr_2 of rvclkhdr_765 @[el2_lib.scala 518:23] + inst rvclkhdr_2 of rvclkhdr_765 @[lib.scala 378:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= clock @[el2_lib.scala 520:18] - rvclkhdr_2.io.en <= _T_4 @[el2_lib.scala 521:17] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] - wire _T_5 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}} @[el2_lib.scala 524:33] - _T_5.bits.way <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_5.bits.pja <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_5.bits.pret <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_5.bits.pcall <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_5.bits.prett <= UInt<31>("h00") @[el2_lib.scala 524:33] - _T_5.bits.br_start_error <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_5.bits.br_error <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_5.bits.toffset <= UInt<12>("h00") @[el2_lib.scala 524:33] - _T_5.bits.hist <= UInt<2>("h00") @[el2_lib.scala 524:33] - _T_5.bits.pc4 <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_5.bits.boffset <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_5.bits.ataken <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_5.bits.misp <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_5.valid <= UInt<1>("h00") @[el2_lib.scala 524:33] - reg _T_6 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, rvclkhdr_2.io.l1clk with : (reset => (reset, _T_5)) @[el2_lib.scala 524:16] - _T_6.bits.way <= i0_predict_p_d.bits.way @[el2_lib.scala 524:16] - _T_6.bits.pja <= i0_predict_p_d.bits.pja @[el2_lib.scala 524:16] - _T_6.bits.pret <= i0_predict_p_d.bits.pret @[el2_lib.scala 524:16] - _T_6.bits.pcall <= i0_predict_p_d.bits.pcall @[el2_lib.scala 524:16] - _T_6.bits.prett <= i0_predict_p_d.bits.prett @[el2_lib.scala 524:16] - _T_6.bits.br_start_error <= i0_predict_p_d.bits.br_start_error @[el2_lib.scala 524:16] - _T_6.bits.br_error <= i0_predict_p_d.bits.br_error @[el2_lib.scala 524:16] - _T_6.bits.toffset <= i0_predict_p_d.bits.toffset @[el2_lib.scala 524:16] - _T_6.bits.hist <= i0_predict_p_d.bits.hist @[el2_lib.scala 524:16] - _T_6.bits.pc4 <= i0_predict_p_d.bits.pc4 @[el2_lib.scala 524:16] - _T_6.bits.boffset <= i0_predict_p_d.bits.boffset @[el2_lib.scala 524:16] - _T_6.bits.ataken <= i0_predict_p_d.bits.ataken @[el2_lib.scala 524:16] - _T_6.bits.misp <= i0_predict_p_d.bits.misp @[el2_lib.scala 524:16] - _T_6.valid <= i0_predict_p_d.valid @[el2_lib.scala 524:16] + rvclkhdr_2.io.clk <= clock @[lib.scala 380:18] + rvclkhdr_2.io.en <= _T_4 @[lib.scala 381:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 382:24] + wire _T_5 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}} @[lib.scala 384:33] + _T_5.bits.way <= UInt<1>("h00") @[lib.scala 384:33] + _T_5.bits.pja <= UInt<1>("h00") @[lib.scala 384:33] + _T_5.bits.pret <= UInt<1>("h00") @[lib.scala 384:33] + _T_5.bits.pcall <= UInt<1>("h00") @[lib.scala 384:33] + _T_5.bits.prett <= UInt<31>("h00") @[lib.scala 384:33] + _T_5.bits.br_start_error <= UInt<1>("h00") @[lib.scala 384:33] + _T_5.bits.br_error <= UInt<1>("h00") @[lib.scala 384:33] + _T_5.bits.toffset <= UInt<12>("h00") @[lib.scala 384:33] + _T_5.bits.hist <= UInt<2>("h00") @[lib.scala 384:33] + _T_5.bits.pc4 <= UInt<1>("h00") @[lib.scala 384:33] + _T_5.bits.boffset <= UInt<1>("h00") @[lib.scala 384:33] + _T_5.bits.ataken <= UInt<1>("h00") @[lib.scala 384:33] + _T_5.bits.misp <= UInt<1>("h00") @[lib.scala 384:33] + _T_5.valid <= UInt<1>("h00") @[lib.scala 384:33] + reg _T_6 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, rvclkhdr_2.io.l1clk with : (reset => (reset, _T_5)) @[lib.scala 384:16] + _T_6.bits.way <= i0_predict_p_d.bits.way @[lib.scala 384:16] + _T_6.bits.pja <= i0_predict_p_d.bits.pja @[lib.scala 384:16] + _T_6.bits.pret <= i0_predict_p_d.bits.pret @[lib.scala 384:16] + _T_6.bits.pcall <= i0_predict_p_d.bits.pcall @[lib.scala 384:16] + _T_6.bits.prett <= i0_predict_p_d.bits.prett @[lib.scala 384:16] + _T_6.bits.br_start_error <= i0_predict_p_d.bits.br_start_error @[lib.scala 384:16] + _T_6.bits.br_error <= i0_predict_p_d.bits.br_error @[lib.scala 384:16] + _T_6.bits.toffset <= i0_predict_p_d.bits.toffset @[lib.scala 384:16] + _T_6.bits.hist <= i0_predict_p_d.bits.hist @[lib.scala 384:16] + _T_6.bits.pc4 <= i0_predict_p_d.bits.pc4 @[lib.scala 384:16] + _T_6.bits.boffset <= i0_predict_p_d.bits.boffset @[lib.scala 384:16] + _T_6.bits.ataken <= i0_predict_p_d.bits.ataken @[lib.scala 384:16] + _T_6.bits.misp <= i0_predict_p_d.bits.misp @[lib.scala 384:16] + _T_6.valid <= i0_predict_p_d.valid @[lib.scala 384:16] i0_predict_p_x.bits.way <= _T_6.bits.way @[exu.scala 65:49] i0_predict_p_x.bits.pja <= _T_6.bits.pja @[exu.scala 65:49] i0_predict_p_x.bits.pret <= _T_6.bits.pret @[exu.scala 65:49] @@ -86040,105 +86032,105 @@ circuit quasar_wrapper : i0_predict_p_x.bits.misp <= _T_6.bits.misp @[exu.scala 65:49] i0_predict_p_x.valid <= _T_6.valid @[exu.scala 65:49] node _T_7 = bits(x_data_en, 0, 0) @[exu.scala 66:70] - inst rvclkhdr_3 of rvclkhdr_766 @[el2_lib.scala 508:23] + inst rvclkhdr_3 of rvclkhdr_766 @[lib.scala 368:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_3.io.en <= _T_7 @[el2_lib.scala 511:17] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg predpipe_x : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - predpipe_x <= predpipe_d @[el2_lib.scala 514:16] + rvclkhdr_3.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_3.io.en <= _T_7 @[lib.scala 371:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg predpipe_x : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + predpipe_x <= predpipe_d @[lib.scala 374:16] node _T_8 = bits(r_data_en, 0, 0) @[exu.scala 67:79] - inst rvclkhdr_4 of rvclkhdr_767 @[el2_lib.scala 508:23] + inst rvclkhdr_4 of rvclkhdr_767 @[lib.scala 368:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_4.io.en <= _T_8 @[el2_lib.scala 511:17] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg predpipe_r : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - predpipe_r <= predpipe_x @[el2_lib.scala 514:16] + rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_4.io.en <= _T_8 @[lib.scala 371:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg predpipe_r : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + predpipe_r <= predpipe_x @[lib.scala 374:16] node _T_9 = bits(x_ctl_en, 0, 0) @[exu.scala 68:80] - inst rvclkhdr_5 of rvclkhdr_768 @[el2_lib.scala 508:23] + inst rvclkhdr_5 of rvclkhdr_768 @[lib.scala 368:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_5.io.en <= _T_9 @[el2_lib.scala 511:17] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg ghr_x : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - ghr_x <= ghr_x_ns @[el2_lib.scala 514:16] + rvclkhdr_5.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_5.io.en <= _T_9 @[lib.scala 371:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg ghr_x : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + ghr_x <= ghr_x_ns @[lib.scala 374:16] node _T_10 = bits(x_ctl_en, 0, 0) @[exu.scala 69:75] - inst rvclkhdr_6 of rvclkhdr_769 @[el2_lib.scala 508:23] + inst rvclkhdr_6 of rvclkhdr_769 @[lib.scala 368:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset - rvclkhdr_6.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_6.io.en <= _T_10 @[el2_lib.scala 511:17] - rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg i0_pred_correct_upper_x : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - i0_pred_correct_upper_x <= i0_pred_correct_upper_d @[el2_lib.scala 514:16] + rvclkhdr_6.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_6.io.en <= _T_10 @[lib.scala 371:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg i0_pred_correct_upper_x : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + i0_pred_correct_upper_x <= i0_pred_correct_upper_d @[lib.scala 374:16] node _T_11 = bits(x_ctl_en, 0, 0) @[exu.scala 70:60] - inst rvclkhdr_7 of rvclkhdr_770 @[el2_lib.scala 508:23] + inst rvclkhdr_7 of rvclkhdr_770 @[lib.scala 368:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset - rvclkhdr_7.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_7.io.en <= _T_11 @[el2_lib.scala 511:17] - rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg i0_flush_upper_x : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - i0_flush_upper_x <= i0_flush_upper_d @[el2_lib.scala 514:16] + rvclkhdr_7.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_7.io.en <= _T_11 @[lib.scala 371:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg i0_flush_upper_x : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + i0_flush_upper_x <= i0_flush_upper_d @[lib.scala 374:16] node _T_12 = bits(x_ctl_en, 0, 0) @[exu.scala 71:78] - inst rvclkhdr_8 of rvclkhdr_771 @[el2_lib.scala 508:23] + inst rvclkhdr_8 of rvclkhdr_771 @[lib.scala 368:23] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset - rvclkhdr_8.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_8.io.en <= _T_12 @[el2_lib.scala 511:17] - rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg i0_taken_x : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - i0_taken_x <= i0_taken_d @[el2_lib.scala 514:16] + rvclkhdr_8.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_8.io.en <= _T_12 @[lib.scala 371:17] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg i0_taken_x : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + i0_taken_x <= i0_taken_d @[lib.scala 374:16] node _T_13 = bits(x_ctl_en, 0, 0) @[exu.scala 72:78] - inst rvclkhdr_9 of rvclkhdr_772 @[el2_lib.scala 508:23] + inst rvclkhdr_9 of rvclkhdr_772 @[lib.scala 368:23] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset - rvclkhdr_9.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_9.io.en <= _T_13 @[el2_lib.scala 511:17] - rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg i0_valid_x : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - i0_valid_x <= i0_valid_d @[el2_lib.scala 514:16] + rvclkhdr_9.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_9.io.en <= _T_13 @[lib.scala 371:17] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg i0_valid_x : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + i0_valid_x <= i0_valid_d @[lib.scala 374:16] node _T_14 = bits(r_ctl_en, 0, 0) @[exu.scala 73:58] - inst rvclkhdr_10 of rvclkhdr_773 @[el2_lib.scala 518:23] + inst rvclkhdr_10 of rvclkhdr_773 @[lib.scala 378:23] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset - rvclkhdr_10.io.clk <= clock @[el2_lib.scala 520:18] - rvclkhdr_10.io.en <= _T_14 @[el2_lib.scala 521:17] - rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] - wire _T_15 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}} @[el2_lib.scala 524:33] - _T_15.bits.way <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_15.bits.pja <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_15.bits.pret <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_15.bits.pcall <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_15.bits.prett <= UInt<31>("h00") @[el2_lib.scala 524:33] - _T_15.bits.br_start_error <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_15.bits.br_error <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_15.bits.toffset <= UInt<12>("h00") @[el2_lib.scala 524:33] - _T_15.bits.hist <= UInt<2>("h00") @[el2_lib.scala 524:33] - _T_15.bits.pc4 <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_15.bits.boffset <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_15.bits.ataken <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_15.bits.misp <= UInt<1>("h00") @[el2_lib.scala 524:33] - _T_15.valid <= UInt<1>("h00") @[el2_lib.scala 524:33] - reg _T_16 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, rvclkhdr_10.io.l1clk with : (reset => (reset, _T_15)) @[el2_lib.scala 524:16] - _T_16.bits.way <= i0_predict_p_x.bits.way @[el2_lib.scala 524:16] - _T_16.bits.pja <= i0_predict_p_x.bits.pja @[el2_lib.scala 524:16] - _T_16.bits.pret <= i0_predict_p_x.bits.pret @[el2_lib.scala 524:16] - _T_16.bits.pcall <= i0_predict_p_x.bits.pcall @[el2_lib.scala 524:16] - _T_16.bits.prett <= i0_predict_p_x.bits.prett @[el2_lib.scala 524:16] - _T_16.bits.br_start_error <= i0_predict_p_x.bits.br_start_error @[el2_lib.scala 524:16] - _T_16.bits.br_error <= i0_predict_p_x.bits.br_error @[el2_lib.scala 524:16] - _T_16.bits.toffset <= i0_predict_p_x.bits.toffset @[el2_lib.scala 524:16] - _T_16.bits.hist <= i0_predict_p_x.bits.hist @[el2_lib.scala 524:16] - _T_16.bits.pc4 <= i0_predict_p_x.bits.pc4 @[el2_lib.scala 524:16] - _T_16.bits.boffset <= i0_predict_p_x.bits.boffset @[el2_lib.scala 524:16] - _T_16.bits.ataken <= i0_predict_p_x.bits.ataken @[el2_lib.scala 524:16] - _T_16.bits.misp <= i0_predict_p_x.bits.misp @[el2_lib.scala 524:16] - _T_16.valid <= i0_predict_p_x.valid @[el2_lib.scala 524:16] + rvclkhdr_10.io.clk <= clock @[lib.scala 380:18] + rvclkhdr_10.io.en <= _T_14 @[lib.scala 381:17] + rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 382:24] + wire _T_15 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}} @[lib.scala 384:33] + _T_15.bits.way <= UInt<1>("h00") @[lib.scala 384:33] + _T_15.bits.pja <= UInt<1>("h00") @[lib.scala 384:33] + _T_15.bits.pret <= UInt<1>("h00") @[lib.scala 384:33] + _T_15.bits.pcall <= UInt<1>("h00") @[lib.scala 384:33] + _T_15.bits.prett <= UInt<31>("h00") @[lib.scala 384:33] + _T_15.bits.br_start_error <= UInt<1>("h00") @[lib.scala 384:33] + _T_15.bits.br_error <= UInt<1>("h00") @[lib.scala 384:33] + _T_15.bits.toffset <= UInt<12>("h00") @[lib.scala 384:33] + _T_15.bits.hist <= UInt<2>("h00") @[lib.scala 384:33] + _T_15.bits.pc4 <= UInt<1>("h00") @[lib.scala 384:33] + _T_15.bits.boffset <= UInt<1>("h00") @[lib.scala 384:33] + _T_15.bits.ataken <= UInt<1>("h00") @[lib.scala 384:33] + _T_15.bits.misp <= UInt<1>("h00") @[lib.scala 384:33] + _T_15.valid <= UInt<1>("h00") @[lib.scala 384:33] + reg _T_16 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, rvclkhdr_10.io.l1clk with : (reset => (reset, _T_15)) @[lib.scala 384:16] + _T_16.bits.way <= i0_predict_p_x.bits.way @[lib.scala 384:16] + _T_16.bits.pja <= i0_predict_p_x.bits.pja @[lib.scala 384:16] + _T_16.bits.pret <= i0_predict_p_x.bits.pret @[lib.scala 384:16] + _T_16.bits.pcall <= i0_predict_p_x.bits.pcall @[lib.scala 384:16] + _T_16.bits.prett <= i0_predict_p_x.bits.prett @[lib.scala 384:16] + _T_16.bits.br_start_error <= i0_predict_p_x.bits.br_start_error @[lib.scala 384:16] + _T_16.bits.br_error <= i0_predict_p_x.bits.br_error @[lib.scala 384:16] + _T_16.bits.toffset <= i0_predict_p_x.bits.toffset @[lib.scala 384:16] + _T_16.bits.hist <= i0_predict_p_x.bits.hist @[lib.scala 384:16] + _T_16.bits.pc4 <= i0_predict_p_x.bits.pc4 @[lib.scala 384:16] + _T_16.bits.boffset <= i0_predict_p_x.bits.boffset @[lib.scala 384:16] + _T_16.bits.ataken <= i0_predict_p_x.bits.ataken @[lib.scala 384:16] + _T_16.bits.misp <= i0_predict_p_x.bits.misp @[lib.scala 384:16] + _T_16.valid <= i0_predict_p_x.valid @[lib.scala 384:16] i0_pp_r.bits.way <= _T_16.bits.way @[exu.scala 73:25] i0_pp_r.bits.pja <= _T_16.bits.pja @[exu.scala 73:25] i0_pp_r.bits.pret <= _T_16.bits.pret @[exu.scala 73:25] @@ -86155,42 +86147,42 @@ circuit quasar_wrapper : i0_pp_r.valid <= _T_16.valid @[exu.scala 73:25] node _T_17 = bits(io.dec_exu.decode_exu.pred_correct_npc_x, 5, 0) @[exu.scala 74:85] node _T_18 = bits(r_ctl_en, 0, 0) @[exu.scala 74:101] - inst rvclkhdr_11 of rvclkhdr_774 @[el2_lib.scala 508:23] + inst rvclkhdr_11 of rvclkhdr_774 @[lib.scala 368:23] rvclkhdr_11.clock <= clock rvclkhdr_11.reset <= reset - rvclkhdr_11.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_11.io.en <= _T_18 @[el2_lib.scala 511:17] - rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg pred_temp1 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - pred_temp1 <= _T_17 @[el2_lib.scala 514:16] + rvclkhdr_11.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_11.io.en <= _T_18 @[lib.scala 371:17] + rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg pred_temp1 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + pred_temp1 <= _T_17 @[lib.scala 374:16] node _T_19 = bits(r_ctl_en, 0, 0) @[exu.scala 75:75] - inst rvclkhdr_12 of rvclkhdr_775 @[el2_lib.scala 508:23] + inst rvclkhdr_12 of rvclkhdr_775 @[lib.scala 368:23] rvclkhdr_12.clock <= clock rvclkhdr_12.reset <= reset - rvclkhdr_12.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_12.io.en <= _T_19 @[el2_lib.scala 511:17] - rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg i0_pred_correct_upper_r : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - i0_pred_correct_upper_r <= i0_pred_correct_upper_x @[el2_lib.scala 514:16] + rvclkhdr_12.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_12.io.en <= _T_19 @[lib.scala 371:17] + rvclkhdr_12.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg i0_pred_correct_upper_r : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + i0_pred_correct_upper_r <= i0_pred_correct_upper_x @[lib.scala 374:16] node _T_20 = bits(r_data_en, 0, 0) @[exu.scala 76:68] - inst rvclkhdr_13 of rvclkhdr_776 @[el2_lib.scala 508:23] + inst rvclkhdr_13 of rvclkhdr_776 @[lib.scala 368:23] rvclkhdr_13.clock <= clock rvclkhdr_13.reset <= reset - rvclkhdr_13.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_13.io.en <= _T_20 @[el2_lib.scala 511:17] - rvclkhdr_13.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg i0_flush_path_upper_r : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - i0_flush_path_upper_r <= i0_flush_path_x @[el2_lib.scala 514:16] + rvclkhdr_13.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_13.io.en <= _T_20 @[lib.scala 371:17] + rvclkhdr_13.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg i0_flush_path_upper_r : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + i0_flush_path_upper_r <= i0_flush_path_x @[lib.scala 374:16] node _T_21 = bits(io.dec_exu.decode_exu.pred_correct_npc_x, 30, 6) @[exu.scala 77:97] node _T_22 = bits(r_data_en, 0, 0) @[exu.scala 77:115] - inst rvclkhdr_14 of rvclkhdr_777 @[el2_lib.scala 508:23] + inst rvclkhdr_14 of rvclkhdr_777 @[lib.scala 368:23] rvclkhdr_14.clock <= clock rvclkhdr_14.reset <= reset - rvclkhdr_14.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_14.io.en <= _T_22 @[el2_lib.scala 511:17] - rvclkhdr_14.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg pred_temp2 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - pred_temp2 <= _T_21 @[el2_lib.scala 514:16] + rvclkhdr_14.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_14.io.en <= _T_22 @[lib.scala 371:17] + rvclkhdr_14.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg pred_temp2 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + pred_temp2 <= _T_21 @[lib.scala 374:16] node _T_23 = cat(pred_temp2, pred_temp1) @[Cat.scala 29:58] pred_correct_npc_r <= _T_23 @[exu.scala 78:41] node _T_24 = eq(UInt<10>("h0200"), UInt<6>("h020")) @[exu.scala 80:24] @@ -86218,34 +86210,34 @@ circuit quasar_wrapper : skip @[exu.scala 80:58] else : @[exu.scala 84:14] node _T_33 = bits(data_gate_en, 0, 0) @[exu.scala 85:65] - inst rvclkhdr_15 of rvclkhdr_778 @[el2_lib.scala 508:23] + inst rvclkhdr_15 of rvclkhdr_778 @[lib.scala 368:23] rvclkhdr_15.clock <= clock rvclkhdr_15.reset <= reset - rvclkhdr_15.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_15.io.en <= _T_33 @[el2_lib.scala 511:17] - rvclkhdr_15.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_34 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_34 <= ghr_d_ns @[el2_lib.scala 514:16] + rvclkhdr_15.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_15.io.en <= _T_33 @[lib.scala 371:17] + rvclkhdr_15.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_34 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_34 <= ghr_d_ns @[lib.scala 374:16] ghr_d <= _T_34 @[exu.scala 85:33] node _T_35 = bits(data_gate_en, 0, 0) @[exu.scala 86:82] - inst rvclkhdr_16 of rvclkhdr_779 @[el2_lib.scala 508:23] + inst rvclkhdr_16 of rvclkhdr_779 @[lib.scala 368:23] rvclkhdr_16.clock <= clock rvclkhdr_16.reset <= reset - rvclkhdr_16.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_16.io.en <= _T_35 @[el2_lib.scala 511:17] - rvclkhdr_16.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_36 : UInt<1>, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_36 <= io.dec_exu.decode_exu.mul_p.valid @[el2_lib.scala 514:16] + rvclkhdr_16.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_16.io.en <= _T_35 @[lib.scala 371:17] + rvclkhdr_16.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_36 : UInt<1>, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_36 <= io.dec_exu.decode_exu.mul_p.valid @[lib.scala 374:16] mul_valid_x <= _T_36 @[exu.scala 86:25] node _T_37 = bits(data_gate_en, 0, 0) @[exu.scala 87:89] - inst rvclkhdr_17 of rvclkhdr_780 @[el2_lib.scala 508:23] + inst rvclkhdr_17 of rvclkhdr_780 @[lib.scala 368:23] rvclkhdr_17.clock <= clock rvclkhdr_17.reset <= reset - rvclkhdr_17.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_17.io.en <= _T_37 @[el2_lib.scala 511:17] - rvclkhdr_17.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_38 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_38 <= io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[el2_lib.scala 514:16] + rvclkhdr_17.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_17.io.en <= _T_37 @[lib.scala 371:17] + rvclkhdr_17.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_38 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_38 <= io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[lib.scala 374:16] flush_lower_ff <= _T_38 @[exu.scala 87:25] skip @[exu.scala 84:14] node _T_39 = neq(ghr_d_ns, ghr_d) @[exu.scala 91:39] @@ -86606,37 +86598,37 @@ circuit quasar_wrapper : input reset : AsyncReset output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>} - node _T = bits(io.start_addr_d, 31, 28) @[el2_lib.scala 496:27] - node start_addr_in_dccm_region_d = eq(_T, UInt<4>("h0f")) @[el2_lib.scala 496:49] - wire start_addr_in_dccm_d : UInt<1> @[el2_lib.scala 497:26] - node _T_1 = bits(io.start_addr_d, 31, 16) @[el2_lib.scala 501:24] - node _T_2 = eq(_T_1, UInt<16>("h0f004")) @[el2_lib.scala 501:39] - start_addr_in_dccm_d <= _T_2 @[el2_lib.scala 501:16] - node _T_3 = bits(io.end_addr_d, 31, 28) @[el2_lib.scala 496:27] - node end_addr_in_dccm_region_d = eq(_T_3, UInt<4>("h0f")) @[el2_lib.scala 496:49] - wire end_addr_in_dccm_d : UInt<1> @[el2_lib.scala 497:26] - node _T_4 = bits(io.end_addr_d, 31, 16) @[el2_lib.scala 501:24] - node _T_5 = eq(_T_4, UInt<16>("h0f004")) @[el2_lib.scala 501:39] - end_addr_in_dccm_d <= _T_5 @[el2_lib.scala 501:16] + node _T = bits(io.start_addr_d, 31, 28) @[lib.scala 356:27] + node start_addr_in_dccm_region_d = eq(_T, UInt<4>("h0f")) @[lib.scala 356:49] + wire start_addr_in_dccm_d : UInt<1> @[lib.scala 357:26] + node _T_1 = bits(io.start_addr_d, 31, 16) @[lib.scala 361:24] + node _T_2 = eq(_T_1, UInt<16>("h0f004")) @[lib.scala 361:39] + start_addr_in_dccm_d <= _T_2 @[lib.scala 361:16] + node _T_3 = bits(io.end_addr_d, 31, 28) @[lib.scala 356:27] + node end_addr_in_dccm_region_d = eq(_T_3, UInt<4>("h0f")) @[lib.scala 356:49] + wire end_addr_in_dccm_d : UInt<1> @[lib.scala 357:26] + node _T_4 = bits(io.end_addr_d, 31, 16) @[lib.scala 361:24] + node _T_5 = eq(_T_4, UInt<16>("h0f004")) @[lib.scala 361:39] + end_addr_in_dccm_d <= _T_5 @[lib.scala 361:16] wire addr_in_iccm : UInt<1> addr_in_iccm <= UInt<1>("h00") node _T_6 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 42:37] node _T_7 = eq(_T_6, UInt<4>("h0e")) @[lsu_addrcheck.scala 42:45] addr_in_iccm <= _T_7 @[lsu_addrcheck.scala 42:18] node _T_8 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 50:89] - node _T_9 = bits(_T_8, 31, 28) @[el2_lib.scala 496:27] - node start_addr_in_pic_region_d = eq(_T_9, UInt<4>("h0f")) @[el2_lib.scala 496:49] - wire start_addr_in_pic_d : UInt<1> @[el2_lib.scala 497:26] - node _T_10 = bits(_T_8, 31, 15) @[el2_lib.scala 501:24] - node _T_11 = eq(_T_10, UInt<17>("h01e018")) @[el2_lib.scala 501:39] - start_addr_in_pic_d <= _T_11 @[el2_lib.scala 501:16] + node _T_9 = bits(_T_8, 31, 28) @[lib.scala 356:27] + node start_addr_in_pic_region_d = eq(_T_9, UInt<4>("h0f")) @[lib.scala 356:49] + wire start_addr_in_pic_d : UInt<1> @[lib.scala 357:26] + node _T_10 = bits(_T_8, 31, 15) @[lib.scala 361:24] + node _T_11 = eq(_T_10, UInt<17>("h01e018")) @[lib.scala 361:39] + start_addr_in_pic_d <= _T_11 @[lib.scala 361:16] node _T_12 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 52:83] - node _T_13 = bits(_T_12, 31, 28) @[el2_lib.scala 496:27] - node end_addr_in_pic_region_d = eq(_T_13, UInt<4>("h0f")) @[el2_lib.scala 496:49] - wire end_addr_in_pic_d : UInt<1> @[el2_lib.scala 497:26] - node _T_14 = bits(_T_12, 31, 15) @[el2_lib.scala 501:24] - node _T_15 = eq(_T_14, UInt<17>("h01e018")) @[el2_lib.scala 501:39] - end_addr_in_pic_d <= _T_15 @[el2_lib.scala 501:16] + node _T_13 = bits(_T_12, 31, 28) @[lib.scala 356:27] + node end_addr_in_pic_region_d = eq(_T_13, UInt<4>("h0f")) @[lib.scala 356:49] + wire end_addr_in_pic_d : UInt<1> @[lib.scala 357:26] + node _T_14 = bits(_T_12, 31, 15) @[lib.scala 361:24] + node _T_15 = eq(_T_14, UInt<17>("h01e018")) @[lib.scala 361:39] + end_addr_in_pic_d <= _T_15 @[lib.scala 361:16] node start_addr_dccm_or_pic = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 54:60] node _T_16 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:48] node _T_17 = eq(_T_16, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:54] @@ -86868,43 +86860,43 @@ circuit quasar_wrapper : node lsu_offset_d = and(_T_1, _T_3) @[lsu_lsc_ctl.scala 96:51] node _T_4 = bits(io.lsu_pkt_d.bits.load_ldst_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 99:66] node rs1_d = mux(_T_4, io.lsu_result_m, lsu_rs1_d) @[lsu_lsc_ctl.scala 99:28] - node _T_5 = bits(rs1_d, 11, 0) @[el2_lib.scala 232:31] + node _T_5 = bits(rs1_d, 11, 0) @[lib.scala 92:31] node _T_6 = cat(UInt<1>("h00"), _T_5) @[Cat.scala 29:58] - node _T_7 = bits(lsu_offset_d, 11, 0) @[el2_lib.scala 232:60] + node _T_7 = bits(lsu_offset_d, 11, 0) @[lib.scala 92:60] node _T_8 = cat(UInt<1>("h00"), _T_7) @[Cat.scala 29:58] - node _T_9 = add(_T_6, _T_8) @[el2_lib.scala 232:39] - node _T_10 = tail(_T_9, 1) @[el2_lib.scala 232:39] - node _T_11 = bits(lsu_offset_d, 11, 11) @[el2_lib.scala 233:41] - node _T_12 = bits(_T_10, 12, 12) @[el2_lib.scala 233:50] - node _T_13 = xor(_T_11, _T_12) @[el2_lib.scala 233:46] - node _T_14 = not(_T_13) @[el2_lib.scala 233:33] + node _T_9 = add(_T_6, _T_8) @[lib.scala 92:39] + node _T_10 = tail(_T_9, 1) @[lib.scala 92:39] + node _T_11 = bits(lsu_offset_d, 11, 11) @[lib.scala 93:41] + node _T_12 = bits(_T_10, 12, 12) @[lib.scala 93:50] + node _T_13 = xor(_T_11, _T_12) @[lib.scala 93:46] + node _T_14 = not(_T_13) @[lib.scala 93:33] node _T_15 = bits(_T_14, 0, 0) @[Bitwise.scala 72:15] node _T_16 = mux(_T_15, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12] - node _T_17 = bits(rs1_d, 31, 12) @[el2_lib.scala 233:63] - node _T_18 = and(_T_16, _T_17) @[el2_lib.scala 233:58] - node _T_19 = bits(lsu_offset_d, 11, 11) @[el2_lib.scala 234:25] - node _T_20 = not(_T_19) @[el2_lib.scala 234:18] - node _T_21 = bits(_T_10, 12, 12) @[el2_lib.scala 234:34] - node _T_22 = and(_T_20, _T_21) @[el2_lib.scala 234:30] + node _T_17 = bits(rs1_d, 31, 12) @[lib.scala 93:63] + node _T_18 = and(_T_16, _T_17) @[lib.scala 93:58] + node _T_19 = bits(lsu_offset_d, 11, 11) @[lib.scala 94:25] + node _T_20 = not(_T_19) @[lib.scala 94:18] + node _T_21 = bits(_T_10, 12, 12) @[lib.scala 94:34] + node _T_22 = and(_T_20, _T_21) @[lib.scala 94:30] node _T_23 = bits(_T_22, 0, 0) @[Bitwise.scala 72:15] node _T_24 = mux(_T_23, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12] - node _T_25 = bits(rs1_d, 31, 12) @[el2_lib.scala 234:47] - node _T_26 = add(_T_25, UInt<1>("h01")) @[el2_lib.scala 234:54] - node _T_27 = tail(_T_26, 1) @[el2_lib.scala 234:54] - node _T_28 = and(_T_24, _T_27) @[el2_lib.scala 234:41] - node _T_29 = or(_T_18, _T_28) @[el2_lib.scala 233:72] - node _T_30 = bits(lsu_offset_d, 11, 11) @[el2_lib.scala 235:24] - node _T_31 = bits(_T_10, 12, 12) @[el2_lib.scala 235:34] - node _T_32 = not(_T_31) @[el2_lib.scala 235:31] - node _T_33 = and(_T_30, _T_32) @[el2_lib.scala 235:29] + node _T_25 = bits(rs1_d, 31, 12) @[lib.scala 94:47] + node _T_26 = add(_T_25, UInt<1>("h01")) @[lib.scala 94:54] + node _T_27 = tail(_T_26, 1) @[lib.scala 94:54] + node _T_28 = and(_T_24, _T_27) @[lib.scala 94:41] + node _T_29 = or(_T_18, _T_28) @[lib.scala 93:72] + node _T_30 = bits(lsu_offset_d, 11, 11) @[lib.scala 95:24] + node _T_31 = bits(_T_10, 12, 12) @[lib.scala 95:34] + node _T_32 = not(_T_31) @[lib.scala 95:31] + node _T_33 = and(_T_30, _T_32) @[lib.scala 95:29] node _T_34 = bits(_T_33, 0, 0) @[Bitwise.scala 72:15] node _T_35 = mux(_T_34, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12] - node _T_36 = bits(rs1_d, 31, 12) @[el2_lib.scala 235:47] - node _T_37 = sub(_T_36, UInt<1>("h01")) @[el2_lib.scala 235:54] - node _T_38 = tail(_T_37, 1) @[el2_lib.scala 235:54] - node _T_39 = and(_T_35, _T_38) @[el2_lib.scala 235:41] - node _T_40 = or(_T_29, _T_39) @[el2_lib.scala 234:61] - node _T_41 = bits(_T_10, 11, 0) @[el2_lib.scala 236:22] + node _T_36 = bits(rs1_d, 31, 12) @[lib.scala 95:47] + node _T_37 = sub(_T_36, UInt<1>("h01")) @[lib.scala 95:54] + node _T_38 = tail(_T_37, 1) @[lib.scala 95:54] + node _T_39 = and(_T_35, _T_38) @[lib.scala 95:41] + node _T_40 = or(_T_29, _T_39) @[lib.scala 94:61] + node _T_41 = bits(_T_10, 11, 0) @[lib.scala 96:22] node full_addr_d = cat(_T_40, _T_41) @[Cat.scala 29:58] node _T_42 = bits(io.lsu_pkt_d.bits.half, 0, 0) @[Bitwise.scala 72:15] node _T_43 = mux(_T_42, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] @@ -87396,15 +87388,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_790 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_790 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_791 : output Q : Clock @@ -87420,15 +87412,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_791 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_791 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] module lsu_dccm_ctl : input clock : Clock @@ -88329,25 +88321,25 @@ circuit quasar_wrapper : node _T_824 = bits(io.end_addr_r, 15, 0) @[lsu_dccm_ctl.scala 171:49] node _T_825 = bits(io.ld_single_ecc_error_r, 0, 0) @[lsu_dccm_ctl.scala 171:90] node _T_826 = bits(io.scan_mode, 0, 0) @[lsu_dccm_ctl.scala 171:116] - inst rvclkhdr of rvclkhdr_790 @[el2_lib.scala 508:23] + inst rvclkhdr of rvclkhdr_790 @[lib.scala 368:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr.io.en <= _T_825 @[el2_lib.scala 511:17] - rvclkhdr.io.scan_mode <= _T_826 @[el2_lib.scala 512:24] - reg ld_sec_addr_hi_r_ff : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - ld_sec_addr_hi_r_ff <= _T_824 @[el2_lib.scala 514:16] + rvclkhdr.io.clk <= clock @[lib.scala 370:18] + rvclkhdr.io.en <= _T_825 @[lib.scala 371:17] + rvclkhdr.io.scan_mode <= _T_826 @[lib.scala 372:24] + reg ld_sec_addr_hi_r_ff : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + ld_sec_addr_hi_r_ff <= _T_824 @[lib.scala 374:16] node _T_827 = bits(io.lsu_addr_r, 15, 0) @[lsu_dccm_ctl.scala 172:49] node _T_828 = bits(io.ld_single_ecc_error_r, 0, 0) @[lsu_dccm_ctl.scala 172:90] node _T_829 = bits(io.scan_mode, 0, 0) @[lsu_dccm_ctl.scala 172:116] - inst rvclkhdr_1 of rvclkhdr_791 @[el2_lib.scala 508:23] + inst rvclkhdr_1 of rvclkhdr_791 @[lib.scala 368:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_1.io.en <= _T_828 @[el2_lib.scala 511:17] - rvclkhdr_1.io.scan_mode <= _T_829 @[el2_lib.scala 512:24] - reg ld_sec_addr_lo_r_ff : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - ld_sec_addr_lo_r_ff <= _T_827 @[el2_lib.scala 514:16] + rvclkhdr_1.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_1.io.en <= _T_828 @[lib.scala 371:17] + rvclkhdr_1.io.scan_mode <= _T_829 @[lib.scala 372:24] + reg ld_sec_addr_lo_r_ff : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + ld_sec_addr_lo_r_ff <= _T_827 @[lib.scala 374:16] node _T_830 = or(io.lsu_pkt_d.bits.word, io.lsu_pkt_d.bits.dword) @[lsu_dccm_ctl.scala 173:125] node _T_831 = eq(_T_830, UInt<1>("h00")) @[lsu_dccm_ctl.scala 173:100] node _T_832 = bits(io.lsu_addr_d, 1, 0) @[lsu_dccm_ctl.scala 173:168] @@ -89505,15 +89497,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_792 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_792 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_793 : output Q : Clock @@ -89529,15 +89521,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_793 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_793 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_794 : output Q : Clock @@ -89553,15 +89545,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_794 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_794 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_795 : output Q : Clock @@ -89577,15 +89569,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_795 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_795 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_796 : output Q : Clock @@ -89601,15 +89593,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_796 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_796 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_797 : output Q : Clock @@ -89625,15 +89617,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_797 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_797 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_798 : output Q : Clock @@ -89649,15 +89641,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_798 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_798 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_799 : output Q : Clock @@ -89673,15 +89665,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_799 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_799 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] module lsu_stbuf : input clock : Clock @@ -90516,91 +90508,91 @@ circuit quasar_wrapper : stbuf_byteen[3] <= _T_662 @[lsu_stbuf.scala 165:16] node _T_663 = bits(stbuf_wr_en, 0, 0) @[lsu_stbuf.scala 167:56] node _T_664 = bits(_T_663, 0, 0) @[lsu_stbuf.scala 167:66] - inst rvclkhdr of rvclkhdr_792 @[el2_lib.scala 508:23] + inst rvclkhdr of rvclkhdr_792 @[lib.scala 368:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr.io.en <= _T_664 @[el2_lib.scala 511:17] - rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_665 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_665 <= stbuf_addrin[0] @[el2_lib.scala 514:16] + rvclkhdr.io.clk <= clock @[lib.scala 370:18] + rvclkhdr.io.en <= _T_664 @[lib.scala 371:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_665 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_665 <= stbuf_addrin[0] @[lib.scala 374:16] stbuf_addr[0] <= _T_665 @[lsu_stbuf.scala 167:19] node _T_666 = bits(stbuf_wr_en, 0, 0) @[lsu_stbuf.scala 168:56] node _T_667 = bits(_T_666, 0, 0) @[lsu_stbuf.scala 168:66] - inst rvclkhdr_1 of rvclkhdr_793 @[el2_lib.scala 508:23] + inst rvclkhdr_1 of rvclkhdr_793 @[lib.scala 368:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_1.io.en <= _T_667 @[el2_lib.scala 511:17] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_668 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_668 <= stbuf_datain[0] @[el2_lib.scala 514:16] + rvclkhdr_1.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_1.io.en <= _T_667 @[lib.scala 371:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_668 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_668 <= stbuf_datain[0] @[lib.scala 374:16] stbuf_data[0] <= _T_668 @[lsu_stbuf.scala 168:19] node _T_669 = bits(stbuf_wr_en, 1, 1) @[lsu_stbuf.scala 167:56] node _T_670 = bits(_T_669, 0, 0) @[lsu_stbuf.scala 167:66] - inst rvclkhdr_2 of rvclkhdr_794 @[el2_lib.scala 508:23] + inst rvclkhdr_2 of rvclkhdr_794 @[lib.scala 368:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_2.io.en <= _T_670 @[el2_lib.scala 511:17] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_671 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_671 <= stbuf_addrin[1] @[el2_lib.scala 514:16] + rvclkhdr_2.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_2.io.en <= _T_670 @[lib.scala 371:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_671 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_671 <= stbuf_addrin[1] @[lib.scala 374:16] stbuf_addr[1] <= _T_671 @[lsu_stbuf.scala 167:19] node _T_672 = bits(stbuf_wr_en, 1, 1) @[lsu_stbuf.scala 168:56] node _T_673 = bits(_T_672, 0, 0) @[lsu_stbuf.scala 168:66] - inst rvclkhdr_3 of rvclkhdr_795 @[el2_lib.scala 508:23] + inst rvclkhdr_3 of rvclkhdr_795 @[lib.scala 368:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_3.io.en <= _T_673 @[el2_lib.scala 511:17] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_674 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_674 <= stbuf_datain[1] @[el2_lib.scala 514:16] + rvclkhdr_3.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_3.io.en <= _T_673 @[lib.scala 371:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_674 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_674 <= stbuf_datain[1] @[lib.scala 374:16] stbuf_data[1] <= _T_674 @[lsu_stbuf.scala 168:19] node _T_675 = bits(stbuf_wr_en, 2, 2) @[lsu_stbuf.scala 167:56] node _T_676 = bits(_T_675, 0, 0) @[lsu_stbuf.scala 167:66] - inst rvclkhdr_4 of rvclkhdr_796 @[el2_lib.scala 508:23] + inst rvclkhdr_4 of rvclkhdr_796 @[lib.scala 368:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_4.io.en <= _T_676 @[el2_lib.scala 511:17] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_677 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_677 <= stbuf_addrin[2] @[el2_lib.scala 514:16] + rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_4.io.en <= _T_676 @[lib.scala 371:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_677 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_677 <= stbuf_addrin[2] @[lib.scala 374:16] stbuf_addr[2] <= _T_677 @[lsu_stbuf.scala 167:19] node _T_678 = bits(stbuf_wr_en, 2, 2) @[lsu_stbuf.scala 168:56] node _T_679 = bits(_T_678, 0, 0) @[lsu_stbuf.scala 168:66] - inst rvclkhdr_5 of rvclkhdr_797 @[el2_lib.scala 508:23] + inst rvclkhdr_5 of rvclkhdr_797 @[lib.scala 368:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_5.io.en <= _T_679 @[el2_lib.scala 511:17] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_680 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_680 <= stbuf_datain[2] @[el2_lib.scala 514:16] + rvclkhdr_5.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_5.io.en <= _T_679 @[lib.scala 371:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_680 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_680 <= stbuf_datain[2] @[lib.scala 374:16] stbuf_data[2] <= _T_680 @[lsu_stbuf.scala 168:19] node _T_681 = bits(stbuf_wr_en, 3, 3) @[lsu_stbuf.scala 167:56] node _T_682 = bits(_T_681, 0, 0) @[lsu_stbuf.scala 167:66] - inst rvclkhdr_6 of rvclkhdr_798 @[el2_lib.scala 508:23] + inst rvclkhdr_6 of rvclkhdr_798 @[lib.scala 368:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset - rvclkhdr_6.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_6.io.en <= _T_682 @[el2_lib.scala 511:17] - rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_683 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_683 <= stbuf_addrin[3] @[el2_lib.scala 514:16] + rvclkhdr_6.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_6.io.en <= _T_682 @[lib.scala 371:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_683 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_683 <= stbuf_addrin[3] @[lib.scala 374:16] stbuf_addr[3] <= _T_683 @[lsu_stbuf.scala 167:19] node _T_684 = bits(stbuf_wr_en, 3, 3) @[lsu_stbuf.scala 168:56] node _T_685 = bits(_T_684, 0, 0) @[lsu_stbuf.scala 168:66] - inst rvclkhdr_7 of rvclkhdr_799 @[el2_lib.scala 508:23] + inst rvclkhdr_7 of rvclkhdr_799 @[lib.scala 368:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset - rvclkhdr_7.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_7.io.en <= _T_685 @[el2_lib.scala 511:17] - rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_686 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_686 <= stbuf_datain[3] @[el2_lib.scala 514:16] + rvclkhdr_7.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_7.io.en <= _T_685 @[lib.scala 371:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_686 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_686 <= stbuf_datain[3] @[lib.scala 374:16] stbuf_data[3] <= _T_686 @[lsu_stbuf.scala 168:19] reg _T_687 : UInt<1>, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_stbuf.scala 170:52] _T_687 <= ldst_dual_d @[lsu_stbuf.scala 170:52] @@ -91369,15 +91361,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_800 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_800 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_801 : output Q : Clock @@ -91393,15 +91385,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_801 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_801 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] module lsu_ecc : input clock : Clock @@ -91452,443 +91444,443 @@ circuit quasar_wrapper : io.sec_data_lo_m <= UInt<1>("h00") @[lsu_ecc.scala 91:32] io.lsu_single_ecc_error_m <= UInt<1>("h00") @[lsu_ecc.scala 92:30] io.lsu_double_ecc_error_m <= UInt<1>("h00") @[lsu_ecc.scala 93:30] - wire _T : UInt<1>[18] @[el2_lib.scala 313:18] - wire _T_1 : UInt<1>[18] @[el2_lib.scala 314:18] - wire _T_2 : UInt<1>[18] @[el2_lib.scala 315:18] - wire _T_3 : UInt<1>[15] @[el2_lib.scala 316:18] - wire _T_4 : UInt<1>[15] @[el2_lib.scala 317:18] - wire _T_5 : UInt<1>[6] @[el2_lib.scala 318:18] - node _T_6 = bits(dccm_rdata_hi_any, 0, 0) @[el2_lib.scala 325:36] - _T[0] <= _T_6 @[el2_lib.scala 325:30] - node _T_7 = bits(dccm_rdata_hi_any, 0, 0) @[el2_lib.scala 326:36] - _T_1[0] <= _T_7 @[el2_lib.scala 326:30] - node _T_8 = bits(dccm_rdata_hi_any, 1, 1) @[el2_lib.scala 325:36] - _T[1] <= _T_8 @[el2_lib.scala 325:30] - node _T_9 = bits(dccm_rdata_hi_any, 1, 1) @[el2_lib.scala 327:36] - _T_2[0] <= _T_9 @[el2_lib.scala 327:30] - node _T_10 = bits(dccm_rdata_hi_any, 2, 2) @[el2_lib.scala 326:36] - _T_1[1] <= _T_10 @[el2_lib.scala 326:30] - node _T_11 = bits(dccm_rdata_hi_any, 2, 2) @[el2_lib.scala 327:36] - _T_2[1] <= _T_11 @[el2_lib.scala 327:30] - node _T_12 = bits(dccm_rdata_hi_any, 3, 3) @[el2_lib.scala 325:36] - _T[2] <= _T_12 @[el2_lib.scala 325:30] - node _T_13 = bits(dccm_rdata_hi_any, 3, 3) @[el2_lib.scala 326:36] - _T_1[2] <= _T_13 @[el2_lib.scala 326:30] - node _T_14 = bits(dccm_rdata_hi_any, 3, 3) @[el2_lib.scala 327:36] - _T_2[2] <= _T_14 @[el2_lib.scala 327:30] - node _T_15 = bits(dccm_rdata_hi_any, 4, 4) @[el2_lib.scala 325:36] - _T[3] <= _T_15 @[el2_lib.scala 325:30] - node _T_16 = bits(dccm_rdata_hi_any, 4, 4) @[el2_lib.scala 328:36] - _T_3[0] <= _T_16 @[el2_lib.scala 328:30] - node _T_17 = bits(dccm_rdata_hi_any, 5, 5) @[el2_lib.scala 326:36] - _T_1[3] <= _T_17 @[el2_lib.scala 326:30] - node _T_18 = bits(dccm_rdata_hi_any, 5, 5) @[el2_lib.scala 328:36] - _T_3[1] <= _T_18 @[el2_lib.scala 328:30] - node _T_19 = bits(dccm_rdata_hi_any, 6, 6) @[el2_lib.scala 325:36] - _T[4] <= _T_19 @[el2_lib.scala 325:30] - node _T_20 = bits(dccm_rdata_hi_any, 6, 6) @[el2_lib.scala 326:36] - _T_1[4] <= _T_20 @[el2_lib.scala 326:30] - node _T_21 = bits(dccm_rdata_hi_any, 6, 6) @[el2_lib.scala 328:36] - _T_3[2] <= _T_21 @[el2_lib.scala 328:30] - node _T_22 = bits(dccm_rdata_hi_any, 7, 7) @[el2_lib.scala 327:36] - _T_2[3] <= _T_22 @[el2_lib.scala 327:30] - node _T_23 = bits(dccm_rdata_hi_any, 7, 7) @[el2_lib.scala 328:36] - _T_3[3] <= _T_23 @[el2_lib.scala 328:30] - node _T_24 = bits(dccm_rdata_hi_any, 8, 8) @[el2_lib.scala 325:36] - _T[5] <= _T_24 @[el2_lib.scala 325:30] - node _T_25 = bits(dccm_rdata_hi_any, 8, 8) @[el2_lib.scala 327:36] - _T_2[4] <= _T_25 @[el2_lib.scala 327:30] - node _T_26 = bits(dccm_rdata_hi_any, 8, 8) @[el2_lib.scala 328:36] - _T_3[4] <= _T_26 @[el2_lib.scala 328:30] - node _T_27 = bits(dccm_rdata_hi_any, 9, 9) @[el2_lib.scala 326:36] - _T_1[5] <= _T_27 @[el2_lib.scala 326:30] - node _T_28 = bits(dccm_rdata_hi_any, 9, 9) @[el2_lib.scala 327:36] - _T_2[5] <= _T_28 @[el2_lib.scala 327:30] - node _T_29 = bits(dccm_rdata_hi_any, 9, 9) @[el2_lib.scala 328:36] - _T_3[5] <= _T_29 @[el2_lib.scala 328:30] - node _T_30 = bits(dccm_rdata_hi_any, 10, 10) @[el2_lib.scala 325:36] - _T[6] <= _T_30 @[el2_lib.scala 325:30] - node _T_31 = bits(dccm_rdata_hi_any, 10, 10) @[el2_lib.scala 326:36] - _T_1[6] <= _T_31 @[el2_lib.scala 326:30] - node _T_32 = bits(dccm_rdata_hi_any, 10, 10) @[el2_lib.scala 327:36] - _T_2[6] <= _T_32 @[el2_lib.scala 327:30] - node _T_33 = bits(dccm_rdata_hi_any, 10, 10) @[el2_lib.scala 328:36] - _T_3[6] <= _T_33 @[el2_lib.scala 328:30] - node _T_34 = bits(dccm_rdata_hi_any, 11, 11) @[el2_lib.scala 325:36] - _T[7] <= _T_34 @[el2_lib.scala 325:30] - node _T_35 = bits(dccm_rdata_hi_any, 11, 11) @[el2_lib.scala 329:36] - _T_4[0] <= _T_35 @[el2_lib.scala 329:30] - node _T_36 = bits(dccm_rdata_hi_any, 12, 12) @[el2_lib.scala 326:36] - _T_1[7] <= _T_36 @[el2_lib.scala 326:30] - node _T_37 = bits(dccm_rdata_hi_any, 12, 12) @[el2_lib.scala 329:36] - _T_4[1] <= _T_37 @[el2_lib.scala 329:30] - node _T_38 = bits(dccm_rdata_hi_any, 13, 13) @[el2_lib.scala 325:36] - _T[8] <= _T_38 @[el2_lib.scala 325:30] - node _T_39 = bits(dccm_rdata_hi_any, 13, 13) @[el2_lib.scala 326:36] - _T_1[8] <= _T_39 @[el2_lib.scala 326:30] - node _T_40 = bits(dccm_rdata_hi_any, 13, 13) @[el2_lib.scala 329:36] - _T_4[2] <= _T_40 @[el2_lib.scala 329:30] - node _T_41 = bits(dccm_rdata_hi_any, 14, 14) @[el2_lib.scala 327:36] - _T_2[7] <= _T_41 @[el2_lib.scala 327:30] - node _T_42 = bits(dccm_rdata_hi_any, 14, 14) @[el2_lib.scala 329:36] - _T_4[3] <= _T_42 @[el2_lib.scala 329:30] - node _T_43 = bits(dccm_rdata_hi_any, 15, 15) @[el2_lib.scala 325:36] - _T[9] <= _T_43 @[el2_lib.scala 325:30] - node _T_44 = bits(dccm_rdata_hi_any, 15, 15) @[el2_lib.scala 327:36] - _T_2[8] <= _T_44 @[el2_lib.scala 327:30] - node _T_45 = bits(dccm_rdata_hi_any, 15, 15) @[el2_lib.scala 329:36] - _T_4[4] <= _T_45 @[el2_lib.scala 329:30] - node _T_46 = bits(dccm_rdata_hi_any, 16, 16) @[el2_lib.scala 326:36] - _T_1[9] <= _T_46 @[el2_lib.scala 326:30] - node _T_47 = bits(dccm_rdata_hi_any, 16, 16) @[el2_lib.scala 327:36] - _T_2[9] <= _T_47 @[el2_lib.scala 327:30] - node _T_48 = bits(dccm_rdata_hi_any, 16, 16) @[el2_lib.scala 329:36] - _T_4[5] <= _T_48 @[el2_lib.scala 329:30] - node _T_49 = bits(dccm_rdata_hi_any, 17, 17) @[el2_lib.scala 325:36] - _T[10] <= _T_49 @[el2_lib.scala 325:30] - node _T_50 = bits(dccm_rdata_hi_any, 17, 17) @[el2_lib.scala 326:36] - _T_1[10] <= _T_50 @[el2_lib.scala 326:30] - node _T_51 = bits(dccm_rdata_hi_any, 17, 17) @[el2_lib.scala 327:36] - _T_2[10] <= _T_51 @[el2_lib.scala 327:30] - node _T_52 = bits(dccm_rdata_hi_any, 17, 17) @[el2_lib.scala 329:36] - _T_4[6] <= _T_52 @[el2_lib.scala 329:30] - node _T_53 = bits(dccm_rdata_hi_any, 18, 18) @[el2_lib.scala 328:36] - _T_3[7] <= _T_53 @[el2_lib.scala 328:30] - node _T_54 = bits(dccm_rdata_hi_any, 18, 18) @[el2_lib.scala 329:36] - _T_4[7] <= _T_54 @[el2_lib.scala 329:30] - node _T_55 = bits(dccm_rdata_hi_any, 19, 19) @[el2_lib.scala 325:36] - _T[11] <= _T_55 @[el2_lib.scala 325:30] - node _T_56 = bits(dccm_rdata_hi_any, 19, 19) @[el2_lib.scala 328:36] - _T_3[8] <= _T_56 @[el2_lib.scala 328:30] - node _T_57 = bits(dccm_rdata_hi_any, 19, 19) @[el2_lib.scala 329:36] - _T_4[8] <= _T_57 @[el2_lib.scala 329:30] - node _T_58 = bits(dccm_rdata_hi_any, 20, 20) @[el2_lib.scala 326:36] - _T_1[11] <= _T_58 @[el2_lib.scala 326:30] - node _T_59 = bits(dccm_rdata_hi_any, 20, 20) @[el2_lib.scala 328:36] - _T_3[9] <= _T_59 @[el2_lib.scala 328:30] - node _T_60 = bits(dccm_rdata_hi_any, 20, 20) @[el2_lib.scala 329:36] - _T_4[9] <= _T_60 @[el2_lib.scala 329:30] - node _T_61 = bits(dccm_rdata_hi_any, 21, 21) @[el2_lib.scala 325:36] - _T[12] <= _T_61 @[el2_lib.scala 325:30] - node _T_62 = bits(dccm_rdata_hi_any, 21, 21) @[el2_lib.scala 326:36] - _T_1[12] <= _T_62 @[el2_lib.scala 326:30] - node _T_63 = bits(dccm_rdata_hi_any, 21, 21) @[el2_lib.scala 328:36] - _T_3[10] <= _T_63 @[el2_lib.scala 328:30] - node _T_64 = bits(dccm_rdata_hi_any, 21, 21) @[el2_lib.scala 329:36] - _T_4[10] <= _T_64 @[el2_lib.scala 329:30] - node _T_65 = bits(dccm_rdata_hi_any, 22, 22) @[el2_lib.scala 327:36] - _T_2[11] <= _T_65 @[el2_lib.scala 327:30] - node _T_66 = bits(dccm_rdata_hi_any, 22, 22) @[el2_lib.scala 328:36] - _T_3[11] <= _T_66 @[el2_lib.scala 328:30] - node _T_67 = bits(dccm_rdata_hi_any, 22, 22) @[el2_lib.scala 329:36] - _T_4[11] <= _T_67 @[el2_lib.scala 329:30] - node _T_68 = bits(dccm_rdata_hi_any, 23, 23) @[el2_lib.scala 325:36] - _T[13] <= _T_68 @[el2_lib.scala 325:30] - node _T_69 = bits(dccm_rdata_hi_any, 23, 23) @[el2_lib.scala 327:36] - _T_2[12] <= _T_69 @[el2_lib.scala 327:30] - node _T_70 = bits(dccm_rdata_hi_any, 23, 23) @[el2_lib.scala 328:36] - _T_3[12] <= _T_70 @[el2_lib.scala 328:30] - node _T_71 = bits(dccm_rdata_hi_any, 23, 23) @[el2_lib.scala 329:36] - _T_4[12] <= _T_71 @[el2_lib.scala 329:30] - node _T_72 = bits(dccm_rdata_hi_any, 24, 24) @[el2_lib.scala 326:36] - _T_1[13] <= _T_72 @[el2_lib.scala 326:30] - node _T_73 = bits(dccm_rdata_hi_any, 24, 24) @[el2_lib.scala 327:36] - _T_2[13] <= _T_73 @[el2_lib.scala 327:30] - node _T_74 = bits(dccm_rdata_hi_any, 24, 24) @[el2_lib.scala 328:36] - _T_3[13] <= _T_74 @[el2_lib.scala 328:30] - node _T_75 = bits(dccm_rdata_hi_any, 24, 24) @[el2_lib.scala 329:36] - _T_4[13] <= _T_75 @[el2_lib.scala 329:30] - node _T_76 = bits(dccm_rdata_hi_any, 25, 25) @[el2_lib.scala 325:36] - _T[14] <= _T_76 @[el2_lib.scala 325:30] - node _T_77 = bits(dccm_rdata_hi_any, 25, 25) @[el2_lib.scala 326:36] - _T_1[14] <= _T_77 @[el2_lib.scala 326:30] - node _T_78 = bits(dccm_rdata_hi_any, 25, 25) @[el2_lib.scala 327:36] - _T_2[14] <= _T_78 @[el2_lib.scala 327:30] - node _T_79 = bits(dccm_rdata_hi_any, 25, 25) @[el2_lib.scala 328:36] - _T_3[14] <= _T_79 @[el2_lib.scala 328:30] - node _T_80 = bits(dccm_rdata_hi_any, 25, 25) @[el2_lib.scala 329:36] - _T_4[14] <= _T_80 @[el2_lib.scala 329:30] - node _T_81 = bits(dccm_rdata_hi_any, 26, 26) @[el2_lib.scala 325:36] - _T[15] <= _T_81 @[el2_lib.scala 325:30] - node _T_82 = bits(dccm_rdata_hi_any, 26, 26) @[el2_lib.scala 330:36] - _T_5[0] <= _T_82 @[el2_lib.scala 330:30] - node _T_83 = bits(dccm_rdata_hi_any, 27, 27) @[el2_lib.scala 326:36] - _T_1[15] <= _T_83 @[el2_lib.scala 326:30] - node _T_84 = bits(dccm_rdata_hi_any, 27, 27) @[el2_lib.scala 330:36] - _T_5[1] <= _T_84 @[el2_lib.scala 330:30] - node _T_85 = bits(dccm_rdata_hi_any, 28, 28) @[el2_lib.scala 325:36] - _T[16] <= _T_85 @[el2_lib.scala 325:30] - node _T_86 = bits(dccm_rdata_hi_any, 28, 28) @[el2_lib.scala 326:36] - _T_1[16] <= _T_86 @[el2_lib.scala 326:30] - node _T_87 = bits(dccm_rdata_hi_any, 28, 28) @[el2_lib.scala 330:36] - _T_5[2] <= _T_87 @[el2_lib.scala 330:30] - node _T_88 = bits(dccm_rdata_hi_any, 29, 29) @[el2_lib.scala 327:36] - _T_2[15] <= _T_88 @[el2_lib.scala 327:30] - node _T_89 = bits(dccm_rdata_hi_any, 29, 29) @[el2_lib.scala 330:36] - _T_5[3] <= _T_89 @[el2_lib.scala 330:30] - node _T_90 = bits(dccm_rdata_hi_any, 30, 30) @[el2_lib.scala 325:36] - _T[17] <= _T_90 @[el2_lib.scala 325:30] - node _T_91 = bits(dccm_rdata_hi_any, 30, 30) @[el2_lib.scala 327:36] - _T_2[16] <= _T_91 @[el2_lib.scala 327:30] - node _T_92 = bits(dccm_rdata_hi_any, 30, 30) @[el2_lib.scala 330:36] - _T_5[4] <= _T_92 @[el2_lib.scala 330:30] - node _T_93 = bits(dccm_rdata_hi_any, 31, 31) @[el2_lib.scala 326:36] - _T_1[17] <= _T_93 @[el2_lib.scala 326:30] - node _T_94 = bits(dccm_rdata_hi_any, 31, 31) @[el2_lib.scala 327:36] - _T_2[17] <= _T_94 @[el2_lib.scala 327:30] - node _T_95 = bits(dccm_rdata_hi_any, 31, 31) @[el2_lib.scala 330:36] - _T_5[5] <= _T_95 @[el2_lib.scala 330:30] - node _T_96 = xorr(dccm_rdata_hi_any) @[el2_lib.scala 333:30] - node _T_97 = xorr(dccm_data_ecc_hi_any) @[el2_lib.scala 333:44] - node _T_98 = xor(_T_96, _T_97) @[el2_lib.scala 333:35] - node _T_99 = not(UInt<1>("h00")) @[el2_lib.scala 333:52] - node _T_100 = and(_T_98, _T_99) @[el2_lib.scala 333:50] - node _T_101 = bits(dccm_data_ecc_hi_any, 5, 5) @[el2_lib.scala 333:68] - node _T_102 = cat(_T_5[2], _T_5[1]) @[el2_lib.scala 333:76] - node _T_103 = cat(_T_102, _T_5[0]) @[el2_lib.scala 333:76] - node _T_104 = cat(_T_5[5], _T_5[4]) @[el2_lib.scala 333:76] - node _T_105 = cat(_T_104, _T_5[3]) @[el2_lib.scala 333:76] - node _T_106 = cat(_T_105, _T_103) @[el2_lib.scala 333:76] - node _T_107 = xorr(_T_106) @[el2_lib.scala 333:83] - node _T_108 = xor(_T_101, _T_107) @[el2_lib.scala 333:71] - node _T_109 = bits(dccm_data_ecc_hi_any, 4, 4) @[el2_lib.scala 333:95] - node _T_110 = cat(_T_4[2], _T_4[1]) @[el2_lib.scala 333:103] - node _T_111 = cat(_T_110, _T_4[0]) @[el2_lib.scala 333:103] - node _T_112 = cat(_T_4[4], _T_4[3]) @[el2_lib.scala 333:103] - node _T_113 = cat(_T_4[6], _T_4[5]) @[el2_lib.scala 333:103] - node _T_114 = cat(_T_113, _T_112) @[el2_lib.scala 333:103] - node _T_115 = cat(_T_114, _T_111) @[el2_lib.scala 333:103] - node _T_116 = cat(_T_4[8], _T_4[7]) @[el2_lib.scala 333:103] - node _T_117 = cat(_T_4[10], _T_4[9]) @[el2_lib.scala 333:103] - node _T_118 = cat(_T_117, _T_116) @[el2_lib.scala 333:103] - node _T_119 = cat(_T_4[12], _T_4[11]) @[el2_lib.scala 333:103] - node _T_120 = cat(_T_4[14], _T_4[13]) @[el2_lib.scala 333:103] - node _T_121 = cat(_T_120, _T_119) @[el2_lib.scala 333:103] - node _T_122 = cat(_T_121, _T_118) @[el2_lib.scala 333:103] - node _T_123 = cat(_T_122, _T_115) @[el2_lib.scala 333:103] - node _T_124 = xorr(_T_123) @[el2_lib.scala 333:110] - node _T_125 = xor(_T_109, _T_124) @[el2_lib.scala 333:98] - node _T_126 = bits(dccm_data_ecc_hi_any, 3, 3) @[el2_lib.scala 333:122] - node _T_127 = cat(_T_3[2], _T_3[1]) @[el2_lib.scala 333:130] - node _T_128 = cat(_T_127, _T_3[0]) @[el2_lib.scala 333:130] - node _T_129 = cat(_T_3[4], _T_3[3]) @[el2_lib.scala 333:130] - node _T_130 = cat(_T_3[6], _T_3[5]) @[el2_lib.scala 333:130] - node _T_131 = cat(_T_130, _T_129) @[el2_lib.scala 333:130] - node _T_132 = cat(_T_131, _T_128) @[el2_lib.scala 333:130] - node _T_133 = cat(_T_3[8], _T_3[7]) @[el2_lib.scala 333:130] - node _T_134 = cat(_T_3[10], _T_3[9]) @[el2_lib.scala 333:130] - node _T_135 = cat(_T_134, _T_133) @[el2_lib.scala 333:130] - node _T_136 = cat(_T_3[12], _T_3[11]) @[el2_lib.scala 333:130] - node _T_137 = cat(_T_3[14], _T_3[13]) @[el2_lib.scala 333:130] - node _T_138 = cat(_T_137, _T_136) @[el2_lib.scala 333:130] - node _T_139 = cat(_T_138, _T_135) @[el2_lib.scala 333:130] - node _T_140 = cat(_T_139, _T_132) @[el2_lib.scala 333:130] - node _T_141 = xorr(_T_140) @[el2_lib.scala 333:137] - node _T_142 = xor(_T_126, _T_141) @[el2_lib.scala 333:125] - node _T_143 = bits(dccm_data_ecc_hi_any, 2, 2) @[el2_lib.scala 333:149] - node _T_144 = cat(_T_2[1], _T_2[0]) @[el2_lib.scala 333:157] - node _T_145 = cat(_T_2[3], _T_2[2]) @[el2_lib.scala 333:157] - node _T_146 = cat(_T_145, _T_144) @[el2_lib.scala 333:157] - node _T_147 = cat(_T_2[5], _T_2[4]) @[el2_lib.scala 333:157] - node _T_148 = cat(_T_2[8], _T_2[7]) @[el2_lib.scala 333:157] - node _T_149 = cat(_T_148, _T_2[6]) @[el2_lib.scala 333:157] - node _T_150 = cat(_T_149, _T_147) @[el2_lib.scala 333:157] - node _T_151 = cat(_T_150, _T_146) @[el2_lib.scala 333:157] - node _T_152 = cat(_T_2[10], _T_2[9]) @[el2_lib.scala 333:157] - node _T_153 = cat(_T_2[12], _T_2[11]) @[el2_lib.scala 333:157] - node _T_154 = cat(_T_153, _T_152) @[el2_lib.scala 333:157] - node _T_155 = cat(_T_2[14], _T_2[13]) @[el2_lib.scala 333:157] - node _T_156 = cat(_T_2[17], _T_2[16]) @[el2_lib.scala 333:157] - node _T_157 = cat(_T_156, _T_2[15]) @[el2_lib.scala 333:157] - node _T_158 = cat(_T_157, _T_155) @[el2_lib.scala 333:157] - node _T_159 = cat(_T_158, _T_154) @[el2_lib.scala 333:157] - node _T_160 = cat(_T_159, _T_151) @[el2_lib.scala 333:157] - node _T_161 = xorr(_T_160) @[el2_lib.scala 333:164] - node _T_162 = xor(_T_143, _T_161) @[el2_lib.scala 333:152] - node _T_163 = bits(dccm_data_ecc_hi_any, 1, 1) @[el2_lib.scala 333:176] - node _T_164 = cat(_T_1[1], _T_1[0]) @[el2_lib.scala 333:184] - node _T_165 = cat(_T_1[3], _T_1[2]) @[el2_lib.scala 333:184] - node _T_166 = cat(_T_165, _T_164) @[el2_lib.scala 333:184] - node _T_167 = cat(_T_1[5], _T_1[4]) @[el2_lib.scala 333:184] - node _T_168 = cat(_T_1[8], _T_1[7]) @[el2_lib.scala 333:184] - node _T_169 = cat(_T_168, _T_1[6]) @[el2_lib.scala 333:184] - node _T_170 = cat(_T_169, _T_167) @[el2_lib.scala 333:184] - node _T_171 = cat(_T_170, _T_166) @[el2_lib.scala 333:184] - node _T_172 = cat(_T_1[10], _T_1[9]) @[el2_lib.scala 333:184] - node _T_173 = cat(_T_1[12], _T_1[11]) @[el2_lib.scala 333:184] - node _T_174 = cat(_T_173, _T_172) @[el2_lib.scala 333:184] - node _T_175 = cat(_T_1[14], _T_1[13]) @[el2_lib.scala 333:184] - node _T_176 = cat(_T_1[17], _T_1[16]) @[el2_lib.scala 333:184] - node _T_177 = cat(_T_176, _T_1[15]) @[el2_lib.scala 333:184] - node _T_178 = cat(_T_177, _T_175) @[el2_lib.scala 333:184] - node _T_179 = cat(_T_178, _T_174) @[el2_lib.scala 333:184] - node _T_180 = cat(_T_179, _T_171) @[el2_lib.scala 333:184] - node _T_181 = xorr(_T_180) @[el2_lib.scala 333:191] - node _T_182 = xor(_T_163, _T_181) @[el2_lib.scala 333:179] - node _T_183 = bits(dccm_data_ecc_hi_any, 0, 0) @[el2_lib.scala 333:203] - node _T_184 = cat(_T[1], _T[0]) @[el2_lib.scala 333:211] - node _T_185 = cat(_T[3], _T[2]) @[el2_lib.scala 333:211] - node _T_186 = cat(_T_185, _T_184) @[el2_lib.scala 333:211] - node _T_187 = cat(_T[5], _T[4]) @[el2_lib.scala 333:211] - node _T_188 = cat(_T[8], _T[7]) @[el2_lib.scala 333:211] - node _T_189 = cat(_T_188, _T[6]) @[el2_lib.scala 333:211] - node _T_190 = cat(_T_189, _T_187) @[el2_lib.scala 333:211] - node _T_191 = cat(_T_190, _T_186) @[el2_lib.scala 333:211] - node _T_192 = cat(_T[10], _T[9]) @[el2_lib.scala 333:211] - node _T_193 = cat(_T[12], _T[11]) @[el2_lib.scala 333:211] - node _T_194 = cat(_T_193, _T_192) @[el2_lib.scala 333:211] - node _T_195 = cat(_T[14], _T[13]) @[el2_lib.scala 333:211] - node _T_196 = cat(_T[17], _T[16]) @[el2_lib.scala 333:211] - node _T_197 = cat(_T_196, _T[15]) @[el2_lib.scala 333:211] - node _T_198 = cat(_T_197, _T_195) @[el2_lib.scala 333:211] - node _T_199 = cat(_T_198, _T_194) @[el2_lib.scala 333:211] - node _T_200 = cat(_T_199, _T_191) @[el2_lib.scala 333:211] - node _T_201 = xorr(_T_200) @[el2_lib.scala 333:218] - node _T_202 = xor(_T_183, _T_201) @[el2_lib.scala 333:206] + wire _T : UInt<1>[18] @[lib.scala 173:18] + wire _T_1 : UInt<1>[18] @[lib.scala 174:18] + wire _T_2 : UInt<1>[18] @[lib.scala 175:18] + wire _T_3 : UInt<1>[15] @[lib.scala 176:18] + wire _T_4 : UInt<1>[15] @[lib.scala 177:18] + wire _T_5 : UInt<1>[6] @[lib.scala 178:18] + node _T_6 = bits(dccm_rdata_hi_any, 0, 0) @[lib.scala 185:36] + _T[0] <= _T_6 @[lib.scala 185:30] + node _T_7 = bits(dccm_rdata_hi_any, 0, 0) @[lib.scala 186:36] + _T_1[0] <= _T_7 @[lib.scala 186:30] + node _T_8 = bits(dccm_rdata_hi_any, 1, 1) @[lib.scala 185:36] + _T[1] <= _T_8 @[lib.scala 185:30] + node _T_9 = bits(dccm_rdata_hi_any, 1, 1) @[lib.scala 187:36] + _T_2[0] <= _T_9 @[lib.scala 187:30] + node _T_10 = bits(dccm_rdata_hi_any, 2, 2) @[lib.scala 186:36] + _T_1[1] <= _T_10 @[lib.scala 186:30] + node _T_11 = bits(dccm_rdata_hi_any, 2, 2) @[lib.scala 187:36] + _T_2[1] <= _T_11 @[lib.scala 187:30] + node _T_12 = bits(dccm_rdata_hi_any, 3, 3) @[lib.scala 185:36] + _T[2] <= _T_12 @[lib.scala 185:30] + node _T_13 = bits(dccm_rdata_hi_any, 3, 3) @[lib.scala 186:36] + _T_1[2] <= _T_13 @[lib.scala 186:30] + node _T_14 = bits(dccm_rdata_hi_any, 3, 3) @[lib.scala 187:36] + _T_2[2] <= _T_14 @[lib.scala 187:30] + node _T_15 = bits(dccm_rdata_hi_any, 4, 4) @[lib.scala 185:36] + _T[3] <= _T_15 @[lib.scala 185:30] + node _T_16 = bits(dccm_rdata_hi_any, 4, 4) @[lib.scala 188:36] + _T_3[0] <= _T_16 @[lib.scala 188:30] + node _T_17 = bits(dccm_rdata_hi_any, 5, 5) @[lib.scala 186:36] + _T_1[3] <= _T_17 @[lib.scala 186:30] + node _T_18 = bits(dccm_rdata_hi_any, 5, 5) @[lib.scala 188:36] + _T_3[1] <= _T_18 @[lib.scala 188:30] + node _T_19 = bits(dccm_rdata_hi_any, 6, 6) @[lib.scala 185:36] + _T[4] <= _T_19 @[lib.scala 185:30] + node _T_20 = bits(dccm_rdata_hi_any, 6, 6) @[lib.scala 186:36] + _T_1[4] <= _T_20 @[lib.scala 186:30] + node _T_21 = bits(dccm_rdata_hi_any, 6, 6) @[lib.scala 188:36] + _T_3[2] <= _T_21 @[lib.scala 188:30] + node _T_22 = bits(dccm_rdata_hi_any, 7, 7) @[lib.scala 187:36] + _T_2[3] <= _T_22 @[lib.scala 187:30] + node _T_23 = bits(dccm_rdata_hi_any, 7, 7) @[lib.scala 188:36] + _T_3[3] <= _T_23 @[lib.scala 188:30] + node _T_24 = bits(dccm_rdata_hi_any, 8, 8) @[lib.scala 185:36] + _T[5] <= _T_24 @[lib.scala 185:30] + node _T_25 = bits(dccm_rdata_hi_any, 8, 8) @[lib.scala 187:36] + _T_2[4] <= _T_25 @[lib.scala 187:30] + node _T_26 = bits(dccm_rdata_hi_any, 8, 8) @[lib.scala 188:36] + _T_3[4] <= _T_26 @[lib.scala 188:30] + node _T_27 = bits(dccm_rdata_hi_any, 9, 9) @[lib.scala 186:36] + _T_1[5] <= _T_27 @[lib.scala 186:30] + node _T_28 = bits(dccm_rdata_hi_any, 9, 9) @[lib.scala 187:36] + _T_2[5] <= _T_28 @[lib.scala 187:30] + node _T_29 = bits(dccm_rdata_hi_any, 9, 9) @[lib.scala 188:36] + _T_3[5] <= _T_29 @[lib.scala 188:30] + node _T_30 = bits(dccm_rdata_hi_any, 10, 10) @[lib.scala 185:36] + _T[6] <= _T_30 @[lib.scala 185:30] + node _T_31 = bits(dccm_rdata_hi_any, 10, 10) @[lib.scala 186:36] + _T_1[6] <= _T_31 @[lib.scala 186:30] + node _T_32 = bits(dccm_rdata_hi_any, 10, 10) @[lib.scala 187:36] + _T_2[6] <= _T_32 @[lib.scala 187:30] + node _T_33 = bits(dccm_rdata_hi_any, 10, 10) @[lib.scala 188:36] + _T_3[6] <= _T_33 @[lib.scala 188:30] + node _T_34 = bits(dccm_rdata_hi_any, 11, 11) @[lib.scala 185:36] + _T[7] <= _T_34 @[lib.scala 185:30] + node _T_35 = bits(dccm_rdata_hi_any, 11, 11) @[lib.scala 189:36] + _T_4[0] <= _T_35 @[lib.scala 189:30] + node _T_36 = bits(dccm_rdata_hi_any, 12, 12) @[lib.scala 186:36] + _T_1[7] <= _T_36 @[lib.scala 186:30] + node _T_37 = bits(dccm_rdata_hi_any, 12, 12) @[lib.scala 189:36] + _T_4[1] <= _T_37 @[lib.scala 189:30] + node _T_38 = bits(dccm_rdata_hi_any, 13, 13) @[lib.scala 185:36] + _T[8] <= _T_38 @[lib.scala 185:30] + node _T_39 = bits(dccm_rdata_hi_any, 13, 13) @[lib.scala 186:36] + _T_1[8] <= _T_39 @[lib.scala 186:30] + node _T_40 = bits(dccm_rdata_hi_any, 13, 13) @[lib.scala 189:36] + _T_4[2] <= _T_40 @[lib.scala 189:30] + node _T_41 = bits(dccm_rdata_hi_any, 14, 14) @[lib.scala 187:36] + _T_2[7] <= _T_41 @[lib.scala 187:30] + node _T_42 = bits(dccm_rdata_hi_any, 14, 14) @[lib.scala 189:36] + _T_4[3] <= _T_42 @[lib.scala 189:30] + node _T_43 = bits(dccm_rdata_hi_any, 15, 15) @[lib.scala 185:36] + _T[9] <= _T_43 @[lib.scala 185:30] + node _T_44 = bits(dccm_rdata_hi_any, 15, 15) @[lib.scala 187:36] + _T_2[8] <= _T_44 @[lib.scala 187:30] + node _T_45 = bits(dccm_rdata_hi_any, 15, 15) @[lib.scala 189:36] + _T_4[4] <= _T_45 @[lib.scala 189:30] + node _T_46 = bits(dccm_rdata_hi_any, 16, 16) @[lib.scala 186:36] + _T_1[9] <= _T_46 @[lib.scala 186:30] + node _T_47 = bits(dccm_rdata_hi_any, 16, 16) @[lib.scala 187:36] + _T_2[9] <= _T_47 @[lib.scala 187:30] + node _T_48 = bits(dccm_rdata_hi_any, 16, 16) @[lib.scala 189:36] + _T_4[5] <= _T_48 @[lib.scala 189:30] + node _T_49 = bits(dccm_rdata_hi_any, 17, 17) @[lib.scala 185:36] + _T[10] <= _T_49 @[lib.scala 185:30] + node _T_50 = bits(dccm_rdata_hi_any, 17, 17) @[lib.scala 186:36] + _T_1[10] <= _T_50 @[lib.scala 186:30] + node _T_51 = bits(dccm_rdata_hi_any, 17, 17) @[lib.scala 187:36] + _T_2[10] <= _T_51 @[lib.scala 187:30] + node _T_52 = bits(dccm_rdata_hi_any, 17, 17) @[lib.scala 189:36] + _T_4[6] <= _T_52 @[lib.scala 189:30] + node _T_53 = bits(dccm_rdata_hi_any, 18, 18) @[lib.scala 188:36] + _T_3[7] <= _T_53 @[lib.scala 188:30] + node _T_54 = bits(dccm_rdata_hi_any, 18, 18) @[lib.scala 189:36] + _T_4[7] <= _T_54 @[lib.scala 189:30] + node _T_55 = bits(dccm_rdata_hi_any, 19, 19) @[lib.scala 185:36] + _T[11] <= _T_55 @[lib.scala 185:30] + node _T_56 = bits(dccm_rdata_hi_any, 19, 19) @[lib.scala 188:36] + _T_3[8] <= _T_56 @[lib.scala 188:30] + node _T_57 = bits(dccm_rdata_hi_any, 19, 19) @[lib.scala 189:36] + _T_4[8] <= _T_57 @[lib.scala 189:30] + node _T_58 = bits(dccm_rdata_hi_any, 20, 20) @[lib.scala 186:36] + _T_1[11] <= _T_58 @[lib.scala 186:30] + node _T_59 = bits(dccm_rdata_hi_any, 20, 20) @[lib.scala 188:36] + _T_3[9] <= _T_59 @[lib.scala 188:30] + node _T_60 = bits(dccm_rdata_hi_any, 20, 20) @[lib.scala 189:36] + _T_4[9] <= _T_60 @[lib.scala 189:30] + node _T_61 = bits(dccm_rdata_hi_any, 21, 21) @[lib.scala 185:36] + _T[12] <= _T_61 @[lib.scala 185:30] + node _T_62 = bits(dccm_rdata_hi_any, 21, 21) @[lib.scala 186:36] + _T_1[12] <= _T_62 @[lib.scala 186:30] + node _T_63 = bits(dccm_rdata_hi_any, 21, 21) @[lib.scala 188:36] + _T_3[10] <= _T_63 @[lib.scala 188:30] + node _T_64 = bits(dccm_rdata_hi_any, 21, 21) @[lib.scala 189:36] + _T_4[10] <= _T_64 @[lib.scala 189:30] + node _T_65 = bits(dccm_rdata_hi_any, 22, 22) @[lib.scala 187:36] + _T_2[11] <= _T_65 @[lib.scala 187:30] + node _T_66 = bits(dccm_rdata_hi_any, 22, 22) @[lib.scala 188:36] + _T_3[11] <= _T_66 @[lib.scala 188:30] + node _T_67 = bits(dccm_rdata_hi_any, 22, 22) @[lib.scala 189:36] + _T_4[11] <= _T_67 @[lib.scala 189:30] + node _T_68 = bits(dccm_rdata_hi_any, 23, 23) @[lib.scala 185:36] + _T[13] <= _T_68 @[lib.scala 185:30] + node _T_69 = bits(dccm_rdata_hi_any, 23, 23) @[lib.scala 187:36] + _T_2[12] <= _T_69 @[lib.scala 187:30] + node _T_70 = bits(dccm_rdata_hi_any, 23, 23) @[lib.scala 188:36] + _T_3[12] <= _T_70 @[lib.scala 188:30] + node _T_71 = bits(dccm_rdata_hi_any, 23, 23) @[lib.scala 189:36] + _T_4[12] <= _T_71 @[lib.scala 189:30] + node _T_72 = bits(dccm_rdata_hi_any, 24, 24) @[lib.scala 186:36] + _T_1[13] <= _T_72 @[lib.scala 186:30] + node _T_73 = bits(dccm_rdata_hi_any, 24, 24) @[lib.scala 187:36] + _T_2[13] <= _T_73 @[lib.scala 187:30] + node _T_74 = bits(dccm_rdata_hi_any, 24, 24) @[lib.scala 188:36] + _T_3[13] <= _T_74 @[lib.scala 188:30] + node _T_75 = bits(dccm_rdata_hi_any, 24, 24) @[lib.scala 189:36] + _T_4[13] <= _T_75 @[lib.scala 189:30] + node _T_76 = bits(dccm_rdata_hi_any, 25, 25) @[lib.scala 185:36] + _T[14] <= _T_76 @[lib.scala 185:30] + node _T_77 = bits(dccm_rdata_hi_any, 25, 25) @[lib.scala 186:36] + _T_1[14] <= _T_77 @[lib.scala 186:30] + node _T_78 = bits(dccm_rdata_hi_any, 25, 25) @[lib.scala 187:36] + _T_2[14] <= _T_78 @[lib.scala 187:30] + node _T_79 = bits(dccm_rdata_hi_any, 25, 25) @[lib.scala 188:36] + _T_3[14] <= _T_79 @[lib.scala 188:30] + node _T_80 = bits(dccm_rdata_hi_any, 25, 25) @[lib.scala 189:36] + _T_4[14] <= _T_80 @[lib.scala 189:30] + node _T_81 = bits(dccm_rdata_hi_any, 26, 26) @[lib.scala 185:36] + _T[15] <= _T_81 @[lib.scala 185:30] + node _T_82 = bits(dccm_rdata_hi_any, 26, 26) @[lib.scala 190:36] + _T_5[0] <= _T_82 @[lib.scala 190:30] + node _T_83 = bits(dccm_rdata_hi_any, 27, 27) @[lib.scala 186:36] + _T_1[15] <= _T_83 @[lib.scala 186:30] + node _T_84 = bits(dccm_rdata_hi_any, 27, 27) @[lib.scala 190:36] + _T_5[1] <= _T_84 @[lib.scala 190:30] + node _T_85 = bits(dccm_rdata_hi_any, 28, 28) @[lib.scala 185:36] + _T[16] <= _T_85 @[lib.scala 185:30] + node _T_86 = bits(dccm_rdata_hi_any, 28, 28) @[lib.scala 186:36] + _T_1[16] <= _T_86 @[lib.scala 186:30] + node _T_87 = bits(dccm_rdata_hi_any, 28, 28) @[lib.scala 190:36] + _T_5[2] <= _T_87 @[lib.scala 190:30] + node _T_88 = bits(dccm_rdata_hi_any, 29, 29) @[lib.scala 187:36] + _T_2[15] <= _T_88 @[lib.scala 187:30] + node _T_89 = bits(dccm_rdata_hi_any, 29, 29) @[lib.scala 190:36] + _T_5[3] <= _T_89 @[lib.scala 190:30] + node _T_90 = bits(dccm_rdata_hi_any, 30, 30) @[lib.scala 185:36] + _T[17] <= _T_90 @[lib.scala 185:30] + node _T_91 = bits(dccm_rdata_hi_any, 30, 30) @[lib.scala 187:36] + _T_2[16] <= _T_91 @[lib.scala 187:30] + node _T_92 = bits(dccm_rdata_hi_any, 30, 30) @[lib.scala 190:36] + _T_5[4] <= _T_92 @[lib.scala 190:30] + node _T_93 = bits(dccm_rdata_hi_any, 31, 31) @[lib.scala 186:36] + _T_1[17] <= _T_93 @[lib.scala 186:30] + node _T_94 = bits(dccm_rdata_hi_any, 31, 31) @[lib.scala 187:36] + _T_2[17] <= _T_94 @[lib.scala 187:30] + node _T_95 = bits(dccm_rdata_hi_any, 31, 31) @[lib.scala 190:36] + _T_5[5] <= _T_95 @[lib.scala 190:30] + node _T_96 = xorr(dccm_rdata_hi_any) @[lib.scala 193:30] + node _T_97 = xorr(dccm_data_ecc_hi_any) @[lib.scala 193:44] + node _T_98 = xor(_T_96, _T_97) @[lib.scala 193:35] + node _T_99 = not(UInt<1>("h00")) @[lib.scala 193:52] + node _T_100 = and(_T_98, _T_99) @[lib.scala 193:50] + node _T_101 = bits(dccm_data_ecc_hi_any, 5, 5) @[lib.scala 193:68] + node _T_102 = cat(_T_5[2], _T_5[1]) @[lib.scala 193:76] + node _T_103 = cat(_T_102, _T_5[0]) @[lib.scala 193:76] + node _T_104 = cat(_T_5[5], _T_5[4]) @[lib.scala 193:76] + node _T_105 = cat(_T_104, _T_5[3]) @[lib.scala 193:76] + node _T_106 = cat(_T_105, _T_103) @[lib.scala 193:76] + node _T_107 = xorr(_T_106) @[lib.scala 193:83] + node _T_108 = xor(_T_101, _T_107) @[lib.scala 193:71] + node _T_109 = bits(dccm_data_ecc_hi_any, 4, 4) @[lib.scala 193:95] + node _T_110 = cat(_T_4[2], _T_4[1]) @[lib.scala 193:103] + node _T_111 = cat(_T_110, _T_4[0]) @[lib.scala 193:103] + node _T_112 = cat(_T_4[4], _T_4[3]) @[lib.scala 193:103] + node _T_113 = cat(_T_4[6], _T_4[5]) @[lib.scala 193:103] + node _T_114 = cat(_T_113, _T_112) @[lib.scala 193:103] + node _T_115 = cat(_T_114, _T_111) @[lib.scala 193:103] + node _T_116 = cat(_T_4[8], _T_4[7]) @[lib.scala 193:103] + node _T_117 = cat(_T_4[10], _T_4[9]) @[lib.scala 193:103] + node _T_118 = cat(_T_117, _T_116) @[lib.scala 193:103] + node _T_119 = cat(_T_4[12], _T_4[11]) @[lib.scala 193:103] + node _T_120 = cat(_T_4[14], _T_4[13]) @[lib.scala 193:103] + node _T_121 = cat(_T_120, _T_119) @[lib.scala 193:103] + node _T_122 = cat(_T_121, _T_118) @[lib.scala 193:103] + node _T_123 = cat(_T_122, _T_115) @[lib.scala 193:103] + node _T_124 = xorr(_T_123) @[lib.scala 193:110] + node _T_125 = xor(_T_109, _T_124) @[lib.scala 193:98] + node _T_126 = bits(dccm_data_ecc_hi_any, 3, 3) @[lib.scala 193:122] + node _T_127 = cat(_T_3[2], _T_3[1]) @[lib.scala 193:130] + node _T_128 = cat(_T_127, _T_3[0]) @[lib.scala 193:130] + node _T_129 = cat(_T_3[4], _T_3[3]) @[lib.scala 193:130] + node _T_130 = cat(_T_3[6], _T_3[5]) @[lib.scala 193:130] + node _T_131 = cat(_T_130, _T_129) @[lib.scala 193:130] + node _T_132 = cat(_T_131, _T_128) @[lib.scala 193:130] + node _T_133 = cat(_T_3[8], _T_3[7]) @[lib.scala 193:130] + node _T_134 = cat(_T_3[10], _T_3[9]) @[lib.scala 193:130] + node _T_135 = cat(_T_134, _T_133) @[lib.scala 193:130] + node _T_136 = cat(_T_3[12], _T_3[11]) @[lib.scala 193:130] + node _T_137 = cat(_T_3[14], _T_3[13]) @[lib.scala 193:130] + node _T_138 = cat(_T_137, _T_136) @[lib.scala 193:130] + node _T_139 = cat(_T_138, _T_135) @[lib.scala 193:130] + node _T_140 = cat(_T_139, _T_132) @[lib.scala 193:130] + node _T_141 = xorr(_T_140) @[lib.scala 193:137] + node _T_142 = xor(_T_126, _T_141) @[lib.scala 193:125] + node _T_143 = bits(dccm_data_ecc_hi_any, 2, 2) @[lib.scala 193:149] + node _T_144 = cat(_T_2[1], _T_2[0]) @[lib.scala 193:157] + node _T_145 = cat(_T_2[3], _T_2[2]) @[lib.scala 193:157] + node _T_146 = cat(_T_145, _T_144) @[lib.scala 193:157] + node _T_147 = cat(_T_2[5], _T_2[4]) @[lib.scala 193:157] + node _T_148 = cat(_T_2[8], _T_2[7]) @[lib.scala 193:157] + node _T_149 = cat(_T_148, _T_2[6]) @[lib.scala 193:157] + node _T_150 = cat(_T_149, _T_147) @[lib.scala 193:157] + node _T_151 = cat(_T_150, _T_146) @[lib.scala 193:157] + node _T_152 = cat(_T_2[10], _T_2[9]) @[lib.scala 193:157] + node _T_153 = cat(_T_2[12], _T_2[11]) @[lib.scala 193:157] + node _T_154 = cat(_T_153, _T_152) @[lib.scala 193:157] + node _T_155 = cat(_T_2[14], _T_2[13]) @[lib.scala 193:157] + node _T_156 = cat(_T_2[17], _T_2[16]) @[lib.scala 193:157] + node _T_157 = cat(_T_156, _T_2[15]) @[lib.scala 193:157] + node _T_158 = cat(_T_157, _T_155) @[lib.scala 193:157] + node _T_159 = cat(_T_158, _T_154) @[lib.scala 193:157] + node _T_160 = cat(_T_159, _T_151) @[lib.scala 193:157] + node _T_161 = xorr(_T_160) @[lib.scala 193:164] + node _T_162 = xor(_T_143, _T_161) @[lib.scala 193:152] + node _T_163 = bits(dccm_data_ecc_hi_any, 1, 1) @[lib.scala 193:176] + node _T_164 = cat(_T_1[1], _T_1[0]) @[lib.scala 193:184] + node _T_165 = cat(_T_1[3], _T_1[2]) @[lib.scala 193:184] + node _T_166 = cat(_T_165, _T_164) @[lib.scala 193:184] + node _T_167 = cat(_T_1[5], _T_1[4]) @[lib.scala 193:184] + node _T_168 = cat(_T_1[8], _T_1[7]) @[lib.scala 193:184] + node _T_169 = cat(_T_168, _T_1[6]) @[lib.scala 193:184] + node _T_170 = cat(_T_169, _T_167) @[lib.scala 193:184] + node _T_171 = cat(_T_170, _T_166) @[lib.scala 193:184] + node _T_172 = cat(_T_1[10], _T_1[9]) @[lib.scala 193:184] + node _T_173 = cat(_T_1[12], _T_1[11]) @[lib.scala 193:184] + node _T_174 = cat(_T_173, _T_172) @[lib.scala 193:184] + node _T_175 = cat(_T_1[14], _T_1[13]) @[lib.scala 193:184] + node _T_176 = cat(_T_1[17], _T_1[16]) @[lib.scala 193:184] + node _T_177 = cat(_T_176, _T_1[15]) @[lib.scala 193:184] + node _T_178 = cat(_T_177, _T_175) @[lib.scala 193:184] + node _T_179 = cat(_T_178, _T_174) @[lib.scala 193:184] + node _T_180 = cat(_T_179, _T_171) @[lib.scala 193:184] + node _T_181 = xorr(_T_180) @[lib.scala 193:191] + node _T_182 = xor(_T_163, _T_181) @[lib.scala 193:179] + node _T_183 = bits(dccm_data_ecc_hi_any, 0, 0) @[lib.scala 193:203] + node _T_184 = cat(_T[1], _T[0]) @[lib.scala 193:211] + node _T_185 = cat(_T[3], _T[2]) @[lib.scala 193:211] + node _T_186 = cat(_T_185, _T_184) @[lib.scala 193:211] + node _T_187 = cat(_T[5], _T[4]) @[lib.scala 193:211] + node _T_188 = cat(_T[8], _T[7]) @[lib.scala 193:211] + node _T_189 = cat(_T_188, _T[6]) @[lib.scala 193:211] + node _T_190 = cat(_T_189, _T_187) @[lib.scala 193:211] + node _T_191 = cat(_T_190, _T_186) @[lib.scala 193:211] + node _T_192 = cat(_T[10], _T[9]) @[lib.scala 193:211] + node _T_193 = cat(_T[12], _T[11]) @[lib.scala 193:211] + node _T_194 = cat(_T_193, _T_192) @[lib.scala 193:211] + node _T_195 = cat(_T[14], _T[13]) @[lib.scala 193:211] + node _T_196 = cat(_T[17], _T[16]) @[lib.scala 193:211] + node _T_197 = cat(_T_196, _T[15]) @[lib.scala 193:211] + node _T_198 = cat(_T_197, _T_195) @[lib.scala 193:211] + node _T_199 = cat(_T_198, _T_194) @[lib.scala 193:211] + node _T_200 = cat(_T_199, _T_191) @[lib.scala 193:211] + node _T_201 = xorr(_T_200) @[lib.scala 193:218] + node _T_202 = xor(_T_183, _T_201) @[lib.scala 193:206] node _T_203 = cat(_T_162, _T_182) @[Cat.scala 29:58] node _T_204 = cat(_T_203, _T_202) @[Cat.scala 29:58] node _T_205 = cat(_T_125, _T_142) @[Cat.scala 29:58] node _T_206 = cat(_T_100, _T_108) @[Cat.scala 29:58] node _T_207 = cat(_T_206, _T_205) @[Cat.scala 29:58] node _T_208 = cat(_T_207, _T_204) @[Cat.scala 29:58] - node _T_209 = neq(_T_208, UInt<1>("h00")) @[el2_lib.scala 334:44] - node _T_210 = and(is_ldst_hi_any, _T_209) @[el2_lib.scala 334:32] - node _T_211 = bits(_T_208, 6, 6) @[el2_lib.scala 334:64] - node single_ecc_error_hi_any = and(_T_210, _T_211) @[el2_lib.scala 334:53] - node _T_212 = neq(_T_208, UInt<1>("h00")) @[el2_lib.scala 335:44] - node _T_213 = and(is_ldst_hi_any, _T_212) @[el2_lib.scala 335:32] - node _T_214 = bits(_T_208, 6, 6) @[el2_lib.scala 335:65] - node _T_215 = not(_T_214) @[el2_lib.scala 335:55] - node double_ecc_error_hi_any = and(_T_213, _T_215) @[el2_lib.scala 335:53] - wire _T_216 : UInt<1>[39] @[el2_lib.scala 336:26] - node _T_217 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_218 = eq(_T_217, UInt<1>("h01")) @[el2_lib.scala 339:41] - _T_216[0] <= _T_218 @[el2_lib.scala 339:23] - node _T_219 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_220 = eq(_T_219, UInt<2>("h02")) @[el2_lib.scala 339:41] - _T_216[1] <= _T_220 @[el2_lib.scala 339:23] - node _T_221 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_222 = eq(_T_221, UInt<2>("h03")) @[el2_lib.scala 339:41] - _T_216[2] <= _T_222 @[el2_lib.scala 339:23] - node _T_223 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_224 = eq(_T_223, UInt<3>("h04")) @[el2_lib.scala 339:41] - _T_216[3] <= _T_224 @[el2_lib.scala 339:23] - node _T_225 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_226 = eq(_T_225, UInt<3>("h05")) @[el2_lib.scala 339:41] - _T_216[4] <= _T_226 @[el2_lib.scala 339:23] - node _T_227 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_228 = eq(_T_227, UInt<3>("h06")) @[el2_lib.scala 339:41] - _T_216[5] <= _T_228 @[el2_lib.scala 339:23] - node _T_229 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_230 = eq(_T_229, UInt<3>("h07")) @[el2_lib.scala 339:41] - _T_216[6] <= _T_230 @[el2_lib.scala 339:23] - node _T_231 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_232 = eq(_T_231, UInt<4>("h08")) @[el2_lib.scala 339:41] - _T_216[7] <= _T_232 @[el2_lib.scala 339:23] - node _T_233 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_234 = eq(_T_233, UInt<4>("h09")) @[el2_lib.scala 339:41] - _T_216[8] <= _T_234 @[el2_lib.scala 339:23] - node _T_235 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_236 = eq(_T_235, UInt<4>("h0a")) @[el2_lib.scala 339:41] - _T_216[9] <= _T_236 @[el2_lib.scala 339:23] - node _T_237 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_238 = eq(_T_237, UInt<4>("h0b")) @[el2_lib.scala 339:41] - _T_216[10] <= _T_238 @[el2_lib.scala 339:23] - node _T_239 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_240 = eq(_T_239, UInt<4>("h0c")) @[el2_lib.scala 339:41] - _T_216[11] <= _T_240 @[el2_lib.scala 339:23] - node _T_241 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_242 = eq(_T_241, UInt<4>("h0d")) @[el2_lib.scala 339:41] - _T_216[12] <= _T_242 @[el2_lib.scala 339:23] - node _T_243 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_244 = eq(_T_243, UInt<4>("h0e")) @[el2_lib.scala 339:41] - _T_216[13] <= _T_244 @[el2_lib.scala 339:23] - node _T_245 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_246 = eq(_T_245, UInt<4>("h0f")) @[el2_lib.scala 339:41] - _T_216[14] <= _T_246 @[el2_lib.scala 339:23] - node _T_247 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_248 = eq(_T_247, UInt<5>("h010")) @[el2_lib.scala 339:41] - _T_216[15] <= _T_248 @[el2_lib.scala 339:23] - node _T_249 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_250 = eq(_T_249, UInt<5>("h011")) @[el2_lib.scala 339:41] - _T_216[16] <= _T_250 @[el2_lib.scala 339:23] - node _T_251 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_252 = eq(_T_251, UInt<5>("h012")) @[el2_lib.scala 339:41] - _T_216[17] <= _T_252 @[el2_lib.scala 339:23] - node _T_253 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_254 = eq(_T_253, UInt<5>("h013")) @[el2_lib.scala 339:41] - _T_216[18] <= _T_254 @[el2_lib.scala 339:23] - node _T_255 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_256 = eq(_T_255, UInt<5>("h014")) @[el2_lib.scala 339:41] - _T_216[19] <= _T_256 @[el2_lib.scala 339:23] - node _T_257 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_258 = eq(_T_257, UInt<5>("h015")) @[el2_lib.scala 339:41] - _T_216[20] <= _T_258 @[el2_lib.scala 339:23] - node _T_259 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_260 = eq(_T_259, UInt<5>("h016")) @[el2_lib.scala 339:41] - _T_216[21] <= _T_260 @[el2_lib.scala 339:23] - node _T_261 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_262 = eq(_T_261, UInt<5>("h017")) @[el2_lib.scala 339:41] - _T_216[22] <= _T_262 @[el2_lib.scala 339:23] - node _T_263 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_264 = eq(_T_263, UInt<5>("h018")) @[el2_lib.scala 339:41] - _T_216[23] <= _T_264 @[el2_lib.scala 339:23] - node _T_265 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_266 = eq(_T_265, UInt<5>("h019")) @[el2_lib.scala 339:41] - _T_216[24] <= _T_266 @[el2_lib.scala 339:23] - node _T_267 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_268 = eq(_T_267, UInt<5>("h01a")) @[el2_lib.scala 339:41] - _T_216[25] <= _T_268 @[el2_lib.scala 339:23] - node _T_269 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_270 = eq(_T_269, UInt<5>("h01b")) @[el2_lib.scala 339:41] - _T_216[26] <= _T_270 @[el2_lib.scala 339:23] - node _T_271 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_272 = eq(_T_271, UInt<5>("h01c")) @[el2_lib.scala 339:41] - _T_216[27] <= _T_272 @[el2_lib.scala 339:23] - node _T_273 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_274 = eq(_T_273, UInt<5>("h01d")) @[el2_lib.scala 339:41] - _T_216[28] <= _T_274 @[el2_lib.scala 339:23] - node _T_275 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_276 = eq(_T_275, UInt<5>("h01e")) @[el2_lib.scala 339:41] - _T_216[29] <= _T_276 @[el2_lib.scala 339:23] - node _T_277 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_278 = eq(_T_277, UInt<5>("h01f")) @[el2_lib.scala 339:41] - _T_216[30] <= _T_278 @[el2_lib.scala 339:23] - node _T_279 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_280 = eq(_T_279, UInt<6>("h020")) @[el2_lib.scala 339:41] - _T_216[31] <= _T_280 @[el2_lib.scala 339:23] - node _T_281 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_282 = eq(_T_281, UInt<6>("h021")) @[el2_lib.scala 339:41] - _T_216[32] <= _T_282 @[el2_lib.scala 339:23] - node _T_283 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_284 = eq(_T_283, UInt<6>("h022")) @[el2_lib.scala 339:41] - _T_216[33] <= _T_284 @[el2_lib.scala 339:23] - node _T_285 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_286 = eq(_T_285, UInt<6>("h023")) @[el2_lib.scala 339:41] - _T_216[34] <= _T_286 @[el2_lib.scala 339:23] - node _T_287 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_288 = eq(_T_287, UInt<6>("h024")) @[el2_lib.scala 339:41] - _T_216[35] <= _T_288 @[el2_lib.scala 339:23] - node _T_289 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_290 = eq(_T_289, UInt<6>("h025")) @[el2_lib.scala 339:41] - _T_216[36] <= _T_290 @[el2_lib.scala 339:23] - node _T_291 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_292 = eq(_T_291, UInt<6>("h026")) @[el2_lib.scala 339:41] - _T_216[37] <= _T_292 @[el2_lib.scala 339:23] - node _T_293 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] - node _T_294 = eq(_T_293, UInt<6>("h027")) @[el2_lib.scala 339:41] - _T_216[38] <= _T_294 @[el2_lib.scala 339:23] - node _T_295 = bits(dccm_data_ecc_hi_any, 6, 6) @[el2_lib.scala 341:37] - node _T_296 = bits(dccm_rdata_hi_any, 31, 26) @[el2_lib.scala 341:45] - node _T_297 = bits(dccm_data_ecc_hi_any, 5, 5) @[el2_lib.scala 341:60] - node _T_298 = bits(dccm_rdata_hi_any, 25, 11) @[el2_lib.scala 341:68] - node _T_299 = bits(dccm_data_ecc_hi_any, 4, 4) @[el2_lib.scala 341:83] - node _T_300 = bits(dccm_rdata_hi_any, 10, 4) @[el2_lib.scala 341:91] - node _T_301 = bits(dccm_data_ecc_hi_any, 3, 3) @[el2_lib.scala 341:105] - node _T_302 = bits(dccm_rdata_hi_any, 3, 1) @[el2_lib.scala 341:113] - node _T_303 = bits(dccm_data_ecc_hi_any, 2, 2) @[el2_lib.scala 341:126] - node _T_304 = bits(dccm_rdata_hi_any, 0, 0) @[el2_lib.scala 341:134] - node _T_305 = bits(dccm_data_ecc_hi_any, 1, 0) @[el2_lib.scala 341:145] + node _T_209 = neq(_T_208, UInt<1>("h00")) @[lib.scala 194:44] + node _T_210 = and(is_ldst_hi_any, _T_209) @[lib.scala 194:32] + node _T_211 = bits(_T_208, 6, 6) @[lib.scala 194:64] + node single_ecc_error_hi_any = and(_T_210, _T_211) @[lib.scala 194:53] + node _T_212 = neq(_T_208, UInt<1>("h00")) @[lib.scala 195:44] + node _T_213 = and(is_ldst_hi_any, _T_212) @[lib.scala 195:32] + node _T_214 = bits(_T_208, 6, 6) @[lib.scala 195:65] + node _T_215 = not(_T_214) @[lib.scala 195:55] + node double_ecc_error_hi_any = and(_T_213, _T_215) @[lib.scala 195:53] + wire _T_216 : UInt<1>[39] @[lib.scala 196:26] + node _T_217 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_218 = eq(_T_217, UInt<1>("h01")) @[lib.scala 199:41] + _T_216[0] <= _T_218 @[lib.scala 199:23] + node _T_219 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_220 = eq(_T_219, UInt<2>("h02")) @[lib.scala 199:41] + _T_216[1] <= _T_220 @[lib.scala 199:23] + node _T_221 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_222 = eq(_T_221, UInt<2>("h03")) @[lib.scala 199:41] + _T_216[2] <= _T_222 @[lib.scala 199:23] + node _T_223 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_224 = eq(_T_223, UInt<3>("h04")) @[lib.scala 199:41] + _T_216[3] <= _T_224 @[lib.scala 199:23] + node _T_225 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_226 = eq(_T_225, UInt<3>("h05")) @[lib.scala 199:41] + _T_216[4] <= _T_226 @[lib.scala 199:23] + node _T_227 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_228 = eq(_T_227, UInt<3>("h06")) @[lib.scala 199:41] + _T_216[5] <= _T_228 @[lib.scala 199:23] + node _T_229 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_230 = eq(_T_229, UInt<3>("h07")) @[lib.scala 199:41] + _T_216[6] <= _T_230 @[lib.scala 199:23] + node _T_231 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_232 = eq(_T_231, UInt<4>("h08")) @[lib.scala 199:41] + _T_216[7] <= _T_232 @[lib.scala 199:23] + node _T_233 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_234 = eq(_T_233, UInt<4>("h09")) @[lib.scala 199:41] + _T_216[8] <= _T_234 @[lib.scala 199:23] + node _T_235 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_236 = eq(_T_235, UInt<4>("h0a")) @[lib.scala 199:41] + _T_216[9] <= _T_236 @[lib.scala 199:23] + node _T_237 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_238 = eq(_T_237, UInt<4>("h0b")) @[lib.scala 199:41] + _T_216[10] <= _T_238 @[lib.scala 199:23] + node _T_239 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_240 = eq(_T_239, UInt<4>("h0c")) @[lib.scala 199:41] + _T_216[11] <= _T_240 @[lib.scala 199:23] + node _T_241 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_242 = eq(_T_241, UInt<4>("h0d")) @[lib.scala 199:41] + _T_216[12] <= _T_242 @[lib.scala 199:23] + node _T_243 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_244 = eq(_T_243, UInt<4>("h0e")) @[lib.scala 199:41] + _T_216[13] <= _T_244 @[lib.scala 199:23] + node _T_245 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_246 = eq(_T_245, UInt<4>("h0f")) @[lib.scala 199:41] + _T_216[14] <= _T_246 @[lib.scala 199:23] + node _T_247 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_248 = eq(_T_247, UInt<5>("h010")) @[lib.scala 199:41] + _T_216[15] <= _T_248 @[lib.scala 199:23] + node _T_249 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_250 = eq(_T_249, UInt<5>("h011")) @[lib.scala 199:41] + _T_216[16] <= _T_250 @[lib.scala 199:23] + node _T_251 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_252 = eq(_T_251, UInt<5>("h012")) @[lib.scala 199:41] + _T_216[17] <= _T_252 @[lib.scala 199:23] + node _T_253 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_254 = eq(_T_253, UInt<5>("h013")) @[lib.scala 199:41] + _T_216[18] <= _T_254 @[lib.scala 199:23] + node _T_255 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_256 = eq(_T_255, UInt<5>("h014")) @[lib.scala 199:41] + _T_216[19] <= _T_256 @[lib.scala 199:23] + node _T_257 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_258 = eq(_T_257, UInt<5>("h015")) @[lib.scala 199:41] + _T_216[20] <= _T_258 @[lib.scala 199:23] + node _T_259 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_260 = eq(_T_259, UInt<5>("h016")) @[lib.scala 199:41] + _T_216[21] <= _T_260 @[lib.scala 199:23] + node _T_261 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_262 = eq(_T_261, UInt<5>("h017")) @[lib.scala 199:41] + _T_216[22] <= _T_262 @[lib.scala 199:23] + node _T_263 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_264 = eq(_T_263, UInt<5>("h018")) @[lib.scala 199:41] + _T_216[23] <= _T_264 @[lib.scala 199:23] + node _T_265 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_266 = eq(_T_265, UInt<5>("h019")) @[lib.scala 199:41] + _T_216[24] <= _T_266 @[lib.scala 199:23] + node _T_267 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_268 = eq(_T_267, UInt<5>("h01a")) @[lib.scala 199:41] + _T_216[25] <= _T_268 @[lib.scala 199:23] + node _T_269 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_270 = eq(_T_269, UInt<5>("h01b")) @[lib.scala 199:41] + _T_216[26] <= _T_270 @[lib.scala 199:23] + node _T_271 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_272 = eq(_T_271, UInt<5>("h01c")) @[lib.scala 199:41] + _T_216[27] <= _T_272 @[lib.scala 199:23] + node _T_273 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_274 = eq(_T_273, UInt<5>("h01d")) @[lib.scala 199:41] + _T_216[28] <= _T_274 @[lib.scala 199:23] + node _T_275 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_276 = eq(_T_275, UInt<5>("h01e")) @[lib.scala 199:41] + _T_216[29] <= _T_276 @[lib.scala 199:23] + node _T_277 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_278 = eq(_T_277, UInt<5>("h01f")) @[lib.scala 199:41] + _T_216[30] <= _T_278 @[lib.scala 199:23] + node _T_279 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_280 = eq(_T_279, UInt<6>("h020")) @[lib.scala 199:41] + _T_216[31] <= _T_280 @[lib.scala 199:23] + node _T_281 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_282 = eq(_T_281, UInt<6>("h021")) @[lib.scala 199:41] + _T_216[32] <= _T_282 @[lib.scala 199:23] + node _T_283 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_284 = eq(_T_283, UInt<6>("h022")) @[lib.scala 199:41] + _T_216[33] <= _T_284 @[lib.scala 199:23] + node _T_285 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_286 = eq(_T_285, UInt<6>("h023")) @[lib.scala 199:41] + _T_216[34] <= _T_286 @[lib.scala 199:23] + node _T_287 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_288 = eq(_T_287, UInt<6>("h024")) @[lib.scala 199:41] + _T_216[35] <= _T_288 @[lib.scala 199:23] + node _T_289 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_290 = eq(_T_289, UInt<6>("h025")) @[lib.scala 199:41] + _T_216[36] <= _T_290 @[lib.scala 199:23] + node _T_291 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_292 = eq(_T_291, UInt<6>("h026")) @[lib.scala 199:41] + _T_216[37] <= _T_292 @[lib.scala 199:23] + node _T_293 = bits(_T_208, 5, 0) @[lib.scala 199:35] + node _T_294 = eq(_T_293, UInt<6>("h027")) @[lib.scala 199:41] + _T_216[38] <= _T_294 @[lib.scala 199:23] + node _T_295 = bits(dccm_data_ecc_hi_any, 6, 6) @[lib.scala 201:37] + node _T_296 = bits(dccm_rdata_hi_any, 31, 26) @[lib.scala 201:45] + node _T_297 = bits(dccm_data_ecc_hi_any, 5, 5) @[lib.scala 201:60] + node _T_298 = bits(dccm_rdata_hi_any, 25, 11) @[lib.scala 201:68] + node _T_299 = bits(dccm_data_ecc_hi_any, 4, 4) @[lib.scala 201:83] + node _T_300 = bits(dccm_rdata_hi_any, 10, 4) @[lib.scala 201:91] + node _T_301 = bits(dccm_data_ecc_hi_any, 3, 3) @[lib.scala 201:105] + node _T_302 = bits(dccm_rdata_hi_any, 3, 1) @[lib.scala 201:113] + node _T_303 = bits(dccm_data_ecc_hi_any, 2, 2) @[lib.scala 201:126] + node _T_304 = bits(dccm_rdata_hi_any, 0, 0) @[lib.scala 201:134] + node _T_305 = bits(dccm_data_ecc_hi_any, 1, 0) @[lib.scala 201:145] node _T_306 = cat(_T_304, _T_305) @[Cat.scala 29:58] node _T_307 = cat(_T_301, _T_302) @[Cat.scala 29:58] node _T_308 = cat(_T_307, _T_303) @[Cat.scala 29:58] @@ -91899,507 +91891,507 @@ circuit quasar_wrapper : node _T_313 = cat(_T_312, _T_297) @[Cat.scala 29:58] node _T_314 = cat(_T_313, _T_311) @[Cat.scala 29:58] node _T_315 = cat(_T_314, _T_309) @[Cat.scala 29:58] - node _T_316 = bits(single_ecc_error_hi_any, 0, 0) @[el2_lib.scala 342:49] - node _T_317 = cat(_T_216[1], _T_216[0]) @[el2_lib.scala 342:69] - node _T_318 = cat(_T_216[3], _T_216[2]) @[el2_lib.scala 342:69] - node _T_319 = cat(_T_318, _T_317) @[el2_lib.scala 342:69] - node _T_320 = cat(_T_216[5], _T_216[4]) @[el2_lib.scala 342:69] - node _T_321 = cat(_T_216[8], _T_216[7]) @[el2_lib.scala 342:69] - node _T_322 = cat(_T_321, _T_216[6]) @[el2_lib.scala 342:69] - node _T_323 = cat(_T_322, _T_320) @[el2_lib.scala 342:69] - node _T_324 = cat(_T_323, _T_319) @[el2_lib.scala 342:69] - node _T_325 = cat(_T_216[10], _T_216[9]) @[el2_lib.scala 342:69] - node _T_326 = cat(_T_216[13], _T_216[12]) @[el2_lib.scala 342:69] - node _T_327 = cat(_T_326, _T_216[11]) @[el2_lib.scala 342:69] - node _T_328 = cat(_T_327, _T_325) @[el2_lib.scala 342:69] - node _T_329 = cat(_T_216[15], _T_216[14]) @[el2_lib.scala 342:69] - node _T_330 = cat(_T_216[18], _T_216[17]) @[el2_lib.scala 342:69] - node _T_331 = cat(_T_330, _T_216[16]) @[el2_lib.scala 342:69] - node _T_332 = cat(_T_331, _T_329) @[el2_lib.scala 342:69] - node _T_333 = cat(_T_332, _T_328) @[el2_lib.scala 342:69] - node _T_334 = cat(_T_333, _T_324) @[el2_lib.scala 342:69] - node _T_335 = cat(_T_216[20], _T_216[19]) @[el2_lib.scala 342:69] - node _T_336 = cat(_T_216[23], _T_216[22]) @[el2_lib.scala 342:69] - node _T_337 = cat(_T_336, _T_216[21]) @[el2_lib.scala 342:69] - node _T_338 = cat(_T_337, _T_335) @[el2_lib.scala 342:69] - node _T_339 = cat(_T_216[25], _T_216[24]) @[el2_lib.scala 342:69] - node _T_340 = cat(_T_216[28], _T_216[27]) @[el2_lib.scala 342:69] - node _T_341 = cat(_T_340, _T_216[26]) @[el2_lib.scala 342:69] - node _T_342 = cat(_T_341, _T_339) @[el2_lib.scala 342:69] - node _T_343 = cat(_T_342, _T_338) @[el2_lib.scala 342:69] - node _T_344 = cat(_T_216[30], _T_216[29]) @[el2_lib.scala 342:69] - node _T_345 = cat(_T_216[33], _T_216[32]) @[el2_lib.scala 342:69] - node _T_346 = cat(_T_345, _T_216[31]) @[el2_lib.scala 342:69] - node _T_347 = cat(_T_346, _T_344) @[el2_lib.scala 342:69] - node _T_348 = cat(_T_216[35], _T_216[34]) @[el2_lib.scala 342:69] - node _T_349 = cat(_T_216[38], _T_216[37]) @[el2_lib.scala 342:69] - node _T_350 = cat(_T_349, _T_216[36]) @[el2_lib.scala 342:69] - node _T_351 = cat(_T_350, _T_348) @[el2_lib.scala 342:69] - node _T_352 = cat(_T_351, _T_347) @[el2_lib.scala 342:69] - node _T_353 = cat(_T_352, _T_343) @[el2_lib.scala 342:69] - node _T_354 = cat(_T_353, _T_334) @[el2_lib.scala 342:69] - node _T_355 = xor(_T_354, _T_315) @[el2_lib.scala 342:76] - node _T_356 = mux(_T_316, _T_355, _T_315) @[el2_lib.scala 342:31] - node _T_357 = bits(_T_356, 37, 32) @[el2_lib.scala 344:37] - node _T_358 = bits(_T_356, 30, 16) @[el2_lib.scala 344:61] - node _T_359 = bits(_T_356, 14, 8) @[el2_lib.scala 344:86] - node _T_360 = bits(_T_356, 6, 4) @[el2_lib.scala 344:110] - node _T_361 = bits(_T_356, 2, 2) @[el2_lib.scala 344:133] + node _T_316 = bits(single_ecc_error_hi_any, 0, 0) @[lib.scala 202:49] + node _T_317 = cat(_T_216[1], _T_216[0]) @[lib.scala 202:69] + node _T_318 = cat(_T_216[3], _T_216[2]) @[lib.scala 202:69] + node _T_319 = cat(_T_318, _T_317) @[lib.scala 202:69] + node _T_320 = cat(_T_216[5], _T_216[4]) @[lib.scala 202:69] + node _T_321 = cat(_T_216[8], _T_216[7]) @[lib.scala 202:69] + node _T_322 = cat(_T_321, _T_216[6]) @[lib.scala 202:69] + node _T_323 = cat(_T_322, _T_320) @[lib.scala 202:69] + node _T_324 = cat(_T_323, _T_319) @[lib.scala 202:69] + node _T_325 = cat(_T_216[10], _T_216[9]) @[lib.scala 202:69] + node _T_326 = cat(_T_216[13], _T_216[12]) @[lib.scala 202:69] + node _T_327 = cat(_T_326, _T_216[11]) @[lib.scala 202:69] + node _T_328 = cat(_T_327, _T_325) @[lib.scala 202:69] + node _T_329 = cat(_T_216[15], _T_216[14]) @[lib.scala 202:69] + node _T_330 = cat(_T_216[18], _T_216[17]) @[lib.scala 202:69] + node _T_331 = cat(_T_330, _T_216[16]) @[lib.scala 202:69] + node _T_332 = cat(_T_331, _T_329) @[lib.scala 202:69] + node _T_333 = cat(_T_332, _T_328) @[lib.scala 202:69] + node _T_334 = cat(_T_333, _T_324) @[lib.scala 202:69] + node _T_335 = cat(_T_216[20], _T_216[19]) @[lib.scala 202:69] + node _T_336 = cat(_T_216[23], _T_216[22]) @[lib.scala 202:69] + node _T_337 = cat(_T_336, _T_216[21]) @[lib.scala 202:69] + node _T_338 = cat(_T_337, _T_335) @[lib.scala 202:69] + node _T_339 = cat(_T_216[25], _T_216[24]) @[lib.scala 202:69] + node _T_340 = cat(_T_216[28], _T_216[27]) @[lib.scala 202:69] + node _T_341 = cat(_T_340, _T_216[26]) @[lib.scala 202:69] + node _T_342 = cat(_T_341, _T_339) @[lib.scala 202:69] + node _T_343 = cat(_T_342, _T_338) @[lib.scala 202:69] + node _T_344 = cat(_T_216[30], _T_216[29]) @[lib.scala 202:69] + node _T_345 = cat(_T_216[33], _T_216[32]) @[lib.scala 202:69] + node _T_346 = cat(_T_345, _T_216[31]) @[lib.scala 202:69] + node _T_347 = cat(_T_346, _T_344) @[lib.scala 202:69] + node _T_348 = cat(_T_216[35], _T_216[34]) @[lib.scala 202:69] + node _T_349 = cat(_T_216[38], _T_216[37]) @[lib.scala 202:69] + node _T_350 = cat(_T_349, _T_216[36]) @[lib.scala 202:69] + node _T_351 = cat(_T_350, _T_348) @[lib.scala 202:69] + node _T_352 = cat(_T_351, _T_347) @[lib.scala 202:69] + node _T_353 = cat(_T_352, _T_343) @[lib.scala 202:69] + node _T_354 = cat(_T_353, _T_334) @[lib.scala 202:69] + node _T_355 = xor(_T_354, _T_315) @[lib.scala 202:76] + node _T_356 = mux(_T_316, _T_355, _T_315) @[lib.scala 202:31] + node _T_357 = bits(_T_356, 37, 32) @[lib.scala 204:37] + node _T_358 = bits(_T_356, 30, 16) @[lib.scala 204:61] + node _T_359 = bits(_T_356, 14, 8) @[lib.scala 204:86] + node _T_360 = bits(_T_356, 6, 4) @[lib.scala 204:110] + node _T_361 = bits(_T_356, 2, 2) @[lib.scala 204:133] node _T_362 = cat(_T_360, _T_361) @[Cat.scala 29:58] node _T_363 = cat(_T_357, _T_358) @[Cat.scala 29:58] node _T_364 = cat(_T_363, _T_359) @[Cat.scala 29:58] node sec_data_hi_any = cat(_T_364, _T_362) @[Cat.scala 29:58] - node _T_365 = bits(_T_356, 38, 38) @[el2_lib.scala 345:39] - node _T_366 = bits(_T_208, 6, 0) @[el2_lib.scala 345:56] - node _T_367 = eq(_T_366, UInt<7>("h040")) @[el2_lib.scala 345:62] - node _T_368 = xor(_T_365, _T_367) @[el2_lib.scala 345:44] - node _T_369 = bits(_T_356, 31, 31) @[el2_lib.scala 345:102] - node _T_370 = bits(_T_356, 15, 15) @[el2_lib.scala 345:124] - node _T_371 = bits(_T_356, 7, 7) @[el2_lib.scala 345:146] - node _T_372 = bits(_T_356, 3, 3) @[el2_lib.scala 345:167] - node _T_373 = bits(_T_356, 1, 0) @[el2_lib.scala 345:188] + node _T_365 = bits(_T_356, 38, 38) @[lib.scala 205:39] + node _T_366 = bits(_T_208, 6, 0) @[lib.scala 205:56] + node _T_367 = eq(_T_366, UInt<7>("h040")) @[lib.scala 205:62] + node _T_368 = xor(_T_365, _T_367) @[lib.scala 205:44] + node _T_369 = bits(_T_356, 31, 31) @[lib.scala 205:102] + node _T_370 = bits(_T_356, 15, 15) @[lib.scala 205:124] + node _T_371 = bits(_T_356, 7, 7) @[lib.scala 205:146] + node _T_372 = bits(_T_356, 3, 3) @[lib.scala 205:167] + node _T_373 = bits(_T_356, 1, 0) @[lib.scala 205:188] node _T_374 = cat(_T_371, _T_372) @[Cat.scala 29:58] node _T_375 = cat(_T_374, _T_373) @[Cat.scala 29:58] node _T_376 = cat(_T_368, _T_369) @[Cat.scala 29:58] node _T_377 = cat(_T_376, _T_370) @[Cat.scala 29:58] node ecc_out_hi_nc = cat(_T_377, _T_375) @[Cat.scala 29:58] - wire _T_378 : UInt<1>[18] @[el2_lib.scala 313:18] - wire _T_379 : UInt<1>[18] @[el2_lib.scala 314:18] - wire _T_380 : UInt<1>[18] @[el2_lib.scala 315:18] - wire _T_381 : UInt<1>[15] @[el2_lib.scala 316:18] - wire _T_382 : UInt<1>[15] @[el2_lib.scala 317:18] - wire _T_383 : UInt<1>[6] @[el2_lib.scala 318:18] - node _T_384 = bits(dccm_rdata_lo_any, 0, 0) @[el2_lib.scala 325:36] - _T_378[0] <= _T_384 @[el2_lib.scala 325:30] - node _T_385 = bits(dccm_rdata_lo_any, 0, 0) @[el2_lib.scala 326:36] - _T_379[0] <= _T_385 @[el2_lib.scala 326:30] - node _T_386 = bits(dccm_rdata_lo_any, 1, 1) @[el2_lib.scala 325:36] - _T_378[1] <= _T_386 @[el2_lib.scala 325:30] - node _T_387 = bits(dccm_rdata_lo_any, 1, 1) @[el2_lib.scala 327:36] - _T_380[0] <= _T_387 @[el2_lib.scala 327:30] - node _T_388 = bits(dccm_rdata_lo_any, 2, 2) @[el2_lib.scala 326:36] - _T_379[1] <= _T_388 @[el2_lib.scala 326:30] - node _T_389 = bits(dccm_rdata_lo_any, 2, 2) @[el2_lib.scala 327:36] - _T_380[1] <= _T_389 @[el2_lib.scala 327:30] - node _T_390 = bits(dccm_rdata_lo_any, 3, 3) @[el2_lib.scala 325:36] - _T_378[2] <= _T_390 @[el2_lib.scala 325:30] - node _T_391 = bits(dccm_rdata_lo_any, 3, 3) @[el2_lib.scala 326:36] - _T_379[2] <= _T_391 @[el2_lib.scala 326:30] - node _T_392 = bits(dccm_rdata_lo_any, 3, 3) @[el2_lib.scala 327:36] - _T_380[2] <= _T_392 @[el2_lib.scala 327:30] - node _T_393 = bits(dccm_rdata_lo_any, 4, 4) @[el2_lib.scala 325:36] - _T_378[3] <= _T_393 @[el2_lib.scala 325:30] - node _T_394 = bits(dccm_rdata_lo_any, 4, 4) @[el2_lib.scala 328:36] - _T_381[0] <= _T_394 @[el2_lib.scala 328:30] - node _T_395 = bits(dccm_rdata_lo_any, 5, 5) @[el2_lib.scala 326:36] - _T_379[3] <= _T_395 @[el2_lib.scala 326:30] - node _T_396 = bits(dccm_rdata_lo_any, 5, 5) @[el2_lib.scala 328:36] - _T_381[1] <= _T_396 @[el2_lib.scala 328:30] - node _T_397 = bits(dccm_rdata_lo_any, 6, 6) @[el2_lib.scala 325:36] - _T_378[4] <= _T_397 @[el2_lib.scala 325:30] - node _T_398 = bits(dccm_rdata_lo_any, 6, 6) @[el2_lib.scala 326:36] - _T_379[4] <= _T_398 @[el2_lib.scala 326:30] - node _T_399 = bits(dccm_rdata_lo_any, 6, 6) @[el2_lib.scala 328:36] - _T_381[2] <= _T_399 @[el2_lib.scala 328:30] - node _T_400 = bits(dccm_rdata_lo_any, 7, 7) @[el2_lib.scala 327:36] - _T_380[3] <= _T_400 @[el2_lib.scala 327:30] - node _T_401 = bits(dccm_rdata_lo_any, 7, 7) @[el2_lib.scala 328:36] - _T_381[3] <= _T_401 @[el2_lib.scala 328:30] - node _T_402 = bits(dccm_rdata_lo_any, 8, 8) @[el2_lib.scala 325:36] - _T_378[5] <= _T_402 @[el2_lib.scala 325:30] - node _T_403 = bits(dccm_rdata_lo_any, 8, 8) @[el2_lib.scala 327:36] - _T_380[4] <= _T_403 @[el2_lib.scala 327:30] - node _T_404 = bits(dccm_rdata_lo_any, 8, 8) @[el2_lib.scala 328:36] - _T_381[4] <= _T_404 @[el2_lib.scala 328:30] - node _T_405 = bits(dccm_rdata_lo_any, 9, 9) @[el2_lib.scala 326:36] - _T_379[5] <= _T_405 @[el2_lib.scala 326:30] - node _T_406 = bits(dccm_rdata_lo_any, 9, 9) @[el2_lib.scala 327:36] - _T_380[5] <= _T_406 @[el2_lib.scala 327:30] - node _T_407 = bits(dccm_rdata_lo_any, 9, 9) @[el2_lib.scala 328:36] - _T_381[5] <= _T_407 @[el2_lib.scala 328:30] - node _T_408 = bits(dccm_rdata_lo_any, 10, 10) @[el2_lib.scala 325:36] - _T_378[6] <= _T_408 @[el2_lib.scala 325:30] - node _T_409 = bits(dccm_rdata_lo_any, 10, 10) @[el2_lib.scala 326:36] - _T_379[6] <= _T_409 @[el2_lib.scala 326:30] - node _T_410 = bits(dccm_rdata_lo_any, 10, 10) @[el2_lib.scala 327:36] - _T_380[6] <= _T_410 @[el2_lib.scala 327:30] - node _T_411 = bits(dccm_rdata_lo_any, 10, 10) @[el2_lib.scala 328:36] - _T_381[6] <= _T_411 @[el2_lib.scala 328:30] - node _T_412 = bits(dccm_rdata_lo_any, 11, 11) @[el2_lib.scala 325:36] - _T_378[7] <= _T_412 @[el2_lib.scala 325:30] - node _T_413 = bits(dccm_rdata_lo_any, 11, 11) @[el2_lib.scala 329:36] - _T_382[0] <= _T_413 @[el2_lib.scala 329:30] - node _T_414 = bits(dccm_rdata_lo_any, 12, 12) @[el2_lib.scala 326:36] - _T_379[7] <= _T_414 @[el2_lib.scala 326:30] - node _T_415 = bits(dccm_rdata_lo_any, 12, 12) @[el2_lib.scala 329:36] - _T_382[1] <= _T_415 @[el2_lib.scala 329:30] - node _T_416 = bits(dccm_rdata_lo_any, 13, 13) @[el2_lib.scala 325:36] - _T_378[8] <= _T_416 @[el2_lib.scala 325:30] - node _T_417 = bits(dccm_rdata_lo_any, 13, 13) @[el2_lib.scala 326:36] - _T_379[8] <= _T_417 @[el2_lib.scala 326:30] - node _T_418 = bits(dccm_rdata_lo_any, 13, 13) @[el2_lib.scala 329:36] - _T_382[2] <= _T_418 @[el2_lib.scala 329:30] - node _T_419 = bits(dccm_rdata_lo_any, 14, 14) @[el2_lib.scala 327:36] - _T_380[7] <= _T_419 @[el2_lib.scala 327:30] - node _T_420 = bits(dccm_rdata_lo_any, 14, 14) @[el2_lib.scala 329:36] - _T_382[3] <= _T_420 @[el2_lib.scala 329:30] - node _T_421 = bits(dccm_rdata_lo_any, 15, 15) @[el2_lib.scala 325:36] - _T_378[9] <= _T_421 @[el2_lib.scala 325:30] - node _T_422 = bits(dccm_rdata_lo_any, 15, 15) @[el2_lib.scala 327:36] - _T_380[8] <= _T_422 @[el2_lib.scala 327:30] - node _T_423 = bits(dccm_rdata_lo_any, 15, 15) @[el2_lib.scala 329:36] - _T_382[4] <= _T_423 @[el2_lib.scala 329:30] - node _T_424 = bits(dccm_rdata_lo_any, 16, 16) @[el2_lib.scala 326:36] - _T_379[9] <= _T_424 @[el2_lib.scala 326:30] - node _T_425 = bits(dccm_rdata_lo_any, 16, 16) @[el2_lib.scala 327:36] - _T_380[9] <= _T_425 @[el2_lib.scala 327:30] - node _T_426 = bits(dccm_rdata_lo_any, 16, 16) @[el2_lib.scala 329:36] - _T_382[5] <= _T_426 @[el2_lib.scala 329:30] - node _T_427 = bits(dccm_rdata_lo_any, 17, 17) @[el2_lib.scala 325:36] - _T_378[10] <= _T_427 @[el2_lib.scala 325:30] - node _T_428 = bits(dccm_rdata_lo_any, 17, 17) @[el2_lib.scala 326:36] - _T_379[10] <= _T_428 @[el2_lib.scala 326:30] - node _T_429 = bits(dccm_rdata_lo_any, 17, 17) @[el2_lib.scala 327:36] - _T_380[10] <= _T_429 @[el2_lib.scala 327:30] - node _T_430 = bits(dccm_rdata_lo_any, 17, 17) @[el2_lib.scala 329:36] - _T_382[6] <= _T_430 @[el2_lib.scala 329:30] - node _T_431 = bits(dccm_rdata_lo_any, 18, 18) @[el2_lib.scala 328:36] - _T_381[7] <= _T_431 @[el2_lib.scala 328:30] - node _T_432 = bits(dccm_rdata_lo_any, 18, 18) @[el2_lib.scala 329:36] - _T_382[7] <= _T_432 @[el2_lib.scala 329:30] - node _T_433 = bits(dccm_rdata_lo_any, 19, 19) @[el2_lib.scala 325:36] - _T_378[11] <= _T_433 @[el2_lib.scala 325:30] - node _T_434 = bits(dccm_rdata_lo_any, 19, 19) @[el2_lib.scala 328:36] - _T_381[8] <= _T_434 @[el2_lib.scala 328:30] - node _T_435 = bits(dccm_rdata_lo_any, 19, 19) @[el2_lib.scala 329:36] - _T_382[8] <= _T_435 @[el2_lib.scala 329:30] - node _T_436 = bits(dccm_rdata_lo_any, 20, 20) @[el2_lib.scala 326:36] - _T_379[11] <= _T_436 @[el2_lib.scala 326:30] - node _T_437 = bits(dccm_rdata_lo_any, 20, 20) @[el2_lib.scala 328:36] - _T_381[9] <= _T_437 @[el2_lib.scala 328:30] - node _T_438 = bits(dccm_rdata_lo_any, 20, 20) @[el2_lib.scala 329:36] - _T_382[9] <= _T_438 @[el2_lib.scala 329:30] - node _T_439 = bits(dccm_rdata_lo_any, 21, 21) @[el2_lib.scala 325:36] - _T_378[12] <= _T_439 @[el2_lib.scala 325:30] - node _T_440 = bits(dccm_rdata_lo_any, 21, 21) @[el2_lib.scala 326:36] - _T_379[12] <= _T_440 @[el2_lib.scala 326:30] - node _T_441 = bits(dccm_rdata_lo_any, 21, 21) @[el2_lib.scala 328:36] - _T_381[10] <= _T_441 @[el2_lib.scala 328:30] - node _T_442 = bits(dccm_rdata_lo_any, 21, 21) @[el2_lib.scala 329:36] - _T_382[10] <= _T_442 @[el2_lib.scala 329:30] - node _T_443 = bits(dccm_rdata_lo_any, 22, 22) @[el2_lib.scala 327:36] - _T_380[11] <= _T_443 @[el2_lib.scala 327:30] - node _T_444 = bits(dccm_rdata_lo_any, 22, 22) @[el2_lib.scala 328:36] - _T_381[11] <= _T_444 @[el2_lib.scala 328:30] - node _T_445 = bits(dccm_rdata_lo_any, 22, 22) @[el2_lib.scala 329:36] - _T_382[11] <= _T_445 @[el2_lib.scala 329:30] - node _T_446 = bits(dccm_rdata_lo_any, 23, 23) @[el2_lib.scala 325:36] - _T_378[13] <= _T_446 @[el2_lib.scala 325:30] - node _T_447 = bits(dccm_rdata_lo_any, 23, 23) @[el2_lib.scala 327:36] - _T_380[12] <= _T_447 @[el2_lib.scala 327:30] - node _T_448 = bits(dccm_rdata_lo_any, 23, 23) @[el2_lib.scala 328:36] - _T_381[12] <= _T_448 @[el2_lib.scala 328:30] - node _T_449 = bits(dccm_rdata_lo_any, 23, 23) @[el2_lib.scala 329:36] - _T_382[12] <= _T_449 @[el2_lib.scala 329:30] - node _T_450 = bits(dccm_rdata_lo_any, 24, 24) @[el2_lib.scala 326:36] - _T_379[13] <= _T_450 @[el2_lib.scala 326:30] - node _T_451 = bits(dccm_rdata_lo_any, 24, 24) @[el2_lib.scala 327:36] - _T_380[13] <= _T_451 @[el2_lib.scala 327:30] - node _T_452 = bits(dccm_rdata_lo_any, 24, 24) @[el2_lib.scala 328:36] - _T_381[13] <= _T_452 @[el2_lib.scala 328:30] - node _T_453 = bits(dccm_rdata_lo_any, 24, 24) @[el2_lib.scala 329:36] - _T_382[13] <= _T_453 @[el2_lib.scala 329:30] - node _T_454 = bits(dccm_rdata_lo_any, 25, 25) @[el2_lib.scala 325:36] - _T_378[14] <= _T_454 @[el2_lib.scala 325:30] - node _T_455 = bits(dccm_rdata_lo_any, 25, 25) @[el2_lib.scala 326:36] - _T_379[14] <= _T_455 @[el2_lib.scala 326:30] - node _T_456 = bits(dccm_rdata_lo_any, 25, 25) @[el2_lib.scala 327:36] - _T_380[14] <= _T_456 @[el2_lib.scala 327:30] - node _T_457 = bits(dccm_rdata_lo_any, 25, 25) @[el2_lib.scala 328:36] - _T_381[14] <= _T_457 @[el2_lib.scala 328:30] - node _T_458 = bits(dccm_rdata_lo_any, 25, 25) @[el2_lib.scala 329:36] - _T_382[14] <= _T_458 @[el2_lib.scala 329:30] - node _T_459 = bits(dccm_rdata_lo_any, 26, 26) @[el2_lib.scala 325:36] - _T_378[15] <= _T_459 @[el2_lib.scala 325:30] - node _T_460 = bits(dccm_rdata_lo_any, 26, 26) @[el2_lib.scala 330:36] - _T_383[0] <= _T_460 @[el2_lib.scala 330:30] - node _T_461 = bits(dccm_rdata_lo_any, 27, 27) @[el2_lib.scala 326:36] - _T_379[15] <= _T_461 @[el2_lib.scala 326:30] - node _T_462 = bits(dccm_rdata_lo_any, 27, 27) @[el2_lib.scala 330:36] - _T_383[1] <= _T_462 @[el2_lib.scala 330:30] - node _T_463 = bits(dccm_rdata_lo_any, 28, 28) @[el2_lib.scala 325:36] - _T_378[16] <= _T_463 @[el2_lib.scala 325:30] - node _T_464 = bits(dccm_rdata_lo_any, 28, 28) @[el2_lib.scala 326:36] - _T_379[16] <= _T_464 @[el2_lib.scala 326:30] - node _T_465 = bits(dccm_rdata_lo_any, 28, 28) @[el2_lib.scala 330:36] - _T_383[2] <= _T_465 @[el2_lib.scala 330:30] - node _T_466 = bits(dccm_rdata_lo_any, 29, 29) @[el2_lib.scala 327:36] - _T_380[15] <= _T_466 @[el2_lib.scala 327:30] - node _T_467 = bits(dccm_rdata_lo_any, 29, 29) @[el2_lib.scala 330:36] - _T_383[3] <= _T_467 @[el2_lib.scala 330:30] - node _T_468 = bits(dccm_rdata_lo_any, 30, 30) @[el2_lib.scala 325:36] - _T_378[17] <= _T_468 @[el2_lib.scala 325:30] - node _T_469 = bits(dccm_rdata_lo_any, 30, 30) @[el2_lib.scala 327:36] - _T_380[16] <= _T_469 @[el2_lib.scala 327:30] - node _T_470 = bits(dccm_rdata_lo_any, 30, 30) @[el2_lib.scala 330:36] - _T_383[4] <= _T_470 @[el2_lib.scala 330:30] - node _T_471 = bits(dccm_rdata_lo_any, 31, 31) @[el2_lib.scala 326:36] - _T_379[17] <= _T_471 @[el2_lib.scala 326:30] - node _T_472 = bits(dccm_rdata_lo_any, 31, 31) @[el2_lib.scala 327:36] - _T_380[17] <= _T_472 @[el2_lib.scala 327:30] - node _T_473 = bits(dccm_rdata_lo_any, 31, 31) @[el2_lib.scala 330:36] - _T_383[5] <= _T_473 @[el2_lib.scala 330:30] - node _T_474 = xorr(dccm_rdata_lo_any) @[el2_lib.scala 333:30] - node _T_475 = xorr(dccm_data_ecc_lo_any) @[el2_lib.scala 333:44] - node _T_476 = xor(_T_474, _T_475) @[el2_lib.scala 333:35] - node _T_477 = not(UInt<1>("h00")) @[el2_lib.scala 333:52] - node _T_478 = and(_T_476, _T_477) @[el2_lib.scala 333:50] - node _T_479 = bits(dccm_data_ecc_lo_any, 5, 5) @[el2_lib.scala 333:68] - node _T_480 = cat(_T_383[2], _T_383[1]) @[el2_lib.scala 333:76] - node _T_481 = cat(_T_480, _T_383[0]) @[el2_lib.scala 333:76] - node _T_482 = cat(_T_383[5], _T_383[4]) @[el2_lib.scala 333:76] - node _T_483 = cat(_T_482, _T_383[3]) @[el2_lib.scala 333:76] - node _T_484 = cat(_T_483, _T_481) @[el2_lib.scala 333:76] - node _T_485 = xorr(_T_484) @[el2_lib.scala 333:83] - node _T_486 = xor(_T_479, _T_485) @[el2_lib.scala 333:71] - node _T_487 = bits(dccm_data_ecc_lo_any, 4, 4) @[el2_lib.scala 333:95] - node _T_488 = cat(_T_382[2], _T_382[1]) @[el2_lib.scala 333:103] - node _T_489 = cat(_T_488, _T_382[0]) @[el2_lib.scala 333:103] - node _T_490 = cat(_T_382[4], _T_382[3]) @[el2_lib.scala 333:103] - node _T_491 = cat(_T_382[6], _T_382[5]) @[el2_lib.scala 333:103] - node _T_492 = cat(_T_491, _T_490) @[el2_lib.scala 333:103] - node _T_493 = cat(_T_492, _T_489) @[el2_lib.scala 333:103] - node _T_494 = cat(_T_382[8], _T_382[7]) @[el2_lib.scala 333:103] - node _T_495 = cat(_T_382[10], _T_382[9]) @[el2_lib.scala 333:103] - node _T_496 = cat(_T_495, _T_494) @[el2_lib.scala 333:103] - node _T_497 = cat(_T_382[12], _T_382[11]) @[el2_lib.scala 333:103] - node _T_498 = cat(_T_382[14], _T_382[13]) @[el2_lib.scala 333:103] - node _T_499 = cat(_T_498, _T_497) @[el2_lib.scala 333:103] - node _T_500 = cat(_T_499, _T_496) @[el2_lib.scala 333:103] - node _T_501 = cat(_T_500, _T_493) @[el2_lib.scala 333:103] - node _T_502 = xorr(_T_501) @[el2_lib.scala 333:110] - node _T_503 = xor(_T_487, _T_502) @[el2_lib.scala 333:98] - node _T_504 = bits(dccm_data_ecc_lo_any, 3, 3) @[el2_lib.scala 333:122] - node _T_505 = cat(_T_381[2], _T_381[1]) @[el2_lib.scala 333:130] - node _T_506 = cat(_T_505, _T_381[0]) @[el2_lib.scala 333:130] - node _T_507 = cat(_T_381[4], _T_381[3]) @[el2_lib.scala 333:130] - node _T_508 = cat(_T_381[6], _T_381[5]) @[el2_lib.scala 333:130] - node _T_509 = cat(_T_508, _T_507) @[el2_lib.scala 333:130] - node _T_510 = cat(_T_509, _T_506) @[el2_lib.scala 333:130] - node _T_511 = cat(_T_381[8], _T_381[7]) @[el2_lib.scala 333:130] - node _T_512 = cat(_T_381[10], _T_381[9]) @[el2_lib.scala 333:130] - node _T_513 = cat(_T_512, _T_511) @[el2_lib.scala 333:130] - node _T_514 = cat(_T_381[12], _T_381[11]) @[el2_lib.scala 333:130] - node _T_515 = cat(_T_381[14], _T_381[13]) @[el2_lib.scala 333:130] - node _T_516 = cat(_T_515, _T_514) @[el2_lib.scala 333:130] - node _T_517 = cat(_T_516, _T_513) @[el2_lib.scala 333:130] - node _T_518 = cat(_T_517, _T_510) @[el2_lib.scala 333:130] - node _T_519 = xorr(_T_518) @[el2_lib.scala 333:137] - node _T_520 = xor(_T_504, _T_519) @[el2_lib.scala 333:125] - node _T_521 = bits(dccm_data_ecc_lo_any, 2, 2) @[el2_lib.scala 333:149] - node _T_522 = cat(_T_380[1], _T_380[0]) @[el2_lib.scala 333:157] - node _T_523 = cat(_T_380[3], _T_380[2]) @[el2_lib.scala 333:157] - node _T_524 = cat(_T_523, _T_522) @[el2_lib.scala 333:157] - node _T_525 = cat(_T_380[5], _T_380[4]) @[el2_lib.scala 333:157] - node _T_526 = cat(_T_380[8], _T_380[7]) @[el2_lib.scala 333:157] - node _T_527 = cat(_T_526, _T_380[6]) @[el2_lib.scala 333:157] - node _T_528 = cat(_T_527, _T_525) @[el2_lib.scala 333:157] - node _T_529 = cat(_T_528, _T_524) @[el2_lib.scala 333:157] - node _T_530 = cat(_T_380[10], _T_380[9]) @[el2_lib.scala 333:157] - node _T_531 = cat(_T_380[12], _T_380[11]) @[el2_lib.scala 333:157] - node _T_532 = cat(_T_531, _T_530) @[el2_lib.scala 333:157] - node _T_533 = cat(_T_380[14], _T_380[13]) @[el2_lib.scala 333:157] - node _T_534 = cat(_T_380[17], _T_380[16]) @[el2_lib.scala 333:157] - node _T_535 = cat(_T_534, _T_380[15]) @[el2_lib.scala 333:157] - node _T_536 = cat(_T_535, _T_533) @[el2_lib.scala 333:157] - node _T_537 = cat(_T_536, _T_532) @[el2_lib.scala 333:157] - node _T_538 = cat(_T_537, _T_529) @[el2_lib.scala 333:157] - node _T_539 = xorr(_T_538) @[el2_lib.scala 333:164] - node _T_540 = xor(_T_521, _T_539) @[el2_lib.scala 333:152] - node _T_541 = bits(dccm_data_ecc_lo_any, 1, 1) @[el2_lib.scala 333:176] - node _T_542 = cat(_T_379[1], _T_379[0]) @[el2_lib.scala 333:184] - node _T_543 = cat(_T_379[3], _T_379[2]) @[el2_lib.scala 333:184] - node _T_544 = cat(_T_543, _T_542) @[el2_lib.scala 333:184] - node _T_545 = cat(_T_379[5], _T_379[4]) @[el2_lib.scala 333:184] - node _T_546 = cat(_T_379[8], _T_379[7]) @[el2_lib.scala 333:184] - node _T_547 = cat(_T_546, _T_379[6]) @[el2_lib.scala 333:184] - node _T_548 = cat(_T_547, _T_545) @[el2_lib.scala 333:184] - node _T_549 = cat(_T_548, _T_544) @[el2_lib.scala 333:184] - node _T_550 = cat(_T_379[10], _T_379[9]) @[el2_lib.scala 333:184] - node _T_551 = cat(_T_379[12], _T_379[11]) @[el2_lib.scala 333:184] - node _T_552 = cat(_T_551, _T_550) @[el2_lib.scala 333:184] - node _T_553 = cat(_T_379[14], _T_379[13]) @[el2_lib.scala 333:184] - node _T_554 = cat(_T_379[17], _T_379[16]) @[el2_lib.scala 333:184] - node _T_555 = cat(_T_554, _T_379[15]) @[el2_lib.scala 333:184] - node _T_556 = cat(_T_555, _T_553) @[el2_lib.scala 333:184] - node _T_557 = cat(_T_556, _T_552) @[el2_lib.scala 333:184] - node _T_558 = cat(_T_557, _T_549) @[el2_lib.scala 333:184] - node _T_559 = xorr(_T_558) @[el2_lib.scala 333:191] - node _T_560 = xor(_T_541, _T_559) @[el2_lib.scala 333:179] - node _T_561 = bits(dccm_data_ecc_lo_any, 0, 0) @[el2_lib.scala 333:203] - node _T_562 = cat(_T_378[1], _T_378[0]) @[el2_lib.scala 333:211] - node _T_563 = cat(_T_378[3], _T_378[2]) @[el2_lib.scala 333:211] - node _T_564 = cat(_T_563, _T_562) @[el2_lib.scala 333:211] - node _T_565 = cat(_T_378[5], _T_378[4]) @[el2_lib.scala 333:211] - node _T_566 = cat(_T_378[8], _T_378[7]) @[el2_lib.scala 333:211] - node _T_567 = cat(_T_566, _T_378[6]) @[el2_lib.scala 333:211] - node _T_568 = cat(_T_567, _T_565) @[el2_lib.scala 333:211] - node _T_569 = cat(_T_568, _T_564) @[el2_lib.scala 333:211] - node _T_570 = cat(_T_378[10], _T_378[9]) @[el2_lib.scala 333:211] - node _T_571 = cat(_T_378[12], _T_378[11]) @[el2_lib.scala 333:211] - node _T_572 = cat(_T_571, _T_570) @[el2_lib.scala 333:211] - node _T_573 = cat(_T_378[14], _T_378[13]) @[el2_lib.scala 333:211] - node _T_574 = cat(_T_378[17], _T_378[16]) @[el2_lib.scala 333:211] - node _T_575 = cat(_T_574, _T_378[15]) @[el2_lib.scala 333:211] - node _T_576 = cat(_T_575, _T_573) @[el2_lib.scala 333:211] - node _T_577 = cat(_T_576, _T_572) @[el2_lib.scala 333:211] - node _T_578 = cat(_T_577, _T_569) @[el2_lib.scala 333:211] - node _T_579 = xorr(_T_578) @[el2_lib.scala 333:218] - node _T_580 = xor(_T_561, _T_579) @[el2_lib.scala 333:206] + wire _T_378 : UInt<1>[18] @[lib.scala 173:18] + wire _T_379 : UInt<1>[18] @[lib.scala 174:18] + wire _T_380 : UInt<1>[18] @[lib.scala 175:18] + wire _T_381 : UInt<1>[15] @[lib.scala 176:18] + wire _T_382 : UInt<1>[15] @[lib.scala 177:18] + wire _T_383 : UInt<1>[6] @[lib.scala 178:18] + node _T_384 = bits(dccm_rdata_lo_any, 0, 0) @[lib.scala 185:36] + _T_378[0] <= _T_384 @[lib.scala 185:30] + node _T_385 = bits(dccm_rdata_lo_any, 0, 0) @[lib.scala 186:36] + _T_379[0] <= _T_385 @[lib.scala 186:30] + node _T_386 = bits(dccm_rdata_lo_any, 1, 1) @[lib.scala 185:36] + _T_378[1] <= _T_386 @[lib.scala 185:30] + node _T_387 = bits(dccm_rdata_lo_any, 1, 1) @[lib.scala 187:36] + _T_380[0] <= _T_387 @[lib.scala 187:30] + node _T_388 = bits(dccm_rdata_lo_any, 2, 2) @[lib.scala 186:36] + _T_379[1] <= _T_388 @[lib.scala 186:30] + node _T_389 = bits(dccm_rdata_lo_any, 2, 2) @[lib.scala 187:36] + _T_380[1] <= _T_389 @[lib.scala 187:30] + node _T_390 = bits(dccm_rdata_lo_any, 3, 3) @[lib.scala 185:36] + _T_378[2] <= _T_390 @[lib.scala 185:30] + node _T_391 = bits(dccm_rdata_lo_any, 3, 3) @[lib.scala 186:36] + _T_379[2] <= _T_391 @[lib.scala 186:30] + node _T_392 = bits(dccm_rdata_lo_any, 3, 3) @[lib.scala 187:36] + _T_380[2] <= _T_392 @[lib.scala 187:30] + node _T_393 = bits(dccm_rdata_lo_any, 4, 4) @[lib.scala 185:36] + _T_378[3] <= _T_393 @[lib.scala 185:30] + node _T_394 = bits(dccm_rdata_lo_any, 4, 4) @[lib.scala 188:36] + _T_381[0] <= _T_394 @[lib.scala 188:30] + node _T_395 = bits(dccm_rdata_lo_any, 5, 5) @[lib.scala 186:36] + _T_379[3] <= _T_395 @[lib.scala 186:30] + node _T_396 = bits(dccm_rdata_lo_any, 5, 5) @[lib.scala 188:36] + _T_381[1] <= _T_396 @[lib.scala 188:30] + node _T_397 = bits(dccm_rdata_lo_any, 6, 6) @[lib.scala 185:36] + _T_378[4] <= _T_397 @[lib.scala 185:30] + node _T_398 = bits(dccm_rdata_lo_any, 6, 6) @[lib.scala 186:36] + _T_379[4] <= _T_398 @[lib.scala 186:30] + node _T_399 = bits(dccm_rdata_lo_any, 6, 6) @[lib.scala 188:36] + _T_381[2] <= _T_399 @[lib.scala 188:30] + node _T_400 = bits(dccm_rdata_lo_any, 7, 7) @[lib.scala 187:36] + _T_380[3] <= _T_400 @[lib.scala 187:30] + node _T_401 = bits(dccm_rdata_lo_any, 7, 7) @[lib.scala 188:36] + _T_381[3] <= _T_401 @[lib.scala 188:30] + node _T_402 = bits(dccm_rdata_lo_any, 8, 8) @[lib.scala 185:36] + _T_378[5] <= _T_402 @[lib.scala 185:30] + node _T_403 = bits(dccm_rdata_lo_any, 8, 8) @[lib.scala 187:36] + _T_380[4] <= _T_403 @[lib.scala 187:30] + node _T_404 = bits(dccm_rdata_lo_any, 8, 8) @[lib.scala 188:36] + _T_381[4] <= _T_404 @[lib.scala 188:30] + node _T_405 = bits(dccm_rdata_lo_any, 9, 9) @[lib.scala 186:36] + _T_379[5] <= _T_405 @[lib.scala 186:30] + node _T_406 = bits(dccm_rdata_lo_any, 9, 9) @[lib.scala 187:36] + _T_380[5] <= _T_406 @[lib.scala 187:30] + node _T_407 = bits(dccm_rdata_lo_any, 9, 9) @[lib.scala 188:36] + _T_381[5] <= _T_407 @[lib.scala 188:30] + node _T_408 = bits(dccm_rdata_lo_any, 10, 10) @[lib.scala 185:36] + _T_378[6] <= _T_408 @[lib.scala 185:30] + node _T_409 = bits(dccm_rdata_lo_any, 10, 10) @[lib.scala 186:36] + _T_379[6] <= _T_409 @[lib.scala 186:30] + node _T_410 = bits(dccm_rdata_lo_any, 10, 10) @[lib.scala 187:36] + _T_380[6] <= _T_410 @[lib.scala 187:30] + node _T_411 = bits(dccm_rdata_lo_any, 10, 10) @[lib.scala 188:36] + _T_381[6] <= _T_411 @[lib.scala 188:30] + node _T_412 = bits(dccm_rdata_lo_any, 11, 11) @[lib.scala 185:36] + _T_378[7] <= _T_412 @[lib.scala 185:30] + node _T_413 = bits(dccm_rdata_lo_any, 11, 11) @[lib.scala 189:36] + _T_382[0] <= _T_413 @[lib.scala 189:30] + node _T_414 = bits(dccm_rdata_lo_any, 12, 12) @[lib.scala 186:36] + _T_379[7] <= _T_414 @[lib.scala 186:30] + node _T_415 = bits(dccm_rdata_lo_any, 12, 12) @[lib.scala 189:36] + _T_382[1] <= _T_415 @[lib.scala 189:30] + node _T_416 = bits(dccm_rdata_lo_any, 13, 13) @[lib.scala 185:36] + _T_378[8] <= _T_416 @[lib.scala 185:30] + node _T_417 = bits(dccm_rdata_lo_any, 13, 13) @[lib.scala 186:36] + _T_379[8] <= _T_417 @[lib.scala 186:30] + node _T_418 = bits(dccm_rdata_lo_any, 13, 13) @[lib.scala 189:36] + _T_382[2] <= _T_418 @[lib.scala 189:30] + node _T_419 = bits(dccm_rdata_lo_any, 14, 14) @[lib.scala 187:36] + _T_380[7] <= _T_419 @[lib.scala 187:30] + node _T_420 = bits(dccm_rdata_lo_any, 14, 14) @[lib.scala 189:36] + _T_382[3] <= _T_420 @[lib.scala 189:30] + node _T_421 = bits(dccm_rdata_lo_any, 15, 15) @[lib.scala 185:36] + _T_378[9] <= _T_421 @[lib.scala 185:30] + node _T_422 = bits(dccm_rdata_lo_any, 15, 15) @[lib.scala 187:36] + _T_380[8] <= _T_422 @[lib.scala 187:30] + node _T_423 = bits(dccm_rdata_lo_any, 15, 15) @[lib.scala 189:36] + _T_382[4] <= _T_423 @[lib.scala 189:30] + node _T_424 = bits(dccm_rdata_lo_any, 16, 16) @[lib.scala 186:36] + _T_379[9] <= _T_424 @[lib.scala 186:30] + node _T_425 = bits(dccm_rdata_lo_any, 16, 16) @[lib.scala 187:36] + _T_380[9] <= _T_425 @[lib.scala 187:30] + node _T_426 = bits(dccm_rdata_lo_any, 16, 16) @[lib.scala 189:36] + _T_382[5] <= _T_426 @[lib.scala 189:30] + node _T_427 = bits(dccm_rdata_lo_any, 17, 17) @[lib.scala 185:36] + _T_378[10] <= _T_427 @[lib.scala 185:30] + node _T_428 = bits(dccm_rdata_lo_any, 17, 17) @[lib.scala 186:36] + _T_379[10] <= _T_428 @[lib.scala 186:30] + node _T_429 = bits(dccm_rdata_lo_any, 17, 17) @[lib.scala 187:36] + _T_380[10] <= _T_429 @[lib.scala 187:30] + node _T_430 = bits(dccm_rdata_lo_any, 17, 17) @[lib.scala 189:36] + _T_382[6] <= _T_430 @[lib.scala 189:30] + node _T_431 = bits(dccm_rdata_lo_any, 18, 18) @[lib.scala 188:36] + _T_381[7] <= _T_431 @[lib.scala 188:30] + node _T_432 = bits(dccm_rdata_lo_any, 18, 18) @[lib.scala 189:36] + _T_382[7] <= _T_432 @[lib.scala 189:30] + node _T_433 = bits(dccm_rdata_lo_any, 19, 19) @[lib.scala 185:36] + _T_378[11] <= _T_433 @[lib.scala 185:30] + node _T_434 = bits(dccm_rdata_lo_any, 19, 19) @[lib.scala 188:36] + _T_381[8] <= _T_434 @[lib.scala 188:30] + node _T_435 = bits(dccm_rdata_lo_any, 19, 19) @[lib.scala 189:36] + _T_382[8] <= _T_435 @[lib.scala 189:30] + node _T_436 = bits(dccm_rdata_lo_any, 20, 20) @[lib.scala 186:36] + _T_379[11] <= _T_436 @[lib.scala 186:30] + node _T_437 = bits(dccm_rdata_lo_any, 20, 20) @[lib.scala 188:36] + _T_381[9] <= _T_437 @[lib.scala 188:30] + node _T_438 = bits(dccm_rdata_lo_any, 20, 20) @[lib.scala 189:36] + _T_382[9] <= _T_438 @[lib.scala 189:30] + node _T_439 = bits(dccm_rdata_lo_any, 21, 21) @[lib.scala 185:36] + _T_378[12] <= _T_439 @[lib.scala 185:30] + node _T_440 = bits(dccm_rdata_lo_any, 21, 21) @[lib.scala 186:36] + _T_379[12] <= _T_440 @[lib.scala 186:30] + node _T_441 = bits(dccm_rdata_lo_any, 21, 21) @[lib.scala 188:36] + _T_381[10] <= _T_441 @[lib.scala 188:30] + node _T_442 = bits(dccm_rdata_lo_any, 21, 21) @[lib.scala 189:36] + _T_382[10] <= _T_442 @[lib.scala 189:30] + node _T_443 = bits(dccm_rdata_lo_any, 22, 22) @[lib.scala 187:36] + _T_380[11] <= _T_443 @[lib.scala 187:30] + node _T_444 = bits(dccm_rdata_lo_any, 22, 22) @[lib.scala 188:36] + _T_381[11] <= _T_444 @[lib.scala 188:30] + node _T_445 = bits(dccm_rdata_lo_any, 22, 22) @[lib.scala 189:36] + _T_382[11] <= _T_445 @[lib.scala 189:30] + node _T_446 = bits(dccm_rdata_lo_any, 23, 23) @[lib.scala 185:36] + _T_378[13] <= _T_446 @[lib.scala 185:30] + node _T_447 = bits(dccm_rdata_lo_any, 23, 23) @[lib.scala 187:36] + _T_380[12] <= _T_447 @[lib.scala 187:30] + node _T_448 = bits(dccm_rdata_lo_any, 23, 23) @[lib.scala 188:36] + _T_381[12] <= _T_448 @[lib.scala 188:30] + node _T_449 = bits(dccm_rdata_lo_any, 23, 23) @[lib.scala 189:36] + _T_382[12] <= _T_449 @[lib.scala 189:30] + node _T_450 = bits(dccm_rdata_lo_any, 24, 24) @[lib.scala 186:36] + _T_379[13] <= _T_450 @[lib.scala 186:30] + node _T_451 = bits(dccm_rdata_lo_any, 24, 24) @[lib.scala 187:36] + _T_380[13] <= _T_451 @[lib.scala 187:30] + node _T_452 = bits(dccm_rdata_lo_any, 24, 24) @[lib.scala 188:36] + _T_381[13] <= _T_452 @[lib.scala 188:30] + node _T_453 = bits(dccm_rdata_lo_any, 24, 24) @[lib.scala 189:36] + _T_382[13] <= _T_453 @[lib.scala 189:30] + node _T_454 = bits(dccm_rdata_lo_any, 25, 25) @[lib.scala 185:36] + _T_378[14] <= _T_454 @[lib.scala 185:30] + node _T_455 = bits(dccm_rdata_lo_any, 25, 25) @[lib.scala 186:36] + _T_379[14] <= _T_455 @[lib.scala 186:30] + node _T_456 = bits(dccm_rdata_lo_any, 25, 25) @[lib.scala 187:36] + _T_380[14] <= _T_456 @[lib.scala 187:30] + node _T_457 = bits(dccm_rdata_lo_any, 25, 25) @[lib.scala 188:36] + _T_381[14] <= _T_457 @[lib.scala 188:30] + node _T_458 = bits(dccm_rdata_lo_any, 25, 25) @[lib.scala 189:36] + _T_382[14] <= _T_458 @[lib.scala 189:30] + node _T_459 = bits(dccm_rdata_lo_any, 26, 26) @[lib.scala 185:36] + _T_378[15] <= _T_459 @[lib.scala 185:30] + node _T_460 = bits(dccm_rdata_lo_any, 26, 26) @[lib.scala 190:36] + _T_383[0] <= _T_460 @[lib.scala 190:30] + node _T_461 = bits(dccm_rdata_lo_any, 27, 27) @[lib.scala 186:36] + _T_379[15] <= _T_461 @[lib.scala 186:30] + node _T_462 = bits(dccm_rdata_lo_any, 27, 27) @[lib.scala 190:36] + _T_383[1] <= _T_462 @[lib.scala 190:30] + node _T_463 = bits(dccm_rdata_lo_any, 28, 28) @[lib.scala 185:36] + _T_378[16] <= _T_463 @[lib.scala 185:30] + node _T_464 = bits(dccm_rdata_lo_any, 28, 28) @[lib.scala 186:36] + _T_379[16] <= _T_464 @[lib.scala 186:30] + node _T_465 = bits(dccm_rdata_lo_any, 28, 28) @[lib.scala 190:36] + _T_383[2] <= _T_465 @[lib.scala 190:30] + node _T_466 = bits(dccm_rdata_lo_any, 29, 29) @[lib.scala 187:36] + _T_380[15] <= _T_466 @[lib.scala 187:30] + node _T_467 = bits(dccm_rdata_lo_any, 29, 29) @[lib.scala 190:36] + _T_383[3] <= _T_467 @[lib.scala 190:30] + node _T_468 = bits(dccm_rdata_lo_any, 30, 30) @[lib.scala 185:36] + _T_378[17] <= _T_468 @[lib.scala 185:30] + node _T_469 = bits(dccm_rdata_lo_any, 30, 30) @[lib.scala 187:36] + _T_380[16] <= _T_469 @[lib.scala 187:30] + node _T_470 = bits(dccm_rdata_lo_any, 30, 30) @[lib.scala 190:36] + _T_383[4] <= _T_470 @[lib.scala 190:30] + node _T_471 = bits(dccm_rdata_lo_any, 31, 31) @[lib.scala 186:36] + _T_379[17] <= _T_471 @[lib.scala 186:30] + node _T_472 = bits(dccm_rdata_lo_any, 31, 31) @[lib.scala 187:36] + _T_380[17] <= _T_472 @[lib.scala 187:30] + node _T_473 = bits(dccm_rdata_lo_any, 31, 31) @[lib.scala 190:36] + _T_383[5] <= _T_473 @[lib.scala 190:30] + node _T_474 = xorr(dccm_rdata_lo_any) @[lib.scala 193:30] + node _T_475 = xorr(dccm_data_ecc_lo_any) @[lib.scala 193:44] + node _T_476 = xor(_T_474, _T_475) @[lib.scala 193:35] + node _T_477 = not(UInt<1>("h00")) @[lib.scala 193:52] + node _T_478 = and(_T_476, _T_477) @[lib.scala 193:50] + node _T_479 = bits(dccm_data_ecc_lo_any, 5, 5) @[lib.scala 193:68] + node _T_480 = cat(_T_383[2], _T_383[1]) @[lib.scala 193:76] + node _T_481 = cat(_T_480, _T_383[0]) @[lib.scala 193:76] + node _T_482 = cat(_T_383[5], _T_383[4]) @[lib.scala 193:76] + node _T_483 = cat(_T_482, _T_383[3]) @[lib.scala 193:76] + node _T_484 = cat(_T_483, _T_481) @[lib.scala 193:76] + node _T_485 = xorr(_T_484) @[lib.scala 193:83] + node _T_486 = xor(_T_479, _T_485) @[lib.scala 193:71] + node _T_487 = bits(dccm_data_ecc_lo_any, 4, 4) @[lib.scala 193:95] + node _T_488 = cat(_T_382[2], _T_382[1]) @[lib.scala 193:103] + node _T_489 = cat(_T_488, _T_382[0]) @[lib.scala 193:103] + node _T_490 = cat(_T_382[4], _T_382[3]) @[lib.scala 193:103] + node _T_491 = cat(_T_382[6], _T_382[5]) @[lib.scala 193:103] + node _T_492 = cat(_T_491, _T_490) @[lib.scala 193:103] + node _T_493 = cat(_T_492, _T_489) @[lib.scala 193:103] + node _T_494 = cat(_T_382[8], _T_382[7]) @[lib.scala 193:103] + node _T_495 = cat(_T_382[10], _T_382[9]) @[lib.scala 193:103] + node _T_496 = cat(_T_495, _T_494) @[lib.scala 193:103] + node _T_497 = cat(_T_382[12], _T_382[11]) @[lib.scala 193:103] + node _T_498 = cat(_T_382[14], _T_382[13]) @[lib.scala 193:103] + node _T_499 = cat(_T_498, _T_497) @[lib.scala 193:103] + node _T_500 = cat(_T_499, _T_496) @[lib.scala 193:103] + node _T_501 = cat(_T_500, _T_493) @[lib.scala 193:103] + node _T_502 = xorr(_T_501) @[lib.scala 193:110] + node _T_503 = xor(_T_487, _T_502) @[lib.scala 193:98] + node _T_504 = bits(dccm_data_ecc_lo_any, 3, 3) @[lib.scala 193:122] + node _T_505 = cat(_T_381[2], _T_381[1]) @[lib.scala 193:130] + node _T_506 = cat(_T_505, _T_381[0]) @[lib.scala 193:130] + node _T_507 = cat(_T_381[4], _T_381[3]) @[lib.scala 193:130] + node _T_508 = cat(_T_381[6], _T_381[5]) @[lib.scala 193:130] + node _T_509 = cat(_T_508, _T_507) @[lib.scala 193:130] + node _T_510 = cat(_T_509, _T_506) @[lib.scala 193:130] + node _T_511 = cat(_T_381[8], _T_381[7]) @[lib.scala 193:130] + node _T_512 = cat(_T_381[10], _T_381[9]) @[lib.scala 193:130] + node _T_513 = cat(_T_512, _T_511) @[lib.scala 193:130] + node _T_514 = cat(_T_381[12], _T_381[11]) @[lib.scala 193:130] + node _T_515 = cat(_T_381[14], _T_381[13]) @[lib.scala 193:130] + node _T_516 = cat(_T_515, _T_514) @[lib.scala 193:130] + node _T_517 = cat(_T_516, _T_513) @[lib.scala 193:130] + node _T_518 = cat(_T_517, _T_510) @[lib.scala 193:130] + node _T_519 = xorr(_T_518) @[lib.scala 193:137] + node _T_520 = xor(_T_504, _T_519) @[lib.scala 193:125] + node _T_521 = bits(dccm_data_ecc_lo_any, 2, 2) @[lib.scala 193:149] + node _T_522 = cat(_T_380[1], _T_380[0]) @[lib.scala 193:157] + node _T_523 = cat(_T_380[3], _T_380[2]) @[lib.scala 193:157] + node _T_524 = cat(_T_523, _T_522) @[lib.scala 193:157] + node _T_525 = cat(_T_380[5], _T_380[4]) @[lib.scala 193:157] + node _T_526 = cat(_T_380[8], _T_380[7]) @[lib.scala 193:157] + node _T_527 = cat(_T_526, _T_380[6]) @[lib.scala 193:157] + node _T_528 = cat(_T_527, _T_525) @[lib.scala 193:157] + node _T_529 = cat(_T_528, _T_524) @[lib.scala 193:157] + node _T_530 = cat(_T_380[10], _T_380[9]) @[lib.scala 193:157] + node _T_531 = cat(_T_380[12], _T_380[11]) @[lib.scala 193:157] + node _T_532 = cat(_T_531, _T_530) @[lib.scala 193:157] + node _T_533 = cat(_T_380[14], _T_380[13]) @[lib.scala 193:157] + node _T_534 = cat(_T_380[17], _T_380[16]) @[lib.scala 193:157] + node _T_535 = cat(_T_534, _T_380[15]) @[lib.scala 193:157] + node _T_536 = cat(_T_535, _T_533) @[lib.scala 193:157] + node _T_537 = cat(_T_536, _T_532) @[lib.scala 193:157] + node _T_538 = cat(_T_537, _T_529) @[lib.scala 193:157] + node _T_539 = xorr(_T_538) @[lib.scala 193:164] + node _T_540 = xor(_T_521, _T_539) @[lib.scala 193:152] + node _T_541 = bits(dccm_data_ecc_lo_any, 1, 1) @[lib.scala 193:176] + node _T_542 = cat(_T_379[1], _T_379[0]) @[lib.scala 193:184] + node _T_543 = cat(_T_379[3], _T_379[2]) @[lib.scala 193:184] + node _T_544 = cat(_T_543, _T_542) @[lib.scala 193:184] + node _T_545 = cat(_T_379[5], _T_379[4]) @[lib.scala 193:184] + node _T_546 = cat(_T_379[8], _T_379[7]) @[lib.scala 193:184] + node _T_547 = cat(_T_546, _T_379[6]) @[lib.scala 193:184] + node _T_548 = cat(_T_547, _T_545) @[lib.scala 193:184] + node _T_549 = cat(_T_548, _T_544) @[lib.scala 193:184] + node _T_550 = cat(_T_379[10], _T_379[9]) @[lib.scala 193:184] + node _T_551 = cat(_T_379[12], _T_379[11]) @[lib.scala 193:184] + node _T_552 = cat(_T_551, _T_550) @[lib.scala 193:184] + node _T_553 = cat(_T_379[14], _T_379[13]) @[lib.scala 193:184] + node _T_554 = cat(_T_379[17], _T_379[16]) @[lib.scala 193:184] + node _T_555 = cat(_T_554, _T_379[15]) @[lib.scala 193:184] + node _T_556 = cat(_T_555, _T_553) @[lib.scala 193:184] + node _T_557 = cat(_T_556, _T_552) @[lib.scala 193:184] + node _T_558 = cat(_T_557, _T_549) @[lib.scala 193:184] + node _T_559 = xorr(_T_558) @[lib.scala 193:191] + node _T_560 = xor(_T_541, _T_559) @[lib.scala 193:179] + node _T_561 = bits(dccm_data_ecc_lo_any, 0, 0) @[lib.scala 193:203] + node _T_562 = cat(_T_378[1], _T_378[0]) @[lib.scala 193:211] + node _T_563 = cat(_T_378[3], _T_378[2]) @[lib.scala 193:211] + node _T_564 = cat(_T_563, _T_562) @[lib.scala 193:211] + node _T_565 = cat(_T_378[5], _T_378[4]) @[lib.scala 193:211] + node _T_566 = cat(_T_378[8], _T_378[7]) @[lib.scala 193:211] + node _T_567 = cat(_T_566, _T_378[6]) @[lib.scala 193:211] + node _T_568 = cat(_T_567, _T_565) @[lib.scala 193:211] + node _T_569 = cat(_T_568, _T_564) @[lib.scala 193:211] + node _T_570 = cat(_T_378[10], _T_378[9]) @[lib.scala 193:211] + node _T_571 = cat(_T_378[12], _T_378[11]) @[lib.scala 193:211] + node _T_572 = cat(_T_571, _T_570) @[lib.scala 193:211] + node _T_573 = cat(_T_378[14], _T_378[13]) @[lib.scala 193:211] + node _T_574 = cat(_T_378[17], _T_378[16]) @[lib.scala 193:211] + node _T_575 = cat(_T_574, _T_378[15]) @[lib.scala 193:211] + node _T_576 = cat(_T_575, _T_573) @[lib.scala 193:211] + node _T_577 = cat(_T_576, _T_572) @[lib.scala 193:211] + node _T_578 = cat(_T_577, _T_569) @[lib.scala 193:211] + node _T_579 = xorr(_T_578) @[lib.scala 193:218] + node _T_580 = xor(_T_561, _T_579) @[lib.scala 193:206] node _T_581 = cat(_T_540, _T_560) @[Cat.scala 29:58] node _T_582 = cat(_T_581, _T_580) @[Cat.scala 29:58] node _T_583 = cat(_T_503, _T_520) @[Cat.scala 29:58] node _T_584 = cat(_T_478, _T_486) @[Cat.scala 29:58] node _T_585 = cat(_T_584, _T_583) @[Cat.scala 29:58] node _T_586 = cat(_T_585, _T_582) @[Cat.scala 29:58] - node _T_587 = neq(_T_586, UInt<1>("h00")) @[el2_lib.scala 334:44] - node _T_588 = and(is_ldst_lo_any, _T_587) @[el2_lib.scala 334:32] - node _T_589 = bits(_T_586, 6, 6) @[el2_lib.scala 334:64] - node single_ecc_error_lo_any = and(_T_588, _T_589) @[el2_lib.scala 334:53] - node _T_590 = neq(_T_586, UInt<1>("h00")) @[el2_lib.scala 335:44] - node _T_591 = and(is_ldst_lo_any, _T_590) @[el2_lib.scala 335:32] - node _T_592 = bits(_T_586, 6, 6) @[el2_lib.scala 335:65] - node _T_593 = not(_T_592) @[el2_lib.scala 335:55] - node double_ecc_error_lo_any = and(_T_591, _T_593) @[el2_lib.scala 335:53] - wire _T_594 : UInt<1>[39] @[el2_lib.scala 336:26] - node _T_595 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_596 = eq(_T_595, UInt<1>("h01")) @[el2_lib.scala 339:41] - _T_594[0] <= _T_596 @[el2_lib.scala 339:23] - node _T_597 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_598 = eq(_T_597, UInt<2>("h02")) @[el2_lib.scala 339:41] - _T_594[1] <= _T_598 @[el2_lib.scala 339:23] - node _T_599 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_600 = eq(_T_599, UInt<2>("h03")) @[el2_lib.scala 339:41] - _T_594[2] <= _T_600 @[el2_lib.scala 339:23] - node _T_601 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_602 = eq(_T_601, UInt<3>("h04")) @[el2_lib.scala 339:41] - _T_594[3] <= _T_602 @[el2_lib.scala 339:23] - node _T_603 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_604 = eq(_T_603, UInt<3>("h05")) @[el2_lib.scala 339:41] - _T_594[4] <= _T_604 @[el2_lib.scala 339:23] - node _T_605 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_606 = eq(_T_605, UInt<3>("h06")) @[el2_lib.scala 339:41] - _T_594[5] <= _T_606 @[el2_lib.scala 339:23] - node _T_607 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_608 = eq(_T_607, UInt<3>("h07")) @[el2_lib.scala 339:41] - _T_594[6] <= _T_608 @[el2_lib.scala 339:23] - node _T_609 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_610 = eq(_T_609, UInt<4>("h08")) @[el2_lib.scala 339:41] - _T_594[7] <= _T_610 @[el2_lib.scala 339:23] - node _T_611 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_612 = eq(_T_611, UInt<4>("h09")) @[el2_lib.scala 339:41] - _T_594[8] <= _T_612 @[el2_lib.scala 339:23] - node _T_613 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_614 = eq(_T_613, UInt<4>("h0a")) @[el2_lib.scala 339:41] - _T_594[9] <= _T_614 @[el2_lib.scala 339:23] - node _T_615 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_616 = eq(_T_615, UInt<4>("h0b")) @[el2_lib.scala 339:41] - _T_594[10] <= _T_616 @[el2_lib.scala 339:23] - node _T_617 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_618 = eq(_T_617, UInt<4>("h0c")) @[el2_lib.scala 339:41] - _T_594[11] <= _T_618 @[el2_lib.scala 339:23] - node _T_619 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_620 = eq(_T_619, UInt<4>("h0d")) @[el2_lib.scala 339:41] - _T_594[12] <= _T_620 @[el2_lib.scala 339:23] - node _T_621 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_622 = eq(_T_621, UInt<4>("h0e")) @[el2_lib.scala 339:41] - _T_594[13] <= _T_622 @[el2_lib.scala 339:23] - node _T_623 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_624 = eq(_T_623, UInt<4>("h0f")) @[el2_lib.scala 339:41] - _T_594[14] <= _T_624 @[el2_lib.scala 339:23] - node _T_625 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_626 = eq(_T_625, UInt<5>("h010")) @[el2_lib.scala 339:41] - _T_594[15] <= _T_626 @[el2_lib.scala 339:23] - node _T_627 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_628 = eq(_T_627, UInt<5>("h011")) @[el2_lib.scala 339:41] - _T_594[16] <= _T_628 @[el2_lib.scala 339:23] - node _T_629 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_630 = eq(_T_629, UInt<5>("h012")) @[el2_lib.scala 339:41] - _T_594[17] <= _T_630 @[el2_lib.scala 339:23] - node _T_631 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_632 = eq(_T_631, UInt<5>("h013")) @[el2_lib.scala 339:41] - _T_594[18] <= _T_632 @[el2_lib.scala 339:23] - node _T_633 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_634 = eq(_T_633, UInt<5>("h014")) @[el2_lib.scala 339:41] - _T_594[19] <= _T_634 @[el2_lib.scala 339:23] - node _T_635 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_636 = eq(_T_635, UInt<5>("h015")) @[el2_lib.scala 339:41] - _T_594[20] <= _T_636 @[el2_lib.scala 339:23] - node _T_637 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_638 = eq(_T_637, UInt<5>("h016")) @[el2_lib.scala 339:41] - _T_594[21] <= _T_638 @[el2_lib.scala 339:23] - node _T_639 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_640 = eq(_T_639, UInt<5>("h017")) @[el2_lib.scala 339:41] - _T_594[22] <= _T_640 @[el2_lib.scala 339:23] - node _T_641 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_642 = eq(_T_641, UInt<5>("h018")) @[el2_lib.scala 339:41] - _T_594[23] <= _T_642 @[el2_lib.scala 339:23] - node _T_643 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_644 = eq(_T_643, UInt<5>("h019")) @[el2_lib.scala 339:41] - _T_594[24] <= _T_644 @[el2_lib.scala 339:23] - node _T_645 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_646 = eq(_T_645, UInt<5>("h01a")) @[el2_lib.scala 339:41] - _T_594[25] <= _T_646 @[el2_lib.scala 339:23] - node _T_647 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_648 = eq(_T_647, UInt<5>("h01b")) @[el2_lib.scala 339:41] - _T_594[26] <= _T_648 @[el2_lib.scala 339:23] - node _T_649 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_650 = eq(_T_649, UInt<5>("h01c")) @[el2_lib.scala 339:41] - _T_594[27] <= _T_650 @[el2_lib.scala 339:23] - node _T_651 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_652 = eq(_T_651, UInt<5>("h01d")) @[el2_lib.scala 339:41] - _T_594[28] <= _T_652 @[el2_lib.scala 339:23] - node _T_653 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_654 = eq(_T_653, UInt<5>("h01e")) @[el2_lib.scala 339:41] - _T_594[29] <= _T_654 @[el2_lib.scala 339:23] - node _T_655 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_656 = eq(_T_655, UInt<5>("h01f")) @[el2_lib.scala 339:41] - _T_594[30] <= _T_656 @[el2_lib.scala 339:23] - node _T_657 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_658 = eq(_T_657, UInt<6>("h020")) @[el2_lib.scala 339:41] - _T_594[31] <= _T_658 @[el2_lib.scala 339:23] - node _T_659 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_660 = eq(_T_659, UInt<6>("h021")) @[el2_lib.scala 339:41] - _T_594[32] <= _T_660 @[el2_lib.scala 339:23] - node _T_661 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_662 = eq(_T_661, UInt<6>("h022")) @[el2_lib.scala 339:41] - _T_594[33] <= _T_662 @[el2_lib.scala 339:23] - node _T_663 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_664 = eq(_T_663, UInt<6>("h023")) @[el2_lib.scala 339:41] - _T_594[34] <= _T_664 @[el2_lib.scala 339:23] - node _T_665 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_666 = eq(_T_665, UInt<6>("h024")) @[el2_lib.scala 339:41] - _T_594[35] <= _T_666 @[el2_lib.scala 339:23] - node _T_667 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_668 = eq(_T_667, UInt<6>("h025")) @[el2_lib.scala 339:41] - _T_594[36] <= _T_668 @[el2_lib.scala 339:23] - node _T_669 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_670 = eq(_T_669, UInt<6>("h026")) @[el2_lib.scala 339:41] - _T_594[37] <= _T_670 @[el2_lib.scala 339:23] - node _T_671 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] - node _T_672 = eq(_T_671, UInt<6>("h027")) @[el2_lib.scala 339:41] - _T_594[38] <= _T_672 @[el2_lib.scala 339:23] - node _T_673 = bits(dccm_data_ecc_lo_any, 6, 6) @[el2_lib.scala 341:37] - node _T_674 = bits(dccm_rdata_lo_any, 31, 26) @[el2_lib.scala 341:45] - node _T_675 = bits(dccm_data_ecc_lo_any, 5, 5) @[el2_lib.scala 341:60] - node _T_676 = bits(dccm_rdata_lo_any, 25, 11) @[el2_lib.scala 341:68] - node _T_677 = bits(dccm_data_ecc_lo_any, 4, 4) @[el2_lib.scala 341:83] - node _T_678 = bits(dccm_rdata_lo_any, 10, 4) @[el2_lib.scala 341:91] - node _T_679 = bits(dccm_data_ecc_lo_any, 3, 3) @[el2_lib.scala 341:105] - node _T_680 = bits(dccm_rdata_lo_any, 3, 1) @[el2_lib.scala 341:113] - node _T_681 = bits(dccm_data_ecc_lo_any, 2, 2) @[el2_lib.scala 341:126] - node _T_682 = bits(dccm_rdata_lo_any, 0, 0) @[el2_lib.scala 341:134] - node _T_683 = bits(dccm_data_ecc_lo_any, 1, 0) @[el2_lib.scala 341:145] + node _T_587 = neq(_T_586, UInt<1>("h00")) @[lib.scala 194:44] + node _T_588 = and(is_ldst_lo_any, _T_587) @[lib.scala 194:32] + node _T_589 = bits(_T_586, 6, 6) @[lib.scala 194:64] + node single_ecc_error_lo_any = and(_T_588, _T_589) @[lib.scala 194:53] + node _T_590 = neq(_T_586, UInt<1>("h00")) @[lib.scala 195:44] + node _T_591 = and(is_ldst_lo_any, _T_590) @[lib.scala 195:32] + node _T_592 = bits(_T_586, 6, 6) @[lib.scala 195:65] + node _T_593 = not(_T_592) @[lib.scala 195:55] + node double_ecc_error_lo_any = and(_T_591, _T_593) @[lib.scala 195:53] + wire _T_594 : UInt<1>[39] @[lib.scala 196:26] + node _T_595 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_596 = eq(_T_595, UInt<1>("h01")) @[lib.scala 199:41] + _T_594[0] <= _T_596 @[lib.scala 199:23] + node _T_597 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_598 = eq(_T_597, UInt<2>("h02")) @[lib.scala 199:41] + _T_594[1] <= _T_598 @[lib.scala 199:23] + node _T_599 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_600 = eq(_T_599, UInt<2>("h03")) @[lib.scala 199:41] + _T_594[2] <= _T_600 @[lib.scala 199:23] + node _T_601 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_602 = eq(_T_601, UInt<3>("h04")) @[lib.scala 199:41] + _T_594[3] <= _T_602 @[lib.scala 199:23] + node _T_603 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_604 = eq(_T_603, UInt<3>("h05")) @[lib.scala 199:41] + _T_594[4] <= _T_604 @[lib.scala 199:23] + node _T_605 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_606 = eq(_T_605, UInt<3>("h06")) @[lib.scala 199:41] + _T_594[5] <= _T_606 @[lib.scala 199:23] + node _T_607 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_608 = eq(_T_607, UInt<3>("h07")) @[lib.scala 199:41] + _T_594[6] <= _T_608 @[lib.scala 199:23] + node _T_609 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_610 = eq(_T_609, UInt<4>("h08")) @[lib.scala 199:41] + _T_594[7] <= _T_610 @[lib.scala 199:23] + node _T_611 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_612 = eq(_T_611, UInt<4>("h09")) @[lib.scala 199:41] + _T_594[8] <= _T_612 @[lib.scala 199:23] + node _T_613 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_614 = eq(_T_613, UInt<4>("h0a")) @[lib.scala 199:41] + _T_594[9] <= _T_614 @[lib.scala 199:23] + node _T_615 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_616 = eq(_T_615, UInt<4>("h0b")) @[lib.scala 199:41] + _T_594[10] <= _T_616 @[lib.scala 199:23] + node _T_617 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_618 = eq(_T_617, UInt<4>("h0c")) @[lib.scala 199:41] + _T_594[11] <= _T_618 @[lib.scala 199:23] + node _T_619 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_620 = eq(_T_619, UInt<4>("h0d")) @[lib.scala 199:41] + _T_594[12] <= _T_620 @[lib.scala 199:23] + node _T_621 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_622 = eq(_T_621, UInt<4>("h0e")) @[lib.scala 199:41] + _T_594[13] <= _T_622 @[lib.scala 199:23] + node _T_623 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_624 = eq(_T_623, UInt<4>("h0f")) @[lib.scala 199:41] + _T_594[14] <= _T_624 @[lib.scala 199:23] + node _T_625 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_626 = eq(_T_625, UInt<5>("h010")) @[lib.scala 199:41] + _T_594[15] <= _T_626 @[lib.scala 199:23] + node _T_627 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_628 = eq(_T_627, UInt<5>("h011")) @[lib.scala 199:41] + _T_594[16] <= _T_628 @[lib.scala 199:23] + node _T_629 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_630 = eq(_T_629, UInt<5>("h012")) @[lib.scala 199:41] + _T_594[17] <= _T_630 @[lib.scala 199:23] + node _T_631 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_632 = eq(_T_631, UInt<5>("h013")) @[lib.scala 199:41] + _T_594[18] <= _T_632 @[lib.scala 199:23] + node _T_633 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_634 = eq(_T_633, UInt<5>("h014")) @[lib.scala 199:41] + _T_594[19] <= _T_634 @[lib.scala 199:23] + node _T_635 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_636 = eq(_T_635, UInt<5>("h015")) @[lib.scala 199:41] + _T_594[20] <= _T_636 @[lib.scala 199:23] + node _T_637 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_638 = eq(_T_637, UInt<5>("h016")) @[lib.scala 199:41] + _T_594[21] <= _T_638 @[lib.scala 199:23] + node _T_639 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_640 = eq(_T_639, UInt<5>("h017")) @[lib.scala 199:41] + _T_594[22] <= _T_640 @[lib.scala 199:23] + node _T_641 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_642 = eq(_T_641, UInt<5>("h018")) @[lib.scala 199:41] + _T_594[23] <= _T_642 @[lib.scala 199:23] + node _T_643 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_644 = eq(_T_643, UInt<5>("h019")) @[lib.scala 199:41] + _T_594[24] <= _T_644 @[lib.scala 199:23] + node _T_645 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_646 = eq(_T_645, UInt<5>("h01a")) @[lib.scala 199:41] + _T_594[25] <= _T_646 @[lib.scala 199:23] + node _T_647 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_648 = eq(_T_647, UInt<5>("h01b")) @[lib.scala 199:41] + _T_594[26] <= _T_648 @[lib.scala 199:23] + node _T_649 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_650 = eq(_T_649, UInt<5>("h01c")) @[lib.scala 199:41] + _T_594[27] <= _T_650 @[lib.scala 199:23] + node _T_651 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_652 = eq(_T_651, UInt<5>("h01d")) @[lib.scala 199:41] + _T_594[28] <= _T_652 @[lib.scala 199:23] + node _T_653 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_654 = eq(_T_653, UInt<5>("h01e")) @[lib.scala 199:41] + _T_594[29] <= _T_654 @[lib.scala 199:23] + node _T_655 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_656 = eq(_T_655, UInt<5>("h01f")) @[lib.scala 199:41] + _T_594[30] <= _T_656 @[lib.scala 199:23] + node _T_657 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_658 = eq(_T_657, UInt<6>("h020")) @[lib.scala 199:41] + _T_594[31] <= _T_658 @[lib.scala 199:23] + node _T_659 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_660 = eq(_T_659, UInt<6>("h021")) @[lib.scala 199:41] + _T_594[32] <= _T_660 @[lib.scala 199:23] + node _T_661 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_662 = eq(_T_661, UInt<6>("h022")) @[lib.scala 199:41] + _T_594[33] <= _T_662 @[lib.scala 199:23] + node _T_663 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_664 = eq(_T_663, UInt<6>("h023")) @[lib.scala 199:41] + _T_594[34] <= _T_664 @[lib.scala 199:23] + node _T_665 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_666 = eq(_T_665, UInt<6>("h024")) @[lib.scala 199:41] + _T_594[35] <= _T_666 @[lib.scala 199:23] + node _T_667 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_668 = eq(_T_667, UInt<6>("h025")) @[lib.scala 199:41] + _T_594[36] <= _T_668 @[lib.scala 199:23] + node _T_669 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_670 = eq(_T_669, UInt<6>("h026")) @[lib.scala 199:41] + _T_594[37] <= _T_670 @[lib.scala 199:23] + node _T_671 = bits(_T_586, 5, 0) @[lib.scala 199:35] + node _T_672 = eq(_T_671, UInt<6>("h027")) @[lib.scala 199:41] + _T_594[38] <= _T_672 @[lib.scala 199:23] + node _T_673 = bits(dccm_data_ecc_lo_any, 6, 6) @[lib.scala 201:37] + node _T_674 = bits(dccm_rdata_lo_any, 31, 26) @[lib.scala 201:45] + node _T_675 = bits(dccm_data_ecc_lo_any, 5, 5) @[lib.scala 201:60] + node _T_676 = bits(dccm_rdata_lo_any, 25, 11) @[lib.scala 201:68] + node _T_677 = bits(dccm_data_ecc_lo_any, 4, 4) @[lib.scala 201:83] + node _T_678 = bits(dccm_rdata_lo_any, 10, 4) @[lib.scala 201:91] + node _T_679 = bits(dccm_data_ecc_lo_any, 3, 3) @[lib.scala 201:105] + node _T_680 = bits(dccm_rdata_lo_any, 3, 1) @[lib.scala 201:113] + node _T_681 = bits(dccm_data_ecc_lo_any, 2, 2) @[lib.scala 201:126] + node _T_682 = bits(dccm_rdata_lo_any, 0, 0) @[lib.scala 201:134] + node _T_683 = bits(dccm_data_ecc_lo_any, 1, 0) @[lib.scala 201:145] node _T_684 = cat(_T_682, _T_683) @[Cat.scala 29:58] node _T_685 = cat(_T_679, _T_680) @[Cat.scala 29:58] node _T_686 = cat(_T_685, _T_681) @[Cat.scala 29:58] @@ -92410,435 +92402,435 @@ circuit quasar_wrapper : node _T_691 = cat(_T_690, _T_675) @[Cat.scala 29:58] node _T_692 = cat(_T_691, _T_689) @[Cat.scala 29:58] node _T_693 = cat(_T_692, _T_687) @[Cat.scala 29:58] - node _T_694 = bits(single_ecc_error_lo_any, 0, 0) @[el2_lib.scala 342:49] - node _T_695 = cat(_T_594[1], _T_594[0]) @[el2_lib.scala 342:69] - node _T_696 = cat(_T_594[3], _T_594[2]) @[el2_lib.scala 342:69] - node _T_697 = cat(_T_696, _T_695) @[el2_lib.scala 342:69] - node _T_698 = cat(_T_594[5], _T_594[4]) @[el2_lib.scala 342:69] - node _T_699 = cat(_T_594[8], _T_594[7]) @[el2_lib.scala 342:69] - node _T_700 = cat(_T_699, _T_594[6]) @[el2_lib.scala 342:69] - node _T_701 = cat(_T_700, _T_698) @[el2_lib.scala 342:69] - node _T_702 = cat(_T_701, _T_697) @[el2_lib.scala 342:69] - node _T_703 = cat(_T_594[10], _T_594[9]) @[el2_lib.scala 342:69] - node _T_704 = cat(_T_594[13], _T_594[12]) @[el2_lib.scala 342:69] - node _T_705 = cat(_T_704, _T_594[11]) @[el2_lib.scala 342:69] - node _T_706 = cat(_T_705, _T_703) @[el2_lib.scala 342:69] - node _T_707 = cat(_T_594[15], _T_594[14]) @[el2_lib.scala 342:69] - node _T_708 = cat(_T_594[18], _T_594[17]) @[el2_lib.scala 342:69] - node _T_709 = cat(_T_708, _T_594[16]) @[el2_lib.scala 342:69] - node _T_710 = cat(_T_709, _T_707) @[el2_lib.scala 342:69] - node _T_711 = cat(_T_710, _T_706) @[el2_lib.scala 342:69] - node _T_712 = cat(_T_711, _T_702) @[el2_lib.scala 342:69] - node _T_713 = cat(_T_594[20], _T_594[19]) @[el2_lib.scala 342:69] - node _T_714 = cat(_T_594[23], _T_594[22]) @[el2_lib.scala 342:69] - node _T_715 = cat(_T_714, _T_594[21]) @[el2_lib.scala 342:69] - node _T_716 = cat(_T_715, _T_713) @[el2_lib.scala 342:69] - node _T_717 = cat(_T_594[25], _T_594[24]) @[el2_lib.scala 342:69] - node _T_718 = cat(_T_594[28], _T_594[27]) @[el2_lib.scala 342:69] - node _T_719 = cat(_T_718, _T_594[26]) @[el2_lib.scala 342:69] - node _T_720 = cat(_T_719, _T_717) @[el2_lib.scala 342:69] - node _T_721 = cat(_T_720, _T_716) @[el2_lib.scala 342:69] - node _T_722 = cat(_T_594[30], _T_594[29]) @[el2_lib.scala 342:69] - node _T_723 = cat(_T_594[33], _T_594[32]) @[el2_lib.scala 342:69] - node _T_724 = cat(_T_723, _T_594[31]) @[el2_lib.scala 342:69] - node _T_725 = cat(_T_724, _T_722) @[el2_lib.scala 342:69] - node _T_726 = cat(_T_594[35], _T_594[34]) @[el2_lib.scala 342:69] - node _T_727 = cat(_T_594[38], _T_594[37]) @[el2_lib.scala 342:69] - node _T_728 = cat(_T_727, _T_594[36]) @[el2_lib.scala 342:69] - node _T_729 = cat(_T_728, _T_726) @[el2_lib.scala 342:69] - node _T_730 = cat(_T_729, _T_725) @[el2_lib.scala 342:69] - node _T_731 = cat(_T_730, _T_721) @[el2_lib.scala 342:69] - node _T_732 = cat(_T_731, _T_712) @[el2_lib.scala 342:69] - node _T_733 = xor(_T_732, _T_693) @[el2_lib.scala 342:76] - node _T_734 = mux(_T_694, _T_733, _T_693) @[el2_lib.scala 342:31] - node _T_735 = bits(_T_734, 37, 32) @[el2_lib.scala 344:37] - node _T_736 = bits(_T_734, 30, 16) @[el2_lib.scala 344:61] - node _T_737 = bits(_T_734, 14, 8) @[el2_lib.scala 344:86] - node _T_738 = bits(_T_734, 6, 4) @[el2_lib.scala 344:110] - node _T_739 = bits(_T_734, 2, 2) @[el2_lib.scala 344:133] + node _T_694 = bits(single_ecc_error_lo_any, 0, 0) @[lib.scala 202:49] + node _T_695 = cat(_T_594[1], _T_594[0]) @[lib.scala 202:69] + node _T_696 = cat(_T_594[3], _T_594[2]) @[lib.scala 202:69] + node _T_697 = cat(_T_696, _T_695) @[lib.scala 202:69] + node _T_698 = cat(_T_594[5], _T_594[4]) @[lib.scala 202:69] + node _T_699 = cat(_T_594[8], _T_594[7]) @[lib.scala 202:69] + node _T_700 = cat(_T_699, _T_594[6]) @[lib.scala 202:69] + node _T_701 = cat(_T_700, _T_698) @[lib.scala 202:69] + node _T_702 = cat(_T_701, _T_697) @[lib.scala 202:69] + node _T_703 = cat(_T_594[10], _T_594[9]) @[lib.scala 202:69] + node _T_704 = cat(_T_594[13], _T_594[12]) @[lib.scala 202:69] + node _T_705 = cat(_T_704, _T_594[11]) @[lib.scala 202:69] + node _T_706 = cat(_T_705, _T_703) @[lib.scala 202:69] + node _T_707 = cat(_T_594[15], _T_594[14]) @[lib.scala 202:69] + node _T_708 = cat(_T_594[18], _T_594[17]) @[lib.scala 202:69] + node _T_709 = cat(_T_708, _T_594[16]) @[lib.scala 202:69] + node _T_710 = cat(_T_709, _T_707) @[lib.scala 202:69] + node _T_711 = cat(_T_710, _T_706) @[lib.scala 202:69] + node _T_712 = cat(_T_711, _T_702) @[lib.scala 202:69] + node _T_713 = cat(_T_594[20], _T_594[19]) @[lib.scala 202:69] + node _T_714 = cat(_T_594[23], _T_594[22]) @[lib.scala 202:69] + node _T_715 = cat(_T_714, _T_594[21]) @[lib.scala 202:69] + node _T_716 = cat(_T_715, _T_713) @[lib.scala 202:69] + node _T_717 = cat(_T_594[25], _T_594[24]) @[lib.scala 202:69] + node _T_718 = cat(_T_594[28], _T_594[27]) @[lib.scala 202:69] + node _T_719 = cat(_T_718, _T_594[26]) @[lib.scala 202:69] + node _T_720 = cat(_T_719, _T_717) @[lib.scala 202:69] + node _T_721 = cat(_T_720, _T_716) @[lib.scala 202:69] + node _T_722 = cat(_T_594[30], _T_594[29]) @[lib.scala 202:69] + node _T_723 = cat(_T_594[33], _T_594[32]) @[lib.scala 202:69] + node _T_724 = cat(_T_723, _T_594[31]) @[lib.scala 202:69] + node _T_725 = cat(_T_724, _T_722) @[lib.scala 202:69] + node _T_726 = cat(_T_594[35], _T_594[34]) @[lib.scala 202:69] + node _T_727 = cat(_T_594[38], _T_594[37]) @[lib.scala 202:69] + node _T_728 = cat(_T_727, _T_594[36]) @[lib.scala 202:69] + node _T_729 = cat(_T_728, _T_726) @[lib.scala 202:69] + node _T_730 = cat(_T_729, _T_725) @[lib.scala 202:69] + node _T_731 = cat(_T_730, _T_721) @[lib.scala 202:69] + node _T_732 = cat(_T_731, _T_712) @[lib.scala 202:69] + node _T_733 = xor(_T_732, _T_693) @[lib.scala 202:76] + node _T_734 = mux(_T_694, _T_733, _T_693) @[lib.scala 202:31] + node _T_735 = bits(_T_734, 37, 32) @[lib.scala 204:37] + node _T_736 = bits(_T_734, 30, 16) @[lib.scala 204:61] + node _T_737 = bits(_T_734, 14, 8) @[lib.scala 204:86] + node _T_738 = bits(_T_734, 6, 4) @[lib.scala 204:110] + node _T_739 = bits(_T_734, 2, 2) @[lib.scala 204:133] node _T_740 = cat(_T_738, _T_739) @[Cat.scala 29:58] node _T_741 = cat(_T_735, _T_736) @[Cat.scala 29:58] node _T_742 = cat(_T_741, _T_737) @[Cat.scala 29:58] node sec_data_lo_any = cat(_T_742, _T_740) @[Cat.scala 29:58] - node _T_743 = bits(_T_734, 38, 38) @[el2_lib.scala 345:39] - node _T_744 = bits(_T_586, 6, 0) @[el2_lib.scala 345:56] - node _T_745 = eq(_T_744, UInt<7>("h040")) @[el2_lib.scala 345:62] - node _T_746 = xor(_T_743, _T_745) @[el2_lib.scala 345:44] - node _T_747 = bits(_T_734, 31, 31) @[el2_lib.scala 345:102] - node _T_748 = bits(_T_734, 15, 15) @[el2_lib.scala 345:124] - node _T_749 = bits(_T_734, 7, 7) @[el2_lib.scala 345:146] - node _T_750 = bits(_T_734, 3, 3) @[el2_lib.scala 345:167] - node _T_751 = bits(_T_734, 1, 0) @[el2_lib.scala 345:188] + node _T_743 = bits(_T_734, 38, 38) @[lib.scala 205:39] + node _T_744 = bits(_T_586, 6, 0) @[lib.scala 205:56] + node _T_745 = eq(_T_744, UInt<7>("h040")) @[lib.scala 205:62] + node _T_746 = xor(_T_743, _T_745) @[lib.scala 205:44] + node _T_747 = bits(_T_734, 31, 31) @[lib.scala 205:102] + node _T_748 = bits(_T_734, 15, 15) @[lib.scala 205:124] + node _T_749 = bits(_T_734, 7, 7) @[lib.scala 205:146] + node _T_750 = bits(_T_734, 3, 3) @[lib.scala 205:167] + node _T_751 = bits(_T_734, 1, 0) @[lib.scala 205:188] node _T_752 = cat(_T_749, _T_750) @[Cat.scala 29:58] node _T_753 = cat(_T_752, _T_751) @[Cat.scala 29:58] node _T_754 = cat(_T_746, _T_747) @[Cat.scala 29:58] node _T_755 = cat(_T_754, _T_748) @[Cat.scala 29:58] node ecc_out_lo_nc = cat(_T_755, _T_753) @[Cat.scala 29:58] - node _T_756 = bits(dccm_wdata_lo_any, 0, 0) @[el2_lib.scala 259:58] - node _T_757 = bits(dccm_wdata_lo_any, 1, 1) @[el2_lib.scala 259:58] - node _T_758 = bits(dccm_wdata_lo_any, 3, 3) @[el2_lib.scala 259:58] - node _T_759 = bits(dccm_wdata_lo_any, 4, 4) @[el2_lib.scala 259:58] - node _T_760 = bits(dccm_wdata_lo_any, 6, 6) @[el2_lib.scala 259:58] - node _T_761 = bits(dccm_wdata_lo_any, 8, 8) @[el2_lib.scala 259:58] - node _T_762 = bits(dccm_wdata_lo_any, 10, 10) @[el2_lib.scala 259:58] - node _T_763 = bits(dccm_wdata_lo_any, 11, 11) @[el2_lib.scala 259:58] - node _T_764 = bits(dccm_wdata_lo_any, 13, 13) @[el2_lib.scala 259:58] - node _T_765 = bits(dccm_wdata_lo_any, 15, 15) @[el2_lib.scala 259:58] - node _T_766 = bits(dccm_wdata_lo_any, 17, 17) @[el2_lib.scala 259:58] - node _T_767 = bits(dccm_wdata_lo_any, 19, 19) @[el2_lib.scala 259:58] - node _T_768 = bits(dccm_wdata_lo_any, 21, 21) @[el2_lib.scala 259:58] - node _T_769 = bits(dccm_wdata_lo_any, 23, 23) @[el2_lib.scala 259:58] - node _T_770 = bits(dccm_wdata_lo_any, 25, 25) @[el2_lib.scala 259:58] - node _T_771 = bits(dccm_wdata_lo_any, 26, 26) @[el2_lib.scala 259:58] - node _T_772 = bits(dccm_wdata_lo_any, 28, 28) @[el2_lib.scala 259:58] - node _T_773 = bits(dccm_wdata_lo_any, 30, 30) @[el2_lib.scala 259:58] - node _T_774 = xor(_T_756, _T_757) @[el2_lib.scala 259:74] - node _T_775 = xor(_T_774, _T_758) @[el2_lib.scala 259:74] - node _T_776 = xor(_T_775, _T_759) @[el2_lib.scala 259:74] - node _T_777 = xor(_T_776, _T_760) @[el2_lib.scala 259:74] - node _T_778 = xor(_T_777, _T_761) @[el2_lib.scala 259:74] - node _T_779 = xor(_T_778, _T_762) @[el2_lib.scala 259:74] - node _T_780 = xor(_T_779, _T_763) @[el2_lib.scala 259:74] - node _T_781 = xor(_T_780, _T_764) @[el2_lib.scala 259:74] - node _T_782 = xor(_T_781, _T_765) @[el2_lib.scala 259:74] - node _T_783 = xor(_T_782, _T_766) @[el2_lib.scala 259:74] - node _T_784 = xor(_T_783, _T_767) @[el2_lib.scala 259:74] - node _T_785 = xor(_T_784, _T_768) @[el2_lib.scala 259:74] - node _T_786 = xor(_T_785, _T_769) @[el2_lib.scala 259:74] - node _T_787 = xor(_T_786, _T_770) @[el2_lib.scala 259:74] - node _T_788 = xor(_T_787, _T_771) @[el2_lib.scala 259:74] - node _T_789 = xor(_T_788, _T_772) @[el2_lib.scala 259:74] - node _T_790 = xor(_T_789, _T_773) @[el2_lib.scala 259:74] - node _T_791 = bits(dccm_wdata_lo_any, 0, 0) @[el2_lib.scala 259:58] - node _T_792 = bits(dccm_wdata_lo_any, 2, 2) @[el2_lib.scala 259:58] - node _T_793 = bits(dccm_wdata_lo_any, 3, 3) @[el2_lib.scala 259:58] - node _T_794 = bits(dccm_wdata_lo_any, 5, 5) @[el2_lib.scala 259:58] - node _T_795 = bits(dccm_wdata_lo_any, 6, 6) @[el2_lib.scala 259:58] - node _T_796 = bits(dccm_wdata_lo_any, 9, 9) @[el2_lib.scala 259:58] - node _T_797 = bits(dccm_wdata_lo_any, 10, 10) @[el2_lib.scala 259:58] - node _T_798 = bits(dccm_wdata_lo_any, 12, 12) @[el2_lib.scala 259:58] - node _T_799 = bits(dccm_wdata_lo_any, 13, 13) @[el2_lib.scala 259:58] - node _T_800 = bits(dccm_wdata_lo_any, 16, 16) @[el2_lib.scala 259:58] - node _T_801 = bits(dccm_wdata_lo_any, 17, 17) @[el2_lib.scala 259:58] - node _T_802 = bits(dccm_wdata_lo_any, 20, 20) @[el2_lib.scala 259:58] - node _T_803 = bits(dccm_wdata_lo_any, 21, 21) @[el2_lib.scala 259:58] - node _T_804 = bits(dccm_wdata_lo_any, 24, 24) @[el2_lib.scala 259:58] - node _T_805 = bits(dccm_wdata_lo_any, 25, 25) @[el2_lib.scala 259:58] - node _T_806 = bits(dccm_wdata_lo_any, 27, 27) @[el2_lib.scala 259:58] - node _T_807 = bits(dccm_wdata_lo_any, 28, 28) @[el2_lib.scala 259:58] - node _T_808 = bits(dccm_wdata_lo_any, 31, 31) @[el2_lib.scala 259:58] - node _T_809 = xor(_T_791, _T_792) @[el2_lib.scala 259:74] - node _T_810 = xor(_T_809, _T_793) @[el2_lib.scala 259:74] - node _T_811 = xor(_T_810, _T_794) @[el2_lib.scala 259:74] - node _T_812 = xor(_T_811, _T_795) @[el2_lib.scala 259:74] - node _T_813 = xor(_T_812, _T_796) @[el2_lib.scala 259:74] - node _T_814 = xor(_T_813, _T_797) @[el2_lib.scala 259:74] - node _T_815 = xor(_T_814, _T_798) @[el2_lib.scala 259:74] - node _T_816 = xor(_T_815, _T_799) @[el2_lib.scala 259:74] - node _T_817 = xor(_T_816, _T_800) @[el2_lib.scala 259:74] - node _T_818 = xor(_T_817, _T_801) @[el2_lib.scala 259:74] - node _T_819 = xor(_T_818, _T_802) @[el2_lib.scala 259:74] - node _T_820 = xor(_T_819, _T_803) @[el2_lib.scala 259:74] - node _T_821 = xor(_T_820, _T_804) @[el2_lib.scala 259:74] - node _T_822 = xor(_T_821, _T_805) @[el2_lib.scala 259:74] - node _T_823 = xor(_T_822, _T_806) @[el2_lib.scala 259:74] - node _T_824 = xor(_T_823, _T_807) @[el2_lib.scala 259:74] - node _T_825 = xor(_T_824, _T_808) @[el2_lib.scala 259:74] - node _T_826 = bits(dccm_wdata_lo_any, 1, 1) @[el2_lib.scala 259:58] - node _T_827 = bits(dccm_wdata_lo_any, 2, 2) @[el2_lib.scala 259:58] - node _T_828 = bits(dccm_wdata_lo_any, 3, 3) @[el2_lib.scala 259:58] - node _T_829 = bits(dccm_wdata_lo_any, 7, 7) @[el2_lib.scala 259:58] - node _T_830 = bits(dccm_wdata_lo_any, 8, 8) @[el2_lib.scala 259:58] - node _T_831 = bits(dccm_wdata_lo_any, 9, 9) @[el2_lib.scala 259:58] - node _T_832 = bits(dccm_wdata_lo_any, 10, 10) @[el2_lib.scala 259:58] - node _T_833 = bits(dccm_wdata_lo_any, 14, 14) @[el2_lib.scala 259:58] - node _T_834 = bits(dccm_wdata_lo_any, 15, 15) @[el2_lib.scala 259:58] - node _T_835 = bits(dccm_wdata_lo_any, 16, 16) @[el2_lib.scala 259:58] - node _T_836 = bits(dccm_wdata_lo_any, 17, 17) @[el2_lib.scala 259:58] - node _T_837 = bits(dccm_wdata_lo_any, 22, 22) @[el2_lib.scala 259:58] - node _T_838 = bits(dccm_wdata_lo_any, 23, 23) @[el2_lib.scala 259:58] - node _T_839 = bits(dccm_wdata_lo_any, 24, 24) @[el2_lib.scala 259:58] - node _T_840 = bits(dccm_wdata_lo_any, 25, 25) @[el2_lib.scala 259:58] - node _T_841 = bits(dccm_wdata_lo_any, 29, 29) @[el2_lib.scala 259:58] - node _T_842 = bits(dccm_wdata_lo_any, 30, 30) @[el2_lib.scala 259:58] - node _T_843 = bits(dccm_wdata_lo_any, 31, 31) @[el2_lib.scala 259:58] - node _T_844 = xor(_T_826, _T_827) @[el2_lib.scala 259:74] - node _T_845 = xor(_T_844, _T_828) @[el2_lib.scala 259:74] - node _T_846 = xor(_T_845, _T_829) @[el2_lib.scala 259:74] - node _T_847 = xor(_T_846, _T_830) @[el2_lib.scala 259:74] - node _T_848 = xor(_T_847, _T_831) @[el2_lib.scala 259:74] - node _T_849 = xor(_T_848, _T_832) @[el2_lib.scala 259:74] - node _T_850 = xor(_T_849, _T_833) @[el2_lib.scala 259:74] - node _T_851 = xor(_T_850, _T_834) @[el2_lib.scala 259:74] - node _T_852 = xor(_T_851, _T_835) @[el2_lib.scala 259:74] - node _T_853 = xor(_T_852, _T_836) @[el2_lib.scala 259:74] - node _T_854 = xor(_T_853, _T_837) @[el2_lib.scala 259:74] - node _T_855 = xor(_T_854, _T_838) @[el2_lib.scala 259:74] - node _T_856 = xor(_T_855, _T_839) @[el2_lib.scala 259:74] - node _T_857 = xor(_T_856, _T_840) @[el2_lib.scala 259:74] - node _T_858 = xor(_T_857, _T_841) @[el2_lib.scala 259:74] - node _T_859 = xor(_T_858, _T_842) @[el2_lib.scala 259:74] - node _T_860 = xor(_T_859, _T_843) @[el2_lib.scala 259:74] - node _T_861 = bits(dccm_wdata_lo_any, 4, 4) @[el2_lib.scala 259:58] - node _T_862 = bits(dccm_wdata_lo_any, 5, 5) @[el2_lib.scala 259:58] - node _T_863 = bits(dccm_wdata_lo_any, 6, 6) @[el2_lib.scala 259:58] - node _T_864 = bits(dccm_wdata_lo_any, 7, 7) @[el2_lib.scala 259:58] - node _T_865 = bits(dccm_wdata_lo_any, 8, 8) @[el2_lib.scala 259:58] - node _T_866 = bits(dccm_wdata_lo_any, 9, 9) @[el2_lib.scala 259:58] - node _T_867 = bits(dccm_wdata_lo_any, 10, 10) @[el2_lib.scala 259:58] - node _T_868 = bits(dccm_wdata_lo_any, 18, 18) @[el2_lib.scala 259:58] - node _T_869 = bits(dccm_wdata_lo_any, 19, 19) @[el2_lib.scala 259:58] - node _T_870 = bits(dccm_wdata_lo_any, 20, 20) @[el2_lib.scala 259:58] - node _T_871 = bits(dccm_wdata_lo_any, 21, 21) @[el2_lib.scala 259:58] - node _T_872 = bits(dccm_wdata_lo_any, 22, 22) @[el2_lib.scala 259:58] - node _T_873 = bits(dccm_wdata_lo_any, 23, 23) @[el2_lib.scala 259:58] - node _T_874 = bits(dccm_wdata_lo_any, 24, 24) @[el2_lib.scala 259:58] - node _T_875 = bits(dccm_wdata_lo_any, 25, 25) @[el2_lib.scala 259:58] - node _T_876 = xor(_T_861, _T_862) @[el2_lib.scala 259:74] - node _T_877 = xor(_T_876, _T_863) @[el2_lib.scala 259:74] - node _T_878 = xor(_T_877, _T_864) @[el2_lib.scala 259:74] - node _T_879 = xor(_T_878, _T_865) @[el2_lib.scala 259:74] - node _T_880 = xor(_T_879, _T_866) @[el2_lib.scala 259:74] - node _T_881 = xor(_T_880, _T_867) @[el2_lib.scala 259:74] - node _T_882 = xor(_T_881, _T_868) @[el2_lib.scala 259:74] - node _T_883 = xor(_T_882, _T_869) @[el2_lib.scala 259:74] - node _T_884 = xor(_T_883, _T_870) @[el2_lib.scala 259:74] - node _T_885 = xor(_T_884, _T_871) @[el2_lib.scala 259:74] - node _T_886 = xor(_T_885, _T_872) @[el2_lib.scala 259:74] - node _T_887 = xor(_T_886, _T_873) @[el2_lib.scala 259:74] - node _T_888 = xor(_T_887, _T_874) @[el2_lib.scala 259:74] - node _T_889 = xor(_T_888, _T_875) @[el2_lib.scala 259:74] - node _T_890 = bits(dccm_wdata_lo_any, 11, 11) @[el2_lib.scala 259:58] - node _T_891 = bits(dccm_wdata_lo_any, 12, 12) @[el2_lib.scala 259:58] - node _T_892 = bits(dccm_wdata_lo_any, 13, 13) @[el2_lib.scala 259:58] - node _T_893 = bits(dccm_wdata_lo_any, 14, 14) @[el2_lib.scala 259:58] - node _T_894 = bits(dccm_wdata_lo_any, 15, 15) @[el2_lib.scala 259:58] - node _T_895 = bits(dccm_wdata_lo_any, 16, 16) @[el2_lib.scala 259:58] - node _T_896 = bits(dccm_wdata_lo_any, 17, 17) @[el2_lib.scala 259:58] - node _T_897 = bits(dccm_wdata_lo_any, 18, 18) @[el2_lib.scala 259:58] - node _T_898 = bits(dccm_wdata_lo_any, 19, 19) @[el2_lib.scala 259:58] - node _T_899 = bits(dccm_wdata_lo_any, 20, 20) @[el2_lib.scala 259:58] - node _T_900 = bits(dccm_wdata_lo_any, 21, 21) @[el2_lib.scala 259:58] - node _T_901 = bits(dccm_wdata_lo_any, 22, 22) @[el2_lib.scala 259:58] - node _T_902 = bits(dccm_wdata_lo_any, 23, 23) @[el2_lib.scala 259:58] - node _T_903 = bits(dccm_wdata_lo_any, 24, 24) @[el2_lib.scala 259:58] - node _T_904 = bits(dccm_wdata_lo_any, 25, 25) @[el2_lib.scala 259:58] - node _T_905 = xor(_T_890, _T_891) @[el2_lib.scala 259:74] - node _T_906 = xor(_T_905, _T_892) @[el2_lib.scala 259:74] - node _T_907 = xor(_T_906, _T_893) @[el2_lib.scala 259:74] - node _T_908 = xor(_T_907, _T_894) @[el2_lib.scala 259:74] - node _T_909 = xor(_T_908, _T_895) @[el2_lib.scala 259:74] - node _T_910 = xor(_T_909, _T_896) @[el2_lib.scala 259:74] - node _T_911 = xor(_T_910, _T_897) @[el2_lib.scala 259:74] - node _T_912 = xor(_T_911, _T_898) @[el2_lib.scala 259:74] - node _T_913 = xor(_T_912, _T_899) @[el2_lib.scala 259:74] - node _T_914 = xor(_T_913, _T_900) @[el2_lib.scala 259:74] - node _T_915 = xor(_T_914, _T_901) @[el2_lib.scala 259:74] - node _T_916 = xor(_T_915, _T_902) @[el2_lib.scala 259:74] - node _T_917 = xor(_T_916, _T_903) @[el2_lib.scala 259:74] - node _T_918 = xor(_T_917, _T_904) @[el2_lib.scala 259:74] - node _T_919 = bits(dccm_wdata_lo_any, 26, 26) @[el2_lib.scala 259:58] - node _T_920 = bits(dccm_wdata_lo_any, 27, 27) @[el2_lib.scala 259:58] - node _T_921 = bits(dccm_wdata_lo_any, 28, 28) @[el2_lib.scala 259:58] - node _T_922 = bits(dccm_wdata_lo_any, 29, 29) @[el2_lib.scala 259:58] - node _T_923 = bits(dccm_wdata_lo_any, 30, 30) @[el2_lib.scala 259:58] - node _T_924 = bits(dccm_wdata_lo_any, 31, 31) @[el2_lib.scala 259:58] - node _T_925 = xor(_T_919, _T_920) @[el2_lib.scala 259:74] - node _T_926 = xor(_T_925, _T_921) @[el2_lib.scala 259:74] - node _T_927 = xor(_T_926, _T_922) @[el2_lib.scala 259:74] - node _T_928 = xor(_T_927, _T_923) @[el2_lib.scala 259:74] - node _T_929 = xor(_T_928, _T_924) @[el2_lib.scala 259:74] + node _T_756 = bits(dccm_wdata_lo_any, 0, 0) @[lib.scala 119:58] + node _T_757 = bits(dccm_wdata_lo_any, 1, 1) @[lib.scala 119:58] + node _T_758 = bits(dccm_wdata_lo_any, 3, 3) @[lib.scala 119:58] + node _T_759 = bits(dccm_wdata_lo_any, 4, 4) @[lib.scala 119:58] + node _T_760 = bits(dccm_wdata_lo_any, 6, 6) @[lib.scala 119:58] + node _T_761 = bits(dccm_wdata_lo_any, 8, 8) @[lib.scala 119:58] + node _T_762 = bits(dccm_wdata_lo_any, 10, 10) @[lib.scala 119:58] + node _T_763 = bits(dccm_wdata_lo_any, 11, 11) @[lib.scala 119:58] + node _T_764 = bits(dccm_wdata_lo_any, 13, 13) @[lib.scala 119:58] + node _T_765 = bits(dccm_wdata_lo_any, 15, 15) @[lib.scala 119:58] + node _T_766 = bits(dccm_wdata_lo_any, 17, 17) @[lib.scala 119:58] + node _T_767 = bits(dccm_wdata_lo_any, 19, 19) @[lib.scala 119:58] + node _T_768 = bits(dccm_wdata_lo_any, 21, 21) @[lib.scala 119:58] + node _T_769 = bits(dccm_wdata_lo_any, 23, 23) @[lib.scala 119:58] + node _T_770 = bits(dccm_wdata_lo_any, 25, 25) @[lib.scala 119:58] + node _T_771 = bits(dccm_wdata_lo_any, 26, 26) @[lib.scala 119:58] + node _T_772 = bits(dccm_wdata_lo_any, 28, 28) @[lib.scala 119:58] + node _T_773 = bits(dccm_wdata_lo_any, 30, 30) @[lib.scala 119:58] + node _T_774 = xor(_T_756, _T_757) @[lib.scala 119:74] + node _T_775 = xor(_T_774, _T_758) @[lib.scala 119:74] + node _T_776 = xor(_T_775, _T_759) @[lib.scala 119:74] + node _T_777 = xor(_T_776, _T_760) @[lib.scala 119:74] + node _T_778 = xor(_T_777, _T_761) @[lib.scala 119:74] + node _T_779 = xor(_T_778, _T_762) @[lib.scala 119:74] + node _T_780 = xor(_T_779, _T_763) @[lib.scala 119:74] + node _T_781 = xor(_T_780, _T_764) @[lib.scala 119:74] + node _T_782 = xor(_T_781, _T_765) @[lib.scala 119:74] + node _T_783 = xor(_T_782, _T_766) @[lib.scala 119:74] + node _T_784 = xor(_T_783, _T_767) @[lib.scala 119:74] + node _T_785 = xor(_T_784, _T_768) @[lib.scala 119:74] + node _T_786 = xor(_T_785, _T_769) @[lib.scala 119:74] + node _T_787 = xor(_T_786, _T_770) @[lib.scala 119:74] + node _T_788 = xor(_T_787, _T_771) @[lib.scala 119:74] + node _T_789 = xor(_T_788, _T_772) @[lib.scala 119:74] + node _T_790 = xor(_T_789, _T_773) @[lib.scala 119:74] + node _T_791 = bits(dccm_wdata_lo_any, 0, 0) @[lib.scala 119:58] + node _T_792 = bits(dccm_wdata_lo_any, 2, 2) @[lib.scala 119:58] + node _T_793 = bits(dccm_wdata_lo_any, 3, 3) @[lib.scala 119:58] + node _T_794 = bits(dccm_wdata_lo_any, 5, 5) @[lib.scala 119:58] + node _T_795 = bits(dccm_wdata_lo_any, 6, 6) @[lib.scala 119:58] + node _T_796 = bits(dccm_wdata_lo_any, 9, 9) @[lib.scala 119:58] + node _T_797 = bits(dccm_wdata_lo_any, 10, 10) @[lib.scala 119:58] + node _T_798 = bits(dccm_wdata_lo_any, 12, 12) @[lib.scala 119:58] + node _T_799 = bits(dccm_wdata_lo_any, 13, 13) @[lib.scala 119:58] + node _T_800 = bits(dccm_wdata_lo_any, 16, 16) @[lib.scala 119:58] + node _T_801 = bits(dccm_wdata_lo_any, 17, 17) @[lib.scala 119:58] + node _T_802 = bits(dccm_wdata_lo_any, 20, 20) @[lib.scala 119:58] + node _T_803 = bits(dccm_wdata_lo_any, 21, 21) @[lib.scala 119:58] + node _T_804 = bits(dccm_wdata_lo_any, 24, 24) @[lib.scala 119:58] + node _T_805 = bits(dccm_wdata_lo_any, 25, 25) @[lib.scala 119:58] + node _T_806 = bits(dccm_wdata_lo_any, 27, 27) @[lib.scala 119:58] + node _T_807 = bits(dccm_wdata_lo_any, 28, 28) @[lib.scala 119:58] + node _T_808 = bits(dccm_wdata_lo_any, 31, 31) @[lib.scala 119:58] + node _T_809 = xor(_T_791, _T_792) @[lib.scala 119:74] + node _T_810 = xor(_T_809, _T_793) @[lib.scala 119:74] + node _T_811 = xor(_T_810, _T_794) @[lib.scala 119:74] + node _T_812 = xor(_T_811, _T_795) @[lib.scala 119:74] + node _T_813 = xor(_T_812, _T_796) @[lib.scala 119:74] + node _T_814 = xor(_T_813, _T_797) @[lib.scala 119:74] + node _T_815 = xor(_T_814, _T_798) @[lib.scala 119:74] + node _T_816 = xor(_T_815, _T_799) @[lib.scala 119:74] + node _T_817 = xor(_T_816, _T_800) @[lib.scala 119:74] + node _T_818 = xor(_T_817, _T_801) @[lib.scala 119:74] + node _T_819 = xor(_T_818, _T_802) @[lib.scala 119:74] + node _T_820 = xor(_T_819, _T_803) @[lib.scala 119:74] + node _T_821 = xor(_T_820, _T_804) @[lib.scala 119:74] + node _T_822 = xor(_T_821, _T_805) @[lib.scala 119:74] + node _T_823 = xor(_T_822, _T_806) @[lib.scala 119:74] + node _T_824 = xor(_T_823, _T_807) @[lib.scala 119:74] + node _T_825 = xor(_T_824, _T_808) @[lib.scala 119:74] + node _T_826 = bits(dccm_wdata_lo_any, 1, 1) @[lib.scala 119:58] + node _T_827 = bits(dccm_wdata_lo_any, 2, 2) @[lib.scala 119:58] + node _T_828 = bits(dccm_wdata_lo_any, 3, 3) @[lib.scala 119:58] + node _T_829 = bits(dccm_wdata_lo_any, 7, 7) @[lib.scala 119:58] + node _T_830 = bits(dccm_wdata_lo_any, 8, 8) @[lib.scala 119:58] + node _T_831 = bits(dccm_wdata_lo_any, 9, 9) @[lib.scala 119:58] + node _T_832 = bits(dccm_wdata_lo_any, 10, 10) @[lib.scala 119:58] + node _T_833 = bits(dccm_wdata_lo_any, 14, 14) @[lib.scala 119:58] + node _T_834 = bits(dccm_wdata_lo_any, 15, 15) @[lib.scala 119:58] + node _T_835 = bits(dccm_wdata_lo_any, 16, 16) @[lib.scala 119:58] + node _T_836 = bits(dccm_wdata_lo_any, 17, 17) @[lib.scala 119:58] + node _T_837 = bits(dccm_wdata_lo_any, 22, 22) @[lib.scala 119:58] + node _T_838 = bits(dccm_wdata_lo_any, 23, 23) @[lib.scala 119:58] + node _T_839 = bits(dccm_wdata_lo_any, 24, 24) @[lib.scala 119:58] + node _T_840 = bits(dccm_wdata_lo_any, 25, 25) @[lib.scala 119:58] + node _T_841 = bits(dccm_wdata_lo_any, 29, 29) @[lib.scala 119:58] + node _T_842 = bits(dccm_wdata_lo_any, 30, 30) @[lib.scala 119:58] + node _T_843 = bits(dccm_wdata_lo_any, 31, 31) @[lib.scala 119:58] + node _T_844 = xor(_T_826, _T_827) @[lib.scala 119:74] + node _T_845 = xor(_T_844, _T_828) @[lib.scala 119:74] + node _T_846 = xor(_T_845, _T_829) @[lib.scala 119:74] + node _T_847 = xor(_T_846, _T_830) @[lib.scala 119:74] + node _T_848 = xor(_T_847, _T_831) @[lib.scala 119:74] + node _T_849 = xor(_T_848, _T_832) @[lib.scala 119:74] + node _T_850 = xor(_T_849, _T_833) @[lib.scala 119:74] + node _T_851 = xor(_T_850, _T_834) @[lib.scala 119:74] + node _T_852 = xor(_T_851, _T_835) @[lib.scala 119:74] + node _T_853 = xor(_T_852, _T_836) @[lib.scala 119:74] + node _T_854 = xor(_T_853, _T_837) @[lib.scala 119:74] + node _T_855 = xor(_T_854, _T_838) @[lib.scala 119:74] + node _T_856 = xor(_T_855, _T_839) @[lib.scala 119:74] + node _T_857 = xor(_T_856, _T_840) @[lib.scala 119:74] + node _T_858 = xor(_T_857, _T_841) @[lib.scala 119:74] + node _T_859 = xor(_T_858, _T_842) @[lib.scala 119:74] + node _T_860 = xor(_T_859, _T_843) @[lib.scala 119:74] + node _T_861 = bits(dccm_wdata_lo_any, 4, 4) @[lib.scala 119:58] + node _T_862 = bits(dccm_wdata_lo_any, 5, 5) @[lib.scala 119:58] + node _T_863 = bits(dccm_wdata_lo_any, 6, 6) @[lib.scala 119:58] + node _T_864 = bits(dccm_wdata_lo_any, 7, 7) @[lib.scala 119:58] + node _T_865 = bits(dccm_wdata_lo_any, 8, 8) @[lib.scala 119:58] + node _T_866 = bits(dccm_wdata_lo_any, 9, 9) @[lib.scala 119:58] + node _T_867 = bits(dccm_wdata_lo_any, 10, 10) @[lib.scala 119:58] + node _T_868 = bits(dccm_wdata_lo_any, 18, 18) @[lib.scala 119:58] + node _T_869 = bits(dccm_wdata_lo_any, 19, 19) @[lib.scala 119:58] + node _T_870 = bits(dccm_wdata_lo_any, 20, 20) @[lib.scala 119:58] + node _T_871 = bits(dccm_wdata_lo_any, 21, 21) @[lib.scala 119:58] + node _T_872 = bits(dccm_wdata_lo_any, 22, 22) @[lib.scala 119:58] + node _T_873 = bits(dccm_wdata_lo_any, 23, 23) @[lib.scala 119:58] + node _T_874 = bits(dccm_wdata_lo_any, 24, 24) @[lib.scala 119:58] + node _T_875 = bits(dccm_wdata_lo_any, 25, 25) @[lib.scala 119:58] + node _T_876 = xor(_T_861, _T_862) @[lib.scala 119:74] + node _T_877 = xor(_T_876, _T_863) @[lib.scala 119:74] + node _T_878 = xor(_T_877, _T_864) @[lib.scala 119:74] + node _T_879 = xor(_T_878, _T_865) @[lib.scala 119:74] + node _T_880 = xor(_T_879, _T_866) @[lib.scala 119:74] + node _T_881 = xor(_T_880, _T_867) @[lib.scala 119:74] + node _T_882 = xor(_T_881, _T_868) @[lib.scala 119:74] + node _T_883 = xor(_T_882, _T_869) @[lib.scala 119:74] + node _T_884 = xor(_T_883, _T_870) @[lib.scala 119:74] + node _T_885 = xor(_T_884, _T_871) @[lib.scala 119:74] + node _T_886 = xor(_T_885, _T_872) @[lib.scala 119:74] + node _T_887 = xor(_T_886, _T_873) @[lib.scala 119:74] + node _T_888 = xor(_T_887, _T_874) @[lib.scala 119:74] + node _T_889 = xor(_T_888, _T_875) @[lib.scala 119:74] + node _T_890 = bits(dccm_wdata_lo_any, 11, 11) @[lib.scala 119:58] + node _T_891 = bits(dccm_wdata_lo_any, 12, 12) @[lib.scala 119:58] + node _T_892 = bits(dccm_wdata_lo_any, 13, 13) @[lib.scala 119:58] + node _T_893 = bits(dccm_wdata_lo_any, 14, 14) @[lib.scala 119:58] + node _T_894 = bits(dccm_wdata_lo_any, 15, 15) @[lib.scala 119:58] + node _T_895 = bits(dccm_wdata_lo_any, 16, 16) @[lib.scala 119:58] + node _T_896 = bits(dccm_wdata_lo_any, 17, 17) @[lib.scala 119:58] + node _T_897 = bits(dccm_wdata_lo_any, 18, 18) @[lib.scala 119:58] + node _T_898 = bits(dccm_wdata_lo_any, 19, 19) @[lib.scala 119:58] + node _T_899 = bits(dccm_wdata_lo_any, 20, 20) @[lib.scala 119:58] + node _T_900 = bits(dccm_wdata_lo_any, 21, 21) @[lib.scala 119:58] + node _T_901 = bits(dccm_wdata_lo_any, 22, 22) @[lib.scala 119:58] + node _T_902 = bits(dccm_wdata_lo_any, 23, 23) @[lib.scala 119:58] + node _T_903 = bits(dccm_wdata_lo_any, 24, 24) @[lib.scala 119:58] + node _T_904 = bits(dccm_wdata_lo_any, 25, 25) @[lib.scala 119:58] + node _T_905 = xor(_T_890, _T_891) @[lib.scala 119:74] + node _T_906 = xor(_T_905, _T_892) @[lib.scala 119:74] + node _T_907 = xor(_T_906, _T_893) @[lib.scala 119:74] + node _T_908 = xor(_T_907, _T_894) @[lib.scala 119:74] + node _T_909 = xor(_T_908, _T_895) @[lib.scala 119:74] + node _T_910 = xor(_T_909, _T_896) @[lib.scala 119:74] + node _T_911 = xor(_T_910, _T_897) @[lib.scala 119:74] + node _T_912 = xor(_T_911, _T_898) @[lib.scala 119:74] + node _T_913 = xor(_T_912, _T_899) @[lib.scala 119:74] + node _T_914 = xor(_T_913, _T_900) @[lib.scala 119:74] + node _T_915 = xor(_T_914, _T_901) @[lib.scala 119:74] + node _T_916 = xor(_T_915, _T_902) @[lib.scala 119:74] + node _T_917 = xor(_T_916, _T_903) @[lib.scala 119:74] + node _T_918 = xor(_T_917, _T_904) @[lib.scala 119:74] + node _T_919 = bits(dccm_wdata_lo_any, 26, 26) @[lib.scala 119:58] + node _T_920 = bits(dccm_wdata_lo_any, 27, 27) @[lib.scala 119:58] + node _T_921 = bits(dccm_wdata_lo_any, 28, 28) @[lib.scala 119:58] + node _T_922 = bits(dccm_wdata_lo_any, 29, 29) @[lib.scala 119:58] + node _T_923 = bits(dccm_wdata_lo_any, 30, 30) @[lib.scala 119:58] + node _T_924 = bits(dccm_wdata_lo_any, 31, 31) @[lib.scala 119:58] + node _T_925 = xor(_T_919, _T_920) @[lib.scala 119:74] + node _T_926 = xor(_T_925, _T_921) @[lib.scala 119:74] + node _T_927 = xor(_T_926, _T_922) @[lib.scala 119:74] + node _T_928 = xor(_T_927, _T_923) @[lib.scala 119:74] + node _T_929 = xor(_T_928, _T_924) @[lib.scala 119:74] node _T_930 = cat(_T_860, _T_825) @[Cat.scala 29:58] node _T_931 = cat(_T_930, _T_790) @[Cat.scala 29:58] node _T_932 = cat(_T_929, _T_918) @[Cat.scala 29:58] node _T_933 = cat(_T_932, _T_889) @[Cat.scala 29:58] node _T_934 = cat(_T_933, _T_931) @[Cat.scala 29:58] - node _T_935 = xorr(dccm_wdata_lo_any) @[el2_lib.scala 267:13] - node _T_936 = xorr(_T_934) @[el2_lib.scala 267:23] - node _T_937 = xor(_T_935, _T_936) @[el2_lib.scala 267:18] + node _T_935 = xorr(dccm_wdata_lo_any) @[lib.scala 127:13] + node _T_936 = xorr(_T_934) @[lib.scala 127:23] + node _T_937 = xor(_T_935, _T_936) @[lib.scala 127:18] node dccm_wdata_ecc_lo_any = cat(_T_937, _T_934) @[Cat.scala 29:58] - node _T_938 = bits(dccm_wdata_hi_any, 0, 0) @[el2_lib.scala 259:58] - node _T_939 = bits(dccm_wdata_hi_any, 1, 1) @[el2_lib.scala 259:58] - node _T_940 = bits(dccm_wdata_hi_any, 3, 3) @[el2_lib.scala 259:58] - node _T_941 = bits(dccm_wdata_hi_any, 4, 4) @[el2_lib.scala 259:58] - node _T_942 = bits(dccm_wdata_hi_any, 6, 6) @[el2_lib.scala 259:58] - node _T_943 = bits(dccm_wdata_hi_any, 8, 8) @[el2_lib.scala 259:58] - node _T_944 = bits(dccm_wdata_hi_any, 10, 10) @[el2_lib.scala 259:58] - node _T_945 = bits(dccm_wdata_hi_any, 11, 11) @[el2_lib.scala 259:58] - node _T_946 = bits(dccm_wdata_hi_any, 13, 13) @[el2_lib.scala 259:58] - node _T_947 = bits(dccm_wdata_hi_any, 15, 15) @[el2_lib.scala 259:58] - node _T_948 = bits(dccm_wdata_hi_any, 17, 17) @[el2_lib.scala 259:58] - node _T_949 = bits(dccm_wdata_hi_any, 19, 19) @[el2_lib.scala 259:58] - node _T_950 = bits(dccm_wdata_hi_any, 21, 21) @[el2_lib.scala 259:58] - node _T_951 = bits(dccm_wdata_hi_any, 23, 23) @[el2_lib.scala 259:58] - node _T_952 = bits(dccm_wdata_hi_any, 25, 25) @[el2_lib.scala 259:58] - node _T_953 = bits(dccm_wdata_hi_any, 26, 26) @[el2_lib.scala 259:58] - node _T_954 = bits(dccm_wdata_hi_any, 28, 28) @[el2_lib.scala 259:58] - node _T_955 = bits(dccm_wdata_hi_any, 30, 30) @[el2_lib.scala 259:58] - node _T_956 = xor(_T_938, _T_939) @[el2_lib.scala 259:74] - node _T_957 = xor(_T_956, _T_940) @[el2_lib.scala 259:74] - node _T_958 = xor(_T_957, _T_941) @[el2_lib.scala 259:74] - node _T_959 = xor(_T_958, _T_942) @[el2_lib.scala 259:74] - node _T_960 = xor(_T_959, _T_943) @[el2_lib.scala 259:74] - node _T_961 = xor(_T_960, _T_944) @[el2_lib.scala 259:74] - node _T_962 = xor(_T_961, _T_945) @[el2_lib.scala 259:74] - node _T_963 = xor(_T_962, _T_946) @[el2_lib.scala 259:74] - node _T_964 = xor(_T_963, _T_947) @[el2_lib.scala 259:74] - node _T_965 = xor(_T_964, _T_948) @[el2_lib.scala 259:74] - node _T_966 = xor(_T_965, _T_949) @[el2_lib.scala 259:74] - node _T_967 = xor(_T_966, _T_950) @[el2_lib.scala 259:74] - node _T_968 = xor(_T_967, _T_951) @[el2_lib.scala 259:74] - node _T_969 = xor(_T_968, _T_952) @[el2_lib.scala 259:74] - node _T_970 = xor(_T_969, _T_953) @[el2_lib.scala 259:74] - node _T_971 = xor(_T_970, _T_954) @[el2_lib.scala 259:74] - node _T_972 = xor(_T_971, _T_955) @[el2_lib.scala 259:74] - node _T_973 = bits(dccm_wdata_hi_any, 0, 0) @[el2_lib.scala 259:58] - node _T_974 = bits(dccm_wdata_hi_any, 2, 2) @[el2_lib.scala 259:58] - node _T_975 = bits(dccm_wdata_hi_any, 3, 3) @[el2_lib.scala 259:58] - node _T_976 = bits(dccm_wdata_hi_any, 5, 5) @[el2_lib.scala 259:58] - node _T_977 = bits(dccm_wdata_hi_any, 6, 6) @[el2_lib.scala 259:58] - node _T_978 = bits(dccm_wdata_hi_any, 9, 9) @[el2_lib.scala 259:58] - node _T_979 = bits(dccm_wdata_hi_any, 10, 10) @[el2_lib.scala 259:58] - node _T_980 = bits(dccm_wdata_hi_any, 12, 12) @[el2_lib.scala 259:58] - node _T_981 = bits(dccm_wdata_hi_any, 13, 13) @[el2_lib.scala 259:58] - node _T_982 = bits(dccm_wdata_hi_any, 16, 16) @[el2_lib.scala 259:58] - node _T_983 = bits(dccm_wdata_hi_any, 17, 17) @[el2_lib.scala 259:58] - node _T_984 = bits(dccm_wdata_hi_any, 20, 20) @[el2_lib.scala 259:58] - node _T_985 = bits(dccm_wdata_hi_any, 21, 21) @[el2_lib.scala 259:58] - node _T_986 = bits(dccm_wdata_hi_any, 24, 24) @[el2_lib.scala 259:58] - node _T_987 = bits(dccm_wdata_hi_any, 25, 25) @[el2_lib.scala 259:58] - node _T_988 = bits(dccm_wdata_hi_any, 27, 27) @[el2_lib.scala 259:58] - node _T_989 = bits(dccm_wdata_hi_any, 28, 28) @[el2_lib.scala 259:58] - node _T_990 = bits(dccm_wdata_hi_any, 31, 31) @[el2_lib.scala 259:58] - node _T_991 = xor(_T_973, _T_974) @[el2_lib.scala 259:74] - node _T_992 = xor(_T_991, _T_975) @[el2_lib.scala 259:74] - node _T_993 = xor(_T_992, _T_976) @[el2_lib.scala 259:74] - node _T_994 = xor(_T_993, _T_977) @[el2_lib.scala 259:74] - node _T_995 = xor(_T_994, _T_978) @[el2_lib.scala 259:74] - node _T_996 = xor(_T_995, _T_979) @[el2_lib.scala 259:74] - node _T_997 = xor(_T_996, _T_980) @[el2_lib.scala 259:74] - node _T_998 = xor(_T_997, _T_981) @[el2_lib.scala 259:74] - node _T_999 = xor(_T_998, _T_982) @[el2_lib.scala 259:74] - node _T_1000 = xor(_T_999, _T_983) @[el2_lib.scala 259:74] - node _T_1001 = xor(_T_1000, _T_984) @[el2_lib.scala 259:74] - node _T_1002 = xor(_T_1001, _T_985) @[el2_lib.scala 259:74] - node _T_1003 = xor(_T_1002, _T_986) @[el2_lib.scala 259:74] - node _T_1004 = xor(_T_1003, _T_987) @[el2_lib.scala 259:74] - node _T_1005 = xor(_T_1004, _T_988) @[el2_lib.scala 259:74] - node _T_1006 = xor(_T_1005, _T_989) @[el2_lib.scala 259:74] - node _T_1007 = xor(_T_1006, _T_990) @[el2_lib.scala 259:74] - node _T_1008 = bits(dccm_wdata_hi_any, 1, 1) @[el2_lib.scala 259:58] - node _T_1009 = bits(dccm_wdata_hi_any, 2, 2) @[el2_lib.scala 259:58] - node _T_1010 = bits(dccm_wdata_hi_any, 3, 3) @[el2_lib.scala 259:58] - node _T_1011 = bits(dccm_wdata_hi_any, 7, 7) @[el2_lib.scala 259:58] - node _T_1012 = bits(dccm_wdata_hi_any, 8, 8) @[el2_lib.scala 259:58] - node _T_1013 = bits(dccm_wdata_hi_any, 9, 9) @[el2_lib.scala 259:58] - node _T_1014 = bits(dccm_wdata_hi_any, 10, 10) @[el2_lib.scala 259:58] - node _T_1015 = bits(dccm_wdata_hi_any, 14, 14) @[el2_lib.scala 259:58] - node _T_1016 = bits(dccm_wdata_hi_any, 15, 15) @[el2_lib.scala 259:58] - node _T_1017 = bits(dccm_wdata_hi_any, 16, 16) @[el2_lib.scala 259:58] - node _T_1018 = bits(dccm_wdata_hi_any, 17, 17) @[el2_lib.scala 259:58] - node _T_1019 = bits(dccm_wdata_hi_any, 22, 22) @[el2_lib.scala 259:58] - node _T_1020 = bits(dccm_wdata_hi_any, 23, 23) @[el2_lib.scala 259:58] - node _T_1021 = bits(dccm_wdata_hi_any, 24, 24) @[el2_lib.scala 259:58] - node _T_1022 = bits(dccm_wdata_hi_any, 25, 25) @[el2_lib.scala 259:58] - node _T_1023 = bits(dccm_wdata_hi_any, 29, 29) @[el2_lib.scala 259:58] - node _T_1024 = bits(dccm_wdata_hi_any, 30, 30) @[el2_lib.scala 259:58] - node _T_1025 = bits(dccm_wdata_hi_any, 31, 31) @[el2_lib.scala 259:58] - node _T_1026 = xor(_T_1008, _T_1009) @[el2_lib.scala 259:74] - node _T_1027 = xor(_T_1026, _T_1010) @[el2_lib.scala 259:74] - node _T_1028 = xor(_T_1027, _T_1011) @[el2_lib.scala 259:74] - node _T_1029 = xor(_T_1028, _T_1012) @[el2_lib.scala 259:74] - node _T_1030 = xor(_T_1029, _T_1013) @[el2_lib.scala 259:74] - node _T_1031 = xor(_T_1030, _T_1014) @[el2_lib.scala 259:74] - node _T_1032 = xor(_T_1031, _T_1015) @[el2_lib.scala 259:74] - node _T_1033 = xor(_T_1032, _T_1016) @[el2_lib.scala 259:74] - node _T_1034 = xor(_T_1033, _T_1017) @[el2_lib.scala 259:74] - node _T_1035 = xor(_T_1034, _T_1018) @[el2_lib.scala 259:74] - node _T_1036 = xor(_T_1035, _T_1019) @[el2_lib.scala 259:74] - node _T_1037 = xor(_T_1036, _T_1020) @[el2_lib.scala 259:74] - node _T_1038 = xor(_T_1037, _T_1021) @[el2_lib.scala 259:74] - node _T_1039 = xor(_T_1038, _T_1022) @[el2_lib.scala 259:74] - node _T_1040 = xor(_T_1039, _T_1023) @[el2_lib.scala 259:74] - node _T_1041 = xor(_T_1040, _T_1024) @[el2_lib.scala 259:74] - node _T_1042 = xor(_T_1041, _T_1025) @[el2_lib.scala 259:74] - node _T_1043 = bits(dccm_wdata_hi_any, 4, 4) @[el2_lib.scala 259:58] - node _T_1044 = bits(dccm_wdata_hi_any, 5, 5) @[el2_lib.scala 259:58] - node _T_1045 = bits(dccm_wdata_hi_any, 6, 6) @[el2_lib.scala 259:58] - node _T_1046 = bits(dccm_wdata_hi_any, 7, 7) @[el2_lib.scala 259:58] - node _T_1047 = bits(dccm_wdata_hi_any, 8, 8) @[el2_lib.scala 259:58] - node _T_1048 = bits(dccm_wdata_hi_any, 9, 9) @[el2_lib.scala 259:58] - node _T_1049 = bits(dccm_wdata_hi_any, 10, 10) @[el2_lib.scala 259:58] - node _T_1050 = bits(dccm_wdata_hi_any, 18, 18) @[el2_lib.scala 259:58] - node _T_1051 = bits(dccm_wdata_hi_any, 19, 19) @[el2_lib.scala 259:58] - node _T_1052 = bits(dccm_wdata_hi_any, 20, 20) @[el2_lib.scala 259:58] - node _T_1053 = bits(dccm_wdata_hi_any, 21, 21) @[el2_lib.scala 259:58] - node _T_1054 = bits(dccm_wdata_hi_any, 22, 22) @[el2_lib.scala 259:58] - node _T_1055 = bits(dccm_wdata_hi_any, 23, 23) @[el2_lib.scala 259:58] - node _T_1056 = bits(dccm_wdata_hi_any, 24, 24) @[el2_lib.scala 259:58] - node _T_1057 = bits(dccm_wdata_hi_any, 25, 25) @[el2_lib.scala 259:58] - node _T_1058 = xor(_T_1043, _T_1044) @[el2_lib.scala 259:74] - node _T_1059 = xor(_T_1058, _T_1045) @[el2_lib.scala 259:74] - node _T_1060 = xor(_T_1059, _T_1046) @[el2_lib.scala 259:74] - node _T_1061 = xor(_T_1060, _T_1047) @[el2_lib.scala 259:74] - node _T_1062 = xor(_T_1061, _T_1048) @[el2_lib.scala 259:74] - node _T_1063 = xor(_T_1062, _T_1049) @[el2_lib.scala 259:74] - node _T_1064 = xor(_T_1063, _T_1050) @[el2_lib.scala 259:74] - node _T_1065 = xor(_T_1064, _T_1051) @[el2_lib.scala 259:74] - node _T_1066 = xor(_T_1065, _T_1052) @[el2_lib.scala 259:74] - node _T_1067 = xor(_T_1066, _T_1053) @[el2_lib.scala 259:74] - node _T_1068 = xor(_T_1067, _T_1054) @[el2_lib.scala 259:74] - node _T_1069 = xor(_T_1068, _T_1055) @[el2_lib.scala 259:74] - node _T_1070 = xor(_T_1069, _T_1056) @[el2_lib.scala 259:74] - node _T_1071 = xor(_T_1070, _T_1057) @[el2_lib.scala 259:74] - node _T_1072 = bits(dccm_wdata_hi_any, 11, 11) @[el2_lib.scala 259:58] - node _T_1073 = bits(dccm_wdata_hi_any, 12, 12) @[el2_lib.scala 259:58] - node _T_1074 = bits(dccm_wdata_hi_any, 13, 13) @[el2_lib.scala 259:58] - node _T_1075 = bits(dccm_wdata_hi_any, 14, 14) @[el2_lib.scala 259:58] - node _T_1076 = bits(dccm_wdata_hi_any, 15, 15) @[el2_lib.scala 259:58] - node _T_1077 = bits(dccm_wdata_hi_any, 16, 16) @[el2_lib.scala 259:58] - node _T_1078 = bits(dccm_wdata_hi_any, 17, 17) @[el2_lib.scala 259:58] - node _T_1079 = bits(dccm_wdata_hi_any, 18, 18) @[el2_lib.scala 259:58] - node _T_1080 = bits(dccm_wdata_hi_any, 19, 19) @[el2_lib.scala 259:58] - node _T_1081 = bits(dccm_wdata_hi_any, 20, 20) @[el2_lib.scala 259:58] - node _T_1082 = bits(dccm_wdata_hi_any, 21, 21) @[el2_lib.scala 259:58] - node _T_1083 = bits(dccm_wdata_hi_any, 22, 22) @[el2_lib.scala 259:58] - node _T_1084 = bits(dccm_wdata_hi_any, 23, 23) @[el2_lib.scala 259:58] - node _T_1085 = bits(dccm_wdata_hi_any, 24, 24) @[el2_lib.scala 259:58] - node _T_1086 = bits(dccm_wdata_hi_any, 25, 25) @[el2_lib.scala 259:58] - node _T_1087 = xor(_T_1072, _T_1073) @[el2_lib.scala 259:74] - node _T_1088 = xor(_T_1087, _T_1074) @[el2_lib.scala 259:74] - node _T_1089 = xor(_T_1088, _T_1075) @[el2_lib.scala 259:74] - node _T_1090 = xor(_T_1089, _T_1076) @[el2_lib.scala 259:74] - node _T_1091 = xor(_T_1090, _T_1077) @[el2_lib.scala 259:74] - node _T_1092 = xor(_T_1091, _T_1078) @[el2_lib.scala 259:74] - node _T_1093 = xor(_T_1092, _T_1079) @[el2_lib.scala 259:74] - node _T_1094 = xor(_T_1093, _T_1080) @[el2_lib.scala 259:74] - node _T_1095 = xor(_T_1094, _T_1081) @[el2_lib.scala 259:74] - node _T_1096 = xor(_T_1095, _T_1082) @[el2_lib.scala 259:74] - node _T_1097 = xor(_T_1096, _T_1083) @[el2_lib.scala 259:74] - node _T_1098 = xor(_T_1097, _T_1084) @[el2_lib.scala 259:74] - node _T_1099 = xor(_T_1098, _T_1085) @[el2_lib.scala 259:74] - node _T_1100 = xor(_T_1099, _T_1086) @[el2_lib.scala 259:74] - node _T_1101 = bits(dccm_wdata_hi_any, 26, 26) @[el2_lib.scala 259:58] - node _T_1102 = bits(dccm_wdata_hi_any, 27, 27) @[el2_lib.scala 259:58] - node _T_1103 = bits(dccm_wdata_hi_any, 28, 28) @[el2_lib.scala 259:58] - node _T_1104 = bits(dccm_wdata_hi_any, 29, 29) @[el2_lib.scala 259:58] - node _T_1105 = bits(dccm_wdata_hi_any, 30, 30) @[el2_lib.scala 259:58] - node _T_1106 = bits(dccm_wdata_hi_any, 31, 31) @[el2_lib.scala 259:58] - node _T_1107 = xor(_T_1101, _T_1102) @[el2_lib.scala 259:74] - node _T_1108 = xor(_T_1107, _T_1103) @[el2_lib.scala 259:74] - node _T_1109 = xor(_T_1108, _T_1104) @[el2_lib.scala 259:74] - node _T_1110 = xor(_T_1109, _T_1105) @[el2_lib.scala 259:74] - node _T_1111 = xor(_T_1110, _T_1106) @[el2_lib.scala 259:74] + node _T_938 = bits(dccm_wdata_hi_any, 0, 0) @[lib.scala 119:58] + node _T_939 = bits(dccm_wdata_hi_any, 1, 1) @[lib.scala 119:58] + node _T_940 = bits(dccm_wdata_hi_any, 3, 3) @[lib.scala 119:58] + node _T_941 = bits(dccm_wdata_hi_any, 4, 4) @[lib.scala 119:58] + node _T_942 = bits(dccm_wdata_hi_any, 6, 6) @[lib.scala 119:58] + node _T_943 = bits(dccm_wdata_hi_any, 8, 8) @[lib.scala 119:58] + node _T_944 = bits(dccm_wdata_hi_any, 10, 10) @[lib.scala 119:58] + node _T_945 = bits(dccm_wdata_hi_any, 11, 11) @[lib.scala 119:58] + node _T_946 = bits(dccm_wdata_hi_any, 13, 13) @[lib.scala 119:58] + node _T_947 = bits(dccm_wdata_hi_any, 15, 15) @[lib.scala 119:58] + node _T_948 = bits(dccm_wdata_hi_any, 17, 17) @[lib.scala 119:58] + node _T_949 = bits(dccm_wdata_hi_any, 19, 19) @[lib.scala 119:58] + node _T_950 = bits(dccm_wdata_hi_any, 21, 21) @[lib.scala 119:58] + node _T_951 = bits(dccm_wdata_hi_any, 23, 23) @[lib.scala 119:58] + node _T_952 = bits(dccm_wdata_hi_any, 25, 25) @[lib.scala 119:58] + node _T_953 = bits(dccm_wdata_hi_any, 26, 26) @[lib.scala 119:58] + node _T_954 = bits(dccm_wdata_hi_any, 28, 28) @[lib.scala 119:58] + node _T_955 = bits(dccm_wdata_hi_any, 30, 30) @[lib.scala 119:58] + node _T_956 = xor(_T_938, _T_939) @[lib.scala 119:74] + node _T_957 = xor(_T_956, _T_940) @[lib.scala 119:74] + node _T_958 = xor(_T_957, _T_941) @[lib.scala 119:74] + node _T_959 = xor(_T_958, _T_942) @[lib.scala 119:74] + node _T_960 = xor(_T_959, _T_943) @[lib.scala 119:74] + node _T_961 = xor(_T_960, _T_944) @[lib.scala 119:74] + node _T_962 = xor(_T_961, _T_945) @[lib.scala 119:74] + node _T_963 = xor(_T_962, _T_946) @[lib.scala 119:74] + node _T_964 = xor(_T_963, _T_947) @[lib.scala 119:74] + node _T_965 = xor(_T_964, _T_948) @[lib.scala 119:74] + node _T_966 = xor(_T_965, _T_949) @[lib.scala 119:74] + node _T_967 = xor(_T_966, _T_950) @[lib.scala 119:74] + node _T_968 = xor(_T_967, _T_951) @[lib.scala 119:74] + node _T_969 = xor(_T_968, _T_952) @[lib.scala 119:74] + node _T_970 = xor(_T_969, _T_953) @[lib.scala 119:74] + node _T_971 = xor(_T_970, _T_954) @[lib.scala 119:74] + node _T_972 = xor(_T_971, _T_955) @[lib.scala 119:74] + node _T_973 = bits(dccm_wdata_hi_any, 0, 0) @[lib.scala 119:58] + node _T_974 = bits(dccm_wdata_hi_any, 2, 2) @[lib.scala 119:58] + node _T_975 = bits(dccm_wdata_hi_any, 3, 3) @[lib.scala 119:58] + node _T_976 = bits(dccm_wdata_hi_any, 5, 5) @[lib.scala 119:58] + node _T_977 = bits(dccm_wdata_hi_any, 6, 6) @[lib.scala 119:58] + node _T_978 = bits(dccm_wdata_hi_any, 9, 9) @[lib.scala 119:58] + node _T_979 = bits(dccm_wdata_hi_any, 10, 10) @[lib.scala 119:58] + node _T_980 = bits(dccm_wdata_hi_any, 12, 12) @[lib.scala 119:58] + node _T_981 = bits(dccm_wdata_hi_any, 13, 13) @[lib.scala 119:58] + node _T_982 = bits(dccm_wdata_hi_any, 16, 16) @[lib.scala 119:58] + node _T_983 = bits(dccm_wdata_hi_any, 17, 17) @[lib.scala 119:58] + node _T_984 = bits(dccm_wdata_hi_any, 20, 20) @[lib.scala 119:58] + node _T_985 = bits(dccm_wdata_hi_any, 21, 21) @[lib.scala 119:58] + node _T_986 = bits(dccm_wdata_hi_any, 24, 24) @[lib.scala 119:58] + node _T_987 = bits(dccm_wdata_hi_any, 25, 25) @[lib.scala 119:58] + node _T_988 = bits(dccm_wdata_hi_any, 27, 27) @[lib.scala 119:58] + node _T_989 = bits(dccm_wdata_hi_any, 28, 28) @[lib.scala 119:58] + node _T_990 = bits(dccm_wdata_hi_any, 31, 31) @[lib.scala 119:58] + node _T_991 = xor(_T_973, _T_974) @[lib.scala 119:74] + node _T_992 = xor(_T_991, _T_975) @[lib.scala 119:74] + node _T_993 = xor(_T_992, _T_976) @[lib.scala 119:74] + node _T_994 = xor(_T_993, _T_977) @[lib.scala 119:74] + node _T_995 = xor(_T_994, _T_978) @[lib.scala 119:74] + node _T_996 = xor(_T_995, _T_979) @[lib.scala 119:74] + node _T_997 = xor(_T_996, _T_980) @[lib.scala 119:74] + node _T_998 = xor(_T_997, _T_981) @[lib.scala 119:74] + node _T_999 = xor(_T_998, _T_982) @[lib.scala 119:74] + node _T_1000 = xor(_T_999, _T_983) @[lib.scala 119:74] + node _T_1001 = xor(_T_1000, _T_984) @[lib.scala 119:74] + node _T_1002 = xor(_T_1001, _T_985) @[lib.scala 119:74] + node _T_1003 = xor(_T_1002, _T_986) @[lib.scala 119:74] + node _T_1004 = xor(_T_1003, _T_987) @[lib.scala 119:74] + node _T_1005 = xor(_T_1004, _T_988) @[lib.scala 119:74] + node _T_1006 = xor(_T_1005, _T_989) @[lib.scala 119:74] + node _T_1007 = xor(_T_1006, _T_990) @[lib.scala 119:74] + node _T_1008 = bits(dccm_wdata_hi_any, 1, 1) @[lib.scala 119:58] + node _T_1009 = bits(dccm_wdata_hi_any, 2, 2) @[lib.scala 119:58] + node _T_1010 = bits(dccm_wdata_hi_any, 3, 3) @[lib.scala 119:58] + node _T_1011 = bits(dccm_wdata_hi_any, 7, 7) @[lib.scala 119:58] + node _T_1012 = bits(dccm_wdata_hi_any, 8, 8) @[lib.scala 119:58] + node _T_1013 = bits(dccm_wdata_hi_any, 9, 9) @[lib.scala 119:58] + node _T_1014 = bits(dccm_wdata_hi_any, 10, 10) @[lib.scala 119:58] + node _T_1015 = bits(dccm_wdata_hi_any, 14, 14) @[lib.scala 119:58] + node _T_1016 = bits(dccm_wdata_hi_any, 15, 15) @[lib.scala 119:58] + node _T_1017 = bits(dccm_wdata_hi_any, 16, 16) @[lib.scala 119:58] + node _T_1018 = bits(dccm_wdata_hi_any, 17, 17) @[lib.scala 119:58] + node _T_1019 = bits(dccm_wdata_hi_any, 22, 22) @[lib.scala 119:58] + node _T_1020 = bits(dccm_wdata_hi_any, 23, 23) @[lib.scala 119:58] + node _T_1021 = bits(dccm_wdata_hi_any, 24, 24) @[lib.scala 119:58] + node _T_1022 = bits(dccm_wdata_hi_any, 25, 25) @[lib.scala 119:58] + node _T_1023 = bits(dccm_wdata_hi_any, 29, 29) @[lib.scala 119:58] + node _T_1024 = bits(dccm_wdata_hi_any, 30, 30) @[lib.scala 119:58] + node _T_1025 = bits(dccm_wdata_hi_any, 31, 31) @[lib.scala 119:58] + node _T_1026 = xor(_T_1008, _T_1009) @[lib.scala 119:74] + node _T_1027 = xor(_T_1026, _T_1010) @[lib.scala 119:74] + node _T_1028 = xor(_T_1027, _T_1011) @[lib.scala 119:74] + node _T_1029 = xor(_T_1028, _T_1012) @[lib.scala 119:74] + node _T_1030 = xor(_T_1029, _T_1013) @[lib.scala 119:74] + node _T_1031 = xor(_T_1030, _T_1014) @[lib.scala 119:74] + node _T_1032 = xor(_T_1031, _T_1015) @[lib.scala 119:74] + node _T_1033 = xor(_T_1032, _T_1016) @[lib.scala 119:74] + node _T_1034 = xor(_T_1033, _T_1017) @[lib.scala 119:74] + node _T_1035 = xor(_T_1034, _T_1018) @[lib.scala 119:74] + node _T_1036 = xor(_T_1035, _T_1019) @[lib.scala 119:74] + node _T_1037 = xor(_T_1036, _T_1020) @[lib.scala 119:74] + node _T_1038 = xor(_T_1037, _T_1021) @[lib.scala 119:74] + node _T_1039 = xor(_T_1038, _T_1022) @[lib.scala 119:74] + node _T_1040 = xor(_T_1039, _T_1023) @[lib.scala 119:74] + node _T_1041 = xor(_T_1040, _T_1024) @[lib.scala 119:74] + node _T_1042 = xor(_T_1041, _T_1025) @[lib.scala 119:74] + node _T_1043 = bits(dccm_wdata_hi_any, 4, 4) @[lib.scala 119:58] + node _T_1044 = bits(dccm_wdata_hi_any, 5, 5) @[lib.scala 119:58] + node _T_1045 = bits(dccm_wdata_hi_any, 6, 6) @[lib.scala 119:58] + node _T_1046 = bits(dccm_wdata_hi_any, 7, 7) @[lib.scala 119:58] + node _T_1047 = bits(dccm_wdata_hi_any, 8, 8) @[lib.scala 119:58] + node _T_1048 = bits(dccm_wdata_hi_any, 9, 9) @[lib.scala 119:58] + node _T_1049 = bits(dccm_wdata_hi_any, 10, 10) @[lib.scala 119:58] + node _T_1050 = bits(dccm_wdata_hi_any, 18, 18) @[lib.scala 119:58] + node _T_1051 = bits(dccm_wdata_hi_any, 19, 19) @[lib.scala 119:58] + node _T_1052 = bits(dccm_wdata_hi_any, 20, 20) @[lib.scala 119:58] + node _T_1053 = bits(dccm_wdata_hi_any, 21, 21) @[lib.scala 119:58] + node _T_1054 = bits(dccm_wdata_hi_any, 22, 22) @[lib.scala 119:58] + node _T_1055 = bits(dccm_wdata_hi_any, 23, 23) @[lib.scala 119:58] + node _T_1056 = bits(dccm_wdata_hi_any, 24, 24) @[lib.scala 119:58] + node _T_1057 = bits(dccm_wdata_hi_any, 25, 25) @[lib.scala 119:58] + node _T_1058 = xor(_T_1043, _T_1044) @[lib.scala 119:74] + node _T_1059 = xor(_T_1058, _T_1045) @[lib.scala 119:74] + node _T_1060 = xor(_T_1059, _T_1046) @[lib.scala 119:74] + node _T_1061 = xor(_T_1060, _T_1047) @[lib.scala 119:74] + node _T_1062 = xor(_T_1061, _T_1048) @[lib.scala 119:74] + node _T_1063 = xor(_T_1062, _T_1049) @[lib.scala 119:74] + node _T_1064 = xor(_T_1063, _T_1050) @[lib.scala 119:74] + node _T_1065 = xor(_T_1064, _T_1051) @[lib.scala 119:74] + node _T_1066 = xor(_T_1065, _T_1052) @[lib.scala 119:74] + node _T_1067 = xor(_T_1066, _T_1053) @[lib.scala 119:74] + node _T_1068 = xor(_T_1067, _T_1054) @[lib.scala 119:74] + node _T_1069 = xor(_T_1068, _T_1055) @[lib.scala 119:74] + node _T_1070 = xor(_T_1069, _T_1056) @[lib.scala 119:74] + node _T_1071 = xor(_T_1070, _T_1057) @[lib.scala 119:74] + node _T_1072 = bits(dccm_wdata_hi_any, 11, 11) @[lib.scala 119:58] + node _T_1073 = bits(dccm_wdata_hi_any, 12, 12) @[lib.scala 119:58] + node _T_1074 = bits(dccm_wdata_hi_any, 13, 13) @[lib.scala 119:58] + node _T_1075 = bits(dccm_wdata_hi_any, 14, 14) @[lib.scala 119:58] + node _T_1076 = bits(dccm_wdata_hi_any, 15, 15) @[lib.scala 119:58] + node _T_1077 = bits(dccm_wdata_hi_any, 16, 16) @[lib.scala 119:58] + node _T_1078 = bits(dccm_wdata_hi_any, 17, 17) @[lib.scala 119:58] + node _T_1079 = bits(dccm_wdata_hi_any, 18, 18) @[lib.scala 119:58] + node _T_1080 = bits(dccm_wdata_hi_any, 19, 19) @[lib.scala 119:58] + node _T_1081 = bits(dccm_wdata_hi_any, 20, 20) @[lib.scala 119:58] + node _T_1082 = bits(dccm_wdata_hi_any, 21, 21) @[lib.scala 119:58] + node _T_1083 = bits(dccm_wdata_hi_any, 22, 22) @[lib.scala 119:58] + node _T_1084 = bits(dccm_wdata_hi_any, 23, 23) @[lib.scala 119:58] + node _T_1085 = bits(dccm_wdata_hi_any, 24, 24) @[lib.scala 119:58] + node _T_1086 = bits(dccm_wdata_hi_any, 25, 25) @[lib.scala 119:58] + node _T_1087 = xor(_T_1072, _T_1073) @[lib.scala 119:74] + node _T_1088 = xor(_T_1087, _T_1074) @[lib.scala 119:74] + node _T_1089 = xor(_T_1088, _T_1075) @[lib.scala 119:74] + node _T_1090 = xor(_T_1089, _T_1076) @[lib.scala 119:74] + node _T_1091 = xor(_T_1090, _T_1077) @[lib.scala 119:74] + node _T_1092 = xor(_T_1091, _T_1078) @[lib.scala 119:74] + node _T_1093 = xor(_T_1092, _T_1079) @[lib.scala 119:74] + node _T_1094 = xor(_T_1093, _T_1080) @[lib.scala 119:74] + node _T_1095 = xor(_T_1094, _T_1081) @[lib.scala 119:74] + node _T_1096 = xor(_T_1095, _T_1082) @[lib.scala 119:74] + node _T_1097 = xor(_T_1096, _T_1083) @[lib.scala 119:74] + node _T_1098 = xor(_T_1097, _T_1084) @[lib.scala 119:74] + node _T_1099 = xor(_T_1098, _T_1085) @[lib.scala 119:74] + node _T_1100 = xor(_T_1099, _T_1086) @[lib.scala 119:74] + node _T_1101 = bits(dccm_wdata_hi_any, 26, 26) @[lib.scala 119:58] + node _T_1102 = bits(dccm_wdata_hi_any, 27, 27) @[lib.scala 119:58] + node _T_1103 = bits(dccm_wdata_hi_any, 28, 28) @[lib.scala 119:58] + node _T_1104 = bits(dccm_wdata_hi_any, 29, 29) @[lib.scala 119:58] + node _T_1105 = bits(dccm_wdata_hi_any, 30, 30) @[lib.scala 119:58] + node _T_1106 = bits(dccm_wdata_hi_any, 31, 31) @[lib.scala 119:58] + node _T_1107 = xor(_T_1101, _T_1102) @[lib.scala 119:74] + node _T_1108 = xor(_T_1107, _T_1103) @[lib.scala 119:74] + node _T_1109 = xor(_T_1108, _T_1104) @[lib.scala 119:74] + node _T_1110 = xor(_T_1109, _T_1105) @[lib.scala 119:74] + node _T_1111 = xor(_T_1110, _T_1106) @[lib.scala 119:74] node _T_1112 = cat(_T_1042, _T_1007) @[Cat.scala 29:58] node _T_1113 = cat(_T_1112, _T_972) @[Cat.scala 29:58] node _T_1114 = cat(_T_1111, _T_1100) @[Cat.scala 29:58] node _T_1115 = cat(_T_1114, _T_1071) @[Cat.scala 29:58] node _T_1116 = cat(_T_1115, _T_1113) @[Cat.scala 29:58] - node _T_1117 = xorr(dccm_wdata_hi_any) @[el2_lib.scala 267:13] - node _T_1118 = xorr(_T_1116) @[el2_lib.scala 267:23] - node _T_1119 = xor(_T_1117, _T_1118) @[el2_lib.scala 267:18] + node _T_1117 = xorr(dccm_wdata_hi_any) @[lib.scala 127:13] + node _T_1118 = xorr(_T_1116) @[lib.scala 127:23] + node _T_1119 = xor(_T_1117, _T_1118) @[lib.scala 127:18] node dccm_wdata_ecc_hi_any = cat(_T_1119, _T_1116) @[Cat.scala 29:58] when UInt<1>("h00") : @[lsu_ecc.scala 103:30] node _T_1120 = bits(io.lsu_addr_r, 2, 2) @[lsu_ecc.scala 104:33] @@ -92941,23 +92933,23 @@ circuit quasar_wrapper : io.stbuf_ecc_any <= dccm_wdata_ecc_lo_any @[lsu_ecc.scala 153:28] io.dma_dccm_wdata_ecc_hi <= dccm_wdata_ecc_hi_any @[lsu_ecc.scala 154:28] io.dma_dccm_wdata_ecc_lo <= dccm_wdata_ecc_lo_any @[lsu_ecc.scala 155:28] - inst rvclkhdr of rvclkhdr_800 @[el2_lib.scala 508:23] + inst rvclkhdr of rvclkhdr_800 @[lib.scala 368:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr.io.en <= io.ld_single_ecc_error_r @[el2_lib.scala 511:17] - rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_1164 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_1164 <= io.sec_data_hi_r @[el2_lib.scala 514:16] + rvclkhdr.io.clk <= clock @[lib.scala 370:18] + rvclkhdr.io.en <= io.ld_single_ecc_error_r @[lib.scala 371:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_1164 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1164 <= io.sec_data_hi_r @[lib.scala 374:16] io.sec_data_hi_r_ff <= _T_1164 @[lsu_ecc.scala 157:23] - inst rvclkhdr_1 of rvclkhdr_801 @[el2_lib.scala 508:23] + inst rvclkhdr_1 of rvclkhdr_801 @[lib.scala 368:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_1.io.en <= io.ld_single_ecc_error_r @[el2_lib.scala 511:17] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_1165 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_1165 <= io.sec_data_lo_r @[el2_lib.scala 514:16] + rvclkhdr_1.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_1.io.en <= io.ld_single_ecc_error_r @[lib.scala 371:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_1165 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1165 <= io.sec_data_lo_r @[lib.scala 374:16] io.sec_data_lo_r_ff <= _T_1165 @[lsu_ecc.scala 158:23] module lsu_trigger : @@ -93022,295 +93014,295 @@ circuit quasar_wrapper : node _T_45 = or(_T_41, _T_44) @[lsu_trigger.scala 18:152] node _T_46 = and(_T_40, _T_45) @[lsu_trigger.scala 18:94] node _T_47 = bits(io.trigger_pkt_any[0].match_pkt, 0, 0) @[lsu_trigger.scala 20:107] - wire _T_48 : UInt<1>[32] @[el2_lib.scala 240:24] - node _T_49 = andr(io.trigger_pkt_any[0].tdata2) @[el2_lib.scala 241:45] - node _T_50 = not(_T_49) @[el2_lib.scala 241:39] - node _T_51 = and(_T_47, _T_50) @[el2_lib.scala 241:37] - node _T_52 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[el2_lib.scala 242:48] - node _T_53 = bits(lsu_match_data_0, 0, 0) @[el2_lib.scala 242:60] - node _T_54 = eq(_T_52, _T_53) @[el2_lib.scala 242:52] - node _T_55 = or(_T_51, _T_54) @[el2_lib.scala 242:41] - _T_48[0] <= _T_55 @[el2_lib.scala 242:18] - node _T_56 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[el2_lib.scala 244:28] - node _T_57 = andr(_T_56) @[el2_lib.scala 244:36] - node _T_58 = and(_T_57, _T_51) @[el2_lib.scala 244:41] - node _T_59 = bits(io.trigger_pkt_any[0].tdata2, 1, 1) @[el2_lib.scala 244:74] - node _T_60 = bits(lsu_match_data_0, 1, 1) @[el2_lib.scala 244:86] - node _T_61 = eq(_T_59, _T_60) @[el2_lib.scala 244:78] - node _T_62 = mux(_T_58, UInt<1>("h01"), _T_61) @[el2_lib.scala 244:23] - _T_48[1] <= _T_62 @[el2_lib.scala 244:17] - node _T_63 = bits(io.trigger_pkt_any[0].tdata2, 1, 0) @[el2_lib.scala 244:28] - node _T_64 = andr(_T_63) @[el2_lib.scala 244:36] - node _T_65 = and(_T_64, _T_51) @[el2_lib.scala 244:41] - node _T_66 = bits(io.trigger_pkt_any[0].tdata2, 2, 2) @[el2_lib.scala 244:74] - node _T_67 = bits(lsu_match_data_0, 2, 2) @[el2_lib.scala 244:86] - node _T_68 = eq(_T_66, _T_67) @[el2_lib.scala 244:78] - node _T_69 = mux(_T_65, UInt<1>("h01"), _T_68) @[el2_lib.scala 244:23] - _T_48[2] <= _T_69 @[el2_lib.scala 244:17] - node _T_70 = bits(io.trigger_pkt_any[0].tdata2, 2, 0) @[el2_lib.scala 244:28] - node _T_71 = andr(_T_70) @[el2_lib.scala 244:36] - node _T_72 = and(_T_71, _T_51) @[el2_lib.scala 244:41] - node _T_73 = bits(io.trigger_pkt_any[0].tdata2, 3, 3) @[el2_lib.scala 244:74] - node _T_74 = bits(lsu_match_data_0, 3, 3) @[el2_lib.scala 244:86] - node _T_75 = eq(_T_73, _T_74) @[el2_lib.scala 244:78] - node _T_76 = mux(_T_72, UInt<1>("h01"), _T_75) @[el2_lib.scala 244:23] - _T_48[3] <= _T_76 @[el2_lib.scala 244:17] - node _T_77 = bits(io.trigger_pkt_any[0].tdata2, 3, 0) @[el2_lib.scala 244:28] - node _T_78 = andr(_T_77) @[el2_lib.scala 244:36] - node _T_79 = and(_T_78, _T_51) @[el2_lib.scala 244:41] - node _T_80 = bits(io.trigger_pkt_any[0].tdata2, 4, 4) @[el2_lib.scala 244:74] - node _T_81 = bits(lsu_match_data_0, 4, 4) @[el2_lib.scala 244:86] - node _T_82 = eq(_T_80, _T_81) @[el2_lib.scala 244:78] - node _T_83 = mux(_T_79, UInt<1>("h01"), _T_82) @[el2_lib.scala 244:23] - _T_48[4] <= _T_83 @[el2_lib.scala 244:17] - node _T_84 = bits(io.trigger_pkt_any[0].tdata2, 4, 0) @[el2_lib.scala 244:28] - node _T_85 = andr(_T_84) @[el2_lib.scala 244:36] - node _T_86 = and(_T_85, _T_51) @[el2_lib.scala 244:41] - node _T_87 = bits(io.trigger_pkt_any[0].tdata2, 5, 5) @[el2_lib.scala 244:74] - node _T_88 = bits(lsu_match_data_0, 5, 5) @[el2_lib.scala 244:86] - node _T_89 = eq(_T_87, _T_88) @[el2_lib.scala 244:78] - node _T_90 = mux(_T_86, UInt<1>("h01"), _T_89) @[el2_lib.scala 244:23] - _T_48[5] <= _T_90 @[el2_lib.scala 244:17] - node _T_91 = bits(io.trigger_pkt_any[0].tdata2, 5, 0) @[el2_lib.scala 244:28] - node _T_92 = andr(_T_91) @[el2_lib.scala 244:36] - node _T_93 = and(_T_92, _T_51) @[el2_lib.scala 244:41] - node _T_94 = bits(io.trigger_pkt_any[0].tdata2, 6, 6) @[el2_lib.scala 244:74] - node _T_95 = bits(lsu_match_data_0, 6, 6) @[el2_lib.scala 244:86] - node _T_96 = eq(_T_94, _T_95) @[el2_lib.scala 244:78] - node _T_97 = mux(_T_93, UInt<1>("h01"), _T_96) @[el2_lib.scala 244:23] - _T_48[6] <= _T_97 @[el2_lib.scala 244:17] - node _T_98 = bits(io.trigger_pkt_any[0].tdata2, 6, 0) @[el2_lib.scala 244:28] - node _T_99 = andr(_T_98) @[el2_lib.scala 244:36] - node _T_100 = and(_T_99, _T_51) @[el2_lib.scala 244:41] - node _T_101 = bits(io.trigger_pkt_any[0].tdata2, 7, 7) @[el2_lib.scala 244:74] - node _T_102 = bits(lsu_match_data_0, 7, 7) @[el2_lib.scala 244:86] - node _T_103 = eq(_T_101, _T_102) @[el2_lib.scala 244:78] - node _T_104 = mux(_T_100, UInt<1>("h01"), _T_103) @[el2_lib.scala 244:23] - _T_48[7] <= _T_104 @[el2_lib.scala 244:17] - node _T_105 = bits(io.trigger_pkt_any[0].tdata2, 7, 0) @[el2_lib.scala 244:28] - node _T_106 = andr(_T_105) @[el2_lib.scala 244:36] - node _T_107 = and(_T_106, _T_51) @[el2_lib.scala 244:41] - node _T_108 = bits(io.trigger_pkt_any[0].tdata2, 8, 8) @[el2_lib.scala 244:74] - node _T_109 = bits(lsu_match_data_0, 8, 8) @[el2_lib.scala 244:86] - node _T_110 = eq(_T_108, _T_109) @[el2_lib.scala 244:78] - node _T_111 = mux(_T_107, UInt<1>("h01"), _T_110) @[el2_lib.scala 244:23] - _T_48[8] <= _T_111 @[el2_lib.scala 244:17] - node _T_112 = bits(io.trigger_pkt_any[0].tdata2, 8, 0) @[el2_lib.scala 244:28] - node _T_113 = andr(_T_112) @[el2_lib.scala 244:36] - node _T_114 = and(_T_113, _T_51) @[el2_lib.scala 244:41] - node _T_115 = bits(io.trigger_pkt_any[0].tdata2, 9, 9) @[el2_lib.scala 244:74] - node _T_116 = bits(lsu_match_data_0, 9, 9) @[el2_lib.scala 244:86] - node _T_117 = eq(_T_115, _T_116) @[el2_lib.scala 244:78] - node _T_118 = mux(_T_114, UInt<1>("h01"), _T_117) @[el2_lib.scala 244:23] - _T_48[9] <= _T_118 @[el2_lib.scala 244:17] - node _T_119 = bits(io.trigger_pkt_any[0].tdata2, 9, 0) @[el2_lib.scala 244:28] - node _T_120 = andr(_T_119) @[el2_lib.scala 244:36] - node _T_121 = and(_T_120, _T_51) @[el2_lib.scala 244:41] - node _T_122 = bits(io.trigger_pkt_any[0].tdata2, 10, 10) @[el2_lib.scala 244:74] - node _T_123 = bits(lsu_match_data_0, 10, 10) @[el2_lib.scala 244:86] - node _T_124 = eq(_T_122, _T_123) @[el2_lib.scala 244:78] - node _T_125 = mux(_T_121, UInt<1>("h01"), _T_124) @[el2_lib.scala 244:23] - _T_48[10] <= _T_125 @[el2_lib.scala 244:17] - node _T_126 = bits(io.trigger_pkt_any[0].tdata2, 10, 0) @[el2_lib.scala 244:28] - node _T_127 = andr(_T_126) @[el2_lib.scala 244:36] - node _T_128 = and(_T_127, _T_51) @[el2_lib.scala 244:41] - node _T_129 = bits(io.trigger_pkt_any[0].tdata2, 11, 11) @[el2_lib.scala 244:74] - node _T_130 = bits(lsu_match_data_0, 11, 11) @[el2_lib.scala 244:86] - node _T_131 = eq(_T_129, _T_130) @[el2_lib.scala 244:78] - node _T_132 = mux(_T_128, UInt<1>("h01"), _T_131) @[el2_lib.scala 244:23] - _T_48[11] <= _T_132 @[el2_lib.scala 244:17] - node _T_133 = bits(io.trigger_pkt_any[0].tdata2, 11, 0) @[el2_lib.scala 244:28] - node _T_134 = andr(_T_133) @[el2_lib.scala 244:36] - node _T_135 = and(_T_134, _T_51) @[el2_lib.scala 244:41] - node _T_136 = bits(io.trigger_pkt_any[0].tdata2, 12, 12) @[el2_lib.scala 244:74] - node _T_137 = bits(lsu_match_data_0, 12, 12) @[el2_lib.scala 244:86] - node _T_138 = eq(_T_136, _T_137) @[el2_lib.scala 244:78] - node _T_139 = mux(_T_135, UInt<1>("h01"), _T_138) @[el2_lib.scala 244:23] - _T_48[12] <= _T_139 @[el2_lib.scala 244:17] - node _T_140 = bits(io.trigger_pkt_any[0].tdata2, 12, 0) @[el2_lib.scala 244:28] - node _T_141 = andr(_T_140) @[el2_lib.scala 244:36] - node _T_142 = and(_T_141, _T_51) @[el2_lib.scala 244:41] - node _T_143 = bits(io.trigger_pkt_any[0].tdata2, 13, 13) @[el2_lib.scala 244:74] - node _T_144 = bits(lsu_match_data_0, 13, 13) @[el2_lib.scala 244:86] - node _T_145 = eq(_T_143, _T_144) @[el2_lib.scala 244:78] - node _T_146 = mux(_T_142, UInt<1>("h01"), _T_145) @[el2_lib.scala 244:23] - _T_48[13] <= _T_146 @[el2_lib.scala 244:17] - node _T_147 = bits(io.trigger_pkt_any[0].tdata2, 13, 0) @[el2_lib.scala 244:28] - node _T_148 = andr(_T_147) @[el2_lib.scala 244:36] - node _T_149 = and(_T_148, _T_51) @[el2_lib.scala 244:41] - node _T_150 = bits(io.trigger_pkt_any[0].tdata2, 14, 14) @[el2_lib.scala 244:74] - node _T_151 = bits(lsu_match_data_0, 14, 14) @[el2_lib.scala 244:86] - node _T_152 = eq(_T_150, _T_151) @[el2_lib.scala 244:78] - node _T_153 = mux(_T_149, UInt<1>("h01"), _T_152) @[el2_lib.scala 244:23] - _T_48[14] <= _T_153 @[el2_lib.scala 244:17] - node _T_154 = bits(io.trigger_pkt_any[0].tdata2, 14, 0) @[el2_lib.scala 244:28] - node _T_155 = andr(_T_154) @[el2_lib.scala 244:36] - node _T_156 = and(_T_155, _T_51) @[el2_lib.scala 244:41] - node _T_157 = bits(io.trigger_pkt_any[0].tdata2, 15, 15) @[el2_lib.scala 244:74] - node _T_158 = bits(lsu_match_data_0, 15, 15) @[el2_lib.scala 244:86] - node _T_159 = eq(_T_157, _T_158) @[el2_lib.scala 244:78] - node _T_160 = mux(_T_156, UInt<1>("h01"), _T_159) @[el2_lib.scala 244:23] - _T_48[15] <= _T_160 @[el2_lib.scala 244:17] - node _T_161 = bits(io.trigger_pkt_any[0].tdata2, 15, 0) @[el2_lib.scala 244:28] - node _T_162 = andr(_T_161) @[el2_lib.scala 244:36] - node _T_163 = and(_T_162, _T_51) @[el2_lib.scala 244:41] - node _T_164 = bits(io.trigger_pkt_any[0].tdata2, 16, 16) @[el2_lib.scala 244:74] - node _T_165 = bits(lsu_match_data_0, 16, 16) @[el2_lib.scala 244:86] - node _T_166 = eq(_T_164, _T_165) @[el2_lib.scala 244:78] - node _T_167 = mux(_T_163, UInt<1>("h01"), _T_166) @[el2_lib.scala 244:23] - _T_48[16] <= _T_167 @[el2_lib.scala 244:17] - node _T_168 = bits(io.trigger_pkt_any[0].tdata2, 16, 0) @[el2_lib.scala 244:28] - node _T_169 = andr(_T_168) @[el2_lib.scala 244:36] - node _T_170 = and(_T_169, _T_51) @[el2_lib.scala 244:41] - node _T_171 = bits(io.trigger_pkt_any[0].tdata2, 17, 17) @[el2_lib.scala 244:74] - node _T_172 = bits(lsu_match_data_0, 17, 17) @[el2_lib.scala 244:86] - node _T_173 = eq(_T_171, _T_172) @[el2_lib.scala 244:78] - node _T_174 = mux(_T_170, UInt<1>("h01"), _T_173) @[el2_lib.scala 244:23] - _T_48[17] <= _T_174 @[el2_lib.scala 244:17] - node _T_175 = bits(io.trigger_pkt_any[0].tdata2, 17, 0) @[el2_lib.scala 244:28] - node _T_176 = andr(_T_175) @[el2_lib.scala 244:36] - node _T_177 = and(_T_176, _T_51) @[el2_lib.scala 244:41] - node _T_178 = bits(io.trigger_pkt_any[0].tdata2, 18, 18) @[el2_lib.scala 244:74] - node _T_179 = bits(lsu_match_data_0, 18, 18) @[el2_lib.scala 244:86] - node _T_180 = eq(_T_178, _T_179) @[el2_lib.scala 244:78] - node _T_181 = mux(_T_177, UInt<1>("h01"), _T_180) @[el2_lib.scala 244:23] - _T_48[18] <= _T_181 @[el2_lib.scala 244:17] - node _T_182 = bits(io.trigger_pkt_any[0].tdata2, 18, 0) @[el2_lib.scala 244:28] - node _T_183 = andr(_T_182) @[el2_lib.scala 244:36] - node _T_184 = and(_T_183, _T_51) @[el2_lib.scala 244:41] - node _T_185 = bits(io.trigger_pkt_any[0].tdata2, 19, 19) @[el2_lib.scala 244:74] - node _T_186 = bits(lsu_match_data_0, 19, 19) @[el2_lib.scala 244:86] - node _T_187 = eq(_T_185, _T_186) @[el2_lib.scala 244:78] - node _T_188 = mux(_T_184, UInt<1>("h01"), _T_187) @[el2_lib.scala 244:23] - _T_48[19] <= _T_188 @[el2_lib.scala 244:17] - node _T_189 = bits(io.trigger_pkt_any[0].tdata2, 19, 0) @[el2_lib.scala 244:28] - node _T_190 = andr(_T_189) @[el2_lib.scala 244:36] - node _T_191 = and(_T_190, _T_51) @[el2_lib.scala 244:41] - node _T_192 = bits(io.trigger_pkt_any[0].tdata2, 20, 20) @[el2_lib.scala 244:74] - node _T_193 = bits(lsu_match_data_0, 20, 20) @[el2_lib.scala 244:86] - node _T_194 = eq(_T_192, _T_193) @[el2_lib.scala 244:78] - node _T_195 = mux(_T_191, UInt<1>("h01"), _T_194) @[el2_lib.scala 244:23] - _T_48[20] <= _T_195 @[el2_lib.scala 244:17] - node _T_196 = bits(io.trigger_pkt_any[0].tdata2, 20, 0) @[el2_lib.scala 244:28] - node _T_197 = andr(_T_196) @[el2_lib.scala 244:36] - node _T_198 = and(_T_197, _T_51) @[el2_lib.scala 244:41] - node _T_199 = bits(io.trigger_pkt_any[0].tdata2, 21, 21) @[el2_lib.scala 244:74] - node _T_200 = bits(lsu_match_data_0, 21, 21) @[el2_lib.scala 244:86] - node _T_201 = eq(_T_199, _T_200) @[el2_lib.scala 244:78] - node _T_202 = mux(_T_198, UInt<1>("h01"), _T_201) @[el2_lib.scala 244:23] - _T_48[21] <= _T_202 @[el2_lib.scala 244:17] - node _T_203 = bits(io.trigger_pkt_any[0].tdata2, 21, 0) @[el2_lib.scala 244:28] - node _T_204 = andr(_T_203) @[el2_lib.scala 244:36] - node _T_205 = and(_T_204, _T_51) @[el2_lib.scala 244:41] - node _T_206 = bits(io.trigger_pkt_any[0].tdata2, 22, 22) @[el2_lib.scala 244:74] - node _T_207 = bits(lsu_match_data_0, 22, 22) @[el2_lib.scala 244:86] - node _T_208 = eq(_T_206, _T_207) @[el2_lib.scala 244:78] - node _T_209 = mux(_T_205, UInt<1>("h01"), _T_208) @[el2_lib.scala 244:23] - _T_48[22] <= _T_209 @[el2_lib.scala 244:17] - node _T_210 = bits(io.trigger_pkt_any[0].tdata2, 22, 0) @[el2_lib.scala 244:28] - node _T_211 = andr(_T_210) @[el2_lib.scala 244:36] - node _T_212 = and(_T_211, _T_51) @[el2_lib.scala 244:41] - node _T_213 = bits(io.trigger_pkt_any[0].tdata2, 23, 23) @[el2_lib.scala 244:74] - node _T_214 = bits(lsu_match_data_0, 23, 23) @[el2_lib.scala 244:86] - node _T_215 = eq(_T_213, _T_214) @[el2_lib.scala 244:78] - node _T_216 = mux(_T_212, UInt<1>("h01"), _T_215) @[el2_lib.scala 244:23] - _T_48[23] <= _T_216 @[el2_lib.scala 244:17] - node _T_217 = bits(io.trigger_pkt_any[0].tdata2, 23, 0) @[el2_lib.scala 244:28] - node _T_218 = andr(_T_217) @[el2_lib.scala 244:36] - node _T_219 = and(_T_218, _T_51) @[el2_lib.scala 244:41] - node _T_220 = bits(io.trigger_pkt_any[0].tdata2, 24, 24) @[el2_lib.scala 244:74] - node _T_221 = bits(lsu_match_data_0, 24, 24) @[el2_lib.scala 244:86] - node _T_222 = eq(_T_220, _T_221) @[el2_lib.scala 244:78] - node _T_223 = mux(_T_219, UInt<1>("h01"), _T_222) @[el2_lib.scala 244:23] - _T_48[24] <= _T_223 @[el2_lib.scala 244:17] - node _T_224 = bits(io.trigger_pkt_any[0].tdata2, 24, 0) @[el2_lib.scala 244:28] - node _T_225 = andr(_T_224) @[el2_lib.scala 244:36] - node _T_226 = and(_T_225, _T_51) @[el2_lib.scala 244:41] - node _T_227 = bits(io.trigger_pkt_any[0].tdata2, 25, 25) @[el2_lib.scala 244:74] - node _T_228 = bits(lsu_match_data_0, 25, 25) @[el2_lib.scala 244:86] - node _T_229 = eq(_T_227, _T_228) @[el2_lib.scala 244:78] - node _T_230 = mux(_T_226, UInt<1>("h01"), _T_229) @[el2_lib.scala 244:23] - _T_48[25] <= _T_230 @[el2_lib.scala 244:17] - node _T_231 = bits(io.trigger_pkt_any[0].tdata2, 25, 0) @[el2_lib.scala 244:28] - node _T_232 = andr(_T_231) @[el2_lib.scala 244:36] - node _T_233 = and(_T_232, _T_51) @[el2_lib.scala 244:41] - node _T_234 = bits(io.trigger_pkt_any[0].tdata2, 26, 26) @[el2_lib.scala 244:74] - node _T_235 = bits(lsu_match_data_0, 26, 26) @[el2_lib.scala 244:86] - node _T_236 = eq(_T_234, _T_235) @[el2_lib.scala 244:78] - node _T_237 = mux(_T_233, UInt<1>("h01"), _T_236) @[el2_lib.scala 244:23] - _T_48[26] <= _T_237 @[el2_lib.scala 244:17] - node _T_238 = bits(io.trigger_pkt_any[0].tdata2, 26, 0) @[el2_lib.scala 244:28] - node _T_239 = andr(_T_238) @[el2_lib.scala 244:36] - node _T_240 = and(_T_239, _T_51) @[el2_lib.scala 244:41] - node _T_241 = bits(io.trigger_pkt_any[0].tdata2, 27, 27) @[el2_lib.scala 244:74] - node _T_242 = bits(lsu_match_data_0, 27, 27) @[el2_lib.scala 244:86] - node _T_243 = eq(_T_241, _T_242) @[el2_lib.scala 244:78] - node _T_244 = mux(_T_240, UInt<1>("h01"), _T_243) @[el2_lib.scala 244:23] - _T_48[27] <= _T_244 @[el2_lib.scala 244:17] - node _T_245 = bits(io.trigger_pkt_any[0].tdata2, 27, 0) @[el2_lib.scala 244:28] - node _T_246 = andr(_T_245) @[el2_lib.scala 244:36] - node _T_247 = and(_T_246, _T_51) @[el2_lib.scala 244:41] - node _T_248 = bits(io.trigger_pkt_any[0].tdata2, 28, 28) @[el2_lib.scala 244:74] - node _T_249 = bits(lsu_match_data_0, 28, 28) @[el2_lib.scala 244:86] - node _T_250 = eq(_T_248, _T_249) @[el2_lib.scala 244:78] - node _T_251 = mux(_T_247, UInt<1>("h01"), _T_250) @[el2_lib.scala 244:23] - _T_48[28] <= _T_251 @[el2_lib.scala 244:17] - node _T_252 = bits(io.trigger_pkt_any[0].tdata2, 28, 0) @[el2_lib.scala 244:28] - node _T_253 = andr(_T_252) @[el2_lib.scala 244:36] - node _T_254 = and(_T_253, _T_51) @[el2_lib.scala 244:41] - node _T_255 = bits(io.trigger_pkt_any[0].tdata2, 29, 29) @[el2_lib.scala 244:74] - node _T_256 = bits(lsu_match_data_0, 29, 29) @[el2_lib.scala 244:86] - node _T_257 = eq(_T_255, _T_256) @[el2_lib.scala 244:78] - node _T_258 = mux(_T_254, UInt<1>("h01"), _T_257) @[el2_lib.scala 244:23] - _T_48[29] <= _T_258 @[el2_lib.scala 244:17] - node _T_259 = bits(io.trigger_pkt_any[0].tdata2, 29, 0) @[el2_lib.scala 244:28] - node _T_260 = andr(_T_259) @[el2_lib.scala 244:36] - node _T_261 = and(_T_260, _T_51) @[el2_lib.scala 244:41] - node _T_262 = bits(io.trigger_pkt_any[0].tdata2, 30, 30) @[el2_lib.scala 244:74] - node _T_263 = bits(lsu_match_data_0, 30, 30) @[el2_lib.scala 244:86] - node _T_264 = eq(_T_262, _T_263) @[el2_lib.scala 244:78] - node _T_265 = mux(_T_261, UInt<1>("h01"), _T_264) @[el2_lib.scala 244:23] - _T_48[30] <= _T_265 @[el2_lib.scala 244:17] - node _T_266 = bits(io.trigger_pkt_any[0].tdata2, 30, 0) @[el2_lib.scala 244:28] - node _T_267 = andr(_T_266) @[el2_lib.scala 244:36] - node _T_268 = and(_T_267, _T_51) @[el2_lib.scala 244:41] - node _T_269 = bits(io.trigger_pkt_any[0].tdata2, 31, 31) @[el2_lib.scala 244:74] - node _T_270 = bits(lsu_match_data_0, 31, 31) @[el2_lib.scala 244:86] - node _T_271 = eq(_T_269, _T_270) @[el2_lib.scala 244:78] - node _T_272 = mux(_T_268, UInt<1>("h01"), _T_271) @[el2_lib.scala 244:23] - _T_48[31] <= _T_272 @[el2_lib.scala 244:17] - node _T_273 = cat(_T_48[1], _T_48[0]) @[el2_lib.scala 245:14] - node _T_274 = cat(_T_48[3], _T_48[2]) @[el2_lib.scala 245:14] - node _T_275 = cat(_T_274, _T_273) @[el2_lib.scala 245:14] - node _T_276 = cat(_T_48[5], _T_48[4]) @[el2_lib.scala 245:14] - node _T_277 = cat(_T_48[7], _T_48[6]) @[el2_lib.scala 245:14] - node _T_278 = cat(_T_277, _T_276) @[el2_lib.scala 245:14] - node _T_279 = cat(_T_278, _T_275) @[el2_lib.scala 245:14] - node _T_280 = cat(_T_48[9], _T_48[8]) @[el2_lib.scala 245:14] - node _T_281 = cat(_T_48[11], _T_48[10]) @[el2_lib.scala 245:14] - node _T_282 = cat(_T_281, _T_280) @[el2_lib.scala 245:14] - node _T_283 = cat(_T_48[13], _T_48[12]) @[el2_lib.scala 245:14] - node _T_284 = cat(_T_48[15], _T_48[14]) @[el2_lib.scala 245:14] - node _T_285 = cat(_T_284, _T_283) @[el2_lib.scala 245:14] - node _T_286 = cat(_T_285, _T_282) @[el2_lib.scala 245:14] - node _T_287 = cat(_T_286, _T_279) @[el2_lib.scala 245:14] - node _T_288 = cat(_T_48[17], _T_48[16]) @[el2_lib.scala 245:14] - node _T_289 = cat(_T_48[19], _T_48[18]) @[el2_lib.scala 245:14] - node _T_290 = cat(_T_289, _T_288) @[el2_lib.scala 245:14] - node _T_291 = cat(_T_48[21], _T_48[20]) @[el2_lib.scala 245:14] - node _T_292 = cat(_T_48[23], _T_48[22]) @[el2_lib.scala 245:14] - node _T_293 = cat(_T_292, _T_291) @[el2_lib.scala 245:14] - node _T_294 = cat(_T_293, _T_290) @[el2_lib.scala 245:14] - node _T_295 = cat(_T_48[25], _T_48[24]) @[el2_lib.scala 245:14] - node _T_296 = cat(_T_48[27], _T_48[26]) @[el2_lib.scala 245:14] - node _T_297 = cat(_T_296, _T_295) @[el2_lib.scala 245:14] - node _T_298 = cat(_T_48[29], _T_48[28]) @[el2_lib.scala 245:14] - node _T_299 = cat(_T_48[31], _T_48[30]) @[el2_lib.scala 245:14] - node _T_300 = cat(_T_299, _T_298) @[el2_lib.scala 245:14] - node _T_301 = cat(_T_300, _T_297) @[el2_lib.scala 245:14] - node _T_302 = cat(_T_301, _T_294) @[el2_lib.scala 245:14] - node _T_303 = cat(_T_302, _T_287) @[el2_lib.scala 245:14] - node _T_304 = andr(_T_303) @[el2_lib.scala 245:25] + wire _T_48 : UInt<1>[32] @[lib.scala 100:24] + node _T_49 = andr(io.trigger_pkt_any[0].tdata2) @[lib.scala 101:45] + node _T_50 = not(_T_49) @[lib.scala 101:39] + node _T_51 = and(_T_47, _T_50) @[lib.scala 101:37] + node _T_52 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[lib.scala 102:48] + node _T_53 = bits(lsu_match_data_0, 0, 0) @[lib.scala 102:60] + node _T_54 = eq(_T_52, _T_53) @[lib.scala 102:52] + node _T_55 = or(_T_51, _T_54) @[lib.scala 102:41] + _T_48[0] <= _T_55 @[lib.scala 102:18] + node _T_56 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[lib.scala 104:28] + node _T_57 = andr(_T_56) @[lib.scala 104:36] + node _T_58 = and(_T_57, _T_51) @[lib.scala 104:41] + node _T_59 = bits(io.trigger_pkt_any[0].tdata2, 1, 1) @[lib.scala 104:74] + node _T_60 = bits(lsu_match_data_0, 1, 1) @[lib.scala 104:86] + node _T_61 = eq(_T_59, _T_60) @[lib.scala 104:78] + node _T_62 = mux(_T_58, UInt<1>("h01"), _T_61) @[lib.scala 104:23] + _T_48[1] <= _T_62 @[lib.scala 104:17] + node _T_63 = bits(io.trigger_pkt_any[0].tdata2, 1, 0) @[lib.scala 104:28] + node _T_64 = andr(_T_63) @[lib.scala 104:36] + node _T_65 = and(_T_64, _T_51) @[lib.scala 104:41] + node _T_66 = bits(io.trigger_pkt_any[0].tdata2, 2, 2) @[lib.scala 104:74] + node _T_67 = bits(lsu_match_data_0, 2, 2) @[lib.scala 104:86] + node _T_68 = eq(_T_66, _T_67) @[lib.scala 104:78] + node _T_69 = mux(_T_65, UInt<1>("h01"), _T_68) @[lib.scala 104:23] + _T_48[2] <= _T_69 @[lib.scala 104:17] + node _T_70 = bits(io.trigger_pkt_any[0].tdata2, 2, 0) @[lib.scala 104:28] + node _T_71 = andr(_T_70) @[lib.scala 104:36] + node _T_72 = and(_T_71, _T_51) @[lib.scala 104:41] + node _T_73 = bits(io.trigger_pkt_any[0].tdata2, 3, 3) @[lib.scala 104:74] + node _T_74 = bits(lsu_match_data_0, 3, 3) @[lib.scala 104:86] + node _T_75 = eq(_T_73, _T_74) @[lib.scala 104:78] + node _T_76 = mux(_T_72, UInt<1>("h01"), _T_75) @[lib.scala 104:23] + _T_48[3] <= _T_76 @[lib.scala 104:17] + node _T_77 = bits(io.trigger_pkt_any[0].tdata2, 3, 0) @[lib.scala 104:28] + node _T_78 = andr(_T_77) @[lib.scala 104:36] + node _T_79 = and(_T_78, _T_51) @[lib.scala 104:41] + node _T_80 = bits(io.trigger_pkt_any[0].tdata2, 4, 4) @[lib.scala 104:74] + node _T_81 = bits(lsu_match_data_0, 4, 4) @[lib.scala 104:86] + node _T_82 = eq(_T_80, _T_81) @[lib.scala 104:78] + node _T_83 = mux(_T_79, UInt<1>("h01"), _T_82) @[lib.scala 104:23] + _T_48[4] <= _T_83 @[lib.scala 104:17] + node _T_84 = bits(io.trigger_pkt_any[0].tdata2, 4, 0) @[lib.scala 104:28] + node _T_85 = andr(_T_84) @[lib.scala 104:36] + node _T_86 = and(_T_85, _T_51) @[lib.scala 104:41] + node _T_87 = bits(io.trigger_pkt_any[0].tdata2, 5, 5) @[lib.scala 104:74] + node _T_88 = bits(lsu_match_data_0, 5, 5) @[lib.scala 104:86] + node _T_89 = eq(_T_87, _T_88) @[lib.scala 104:78] + node _T_90 = mux(_T_86, UInt<1>("h01"), _T_89) @[lib.scala 104:23] + _T_48[5] <= _T_90 @[lib.scala 104:17] + node _T_91 = bits(io.trigger_pkt_any[0].tdata2, 5, 0) @[lib.scala 104:28] + node _T_92 = andr(_T_91) @[lib.scala 104:36] + node _T_93 = and(_T_92, _T_51) @[lib.scala 104:41] + node _T_94 = bits(io.trigger_pkt_any[0].tdata2, 6, 6) @[lib.scala 104:74] + node _T_95 = bits(lsu_match_data_0, 6, 6) @[lib.scala 104:86] + node _T_96 = eq(_T_94, _T_95) @[lib.scala 104:78] + node _T_97 = mux(_T_93, UInt<1>("h01"), _T_96) @[lib.scala 104:23] + _T_48[6] <= _T_97 @[lib.scala 104:17] + node _T_98 = bits(io.trigger_pkt_any[0].tdata2, 6, 0) @[lib.scala 104:28] + node _T_99 = andr(_T_98) @[lib.scala 104:36] + node _T_100 = and(_T_99, _T_51) @[lib.scala 104:41] + node _T_101 = bits(io.trigger_pkt_any[0].tdata2, 7, 7) @[lib.scala 104:74] + node _T_102 = bits(lsu_match_data_0, 7, 7) @[lib.scala 104:86] + node _T_103 = eq(_T_101, _T_102) @[lib.scala 104:78] + node _T_104 = mux(_T_100, UInt<1>("h01"), _T_103) @[lib.scala 104:23] + _T_48[7] <= _T_104 @[lib.scala 104:17] + node _T_105 = bits(io.trigger_pkt_any[0].tdata2, 7, 0) @[lib.scala 104:28] + node _T_106 = andr(_T_105) @[lib.scala 104:36] + node _T_107 = and(_T_106, _T_51) @[lib.scala 104:41] + node _T_108 = bits(io.trigger_pkt_any[0].tdata2, 8, 8) @[lib.scala 104:74] + node _T_109 = bits(lsu_match_data_0, 8, 8) @[lib.scala 104:86] + node _T_110 = eq(_T_108, _T_109) @[lib.scala 104:78] + node _T_111 = mux(_T_107, UInt<1>("h01"), _T_110) @[lib.scala 104:23] + _T_48[8] <= _T_111 @[lib.scala 104:17] + node _T_112 = bits(io.trigger_pkt_any[0].tdata2, 8, 0) @[lib.scala 104:28] + node _T_113 = andr(_T_112) @[lib.scala 104:36] + node _T_114 = and(_T_113, _T_51) @[lib.scala 104:41] + node _T_115 = bits(io.trigger_pkt_any[0].tdata2, 9, 9) @[lib.scala 104:74] + node _T_116 = bits(lsu_match_data_0, 9, 9) @[lib.scala 104:86] + node _T_117 = eq(_T_115, _T_116) @[lib.scala 104:78] + node _T_118 = mux(_T_114, UInt<1>("h01"), _T_117) @[lib.scala 104:23] + _T_48[9] <= _T_118 @[lib.scala 104:17] + node _T_119 = bits(io.trigger_pkt_any[0].tdata2, 9, 0) @[lib.scala 104:28] + node _T_120 = andr(_T_119) @[lib.scala 104:36] + node _T_121 = and(_T_120, _T_51) @[lib.scala 104:41] + node _T_122 = bits(io.trigger_pkt_any[0].tdata2, 10, 10) @[lib.scala 104:74] + node _T_123 = bits(lsu_match_data_0, 10, 10) @[lib.scala 104:86] + node _T_124 = eq(_T_122, _T_123) @[lib.scala 104:78] + node _T_125 = mux(_T_121, UInt<1>("h01"), _T_124) @[lib.scala 104:23] + _T_48[10] <= _T_125 @[lib.scala 104:17] + node _T_126 = bits(io.trigger_pkt_any[0].tdata2, 10, 0) @[lib.scala 104:28] + node _T_127 = andr(_T_126) @[lib.scala 104:36] + node _T_128 = and(_T_127, _T_51) @[lib.scala 104:41] + node _T_129 = bits(io.trigger_pkt_any[0].tdata2, 11, 11) @[lib.scala 104:74] + node _T_130 = bits(lsu_match_data_0, 11, 11) @[lib.scala 104:86] + node _T_131 = eq(_T_129, _T_130) @[lib.scala 104:78] + node _T_132 = mux(_T_128, UInt<1>("h01"), _T_131) @[lib.scala 104:23] + _T_48[11] <= _T_132 @[lib.scala 104:17] + node _T_133 = bits(io.trigger_pkt_any[0].tdata2, 11, 0) @[lib.scala 104:28] + node _T_134 = andr(_T_133) @[lib.scala 104:36] + node _T_135 = and(_T_134, _T_51) @[lib.scala 104:41] + node _T_136 = bits(io.trigger_pkt_any[0].tdata2, 12, 12) @[lib.scala 104:74] + node _T_137 = bits(lsu_match_data_0, 12, 12) @[lib.scala 104:86] + node _T_138 = eq(_T_136, _T_137) @[lib.scala 104:78] + node _T_139 = mux(_T_135, UInt<1>("h01"), _T_138) @[lib.scala 104:23] + _T_48[12] <= _T_139 @[lib.scala 104:17] + node _T_140 = bits(io.trigger_pkt_any[0].tdata2, 12, 0) @[lib.scala 104:28] + node _T_141 = andr(_T_140) @[lib.scala 104:36] + node _T_142 = and(_T_141, _T_51) @[lib.scala 104:41] + node _T_143 = bits(io.trigger_pkt_any[0].tdata2, 13, 13) @[lib.scala 104:74] + node _T_144 = bits(lsu_match_data_0, 13, 13) @[lib.scala 104:86] + node _T_145 = eq(_T_143, _T_144) @[lib.scala 104:78] + node _T_146 = mux(_T_142, UInt<1>("h01"), _T_145) @[lib.scala 104:23] + _T_48[13] <= _T_146 @[lib.scala 104:17] + node _T_147 = bits(io.trigger_pkt_any[0].tdata2, 13, 0) @[lib.scala 104:28] + node _T_148 = andr(_T_147) @[lib.scala 104:36] + node _T_149 = and(_T_148, _T_51) @[lib.scala 104:41] + node _T_150 = bits(io.trigger_pkt_any[0].tdata2, 14, 14) @[lib.scala 104:74] + node _T_151 = bits(lsu_match_data_0, 14, 14) @[lib.scala 104:86] + node _T_152 = eq(_T_150, _T_151) @[lib.scala 104:78] + node _T_153 = mux(_T_149, UInt<1>("h01"), _T_152) @[lib.scala 104:23] + _T_48[14] <= _T_153 @[lib.scala 104:17] + node _T_154 = bits(io.trigger_pkt_any[0].tdata2, 14, 0) @[lib.scala 104:28] + node _T_155 = andr(_T_154) @[lib.scala 104:36] + node _T_156 = and(_T_155, _T_51) @[lib.scala 104:41] + node _T_157 = bits(io.trigger_pkt_any[0].tdata2, 15, 15) @[lib.scala 104:74] + node _T_158 = bits(lsu_match_data_0, 15, 15) @[lib.scala 104:86] + node _T_159 = eq(_T_157, _T_158) @[lib.scala 104:78] + node _T_160 = mux(_T_156, UInt<1>("h01"), _T_159) @[lib.scala 104:23] + _T_48[15] <= _T_160 @[lib.scala 104:17] + node _T_161 = bits(io.trigger_pkt_any[0].tdata2, 15, 0) @[lib.scala 104:28] + node _T_162 = andr(_T_161) @[lib.scala 104:36] + node _T_163 = and(_T_162, _T_51) @[lib.scala 104:41] + node _T_164 = bits(io.trigger_pkt_any[0].tdata2, 16, 16) @[lib.scala 104:74] + node _T_165 = bits(lsu_match_data_0, 16, 16) @[lib.scala 104:86] + node _T_166 = eq(_T_164, _T_165) @[lib.scala 104:78] + node _T_167 = mux(_T_163, UInt<1>("h01"), _T_166) @[lib.scala 104:23] + _T_48[16] <= _T_167 @[lib.scala 104:17] + node _T_168 = bits(io.trigger_pkt_any[0].tdata2, 16, 0) @[lib.scala 104:28] + node _T_169 = andr(_T_168) @[lib.scala 104:36] + node _T_170 = and(_T_169, _T_51) @[lib.scala 104:41] + node _T_171 = bits(io.trigger_pkt_any[0].tdata2, 17, 17) @[lib.scala 104:74] + node _T_172 = bits(lsu_match_data_0, 17, 17) @[lib.scala 104:86] + node _T_173 = eq(_T_171, _T_172) @[lib.scala 104:78] + node _T_174 = mux(_T_170, UInt<1>("h01"), _T_173) @[lib.scala 104:23] + _T_48[17] <= _T_174 @[lib.scala 104:17] + node _T_175 = bits(io.trigger_pkt_any[0].tdata2, 17, 0) @[lib.scala 104:28] + node _T_176 = andr(_T_175) @[lib.scala 104:36] + node _T_177 = and(_T_176, _T_51) @[lib.scala 104:41] + node _T_178 = bits(io.trigger_pkt_any[0].tdata2, 18, 18) @[lib.scala 104:74] + node _T_179 = bits(lsu_match_data_0, 18, 18) @[lib.scala 104:86] + node _T_180 = eq(_T_178, _T_179) @[lib.scala 104:78] + node _T_181 = mux(_T_177, UInt<1>("h01"), _T_180) @[lib.scala 104:23] + _T_48[18] <= _T_181 @[lib.scala 104:17] + node _T_182 = bits(io.trigger_pkt_any[0].tdata2, 18, 0) @[lib.scala 104:28] + node _T_183 = andr(_T_182) @[lib.scala 104:36] + node _T_184 = and(_T_183, _T_51) @[lib.scala 104:41] + node _T_185 = bits(io.trigger_pkt_any[0].tdata2, 19, 19) @[lib.scala 104:74] + node _T_186 = bits(lsu_match_data_0, 19, 19) @[lib.scala 104:86] + node _T_187 = eq(_T_185, _T_186) @[lib.scala 104:78] + node _T_188 = mux(_T_184, UInt<1>("h01"), _T_187) @[lib.scala 104:23] + _T_48[19] <= _T_188 @[lib.scala 104:17] + node _T_189 = bits(io.trigger_pkt_any[0].tdata2, 19, 0) @[lib.scala 104:28] + node _T_190 = andr(_T_189) @[lib.scala 104:36] + node _T_191 = and(_T_190, _T_51) @[lib.scala 104:41] + node _T_192 = bits(io.trigger_pkt_any[0].tdata2, 20, 20) @[lib.scala 104:74] + node _T_193 = bits(lsu_match_data_0, 20, 20) @[lib.scala 104:86] + node _T_194 = eq(_T_192, _T_193) @[lib.scala 104:78] + node _T_195 = mux(_T_191, UInt<1>("h01"), _T_194) @[lib.scala 104:23] + _T_48[20] <= _T_195 @[lib.scala 104:17] + node _T_196 = bits(io.trigger_pkt_any[0].tdata2, 20, 0) @[lib.scala 104:28] + node _T_197 = andr(_T_196) @[lib.scala 104:36] + node _T_198 = and(_T_197, _T_51) @[lib.scala 104:41] + node _T_199 = bits(io.trigger_pkt_any[0].tdata2, 21, 21) @[lib.scala 104:74] + node _T_200 = bits(lsu_match_data_0, 21, 21) @[lib.scala 104:86] + node _T_201 = eq(_T_199, _T_200) @[lib.scala 104:78] + node _T_202 = mux(_T_198, UInt<1>("h01"), _T_201) @[lib.scala 104:23] + _T_48[21] <= _T_202 @[lib.scala 104:17] + node _T_203 = bits(io.trigger_pkt_any[0].tdata2, 21, 0) @[lib.scala 104:28] + node _T_204 = andr(_T_203) @[lib.scala 104:36] + node _T_205 = and(_T_204, _T_51) @[lib.scala 104:41] + node _T_206 = bits(io.trigger_pkt_any[0].tdata2, 22, 22) @[lib.scala 104:74] + node _T_207 = bits(lsu_match_data_0, 22, 22) @[lib.scala 104:86] + node _T_208 = eq(_T_206, _T_207) @[lib.scala 104:78] + node _T_209 = mux(_T_205, UInt<1>("h01"), _T_208) @[lib.scala 104:23] + _T_48[22] <= _T_209 @[lib.scala 104:17] + node _T_210 = bits(io.trigger_pkt_any[0].tdata2, 22, 0) @[lib.scala 104:28] + node _T_211 = andr(_T_210) @[lib.scala 104:36] + node _T_212 = and(_T_211, _T_51) @[lib.scala 104:41] + node _T_213 = bits(io.trigger_pkt_any[0].tdata2, 23, 23) @[lib.scala 104:74] + node _T_214 = bits(lsu_match_data_0, 23, 23) @[lib.scala 104:86] + node _T_215 = eq(_T_213, _T_214) @[lib.scala 104:78] + node _T_216 = mux(_T_212, UInt<1>("h01"), _T_215) @[lib.scala 104:23] + _T_48[23] <= _T_216 @[lib.scala 104:17] + node _T_217 = bits(io.trigger_pkt_any[0].tdata2, 23, 0) @[lib.scala 104:28] + node _T_218 = andr(_T_217) @[lib.scala 104:36] + node _T_219 = and(_T_218, _T_51) @[lib.scala 104:41] + node _T_220 = bits(io.trigger_pkt_any[0].tdata2, 24, 24) @[lib.scala 104:74] + node _T_221 = bits(lsu_match_data_0, 24, 24) @[lib.scala 104:86] + node _T_222 = eq(_T_220, _T_221) @[lib.scala 104:78] + node _T_223 = mux(_T_219, UInt<1>("h01"), _T_222) @[lib.scala 104:23] + _T_48[24] <= _T_223 @[lib.scala 104:17] + node _T_224 = bits(io.trigger_pkt_any[0].tdata2, 24, 0) @[lib.scala 104:28] + node _T_225 = andr(_T_224) @[lib.scala 104:36] + node _T_226 = and(_T_225, _T_51) @[lib.scala 104:41] + node _T_227 = bits(io.trigger_pkt_any[0].tdata2, 25, 25) @[lib.scala 104:74] + node _T_228 = bits(lsu_match_data_0, 25, 25) @[lib.scala 104:86] + node _T_229 = eq(_T_227, _T_228) @[lib.scala 104:78] + node _T_230 = mux(_T_226, UInt<1>("h01"), _T_229) @[lib.scala 104:23] + _T_48[25] <= _T_230 @[lib.scala 104:17] + node _T_231 = bits(io.trigger_pkt_any[0].tdata2, 25, 0) @[lib.scala 104:28] + node _T_232 = andr(_T_231) @[lib.scala 104:36] + node _T_233 = and(_T_232, _T_51) @[lib.scala 104:41] + node _T_234 = bits(io.trigger_pkt_any[0].tdata2, 26, 26) @[lib.scala 104:74] + node _T_235 = bits(lsu_match_data_0, 26, 26) @[lib.scala 104:86] + node _T_236 = eq(_T_234, _T_235) @[lib.scala 104:78] + node _T_237 = mux(_T_233, UInt<1>("h01"), _T_236) @[lib.scala 104:23] + _T_48[26] <= _T_237 @[lib.scala 104:17] + node _T_238 = bits(io.trigger_pkt_any[0].tdata2, 26, 0) @[lib.scala 104:28] + node _T_239 = andr(_T_238) @[lib.scala 104:36] + node _T_240 = and(_T_239, _T_51) @[lib.scala 104:41] + node _T_241 = bits(io.trigger_pkt_any[0].tdata2, 27, 27) @[lib.scala 104:74] + node _T_242 = bits(lsu_match_data_0, 27, 27) @[lib.scala 104:86] + node _T_243 = eq(_T_241, _T_242) @[lib.scala 104:78] + node _T_244 = mux(_T_240, UInt<1>("h01"), _T_243) @[lib.scala 104:23] + _T_48[27] <= _T_244 @[lib.scala 104:17] + node _T_245 = bits(io.trigger_pkt_any[0].tdata2, 27, 0) @[lib.scala 104:28] + node _T_246 = andr(_T_245) @[lib.scala 104:36] + node _T_247 = and(_T_246, _T_51) @[lib.scala 104:41] + node _T_248 = bits(io.trigger_pkt_any[0].tdata2, 28, 28) @[lib.scala 104:74] + node _T_249 = bits(lsu_match_data_0, 28, 28) @[lib.scala 104:86] + node _T_250 = eq(_T_248, _T_249) @[lib.scala 104:78] + node _T_251 = mux(_T_247, UInt<1>("h01"), _T_250) @[lib.scala 104:23] + _T_48[28] <= _T_251 @[lib.scala 104:17] + node _T_252 = bits(io.trigger_pkt_any[0].tdata2, 28, 0) @[lib.scala 104:28] + node _T_253 = andr(_T_252) @[lib.scala 104:36] + node _T_254 = and(_T_253, _T_51) @[lib.scala 104:41] + node _T_255 = bits(io.trigger_pkt_any[0].tdata2, 29, 29) @[lib.scala 104:74] + node _T_256 = bits(lsu_match_data_0, 29, 29) @[lib.scala 104:86] + node _T_257 = eq(_T_255, _T_256) @[lib.scala 104:78] + node _T_258 = mux(_T_254, UInt<1>("h01"), _T_257) @[lib.scala 104:23] + _T_48[29] <= _T_258 @[lib.scala 104:17] + node _T_259 = bits(io.trigger_pkt_any[0].tdata2, 29, 0) @[lib.scala 104:28] + node _T_260 = andr(_T_259) @[lib.scala 104:36] + node _T_261 = and(_T_260, _T_51) @[lib.scala 104:41] + node _T_262 = bits(io.trigger_pkt_any[0].tdata2, 30, 30) @[lib.scala 104:74] + node _T_263 = bits(lsu_match_data_0, 30, 30) @[lib.scala 104:86] + node _T_264 = eq(_T_262, _T_263) @[lib.scala 104:78] + node _T_265 = mux(_T_261, UInt<1>("h01"), _T_264) @[lib.scala 104:23] + _T_48[30] <= _T_265 @[lib.scala 104:17] + node _T_266 = bits(io.trigger_pkt_any[0].tdata2, 30, 0) @[lib.scala 104:28] + node _T_267 = andr(_T_266) @[lib.scala 104:36] + node _T_268 = and(_T_267, _T_51) @[lib.scala 104:41] + node _T_269 = bits(io.trigger_pkt_any[0].tdata2, 31, 31) @[lib.scala 104:74] + node _T_270 = bits(lsu_match_data_0, 31, 31) @[lib.scala 104:86] + node _T_271 = eq(_T_269, _T_270) @[lib.scala 104:78] + node _T_272 = mux(_T_268, UInt<1>("h01"), _T_271) @[lib.scala 104:23] + _T_48[31] <= _T_272 @[lib.scala 104:17] + node _T_273 = cat(_T_48[1], _T_48[0]) @[lib.scala 105:14] + node _T_274 = cat(_T_48[3], _T_48[2]) @[lib.scala 105:14] + node _T_275 = cat(_T_274, _T_273) @[lib.scala 105:14] + node _T_276 = cat(_T_48[5], _T_48[4]) @[lib.scala 105:14] + node _T_277 = cat(_T_48[7], _T_48[6]) @[lib.scala 105:14] + node _T_278 = cat(_T_277, _T_276) @[lib.scala 105:14] + node _T_279 = cat(_T_278, _T_275) @[lib.scala 105:14] + node _T_280 = cat(_T_48[9], _T_48[8]) @[lib.scala 105:14] + node _T_281 = cat(_T_48[11], _T_48[10]) @[lib.scala 105:14] + node _T_282 = cat(_T_281, _T_280) @[lib.scala 105:14] + node _T_283 = cat(_T_48[13], _T_48[12]) @[lib.scala 105:14] + node _T_284 = cat(_T_48[15], _T_48[14]) @[lib.scala 105:14] + node _T_285 = cat(_T_284, _T_283) @[lib.scala 105:14] + node _T_286 = cat(_T_285, _T_282) @[lib.scala 105:14] + node _T_287 = cat(_T_286, _T_279) @[lib.scala 105:14] + node _T_288 = cat(_T_48[17], _T_48[16]) @[lib.scala 105:14] + node _T_289 = cat(_T_48[19], _T_48[18]) @[lib.scala 105:14] + node _T_290 = cat(_T_289, _T_288) @[lib.scala 105:14] + node _T_291 = cat(_T_48[21], _T_48[20]) @[lib.scala 105:14] + node _T_292 = cat(_T_48[23], _T_48[22]) @[lib.scala 105:14] + node _T_293 = cat(_T_292, _T_291) @[lib.scala 105:14] + node _T_294 = cat(_T_293, _T_290) @[lib.scala 105:14] + node _T_295 = cat(_T_48[25], _T_48[24]) @[lib.scala 105:14] + node _T_296 = cat(_T_48[27], _T_48[26]) @[lib.scala 105:14] + node _T_297 = cat(_T_296, _T_295) @[lib.scala 105:14] + node _T_298 = cat(_T_48[29], _T_48[28]) @[lib.scala 105:14] + node _T_299 = cat(_T_48[31], _T_48[30]) @[lib.scala 105:14] + node _T_300 = cat(_T_299, _T_298) @[lib.scala 105:14] + node _T_301 = cat(_T_300, _T_297) @[lib.scala 105:14] + node _T_302 = cat(_T_301, _T_294) @[lib.scala 105:14] + node _T_303 = cat(_T_302, _T_287) @[lib.scala 105:14] + node _T_304 = andr(_T_303) @[lib.scala 105:25] node _T_305 = and(_T_46, _T_304) @[lsu_trigger.scala 19:92] node _T_306 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_trigger.scala 18:71] node _T_307 = and(io.lsu_pkt_m.valid, _T_306) @[lsu_trigger.scala 18:69] @@ -93321,295 +93313,295 @@ circuit quasar_wrapper : node _T_312 = or(_T_308, _T_311) @[lsu_trigger.scala 18:152] node _T_313 = and(_T_307, _T_312) @[lsu_trigger.scala 18:94] node _T_314 = bits(io.trigger_pkt_any[1].match_pkt, 0, 0) @[lsu_trigger.scala 20:107] - wire _T_315 : UInt<1>[32] @[el2_lib.scala 240:24] - node _T_316 = andr(io.trigger_pkt_any[1].tdata2) @[el2_lib.scala 241:45] - node _T_317 = not(_T_316) @[el2_lib.scala 241:39] - node _T_318 = and(_T_314, _T_317) @[el2_lib.scala 241:37] - node _T_319 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[el2_lib.scala 242:48] - node _T_320 = bits(lsu_match_data_1, 0, 0) @[el2_lib.scala 242:60] - node _T_321 = eq(_T_319, _T_320) @[el2_lib.scala 242:52] - node _T_322 = or(_T_318, _T_321) @[el2_lib.scala 242:41] - _T_315[0] <= _T_322 @[el2_lib.scala 242:18] - node _T_323 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[el2_lib.scala 244:28] - node _T_324 = andr(_T_323) @[el2_lib.scala 244:36] - node _T_325 = and(_T_324, _T_318) @[el2_lib.scala 244:41] - node _T_326 = bits(io.trigger_pkt_any[1].tdata2, 1, 1) @[el2_lib.scala 244:74] - node _T_327 = bits(lsu_match_data_1, 1, 1) @[el2_lib.scala 244:86] - node _T_328 = eq(_T_326, _T_327) @[el2_lib.scala 244:78] - node _T_329 = mux(_T_325, UInt<1>("h01"), _T_328) @[el2_lib.scala 244:23] - _T_315[1] <= _T_329 @[el2_lib.scala 244:17] - node _T_330 = bits(io.trigger_pkt_any[1].tdata2, 1, 0) @[el2_lib.scala 244:28] - node _T_331 = andr(_T_330) @[el2_lib.scala 244:36] - node _T_332 = and(_T_331, _T_318) @[el2_lib.scala 244:41] - node _T_333 = bits(io.trigger_pkt_any[1].tdata2, 2, 2) @[el2_lib.scala 244:74] - node _T_334 = bits(lsu_match_data_1, 2, 2) @[el2_lib.scala 244:86] - node _T_335 = eq(_T_333, _T_334) @[el2_lib.scala 244:78] - node _T_336 = mux(_T_332, UInt<1>("h01"), _T_335) @[el2_lib.scala 244:23] - _T_315[2] <= _T_336 @[el2_lib.scala 244:17] - node _T_337 = bits(io.trigger_pkt_any[1].tdata2, 2, 0) @[el2_lib.scala 244:28] - node _T_338 = andr(_T_337) @[el2_lib.scala 244:36] - node _T_339 = and(_T_338, _T_318) @[el2_lib.scala 244:41] - node _T_340 = bits(io.trigger_pkt_any[1].tdata2, 3, 3) @[el2_lib.scala 244:74] - node _T_341 = bits(lsu_match_data_1, 3, 3) @[el2_lib.scala 244:86] - node _T_342 = eq(_T_340, _T_341) @[el2_lib.scala 244:78] - node _T_343 = mux(_T_339, UInt<1>("h01"), _T_342) @[el2_lib.scala 244:23] - _T_315[3] <= _T_343 @[el2_lib.scala 244:17] - node _T_344 = bits(io.trigger_pkt_any[1].tdata2, 3, 0) @[el2_lib.scala 244:28] - node _T_345 = andr(_T_344) @[el2_lib.scala 244:36] - node _T_346 = and(_T_345, _T_318) @[el2_lib.scala 244:41] - node _T_347 = bits(io.trigger_pkt_any[1].tdata2, 4, 4) @[el2_lib.scala 244:74] - node _T_348 = bits(lsu_match_data_1, 4, 4) @[el2_lib.scala 244:86] - node _T_349 = eq(_T_347, _T_348) @[el2_lib.scala 244:78] - node _T_350 = mux(_T_346, UInt<1>("h01"), _T_349) @[el2_lib.scala 244:23] - _T_315[4] <= _T_350 @[el2_lib.scala 244:17] - node _T_351 = bits(io.trigger_pkt_any[1].tdata2, 4, 0) @[el2_lib.scala 244:28] - node _T_352 = andr(_T_351) @[el2_lib.scala 244:36] - node _T_353 = and(_T_352, _T_318) @[el2_lib.scala 244:41] - node _T_354 = bits(io.trigger_pkt_any[1].tdata2, 5, 5) @[el2_lib.scala 244:74] - node _T_355 = bits(lsu_match_data_1, 5, 5) @[el2_lib.scala 244:86] - node _T_356 = eq(_T_354, _T_355) @[el2_lib.scala 244:78] - node _T_357 = mux(_T_353, UInt<1>("h01"), _T_356) @[el2_lib.scala 244:23] - _T_315[5] <= _T_357 @[el2_lib.scala 244:17] - node _T_358 = bits(io.trigger_pkt_any[1].tdata2, 5, 0) @[el2_lib.scala 244:28] - node _T_359 = andr(_T_358) @[el2_lib.scala 244:36] - node _T_360 = and(_T_359, _T_318) @[el2_lib.scala 244:41] - node _T_361 = bits(io.trigger_pkt_any[1].tdata2, 6, 6) @[el2_lib.scala 244:74] - node _T_362 = bits(lsu_match_data_1, 6, 6) @[el2_lib.scala 244:86] - node _T_363 = eq(_T_361, _T_362) @[el2_lib.scala 244:78] - node _T_364 = mux(_T_360, UInt<1>("h01"), _T_363) @[el2_lib.scala 244:23] - _T_315[6] <= _T_364 @[el2_lib.scala 244:17] - node _T_365 = bits(io.trigger_pkt_any[1].tdata2, 6, 0) @[el2_lib.scala 244:28] - node _T_366 = andr(_T_365) @[el2_lib.scala 244:36] - node _T_367 = and(_T_366, _T_318) @[el2_lib.scala 244:41] - node _T_368 = bits(io.trigger_pkt_any[1].tdata2, 7, 7) @[el2_lib.scala 244:74] - node _T_369 = bits(lsu_match_data_1, 7, 7) @[el2_lib.scala 244:86] - node _T_370 = eq(_T_368, _T_369) @[el2_lib.scala 244:78] - node _T_371 = mux(_T_367, UInt<1>("h01"), _T_370) @[el2_lib.scala 244:23] - _T_315[7] <= _T_371 @[el2_lib.scala 244:17] - node _T_372 = bits(io.trigger_pkt_any[1].tdata2, 7, 0) @[el2_lib.scala 244:28] - node _T_373 = andr(_T_372) @[el2_lib.scala 244:36] - node _T_374 = and(_T_373, _T_318) @[el2_lib.scala 244:41] - node _T_375 = bits(io.trigger_pkt_any[1].tdata2, 8, 8) @[el2_lib.scala 244:74] - node _T_376 = bits(lsu_match_data_1, 8, 8) @[el2_lib.scala 244:86] - node _T_377 = eq(_T_375, _T_376) @[el2_lib.scala 244:78] - node _T_378 = mux(_T_374, UInt<1>("h01"), _T_377) @[el2_lib.scala 244:23] - _T_315[8] <= _T_378 @[el2_lib.scala 244:17] - node _T_379 = bits(io.trigger_pkt_any[1].tdata2, 8, 0) @[el2_lib.scala 244:28] - node _T_380 = andr(_T_379) @[el2_lib.scala 244:36] - node _T_381 = and(_T_380, _T_318) @[el2_lib.scala 244:41] - node _T_382 = bits(io.trigger_pkt_any[1].tdata2, 9, 9) @[el2_lib.scala 244:74] - node _T_383 = bits(lsu_match_data_1, 9, 9) @[el2_lib.scala 244:86] - node _T_384 = eq(_T_382, _T_383) @[el2_lib.scala 244:78] - node _T_385 = mux(_T_381, UInt<1>("h01"), _T_384) @[el2_lib.scala 244:23] - _T_315[9] <= _T_385 @[el2_lib.scala 244:17] - node _T_386 = bits(io.trigger_pkt_any[1].tdata2, 9, 0) @[el2_lib.scala 244:28] - node _T_387 = andr(_T_386) @[el2_lib.scala 244:36] - node _T_388 = and(_T_387, _T_318) @[el2_lib.scala 244:41] - node _T_389 = bits(io.trigger_pkt_any[1].tdata2, 10, 10) @[el2_lib.scala 244:74] - node _T_390 = bits(lsu_match_data_1, 10, 10) @[el2_lib.scala 244:86] - node _T_391 = eq(_T_389, _T_390) @[el2_lib.scala 244:78] - node _T_392 = mux(_T_388, UInt<1>("h01"), _T_391) @[el2_lib.scala 244:23] - _T_315[10] <= _T_392 @[el2_lib.scala 244:17] - node _T_393 = bits(io.trigger_pkt_any[1].tdata2, 10, 0) @[el2_lib.scala 244:28] - node _T_394 = andr(_T_393) @[el2_lib.scala 244:36] - node _T_395 = and(_T_394, _T_318) @[el2_lib.scala 244:41] - node _T_396 = bits(io.trigger_pkt_any[1].tdata2, 11, 11) @[el2_lib.scala 244:74] - node _T_397 = bits(lsu_match_data_1, 11, 11) @[el2_lib.scala 244:86] - node _T_398 = eq(_T_396, _T_397) @[el2_lib.scala 244:78] - node _T_399 = mux(_T_395, UInt<1>("h01"), _T_398) @[el2_lib.scala 244:23] - _T_315[11] <= _T_399 @[el2_lib.scala 244:17] - node _T_400 = bits(io.trigger_pkt_any[1].tdata2, 11, 0) @[el2_lib.scala 244:28] - node _T_401 = andr(_T_400) @[el2_lib.scala 244:36] - node _T_402 = and(_T_401, _T_318) @[el2_lib.scala 244:41] - node _T_403 = bits(io.trigger_pkt_any[1].tdata2, 12, 12) @[el2_lib.scala 244:74] - node _T_404 = bits(lsu_match_data_1, 12, 12) @[el2_lib.scala 244:86] - node _T_405 = eq(_T_403, _T_404) @[el2_lib.scala 244:78] - node _T_406 = mux(_T_402, UInt<1>("h01"), _T_405) @[el2_lib.scala 244:23] - _T_315[12] <= _T_406 @[el2_lib.scala 244:17] - node _T_407 = bits(io.trigger_pkt_any[1].tdata2, 12, 0) @[el2_lib.scala 244:28] - node _T_408 = andr(_T_407) @[el2_lib.scala 244:36] - node _T_409 = and(_T_408, _T_318) @[el2_lib.scala 244:41] - node _T_410 = bits(io.trigger_pkt_any[1].tdata2, 13, 13) @[el2_lib.scala 244:74] - node _T_411 = bits(lsu_match_data_1, 13, 13) @[el2_lib.scala 244:86] - node _T_412 = eq(_T_410, _T_411) @[el2_lib.scala 244:78] - node _T_413 = mux(_T_409, UInt<1>("h01"), _T_412) @[el2_lib.scala 244:23] - _T_315[13] <= _T_413 @[el2_lib.scala 244:17] - node _T_414 = bits(io.trigger_pkt_any[1].tdata2, 13, 0) @[el2_lib.scala 244:28] - node _T_415 = andr(_T_414) @[el2_lib.scala 244:36] - node _T_416 = and(_T_415, _T_318) @[el2_lib.scala 244:41] - node _T_417 = bits(io.trigger_pkt_any[1].tdata2, 14, 14) @[el2_lib.scala 244:74] - node _T_418 = bits(lsu_match_data_1, 14, 14) @[el2_lib.scala 244:86] - node _T_419 = eq(_T_417, _T_418) @[el2_lib.scala 244:78] - node _T_420 = mux(_T_416, UInt<1>("h01"), _T_419) @[el2_lib.scala 244:23] - _T_315[14] <= _T_420 @[el2_lib.scala 244:17] - node _T_421 = bits(io.trigger_pkt_any[1].tdata2, 14, 0) @[el2_lib.scala 244:28] - node _T_422 = andr(_T_421) @[el2_lib.scala 244:36] - node _T_423 = and(_T_422, _T_318) @[el2_lib.scala 244:41] - node _T_424 = bits(io.trigger_pkt_any[1].tdata2, 15, 15) @[el2_lib.scala 244:74] - node _T_425 = bits(lsu_match_data_1, 15, 15) @[el2_lib.scala 244:86] - node _T_426 = eq(_T_424, _T_425) @[el2_lib.scala 244:78] - node _T_427 = mux(_T_423, UInt<1>("h01"), _T_426) @[el2_lib.scala 244:23] - _T_315[15] <= _T_427 @[el2_lib.scala 244:17] - node _T_428 = bits(io.trigger_pkt_any[1].tdata2, 15, 0) @[el2_lib.scala 244:28] - node _T_429 = andr(_T_428) @[el2_lib.scala 244:36] - node _T_430 = and(_T_429, _T_318) @[el2_lib.scala 244:41] - node _T_431 = bits(io.trigger_pkt_any[1].tdata2, 16, 16) @[el2_lib.scala 244:74] - node _T_432 = bits(lsu_match_data_1, 16, 16) @[el2_lib.scala 244:86] - node _T_433 = eq(_T_431, _T_432) @[el2_lib.scala 244:78] - node _T_434 = mux(_T_430, UInt<1>("h01"), _T_433) @[el2_lib.scala 244:23] - _T_315[16] <= _T_434 @[el2_lib.scala 244:17] - node _T_435 = bits(io.trigger_pkt_any[1].tdata2, 16, 0) @[el2_lib.scala 244:28] - node _T_436 = andr(_T_435) @[el2_lib.scala 244:36] - node _T_437 = and(_T_436, _T_318) @[el2_lib.scala 244:41] - node _T_438 = bits(io.trigger_pkt_any[1].tdata2, 17, 17) @[el2_lib.scala 244:74] - node _T_439 = bits(lsu_match_data_1, 17, 17) @[el2_lib.scala 244:86] - node _T_440 = eq(_T_438, _T_439) @[el2_lib.scala 244:78] - node _T_441 = mux(_T_437, UInt<1>("h01"), _T_440) @[el2_lib.scala 244:23] - _T_315[17] <= _T_441 @[el2_lib.scala 244:17] - node _T_442 = bits(io.trigger_pkt_any[1].tdata2, 17, 0) @[el2_lib.scala 244:28] - node _T_443 = andr(_T_442) @[el2_lib.scala 244:36] - node _T_444 = and(_T_443, _T_318) @[el2_lib.scala 244:41] - node _T_445 = bits(io.trigger_pkt_any[1].tdata2, 18, 18) @[el2_lib.scala 244:74] - node _T_446 = bits(lsu_match_data_1, 18, 18) @[el2_lib.scala 244:86] - node _T_447 = eq(_T_445, _T_446) @[el2_lib.scala 244:78] - node _T_448 = mux(_T_444, UInt<1>("h01"), _T_447) @[el2_lib.scala 244:23] - _T_315[18] <= _T_448 @[el2_lib.scala 244:17] - node _T_449 = bits(io.trigger_pkt_any[1].tdata2, 18, 0) @[el2_lib.scala 244:28] - node _T_450 = andr(_T_449) @[el2_lib.scala 244:36] - node _T_451 = and(_T_450, _T_318) @[el2_lib.scala 244:41] - node _T_452 = bits(io.trigger_pkt_any[1].tdata2, 19, 19) @[el2_lib.scala 244:74] - node _T_453 = bits(lsu_match_data_1, 19, 19) @[el2_lib.scala 244:86] - node _T_454 = eq(_T_452, _T_453) @[el2_lib.scala 244:78] - node _T_455 = mux(_T_451, UInt<1>("h01"), _T_454) @[el2_lib.scala 244:23] - _T_315[19] <= _T_455 @[el2_lib.scala 244:17] - node _T_456 = bits(io.trigger_pkt_any[1].tdata2, 19, 0) @[el2_lib.scala 244:28] - node _T_457 = andr(_T_456) @[el2_lib.scala 244:36] - node _T_458 = and(_T_457, _T_318) @[el2_lib.scala 244:41] - node _T_459 = bits(io.trigger_pkt_any[1].tdata2, 20, 20) @[el2_lib.scala 244:74] - node _T_460 = bits(lsu_match_data_1, 20, 20) @[el2_lib.scala 244:86] - node _T_461 = eq(_T_459, _T_460) @[el2_lib.scala 244:78] - node _T_462 = mux(_T_458, UInt<1>("h01"), _T_461) @[el2_lib.scala 244:23] - _T_315[20] <= _T_462 @[el2_lib.scala 244:17] - node _T_463 = bits(io.trigger_pkt_any[1].tdata2, 20, 0) @[el2_lib.scala 244:28] - node _T_464 = andr(_T_463) @[el2_lib.scala 244:36] - node _T_465 = and(_T_464, _T_318) @[el2_lib.scala 244:41] - node _T_466 = bits(io.trigger_pkt_any[1].tdata2, 21, 21) @[el2_lib.scala 244:74] - node _T_467 = bits(lsu_match_data_1, 21, 21) @[el2_lib.scala 244:86] - node _T_468 = eq(_T_466, _T_467) @[el2_lib.scala 244:78] - node _T_469 = mux(_T_465, UInt<1>("h01"), _T_468) @[el2_lib.scala 244:23] - _T_315[21] <= _T_469 @[el2_lib.scala 244:17] - node _T_470 = bits(io.trigger_pkt_any[1].tdata2, 21, 0) @[el2_lib.scala 244:28] - node _T_471 = andr(_T_470) @[el2_lib.scala 244:36] - node _T_472 = and(_T_471, _T_318) @[el2_lib.scala 244:41] - node _T_473 = bits(io.trigger_pkt_any[1].tdata2, 22, 22) @[el2_lib.scala 244:74] - node _T_474 = bits(lsu_match_data_1, 22, 22) @[el2_lib.scala 244:86] - node _T_475 = eq(_T_473, _T_474) @[el2_lib.scala 244:78] - node _T_476 = mux(_T_472, UInt<1>("h01"), _T_475) @[el2_lib.scala 244:23] - _T_315[22] <= _T_476 @[el2_lib.scala 244:17] - node _T_477 = bits(io.trigger_pkt_any[1].tdata2, 22, 0) @[el2_lib.scala 244:28] - node _T_478 = andr(_T_477) @[el2_lib.scala 244:36] - node _T_479 = and(_T_478, _T_318) @[el2_lib.scala 244:41] - node _T_480 = bits(io.trigger_pkt_any[1].tdata2, 23, 23) @[el2_lib.scala 244:74] - node _T_481 = bits(lsu_match_data_1, 23, 23) @[el2_lib.scala 244:86] - node _T_482 = eq(_T_480, _T_481) @[el2_lib.scala 244:78] - node _T_483 = mux(_T_479, UInt<1>("h01"), _T_482) @[el2_lib.scala 244:23] - _T_315[23] <= _T_483 @[el2_lib.scala 244:17] - node _T_484 = bits(io.trigger_pkt_any[1].tdata2, 23, 0) @[el2_lib.scala 244:28] - node _T_485 = andr(_T_484) @[el2_lib.scala 244:36] - node _T_486 = and(_T_485, _T_318) @[el2_lib.scala 244:41] - node _T_487 = bits(io.trigger_pkt_any[1].tdata2, 24, 24) @[el2_lib.scala 244:74] - node _T_488 = bits(lsu_match_data_1, 24, 24) @[el2_lib.scala 244:86] - node _T_489 = eq(_T_487, _T_488) @[el2_lib.scala 244:78] - node _T_490 = mux(_T_486, UInt<1>("h01"), _T_489) @[el2_lib.scala 244:23] - _T_315[24] <= _T_490 @[el2_lib.scala 244:17] - node _T_491 = bits(io.trigger_pkt_any[1].tdata2, 24, 0) @[el2_lib.scala 244:28] - node _T_492 = andr(_T_491) @[el2_lib.scala 244:36] - node _T_493 = and(_T_492, _T_318) @[el2_lib.scala 244:41] - node _T_494 = bits(io.trigger_pkt_any[1].tdata2, 25, 25) @[el2_lib.scala 244:74] - node _T_495 = bits(lsu_match_data_1, 25, 25) @[el2_lib.scala 244:86] - node _T_496 = eq(_T_494, _T_495) @[el2_lib.scala 244:78] - node _T_497 = mux(_T_493, UInt<1>("h01"), _T_496) @[el2_lib.scala 244:23] - _T_315[25] <= _T_497 @[el2_lib.scala 244:17] - node _T_498 = bits(io.trigger_pkt_any[1].tdata2, 25, 0) @[el2_lib.scala 244:28] - node _T_499 = andr(_T_498) @[el2_lib.scala 244:36] - node _T_500 = and(_T_499, _T_318) @[el2_lib.scala 244:41] - node _T_501 = bits(io.trigger_pkt_any[1].tdata2, 26, 26) @[el2_lib.scala 244:74] - node _T_502 = bits(lsu_match_data_1, 26, 26) @[el2_lib.scala 244:86] - node _T_503 = eq(_T_501, _T_502) @[el2_lib.scala 244:78] - node _T_504 = mux(_T_500, UInt<1>("h01"), _T_503) @[el2_lib.scala 244:23] - _T_315[26] <= _T_504 @[el2_lib.scala 244:17] - node _T_505 = bits(io.trigger_pkt_any[1].tdata2, 26, 0) @[el2_lib.scala 244:28] - node _T_506 = andr(_T_505) @[el2_lib.scala 244:36] - node _T_507 = and(_T_506, _T_318) @[el2_lib.scala 244:41] - node _T_508 = bits(io.trigger_pkt_any[1].tdata2, 27, 27) @[el2_lib.scala 244:74] - node _T_509 = bits(lsu_match_data_1, 27, 27) @[el2_lib.scala 244:86] - node _T_510 = eq(_T_508, _T_509) @[el2_lib.scala 244:78] - node _T_511 = mux(_T_507, UInt<1>("h01"), _T_510) @[el2_lib.scala 244:23] - _T_315[27] <= _T_511 @[el2_lib.scala 244:17] - node _T_512 = bits(io.trigger_pkt_any[1].tdata2, 27, 0) @[el2_lib.scala 244:28] - node _T_513 = andr(_T_512) @[el2_lib.scala 244:36] - node _T_514 = and(_T_513, _T_318) @[el2_lib.scala 244:41] - node _T_515 = bits(io.trigger_pkt_any[1].tdata2, 28, 28) @[el2_lib.scala 244:74] - node _T_516 = bits(lsu_match_data_1, 28, 28) @[el2_lib.scala 244:86] - node _T_517 = eq(_T_515, _T_516) @[el2_lib.scala 244:78] - node _T_518 = mux(_T_514, UInt<1>("h01"), _T_517) @[el2_lib.scala 244:23] - _T_315[28] <= _T_518 @[el2_lib.scala 244:17] - node _T_519 = bits(io.trigger_pkt_any[1].tdata2, 28, 0) @[el2_lib.scala 244:28] - node _T_520 = andr(_T_519) @[el2_lib.scala 244:36] - node _T_521 = and(_T_520, _T_318) @[el2_lib.scala 244:41] - node _T_522 = bits(io.trigger_pkt_any[1].tdata2, 29, 29) @[el2_lib.scala 244:74] - node _T_523 = bits(lsu_match_data_1, 29, 29) @[el2_lib.scala 244:86] - node _T_524 = eq(_T_522, _T_523) @[el2_lib.scala 244:78] - node _T_525 = mux(_T_521, UInt<1>("h01"), _T_524) @[el2_lib.scala 244:23] - _T_315[29] <= _T_525 @[el2_lib.scala 244:17] - node _T_526 = bits(io.trigger_pkt_any[1].tdata2, 29, 0) @[el2_lib.scala 244:28] - node _T_527 = andr(_T_526) @[el2_lib.scala 244:36] - node _T_528 = and(_T_527, _T_318) @[el2_lib.scala 244:41] - node _T_529 = bits(io.trigger_pkt_any[1].tdata2, 30, 30) @[el2_lib.scala 244:74] - node _T_530 = bits(lsu_match_data_1, 30, 30) @[el2_lib.scala 244:86] - node _T_531 = eq(_T_529, _T_530) @[el2_lib.scala 244:78] - node _T_532 = mux(_T_528, UInt<1>("h01"), _T_531) @[el2_lib.scala 244:23] - _T_315[30] <= _T_532 @[el2_lib.scala 244:17] - node _T_533 = bits(io.trigger_pkt_any[1].tdata2, 30, 0) @[el2_lib.scala 244:28] - node _T_534 = andr(_T_533) @[el2_lib.scala 244:36] - node _T_535 = and(_T_534, _T_318) @[el2_lib.scala 244:41] - node _T_536 = bits(io.trigger_pkt_any[1].tdata2, 31, 31) @[el2_lib.scala 244:74] - node _T_537 = bits(lsu_match_data_1, 31, 31) @[el2_lib.scala 244:86] - node _T_538 = eq(_T_536, _T_537) @[el2_lib.scala 244:78] - node _T_539 = mux(_T_535, UInt<1>("h01"), _T_538) @[el2_lib.scala 244:23] - _T_315[31] <= _T_539 @[el2_lib.scala 244:17] - node _T_540 = cat(_T_315[1], _T_315[0]) @[el2_lib.scala 245:14] - node _T_541 = cat(_T_315[3], _T_315[2]) @[el2_lib.scala 245:14] - node _T_542 = cat(_T_541, _T_540) @[el2_lib.scala 245:14] - node _T_543 = cat(_T_315[5], _T_315[4]) @[el2_lib.scala 245:14] - node _T_544 = cat(_T_315[7], _T_315[6]) @[el2_lib.scala 245:14] - node _T_545 = cat(_T_544, _T_543) @[el2_lib.scala 245:14] - node _T_546 = cat(_T_545, _T_542) @[el2_lib.scala 245:14] - node _T_547 = cat(_T_315[9], _T_315[8]) @[el2_lib.scala 245:14] - node _T_548 = cat(_T_315[11], _T_315[10]) @[el2_lib.scala 245:14] - node _T_549 = cat(_T_548, _T_547) @[el2_lib.scala 245:14] - node _T_550 = cat(_T_315[13], _T_315[12]) @[el2_lib.scala 245:14] - node _T_551 = cat(_T_315[15], _T_315[14]) @[el2_lib.scala 245:14] - node _T_552 = cat(_T_551, _T_550) @[el2_lib.scala 245:14] - node _T_553 = cat(_T_552, _T_549) @[el2_lib.scala 245:14] - node _T_554 = cat(_T_553, _T_546) @[el2_lib.scala 245:14] - node _T_555 = cat(_T_315[17], _T_315[16]) @[el2_lib.scala 245:14] - node _T_556 = cat(_T_315[19], _T_315[18]) @[el2_lib.scala 245:14] - node _T_557 = cat(_T_556, _T_555) @[el2_lib.scala 245:14] - node _T_558 = cat(_T_315[21], _T_315[20]) @[el2_lib.scala 245:14] - node _T_559 = cat(_T_315[23], _T_315[22]) @[el2_lib.scala 245:14] - node _T_560 = cat(_T_559, _T_558) @[el2_lib.scala 245:14] - node _T_561 = cat(_T_560, _T_557) @[el2_lib.scala 245:14] - node _T_562 = cat(_T_315[25], _T_315[24]) @[el2_lib.scala 245:14] - node _T_563 = cat(_T_315[27], _T_315[26]) @[el2_lib.scala 245:14] - node _T_564 = cat(_T_563, _T_562) @[el2_lib.scala 245:14] - node _T_565 = cat(_T_315[29], _T_315[28]) @[el2_lib.scala 245:14] - node _T_566 = cat(_T_315[31], _T_315[30]) @[el2_lib.scala 245:14] - node _T_567 = cat(_T_566, _T_565) @[el2_lib.scala 245:14] - node _T_568 = cat(_T_567, _T_564) @[el2_lib.scala 245:14] - node _T_569 = cat(_T_568, _T_561) @[el2_lib.scala 245:14] - node _T_570 = cat(_T_569, _T_554) @[el2_lib.scala 245:14] - node _T_571 = andr(_T_570) @[el2_lib.scala 245:25] + wire _T_315 : UInt<1>[32] @[lib.scala 100:24] + node _T_316 = andr(io.trigger_pkt_any[1].tdata2) @[lib.scala 101:45] + node _T_317 = not(_T_316) @[lib.scala 101:39] + node _T_318 = and(_T_314, _T_317) @[lib.scala 101:37] + node _T_319 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[lib.scala 102:48] + node _T_320 = bits(lsu_match_data_1, 0, 0) @[lib.scala 102:60] + node _T_321 = eq(_T_319, _T_320) @[lib.scala 102:52] + node _T_322 = or(_T_318, _T_321) @[lib.scala 102:41] + _T_315[0] <= _T_322 @[lib.scala 102:18] + node _T_323 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[lib.scala 104:28] + node _T_324 = andr(_T_323) @[lib.scala 104:36] + node _T_325 = and(_T_324, _T_318) @[lib.scala 104:41] + node _T_326 = bits(io.trigger_pkt_any[1].tdata2, 1, 1) @[lib.scala 104:74] + node _T_327 = bits(lsu_match_data_1, 1, 1) @[lib.scala 104:86] + node _T_328 = eq(_T_326, _T_327) @[lib.scala 104:78] + node _T_329 = mux(_T_325, UInt<1>("h01"), _T_328) @[lib.scala 104:23] + _T_315[1] <= _T_329 @[lib.scala 104:17] + node _T_330 = bits(io.trigger_pkt_any[1].tdata2, 1, 0) @[lib.scala 104:28] + node _T_331 = andr(_T_330) @[lib.scala 104:36] + node _T_332 = and(_T_331, _T_318) @[lib.scala 104:41] + node _T_333 = bits(io.trigger_pkt_any[1].tdata2, 2, 2) @[lib.scala 104:74] + node _T_334 = bits(lsu_match_data_1, 2, 2) @[lib.scala 104:86] + node _T_335 = eq(_T_333, _T_334) @[lib.scala 104:78] + node _T_336 = mux(_T_332, UInt<1>("h01"), _T_335) @[lib.scala 104:23] + _T_315[2] <= _T_336 @[lib.scala 104:17] + node _T_337 = bits(io.trigger_pkt_any[1].tdata2, 2, 0) @[lib.scala 104:28] + node _T_338 = andr(_T_337) @[lib.scala 104:36] + node _T_339 = and(_T_338, _T_318) @[lib.scala 104:41] + node _T_340 = bits(io.trigger_pkt_any[1].tdata2, 3, 3) @[lib.scala 104:74] + node _T_341 = bits(lsu_match_data_1, 3, 3) @[lib.scala 104:86] + node _T_342 = eq(_T_340, _T_341) @[lib.scala 104:78] + node _T_343 = mux(_T_339, UInt<1>("h01"), _T_342) @[lib.scala 104:23] + _T_315[3] <= _T_343 @[lib.scala 104:17] + node _T_344 = bits(io.trigger_pkt_any[1].tdata2, 3, 0) @[lib.scala 104:28] + node _T_345 = andr(_T_344) @[lib.scala 104:36] + node _T_346 = and(_T_345, _T_318) @[lib.scala 104:41] + node _T_347 = bits(io.trigger_pkt_any[1].tdata2, 4, 4) @[lib.scala 104:74] + node _T_348 = bits(lsu_match_data_1, 4, 4) @[lib.scala 104:86] + node _T_349 = eq(_T_347, _T_348) @[lib.scala 104:78] + node _T_350 = mux(_T_346, UInt<1>("h01"), _T_349) @[lib.scala 104:23] + _T_315[4] <= _T_350 @[lib.scala 104:17] + node _T_351 = bits(io.trigger_pkt_any[1].tdata2, 4, 0) @[lib.scala 104:28] + node _T_352 = andr(_T_351) @[lib.scala 104:36] + node _T_353 = and(_T_352, _T_318) @[lib.scala 104:41] + node _T_354 = bits(io.trigger_pkt_any[1].tdata2, 5, 5) @[lib.scala 104:74] + node _T_355 = bits(lsu_match_data_1, 5, 5) @[lib.scala 104:86] + node _T_356 = eq(_T_354, _T_355) @[lib.scala 104:78] + node _T_357 = mux(_T_353, UInt<1>("h01"), _T_356) @[lib.scala 104:23] + _T_315[5] <= _T_357 @[lib.scala 104:17] + node _T_358 = bits(io.trigger_pkt_any[1].tdata2, 5, 0) @[lib.scala 104:28] + node _T_359 = andr(_T_358) @[lib.scala 104:36] + node _T_360 = and(_T_359, _T_318) @[lib.scala 104:41] + node _T_361 = bits(io.trigger_pkt_any[1].tdata2, 6, 6) @[lib.scala 104:74] + node _T_362 = bits(lsu_match_data_1, 6, 6) @[lib.scala 104:86] + node _T_363 = eq(_T_361, _T_362) @[lib.scala 104:78] + node _T_364 = mux(_T_360, UInt<1>("h01"), _T_363) @[lib.scala 104:23] + _T_315[6] <= _T_364 @[lib.scala 104:17] + node _T_365 = bits(io.trigger_pkt_any[1].tdata2, 6, 0) @[lib.scala 104:28] + node _T_366 = andr(_T_365) @[lib.scala 104:36] + node _T_367 = and(_T_366, _T_318) @[lib.scala 104:41] + node _T_368 = bits(io.trigger_pkt_any[1].tdata2, 7, 7) @[lib.scala 104:74] + node _T_369 = bits(lsu_match_data_1, 7, 7) @[lib.scala 104:86] + node _T_370 = eq(_T_368, _T_369) @[lib.scala 104:78] + node _T_371 = mux(_T_367, UInt<1>("h01"), _T_370) @[lib.scala 104:23] + _T_315[7] <= _T_371 @[lib.scala 104:17] + node _T_372 = bits(io.trigger_pkt_any[1].tdata2, 7, 0) @[lib.scala 104:28] + node _T_373 = andr(_T_372) @[lib.scala 104:36] + node _T_374 = and(_T_373, _T_318) @[lib.scala 104:41] + node _T_375 = bits(io.trigger_pkt_any[1].tdata2, 8, 8) @[lib.scala 104:74] + node _T_376 = bits(lsu_match_data_1, 8, 8) @[lib.scala 104:86] + node _T_377 = eq(_T_375, _T_376) @[lib.scala 104:78] + node _T_378 = mux(_T_374, UInt<1>("h01"), _T_377) @[lib.scala 104:23] + _T_315[8] <= _T_378 @[lib.scala 104:17] + node _T_379 = bits(io.trigger_pkt_any[1].tdata2, 8, 0) @[lib.scala 104:28] + node _T_380 = andr(_T_379) @[lib.scala 104:36] + node _T_381 = and(_T_380, _T_318) @[lib.scala 104:41] + node _T_382 = bits(io.trigger_pkt_any[1].tdata2, 9, 9) @[lib.scala 104:74] + node _T_383 = bits(lsu_match_data_1, 9, 9) @[lib.scala 104:86] + node _T_384 = eq(_T_382, _T_383) @[lib.scala 104:78] + node _T_385 = mux(_T_381, UInt<1>("h01"), _T_384) @[lib.scala 104:23] + _T_315[9] <= _T_385 @[lib.scala 104:17] + node _T_386 = bits(io.trigger_pkt_any[1].tdata2, 9, 0) @[lib.scala 104:28] + node _T_387 = andr(_T_386) @[lib.scala 104:36] + node _T_388 = and(_T_387, _T_318) @[lib.scala 104:41] + node _T_389 = bits(io.trigger_pkt_any[1].tdata2, 10, 10) @[lib.scala 104:74] + node _T_390 = bits(lsu_match_data_1, 10, 10) @[lib.scala 104:86] + node _T_391 = eq(_T_389, _T_390) @[lib.scala 104:78] + node _T_392 = mux(_T_388, UInt<1>("h01"), _T_391) @[lib.scala 104:23] + _T_315[10] <= _T_392 @[lib.scala 104:17] + node _T_393 = bits(io.trigger_pkt_any[1].tdata2, 10, 0) @[lib.scala 104:28] + node _T_394 = andr(_T_393) @[lib.scala 104:36] + node _T_395 = and(_T_394, _T_318) @[lib.scala 104:41] + node _T_396 = bits(io.trigger_pkt_any[1].tdata2, 11, 11) @[lib.scala 104:74] + node _T_397 = bits(lsu_match_data_1, 11, 11) @[lib.scala 104:86] + node _T_398 = eq(_T_396, _T_397) @[lib.scala 104:78] + node _T_399 = mux(_T_395, UInt<1>("h01"), _T_398) @[lib.scala 104:23] + _T_315[11] <= _T_399 @[lib.scala 104:17] + node _T_400 = bits(io.trigger_pkt_any[1].tdata2, 11, 0) @[lib.scala 104:28] + node _T_401 = andr(_T_400) @[lib.scala 104:36] + node _T_402 = and(_T_401, _T_318) @[lib.scala 104:41] + node _T_403 = bits(io.trigger_pkt_any[1].tdata2, 12, 12) @[lib.scala 104:74] + node _T_404 = bits(lsu_match_data_1, 12, 12) @[lib.scala 104:86] + node _T_405 = eq(_T_403, _T_404) @[lib.scala 104:78] + node _T_406 = mux(_T_402, UInt<1>("h01"), _T_405) @[lib.scala 104:23] + _T_315[12] <= _T_406 @[lib.scala 104:17] + node _T_407 = bits(io.trigger_pkt_any[1].tdata2, 12, 0) @[lib.scala 104:28] + node _T_408 = andr(_T_407) @[lib.scala 104:36] + node _T_409 = and(_T_408, _T_318) @[lib.scala 104:41] + node _T_410 = bits(io.trigger_pkt_any[1].tdata2, 13, 13) @[lib.scala 104:74] + node _T_411 = bits(lsu_match_data_1, 13, 13) @[lib.scala 104:86] + node _T_412 = eq(_T_410, _T_411) @[lib.scala 104:78] + node _T_413 = mux(_T_409, UInt<1>("h01"), _T_412) @[lib.scala 104:23] + _T_315[13] <= _T_413 @[lib.scala 104:17] + node _T_414 = bits(io.trigger_pkt_any[1].tdata2, 13, 0) @[lib.scala 104:28] + node _T_415 = andr(_T_414) @[lib.scala 104:36] + node _T_416 = and(_T_415, _T_318) @[lib.scala 104:41] + node _T_417 = bits(io.trigger_pkt_any[1].tdata2, 14, 14) @[lib.scala 104:74] + node _T_418 = bits(lsu_match_data_1, 14, 14) @[lib.scala 104:86] + node _T_419 = eq(_T_417, _T_418) @[lib.scala 104:78] + node _T_420 = mux(_T_416, UInt<1>("h01"), _T_419) @[lib.scala 104:23] + _T_315[14] <= _T_420 @[lib.scala 104:17] + node _T_421 = bits(io.trigger_pkt_any[1].tdata2, 14, 0) @[lib.scala 104:28] + node _T_422 = andr(_T_421) @[lib.scala 104:36] + node _T_423 = and(_T_422, _T_318) @[lib.scala 104:41] + node _T_424 = bits(io.trigger_pkt_any[1].tdata2, 15, 15) @[lib.scala 104:74] + node _T_425 = bits(lsu_match_data_1, 15, 15) @[lib.scala 104:86] + node _T_426 = eq(_T_424, _T_425) @[lib.scala 104:78] + node _T_427 = mux(_T_423, UInt<1>("h01"), _T_426) @[lib.scala 104:23] + _T_315[15] <= _T_427 @[lib.scala 104:17] + node _T_428 = bits(io.trigger_pkt_any[1].tdata2, 15, 0) @[lib.scala 104:28] + node _T_429 = andr(_T_428) @[lib.scala 104:36] + node _T_430 = and(_T_429, _T_318) @[lib.scala 104:41] + node _T_431 = bits(io.trigger_pkt_any[1].tdata2, 16, 16) @[lib.scala 104:74] + node _T_432 = bits(lsu_match_data_1, 16, 16) @[lib.scala 104:86] + node _T_433 = eq(_T_431, _T_432) @[lib.scala 104:78] + node _T_434 = mux(_T_430, UInt<1>("h01"), _T_433) @[lib.scala 104:23] + _T_315[16] <= _T_434 @[lib.scala 104:17] + node _T_435 = bits(io.trigger_pkt_any[1].tdata2, 16, 0) @[lib.scala 104:28] + node _T_436 = andr(_T_435) @[lib.scala 104:36] + node _T_437 = and(_T_436, _T_318) @[lib.scala 104:41] + node _T_438 = bits(io.trigger_pkt_any[1].tdata2, 17, 17) @[lib.scala 104:74] + node _T_439 = bits(lsu_match_data_1, 17, 17) @[lib.scala 104:86] + node _T_440 = eq(_T_438, _T_439) @[lib.scala 104:78] + node _T_441 = mux(_T_437, UInt<1>("h01"), _T_440) @[lib.scala 104:23] + _T_315[17] <= _T_441 @[lib.scala 104:17] + node _T_442 = bits(io.trigger_pkt_any[1].tdata2, 17, 0) @[lib.scala 104:28] + node _T_443 = andr(_T_442) @[lib.scala 104:36] + node _T_444 = and(_T_443, _T_318) @[lib.scala 104:41] + node _T_445 = bits(io.trigger_pkt_any[1].tdata2, 18, 18) @[lib.scala 104:74] + node _T_446 = bits(lsu_match_data_1, 18, 18) @[lib.scala 104:86] + node _T_447 = eq(_T_445, _T_446) @[lib.scala 104:78] + node _T_448 = mux(_T_444, UInt<1>("h01"), _T_447) @[lib.scala 104:23] + _T_315[18] <= _T_448 @[lib.scala 104:17] + node _T_449 = bits(io.trigger_pkt_any[1].tdata2, 18, 0) @[lib.scala 104:28] + node _T_450 = andr(_T_449) @[lib.scala 104:36] + node _T_451 = and(_T_450, _T_318) @[lib.scala 104:41] + node _T_452 = bits(io.trigger_pkt_any[1].tdata2, 19, 19) @[lib.scala 104:74] + node _T_453 = bits(lsu_match_data_1, 19, 19) @[lib.scala 104:86] + node _T_454 = eq(_T_452, _T_453) @[lib.scala 104:78] + node _T_455 = mux(_T_451, UInt<1>("h01"), _T_454) @[lib.scala 104:23] + _T_315[19] <= _T_455 @[lib.scala 104:17] + node _T_456 = bits(io.trigger_pkt_any[1].tdata2, 19, 0) @[lib.scala 104:28] + node _T_457 = andr(_T_456) @[lib.scala 104:36] + node _T_458 = and(_T_457, _T_318) @[lib.scala 104:41] + node _T_459 = bits(io.trigger_pkt_any[1].tdata2, 20, 20) @[lib.scala 104:74] + node _T_460 = bits(lsu_match_data_1, 20, 20) @[lib.scala 104:86] + node _T_461 = eq(_T_459, _T_460) @[lib.scala 104:78] + node _T_462 = mux(_T_458, UInt<1>("h01"), _T_461) @[lib.scala 104:23] + _T_315[20] <= _T_462 @[lib.scala 104:17] + node _T_463 = bits(io.trigger_pkt_any[1].tdata2, 20, 0) @[lib.scala 104:28] + node _T_464 = andr(_T_463) @[lib.scala 104:36] + node _T_465 = and(_T_464, _T_318) @[lib.scala 104:41] + node _T_466 = bits(io.trigger_pkt_any[1].tdata2, 21, 21) @[lib.scala 104:74] + node _T_467 = bits(lsu_match_data_1, 21, 21) @[lib.scala 104:86] + node _T_468 = eq(_T_466, _T_467) @[lib.scala 104:78] + node _T_469 = mux(_T_465, UInt<1>("h01"), _T_468) @[lib.scala 104:23] + _T_315[21] <= _T_469 @[lib.scala 104:17] + node _T_470 = bits(io.trigger_pkt_any[1].tdata2, 21, 0) @[lib.scala 104:28] + node _T_471 = andr(_T_470) @[lib.scala 104:36] + node _T_472 = and(_T_471, _T_318) @[lib.scala 104:41] + node _T_473 = bits(io.trigger_pkt_any[1].tdata2, 22, 22) @[lib.scala 104:74] + node _T_474 = bits(lsu_match_data_1, 22, 22) @[lib.scala 104:86] + node _T_475 = eq(_T_473, _T_474) @[lib.scala 104:78] + node _T_476 = mux(_T_472, UInt<1>("h01"), _T_475) @[lib.scala 104:23] + _T_315[22] <= _T_476 @[lib.scala 104:17] + node _T_477 = bits(io.trigger_pkt_any[1].tdata2, 22, 0) @[lib.scala 104:28] + node _T_478 = andr(_T_477) @[lib.scala 104:36] + node _T_479 = and(_T_478, _T_318) @[lib.scala 104:41] + node _T_480 = bits(io.trigger_pkt_any[1].tdata2, 23, 23) @[lib.scala 104:74] + node _T_481 = bits(lsu_match_data_1, 23, 23) @[lib.scala 104:86] + node _T_482 = eq(_T_480, _T_481) @[lib.scala 104:78] + node _T_483 = mux(_T_479, UInt<1>("h01"), _T_482) @[lib.scala 104:23] + _T_315[23] <= _T_483 @[lib.scala 104:17] + node _T_484 = bits(io.trigger_pkt_any[1].tdata2, 23, 0) @[lib.scala 104:28] + node _T_485 = andr(_T_484) @[lib.scala 104:36] + node _T_486 = and(_T_485, _T_318) @[lib.scala 104:41] + node _T_487 = bits(io.trigger_pkt_any[1].tdata2, 24, 24) @[lib.scala 104:74] + node _T_488 = bits(lsu_match_data_1, 24, 24) @[lib.scala 104:86] + node _T_489 = eq(_T_487, _T_488) @[lib.scala 104:78] + node _T_490 = mux(_T_486, UInt<1>("h01"), _T_489) @[lib.scala 104:23] + _T_315[24] <= _T_490 @[lib.scala 104:17] + node _T_491 = bits(io.trigger_pkt_any[1].tdata2, 24, 0) @[lib.scala 104:28] + node _T_492 = andr(_T_491) @[lib.scala 104:36] + node _T_493 = and(_T_492, _T_318) @[lib.scala 104:41] + node _T_494 = bits(io.trigger_pkt_any[1].tdata2, 25, 25) @[lib.scala 104:74] + node _T_495 = bits(lsu_match_data_1, 25, 25) @[lib.scala 104:86] + node _T_496 = eq(_T_494, _T_495) @[lib.scala 104:78] + node _T_497 = mux(_T_493, UInt<1>("h01"), _T_496) @[lib.scala 104:23] + _T_315[25] <= _T_497 @[lib.scala 104:17] + node _T_498 = bits(io.trigger_pkt_any[1].tdata2, 25, 0) @[lib.scala 104:28] + node _T_499 = andr(_T_498) @[lib.scala 104:36] + node _T_500 = and(_T_499, _T_318) @[lib.scala 104:41] + node _T_501 = bits(io.trigger_pkt_any[1].tdata2, 26, 26) @[lib.scala 104:74] + node _T_502 = bits(lsu_match_data_1, 26, 26) @[lib.scala 104:86] + node _T_503 = eq(_T_501, _T_502) @[lib.scala 104:78] + node _T_504 = mux(_T_500, UInt<1>("h01"), _T_503) @[lib.scala 104:23] + _T_315[26] <= _T_504 @[lib.scala 104:17] + node _T_505 = bits(io.trigger_pkt_any[1].tdata2, 26, 0) @[lib.scala 104:28] + node _T_506 = andr(_T_505) @[lib.scala 104:36] + node _T_507 = and(_T_506, _T_318) @[lib.scala 104:41] + node _T_508 = bits(io.trigger_pkt_any[1].tdata2, 27, 27) @[lib.scala 104:74] + node _T_509 = bits(lsu_match_data_1, 27, 27) @[lib.scala 104:86] + node _T_510 = eq(_T_508, _T_509) @[lib.scala 104:78] + node _T_511 = mux(_T_507, UInt<1>("h01"), _T_510) @[lib.scala 104:23] + _T_315[27] <= _T_511 @[lib.scala 104:17] + node _T_512 = bits(io.trigger_pkt_any[1].tdata2, 27, 0) @[lib.scala 104:28] + node _T_513 = andr(_T_512) @[lib.scala 104:36] + node _T_514 = and(_T_513, _T_318) @[lib.scala 104:41] + node _T_515 = bits(io.trigger_pkt_any[1].tdata2, 28, 28) @[lib.scala 104:74] + node _T_516 = bits(lsu_match_data_1, 28, 28) @[lib.scala 104:86] + node _T_517 = eq(_T_515, _T_516) @[lib.scala 104:78] + node _T_518 = mux(_T_514, UInt<1>("h01"), _T_517) @[lib.scala 104:23] + _T_315[28] <= _T_518 @[lib.scala 104:17] + node _T_519 = bits(io.trigger_pkt_any[1].tdata2, 28, 0) @[lib.scala 104:28] + node _T_520 = andr(_T_519) @[lib.scala 104:36] + node _T_521 = and(_T_520, _T_318) @[lib.scala 104:41] + node _T_522 = bits(io.trigger_pkt_any[1].tdata2, 29, 29) @[lib.scala 104:74] + node _T_523 = bits(lsu_match_data_1, 29, 29) @[lib.scala 104:86] + node _T_524 = eq(_T_522, _T_523) @[lib.scala 104:78] + node _T_525 = mux(_T_521, UInt<1>("h01"), _T_524) @[lib.scala 104:23] + _T_315[29] <= _T_525 @[lib.scala 104:17] + node _T_526 = bits(io.trigger_pkt_any[1].tdata2, 29, 0) @[lib.scala 104:28] + node _T_527 = andr(_T_526) @[lib.scala 104:36] + node _T_528 = and(_T_527, _T_318) @[lib.scala 104:41] + node _T_529 = bits(io.trigger_pkt_any[1].tdata2, 30, 30) @[lib.scala 104:74] + node _T_530 = bits(lsu_match_data_1, 30, 30) @[lib.scala 104:86] + node _T_531 = eq(_T_529, _T_530) @[lib.scala 104:78] + node _T_532 = mux(_T_528, UInt<1>("h01"), _T_531) @[lib.scala 104:23] + _T_315[30] <= _T_532 @[lib.scala 104:17] + node _T_533 = bits(io.trigger_pkt_any[1].tdata2, 30, 0) @[lib.scala 104:28] + node _T_534 = andr(_T_533) @[lib.scala 104:36] + node _T_535 = and(_T_534, _T_318) @[lib.scala 104:41] + node _T_536 = bits(io.trigger_pkt_any[1].tdata2, 31, 31) @[lib.scala 104:74] + node _T_537 = bits(lsu_match_data_1, 31, 31) @[lib.scala 104:86] + node _T_538 = eq(_T_536, _T_537) @[lib.scala 104:78] + node _T_539 = mux(_T_535, UInt<1>("h01"), _T_538) @[lib.scala 104:23] + _T_315[31] <= _T_539 @[lib.scala 104:17] + node _T_540 = cat(_T_315[1], _T_315[0]) @[lib.scala 105:14] + node _T_541 = cat(_T_315[3], _T_315[2]) @[lib.scala 105:14] + node _T_542 = cat(_T_541, _T_540) @[lib.scala 105:14] + node _T_543 = cat(_T_315[5], _T_315[4]) @[lib.scala 105:14] + node _T_544 = cat(_T_315[7], _T_315[6]) @[lib.scala 105:14] + node _T_545 = cat(_T_544, _T_543) @[lib.scala 105:14] + node _T_546 = cat(_T_545, _T_542) @[lib.scala 105:14] + node _T_547 = cat(_T_315[9], _T_315[8]) @[lib.scala 105:14] + node _T_548 = cat(_T_315[11], _T_315[10]) @[lib.scala 105:14] + node _T_549 = cat(_T_548, _T_547) @[lib.scala 105:14] + node _T_550 = cat(_T_315[13], _T_315[12]) @[lib.scala 105:14] + node _T_551 = cat(_T_315[15], _T_315[14]) @[lib.scala 105:14] + node _T_552 = cat(_T_551, _T_550) @[lib.scala 105:14] + node _T_553 = cat(_T_552, _T_549) @[lib.scala 105:14] + node _T_554 = cat(_T_553, _T_546) @[lib.scala 105:14] + node _T_555 = cat(_T_315[17], _T_315[16]) @[lib.scala 105:14] + node _T_556 = cat(_T_315[19], _T_315[18]) @[lib.scala 105:14] + node _T_557 = cat(_T_556, _T_555) @[lib.scala 105:14] + node _T_558 = cat(_T_315[21], _T_315[20]) @[lib.scala 105:14] + node _T_559 = cat(_T_315[23], _T_315[22]) @[lib.scala 105:14] + node _T_560 = cat(_T_559, _T_558) @[lib.scala 105:14] + node _T_561 = cat(_T_560, _T_557) @[lib.scala 105:14] + node _T_562 = cat(_T_315[25], _T_315[24]) @[lib.scala 105:14] + node _T_563 = cat(_T_315[27], _T_315[26]) @[lib.scala 105:14] + node _T_564 = cat(_T_563, _T_562) @[lib.scala 105:14] + node _T_565 = cat(_T_315[29], _T_315[28]) @[lib.scala 105:14] + node _T_566 = cat(_T_315[31], _T_315[30]) @[lib.scala 105:14] + node _T_567 = cat(_T_566, _T_565) @[lib.scala 105:14] + node _T_568 = cat(_T_567, _T_564) @[lib.scala 105:14] + node _T_569 = cat(_T_568, _T_561) @[lib.scala 105:14] + node _T_570 = cat(_T_569, _T_554) @[lib.scala 105:14] + node _T_571 = andr(_T_570) @[lib.scala 105:25] node _T_572 = and(_T_313, _T_571) @[lsu_trigger.scala 19:92] node _T_573 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_trigger.scala 18:71] node _T_574 = and(io.lsu_pkt_m.valid, _T_573) @[lsu_trigger.scala 18:69] @@ -93620,295 +93612,295 @@ circuit quasar_wrapper : node _T_579 = or(_T_575, _T_578) @[lsu_trigger.scala 18:152] node _T_580 = and(_T_574, _T_579) @[lsu_trigger.scala 18:94] node _T_581 = bits(io.trigger_pkt_any[2].match_pkt, 0, 0) @[lsu_trigger.scala 20:107] - wire _T_582 : UInt<1>[32] @[el2_lib.scala 240:24] - node _T_583 = andr(io.trigger_pkt_any[2].tdata2) @[el2_lib.scala 241:45] - node _T_584 = not(_T_583) @[el2_lib.scala 241:39] - node _T_585 = and(_T_581, _T_584) @[el2_lib.scala 241:37] - node _T_586 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[el2_lib.scala 242:48] - node _T_587 = bits(lsu_match_data_2, 0, 0) @[el2_lib.scala 242:60] - node _T_588 = eq(_T_586, _T_587) @[el2_lib.scala 242:52] - node _T_589 = or(_T_585, _T_588) @[el2_lib.scala 242:41] - _T_582[0] <= _T_589 @[el2_lib.scala 242:18] - node _T_590 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[el2_lib.scala 244:28] - node _T_591 = andr(_T_590) @[el2_lib.scala 244:36] - node _T_592 = and(_T_591, _T_585) @[el2_lib.scala 244:41] - node _T_593 = bits(io.trigger_pkt_any[2].tdata2, 1, 1) @[el2_lib.scala 244:74] - node _T_594 = bits(lsu_match_data_2, 1, 1) @[el2_lib.scala 244:86] - node _T_595 = eq(_T_593, _T_594) @[el2_lib.scala 244:78] - node _T_596 = mux(_T_592, UInt<1>("h01"), _T_595) @[el2_lib.scala 244:23] - _T_582[1] <= _T_596 @[el2_lib.scala 244:17] - node _T_597 = bits(io.trigger_pkt_any[2].tdata2, 1, 0) @[el2_lib.scala 244:28] - node _T_598 = andr(_T_597) @[el2_lib.scala 244:36] - node _T_599 = and(_T_598, _T_585) @[el2_lib.scala 244:41] - node _T_600 = bits(io.trigger_pkt_any[2].tdata2, 2, 2) @[el2_lib.scala 244:74] - node _T_601 = bits(lsu_match_data_2, 2, 2) @[el2_lib.scala 244:86] - node _T_602 = eq(_T_600, _T_601) @[el2_lib.scala 244:78] - node _T_603 = mux(_T_599, UInt<1>("h01"), _T_602) @[el2_lib.scala 244:23] - _T_582[2] <= _T_603 @[el2_lib.scala 244:17] - node _T_604 = bits(io.trigger_pkt_any[2].tdata2, 2, 0) @[el2_lib.scala 244:28] - node _T_605 = andr(_T_604) @[el2_lib.scala 244:36] - node _T_606 = and(_T_605, _T_585) @[el2_lib.scala 244:41] - node _T_607 = bits(io.trigger_pkt_any[2].tdata2, 3, 3) @[el2_lib.scala 244:74] - node _T_608 = bits(lsu_match_data_2, 3, 3) @[el2_lib.scala 244:86] - node _T_609 = eq(_T_607, _T_608) @[el2_lib.scala 244:78] - node _T_610 = mux(_T_606, UInt<1>("h01"), _T_609) @[el2_lib.scala 244:23] - _T_582[3] <= _T_610 @[el2_lib.scala 244:17] - node _T_611 = bits(io.trigger_pkt_any[2].tdata2, 3, 0) @[el2_lib.scala 244:28] - node _T_612 = andr(_T_611) @[el2_lib.scala 244:36] - node _T_613 = and(_T_612, _T_585) @[el2_lib.scala 244:41] - node _T_614 = bits(io.trigger_pkt_any[2].tdata2, 4, 4) @[el2_lib.scala 244:74] - node _T_615 = bits(lsu_match_data_2, 4, 4) @[el2_lib.scala 244:86] - node _T_616 = eq(_T_614, _T_615) @[el2_lib.scala 244:78] - node _T_617 = mux(_T_613, UInt<1>("h01"), _T_616) @[el2_lib.scala 244:23] - _T_582[4] <= _T_617 @[el2_lib.scala 244:17] - node _T_618 = bits(io.trigger_pkt_any[2].tdata2, 4, 0) @[el2_lib.scala 244:28] - node _T_619 = andr(_T_618) @[el2_lib.scala 244:36] - node _T_620 = and(_T_619, _T_585) @[el2_lib.scala 244:41] - node _T_621 = bits(io.trigger_pkt_any[2].tdata2, 5, 5) @[el2_lib.scala 244:74] - node _T_622 = bits(lsu_match_data_2, 5, 5) @[el2_lib.scala 244:86] - node _T_623 = eq(_T_621, _T_622) @[el2_lib.scala 244:78] - node _T_624 = mux(_T_620, UInt<1>("h01"), _T_623) @[el2_lib.scala 244:23] - _T_582[5] <= _T_624 @[el2_lib.scala 244:17] - node _T_625 = bits(io.trigger_pkt_any[2].tdata2, 5, 0) @[el2_lib.scala 244:28] - node _T_626 = andr(_T_625) @[el2_lib.scala 244:36] - node _T_627 = and(_T_626, _T_585) @[el2_lib.scala 244:41] - node _T_628 = bits(io.trigger_pkt_any[2].tdata2, 6, 6) @[el2_lib.scala 244:74] - node _T_629 = bits(lsu_match_data_2, 6, 6) @[el2_lib.scala 244:86] - node _T_630 = eq(_T_628, _T_629) @[el2_lib.scala 244:78] - node _T_631 = mux(_T_627, UInt<1>("h01"), _T_630) @[el2_lib.scala 244:23] - _T_582[6] <= _T_631 @[el2_lib.scala 244:17] - node _T_632 = bits(io.trigger_pkt_any[2].tdata2, 6, 0) @[el2_lib.scala 244:28] - node _T_633 = andr(_T_632) @[el2_lib.scala 244:36] - node _T_634 = and(_T_633, _T_585) @[el2_lib.scala 244:41] - node _T_635 = bits(io.trigger_pkt_any[2].tdata2, 7, 7) @[el2_lib.scala 244:74] - node _T_636 = bits(lsu_match_data_2, 7, 7) @[el2_lib.scala 244:86] - node _T_637 = eq(_T_635, _T_636) @[el2_lib.scala 244:78] - node _T_638 = mux(_T_634, UInt<1>("h01"), _T_637) @[el2_lib.scala 244:23] - _T_582[7] <= _T_638 @[el2_lib.scala 244:17] - node _T_639 = bits(io.trigger_pkt_any[2].tdata2, 7, 0) @[el2_lib.scala 244:28] - node _T_640 = andr(_T_639) @[el2_lib.scala 244:36] - node _T_641 = and(_T_640, _T_585) @[el2_lib.scala 244:41] - node _T_642 = bits(io.trigger_pkt_any[2].tdata2, 8, 8) @[el2_lib.scala 244:74] - node _T_643 = bits(lsu_match_data_2, 8, 8) @[el2_lib.scala 244:86] - node _T_644 = eq(_T_642, _T_643) @[el2_lib.scala 244:78] - node _T_645 = mux(_T_641, UInt<1>("h01"), _T_644) @[el2_lib.scala 244:23] - _T_582[8] <= _T_645 @[el2_lib.scala 244:17] - node _T_646 = bits(io.trigger_pkt_any[2].tdata2, 8, 0) @[el2_lib.scala 244:28] - node _T_647 = andr(_T_646) @[el2_lib.scala 244:36] - node _T_648 = and(_T_647, _T_585) @[el2_lib.scala 244:41] - node _T_649 = bits(io.trigger_pkt_any[2].tdata2, 9, 9) @[el2_lib.scala 244:74] - node _T_650 = bits(lsu_match_data_2, 9, 9) @[el2_lib.scala 244:86] - node _T_651 = eq(_T_649, _T_650) @[el2_lib.scala 244:78] - node _T_652 = mux(_T_648, UInt<1>("h01"), _T_651) @[el2_lib.scala 244:23] - _T_582[9] <= _T_652 @[el2_lib.scala 244:17] - node _T_653 = bits(io.trigger_pkt_any[2].tdata2, 9, 0) @[el2_lib.scala 244:28] - node _T_654 = andr(_T_653) @[el2_lib.scala 244:36] - node _T_655 = and(_T_654, _T_585) @[el2_lib.scala 244:41] - node _T_656 = bits(io.trigger_pkt_any[2].tdata2, 10, 10) @[el2_lib.scala 244:74] - node _T_657 = bits(lsu_match_data_2, 10, 10) @[el2_lib.scala 244:86] - node _T_658 = eq(_T_656, _T_657) @[el2_lib.scala 244:78] - node _T_659 = mux(_T_655, UInt<1>("h01"), _T_658) @[el2_lib.scala 244:23] - _T_582[10] <= _T_659 @[el2_lib.scala 244:17] - node _T_660 = bits(io.trigger_pkt_any[2].tdata2, 10, 0) @[el2_lib.scala 244:28] - node _T_661 = andr(_T_660) @[el2_lib.scala 244:36] - node _T_662 = and(_T_661, _T_585) @[el2_lib.scala 244:41] - node _T_663 = bits(io.trigger_pkt_any[2].tdata2, 11, 11) @[el2_lib.scala 244:74] - node _T_664 = bits(lsu_match_data_2, 11, 11) @[el2_lib.scala 244:86] - node _T_665 = eq(_T_663, _T_664) @[el2_lib.scala 244:78] - node _T_666 = mux(_T_662, UInt<1>("h01"), _T_665) @[el2_lib.scala 244:23] - _T_582[11] <= _T_666 @[el2_lib.scala 244:17] - node _T_667 = bits(io.trigger_pkt_any[2].tdata2, 11, 0) @[el2_lib.scala 244:28] - node _T_668 = andr(_T_667) @[el2_lib.scala 244:36] - node _T_669 = and(_T_668, _T_585) @[el2_lib.scala 244:41] - node _T_670 = bits(io.trigger_pkt_any[2].tdata2, 12, 12) @[el2_lib.scala 244:74] - node _T_671 = bits(lsu_match_data_2, 12, 12) @[el2_lib.scala 244:86] - node _T_672 = eq(_T_670, _T_671) @[el2_lib.scala 244:78] - node _T_673 = mux(_T_669, UInt<1>("h01"), _T_672) @[el2_lib.scala 244:23] - _T_582[12] <= _T_673 @[el2_lib.scala 244:17] - node _T_674 = bits(io.trigger_pkt_any[2].tdata2, 12, 0) @[el2_lib.scala 244:28] - node _T_675 = andr(_T_674) @[el2_lib.scala 244:36] - node _T_676 = and(_T_675, _T_585) @[el2_lib.scala 244:41] - node _T_677 = bits(io.trigger_pkt_any[2].tdata2, 13, 13) @[el2_lib.scala 244:74] - node _T_678 = bits(lsu_match_data_2, 13, 13) @[el2_lib.scala 244:86] - node _T_679 = eq(_T_677, _T_678) @[el2_lib.scala 244:78] - node _T_680 = mux(_T_676, UInt<1>("h01"), _T_679) @[el2_lib.scala 244:23] - _T_582[13] <= _T_680 @[el2_lib.scala 244:17] - node _T_681 = bits(io.trigger_pkt_any[2].tdata2, 13, 0) @[el2_lib.scala 244:28] - node _T_682 = andr(_T_681) @[el2_lib.scala 244:36] - node _T_683 = and(_T_682, _T_585) @[el2_lib.scala 244:41] - node _T_684 = bits(io.trigger_pkt_any[2].tdata2, 14, 14) @[el2_lib.scala 244:74] - node _T_685 = bits(lsu_match_data_2, 14, 14) @[el2_lib.scala 244:86] - node _T_686 = eq(_T_684, _T_685) @[el2_lib.scala 244:78] - node _T_687 = mux(_T_683, UInt<1>("h01"), _T_686) @[el2_lib.scala 244:23] - _T_582[14] <= _T_687 @[el2_lib.scala 244:17] - node _T_688 = bits(io.trigger_pkt_any[2].tdata2, 14, 0) @[el2_lib.scala 244:28] - node _T_689 = andr(_T_688) @[el2_lib.scala 244:36] - node _T_690 = and(_T_689, _T_585) @[el2_lib.scala 244:41] - node _T_691 = bits(io.trigger_pkt_any[2].tdata2, 15, 15) @[el2_lib.scala 244:74] - node _T_692 = bits(lsu_match_data_2, 15, 15) @[el2_lib.scala 244:86] - node _T_693 = eq(_T_691, _T_692) @[el2_lib.scala 244:78] - node _T_694 = mux(_T_690, UInt<1>("h01"), _T_693) @[el2_lib.scala 244:23] - _T_582[15] <= _T_694 @[el2_lib.scala 244:17] - node _T_695 = bits(io.trigger_pkt_any[2].tdata2, 15, 0) @[el2_lib.scala 244:28] - node _T_696 = andr(_T_695) @[el2_lib.scala 244:36] - node _T_697 = and(_T_696, _T_585) @[el2_lib.scala 244:41] - node _T_698 = bits(io.trigger_pkt_any[2].tdata2, 16, 16) @[el2_lib.scala 244:74] - node _T_699 = bits(lsu_match_data_2, 16, 16) @[el2_lib.scala 244:86] - node _T_700 = eq(_T_698, _T_699) @[el2_lib.scala 244:78] - node _T_701 = mux(_T_697, UInt<1>("h01"), _T_700) @[el2_lib.scala 244:23] - _T_582[16] <= _T_701 @[el2_lib.scala 244:17] - node _T_702 = bits(io.trigger_pkt_any[2].tdata2, 16, 0) @[el2_lib.scala 244:28] - node _T_703 = andr(_T_702) @[el2_lib.scala 244:36] - node _T_704 = and(_T_703, _T_585) @[el2_lib.scala 244:41] - node _T_705 = bits(io.trigger_pkt_any[2].tdata2, 17, 17) @[el2_lib.scala 244:74] - node _T_706 = bits(lsu_match_data_2, 17, 17) @[el2_lib.scala 244:86] - node _T_707 = eq(_T_705, _T_706) @[el2_lib.scala 244:78] - node _T_708 = mux(_T_704, UInt<1>("h01"), _T_707) @[el2_lib.scala 244:23] - _T_582[17] <= _T_708 @[el2_lib.scala 244:17] - node _T_709 = bits(io.trigger_pkt_any[2].tdata2, 17, 0) @[el2_lib.scala 244:28] - node _T_710 = andr(_T_709) @[el2_lib.scala 244:36] - node _T_711 = and(_T_710, _T_585) @[el2_lib.scala 244:41] - node _T_712 = bits(io.trigger_pkt_any[2].tdata2, 18, 18) @[el2_lib.scala 244:74] - node _T_713 = bits(lsu_match_data_2, 18, 18) @[el2_lib.scala 244:86] - node _T_714 = eq(_T_712, _T_713) @[el2_lib.scala 244:78] - node _T_715 = mux(_T_711, UInt<1>("h01"), _T_714) @[el2_lib.scala 244:23] - _T_582[18] <= _T_715 @[el2_lib.scala 244:17] - node _T_716 = bits(io.trigger_pkt_any[2].tdata2, 18, 0) @[el2_lib.scala 244:28] - node _T_717 = andr(_T_716) @[el2_lib.scala 244:36] - node _T_718 = and(_T_717, _T_585) @[el2_lib.scala 244:41] - node _T_719 = bits(io.trigger_pkt_any[2].tdata2, 19, 19) @[el2_lib.scala 244:74] - node _T_720 = bits(lsu_match_data_2, 19, 19) @[el2_lib.scala 244:86] - node _T_721 = eq(_T_719, _T_720) @[el2_lib.scala 244:78] - node _T_722 = mux(_T_718, UInt<1>("h01"), _T_721) @[el2_lib.scala 244:23] - _T_582[19] <= _T_722 @[el2_lib.scala 244:17] - node _T_723 = bits(io.trigger_pkt_any[2].tdata2, 19, 0) @[el2_lib.scala 244:28] - node _T_724 = andr(_T_723) @[el2_lib.scala 244:36] - node _T_725 = and(_T_724, _T_585) @[el2_lib.scala 244:41] - node _T_726 = bits(io.trigger_pkt_any[2].tdata2, 20, 20) @[el2_lib.scala 244:74] - node _T_727 = bits(lsu_match_data_2, 20, 20) @[el2_lib.scala 244:86] - node _T_728 = eq(_T_726, _T_727) @[el2_lib.scala 244:78] - node _T_729 = mux(_T_725, UInt<1>("h01"), _T_728) @[el2_lib.scala 244:23] - _T_582[20] <= _T_729 @[el2_lib.scala 244:17] - node _T_730 = bits(io.trigger_pkt_any[2].tdata2, 20, 0) @[el2_lib.scala 244:28] - node _T_731 = andr(_T_730) @[el2_lib.scala 244:36] - node _T_732 = and(_T_731, _T_585) @[el2_lib.scala 244:41] - node _T_733 = bits(io.trigger_pkt_any[2].tdata2, 21, 21) @[el2_lib.scala 244:74] - node _T_734 = bits(lsu_match_data_2, 21, 21) @[el2_lib.scala 244:86] - node _T_735 = eq(_T_733, _T_734) @[el2_lib.scala 244:78] - node _T_736 = mux(_T_732, UInt<1>("h01"), _T_735) @[el2_lib.scala 244:23] - _T_582[21] <= _T_736 @[el2_lib.scala 244:17] - node _T_737 = bits(io.trigger_pkt_any[2].tdata2, 21, 0) @[el2_lib.scala 244:28] - node _T_738 = andr(_T_737) @[el2_lib.scala 244:36] - node _T_739 = and(_T_738, _T_585) @[el2_lib.scala 244:41] - node _T_740 = bits(io.trigger_pkt_any[2].tdata2, 22, 22) @[el2_lib.scala 244:74] - node _T_741 = bits(lsu_match_data_2, 22, 22) @[el2_lib.scala 244:86] - node _T_742 = eq(_T_740, _T_741) @[el2_lib.scala 244:78] - node _T_743 = mux(_T_739, UInt<1>("h01"), _T_742) @[el2_lib.scala 244:23] - _T_582[22] <= _T_743 @[el2_lib.scala 244:17] - node _T_744 = bits(io.trigger_pkt_any[2].tdata2, 22, 0) @[el2_lib.scala 244:28] - node _T_745 = andr(_T_744) @[el2_lib.scala 244:36] - node _T_746 = and(_T_745, _T_585) @[el2_lib.scala 244:41] - node _T_747 = bits(io.trigger_pkt_any[2].tdata2, 23, 23) @[el2_lib.scala 244:74] - node _T_748 = bits(lsu_match_data_2, 23, 23) @[el2_lib.scala 244:86] - node _T_749 = eq(_T_747, _T_748) @[el2_lib.scala 244:78] - node _T_750 = mux(_T_746, UInt<1>("h01"), _T_749) @[el2_lib.scala 244:23] - _T_582[23] <= _T_750 @[el2_lib.scala 244:17] - node _T_751 = bits(io.trigger_pkt_any[2].tdata2, 23, 0) @[el2_lib.scala 244:28] - node _T_752 = andr(_T_751) @[el2_lib.scala 244:36] - node _T_753 = and(_T_752, _T_585) @[el2_lib.scala 244:41] - node _T_754 = bits(io.trigger_pkt_any[2].tdata2, 24, 24) @[el2_lib.scala 244:74] - node _T_755 = bits(lsu_match_data_2, 24, 24) @[el2_lib.scala 244:86] - node _T_756 = eq(_T_754, _T_755) @[el2_lib.scala 244:78] - node _T_757 = mux(_T_753, UInt<1>("h01"), _T_756) @[el2_lib.scala 244:23] - _T_582[24] <= _T_757 @[el2_lib.scala 244:17] - node _T_758 = bits(io.trigger_pkt_any[2].tdata2, 24, 0) @[el2_lib.scala 244:28] - node _T_759 = andr(_T_758) @[el2_lib.scala 244:36] - node _T_760 = and(_T_759, _T_585) @[el2_lib.scala 244:41] - node _T_761 = bits(io.trigger_pkt_any[2].tdata2, 25, 25) @[el2_lib.scala 244:74] - node _T_762 = bits(lsu_match_data_2, 25, 25) @[el2_lib.scala 244:86] - node _T_763 = eq(_T_761, _T_762) @[el2_lib.scala 244:78] - node _T_764 = mux(_T_760, UInt<1>("h01"), _T_763) @[el2_lib.scala 244:23] - _T_582[25] <= _T_764 @[el2_lib.scala 244:17] - node _T_765 = bits(io.trigger_pkt_any[2].tdata2, 25, 0) @[el2_lib.scala 244:28] - node _T_766 = andr(_T_765) @[el2_lib.scala 244:36] - node _T_767 = and(_T_766, _T_585) @[el2_lib.scala 244:41] - node _T_768 = bits(io.trigger_pkt_any[2].tdata2, 26, 26) @[el2_lib.scala 244:74] - node _T_769 = bits(lsu_match_data_2, 26, 26) @[el2_lib.scala 244:86] - node _T_770 = eq(_T_768, _T_769) @[el2_lib.scala 244:78] - node _T_771 = mux(_T_767, UInt<1>("h01"), _T_770) @[el2_lib.scala 244:23] - _T_582[26] <= _T_771 @[el2_lib.scala 244:17] - node _T_772 = bits(io.trigger_pkt_any[2].tdata2, 26, 0) @[el2_lib.scala 244:28] - node _T_773 = andr(_T_772) @[el2_lib.scala 244:36] - node _T_774 = and(_T_773, _T_585) @[el2_lib.scala 244:41] - node _T_775 = bits(io.trigger_pkt_any[2].tdata2, 27, 27) @[el2_lib.scala 244:74] - node _T_776 = bits(lsu_match_data_2, 27, 27) @[el2_lib.scala 244:86] - node _T_777 = eq(_T_775, _T_776) @[el2_lib.scala 244:78] - node _T_778 = mux(_T_774, UInt<1>("h01"), _T_777) @[el2_lib.scala 244:23] - _T_582[27] <= _T_778 @[el2_lib.scala 244:17] - node _T_779 = bits(io.trigger_pkt_any[2].tdata2, 27, 0) @[el2_lib.scala 244:28] - node _T_780 = andr(_T_779) @[el2_lib.scala 244:36] - node _T_781 = and(_T_780, _T_585) @[el2_lib.scala 244:41] - node _T_782 = bits(io.trigger_pkt_any[2].tdata2, 28, 28) @[el2_lib.scala 244:74] - node _T_783 = bits(lsu_match_data_2, 28, 28) @[el2_lib.scala 244:86] - node _T_784 = eq(_T_782, _T_783) @[el2_lib.scala 244:78] - node _T_785 = mux(_T_781, UInt<1>("h01"), _T_784) @[el2_lib.scala 244:23] - _T_582[28] <= _T_785 @[el2_lib.scala 244:17] - node _T_786 = bits(io.trigger_pkt_any[2].tdata2, 28, 0) @[el2_lib.scala 244:28] - node _T_787 = andr(_T_786) @[el2_lib.scala 244:36] - node _T_788 = and(_T_787, _T_585) @[el2_lib.scala 244:41] - node _T_789 = bits(io.trigger_pkt_any[2].tdata2, 29, 29) @[el2_lib.scala 244:74] - node _T_790 = bits(lsu_match_data_2, 29, 29) @[el2_lib.scala 244:86] - node _T_791 = eq(_T_789, _T_790) @[el2_lib.scala 244:78] - node _T_792 = mux(_T_788, UInt<1>("h01"), _T_791) @[el2_lib.scala 244:23] - _T_582[29] <= _T_792 @[el2_lib.scala 244:17] - node _T_793 = bits(io.trigger_pkt_any[2].tdata2, 29, 0) @[el2_lib.scala 244:28] - node _T_794 = andr(_T_793) @[el2_lib.scala 244:36] - node _T_795 = and(_T_794, _T_585) @[el2_lib.scala 244:41] - node _T_796 = bits(io.trigger_pkt_any[2].tdata2, 30, 30) @[el2_lib.scala 244:74] - node _T_797 = bits(lsu_match_data_2, 30, 30) @[el2_lib.scala 244:86] - node _T_798 = eq(_T_796, _T_797) @[el2_lib.scala 244:78] - node _T_799 = mux(_T_795, UInt<1>("h01"), _T_798) @[el2_lib.scala 244:23] - _T_582[30] <= _T_799 @[el2_lib.scala 244:17] - node _T_800 = bits(io.trigger_pkt_any[2].tdata2, 30, 0) @[el2_lib.scala 244:28] - node _T_801 = andr(_T_800) @[el2_lib.scala 244:36] - node _T_802 = and(_T_801, _T_585) @[el2_lib.scala 244:41] - node _T_803 = bits(io.trigger_pkt_any[2].tdata2, 31, 31) @[el2_lib.scala 244:74] - node _T_804 = bits(lsu_match_data_2, 31, 31) @[el2_lib.scala 244:86] - node _T_805 = eq(_T_803, _T_804) @[el2_lib.scala 244:78] - node _T_806 = mux(_T_802, UInt<1>("h01"), _T_805) @[el2_lib.scala 244:23] - _T_582[31] <= _T_806 @[el2_lib.scala 244:17] - node _T_807 = cat(_T_582[1], _T_582[0]) @[el2_lib.scala 245:14] - node _T_808 = cat(_T_582[3], _T_582[2]) @[el2_lib.scala 245:14] - node _T_809 = cat(_T_808, _T_807) @[el2_lib.scala 245:14] - node _T_810 = cat(_T_582[5], _T_582[4]) @[el2_lib.scala 245:14] - node _T_811 = cat(_T_582[7], _T_582[6]) @[el2_lib.scala 245:14] - node _T_812 = cat(_T_811, _T_810) @[el2_lib.scala 245:14] - node _T_813 = cat(_T_812, _T_809) @[el2_lib.scala 245:14] - node _T_814 = cat(_T_582[9], _T_582[8]) @[el2_lib.scala 245:14] - node _T_815 = cat(_T_582[11], _T_582[10]) @[el2_lib.scala 245:14] - node _T_816 = cat(_T_815, _T_814) @[el2_lib.scala 245:14] - node _T_817 = cat(_T_582[13], _T_582[12]) @[el2_lib.scala 245:14] - node _T_818 = cat(_T_582[15], _T_582[14]) @[el2_lib.scala 245:14] - node _T_819 = cat(_T_818, _T_817) @[el2_lib.scala 245:14] - node _T_820 = cat(_T_819, _T_816) @[el2_lib.scala 245:14] - node _T_821 = cat(_T_820, _T_813) @[el2_lib.scala 245:14] - node _T_822 = cat(_T_582[17], _T_582[16]) @[el2_lib.scala 245:14] - node _T_823 = cat(_T_582[19], _T_582[18]) @[el2_lib.scala 245:14] - node _T_824 = cat(_T_823, _T_822) @[el2_lib.scala 245:14] - node _T_825 = cat(_T_582[21], _T_582[20]) @[el2_lib.scala 245:14] - node _T_826 = cat(_T_582[23], _T_582[22]) @[el2_lib.scala 245:14] - node _T_827 = cat(_T_826, _T_825) @[el2_lib.scala 245:14] - node _T_828 = cat(_T_827, _T_824) @[el2_lib.scala 245:14] - node _T_829 = cat(_T_582[25], _T_582[24]) @[el2_lib.scala 245:14] - node _T_830 = cat(_T_582[27], _T_582[26]) @[el2_lib.scala 245:14] - node _T_831 = cat(_T_830, _T_829) @[el2_lib.scala 245:14] - node _T_832 = cat(_T_582[29], _T_582[28]) @[el2_lib.scala 245:14] - node _T_833 = cat(_T_582[31], _T_582[30]) @[el2_lib.scala 245:14] - node _T_834 = cat(_T_833, _T_832) @[el2_lib.scala 245:14] - node _T_835 = cat(_T_834, _T_831) @[el2_lib.scala 245:14] - node _T_836 = cat(_T_835, _T_828) @[el2_lib.scala 245:14] - node _T_837 = cat(_T_836, _T_821) @[el2_lib.scala 245:14] - node _T_838 = andr(_T_837) @[el2_lib.scala 245:25] + wire _T_582 : UInt<1>[32] @[lib.scala 100:24] + node _T_583 = andr(io.trigger_pkt_any[2].tdata2) @[lib.scala 101:45] + node _T_584 = not(_T_583) @[lib.scala 101:39] + node _T_585 = and(_T_581, _T_584) @[lib.scala 101:37] + node _T_586 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[lib.scala 102:48] + node _T_587 = bits(lsu_match_data_2, 0, 0) @[lib.scala 102:60] + node _T_588 = eq(_T_586, _T_587) @[lib.scala 102:52] + node _T_589 = or(_T_585, _T_588) @[lib.scala 102:41] + _T_582[0] <= _T_589 @[lib.scala 102:18] + node _T_590 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[lib.scala 104:28] + node _T_591 = andr(_T_590) @[lib.scala 104:36] + node _T_592 = and(_T_591, _T_585) @[lib.scala 104:41] + node _T_593 = bits(io.trigger_pkt_any[2].tdata2, 1, 1) @[lib.scala 104:74] + node _T_594 = bits(lsu_match_data_2, 1, 1) @[lib.scala 104:86] + node _T_595 = eq(_T_593, _T_594) @[lib.scala 104:78] + node _T_596 = mux(_T_592, UInt<1>("h01"), _T_595) @[lib.scala 104:23] + _T_582[1] <= _T_596 @[lib.scala 104:17] + node _T_597 = bits(io.trigger_pkt_any[2].tdata2, 1, 0) @[lib.scala 104:28] + node _T_598 = andr(_T_597) @[lib.scala 104:36] + node _T_599 = and(_T_598, _T_585) @[lib.scala 104:41] + node _T_600 = bits(io.trigger_pkt_any[2].tdata2, 2, 2) @[lib.scala 104:74] + node _T_601 = bits(lsu_match_data_2, 2, 2) @[lib.scala 104:86] + node _T_602 = eq(_T_600, _T_601) @[lib.scala 104:78] + node _T_603 = mux(_T_599, UInt<1>("h01"), _T_602) @[lib.scala 104:23] + _T_582[2] <= _T_603 @[lib.scala 104:17] + node _T_604 = bits(io.trigger_pkt_any[2].tdata2, 2, 0) @[lib.scala 104:28] + node _T_605 = andr(_T_604) @[lib.scala 104:36] + node _T_606 = and(_T_605, _T_585) @[lib.scala 104:41] + node _T_607 = bits(io.trigger_pkt_any[2].tdata2, 3, 3) @[lib.scala 104:74] + node _T_608 = bits(lsu_match_data_2, 3, 3) @[lib.scala 104:86] + node _T_609 = eq(_T_607, _T_608) @[lib.scala 104:78] + node _T_610 = mux(_T_606, UInt<1>("h01"), _T_609) @[lib.scala 104:23] + _T_582[3] <= _T_610 @[lib.scala 104:17] + node _T_611 = bits(io.trigger_pkt_any[2].tdata2, 3, 0) @[lib.scala 104:28] + node _T_612 = andr(_T_611) @[lib.scala 104:36] + node _T_613 = and(_T_612, _T_585) @[lib.scala 104:41] + node _T_614 = bits(io.trigger_pkt_any[2].tdata2, 4, 4) @[lib.scala 104:74] + node _T_615 = bits(lsu_match_data_2, 4, 4) @[lib.scala 104:86] + node _T_616 = eq(_T_614, _T_615) @[lib.scala 104:78] + node _T_617 = mux(_T_613, UInt<1>("h01"), _T_616) @[lib.scala 104:23] + _T_582[4] <= _T_617 @[lib.scala 104:17] + node _T_618 = bits(io.trigger_pkt_any[2].tdata2, 4, 0) @[lib.scala 104:28] + node _T_619 = andr(_T_618) @[lib.scala 104:36] + node _T_620 = and(_T_619, _T_585) @[lib.scala 104:41] + node _T_621 = bits(io.trigger_pkt_any[2].tdata2, 5, 5) @[lib.scala 104:74] + node _T_622 = bits(lsu_match_data_2, 5, 5) @[lib.scala 104:86] + node _T_623 = eq(_T_621, _T_622) @[lib.scala 104:78] + node _T_624 = mux(_T_620, UInt<1>("h01"), _T_623) @[lib.scala 104:23] + _T_582[5] <= _T_624 @[lib.scala 104:17] + node _T_625 = bits(io.trigger_pkt_any[2].tdata2, 5, 0) @[lib.scala 104:28] + node _T_626 = andr(_T_625) @[lib.scala 104:36] + node _T_627 = and(_T_626, _T_585) @[lib.scala 104:41] + node _T_628 = bits(io.trigger_pkt_any[2].tdata2, 6, 6) @[lib.scala 104:74] + node _T_629 = bits(lsu_match_data_2, 6, 6) @[lib.scala 104:86] + node _T_630 = eq(_T_628, _T_629) @[lib.scala 104:78] + node _T_631 = mux(_T_627, UInt<1>("h01"), _T_630) @[lib.scala 104:23] + _T_582[6] <= _T_631 @[lib.scala 104:17] + node _T_632 = bits(io.trigger_pkt_any[2].tdata2, 6, 0) @[lib.scala 104:28] + node _T_633 = andr(_T_632) @[lib.scala 104:36] + node _T_634 = and(_T_633, _T_585) @[lib.scala 104:41] + node _T_635 = bits(io.trigger_pkt_any[2].tdata2, 7, 7) @[lib.scala 104:74] + node _T_636 = bits(lsu_match_data_2, 7, 7) @[lib.scala 104:86] + node _T_637 = eq(_T_635, _T_636) @[lib.scala 104:78] + node _T_638 = mux(_T_634, UInt<1>("h01"), _T_637) @[lib.scala 104:23] + _T_582[7] <= _T_638 @[lib.scala 104:17] + node _T_639 = bits(io.trigger_pkt_any[2].tdata2, 7, 0) @[lib.scala 104:28] + node _T_640 = andr(_T_639) @[lib.scala 104:36] + node _T_641 = and(_T_640, _T_585) @[lib.scala 104:41] + node _T_642 = bits(io.trigger_pkt_any[2].tdata2, 8, 8) @[lib.scala 104:74] + node _T_643 = bits(lsu_match_data_2, 8, 8) @[lib.scala 104:86] + node _T_644 = eq(_T_642, _T_643) @[lib.scala 104:78] + node _T_645 = mux(_T_641, UInt<1>("h01"), _T_644) @[lib.scala 104:23] + _T_582[8] <= _T_645 @[lib.scala 104:17] + node _T_646 = bits(io.trigger_pkt_any[2].tdata2, 8, 0) @[lib.scala 104:28] + node _T_647 = andr(_T_646) @[lib.scala 104:36] + node _T_648 = and(_T_647, _T_585) @[lib.scala 104:41] + node _T_649 = bits(io.trigger_pkt_any[2].tdata2, 9, 9) @[lib.scala 104:74] + node _T_650 = bits(lsu_match_data_2, 9, 9) @[lib.scala 104:86] + node _T_651 = eq(_T_649, _T_650) @[lib.scala 104:78] + node _T_652 = mux(_T_648, UInt<1>("h01"), _T_651) @[lib.scala 104:23] + _T_582[9] <= _T_652 @[lib.scala 104:17] + node _T_653 = bits(io.trigger_pkt_any[2].tdata2, 9, 0) @[lib.scala 104:28] + node _T_654 = andr(_T_653) @[lib.scala 104:36] + node _T_655 = and(_T_654, _T_585) @[lib.scala 104:41] + node _T_656 = bits(io.trigger_pkt_any[2].tdata2, 10, 10) @[lib.scala 104:74] + node _T_657 = bits(lsu_match_data_2, 10, 10) @[lib.scala 104:86] + node _T_658 = eq(_T_656, _T_657) @[lib.scala 104:78] + node _T_659 = mux(_T_655, UInt<1>("h01"), _T_658) @[lib.scala 104:23] + _T_582[10] <= _T_659 @[lib.scala 104:17] + node _T_660 = bits(io.trigger_pkt_any[2].tdata2, 10, 0) @[lib.scala 104:28] + node _T_661 = andr(_T_660) @[lib.scala 104:36] + node _T_662 = and(_T_661, _T_585) @[lib.scala 104:41] + node _T_663 = bits(io.trigger_pkt_any[2].tdata2, 11, 11) @[lib.scala 104:74] + node _T_664 = bits(lsu_match_data_2, 11, 11) @[lib.scala 104:86] + node _T_665 = eq(_T_663, _T_664) @[lib.scala 104:78] + node _T_666 = mux(_T_662, UInt<1>("h01"), _T_665) @[lib.scala 104:23] + _T_582[11] <= _T_666 @[lib.scala 104:17] + node _T_667 = bits(io.trigger_pkt_any[2].tdata2, 11, 0) @[lib.scala 104:28] + node _T_668 = andr(_T_667) @[lib.scala 104:36] + node _T_669 = and(_T_668, _T_585) @[lib.scala 104:41] + node _T_670 = bits(io.trigger_pkt_any[2].tdata2, 12, 12) @[lib.scala 104:74] + node _T_671 = bits(lsu_match_data_2, 12, 12) @[lib.scala 104:86] + node _T_672 = eq(_T_670, _T_671) @[lib.scala 104:78] + node _T_673 = mux(_T_669, UInt<1>("h01"), _T_672) @[lib.scala 104:23] + _T_582[12] <= _T_673 @[lib.scala 104:17] + node _T_674 = bits(io.trigger_pkt_any[2].tdata2, 12, 0) @[lib.scala 104:28] + node _T_675 = andr(_T_674) @[lib.scala 104:36] + node _T_676 = and(_T_675, _T_585) @[lib.scala 104:41] + node _T_677 = bits(io.trigger_pkt_any[2].tdata2, 13, 13) @[lib.scala 104:74] + node _T_678 = bits(lsu_match_data_2, 13, 13) @[lib.scala 104:86] + node _T_679 = eq(_T_677, _T_678) @[lib.scala 104:78] + node _T_680 = mux(_T_676, UInt<1>("h01"), _T_679) @[lib.scala 104:23] + _T_582[13] <= _T_680 @[lib.scala 104:17] + node _T_681 = bits(io.trigger_pkt_any[2].tdata2, 13, 0) @[lib.scala 104:28] + node _T_682 = andr(_T_681) @[lib.scala 104:36] + node _T_683 = and(_T_682, _T_585) @[lib.scala 104:41] + node _T_684 = bits(io.trigger_pkt_any[2].tdata2, 14, 14) @[lib.scala 104:74] + node _T_685 = bits(lsu_match_data_2, 14, 14) @[lib.scala 104:86] + node _T_686 = eq(_T_684, _T_685) @[lib.scala 104:78] + node _T_687 = mux(_T_683, UInt<1>("h01"), _T_686) @[lib.scala 104:23] + _T_582[14] <= _T_687 @[lib.scala 104:17] + node _T_688 = bits(io.trigger_pkt_any[2].tdata2, 14, 0) @[lib.scala 104:28] + node _T_689 = andr(_T_688) @[lib.scala 104:36] + node _T_690 = and(_T_689, _T_585) @[lib.scala 104:41] + node _T_691 = bits(io.trigger_pkt_any[2].tdata2, 15, 15) @[lib.scala 104:74] + node _T_692 = bits(lsu_match_data_2, 15, 15) @[lib.scala 104:86] + node _T_693 = eq(_T_691, _T_692) @[lib.scala 104:78] + node _T_694 = mux(_T_690, UInt<1>("h01"), _T_693) @[lib.scala 104:23] + _T_582[15] <= _T_694 @[lib.scala 104:17] + node _T_695 = bits(io.trigger_pkt_any[2].tdata2, 15, 0) @[lib.scala 104:28] + node _T_696 = andr(_T_695) @[lib.scala 104:36] + node _T_697 = and(_T_696, _T_585) @[lib.scala 104:41] + node _T_698 = bits(io.trigger_pkt_any[2].tdata2, 16, 16) @[lib.scala 104:74] + node _T_699 = bits(lsu_match_data_2, 16, 16) @[lib.scala 104:86] + node _T_700 = eq(_T_698, _T_699) @[lib.scala 104:78] + node _T_701 = mux(_T_697, UInt<1>("h01"), _T_700) @[lib.scala 104:23] + _T_582[16] <= _T_701 @[lib.scala 104:17] + node _T_702 = bits(io.trigger_pkt_any[2].tdata2, 16, 0) @[lib.scala 104:28] + node _T_703 = andr(_T_702) @[lib.scala 104:36] + node _T_704 = and(_T_703, _T_585) @[lib.scala 104:41] + node _T_705 = bits(io.trigger_pkt_any[2].tdata2, 17, 17) @[lib.scala 104:74] + node _T_706 = bits(lsu_match_data_2, 17, 17) @[lib.scala 104:86] + node _T_707 = eq(_T_705, _T_706) @[lib.scala 104:78] + node _T_708 = mux(_T_704, UInt<1>("h01"), _T_707) @[lib.scala 104:23] + _T_582[17] <= _T_708 @[lib.scala 104:17] + node _T_709 = bits(io.trigger_pkt_any[2].tdata2, 17, 0) @[lib.scala 104:28] + node _T_710 = andr(_T_709) @[lib.scala 104:36] + node _T_711 = and(_T_710, _T_585) @[lib.scala 104:41] + node _T_712 = bits(io.trigger_pkt_any[2].tdata2, 18, 18) @[lib.scala 104:74] + node _T_713 = bits(lsu_match_data_2, 18, 18) @[lib.scala 104:86] + node _T_714 = eq(_T_712, _T_713) @[lib.scala 104:78] + node _T_715 = mux(_T_711, UInt<1>("h01"), _T_714) @[lib.scala 104:23] + _T_582[18] <= _T_715 @[lib.scala 104:17] + node _T_716 = bits(io.trigger_pkt_any[2].tdata2, 18, 0) @[lib.scala 104:28] + node _T_717 = andr(_T_716) @[lib.scala 104:36] + node _T_718 = and(_T_717, _T_585) @[lib.scala 104:41] + node _T_719 = bits(io.trigger_pkt_any[2].tdata2, 19, 19) @[lib.scala 104:74] + node _T_720 = bits(lsu_match_data_2, 19, 19) @[lib.scala 104:86] + node _T_721 = eq(_T_719, _T_720) @[lib.scala 104:78] + node _T_722 = mux(_T_718, UInt<1>("h01"), _T_721) @[lib.scala 104:23] + _T_582[19] <= _T_722 @[lib.scala 104:17] + node _T_723 = bits(io.trigger_pkt_any[2].tdata2, 19, 0) @[lib.scala 104:28] + node _T_724 = andr(_T_723) @[lib.scala 104:36] + node _T_725 = and(_T_724, _T_585) @[lib.scala 104:41] + node _T_726 = bits(io.trigger_pkt_any[2].tdata2, 20, 20) @[lib.scala 104:74] + node _T_727 = bits(lsu_match_data_2, 20, 20) @[lib.scala 104:86] + node _T_728 = eq(_T_726, _T_727) @[lib.scala 104:78] + node _T_729 = mux(_T_725, UInt<1>("h01"), _T_728) @[lib.scala 104:23] + _T_582[20] <= _T_729 @[lib.scala 104:17] + node _T_730 = bits(io.trigger_pkt_any[2].tdata2, 20, 0) @[lib.scala 104:28] + node _T_731 = andr(_T_730) @[lib.scala 104:36] + node _T_732 = and(_T_731, _T_585) @[lib.scala 104:41] + node _T_733 = bits(io.trigger_pkt_any[2].tdata2, 21, 21) @[lib.scala 104:74] + node _T_734 = bits(lsu_match_data_2, 21, 21) @[lib.scala 104:86] + node _T_735 = eq(_T_733, _T_734) @[lib.scala 104:78] + node _T_736 = mux(_T_732, UInt<1>("h01"), _T_735) @[lib.scala 104:23] + _T_582[21] <= _T_736 @[lib.scala 104:17] + node _T_737 = bits(io.trigger_pkt_any[2].tdata2, 21, 0) @[lib.scala 104:28] + node _T_738 = andr(_T_737) @[lib.scala 104:36] + node _T_739 = and(_T_738, _T_585) @[lib.scala 104:41] + node _T_740 = bits(io.trigger_pkt_any[2].tdata2, 22, 22) @[lib.scala 104:74] + node _T_741 = bits(lsu_match_data_2, 22, 22) @[lib.scala 104:86] + node _T_742 = eq(_T_740, _T_741) @[lib.scala 104:78] + node _T_743 = mux(_T_739, UInt<1>("h01"), _T_742) @[lib.scala 104:23] + _T_582[22] <= _T_743 @[lib.scala 104:17] + node _T_744 = bits(io.trigger_pkt_any[2].tdata2, 22, 0) @[lib.scala 104:28] + node _T_745 = andr(_T_744) @[lib.scala 104:36] + node _T_746 = and(_T_745, _T_585) @[lib.scala 104:41] + node _T_747 = bits(io.trigger_pkt_any[2].tdata2, 23, 23) @[lib.scala 104:74] + node _T_748 = bits(lsu_match_data_2, 23, 23) @[lib.scala 104:86] + node _T_749 = eq(_T_747, _T_748) @[lib.scala 104:78] + node _T_750 = mux(_T_746, UInt<1>("h01"), _T_749) @[lib.scala 104:23] + _T_582[23] <= _T_750 @[lib.scala 104:17] + node _T_751 = bits(io.trigger_pkt_any[2].tdata2, 23, 0) @[lib.scala 104:28] + node _T_752 = andr(_T_751) @[lib.scala 104:36] + node _T_753 = and(_T_752, _T_585) @[lib.scala 104:41] + node _T_754 = bits(io.trigger_pkt_any[2].tdata2, 24, 24) @[lib.scala 104:74] + node _T_755 = bits(lsu_match_data_2, 24, 24) @[lib.scala 104:86] + node _T_756 = eq(_T_754, _T_755) @[lib.scala 104:78] + node _T_757 = mux(_T_753, UInt<1>("h01"), _T_756) @[lib.scala 104:23] + _T_582[24] <= _T_757 @[lib.scala 104:17] + node _T_758 = bits(io.trigger_pkt_any[2].tdata2, 24, 0) @[lib.scala 104:28] + node _T_759 = andr(_T_758) @[lib.scala 104:36] + node _T_760 = and(_T_759, _T_585) @[lib.scala 104:41] + node _T_761 = bits(io.trigger_pkt_any[2].tdata2, 25, 25) @[lib.scala 104:74] + node _T_762 = bits(lsu_match_data_2, 25, 25) @[lib.scala 104:86] + node _T_763 = eq(_T_761, _T_762) @[lib.scala 104:78] + node _T_764 = mux(_T_760, UInt<1>("h01"), _T_763) @[lib.scala 104:23] + _T_582[25] <= _T_764 @[lib.scala 104:17] + node _T_765 = bits(io.trigger_pkt_any[2].tdata2, 25, 0) @[lib.scala 104:28] + node _T_766 = andr(_T_765) @[lib.scala 104:36] + node _T_767 = and(_T_766, _T_585) @[lib.scala 104:41] + node _T_768 = bits(io.trigger_pkt_any[2].tdata2, 26, 26) @[lib.scala 104:74] + node _T_769 = bits(lsu_match_data_2, 26, 26) @[lib.scala 104:86] + node _T_770 = eq(_T_768, _T_769) @[lib.scala 104:78] + node _T_771 = mux(_T_767, UInt<1>("h01"), _T_770) @[lib.scala 104:23] + _T_582[26] <= _T_771 @[lib.scala 104:17] + node _T_772 = bits(io.trigger_pkt_any[2].tdata2, 26, 0) @[lib.scala 104:28] + node _T_773 = andr(_T_772) @[lib.scala 104:36] + node _T_774 = and(_T_773, _T_585) @[lib.scala 104:41] + node _T_775 = bits(io.trigger_pkt_any[2].tdata2, 27, 27) @[lib.scala 104:74] + node _T_776 = bits(lsu_match_data_2, 27, 27) @[lib.scala 104:86] + node _T_777 = eq(_T_775, _T_776) @[lib.scala 104:78] + node _T_778 = mux(_T_774, UInt<1>("h01"), _T_777) @[lib.scala 104:23] + _T_582[27] <= _T_778 @[lib.scala 104:17] + node _T_779 = bits(io.trigger_pkt_any[2].tdata2, 27, 0) @[lib.scala 104:28] + node _T_780 = andr(_T_779) @[lib.scala 104:36] + node _T_781 = and(_T_780, _T_585) @[lib.scala 104:41] + node _T_782 = bits(io.trigger_pkt_any[2].tdata2, 28, 28) @[lib.scala 104:74] + node _T_783 = bits(lsu_match_data_2, 28, 28) @[lib.scala 104:86] + node _T_784 = eq(_T_782, _T_783) @[lib.scala 104:78] + node _T_785 = mux(_T_781, UInt<1>("h01"), _T_784) @[lib.scala 104:23] + _T_582[28] <= _T_785 @[lib.scala 104:17] + node _T_786 = bits(io.trigger_pkt_any[2].tdata2, 28, 0) @[lib.scala 104:28] + node _T_787 = andr(_T_786) @[lib.scala 104:36] + node _T_788 = and(_T_787, _T_585) @[lib.scala 104:41] + node _T_789 = bits(io.trigger_pkt_any[2].tdata2, 29, 29) @[lib.scala 104:74] + node _T_790 = bits(lsu_match_data_2, 29, 29) @[lib.scala 104:86] + node _T_791 = eq(_T_789, _T_790) @[lib.scala 104:78] + node _T_792 = mux(_T_788, UInt<1>("h01"), _T_791) @[lib.scala 104:23] + _T_582[29] <= _T_792 @[lib.scala 104:17] + node _T_793 = bits(io.trigger_pkt_any[2].tdata2, 29, 0) @[lib.scala 104:28] + node _T_794 = andr(_T_793) @[lib.scala 104:36] + node _T_795 = and(_T_794, _T_585) @[lib.scala 104:41] + node _T_796 = bits(io.trigger_pkt_any[2].tdata2, 30, 30) @[lib.scala 104:74] + node _T_797 = bits(lsu_match_data_2, 30, 30) @[lib.scala 104:86] + node _T_798 = eq(_T_796, _T_797) @[lib.scala 104:78] + node _T_799 = mux(_T_795, UInt<1>("h01"), _T_798) @[lib.scala 104:23] + _T_582[30] <= _T_799 @[lib.scala 104:17] + node _T_800 = bits(io.trigger_pkt_any[2].tdata2, 30, 0) @[lib.scala 104:28] + node _T_801 = andr(_T_800) @[lib.scala 104:36] + node _T_802 = and(_T_801, _T_585) @[lib.scala 104:41] + node _T_803 = bits(io.trigger_pkt_any[2].tdata2, 31, 31) @[lib.scala 104:74] + node _T_804 = bits(lsu_match_data_2, 31, 31) @[lib.scala 104:86] + node _T_805 = eq(_T_803, _T_804) @[lib.scala 104:78] + node _T_806 = mux(_T_802, UInt<1>("h01"), _T_805) @[lib.scala 104:23] + _T_582[31] <= _T_806 @[lib.scala 104:17] + node _T_807 = cat(_T_582[1], _T_582[0]) @[lib.scala 105:14] + node _T_808 = cat(_T_582[3], _T_582[2]) @[lib.scala 105:14] + node _T_809 = cat(_T_808, _T_807) @[lib.scala 105:14] + node _T_810 = cat(_T_582[5], _T_582[4]) @[lib.scala 105:14] + node _T_811 = cat(_T_582[7], _T_582[6]) @[lib.scala 105:14] + node _T_812 = cat(_T_811, _T_810) @[lib.scala 105:14] + node _T_813 = cat(_T_812, _T_809) @[lib.scala 105:14] + node _T_814 = cat(_T_582[9], _T_582[8]) @[lib.scala 105:14] + node _T_815 = cat(_T_582[11], _T_582[10]) @[lib.scala 105:14] + node _T_816 = cat(_T_815, _T_814) @[lib.scala 105:14] + node _T_817 = cat(_T_582[13], _T_582[12]) @[lib.scala 105:14] + node _T_818 = cat(_T_582[15], _T_582[14]) @[lib.scala 105:14] + node _T_819 = cat(_T_818, _T_817) @[lib.scala 105:14] + node _T_820 = cat(_T_819, _T_816) @[lib.scala 105:14] + node _T_821 = cat(_T_820, _T_813) @[lib.scala 105:14] + node _T_822 = cat(_T_582[17], _T_582[16]) @[lib.scala 105:14] + node _T_823 = cat(_T_582[19], _T_582[18]) @[lib.scala 105:14] + node _T_824 = cat(_T_823, _T_822) @[lib.scala 105:14] + node _T_825 = cat(_T_582[21], _T_582[20]) @[lib.scala 105:14] + node _T_826 = cat(_T_582[23], _T_582[22]) @[lib.scala 105:14] + node _T_827 = cat(_T_826, _T_825) @[lib.scala 105:14] + node _T_828 = cat(_T_827, _T_824) @[lib.scala 105:14] + node _T_829 = cat(_T_582[25], _T_582[24]) @[lib.scala 105:14] + node _T_830 = cat(_T_582[27], _T_582[26]) @[lib.scala 105:14] + node _T_831 = cat(_T_830, _T_829) @[lib.scala 105:14] + node _T_832 = cat(_T_582[29], _T_582[28]) @[lib.scala 105:14] + node _T_833 = cat(_T_582[31], _T_582[30]) @[lib.scala 105:14] + node _T_834 = cat(_T_833, _T_832) @[lib.scala 105:14] + node _T_835 = cat(_T_834, _T_831) @[lib.scala 105:14] + node _T_836 = cat(_T_835, _T_828) @[lib.scala 105:14] + node _T_837 = cat(_T_836, _T_821) @[lib.scala 105:14] + node _T_838 = andr(_T_837) @[lib.scala 105:25] node _T_839 = and(_T_580, _T_838) @[lsu_trigger.scala 19:92] node _T_840 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_trigger.scala 18:71] node _T_841 = and(io.lsu_pkt_m.valid, _T_840) @[lsu_trigger.scala 18:69] @@ -93919,295 +93911,295 @@ circuit quasar_wrapper : node _T_846 = or(_T_842, _T_845) @[lsu_trigger.scala 18:152] node _T_847 = and(_T_841, _T_846) @[lsu_trigger.scala 18:94] node _T_848 = bits(io.trigger_pkt_any[3].match_pkt, 0, 0) @[lsu_trigger.scala 20:107] - wire _T_849 : UInt<1>[32] @[el2_lib.scala 240:24] - node _T_850 = andr(io.trigger_pkt_any[3].tdata2) @[el2_lib.scala 241:45] - node _T_851 = not(_T_850) @[el2_lib.scala 241:39] - node _T_852 = and(_T_848, _T_851) @[el2_lib.scala 241:37] - node _T_853 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[el2_lib.scala 242:48] - node _T_854 = bits(lsu_match_data_3, 0, 0) @[el2_lib.scala 242:60] - node _T_855 = eq(_T_853, _T_854) @[el2_lib.scala 242:52] - node _T_856 = or(_T_852, _T_855) @[el2_lib.scala 242:41] - _T_849[0] <= _T_856 @[el2_lib.scala 242:18] - node _T_857 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[el2_lib.scala 244:28] - node _T_858 = andr(_T_857) @[el2_lib.scala 244:36] - node _T_859 = and(_T_858, _T_852) @[el2_lib.scala 244:41] - node _T_860 = bits(io.trigger_pkt_any[3].tdata2, 1, 1) @[el2_lib.scala 244:74] - node _T_861 = bits(lsu_match_data_3, 1, 1) @[el2_lib.scala 244:86] - node _T_862 = eq(_T_860, _T_861) @[el2_lib.scala 244:78] - node _T_863 = mux(_T_859, UInt<1>("h01"), _T_862) @[el2_lib.scala 244:23] - _T_849[1] <= _T_863 @[el2_lib.scala 244:17] - node _T_864 = bits(io.trigger_pkt_any[3].tdata2, 1, 0) @[el2_lib.scala 244:28] - node _T_865 = andr(_T_864) @[el2_lib.scala 244:36] - node _T_866 = and(_T_865, _T_852) @[el2_lib.scala 244:41] - node _T_867 = bits(io.trigger_pkt_any[3].tdata2, 2, 2) @[el2_lib.scala 244:74] - node _T_868 = bits(lsu_match_data_3, 2, 2) @[el2_lib.scala 244:86] - node _T_869 = eq(_T_867, _T_868) @[el2_lib.scala 244:78] - node _T_870 = mux(_T_866, UInt<1>("h01"), _T_869) @[el2_lib.scala 244:23] - _T_849[2] <= _T_870 @[el2_lib.scala 244:17] - node _T_871 = bits(io.trigger_pkt_any[3].tdata2, 2, 0) @[el2_lib.scala 244:28] - node _T_872 = andr(_T_871) @[el2_lib.scala 244:36] - node _T_873 = and(_T_872, _T_852) @[el2_lib.scala 244:41] - node _T_874 = bits(io.trigger_pkt_any[3].tdata2, 3, 3) @[el2_lib.scala 244:74] - node _T_875 = bits(lsu_match_data_3, 3, 3) @[el2_lib.scala 244:86] - node _T_876 = eq(_T_874, _T_875) @[el2_lib.scala 244:78] - node _T_877 = mux(_T_873, UInt<1>("h01"), _T_876) @[el2_lib.scala 244:23] - _T_849[3] <= _T_877 @[el2_lib.scala 244:17] - node _T_878 = bits(io.trigger_pkt_any[3].tdata2, 3, 0) @[el2_lib.scala 244:28] - node _T_879 = andr(_T_878) @[el2_lib.scala 244:36] - node _T_880 = and(_T_879, _T_852) @[el2_lib.scala 244:41] - node _T_881 = bits(io.trigger_pkt_any[3].tdata2, 4, 4) @[el2_lib.scala 244:74] - node _T_882 = bits(lsu_match_data_3, 4, 4) @[el2_lib.scala 244:86] - node _T_883 = eq(_T_881, _T_882) @[el2_lib.scala 244:78] - node _T_884 = mux(_T_880, UInt<1>("h01"), _T_883) @[el2_lib.scala 244:23] - _T_849[4] <= _T_884 @[el2_lib.scala 244:17] - node _T_885 = bits(io.trigger_pkt_any[3].tdata2, 4, 0) @[el2_lib.scala 244:28] - node _T_886 = andr(_T_885) @[el2_lib.scala 244:36] - node _T_887 = and(_T_886, _T_852) @[el2_lib.scala 244:41] - node _T_888 = bits(io.trigger_pkt_any[3].tdata2, 5, 5) @[el2_lib.scala 244:74] - node _T_889 = bits(lsu_match_data_3, 5, 5) @[el2_lib.scala 244:86] - node _T_890 = eq(_T_888, _T_889) @[el2_lib.scala 244:78] - node _T_891 = mux(_T_887, UInt<1>("h01"), _T_890) @[el2_lib.scala 244:23] - _T_849[5] <= _T_891 @[el2_lib.scala 244:17] - node _T_892 = bits(io.trigger_pkt_any[3].tdata2, 5, 0) @[el2_lib.scala 244:28] - node _T_893 = andr(_T_892) @[el2_lib.scala 244:36] - node _T_894 = and(_T_893, _T_852) @[el2_lib.scala 244:41] - node _T_895 = bits(io.trigger_pkt_any[3].tdata2, 6, 6) @[el2_lib.scala 244:74] - node _T_896 = bits(lsu_match_data_3, 6, 6) @[el2_lib.scala 244:86] - node _T_897 = eq(_T_895, _T_896) @[el2_lib.scala 244:78] - node _T_898 = mux(_T_894, UInt<1>("h01"), _T_897) @[el2_lib.scala 244:23] - _T_849[6] <= _T_898 @[el2_lib.scala 244:17] - node _T_899 = bits(io.trigger_pkt_any[3].tdata2, 6, 0) @[el2_lib.scala 244:28] - node _T_900 = andr(_T_899) @[el2_lib.scala 244:36] - node _T_901 = and(_T_900, _T_852) @[el2_lib.scala 244:41] - node _T_902 = bits(io.trigger_pkt_any[3].tdata2, 7, 7) @[el2_lib.scala 244:74] - node _T_903 = bits(lsu_match_data_3, 7, 7) @[el2_lib.scala 244:86] - node _T_904 = eq(_T_902, _T_903) @[el2_lib.scala 244:78] - node _T_905 = mux(_T_901, UInt<1>("h01"), _T_904) @[el2_lib.scala 244:23] - _T_849[7] <= _T_905 @[el2_lib.scala 244:17] - node _T_906 = bits(io.trigger_pkt_any[3].tdata2, 7, 0) @[el2_lib.scala 244:28] - node _T_907 = andr(_T_906) @[el2_lib.scala 244:36] - node _T_908 = and(_T_907, _T_852) @[el2_lib.scala 244:41] - node _T_909 = bits(io.trigger_pkt_any[3].tdata2, 8, 8) @[el2_lib.scala 244:74] - node _T_910 = bits(lsu_match_data_3, 8, 8) @[el2_lib.scala 244:86] - node _T_911 = eq(_T_909, _T_910) @[el2_lib.scala 244:78] - node _T_912 = mux(_T_908, UInt<1>("h01"), _T_911) @[el2_lib.scala 244:23] - _T_849[8] <= _T_912 @[el2_lib.scala 244:17] - node _T_913 = bits(io.trigger_pkt_any[3].tdata2, 8, 0) @[el2_lib.scala 244:28] - node _T_914 = andr(_T_913) @[el2_lib.scala 244:36] - node _T_915 = and(_T_914, _T_852) @[el2_lib.scala 244:41] - node _T_916 = bits(io.trigger_pkt_any[3].tdata2, 9, 9) @[el2_lib.scala 244:74] - node _T_917 = bits(lsu_match_data_3, 9, 9) @[el2_lib.scala 244:86] - node _T_918 = eq(_T_916, _T_917) @[el2_lib.scala 244:78] - node _T_919 = mux(_T_915, UInt<1>("h01"), _T_918) @[el2_lib.scala 244:23] - _T_849[9] <= _T_919 @[el2_lib.scala 244:17] - node _T_920 = bits(io.trigger_pkt_any[3].tdata2, 9, 0) @[el2_lib.scala 244:28] - node _T_921 = andr(_T_920) @[el2_lib.scala 244:36] - node _T_922 = and(_T_921, _T_852) @[el2_lib.scala 244:41] - node _T_923 = bits(io.trigger_pkt_any[3].tdata2, 10, 10) @[el2_lib.scala 244:74] - node _T_924 = bits(lsu_match_data_3, 10, 10) @[el2_lib.scala 244:86] - node _T_925 = eq(_T_923, _T_924) @[el2_lib.scala 244:78] - node _T_926 = mux(_T_922, UInt<1>("h01"), _T_925) @[el2_lib.scala 244:23] - _T_849[10] <= _T_926 @[el2_lib.scala 244:17] - node _T_927 = bits(io.trigger_pkt_any[3].tdata2, 10, 0) @[el2_lib.scala 244:28] - node _T_928 = andr(_T_927) @[el2_lib.scala 244:36] - node _T_929 = and(_T_928, _T_852) @[el2_lib.scala 244:41] - node _T_930 = bits(io.trigger_pkt_any[3].tdata2, 11, 11) @[el2_lib.scala 244:74] - node _T_931 = bits(lsu_match_data_3, 11, 11) @[el2_lib.scala 244:86] - node _T_932 = eq(_T_930, _T_931) @[el2_lib.scala 244:78] - node _T_933 = mux(_T_929, UInt<1>("h01"), _T_932) @[el2_lib.scala 244:23] - _T_849[11] <= _T_933 @[el2_lib.scala 244:17] - node _T_934 = bits(io.trigger_pkt_any[3].tdata2, 11, 0) @[el2_lib.scala 244:28] - node _T_935 = andr(_T_934) @[el2_lib.scala 244:36] - node _T_936 = and(_T_935, _T_852) @[el2_lib.scala 244:41] - node _T_937 = bits(io.trigger_pkt_any[3].tdata2, 12, 12) @[el2_lib.scala 244:74] - node _T_938 = bits(lsu_match_data_3, 12, 12) @[el2_lib.scala 244:86] - node _T_939 = eq(_T_937, _T_938) @[el2_lib.scala 244:78] - node _T_940 = mux(_T_936, UInt<1>("h01"), _T_939) @[el2_lib.scala 244:23] - _T_849[12] <= _T_940 @[el2_lib.scala 244:17] - node _T_941 = bits(io.trigger_pkt_any[3].tdata2, 12, 0) @[el2_lib.scala 244:28] - node _T_942 = andr(_T_941) @[el2_lib.scala 244:36] - node _T_943 = and(_T_942, _T_852) @[el2_lib.scala 244:41] - node _T_944 = bits(io.trigger_pkt_any[3].tdata2, 13, 13) @[el2_lib.scala 244:74] - node _T_945 = bits(lsu_match_data_3, 13, 13) @[el2_lib.scala 244:86] - node _T_946 = eq(_T_944, _T_945) @[el2_lib.scala 244:78] - node _T_947 = mux(_T_943, UInt<1>("h01"), _T_946) @[el2_lib.scala 244:23] - _T_849[13] <= _T_947 @[el2_lib.scala 244:17] - node _T_948 = bits(io.trigger_pkt_any[3].tdata2, 13, 0) @[el2_lib.scala 244:28] - node _T_949 = andr(_T_948) @[el2_lib.scala 244:36] - node _T_950 = and(_T_949, _T_852) @[el2_lib.scala 244:41] - node _T_951 = bits(io.trigger_pkt_any[3].tdata2, 14, 14) @[el2_lib.scala 244:74] - node _T_952 = bits(lsu_match_data_3, 14, 14) @[el2_lib.scala 244:86] - node _T_953 = eq(_T_951, _T_952) @[el2_lib.scala 244:78] - node _T_954 = mux(_T_950, UInt<1>("h01"), _T_953) @[el2_lib.scala 244:23] - _T_849[14] <= _T_954 @[el2_lib.scala 244:17] - node _T_955 = bits(io.trigger_pkt_any[3].tdata2, 14, 0) @[el2_lib.scala 244:28] - node _T_956 = andr(_T_955) @[el2_lib.scala 244:36] - node _T_957 = and(_T_956, _T_852) @[el2_lib.scala 244:41] - node _T_958 = bits(io.trigger_pkt_any[3].tdata2, 15, 15) @[el2_lib.scala 244:74] - node _T_959 = bits(lsu_match_data_3, 15, 15) @[el2_lib.scala 244:86] - node _T_960 = eq(_T_958, _T_959) @[el2_lib.scala 244:78] - node _T_961 = mux(_T_957, UInt<1>("h01"), _T_960) @[el2_lib.scala 244:23] - _T_849[15] <= _T_961 @[el2_lib.scala 244:17] - node _T_962 = bits(io.trigger_pkt_any[3].tdata2, 15, 0) @[el2_lib.scala 244:28] - node _T_963 = andr(_T_962) @[el2_lib.scala 244:36] - node _T_964 = and(_T_963, _T_852) @[el2_lib.scala 244:41] - node _T_965 = bits(io.trigger_pkt_any[3].tdata2, 16, 16) @[el2_lib.scala 244:74] - node _T_966 = bits(lsu_match_data_3, 16, 16) @[el2_lib.scala 244:86] - node _T_967 = eq(_T_965, _T_966) @[el2_lib.scala 244:78] - node _T_968 = mux(_T_964, UInt<1>("h01"), _T_967) @[el2_lib.scala 244:23] - _T_849[16] <= _T_968 @[el2_lib.scala 244:17] - node _T_969 = bits(io.trigger_pkt_any[3].tdata2, 16, 0) @[el2_lib.scala 244:28] - node _T_970 = andr(_T_969) @[el2_lib.scala 244:36] - node _T_971 = and(_T_970, _T_852) @[el2_lib.scala 244:41] - node _T_972 = bits(io.trigger_pkt_any[3].tdata2, 17, 17) @[el2_lib.scala 244:74] - node _T_973 = bits(lsu_match_data_3, 17, 17) @[el2_lib.scala 244:86] - node _T_974 = eq(_T_972, _T_973) @[el2_lib.scala 244:78] - node _T_975 = mux(_T_971, UInt<1>("h01"), _T_974) @[el2_lib.scala 244:23] - _T_849[17] <= _T_975 @[el2_lib.scala 244:17] - node _T_976 = bits(io.trigger_pkt_any[3].tdata2, 17, 0) @[el2_lib.scala 244:28] - node _T_977 = andr(_T_976) @[el2_lib.scala 244:36] - node _T_978 = and(_T_977, _T_852) @[el2_lib.scala 244:41] - node _T_979 = bits(io.trigger_pkt_any[3].tdata2, 18, 18) @[el2_lib.scala 244:74] - node _T_980 = bits(lsu_match_data_3, 18, 18) @[el2_lib.scala 244:86] - node _T_981 = eq(_T_979, _T_980) @[el2_lib.scala 244:78] - node _T_982 = mux(_T_978, UInt<1>("h01"), _T_981) @[el2_lib.scala 244:23] - _T_849[18] <= _T_982 @[el2_lib.scala 244:17] - node _T_983 = bits(io.trigger_pkt_any[3].tdata2, 18, 0) @[el2_lib.scala 244:28] - node _T_984 = andr(_T_983) @[el2_lib.scala 244:36] - node _T_985 = and(_T_984, _T_852) @[el2_lib.scala 244:41] - node _T_986 = bits(io.trigger_pkt_any[3].tdata2, 19, 19) @[el2_lib.scala 244:74] - node _T_987 = bits(lsu_match_data_3, 19, 19) @[el2_lib.scala 244:86] - node _T_988 = eq(_T_986, _T_987) @[el2_lib.scala 244:78] - node _T_989 = mux(_T_985, UInt<1>("h01"), _T_988) @[el2_lib.scala 244:23] - _T_849[19] <= _T_989 @[el2_lib.scala 244:17] - node _T_990 = bits(io.trigger_pkt_any[3].tdata2, 19, 0) @[el2_lib.scala 244:28] - node _T_991 = andr(_T_990) @[el2_lib.scala 244:36] - node _T_992 = and(_T_991, _T_852) @[el2_lib.scala 244:41] - node _T_993 = bits(io.trigger_pkt_any[3].tdata2, 20, 20) @[el2_lib.scala 244:74] - node _T_994 = bits(lsu_match_data_3, 20, 20) @[el2_lib.scala 244:86] - node _T_995 = eq(_T_993, _T_994) @[el2_lib.scala 244:78] - node _T_996 = mux(_T_992, UInt<1>("h01"), _T_995) @[el2_lib.scala 244:23] - _T_849[20] <= _T_996 @[el2_lib.scala 244:17] - node _T_997 = bits(io.trigger_pkt_any[3].tdata2, 20, 0) @[el2_lib.scala 244:28] - node _T_998 = andr(_T_997) @[el2_lib.scala 244:36] - node _T_999 = and(_T_998, _T_852) @[el2_lib.scala 244:41] - node _T_1000 = bits(io.trigger_pkt_any[3].tdata2, 21, 21) @[el2_lib.scala 244:74] - node _T_1001 = bits(lsu_match_data_3, 21, 21) @[el2_lib.scala 244:86] - node _T_1002 = eq(_T_1000, _T_1001) @[el2_lib.scala 244:78] - node _T_1003 = mux(_T_999, UInt<1>("h01"), _T_1002) @[el2_lib.scala 244:23] - _T_849[21] <= _T_1003 @[el2_lib.scala 244:17] - node _T_1004 = bits(io.trigger_pkt_any[3].tdata2, 21, 0) @[el2_lib.scala 244:28] - node _T_1005 = andr(_T_1004) @[el2_lib.scala 244:36] - node _T_1006 = and(_T_1005, _T_852) @[el2_lib.scala 244:41] - node _T_1007 = bits(io.trigger_pkt_any[3].tdata2, 22, 22) @[el2_lib.scala 244:74] - node _T_1008 = bits(lsu_match_data_3, 22, 22) @[el2_lib.scala 244:86] - node _T_1009 = eq(_T_1007, _T_1008) @[el2_lib.scala 244:78] - node _T_1010 = mux(_T_1006, UInt<1>("h01"), _T_1009) @[el2_lib.scala 244:23] - _T_849[22] <= _T_1010 @[el2_lib.scala 244:17] - node _T_1011 = bits(io.trigger_pkt_any[3].tdata2, 22, 0) @[el2_lib.scala 244:28] - node _T_1012 = andr(_T_1011) @[el2_lib.scala 244:36] - node _T_1013 = and(_T_1012, _T_852) @[el2_lib.scala 244:41] - node _T_1014 = bits(io.trigger_pkt_any[3].tdata2, 23, 23) @[el2_lib.scala 244:74] - node _T_1015 = bits(lsu_match_data_3, 23, 23) @[el2_lib.scala 244:86] - node _T_1016 = eq(_T_1014, _T_1015) @[el2_lib.scala 244:78] - node _T_1017 = mux(_T_1013, UInt<1>("h01"), _T_1016) @[el2_lib.scala 244:23] - _T_849[23] <= _T_1017 @[el2_lib.scala 244:17] - node _T_1018 = bits(io.trigger_pkt_any[3].tdata2, 23, 0) @[el2_lib.scala 244:28] - node _T_1019 = andr(_T_1018) @[el2_lib.scala 244:36] - node _T_1020 = and(_T_1019, _T_852) @[el2_lib.scala 244:41] - node _T_1021 = bits(io.trigger_pkt_any[3].tdata2, 24, 24) @[el2_lib.scala 244:74] - node _T_1022 = bits(lsu_match_data_3, 24, 24) @[el2_lib.scala 244:86] - node _T_1023 = eq(_T_1021, _T_1022) @[el2_lib.scala 244:78] - node _T_1024 = mux(_T_1020, UInt<1>("h01"), _T_1023) @[el2_lib.scala 244:23] - _T_849[24] <= _T_1024 @[el2_lib.scala 244:17] - node _T_1025 = bits(io.trigger_pkt_any[3].tdata2, 24, 0) @[el2_lib.scala 244:28] - node _T_1026 = andr(_T_1025) @[el2_lib.scala 244:36] - node _T_1027 = and(_T_1026, _T_852) @[el2_lib.scala 244:41] - node _T_1028 = bits(io.trigger_pkt_any[3].tdata2, 25, 25) @[el2_lib.scala 244:74] - node _T_1029 = bits(lsu_match_data_3, 25, 25) @[el2_lib.scala 244:86] - node _T_1030 = eq(_T_1028, _T_1029) @[el2_lib.scala 244:78] - node _T_1031 = mux(_T_1027, UInt<1>("h01"), _T_1030) @[el2_lib.scala 244:23] - _T_849[25] <= _T_1031 @[el2_lib.scala 244:17] - node _T_1032 = bits(io.trigger_pkt_any[3].tdata2, 25, 0) @[el2_lib.scala 244:28] - node _T_1033 = andr(_T_1032) @[el2_lib.scala 244:36] - node _T_1034 = and(_T_1033, _T_852) @[el2_lib.scala 244:41] - node _T_1035 = bits(io.trigger_pkt_any[3].tdata2, 26, 26) @[el2_lib.scala 244:74] - node _T_1036 = bits(lsu_match_data_3, 26, 26) @[el2_lib.scala 244:86] - node _T_1037 = eq(_T_1035, _T_1036) @[el2_lib.scala 244:78] - node _T_1038 = mux(_T_1034, UInt<1>("h01"), _T_1037) @[el2_lib.scala 244:23] - _T_849[26] <= _T_1038 @[el2_lib.scala 244:17] - node _T_1039 = bits(io.trigger_pkt_any[3].tdata2, 26, 0) @[el2_lib.scala 244:28] - node _T_1040 = andr(_T_1039) @[el2_lib.scala 244:36] - node _T_1041 = and(_T_1040, _T_852) @[el2_lib.scala 244:41] - node _T_1042 = bits(io.trigger_pkt_any[3].tdata2, 27, 27) @[el2_lib.scala 244:74] - node _T_1043 = bits(lsu_match_data_3, 27, 27) @[el2_lib.scala 244:86] - node _T_1044 = eq(_T_1042, _T_1043) @[el2_lib.scala 244:78] - node _T_1045 = mux(_T_1041, UInt<1>("h01"), _T_1044) @[el2_lib.scala 244:23] - _T_849[27] <= _T_1045 @[el2_lib.scala 244:17] - node _T_1046 = bits(io.trigger_pkt_any[3].tdata2, 27, 0) @[el2_lib.scala 244:28] - node _T_1047 = andr(_T_1046) @[el2_lib.scala 244:36] - node _T_1048 = and(_T_1047, _T_852) @[el2_lib.scala 244:41] - node _T_1049 = bits(io.trigger_pkt_any[3].tdata2, 28, 28) @[el2_lib.scala 244:74] - node _T_1050 = bits(lsu_match_data_3, 28, 28) @[el2_lib.scala 244:86] - node _T_1051 = eq(_T_1049, _T_1050) @[el2_lib.scala 244:78] - node _T_1052 = mux(_T_1048, UInt<1>("h01"), _T_1051) @[el2_lib.scala 244:23] - _T_849[28] <= _T_1052 @[el2_lib.scala 244:17] - node _T_1053 = bits(io.trigger_pkt_any[3].tdata2, 28, 0) @[el2_lib.scala 244:28] - node _T_1054 = andr(_T_1053) @[el2_lib.scala 244:36] - node _T_1055 = and(_T_1054, _T_852) @[el2_lib.scala 244:41] - node _T_1056 = bits(io.trigger_pkt_any[3].tdata2, 29, 29) @[el2_lib.scala 244:74] - node _T_1057 = bits(lsu_match_data_3, 29, 29) @[el2_lib.scala 244:86] - node _T_1058 = eq(_T_1056, _T_1057) @[el2_lib.scala 244:78] - node _T_1059 = mux(_T_1055, UInt<1>("h01"), _T_1058) @[el2_lib.scala 244:23] - _T_849[29] <= _T_1059 @[el2_lib.scala 244:17] - node _T_1060 = bits(io.trigger_pkt_any[3].tdata2, 29, 0) @[el2_lib.scala 244:28] - node _T_1061 = andr(_T_1060) @[el2_lib.scala 244:36] - node _T_1062 = and(_T_1061, _T_852) @[el2_lib.scala 244:41] - node _T_1063 = bits(io.trigger_pkt_any[3].tdata2, 30, 30) @[el2_lib.scala 244:74] - node _T_1064 = bits(lsu_match_data_3, 30, 30) @[el2_lib.scala 244:86] - node _T_1065 = eq(_T_1063, _T_1064) @[el2_lib.scala 244:78] - node _T_1066 = mux(_T_1062, UInt<1>("h01"), _T_1065) @[el2_lib.scala 244:23] - _T_849[30] <= _T_1066 @[el2_lib.scala 244:17] - node _T_1067 = bits(io.trigger_pkt_any[3].tdata2, 30, 0) @[el2_lib.scala 244:28] - node _T_1068 = andr(_T_1067) @[el2_lib.scala 244:36] - node _T_1069 = and(_T_1068, _T_852) @[el2_lib.scala 244:41] - node _T_1070 = bits(io.trigger_pkt_any[3].tdata2, 31, 31) @[el2_lib.scala 244:74] - node _T_1071 = bits(lsu_match_data_3, 31, 31) @[el2_lib.scala 244:86] - node _T_1072 = eq(_T_1070, _T_1071) @[el2_lib.scala 244:78] - node _T_1073 = mux(_T_1069, UInt<1>("h01"), _T_1072) @[el2_lib.scala 244:23] - _T_849[31] <= _T_1073 @[el2_lib.scala 244:17] - node _T_1074 = cat(_T_849[1], _T_849[0]) @[el2_lib.scala 245:14] - node _T_1075 = cat(_T_849[3], _T_849[2]) @[el2_lib.scala 245:14] - node _T_1076 = cat(_T_1075, _T_1074) @[el2_lib.scala 245:14] - node _T_1077 = cat(_T_849[5], _T_849[4]) @[el2_lib.scala 245:14] - node _T_1078 = cat(_T_849[7], _T_849[6]) @[el2_lib.scala 245:14] - node _T_1079 = cat(_T_1078, _T_1077) @[el2_lib.scala 245:14] - node _T_1080 = cat(_T_1079, _T_1076) @[el2_lib.scala 245:14] - node _T_1081 = cat(_T_849[9], _T_849[8]) @[el2_lib.scala 245:14] - node _T_1082 = cat(_T_849[11], _T_849[10]) @[el2_lib.scala 245:14] - node _T_1083 = cat(_T_1082, _T_1081) @[el2_lib.scala 245:14] - node _T_1084 = cat(_T_849[13], _T_849[12]) @[el2_lib.scala 245:14] - node _T_1085 = cat(_T_849[15], _T_849[14]) @[el2_lib.scala 245:14] - node _T_1086 = cat(_T_1085, _T_1084) @[el2_lib.scala 245:14] - node _T_1087 = cat(_T_1086, _T_1083) @[el2_lib.scala 245:14] - node _T_1088 = cat(_T_1087, _T_1080) @[el2_lib.scala 245:14] - node _T_1089 = cat(_T_849[17], _T_849[16]) @[el2_lib.scala 245:14] - node _T_1090 = cat(_T_849[19], _T_849[18]) @[el2_lib.scala 245:14] - node _T_1091 = cat(_T_1090, _T_1089) @[el2_lib.scala 245:14] - node _T_1092 = cat(_T_849[21], _T_849[20]) @[el2_lib.scala 245:14] - node _T_1093 = cat(_T_849[23], _T_849[22]) @[el2_lib.scala 245:14] - node _T_1094 = cat(_T_1093, _T_1092) @[el2_lib.scala 245:14] - node _T_1095 = cat(_T_1094, _T_1091) @[el2_lib.scala 245:14] - node _T_1096 = cat(_T_849[25], _T_849[24]) @[el2_lib.scala 245:14] - node _T_1097 = cat(_T_849[27], _T_849[26]) @[el2_lib.scala 245:14] - node _T_1098 = cat(_T_1097, _T_1096) @[el2_lib.scala 245:14] - node _T_1099 = cat(_T_849[29], _T_849[28]) @[el2_lib.scala 245:14] - node _T_1100 = cat(_T_849[31], _T_849[30]) @[el2_lib.scala 245:14] - node _T_1101 = cat(_T_1100, _T_1099) @[el2_lib.scala 245:14] - node _T_1102 = cat(_T_1101, _T_1098) @[el2_lib.scala 245:14] - node _T_1103 = cat(_T_1102, _T_1095) @[el2_lib.scala 245:14] - node _T_1104 = cat(_T_1103, _T_1088) @[el2_lib.scala 245:14] - node _T_1105 = andr(_T_1104) @[el2_lib.scala 245:25] + wire _T_849 : UInt<1>[32] @[lib.scala 100:24] + node _T_850 = andr(io.trigger_pkt_any[3].tdata2) @[lib.scala 101:45] + node _T_851 = not(_T_850) @[lib.scala 101:39] + node _T_852 = and(_T_848, _T_851) @[lib.scala 101:37] + node _T_853 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[lib.scala 102:48] + node _T_854 = bits(lsu_match_data_3, 0, 0) @[lib.scala 102:60] + node _T_855 = eq(_T_853, _T_854) @[lib.scala 102:52] + node _T_856 = or(_T_852, _T_855) @[lib.scala 102:41] + _T_849[0] <= _T_856 @[lib.scala 102:18] + node _T_857 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[lib.scala 104:28] + node _T_858 = andr(_T_857) @[lib.scala 104:36] + node _T_859 = and(_T_858, _T_852) @[lib.scala 104:41] + node _T_860 = bits(io.trigger_pkt_any[3].tdata2, 1, 1) @[lib.scala 104:74] + node _T_861 = bits(lsu_match_data_3, 1, 1) @[lib.scala 104:86] + node _T_862 = eq(_T_860, _T_861) @[lib.scala 104:78] + node _T_863 = mux(_T_859, UInt<1>("h01"), _T_862) @[lib.scala 104:23] + _T_849[1] <= _T_863 @[lib.scala 104:17] + node _T_864 = bits(io.trigger_pkt_any[3].tdata2, 1, 0) @[lib.scala 104:28] + node _T_865 = andr(_T_864) @[lib.scala 104:36] + node _T_866 = and(_T_865, _T_852) @[lib.scala 104:41] + node _T_867 = bits(io.trigger_pkt_any[3].tdata2, 2, 2) @[lib.scala 104:74] + node _T_868 = bits(lsu_match_data_3, 2, 2) @[lib.scala 104:86] + node _T_869 = eq(_T_867, _T_868) @[lib.scala 104:78] + node _T_870 = mux(_T_866, UInt<1>("h01"), _T_869) @[lib.scala 104:23] + _T_849[2] <= _T_870 @[lib.scala 104:17] + node _T_871 = bits(io.trigger_pkt_any[3].tdata2, 2, 0) @[lib.scala 104:28] + node _T_872 = andr(_T_871) @[lib.scala 104:36] + node _T_873 = and(_T_872, _T_852) @[lib.scala 104:41] + node _T_874 = bits(io.trigger_pkt_any[3].tdata2, 3, 3) @[lib.scala 104:74] + node _T_875 = bits(lsu_match_data_3, 3, 3) @[lib.scala 104:86] + node _T_876 = eq(_T_874, _T_875) @[lib.scala 104:78] + node _T_877 = mux(_T_873, UInt<1>("h01"), _T_876) @[lib.scala 104:23] + _T_849[3] <= _T_877 @[lib.scala 104:17] + node _T_878 = bits(io.trigger_pkt_any[3].tdata2, 3, 0) @[lib.scala 104:28] + node _T_879 = andr(_T_878) @[lib.scala 104:36] + node _T_880 = and(_T_879, _T_852) @[lib.scala 104:41] + node _T_881 = bits(io.trigger_pkt_any[3].tdata2, 4, 4) @[lib.scala 104:74] + node _T_882 = bits(lsu_match_data_3, 4, 4) @[lib.scala 104:86] + node _T_883 = eq(_T_881, _T_882) @[lib.scala 104:78] + node _T_884 = mux(_T_880, UInt<1>("h01"), _T_883) @[lib.scala 104:23] + _T_849[4] <= _T_884 @[lib.scala 104:17] + node _T_885 = bits(io.trigger_pkt_any[3].tdata2, 4, 0) @[lib.scala 104:28] + node _T_886 = andr(_T_885) @[lib.scala 104:36] + node _T_887 = and(_T_886, _T_852) @[lib.scala 104:41] + node _T_888 = bits(io.trigger_pkt_any[3].tdata2, 5, 5) @[lib.scala 104:74] + node _T_889 = bits(lsu_match_data_3, 5, 5) @[lib.scala 104:86] + node _T_890 = eq(_T_888, _T_889) @[lib.scala 104:78] + node _T_891 = mux(_T_887, UInt<1>("h01"), _T_890) @[lib.scala 104:23] + _T_849[5] <= _T_891 @[lib.scala 104:17] + node _T_892 = bits(io.trigger_pkt_any[3].tdata2, 5, 0) @[lib.scala 104:28] + node _T_893 = andr(_T_892) @[lib.scala 104:36] + node _T_894 = and(_T_893, _T_852) @[lib.scala 104:41] + node _T_895 = bits(io.trigger_pkt_any[3].tdata2, 6, 6) @[lib.scala 104:74] + node _T_896 = bits(lsu_match_data_3, 6, 6) @[lib.scala 104:86] + node _T_897 = eq(_T_895, _T_896) @[lib.scala 104:78] + node _T_898 = mux(_T_894, UInt<1>("h01"), _T_897) @[lib.scala 104:23] + _T_849[6] <= _T_898 @[lib.scala 104:17] + node _T_899 = bits(io.trigger_pkt_any[3].tdata2, 6, 0) @[lib.scala 104:28] + node _T_900 = andr(_T_899) @[lib.scala 104:36] + node _T_901 = and(_T_900, _T_852) @[lib.scala 104:41] + node _T_902 = bits(io.trigger_pkt_any[3].tdata2, 7, 7) @[lib.scala 104:74] + node _T_903 = bits(lsu_match_data_3, 7, 7) @[lib.scala 104:86] + node _T_904 = eq(_T_902, _T_903) @[lib.scala 104:78] + node _T_905 = mux(_T_901, UInt<1>("h01"), _T_904) @[lib.scala 104:23] + _T_849[7] <= _T_905 @[lib.scala 104:17] + node _T_906 = bits(io.trigger_pkt_any[3].tdata2, 7, 0) @[lib.scala 104:28] + node _T_907 = andr(_T_906) @[lib.scala 104:36] + node _T_908 = and(_T_907, _T_852) @[lib.scala 104:41] + node _T_909 = bits(io.trigger_pkt_any[3].tdata2, 8, 8) @[lib.scala 104:74] + node _T_910 = bits(lsu_match_data_3, 8, 8) @[lib.scala 104:86] + node _T_911 = eq(_T_909, _T_910) @[lib.scala 104:78] + node _T_912 = mux(_T_908, UInt<1>("h01"), _T_911) @[lib.scala 104:23] + _T_849[8] <= _T_912 @[lib.scala 104:17] + node _T_913 = bits(io.trigger_pkt_any[3].tdata2, 8, 0) @[lib.scala 104:28] + node _T_914 = andr(_T_913) @[lib.scala 104:36] + node _T_915 = and(_T_914, _T_852) @[lib.scala 104:41] + node _T_916 = bits(io.trigger_pkt_any[3].tdata2, 9, 9) @[lib.scala 104:74] + node _T_917 = bits(lsu_match_data_3, 9, 9) @[lib.scala 104:86] + node _T_918 = eq(_T_916, _T_917) @[lib.scala 104:78] + node _T_919 = mux(_T_915, UInt<1>("h01"), _T_918) @[lib.scala 104:23] + _T_849[9] <= _T_919 @[lib.scala 104:17] + node _T_920 = bits(io.trigger_pkt_any[3].tdata2, 9, 0) @[lib.scala 104:28] + node _T_921 = andr(_T_920) @[lib.scala 104:36] + node _T_922 = and(_T_921, _T_852) @[lib.scala 104:41] + node _T_923 = bits(io.trigger_pkt_any[3].tdata2, 10, 10) @[lib.scala 104:74] + node _T_924 = bits(lsu_match_data_3, 10, 10) @[lib.scala 104:86] + node _T_925 = eq(_T_923, _T_924) @[lib.scala 104:78] + node _T_926 = mux(_T_922, UInt<1>("h01"), _T_925) @[lib.scala 104:23] + _T_849[10] <= _T_926 @[lib.scala 104:17] + node _T_927 = bits(io.trigger_pkt_any[3].tdata2, 10, 0) @[lib.scala 104:28] + node _T_928 = andr(_T_927) @[lib.scala 104:36] + node _T_929 = and(_T_928, _T_852) @[lib.scala 104:41] + node _T_930 = bits(io.trigger_pkt_any[3].tdata2, 11, 11) @[lib.scala 104:74] + node _T_931 = bits(lsu_match_data_3, 11, 11) @[lib.scala 104:86] + node _T_932 = eq(_T_930, _T_931) @[lib.scala 104:78] + node _T_933 = mux(_T_929, UInt<1>("h01"), _T_932) @[lib.scala 104:23] + _T_849[11] <= _T_933 @[lib.scala 104:17] + node _T_934 = bits(io.trigger_pkt_any[3].tdata2, 11, 0) @[lib.scala 104:28] + node _T_935 = andr(_T_934) @[lib.scala 104:36] + node _T_936 = and(_T_935, _T_852) @[lib.scala 104:41] + node _T_937 = bits(io.trigger_pkt_any[3].tdata2, 12, 12) @[lib.scala 104:74] + node _T_938 = bits(lsu_match_data_3, 12, 12) @[lib.scala 104:86] + node _T_939 = eq(_T_937, _T_938) @[lib.scala 104:78] + node _T_940 = mux(_T_936, UInt<1>("h01"), _T_939) @[lib.scala 104:23] + _T_849[12] <= _T_940 @[lib.scala 104:17] + node _T_941 = bits(io.trigger_pkt_any[3].tdata2, 12, 0) @[lib.scala 104:28] + node _T_942 = andr(_T_941) @[lib.scala 104:36] + node _T_943 = and(_T_942, _T_852) @[lib.scala 104:41] + node _T_944 = bits(io.trigger_pkt_any[3].tdata2, 13, 13) @[lib.scala 104:74] + node _T_945 = bits(lsu_match_data_3, 13, 13) @[lib.scala 104:86] + node _T_946 = eq(_T_944, _T_945) @[lib.scala 104:78] + node _T_947 = mux(_T_943, UInt<1>("h01"), _T_946) @[lib.scala 104:23] + _T_849[13] <= _T_947 @[lib.scala 104:17] + node _T_948 = bits(io.trigger_pkt_any[3].tdata2, 13, 0) @[lib.scala 104:28] + node _T_949 = andr(_T_948) @[lib.scala 104:36] + node _T_950 = and(_T_949, _T_852) @[lib.scala 104:41] + node _T_951 = bits(io.trigger_pkt_any[3].tdata2, 14, 14) @[lib.scala 104:74] + node _T_952 = bits(lsu_match_data_3, 14, 14) @[lib.scala 104:86] + node _T_953 = eq(_T_951, _T_952) @[lib.scala 104:78] + node _T_954 = mux(_T_950, UInt<1>("h01"), _T_953) @[lib.scala 104:23] + _T_849[14] <= _T_954 @[lib.scala 104:17] + node _T_955 = bits(io.trigger_pkt_any[3].tdata2, 14, 0) @[lib.scala 104:28] + node _T_956 = andr(_T_955) @[lib.scala 104:36] + node _T_957 = and(_T_956, _T_852) @[lib.scala 104:41] + node _T_958 = bits(io.trigger_pkt_any[3].tdata2, 15, 15) @[lib.scala 104:74] + node _T_959 = bits(lsu_match_data_3, 15, 15) @[lib.scala 104:86] + node _T_960 = eq(_T_958, _T_959) @[lib.scala 104:78] + node _T_961 = mux(_T_957, UInt<1>("h01"), _T_960) @[lib.scala 104:23] + _T_849[15] <= _T_961 @[lib.scala 104:17] + node _T_962 = bits(io.trigger_pkt_any[3].tdata2, 15, 0) @[lib.scala 104:28] + node _T_963 = andr(_T_962) @[lib.scala 104:36] + node _T_964 = and(_T_963, _T_852) @[lib.scala 104:41] + node _T_965 = bits(io.trigger_pkt_any[3].tdata2, 16, 16) @[lib.scala 104:74] + node _T_966 = bits(lsu_match_data_3, 16, 16) @[lib.scala 104:86] + node _T_967 = eq(_T_965, _T_966) @[lib.scala 104:78] + node _T_968 = mux(_T_964, UInt<1>("h01"), _T_967) @[lib.scala 104:23] + _T_849[16] <= _T_968 @[lib.scala 104:17] + node _T_969 = bits(io.trigger_pkt_any[3].tdata2, 16, 0) @[lib.scala 104:28] + node _T_970 = andr(_T_969) @[lib.scala 104:36] + node _T_971 = and(_T_970, _T_852) @[lib.scala 104:41] + node _T_972 = bits(io.trigger_pkt_any[3].tdata2, 17, 17) @[lib.scala 104:74] + node _T_973 = bits(lsu_match_data_3, 17, 17) @[lib.scala 104:86] + node _T_974 = eq(_T_972, _T_973) @[lib.scala 104:78] + node _T_975 = mux(_T_971, UInt<1>("h01"), _T_974) @[lib.scala 104:23] + _T_849[17] <= _T_975 @[lib.scala 104:17] + node _T_976 = bits(io.trigger_pkt_any[3].tdata2, 17, 0) @[lib.scala 104:28] + node _T_977 = andr(_T_976) @[lib.scala 104:36] + node _T_978 = and(_T_977, _T_852) @[lib.scala 104:41] + node _T_979 = bits(io.trigger_pkt_any[3].tdata2, 18, 18) @[lib.scala 104:74] + node _T_980 = bits(lsu_match_data_3, 18, 18) @[lib.scala 104:86] + node _T_981 = eq(_T_979, _T_980) @[lib.scala 104:78] + node _T_982 = mux(_T_978, UInt<1>("h01"), _T_981) @[lib.scala 104:23] + _T_849[18] <= _T_982 @[lib.scala 104:17] + node _T_983 = bits(io.trigger_pkt_any[3].tdata2, 18, 0) @[lib.scala 104:28] + node _T_984 = andr(_T_983) @[lib.scala 104:36] + node _T_985 = and(_T_984, _T_852) @[lib.scala 104:41] + node _T_986 = bits(io.trigger_pkt_any[3].tdata2, 19, 19) @[lib.scala 104:74] + node _T_987 = bits(lsu_match_data_3, 19, 19) @[lib.scala 104:86] + node _T_988 = eq(_T_986, _T_987) @[lib.scala 104:78] + node _T_989 = mux(_T_985, UInt<1>("h01"), _T_988) @[lib.scala 104:23] + _T_849[19] <= _T_989 @[lib.scala 104:17] + node _T_990 = bits(io.trigger_pkt_any[3].tdata2, 19, 0) @[lib.scala 104:28] + node _T_991 = andr(_T_990) @[lib.scala 104:36] + node _T_992 = and(_T_991, _T_852) @[lib.scala 104:41] + node _T_993 = bits(io.trigger_pkt_any[3].tdata2, 20, 20) @[lib.scala 104:74] + node _T_994 = bits(lsu_match_data_3, 20, 20) @[lib.scala 104:86] + node _T_995 = eq(_T_993, _T_994) @[lib.scala 104:78] + node _T_996 = mux(_T_992, UInt<1>("h01"), _T_995) @[lib.scala 104:23] + _T_849[20] <= _T_996 @[lib.scala 104:17] + node _T_997 = bits(io.trigger_pkt_any[3].tdata2, 20, 0) @[lib.scala 104:28] + node _T_998 = andr(_T_997) @[lib.scala 104:36] + node _T_999 = and(_T_998, _T_852) @[lib.scala 104:41] + node _T_1000 = bits(io.trigger_pkt_any[3].tdata2, 21, 21) @[lib.scala 104:74] + node _T_1001 = bits(lsu_match_data_3, 21, 21) @[lib.scala 104:86] + node _T_1002 = eq(_T_1000, _T_1001) @[lib.scala 104:78] + node _T_1003 = mux(_T_999, UInt<1>("h01"), _T_1002) @[lib.scala 104:23] + _T_849[21] <= _T_1003 @[lib.scala 104:17] + node _T_1004 = bits(io.trigger_pkt_any[3].tdata2, 21, 0) @[lib.scala 104:28] + node _T_1005 = andr(_T_1004) @[lib.scala 104:36] + node _T_1006 = and(_T_1005, _T_852) @[lib.scala 104:41] + node _T_1007 = bits(io.trigger_pkt_any[3].tdata2, 22, 22) @[lib.scala 104:74] + node _T_1008 = bits(lsu_match_data_3, 22, 22) @[lib.scala 104:86] + node _T_1009 = eq(_T_1007, _T_1008) @[lib.scala 104:78] + node _T_1010 = mux(_T_1006, UInt<1>("h01"), _T_1009) @[lib.scala 104:23] + _T_849[22] <= _T_1010 @[lib.scala 104:17] + node _T_1011 = bits(io.trigger_pkt_any[3].tdata2, 22, 0) @[lib.scala 104:28] + node _T_1012 = andr(_T_1011) @[lib.scala 104:36] + node _T_1013 = and(_T_1012, _T_852) @[lib.scala 104:41] + node _T_1014 = bits(io.trigger_pkt_any[3].tdata2, 23, 23) @[lib.scala 104:74] + node _T_1015 = bits(lsu_match_data_3, 23, 23) @[lib.scala 104:86] + node _T_1016 = eq(_T_1014, _T_1015) @[lib.scala 104:78] + node _T_1017 = mux(_T_1013, UInt<1>("h01"), _T_1016) @[lib.scala 104:23] + _T_849[23] <= _T_1017 @[lib.scala 104:17] + node _T_1018 = bits(io.trigger_pkt_any[3].tdata2, 23, 0) @[lib.scala 104:28] + node _T_1019 = andr(_T_1018) @[lib.scala 104:36] + node _T_1020 = and(_T_1019, _T_852) @[lib.scala 104:41] + node _T_1021 = bits(io.trigger_pkt_any[3].tdata2, 24, 24) @[lib.scala 104:74] + node _T_1022 = bits(lsu_match_data_3, 24, 24) @[lib.scala 104:86] + node _T_1023 = eq(_T_1021, _T_1022) @[lib.scala 104:78] + node _T_1024 = mux(_T_1020, UInt<1>("h01"), _T_1023) @[lib.scala 104:23] + _T_849[24] <= _T_1024 @[lib.scala 104:17] + node _T_1025 = bits(io.trigger_pkt_any[3].tdata2, 24, 0) @[lib.scala 104:28] + node _T_1026 = andr(_T_1025) @[lib.scala 104:36] + node _T_1027 = and(_T_1026, _T_852) @[lib.scala 104:41] + node _T_1028 = bits(io.trigger_pkt_any[3].tdata2, 25, 25) @[lib.scala 104:74] + node _T_1029 = bits(lsu_match_data_3, 25, 25) @[lib.scala 104:86] + node _T_1030 = eq(_T_1028, _T_1029) @[lib.scala 104:78] + node _T_1031 = mux(_T_1027, UInt<1>("h01"), _T_1030) @[lib.scala 104:23] + _T_849[25] <= _T_1031 @[lib.scala 104:17] + node _T_1032 = bits(io.trigger_pkt_any[3].tdata2, 25, 0) @[lib.scala 104:28] + node _T_1033 = andr(_T_1032) @[lib.scala 104:36] + node _T_1034 = and(_T_1033, _T_852) @[lib.scala 104:41] + node _T_1035 = bits(io.trigger_pkt_any[3].tdata2, 26, 26) @[lib.scala 104:74] + node _T_1036 = bits(lsu_match_data_3, 26, 26) @[lib.scala 104:86] + node _T_1037 = eq(_T_1035, _T_1036) @[lib.scala 104:78] + node _T_1038 = mux(_T_1034, UInt<1>("h01"), _T_1037) @[lib.scala 104:23] + _T_849[26] <= _T_1038 @[lib.scala 104:17] + node _T_1039 = bits(io.trigger_pkt_any[3].tdata2, 26, 0) @[lib.scala 104:28] + node _T_1040 = andr(_T_1039) @[lib.scala 104:36] + node _T_1041 = and(_T_1040, _T_852) @[lib.scala 104:41] + node _T_1042 = bits(io.trigger_pkt_any[3].tdata2, 27, 27) @[lib.scala 104:74] + node _T_1043 = bits(lsu_match_data_3, 27, 27) @[lib.scala 104:86] + node _T_1044 = eq(_T_1042, _T_1043) @[lib.scala 104:78] + node _T_1045 = mux(_T_1041, UInt<1>("h01"), _T_1044) @[lib.scala 104:23] + _T_849[27] <= _T_1045 @[lib.scala 104:17] + node _T_1046 = bits(io.trigger_pkt_any[3].tdata2, 27, 0) @[lib.scala 104:28] + node _T_1047 = andr(_T_1046) @[lib.scala 104:36] + node _T_1048 = and(_T_1047, _T_852) @[lib.scala 104:41] + node _T_1049 = bits(io.trigger_pkt_any[3].tdata2, 28, 28) @[lib.scala 104:74] + node _T_1050 = bits(lsu_match_data_3, 28, 28) @[lib.scala 104:86] + node _T_1051 = eq(_T_1049, _T_1050) @[lib.scala 104:78] + node _T_1052 = mux(_T_1048, UInt<1>("h01"), _T_1051) @[lib.scala 104:23] + _T_849[28] <= _T_1052 @[lib.scala 104:17] + node _T_1053 = bits(io.trigger_pkt_any[3].tdata2, 28, 0) @[lib.scala 104:28] + node _T_1054 = andr(_T_1053) @[lib.scala 104:36] + node _T_1055 = and(_T_1054, _T_852) @[lib.scala 104:41] + node _T_1056 = bits(io.trigger_pkt_any[3].tdata2, 29, 29) @[lib.scala 104:74] + node _T_1057 = bits(lsu_match_data_3, 29, 29) @[lib.scala 104:86] + node _T_1058 = eq(_T_1056, _T_1057) @[lib.scala 104:78] + node _T_1059 = mux(_T_1055, UInt<1>("h01"), _T_1058) @[lib.scala 104:23] + _T_849[29] <= _T_1059 @[lib.scala 104:17] + node _T_1060 = bits(io.trigger_pkt_any[3].tdata2, 29, 0) @[lib.scala 104:28] + node _T_1061 = andr(_T_1060) @[lib.scala 104:36] + node _T_1062 = and(_T_1061, _T_852) @[lib.scala 104:41] + node _T_1063 = bits(io.trigger_pkt_any[3].tdata2, 30, 30) @[lib.scala 104:74] + node _T_1064 = bits(lsu_match_data_3, 30, 30) @[lib.scala 104:86] + node _T_1065 = eq(_T_1063, _T_1064) @[lib.scala 104:78] + node _T_1066 = mux(_T_1062, UInt<1>("h01"), _T_1065) @[lib.scala 104:23] + _T_849[30] <= _T_1066 @[lib.scala 104:17] + node _T_1067 = bits(io.trigger_pkt_any[3].tdata2, 30, 0) @[lib.scala 104:28] + node _T_1068 = andr(_T_1067) @[lib.scala 104:36] + node _T_1069 = and(_T_1068, _T_852) @[lib.scala 104:41] + node _T_1070 = bits(io.trigger_pkt_any[3].tdata2, 31, 31) @[lib.scala 104:74] + node _T_1071 = bits(lsu_match_data_3, 31, 31) @[lib.scala 104:86] + node _T_1072 = eq(_T_1070, _T_1071) @[lib.scala 104:78] + node _T_1073 = mux(_T_1069, UInt<1>("h01"), _T_1072) @[lib.scala 104:23] + _T_849[31] <= _T_1073 @[lib.scala 104:17] + node _T_1074 = cat(_T_849[1], _T_849[0]) @[lib.scala 105:14] + node _T_1075 = cat(_T_849[3], _T_849[2]) @[lib.scala 105:14] + node _T_1076 = cat(_T_1075, _T_1074) @[lib.scala 105:14] + node _T_1077 = cat(_T_849[5], _T_849[4]) @[lib.scala 105:14] + node _T_1078 = cat(_T_849[7], _T_849[6]) @[lib.scala 105:14] + node _T_1079 = cat(_T_1078, _T_1077) @[lib.scala 105:14] + node _T_1080 = cat(_T_1079, _T_1076) @[lib.scala 105:14] + node _T_1081 = cat(_T_849[9], _T_849[8]) @[lib.scala 105:14] + node _T_1082 = cat(_T_849[11], _T_849[10]) @[lib.scala 105:14] + node _T_1083 = cat(_T_1082, _T_1081) @[lib.scala 105:14] + node _T_1084 = cat(_T_849[13], _T_849[12]) @[lib.scala 105:14] + node _T_1085 = cat(_T_849[15], _T_849[14]) @[lib.scala 105:14] + node _T_1086 = cat(_T_1085, _T_1084) @[lib.scala 105:14] + node _T_1087 = cat(_T_1086, _T_1083) @[lib.scala 105:14] + node _T_1088 = cat(_T_1087, _T_1080) @[lib.scala 105:14] + node _T_1089 = cat(_T_849[17], _T_849[16]) @[lib.scala 105:14] + node _T_1090 = cat(_T_849[19], _T_849[18]) @[lib.scala 105:14] + node _T_1091 = cat(_T_1090, _T_1089) @[lib.scala 105:14] + node _T_1092 = cat(_T_849[21], _T_849[20]) @[lib.scala 105:14] + node _T_1093 = cat(_T_849[23], _T_849[22]) @[lib.scala 105:14] + node _T_1094 = cat(_T_1093, _T_1092) @[lib.scala 105:14] + node _T_1095 = cat(_T_1094, _T_1091) @[lib.scala 105:14] + node _T_1096 = cat(_T_849[25], _T_849[24]) @[lib.scala 105:14] + node _T_1097 = cat(_T_849[27], _T_849[26]) @[lib.scala 105:14] + node _T_1098 = cat(_T_1097, _T_1096) @[lib.scala 105:14] + node _T_1099 = cat(_T_849[29], _T_849[28]) @[lib.scala 105:14] + node _T_1100 = cat(_T_849[31], _T_849[30]) @[lib.scala 105:14] + node _T_1101 = cat(_T_1100, _T_1099) @[lib.scala 105:14] + node _T_1102 = cat(_T_1101, _T_1098) @[lib.scala 105:14] + node _T_1103 = cat(_T_1102, _T_1095) @[lib.scala 105:14] + node _T_1104 = cat(_T_1103, _T_1088) @[lib.scala 105:14] + node _T_1105 = andr(_T_1104) @[lib.scala 105:25] node _T_1106 = and(_T_847, _T_1105) @[lsu_trigger.scala 19:92] node _T_1107 = cat(_T_1106, _T_839) @[Cat.scala 29:58] node _T_1108 = cat(_T_1107, _T_572) @[Cat.scala 29:58] @@ -94228,15 +94220,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_802 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_802 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_803 : output Q : Clock @@ -94252,15 +94244,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_803 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_803 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_804 : output Q : Clock @@ -94276,15 +94268,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_804 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_804 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_805 : output Q : Clock @@ -94300,15 +94292,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_805 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_805 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_806 : output Q : Clock @@ -94324,15 +94316,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_806 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_806 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_807 : output Q : Clock @@ -94348,15 +94340,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_807 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_807 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_808 : output Q : Clock @@ -94372,15 +94364,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_808 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_808 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_809 : output Q : Clock @@ -94396,15 +94388,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_809 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_809 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_810 : output Q : Clock @@ -94420,15 +94412,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_810 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_810 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_811 : output Q : Clock @@ -94444,15 +94436,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_811 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_811 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_812 : output Q : Clock @@ -94468,15 +94460,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_812 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_812 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_813 : output Q : Clock @@ -94492,15 +94484,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_813 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_813 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] module lsu_clkdomain : input clock : Clock @@ -94558,100 +94550,100 @@ circuit quasar_wrapper : _T_24 <= lsu_c1_r_clken @[lsu_clkdomain.scala 83:67] lsu_c1_r_clken_q <= _T_24 @[lsu_clkdomain.scala 83:26] node _T_25 = bits(lsu_c1_m_clken, 0, 0) @[lsu_clkdomain.scala 85:59] - inst rvclkhdr of rvclkhdr_802 @[el2_lib.scala 483:22] + inst rvclkhdr of rvclkhdr_802 @[lib.scala 343:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr.io.en <= _T_25 @[el2_lib.scala 485:16] - rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr.io.clk <= clock @[lib.scala 344:17] + rvclkhdr.io.en <= _T_25 @[lib.scala 345:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] io.lsu_c1_m_clk <= rvclkhdr.io.l1clk @[lsu_clkdomain.scala 85:26] node _T_26 = bits(lsu_c1_r_clken, 0, 0) @[lsu_clkdomain.scala 86:59] - inst rvclkhdr_1 of rvclkhdr_803 @[el2_lib.scala 483:22] + inst rvclkhdr_1 of rvclkhdr_803 @[lib.scala 343:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_1.io.en <= _T_26 @[el2_lib.scala 485:16] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_1.io.en <= _T_26 @[lib.scala 345:16] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] io.lsu_c1_r_clk <= rvclkhdr_1.io.l1clk @[lsu_clkdomain.scala 86:26] node _T_27 = bits(lsu_c2_m_clken, 0, 0) @[lsu_clkdomain.scala 87:59] - inst rvclkhdr_2 of rvclkhdr_804 @[el2_lib.scala 483:22] + inst rvclkhdr_2 of rvclkhdr_804 @[lib.scala 343:22] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_2.io.en <= _T_27 @[el2_lib.scala 485:16] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_2.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_2.io.en <= _T_27 @[lib.scala 345:16] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 346:23] io.lsu_c2_m_clk <= rvclkhdr_2.io.l1clk @[lsu_clkdomain.scala 87:26] node _T_28 = bits(lsu_c2_r_clken, 0, 0) @[lsu_clkdomain.scala 88:59] - inst rvclkhdr_3 of rvclkhdr_805 @[el2_lib.scala 483:22] + inst rvclkhdr_3 of rvclkhdr_805 @[lib.scala 343:22] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_3.io.en <= _T_28 @[el2_lib.scala 485:16] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_3.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_3.io.en <= _T_28 @[lib.scala 345:16] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 346:23] io.lsu_c2_r_clk <= rvclkhdr_3.io.l1clk @[lsu_clkdomain.scala 88:26] node _T_29 = bits(lsu_store_c1_m_clken, 0, 0) @[lsu_clkdomain.scala 89:65] - inst rvclkhdr_4 of rvclkhdr_806 @[el2_lib.scala 483:22] + inst rvclkhdr_4 of rvclkhdr_806 @[lib.scala 343:22] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_4.io.en <= _T_29 @[el2_lib.scala 485:16] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_4.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_4.io.en <= _T_29 @[lib.scala 345:16] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 346:23] io.lsu_store_c1_m_clk <= rvclkhdr_4.io.l1clk @[lsu_clkdomain.scala 89:26] node _T_30 = bits(lsu_store_c1_r_clken, 0, 0) @[lsu_clkdomain.scala 90:65] - inst rvclkhdr_5 of rvclkhdr_807 @[el2_lib.scala 483:22] + inst rvclkhdr_5 of rvclkhdr_807 @[lib.scala 343:22] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_5.io.en <= _T_30 @[el2_lib.scala 485:16] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_5.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_5.io.en <= _T_30 @[lib.scala 345:16] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 346:23] io.lsu_store_c1_r_clk <= rvclkhdr_5.io.l1clk @[lsu_clkdomain.scala 90:26] node _T_31 = bits(lsu_stbuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 91:63] - inst rvclkhdr_6 of rvclkhdr_808 @[el2_lib.scala 483:22] + inst rvclkhdr_6 of rvclkhdr_808 @[lib.scala 343:22] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset - rvclkhdr_6.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_6.io.en <= _T_31 @[el2_lib.scala 485:16] - rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_6.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_6.io.en <= _T_31 @[lib.scala 345:16] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 346:23] io.lsu_stbuf_c1_clk <= rvclkhdr_6.io.l1clk @[lsu_clkdomain.scala 91:26] node _T_32 = bits(lsu_bus_ibuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 92:66] - inst rvclkhdr_7 of rvclkhdr_809 @[el2_lib.scala 483:22] + inst rvclkhdr_7 of rvclkhdr_809 @[lib.scala 343:22] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset - rvclkhdr_7.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_7.io.en <= _T_32 @[el2_lib.scala 485:16] - rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_7.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_7.io.en <= _T_32 @[lib.scala 345:16] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 346:23] io.lsu_bus_ibuf_c1_clk <= rvclkhdr_7.io.l1clk @[lsu_clkdomain.scala 92:26] node _T_33 = bits(lsu_bus_obuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 93:66] - inst rvclkhdr_8 of rvclkhdr_810 @[el2_lib.scala 483:22] + inst rvclkhdr_8 of rvclkhdr_810 @[lib.scala 343:22] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset - rvclkhdr_8.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_8.io.en <= _T_33 @[el2_lib.scala 485:16] - rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_8.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_8.io.en <= _T_33 @[lib.scala 345:16] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 346:23] io.lsu_bus_obuf_c1_clk <= rvclkhdr_8.io.l1clk @[lsu_clkdomain.scala 93:26] node _T_34 = bits(lsu_bus_buf_c1_clken, 0, 0) @[lsu_clkdomain.scala 94:65] - inst rvclkhdr_9 of rvclkhdr_811 @[el2_lib.scala 483:22] + inst rvclkhdr_9 of rvclkhdr_811 @[lib.scala 343:22] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset - rvclkhdr_9.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_9.io.en <= _T_34 @[el2_lib.scala 485:16] - rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_9.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_9.io.en <= _T_34 @[lib.scala 345:16] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 346:23] io.lsu_bus_buf_c1_clk <= rvclkhdr_9.io.l1clk @[lsu_clkdomain.scala 94:26] node _T_35 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_clkdomain.scala 95:62] - inst rvclkhdr_10 of rvclkhdr_812 @[el2_lib.scala 483:22] + inst rvclkhdr_10 of rvclkhdr_812 @[lib.scala 343:22] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset - rvclkhdr_10.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_10.io.en <= _T_35 @[el2_lib.scala 485:16] - rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_10.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_10.io.en <= _T_35 @[lib.scala 345:16] + rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 346:23] io.lsu_busm_clk <= rvclkhdr_10.io.l1clk @[lsu_clkdomain.scala 95:26] node _T_36 = bits(lsu_free_c2_clken, 0, 0) @[lsu_clkdomain.scala 96:62] - inst rvclkhdr_11 of rvclkhdr_813 @[el2_lib.scala 483:22] + inst rvclkhdr_11 of rvclkhdr_813 @[lib.scala 343:22] rvclkhdr_11.clock <= clock rvclkhdr_11.reset <= reset - rvclkhdr_11.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_11.io.en <= _T_36 @[el2_lib.scala 485:16] - rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_11.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_11.io.en <= _T_36 @[lib.scala 345:16] + rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 346:23] io.lsu_free_c2_clk <= rvclkhdr_11.io.l1clk @[lsu_clkdomain.scala 96:26] extmodule gated_latch_814 : @@ -94668,15 +94660,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_814 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_814 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_815 : output Q : Clock @@ -94692,15 +94684,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_815 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_815 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_816 : output Q : Clock @@ -94716,15 +94708,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_816 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_816 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_817 : output Q : Clock @@ -94740,15 +94732,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_817 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_817 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_818 : output Q : Clock @@ -94764,15 +94756,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_818 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_818 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_819 : output Q : Clock @@ -94788,15 +94780,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_819 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_819 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_820 : output Q : Clock @@ -94812,15 +94804,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_820 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_820 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_821 : output Q : Clock @@ -94836,15 +94828,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_821 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_821 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_822 : output Q : Clock @@ -94860,15 +94852,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_822 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_822 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_823 : output Q : Clock @@ -94884,15 +94876,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_823 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_823 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_824 : output Q : Clock @@ -94908,15 +94900,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_824 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_824 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_825 : output Q : Clock @@ -94932,15 +94924,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_825 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_825 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] module lsu_bus_buffer : input clock : Clock @@ -96238,28 +96230,28 @@ circuit quasar_wrapper : when ibuf_wr_en : @[Reg.scala 28:19] ibuf_sz <= ibuf_sz_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - inst rvclkhdr of rvclkhdr_814 @[el2_lib.scala 508:23] + inst rvclkhdr of rvclkhdr_814 @[lib.scala 368:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr.io.en <= ibuf_wr_en @[el2_lib.scala 511:17] - rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_1012 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_1012 <= ibuf_addr_in @[el2_lib.scala 514:16] + rvclkhdr.io.clk <= clock @[lib.scala 370:18] + rvclkhdr.io.en <= ibuf_wr_en @[lib.scala 371:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_1012 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1012 <= ibuf_addr_in @[lib.scala 374:16] ibuf_addr <= _T_1012 @[lsu_bus_buffer.scala 250:13] reg _T_1013 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when ibuf_wr_en : @[Reg.scala 28:19] _T_1013 <= ibuf_byteen_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] ibuf_byteen <= _T_1013 @[lsu_bus_buffer.scala 251:15] - inst rvclkhdr_1 of rvclkhdr_815 @[el2_lib.scala 508:23] + inst rvclkhdr_1 of rvclkhdr_815 @[lib.scala 368:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_1.io.en <= ibuf_wr_en @[el2_lib.scala 511:17] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_1014 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_1014 <= ibuf_data_in @[el2_lib.scala 514:16] + rvclkhdr_1.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_1.io.en <= ibuf_wr_en @[lib.scala 371:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_1014 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1014 <= ibuf_data_in @[lib.scala 374:16] ibuf_data <= _T_1014 @[lsu_bus_buffer.scala 252:13] reg _T_1015 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 253:55] _T_1015 <= ibuf_timer_in @[lsu_bus_buffer.scala 253:55] @@ -97292,27 +97284,27 @@ circuit quasar_wrapper : when obuf_wr_en : @[Reg.scala 28:19] obuf_sz <= obuf_sz_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - inst rvclkhdr_2 of rvclkhdr_816 @[el2_lib.scala 508:23] + inst rvclkhdr_2 of rvclkhdr_816 @[lib.scala 368:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_2.io.en <= obuf_wr_en @[el2_lib.scala 511:17] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_1851 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_1851 <= obuf_addr_in @[el2_lib.scala 514:16] + rvclkhdr_2.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_2.io.en <= obuf_wr_en @[lib.scala 371:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_1851 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1851 <= obuf_addr_in @[lib.scala 374:16] obuf_addr <= _T_1851 @[lsu_bus_buffer.scala 358:13] reg obuf_byteen : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] obuf_byteen <= obuf_byteen_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - inst rvclkhdr_3 of rvclkhdr_817 @[el2_lib.scala 508:23] + inst rvclkhdr_3 of rvclkhdr_817 @[lib.scala 368:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_3.io.en <= obuf_wr_en @[el2_lib.scala 511:17] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg obuf_data : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - obuf_data <= obuf_data_in @[el2_lib.scala 514:16] + rvclkhdr_3.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_3.io.en <= obuf_wr_en @[lib.scala 371:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg obuf_data : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + obuf_data <= obuf_data_in @[lib.scala 374:16] reg _T_1852 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 361:54] _T_1852 <= obuf_wr_timer_in @[lsu_bus_buffer.scala 361:54] obuf_wr_timer <= _T_1852 @[lsu_bus_buffer.scala 361:17] @@ -100360,41 +100352,41 @@ circuit quasar_wrapper : buf_sz[2] <= _T_4369 @[lsu_bus_buffer.scala 514:10] buf_sz[3] <= _T_4371 @[lsu_bus_buffer.scala 514:10] node _T_4372 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 515:80] - inst rvclkhdr_4 of rvclkhdr_818 @[el2_lib.scala 508:23] + inst rvclkhdr_4 of rvclkhdr_818 @[lib.scala 368:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_4.io.en <= _T_4372 @[el2_lib.scala 511:17] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_4373 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_4373 <= buf_addr_in[0] @[el2_lib.scala 514:16] + rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_4.io.en <= _T_4372 @[lib.scala 371:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_4373 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_4373 <= buf_addr_in[0] @[lib.scala 374:16] node _T_4374 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 515:80] - inst rvclkhdr_5 of rvclkhdr_819 @[el2_lib.scala 508:23] + inst rvclkhdr_5 of rvclkhdr_819 @[lib.scala 368:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_5.io.en <= _T_4374 @[el2_lib.scala 511:17] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_4375 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_4375 <= buf_addr_in[1] @[el2_lib.scala 514:16] + rvclkhdr_5.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_5.io.en <= _T_4374 @[lib.scala 371:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_4375 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_4375 <= buf_addr_in[1] @[lib.scala 374:16] node _T_4376 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 515:80] - inst rvclkhdr_6 of rvclkhdr_820 @[el2_lib.scala 508:23] + inst rvclkhdr_6 of rvclkhdr_820 @[lib.scala 368:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset - rvclkhdr_6.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_6.io.en <= _T_4376 @[el2_lib.scala 511:17] - rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_4377 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_4377 <= buf_addr_in[2] @[el2_lib.scala 514:16] + rvclkhdr_6.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_6.io.en <= _T_4376 @[lib.scala 371:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_4377 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_4377 <= buf_addr_in[2] @[lib.scala 374:16] node _T_4378 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 515:80] - inst rvclkhdr_7 of rvclkhdr_821 @[el2_lib.scala 508:23] + inst rvclkhdr_7 of rvclkhdr_821 @[lib.scala 368:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset - rvclkhdr_7.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_7.io.en <= _T_4378 @[el2_lib.scala 511:17] - rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_4379 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_4379 <= buf_addr_in[3] @[el2_lib.scala 514:16] + rvclkhdr_7.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_7.io.en <= _T_4378 @[lib.scala 371:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_4379 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_4379 <= buf_addr_in[3] @[lib.scala 374:16] buf_addr[0] <= _T_4373 @[lsu_bus_buffer.scala 515:12] buf_addr[1] <= _T_4375 @[lsu_bus_buffer.scala 515:12] buf_addr[2] <= _T_4377 @[lsu_bus_buffer.scala 515:12] @@ -100423,38 +100415,38 @@ circuit quasar_wrapper : buf_byteen[1] <= _T_4383 @[lsu_bus_buffer.scala 516:14] buf_byteen[2] <= _T_4385 @[lsu_bus_buffer.scala 516:14] buf_byteen[3] <= _T_4387 @[lsu_bus_buffer.scala 516:14] - inst rvclkhdr_8 of rvclkhdr_822 @[el2_lib.scala 508:23] + inst rvclkhdr_8 of rvclkhdr_822 @[lib.scala 368:23] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset - rvclkhdr_8.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_8.io.en <= buf_data_en[0] @[el2_lib.scala 511:17] - rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_4388 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_4388 <= buf_data_in[0] @[el2_lib.scala 514:16] - inst rvclkhdr_9 of rvclkhdr_823 @[el2_lib.scala 508:23] + rvclkhdr_8.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_8.io.en <= buf_data_en[0] @[lib.scala 371:17] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_4388 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_4388 <= buf_data_in[0] @[lib.scala 374:16] + inst rvclkhdr_9 of rvclkhdr_823 @[lib.scala 368:23] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset - rvclkhdr_9.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_9.io.en <= buf_data_en[1] @[el2_lib.scala 511:17] - rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_4389 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_4389 <= buf_data_in[1] @[el2_lib.scala 514:16] - inst rvclkhdr_10 of rvclkhdr_824 @[el2_lib.scala 508:23] + rvclkhdr_9.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_9.io.en <= buf_data_en[1] @[lib.scala 371:17] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_4389 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_4389 <= buf_data_in[1] @[lib.scala 374:16] + inst rvclkhdr_10 of rvclkhdr_824 @[lib.scala 368:23] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset - rvclkhdr_10.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_10.io.en <= buf_data_en[2] @[el2_lib.scala 511:17] - rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_4390 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_4390 <= buf_data_in[2] @[el2_lib.scala 514:16] - inst rvclkhdr_11 of rvclkhdr_825 @[el2_lib.scala 508:23] + rvclkhdr_10.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_10.io.en <= buf_data_en[2] @[lib.scala 371:17] + rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_4390 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_4390 <= buf_data_in[2] @[lib.scala 374:16] + inst rvclkhdr_11 of rvclkhdr_825 @[lib.scala 368:23] rvclkhdr_11.clock <= clock rvclkhdr_11.reset <= reset - rvclkhdr_11.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_11.io.en <= buf_data_en[3] @[el2_lib.scala 511:17] - rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_4391 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_4391 <= buf_data_in[3] @[el2_lib.scala 514:16] + rvclkhdr_11.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_11.io.en <= buf_data_en[3] @[lib.scala 371:17] + rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_4391 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_4391 <= buf_data_in[3] @[lib.scala 374:16] buf_data[0] <= _T_4388 @[lsu_bus_buffer.scala 517:12] buf_data[1] <= _T_4389 @[lsu_bus_buffer.scala 517:12] buf_data[2] <= _T_4390 @[lsu_bus_buffer.scala 517:12] @@ -102430,15 +102422,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_826 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_826 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_827 : output Q : Clock @@ -102454,15 +102446,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_827 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_827 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_828 : output Q : Clock @@ -102478,15 +102470,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_828 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_828 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_829 : output Q : Clock @@ -102502,15 +102494,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_829 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_829 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_830 : output Q : Clock @@ -102526,15 +102518,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_830 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_830 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] module pic_ctrl : input clock : Clock @@ -102739,49 +102731,49 @@ circuit quasar_wrapper : node _T_27 = and(raddr_config_gw_base_match, picm_rden_ff) @[pic_ctrl.scala 129:108] node _T_28 = or(_T_26, _T_27) @[pic_ctrl.scala 129:76] node gw_config_c1_clken = or(_T_28, io.clk_override) @[pic_ctrl.scala 129:124] - inst rvclkhdr of rvclkhdr_826 @[el2_lib.scala 483:22] + inst rvclkhdr of rvclkhdr_826 @[lib.scala 343:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr.io.en <= pic_raddr_c1_clken @[el2_lib.scala 485:16] - rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr.io.clk <= clock @[lib.scala 344:17] + rvclkhdr.io.en <= pic_raddr_c1_clken @[lib.scala 345:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] pic_raddr_c1_clk <= rvclkhdr.io.l1clk @[pic_ctrl.scala 132:21] - inst rvclkhdr_1 of rvclkhdr_827 @[el2_lib.scala 483:22] + inst rvclkhdr_1 of rvclkhdr_827 @[lib.scala 343:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_1.io.en <= pic_data_c1_clken @[el2_lib.scala 485:16] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_1.io.en <= pic_data_c1_clken @[lib.scala 345:16] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] pic_data_c1_clk <= rvclkhdr_1.io.l1clk @[pic_ctrl.scala 133:21] node _T_29 = bits(pic_pri_c1_clken, 0, 0) @[pic_ctrl.scala 134:56] - inst rvclkhdr_2 of rvclkhdr_828 @[el2_lib.scala 483:22] + inst rvclkhdr_2 of rvclkhdr_828 @[lib.scala 343:22] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_2.io.en <= _T_29 @[el2_lib.scala 485:16] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_2.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_2.io.en <= _T_29 @[lib.scala 345:16] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 346:23] pic_pri_c1_clk <= rvclkhdr_2.io.l1clk @[pic_ctrl.scala 134:21] node _T_30 = bits(pic_int_c1_clken, 0, 0) @[pic_ctrl.scala 135:56] - inst rvclkhdr_3 of rvclkhdr_829 @[el2_lib.scala 483:22] + inst rvclkhdr_3 of rvclkhdr_829 @[lib.scala 343:22] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_3.io.en <= _T_30 @[el2_lib.scala 485:16] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_3.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_3.io.en <= _T_30 @[lib.scala 345:16] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 346:23] pic_int_c1_clk <= rvclkhdr_3.io.l1clk @[pic_ctrl.scala 135:21] node _T_31 = bits(gw_config_c1_clken, 0, 0) @[pic_ctrl.scala 136:58] - inst rvclkhdr_4 of rvclkhdr_830 @[el2_lib.scala 483:22] + inst rvclkhdr_4 of rvclkhdr_830 @[lib.scala 343:22] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_4.io.en <= _T_31 @[el2_lib.scala 485:16] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_4.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_4.io.en <= _T_31 @[lib.scala 345:16] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 346:23] gw_config_c1_clk <= rvclkhdr_4.io.l1clk @[pic_ctrl.scala 136:21] node _T_32 = bits(io.extintsrc_req, 31, 1) @[pic_ctrl.scala 139:58] - reg _T_33 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 177:81] - _T_33 <= _T_32 @[el2_lib.scala 177:81] - reg _T_34 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 177:58] - _T_34 <= _T_33 @[el2_lib.scala 177:58] + reg _T_33 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 37:81] + _T_33 <= _T_32 @[lib.scala 37:81] + reg _T_34 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 37:58] + _T_34 <= _T_33 @[lib.scala 37:58] node _T_35 = bits(io.extintsrc_req, 0, 0) @[pic_ctrl.scala 139:113] node extintsrc_req_sync = cat(_T_34, _T_35) @[Cat.scala 29:58] node _T_36 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 141:122] @@ -106723,15 +106715,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_831 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_831 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_832 : output Q : Clock @@ -106747,15 +106739,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_832 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_832 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_833 : output Q : Clock @@ -106771,15 +106763,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_833 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_833 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_834 : output Q : Clock @@ -106795,15 +106787,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_834 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_834 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_835 : output Q : Clock @@ -106819,15 +106811,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_835 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_835 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_836 : output Q : Clock @@ -106843,15 +106835,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_836 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_836 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_837 : output Q : Clock @@ -106867,15 +106859,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_837 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_837 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_838 : output Q : Clock @@ -106891,15 +106883,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_838 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_838 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_839 : output Q : Clock @@ -106915,15 +106907,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_839 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_839 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_840 : output Q : Clock @@ -106939,15 +106931,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_840 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_840 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_841 : output Q : Clock @@ -106963,15 +106955,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_841 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_841 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_842 : output Q : Clock @@ -106987,15 +106979,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_842 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_842 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_843 : output Q : Clock @@ -107011,15 +107003,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_843 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_843 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_844 : output Q : Clock @@ -107035,15 +107027,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_844 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_844 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_845 : output Q : Clock @@ -107059,15 +107051,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_845 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_845 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_846 : output Q : Clock @@ -107083,15 +107075,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_846 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_846 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] module dma_ctrl : input clock : Clock @@ -107226,26 +107218,26 @@ circuit quasar_wrapper : wire fifo_byteen_in : UInt<8> fifo_byteen_in <= UInt<1>("h00") node _T = bits(dma_mem_addr_int, 31, 0) @[dma_ctrl.scala 188:95] - node _T_1 = bits(_T, 31, 28) @[el2_lib.scala 496:27] - node dma_mem_addr_in_dccm_region_nc = eq(_T_1, UInt<4>("h0f")) @[el2_lib.scala 496:49] - wire dma_mem_addr_in_dccm : UInt<1> @[el2_lib.scala 497:26] - node _T_2 = bits(_T, 31, 16) @[el2_lib.scala 501:24] - node _T_3 = eq(_T_2, UInt<16>("h0f004")) @[el2_lib.scala 501:39] - dma_mem_addr_in_dccm <= _T_3 @[el2_lib.scala 501:16] + node _T_1 = bits(_T, 31, 28) @[lib.scala 356:27] + node dma_mem_addr_in_dccm_region_nc = eq(_T_1, UInt<4>("h0f")) @[lib.scala 356:49] + wire dma_mem_addr_in_dccm : UInt<1> @[lib.scala 357:26] + node _T_2 = bits(_T, 31, 16) @[lib.scala 361:24] + node _T_3 = eq(_T_2, UInt<16>("h0f004")) @[lib.scala 361:39] + dma_mem_addr_in_dccm <= _T_3 @[lib.scala 361:16] node _T_4 = bits(dma_mem_addr_int, 31, 0) @[dma_ctrl.scala 192:93] - node _T_5 = bits(_T_4, 31, 28) @[el2_lib.scala 496:27] - node dma_mem_addr_in_pic_region_nc = eq(_T_5, UInt<4>("h0f")) @[el2_lib.scala 496:49] - wire dma_mem_addr_in_pic : UInt<1> @[el2_lib.scala 497:26] - node _T_6 = bits(_T_4, 31, 15) @[el2_lib.scala 501:24] - node _T_7 = eq(_T_6, UInt<17>("h01e018")) @[el2_lib.scala 501:39] - dma_mem_addr_in_pic <= _T_7 @[el2_lib.scala 501:16] + node _T_5 = bits(_T_4, 31, 28) @[lib.scala 356:27] + node dma_mem_addr_in_pic_region_nc = eq(_T_5, UInt<4>("h0f")) @[lib.scala 356:49] + wire dma_mem_addr_in_pic : UInt<1> @[lib.scala 357:26] + node _T_6 = bits(_T_4, 31, 15) @[lib.scala 361:24] + node _T_7 = eq(_T_6, UInt<17>("h01e018")) @[lib.scala 361:39] + dma_mem_addr_in_pic <= _T_7 @[lib.scala 361:16] node _T_8 = bits(dma_mem_addr_int, 31, 0) @[dma_ctrl.scala 196:111] - node _T_9 = bits(_T_8, 31, 28) @[el2_lib.scala 496:27] - node dma_mem_addr_in_iccm_region_nc = eq(_T_9, UInt<4>("h0e")) @[el2_lib.scala 496:49] - wire dma_mem_addr_in_iccm : UInt<1> @[el2_lib.scala 497:26] - node _T_10 = bits(_T_8, 31, 16) @[el2_lib.scala 501:24] - node _T_11 = eq(_T_10, UInt<16>("h0ee00")) @[el2_lib.scala 501:39] - dma_mem_addr_in_iccm <= _T_11 @[el2_lib.scala 501:16] + node _T_9 = bits(_T_8, 31, 28) @[lib.scala 356:27] + node dma_mem_addr_in_iccm_region_nc = eq(_T_9, UInt<4>("h0e")) @[lib.scala 356:49] + wire dma_mem_addr_in_iccm : UInt<1> @[lib.scala 357:26] + node _T_10 = bits(_T_8, 31, 16) @[lib.scala 361:24] + node _T_11 = eq(_T_10, UInt<16>("h0ee00")) @[lib.scala 361:39] + dma_mem_addr_in_iccm <= _T_11 @[lib.scala 361:16] node _T_12 = bits(io.dbg_dma.dbg_ib.dbg_cmd_valid, 0, 0) @[dma_ctrl.scala 200:66] node _T_13 = bits(io.dbg_dma.dbg_ib.dbg_cmd_addr, 31, 0) @[dma_ctrl.scala 200:104] node _T_14 = bits(bus_cmd_addr, 31, 0) @[dma_ctrl.scala 200:124] @@ -108102,54 +108094,54 @@ circuit quasar_wrapper : node _T_803 = cat(_T_802, _T_771) @[Cat.scala 29:58] fifo_done_bus <= _T_803 @[dma_ctrl.scala 243:21] node _T_804 = bits(fifo_cmd_en, 0, 0) @[dma_ctrl.scala 245:84] - inst rvclkhdr of rvclkhdr_831 @[el2_lib.scala 508:23] + inst rvclkhdr of rvclkhdr_831 @[lib.scala 368:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr.io.en <= _T_804 @[el2_lib.scala 511:17] - rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_805 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_805 <= fifo_addr_in @[el2_lib.scala 514:16] + rvclkhdr.io.clk <= clock @[lib.scala 370:18] + rvclkhdr.io.en <= _T_804 @[lib.scala 371:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_805 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_805 <= fifo_addr_in @[lib.scala 374:16] fifo_addr[0] <= _T_805 @[dma_ctrl.scala 245:49] node _T_806 = bits(fifo_cmd_en, 1, 1) @[dma_ctrl.scala 245:84] - inst rvclkhdr_1 of rvclkhdr_832 @[el2_lib.scala 508:23] + inst rvclkhdr_1 of rvclkhdr_832 @[lib.scala 368:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_1.io.en <= _T_806 @[el2_lib.scala 511:17] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_807 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_807 <= fifo_addr_in @[el2_lib.scala 514:16] + rvclkhdr_1.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_1.io.en <= _T_806 @[lib.scala 371:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_807 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_807 <= fifo_addr_in @[lib.scala 374:16] fifo_addr[1] <= _T_807 @[dma_ctrl.scala 245:49] node _T_808 = bits(fifo_cmd_en, 2, 2) @[dma_ctrl.scala 245:84] - inst rvclkhdr_2 of rvclkhdr_833 @[el2_lib.scala 508:23] + inst rvclkhdr_2 of rvclkhdr_833 @[lib.scala 368:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset - rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_2.io.en <= _T_808 @[el2_lib.scala 511:17] - rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_809 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_809 <= fifo_addr_in @[el2_lib.scala 514:16] + rvclkhdr_2.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_2.io.en <= _T_808 @[lib.scala 371:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_809 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_809 <= fifo_addr_in @[lib.scala 374:16] fifo_addr[2] <= _T_809 @[dma_ctrl.scala 245:49] node _T_810 = bits(fifo_cmd_en, 3, 3) @[dma_ctrl.scala 245:84] - inst rvclkhdr_3 of rvclkhdr_834 @[el2_lib.scala 508:23] + inst rvclkhdr_3 of rvclkhdr_834 @[lib.scala 368:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset - rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_3.io.en <= _T_810 @[el2_lib.scala 511:17] - rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_811 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_811 <= fifo_addr_in @[el2_lib.scala 514:16] + rvclkhdr_3.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_3.io.en <= _T_810 @[lib.scala 371:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_811 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_811 <= fifo_addr_in @[lib.scala 374:16] fifo_addr[3] <= _T_811 @[dma_ctrl.scala 245:49] node _T_812 = bits(fifo_cmd_en, 4, 4) @[dma_ctrl.scala 245:84] - inst rvclkhdr_4 of rvclkhdr_835 @[el2_lib.scala 508:23] + inst rvclkhdr_4 of rvclkhdr_835 @[lib.scala 368:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset - rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_4.io.en <= _T_812 @[el2_lib.scala 511:17] - rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_813 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_813 <= fifo_addr_in @[el2_lib.scala 514:16] + rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_4.io.en <= _T_812 @[lib.scala 371:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_813 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_813 <= fifo_addr_in @[lib.scala 374:16] fifo_addr[4] <= _T_813 @[dma_ctrl.scala 245:49] node _T_814 = bits(fifo_sz_in, 2, 0) @[dma_ctrl.scala 247:100] node _T_815 = bits(fifo_cmd_en, 0, 0) @[dma_ctrl.scala 247:123] @@ -108317,54 +108309,54 @@ circuit quasar_wrapper : node _T_890 = cat(_T_889, _T_878) @[Cat.scala 29:58] fifo_dbg <= _T_890 @[dma_ctrl.scala 255:21] node _T_891 = bits(fifo_data_en, 0, 0) @[dma_ctrl.scala 257:88] - inst rvclkhdr_5 of rvclkhdr_836 @[el2_lib.scala 508:23] + inst rvclkhdr_5 of rvclkhdr_836 @[lib.scala 368:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_5.io.en <= _T_891 @[el2_lib.scala 511:17] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_892 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_892 <= fifo_data_in[0] @[el2_lib.scala 514:16] + rvclkhdr_5.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_5.io.en <= _T_891 @[lib.scala 371:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_892 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_892 <= fifo_data_in[0] @[lib.scala 374:16] fifo_data[0] <= _T_892 @[dma_ctrl.scala 257:49] node _T_893 = bits(fifo_data_en, 1, 1) @[dma_ctrl.scala 257:88] - inst rvclkhdr_6 of rvclkhdr_837 @[el2_lib.scala 508:23] + inst rvclkhdr_6 of rvclkhdr_837 @[lib.scala 368:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset - rvclkhdr_6.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_6.io.en <= _T_893 @[el2_lib.scala 511:17] - rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_894 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_894 <= fifo_data_in[1] @[el2_lib.scala 514:16] + rvclkhdr_6.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_6.io.en <= _T_893 @[lib.scala 371:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_894 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_894 <= fifo_data_in[1] @[lib.scala 374:16] fifo_data[1] <= _T_894 @[dma_ctrl.scala 257:49] node _T_895 = bits(fifo_data_en, 2, 2) @[dma_ctrl.scala 257:88] - inst rvclkhdr_7 of rvclkhdr_838 @[el2_lib.scala 508:23] + inst rvclkhdr_7 of rvclkhdr_838 @[lib.scala 368:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset - rvclkhdr_7.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_7.io.en <= _T_895 @[el2_lib.scala 511:17] - rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_896 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_896 <= fifo_data_in[2] @[el2_lib.scala 514:16] + rvclkhdr_7.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_7.io.en <= _T_895 @[lib.scala 371:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_896 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_896 <= fifo_data_in[2] @[lib.scala 374:16] fifo_data[2] <= _T_896 @[dma_ctrl.scala 257:49] node _T_897 = bits(fifo_data_en, 3, 3) @[dma_ctrl.scala 257:88] - inst rvclkhdr_8 of rvclkhdr_839 @[el2_lib.scala 508:23] + inst rvclkhdr_8 of rvclkhdr_839 @[lib.scala 368:23] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset - rvclkhdr_8.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_8.io.en <= _T_897 @[el2_lib.scala 511:17] - rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_898 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_898 <= fifo_data_in[3] @[el2_lib.scala 514:16] + rvclkhdr_8.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_8.io.en <= _T_897 @[lib.scala 371:17] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_898 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_898 <= fifo_data_in[3] @[lib.scala 374:16] fifo_data[3] <= _T_898 @[dma_ctrl.scala 257:49] node _T_899 = bits(fifo_data_en, 4, 4) @[dma_ctrl.scala 257:88] - inst rvclkhdr_9 of rvclkhdr_840 @[el2_lib.scala 508:23] + inst rvclkhdr_9 of rvclkhdr_840 @[lib.scala 368:23] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset - rvclkhdr_9.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_9.io.en <= _T_899 @[el2_lib.scala 511:17] - rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_900 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_900 <= fifo_data_in[4] @[el2_lib.scala 514:16] + rvclkhdr_9.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_9.io.en <= _T_899 @[lib.scala 371:17] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_900 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_900 <= fifo_data_in[4] @[lib.scala 374:16] fifo_data[4] <= _T_900 @[dma_ctrl.scala 257:49] node _T_901 = bits(fifo_cmd_en, 0, 0) @[dma_ctrl.scala 259:120] reg _T_902 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] @@ -108845,23 +108837,23 @@ circuit quasar_wrapper : wrbuf_sz <= io.dma_axi.aw.bits.size @[Reg.scala 28:23] skip @[Reg.scala 28:19] node _T_1212 = and(wrbuf_en, io.dma_bus_clk_en) @[dma_ctrl.scala 430:68] - inst rvclkhdr_10 of rvclkhdr_844 @[el2_lib.scala 508:23] + inst rvclkhdr_10 of rvclkhdr_844 @[lib.scala 368:23] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset - rvclkhdr_10.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_10.io.en <= _T_1212 @[el2_lib.scala 511:17] - rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg wrbuf_addr : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - wrbuf_addr <= io.dma_axi.aw.bits.addr @[el2_lib.scala 514:16] + rvclkhdr_10.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_10.io.en <= _T_1212 @[lib.scala 371:17] + rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg wrbuf_addr : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + wrbuf_addr <= io.dma_axi.aw.bits.addr @[lib.scala 374:16] node _T_1213 = and(wrbuf_data_en, io.dma_bus_clk_en) @[dma_ctrl.scala 432:72] - inst rvclkhdr_11 of rvclkhdr_845 @[el2_lib.scala 508:23] + inst rvclkhdr_11 of rvclkhdr_845 @[lib.scala 368:23] rvclkhdr_11.clock <= clock rvclkhdr_11.reset <= reset - rvclkhdr_11.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_11.io.en <= _T_1213 @[el2_lib.scala 511:17] - rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg wrbuf_data : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - wrbuf_data <= io.dma_axi.w.bits.data @[el2_lib.scala 514:16] + rvclkhdr_11.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_11.io.en <= _T_1213 @[lib.scala 371:17] + rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg wrbuf_data : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + wrbuf_data <= io.dma_axi.w.bits.data @[lib.scala 374:16] reg wrbuf_byteen : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when wrbuf_data_en : @[Reg.scala 28:19] wrbuf_byteen <= io.dma_axi.w.bits.strb @[Reg.scala 28:23] @@ -108887,14 +108879,14 @@ circuit quasar_wrapper : rdbuf_sz <= io.dma_axi.ar.bits.size @[Reg.scala 28:23] skip @[Reg.scala 28:19] node _T_1221 = and(rdbuf_en, io.dma_bus_clk_en) @[dma_ctrl.scala 454:61] - inst rvclkhdr_12 of rvclkhdr_846 @[el2_lib.scala 508:23] + inst rvclkhdr_12 of rvclkhdr_846 @[lib.scala 368:23] rvclkhdr_12.clock <= clock rvclkhdr_12.reset <= reset - rvclkhdr_12.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_12.io.en <= _T_1221 @[el2_lib.scala 511:17] - rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg rdbuf_addr : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - rdbuf_addr <= io.dma_axi.ar.bits.addr @[el2_lib.scala 514:16] + rvclkhdr_12.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_12.io.en <= _T_1221 @[lib.scala 371:17] + rvclkhdr_12.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg rdbuf_addr : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + rdbuf_addr <= io.dma_axi.ar.bits.addr @[lib.scala 374:16] node _T_1222 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[dma_ctrl.scala 456:44] node _T_1223 = and(wrbuf_vld, _T_1222) @[dma_ctrl.scala 456:42] node _T_1224 = not(_T_1223) @[dma_ctrl.scala 456:30] @@ -108997,15 +108989,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_847 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_847 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] extmodule gated_latch_848 : output Q : Clock @@ -109021,15 +109013,15 @@ circuit quasar_wrapper : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of gated_latch_848 @[el2_lib.scala 474:26] + inst clkhdr of gated_latch_848 @[lib.scala 334:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] - clkhdr.CK <= io.clk @[el2_lib.scala 476:18] - clkhdr.EN <= io.en @[el2_lib.scala 477:18] - clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] module quasar : input clock : Clock @@ -109066,19 +109058,19 @@ circuit quasar_wrapper : node _T_5 = eq(dec.io.dec_pause_state_cg, UInt<1>("h00")) @[quasar.scala 167:23] node _T_6 = or(_T_5, dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r) @[quasar.scala 167:50] node active_state = or(_T_6, dec.io.dec_tlu_misc_clk_override) @[quasar.scala 167:98] - inst rvclkhdr of rvclkhdr_847 @[el2_lib.scala 483:22] + inst rvclkhdr of rvclkhdr_847 @[lib.scala 343:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset - rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr.io.en <= UInt<1>("h01") @[el2_lib.scala 485:16] - rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr.io.clk <= clock @[lib.scala 344:17] + rvclkhdr.io.en <= UInt<1>("h01") @[lib.scala 345:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] node _T_7 = bits(active_state, 0, 0) @[quasar.scala 169:49] - inst rvclkhdr_1 of rvclkhdr_848 @[el2_lib.scala 483:22] + inst rvclkhdr_1 of rvclkhdr_848 @[lib.scala 343:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_1.io.en <= _T_7 @[el2_lib.scala 485:16] - rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_1.io.en <= _T_7 @[lib.scala 345:16] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] node core_dbg_cmd_done = or(dma_ctrl.io.dma_dbg_cmd_done, dec.io.dec_dbg_cmd_done) @[quasar.scala 170:56] node core_dbg_cmd_fail = or(dma_ctrl.io.dma_dbg_cmd_fail, dec.io.dec_dbg_cmd_fail) @[quasar.scala 171:56] node core_dbg_rddata = mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) @[quasar.scala 172:28] diff --git a/quasar_wrapper.v b/quasar_wrapper.v index c90186cd..0d9841d2 100644 --- a/quasar_wrapper.v +++ b/quasar_wrapper.v @@ -4,20 +4,20 @@ module rvclkhdr( input io_en, input io_scan_mode ); - wire clkhdr_Q; // @[el2_lib.scala 474:26] - wire clkhdr_CK; // @[el2_lib.scala 474:26] - wire clkhdr_EN; // @[el2_lib.scala 474:26] - wire clkhdr_SE; // @[el2_lib.scala 474:26] - gated_latch clkhdr ( // @[el2_lib.scala 474:26] + wire clkhdr_Q; // @[lib.scala 334:26] + wire clkhdr_CK; // @[lib.scala 334:26] + wire clkhdr_EN; // @[lib.scala 334:26] + wire clkhdr_SE; // @[lib.scala 334:26] + gated_latch clkhdr ( // @[lib.scala 334:26] .Q(clkhdr_Q), .CK(clkhdr_CK), .EN(clkhdr_EN), .SE(clkhdr_SE) ); - assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14] - assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18] - assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18] - assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18] + assign io_l1clk = clkhdr_Q; // @[lib.scala 335:14] + assign clkhdr_CK = io_clk; // @[lib.scala 336:18] + assign clkhdr_EN = io_en; // @[lib.scala 337:18] + assign clkhdr_SE = io_scan_mode; // @[lib.scala 338:18] endmodule module ifu_mem_ctl( input clock, @@ -594,382 +594,382 @@ module ifu_mem_ctl( reg [31:0] _RAND_471; reg [31:0] _RAND_472; `endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_1_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_1_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_2_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_2_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_3_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_3_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_4_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_4_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_5_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_5_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_6_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_6_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_7_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_7_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_8_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_8_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_9_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_9_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_10_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_10_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_11_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_11_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_12_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_12_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_12_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_12_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_13_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_13_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_13_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_13_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_14_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_14_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_14_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_14_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_15_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_15_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_15_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_15_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_16_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_16_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_16_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_16_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_17_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_17_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_17_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_17_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_18_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_18_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_18_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_18_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_19_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_19_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_19_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_19_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_20_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_20_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_20_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_20_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_21_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_21_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_21_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_21_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_22_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_22_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_22_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_22_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_23_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_23_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_23_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_23_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_24_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_24_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_24_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_24_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_25_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_25_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_25_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_25_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_26_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_26_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_26_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_26_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_27_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_27_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_27_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_27_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_28_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_28_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_28_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_28_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_29_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_29_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_29_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_29_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_30_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_30_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_30_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_30_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_31_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_31_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_31_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_31_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_32_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_32_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_32_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_32_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_33_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_33_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_33_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_33_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_34_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_34_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_34_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_34_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_35_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_35_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_35_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_35_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_36_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_36_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_36_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_36_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_37_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_37_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_37_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_37_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_38_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_38_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_38_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_38_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_39_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_39_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_39_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_39_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_40_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_40_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_40_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_40_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_41_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_41_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_41_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_41_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_42_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_42_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_42_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_42_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_43_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_43_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_43_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_43_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_44_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_44_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_44_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_44_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_45_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_45_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_45_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_45_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_46_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_46_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_46_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_46_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_47_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_47_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_47_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_47_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_48_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_48_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_48_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_48_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_49_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_49_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_49_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_49_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_50_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_50_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_50_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_50_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_51_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_51_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_51_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_51_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_52_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_52_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_52_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_52_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_53_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_53_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_53_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_53_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_54_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_54_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_54_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_54_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_55_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_55_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_55_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_55_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_56_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_56_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_56_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_56_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_57_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_57_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_57_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_57_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_58_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_58_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_58_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_58_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_59_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_59_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_59_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_59_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_60_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_60_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_60_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_60_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_61_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_61_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_61_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_61_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_62_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_62_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_62_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_62_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_63_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_63_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_63_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_63_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_64_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_64_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_64_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_64_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_65_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_65_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_65_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_65_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_66_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_66_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_66_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_66_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_67_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_67_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_67_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_67_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_68_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_68_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_68_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_68_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_69_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_69_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_69_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_69_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_70_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_70_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_70_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_70_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_71_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_71_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_71_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_71_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_72_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_72_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_72_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_72_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_73_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_73_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_73_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_73_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_74_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_74_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_74_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_74_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_75_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_75_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_75_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_75_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_76_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_76_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_76_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_76_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_77_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_77_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_77_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_77_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_78_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_78_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_78_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_78_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_79_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_79_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_79_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_79_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_80_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_80_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_80_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_80_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_81_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_81_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_81_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_81_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_82_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_82_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_82_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_82_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_83_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_83_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_83_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_83_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_84_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_84_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_84_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_84_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_85_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_85_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_85_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_85_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_86_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_86_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_86_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_86_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_87_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_87_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_87_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_87_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_88_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_88_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_88_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_88_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_89_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_89_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_89_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_89_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_90_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_90_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_90_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_90_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_91_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_91_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_91_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_91_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_92_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_92_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_92_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_92_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_93_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_93_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_93_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_93_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_io_en; // @[lib.scala 343:22] + wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_en; // @[lib.scala 343:22] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_2_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_2_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_2_io_en; // @[lib.scala 343:22] + wire rvclkhdr_2_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_3_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_3_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_3_io_en; // @[lib.scala 343:22] + wire rvclkhdr_3_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_4_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_4_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_4_io_en; // @[lib.scala 343:22] + wire rvclkhdr_4_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_5_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_5_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_5_io_en; // @[lib.scala 343:22] + wire rvclkhdr_5_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_6_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_6_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_6_io_en; // @[lib.scala 343:22] + wire rvclkhdr_6_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_7_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_7_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_7_io_en; // @[lib.scala 343:22] + wire rvclkhdr_7_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_8_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_8_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_8_io_en; // @[lib.scala 343:22] + wire rvclkhdr_8_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_9_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_9_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_9_io_en; // @[lib.scala 343:22] + wire rvclkhdr_9_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_10_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_10_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_10_io_en; // @[lib.scala 343:22] + wire rvclkhdr_10_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_11_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_11_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_11_io_en; // @[lib.scala 343:22] + wire rvclkhdr_11_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_12_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_12_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_12_io_en; // @[lib.scala 343:22] + wire rvclkhdr_12_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_13_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_13_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_13_io_en; // @[lib.scala 343:22] + wire rvclkhdr_13_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_14_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_14_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_14_io_en; // @[lib.scala 343:22] + wire rvclkhdr_14_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_15_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_15_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_15_io_en; // @[lib.scala 343:22] + wire rvclkhdr_15_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_16_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_16_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_16_io_en; // @[lib.scala 343:22] + wire rvclkhdr_16_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_17_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_17_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_17_io_en; // @[lib.scala 343:22] + wire rvclkhdr_17_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_18_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_18_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_18_io_en; // @[lib.scala 343:22] + wire rvclkhdr_18_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_19_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_19_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_19_io_en; // @[lib.scala 343:22] + wire rvclkhdr_19_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_20_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_20_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_20_io_en; // @[lib.scala 343:22] + wire rvclkhdr_20_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_21_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_21_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_21_io_en; // @[lib.scala 343:22] + wire rvclkhdr_21_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_22_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_22_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_22_io_en; // @[lib.scala 343:22] + wire rvclkhdr_22_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_23_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_23_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_23_io_en; // @[lib.scala 343:22] + wire rvclkhdr_23_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_24_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_24_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_24_io_en; // @[lib.scala 343:22] + wire rvclkhdr_24_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_25_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_25_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_25_io_en; // @[lib.scala 343:22] + wire rvclkhdr_25_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_26_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_26_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_26_io_en; // @[lib.scala 343:22] + wire rvclkhdr_26_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_27_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_27_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_27_io_en; // @[lib.scala 343:22] + wire rvclkhdr_27_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_28_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_28_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_28_io_en; // @[lib.scala 343:22] + wire rvclkhdr_28_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_29_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_29_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_29_io_en; // @[lib.scala 343:22] + wire rvclkhdr_29_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_30_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_30_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_30_io_en; // @[lib.scala 343:22] + wire rvclkhdr_30_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_31_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_31_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_31_io_en; // @[lib.scala 343:22] + wire rvclkhdr_31_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_32_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_32_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_32_io_en; // @[lib.scala 343:22] + wire rvclkhdr_32_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_33_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_33_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_33_io_en; // @[lib.scala 343:22] + wire rvclkhdr_33_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_34_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_34_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_34_io_en; // @[lib.scala 343:22] + wire rvclkhdr_34_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_35_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_35_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_35_io_en; // @[lib.scala 343:22] + wire rvclkhdr_35_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_36_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_36_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_36_io_en; // @[lib.scala 343:22] + wire rvclkhdr_36_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_37_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_37_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_37_io_en; // @[lib.scala 343:22] + wire rvclkhdr_37_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_38_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_38_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_38_io_en; // @[lib.scala 343:22] + wire rvclkhdr_38_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_39_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_39_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_39_io_en; // @[lib.scala 343:22] + wire rvclkhdr_39_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_40_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_40_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_40_io_en; // @[lib.scala 343:22] + wire rvclkhdr_40_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_41_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_41_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_41_io_en; // @[lib.scala 343:22] + wire rvclkhdr_41_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_42_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_42_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_42_io_en; // @[lib.scala 343:22] + wire rvclkhdr_42_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_43_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_43_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_43_io_en; // @[lib.scala 343:22] + wire rvclkhdr_43_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_44_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_44_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_44_io_en; // @[lib.scala 343:22] + wire rvclkhdr_44_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_45_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_45_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_45_io_en; // @[lib.scala 343:22] + wire rvclkhdr_45_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_46_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_46_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_46_io_en; // @[lib.scala 343:22] + wire rvclkhdr_46_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_47_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_47_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_47_io_en; // @[lib.scala 343:22] + wire rvclkhdr_47_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_48_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_48_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_48_io_en; // @[lib.scala 343:22] + wire rvclkhdr_48_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_49_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_49_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_49_io_en; // @[lib.scala 343:22] + wire rvclkhdr_49_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_50_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_50_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_50_io_en; // @[lib.scala 343:22] + wire rvclkhdr_50_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_51_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_51_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_51_io_en; // @[lib.scala 343:22] + wire rvclkhdr_51_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_52_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_52_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_52_io_en; // @[lib.scala 343:22] + wire rvclkhdr_52_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_53_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_53_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_53_io_en; // @[lib.scala 343:22] + wire rvclkhdr_53_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_54_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_54_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_54_io_en; // @[lib.scala 343:22] + wire rvclkhdr_54_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_55_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_55_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_55_io_en; // @[lib.scala 343:22] + wire rvclkhdr_55_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_56_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_56_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_56_io_en; // @[lib.scala 343:22] + wire rvclkhdr_56_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_57_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_57_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_57_io_en; // @[lib.scala 343:22] + wire rvclkhdr_57_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_58_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_58_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_58_io_en; // @[lib.scala 343:22] + wire rvclkhdr_58_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_59_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_59_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_59_io_en; // @[lib.scala 343:22] + wire rvclkhdr_59_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_60_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_60_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_60_io_en; // @[lib.scala 343:22] + wire rvclkhdr_60_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_61_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_61_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_61_io_en; // @[lib.scala 343:22] + wire rvclkhdr_61_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_62_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_62_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_62_io_en; // @[lib.scala 343:22] + wire rvclkhdr_62_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_63_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_63_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_63_io_en; // @[lib.scala 343:22] + wire rvclkhdr_63_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_64_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_64_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_64_io_en; // @[lib.scala 343:22] + wire rvclkhdr_64_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_65_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_65_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_65_io_en; // @[lib.scala 343:22] + wire rvclkhdr_65_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_66_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_66_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_66_io_en; // @[lib.scala 343:22] + wire rvclkhdr_66_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_67_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_67_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_67_io_en; // @[lib.scala 343:22] + wire rvclkhdr_67_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_68_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_68_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_68_io_en; // @[lib.scala 343:22] + wire rvclkhdr_68_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_69_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_69_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_69_io_en; // @[lib.scala 343:22] + wire rvclkhdr_69_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_70_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_70_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_70_io_en; // @[lib.scala 343:22] + wire rvclkhdr_70_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_71_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_71_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_71_io_en; // @[lib.scala 343:22] + wire rvclkhdr_71_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_72_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_72_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_72_io_en; // @[lib.scala 343:22] + wire rvclkhdr_72_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_73_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_73_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_73_io_en; // @[lib.scala 343:22] + wire rvclkhdr_73_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_74_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_74_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_74_io_en; // @[lib.scala 343:22] + wire rvclkhdr_74_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_75_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_75_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_75_io_en; // @[lib.scala 343:22] + wire rvclkhdr_75_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_76_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_76_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_76_io_en; // @[lib.scala 343:22] + wire rvclkhdr_76_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_77_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_77_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_77_io_en; // @[lib.scala 343:22] + wire rvclkhdr_77_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_78_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_78_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_78_io_en; // @[lib.scala 343:22] + wire rvclkhdr_78_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_79_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_79_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_79_io_en; // @[lib.scala 343:22] + wire rvclkhdr_79_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_80_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_80_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_80_io_en; // @[lib.scala 343:22] + wire rvclkhdr_80_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_81_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_81_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_81_io_en; // @[lib.scala 343:22] + wire rvclkhdr_81_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_82_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_82_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_82_io_en; // @[lib.scala 343:22] + wire rvclkhdr_82_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_83_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_83_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_83_io_en; // @[lib.scala 343:22] + wire rvclkhdr_83_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_84_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_84_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_84_io_en; // @[lib.scala 343:22] + wire rvclkhdr_84_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_85_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_85_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_85_io_en; // @[lib.scala 343:22] + wire rvclkhdr_85_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_86_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_86_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_86_io_en; // @[lib.scala 343:22] + wire rvclkhdr_86_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_87_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_87_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_87_io_en; // @[lib.scala 343:22] + wire rvclkhdr_87_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_88_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_88_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_88_io_en; // @[lib.scala 343:22] + wire rvclkhdr_88_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_89_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_89_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_89_io_en; // @[lib.scala 343:22] + wire rvclkhdr_89_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_90_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_90_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_90_io_en; // @[lib.scala 343:22] + wire rvclkhdr_90_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_91_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_91_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_91_io_en; // @[lib.scala 343:22] + wire rvclkhdr_91_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_92_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_92_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_92_io_en; // @[lib.scala 343:22] + wire rvclkhdr_92_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_93_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_93_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_93_io_en; // @[lib.scala 343:22] + wire rvclkhdr_93_io_scan_mode; // @[lib.scala 343:22] reg flush_final_f; // @[ifu_mem_ctl.scala 90:53] reg ifc_fetch_req_f_raw; // @[ifu_mem_ctl.scala 227:61] wire _T_319 = ~io_exu_flush_final; // @[ifu_mem_ctl.scala 228:44] @@ -1001,66 +1001,66 @@ module ifu_mem_ctl( wire _T_3125 = _T_3124 | iccm_dma_rvalid_in; // @[ifu_mem_ctl.scala 605:134] wire _T_3127 = _T_3125 & _T_3134; // @[ifu_mem_ctl.scala 605:156] wire [1:0] iccm_ecc_word_enable = {_T_3135,_T_3127}; // @[Cat.scala 29:58] - wire _T_3620 = ^io_iccm_rd_data_ecc[70:39]; // @[el2_lib.scala 333:30] - wire _T_3621 = ^io_iccm_rd_data_ecc[77:71]; // @[el2_lib.scala 333:44] - wire _T_3622 = _T_3620 ^ _T_3621; // @[el2_lib.scala 333:35] - wire [5:0] _T_3630 = {io_iccm_rd_data_ecc[70],io_iccm_rd_data_ecc[69],io_iccm_rd_data_ecc[68],io_iccm_rd_data_ecc[67],io_iccm_rd_data_ecc[66],io_iccm_rd_data_ecc[65]}; // @[el2_lib.scala 333:76] - wire _T_3631 = ^_T_3630; // @[el2_lib.scala 333:83] - wire _T_3632 = io_iccm_rd_data_ecc[76] ^ _T_3631; // @[el2_lib.scala 333:71] - wire [6:0] _T_3639 = {io_iccm_rd_data_ecc[56],io_iccm_rd_data_ecc[55],io_iccm_rd_data_ecc[54],io_iccm_rd_data_ecc[53],io_iccm_rd_data_ecc[52],io_iccm_rd_data_ecc[51],io_iccm_rd_data_ecc[50]}; // @[el2_lib.scala 333:103] - wire [14:0] _T_3647 = {io_iccm_rd_data_ecc[64],io_iccm_rd_data_ecc[63],io_iccm_rd_data_ecc[62],io_iccm_rd_data_ecc[61],io_iccm_rd_data_ecc[60],io_iccm_rd_data_ecc[59],io_iccm_rd_data_ecc[58],io_iccm_rd_data_ecc[57],_T_3639}; // @[el2_lib.scala 333:103] - wire _T_3648 = ^_T_3647; // @[el2_lib.scala 333:110] - wire _T_3649 = io_iccm_rd_data_ecc[75] ^ _T_3648; // @[el2_lib.scala 333:98] - wire [6:0] _T_3656 = {io_iccm_rd_data_ecc[49],io_iccm_rd_data_ecc[48],io_iccm_rd_data_ecc[47],io_iccm_rd_data_ecc[46],io_iccm_rd_data_ecc[45],io_iccm_rd_data_ecc[44],io_iccm_rd_data_ecc[43]}; // @[el2_lib.scala 333:130] - wire [14:0] _T_3664 = {io_iccm_rd_data_ecc[64],io_iccm_rd_data_ecc[63],io_iccm_rd_data_ecc[62],io_iccm_rd_data_ecc[61],io_iccm_rd_data_ecc[60],io_iccm_rd_data_ecc[59],io_iccm_rd_data_ecc[58],io_iccm_rd_data_ecc[57],_T_3656}; // @[el2_lib.scala 333:130] - wire _T_3665 = ^_T_3664; // @[el2_lib.scala 333:137] - wire _T_3666 = io_iccm_rd_data_ecc[74] ^ _T_3665; // @[el2_lib.scala 333:125] - wire [8:0] _T_3675 = {io_iccm_rd_data_ecc[54],io_iccm_rd_data_ecc[53],io_iccm_rd_data_ecc[49],io_iccm_rd_data_ecc[48],io_iccm_rd_data_ecc[47],io_iccm_rd_data_ecc[46],io_iccm_rd_data_ecc[42],io_iccm_rd_data_ecc[41],io_iccm_rd_data_ecc[40]}; // @[el2_lib.scala 333:157] - wire [17:0] _T_3684 = {io_iccm_rd_data_ecc[70],io_iccm_rd_data_ecc[69],io_iccm_rd_data_ecc[68],io_iccm_rd_data_ecc[64],io_iccm_rd_data_ecc[63],io_iccm_rd_data_ecc[62],io_iccm_rd_data_ecc[61],io_iccm_rd_data_ecc[56],io_iccm_rd_data_ecc[55],_T_3675}; // @[el2_lib.scala 333:157] - wire _T_3685 = ^_T_3684; // @[el2_lib.scala 333:164] - wire _T_3686 = io_iccm_rd_data_ecc[73] ^ _T_3685; // @[el2_lib.scala 333:152] - wire [8:0] _T_3695 = {io_iccm_rd_data_ecc[52],io_iccm_rd_data_ecc[51],io_iccm_rd_data_ecc[49],io_iccm_rd_data_ecc[48],io_iccm_rd_data_ecc[45],io_iccm_rd_data_ecc[44],io_iccm_rd_data_ecc[42],io_iccm_rd_data_ecc[41],io_iccm_rd_data_ecc[39]}; // @[el2_lib.scala 333:184] - wire [17:0] _T_3704 = {io_iccm_rd_data_ecc[70],io_iccm_rd_data_ecc[67],io_iccm_rd_data_ecc[66],io_iccm_rd_data_ecc[64],io_iccm_rd_data_ecc[63],io_iccm_rd_data_ecc[60],io_iccm_rd_data_ecc[59],io_iccm_rd_data_ecc[56],io_iccm_rd_data_ecc[55],_T_3695}; // @[el2_lib.scala 333:184] - wire _T_3705 = ^_T_3704; // @[el2_lib.scala 333:191] - wire _T_3706 = io_iccm_rd_data_ecc[72] ^ _T_3705; // @[el2_lib.scala 333:179] - wire [8:0] _T_3715 = {io_iccm_rd_data_ecc[52],io_iccm_rd_data_ecc[50],io_iccm_rd_data_ecc[49],io_iccm_rd_data_ecc[47],io_iccm_rd_data_ecc[45],io_iccm_rd_data_ecc[43],io_iccm_rd_data_ecc[42],io_iccm_rd_data_ecc[40],io_iccm_rd_data_ecc[39]}; // @[el2_lib.scala 333:211] - wire [17:0] _T_3724 = {io_iccm_rd_data_ecc[69],io_iccm_rd_data_ecc[67],io_iccm_rd_data_ecc[65],io_iccm_rd_data_ecc[64],io_iccm_rd_data_ecc[62],io_iccm_rd_data_ecc[60],io_iccm_rd_data_ecc[58],io_iccm_rd_data_ecc[56],io_iccm_rd_data_ecc[54],_T_3715}; // @[el2_lib.scala 333:211] - wire _T_3725 = ^_T_3724; // @[el2_lib.scala 333:218] - wire _T_3726 = io_iccm_rd_data_ecc[71] ^ _T_3725; // @[el2_lib.scala 333:206] + wire _T_3620 = ^io_iccm_rd_data_ecc[70:39]; // @[lib.scala 193:30] + wire _T_3621 = ^io_iccm_rd_data_ecc[77:71]; // @[lib.scala 193:44] + wire _T_3622 = _T_3620 ^ _T_3621; // @[lib.scala 193:35] + wire [5:0] _T_3630 = {io_iccm_rd_data_ecc[70],io_iccm_rd_data_ecc[69],io_iccm_rd_data_ecc[68],io_iccm_rd_data_ecc[67],io_iccm_rd_data_ecc[66],io_iccm_rd_data_ecc[65]}; // @[lib.scala 193:76] + wire _T_3631 = ^_T_3630; // @[lib.scala 193:83] + wire _T_3632 = io_iccm_rd_data_ecc[76] ^ _T_3631; // @[lib.scala 193:71] + wire [6:0] _T_3639 = {io_iccm_rd_data_ecc[56],io_iccm_rd_data_ecc[55],io_iccm_rd_data_ecc[54],io_iccm_rd_data_ecc[53],io_iccm_rd_data_ecc[52],io_iccm_rd_data_ecc[51],io_iccm_rd_data_ecc[50]}; // @[lib.scala 193:103] + wire [14:0] _T_3647 = {io_iccm_rd_data_ecc[64],io_iccm_rd_data_ecc[63],io_iccm_rd_data_ecc[62],io_iccm_rd_data_ecc[61],io_iccm_rd_data_ecc[60],io_iccm_rd_data_ecc[59],io_iccm_rd_data_ecc[58],io_iccm_rd_data_ecc[57],_T_3639}; // @[lib.scala 193:103] + wire _T_3648 = ^_T_3647; // @[lib.scala 193:110] + wire _T_3649 = io_iccm_rd_data_ecc[75] ^ _T_3648; // @[lib.scala 193:98] + wire [6:0] _T_3656 = {io_iccm_rd_data_ecc[49],io_iccm_rd_data_ecc[48],io_iccm_rd_data_ecc[47],io_iccm_rd_data_ecc[46],io_iccm_rd_data_ecc[45],io_iccm_rd_data_ecc[44],io_iccm_rd_data_ecc[43]}; // @[lib.scala 193:130] + wire [14:0] _T_3664 = {io_iccm_rd_data_ecc[64],io_iccm_rd_data_ecc[63],io_iccm_rd_data_ecc[62],io_iccm_rd_data_ecc[61],io_iccm_rd_data_ecc[60],io_iccm_rd_data_ecc[59],io_iccm_rd_data_ecc[58],io_iccm_rd_data_ecc[57],_T_3656}; // @[lib.scala 193:130] + wire _T_3665 = ^_T_3664; // @[lib.scala 193:137] + wire _T_3666 = io_iccm_rd_data_ecc[74] ^ _T_3665; // @[lib.scala 193:125] + wire [8:0] _T_3675 = {io_iccm_rd_data_ecc[54],io_iccm_rd_data_ecc[53],io_iccm_rd_data_ecc[49],io_iccm_rd_data_ecc[48],io_iccm_rd_data_ecc[47],io_iccm_rd_data_ecc[46],io_iccm_rd_data_ecc[42],io_iccm_rd_data_ecc[41],io_iccm_rd_data_ecc[40]}; // @[lib.scala 193:157] + wire [17:0] _T_3684 = {io_iccm_rd_data_ecc[70],io_iccm_rd_data_ecc[69],io_iccm_rd_data_ecc[68],io_iccm_rd_data_ecc[64],io_iccm_rd_data_ecc[63],io_iccm_rd_data_ecc[62],io_iccm_rd_data_ecc[61],io_iccm_rd_data_ecc[56],io_iccm_rd_data_ecc[55],_T_3675}; // @[lib.scala 193:157] + wire _T_3685 = ^_T_3684; // @[lib.scala 193:164] + wire _T_3686 = io_iccm_rd_data_ecc[73] ^ _T_3685; // @[lib.scala 193:152] + wire [8:0] _T_3695 = {io_iccm_rd_data_ecc[52],io_iccm_rd_data_ecc[51],io_iccm_rd_data_ecc[49],io_iccm_rd_data_ecc[48],io_iccm_rd_data_ecc[45],io_iccm_rd_data_ecc[44],io_iccm_rd_data_ecc[42],io_iccm_rd_data_ecc[41],io_iccm_rd_data_ecc[39]}; // @[lib.scala 193:184] + wire [17:0] _T_3704 = {io_iccm_rd_data_ecc[70],io_iccm_rd_data_ecc[67],io_iccm_rd_data_ecc[66],io_iccm_rd_data_ecc[64],io_iccm_rd_data_ecc[63],io_iccm_rd_data_ecc[60],io_iccm_rd_data_ecc[59],io_iccm_rd_data_ecc[56],io_iccm_rd_data_ecc[55],_T_3695}; // @[lib.scala 193:184] + wire _T_3705 = ^_T_3704; // @[lib.scala 193:191] + wire _T_3706 = io_iccm_rd_data_ecc[72] ^ _T_3705; // @[lib.scala 193:179] + wire [8:0] _T_3715 = {io_iccm_rd_data_ecc[52],io_iccm_rd_data_ecc[50],io_iccm_rd_data_ecc[49],io_iccm_rd_data_ecc[47],io_iccm_rd_data_ecc[45],io_iccm_rd_data_ecc[43],io_iccm_rd_data_ecc[42],io_iccm_rd_data_ecc[40],io_iccm_rd_data_ecc[39]}; // @[lib.scala 193:211] + wire [17:0] _T_3724 = {io_iccm_rd_data_ecc[69],io_iccm_rd_data_ecc[67],io_iccm_rd_data_ecc[65],io_iccm_rd_data_ecc[64],io_iccm_rd_data_ecc[62],io_iccm_rd_data_ecc[60],io_iccm_rd_data_ecc[58],io_iccm_rd_data_ecc[56],io_iccm_rd_data_ecc[54],_T_3715}; // @[lib.scala 193:211] + wire _T_3725 = ^_T_3724; // @[lib.scala 193:218] + wire _T_3726 = io_iccm_rd_data_ecc[71] ^ _T_3725; // @[lib.scala 193:206] wire [6:0] _T_3732 = {_T_3622,_T_3632,_T_3649,_T_3666,_T_3686,_T_3706,_T_3726}; // @[Cat.scala 29:58] - wire _T_3733 = _T_3732 != 7'h0; // @[el2_lib.scala 334:44] - wire _T_3734 = iccm_ecc_word_enable[1] & _T_3733; // @[el2_lib.scala 334:32] - wire _T_3736 = _T_3734 & _T_3732[6]; // @[el2_lib.scala 334:53] - wire _T_3235 = ^io_iccm_rd_data_ecc[31:0]; // @[el2_lib.scala 333:30] - wire _T_3236 = ^io_iccm_rd_data_ecc[38:32]; // @[el2_lib.scala 333:44] - wire _T_3237 = _T_3235 ^ _T_3236; // @[el2_lib.scala 333:35] - wire [5:0] _T_3245 = {io_iccm_rd_data_ecc[31],io_iccm_rd_data_ecc[30],io_iccm_rd_data_ecc[29],io_iccm_rd_data_ecc[28],io_iccm_rd_data_ecc[27],io_iccm_rd_data_ecc[26]}; // @[el2_lib.scala 333:76] - wire _T_3246 = ^_T_3245; // @[el2_lib.scala 333:83] - wire _T_3247 = io_iccm_rd_data_ecc[37] ^ _T_3246; // @[el2_lib.scala 333:71] - wire [6:0] _T_3254 = {io_iccm_rd_data_ecc[17],io_iccm_rd_data_ecc[16],io_iccm_rd_data_ecc[15],io_iccm_rd_data_ecc[14],io_iccm_rd_data_ecc[13],io_iccm_rd_data_ecc[12],io_iccm_rd_data_ecc[11]}; // @[el2_lib.scala 333:103] - wire [14:0] _T_3262 = {io_iccm_rd_data_ecc[25],io_iccm_rd_data_ecc[24],io_iccm_rd_data_ecc[23],io_iccm_rd_data_ecc[22],io_iccm_rd_data_ecc[21],io_iccm_rd_data_ecc[20],io_iccm_rd_data_ecc[19],io_iccm_rd_data_ecc[18],_T_3254}; // @[el2_lib.scala 333:103] - wire _T_3263 = ^_T_3262; // @[el2_lib.scala 333:110] - wire _T_3264 = io_iccm_rd_data_ecc[36] ^ _T_3263; // @[el2_lib.scala 333:98] - wire [6:0] _T_3271 = {io_iccm_rd_data_ecc[10],io_iccm_rd_data_ecc[9],io_iccm_rd_data_ecc[8],io_iccm_rd_data_ecc[7],io_iccm_rd_data_ecc[6],io_iccm_rd_data_ecc[5],io_iccm_rd_data_ecc[4]}; // @[el2_lib.scala 333:130] - wire [14:0] _T_3279 = {io_iccm_rd_data_ecc[25],io_iccm_rd_data_ecc[24],io_iccm_rd_data_ecc[23],io_iccm_rd_data_ecc[22],io_iccm_rd_data_ecc[21],io_iccm_rd_data_ecc[20],io_iccm_rd_data_ecc[19],io_iccm_rd_data_ecc[18],_T_3271}; // @[el2_lib.scala 333:130] - wire _T_3280 = ^_T_3279; // @[el2_lib.scala 333:137] - wire _T_3281 = io_iccm_rd_data_ecc[35] ^ _T_3280; // @[el2_lib.scala 333:125] - wire [8:0] _T_3290 = {io_iccm_rd_data_ecc[15],io_iccm_rd_data_ecc[14],io_iccm_rd_data_ecc[10],io_iccm_rd_data_ecc[9],io_iccm_rd_data_ecc[8],io_iccm_rd_data_ecc[7],io_iccm_rd_data_ecc[3],io_iccm_rd_data_ecc[2],io_iccm_rd_data_ecc[1]}; // @[el2_lib.scala 333:157] - wire [17:0] _T_3299 = {io_iccm_rd_data_ecc[31],io_iccm_rd_data_ecc[30],io_iccm_rd_data_ecc[29],io_iccm_rd_data_ecc[25],io_iccm_rd_data_ecc[24],io_iccm_rd_data_ecc[23],io_iccm_rd_data_ecc[22],io_iccm_rd_data_ecc[17],io_iccm_rd_data_ecc[16],_T_3290}; // @[el2_lib.scala 333:157] - wire _T_3300 = ^_T_3299; // @[el2_lib.scala 333:164] - wire _T_3301 = io_iccm_rd_data_ecc[34] ^ _T_3300; // @[el2_lib.scala 333:152] - wire [8:0] _T_3310 = {io_iccm_rd_data_ecc[13],io_iccm_rd_data_ecc[12],io_iccm_rd_data_ecc[10],io_iccm_rd_data_ecc[9],io_iccm_rd_data_ecc[6],io_iccm_rd_data_ecc[5],io_iccm_rd_data_ecc[3],io_iccm_rd_data_ecc[2],io_iccm_rd_data_ecc[0]}; // @[el2_lib.scala 333:184] - wire [17:0] _T_3319 = {io_iccm_rd_data_ecc[31],io_iccm_rd_data_ecc[28],io_iccm_rd_data_ecc[27],io_iccm_rd_data_ecc[25],io_iccm_rd_data_ecc[24],io_iccm_rd_data_ecc[21],io_iccm_rd_data_ecc[20],io_iccm_rd_data_ecc[17],io_iccm_rd_data_ecc[16],_T_3310}; // @[el2_lib.scala 333:184] - wire _T_3320 = ^_T_3319; // @[el2_lib.scala 333:191] - wire _T_3321 = io_iccm_rd_data_ecc[33] ^ _T_3320; // @[el2_lib.scala 333:179] - wire [8:0] _T_3330 = {io_iccm_rd_data_ecc[13],io_iccm_rd_data_ecc[11],io_iccm_rd_data_ecc[10],io_iccm_rd_data_ecc[8],io_iccm_rd_data_ecc[6],io_iccm_rd_data_ecc[4],io_iccm_rd_data_ecc[3],io_iccm_rd_data_ecc[1],io_iccm_rd_data_ecc[0]}; // @[el2_lib.scala 333:211] - wire [17:0] _T_3339 = {io_iccm_rd_data_ecc[30],io_iccm_rd_data_ecc[28],io_iccm_rd_data_ecc[26],io_iccm_rd_data_ecc[25],io_iccm_rd_data_ecc[23],io_iccm_rd_data_ecc[21],io_iccm_rd_data_ecc[19],io_iccm_rd_data_ecc[17],io_iccm_rd_data_ecc[15],_T_3330}; // @[el2_lib.scala 333:211] - wire _T_3340 = ^_T_3339; // @[el2_lib.scala 333:218] - wire _T_3341 = io_iccm_rd_data_ecc[32] ^ _T_3340; // @[el2_lib.scala 333:206] + wire _T_3733 = _T_3732 != 7'h0; // @[lib.scala 194:44] + wire _T_3734 = iccm_ecc_word_enable[1] & _T_3733; // @[lib.scala 194:32] + wire _T_3736 = _T_3734 & _T_3732[6]; // @[lib.scala 194:53] + wire _T_3235 = ^io_iccm_rd_data_ecc[31:0]; // @[lib.scala 193:30] + wire _T_3236 = ^io_iccm_rd_data_ecc[38:32]; // @[lib.scala 193:44] + wire _T_3237 = _T_3235 ^ _T_3236; // @[lib.scala 193:35] + wire [5:0] _T_3245 = {io_iccm_rd_data_ecc[31],io_iccm_rd_data_ecc[30],io_iccm_rd_data_ecc[29],io_iccm_rd_data_ecc[28],io_iccm_rd_data_ecc[27],io_iccm_rd_data_ecc[26]}; // @[lib.scala 193:76] + wire _T_3246 = ^_T_3245; // @[lib.scala 193:83] + wire _T_3247 = io_iccm_rd_data_ecc[37] ^ _T_3246; // @[lib.scala 193:71] + wire [6:0] _T_3254 = {io_iccm_rd_data_ecc[17],io_iccm_rd_data_ecc[16],io_iccm_rd_data_ecc[15],io_iccm_rd_data_ecc[14],io_iccm_rd_data_ecc[13],io_iccm_rd_data_ecc[12],io_iccm_rd_data_ecc[11]}; // @[lib.scala 193:103] + wire [14:0] _T_3262 = {io_iccm_rd_data_ecc[25],io_iccm_rd_data_ecc[24],io_iccm_rd_data_ecc[23],io_iccm_rd_data_ecc[22],io_iccm_rd_data_ecc[21],io_iccm_rd_data_ecc[20],io_iccm_rd_data_ecc[19],io_iccm_rd_data_ecc[18],_T_3254}; // @[lib.scala 193:103] + wire _T_3263 = ^_T_3262; // @[lib.scala 193:110] + wire _T_3264 = io_iccm_rd_data_ecc[36] ^ _T_3263; // @[lib.scala 193:98] + wire [6:0] _T_3271 = {io_iccm_rd_data_ecc[10],io_iccm_rd_data_ecc[9],io_iccm_rd_data_ecc[8],io_iccm_rd_data_ecc[7],io_iccm_rd_data_ecc[6],io_iccm_rd_data_ecc[5],io_iccm_rd_data_ecc[4]}; // @[lib.scala 193:130] + wire [14:0] _T_3279 = {io_iccm_rd_data_ecc[25],io_iccm_rd_data_ecc[24],io_iccm_rd_data_ecc[23],io_iccm_rd_data_ecc[22],io_iccm_rd_data_ecc[21],io_iccm_rd_data_ecc[20],io_iccm_rd_data_ecc[19],io_iccm_rd_data_ecc[18],_T_3271}; // @[lib.scala 193:130] + wire _T_3280 = ^_T_3279; // @[lib.scala 193:137] + wire _T_3281 = io_iccm_rd_data_ecc[35] ^ _T_3280; // @[lib.scala 193:125] + wire [8:0] _T_3290 = {io_iccm_rd_data_ecc[15],io_iccm_rd_data_ecc[14],io_iccm_rd_data_ecc[10],io_iccm_rd_data_ecc[9],io_iccm_rd_data_ecc[8],io_iccm_rd_data_ecc[7],io_iccm_rd_data_ecc[3],io_iccm_rd_data_ecc[2],io_iccm_rd_data_ecc[1]}; // @[lib.scala 193:157] + wire [17:0] _T_3299 = {io_iccm_rd_data_ecc[31],io_iccm_rd_data_ecc[30],io_iccm_rd_data_ecc[29],io_iccm_rd_data_ecc[25],io_iccm_rd_data_ecc[24],io_iccm_rd_data_ecc[23],io_iccm_rd_data_ecc[22],io_iccm_rd_data_ecc[17],io_iccm_rd_data_ecc[16],_T_3290}; // @[lib.scala 193:157] + wire _T_3300 = ^_T_3299; // @[lib.scala 193:164] + wire _T_3301 = io_iccm_rd_data_ecc[34] ^ _T_3300; // @[lib.scala 193:152] + wire [8:0] _T_3310 = {io_iccm_rd_data_ecc[13],io_iccm_rd_data_ecc[12],io_iccm_rd_data_ecc[10],io_iccm_rd_data_ecc[9],io_iccm_rd_data_ecc[6],io_iccm_rd_data_ecc[5],io_iccm_rd_data_ecc[3],io_iccm_rd_data_ecc[2],io_iccm_rd_data_ecc[0]}; // @[lib.scala 193:184] + wire [17:0] _T_3319 = {io_iccm_rd_data_ecc[31],io_iccm_rd_data_ecc[28],io_iccm_rd_data_ecc[27],io_iccm_rd_data_ecc[25],io_iccm_rd_data_ecc[24],io_iccm_rd_data_ecc[21],io_iccm_rd_data_ecc[20],io_iccm_rd_data_ecc[17],io_iccm_rd_data_ecc[16],_T_3310}; // @[lib.scala 193:184] + wire _T_3320 = ^_T_3319; // @[lib.scala 193:191] + wire _T_3321 = io_iccm_rd_data_ecc[33] ^ _T_3320; // @[lib.scala 193:179] + wire [8:0] _T_3330 = {io_iccm_rd_data_ecc[13],io_iccm_rd_data_ecc[11],io_iccm_rd_data_ecc[10],io_iccm_rd_data_ecc[8],io_iccm_rd_data_ecc[6],io_iccm_rd_data_ecc[4],io_iccm_rd_data_ecc[3],io_iccm_rd_data_ecc[1],io_iccm_rd_data_ecc[0]}; // @[lib.scala 193:211] + wire [17:0] _T_3339 = {io_iccm_rd_data_ecc[30],io_iccm_rd_data_ecc[28],io_iccm_rd_data_ecc[26],io_iccm_rd_data_ecc[25],io_iccm_rd_data_ecc[23],io_iccm_rd_data_ecc[21],io_iccm_rd_data_ecc[19],io_iccm_rd_data_ecc[17],io_iccm_rd_data_ecc[15],_T_3330}; // @[lib.scala 193:211] + wire _T_3340 = ^_T_3339; // @[lib.scala 193:218] + wire _T_3341 = io_iccm_rd_data_ecc[32] ^ _T_3340; // @[lib.scala 193:206] wire [6:0] _T_3347 = {_T_3237,_T_3247,_T_3264,_T_3281,_T_3301,_T_3321,_T_3341}; // @[Cat.scala 29:58] - wire _T_3348 = _T_3347 != 7'h0; // @[el2_lib.scala 334:44] - wire _T_3349 = iccm_ecc_word_enable[0] & _T_3348; // @[el2_lib.scala 334:32] - wire _T_3351 = _T_3349 & _T_3347[6]; // @[el2_lib.scala 334:53] + wire _T_3348 = _T_3347 != 7'h0; // @[lib.scala 194:44] + wire _T_3349 = iccm_ecc_word_enable[0] & _T_3348; // @[lib.scala 194:32] + wire _T_3351 = _T_3349 & _T_3347[6]; // @[lib.scala 194:53] wire [1:0] iccm_single_ecc_error = {_T_3736,_T_3351}; // @[Cat.scala 29:58] wire _T_3 = |iccm_single_ecc_error; // @[ifu_mem_ctl.scala 95:52] reg dma_iccm_req_f; // @[ifu_mem_ctl.scala 568:51] @@ -1977,40 +1977,40 @@ module ifu_mem_ctl( wire sel_mb_status_addr = _T_347 | reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 242:119] wire [30:0] ifu_status_wr_addr = sel_mb_status_addr ? _T_338 : ifu_fetch_addr_int_f; // @[ifu_mem_ctl.scala 243:31] reg [63:0] ifu_bus_rdata_ff; // @[ifu_mem_ctl.scala 513:48] - wire [6:0] _T_570 = {ifu_bus_rdata_ff[63],ifu_bus_rdata_ff[62],ifu_bus_rdata_ff[61],ifu_bus_rdata_ff[60],ifu_bus_rdata_ff[59],ifu_bus_rdata_ff[58],ifu_bus_rdata_ff[57]}; // @[el2_lib.scala 416:13] - wire _T_571 = ^_T_570; // @[el2_lib.scala 416:20] - wire [6:0] _T_577 = {ifu_bus_rdata_ff[32],ifu_bus_rdata_ff[31],ifu_bus_rdata_ff[30],ifu_bus_rdata_ff[29],ifu_bus_rdata_ff[28],ifu_bus_rdata_ff[27],ifu_bus_rdata_ff[26]}; // @[el2_lib.scala 416:30] - wire [7:0] _T_584 = {ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[39],ifu_bus_rdata_ff[38],ifu_bus_rdata_ff[37],ifu_bus_rdata_ff[36],ifu_bus_rdata_ff[35],ifu_bus_rdata_ff[34],ifu_bus_rdata_ff[33]}; // @[el2_lib.scala 416:30] - wire [14:0] _T_585 = {ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[39],ifu_bus_rdata_ff[38],ifu_bus_rdata_ff[37],ifu_bus_rdata_ff[36],ifu_bus_rdata_ff[35],ifu_bus_rdata_ff[34],ifu_bus_rdata_ff[33],_T_577}; // @[el2_lib.scala 416:30] - wire [7:0] _T_592 = {ifu_bus_rdata_ff[48],ifu_bus_rdata_ff[47],ifu_bus_rdata_ff[46],ifu_bus_rdata_ff[45],ifu_bus_rdata_ff[44],ifu_bus_rdata_ff[43],ifu_bus_rdata_ff[42],ifu_bus_rdata_ff[41]}; // @[el2_lib.scala 416:30] - wire [30:0] _T_601 = {ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[53],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[51],ifu_bus_rdata_ff[50],ifu_bus_rdata_ff[49],_T_592,_T_585}; // @[el2_lib.scala 416:30] - wire _T_602 = ^_T_601; // @[el2_lib.scala 416:37] - wire [6:0] _T_608 = {ifu_bus_rdata_ff[17],ifu_bus_rdata_ff[16],ifu_bus_rdata_ff[15],ifu_bus_rdata_ff[14],ifu_bus_rdata_ff[13],ifu_bus_rdata_ff[12],ifu_bus_rdata_ff[11]}; // @[el2_lib.scala 416:47] - wire [14:0] _T_616 = {ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[24],ifu_bus_rdata_ff[23],ifu_bus_rdata_ff[22],ifu_bus_rdata_ff[21],ifu_bus_rdata_ff[20],ifu_bus_rdata_ff[19],ifu_bus_rdata_ff[18],_T_608}; // @[el2_lib.scala 416:47] - wire [30:0] _T_632 = {ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[53],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[51],ifu_bus_rdata_ff[50],ifu_bus_rdata_ff[49],_T_592,_T_616}; // @[el2_lib.scala 416:47] - wire _T_633 = ^_T_632; // @[el2_lib.scala 416:54] - wire [6:0] _T_639 = {ifu_bus_rdata_ff[10],ifu_bus_rdata_ff[9],ifu_bus_rdata_ff[8],ifu_bus_rdata_ff[7],ifu_bus_rdata_ff[6],ifu_bus_rdata_ff[5],ifu_bus_rdata_ff[4]}; // @[el2_lib.scala 416:64] - wire [14:0] _T_647 = {ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[24],ifu_bus_rdata_ff[23],ifu_bus_rdata_ff[22],ifu_bus_rdata_ff[21],ifu_bus_rdata_ff[20],ifu_bus_rdata_ff[19],ifu_bus_rdata_ff[18],_T_639}; // @[el2_lib.scala 416:64] - wire [30:0] _T_663 = {ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[53],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[51],ifu_bus_rdata_ff[50],ifu_bus_rdata_ff[49],_T_584,_T_647}; // @[el2_lib.scala 416:64] - wire _T_664 = ^_T_663; // @[el2_lib.scala 416:71] - wire [7:0] _T_671 = {ifu_bus_rdata_ff[14],ifu_bus_rdata_ff[10],ifu_bus_rdata_ff[9],ifu_bus_rdata_ff[8],ifu_bus_rdata_ff[7],ifu_bus_rdata_ff[3],ifu_bus_rdata_ff[2],ifu_bus_rdata_ff[1]}; // @[el2_lib.scala 416:81] - wire [16:0] _T_680 = {ifu_bus_rdata_ff[30],ifu_bus_rdata_ff[29],ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[24],ifu_bus_rdata_ff[23],ifu_bus_rdata_ff[22],ifu_bus_rdata_ff[17],ifu_bus_rdata_ff[16],ifu_bus_rdata_ff[15],_T_671}; // @[el2_lib.scala 416:81] - wire [8:0] _T_688 = {ifu_bus_rdata_ff[47],ifu_bus_rdata_ff[46],ifu_bus_rdata_ff[45],ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[39],ifu_bus_rdata_ff[38],ifu_bus_rdata_ff[37],ifu_bus_rdata_ff[32],ifu_bus_rdata_ff[31]}; // @[el2_lib.scala 416:81] - wire [17:0] _T_697 = {ifu_bus_rdata_ff[63],ifu_bus_rdata_ff[62],ifu_bus_rdata_ff[61],ifu_bus_rdata_ff[60],ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[53],ifu_bus_rdata_ff[48],_T_688}; // @[el2_lib.scala 416:81] - wire [34:0] _T_698 = {_T_697,_T_680}; // @[el2_lib.scala 416:81] - wire _T_699 = ^_T_698; // @[el2_lib.scala 416:88] - wire [7:0] _T_706 = {ifu_bus_rdata_ff[12],ifu_bus_rdata_ff[10],ifu_bus_rdata_ff[9],ifu_bus_rdata_ff[6],ifu_bus_rdata_ff[5],ifu_bus_rdata_ff[3],ifu_bus_rdata_ff[2],ifu_bus_rdata_ff[0]}; // @[el2_lib.scala 416:98] - wire [16:0] _T_715 = {ifu_bus_rdata_ff[28],ifu_bus_rdata_ff[27],ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[24],ifu_bus_rdata_ff[21],ifu_bus_rdata_ff[20],ifu_bus_rdata_ff[17],ifu_bus_rdata_ff[16],ifu_bus_rdata_ff[13],_T_706}; // @[el2_lib.scala 416:98] - wire [8:0] _T_723 = {ifu_bus_rdata_ff[47],ifu_bus_rdata_ff[44],ifu_bus_rdata_ff[43],ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[39],ifu_bus_rdata_ff[36],ifu_bus_rdata_ff[35],ifu_bus_rdata_ff[32],ifu_bus_rdata_ff[31]}; // @[el2_lib.scala 416:98] - wire [17:0] _T_732 = {ifu_bus_rdata_ff[63],ifu_bus_rdata_ff[62],ifu_bus_rdata_ff[59],ifu_bus_rdata_ff[58],ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[51],ifu_bus_rdata_ff[48],_T_723}; // @[el2_lib.scala 416:98] - wire [34:0] _T_733 = {_T_732,_T_715}; // @[el2_lib.scala 416:98] - wire _T_734 = ^_T_733; // @[el2_lib.scala 416:105] - wire [7:0] _T_741 = {ifu_bus_rdata_ff[11],ifu_bus_rdata_ff[10],ifu_bus_rdata_ff[8],ifu_bus_rdata_ff[6],ifu_bus_rdata_ff[4],ifu_bus_rdata_ff[3],ifu_bus_rdata_ff[1],ifu_bus_rdata_ff[0]}; // @[el2_lib.scala 416:115] - wire [16:0] _T_750 = {ifu_bus_rdata_ff[28],ifu_bus_rdata_ff[26],ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[23],ifu_bus_rdata_ff[21],ifu_bus_rdata_ff[19],ifu_bus_rdata_ff[17],ifu_bus_rdata_ff[15],ifu_bus_rdata_ff[13],_T_741}; // @[el2_lib.scala 416:115] - wire [8:0] _T_758 = {ifu_bus_rdata_ff[46],ifu_bus_rdata_ff[44],ifu_bus_rdata_ff[42],ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[38],ifu_bus_rdata_ff[36],ifu_bus_rdata_ff[34],ifu_bus_rdata_ff[32],ifu_bus_rdata_ff[30]}; // @[el2_lib.scala 416:115] - wire [17:0] _T_767 = {ifu_bus_rdata_ff[63],ifu_bus_rdata_ff[61],ifu_bus_rdata_ff[59],ifu_bus_rdata_ff[57],ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[50],ifu_bus_rdata_ff[48],_T_758}; // @[el2_lib.scala 416:115] - wire [34:0] _T_768 = {_T_767,_T_750}; // @[el2_lib.scala 416:115] - wire _T_769 = ^_T_768; // @[el2_lib.scala 416:122] + wire [6:0] _T_570 = {ifu_bus_rdata_ff[63],ifu_bus_rdata_ff[62],ifu_bus_rdata_ff[61],ifu_bus_rdata_ff[60],ifu_bus_rdata_ff[59],ifu_bus_rdata_ff[58],ifu_bus_rdata_ff[57]}; // @[lib.scala 276:13] + wire _T_571 = ^_T_570; // @[lib.scala 276:20] + wire [6:0] _T_577 = {ifu_bus_rdata_ff[32],ifu_bus_rdata_ff[31],ifu_bus_rdata_ff[30],ifu_bus_rdata_ff[29],ifu_bus_rdata_ff[28],ifu_bus_rdata_ff[27],ifu_bus_rdata_ff[26]}; // @[lib.scala 276:30] + wire [7:0] _T_584 = {ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[39],ifu_bus_rdata_ff[38],ifu_bus_rdata_ff[37],ifu_bus_rdata_ff[36],ifu_bus_rdata_ff[35],ifu_bus_rdata_ff[34],ifu_bus_rdata_ff[33]}; // @[lib.scala 276:30] + wire [14:0] _T_585 = {ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[39],ifu_bus_rdata_ff[38],ifu_bus_rdata_ff[37],ifu_bus_rdata_ff[36],ifu_bus_rdata_ff[35],ifu_bus_rdata_ff[34],ifu_bus_rdata_ff[33],_T_577}; // @[lib.scala 276:30] + wire [7:0] _T_592 = {ifu_bus_rdata_ff[48],ifu_bus_rdata_ff[47],ifu_bus_rdata_ff[46],ifu_bus_rdata_ff[45],ifu_bus_rdata_ff[44],ifu_bus_rdata_ff[43],ifu_bus_rdata_ff[42],ifu_bus_rdata_ff[41]}; // @[lib.scala 276:30] + wire [30:0] _T_601 = {ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[53],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[51],ifu_bus_rdata_ff[50],ifu_bus_rdata_ff[49],_T_592,_T_585}; // @[lib.scala 276:30] + wire _T_602 = ^_T_601; // @[lib.scala 276:37] + wire [6:0] _T_608 = {ifu_bus_rdata_ff[17],ifu_bus_rdata_ff[16],ifu_bus_rdata_ff[15],ifu_bus_rdata_ff[14],ifu_bus_rdata_ff[13],ifu_bus_rdata_ff[12],ifu_bus_rdata_ff[11]}; // @[lib.scala 276:47] + wire [14:0] _T_616 = {ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[24],ifu_bus_rdata_ff[23],ifu_bus_rdata_ff[22],ifu_bus_rdata_ff[21],ifu_bus_rdata_ff[20],ifu_bus_rdata_ff[19],ifu_bus_rdata_ff[18],_T_608}; // @[lib.scala 276:47] + wire [30:0] _T_632 = {ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[53],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[51],ifu_bus_rdata_ff[50],ifu_bus_rdata_ff[49],_T_592,_T_616}; // @[lib.scala 276:47] + wire _T_633 = ^_T_632; // @[lib.scala 276:54] + wire [6:0] _T_639 = {ifu_bus_rdata_ff[10],ifu_bus_rdata_ff[9],ifu_bus_rdata_ff[8],ifu_bus_rdata_ff[7],ifu_bus_rdata_ff[6],ifu_bus_rdata_ff[5],ifu_bus_rdata_ff[4]}; // @[lib.scala 276:64] + wire [14:0] _T_647 = {ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[24],ifu_bus_rdata_ff[23],ifu_bus_rdata_ff[22],ifu_bus_rdata_ff[21],ifu_bus_rdata_ff[20],ifu_bus_rdata_ff[19],ifu_bus_rdata_ff[18],_T_639}; // @[lib.scala 276:64] + wire [30:0] _T_663 = {ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[53],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[51],ifu_bus_rdata_ff[50],ifu_bus_rdata_ff[49],_T_584,_T_647}; // @[lib.scala 276:64] + wire _T_664 = ^_T_663; // @[lib.scala 276:71] + wire [7:0] _T_671 = {ifu_bus_rdata_ff[14],ifu_bus_rdata_ff[10],ifu_bus_rdata_ff[9],ifu_bus_rdata_ff[8],ifu_bus_rdata_ff[7],ifu_bus_rdata_ff[3],ifu_bus_rdata_ff[2],ifu_bus_rdata_ff[1]}; // @[lib.scala 276:81] + wire [16:0] _T_680 = {ifu_bus_rdata_ff[30],ifu_bus_rdata_ff[29],ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[24],ifu_bus_rdata_ff[23],ifu_bus_rdata_ff[22],ifu_bus_rdata_ff[17],ifu_bus_rdata_ff[16],ifu_bus_rdata_ff[15],_T_671}; // @[lib.scala 276:81] + wire [8:0] _T_688 = {ifu_bus_rdata_ff[47],ifu_bus_rdata_ff[46],ifu_bus_rdata_ff[45],ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[39],ifu_bus_rdata_ff[38],ifu_bus_rdata_ff[37],ifu_bus_rdata_ff[32],ifu_bus_rdata_ff[31]}; // @[lib.scala 276:81] + wire [17:0] _T_697 = {ifu_bus_rdata_ff[63],ifu_bus_rdata_ff[62],ifu_bus_rdata_ff[61],ifu_bus_rdata_ff[60],ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[53],ifu_bus_rdata_ff[48],_T_688}; // @[lib.scala 276:81] + wire [34:0] _T_698 = {_T_697,_T_680}; // @[lib.scala 276:81] + wire _T_699 = ^_T_698; // @[lib.scala 276:88] + wire [7:0] _T_706 = {ifu_bus_rdata_ff[12],ifu_bus_rdata_ff[10],ifu_bus_rdata_ff[9],ifu_bus_rdata_ff[6],ifu_bus_rdata_ff[5],ifu_bus_rdata_ff[3],ifu_bus_rdata_ff[2],ifu_bus_rdata_ff[0]}; // @[lib.scala 276:98] + wire [16:0] _T_715 = {ifu_bus_rdata_ff[28],ifu_bus_rdata_ff[27],ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[24],ifu_bus_rdata_ff[21],ifu_bus_rdata_ff[20],ifu_bus_rdata_ff[17],ifu_bus_rdata_ff[16],ifu_bus_rdata_ff[13],_T_706}; // @[lib.scala 276:98] + wire [8:0] _T_723 = {ifu_bus_rdata_ff[47],ifu_bus_rdata_ff[44],ifu_bus_rdata_ff[43],ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[39],ifu_bus_rdata_ff[36],ifu_bus_rdata_ff[35],ifu_bus_rdata_ff[32],ifu_bus_rdata_ff[31]}; // @[lib.scala 276:98] + wire [17:0] _T_732 = {ifu_bus_rdata_ff[63],ifu_bus_rdata_ff[62],ifu_bus_rdata_ff[59],ifu_bus_rdata_ff[58],ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[55],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[51],ifu_bus_rdata_ff[48],_T_723}; // @[lib.scala 276:98] + wire [34:0] _T_733 = {_T_732,_T_715}; // @[lib.scala 276:98] + wire _T_734 = ^_T_733; // @[lib.scala 276:105] + wire [7:0] _T_741 = {ifu_bus_rdata_ff[11],ifu_bus_rdata_ff[10],ifu_bus_rdata_ff[8],ifu_bus_rdata_ff[6],ifu_bus_rdata_ff[4],ifu_bus_rdata_ff[3],ifu_bus_rdata_ff[1],ifu_bus_rdata_ff[0]}; // @[lib.scala 276:115] + wire [16:0] _T_750 = {ifu_bus_rdata_ff[28],ifu_bus_rdata_ff[26],ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[23],ifu_bus_rdata_ff[21],ifu_bus_rdata_ff[19],ifu_bus_rdata_ff[17],ifu_bus_rdata_ff[15],ifu_bus_rdata_ff[13],_T_741}; // @[lib.scala 276:115] + wire [8:0] _T_758 = {ifu_bus_rdata_ff[46],ifu_bus_rdata_ff[44],ifu_bus_rdata_ff[42],ifu_bus_rdata_ff[40],ifu_bus_rdata_ff[38],ifu_bus_rdata_ff[36],ifu_bus_rdata_ff[34],ifu_bus_rdata_ff[32],ifu_bus_rdata_ff[30]}; // @[lib.scala 276:115] + wire [17:0] _T_767 = {ifu_bus_rdata_ff[63],ifu_bus_rdata_ff[61],ifu_bus_rdata_ff[59],ifu_bus_rdata_ff[57],ifu_bus_rdata_ff[56],ifu_bus_rdata_ff[54],ifu_bus_rdata_ff[52],ifu_bus_rdata_ff[50],ifu_bus_rdata_ff[48],_T_758}; // @[lib.scala 276:115] + wire [34:0] _T_768 = {_T_767,_T_750}; // @[lib.scala 276:115] + wire _T_769 = ^_T_768; // @[lib.scala 276:122] wire [3:0] _T_2330 = {ifu_bus_rid_ff[2:1],_T_2289,1'h1}; // @[Cat.scala 29:58] wire _T_2331 = _T_2330 == 4'h0; // @[ifu_mem_ctl.scala 381:89] reg [31:0] ic_miss_buff_data_0; // @[ifu_mem_ctl.scala 316:65] @@ -2124,40 +2124,40 @@ module ifu_mem_ctl( wire [31:0] _T_2473 = _T_2456 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2488 = _T_2487 | _T_2473; // @[Mux.scala 27:72] wire [63:0] ic_miss_buff_half = {_T_2408,_T_2488}; // @[Cat.scala 29:58] - wire [6:0] _T_992 = {ic_miss_buff_half[63],ic_miss_buff_half[62],ic_miss_buff_half[61],ic_miss_buff_half[60],ic_miss_buff_half[59],ic_miss_buff_half[58],ic_miss_buff_half[57]}; // @[el2_lib.scala 416:13] - wire _T_993 = ^_T_992; // @[el2_lib.scala 416:20] - wire [6:0] _T_999 = {ic_miss_buff_half[32],ic_miss_buff_half[31],ic_miss_buff_half[30],ic_miss_buff_half[29],ic_miss_buff_half[28],ic_miss_buff_half[27],ic_miss_buff_half[26]}; // @[el2_lib.scala 416:30] - wire [7:0] _T_1006 = {ic_miss_buff_half[40],ic_miss_buff_half[39],ic_miss_buff_half[38],ic_miss_buff_half[37],ic_miss_buff_half[36],ic_miss_buff_half[35],ic_miss_buff_half[34],ic_miss_buff_half[33]}; // @[el2_lib.scala 416:30] - wire [14:0] _T_1007 = {ic_miss_buff_half[40],ic_miss_buff_half[39],ic_miss_buff_half[38],ic_miss_buff_half[37],ic_miss_buff_half[36],ic_miss_buff_half[35],ic_miss_buff_half[34],ic_miss_buff_half[33],_T_999}; // @[el2_lib.scala 416:30] - wire [7:0] _T_1014 = {ic_miss_buff_half[48],ic_miss_buff_half[47],ic_miss_buff_half[46],ic_miss_buff_half[45],ic_miss_buff_half[44],ic_miss_buff_half[43],ic_miss_buff_half[42],ic_miss_buff_half[41]}; // @[el2_lib.scala 416:30] - wire [30:0] _T_1023 = {ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[54],ic_miss_buff_half[53],ic_miss_buff_half[52],ic_miss_buff_half[51],ic_miss_buff_half[50],ic_miss_buff_half[49],_T_1014,_T_1007}; // @[el2_lib.scala 416:30] - wire _T_1024 = ^_T_1023; // @[el2_lib.scala 416:37] - wire [6:0] _T_1030 = {ic_miss_buff_half[17],ic_miss_buff_half[16],ic_miss_buff_half[15],ic_miss_buff_half[14],ic_miss_buff_half[13],ic_miss_buff_half[12],ic_miss_buff_half[11]}; // @[el2_lib.scala 416:47] - wire [14:0] _T_1038 = {ic_miss_buff_half[25],ic_miss_buff_half[24],ic_miss_buff_half[23],ic_miss_buff_half[22],ic_miss_buff_half[21],ic_miss_buff_half[20],ic_miss_buff_half[19],ic_miss_buff_half[18],_T_1030}; // @[el2_lib.scala 416:47] - wire [30:0] _T_1054 = {ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[54],ic_miss_buff_half[53],ic_miss_buff_half[52],ic_miss_buff_half[51],ic_miss_buff_half[50],ic_miss_buff_half[49],_T_1014,_T_1038}; // @[el2_lib.scala 416:47] - wire _T_1055 = ^_T_1054; // @[el2_lib.scala 416:54] - wire [6:0] _T_1061 = {ic_miss_buff_half[10],ic_miss_buff_half[9],ic_miss_buff_half[8],ic_miss_buff_half[7],ic_miss_buff_half[6],ic_miss_buff_half[5],ic_miss_buff_half[4]}; // @[el2_lib.scala 416:64] - wire [14:0] _T_1069 = {ic_miss_buff_half[25],ic_miss_buff_half[24],ic_miss_buff_half[23],ic_miss_buff_half[22],ic_miss_buff_half[21],ic_miss_buff_half[20],ic_miss_buff_half[19],ic_miss_buff_half[18],_T_1061}; // @[el2_lib.scala 416:64] - wire [30:0] _T_1085 = {ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[54],ic_miss_buff_half[53],ic_miss_buff_half[52],ic_miss_buff_half[51],ic_miss_buff_half[50],ic_miss_buff_half[49],_T_1006,_T_1069}; // @[el2_lib.scala 416:64] - wire _T_1086 = ^_T_1085; // @[el2_lib.scala 416:71] - wire [7:0] _T_1093 = {ic_miss_buff_half[14],ic_miss_buff_half[10],ic_miss_buff_half[9],ic_miss_buff_half[8],ic_miss_buff_half[7],ic_miss_buff_half[3],ic_miss_buff_half[2],ic_miss_buff_half[1]}; // @[el2_lib.scala 416:81] - wire [16:0] _T_1102 = {ic_miss_buff_half[30],ic_miss_buff_half[29],ic_miss_buff_half[25],ic_miss_buff_half[24],ic_miss_buff_half[23],ic_miss_buff_half[22],ic_miss_buff_half[17],ic_miss_buff_half[16],ic_miss_buff_half[15],_T_1093}; // @[el2_lib.scala 416:81] - wire [8:0] _T_1110 = {ic_miss_buff_half[47],ic_miss_buff_half[46],ic_miss_buff_half[45],ic_miss_buff_half[40],ic_miss_buff_half[39],ic_miss_buff_half[38],ic_miss_buff_half[37],ic_miss_buff_half[32],ic_miss_buff_half[31]}; // @[el2_lib.scala 416:81] - wire [17:0] _T_1119 = {ic_miss_buff_half[63],ic_miss_buff_half[62],ic_miss_buff_half[61],ic_miss_buff_half[60],ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[54],ic_miss_buff_half[53],ic_miss_buff_half[48],_T_1110}; // @[el2_lib.scala 416:81] - wire [34:0] _T_1120 = {_T_1119,_T_1102}; // @[el2_lib.scala 416:81] - wire _T_1121 = ^_T_1120; // @[el2_lib.scala 416:88] - wire [7:0] _T_1128 = {ic_miss_buff_half[12],ic_miss_buff_half[10],ic_miss_buff_half[9],ic_miss_buff_half[6],ic_miss_buff_half[5],ic_miss_buff_half[3],ic_miss_buff_half[2],ic_miss_buff_half[0]}; // @[el2_lib.scala 416:98] - wire [16:0] _T_1137 = {ic_miss_buff_half[28],ic_miss_buff_half[27],ic_miss_buff_half[25],ic_miss_buff_half[24],ic_miss_buff_half[21],ic_miss_buff_half[20],ic_miss_buff_half[17],ic_miss_buff_half[16],ic_miss_buff_half[13],_T_1128}; // @[el2_lib.scala 416:98] - wire [8:0] _T_1145 = {ic_miss_buff_half[47],ic_miss_buff_half[44],ic_miss_buff_half[43],ic_miss_buff_half[40],ic_miss_buff_half[39],ic_miss_buff_half[36],ic_miss_buff_half[35],ic_miss_buff_half[32],ic_miss_buff_half[31]}; // @[el2_lib.scala 416:98] - wire [17:0] _T_1154 = {ic_miss_buff_half[63],ic_miss_buff_half[62],ic_miss_buff_half[59],ic_miss_buff_half[58],ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[52],ic_miss_buff_half[51],ic_miss_buff_half[48],_T_1145}; // @[el2_lib.scala 416:98] - wire [34:0] _T_1155 = {_T_1154,_T_1137}; // @[el2_lib.scala 416:98] - wire _T_1156 = ^_T_1155; // @[el2_lib.scala 416:105] - wire [7:0] _T_1163 = {ic_miss_buff_half[11],ic_miss_buff_half[10],ic_miss_buff_half[8],ic_miss_buff_half[6],ic_miss_buff_half[4],ic_miss_buff_half[3],ic_miss_buff_half[1],ic_miss_buff_half[0]}; // @[el2_lib.scala 416:115] - wire [16:0] _T_1172 = {ic_miss_buff_half[28],ic_miss_buff_half[26],ic_miss_buff_half[25],ic_miss_buff_half[23],ic_miss_buff_half[21],ic_miss_buff_half[19],ic_miss_buff_half[17],ic_miss_buff_half[15],ic_miss_buff_half[13],_T_1163}; // @[el2_lib.scala 416:115] - wire [8:0] _T_1180 = {ic_miss_buff_half[46],ic_miss_buff_half[44],ic_miss_buff_half[42],ic_miss_buff_half[40],ic_miss_buff_half[38],ic_miss_buff_half[36],ic_miss_buff_half[34],ic_miss_buff_half[32],ic_miss_buff_half[30]}; // @[el2_lib.scala 416:115] - wire [17:0] _T_1189 = {ic_miss_buff_half[63],ic_miss_buff_half[61],ic_miss_buff_half[59],ic_miss_buff_half[57],ic_miss_buff_half[56],ic_miss_buff_half[54],ic_miss_buff_half[52],ic_miss_buff_half[50],ic_miss_buff_half[48],_T_1180}; // @[el2_lib.scala 416:115] - wire [34:0] _T_1190 = {_T_1189,_T_1172}; // @[el2_lib.scala 416:115] - wire _T_1191 = ^_T_1190; // @[el2_lib.scala 416:122] + wire [6:0] _T_992 = {ic_miss_buff_half[63],ic_miss_buff_half[62],ic_miss_buff_half[61],ic_miss_buff_half[60],ic_miss_buff_half[59],ic_miss_buff_half[58],ic_miss_buff_half[57]}; // @[lib.scala 276:13] + wire _T_993 = ^_T_992; // @[lib.scala 276:20] + wire [6:0] _T_999 = {ic_miss_buff_half[32],ic_miss_buff_half[31],ic_miss_buff_half[30],ic_miss_buff_half[29],ic_miss_buff_half[28],ic_miss_buff_half[27],ic_miss_buff_half[26]}; // @[lib.scala 276:30] + wire [7:0] _T_1006 = {ic_miss_buff_half[40],ic_miss_buff_half[39],ic_miss_buff_half[38],ic_miss_buff_half[37],ic_miss_buff_half[36],ic_miss_buff_half[35],ic_miss_buff_half[34],ic_miss_buff_half[33]}; // @[lib.scala 276:30] + wire [14:0] _T_1007 = {ic_miss_buff_half[40],ic_miss_buff_half[39],ic_miss_buff_half[38],ic_miss_buff_half[37],ic_miss_buff_half[36],ic_miss_buff_half[35],ic_miss_buff_half[34],ic_miss_buff_half[33],_T_999}; // @[lib.scala 276:30] + wire [7:0] _T_1014 = {ic_miss_buff_half[48],ic_miss_buff_half[47],ic_miss_buff_half[46],ic_miss_buff_half[45],ic_miss_buff_half[44],ic_miss_buff_half[43],ic_miss_buff_half[42],ic_miss_buff_half[41]}; // @[lib.scala 276:30] + wire [30:0] _T_1023 = {ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[54],ic_miss_buff_half[53],ic_miss_buff_half[52],ic_miss_buff_half[51],ic_miss_buff_half[50],ic_miss_buff_half[49],_T_1014,_T_1007}; // @[lib.scala 276:30] + wire _T_1024 = ^_T_1023; // @[lib.scala 276:37] + wire [6:0] _T_1030 = {ic_miss_buff_half[17],ic_miss_buff_half[16],ic_miss_buff_half[15],ic_miss_buff_half[14],ic_miss_buff_half[13],ic_miss_buff_half[12],ic_miss_buff_half[11]}; // @[lib.scala 276:47] + wire [14:0] _T_1038 = {ic_miss_buff_half[25],ic_miss_buff_half[24],ic_miss_buff_half[23],ic_miss_buff_half[22],ic_miss_buff_half[21],ic_miss_buff_half[20],ic_miss_buff_half[19],ic_miss_buff_half[18],_T_1030}; // @[lib.scala 276:47] + wire [30:0] _T_1054 = {ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[54],ic_miss_buff_half[53],ic_miss_buff_half[52],ic_miss_buff_half[51],ic_miss_buff_half[50],ic_miss_buff_half[49],_T_1014,_T_1038}; // @[lib.scala 276:47] + wire _T_1055 = ^_T_1054; // @[lib.scala 276:54] + wire [6:0] _T_1061 = {ic_miss_buff_half[10],ic_miss_buff_half[9],ic_miss_buff_half[8],ic_miss_buff_half[7],ic_miss_buff_half[6],ic_miss_buff_half[5],ic_miss_buff_half[4]}; // @[lib.scala 276:64] + wire [14:0] _T_1069 = {ic_miss_buff_half[25],ic_miss_buff_half[24],ic_miss_buff_half[23],ic_miss_buff_half[22],ic_miss_buff_half[21],ic_miss_buff_half[20],ic_miss_buff_half[19],ic_miss_buff_half[18],_T_1061}; // @[lib.scala 276:64] + wire [30:0] _T_1085 = {ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[54],ic_miss_buff_half[53],ic_miss_buff_half[52],ic_miss_buff_half[51],ic_miss_buff_half[50],ic_miss_buff_half[49],_T_1006,_T_1069}; // @[lib.scala 276:64] + wire _T_1086 = ^_T_1085; // @[lib.scala 276:71] + wire [7:0] _T_1093 = {ic_miss_buff_half[14],ic_miss_buff_half[10],ic_miss_buff_half[9],ic_miss_buff_half[8],ic_miss_buff_half[7],ic_miss_buff_half[3],ic_miss_buff_half[2],ic_miss_buff_half[1]}; // @[lib.scala 276:81] + wire [16:0] _T_1102 = {ic_miss_buff_half[30],ic_miss_buff_half[29],ic_miss_buff_half[25],ic_miss_buff_half[24],ic_miss_buff_half[23],ic_miss_buff_half[22],ic_miss_buff_half[17],ic_miss_buff_half[16],ic_miss_buff_half[15],_T_1093}; // @[lib.scala 276:81] + wire [8:0] _T_1110 = {ic_miss_buff_half[47],ic_miss_buff_half[46],ic_miss_buff_half[45],ic_miss_buff_half[40],ic_miss_buff_half[39],ic_miss_buff_half[38],ic_miss_buff_half[37],ic_miss_buff_half[32],ic_miss_buff_half[31]}; // @[lib.scala 276:81] + wire [17:0] _T_1119 = {ic_miss_buff_half[63],ic_miss_buff_half[62],ic_miss_buff_half[61],ic_miss_buff_half[60],ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[54],ic_miss_buff_half[53],ic_miss_buff_half[48],_T_1110}; // @[lib.scala 276:81] + wire [34:0] _T_1120 = {_T_1119,_T_1102}; // @[lib.scala 276:81] + wire _T_1121 = ^_T_1120; // @[lib.scala 276:88] + wire [7:0] _T_1128 = {ic_miss_buff_half[12],ic_miss_buff_half[10],ic_miss_buff_half[9],ic_miss_buff_half[6],ic_miss_buff_half[5],ic_miss_buff_half[3],ic_miss_buff_half[2],ic_miss_buff_half[0]}; // @[lib.scala 276:98] + wire [16:0] _T_1137 = {ic_miss_buff_half[28],ic_miss_buff_half[27],ic_miss_buff_half[25],ic_miss_buff_half[24],ic_miss_buff_half[21],ic_miss_buff_half[20],ic_miss_buff_half[17],ic_miss_buff_half[16],ic_miss_buff_half[13],_T_1128}; // @[lib.scala 276:98] + wire [8:0] _T_1145 = {ic_miss_buff_half[47],ic_miss_buff_half[44],ic_miss_buff_half[43],ic_miss_buff_half[40],ic_miss_buff_half[39],ic_miss_buff_half[36],ic_miss_buff_half[35],ic_miss_buff_half[32],ic_miss_buff_half[31]}; // @[lib.scala 276:98] + wire [17:0] _T_1154 = {ic_miss_buff_half[63],ic_miss_buff_half[62],ic_miss_buff_half[59],ic_miss_buff_half[58],ic_miss_buff_half[56],ic_miss_buff_half[55],ic_miss_buff_half[52],ic_miss_buff_half[51],ic_miss_buff_half[48],_T_1145}; // @[lib.scala 276:98] + wire [34:0] _T_1155 = {_T_1154,_T_1137}; // @[lib.scala 276:98] + wire _T_1156 = ^_T_1155; // @[lib.scala 276:105] + wire [7:0] _T_1163 = {ic_miss_buff_half[11],ic_miss_buff_half[10],ic_miss_buff_half[8],ic_miss_buff_half[6],ic_miss_buff_half[4],ic_miss_buff_half[3],ic_miss_buff_half[1],ic_miss_buff_half[0]}; // @[lib.scala 276:115] + wire [16:0] _T_1172 = {ic_miss_buff_half[28],ic_miss_buff_half[26],ic_miss_buff_half[25],ic_miss_buff_half[23],ic_miss_buff_half[21],ic_miss_buff_half[19],ic_miss_buff_half[17],ic_miss_buff_half[15],ic_miss_buff_half[13],_T_1163}; // @[lib.scala 276:115] + wire [8:0] _T_1180 = {ic_miss_buff_half[46],ic_miss_buff_half[44],ic_miss_buff_half[42],ic_miss_buff_half[40],ic_miss_buff_half[38],ic_miss_buff_half[36],ic_miss_buff_half[34],ic_miss_buff_half[32],ic_miss_buff_half[30]}; // @[lib.scala 276:115] + wire [17:0] _T_1189 = {ic_miss_buff_half[63],ic_miss_buff_half[61],ic_miss_buff_half[59],ic_miss_buff_half[57],ic_miss_buff_half[56],ic_miss_buff_half[54],ic_miss_buff_half[52],ic_miss_buff_half[50],ic_miss_buff_half[48],_T_1180}; // @[lib.scala 276:115] + wire [34:0] _T_1190 = {_T_1189,_T_1172}; // @[lib.scala 276:115] + wire _T_1191 = ^_T_1190; // @[lib.scala 276:122] wire [70:0] _T_1236 = {_T_571,_T_602,_T_633,_T_664,_T_699,_T_734,_T_769,ifu_bus_rdata_ff}; // @[Cat.scala 29:58] wire [70:0] _T_1235 = {_T_993,_T_1024,_T_1055,_T_1086,_T_1121,_T_1156,_T_1191,_T_2408,_T_2488}; // @[Cat.scala 29:58] wire [141:0] _T_1237 = {_T_571,_T_602,_T_633,_T_664,_T_699,_T_734,_T_769,ifu_bus_rdata_ff,_T_1235}; // @[Cat.scala 29:58] @@ -3455,182 +3455,182 @@ module ifu_mem_ctl( wire _T_2714 = _T_2709 & _T_2713; // @[ifu_mem_ctl.scala 570:70] wire _T_2715 = io_ifc_iccm_access_bf & io_ifc_fetch_req_bf; // @[ifu_mem_ctl.scala 570:128] wire [2:0] _T_2720 = io_dma_mem_ctl_dma_iccm_req ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire _T_2741 = io_dma_mem_ctl_dma_mem_wdata[32] ^ io_dma_mem_ctl_dma_mem_wdata[33]; // @[el2_lib.scala 259:74] - wire _T_2742 = _T_2741 ^ io_dma_mem_ctl_dma_mem_wdata[35]; // @[el2_lib.scala 259:74] - wire _T_2743 = _T_2742 ^ io_dma_mem_ctl_dma_mem_wdata[36]; // @[el2_lib.scala 259:74] - wire _T_2744 = _T_2743 ^ io_dma_mem_ctl_dma_mem_wdata[38]; // @[el2_lib.scala 259:74] - wire _T_2745 = _T_2744 ^ io_dma_mem_ctl_dma_mem_wdata[40]; // @[el2_lib.scala 259:74] - wire _T_2746 = _T_2745 ^ io_dma_mem_ctl_dma_mem_wdata[42]; // @[el2_lib.scala 259:74] - wire _T_2747 = _T_2746 ^ io_dma_mem_ctl_dma_mem_wdata[43]; // @[el2_lib.scala 259:74] - wire _T_2748 = _T_2747 ^ io_dma_mem_ctl_dma_mem_wdata[45]; // @[el2_lib.scala 259:74] - wire _T_2749 = _T_2748 ^ io_dma_mem_ctl_dma_mem_wdata[47]; // @[el2_lib.scala 259:74] - wire _T_2750 = _T_2749 ^ io_dma_mem_ctl_dma_mem_wdata[49]; // @[el2_lib.scala 259:74] - wire _T_2751 = _T_2750 ^ io_dma_mem_ctl_dma_mem_wdata[51]; // @[el2_lib.scala 259:74] - wire _T_2752 = _T_2751 ^ io_dma_mem_ctl_dma_mem_wdata[53]; // @[el2_lib.scala 259:74] - wire _T_2753 = _T_2752 ^ io_dma_mem_ctl_dma_mem_wdata[55]; // @[el2_lib.scala 259:74] - wire _T_2754 = _T_2753 ^ io_dma_mem_ctl_dma_mem_wdata[57]; // @[el2_lib.scala 259:74] - wire _T_2755 = _T_2754 ^ io_dma_mem_ctl_dma_mem_wdata[58]; // @[el2_lib.scala 259:74] - wire _T_2756 = _T_2755 ^ io_dma_mem_ctl_dma_mem_wdata[60]; // @[el2_lib.scala 259:74] - wire _T_2757 = _T_2756 ^ io_dma_mem_ctl_dma_mem_wdata[62]; // @[el2_lib.scala 259:74] - wire _T_2776 = io_dma_mem_ctl_dma_mem_wdata[32] ^ io_dma_mem_ctl_dma_mem_wdata[34]; // @[el2_lib.scala 259:74] - wire _T_2777 = _T_2776 ^ io_dma_mem_ctl_dma_mem_wdata[35]; // @[el2_lib.scala 259:74] - wire _T_2778 = _T_2777 ^ io_dma_mem_ctl_dma_mem_wdata[37]; // @[el2_lib.scala 259:74] - wire _T_2779 = _T_2778 ^ io_dma_mem_ctl_dma_mem_wdata[38]; // @[el2_lib.scala 259:74] - wire _T_2780 = _T_2779 ^ io_dma_mem_ctl_dma_mem_wdata[41]; // @[el2_lib.scala 259:74] - wire _T_2781 = _T_2780 ^ io_dma_mem_ctl_dma_mem_wdata[42]; // @[el2_lib.scala 259:74] - wire _T_2782 = _T_2781 ^ io_dma_mem_ctl_dma_mem_wdata[44]; // @[el2_lib.scala 259:74] - wire _T_2783 = _T_2782 ^ io_dma_mem_ctl_dma_mem_wdata[45]; // @[el2_lib.scala 259:74] - wire _T_2784 = _T_2783 ^ io_dma_mem_ctl_dma_mem_wdata[48]; // @[el2_lib.scala 259:74] - wire _T_2785 = _T_2784 ^ io_dma_mem_ctl_dma_mem_wdata[49]; // @[el2_lib.scala 259:74] - wire _T_2786 = _T_2785 ^ io_dma_mem_ctl_dma_mem_wdata[52]; // @[el2_lib.scala 259:74] - wire _T_2787 = _T_2786 ^ io_dma_mem_ctl_dma_mem_wdata[53]; // @[el2_lib.scala 259:74] - wire _T_2788 = _T_2787 ^ io_dma_mem_ctl_dma_mem_wdata[56]; // @[el2_lib.scala 259:74] - wire _T_2789 = _T_2788 ^ io_dma_mem_ctl_dma_mem_wdata[57]; // @[el2_lib.scala 259:74] - wire _T_2790 = _T_2789 ^ io_dma_mem_ctl_dma_mem_wdata[59]; // @[el2_lib.scala 259:74] - wire _T_2791 = _T_2790 ^ io_dma_mem_ctl_dma_mem_wdata[60]; // @[el2_lib.scala 259:74] - wire _T_2792 = _T_2791 ^ io_dma_mem_ctl_dma_mem_wdata[63]; // @[el2_lib.scala 259:74] - wire _T_2811 = io_dma_mem_ctl_dma_mem_wdata[33] ^ io_dma_mem_ctl_dma_mem_wdata[34]; // @[el2_lib.scala 259:74] - wire _T_2812 = _T_2811 ^ io_dma_mem_ctl_dma_mem_wdata[35]; // @[el2_lib.scala 259:74] - wire _T_2813 = _T_2812 ^ io_dma_mem_ctl_dma_mem_wdata[39]; // @[el2_lib.scala 259:74] - wire _T_2814 = _T_2813 ^ io_dma_mem_ctl_dma_mem_wdata[40]; // @[el2_lib.scala 259:74] - wire _T_2815 = _T_2814 ^ io_dma_mem_ctl_dma_mem_wdata[41]; // @[el2_lib.scala 259:74] - wire _T_2816 = _T_2815 ^ io_dma_mem_ctl_dma_mem_wdata[42]; // @[el2_lib.scala 259:74] - wire _T_2817 = _T_2816 ^ io_dma_mem_ctl_dma_mem_wdata[46]; // @[el2_lib.scala 259:74] - wire _T_2818 = _T_2817 ^ io_dma_mem_ctl_dma_mem_wdata[47]; // @[el2_lib.scala 259:74] - wire _T_2819 = _T_2818 ^ io_dma_mem_ctl_dma_mem_wdata[48]; // @[el2_lib.scala 259:74] - wire _T_2820 = _T_2819 ^ io_dma_mem_ctl_dma_mem_wdata[49]; // @[el2_lib.scala 259:74] - wire _T_2821 = _T_2820 ^ io_dma_mem_ctl_dma_mem_wdata[54]; // @[el2_lib.scala 259:74] - wire _T_2822 = _T_2821 ^ io_dma_mem_ctl_dma_mem_wdata[55]; // @[el2_lib.scala 259:74] - wire _T_2823 = _T_2822 ^ io_dma_mem_ctl_dma_mem_wdata[56]; // @[el2_lib.scala 259:74] - wire _T_2824 = _T_2823 ^ io_dma_mem_ctl_dma_mem_wdata[57]; // @[el2_lib.scala 259:74] - wire _T_2825 = _T_2824 ^ io_dma_mem_ctl_dma_mem_wdata[61]; // @[el2_lib.scala 259:74] - wire _T_2826 = _T_2825 ^ io_dma_mem_ctl_dma_mem_wdata[62]; // @[el2_lib.scala 259:74] - wire _T_2827 = _T_2826 ^ io_dma_mem_ctl_dma_mem_wdata[63]; // @[el2_lib.scala 259:74] - wire _T_2843 = io_dma_mem_ctl_dma_mem_wdata[36] ^ io_dma_mem_ctl_dma_mem_wdata[37]; // @[el2_lib.scala 259:74] - wire _T_2844 = _T_2843 ^ io_dma_mem_ctl_dma_mem_wdata[38]; // @[el2_lib.scala 259:74] - wire _T_2845 = _T_2844 ^ io_dma_mem_ctl_dma_mem_wdata[39]; // @[el2_lib.scala 259:74] - wire _T_2846 = _T_2845 ^ io_dma_mem_ctl_dma_mem_wdata[40]; // @[el2_lib.scala 259:74] - wire _T_2847 = _T_2846 ^ io_dma_mem_ctl_dma_mem_wdata[41]; // @[el2_lib.scala 259:74] - wire _T_2848 = _T_2847 ^ io_dma_mem_ctl_dma_mem_wdata[42]; // @[el2_lib.scala 259:74] - wire _T_2849 = _T_2848 ^ io_dma_mem_ctl_dma_mem_wdata[50]; // @[el2_lib.scala 259:74] - wire _T_2850 = _T_2849 ^ io_dma_mem_ctl_dma_mem_wdata[51]; // @[el2_lib.scala 259:74] - wire _T_2851 = _T_2850 ^ io_dma_mem_ctl_dma_mem_wdata[52]; // @[el2_lib.scala 259:74] - wire _T_2852 = _T_2851 ^ io_dma_mem_ctl_dma_mem_wdata[53]; // @[el2_lib.scala 259:74] - wire _T_2853 = _T_2852 ^ io_dma_mem_ctl_dma_mem_wdata[54]; // @[el2_lib.scala 259:74] - wire _T_2854 = _T_2853 ^ io_dma_mem_ctl_dma_mem_wdata[55]; // @[el2_lib.scala 259:74] - wire _T_2855 = _T_2854 ^ io_dma_mem_ctl_dma_mem_wdata[56]; // @[el2_lib.scala 259:74] - wire _T_2856 = _T_2855 ^ io_dma_mem_ctl_dma_mem_wdata[57]; // @[el2_lib.scala 259:74] - wire _T_2872 = io_dma_mem_ctl_dma_mem_wdata[43] ^ io_dma_mem_ctl_dma_mem_wdata[44]; // @[el2_lib.scala 259:74] - wire _T_2873 = _T_2872 ^ io_dma_mem_ctl_dma_mem_wdata[45]; // @[el2_lib.scala 259:74] - wire _T_2874 = _T_2873 ^ io_dma_mem_ctl_dma_mem_wdata[46]; // @[el2_lib.scala 259:74] - wire _T_2875 = _T_2874 ^ io_dma_mem_ctl_dma_mem_wdata[47]; // @[el2_lib.scala 259:74] - wire _T_2876 = _T_2875 ^ io_dma_mem_ctl_dma_mem_wdata[48]; // @[el2_lib.scala 259:74] - wire _T_2877 = _T_2876 ^ io_dma_mem_ctl_dma_mem_wdata[49]; // @[el2_lib.scala 259:74] - wire _T_2878 = _T_2877 ^ io_dma_mem_ctl_dma_mem_wdata[50]; // @[el2_lib.scala 259:74] - wire _T_2879 = _T_2878 ^ io_dma_mem_ctl_dma_mem_wdata[51]; // @[el2_lib.scala 259:74] - wire _T_2880 = _T_2879 ^ io_dma_mem_ctl_dma_mem_wdata[52]; // @[el2_lib.scala 259:74] - wire _T_2881 = _T_2880 ^ io_dma_mem_ctl_dma_mem_wdata[53]; // @[el2_lib.scala 259:74] - wire _T_2882 = _T_2881 ^ io_dma_mem_ctl_dma_mem_wdata[54]; // @[el2_lib.scala 259:74] - wire _T_2883 = _T_2882 ^ io_dma_mem_ctl_dma_mem_wdata[55]; // @[el2_lib.scala 259:74] - wire _T_2884 = _T_2883 ^ io_dma_mem_ctl_dma_mem_wdata[56]; // @[el2_lib.scala 259:74] - wire _T_2885 = _T_2884 ^ io_dma_mem_ctl_dma_mem_wdata[57]; // @[el2_lib.scala 259:74] - wire _T_2892 = io_dma_mem_ctl_dma_mem_wdata[58] ^ io_dma_mem_ctl_dma_mem_wdata[59]; // @[el2_lib.scala 259:74] - wire _T_2893 = _T_2892 ^ io_dma_mem_ctl_dma_mem_wdata[60]; // @[el2_lib.scala 259:74] - wire _T_2894 = _T_2893 ^ io_dma_mem_ctl_dma_mem_wdata[61]; // @[el2_lib.scala 259:74] - wire _T_2895 = _T_2894 ^ io_dma_mem_ctl_dma_mem_wdata[62]; // @[el2_lib.scala 259:74] - wire _T_2896 = _T_2895 ^ io_dma_mem_ctl_dma_mem_wdata[63]; // @[el2_lib.scala 259:74] + wire _T_2741 = io_dma_mem_ctl_dma_mem_wdata[32] ^ io_dma_mem_ctl_dma_mem_wdata[33]; // @[lib.scala 119:74] + wire _T_2742 = _T_2741 ^ io_dma_mem_ctl_dma_mem_wdata[35]; // @[lib.scala 119:74] + wire _T_2743 = _T_2742 ^ io_dma_mem_ctl_dma_mem_wdata[36]; // @[lib.scala 119:74] + wire _T_2744 = _T_2743 ^ io_dma_mem_ctl_dma_mem_wdata[38]; // @[lib.scala 119:74] + wire _T_2745 = _T_2744 ^ io_dma_mem_ctl_dma_mem_wdata[40]; // @[lib.scala 119:74] + wire _T_2746 = _T_2745 ^ io_dma_mem_ctl_dma_mem_wdata[42]; // @[lib.scala 119:74] + wire _T_2747 = _T_2746 ^ io_dma_mem_ctl_dma_mem_wdata[43]; // @[lib.scala 119:74] + wire _T_2748 = _T_2747 ^ io_dma_mem_ctl_dma_mem_wdata[45]; // @[lib.scala 119:74] + wire _T_2749 = _T_2748 ^ io_dma_mem_ctl_dma_mem_wdata[47]; // @[lib.scala 119:74] + wire _T_2750 = _T_2749 ^ io_dma_mem_ctl_dma_mem_wdata[49]; // @[lib.scala 119:74] + wire _T_2751 = _T_2750 ^ io_dma_mem_ctl_dma_mem_wdata[51]; // @[lib.scala 119:74] + wire _T_2752 = _T_2751 ^ io_dma_mem_ctl_dma_mem_wdata[53]; // @[lib.scala 119:74] + wire _T_2753 = _T_2752 ^ io_dma_mem_ctl_dma_mem_wdata[55]; // @[lib.scala 119:74] + wire _T_2754 = _T_2753 ^ io_dma_mem_ctl_dma_mem_wdata[57]; // @[lib.scala 119:74] + wire _T_2755 = _T_2754 ^ io_dma_mem_ctl_dma_mem_wdata[58]; // @[lib.scala 119:74] + wire _T_2756 = _T_2755 ^ io_dma_mem_ctl_dma_mem_wdata[60]; // @[lib.scala 119:74] + wire _T_2757 = _T_2756 ^ io_dma_mem_ctl_dma_mem_wdata[62]; // @[lib.scala 119:74] + wire _T_2776 = io_dma_mem_ctl_dma_mem_wdata[32] ^ io_dma_mem_ctl_dma_mem_wdata[34]; // @[lib.scala 119:74] + wire _T_2777 = _T_2776 ^ io_dma_mem_ctl_dma_mem_wdata[35]; // @[lib.scala 119:74] + wire _T_2778 = _T_2777 ^ io_dma_mem_ctl_dma_mem_wdata[37]; // @[lib.scala 119:74] + wire _T_2779 = _T_2778 ^ io_dma_mem_ctl_dma_mem_wdata[38]; // @[lib.scala 119:74] + wire _T_2780 = _T_2779 ^ io_dma_mem_ctl_dma_mem_wdata[41]; // @[lib.scala 119:74] + wire _T_2781 = _T_2780 ^ io_dma_mem_ctl_dma_mem_wdata[42]; // @[lib.scala 119:74] + wire _T_2782 = _T_2781 ^ io_dma_mem_ctl_dma_mem_wdata[44]; // @[lib.scala 119:74] + wire _T_2783 = _T_2782 ^ io_dma_mem_ctl_dma_mem_wdata[45]; // @[lib.scala 119:74] + wire _T_2784 = _T_2783 ^ io_dma_mem_ctl_dma_mem_wdata[48]; // @[lib.scala 119:74] + wire _T_2785 = _T_2784 ^ io_dma_mem_ctl_dma_mem_wdata[49]; // @[lib.scala 119:74] + wire _T_2786 = _T_2785 ^ io_dma_mem_ctl_dma_mem_wdata[52]; // @[lib.scala 119:74] + wire _T_2787 = _T_2786 ^ io_dma_mem_ctl_dma_mem_wdata[53]; // @[lib.scala 119:74] + wire _T_2788 = _T_2787 ^ io_dma_mem_ctl_dma_mem_wdata[56]; // @[lib.scala 119:74] + wire _T_2789 = _T_2788 ^ io_dma_mem_ctl_dma_mem_wdata[57]; // @[lib.scala 119:74] + wire _T_2790 = _T_2789 ^ io_dma_mem_ctl_dma_mem_wdata[59]; // @[lib.scala 119:74] + wire _T_2791 = _T_2790 ^ io_dma_mem_ctl_dma_mem_wdata[60]; // @[lib.scala 119:74] + wire _T_2792 = _T_2791 ^ io_dma_mem_ctl_dma_mem_wdata[63]; // @[lib.scala 119:74] + wire _T_2811 = io_dma_mem_ctl_dma_mem_wdata[33] ^ io_dma_mem_ctl_dma_mem_wdata[34]; // @[lib.scala 119:74] + wire _T_2812 = _T_2811 ^ io_dma_mem_ctl_dma_mem_wdata[35]; // @[lib.scala 119:74] + wire _T_2813 = _T_2812 ^ io_dma_mem_ctl_dma_mem_wdata[39]; // @[lib.scala 119:74] + wire _T_2814 = _T_2813 ^ io_dma_mem_ctl_dma_mem_wdata[40]; // @[lib.scala 119:74] + wire _T_2815 = _T_2814 ^ io_dma_mem_ctl_dma_mem_wdata[41]; // @[lib.scala 119:74] + wire _T_2816 = _T_2815 ^ io_dma_mem_ctl_dma_mem_wdata[42]; // @[lib.scala 119:74] + wire _T_2817 = _T_2816 ^ io_dma_mem_ctl_dma_mem_wdata[46]; // @[lib.scala 119:74] + wire _T_2818 = _T_2817 ^ io_dma_mem_ctl_dma_mem_wdata[47]; // @[lib.scala 119:74] + wire _T_2819 = _T_2818 ^ io_dma_mem_ctl_dma_mem_wdata[48]; // @[lib.scala 119:74] + wire _T_2820 = _T_2819 ^ io_dma_mem_ctl_dma_mem_wdata[49]; // @[lib.scala 119:74] + wire _T_2821 = _T_2820 ^ io_dma_mem_ctl_dma_mem_wdata[54]; // @[lib.scala 119:74] + wire _T_2822 = _T_2821 ^ io_dma_mem_ctl_dma_mem_wdata[55]; // @[lib.scala 119:74] + wire _T_2823 = _T_2822 ^ io_dma_mem_ctl_dma_mem_wdata[56]; // @[lib.scala 119:74] + wire _T_2824 = _T_2823 ^ io_dma_mem_ctl_dma_mem_wdata[57]; // @[lib.scala 119:74] + wire _T_2825 = _T_2824 ^ io_dma_mem_ctl_dma_mem_wdata[61]; // @[lib.scala 119:74] + wire _T_2826 = _T_2825 ^ io_dma_mem_ctl_dma_mem_wdata[62]; // @[lib.scala 119:74] + wire _T_2827 = _T_2826 ^ io_dma_mem_ctl_dma_mem_wdata[63]; // @[lib.scala 119:74] + wire _T_2843 = io_dma_mem_ctl_dma_mem_wdata[36] ^ io_dma_mem_ctl_dma_mem_wdata[37]; // @[lib.scala 119:74] + wire _T_2844 = _T_2843 ^ io_dma_mem_ctl_dma_mem_wdata[38]; // @[lib.scala 119:74] + wire _T_2845 = _T_2844 ^ io_dma_mem_ctl_dma_mem_wdata[39]; // @[lib.scala 119:74] + wire _T_2846 = _T_2845 ^ io_dma_mem_ctl_dma_mem_wdata[40]; // @[lib.scala 119:74] + wire _T_2847 = _T_2846 ^ io_dma_mem_ctl_dma_mem_wdata[41]; // @[lib.scala 119:74] + wire _T_2848 = _T_2847 ^ io_dma_mem_ctl_dma_mem_wdata[42]; // @[lib.scala 119:74] + wire _T_2849 = _T_2848 ^ io_dma_mem_ctl_dma_mem_wdata[50]; // @[lib.scala 119:74] + wire _T_2850 = _T_2849 ^ io_dma_mem_ctl_dma_mem_wdata[51]; // @[lib.scala 119:74] + wire _T_2851 = _T_2850 ^ io_dma_mem_ctl_dma_mem_wdata[52]; // @[lib.scala 119:74] + wire _T_2852 = _T_2851 ^ io_dma_mem_ctl_dma_mem_wdata[53]; // @[lib.scala 119:74] + wire _T_2853 = _T_2852 ^ io_dma_mem_ctl_dma_mem_wdata[54]; // @[lib.scala 119:74] + wire _T_2854 = _T_2853 ^ io_dma_mem_ctl_dma_mem_wdata[55]; // @[lib.scala 119:74] + wire _T_2855 = _T_2854 ^ io_dma_mem_ctl_dma_mem_wdata[56]; // @[lib.scala 119:74] + wire _T_2856 = _T_2855 ^ io_dma_mem_ctl_dma_mem_wdata[57]; // @[lib.scala 119:74] + wire _T_2872 = io_dma_mem_ctl_dma_mem_wdata[43] ^ io_dma_mem_ctl_dma_mem_wdata[44]; // @[lib.scala 119:74] + wire _T_2873 = _T_2872 ^ io_dma_mem_ctl_dma_mem_wdata[45]; // @[lib.scala 119:74] + wire _T_2874 = _T_2873 ^ io_dma_mem_ctl_dma_mem_wdata[46]; // @[lib.scala 119:74] + wire _T_2875 = _T_2874 ^ io_dma_mem_ctl_dma_mem_wdata[47]; // @[lib.scala 119:74] + wire _T_2876 = _T_2875 ^ io_dma_mem_ctl_dma_mem_wdata[48]; // @[lib.scala 119:74] + wire _T_2877 = _T_2876 ^ io_dma_mem_ctl_dma_mem_wdata[49]; // @[lib.scala 119:74] + wire _T_2878 = _T_2877 ^ io_dma_mem_ctl_dma_mem_wdata[50]; // @[lib.scala 119:74] + wire _T_2879 = _T_2878 ^ io_dma_mem_ctl_dma_mem_wdata[51]; // @[lib.scala 119:74] + wire _T_2880 = _T_2879 ^ io_dma_mem_ctl_dma_mem_wdata[52]; // @[lib.scala 119:74] + wire _T_2881 = _T_2880 ^ io_dma_mem_ctl_dma_mem_wdata[53]; // @[lib.scala 119:74] + wire _T_2882 = _T_2881 ^ io_dma_mem_ctl_dma_mem_wdata[54]; // @[lib.scala 119:74] + wire _T_2883 = _T_2882 ^ io_dma_mem_ctl_dma_mem_wdata[55]; // @[lib.scala 119:74] + wire _T_2884 = _T_2883 ^ io_dma_mem_ctl_dma_mem_wdata[56]; // @[lib.scala 119:74] + wire _T_2885 = _T_2884 ^ io_dma_mem_ctl_dma_mem_wdata[57]; // @[lib.scala 119:74] + wire _T_2892 = io_dma_mem_ctl_dma_mem_wdata[58] ^ io_dma_mem_ctl_dma_mem_wdata[59]; // @[lib.scala 119:74] + wire _T_2893 = _T_2892 ^ io_dma_mem_ctl_dma_mem_wdata[60]; // @[lib.scala 119:74] + wire _T_2894 = _T_2893 ^ io_dma_mem_ctl_dma_mem_wdata[61]; // @[lib.scala 119:74] + wire _T_2895 = _T_2894 ^ io_dma_mem_ctl_dma_mem_wdata[62]; // @[lib.scala 119:74] + wire _T_2896 = _T_2895 ^ io_dma_mem_ctl_dma_mem_wdata[63]; // @[lib.scala 119:74] wire [5:0] _T_2901 = {_T_2896,_T_2885,_T_2856,_T_2827,_T_2792,_T_2757}; // @[Cat.scala 29:58] - wire _T_2902 = ^io_dma_mem_ctl_dma_mem_wdata[63:32]; // @[el2_lib.scala 267:13] - wire _T_2903 = ^_T_2901; // @[el2_lib.scala 267:23] - wire _T_2904 = _T_2902 ^ _T_2903; // @[el2_lib.scala 267:18] - wire _T_2925 = io_dma_mem_ctl_dma_mem_wdata[0] ^ io_dma_mem_ctl_dma_mem_wdata[1]; // @[el2_lib.scala 259:74] - wire _T_2926 = _T_2925 ^ io_dma_mem_ctl_dma_mem_wdata[3]; // @[el2_lib.scala 259:74] - wire _T_2927 = _T_2926 ^ io_dma_mem_ctl_dma_mem_wdata[4]; // @[el2_lib.scala 259:74] - wire _T_2928 = _T_2927 ^ io_dma_mem_ctl_dma_mem_wdata[6]; // @[el2_lib.scala 259:74] - wire _T_2929 = _T_2928 ^ io_dma_mem_ctl_dma_mem_wdata[8]; // @[el2_lib.scala 259:74] - wire _T_2930 = _T_2929 ^ io_dma_mem_ctl_dma_mem_wdata[10]; // @[el2_lib.scala 259:74] - wire _T_2931 = _T_2930 ^ io_dma_mem_ctl_dma_mem_wdata[11]; // @[el2_lib.scala 259:74] - wire _T_2932 = _T_2931 ^ io_dma_mem_ctl_dma_mem_wdata[13]; // @[el2_lib.scala 259:74] - wire _T_2933 = _T_2932 ^ io_dma_mem_ctl_dma_mem_wdata[15]; // @[el2_lib.scala 259:74] - wire _T_2934 = _T_2933 ^ io_dma_mem_ctl_dma_mem_wdata[17]; // @[el2_lib.scala 259:74] - wire _T_2935 = _T_2934 ^ io_dma_mem_ctl_dma_mem_wdata[19]; // @[el2_lib.scala 259:74] - wire _T_2936 = _T_2935 ^ io_dma_mem_ctl_dma_mem_wdata[21]; // @[el2_lib.scala 259:74] - wire _T_2937 = _T_2936 ^ io_dma_mem_ctl_dma_mem_wdata[23]; // @[el2_lib.scala 259:74] - wire _T_2938 = _T_2937 ^ io_dma_mem_ctl_dma_mem_wdata[25]; // @[el2_lib.scala 259:74] - wire _T_2939 = _T_2938 ^ io_dma_mem_ctl_dma_mem_wdata[26]; // @[el2_lib.scala 259:74] - wire _T_2940 = _T_2939 ^ io_dma_mem_ctl_dma_mem_wdata[28]; // @[el2_lib.scala 259:74] - wire _T_2941 = _T_2940 ^ io_dma_mem_ctl_dma_mem_wdata[30]; // @[el2_lib.scala 259:74] - wire _T_2960 = io_dma_mem_ctl_dma_mem_wdata[0] ^ io_dma_mem_ctl_dma_mem_wdata[2]; // @[el2_lib.scala 259:74] - wire _T_2961 = _T_2960 ^ io_dma_mem_ctl_dma_mem_wdata[3]; // @[el2_lib.scala 259:74] - wire _T_2962 = _T_2961 ^ io_dma_mem_ctl_dma_mem_wdata[5]; // @[el2_lib.scala 259:74] - wire _T_2963 = _T_2962 ^ io_dma_mem_ctl_dma_mem_wdata[6]; // @[el2_lib.scala 259:74] - wire _T_2964 = _T_2963 ^ io_dma_mem_ctl_dma_mem_wdata[9]; // @[el2_lib.scala 259:74] - wire _T_2965 = _T_2964 ^ io_dma_mem_ctl_dma_mem_wdata[10]; // @[el2_lib.scala 259:74] - wire _T_2966 = _T_2965 ^ io_dma_mem_ctl_dma_mem_wdata[12]; // @[el2_lib.scala 259:74] - wire _T_2967 = _T_2966 ^ io_dma_mem_ctl_dma_mem_wdata[13]; // @[el2_lib.scala 259:74] - wire _T_2968 = _T_2967 ^ io_dma_mem_ctl_dma_mem_wdata[16]; // @[el2_lib.scala 259:74] - wire _T_2969 = _T_2968 ^ io_dma_mem_ctl_dma_mem_wdata[17]; // @[el2_lib.scala 259:74] - wire _T_2970 = _T_2969 ^ io_dma_mem_ctl_dma_mem_wdata[20]; // @[el2_lib.scala 259:74] - wire _T_2971 = _T_2970 ^ io_dma_mem_ctl_dma_mem_wdata[21]; // @[el2_lib.scala 259:74] - wire _T_2972 = _T_2971 ^ io_dma_mem_ctl_dma_mem_wdata[24]; // @[el2_lib.scala 259:74] - wire _T_2973 = _T_2972 ^ io_dma_mem_ctl_dma_mem_wdata[25]; // @[el2_lib.scala 259:74] - wire _T_2974 = _T_2973 ^ io_dma_mem_ctl_dma_mem_wdata[27]; // @[el2_lib.scala 259:74] - wire _T_2975 = _T_2974 ^ io_dma_mem_ctl_dma_mem_wdata[28]; // @[el2_lib.scala 259:74] - wire _T_2976 = _T_2975 ^ io_dma_mem_ctl_dma_mem_wdata[31]; // @[el2_lib.scala 259:74] - wire _T_2995 = io_dma_mem_ctl_dma_mem_wdata[1] ^ io_dma_mem_ctl_dma_mem_wdata[2]; // @[el2_lib.scala 259:74] - wire _T_2996 = _T_2995 ^ io_dma_mem_ctl_dma_mem_wdata[3]; // @[el2_lib.scala 259:74] - wire _T_2997 = _T_2996 ^ io_dma_mem_ctl_dma_mem_wdata[7]; // @[el2_lib.scala 259:74] - wire _T_2998 = _T_2997 ^ io_dma_mem_ctl_dma_mem_wdata[8]; // @[el2_lib.scala 259:74] - wire _T_2999 = _T_2998 ^ io_dma_mem_ctl_dma_mem_wdata[9]; // @[el2_lib.scala 259:74] - wire _T_3000 = _T_2999 ^ io_dma_mem_ctl_dma_mem_wdata[10]; // @[el2_lib.scala 259:74] - wire _T_3001 = _T_3000 ^ io_dma_mem_ctl_dma_mem_wdata[14]; // @[el2_lib.scala 259:74] - wire _T_3002 = _T_3001 ^ io_dma_mem_ctl_dma_mem_wdata[15]; // @[el2_lib.scala 259:74] - wire _T_3003 = _T_3002 ^ io_dma_mem_ctl_dma_mem_wdata[16]; // @[el2_lib.scala 259:74] - wire _T_3004 = _T_3003 ^ io_dma_mem_ctl_dma_mem_wdata[17]; // @[el2_lib.scala 259:74] - wire _T_3005 = _T_3004 ^ io_dma_mem_ctl_dma_mem_wdata[22]; // @[el2_lib.scala 259:74] - wire _T_3006 = _T_3005 ^ io_dma_mem_ctl_dma_mem_wdata[23]; // @[el2_lib.scala 259:74] - wire _T_3007 = _T_3006 ^ io_dma_mem_ctl_dma_mem_wdata[24]; // @[el2_lib.scala 259:74] - wire _T_3008 = _T_3007 ^ io_dma_mem_ctl_dma_mem_wdata[25]; // @[el2_lib.scala 259:74] - wire _T_3009 = _T_3008 ^ io_dma_mem_ctl_dma_mem_wdata[29]; // @[el2_lib.scala 259:74] - wire _T_3010 = _T_3009 ^ io_dma_mem_ctl_dma_mem_wdata[30]; // @[el2_lib.scala 259:74] - wire _T_3011 = _T_3010 ^ io_dma_mem_ctl_dma_mem_wdata[31]; // @[el2_lib.scala 259:74] - wire _T_3027 = io_dma_mem_ctl_dma_mem_wdata[4] ^ io_dma_mem_ctl_dma_mem_wdata[5]; // @[el2_lib.scala 259:74] - wire _T_3028 = _T_3027 ^ io_dma_mem_ctl_dma_mem_wdata[6]; // @[el2_lib.scala 259:74] - wire _T_3029 = _T_3028 ^ io_dma_mem_ctl_dma_mem_wdata[7]; // @[el2_lib.scala 259:74] - wire _T_3030 = _T_3029 ^ io_dma_mem_ctl_dma_mem_wdata[8]; // @[el2_lib.scala 259:74] - wire _T_3031 = _T_3030 ^ io_dma_mem_ctl_dma_mem_wdata[9]; // @[el2_lib.scala 259:74] - wire _T_3032 = _T_3031 ^ io_dma_mem_ctl_dma_mem_wdata[10]; // @[el2_lib.scala 259:74] - wire _T_3033 = _T_3032 ^ io_dma_mem_ctl_dma_mem_wdata[18]; // @[el2_lib.scala 259:74] - wire _T_3034 = _T_3033 ^ io_dma_mem_ctl_dma_mem_wdata[19]; // @[el2_lib.scala 259:74] - wire _T_3035 = _T_3034 ^ io_dma_mem_ctl_dma_mem_wdata[20]; // @[el2_lib.scala 259:74] - wire _T_3036 = _T_3035 ^ io_dma_mem_ctl_dma_mem_wdata[21]; // @[el2_lib.scala 259:74] - wire _T_3037 = _T_3036 ^ io_dma_mem_ctl_dma_mem_wdata[22]; // @[el2_lib.scala 259:74] - wire _T_3038 = _T_3037 ^ io_dma_mem_ctl_dma_mem_wdata[23]; // @[el2_lib.scala 259:74] - wire _T_3039 = _T_3038 ^ io_dma_mem_ctl_dma_mem_wdata[24]; // @[el2_lib.scala 259:74] - wire _T_3040 = _T_3039 ^ io_dma_mem_ctl_dma_mem_wdata[25]; // @[el2_lib.scala 259:74] - wire _T_3056 = io_dma_mem_ctl_dma_mem_wdata[11] ^ io_dma_mem_ctl_dma_mem_wdata[12]; // @[el2_lib.scala 259:74] - wire _T_3057 = _T_3056 ^ io_dma_mem_ctl_dma_mem_wdata[13]; // @[el2_lib.scala 259:74] - wire _T_3058 = _T_3057 ^ io_dma_mem_ctl_dma_mem_wdata[14]; // @[el2_lib.scala 259:74] - wire _T_3059 = _T_3058 ^ io_dma_mem_ctl_dma_mem_wdata[15]; // @[el2_lib.scala 259:74] - wire _T_3060 = _T_3059 ^ io_dma_mem_ctl_dma_mem_wdata[16]; // @[el2_lib.scala 259:74] - wire _T_3061 = _T_3060 ^ io_dma_mem_ctl_dma_mem_wdata[17]; // @[el2_lib.scala 259:74] - wire _T_3062 = _T_3061 ^ io_dma_mem_ctl_dma_mem_wdata[18]; // @[el2_lib.scala 259:74] - wire _T_3063 = _T_3062 ^ io_dma_mem_ctl_dma_mem_wdata[19]; // @[el2_lib.scala 259:74] - wire _T_3064 = _T_3063 ^ io_dma_mem_ctl_dma_mem_wdata[20]; // @[el2_lib.scala 259:74] - wire _T_3065 = _T_3064 ^ io_dma_mem_ctl_dma_mem_wdata[21]; // @[el2_lib.scala 259:74] - wire _T_3066 = _T_3065 ^ io_dma_mem_ctl_dma_mem_wdata[22]; // @[el2_lib.scala 259:74] - wire _T_3067 = _T_3066 ^ io_dma_mem_ctl_dma_mem_wdata[23]; // @[el2_lib.scala 259:74] - wire _T_3068 = _T_3067 ^ io_dma_mem_ctl_dma_mem_wdata[24]; // @[el2_lib.scala 259:74] - wire _T_3069 = _T_3068 ^ io_dma_mem_ctl_dma_mem_wdata[25]; // @[el2_lib.scala 259:74] - wire _T_3076 = io_dma_mem_ctl_dma_mem_wdata[26] ^ io_dma_mem_ctl_dma_mem_wdata[27]; // @[el2_lib.scala 259:74] - wire _T_3077 = _T_3076 ^ io_dma_mem_ctl_dma_mem_wdata[28]; // @[el2_lib.scala 259:74] - wire _T_3078 = _T_3077 ^ io_dma_mem_ctl_dma_mem_wdata[29]; // @[el2_lib.scala 259:74] - wire _T_3079 = _T_3078 ^ io_dma_mem_ctl_dma_mem_wdata[30]; // @[el2_lib.scala 259:74] - wire _T_3080 = _T_3079 ^ io_dma_mem_ctl_dma_mem_wdata[31]; // @[el2_lib.scala 259:74] + wire _T_2902 = ^io_dma_mem_ctl_dma_mem_wdata[63:32]; // @[lib.scala 127:13] + wire _T_2903 = ^_T_2901; // @[lib.scala 127:23] + wire _T_2904 = _T_2902 ^ _T_2903; // @[lib.scala 127:18] + wire _T_2925 = io_dma_mem_ctl_dma_mem_wdata[0] ^ io_dma_mem_ctl_dma_mem_wdata[1]; // @[lib.scala 119:74] + wire _T_2926 = _T_2925 ^ io_dma_mem_ctl_dma_mem_wdata[3]; // @[lib.scala 119:74] + wire _T_2927 = _T_2926 ^ io_dma_mem_ctl_dma_mem_wdata[4]; // @[lib.scala 119:74] + wire _T_2928 = _T_2927 ^ io_dma_mem_ctl_dma_mem_wdata[6]; // @[lib.scala 119:74] + wire _T_2929 = _T_2928 ^ io_dma_mem_ctl_dma_mem_wdata[8]; // @[lib.scala 119:74] + wire _T_2930 = _T_2929 ^ io_dma_mem_ctl_dma_mem_wdata[10]; // @[lib.scala 119:74] + wire _T_2931 = _T_2930 ^ io_dma_mem_ctl_dma_mem_wdata[11]; // @[lib.scala 119:74] + wire _T_2932 = _T_2931 ^ io_dma_mem_ctl_dma_mem_wdata[13]; // @[lib.scala 119:74] + wire _T_2933 = _T_2932 ^ io_dma_mem_ctl_dma_mem_wdata[15]; // @[lib.scala 119:74] + wire _T_2934 = _T_2933 ^ io_dma_mem_ctl_dma_mem_wdata[17]; // @[lib.scala 119:74] + wire _T_2935 = _T_2934 ^ io_dma_mem_ctl_dma_mem_wdata[19]; // @[lib.scala 119:74] + wire _T_2936 = _T_2935 ^ io_dma_mem_ctl_dma_mem_wdata[21]; // @[lib.scala 119:74] + wire _T_2937 = _T_2936 ^ io_dma_mem_ctl_dma_mem_wdata[23]; // @[lib.scala 119:74] + wire _T_2938 = _T_2937 ^ io_dma_mem_ctl_dma_mem_wdata[25]; // @[lib.scala 119:74] + wire _T_2939 = _T_2938 ^ io_dma_mem_ctl_dma_mem_wdata[26]; // @[lib.scala 119:74] + wire _T_2940 = _T_2939 ^ io_dma_mem_ctl_dma_mem_wdata[28]; // @[lib.scala 119:74] + wire _T_2941 = _T_2940 ^ io_dma_mem_ctl_dma_mem_wdata[30]; // @[lib.scala 119:74] + wire _T_2960 = io_dma_mem_ctl_dma_mem_wdata[0] ^ io_dma_mem_ctl_dma_mem_wdata[2]; // @[lib.scala 119:74] + wire _T_2961 = _T_2960 ^ io_dma_mem_ctl_dma_mem_wdata[3]; // @[lib.scala 119:74] + wire _T_2962 = _T_2961 ^ io_dma_mem_ctl_dma_mem_wdata[5]; // @[lib.scala 119:74] + wire _T_2963 = _T_2962 ^ io_dma_mem_ctl_dma_mem_wdata[6]; // @[lib.scala 119:74] + wire _T_2964 = _T_2963 ^ io_dma_mem_ctl_dma_mem_wdata[9]; // @[lib.scala 119:74] + wire _T_2965 = _T_2964 ^ io_dma_mem_ctl_dma_mem_wdata[10]; // @[lib.scala 119:74] + wire _T_2966 = _T_2965 ^ io_dma_mem_ctl_dma_mem_wdata[12]; // @[lib.scala 119:74] + wire _T_2967 = _T_2966 ^ io_dma_mem_ctl_dma_mem_wdata[13]; // @[lib.scala 119:74] + wire _T_2968 = _T_2967 ^ io_dma_mem_ctl_dma_mem_wdata[16]; // @[lib.scala 119:74] + wire _T_2969 = _T_2968 ^ io_dma_mem_ctl_dma_mem_wdata[17]; // @[lib.scala 119:74] + wire _T_2970 = _T_2969 ^ io_dma_mem_ctl_dma_mem_wdata[20]; // @[lib.scala 119:74] + wire _T_2971 = _T_2970 ^ io_dma_mem_ctl_dma_mem_wdata[21]; // @[lib.scala 119:74] + wire _T_2972 = _T_2971 ^ io_dma_mem_ctl_dma_mem_wdata[24]; // @[lib.scala 119:74] + wire _T_2973 = _T_2972 ^ io_dma_mem_ctl_dma_mem_wdata[25]; // @[lib.scala 119:74] + wire _T_2974 = _T_2973 ^ io_dma_mem_ctl_dma_mem_wdata[27]; // @[lib.scala 119:74] + wire _T_2975 = _T_2974 ^ io_dma_mem_ctl_dma_mem_wdata[28]; // @[lib.scala 119:74] + wire _T_2976 = _T_2975 ^ io_dma_mem_ctl_dma_mem_wdata[31]; // @[lib.scala 119:74] + wire _T_2995 = io_dma_mem_ctl_dma_mem_wdata[1] ^ io_dma_mem_ctl_dma_mem_wdata[2]; // @[lib.scala 119:74] + wire _T_2996 = _T_2995 ^ io_dma_mem_ctl_dma_mem_wdata[3]; // @[lib.scala 119:74] + wire _T_2997 = _T_2996 ^ io_dma_mem_ctl_dma_mem_wdata[7]; // @[lib.scala 119:74] + wire _T_2998 = _T_2997 ^ io_dma_mem_ctl_dma_mem_wdata[8]; // @[lib.scala 119:74] + wire _T_2999 = _T_2998 ^ io_dma_mem_ctl_dma_mem_wdata[9]; // @[lib.scala 119:74] + wire _T_3000 = _T_2999 ^ io_dma_mem_ctl_dma_mem_wdata[10]; // @[lib.scala 119:74] + wire _T_3001 = _T_3000 ^ io_dma_mem_ctl_dma_mem_wdata[14]; // @[lib.scala 119:74] + wire _T_3002 = _T_3001 ^ io_dma_mem_ctl_dma_mem_wdata[15]; // @[lib.scala 119:74] + wire _T_3003 = _T_3002 ^ io_dma_mem_ctl_dma_mem_wdata[16]; // @[lib.scala 119:74] + wire _T_3004 = _T_3003 ^ io_dma_mem_ctl_dma_mem_wdata[17]; // @[lib.scala 119:74] + wire _T_3005 = _T_3004 ^ io_dma_mem_ctl_dma_mem_wdata[22]; // @[lib.scala 119:74] + wire _T_3006 = _T_3005 ^ io_dma_mem_ctl_dma_mem_wdata[23]; // @[lib.scala 119:74] + wire _T_3007 = _T_3006 ^ io_dma_mem_ctl_dma_mem_wdata[24]; // @[lib.scala 119:74] + wire _T_3008 = _T_3007 ^ io_dma_mem_ctl_dma_mem_wdata[25]; // @[lib.scala 119:74] + wire _T_3009 = _T_3008 ^ io_dma_mem_ctl_dma_mem_wdata[29]; // @[lib.scala 119:74] + wire _T_3010 = _T_3009 ^ io_dma_mem_ctl_dma_mem_wdata[30]; // @[lib.scala 119:74] + wire _T_3011 = _T_3010 ^ io_dma_mem_ctl_dma_mem_wdata[31]; // @[lib.scala 119:74] + wire _T_3027 = io_dma_mem_ctl_dma_mem_wdata[4] ^ io_dma_mem_ctl_dma_mem_wdata[5]; // @[lib.scala 119:74] + wire _T_3028 = _T_3027 ^ io_dma_mem_ctl_dma_mem_wdata[6]; // @[lib.scala 119:74] + wire _T_3029 = _T_3028 ^ io_dma_mem_ctl_dma_mem_wdata[7]; // @[lib.scala 119:74] + wire _T_3030 = _T_3029 ^ io_dma_mem_ctl_dma_mem_wdata[8]; // @[lib.scala 119:74] + wire _T_3031 = _T_3030 ^ io_dma_mem_ctl_dma_mem_wdata[9]; // @[lib.scala 119:74] + wire _T_3032 = _T_3031 ^ io_dma_mem_ctl_dma_mem_wdata[10]; // @[lib.scala 119:74] + wire _T_3033 = _T_3032 ^ io_dma_mem_ctl_dma_mem_wdata[18]; // @[lib.scala 119:74] + wire _T_3034 = _T_3033 ^ io_dma_mem_ctl_dma_mem_wdata[19]; // @[lib.scala 119:74] + wire _T_3035 = _T_3034 ^ io_dma_mem_ctl_dma_mem_wdata[20]; // @[lib.scala 119:74] + wire _T_3036 = _T_3035 ^ io_dma_mem_ctl_dma_mem_wdata[21]; // @[lib.scala 119:74] + wire _T_3037 = _T_3036 ^ io_dma_mem_ctl_dma_mem_wdata[22]; // @[lib.scala 119:74] + wire _T_3038 = _T_3037 ^ io_dma_mem_ctl_dma_mem_wdata[23]; // @[lib.scala 119:74] + wire _T_3039 = _T_3038 ^ io_dma_mem_ctl_dma_mem_wdata[24]; // @[lib.scala 119:74] + wire _T_3040 = _T_3039 ^ io_dma_mem_ctl_dma_mem_wdata[25]; // @[lib.scala 119:74] + wire _T_3056 = io_dma_mem_ctl_dma_mem_wdata[11] ^ io_dma_mem_ctl_dma_mem_wdata[12]; // @[lib.scala 119:74] + wire _T_3057 = _T_3056 ^ io_dma_mem_ctl_dma_mem_wdata[13]; // @[lib.scala 119:74] + wire _T_3058 = _T_3057 ^ io_dma_mem_ctl_dma_mem_wdata[14]; // @[lib.scala 119:74] + wire _T_3059 = _T_3058 ^ io_dma_mem_ctl_dma_mem_wdata[15]; // @[lib.scala 119:74] + wire _T_3060 = _T_3059 ^ io_dma_mem_ctl_dma_mem_wdata[16]; // @[lib.scala 119:74] + wire _T_3061 = _T_3060 ^ io_dma_mem_ctl_dma_mem_wdata[17]; // @[lib.scala 119:74] + wire _T_3062 = _T_3061 ^ io_dma_mem_ctl_dma_mem_wdata[18]; // @[lib.scala 119:74] + wire _T_3063 = _T_3062 ^ io_dma_mem_ctl_dma_mem_wdata[19]; // @[lib.scala 119:74] + wire _T_3064 = _T_3063 ^ io_dma_mem_ctl_dma_mem_wdata[20]; // @[lib.scala 119:74] + wire _T_3065 = _T_3064 ^ io_dma_mem_ctl_dma_mem_wdata[21]; // @[lib.scala 119:74] + wire _T_3066 = _T_3065 ^ io_dma_mem_ctl_dma_mem_wdata[22]; // @[lib.scala 119:74] + wire _T_3067 = _T_3066 ^ io_dma_mem_ctl_dma_mem_wdata[23]; // @[lib.scala 119:74] + wire _T_3068 = _T_3067 ^ io_dma_mem_ctl_dma_mem_wdata[24]; // @[lib.scala 119:74] + wire _T_3069 = _T_3068 ^ io_dma_mem_ctl_dma_mem_wdata[25]; // @[lib.scala 119:74] + wire _T_3076 = io_dma_mem_ctl_dma_mem_wdata[26] ^ io_dma_mem_ctl_dma_mem_wdata[27]; // @[lib.scala 119:74] + wire _T_3077 = _T_3076 ^ io_dma_mem_ctl_dma_mem_wdata[28]; // @[lib.scala 119:74] + wire _T_3078 = _T_3077 ^ io_dma_mem_ctl_dma_mem_wdata[29]; // @[lib.scala 119:74] + wire _T_3079 = _T_3078 ^ io_dma_mem_ctl_dma_mem_wdata[30]; // @[lib.scala 119:74] + wire _T_3080 = _T_3079 ^ io_dma_mem_ctl_dma_mem_wdata[31]; // @[lib.scala 119:74] wire [5:0] _T_3085 = {_T_3080,_T_3069,_T_3040,_T_3011,_T_2976,_T_2941}; // @[Cat.scala 29:58] - wire _T_3086 = ^io_dma_mem_ctl_dma_mem_wdata[31:0]; // @[el2_lib.scala 267:13] - wire _T_3087 = ^_T_3085; // @[el2_lib.scala 267:23] - wire _T_3088 = _T_3086 ^ _T_3087; // @[el2_lib.scala 267:18] + wire _T_3086 = ^io_dma_mem_ctl_dma_mem_wdata[31:0]; // @[lib.scala 127:13] + wire _T_3087 = ^_T_3085; // @[lib.scala 127:23] + wire _T_3088 = _T_3086 ^ _T_3087; // @[lib.scala 127:18] wire [6:0] _T_3089 = {_T_3088,_T_3080,_T_3069,_T_3040,_T_3011,_T_2976,_T_2941}; // @[Cat.scala 29:58] wire [13:0] dma_mem_ecc = {_T_2904,_T_2896,_T_2885,_T_2856,_T_2827,_T_2792,_T_2757,_T_3089}; // @[Cat.scala 29:58] wire _T_3091 = ~_T_2709; // @[ifu_mem_ctl.scala 576:45] @@ -3639,109 +3639,109 @@ module ifu_mem_ctl( wire [77:0] _T_3093 = {iccm_ecc_corr_data_ff,iccm_ecc_corr_data_ff}; // @[Cat.scala 29:58] wire [77:0] _T_3100 = {dma_mem_ecc[13:7],io_dma_mem_ctl_dma_mem_wdata[63:32],dma_mem_ecc[6:0],io_dma_mem_ctl_dma_mem_wdata[31:0]}; // @[Cat.scala 29:58] reg [1:0] dma_mem_addr_ff; // @[ifu_mem_ctl.scala 590:53] - wire _T_3435 = _T_3347[5:0] == 6'h27; // @[el2_lib.scala 339:41] - wire _T_3433 = _T_3347[5:0] == 6'h26; // @[el2_lib.scala 339:41] - wire _T_3431 = _T_3347[5:0] == 6'h25; // @[el2_lib.scala 339:41] - wire _T_3429 = _T_3347[5:0] == 6'h24; // @[el2_lib.scala 339:41] - wire _T_3427 = _T_3347[5:0] == 6'h23; // @[el2_lib.scala 339:41] - wire _T_3425 = _T_3347[5:0] == 6'h22; // @[el2_lib.scala 339:41] - wire _T_3423 = _T_3347[5:0] == 6'h21; // @[el2_lib.scala 339:41] - wire _T_3421 = _T_3347[5:0] == 6'h20; // @[el2_lib.scala 339:41] - wire _T_3419 = _T_3347[5:0] == 6'h1f; // @[el2_lib.scala 339:41] - wire _T_3417 = _T_3347[5:0] == 6'h1e; // @[el2_lib.scala 339:41] - wire [9:0] _T_3493 = {_T_3435,_T_3433,_T_3431,_T_3429,_T_3427,_T_3425,_T_3423,_T_3421,_T_3419,_T_3417}; // @[el2_lib.scala 342:69] - wire _T_3415 = _T_3347[5:0] == 6'h1d; // @[el2_lib.scala 339:41] - wire _T_3413 = _T_3347[5:0] == 6'h1c; // @[el2_lib.scala 339:41] - wire _T_3411 = _T_3347[5:0] == 6'h1b; // @[el2_lib.scala 339:41] - wire _T_3409 = _T_3347[5:0] == 6'h1a; // @[el2_lib.scala 339:41] - wire _T_3407 = _T_3347[5:0] == 6'h19; // @[el2_lib.scala 339:41] - wire _T_3405 = _T_3347[5:0] == 6'h18; // @[el2_lib.scala 339:41] - wire _T_3403 = _T_3347[5:0] == 6'h17; // @[el2_lib.scala 339:41] - wire _T_3401 = _T_3347[5:0] == 6'h16; // @[el2_lib.scala 339:41] - wire _T_3399 = _T_3347[5:0] == 6'h15; // @[el2_lib.scala 339:41] - wire _T_3397 = _T_3347[5:0] == 6'h14; // @[el2_lib.scala 339:41] - wire [9:0] _T_3484 = {_T_3415,_T_3413,_T_3411,_T_3409,_T_3407,_T_3405,_T_3403,_T_3401,_T_3399,_T_3397}; // @[el2_lib.scala 342:69] - wire _T_3395 = _T_3347[5:0] == 6'h13; // @[el2_lib.scala 339:41] - wire _T_3393 = _T_3347[5:0] == 6'h12; // @[el2_lib.scala 339:41] - wire _T_3391 = _T_3347[5:0] == 6'h11; // @[el2_lib.scala 339:41] - wire _T_3389 = _T_3347[5:0] == 6'h10; // @[el2_lib.scala 339:41] - wire _T_3387 = _T_3347[5:0] == 6'hf; // @[el2_lib.scala 339:41] - wire _T_3385 = _T_3347[5:0] == 6'he; // @[el2_lib.scala 339:41] - wire _T_3383 = _T_3347[5:0] == 6'hd; // @[el2_lib.scala 339:41] - wire _T_3381 = _T_3347[5:0] == 6'hc; // @[el2_lib.scala 339:41] - wire _T_3379 = _T_3347[5:0] == 6'hb; // @[el2_lib.scala 339:41] - wire _T_3377 = _T_3347[5:0] == 6'ha; // @[el2_lib.scala 339:41] - wire [9:0] _T_3474 = {_T_3395,_T_3393,_T_3391,_T_3389,_T_3387,_T_3385,_T_3383,_T_3381,_T_3379,_T_3377}; // @[el2_lib.scala 342:69] - wire _T_3375 = _T_3347[5:0] == 6'h9; // @[el2_lib.scala 339:41] - wire _T_3373 = _T_3347[5:0] == 6'h8; // @[el2_lib.scala 339:41] - wire _T_3371 = _T_3347[5:0] == 6'h7; // @[el2_lib.scala 339:41] - wire _T_3369 = _T_3347[5:0] == 6'h6; // @[el2_lib.scala 339:41] - wire _T_3367 = _T_3347[5:0] == 6'h5; // @[el2_lib.scala 339:41] - wire _T_3365 = _T_3347[5:0] == 6'h4; // @[el2_lib.scala 339:41] - wire _T_3363 = _T_3347[5:0] == 6'h3; // @[el2_lib.scala 339:41] - wire _T_3361 = _T_3347[5:0] == 6'h2; // @[el2_lib.scala 339:41] - wire _T_3359 = _T_3347[5:0] == 6'h1; // @[el2_lib.scala 339:41] - wire [18:0] _T_3475 = {_T_3474,_T_3375,_T_3373,_T_3371,_T_3369,_T_3367,_T_3365,_T_3363,_T_3361,_T_3359}; // @[el2_lib.scala 342:69] - wire [38:0] _T_3495 = {_T_3493,_T_3484,_T_3475}; // @[el2_lib.scala 342:69] + wire _T_3435 = _T_3347[5:0] == 6'h27; // @[lib.scala 199:41] + wire _T_3433 = _T_3347[5:0] == 6'h26; // @[lib.scala 199:41] + wire _T_3431 = _T_3347[5:0] == 6'h25; // @[lib.scala 199:41] + wire _T_3429 = _T_3347[5:0] == 6'h24; // @[lib.scala 199:41] + wire _T_3427 = _T_3347[5:0] == 6'h23; // @[lib.scala 199:41] + wire _T_3425 = _T_3347[5:0] == 6'h22; // @[lib.scala 199:41] + wire _T_3423 = _T_3347[5:0] == 6'h21; // @[lib.scala 199:41] + wire _T_3421 = _T_3347[5:0] == 6'h20; // @[lib.scala 199:41] + wire _T_3419 = _T_3347[5:0] == 6'h1f; // @[lib.scala 199:41] + wire _T_3417 = _T_3347[5:0] == 6'h1e; // @[lib.scala 199:41] + wire [9:0] _T_3493 = {_T_3435,_T_3433,_T_3431,_T_3429,_T_3427,_T_3425,_T_3423,_T_3421,_T_3419,_T_3417}; // @[lib.scala 202:69] + wire _T_3415 = _T_3347[5:0] == 6'h1d; // @[lib.scala 199:41] + wire _T_3413 = _T_3347[5:0] == 6'h1c; // @[lib.scala 199:41] + wire _T_3411 = _T_3347[5:0] == 6'h1b; // @[lib.scala 199:41] + wire _T_3409 = _T_3347[5:0] == 6'h1a; // @[lib.scala 199:41] + wire _T_3407 = _T_3347[5:0] == 6'h19; // @[lib.scala 199:41] + wire _T_3405 = _T_3347[5:0] == 6'h18; // @[lib.scala 199:41] + wire _T_3403 = _T_3347[5:0] == 6'h17; // @[lib.scala 199:41] + wire _T_3401 = _T_3347[5:0] == 6'h16; // @[lib.scala 199:41] + wire _T_3399 = _T_3347[5:0] == 6'h15; // @[lib.scala 199:41] + wire _T_3397 = _T_3347[5:0] == 6'h14; // @[lib.scala 199:41] + wire [9:0] _T_3484 = {_T_3415,_T_3413,_T_3411,_T_3409,_T_3407,_T_3405,_T_3403,_T_3401,_T_3399,_T_3397}; // @[lib.scala 202:69] + wire _T_3395 = _T_3347[5:0] == 6'h13; // @[lib.scala 199:41] + wire _T_3393 = _T_3347[5:0] == 6'h12; // @[lib.scala 199:41] + wire _T_3391 = _T_3347[5:0] == 6'h11; // @[lib.scala 199:41] + wire _T_3389 = _T_3347[5:0] == 6'h10; // @[lib.scala 199:41] + wire _T_3387 = _T_3347[5:0] == 6'hf; // @[lib.scala 199:41] + wire _T_3385 = _T_3347[5:0] == 6'he; // @[lib.scala 199:41] + wire _T_3383 = _T_3347[5:0] == 6'hd; // @[lib.scala 199:41] + wire _T_3381 = _T_3347[5:0] == 6'hc; // @[lib.scala 199:41] + wire _T_3379 = _T_3347[5:0] == 6'hb; // @[lib.scala 199:41] + wire _T_3377 = _T_3347[5:0] == 6'ha; // @[lib.scala 199:41] + wire [9:0] _T_3474 = {_T_3395,_T_3393,_T_3391,_T_3389,_T_3387,_T_3385,_T_3383,_T_3381,_T_3379,_T_3377}; // @[lib.scala 202:69] + wire _T_3375 = _T_3347[5:0] == 6'h9; // @[lib.scala 199:41] + wire _T_3373 = _T_3347[5:0] == 6'h8; // @[lib.scala 199:41] + wire _T_3371 = _T_3347[5:0] == 6'h7; // @[lib.scala 199:41] + wire _T_3369 = _T_3347[5:0] == 6'h6; // @[lib.scala 199:41] + wire _T_3367 = _T_3347[5:0] == 6'h5; // @[lib.scala 199:41] + wire _T_3365 = _T_3347[5:0] == 6'h4; // @[lib.scala 199:41] + wire _T_3363 = _T_3347[5:0] == 6'h3; // @[lib.scala 199:41] + wire _T_3361 = _T_3347[5:0] == 6'h2; // @[lib.scala 199:41] + wire _T_3359 = _T_3347[5:0] == 6'h1; // @[lib.scala 199:41] + wire [18:0] _T_3475 = {_T_3474,_T_3375,_T_3373,_T_3371,_T_3369,_T_3367,_T_3365,_T_3363,_T_3361,_T_3359}; // @[lib.scala 202:69] + wire [38:0] _T_3495 = {_T_3493,_T_3484,_T_3475}; // @[lib.scala 202:69] wire [7:0] _T_3450 = {io_iccm_rd_data_ecc[35],io_iccm_rd_data_ecc[3:1],io_iccm_rd_data_ecc[34],io_iccm_rd_data_ecc[0],io_iccm_rd_data_ecc[33:32]}; // @[Cat.scala 29:58] wire [38:0] _T_3456 = {io_iccm_rd_data_ecc[38],io_iccm_rd_data_ecc[31:26],io_iccm_rd_data_ecc[37],io_iccm_rd_data_ecc[25:11],io_iccm_rd_data_ecc[36],io_iccm_rd_data_ecc[10:4],_T_3450}; // @[Cat.scala 29:58] - wire [38:0] _T_3496 = _T_3495 ^ _T_3456; // @[el2_lib.scala 342:76] - wire [38:0] _T_3497 = _T_3351 ? _T_3496 : _T_3456; // @[el2_lib.scala 342:31] + wire [38:0] _T_3496 = _T_3495 ^ _T_3456; // @[lib.scala 202:76] + wire [38:0] _T_3497 = _T_3351 ? _T_3496 : _T_3456; // @[lib.scala 202:31] wire [31:0] iccm_corrected_data_0 = {_T_3497[37:32],_T_3497[30:16],_T_3497[14:8],_T_3497[6:4],_T_3497[2]}; // @[Cat.scala 29:58] - wire _T_3820 = _T_3732[5:0] == 6'h27; // @[el2_lib.scala 339:41] - wire _T_3818 = _T_3732[5:0] == 6'h26; // @[el2_lib.scala 339:41] - wire _T_3816 = _T_3732[5:0] == 6'h25; // @[el2_lib.scala 339:41] - wire _T_3814 = _T_3732[5:0] == 6'h24; // @[el2_lib.scala 339:41] - wire _T_3812 = _T_3732[5:0] == 6'h23; // @[el2_lib.scala 339:41] - wire _T_3810 = _T_3732[5:0] == 6'h22; // @[el2_lib.scala 339:41] - wire _T_3808 = _T_3732[5:0] == 6'h21; // @[el2_lib.scala 339:41] - wire _T_3806 = _T_3732[5:0] == 6'h20; // @[el2_lib.scala 339:41] - wire _T_3804 = _T_3732[5:0] == 6'h1f; // @[el2_lib.scala 339:41] - wire _T_3802 = _T_3732[5:0] == 6'h1e; // @[el2_lib.scala 339:41] - wire [9:0] _T_3878 = {_T_3820,_T_3818,_T_3816,_T_3814,_T_3812,_T_3810,_T_3808,_T_3806,_T_3804,_T_3802}; // @[el2_lib.scala 342:69] - wire _T_3800 = _T_3732[5:0] == 6'h1d; // @[el2_lib.scala 339:41] - wire _T_3798 = _T_3732[5:0] == 6'h1c; // @[el2_lib.scala 339:41] - wire _T_3796 = _T_3732[5:0] == 6'h1b; // @[el2_lib.scala 339:41] - wire _T_3794 = _T_3732[5:0] == 6'h1a; // @[el2_lib.scala 339:41] - wire _T_3792 = _T_3732[5:0] == 6'h19; // @[el2_lib.scala 339:41] - wire _T_3790 = _T_3732[5:0] == 6'h18; // @[el2_lib.scala 339:41] - wire _T_3788 = _T_3732[5:0] == 6'h17; // @[el2_lib.scala 339:41] - wire _T_3786 = _T_3732[5:0] == 6'h16; // @[el2_lib.scala 339:41] - wire _T_3784 = _T_3732[5:0] == 6'h15; // @[el2_lib.scala 339:41] - wire _T_3782 = _T_3732[5:0] == 6'h14; // @[el2_lib.scala 339:41] - wire [9:0] _T_3869 = {_T_3800,_T_3798,_T_3796,_T_3794,_T_3792,_T_3790,_T_3788,_T_3786,_T_3784,_T_3782}; // @[el2_lib.scala 342:69] - wire _T_3780 = _T_3732[5:0] == 6'h13; // @[el2_lib.scala 339:41] - wire _T_3778 = _T_3732[5:0] == 6'h12; // @[el2_lib.scala 339:41] - wire _T_3776 = _T_3732[5:0] == 6'h11; // @[el2_lib.scala 339:41] - wire _T_3774 = _T_3732[5:0] == 6'h10; // @[el2_lib.scala 339:41] - wire _T_3772 = _T_3732[5:0] == 6'hf; // @[el2_lib.scala 339:41] - wire _T_3770 = _T_3732[5:0] == 6'he; // @[el2_lib.scala 339:41] - wire _T_3768 = _T_3732[5:0] == 6'hd; // @[el2_lib.scala 339:41] - wire _T_3766 = _T_3732[5:0] == 6'hc; // @[el2_lib.scala 339:41] - wire _T_3764 = _T_3732[5:0] == 6'hb; // @[el2_lib.scala 339:41] - wire _T_3762 = _T_3732[5:0] == 6'ha; // @[el2_lib.scala 339:41] - wire [9:0] _T_3859 = {_T_3780,_T_3778,_T_3776,_T_3774,_T_3772,_T_3770,_T_3768,_T_3766,_T_3764,_T_3762}; // @[el2_lib.scala 342:69] - wire _T_3760 = _T_3732[5:0] == 6'h9; // @[el2_lib.scala 339:41] - wire _T_3758 = _T_3732[5:0] == 6'h8; // @[el2_lib.scala 339:41] - wire _T_3756 = _T_3732[5:0] == 6'h7; // @[el2_lib.scala 339:41] - wire _T_3754 = _T_3732[5:0] == 6'h6; // @[el2_lib.scala 339:41] - wire _T_3752 = _T_3732[5:0] == 6'h5; // @[el2_lib.scala 339:41] - wire _T_3750 = _T_3732[5:0] == 6'h4; // @[el2_lib.scala 339:41] - wire _T_3748 = _T_3732[5:0] == 6'h3; // @[el2_lib.scala 339:41] - wire _T_3746 = _T_3732[5:0] == 6'h2; // @[el2_lib.scala 339:41] - wire _T_3744 = _T_3732[5:0] == 6'h1; // @[el2_lib.scala 339:41] - wire [18:0] _T_3860 = {_T_3859,_T_3760,_T_3758,_T_3756,_T_3754,_T_3752,_T_3750,_T_3748,_T_3746,_T_3744}; // @[el2_lib.scala 342:69] - wire [38:0] _T_3880 = {_T_3878,_T_3869,_T_3860}; // @[el2_lib.scala 342:69] + wire _T_3820 = _T_3732[5:0] == 6'h27; // @[lib.scala 199:41] + wire _T_3818 = _T_3732[5:0] == 6'h26; // @[lib.scala 199:41] + wire _T_3816 = _T_3732[5:0] == 6'h25; // @[lib.scala 199:41] + wire _T_3814 = _T_3732[5:0] == 6'h24; // @[lib.scala 199:41] + wire _T_3812 = _T_3732[5:0] == 6'h23; // @[lib.scala 199:41] + wire _T_3810 = _T_3732[5:0] == 6'h22; // @[lib.scala 199:41] + wire _T_3808 = _T_3732[5:0] == 6'h21; // @[lib.scala 199:41] + wire _T_3806 = _T_3732[5:0] == 6'h20; // @[lib.scala 199:41] + wire _T_3804 = _T_3732[5:0] == 6'h1f; // @[lib.scala 199:41] + wire _T_3802 = _T_3732[5:0] == 6'h1e; // @[lib.scala 199:41] + wire [9:0] _T_3878 = {_T_3820,_T_3818,_T_3816,_T_3814,_T_3812,_T_3810,_T_3808,_T_3806,_T_3804,_T_3802}; // @[lib.scala 202:69] + wire _T_3800 = _T_3732[5:0] == 6'h1d; // @[lib.scala 199:41] + wire _T_3798 = _T_3732[5:0] == 6'h1c; // @[lib.scala 199:41] + wire _T_3796 = _T_3732[5:0] == 6'h1b; // @[lib.scala 199:41] + wire _T_3794 = _T_3732[5:0] == 6'h1a; // @[lib.scala 199:41] + wire _T_3792 = _T_3732[5:0] == 6'h19; // @[lib.scala 199:41] + wire _T_3790 = _T_3732[5:0] == 6'h18; // @[lib.scala 199:41] + wire _T_3788 = _T_3732[5:0] == 6'h17; // @[lib.scala 199:41] + wire _T_3786 = _T_3732[5:0] == 6'h16; // @[lib.scala 199:41] + wire _T_3784 = _T_3732[5:0] == 6'h15; // @[lib.scala 199:41] + wire _T_3782 = _T_3732[5:0] == 6'h14; // @[lib.scala 199:41] + wire [9:0] _T_3869 = {_T_3800,_T_3798,_T_3796,_T_3794,_T_3792,_T_3790,_T_3788,_T_3786,_T_3784,_T_3782}; // @[lib.scala 202:69] + wire _T_3780 = _T_3732[5:0] == 6'h13; // @[lib.scala 199:41] + wire _T_3778 = _T_3732[5:0] == 6'h12; // @[lib.scala 199:41] + wire _T_3776 = _T_3732[5:0] == 6'h11; // @[lib.scala 199:41] + wire _T_3774 = _T_3732[5:0] == 6'h10; // @[lib.scala 199:41] + wire _T_3772 = _T_3732[5:0] == 6'hf; // @[lib.scala 199:41] + wire _T_3770 = _T_3732[5:0] == 6'he; // @[lib.scala 199:41] + wire _T_3768 = _T_3732[5:0] == 6'hd; // @[lib.scala 199:41] + wire _T_3766 = _T_3732[5:0] == 6'hc; // @[lib.scala 199:41] + wire _T_3764 = _T_3732[5:0] == 6'hb; // @[lib.scala 199:41] + wire _T_3762 = _T_3732[5:0] == 6'ha; // @[lib.scala 199:41] + wire [9:0] _T_3859 = {_T_3780,_T_3778,_T_3776,_T_3774,_T_3772,_T_3770,_T_3768,_T_3766,_T_3764,_T_3762}; // @[lib.scala 202:69] + wire _T_3760 = _T_3732[5:0] == 6'h9; // @[lib.scala 199:41] + wire _T_3758 = _T_3732[5:0] == 6'h8; // @[lib.scala 199:41] + wire _T_3756 = _T_3732[5:0] == 6'h7; // @[lib.scala 199:41] + wire _T_3754 = _T_3732[5:0] == 6'h6; // @[lib.scala 199:41] + wire _T_3752 = _T_3732[5:0] == 6'h5; // @[lib.scala 199:41] + wire _T_3750 = _T_3732[5:0] == 6'h4; // @[lib.scala 199:41] + wire _T_3748 = _T_3732[5:0] == 6'h3; // @[lib.scala 199:41] + wire _T_3746 = _T_3732[5:0] == 6'h2; // @[lib.scala 199:41] + wire _T_3744 = _T_3732[5:0] == 6'h1; // @[lib.scala 199:41] + wire [18:0] _T_3860 = {_T_3859,_T_3760,_T_3758,_T_3756,_T_3754,_T_3752,_T_3750,_T_3748,_T_3746,_T_3744}; // @[lib.scala 202:69] + wire [38:0] _T_3880 = {_T_3878,_T_3869,_T_3860}; // @[lib.scala 202:69] wire [7:0] _T_3835 = {io_iccm_rd_data_ecc[74],io_iccm_rd_data_ecc[42:40],io_iccm_rd_data_ecc[73],io_iccm_rd_data_ecc[39],io_iccm_rd_data_ecc[72:71]}; // @[Cat.scala 29:58] wire [38:0] _T_3841 = {io_iccm_rd_data_ecc[77],io_iccm_rd_data_ecc[70:65],io_iccm_rd_data_ecc[76],io_iccm_rd_data_ecc[64:50],io_iccm_rd_data_ecc[75],io_iccm_rd_data_ecc[49:43],_T_3835}; // @[Cat.scala 29:58] - wire [38:0] _T_3881 = _T_3880 ^ _T_3841; // @[el2_lib.scala 342:76] - wire [38:0] _T_3882 = _T_3736 ? _T_3881 : _T_3841; // @[el2_lib.scala 342:31] + wire [38:0] _T_3881 = _T_3880 ^ _T_3841; // @[lib.scala 202:76] + wire [38:0] _T_3882 = _T_3736 ? _T_3881 : _T_3841; // @[lib.scala 202:31] wire [31:0] iccm_corrected_data_1 = {_T_3882[37:32],_T_3882[30:16],_T_3882[14:8],_T_3882[6:4],_T_3882[2]}; // @[Cat.scala 29:58] wire [31:0] iccm_dma_rdata_1_muxed = dma_mem_addr_ff[0] ? iccm_corrected_data_0 : iccm_corrected_data_1; // @[ifu_mem_ctl.scala 582:35] - wire _T_3740 = ~_T_3732[6]; // @[el2_lib.scala 335:55] - wire _T_3741 = _T_3734 & _T_3740; // @[el2_lib.scala 335:53] - wire _T_3355 = ~_T_3347[6]; // @[el2_lib.scala 335:55] - wire _T_3356 = _T_3349 & _T_3355; // @[el2_lib.scala 335:53] + wire _T_3740 = ~_T_3732[6]; // @[lib.scala 195:55] + wire _T_3741 = _T_3734 & _T_3740; // @[lib.scala 195:53] + wire _T_3355 = ~_T_3347[6]; // @[lib.scala 195:55] + wire _T_3356 = _T_3349 & _T_3355; // @[lib.scala 195:53] wire [1:0] iccm_double_ecc_error = {_T_3741,_T_3356}; // @[Cat.scala 29:58] wire iccm_dma_ecc_error_in = |iccm_double_ecc_error; // @[ifu_mem_ctl.scala 584:53] wire [63:0] _T_3104 = {io_dma_mem_ctl_dma_mem_addr,io_dma_mem_ctl_dma_mem_addr}; // @[Cat.scala 29:58] @@ -3756,11 +3756,11 @@ module ifu_mem_ctl( reg [13:0] iccm_ecc_corr_index_ff; // @[Reg.scala 27:20] wire [14:0] _T_3115 = {iccm_ecc_corr_index_ff,1'h0}; // @[Cat.scala 29:58] wire [14:0] _T_3117 = _T_3114 ? _T_3115 : io_ifc_fetch_addr_bf[14:0]; // @[ifu_mem_ctl.scala 600:8] - wire _T_3509 = _T_3347 == 7'h40; // @[el2_lib.scala 345:62] - wire _T_3510 = _T_3497[38] ^ _T_3509; // @[el2_lib.scala 345:44] + wire _T_3509 = _T_3347 == 7'h40; // @[lib.scala 205:62] + wire _T_3510 = _T_3497[38] ^ _T_3509; // @[lib.scala 205:44] wire [6:0] iccm_corrected_ecc_0 = {_T_3510,_T_3497[31],_T_3497[15],_T_3497[7],_T_3497[3],_T_3497[1:0]}; // @[Cat.scala 29:58] - wire _T_3894 = _T_3732 == 7'h40; // @[el2_lib.scala 345:62] - wire _T_3895 = _T_3882[38] ^ _T_3894; // @[el2_lib.scala 345:44] + wire _T_3894 = _T_3732 == 7'h40; // @[lib.scala 205:62] + wire _T_3895 = _T_3882[38] ^ _T_3894; // @[lib.scala 205:44] wire [6:0] iccm_corrected_ecc_1 = {_T_3895,_T_3882[31],_T_3882[15],_T_3882[7],_T_3882[3],_T_3882[1:0]}; // @[Cat.scala 29:58] wire _T_3911 = _T_3 & ifc_iccm_access_f; // @[ifu_mem_ctl.scala 612:75] wire [31:0] iccm_corrected_data_f_mux = iccm_single_ecc_error[0] ? iccm_corrected_data_0 : iccm_corrected_data_1; // @[ifu_mem_ctl.scala 614:38] @@ -5085,565 +5085,565 @@ module ifu_mem_ctl( wire _T_9884 = ~ifc_region_acc_okay; // @[ifu_mem_ctl.scala 781:65] wire _T_9885 = _T_3939 & _T_9884; // @[ifu_mem_ctl.scala 781:63] wire ifc_region_acc_fault_memory_bf = _T_9885 & io_ifc_fetch_req_bf; // @[ifu_mem_ctl.scala 781:86] - rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en), .io_scan_mode(rvclkhdr_io_scan_mode) ); - rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_1_io_l1clk), .io_clk(rvclkhdr_1_io_clk), .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_2 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_2_io_l1clk), .io_clk(rvclkhdr_2_io_clk), .io_en(rvclkhdr_2_io_en), .io_scan_mode(rvclkhdr_2_io_scan_mode) ); - rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_3 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_3_io_l1clk), .io_clk(rvclkhdr_3_io_clk), .io_en(rvclkhdr_3_io_en), .io_scan_mode(rvclkhdr_3_io_scan_mode) ); - rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_4 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_4_io_l1clk), .io_clk(rvclkhdr_4_io_clk), .io_en(rvclkhdr_4_io_en), .io_scan_mode(rvclkhdr_4_io_scan_mode) ); - rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_5 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_5_io_l1clk), .io_clk(rvclkhdr_5_io_clk), .io_en(rvclkhdr_5_io_en), .io_scan_mode(rvclkhdr_5_io_scan_mode) ); - rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_6 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_6_io_l1clk), .io_clk(rvclkhdr_6_io_clk), .io_en(rvclkhdr_6_io_en), .io_scan_mode(rvclkhdr_6_io_scan_mode) ); - rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_7 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_7_io_l1clk), .io_clk(rvclkhdr_7_io_clk), .io_en(rvclkhdr_7_io_en), .io_scan_mode(rvclkhdr_7_io_scan_mode) ); - rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_8 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_8_io_l1clk), .io_clk(rvclkhdr_8_io_clk), .io_en(rvclkhdr_8_io_en), .io_scan_mode(rvclkhdr_8_io_scan_mode) ); - rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_9 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_9_io_l1clk), .io_clk(rvclkhdr_9_io_clk), .io_en(rvclkhdr_9_io_en), .io_scan_mode(rvclkhdr_9_io_scan_mode) ); - rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_10 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_10_io_l1clk), .io_clk(rvclkhdr_10_io_clk), .io_en(rvclkhdr_10_io_en), .io_scan_mode(rvclkhdr_10_io_scan_mode) ); - rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_11 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_11_io_l1clk), .io_clk(rvclkhdr_11_io_clk), .io_en(rvclkhdr_11_io_en), .io_scan_mode(rvclkhdr_11_io_scan_mode) ); - rvclkhdr rvclkhdr_12 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_12 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_12_io_l1clk), .io_clk(rvclkhdr_12_io_clk), .io_en(rvclkhdr_12_io_en), .io_scan_mode(rvclkhdr_12_io_scan_mode) ); - rvclkhdr rvclkhdr_13 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_13 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_13_io_l1clk), .io_clk(rvclkhdr_13_io_clk), .io_en(rvclkhdr_13_io_en), .io_scan_mode(rvclkhdr_13_io_scan_mode) ); - rvclkhdr rvclkhdr_14 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_14 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_14_io_l1clk), .io_clk(rvclkhdr_14_io_clk), .io_en(rvclkhdr_14_io_en), .io_scan_mode(rvclkhdr_14_io_scan_mode) ); - rvclkhdr rvclkhdr_15 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_15 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_15_io_l1clk), .io_clk(rvclkhdr_15_io_clk), .io_en(rvclkhdr_15_io_en), .io_scan_mode(rvclkhdr_15_io_scan_mode) ); - rvclkhdr rvclkhdr_16 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_16 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_16_io_l1clk), .io_clk(rvclkhdr_16_io_clk), .io_en(rvclkhdr_16_io_en), .io_scan_mode(rvclkhdr_16_io_scan_mode) ); - rvclkhdr rvclkhdr_17 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_17 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_17_io_l1clk), .io_clk(rvclkhdr_17_io_clk), .io_en(rvclkhdr_17_io_en), .io_scan_mode(rvclkhdr_17_io_scan_mode) ); - rvclkhdr rvclkhdr_18 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_18 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_18_io_l1clk), .io_clk(rvclkhdr_18_io_clk), .io_en(rvclkhdr_18_io_en), .io_scan_mode(rvclkhdr_18_io_scan_mode) ); - rvclkhdr rvclkhdr_19 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_19 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_19_io_l1clk), .io_clk(rvclkhdr_19_io_clk), .io_en(rvclkhdr_19_io_en), .io_scan_mode(rvclkhdr_19_io_scan_mode) ); - rvclkhdr rvclkhdr_20 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_20 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_20_io_l1clk), .io_clk(rvclkhdr_20_io_clk), .io_en(rvclkhdr_20_io_en), .io_scan_mode(rvclkhdr_20_io_scan_mode) ); - rvclkhdr rvclkhdr_21 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_21 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_21_io_l1clk), .io_clk(rvclkhdr_21_io_clk), .io_en(rvclkhdr_21_io_en), .io_scan_mode(rvclkhdr_21_io_scan_mode) ); - rvclkhdr rvclkhdr_22 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_22 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_22_io_l1clk), .io_clk(rvclkhdr_22_io_clk), .io_en(rvclkhdr_22_io_en), .io_scan_mode(rvclkhdr_22_io_scan_mode) ); - rvclkhdr rvclkhdr_23 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_23 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_23_io_l1clk), .io_clk(rvclkhdr_23_io_clk), .io_en(rvclkhdr_23_io_en), .io_scan_mode(rvclkhdr_23_io_scan_mode) ); - rvclkhdr rvclkhdr_24 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_24 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_24_io_l1clk), .io_clk(rvclkhdr_24_io_clk), .io_en(rvclkhdr_24_io_en), .io_scan_mode(rvclkhdr_24_io_scan_mode) ); - rvclkhdr rvclkhdr_25 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_25 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_25_io_l1clk), .io_clk(rvclkhdr_25_io_clk), .io_en(rvclkhdr_25_io_en), .io_scan_mode(rvclkhdr_25_io_scan_mode) ); - rvclkhdr rvclkhdr_26 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_26 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_26_io_l1clk), .io_clk(rvclkhdr_26_io_clk), .io_en(rvclkhdr_26_io_en), .io_scan_mode(rvclkhdr_26_io_scan_mode) ); - rvclkhdr rvclkhdr_27 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_27 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_27_io_l1clk), .io_clk(rvclkhdr_27_io_clk), .io_en(rvclkhdr_27_io_en), .io_scan_mode(rvclkhdr_27_io_scan_mode) ); - rvclkhdr rvclkhdr_28 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_28 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_28_io_l1clk), .io_clk(rvclkhdr_28_io_clk), .io_en(rvclkhdr_28_io_en), .io_scan_mode(rvclkhdr_28_io_scan_mode) ); - rvclkhdr rvclkhdr_29 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_29 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_29_io_l1clk), .io_clk(rvclkhdr_29_io_clk), .io_en(rvclkhdr_29_io_en), .io_scan_mode(rvclkhdr_29_io_scan_mode) ); - rvclkhdr rvclkhdr_30 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_30 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_30_io_l1clk), .io_clk(rvclkhdr_30_io_clk), .io_en(rvclkhdr_30_io_en), .io_scan_mode(rvclkhdr_30_io_scan_mode) ); - rvclkhdr rvclkhdr_31 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_31 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_31_io_l1clk), .io_clk(rvclkhdr_31_io_clk), .io_en(rvclkhdr_31_io_en), .io_scan_mode(rvclkhdr_31_io_scan_mode) ); - rvclkhdr rvclkhdr_32 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_32 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_32_io_l1clk), .io_clk(rvclkhdr_32_io_clk), .io_en(rvclkhdr_32_io_en), .io_scan_mode(rvclkhdr_32_io_scan_mode) ); - rvclkhdr rvclkhdr_33 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_33 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_33_io_l1clk), .io_clk(rvclkhdr_33_io_clk), .io_en(rvclkhdr_33_io_en), .io_scan_mode(rvclkhdr_33_io_scan_mode) ); - rvclkhdr rvclkhdr_34 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_34 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_34_io_l1clk), .io_clk(rvclkhdr_34_io_clk), .io_en(rvclkhdr_34_io_en), .io_scan_mode(rvclkhdr_34_io_scan_mode) ); - rvclkhdr rvclkhdr_35 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_35 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_35_io_l1clk), .io_clk(rvclkhdr_35_io_clk), .io_en(rvclkhdr_35_io_en), .io_scan_mode(rvclkhdr_35_io_scan_mode) ); - rvclkhdr rvclkhdr_36 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_36 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_36_io_l1clk), .io_clk(rvclkhdr_36_io_clk), .io_en(rvclkhdr_36_io_en), .io_scan_mode(rvclkhdr_36_io_scan_mode) ); - rvclkhdr rvclkhdr_37 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_37 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_37_io_l1clk), .io_clk(rvclkhdr_37_io_clk), .io_en(rvclkhdr_37_io_en), .io_scan_mode(rvclkhdr_37_io_scan_mode) ); - rvclkhdr rvclkhdr_38 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_38 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_38_io_l1clk), .io_clk(rvclkhdr_38_io_clk), .io_en(rvclkhdr_38_io_en), .io_scan_mode(rvclkhdr_38_io_scan_mode) ); - rvclkhdr rvclkhdr_39 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_39 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_39_io_l1clk), .io_clk(rvclkhdr_39_io_clk), .io_en(rvclkhdr_39_io_en), .io_scan_mode(rvclkhdr_39_io_scan_mode) ); - rvclkhdr rvclkhdr_40 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_40 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_40_io_l1clk), .io_clk(rvclkhdr_40_io_clk), .io_en(rvclkhdr_40_io_en), .io_scan_mode(rvclkhdr_40_io_scan_mode) ); - rvclkhdr rvclkhdr_41 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_41 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_41_io_l1clk), .io_clk(rvclkhdr_41_io_clk), .io_en(rvclkhdr_41_io_en), .io_scan_mode(rvclkhdr_41_io_scan_mode) ); - rvclkhdr rvclkhdr_42 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_42 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_42_io_l1clk), .io_clk(rvclkhdr_42_io_clk), .io_en(rvclkhdr_42_io_en), .io_scan_mode(rvclkhdr_42_io_scan_mode) ); - rvclkhdr rvclkhdr_43 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_43 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_43_io_l1clk), .io_clk(rvclkhdr_43_io_clk), .io_en(rvclkhdr_43_io_en), .io_scan_mode(rvclkhdr_43_io_scan_mode) ); - rvclkhdr rvclkhdr_44 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_44 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_44_io_l1clk), .io_clk(rvclkhdr_44_io_clk), .io_en(rvclkhdr_44_io_en), .io_scan_mode(rvclkhdr_44_io_scan_mode) ); - rvclkhdr rvclkhdr_45 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_45 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_45_io_l1clk), .io_clk(rvclkhdr_45_io_clk), .io_en(rvclkhdr_45_io_en), .io_scan_mode(rvclkhdr_45_io_scan_mode) ); - rvclkhdr rvclkhdr_46 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_46 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_46_io_l1clk), .io_clk(rvclkhdr_46_io_clk), .io_en(rvclkhdr_46_io_en), .io_scan_mode(rvclkhdr_46_io_scan_mode) ); - rvclkhdr rvclkhdr_47 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_47 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_47_io_l1clk), .io_clk(rvclkhdr_47_io_clk), .io_en(rvclkhdr_47_io_en), .io_scan_mode(rvclkhdr_47_io_scan_mode) ); - rvclkhdr rvclkhdr_48 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_48 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_48_io_l1clk), .io_clk(rvclkhdr_48_io_clk), .io_en(rvclkhdr_48_io_en), .io_scan_mode(rvclkhdr_48_io_scan_mode) ); - rvclkhdr rvclkhdr_49 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_49 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_49_io_l1clk), .io_clk(rvclkhdr_49_io_clk), .io_en(rvclkhdr_49_io_en), .io_scan_mode(rvclkhdr_49_io_scan_mode) ); - rvclkhdr rvclkhdr_50 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_50 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_50_io_l1clk), .io_clk(rvclkhdr_50_io_clk), .io_en(rvclkhdr_50_io_en), .io_scan_mode(rvclkhdr_50_io_scan_mode) ); - rvclkhdr rvclkhdr_51 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_51 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_51_io_l1clk), .io_clk(rvclkhdr_51_io_clk), .io_en(rvclkhdr_51_io_en), .io_scan_mode(rvclkhdr_51_io_scan_mode) ); - rvclkhdr rvclkhdr_52 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_52 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_52_io_l1clk), .io_clk(rvclkhdr_52_io_clk), .io_en(rvclkhdr_52_io_en), .io_scan_mode(rvclkhdr_52_io_scan_mode) ); - rvclkhdr rvclkhdr_53 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_53 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_53_io_l1clk), .io_clk(rvclkhdr_53_io_clk), .io_en(rvclkhdr_53_io_en), .io_scan_mode(rvclkhdr_53_io_scan_mode) ); - rvclkhdr rvclkhdr_54 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_54 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_54_io_l1clk), .io_clk(rvclkhdr_54_io_clk), .io_en(rvclkhdr_54_io_en), .io_scan_mode(rvclkhdr_54_io_scan_mode) ); - rvclkhdr rvclkhdr_55 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_55 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_55_io_l1clk), .io_clk(rvclkhdr_55_io_clk), .io_en(rvclkhdr_55_io_en), .io_scan_mode(rvclkhdr_55_io_scan_mode) ); - rvclkhdr rvclkhdr_56 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_56 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_56_io_l1clk), .io_clk(rvclkhdr_56_io_clk), .io_en(rvclkhdr_56_io_en), .io_scan_mode(rvclkhdr_56_io_scan_mode) ); - rvclkhdr rvclkhdr_57 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_57 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_57_io_l1clk), .io_clk(rvclkhdr_57_io_clk), .io_en(rvclkhdr_57_io_en), .io_scan_mode(rvclkhdr_57_io_scan_mode) ); - rvclkhdr rvclkhdr_58 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_58 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_58_io_l1clk), .io_clk(rvclkhdr_58_io_clk), .io_en(rvclkhdr_58_io_en), .io_scan_mode(rvclkhdr_58_io_scan_mode) ); - rvclkhdr rvclkhdr_59 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_59 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_59_io_l1clk), .io_clk(rvclkhdr_59_io_clk), .io_en(rvclkhdr_59_io_en), .io_scan_mode(rvclkhdr_59_io_scan_mode) ); - rvclkhdr rvclkhdr_60 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_60 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_60_io_l1clk), .io_clk(rvclkhdr_60_io_clk), .io_en(rvclkhdr_60_io_en), .io_scan_mode(rvclkhdr_60_io_scan_mode) ); - rvclkhdr rvclkhdr_61 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_61 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_61_io_l1clk), .io_clk(rvclkhdr_61_io_clk), .io_en(rvclkhdr_61_io_en), .io_scan_mode(rvclkhdr_61_io_scan_mode) ); - rvclkhdr rvclkhdr_62 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_62 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_62_io_l1clk), .io_clk(rvclkhdr_62_io_clk), .io_en(rvclkhdr_62_io_en), .io_scan_mode(rvclkhdr_62_io_scan_mode) ); - rvclkhdr rvclkhdr_63 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_63 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_63_io_l1clk), .io_clk(rvclkhdr_63_io_clk), .io_en(rvclkhdr_63_io_en), .io_scan_mode(rvclkhdr_63_io_scan_mode) ); - rvclkhdr rvclkhdr_64 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_64 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_64_io_l1clk), .io_clk(rvclkhdr_64_io_clk), .io_en(rvclkhdr_64_io_en), .io_scan_mode(rvclkhdr_64_io_scan_mode) ); - rvclkhdr rvclkhdr_65 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_65 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_65_io_l1clk), .io_clk(rvclkhdr_65_io_clk), .io_en(rvclkhdr_65_io_en), .io_scan_mode(rvclkhdr_65_io_scan_mode) ); - rvclkhdr rvclkhdr_66 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_66 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_66_io_l1clk), .io_clk(rvclkhdr_66_io_clk), .io_en(rvclkhdr_66_io_en), .io_scan_mode(rvclkhdr_66_io_scan_mode) ); - rvclkhdr rvclkhdr_67 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_67 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_67_io_l1clk), .io_clk(rvclkhdr_67_io_clk), .io_en(rvclkhdr_67_io_en), .io_scan_mode(rvclkhdr_67_io_scan_mode) ); - rvclkhdr rvclkhdr_68 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_68 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_68_io_l1clk), .io_clk(rvclkhdr_68_io_clk), .io_en(rvclkhdr_68_io_en), .io_scan_mode(rvclkhdr_68_io_scan_mode) ); - rvclkhdr rvclkhdr_69 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_69 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_69_io_l1clk), .io_clk(rvclkhdr_69_io_clk), .io_en(rvclkhdr_69_io_en), .io_scan_mode(rvclkhdr_69_io_scan_mode) ); - rvclkhdr rvclkhdr_70 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_70 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_70_io_l1clk), .io_clk(rvclkhdr_70_io_clk), .io_en(rvclkhdr_70_io_en), .io_scan_mode(rvclkhdr_70_io_scan_mode) ); - rvclkhdr rvclkhdr_71 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_71 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_71_io_l1clk), .io_clk(rvclkhdr_71_io_clk), .io_en(rvclkhdr_71_io_en), .io_scan_mode(rvclkhdr_71_io_scan_mode) ); - rvclkhdr rvclkhdr_72 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_72 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_72_io_l1clk), .io_clk(rvclkhdr_72_io_clk), .io_en(rvclkhdr_72_io_en), .io_scan_mode(rvclkhdr_72_io_scan_mode) ); - rvclkhdr rvclkhdr_73 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_73 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_73_io_l1clk), .io_clk(rvclkhdr_73_io_clk), .io_en(rvclkhdr_73_io_en), .io_scan_mode(rvclkhdr_73_io_scan_mode) ); - rvclkhdr rvclkhdr_74 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_74 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_74_io_l1clk), .io_clk(rvclkhdr_74_io_clk), .io_en(rvclkhdr_74_io_en), .io_scan_mode(rvclkhdr_74_io_scan_mode) ); - rvclkhdr rvclkhdr_75 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_75 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_75_io_l1clk), .io_clk(rvclkhdr_75_io_clk), .io_en(rvclkhdr_75_io_en), .io_scan_mode(rvclkhdr_75_io_scan_mode) ); - rvclkhdr rvclkhdr_76 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_76 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_76_io_l1clk), .io_clk(rvclkhdr_76_io_clk), .io_en(rvclkhdr_76_io_en), .io_scan_mode(rvclkhdr_76_io_scan_mode) ); - rvclkhdr rvclkhdr_77 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_77 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_77_io_l1clk), .io_clk(rvclkhdr_77_io_clk), .io_en(rvclkhdr_77_io_en), .io_scan_mode(rvclkhdr_77_io_scan_mode) ); - rvclkhdr rvclkhdr_78 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_78 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_78_io_l1clk), .io_clk(rvclkhdr_78_io_clk), .io_en(rvclkhdr_78_io_en), .io_scan_mode(rvclkhdr_78_io_scan_mode) ); - rvclkhdr rvclkhdr_79 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_79 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_79_io_l1clk), .io_clk(rvclkhdr_79_io_clk), .io_en(rvclkhdr_79_io_en), .io_scan_mode(rvclkhdr_79_io_scan_mode) ); - rvclkhdr rvclkhdr_80 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_80 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_80_io_l1clk), .io_clk(rvclkhdr_80_io_clk), .io_en(rvclkhdr_80_io_en), .io_scan_mode(rvclkhdr_80_io_scan_mode) ); - rvclkhdr rvclkhdr_81 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_81 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_81_io_l1clk), .io_clk(rvclkhdr_81_io_clk), .io_en(rvclkhdr_81_io_en), .io_scan_mode(rvclkhdr_81_io_scan_mode) ); - rvclkhdr rvclkhdr_82 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_82 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_82_io_l1clk), .io_clk(rvclkhdr_82_io_clk), .io_en(rvclkhdr_82_io_en), .io_scan_mode(rvclkhdr_82_io_scan_mode) ); - rvclkhdr rvclkhdr_83 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_83 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_83_io_l1clk), .io_clk(rvclkhdr_83_io_clk), .io_en(rvclkhdr_83_io_en), .io_scan_mode(rvclkhdr_83_io_scan_mode) ); - rvclkhdr rvclkhdr_84 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_84 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_84_io_l1clk), .io_clk(rvclkhdr_84_io_clk), .io_en(rvclkhdr_84_io_en), .io_scan_mode(rvclkhdr_84_io_scan_mode) ); - rvclkhdr rvclkhdr_85 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_85 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_85_io_l1clk), .io_clk(rvclkhdr_85_io_clk), .io_en(rvclkhdr_85_io_en), .io_scan_mode(rvclkhdr_85_io_scan_mode) ); - rvclkhdr rvclkhdr_86 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_86 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_86_io_l1clk), .io_clk(rvclkhdr_86_io_clk), .io_en(rvclkhdr_86_io_en), .io_scan_mode(rvclkhdr_86_io_scan_mode) ); - rvclkhdr rvclkhdr_87 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_87 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_87_io_l1clk), .io_clk(rvclkhdr_87_io_clk), .io_en(rvclkhdr_87_io_en), .io_scan_mode(rvclkhdr_87_io_scan_mode) ); - rvclkhdr rvclkhdr_88 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_88 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_88_io_l1clk), .io_clk(rvclkhdr_88_io_clk), .io_en(rvclkhdr_88_io_en), .io_scan_mode(rvclkhdr_88_io_scan_mode) ); - rvclkhdr rvclkhdr_89 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_89 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_89_io_l1clk), .io_clk(rvclkhdr_89_io_clk), .io_en(rvclkhdr_89_io_en), .io_scan_mode(rvclkhdr_89_io_scan_mode) ); - rvclkhdr rvclkhdr_90 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_90 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_90_io_l1clk), .io_clk(rvclkhdr_90_io_clk), .io_en(rvclkhdr_90_io_en), .io_scan_mode(rvclkhdr_90_io_scan_mode) ); - rvclkhdr rvclkhdr_91 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_91 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_91_io_l1clk), .io_clk(rvclkhdr_91_io_clk), .io_en(rvclkhdr_91_io_en), .io_scan_mode(rvclkhdr_91_io_scan_mode) ); - rvclkhdr rvclkhdr_92 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_92 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_92_io_l1clk), .io_clk(rvclkhdr_92_io_clk), .io_en(rvclkhdr_92_io_en), .io_scan_mode(rvclkhdr_92_io_scan_mode) ); - rvclkhdr rvclkhdr_93 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_93 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_93_io_l1clk), .io_clk(rvclkhdr_93_io_clk), .io_en(rvclkhdr_93_io_en), @@ -5701,288 +5701,288 @@ module ifu_mem_ctl( assign io_ifu_async_error_start = io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err | io_dec_mem_ctrl_ifu_ic_error_start; // @[ifu_mem_ctl.scala 96:28] assign io_ic_fetch_val_f = {_T_1286,fetch_req_f_qual}; // @[ifu_mem_ctl.scala 305:21] assign io_ic_data_f = ic_final_data[31:0]; // @[ifu_mem_ctl.scala 298:16] - assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_io_en = ic_debug_rd_en_ff; // @[el2_lib.scala 485:16] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_1_io_en = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_lib.scala 485:16] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_2_io_en = _T_2 | scnd_miss_req; // @[el2_lib.scala 485:16] - assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_3_io_en = _T_309 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[el2_lib.scala 485:16] - assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_4_io_en = bus_ifu_wr_en & _T_1289; // @[el2_lib.scala 485:16] - assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_5_io_en = bus_ifu_wr_en & _T_1290; // @[el2_lib.scala 485:16] - assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_6_io_en = bus_ifu_wr_en & _T_1291; // @[el2_lib.scala 485:16] - assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_7_io_en = bus_ifu_wr_en & _T_1292; // @[el2_lib.scala 485:16] - assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_8_io_en = bus_ifu_wr_en & _T_1293; // @[el2_lib.scala 485:16] - assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_9_io_en = bus_ifu_wr_en & _T_1294; // @[el2_lib.scala 485:16] - assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_10_io_en = bus_ifu_wr_en & _T_1295; // @[el2_lib.scala 485:16] - assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_11_io_en = bus_ifu_wr_en & _T_1296; // @[el2_lib.scala 485:16] - assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_12_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_12_io_en = bus_ifu_wr_en & _T_1289; // @[el2_lib.scala 485:16] - assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_13_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_13_io_en = bus_ifu_wr_en & _T_1290; // @[el2_lib.scala 485:16] - assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_14_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_14_io_en = bus_ifu_wr_en & _T_1291; // @[el2_lib.scala 485:16] - assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_15_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_15_io_en = bus_ifu_wr_en & _T_1292; // @[el2_lib.scala 485:16] - assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_16_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_16_io_en = bus_ifu_wr_en & _T_1293; // @[el2_lib.scala 485:16] - assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_17_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_17_io_en = bus_ifu_wr_en & _T_1294; // @[el2_lib.scala 485:16] - assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_18_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_18_io_en = bus_ifu_wr_en & _T_1295; // @[el2_lib.scala 485:16] - assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_19_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_19_io_en = bus_ifu_wr_en & _T_1296; // @[el2_lib.scala 485:16] - assign rvclkhdr_19_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_20_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_20_io_en = bus_ifu_wr_en & _T_1289; // @[el2_lib.scala 485:16] - assign rvclkhdr_20_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_21_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_21_io_en = bus_ifu_wr_en & _T_1290; // @[el2_lib.scala 485:16] - assign rvclkhdr_21_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_22_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_22_io_en = bus_ifu_wr_en & _T_1291; // @[el2_lib.scala 485:16] - assign rvclkhdr_22_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_23_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_23_io_en = bus_ifu_wr_en & _T_1292; // @[el2_lib.scala 485:16] - assign rvclkhdr_23_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_24_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_24_io_en = bus_ifu_wr_en & _T_1293; // @[el2_lib.scala 485:16] - assign rvclkhdr_24_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_25_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_25_io_en = bus_ifu_wr_en & _T_1294; // @[el2_lib.scala 485:16] - assign rvclkhdr_25_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_26_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_26_io_en = bus_ifu_wr_en & _T_1295; // @[el2_lib.scala 485:16] - assign rvclkhdr_26_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_27_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_27_io_en = bus_ifu_wr_en & _T_1296; // @[el2_lib.scala 485:16] - assign rvclkhdr_27_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_28_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_28_io_en = bus_ifu_wr_en & _T_1289; // @[el2_lib.scala 485:16] - assign rvclkhdr_28_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_29_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_29_io_en = bus_ifu_wr_en & _T_1290; // @[el2_lib.scala 485:16] - assign rvclkhdr_29_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_30_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_30_io_en = bus_ifu_wr_en & _T_1291; // @[el2_lib.scala 485:16] - assign rvclkhdr_30_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_31_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_31_io_en = bus_ifu_wr_en & _T_1292; // @[el2_lib.scala 485:16] - assign rvclkhdr_31_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_32_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_32_io_en = bus_ifu_wr_en & _T_1293; // @[el2_lib.scala 485:16] - assign rvclkhdr_32_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_33_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_33_io_en = bus_ifu_wr_en & _T_1294; // @[el2_lib.scala 485:16] - assign rvclkhdr_33_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_34_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_34_io_en = bus_ifu_wr_en & _T_1295; // @[el2_lib.scala 485:16] - assign rvclkhdr_34_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_35_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_35_io_en = bus_ifu_wr_en & _T_1296; // @[el2_lib.scala 485:16] - assign rvclkhdr_35_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_36_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_36_io_en = bus_ifu_wr_en & _T_1289; // @[el2_lib.scala 485:16] - assign rvclkhdr_36_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_37_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_37_io_en = bus_ifu_wr_en & _T_1290; // @[el2_lib.scala 485:16] - assign rvclkhdr_37_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_38_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_38_io_en = bus_ifu_wr_en & _T_1291; // @[el2_lib.scala 485:16] - assign rvclkhdr_38_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_39_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_39_io_en = bus_ifu_wr_en & _T_1292; // @[el2_lib.scala 485:16] - assign rvclkhdr_39_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_40_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_40_io_en = bus_ifu_wr_en & _T_1293; // @[el2_lib.scala 485:16] - assign rvclkhdr_40_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_41_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_41_io_en = bus_ifu_wr_en & _T_1294; // @[el2_lib.scala 485:16] - assign rvclkhdr_41_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_42_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_42_io_en = bus_ifu_wr_en & _T_1295; // @[el2_lib.scala 485:16] - assign rvclkhdr_42_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_43_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_43_io_en = bus_ifu_wr_en & _T_1296; // @[el2_lib.scala 485:16] - assign rvclkhdr_43_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_44_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_44_io_en = bus_ifu_wr_en & _T_1289; // @[el2_lib.scala 485:16] - assign rvclkhdr_44_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_45_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_45_io_en = bus_ifu_wr_en & _T_1290; // @[el2_lib.scala 485:16] - assign rvclkhdr_45_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_46_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_46_io_en = bus_ifu_wr_en & _T_1291; // @[el2_lib.scala 485:16] - assign rvclkhdr_46_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_47_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_47_io_en = bus_ifu_wr_en & _T_1292; // @[el2_lib.scala 485:16] - assign rvclkhdr_47_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_48_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_48_io_en = bus_ifu_wr_en & _T_1293; // @[el2_lib.scala 485:16] - assign rvclkhdr_48_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_49_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_49_io_en = bus_ifu_wr_en & _T_1294; // @[el2_lib.scala 485:16] - assign rvclkhdr_49_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_50_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_50_io_en = bus_ifu_wr_en & _T_1295; // @[el2_lib.scala 485:16] - assign rvclkhdr_50_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_51_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_51_io_en = bus_ifu_wr_en & _T_1296; // @[el2_lib.scala 485:16] - assign rvclkhdr_51_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_52_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_52_io_en = bus_ifu_wr_en & _T_1289; // @[el2_lib.scala 485:16] - assign rvclkhdr_52_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_53_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_53_io_en = bus_ifu_wr_en & _T_1290; // @[el2_lib.scala 485:16] - assign rvclkhdr_53_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_54_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_54_io_en = bus_ifu_wr_en & _T_1291; // @[el2_lib.scala 485:16] - assign rvclkhdr_54_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_55_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_55_io_en = bus_ifu_wr_en & _T_1292; // @[el2_lib.scala 485:16] - assign rvclkhdr_55_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_56_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_56_io_en = bus_ifu_wr_en & _T_1293; // @[el2_lib.scala 485:16] - assign rvclkhdr_56_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_57_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_57_io_en = bus_ifu_wr_en & _T_1294; // @[el2_lib.scala 485:16] - assign rvclkhdr_57_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_58_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_58_io_en = bus_ifu_wr_en & _T_1295; // @[el2_lib.scala 485:16] - assign rvclkhdr_58_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_59_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_59_io_en = bus_ifu_wr_en & _T_1296; // @[el2_lib.scala 485:16] - assign rvclkhdr_59_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_60_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_60_io_en = bus_ifu_wr_en & _T_1289; // @[el2_lib.scala 485:16] - assign rvclkhdr_60_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_61_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_61_io_en = bus_ifu_wr_en & _T_1290; // @[el2_lib.scala 485:16] - assign rvclkhdr_61_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_62_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_62_io_en = bus_ifu_wr_en & _T_1291; // @[el2_lib.scala 485:16] - assign rvclkhdr_62_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_63_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_63_io_en = bus_ifu_wr_en & _T_1292; // @[el2_lib.scala 485:16] - assign rvclkhdr_63_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_64_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_64_io_en = bus_ifu_wr_en & _T_1293; // @[el2_lib.scala 485:16] - assign rvclkhdr_64_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_65_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_65_io_en = bus_ifu_wr_en & _T_1294; // @[el2_lib.scala 485:16] - assign rvclkhdr_65_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_66_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_66_io_en = bus_ifu_wr_en & _T_1295; // @[el2_lib.scala 485:16] - assign rvclkhdr_66_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_67_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_67_io_en = bus_ifu_wr_en & _T_1296; // @[el2_lib.scala 485:16] - assign rvclkhdr_67_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_68_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_68_io_en = io_ifu_bus_clk_en; // @[el2_lib.scala 485:16] - assign rvclkhdr_68_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_69_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_69_io_en = io_ifu_bus_clk_en | io_dec_mem_ctrl_dec_tlu_force_halt; // @[el2_lib.scala 485:16] - assign rvclkhdr_69_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_70_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_70_io_en = ifu_status_wr_addr_ff[6:3] == 4'h0; // @[el2_lib.scala 485:16] - assign rvclkhdr_70_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_71_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_71_io_en = ifu_status_wr_addr_ff[6:3] == 4'h1; // @[el2_lib.scala 485:16] - assign rvclkhdr_71_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_72_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_72_io_en = ifu_status_wr_addr_ff[6:3] == 4'h2; // @[el2_lib.scala 485:16] - assign rvclkhdr_72_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_73_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_73_io_en = ifu_status_wr_addr_ff[6:3] == 4'h3; // @[el2_lib.scala 485:16] - assign rvclkhdr_73_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_74_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_74_io_en = ifu_status_wr_addr_ff[6:3] == 4'h4; // @[el2_lib.scala 485:16] - assign rvclkhdr_74_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_75_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_75_io_en = ifu_status_wr_addr_ff[6:3] == 4'h5; // @[el2_lib.scala 485:16] - assign rvclkhdr_75_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_76_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_76_io_en = ifu_status_wr_addr_ff[6:3] == 4'h6; // @[el2_lib.scala 485:16] - assign rvclkhdr_76_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_77_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_77_io_en = ifu_status_wr_addr_ff[6:3] == 4'h7; // @[el2_lib.scala 485:16] - assign rvclkhdr_77_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_78_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_78_io_en = ifu_status_wr_addr_ff[6:3] == 4'h8; // @[el2_lib.scala 485:16] - assign rvclkhdr_78_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_79_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_79_io_en = ifu_status_wr_addr_ff[6:3] == 4'h9; // @[el2_lib.scala 485:16] - assign rvclkhdr_79_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_80_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_80_io_en = ifu_status_wr_addr_ff[6:3] == 4'ha; // @[el2_lib.scala 485:16] - assign rvclkhdr_80_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_81_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_81_io_en = ifu_status_wr_addr_ff[6:3] == 4'hb; // @[el2_lib.scala 485:16] - assign rvclkhdr_81_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_82_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_82_io_en = ifu_status_wr_addr_ff[6:3] == 4'hc; // @[el2_lib.scala 485:16] - assign rvclkhdr_82_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_83_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_83_io_en = ifu_status_wr_addr_ff[6:3] == 4'hd; // @[el2_lib.scala 485:16] - assign rvclkhdr_83_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_84_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_84_io_en = ifu_status_wr_addr_ff[6:3] == 4'he; // @[el2_lib.scala 485:16] - assign rvclkhdr_84_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_85_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_85_io_en = ifu_status_wr_addr_ff[6:3] == 4'hf; // @[el2_lib.scala 485:16] - assign rvclkhdr_85_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_86_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_86_io_en = tag_valid_clken_0[0]; // @[el2_lib.scala 485:16] - assign rvclkhdr_86_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_87_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_87_io_en = tag_valid_clken_0[1]; // @[el2_lib.scala 485:16] - assign rvclkhdr_87_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_88_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_88_io_en = tag_valid_clken_1[0]; // @[el2_lib.scala 485:16] - assign rvclkhdr_88_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_89_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_89_io_en = tag_valid_clken_1[1]; // @[el2_lib.scala 485:16] - assign rvclkhdr_89_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_90_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_90_io_en = tag_valid_clken_2[0]; // @[el2_lib.scala 485:16] - assign rvclkhdr_90_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_91_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_91_io_en = tag_valid_clken_2[1]; // @[el2_lib.scala 485:16] - assign rvclkhdr_91_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_92_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_92_io_en = tag_valid_clken_3[0]; // @[el2_lib.scala 485:16] - assign rvclkhdr_92_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_93_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_93_io_en = tag_valid_clken_3[1]; // @[el2_lib.scala 485:16] - assign rvclkhdr_93_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_io_en = ic_debug_rd_en_ff; // @[lib.scala 345:16] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_1_io_en = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[lib.scala 345:16] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_2_io_en = _T_2 | scnd_miss_req; // @[lib.scala 345:16] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_3_io_en = _T_309 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[lib.scala 345:16] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_4_io_en = bus_ifu_wr_en & _T_1289; // @[lib.scala 345:16] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_5_io_en = bus_ifu_wr_en & _T_1290; // @[lib.scala 345:16] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_6_io_en = bus_ifu_wr_en & _T_1291; // @[lib.scala 345:16] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_7_io_en = bus_ifu_wr_en & _T_1292; // @[lib.scala 345:16] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_8_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_8_io_en = bus_ifu_wr_en & _T_1293; // @[lib.scala 345:16] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_9_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_9_io_en = bus_ifu_wr_en & _T_1294; // @[lib.scala 345:16] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_10_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_10_io_en = bus_ifu_wr_en & _T_1295; // @[lib.scala 345:16] + assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_11_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_11_io_en = bus_ifu_wr_en & _T_1296; // @[lib.scala 345:16] + assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_12_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_12_io_en = bus_ifu_wr_en & _T_1289; // @[lib.scala 345:16] + assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_13_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_13_io_en = bus_ifu_wr_en & _T_1290; // @[lib.scala 345:16] + assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_14_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_14_io_en = bus_ifu_wr_en & _T_1291; // @[lib.scala 345:16] + assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_15_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_15_io_en = bus_ifu_wr_en & _T_1292; // @[lib.scala 345:16] + assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_16_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_16_io_en = bus_ifu_wr_en & _T_1293; // @[lib.scala 345:16] + assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_17_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_17_io_en = bus_ifu_wr_en & _T_1294; // @[lib.scala 345:16] + assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_18_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_18_io_en = bus_ifu_wr_en & _T_1295; // @[lib.scala 345:16] + assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_19_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_19_io_en = bus_ifu_wr_en & _T_1296; // @[lib.scala 345:16] + assign rvclkhdr_19_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_20_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_20_io_en = bus_ifu_wr_en & _T_1289; // @[lib.scala 345:16] + assign rvclkhdr_20_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_21_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_21_io_en = bus_ifu_wr_en & _T_1290; // @[lib.scala 345:16] + assign rvclkhdr_21_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_22_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_22_io_en = bus_ifu_wr_en & _T_1291; // @[lib.scala 345:16] + assign rvclkhdr_22_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_23_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_23_io_en = bus_ifu_wr_en & _T_1292; // @[lib.scala 345:16] + assign rvclkhdr_23_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_24_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_24_io_en = bus_ifu_wr_en & _T_1293; // @[lib.scala 345:16] + assign rvclkhdr_24_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_25_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_25_io_en = bus_ifu_wr_en & _T_1294; // @[lib.scala 345:16] + assign rvclkhdr_25_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_26_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_26_io_en = bus_ifu_wr_en & _T_1295; // @[lib.scala 345:16] + assign rvclkhdr_26_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_27_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_27_io_en = bus_ifu_wr_en & _T_1296; // @[lib.scala 345:16] + assign rvclkhdr_27_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_28_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_28_io_en = bus_ifu_wr_en & _T_1289; // @[lib.scala 345:16] + assign rvclkhdr_28_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_29_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_29_io_en = bus_ifu_wr_en & _T_1290; // @[lib.scala 345:16] + assign rvclkhdr_29_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_30_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_30_io_en = bus_ifu_wr_en & _T_1291; // @[lib.scala 345:16] + assign rvclkhdr_30_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_31_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_31_io_en = bus_ifu_wr_en & _T_1292; // @[lib.scala 345:16] + assign rvclkhdr_31_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_32_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_32_io_en = bus_ifu_wr_en & _T_1293; // @[lib.scala 345:16] + assign rvclkhdr_32_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_33_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_33_io_en = bus_ifu_wr_en & _T_1294; // @[lib.scala 345:16] + assign rvclkhdr_33_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_34_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_34_io_en = bus_ifu_wr_en & _T_1295; // @[lib.scala 345:16] + assign rvclkhdr_34_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_35_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_35_io_en = bus_ifu_wr_en & _T_1296; // @[lib.scala 345:16] + assign rvclkhdr_35_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_36_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_36_io_en = bus_ifu_wr_en & _T_1289; // @[lib.scala 345:16] + assign rvclkhdr_36_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_37_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_37_io_en = bus_ifu_wr_en & _T_1290; // @[lib.scala 345:16] + assign rvclkhdr_37_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_38_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_38_io_en = bus_ifu_wr_en & _T_1291; // @[lib.scala 345:16] + assign rvclkhdr_38_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_39_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_39_io_en = bus_ifu_wr_en & _T_1292; // @[lib.scala 345:16] + assign rvclkhdr_39_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_40_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_40_io_en = bus_ifu_wr_en & _T_1293; // @[lib.scala 345:16] + assign rvclkhdr_40_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_41_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_41_io_en = bus_ifu_wr_en & _T_1294; // @[lib.scala 345:16] + assign rvclkhdr_41_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_42_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_42_io_en = bus_ifu_wr_en & _T_1295; // @[lib.scala 345:16] + assign rvclkhdr_42_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_43_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_43_io_en = bus_ifu_wr_en & _T_1296; // @[lib.scala 345:16] + assign rvclkhdr_43_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_44_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_44_io_en = bus_ifu_wr_en & _T_1289; // @[lib.scala 345:16] + assign rvclkhdr_44_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_45_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_45_io_en = bus_ifu_wr_en & _T_1290; // @[lib.scala 345:16] + assign rvclkhdr_45_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_46_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_46_io_en = bus_ifu_wr_en & _T_1291; // @[lib.scala 345:16] + assign rvclkhdr_46_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_47_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_47_io_en = bus_ifu_wr_en & _T_1292; // @[lib.scala 345:16] + assign rvclkhdr_47_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_48_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_48_io_en = bus_ifu_wr_en & _T_1293; // @[lib.scala 345:16] + assign rvclkhdr_48_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_49_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_49_io_en = bus_ifu_wr_en & _T_1294; // @[lib.scala 345:16] + assign rvclkhdr_49_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_50_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_50_io_en = bus_ifu_wr_en & _T_1295; // @[lib.scala 345:16] + assign rvclkhdr_50_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_51_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_51_io_en = bus_ifu_wr_en & _T_1296; // @[lib.scala 345:16] + assign rvclkhdr_51_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_52_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_52_io_en = bus_ifu_wr_en & _T_1289; // @[lib.scala 345:16] + assign rvclkhdr_52_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_53_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_53_io_en = bus_ifu_wr_en & _T_1290; // @[lib.scala 345:16] + assign rvclkhdr_53_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_54_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_54_io_en = bus_ifu_wr_en & _T_1291; // @[lib.scala 345:16] + assign rvclkhdr_54_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_55_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_55_io_en = bus_ifu_wr_en & _T_1292; // @[lib.scala 345:16] + assign rvclkhdr_55_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_56_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_56_io_en = bus_ifu_wr_en & _T_1293; // @[lib.scala 345:16] + assign rvclkhdr_56_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_57_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_57_io_en = bus_ifu_wr_en & _T_1294; // @[lib.scala 345:16] + assign rvclkhdr_57_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_58_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_58_io_en = bus_ifu_wr_en & _T_1295; // @[lib.scala 345:16] + assign rvclkhdr_58_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_59_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_59_io_en = bus_ifu_wr_en & _T_1296; // @[lib.scala 345:16] + assign rvclkhdr_59_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_60_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_60_io_en = bus_ifu_wr_en & _T_1289; // @[lib.scala 345:16] + assign rvclkhdr_60_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_61_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_61_io_en = bus_ifu_wr_en & _T_1290; // @[lib.scala 345:16] + assign rvclkhdr_61_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_62_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_62_io_en = bus_ifu_wr_en & _T_1291; // @[lib.scala 345:16] + assign rvclkhdr_62_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_63_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_63_io_en = bus_ifu_wr_en & _T_1292; // @[lib.scala 345:16] + assign rvclkhdr_63_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_64_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_64_io_en = bus_ifu_wr_en & _T_1293; // @[lib.scala 345:16] + assign rvclkhdr_64_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_65_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_65_io_en = bus_ifu_wr_en & _T_1294; // @[lib.scala 345:16] + assign rvclkhdr_65_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_66_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_66_io_en = bus_ifu_wr_en & _T_1295; // @[lib.scala 345:16] + assign rvclkhdr_66_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_67_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_67_io_en = bus_ifu_wr_en & _T_1296; // @[lib.scala 345:16] + assign rvclkhdr_67_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_68_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_68_io_en = io_ifu_bus_clk_en; // @[lib.scala 345:16] + assign rvclkhdr_68_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_69_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_69_io_en = io_ifu_bus_clk_en | io_dec_mem_ctrl_dec_tlu_force_halt; // @[lib.scala 345:16] + assign rvclkhdr_69_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_70_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_70_io_en = ifu_status_wr_addr_ff[6:3] == 4'h0; // @[lib.scala 345:16] + assign rvclkhdr_70_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_71_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_71_io_en = ifu_status_wr_addr_ff[6:3] == 4'h1; // @[lib.scala 345:16] + assign rvclkhdr_71_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_72_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_72_io_en = ifu_status_wr_addr_ff[6:3] == 4'h2; // @[lib.scala 345:16] + assign rvclkhdr_72_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_73_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_73_io_en = ifu_status_wr_addr_ff[6:3] == 4'h3; // @[lib.scala 345:16] + assign rvclkhdr_73_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_74_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_74_io_en = ifu_status_wr_addr_ff[6:3] == 4'h4; // @[lib.scala 345:16] + assign rvclkhdr_74_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_75_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_75_io_en = ifu_status_wr_addr_ff[6:3] == 4'h5; // @[lib.scala 345:16] + assign rvclkhdr_75_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_76_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_76_io_en = ifu_status_wr_addr_ff[6:3] == 4'h6; // @[lib.scala 345:16] + assign rvclkhdr_76_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_77_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_77_io_en = ifu_status_wr_addr_ff[6:3] == 4'h7; // @[lib.scala 345:16] + assign rvclkhdr_77_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_78_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_78_io_en = ifu_status_wr_addr_ff[6:3] == 4'h8; // @[lib.scala 345:16] + assign rvclkhdr_78_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_79_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_79_io_en = ifu_status_wr_addr_ff[6:3] == 4'h9; // @[lib.scala 345:16] + assign rvclkhdr_79_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_80_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_80_io_en = ifu_status_wr_addr_ff[6:3] == 4'ha; // @[lib.scala 345:16] + assign rvclkhdr_80_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_81_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_81_io_en = ifu_status_wr_addr_ff[6:3] == 4'hb; // @[lib.scala 345:16] + assign rvclkhdr_81_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_82_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_82_io_en = ifu_status_wr_addr_ff[6:3] == 4'hc; // @[lib.scala 345:16] + assign rvclkhdr_82_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_83_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_83_io_en = ifu_status_wr_addr_ff[6:3] == 4'hd; // @[lib.scala 345:16] + assign rvclkhdr_83_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_84_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_84_io_en = ifu_status_wr_addr_ff[6:3] == 4'he; // @[lib.scala 345:16] + assign rvclkhdr_84_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_85_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_85_io_en = ifu_status_wr_addr_ff[6:3] == 4'hf; // @[lib.scala 345:16] + assign rvclkhdr_85_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_86_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_86_io_en = tag_valid_clken_0[0]; // @[lib.scala 345:16] + assign rvclkhdr_86_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_87_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_87_io_en = tag_valid_clken_0[1]; // @[lib.scala 345:16] + assign rvclkhdr_87_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_88_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_88_io_en = tag_valid_clken_1[0]; // @[lib.scala 345:16] + assign rvclkhdr_88_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_89_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_89_io_en = tag_valid_clken_1[1]; // @[lib.scala 345:16] + assign rvclkhdr_89_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_90_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_90_io_en = tag_valid_clken_2[0]; // @[lib.scala 345:16] + assign rvclkhdr_90_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_91_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_91_io_en = tag_valid_clken_2[1]; // @[lib.scala 345:16] + assign rvclkhdr_91_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_92_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_92_io_en = tag_valid_clken_3[0]; // @[lib.scala 345:16] + assign rvclkhdr_92_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_93_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_93_io_en = tag_valid_clken_3[1]; // @[lib.scala 345:16] + assign rvclkhdr_93_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -12951,2222 +12951,2222 @@ module ifu_bp_ctl( reg [31:0] _RAND_1037; reg [31:0] _RAND_1038; `endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_8_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_8_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_9_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_9_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_10_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_10_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_11_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_11_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_12_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_12_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_12_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_12_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_13_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_13_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_13_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_13_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_14_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_14_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_14_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_14_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_15_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_15_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_15_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_15_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_16_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_16_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_16_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_16_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_17_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_17_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_17_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_17_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_18_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_18_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_18_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_18_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_19_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_19_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_19_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_19_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_20_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_20_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_20_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_20_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_21_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_21_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_21_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_21_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_22_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_22_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_22_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_22_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_23_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_23_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_23_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_23_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_24_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_24_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_24_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_24_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_25_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_25_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_25_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_25_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_26_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_26_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_26_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_26_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_27_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_27_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_27_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_27_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_28_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_28_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_28_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_28_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_29_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_29_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_29_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_29_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_30_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_30_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_30_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_30_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_31_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_31_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_31_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_31_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_32_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_32_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_32_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_32_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_33_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_33_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_33_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_33_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_34_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_34_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_34_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_34_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_35_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_35_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_35_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_35_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_36_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_36_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_36_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_36_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_37_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_37_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_37_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_37_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_38_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_38_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_38_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_38_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_39_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_39_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_39_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_39_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_40_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_40_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_40_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_40_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_41_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_41_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_41_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_41_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_42_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_42_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_42_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_42_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_43_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_43_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_43_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_43_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_44_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_44_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_44_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_44_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_45_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_45_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_45_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_45_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_46_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_46_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_46_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_46_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_47_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_47_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_47_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_47_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_48_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_48_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_48_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_48_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_49_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_49_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_49_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_49_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_50_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_50_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_50_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_50_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_51_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_51_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_51_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_51_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_52_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_52_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_52_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_52_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_53_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_53_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_53_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_53_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_54_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_54_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_54_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_54_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_55_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_55_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_55_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_55_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_56_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_56_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_56_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_56_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_57_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_57_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_57_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_57_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_58_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_58_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_58_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_58_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_59_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_59_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_59_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_59_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_60_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_60_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_60_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_60_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_61_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_61_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_61_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_61_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_62_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_62_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_62_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_62_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_63_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_63_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_63_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_63_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_64_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_64_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_64_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_64_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_65_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_65_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_65_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_65_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_66_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_66_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_66_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_66_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_67_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_67_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_67_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_67_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_68_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_68_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_68_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_68_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_69_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_69_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_69_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_69_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_70_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_70_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_70_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_70_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_71_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_71_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_71_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_71_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_72_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_72_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_72_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_72_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_73_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_73_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_73_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_73_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_74_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_74_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_74_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_74_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_75_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_75_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_75_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_75_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_76_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_76_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_76_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_76_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_77_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_77_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_77_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_77_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_78_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_78_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_78_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_78_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_79_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_79_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_79_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_79_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_80_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_80_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_80_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_80_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_81_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_81_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_81_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_81_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_82_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_82_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_82_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_82_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_83_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_83_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_83_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_83_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_84_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_84_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_84_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_84_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_85_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_85_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_85_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_85_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_86_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_86_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_86_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_86_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_87_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_87_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_87_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_87_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_88_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_88_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_88_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_88_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_89_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_89_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_89_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_89_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_90_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_90_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_90_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_90_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_91_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_91_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_91_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_91_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_92_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_92_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_92_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_92_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_93_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_93_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_93_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_93_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_94_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_94_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_94_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_94_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_95_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_95_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_95_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_95_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_96_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_96_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_96_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_96_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_97_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_97_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_97_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_97_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_98_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_98_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_98_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_98_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_99_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_99_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_99_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_99_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_100_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_100_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_100_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_100_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_101_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_101_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_101_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_101_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_102_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_102_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_102_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_102_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_103_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_103_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_103_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_103_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_104_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_104_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_104_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_104_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_105_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_105_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_105_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_105_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_106_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_106_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_106_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_106_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_107_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_107_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_107_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_107_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_108_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_108_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_108_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_108_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_109_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_109_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_109_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_109_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_110_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_110_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_110_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_110_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_111_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_111_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_111_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_111_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_112_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_112_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_112_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_112_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_113_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_113_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_113_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_113_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_114_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_114_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_114_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_114_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_115_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_115_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_115_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_115_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_116_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_116_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_116_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_116_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_117_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_117_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_117_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_117_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_118_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_118_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_118_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_118_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_119_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_119_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_119_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_119_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_120_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_120_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_120_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_120_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_121_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_121_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_121_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_121_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_122_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_122_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_122_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_122_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_123_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_123_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_123_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_123_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_124_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_124_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_124_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_124_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_125_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_125_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_125_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_125_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_126_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_126_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_126_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_126_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_127_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_127_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_127_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_127_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_128_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_128_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_128_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_128_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_129_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_129_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_129_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_129_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_130_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_130_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_130_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_130_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_131_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_131_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_131_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_131_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_132_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_132_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_132_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_132_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_133_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_133_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_133_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_133_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_134_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_134_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_134_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_134_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_135_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_135_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_135_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_135_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_136_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_136_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_136_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_136_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_137_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_137_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_137_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_137_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_138_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_138_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_138_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_138_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_139_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_139_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_139_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_139_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_140_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_140_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_140_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_140_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_141_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_141_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_141_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_141_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_142_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_142_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_142_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_142_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_143_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_143_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_143_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_143_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_144_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_144_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_144_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_144_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_145_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_145_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_145_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_145_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_146_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_146_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_146_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_146_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_147_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_147_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_147_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_147_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_148_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_148_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_148_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_148_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_149_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_149_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_149_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_149_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_150_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_150_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_150_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_150_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_151_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_151_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_151_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_151_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_152_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_152_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_152_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_152_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_153_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_153_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_153_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_153_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_154_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_154_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_154_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_154_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_155_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_155_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_155_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_155_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_156_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_156_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_156_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_156_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_157_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_157_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_157_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_157_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_158_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_158_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_158_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_158_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_159_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_159_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_159_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_159_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_160_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_160_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_160_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_160_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_161_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_161_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_161_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_161_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_162_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_162_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_162_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_162_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_163_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_163_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_163_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_163_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_164_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_164_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_164_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_164_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_165_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_165_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_165_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_165_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_166_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_166_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_166_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_166_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_167_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_167_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_167_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_167_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_168_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_168_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_168_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_168_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_169_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_169_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_169_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_169_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_170_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_170_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_170_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_170_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_171_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_171_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_171_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_171_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_172_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_172_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_172_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_172_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_173_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_173_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_173_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_173_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_174_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_174_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_174_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_174_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_175_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_175_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_175_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_175_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_176_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_176_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_176_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_176_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_177_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_177_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_177_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_177_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_178_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_178_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_178_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_178_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_179_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_179_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_179_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_179_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_180_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_180_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_180_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_180_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_181_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_181_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_181_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_181_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_182_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_182_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_182_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_182_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_183_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_183_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_183_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_183_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_184_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_184_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_184_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_184_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_185_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_185_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_185_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_185_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_186_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_186_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_186_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_186_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_187_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_187_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_187_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_187_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_188_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_188_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_188_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_188_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_189_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_189_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_189_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_189_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_190_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_190_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_190_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_190_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_191_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_191_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_191_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_191_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_192_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_192_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_192_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_192_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_193_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_193_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_193_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_193_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_194_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_194_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_194_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_194_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_195_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_195_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_195_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_195_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_196_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_196_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_196_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_196_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_197_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_197_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_197_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_197_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_198_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_198_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_198_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_198_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_199_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_199_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_199_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_199_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_200_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_200_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_200_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_200_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_201_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_201_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_201_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_201_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_202_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_202_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_202_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_202_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_203_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_203_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_203_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_203_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_204_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_204_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_204_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_204_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_205_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_205_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_205_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_205_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_206_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_206_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_206_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_206_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_207_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_207_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_207_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_207_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_208_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_208_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_208_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_208_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_209_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_209_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_209_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_209_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_210_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_210_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_210_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_210_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_211_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_211_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_211_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_211_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_212_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_212_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_212_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_212_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_213_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_213_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_213_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_213_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_214_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_214_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_214_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_214_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_215_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_215_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_215_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_215_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_216_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_216_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_216_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_216_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_217_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_217_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_217_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_217_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_218_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_218_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_218_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_218_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_219_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_219_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_219_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_219_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_220_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_220_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_220_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_220_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_221_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_221_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_221_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_221_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_222_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_222_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_222_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_222_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_223_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_223_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_223_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_223_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_224_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_224_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_224_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_224_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_225_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_225_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_225_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_225_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_226_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_226_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_226_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_226_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_227_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_227_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_227_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_227_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_228_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_228_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_228_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_228_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_229_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_229_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_229_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_229_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_230_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_230_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_230_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_230_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_231_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_231_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_231_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_231_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_232_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_232_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_232_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_232_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_233_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_233_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_233_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_233_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_234_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_234_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_234_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_234_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_235_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_235_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_235_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_235_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_236_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_236_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_236_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_236_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_237_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_237_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_237_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_237_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_238_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_238_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_238_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_238_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_239_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_239_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_239_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_239_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_240_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_240_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_240_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_240_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_241_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_241_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_241_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_241_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_242_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_242_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_242_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_242_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_243_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_243_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_243_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_243_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_244_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_244_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_244_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_244_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_245_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_245_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_245_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_245_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_246_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_246_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_246_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_246_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_247_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_247_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_247_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_247_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_248_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_248_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_248_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_248_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_249_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_249_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_249_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_249_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_250_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_250_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_250_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_250_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_251_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_251_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_251_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_251_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_252_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_252_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_252_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_252_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_253_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_253_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_253_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_253_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_254_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_254_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_254_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_254_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_255_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_255_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_255_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_255_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_256_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_256_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_256_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_256_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_257_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_257_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_257_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_257_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_258_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_258_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_258_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_258_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_259_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_259_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_259_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_259_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_260_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_260_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_260_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_260_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_261_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_261_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_261_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_261_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_262_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_262_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_262_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_262_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_263_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_263_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_263_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_263_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_264_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_264_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_264_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_264_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_265_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_265_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_265_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_265_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_266_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_266_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_266_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_266_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_267_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_267_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_267_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_267_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_268_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_268_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_268_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_268_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_269_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_269_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_269_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_269_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_270_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_270_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_270_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_270_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_271_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_271_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_271_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_271_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_272_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_272_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_272_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_272_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_273_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_273_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_273_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_273_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_274_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_274_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_274_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_274_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_275_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_275_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_275_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_275_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_276_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_276_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_276_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_276_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_277_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_277_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_277_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_277_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_278_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_278_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_278_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_278_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_279_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_279_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_279_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_279_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_280_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_280_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_280_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_280_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_281_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_281_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_281_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_281_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_282_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_282_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_282_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_282_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_283_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_283_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_283_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_283_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_284_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_284_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_284_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_284_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_285_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_285_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_285_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_285_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_286_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_286_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_286_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_286_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_287_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_287_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_287_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_287_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_288_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_288_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_288_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_288_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_289_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_289_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_289_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_289_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_290_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_290_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_290_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_290_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_291_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_291_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_291_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_291_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_292_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_292_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_292_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_292_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_293_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_293_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_293_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_293_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_294_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_294_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_294_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_294_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_295_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_295_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_295_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_295_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_296_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_296_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_296_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_296_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_297_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_297_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_297_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_297_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_298_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_298_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_298_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_298_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_299_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_299_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_299_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_299_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_300_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_300_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_300_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_300_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_301_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_301_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_301_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_301_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_302_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_302_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_302_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_302_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_303_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_303_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_303_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_303_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_304_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_304_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_304_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_304_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_305_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_305_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_305_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_305_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_306_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_306_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_306_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_306_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_307_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_307_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_307_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_307_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_308_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_308_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_308_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_308_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_309_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_309_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_309_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_309_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_310_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_310_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_310_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_310_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_311_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_311_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_311_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_311_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_312_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_312_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_312_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_312_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_313_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_313_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_313_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_313_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_314_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_314_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_314_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_314_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_315_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_315_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_315_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_315_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_316_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_316_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_316_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_316_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_317_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_317_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_317_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_317_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_318_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_318_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_318_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_318_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_319_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_319_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_319_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_319_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_320_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_320_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_320_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_320_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_321_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_321_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_321_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_321_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_322_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_322_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_322_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_322_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_323_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_323_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_323_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_323_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_324_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_324_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_324_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_324_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_325_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_325_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_325_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_325_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_326_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_326_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_326_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_326_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_327_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_327_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_327_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_327_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_328_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_328_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_328_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_328_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_329_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_329_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_329_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_329_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_330_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_330_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_330_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_330_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_331_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_331_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_331_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_331_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_332_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_332_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_332_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_332_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_333_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_333_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_333_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_333_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_334_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_334_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_334_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_334_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_335_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_335_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_335_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_335_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_336_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_336_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_336_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_336_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_337_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_337_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_337_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_337_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_338_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_338_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_338_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_338_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_339_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_339_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_339_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_339_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_340_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_340_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_340_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_340_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_341_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_341_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_341_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_341_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_342_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_342_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_342_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_342_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_343_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_343_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_343_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_343_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_344_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_344_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_344_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_344_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_345_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_345_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_345_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_345_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_346_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_346_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_346_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_346_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_347_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_347_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_347_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_347_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_348_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_348_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_348_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_348_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_349_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_349_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_349_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_349_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_350_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_350_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_350_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_350_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_351_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_351_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_351_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_351_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_352_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_352_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_352_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_352_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_353_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_353_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_353_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_353_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_354_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_354_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_354_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_354_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_355_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_355_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_355_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_355_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_356_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_356_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_356_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_356_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_357_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_357_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_357_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_357_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_358_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_358_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_358_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_358_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_359_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_359_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_359_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_359_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_360_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_360_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_360_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_360_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_361_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_361_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_361_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_361_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_362_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_362_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_362_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_362_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_363_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_363_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_363_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_363_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_364_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_364_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_364_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_364_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_365_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_365_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_365_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_365_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_366_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_366_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_366_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_366_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_367_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_367_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_367_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_367_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_368_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_368_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_368_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_368_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_369_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_369_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_369_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_369_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_370_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_370_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_370_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_370_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_371_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_371_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_371_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_371_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_372_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_372_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_372_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_372_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_373_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_373_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_373_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_373_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_374_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_374_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_374_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_374_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_375_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_375_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_375_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_375_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_376_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_376_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_376_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_376_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_377_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_377_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_377_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_377_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_378_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_378_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_378_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_378_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_379_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_379_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_379_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_379_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_380_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_380_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_380_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_380_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_381_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_381_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_381_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_381_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_382_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_382_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_382_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_382_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_383_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_383_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_383_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_383_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_384_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_384_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_384_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_384_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_385_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_385_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_385_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_385_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_386_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_386_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_386_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_386_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_387_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_387_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_387_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_387_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_388_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_388_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_388_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_388_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_389_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_389_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_389_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_389_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_390_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_390_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_390_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_390_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_391_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_391_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_391_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_391_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_392_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_392_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_392_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_392_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_393_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_393_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_393_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_393_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_394_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_394_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_394_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_394_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_395_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_395_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_395_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_395_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_396_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_396_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_396_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_396_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_397_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_397_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_397_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_397_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_398_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_398_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_398_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_398_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_399_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_399_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_399_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_399_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_400_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_400_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_400_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_400_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_401_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_401_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_401_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_401_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_402_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_402_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_402_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_402_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_403_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_403_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_403_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_403_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_404_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_404_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_404_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_404_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_405_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_405_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_405_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_405_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_406_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_406_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_406_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_406_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_407_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_407_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_407_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_407_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_408_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_408_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_408_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_408_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_409_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_409_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_409_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_409_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_410_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_410_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_410_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_410_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_411_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_411_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_411_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_411_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_412_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_412_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_412_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_412_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_413_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_413_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_413_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_413_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_414_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_414_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_414_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_414_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_415_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_415_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_415_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_415_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_416_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_416_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_416_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_416_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_417_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_417_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_417_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_417_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_418_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_418_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_418_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_418_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_419_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_419_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_419_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_419_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_420_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_420_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_420_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_420_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_421_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_421_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_421_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_421_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_422_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_422_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_422_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_422_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_423_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_423_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_423_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_423_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_424_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_424_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_424_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_424_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_425_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_425_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_425_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_425_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_426_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_426_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_426_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_426_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_427_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_427_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_427_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_427_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_428_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_428_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_428_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_428_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_429_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_429_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_429_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_429_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_430_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_430_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_430_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_430_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_431_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_431_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_431_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_431_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_432_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_432_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_432_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_432_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_433_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_433_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_433_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_433_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_434_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_434_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_434_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_434_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_435_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_435_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_435_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_435_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_436_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_436_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_436_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_436_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_437_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_437_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_437_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_437_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_438_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_438_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_438_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_438_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_439_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_439_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_439_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_439_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_440_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_440_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_440_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_440_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_441_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_441_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_441_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_441_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_442_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_442_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_442_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_442_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_443_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_443_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_443_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_443_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_444_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_444_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_444_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_444_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_445_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_445_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_445_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_445_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_446_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_446_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_446_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_446_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_447_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_447_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_447_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_447_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_448_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_448_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_448_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_448_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_449_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_449_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_449_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_449_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_450_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_450_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_450_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_450_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_451_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_451_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_451_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_451_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_452_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_452_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_452_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_452_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_453_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_453_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_453_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_453_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_454_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_454_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_454_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_454_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_455_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_455_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_455_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_455_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_456_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_456_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_456_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_456_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_457_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_457_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_457_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_457_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_458_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_458_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_458_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_458_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_459_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_459_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_459_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_459_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_460_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_460_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_460_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_460_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_461_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_461_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_461_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_461_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_462_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_462_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_462_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_462_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_463_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_463_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_463_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_463_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_464_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_464_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_464_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_464_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_465_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_465_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_465_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_465_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_466_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_466_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_466_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_466_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_467_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_467_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_467_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_467_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_468_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_468_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_468_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_468_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_469_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_469_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_469_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_469_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_470_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_470_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_470_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_470_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_471_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_471_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_471_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_471_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_472_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_472_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_472_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_472_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_473_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_473_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_473_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_473_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_474_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_474_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_474_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_474_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_475_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_475_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_475_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_475_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_476_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_476_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_476_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_476_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_477_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_477_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_477_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_477_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_478_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_478_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_478_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_478_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_479_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_479_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_479_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_479_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_480_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_480_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_480_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_480_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_481_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_481_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_481_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_481_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_482_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_482_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_482_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_482_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_483_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_483_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_483_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_483_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_484_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_484_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_484_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_484_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_485_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_485_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_485_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_485_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_486_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_486_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_486_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_486_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_487_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_487_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_487_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_487_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_488_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_488_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_488_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_488_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_489_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_489_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_489_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_489_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_490_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_490_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_490_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_490_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_491_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_491_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_491_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_491_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_492_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_492_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_492_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_492_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_493_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_493_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_493_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_493_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_494_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_494_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_494_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_494_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_495_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_495_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_495_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_495_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_496_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_496_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_496_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_496_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_497_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_497_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_497_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_497_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_498_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_498_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_498_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_498_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_499_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_499_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_499_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_499_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_500_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_500_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_500_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_500_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_501_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_501_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_501_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_501_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_502_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_502_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_502_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_502_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_503_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_503_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_503_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_503_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_504_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_504_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_504_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_504_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_505_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_505_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_505_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_505_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_506_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_506_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_506_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_506_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_507_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_507_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_507_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_507_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_508_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_508_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_508_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_508_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_509_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_509_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_509_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_509_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_510_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_510_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_510_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_510_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_511_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_511_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_511_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_511_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_512_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_512_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_512_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_512_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_513_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_513_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_513_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_513_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_514_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_514_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_514_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_514_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_515_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_515_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_515_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_515_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_516_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_516_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_516_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_516_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_517_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_517_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_517_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_517_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_518_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_518_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_518_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_518_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_519_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_519_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_519_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_519_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_520_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_520_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_520_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_520_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_521_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_521_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_521_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_521_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_522_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_522_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_522_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_522_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_523_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_523_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_523_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_523_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_524_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_524_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_524_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_524_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_525_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_525_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_525_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_525_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_526_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_526_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_526_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_526_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_527_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_527_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_527_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_527_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_528_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_528_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_528_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_528_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_529_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_529_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_529_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_529_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_530_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_530_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_530_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_530_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_531_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_531_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_531_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_531_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_532_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_532_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_532_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_532_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_533_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_533_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_533_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_533_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_534_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_534_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_534_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_534_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_535_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_535_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_535_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_535_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_536_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_536_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_536_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_536_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_537_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_537_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_537_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_537_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_538_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_538_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_538_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_538_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_539_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_539_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_539_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_539_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_540_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_540_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_540_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_540_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_541_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_541_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_541_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_541_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_542_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_542_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_542_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_542_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_543_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_543_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_543_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_543_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_544_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_544_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_544_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_544_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_545_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_545_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_545_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_545_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_546_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_546_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_546_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_546_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_547_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_547_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_547_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_547_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_548_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_548_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_548_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_548_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_549_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_549_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_549_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_549_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_550_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_550_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_550_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_550_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_551_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_551_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_551_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_551_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_552_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_552_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_552_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_552_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_553_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_553_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_553_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_553_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_io_en; // @[lib.scala 368:23] + wire rvclkhdr_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_en; // @[lib.scala 368:23] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_en; // @[lib.scala 368:23] + wire rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_en; // @[lib.scala 368:23] + wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_en; // @[lib.scala 368:23] + wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_5_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_en; // @[lib.scala 368:23] + wire rvclkhdr_5_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_6_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_6_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_6_io_en; // @[lib.scala 368:23] + wire rvclkhdr_6_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_7_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_7_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_7_io_en; // @[lib.scala 368:23] + wire rvclkhdr_7_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_8_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_8_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_8_io_en; // @[lib.scala 368:23] + wire rvclkhdr_8_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_9_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_9_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_9_io_en; // @[lib.scala 368:23] + wire rvclkhdr_9_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_10_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_10_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_10_io_en; // @[lib.scala 368:23] + wire rvclkhdr_10_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_11_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_11_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_11_io_en; // @[lib.scala 368:23] + wire rvclkhdr_11_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_12_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_12_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_12_io_en; // @[lib.scala 368:23] + wire rvclkhdr_12_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_13_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_13_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_13_io_en; // @[lib.scala 368:23] + wire rvclkhdr_13_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_14_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_14_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_14_io_en; // @[lib.scala 368:23] + wire rvclkhdr_14_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_15_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_15_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_15_io_en; // @[lib.scala 368:23] + wire rvclkhdr_15_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_16_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_16_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_16_io_en; // @[lib.scala 368:23] + wire rvclkhdr_16_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_17_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_17_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_17_io_en; // @[lib.scala 368:23] + wire rvclkhdr_17_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_18_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_18_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_18_io_en; // @[lib.scala 368:23] + wire rvclkhdr_18_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_19_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_19_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_19_io_en; // @[lib.scala 368:23] + wire rvclkhdr_19_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_20_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_20_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_20_io_en; // @[lib.scala 368:23] + wire rvclkhdr_20_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_21_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_21_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_21_io_en; // @[lib.scala 368:23] + wire rvclkhdr_21_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_22_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_22_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_22_io_en; // @[lib.scala 368:23] + wire rvclkhdr_22_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_23_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_23_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_23_io_en; // @[lib.scala 368:23] + wire rvclkhdr_23_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_24_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_24_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_24_io_en; // @[lib.scala 368:23] + wire rvclkhdr_24_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_25_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_25_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_25_io_en; // @[lib.scala 368:23] + wire rvclkhdr_25_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_26_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_26_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_26_io_en; // @[lib.scala 368:23] + wire rvclkhdr_26_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_27_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_27_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_27_io_en; // @[lib.scala 368:23] + wire rvclkhdr_27_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_28_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_28_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_28_io_en; // @[lib.scala 368:23] + wire rvclkhdr_28_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_29_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_29_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_29_io_en; // @[lib.scala 368:23] + wire rvclkhdr_29_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_30_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_30_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_30_io_en; // @[lib.scala 368:23] + wire rvclkhdr_30_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_31_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_31_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_31_io_en; // @[lib.scala 368:23] + wire rvclkhdr_31_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_32_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_32_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_32_io_en; // @[lib.scala 368:23] + wire rvclkhdr_32_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_33_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_33_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_33_io_en; // @[lib.scala 368:23] + wire rvclkhdr_33_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_34_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_34_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_34_io_en; // @[lib.scala 368:23] + wire rvclkhdr_34_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_35_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_35_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_35_io_en; // @[lib.scala 368:23] + wire rvclkhdr_35_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_36_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_36_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_36_io_en; // @[lib.scala 368:23] + wire rvclkhdr_36_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_37_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_37_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_37_io_en; // @[lib.scala 368:23] + wire rvclkhdr_37_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_38_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_38_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_38_io_en; // @[lib.scala 368:23] + wire rvclkhdr_38_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_39_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_39_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_39_io_en; // @[lib.scala 368:23] + wire rvclkhdr_39_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_40_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_40_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_40_io_en; // @[lib.scala 368:23] + wire rvclkhdr_40_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_41_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_41_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_41_io_en; // @[lib.scala 368:23] + wire rvclkhdr_41_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_42_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_42_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_42_io_en; // @[lib.scala 368:23] + wire rvclkhdr_42_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_43_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_43_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_43_io_en; // @[lib.scala 368:23] + wire rvclkhdr_43_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_44_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_44_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_44_io_en; // @[lib.scala 368:23] + wire rvclkhdr_44_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_45_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_45_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_45_io_en; // @[lib.scala 368:23] + wire rvclkhdr_45_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_46_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_46_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_46_io_en; // @[lib.scala 368:23] + wire rvclkhdr_46_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_47_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_47_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_47_io_en; // @[lib.scala 368:23] + wire rvclkhdr_47_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_48_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_48_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_48_io_en; // @[lib.scala 368:23] + wire rvclkhdr_48_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_49_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_49_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_49_io_en; // @[lib.scala 368:23] + wire rvclkhdr_49_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_50_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_50_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_50_io_en; // @[lib.scala 368:23] + wire rvclkhdr_50_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_51_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_51_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_51_io_en; // @[lib.scala 368:23] + wire rvclkhdr_51_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_52_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_52_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_52_io_en; // @[lib.scala 368:23] + wire rvclkhdr_52_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_53_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_53_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_53_io_en; // @[lib.scala 368:23] + wire rvclkhdr_53_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_54_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_54_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_54_io_en; // @[lib.scala 368:23] + wire rvclkhdr_54_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_55_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_55_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_55_io_en; // @[lib.scala 368:23] + wire rvclkhdr_55_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_56_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_56_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_56_io_en; // @[lib.scala 368:23] + wire rvclkhdr_56_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_57_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_57_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_57_io_en; // @[lib.scala 368:23] + wire rvclkhdr_57_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_58_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_58_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_58_io_en; // @[lib.scala 368:23] + wire rvclkhdr_58_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_59_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_59_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_59_io_en; // @[lib.scala 368:23] + wire rvclkhdr_59_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_60_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_60_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_60_io_en; // @[lib.scala 368:23] + wire rvclkhdr_60_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_61_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_61_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_61_io_en; // @[lib.scala 368:23] + wire rvclkhdr_61_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_62_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_62_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_62_io_en; // @[lib.scala 368:23] + wire rvclkhdr_62_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_63_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_63_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_63_io_en; // @[lib.scala 368:23] + wire rvclkhdr_63_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_64_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_64_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_64_io_en; // @[lib.scala 368:23] + wire rvclkhdr_64_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_65_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_65_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_65_io_en; // @[lib.scala 368:23] + wire rvclkhdr_65_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_66_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_66_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_66_io_en; // @[lib.scala 368:23] + wire rvclkhdr_66_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_67_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_67_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_67_io_en; // @[lib.scala 368:23] + wire rvclkhdr_67_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_68_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_68_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_68_io_en; // @[lib.scala 368:23] + wire rvclkhdr_68_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_69_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_69_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_69_io_en; // @[lib.scala 368:23] + wire rvclkhdr_69_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_70_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_70_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_70_io_en; // @[lib.scala 368:23] + wire rvclkhdr_70_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_71_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_71_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_71_io_en; // @[lib.scala 368:23] + wire rvclkhdr_71_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_72_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_72_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_72_io_en; // @[lib.scala 368:23] + wire rvclkhdr_72_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_73_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_73_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_73_io_en; // @[lib.scala 368:23] + wire rvclkhdr_73_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_74_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_74_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_74_io_en; // @[lib.scala 368:23] + wire rvclkhdr_74_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_75_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_75_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_75_io_en; // @[lib.scala 368:23] + wire rvclkhdr_75_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_76_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_76_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_76_io_en; // @[lib.scala 368:23] + wire rvclkhdr_76_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_77_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_77_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_77_io_en; // @[lib.scala 368:23] + wire rvclkhdr_77_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_78_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_78_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_78_io_en; // @[lib.scala 368:23] + wire rvclkhdr_78_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_79_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_79_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_79_io_en; // @[lib.scala 368:23] + wire rvclkhdr_79_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_80_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_80_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_80_io_en; // @[lib.scala 368:23] + wire rvclkhdr_80_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_81_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_81_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_81_io_en; // @[lib.scala 368:23] + wire rvclkhdr_81_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_82_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_82_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_82_io_en; // @[lib.scala 368:23] + wire rvclkhdr_82_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_83_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_83_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_83_io_en; // @[lib.scala 368:23] + wire rvclkhdr_83_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_84_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_84_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_84_io_en; // @[lib.scala 368:23] + wire rvclkhdr_84_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_85_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_85_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_85_io_en; // @[lib.scala 368:23] + wire rvclkhdr_85_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_86_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_86_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_86_io_en; // @[lib.scala 368:23] + wire rvclkhdr_86_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_87_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_87_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_87_io_en; // @[lib.scala 368:23] + wire rvclkhdr_87_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_88_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_88_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_88_io_en; // @[lib.scala 368:23] + wire rvclkhdr_88_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_89_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_89_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_89_io_en; // @[lib.scala 368:23] + wire rvclkhdr_89_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_90_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_90_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_90_io_en; // @[lib.scala 368:23] + wire rvclkhdr_90_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_91_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_91_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_91_io_en; // @[lib.scala 368:23] + wire rvclkhdr_91_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_92_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_92_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_92_io_en; // @[lib.scala 368:23] + wire rvclkhdr_92_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_93_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_93_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_93_io_en; // @[lib.scala 368:23] + wire rvclkhdr_93_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_94_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_94_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_94_io_en; // @[lib.scala 368:23] + wire rvclkhdr_94_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_95_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_95_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_95_io_en; // @[lib.scala 368:23] + wire rvclkhdr_95_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_96_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_96_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_96_io_en; // @[lib.scala 368:23] + wire rvclkhdr_96_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_97_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_97_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_97_io_en; // @[lib.scala 368:23] + wire rvclkhdr_97_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_98_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_98_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_98_io_en; // @[lib.scala 368:23] + wire rvclkhdr_98_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_99_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_99_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_99_io_en; // @[lib.scala 368:23] + wire rvclkhdr_99_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_100_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_100_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_100_io_en; // @[lib.scala 368:23] + wire rvclkhdr_100_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_101_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_101_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_101_io_en; // @[lib.scala 368:23] + wire rvclkhdr_101_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_102_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_102_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_102_io_en; // @[lib.scala 368:23] + wire rvclkhdr_102_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_103_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_103_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_103_io_en; // @[lib.scala 368:23] + wire rvclkhdr_103_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_104_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_104_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_104_io_en; // @[lib.scala 368:23] + wire rvclkhdr_104_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_105_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_105_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_105_io_en; // @[lib.scala 368:23] + wire rvclkhdr_105_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_106_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_106_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_106_io_en; // @[lib.scala 368:23] + wire rvclkhdr_106_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_107_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_107_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_107_io_en; // @[lib.scala 368:23] + wire rvclkhdr_107_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_108_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_108_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_108_io_en; // @[lib.scala 368:23] + wire rvclkhdr_108_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_109_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_109_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_109_io_en; // @[lib.scala 368:23] + wire rvclkhdr_109_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_110_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_110_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_110_io_en; // @[lib.scala 368:23] + wire rvclkhdr_110_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_111_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_111_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_111_io_en; // @[lib.scala 368:23] + wire rvclkhdr_111_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_112_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_112_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_112_io_en; // @[lib.scala 368:23] + wire rvclkhdr_112_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_113_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_113_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_113_io_en; // @[lib.scala 368:23] + wire rvclkhdr_113_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_114_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_114_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_114_io_en; // @[lib.scala 368:23] + wire rvclkhdr_114_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_115_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_115_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_115_io_en; // @[lib.scala 368:23] + wire rvclkhdr_115_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_116_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_116_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_116_io_en; // @[lib.scala 368:23] + wire rvclkhdr_116_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_117_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_117_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_117_io_en; // @[lib.scala 368:23] + wire rvclkhdr_117_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_118_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_118_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_118_io_en; // @[lib.scala 368:23] + wire rvclkhdr_118_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_119_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_119_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_119_io_en; // @[lib.scala 368:23] + wire rvclkhdr_119_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_120_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_120_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_120_io_en; // @[lib.scala 368:23] + wire rvclkhdr_120_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_121_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_121_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_121_io_en; // @[lib.scala 368:23] + wire rvclkhdr_121_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_122_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_122_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_122_io_en; // @[lib.scala 368:23] + wire rvclkhdr_122_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_123_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_123_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_123_io_en; // @[lib.scala 368:23] + wire rvclkhdr_123_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_124_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_124_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_124_io_en; // @[lib.scala 368:23] + wire rvclkhdr_124_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_125_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_125_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_125_io_en; // @[lib.scala 368:23] + wire rvclkhdr_125_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_126_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_126_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_126_io_en; // @[lib.scala 368:23] + wire rvclkhdr_126_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_127_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_127_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_127_io_en; // @[lib.scala 368:23] + wire rvclkhdr_127_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_128_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_128_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_128_io_en; // @[lib.scala 368:23] + wire rvclkhdr_128_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_129_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_129_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_129_io_en; // @[lib.scala 368:23] + wire rvclkhdr_129_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_130_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_130_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_130_io_en; // @[lib.scala 368:23] + wire rvclkhdr_130_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_131_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_131_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_131_io_en; // @[lib.scala 368:23] + wire rvclkhdr_131_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_132_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_132_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_132_io_en; // @[lib.scala 368:23] + wire rvclkhdr_132_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_133_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_133_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_133_io_en; // @[lib.scala 368:23] + wire rvclkhdr_133_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_134_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_134_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_134_io_en; // @[lib.scala 368:23] + wire rvclkhdr_134_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_135_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_135_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_135_io_en; // @[lib.scala 368:23] + wire rvclkhdr_135_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_136_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_136_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_136_io_en; // @[lib.scala 368:23] + wire rvclkhdr_136_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_137_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_137_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_137_io_en; // @[lib.scala 368:23] + wire rvclkhdr_137_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_138_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_138_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_138_io_en; // @[lib.scala 368:23] + wire rvclkhdr_138_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_139_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_139_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_139_io_en; // @[lib.scala 368:23] + wire rvclkhdr_139_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_140_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_140_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_140_io_en; // @[lib.scala 368:23] + wire rvclkhdr_140_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_141_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_141_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_141_io_en; // @[lib.scala 368:23] + wire rvclkhdr_141_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_142_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_142_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_142_io_en; // @[lib.scala 368:23] + wire rvclkhdr_142_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_143_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_143_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_143_io_en; // @[lib.scala 368:23] + wire rvclkhdr_143_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_144_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_144_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_144_io_en; // @[lib.scala 368:23] + wire rvclkhdr_144_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_145_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_145_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_145_io_en; // @[lib.scala 368:23] + wire rvclkhdr_145_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_146_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_146_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_146_io_en; // @[lib.scala 368:23] + wire rvclkhdr_146_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_147_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_147_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_147_io_en; // @[lib.scala 368:23] + wire rvclkhdr_147_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_148_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_148_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_148_io_en; // @[lib.scala 368:23] + wire rvclkhdr_148_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_149_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_149_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_149_io_en; // @[lib.scala 368:23] + wire rvclkhdr_149_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_150_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_150_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_150_io_en; // @[lib.scala 368:23] + wire rvclkhdr_150_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_151_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_151_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_151_io_en; // @[lib.scala 368:23] + wire rvclkhdr_151_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_152_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_152_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_152_io_en; // @[lib.scala 368:23] + wire rvclkhdr_152_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_153_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_153_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_153_io_en; // @[lib.scala 368:23] + wire rvclkhdr_153_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_154_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_154_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_154_io_en; // @[lib.scala 368:23] + wire rvclkhdr_154_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_155_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_155_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_155_io_en; // @[lib.scala 368:23] + wire rvclkhdr_155_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_156_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_156_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_156_io_en; // @[lib.scala 368:23] + wire rvclkhdr_156_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_157_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_157_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_157_io_en; // @[lib.scala 368:23] + wire rvclkhdr_157_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_158_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_158_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_158_io_en; // @[lib.scala 368:23] + wire rvclkhdr_158_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_159_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_159_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_159_io_en; // @[lib.scala 368:23] + wire rvclkhdr_159_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_160_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_160_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_160_io_en; // @[lib.scala 368:23] + wire rvclkhdr_160_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_161_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_161_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_161_io_en; // @[lib.scala 368:23] + wire rvclkhdr_161_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_162_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_162_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_162_io_en; // @[lib.scala 368:23] + wire rvclkhdr_162_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_163_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_163_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_163_io_en; // @[lib.scala 368:23] + wire rvclkhdr_163_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_164_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_164_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_164_io_en; // @[lib.scala 368:23] + wire rvclkhdr_164_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_165_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_165_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_165_io_en; // @[lib.scala 368:23] + wire rvclkhdr_165_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_166_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_166_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_166_io_en; // @[lib.scala 368:23] + wire rvclkhdr_166_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_167_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_167_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_167_io_en; // @[lib.scala 368:23] + wire rvclkhdr_167_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_168_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_168_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_168_io_en; // @[lib.scala 368:23] + wire rvclkhdr_168_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_169_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_169_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_169_io_en; // @[lib.scala 368:23] + wire rvclkhdr_169_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_170_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_170_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_170_io_en; // @[lib.scala 368:23] + wire rvclkhdr_170_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_171_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_171_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_171_io_en; // @[lib.scala 368:23] + wire rvclkhdr_171_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_172_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_172_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_172_io_en; // @[lib.scala 368:23] + wire rvclkhdr_172_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_173_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_173_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_173_io_en; // @[lib.scala 368:23] + wire rvclkhdr_173_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_174_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_174_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_174_io_en; // @[lib.scala 368:23] + wire rvclkhdr_174_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_175_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_175_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_175_io_en; // @[lib.scala 368:23] + wire rvclkhdr_175_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_176_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_176_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_176_io_en; // @[lib.scala 368:23] + wire rvclkhdr_176_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_177_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_177_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_177_io_en; // @[lib.scala 368:23] + wire rvclkhdr_177_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_178_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_178_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_178_io_en; // @[lib.scala 368:23] + wire rvclkhdr_178_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_179_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_179_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_179_io_en; // @[lib.scala 368:23] + wire rvclkhdr_179_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_180_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_180_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_180_io_en; // @[lib.scala 368:23] + wire rvclkhdr_180_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_181_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_181_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_181_io_en; // @[lib.scala 368:23] + wire rvclkhdr_181_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_182_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_182_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_182_io_en; // @[lib.scala 368:23] + wire rvclkhdr_182_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_183_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_183_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_183_io_en; // @[lib.scala 368:23] + wire rvclkhdr_183_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_184_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_184_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_184_io_en; // @[lib.scala 368:23] + wire rvclkhdr_184_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_185_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_185_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_185_io_en; // @[lib.scala 368:23] + wire rvclkhdr_185_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_186_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_186_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_186_io_en; // @[lib.scala 368:23] + wire rvclkhdr_186_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_187_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_187_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_187_io_en; // @[lib.scala 368:23] + wire rvclkhdr_187_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_188_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_188_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_188_io_en; // @[lib.scala 368:23] + wire rvclkhdr_188_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_189_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_189_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_189_io_en; // @[lib.scala 368:23] + wire rvclkhdr_189_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_190_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_190_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_190_io_en; // @[lib.scala 368:23] + wire rvclkhdr_190_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_191_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_191_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_191_io_en; // @[lib.scala 368:23] + wire rvclkhdr_191_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_192_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_192_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_192_io_en; // @[lib.scala 368:23] + wire rvclkhdr_192_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_193_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_193_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_193_io_en; // @[lib.scala 368:23] + wire rvclkhdr_193_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_194_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_194_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_194_io_en; // @[lib.scala 368:23] + wire rvclkhdr_194_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_195_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_195_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_195_io_en; // @[lib.scala 368:23] + wire rvclkhdr_195_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_196_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_196_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_196_io_en; // @[lib.scala 368:23] + wire rvclkhdr_196_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_197_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_197_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_197_io_en; // @[lib.scala 368:23] + wire rvclkhdr_197_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_198_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_198_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_198_io_en; // @[lib.scala 368:23] + wire rvclkhdr_198_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_199_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_199_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_199_io_en; // @[lib.scala 368:23] + wire rvclkhdr_199_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_200_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_200_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_200_io_en; // @[lib.scala 368:23] + wire rvclkhdr_200_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_201_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_201_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_201_io_en; // @[lib.scala 368:23] + wire rvclkhdr_201_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_202_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_202_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_202_io_en; // @[lib.scala 368:23] + wire rvclkhdr_202_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_203_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_203_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_203_io_en; // @[lib.scala 368:23] + wire rvclkhdr_203_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_204_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_204_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_204_io_en; // @[lib.scala 368:23] + wire rvclkhdr_204_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_205_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_205_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_205_io_en; // @[lib.scala 368:23] + wire rvclkhdr_205_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_206_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_206_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_206_io_en; // @[lib.scala 368:23] + wire rvclkhdr_206_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_207_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_207_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_207_io_en; // @[lib.scala 368:23] + wire rvclkhdr_207_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_208_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_208_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_208_io_en; // @[lib.scala 368:23] + wire rvclkhdr_208_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_209_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_209_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_209_io_en; // @[lib.scala 368:23] + wire rvclkhdr_209_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_210_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_210_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_210_io_en; // @[lib.scala 368:23] + wire rvclkhdr_210_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_211_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_211_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_211_io_en; // @[lib.scala 368:23] + wire rvclkhdr_211_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_212_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_212_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_212_io_en; // @[lib.scala 368:23] + wire rvclkhdr_212_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_213_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_213_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_213_io_en; // @[lib.scala 368:23] + wire rvclkhdr_213_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_214_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_214_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_214_io_en; // @[lib.scala 368:23] + wire rvclkhdr_214_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_215_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_215_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_215_io_en; // @[lib.scala 368:23] + wire rvclkhdr_215_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_216_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_216_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_216_io_en; // @[lib.scala 368:23] + wire rvclkhdr_216_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_217_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_217_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_217_io_en; // @[lib.scala 368:23] + wire rvclkhdr_217_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_218_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_218_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_218_io_en; // @[lib.scala 368:23] + wire rvclkhdr_218_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_219_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_219_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_219_io_en; // @[lib.scala 368:23] + wire rvclkhdr_219_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_220_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_220_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_220_io_en; // @[lib.scala 368:23] + wire rvclkhdr_220_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_221_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_221_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_221_io_en; // @[lib.scala 368:23] + wire rvclkhdr_221_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_222_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_222_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_222_io_en; // @[lib.scala 368:23] + wire rvclkhdr_222_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_223_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_223_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_223_io_en; // @[lib.scala 368:23] + wire rvclkhdr_223_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_224_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_224_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_224_io_en; // @[lib.scala 368:23] + wire rvclkhdr_224_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_225_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_225_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_225_io_en; // @[lib.scala 368:23] + wire rvclkhdr_225_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_226_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_226_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_226_io_en; // @[lib.scala 368:23] + wire rvclkhdr_226_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_227_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_227_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_227_io_en; // @[lib.scala 368:23] + wire rvclkhdr_227_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_228_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_228_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_228_io_en; // @[lib.scala 368:23] + wire rvclkhdr_228_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_229_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_229_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_229_io_en; // @[lib.scala 368:23] + wire rvclkhdr_229_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_230_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_230_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_230_io_en; // @[lib.scala 368:23] + wire rvclkhdr_230_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_231_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_231_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_231_io_en; // @[lib.scala 368:23] + wire rvclkhdr_231_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_232_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_232_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_232_io_en; // @[lib.scala 368:23] + wire rvclkhdr_232_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_233_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_233_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_233_io_en; // @[lib.scala 368:23] + wire rvclkhdr_233_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_234_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_234_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_234_io_en; // @[lib.scala 368:23] + wire rvclkhdr_234_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_235_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_235_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_235_io_en; // @[lib.scala 368:23] + wire rvclkhdr_235_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_236_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_236_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_236_io_en; // @[lib.scala 368:23] + wire rvclkhdr_236_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_237_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_237_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_237_io_en; // @[lib.scala 368:23] + wire rvclkhdr_237_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_238_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_238_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_238_io_en; // @[lib.scala 368:23] + wire rvclkhdr_238_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_239_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_239_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_239_io_en; // @[lib.scala 368:23] + wire rvclkhdr_239_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_240_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_240_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_240_io_en; // @[lib.scala 368:23] + wire rvclkhdr_240_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_241_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_241_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_241_io_en; // @[lib.scala 368:23] + wire rvclkhdr_241_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_242_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_242_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_242_io_en; // @[lib.scala 368:23] + wire rvclkhdr_242_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_243_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_243_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_243_io_en; // @[lib.scala 368:23] + wire rvclkhdr_243_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_244_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_244_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_244_io_en; // @[lib.scala 368:23] + wire rvclkhdr_244_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_245_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_245_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_245_io_en; // @[lib.scala 368:23] + wire rvclkhdr_245_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_246_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_246_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_246_io_en; // @[lib.scala 368:23] + wire rvclkhdr_246_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_247_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_247_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_247_io_en; // @[lib.scala 368:23] + wire rvclkhdr_247_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_248_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_248_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_248_io_en; // @[lib.scala 368:23] + wire rvclkhdr_248_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_249_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_249_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_249_io_en; // @[lib.scala 368:23] + wire rvclkhdr_249_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_250_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_250_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_250_io_en; // @[lib.scala 368:23] + wire rvclkhdr_250_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_251_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_251_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_251_io_en; // @[lib.scala 368:23] + wire rvclkhdr_251_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_252_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_252_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_252_io_en; // @[lib.scala 368:23] + wire rvclkhdr_252_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_253_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_253_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_253_io_en; // @[lib.scala 368:23] + wire rvclkhdr_253_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_254_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_254_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_254_io_en; // @[lib.scala 368:23] + wire rvclkhdr_254_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_255_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_255_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_255_io_en; // @[lib.scala 368:23] + wire rvclkhdr_255_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_256_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_256_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_256_io_en; // @[lib.scala 368:23] + wire rvclkhdr_256_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_257_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_257_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_257_io_en; // @[lib.scala 368:23] + wire rvclkhdr_257_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_258_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_258_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_258_io_en; // @[lib.scala 368:23] + wire rvclkhdr_258_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_259_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_259_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_259_io_en; // @[lib.scala 368:23] + wire rvclkhdr_259_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_260_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_260_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_260_io_en; // @[lib.scala 368:23] + wire rvclkhdr_260_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_261_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_261_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_261_io_en; // @[lib.scala 368:23] + wire rvclkhdr_261_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_262_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_262_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_262_io_en; // @[lib.scala 368:23] + wire rvclkhdr_262_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_263_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_263_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_263_io_en; // @[lib.scala 368:23] + wire rvclkhdr_263_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_264_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_264_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_264_io_en; // @[lib.scala 368:23] + wire rvclkhdr_264_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_265_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_265_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_265_io_en; // @[lib.scala 368:23] + wire rvclkhdr_265_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_266_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_266_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_266_io_en; // @[lib.scala 368:23] + wire rvclkhdr_266_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_267_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_267_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_267_io_en; // @[lib.scala 368:23] + wire rvclkhdr_267_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_268_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_268_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_268_io_en; // @[lib.scala 368:23] + wire rvclkhdr_268_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_269_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_269_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_269_io_en; // @[lib.scala 368:23] + wire rvclkhdr_269_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_270_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_270_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_270_io_en; // @[lib.scala 368:23] + wire rvclkhdr_270_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_271_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_271_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_271_io_en; // @[lib.scala 368:23] + wire rvclkhdr_271_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_272_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_272_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_272_io_en; // @[lib.scala 368:23] + wire rvclkhdr_272_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_273_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_273_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_273_io_en; // @[lib.scala 368:23] + wire rvclkhdr_273_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_274_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_274_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_274_io_en; // @[lib.scala 368:23] + wire rvclkhdr_274_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_275_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_275_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_275_io_en; // @[lib.scala 368:23] + wire rvclkhdr_275_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_276_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_276_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_276_io_en; // @[lib.scala 368:23] + wire rvclkhdr_276_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_277_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_277_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_277_io_en; // @[lib.scala 368:23] + wire rvclkhdr_277_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_278_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_278_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_278_io_en; // @[lib.scala 368:23] + wire rvclkhdr_278_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_279_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_279_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_279_io_en; // @[lib.scala 368:23] + wire rvclkhdr_279_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_280_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_280_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_280_io_en; // @[lib.scala 368:23] + wire rvclkhdr_280_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_281_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_281_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_281_io_en; // @[lib.scala 368:23] + wire rvclkhdr_281_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_282_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_282_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_282_io_en; // @[lib.scala 368:23] + wire rvclkhdr_282_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_283_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_283_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_283_io_en; // @[lib.scala 368:23] + wire rvclkhdr_283_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_284_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_284_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_284_io_en; // @[lib.scala 368:23] + wire rvclkhdr_284_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_285_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_285_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_285_io_en; // @[lib.scala 368:23] + wire rvclkhdr_285_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_286_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_286_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_286_io_en; // @[lib.scala 368:23] + wire rvclkhdr_286_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_287_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_287_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_287_io_en; // @[lib.scala 368:23] + wire rvclkhdr_287_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_288_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_288_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_288_io_en; // @[lib.scala 368:23] + wire rvclkhdr_288_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_289_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_289_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_289_io_en; // @[lib.scala 368:23] + wire rvclkhdr_289_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_290_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_290_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_290_io_en; // @[lib.scala 368:23] + wire rvclkhdr_290_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_291_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_291_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_291_io_en; // @[lib.scala 368:23] + wire rvclkhdr_291_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_292_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_292_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_292_io_en; // @[lib.scala 368:23] + wire rvclkhdr_292_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_293_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_293_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_293_io_en; // @[lib.scala 368:23] + wire rvclkhdr_293_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_294_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_294_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_294_io_en; // @[lib.scala 368:23] + wire rvclkhdr_294_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_295_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_295_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_295_io_en; // @[lib.scala 368:23] + wire rvclkhdr_295_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_296_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_296_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_296_io_en; // @[lib.scala 368:23] + wire rvclkhdr_296_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_297_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_297_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_297_io_en; // @[lib.scala 368:23] + wire rvclkhdr_297_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_298_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_298_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_298_io_en; // @[lib.scala 368:23] + wire rvclkhdr_298_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_299_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_299_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_299_io_en; // @[lib.scala 368:23] + wire rvclkhdr_299_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_300_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_300_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_300_io_en; // @[lib.scala 368:23] + wire rvclkhdr_300_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_301_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_301_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_301_io_en; // @[lib.scala 368:23] + wire rvclkhdr_301_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_302_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_302_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_302_io_en; // @[lib.scala 368:23] + wire rvclkhdr_302_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_303_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_303_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_303_io_en; // @[lib.scala 368:23] + wire rvclkhdr_303_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_304_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_304_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_304_io_en; // @[lib.scala 368:23] + wire rvclkhdr_304_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_305_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_305_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_305_io_en; // @[lib.scala 368:23] + wire rvclkhdr_305_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_306_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_306_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_306_io_en; // @[lib.scala 368:23] + wire rvclkhdr_306_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_307_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_307_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_307_io_en; // @[lib.scala 368:23] + wire rvclkhdr_307_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_308_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_308_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_308_io_en; // @[lib.scala 368:23] + wire rvclkhdr_308_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_309_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_309_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_309_io_en; // @[lib.scala 368:23] + wire rvclkhdr_309_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_310_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_310_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_310_io_en; // @[lib.scala 368:23] + wire rvclkhdr_310_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_311_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_311_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_311_io_en; // @[lib.scala 368:23] + wire rvclkhdr_311_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_312_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_312_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_312_io_en; // @[lib.scala 368:23] + wire rvclkhdr_312_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_313_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_313_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_313_io_en; // @[lib.scala 368:23] + wire rvclkhdr_313_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_314_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_314_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_314_io_en; // @[lib.scala 368:23] + wire rvclkhdr_314_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_315_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_315_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_315_io_en; // @[lib.scala 368:23] + wire rvclkhdr_315_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_316_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_316_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_316_io_en; // @[lib.scala 368:23] + wire rvclkhdr_316_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_317_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_317_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_317_io_en; // @[lib.scala 368:23] + wire rvclkhdr_317_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_318_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_318_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_318_io_en; // @[lib.scala 368:23] + wire rvclkhdr_318_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_319_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_319_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_319_io_en; // @[lib.scala 368:23] + wire rvclkhdr_319_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_320_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_320_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_320_io_en; // @[lib.scala 368:23] + wire rvclkhdr_320_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_321_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_321_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_321_io_en; // @[lib.scala 368:23] + wire rvclkhdr_321_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_322_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_322_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_322_io_en; // @[lib.scala 368:23] + wire rvclkhdr_322_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_323_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_323_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_323_io_en; // @[lib.scala 368:23] + wire rvclkhdr_323_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_324_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_324_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_324_io_en; // @[lib.scala 368:23] + wire rvclkhdr_324_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_325_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_325_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_325_io_en; // @[lib.scala 368:23] + wire rvclkhdr_325_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_326_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_326_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_326_io_en; // @[lib.scala 368:23] + wire rvclkhdr_326_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_327_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_327_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_327_io_en; // @[lib.scala 368:23] + wire rvclkhdr_327_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_328_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_328_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_328_io_en; // @[lib.scala 368:23] + wire rvclkhdr_328_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_329_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_329_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_329_io_en; // @[lib.scala 368:23] + wire rvclkhdr_329_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_330_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_330_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_330_io_en; // @[lib.scala 368:23] + wire rvclkhdr_330_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_331_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_331_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_331_io_en; // @[lib.scala 368:23] + wire rvclkhdr_331_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_332_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_332_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_332_io_en; // @[lib.scala 368:23] + wire rvclkhdr_332_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_333_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_333_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_333_io_en; // @[lib.scala 368:23] + wire rvclkhdr_333_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_334_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_334_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_334_io_en; // @[lib.scala 368:23] + wire rvclkhdr_334_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_335_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_335_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_335_io_en; // @[lib.scala 368:23] + wire rvclkhdr_335_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_336_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_336_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_336_io_en; // @[lib.scala 368:23] + wire rvclkhdr_336_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_337_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_337_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_337_io_en; // @[lib.scala 368:23] + wire rvclkhdr_337_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_338_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_338_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_338_io_en; // @[lib.scala 368:23] + wire rvclkhdr_338_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_339_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_339_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_339_io_en; // @[lib.scala 368:23] + wire rvclkhdr_339_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_340_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_340_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_340_io_en; // @[lib.scala 368:23] + wire rvclkhdr_340_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_341_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_341_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_341_io_en; // @[lib.scala 368:23] + wire rvclkhdr_341_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_342_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_342_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_342_io_en; // @[lib.scala 368:23] + wire rvclkhdr_342_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_343_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_343_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_343_io_en; // @[lib.scala 368:23] + wire rvclkhdr_343_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_344_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_344_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_344_io_en; // @[lib.scala 368:23] + wire rvclkhdr_344_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_345_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_345_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_345_io_en; // @[lib.scala 368:23] + wire rvclkhdr_345_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_346_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_346_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_346_io_en; // @[lib.scala 368:23] + wire rvclkhdr_346_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_347_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_347_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_347_io_en; // @[lib.scala 368:23] + wire rvclkhdr_347_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_348_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_348_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_348_io_en; // @[lib.scala 368:23] + wire rvclkhdr_348_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_349_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_349_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_349_io_en; // @[lib.scala 368:23] + wire rvclkhdr_349_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_350_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_350_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_350_io_en; // @[lib.scala 368:23] + wire rvclkhdr_350_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_351_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_351_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_351_io_en; // @[lib.scala 368:23] + wire rvclkhdr_351_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_352_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_352_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_352_io_en; // @[lib.scala 368:23] + wire rvclkhdr_352_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_353_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_353_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_353_io_en; // @[lib.scala 368:23] + wire rvclkhdr_353_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_354_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_354_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_354_io_en; // @[lib.scala 368:23] + wire rvclkhdr_354_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_355_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_355_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_355_io_en; // @[lib.scala 368:23] + wire rvclkhdr_355_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_356_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_356_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_356_io_en; // @[lib.scala 368:23] + wire rvclkhdr_356_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_357_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_357_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_357_io_en; // @[lib.scala 368:23] + wire rvclkhdr_357_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_358_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_358_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_358_io_en; // @[lib.scala 368:23] + wire rvclkhdr_358_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_359_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_359_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_359_io_en; // @[lib.scala 368:23] + wire rvclkhdr_359_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_360_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_360_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_360_io_en; // @[lib.scala 368:23] + wire rvclkhdr_360_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_361_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_361_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_361_io_en; // @[lib.scala 368:23] + wire rvclkhdr_361_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_362_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_362_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_362_io_en; // @[lib.scala 368:23] + wire rvclkhdr_362_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_363_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_363_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_363_io_en; // @[lib.scala 368:23] + wire rvclkhdr_363_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_364_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_364_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_364_io_en; // @[lib.scala 368:23] + wire rvclkhdr_364_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_365_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_365_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_365_io_en; // @[lib.scala 368:23] + wire rvclkhdr_365_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_366_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_366_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_366_io_en; // @[lib.scala 368:23] + wire rvclkhdr_366_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_367_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_367_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_367_io_en; // @[lib.scala 368:23] + wire rvclkhdr_367_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_368_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_368_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_368_io_en; // @[lib.scala 368:23] + wire rvclkhdr_368_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_369_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_369_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_369_io_en; // @[lib.scala 368:23] + wire rvclkhdr_369_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_370_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_370_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_370_io_en; // @[lib.scala 368:23] + wire rvclkhdr_370_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_371_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_371_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_371_io_en; // @[lib.scala 368:23] + wire rvclkhdr_371_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_372_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_372_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_372_io_en; // @[lib.scala 368:23] + wire rvclkhdr_372_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_373_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_373_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_373_io_en; // @[lib.scala 368:23] + wire rvclkhdr_373_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_374_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_374_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_374_io_en; // @[lib.scala 368:23] + wire rvclkhdr_374_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_375_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_375_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_375_io_en; // @[lib.scala 368:23] + wire rvclkhdr_375_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_376_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_376_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_376_io_en; // @[lib.scala 368:23] + wire rvclkhdr_376_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_377_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_377_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_377_io_en; // @[lib.scala 368:23] + wire rvclkhdr_377_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_378_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_378_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_378_io_en; // @[lib.scala 368:23] + wire rvclkhdr_378_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_379_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_379_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_379_io_en; // @[lib.scala 368:23] + wire rvclkhdr_379_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_380_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_380_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_380_io_en; // @[lib.scala 368:23] + wire rvclkhdr_380_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_381_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_381_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_381_io_en; // @[lib.scala 368:23] + wire rvclkhdr_381_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_382_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_382_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_382_io_en; // @[lib.scala 368:23] + wire rvclkhdr_382_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_383_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_383_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_383_io_en; // @[lib.scala 368:23] + wire rvclkhdr_383_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_384_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_384_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_384_io_en; // @[lib.scala 368:23] + wire rvclkhdr_384_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_385_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_385_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_385_io_en; // @[lib.scala 368:23] + wire rvclkhdr_385_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_386_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_386_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_386_io_en; // @[lib.scala 368:23] + wire rvclkhdr_386_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_387_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_387_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_387_io_en; // @[lib.scala 368:23] + wire rvclkhdr_387_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_388_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_388_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_388_io_en; // @[lib.scala 368:23] + wire rvclkhdr_388_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_389_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_389_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_389_io_en; // @[lib.scala 368:23] + wire rvclkhdr_389_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_390_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_390_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_390_io_en; // @[lib.scala 368:23] + wire rvclkhdr_390_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_391_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_391_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_391_io_en; // @[lib.scala 368:23] + wire rvclkhdr_391_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_392_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_392_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_392_io_en; // @[lib.scala 368:23] + wire rvclkhdr_392_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_393_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_393_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_393_io_en; // @[lib.scala 368:23] + wire rvclkhdr_393_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_394_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_394_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_394_io_en; // @[lib.scala 368:23] + wire rvclkhdr_394_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_395_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_395_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_395_io_en; // @[lib.scala 368:23] + wire rvclkhdr_395_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_396_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_396_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_396_io_en; // @[lib.scala 368:23] + wire rvclkhdr_396_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_397_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_397_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_397_io_en; // @[lib.scala 368:23] + wire rvclkhdr_397_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_398_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_398_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_398_io_en; // @[lib.scala 368:23] + wire rvclkhdr_398_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_399_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_399_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_399_io_en; // @[lib.scala 368:23] + wire rvclkhdr_399_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_400_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_400_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_400_io_en; // @[lib.scala 368:23] + wire rvclkhdr_400_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_401_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_401_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_401_io_en; // @[lib.scala 368:23] + wire rvclkhdr_401_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_402_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_402_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_402_io_en; // @[lib.scala 368:23] + wire rvclkhdr_402_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_403_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_403_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_403_io_en; // @[lib.scala 368:23] + wire rvclkhdr_403_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_404_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_404_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_404_io_en; // @[lib.scala 368:23] + wire rvclkhdr_404_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_405_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_405_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_405_io_en; // @[lib.scala 368:23] + wire rvclkhdr_405_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_406_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_406_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_406_io_en; // @[lib.scala 368:23] + wire rvclkhdr_406_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_407_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_407_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_407_io_en; // @[lib.scala 368:23] + wire rvclkhdr_407_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_408_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_408_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_408_io_en; // @[lib.scala 368:23] + wire rvclkhdr_408_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_409_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_409_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_409_io_en; // @[lib.scala 368:23] + wire rvclkhdr_409_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_410_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_410_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_410_io_en; // @[lib.scala 368:23] + wire rvclkhdr_410_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_411_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_411_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_411_io_en; // @[lib.scala 368:23] + wire rvclkhdr_411_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_412_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_412_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_412_io_en; // @[lib.scala 368:23] + wire rvclkhdr_412_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_413_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_413_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_413_io_en; // @[lib.scala 368:23] + wire rvclkhdr_413_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_414_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_414_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_414_io_en; // @[lib.scala 368:23] + wire rvclkhdr_414_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_415_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_415_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_415_io_en; // @[lib.scala 368:23] + wire rvclkhdr_415_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_416_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_416_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_416_io_en; // @[lib.scala 368:23] + wire rvclkhdr_416_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_417_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_417_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_417_io_en; // @[lib.scala 368:23] + wire rvclkhdr_417_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_418_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_418_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_418_io_en; // @[lib.scala 368:23] + wire rvclkhdr_418_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_419_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_419_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_419_io_en; // @[lib.scala 368:23] + wire rvclkhdr_419_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_420_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_420_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_420_io_en; // @[lib.scala 368:23] + wire rvclkhdr_420_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_421_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_421_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_421_io_en; // @[lib.scala 368:23] + wire rvclkhdr_421_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_422_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_422_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_422_io_en; // @[lib.scala 368:23] + wire rvclkhdr_422_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_423_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_423_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_423_io_en; // @[lib.scala 368:23] + wire rvclkhdr_423_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_424_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_424_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_424_io_en; // @[lib.scala 368:23] + wire rvclkhdr_424_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_425_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_425_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_425_io_en; // @[lib.scala 368:23] + wire rvclkhdr_425_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_426_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_426_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_426_io_en; // @[lib.scala 368:23] + wire rvclkhdr_426_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_427_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_427_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_427_io_en; // @[lib.scala 368:23] + wire rvclkhdr_427_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_428_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_428_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_428_io_en; // @[lib.scala 368:23] + wire rvclkhdr_428_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_429_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_429_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_429_io_en; // @[lib.scala 368:23] + wire rvclkhdr_429_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_430_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_430_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_430_io_en; // @[lib.scala 368:23] + wire rvclkhdr_430_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_431_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_431_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_431_io_en; // @[lib.scala 368:23] + wire rvclkhdr_431_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_432_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_432_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_432_io_en; // @[lib.scala 368:23] + wire rvclkhdr_432_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_433_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_433_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_433_io_en; // @[lib.scala 368:23] + wire rvclkhdr_433_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_434_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_434_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_434_io_en; // @[lib.scala 368:23] + wire rvclkhdr_434_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_435_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_435_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_435_io_en; // @[lib.scala 368:23] + wire rvclkhdr_435_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_436_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_436_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_436_io_en; // @[lib.scala 368:23] + wire rvclkhdr_436_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_437_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_437_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_437_io_en; // @[lib.scala 368:23] + wire rvclkhdr_437_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_438_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_438_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_438_io_en; // @[lib.scala 368:23] + wire rvclkhdr_438_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_439_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_439_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_439_io_en; // @[lib.scala 368:23] + wire rvclkhdr_439_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_440_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_440_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_440_io_en; // @[lib.scala 368:23] + wire rvclkhdr_440_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_441_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_441_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_441_io_en; // @[lib.scala 368:23] + wire rvclkhdr_441_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_442_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_442_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_442_io_en; // @[lib.scala 368:23] + wire rvclkhdr_442_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_443_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_443_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_443_io_en; // @[lib.scala 368:23] + wire rvclkhdr_443_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_444_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_444_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_444_io_en; // @[lib.scala 368:23] + wire rvclkhdr_444_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_445_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_445_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_445_io_en; // @[lib.scala 368:23] + wire rvclkhdr_445_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_446_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_446_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_446_io_en; // @[lib.scala 368:23] + wire rvclkhdr_446_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_447_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_447_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_447_io_en; // @[lib.scala 368:23] + wire rvclkhdr_447_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_448_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_448_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_448_io_en; // @[lib.scala 368:23] + wire rvclkhdr_448_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_449_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_449_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_449_io_en; // @[lib.scala 368:23] + wire rvclkhdr_449_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_450_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_450_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_450_io_en; // @[lib.scala 368:23] + wire rvclkhdr_450_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_451_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_451_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_451_io_en; // @[lib.scala 368:23] + wire rvclkhdr_451_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_452_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_452_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_452_io_en; // @[lib.scala 368:23] + wire rvclkhdr_452_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_453_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_453_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_453_io_en; // @[lib.scala 368:23] + wire rvclkhdr_453_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_454_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_454_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_454_io_en; // @[lib.scala 368:23] + wire rvclkhdr_454_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_455_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_455_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_455_io_en; // @[lib.scala 368:23] + wire rvclkhdr_455_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_456_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_456_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_456_io_en; // @[lib.scala 368:23] + wire rvclkhdr_456_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_457_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_457_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_457_io_en; // @[lib.scala 368:23] + wire rvclkhdr_457_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_458_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_458_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_458_io_en; // @[lib.scala 368:23] + wire rvclkhdr_458_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_459_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_459_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_459_io_en; // @[lib.scala 368:23] + wire rvclkhdr_459_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_460_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_460_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_460_io_en; // @[lib.scala 368:23] + wire rvclkhdr_460_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_461_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_461_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_461_io_en; // @[lib.scala 368:23] + wire rvclkhdr_461_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_462_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_462_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_462_io_en; // @[lib.scala 368:23] + wire rvclkhdr_462_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_463_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_463_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_463_io_en; // @[lib.scala 368:23] + wire rvclkhdr_463_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_464_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_464_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_464_io_en; // @[lib.scala 368:23] + wire rvclkhdr_464_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_465_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_465_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_465_io_en; // @[lib.scala 368:23] + wire rvclkhdr_465_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_466_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_466_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_466_io_en; // @[lib.scala 368:23] + wire rvclkhdr_466_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_467_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_467_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_467_io_en; // @[lib.scala 368:23] + wire rvclkhdr_467_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_468_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_468_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_468_io_en; // @[lib.scala 368:23] + wire rvclkhdr_468_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_469_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_469_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_469_io_en; // @[lib.scala 368:23] + wire rvclkhdr_469_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_470_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_470_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_470_io_en; // @[lib.scala 368:23] + wire rvclkhdr_470_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_471_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_471_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_471_io_en; // @[lib.scala 368:23] + wire rvclkhdr_471_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_472_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_472_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_472_io_en; // @[lib.scala 368:23] + wire rvclkhdr_472_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_473_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_473_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_473_io_en; // @[lib.scala 368:23] + wire rvclkhdr_473_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_474_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_474_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_474_io_en; // @[lib.scala 368:23] + wire rvclkhdr_474_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_475_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_475_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_475_io_en; // @[lib.scala 368:23] + wire rvclkhdr_475_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_476_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_476_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_476_io_en; // @[lib.scala 368:23] + wire rvclkhdr_476_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_477_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_477_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_477_io_en; // @[lib.scala 368:23] + wire rvclkhdr_477_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_478_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_478_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_478_io_en; // @[lib.scala 368:23] + wire rvclkhdr_478_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_479_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_479_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_479_io_en; // @[lib.scala 368:23] + wire rvclkhdr_479_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_480_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_480_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_480_io_en; // @[lib.scala 368:23] + wire rvclkhdr_480_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_481_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_481_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_481_io_en; // @[lib.scala 368:23] + wire rvclkhdr_481_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_482_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_482_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_482_io_en; // @[lib.scala 368:23] + wire rvclkhdr_482_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_483_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_483_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_483_io_en; // @[lib.scala 368:23] + wire rvclkhdr_483_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_484_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_484_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_484_io_en; // @[lib.scala 368:23] + wire rvclkhdr_484_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_485_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_485_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_485_io_en; // @[lib.scala 368:23] + wire rvclkhdr_485_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_486_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_486_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_486_io_en; // @[lib.scala 368:23] + wire rvclkhdr_486_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_487_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_487_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_487_io_en; // @[lib.scala 368:23] + wire rvclkhdr_487_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_488_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_488_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_488_io_en; // @[lib.scala 368:23] + wire rvclkhdr_488_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_489_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_489_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_489_io_en; // @[lib.scala 368:23] + wire rvclkhdr_489_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_490_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_490_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_490_io_en; // @[lib.scala 368:23] + wire rvclkhdr_490_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_491_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_491_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_491_io_en; // @[lib.scala 368:23] + wire rvclkhdr_491_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_492_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_492_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_492_io_en; // @[lib.scala 368:23] + wire rvclkhdr_492_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_493_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_493_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_493_io_en; // @[lib.scala 368:23] + wire rvclkhdr_493_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_494_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_494_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_494_io_en; // @[lib.scala 368:23] + wire rvclkhdr_494_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_495_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_495_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_495_io_en; // @[lib.scala 368:23] + wire rvclkhdr_495_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_496_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_496_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_496_io_en; // @[lib.scala 368:23] + wire rvclkhdr_496_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_497_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_497_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_497_io_en; // @[lib.scala 368:23] + wire rvclkhdr_497_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_498_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_498_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_498_io_en; // @[lib.scala 368:23] + wire rvclkhdr_498_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_499_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_499_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_499_io_en; // @[lib.scala 368:23] + wire rvclkhdr_499_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_500_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_500_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_500_io_en; // @[lib.scala 368:23] + wire rvclkhdr_500_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_501_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_501_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_501_io_en; // @[lib.scala 368:23] + wire rvclkhdr_501_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_502_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_502_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_502_io_en; // @[lib.scala 368:23] + wire rvclkhdr_502_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_503_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_503_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_503_io_en; // @[lib.scala 368:23] + wire rvclkhdr_503_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_504_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_504_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_504_io_en; // @[lib.scala 368:23] + wire rvclkhdr_504_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_505_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_505_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_505_io_en; // @[lib.scala 368:23] + wire rvclkhdr_505_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_506_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_506_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_506_io_en; // @[lib.scala 368:23] + wire rvclkhdr_506_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_507_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_507_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_507_io_en; // @[lib.scala 368:23] + wire rvclkhdr_507_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_508_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_508_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_508_io_en; // @[lib.scala 368:23] + wire rvclkhdr_508_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_509_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_509_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_509_io_en; // @[lib.scala 368:23] + wire rvclkhdr_509_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_510_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_510_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_510_io_en; // @[lib.scala 368:23] + wire rvclkhdr_510_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_511_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_511_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_511_io_en; // @[lib.scala 368:23] + wire rvclkhdr_511_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_512_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_512_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_512_io_en; // @[lib.scala 368:23] + wire rvclkhdr_512_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_513_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_513_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_513_io_en; // @[lib.scala 368:23] + wire rvclkhdr_513_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_514_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_514_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_514_io_en; // @[lib.scala 368:23] + wire rvclkhdr_514_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_515_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_515_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_515_io_en; // @[lib.scala 368:23] + wire rvclkhdr_515_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_516_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_516_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_516_io_en; // @[lib.scala 368:23] + wire rvclkhdr_516_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_517_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_517_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_517_io_en; // @[lib.scala 368:23] + wire rvclkhdr_517_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_518_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_518_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_518_io_en; // @[lib.scala 368:23] + wire rvclkhdr_518_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_519_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_519_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_519_io_en; // @[lib.scala 368:23] + wire rvclkhdr_519_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_520_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_520_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_520_io_en; // @[lib.scala 368:23] + wire rvclkhdr_520_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_521_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_521_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_521_io_en; // @[lib.scala 368:23] + wire rvclkhdr_521_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_522_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_522_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_522_io_en; // @[lib.scala 343:22] + wire rvclkhdr_522_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_523_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_523_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_523_io_en; // @[lib.scala 343:22] + wire rvclkhdr_523_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_524_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_524_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_524_io_en; // @[lib.scala 343:22] + wire rvclkhdr_524_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_525_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_525_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_525_io_en; // @[lib.scala 343:22] + wire rvclkhdr_525_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_526_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_526_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_526_io_en; // @[lib.scala 343:22] + wire rvclkhdr_526_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_527_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_527_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_527_io_en; // @[lib.scala 343:22] + wire rvclkhdr_527_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_528_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_528_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_528_io_en; // @[lib.scala 343:22] + wire rvclkhdr_528_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_529_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_529_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_529_io_en; // @[lib.scala 343:22] + wire rvclkhdr_529_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_530_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_530_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_530_io_en; // @[lib.scala 343:22] + wire rvclkhdr_530_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_531_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_531_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_531_io_en; // @[lib.scala 343:22] + wire rvclkhdr_531_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_532_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_532_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_532_io_en; // @[lib.scala 343:22] + wire rvclkhdr_532_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_533_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_533_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_533_io_en; // @[lib.scala 343:22] + wire rvclkhdr_533_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_534_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_534_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_534_io_en; // @[lib.scala 343:22] + wire rvclkhdr_534_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_535_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_535_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_535_io_en; // @[lib.scala 343:22] + wire rvclkhdr_535_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_536_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_536_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_536_io_en; // @[lib.scala 343:22] + wire rvclkhdr_536_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_537_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_537_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_537_io_en; // @[lib.scala 343:22] + wire rvclkhdr_537_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_538_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_538_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_538_io_en; // @[lib.scala 343:22] + wire rvclkhdr_538_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_539_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_539_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_539_io_en; // @[lib.scala 343:22] + wire rvclkhdr_539_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_540_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_540_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_540_io_en; // @[lib.scala 343:22] + wire rvclkhdr_540_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_541_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_541_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_541_io_en; // @[lib.scala 343:22] + wire rvclkhdr_541_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_542_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_542_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_542_io_en; // @[lib.scala 343:22] + wire rvclkhdr_542_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_543_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_543_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_543_io_en; // @[lib.scala 343:22] + wire rvclkhdr_543_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_544_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_544_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_544_io_en; // @[lib.scala 343:22] + wire rvclkhdr_544_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_545_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_545_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_545_io_en; // @[lib.scala 343:22] + wire rvclkhdr_545_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_546_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_546_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_546_io_en; // @[lib.scala 343:22] + wire rvclkhdr_546_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_547_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_547_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_547_io_en; // @[lib.scala 343:22] + wire rvclkhdr_547_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_548_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_548_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_548_io_en; // @[lib.scala 343:22] + wire rvclkhdr_548_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_549_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_549_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_549_io_en; // @[lib.scala 343:22] + wire rvclkhdr_549_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_550_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_550_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_550_io_en; // @[lib.scala 343:22] + wire rvclkhdr_550_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_551_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_551_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_551_io_en; // @[lib.scala 343:22] + wire rvclkhdr_551_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_552_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_552_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_552_io_en; // @[lib.scala 343:22] + wire rvclkhdr_552_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_553_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_553_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_553_io_en; // @[lib.scala 343:22] + wire rvclkhdr_553_io_scan_mode; // @[lib.scala 343:22] wire _T_40 = io_dec_bp_dec_tlu_flush_leak_one_wb & io_dec_tlu_flush_lower_wb; // @[ifu_bp_ctl.scala 123:54] reg leak_one_f_d1; // @[ifu_bp_ctl.scala 117:56] wire _T_41 = ~io_dec_tlu_flush_lower_wb; // @[ifu_bp_ctl.scala 123:102] @@ -15175,1038 +15175,1038 @@ module ifu_bp_ctl( wire _T = ~leak_one_f; // @[ifu_bp_ctl.scala 60:58] wire exu_mp_valid = io_exu_bp_exu_mp_pkt_bits_misp & _T; // @[ifu_bp_ctl.scala 60:56] wire dec_tlu_error_wb = io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error | io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[ifu_bp_ctl.scala 82:50] - wire [7:0] _T_4 = io_ifc_fetch_addr_f[8:1] ^ io_ifc_fetch_addr_f[16:9]; // @[el2_lib.scala 191:47] - wire [7:0] btb_rd_addr_f = _T_4 ^ io_ifc_fetch_addr_f[24:17]; // @[el2_lib.scala 191:85] + wire [7:0] _T_4 = io_ifc_fetch_addr_f[8:1] ^ io_ifc_fetch_addr_f[16:9]; // @[lib.scala 51:47] + wire [7:0] btb_rd_addr_f = _T_4 ^ io_ifc_fetch_addr_f[24:17]; // @[lib.scala 51:85] wire [29:0] fetch_addr_p1_f = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[ifu_bp_ctl.scala 90:51] wire [30:0] _T_8 = {fetch_addr_p1_f,1'h0}; // @[Cat.scala 29:58] - wire [7:0] _T_11 = _T_8[8:1] ^ _T_8[16:9]; // @[el2_lib.scala 191:47] - wire [7:0] btb_rd_addr_p1_f = _T_11 ^ _T_8[24:17]; // @[el2_lib.scala 191:85] + wire [7:0] _T_11 = _T_8[8:1] ^ _T_8[16:9]; // @[lib.scala 51:47] + wire [7:0] btb_rd_addr_p1_f = _T_11 ^ _T_8[24:17]; // @[lib.scala 51:85] wire _T_144 = ~io_ifc_fetch_addr_f[0]; // @[ifu_bp_ctl.scala 174:40] wire _T_2112 = btb_rd_addr_f == 8'h0; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_0; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_0; // @[lib.scala 374:16] wire [21:0] _T_2624 = _T_2112 ? btb_bank0_rd_data_way0_out_0 : 22'h0; // @[Mux.scala 27:72] wire _T_2114 = btb_rd_addr_f == 8'h1; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_1; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_1; // @[lib.scala 374:16] wire [21:0] _T_2625 = _T_2114 ? btb_bank0_rd_data_way0_out_1 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2880 = _T_2624 | _T_2625; // @[Mux.scala 27:72] wire _T_2116 = btb_rd_addr_f == 8'h2; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_2; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_2; // @[lib.scala 374:16] wire [21:0] _T_2626 = _T_2116 ? btb_bank0_rd_data_way0_out_2 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2881 = _T_2880 | _T_2626; // @[Mux.scala 27:72] wire _T_2118 = btb_rd_addr_f == 8'h3; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_3; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_3; // @[lib.scala 374:16] wire [21:0] _T_2627 = _T_2118 ? btb_bank0_rd_data_way0_out_3 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2882 = _T_2881 | _T_2627; // @[Mux.scala 27:72] wire _T_2120 = btb_rd_addr_f == 8'h4; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_4; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_4; // @[lib.scala 374:16] wire [21:0] _T_2628 = _T_2120 ? btb_bank0_rd_data_way0_out_4 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2883 = _T_2882 | _T_2628; // @[Mux.scala 27:72] wire _T_2122 = btb_rd_addr_f == 8'h5; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_5; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_5; // @[lib.scala 374:16] wire [21:0] _T_2629 = _T_2122 ? btb_bank0_rd_data_way0_out_5 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2884 = _T_2883 | _T_2629; // @[Mux.scala 27:72] wire _T_2124 = btb_rd_addr_f == 8'h6; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_6; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_6; // @[lib.scala 374:16] wire [21:0] _T_2630 = _T_2124 ? btb_bank0_rd_data_way0_out_6 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2885 = _T_2884 | _T_2630; // @[Mux.scala 27:72] wire _T_2126 = btb_rd_addr_f == 8'h7; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_7; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_7; // @[lib.scala 374:16] wire [21:0] _T_2631 = _T_2126 ? btb_bank0_rd_data_way0_out_7 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2886 = _T_2885 | _T_2631; // @[Mux.scala 27:72] wire _T_2128 = btb_rd_addr_f == 8'h8; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_8; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_8; // @[lib.scala 374:16] wire [21:0] _T_2632 = _T_2128 ? btb_bank0_rd_data_way0_out_8 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2887 = _T_2886 | _T_2632; // @[Mux.scala 27:72] wire _T_2130 = btb_rd_addr_f == 8'h9; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_9; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_9; // @[lib.scala 374:16] wire [21:0] _T_2633 = _T_2130 ? btb_bank0_rd_data_way0_out_9 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2888 = _T_2887 | _T_2633; // @[Mux.scala 27:72] wire _T_2132 = btb_rd_addr_f == 8'ha; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_10; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_10; // @[lib.scala 374:16] wire [21:0] _T_2634 = _T_2132 ? btb_bank0_rd_data_way0_out_10 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2889 = _T_2888 | _T_2634; // @[Mux.scala 27:72] wire _T_2134 = btb_rd_addr_f == 8'hb; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_11; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_11; // @[lib.scala 374:16] wire [21:0] _T_2635 = _T_2134 ? btb_bank0_rd_data_way0_out_11 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2890 = _T_2889 | _T_2635; // @[Mux.scala 27:72] wire _T_2136 = btb_rd_addr_f == 8'hc; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_12; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_12; // @[lib.scala 374:16] wire [21:0] _T_2636 = _T_2136 ? btb_bank0_rd_data_way0_out_12 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2891 = _T_2890 | _T_2636; // @[Mux.scala 27:72] wire _T_2138 = btb_rd_addr_f == 8'hd; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_13; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_13; // @[lib.scala 374:16] wire [21:0] _T_2637 = _T_2138 ? btb_bank0_rd_data_way0_out_13 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2892 = _T_2891 | _T_2637; // @[Mux.scala 27:72] wire _T_2140 = btb_rd_addr_f == 8'he; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_14; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_14; // @[lib.scala 374:16] wire [21:0] _T_2638 = _T_2140 ? btb_bank0_rd_data_way0_out_14 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2893 = _T_2892 | _T_2638; // @[Mux.scala 27:72] wire _T_2142 = btb_rd_addr_f == 8'hf; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_15; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_15; // @[lib.scala 374:16] wire [21:0] _T_2639 = _T_2142 ? btb_bank0_rd_data_way0_out_15 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2894 = _T_2893 | _T_2639; // @[Mux.scala 27:72] wire _T_2144 = btb_rd_addr_f == 8'h10; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_16; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_16; // @[lib.scala 374:16] wire [21:0] _T_2640 = _T_2144 ? btb_bank0_rd_data_way0_out_16 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2895 = _T_2894 | _T_2640; // @[Mux.scala 27:72] wire _T_2146 = btb_rd_addr_f == 8'h11; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_17; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_17; // @[lib.scala 374:16] wire [21:0] _T_2641 = _T_2146 ? btb_bank0_rd_data_way0_out_17 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2896 = _T_2895 | _T_2641; // @[Mux.scala 27:72] wire _T_2148 = btb_rd_addr_f == 8'h12; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_18; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_18; // @[lib.scala 374:16] wire [21:0] _T_2642 = _T_2148 ? btb_bank0_rd_data_way0_out_18 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2897 = _T_2896 | _T_2642; // @[Mux.scala 27:72] wire _T_2150 = btb_rd_addr_f == 8'h13; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_19; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_19; // @[lib.scala 374:16] wire [21:0] _T_2643 = _T_2150 ? btb_bank0_rd_data_way0_out_19 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2898 = _T_2897 | _T_2643; // @[Mux.scala 27:72] wire _T_2152 = btb_rd_addr_f == 8'h14; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_20; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_20; // @[lib.scala 374:16] wire [21:0] _T_2644 = _T_2152 ? btb_bank0_rd_data_way0_out_20 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2899 = _T_2898 | _T_2644; // @[Mux.scala 27:72] wire _T_2154 = btb_rd_addr_f == 8'h15; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_21; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_21; // @[lib.scala 374:16] wire [21:0] _T_2645 = _T_2154 ? btb_bank0_rd_data_way0_out_21 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2900 = _T_2899 | _T_2645; // @[Mux.scala 27:72] wire _T_2156 = btb_rd_addr_f == 8'h16; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_22; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_22; // @[lib.scala 374:16] wire [21:0] _T_2646 = _T_2156 ? btb_bank0_rd_data_way0_out_22 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2901 = _T_2900 | _T_2646; // @[Mux.scala 27:72] wire _T_2158 = btb_rd_addr_f == 8'h17; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_23; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_23; // @[lib.scala 374:16] wire [21:0] _T_2647 = _T_2158 ? btb_bank0_rd_data_way0_out_23 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2902 = _T_2901 | _T_2647; // @[Mux.scala 27:72] wire _T_2160 = btb_rd_addr_f == 8'h18; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_24; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_24; // @[lib.scala 374:16] wire [21:0] _T_2648 = _T_2160 ? btb_bank0_rd_data_way0_out_24 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2903 = _T_2902 | _T_2648; // @[Mux.scala 27:72] wire _T_2162 = btb_rd_addr_f == 8'h19; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_25; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_25; // @[lib.scala 374:16] wire [21:0] _T_2649 = _T_2162 ? btb_bank0_rd_data_way0_out_25 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2904 = _T_2903 | _T_2649; // @[Mux.scala 27:72] wire _T_2164 = btb_rd_addr_f == 8'h1a; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_26; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_26; // @[lib.scala 374:16] wire [21:0] _T_2650 = _T_2164 ? btb_bank0_rd_data_way0_out_26 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2905 = _T_2904 | _T_2650; // @[Mux.scala 27:72] wire _T_2166 = btb_rd_addr_f == 8'h1b; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_27; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_27; // @[lib.scala 374:16] wire [21:0] _T_2651 = _T_2166 ? btb_bank0_rd_data_way0_out_27 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2906 = _T_2905 | _T_2651; // @[Mux.scala 27:72] wire _T_2168 = btb_rd_addr_f == 8'h1c; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_28; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_28; // @[lib.scala 374:16] wire [21:0] _T_2652 = _T_2168 ? btb_bank0_rd_data_way0_out_28 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2907 = _T_2906 | _T_2652; // @[Mux.scala 27:72] wire _T_2170 = btb_rd_addr_f == 8'h1d; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_29; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_29; // @[lib.scala 374:16] wire [21:0] _T_2653 = _T_2170 ? btb_bank0_rd_data_way0_out_29 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2908 = _T_2907 | _T_2653; // @[Mux.scala 27:72] wire _T_2172 = btb_rd_addr_f == 8'h1e; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_30; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_30; // @[lib.scala 374:16] wire [21:0] _T_2654 = _T_2172 ? btb_bank0_rd_data_way0_out_30 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2909 = _T_2908 | _T_2654; // @[Mux.scala 27:72] wire _T_2174 = btb_rd_addr_f == 8'h1f; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_31; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_31; // @[lib.scala 374:16] wire [21:0] _T_2655 = _T_2174 ? btb_bank0_rd_data_way0_out_31 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2910 = _T_2909 | _T_2655; // @[Mux.scala 27:72] wire _T_2176 = btb_rd_addr_f == 8'h20; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_32; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_32; // @[lib.scala 374:16] wire [21:0] _T_2656 = _T_2176 ? btb_bank0_rd_data_way0_out_32 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2911 = _T_2910 | _T_2656; // @[Mux.scala 27:72] wire _T_2178 = btb_rd_addr_f == 8'h21; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_33; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_33; // @[lib.scala 374:16] wire [21:0] _T_2657 = _T_2178 ? btb_bank0_rd_data_way0_out_33 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2912 = _T_2911 | _T_2657; // @[Mux.scala 27:72] wire _T_2180 = btb_rd_addr_f == 8'h22; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_34; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_34; // @[lib.scala 374:16] wire [21:0] _T_2658 = _T_2180 ? btb_bank0_rd_data_way0_out_34 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2913 = _T_2912 | _T_2658; // @[Mux.scala 27:72] wire _T_2182 = btb_rd_addr_f == 8'h23; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_35; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_35; // @[lib.scala 374:16] wire [21:0] _T_2659 = _T_2182 ? btb_bank0_rd_data_way0_out_35 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2914 = _T_2913 | _T_2659; // @[Mux.scala 27:72] wire _T_2184 = btb_rd_addr_f == 8'h24; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_36; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_36; // @[lib.scala 374:16] wire [21:0] _T_2660 = _T_2184 ? btb_bank0_rd_data_way0_out_36 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2915 = _T_2914 | _T_2660; // @[Mux.scala 27:72] wire _T_2186 = btb_rd_addr_f == 8'h25; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_37; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_37; // @[lib.scala 374:16] wire [21:0] _T_2661 = _T_2186 ? btb_bank0_rd_data_way0_out_37 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2916 = _T_2915 | _T_2661; // @[Mux.scala 27:72] wire _T_2188 = btb_rd_addr_f == 8'h26; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_38; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_38; // @[lib.scala 374:16] wire [21:0] _T_2662 = _T_2188 ? btb_bank0_rd_data_way0_out_38 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2917 = _T_2916 | _T_2662; // @[Mux.scala 27:72] wire _T_2190 = btb_rd_addr_f == 8'h27; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_39; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_39; // @[lib.scala 374:16] wire [21:0] _T_2663 = _T_2190 ? btb_bank0_rd_data_way0_out_39 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2918 = _T_2917 | _T_2663; // @[Mux.scala 27:72] wire _T_2192 = btb_rd_addr_f == 8'h28; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_40; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_40; // @[lib.scala 374:16] wire [21:0] _T_2664 = _T_2192 ? btb_bank0_rd_data_way0_out_40 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2919 = _T_2918 | _T_2664; // @[Mux.scala 27:72] wire _T_2194 = btb_rd_addr_f == 8'h29; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_41; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_41; // @[lib.scala 374:16] wire [21:0] _T_2665 = _T_2194 ? btb_bank0_rd_data_way0_out_41 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2920 = _T_2919 | _T_2665; // @[Mux.scala 27:72] wire _T_2196 = btb_rd_addr_f == 8'h2a; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_42; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_42; // @[lib.scala 374:16] wire [21:0] _T_2666 = _T_2196 ? btb_bank0_rd_data_way0_out_42 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2921 = _T_2920 | _T_2666; // @[Mux.scala 27:72] wire _T_2198 = btb_rd_addr_f == 8'h2b; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_43; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_43; // @[lib.scala 374:16] wire [21:0] _T_2667 = _T_2198 ? btb_bank0_rd_data_way0_out_43 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2922 = _T_2921 | _T_2667; // @[Mux.scala 27:72] wire _T_2200 = btb_rd_addr_f == 8'h2c; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_44; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_44; // @[lib.scala 374:16] wire [21:0] _T_2668 = _T_2200 ? btb_bank0_rd_data_way0_out_44 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2923 = _T_2922 | _T_2668; // @[Mux.scala 27:72] wire _T_2202 = btb_rd_addr_f == 8'h2d; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_45; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_45; // @[lib.scala 374:16] wire [21:0] _T_2669 = _T_2202 ? btb_bank0_rd_data_way0_out_45 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2924 = _T_2923 | _T_2669; // @[Mux.scala 27:72] wire _T_2204 = btb_rd_addr_f == 8'h2e; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_46; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_46; // @[lib.scala 374:16] wire [21:0] _T_2670 = _T_2204 ? btb_bank0_rd_data_way0_out_46 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2925 = _T_2924 | _T_2670; // @[Mux.scala 27:72] wire _T_2206 = btb_rd_addr_f == 8'h2f; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_47; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_47; // @[lib.scala 374:16] wire [21:0] _T_2671 = _T_2206 ? btb_bank0_rd_data_way0_out_47 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2926 = _T_2925 | _T_2671; // @[Mux.scala 27:72] wire _T_2208 = btb_rd_addr_f == 8'h30; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_48; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_48; // @[lib.scala 374:16] wire [21:0] _T_2672 = _T_2208 ? btb_bank0_rd_data_way0_out_48 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2927 = _T_2926 | _T_2672; // @[Mux.scala 27:72] wire _T_2210 = btb_rd_addr_f == 8'h31; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_49; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_49; // @[lib.scala 374:16] wire [21:0] _T_2673 = _T_2210 ? btb_bank0_rd_data_way0_out_49 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2928 = _T_2927 | _T_2673; // @[Mux.scala 27:72] wire _T_2212 = btb_rd_addr_f == 8'h32; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_50; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_50; // @[lib.scala 374:16] wire [21:0] _T_2674 = _T_2212 ? btb_bank0_rd_data_way0_out_50 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2929 = _T_2928 | _T_2674; // @[Mux.scala 27:72] wire _T_2214 = btb_rd_addr_f == 8'h33; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_51; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_51; // @[lib.scala 374:16] wire [21:0] _T_2675 = _T_2214 ? btb_bank0_rd_data_way0_out_51 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2930 = _T_2929 | _T_2675; // @[Mux.scala 27:72] wire _T_2216 = btb_rd_addr_f == 8'h34; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_52; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_52; // @[lib.scala 374:16] wire [21:0] _T_2676 = _T_2216 ? btb_bank0_rd_data_way0_out_52 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2931 = _T_2930 | _T_2676; // @[Mux.scala 27:72] wire _T_2218 = btb_rd_addr_f == 8'h35; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_53; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_53; // @[lib.scala 374:16] wire [21:0] _T_2677 = _T_2218 ? btb_bank0_rd_data_way0_out_53 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2932 = _T_2931 | _T_2677; // @[Mux.scala 27:72] wire _T_2220 = btb_rd_addr_f == 8'h36; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_54; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_54; // @[lib.scala 374:16] wire [21:0] _T_2678 = _T_2220 ? btb_bank0_rd_data_way0_out_54 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2933 = _T_2932 | _T_2678; // @[Mux.scala 27:72] wire _T_2222 = btb_rd_addr_f == 8'h37; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_55; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_55; // @[lib.scala 374:16] wire [21:0] _T_2679 = _T_2222 ? btb_bank0_rd_data_way0_out_55 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2934 = _T_2933 | _T_2679; // @[Mux.scala 27:72] wire _T_2224 = btb_rd_addr_f == 8'h38; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_56; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_56; // @[lib.scala 374:16] wire [21:0] _T_2680 = _T_2224 ? btb_bank0_rd_data_way0_out_56 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2935 = _T_2934 | _T_2680; // @[Mux.scala 27:72] wire _T_2226 = btb_rd_addr_f == 8'h39; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_57; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_57; // @[lib.scala 374:16] wire [21:0] _T_2681 = _T_2226 ? btb_bank0_rd_data_way0_out_57 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2936 = _T_2935 | _T_2681; // @[Mux.scala 27:72] wire _T_2228 = btb_rd_addr_f == 8'h3a; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_58; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_58; // @[lib.scala 374:16] wire [21:0] _T_2682 = _T_2228 ? btb_bank0_rd_data_way0_out_58 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2937 = _T_2936 | _T_2682; // @[Mux.scala 27:72] wire _T_2230 = btb_rd_addr_f == 8'h3b; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_59; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_59; // @[lib.scala 374:16] wire [21:0] _T_2683 = _T_2230 ? btb_bank0_rd_data_way0_out_59 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2938 = _T_2937 | _T_2683; // @[Mux.scala 27:72] wire _T_2232 = btb_rd_addr_f == 8'h3c; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_60; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_60; // @[lib.scala 374:16] wire [21:0] _T_2684 = _T_2232 ? btb_bank0_rd_data_way0_out_60 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2939 = _T_2938 | _T_2684; // @[Mux.scala 27:72] wire _T_2234 = btb_rd_addr_f == 8'h3d; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_61; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_61; // @[lib.scala 374:16] wire [21:0] _T_2685 = _T_2234 ? btb_bank0_rd_data_way0_out_61 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2940 = _T_2939 | _T_2685; // @[Mux.scala 27:72] wire _T_2236 = btb_rd_addr_f == 8'h3e; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_62; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_62; // @[lib.scala 374:16] wire [21:0] _T_2686 = _T_2236 ? btb_bank0_rd_data_way0_out_62 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2941 = _T_2940 | _T_2686; // @[Mux.scala 27:72] wire _T_2238 = btb_rd_addr_f == 8'h3f; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_63; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_63; // @[lib.scala 374:16] wire [21:0] _T_2687 = _T_2238 ? btb_bank0_rd_data_way0_out_63 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2942 = _T_2941 | _T_2687; // @[Mux.scala 27:72] wire _T_2240 = btb_rd_addr_f == 8'h40; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_64; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_64; // @[lib.scala 374:16] wire [21:0] _T_2688 = _T_2240 ? btb_bank0_rd_data_way0_out_64 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2943 = _T_2942 | _T_2688; // @[Mux.scala 27:72] wire _T_2242 = btb_rd_addr_f == 8'h41; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_65; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_65; // @[lib.scala 374:16] wire [21:0] _T_2689 = _T_2242 ? btb_bank0_rd_data_way0_out_65 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2944 = _T_2943 | _T_2689; // @[Mux.scala 27:72] wire _T_2244 = btb_rd_addr_f == 8'h42; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_66; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_66; // @[lib.scala 374:16] wire [21:0] _T_2690 = _T_2244 ? btb_bank0_rd_data_way0_out_66 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2945 = _T_2944 | _T_2690; // @[Mux.scala 27:72] wire _T_2246 = btb_rd_addr_f == 8'h43; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_67; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_67; // @[lib.scala 374:16] wire [21:0] _T_2691 = _T_2246 ? btb_bank0_rd_data_way0_out_67 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2946 = _T_2945 | _T_2691; // @[Mux.scala 27:72] wire _T_2248 = btb_rd_addr_f == 8'h44; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_68; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_68; // @[lib.scala 374:16] wire [21:0] _T_2692 = _T_2248 ? btb_bank0_rd_data_way0_out_68 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2947 = _T_2946 | _T_2692; // @[Mux.scala 27:72] wire _T_2250 = btb_rd_addr_f == 8'h45; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_69; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_69; // @[lib.scala 374:16] wire [21:0] _T_2693 = _T_2250 ? btb_bank0_rd_data_way0_out_69 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2948 = _T_2947 | _T_2693; // @[Mux.scala 27:72] wire _T_2252 = btb_rd_addr_f == 8'h46; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_70; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_70; // @[lib.scala 374:16] wire [21:0] _T_2694 = _T_2252 ? btb_bank0_rd_data_way0_out_70 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2949 = _T_2948 | _T_2694; // @[Mux.scala 27:72] wire _T_2254 = btb_rd_addr_f == 8'h47; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_71; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_71; // @[lib.scala 374:16] wire [21:0] _T_2695 = _T_2254 ? btb_bank0_rd_data_way0_out_71 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2950 = _T_2949 | _T_2695; // @[Mux.scala 27:72] wire _T_2256 = btb_rd_addr_f == 8'h48; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_72; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_72; // @[lib.scala 374:16] wire [21:0] _T_2696 = _T_2256 ? btb_bank0_rd_data_way0_out_72 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2951 = _T_2950 | _T_2696; // @[Mux.scala 27:72] wire _T_2258 = btb_rd_addr_f == 8'h49; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_73; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_73; // @[lib.scala 374:16] wire [21:0] _T_2697 = _T_2258 ? btb_bank0_rd_data_way0_out_73 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2952 = _T_2951 | _T_2697; // @[Mux.scala 27:72] wire _T_2260 = btb_rd_addr_f == 8'h4a; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_74; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_74; // @[lib.scala 374:16] wire [21:0] _T_2698 = _T_2260 ? btb_bank0_rd_data_way0_out_74 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2953 = _T_2952 | _T_2698; // @[Mux.scala 27:72] wire _T_2262 = btb_rd_addr_f == 8'h4b; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_75; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_75; // @[lib.scala 374:16] wire [21:0] _T_2699 = _T_2262 ? btb_bank0_rd_data_way0_out_75 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2954 = _T_2953 | _T_2699; // @[Mux.scala 27:72] wire _T_2264 = btb_rd_addr_f == 8'h4c; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_76; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_76; // @[lib.scala 374:16] wire [21:0] _T_2700 = _T_2264 ? btb_bank0_rd_data_way0_out_76 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2955 = _T_2954 | _T_2700; // @[Mux.scala 27:72] wire _T_2266 = btb_rd_addr_f == 8'h4d; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_77; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_77; // @[lib.scala 374:16] wire [21:0] _T_2701 = _T_2266 ? btb_bank0_rd_data_way0_out_77 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2956 = _T_2955 | _T_2701; // @[Mux.scala 27:72] wire _T_2268 = btb_rd_addr_f == 8'h4e; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_78; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_78; // @[lib.scala 374:16] wire [21:0] _T_2702 = _T_2268 ? btb_bank0_rd_data_way0_out_78 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2957 = _T_2956 | _T_2702; // @[Mux.scala 27:72] wire _T_2270 = btb_rd_addr_f == 8'h4f; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_79; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_79; // @[lib.scala 374:16] wire [21:0] _T_2703 = _T_2270 ? btb_bank0_rd_data_way0_out_79 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2958 = _T_2957 | _T_2703; // @[Mux.scala 27:72] wire _T_2272 = btb_rd_addr_f == 8'h50; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_80; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_80; // @[lib.scala 374:16] wire [21:0] _T_2704 = _T_2272 ? btb_bank0_rd_data_way0_out_80 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2959 = _T_2958 | _T_2704; // @[Mux.scala 27:72] wire _T_2274 = btb_rd_addr_f == 8'h51; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_81; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_81; // @[lib.scala 374:16] wire [21:0] _T_2705 = _T_2274 ? btb_bank0_rd_data_way0_out_81 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2960 = _T_2959 | _T_2705; // @[Mux.scala 27:72] wire _T_2276 = btb_rd_addr_f == 8'h52; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_82; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_82; // @[lib.scala 374:16] wire [21:0] _T_2706 = _T_2276 ? btb_bank0_rd_data_way0_out_82 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2961 = _T_2960 | _T_2706; // @[Mux.scala 27:72] wire _T_2278 = btb_rd_addr_f == 8'h53; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_83; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_83; // @[lib.scala 374:16] wire [21:0] _T_2707 = _T_2278 ? btb_bank0_rd_data_way0_out_83 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2962 = _T_2961 | _T_2707; // @[Mux.scala 27:72] wire _T_2280 = btb_rd_addr_f == 8'h54; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_84; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_84; // @[lib.scala 374:16] wire [21:0] _T_2708 = _T_2280 ? btb_bank0_rd_data_way0_out_84 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2963 = _T_2962 | _T_2708; // @[Mux.scala 27:72] wire _T_2282 = btb_rd_addr_f == 8'h55; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_85; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_85; // @[lib.scala 374:16] wire [21:0] _T_2709 = _T_2282 ? btb_bank0_rd_data_way0_out_85 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2964 = _T_2963 | _T_2709; // @[Mux.scala 27:72] wire _T_2284 = btb_rd_addr_f == 8'h56; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_86; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_86; // @[lib.scala 374:16] wire [21:0] _T_2710 = _T_2284 ? btb_bank0_rd_data_way0_out_86 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2965 = _T_2964 | _T_2710; // @[Mux.scala 27:72] wire _T_2286 = btb_rd_addr_f == 8'h57; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_87; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_87; // @[lib.scala 374:16] wire [21:0] _T_2711 = _T_2286 ? btb_bank0_rd_data_way0_out_87 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2966 = _T_2965 | _T_2711; // @[Mux.scala 27:72] wire _T_2288 = btb_rd_addr_f == 8'h58; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_88; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_88; // @[lib.scala 374:16] wire [21:0] _T_2712 = _T_2288 ? btb_bank0_rd_data_way0_out_88 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2967 = _T_2966 | _T_2712; // @[Mux.scala 27:72] wire _T_2290 = btb_rd_addr_f == 8'h59; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_89; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_89; // @[lib.scala 374:16] wire [21:0] _T_2713 = _T_2290 ? btb_bank0_rd_data_way0_out_89 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2968 = _T_2967 | _T_2713; // @[Mux.scala 27:72] wire _T_2292 = btb_rd_addr_f == 8'h5a; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_90; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_90; // @[lib.scala 374:16] wire [21:0] _T_2714 = _T_2292 ? btb_bank0_rd_data_way0_out_90 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2969 = _T_2968 | _T_2714; // @[Mux.scala 27:72] wire _T_2294 = btb_rd_addr_f == 8'h5b; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_91; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_91; // @[lib.scala 374:16] wire [21:0] _T_2715 = _T_2294 ? btb_bank0_rd_data_way0_out_91 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2970 = _T_2969 | _T_2715; // @[Mux.scala 27:72] wire _T_2296 = btb_rd_addr_f == 8'h5c; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_92; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_92; // @[lib.scala 374:16] wire [21:0] _T_2716 = _T_2296 ? btb_bank0_rd_data_way0_out_92 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2971 = _T_2970 | _T_2716; // @[Mux.scala 27:72] wire _T_2298 = btb_rd_addr_f == 8'h5d; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_93; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_93; // @[lib.scala 374:16] wire [21:0] _T_2717 = _T_2298 ? btb_bank0_rd_data_way0_out_93 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2972 = _T_2971 | _T_2717; // @[Mux.scala 27:72] wire _T_2300 = btb_rd_addr_f == 8'h5e; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_94; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_94; // @[lib.scala 374:16] wire [21:0] _T_2718 = _T_2300 ? btb_bank0_rd_data_way0_out_94 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2973 = _T_2972 | _T_2718; // @[Mux.scala 27:72] wire _T_2302 = btb_rd_addr_f == 8'h5f; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_95; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_95; // @[lib.scala 374:16] wire [21:0] _T_2719 = _T_2302 ? btb_bank0_rd_data_way0_out_95 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2974 = _T_2973 | _T_2719; // @[Mux.scala 27:72] wire _T_2304 = btb_rd_addr_f == 8'h60; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_96; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_96; // @[lib.scala 374:16] wire [21:0] _T_2720 = _T_2304 ? btb_bank0_rd_data_way0_out_96 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2975 = _T_2974 | _T_2720; // @[Mux.scala 27:72] wire _T_2306 = btb_rd_addr_f == 8'h61; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_97; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_97; // @[lib.scala 374:16] wire [21:0] _T_2721 = _T_2306 ? btb_bank0_rd_data_way0_out_97 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2976 = _T_2975 | _T_2721; // @[Mux.scala 27:72] wire _T_2308 = btb_rd_addr_f == 8'h62; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_98; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_98; // @[lib.scala 374:16] wire [21:0] _T_2722 = _T_2308 ? btb_bank0_rd_data_way0_out_98 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2977 = _T_2976 | _T_2722; // @[Mux.scala 27:72] wire _T_2310 = btb_rd_addr_f == 8'h63; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_99; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_99; // @[lib.scala 374:16] wire [21:0] _T_2723 = _T_2310 ? btb_bank0_rd_data_way0_out_99 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2978 = _T_2977 | _T_2723; // @[Mux.scala 27:72] wire _T_2312 = btb_rd_addr_f == 8'h64; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_100; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_100; // @[lib.scala 374:16] wire [21:0] _T_2724 = _T_2312 ? btb_bank0_rd_data_way0_out_100 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2979 = _T_2978 | _T_2724; // @[Mux.scala 27:72] wire _T_2314 = btb_rd_addr_f == 8'h65; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_101; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_101; // @[lib.scala 374:16] wire [21:0] _T_2725 = _T_2314 ? btb_bank0_rd_data_way0_out_101 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2980 = _T_2979 | _T_2725; // @[Mux.scala 27:72] wire _T_2316 = btb_rd_addr_f == 8'h66; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_102; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_102; // @[lib.scala 374:16] wire [21:0] _T_2726 = _T_2316 ? btb_bank0_rd_data_way0_out_102 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2981 = _T_2980 | _T_2726; // @[Mux.scala 27:72] wire _T_2318 = btb_rd_addr_f == 8'h67; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_103; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_103; // @[lib.scala 374:16] wire [21:0] _T_2727 = _T_2318 ? btb_bank0_rd_data_way0_out_103 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2982 = _T_2981 | _T_2727; // @[Mux.scala 27:72] wire _T_2320 = btb_rd_addr_f == 8'h68; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_104; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_104; // @[lib.scala 374:16] wire [21:0] _T_2728 = _T_2320 ? btb_bank0_rd_data_way0_out_104 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2983 = _T_2982 | _T_2728; // @[Mux.scala 27:72] wire _T_2322 = btb_rd_addr_f == 8'h69; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_105; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_105; // @[lib.scala 374:16] wire [21:0] _T_2729 = _T_2322 ? btb_bank0_rd_data_way0_out_105 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2984 = _T_2983 | _T_2729; // @[Mux.scala 27:72] wire _T_2324 = btb_rd_addr_f == 8'h6a; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_106; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_106; // @[lib.scala 374:16] wire [21:0] _T_2730 = _T_2324 ? btb_bank0_rd_data_way0_out_106 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2985 = _T_2984 | _T_2730; // @[Mux.scala 27:72] wire _T_2326 = btb_rd_addr_f == 8'h6b; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_107; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_107; // @[lib.scala 374:16] wire [21:0] _T_2731 = _T_2326 ? btb_bank0_rd_data_way0_out_107 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2986 = _T_2985 | _T_2731; // @[Mux.scala 27:72] wire _T_2328 = btb_rd_addr_f == 8'h6c; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_108; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_108; // @[lib.scala 374:16] wire [21:0] _T_2732 = _T_2328 ? btb_bank0_rd_data_way0_out_108 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2987 = _T_2986 | _T_2732; // @[Mux.scala 27:72] wire _T_2330 = btb_rd_addr_f == 8'h6d; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_109; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_109; // @[lib.scala 374:16] wire [21:0] _T_2733 = _T_2330 ? btb_bank0_rd_data_way0_out_109 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2988 = _T_2987 | _T_2733; // @[Mux.scala 27:72] wire _T_2332 = btb_rd_addr_f == 8'h6e; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_110; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_110; // @[lib.scala 374:16] wire [21:0] _T_2734 = _T_2332 ? btb_bank0_rd_data_way0_out_110 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2989 = _T_2988 | _T_2734; // @[Mux.scala 27:72] wire _T_2334 = btb_rd_addr_f == 8'h6f; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_111; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_111; // @[lib.scala 374:16] wire [21:0] _T_2735 = _T_2334 ? btb_bank0_rd_data_way0_out_111 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2990 = _T_2989 | _T_2735; // @[Mux.scala 27:72] wire _T_2336 = btb_rd_addr_f == 8'h70; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_112; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_112; // @[lib.scala 374:16] wire [21:0] _T_2736 = _T_2336 ? btb_bank0_rd_data_way0_out_112 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2991 = _T_2990 | _T_2736; // @[Mux.scala 27:72] wire _T_2338 = btb_rd_addr_f == 8'h71; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_113; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_113; // @[lib.scala 374:16] wire [21:0] _T_2737 = _T_2338 ? btb_bank0_rd_data_way0_out_113 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2992 = _T_2991 | _T_2737; // @[Mux.scala 27:72] wire _T_2340 = btb_rd_addr_f == 8'h72; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_114; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_114; // @[lib.scala 374:16] wire [21:0] _T_2738 = _T_2340 ? btb_bank0_rd_data_way0_out_114 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2993 = _T_2992 | _T_2738; // @[Mux.scala 27:72] wire _T_2342 = btb_rd_addr_f == 8'h73; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_115; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_115; // @[lib.scala 374:16] wire [21:0] _T_2739 = _T_2342 ? btb_bank0_rd_data_way0_out_115 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2994 = _T_2993 | _T_2739; // @[Mux.scala 27:72] wire _T_2344 = btb_rd_addr_f == 8'h74; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_116; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_116; // @[lib.scala 374:16] wire [21:0] _T_2740 = _T_2344 ? btb_bank0_rd_data_way0_out_116 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2995 = _T_2994 | _T_2740; // @[Mux.scala 27:72] wire _T_2346 = btb_rd_addr_f == 8'h75; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_117; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_117; // @[lib.scala 374:16] wire [21:0] _T_2741 = _T_2346 ? btb_bank0_rd_data_way0_out_117 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2996 = _T_2995 | _T_2741; // @[Mux.scala 27:72] wire _T_2348 = btb_rd_addr_f == 8'h76; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_118; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_118; // @[lib.scala 374:16] wire [21:0] _T_2742 = _T_2348 ? btb_bank0_rd_data_way0_out_118 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2997 = _T_2996 | _T_2742; // @[Mux.scala 27:72] wire _T_2350 = btb_rd_addr_f == 8'h77; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_119; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_119; // @[lib.scala 374:16] wire [21:0] _T_2743 = _T_2350 ? btb_bank0_rd_data_way0_out_119 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2998 = _T_2997 | _T_2743; // @[Mux.scala 27:72] wire _T_2352 = btb_rd_addr_f == 8'h78; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_120; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_120; // @[lib.scala 374:16] wire [21:0] _T_2744 = _T_2352 ? btb_bank0_rd_data_way0_out_120 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2999 = _T_2998 | _T_2744; // @[Mux.scala 27:72] wire _T_2354 = btb_rd_addr_f == 8'h79; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_121; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_121; // @[lib.scala 374:16] wire [21:0] _T_2745 = _T_2354 ? btb_bank0_rd_data_way0_out_121 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3000 = _T_2999 | _T_2745; // @[Mux.scala 27:72] wire _T_2356 = btb_rd_addr_f == 8'h7a; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_122; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_122; // @[lib.scala 374:16] wire [21:0] _T_2746 = _T_2356 ? btb_bank0_rd_data_way0_out_122 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3001 = _T_3000 | _T_2746; // @[Mux.scala 27:72] wire _T_2358 = btb_rd_addr_f == 8'h7b; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_123; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_123; // @[lib.scala 374:16] wire [21:0] _T_2747 = _T_2358 ? btb_bank0_rd_data_way0_out_123 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3002 = _T_3001 | _T_2747; // @[Mux.scala 27:72] wire _T_2360 = btb_rd_addr_f == 8'h7c; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_124; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_124; // @[lib.scala 374:16] wire [21:0] _T_2748 = _T_2360 ? btb_bank0_rd_data_way0_out_124 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3003 = _T_3002 | _T_2748; // @[Mux.scala 27:72] wire _T_2362 = btb_rd_addr_f == 8'h7d; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_125; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_125; // @[lib.scala 374:16] wire [21:0] _T_2749 = _T_2362 ? btb_bank0_rd_data_way0_out_125 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3004 = _T_3003 | _T_2749; // @[Mux.scala 27:72] wire _T_2364 = btb_rd_addr_f == 8'h7e; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_126; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_126; // @[lib.scala 374:16] wire [21:0] _T_2750 = _T_2364 ? btb_bank0_rd_data_way0_out_126 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3005 = _T_3004 | _T_2750; // @[Mux.scala 27:72] wire _T_2366 = btb_rd_addr_f == 8'h7f; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_127; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_127; // @[lib.scala 374:16] wire [21:0] _T_2751 = _T_2366 ? btb_bank0_rd_data_way0_out_127 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3006 = _T_3005 | _T_2751; // @[Mux.scala 27:72] wire _T_2368 = btb_rd_addr_f == 8'h80; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_128; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_128; // @[lib.scala 374:16] wire [21:0] _T_2752 = _T_2368 ? btb_bank0_rd_data_way0_out_128 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3007 = _T_3006 | _T_2752; // @[Mux.scala 27:72] wire _T_2370 = btb_rd_addr_f == 8'h81; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_129; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_129; // @[lib.scala 374:16] wire [21:0] _T_2753 = _T_2370 ? btb_bank0_rd_data_way0_out_129 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3008 = _T_3007 | _T_2753; // @[Mux.scala 27:72] wire _T_2372 = btb_rd_addr_f == 8'h82; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_130; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_130; // @[lib.scala 374:16] wire [21:0] _T_2754 = _T_2372 ? btb_bank0_rd_data_way0_out_130 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3009 = _T_3008 | _T_2754; // @[Mux.scala 27:72] wire _T_2374 = btb_rd_addr_f == 8'h83; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_131; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_131; // @[lib.scala 374:16] wire [21:0] _T_2755 = _T_2374 ? btb_bank0_rd_data_way0_out_131 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3010 = _T_3009 | _T_2755; // @[Mux.scala 27:72] wire _T_2376 = btb_rd_addr_f == 8'h84; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_132; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_132; // @[lib.scala 374:16] wire [21:0] _T_2756 = _T_2376 ? btb_bank0_rd_data_way0_out_132 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3011 = _T_3010 | _T_2756; // @[Mux.scala 27:72] wire _T_2378 = btb_rd_addr_f == 8'h85; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_133; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_133; // @[lib.scala 374:16] wire [21:0] _T_2757 = _T_2378 ? btb_bank0_rd_data_way0_out_133 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3012 = _T_3011 | _T_2757; // @[Mux.scala 27:72] wire _T_2380 = btb_rd_addr_f == 8'h86; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_134; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_134; // @[lib.scala 374:16] wire [21:0] _T_2758 = _T_2380 ? btb_bank0_rd_data_way0_out_134 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3013 = _T_3012 | _T_2758; // @[Mux.scala 27:72] wire _T_2382 = btb_rd_addr_f == 8'h87; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_135; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_135; // @[lib.scala 374:16] wire [21:0] _T_2759 = _T_2382 ? btb_bank0_rd_data_way0_out_135 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3014 = _T_3013 | _T_2759; // @[Mux.scala 27:72] wire _T_2384 = btb_rd_addr_f == 8'h88; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_136; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_136; // @[lib.scala 374:16] wire [21:0] _T_2760 = _T_2384 ? btb_bank0_rd_data_way0_out_136 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3015 = _T_3014 | _T_2760; // @[Mux.scala 27:72] wire _T_2386 = btb_rd_addr_f == 8'h89; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_137; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_137; // @[lib.scala 374:16] wire [21:0] _T_2761 = _T_2386 ? btb_bank0_rd_data_way0_out_137 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3016 = _T_3015 | _T_2761; // @[Mux.scala 27:72] wire _T_2388 = btb_rd_addr_f == 8'h8a; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_138; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_138; // @[lib.scala 374:16] wire [21:0] _T_2762 = _T_2388 ? btb_bank0_rd_data_way0_out_138 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3017 = _T_3016 | _T_2762; // @[Mux.scala 27:72] wire _T_2390 = btb_rd_addr_f == 8'h8b; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_139; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_139; // @[lib.scala 374:16] wire [21:0] _T_2763 = _T_2390 ? btb_bank0_rd_data_way0_out_139 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3018 = _T_3017 | _T_2763; // @[Mux.scala 27:72] wire _T_2392 = btb_rd_addr_f == 8'h8c; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_140; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_140; // @[lib.scala 374:16] wire [21:0] _T_2764 = _T_2392 ? btb_bank0_rd_data_way0_out_140 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3019 = _T_3018 | _T_2764; // @[Mux.scala 27:72] wire _T_2394 = btb_rd_addr_f == 8'h8d; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_141; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_141; // @[lib.scala 374:16] wire [21:0] _T_2765 = _T_2394 ? btb_bank0_rd_data_way0_out_141 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3020 = _T_3019 | _T_2765; // @[Mux.scala 27:72] wire _T_2396 = btb_rd_addr_f == 8'h8e; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_142; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_142; // @[lib.scala 374:16] wire [21:0] _T_2766 = _T_2396 ? btb_bank0_rd_data_way0_out_142 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3021 = _T_3020 | _T_2766; // @[Mux.scala 27:72] wire _T_2398 = btb_rd_addr_f == 8'h8f; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_143; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_143; // @[lib.scala 374:16] wire [21:0] _T_2767 = _T_2398 ? btb_bank0_rd_data_way0_out_143 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3022 = _T_3021 | _T_2767; // @[Mux.scala 27:72] wire _T_2400 = btb_rd_addr_f == 8'h90; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_144; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_144; // @[lib.scala 374:16] wire [21:0] _T_2768 = _T_2400 ? btb_bank0_rd_data_way0_out_144 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3023 = _T_3022 | _T_2768; // @[Mux.scala 27:72] wire _T_2402 = btb_rd_addr_f == 8'h91; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_145; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_145; // @[lib.scala 374:16] wire [21:0] _T_2769 = _T_2402 ? btb_bank0_rd_data_way0_out_145 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3024 = _T_3023 | _T_2769; // @[Mux.scala 27:72] wire _T_2404 = btb_rd_addr_f == 8'h92; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_146; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_146; // @[lib.scala 374:16] wire [21:0] _T_2770 = _T_2404 ? btb_bank0_rd_data_way0_out_146 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3025 = _T_3024 | _T_2770; // @[Mux.scala 27:72] wire _T_2406 = btb_rd_addr_f == 8'h93; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_147; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_147; // @[lib.scala 374:16] wire [21:0] _T_2771 = _T_2406 ? btb_bank0_rd_data_way0_out_147 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3026 = _T_3025 | _T_2771; // @[Mux.scala 27:72] wire _T_2408 = btb_rd_addr_f == 8'h94; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_148; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_148; // @[lib.scala 374:16] wire [21:0] _T_2772 = _T_2408 ? btb_bank0_rd_data_way0_out_148 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3027 = _T_3026 | _T_2772; // @[Mux.scala 27:72] wire _T_2410 = btb_rd_addr_f == 8'h95; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_149; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_149; // @[lib.scala 374:16] wire [21:0] _T_2773 = _T_2410 ? btb_bank0_rd_data_way0_out_149 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3028 = _T_3027 | _T_2773; // @[Mux.scala 27:72] wire _T_2412 = btb_rd_addr_f == 8'h96; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_150; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_150; // @[lib.scala 374:16] wire [21:0] _T_2774 = _T_2412 ? btb_bank0_rd_data_way0_out_150 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3029 = _T_3028 | _T_2774; // @[Mux.scala 27:72] wire _T_2414 = btb_rd_addr_f == 8'h97; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_151; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_151; // @[lib.scala 374:16] wire [21:0] _T_2775 = _T_2414 ? btb_bank0_rd_data_way0_out_151 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3030 = _T_3029 | _T_2775; // @[Mux.scala 27:72] wire _T_2416 = btb_rd_addr_f == 8'h98; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_152; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_152; // @[lib.scala 374:16] wire [21:0] _T_2776 = _T_2416 ? btb_bank0_rd_data_way0_out_152 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3031 = _T_3030 | _T_2776; // @[Mux.scala 27:72] wire _T_2418 = btb_rd_addr_f == 8'h99; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_153; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_153; // @[lib.scala 374:16] wire [21:0] _T_2777 = _T_2418 ? btb_bank0_rd_data_way0_out_153 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3032 = _T_3031 | _T_2777; // @[Mux.scala 27:72] wire _T_2420 = btb_rd_addr_f == 8'h9a; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_154; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_154; // @[lib.scala 374:16] wire [21:0] _T_2778 = _T_2420 ? btb_bank0_rd_data_way0_out_154 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3033 = _T_3032 | _T_2778; // @[Mux.scala 27:72] wire _T_2422 = btb_rd_addr_f == 8'h9b; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_155; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_155; // @[lib.scala 374:16] wire [21:0] _T_2779 = _T_2422 ? btb_bank0_rd_data_way0_out_155 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3034 = _T_3033 | _T_2779; // @[Mux.scala 27:72] wire _T_2424 = btb_rd_addr_f == 8'h9c; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_156; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_156; // @[lib.scala 374:16] wire [21:0] _T_2780 = _T_2424 ? btb_bank0_rd_data_way0_out_156 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3035 = _T_3034 | _T_2780; // @[Mux.scala 27:72] wire _T_2426 = btb_rd_addr_f == 8'h9d; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_157; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_157; // @[lib.scala 374:16] wire [21:0] _T_2781 = _T_2426 ? btb_bank0_rd_data_way0_out_157 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3036 = _T_3035 | _T_2781; // @[Mux.scala 27:72] wire _T_2428 = btb_rd_addr_f == 8'h9e; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_158; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_158; // @[lib.scala 374:16] wire [21:0] _T_2782 = _T_2428 ? btb_bank0_rd_data_way0_out_158 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3037 = _T_3036 | _T_2782; // @[Mux.scala 27:72] wire _T_2430 = btb_rd_addr_f == 8'h9f; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_159; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_159; // @[lib.scala 374:16] wire [21:0] _T_2783 = _T_2430 ? btb_bank0_rd_data_way0_out_159 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3038 = _T_3037 | _T_2783; // @[Mux.scala 27:72] wire _T_2432 = btb_rd_addr_f == 8'ha0; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_160; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_160; // @[lib.scala 374:16] wire [21:0] _T_2784 = _T_2432 ? btb_bank0_rd_data_way0_out_160 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3039 = _T_3038 | _T_2784; // @[Mux.scala 27:72] wire _T_2434 = btb_rd_addr_f == 8'ha1; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_161; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_161; // @[lib.scala 374:16] wire [21:0] _T_2785 = _T_2434 ? btb_bank0_rd_data_way0_out_161 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3040 = _T_3039 | _T_2785; // @[Mux.scala 27:72] wire _T_2436 = btb_rd_addr_f == 8'ha2; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_162; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_162; // @[lib.scala 374:16] wire [21:0] _T_2786 = _T_2436 ? btb_bank0_rd_data_way0_out_162 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3041 = _T_3040 | _T_2786; // @[Mux.scala 27:72] wire _T_2438 = btb_rd_addr_f == 8'ha3; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_163; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_163; // @[lib.scala 374:16] wire [21:0] _T_2787 = _T_2438 ? btb_bank0_rd_data_way0_out_163 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3042 = _T_3041 | _T_2787; // @[Mux.scala 27:72] wire _T_2440 = btb_rd_addr_f == 8'ha4; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_164; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_164; // @[lib.scala 374:16] wire [21:0] _T_2788 = _T_2440 ? btb_bank0_rd_data_way0_out_164 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3043 = _T_3042 | _T_2788; // @[Mux.scala 27:72] wire _T_2442 = btb_rd_addr_f == 8'ha5; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_165; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_165; // @[lib.scala 374:16] wire [21:0] _T_2789 = _T_2442 ? btb_bank0_rd_data_way0_out_165 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3044 = _T_3043 | _T_2789; // @[Mux.scala 27:72] wire _T_2444 = btb_rd_addr_f == 8'ha6; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_166; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_166; // @[lib.scala 374:16] wire [21:0] _T_2790 = _T_2444 ? btb_bank0_rd_data_way0_out_166 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3045 = _T_3044 | _T_2790; // @[Mux.scala 27:72] wire _T_2446 = btb_rd_addr_f == 8'ha7; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_167; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_167; // @[lib.scala 374:16] wire [21:0] _T_2791 = _T_2446 ? btb_bank0_rd_data_way0_out_167 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3046 = _T_3045 | _T_2791; // @[Mux.scala 27:72] wire _T_2448 = btb_rd_addr_f == 8'ha8; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_168; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_168; // @[lib.scala 374:16] wire [21:0] _T_2792 = _T_2448 ? btb_bank0_rd_data_way0_out_168 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3047 = _T_3046 | _T_2792; // @[Mux.scala 27:72] wire _T_2450 = btb_rd_addr_f == 8'ha9; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_169; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_169; // @[lib.scala 374:16] wire [21:0] _T_2793 = _T_2450 ? btb_bank0_rd_data_way0_out_169 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3048 = _T_3047 | _T_2793; // @[Mux.scala 27:72] wire _T_2452 = btb_rd_addr_f == 8'haa; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_170; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_170; // @[lib.scala 374:16] wire [21:0] _T_2794 = _T_2452 ? btb_bank0_rd_data_way0_out_170 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3049 = _T_3048 | _T_2794; // @[Mux.scala 27:72] wire _T_2454 = btb_rd_addr_f == 8'hab; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_171; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_171; // @[lib.scala 374:16] wire [21:0] _T_2795 = _T_2454 ? btb_bank0_rd_data_way0_out_171 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3050 = _T_3049 | _T_2795; // @[Mux.scala 27:72] wire _T_2456 = btb_rd_addr_f == 8'hac; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_172; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_172; // @[lib.scala 374:16] wire [21:0] _T_2796 = _T_2456 ? btb_bank0_rd_data_way0_out_172 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3051 = _T_3050 | _T_2796; // @[Mux.scala 27:72] wire _T_2458 = btb_rd_addr_f == 8'had; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_173; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_173; // @[lib.scala 374:16] wire [21:0] _T_2797 = _T_2458 ? btb_bank0_rd_data_way0_out_173 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3052 = _T_3051 | _T_2797; // @[Mux.scala 27:72] wire _T_2460 = btb_rd_addr_f == 8'hae; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_174; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_174; // @[lib.scala 374:16] wire [21:0] _T_2798 = _T_2460 ? btb_bank0_rd_data_way0_out_174 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3053 = _T_3052 | _T_2798; // @[Mux.scala 27:72] wire _T_2462 = btb_rd_addr_f == 8'haf; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_175; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_175; // @[lib.scala 374:16] wire [21:0] _T_2799 = _T_2462 ? btb_bank0_rd_data_way0_out_175 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3054 = _T_3053 | _T_2799; // @[Mux.scala 27:72] wire _T_2464 = btb_rd_addr_f == 8'hb0; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_176; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_176; // @[lib.scala 374:16] wire [21:0] _T_2800 = _T_2464 ? btb_bank0_rd_data_way0_out_176 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3055 = _T_3054 | _T_2800; // @[Mux.scala 27:72] wire _T_2466 = btb_rd_addr_f == 8'hb1; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_177; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_177; // @[lib.scala 374:16] wire [21:0] _T_2801 = _T_2466 ? btb_bank0_rd_data_way0_out_177 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3056 = _T_3055 | _T_2801; // @[Mux.scala 27:72] wire _T_2468 = btb_rd_addr_f == 8'hb2; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_178; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_178; // @[lib.scala 374:16] wire [21:0] _T_2802 = _T_2468 ? btb_bank0_rd_data_way0_out_178 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3057 = _T_3056 | _T_2802; // @[Mux.scala 27:72] wire _T_2470 = btb_rd_addr_f == 8'hb3; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_179; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_179; // @[lib.scala 374:16] wire [21:0] _T_2803 = _T_2470 ? btb_bank0_rd_data_way0_out_179 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3058 = _T_3057 | _T_2803; // @[Mux.scala 27:72] wire _T_2472 = btb_rd_addr_f == 8'hb4; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_180; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_180; // @[lib.scala 374:16] wire [21:0] _T_2804 = _T_2472 ? btb_bank0_rd_data_way0_out_180 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3059 = _T_3058 | _T_2804; // @[Mux.scala 27:72] wire _T_2474 = btb_rd_addr_f == 8'hb5; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_181; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_181; // @[lib.scala 374:16] wire [21:0] _T_2805 = _T_2474 ? btb_bank0_rd_data_way0_out_181 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3060 = _T_3059 | _T_2805; // @[Mux.scala 27:72] wire _T_2476 = btb_rd_addr_f == 8'hb6; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_182; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_182; // @[lib.scala 374:16] wire [21:0] _T_2806 = _T_2476 ? btb_bank0_rd_data_way0_out_182 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3061 = _T_3060 | _T_2806; // @[Mux.scala 27:72] wire _T_2478 = btb_rd_addr_f == 8'hb7; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_183; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_183; // @[lib.scala 374:16] wire [21:0] _T_2807 = _T_2478 ? btb_bank0_rd_data_way0_out_183 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3062 = _T_3061 | _T_2807; // @[Mux.scala 27:72] wire _T_2480 = btb_rd_addr_f == 8'hb8; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_184; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_184; // @[lib.scala 374:16] wire [21:0] _T_2808 = _T_2480 ? btb_bank0_rd_data_way0_out_184 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3063 = _T_3062 | _T_2808; // @[Mux.scala 27:72] wire _T_2482 = btb_rd_addr_f == 8'hb9; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_185; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_185; // @[lib.scala 374:16] wire [21:0] _T_2809 = _T_2482 ? btb_bank0_rd_data_way0_out_185 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3064 = _T_3063 | _T_2809; // @[Mux.scala 27:72] wire _T_2484 = btb_rd_addr_f == 8'hba; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_186; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_186; // @[lib.scala 374:16] wire [21:0] _T_2810 = _T_2484 ? btb_bank0_rd_data_way0_out_186 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3065 = _T_3064 | _T_2810; // @[Mux.scala 27:72] wire _T_2486 = btb_rd_addr_f == 8'hbb; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_187; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_187; // @[lib.scala 374:16] wire [21:0] _T_2811 = _T_2486 ? btb_bank0_rd_data_way0_out_187 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3066 = _T_3065 | _T_2811; // @[Mux.scala 27:72] wire _T_2488 = btb_rd_addr_f == 8'hbc; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_188; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_188; // @[lib.scala 374:16] wire [21:0] _T_2812 = _T_2488 ? btb_bank0_rd_data_way0_out_188 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3067 = _T_3066 | _T_2812; // @[Mux.scala 27:72] wire _T_2490 = btb_rd_addr_f == 8'hbd; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_189; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_189; // @[lib.scala 374:16] wire [21:0] _T_2813 = _T_2490 ? btb_bank0_rd_data_way0_out_189 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3068 = _T_3067 | _T_2813; // @[Mux.scala 27:72] wire _T_2492 = btb_rd_addr_f == 8'hbe; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_190; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_190; // @[lib.scala 374:16] wire [21:0] _T_2814 = _T_2492 ? btb_bank0_rd_data_way0_out_190 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3069 = _T_3068 | _T_2814; // @[Mux.scala 27:72] wire _T_2494 = btb_rd_addr_f == 8'hbf; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_191; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_191; // @[lib.scala 374:16] wire [21:0] _T_2815 = _T_2494 ? btb_bank0_rd_data_way0_out_191 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3070 = _T_3069 | _T_2815; // @[Mux.scala 27:72] wire _T_2496 = btb_rd_addr_f == 8'hc0; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_192; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_192; // @[lib.scala 374:16] wire [21:0] _T_2816 = _T_2496 ? btb_bank0_rd_data_way0_out_192 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3071 = _T_3070 | _T_2816; // @[Mux.scala 27:72] wire _T_2498 = btb_rd_addr_f == 8'hc1; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_193; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_193; // @[lib.scala 374:16] wire [21:0] _T_2817 = _T_2498 ? btb_bank0_rd_data_way0_out_193 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3072 = _T_3071 | _T_2817; // @[Mux.scala 27:72] wire _T_2500 = btb_rd_addr_f == 8'hc2; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_194; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_194; // @[lib.scala 374:16] wire [21:0] _T_2818 = _T_2500 ? btb_bank0_rd_data_way0_out_194 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3073 = _T_3072 | _T_2818; // @[Mux.scala 27:72] wire _T_2502 = btb_rd_addr_f == 8'hc3; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_195; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_195; // @[lib.scala 374:16] wire [21:0] _T_2819 = _T_2502 ? btb_bank0_rd_data_way0_out_195 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3074 = _T_3073 | _T_2819; // @[Mux.scala 27:72] wire _T_2504 = btb_rd_addr_f == 8'hc4; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_196; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_196; // @[lib.scala 374:16] wire [21:0] _T_2820 = _T_2504 ? btb_bank0_rd_data_way0_out_196 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3075 = _T_3074 | _T_2820; // @[Mux.scala 27:72] wire _T_2506 = btb_rd_addr_f == 8'hc5; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_197; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_197; // @[lib.scala 374:16] wire [21:0] _T_2821 = _T_2506 ? btb_bank0_rd_data_way0_out_197 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3076 = _T_3075 | _T_2821; // @[Mux.scala 27:72] wire _T_2508 = btb_rd_addr_f == 8'hc6; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_198; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_198; // @[lib.scala 374:16] wire [21:0] _T_2822 = _T_2508 ? btb_bank0_rd_data_way0_out_198 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3077 = _T_3076 | _T_2822; // @[Mux.scala 27:72] wire _T_2510 = btb_rd_addr_f == 8'hc7; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_199; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_199; // @[lib.scala 374:16] wire [21:0] _T_2823 = _T_2510 ? btb_bank0_rd_data_way0_out_199 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3078 = _T_3077 | _T_2823; // @[Mux.scala 27:72] wire _T_2512 = btb_rd_addr_f == 8'hc8; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_200; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_200; // @[lib.scala 374:16] wire [21:0] _T_2824 = _T_2512 ? btb_bank0_rd_data_way0_out_200 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3079 = _T_3078 | _T_2824; // @[Mux.scala 27:72] wire _T_2514 = btb_rd_addr_f == 8'hc9; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_201; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_201; // @[lib.scala 374:16] wire [21:0] _T_2825 = _T_2514 ? btb_bank0_rd_data_way0_out_201 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3080 = _T_3079 | _T_2825; // @[Mux.scala 27:72] wire _T_2516 = btb_rd_addr_f == 8'hca; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_202; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_202; // @[lib.scala 374:16] wire [21:0] _T_2826 = _T_2516 ? btb_bank0_rd_data_way0_out_202 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3081 = _T_3080 | _T_2826; // @[Mux.scala 27:72] wire _T_2518 = btb_rd_addr_f == 8'hcb; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_203; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_203; // @[lib.scala 374:16] wire [21:0] _T_2827 = _T_2518 ? btb_bank0_rd_data_way0_out_203 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3082 = _T_3081 | _T_2827; // @[Mux.scala 27:72] wire _T_2520 = btb_rd_addr_f == 8'hcc; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_204; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_204; // @[lib.scala 374:16] wire [21:0] _T_2828 = _T_2520 ? btb_bank0_rd_data_way0_out_204 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3083 = _T_3082 | _T_2828; // @[Mux.scala 27:72] wire _T_2522 = btb_rd_addr_f == 8'hcd; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_205; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_205; // @[lib.scala 374:16] wire [21:0] _T_2829 = _T_2522 ? btb_bank0_rd_data_way0_out_205 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3084 = _T_3083 | _T_2829; // @[Mux.scala 27:72] wire _T_2524 = btb_rd_addr_f == 8'hce; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_206; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_206; // @[lib.scala 374:16] wire [21:0] _T_2830 = _T_2524 ? btb_bank0_rd_data_way0_out_206 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3085 = _T_3084 | _T_2830; // @[Mux.scala 27:72] wire _T_2526 = btb_rd_addr_f == 8'hcf; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_207; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_207; // @[lib.scala 374:16] wire [21:0] _T_2831 = _T_2526 ? btb_bank0_rd_data_way0_out_207 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3086 = _T_3085 | _T_2831; // @[Mux.scala 27:72] wire _T_2528 = btb_rd_addr_f == 8'hd0; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_208; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_208; // @[lib.scala 374:16] wire [21:0] _T_2832 = _T_2528 ? btb_bank0_rd_data_way0_out_208 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3087 = _T_3086 | _T_2832; // @[Mux.scala 27:72] wire _T_2530 = btb_rd_addr_f == 8'hd1; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_209; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_209; // @[lib.scala 374:16] wire [21:0] _T_2833 = _T_2530 ? btb_bank0_rd_data_way0_out_209 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3088 = _T_3087 | _T_2833; // @[Mux.scala 27:72] wire _T_2532 = btb_rd_addr_f == 8'hd2; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_210; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_210; // @[lib.scala 374:16] wire [21:0] _T_2834 = _T_2532 ? btb_bank0_rd_data_way0_out_210 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3089 = _T_3088 | _T_2834; // @[Mux.scala 27:72] wire _T_2534 = btb_rd_addr_f == 8'hd3; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_211; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_211; // @[lib.scala 374:16] wire [21:0] _T_2835 = _T_2534 ? btb_bank0_rd_data_way0_out_211 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3090 = _T_3089 | _T_2835; // @[Mux.scala 27:72] wire _T_2536 = btb_rd_addr_f == 8'hd4; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_212; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_212; // @[lib.scala 374:16] wire [21:0] _T_2836 = _T_2536 ? btb_bank0_rd_data_way0_out_212 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3091 = _T_3090 | _T_2836; // @[Mux.scala 27:72] wire _T_2538 = btb_rd_addr_f == 8'hd5; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_213; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_213; // @[lib.scala 374:16] wire [21:0] _T_2837 = _T_2538 ? btb_bank0_rd_data_way0_out_213 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3092 = _T_3091 | _T_2837; // @[Mux.scala 27:72] wire _T_2540 = btb_rd_addr_f == 8'hd6; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_214; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_214; // @[lib.scala 374:16] wire [21:0] _T_2838 = _T_2540 ? btb_bank0_rd_data_way0_out_214 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3093 = _T_3092 | _T_2838; // @[Mux.scala 27:72] wire _T_2542 = btb_rd_addr_f == 8'hd7; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_215; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_215; // @[lib.scala 374:16] wire [21:0] _T_2839 = _T_2542 ? btb_bank0_rd_data_way0_out_215 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3094 = _T_3093 | _T_2839; // @[Mux.scala 27:72] wire _T_2544 = btb_rd_addr_f == 8'hd8; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_216; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_216; // @[lib.scala 374:16] wire [21:0] _T_2840 = _T_2544 ? btb_bank0_rd_data_way0_out_216 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3095 = _T_3094 | _T_2840; // @[Mux.scala 27:72] wire _T_2546 = btb_rd_addr_f == 8'hd9; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_217; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_217; // @[lib.scala 374:16] wire [21:0] _T_2841 = _T_2546 ? btb_bank0_rd_data_way0_out_217 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3096 = _T_3095 | _T_2841; // @[Mux.scala 27:72] wire _T_2548 = btb_rd_addr_f == 8'hda; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_218; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_218; // @[lib.scala 374:16] wire [21:0] _T_2842 = _T_2548 ? btb_bank0_rd_data_way0_out_218 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3097 = _T_3096 | _T_2842; // @[Mux.scala 27:72] wire _T_2550 = btb_rd_addr_f == 8'hdb; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_219; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_219; // @[lib.scala 374:16] wire [21:0] _T_2843 = _T_2550 ? btb_bank0_rd_data_way0_out_219 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3098 = _T_3097 | _T_2843; // @[Mux.scala 27:72] wire _T_2552 = btb_rd_addr_f == 8'hdc; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_220; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_220; // @[lib.scala 374:16] wire [21:0] _T_2844 = _T_2552 ? btb_bank0_rd_data_way0_out_220 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3099 = _T_3098 | _T_2844; // @[Mux.scala 27:72] wire _T_2554 = btb_rd_addr_f == 8'hdd; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_221; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_221; // @[lib.scala 374:16] wire [21:0] _T_2845 = _T_2554 ? btb_bank0_rd_data_way0_out_221 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3100 = _T_3099 | _T_2845; // @[Mux.scala 27:72] wire _T_2556 = btb_rd_addr_f == 8'hde; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_222; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_222; // @[lib.scala 374:16] wire [21:0] _T_2846 = _T_2556 ? btb_bank0_rd_data_way0_out_222 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3101 = _T_3100 | _T_2846; // @[Mux.scala 27:72] wire _T_2558 = btb_rd_addr_f == 8'hdf; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_223; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_223; // @[lib.scala 374:16] wire [21:0] _T_2847 = _T_2558 ? btb_bank0_rd_data_way0_out_223 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3102 = _T_3101 | _T_2847; // @[Mux.scala 27:72] wire _T_2560 = btb_rd_addr_f == 8'he0; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_224; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_224; // @[lib.scala 374:16] wire [21:0] _T_2848 = _T_2560 ? btb_bank0_rd_data_way0_out_224 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3103 = _T_3102 | _T_2848; // @[Mux.scala 27:72] wire _T_2562 = btb_rd_addr_f == 8'he1; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_225; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_225; // @[lib.scala 374:16] wire [21:0] _T_2849 = _T_2562 ? btb_bank0_rd_data_way0_out_225 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3104 = _T_3103 | _T_2849; // @[Mux.scala 27:72] wire _T_2564 = btb_rd_addr_f == 8'he2; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_226; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_226; // @[lib.scala 374:16] wire [21:0] _T_2850 = _T_2564 ? btb_bank0_rd_data_way0_out_226 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3105 = _T_3104 | _T_2850; // @[Mux.scala 27:72] wire _T_2566 = btb_rd_addr_f == 8'he3; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_227; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_227; // @[lib.scala 374:16] wire [21:0] _T_2851 = _T_2566 ? btb_bank0_rd_data_way0_out_227 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3106 = _T_3105 | _T_2851; // @[Mux.scala 27:72] wire _T_2568 = btb_rd_addr_f == 8'he4; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_228; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_228; // @[lib.scala 374:16] wire [21:0] _T_2852 = _T_2568 ? btb_bank0_rd_data_way0_out_228 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3107 = _T_3106 | _T_2852; // @[Mux.scala 27:72] wire _T_2570 = btb_rd_addr_f == 8'he5; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_229; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_229; // @[lib.scala 374:16] wire [21:0] _T_2853 = _T_2570 ? btb_bank0_rd_data_way0_out_229 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3108 = _T_3107 | _T_2853; // @[Mux.scala 27:72] wire _T_2572 = btb_rd_addr_f == 8'he6; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_230; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_230; // @[lib.scala 374:16] wire [21:0] _T_2854 = _T_2572 ? btb_bank0_rd_data_way0_out_230 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3109 = _T_3108 | _T_2854; // @[Mux.scala 27:72] wire _T_2574 = btb_rd_addr_f == 8'he7; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_231; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_231; // @[lib.scala 374:16] wire [21:0] _T_2855 = _T_2574 ? btb_bank0_rd_data_way0_out_231 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3110 = _T_3109 | _T_2855; // @[Mux.scala 27:72] wire _T_2576 = btb_rd_addr_f == 8'he8; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_232; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_232; // @[lib.scala 374:16] wire [21:0] _T_2856 = _T_2576 ? btb_bank0_rd_data_way0_out_232 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3111 = _T_3110 | _T_2856; // @[Mux.scala 27:72] wire _T_2578 = btb_rd_addr_f == 8'he9; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_233; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_233; // @[lib.scala 374:16] wire [21:0] _T_2857 = _T_2578 ? btb_bank0_rd_data_way0_out_233 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3112 = _T_3111 | _T_2857; // @[Mux.scala 27:72] wire _T_2580 = btb_rd_addr_f == 8'hea; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_234; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_234; // @[lib.scala 374:16] wire [21:0] _T_2858 = _T_2580 ? btb_bank0_rd_data_way0_out_234 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3113 = _T_3112 | _T_2858; // @[Mux.scala 27:72] wire _T_2582 = btb_rd_addr_f == 8'heb; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_235; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_235; // @[lib.scala 374:16] wire [21:0] _T_2859 = _T_2582 ? btb_bank0_rd_data_way0_out_235 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3114 = _T_3113 | _T_2859; // @[Mux.scala 27:72] wire _T_2584 = btb_rd_addr_f == 8'hec; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_236; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_236; // @[lib.scala 374:16] wire [21:0] _T_2860 = _T_2584 ? btb_bank0_rd_data_way0_out_236 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3115 = _T_3114 | _T_2860; // @[Mux.scala 27:72] wire _T_2586 = btb_rd_addr_f == 8'hed; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_237; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_237; // @[lib.scala 374:16] wire [21:0] _T_2861 = _T_2586 ? btb_bank0_rd_data_way0_out_237 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3116 = _T_3115 | _T_2861; // @[Mux.scala 27:72] wire _T_2588 = btb_rd_addr_f == 8'hee; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_238; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_238; // @[lib.scala 374:16] wire [21:0] _T_2862 = _T_2588 ? btb_bank0_rd_data_way0_out_238 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3117 = _T_3116 | _T_2862; // @[Mux.scala 27:72] wire _T_2590 = btb_rd_addr_f == 8'hef; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_239; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_239; // @[lib.scala 374:16] wire [21:0] _T_2863 = _T_2590 ? btb_bank0_rd_data_way0_out_239 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3118 = _T_3117 | _T_2863; // @[Mux.scala 27:72] wire _T_2592 = btb_rd_addr_f == 8'hf0; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_240; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_240; // @[lib.scala 374:16] wire [21:0] _T_2864 = _T_2592 ? btb_bank0_rd_data_way0_out_240 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3119 = _T_3118 | _T_2864; // @[Mux.scala 27:72] wire _T_2594 = btb_rd_addr_f == 8'hf1; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_241; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_241; // @[lib.scala 374:16] wire [21:0] _T_2865 = _T_2594 ? btb_bank0_rd_data_way0_out_241 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3120 = _T_3119 | _T_2865; // @[Mux.scala 27:72] wire _T_2596 = btb_rd_addr_f == 8'hf2; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_242; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_242; // @[lib.scala 374:16] wire [21:0] _T_2866 = _T_2596 ? btb_bank0_rd_data_way0_out_242 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3121 = _T_3120 | _T_2866; // @[Mux.scala 27:72] wire _T_2598 = btb_rd_addr_f == 8'hf3; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_243; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_243; // @[lib.scala 374:16] wire [21:0] _T_2867 = _T_2598 ? btb_bank0_rd_data_way0_out_243 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3122 = _T_3121 | _T_2867; // @[Mux.scala 27:72] wire _T_2600 = btb_rd_addr_f == 8'hf4; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_244; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_244; // @[lib.scala 374:16] wire [21:0] _T_2868 = _T_2600 ? btb_bank0_rd_data_way0_out_244 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3123 = _T_3122 | _T_2868; // @[Mux.scala 27:72] wire _T_2602 = btb_rd_addr_f == 8'hf5; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_245; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_245; // @[lib.scala 374:16] wire [21:0] _T_2869 = _T_2602 ? btb_bank0_rd_data_way0_out_245 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3124 = _T_3123 | _T_2869; // @[Mux.scala 27:72] wire _T_2604 = btb_rd_addr_f == 8'hf6; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_246; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_246; // @[lib.scala 374:16] wire [21:0] _T_2870 = _T_2604 ? btb_bank0_rd_data_way0_out_246 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3125 = _T_3124 | _T_2870; // @[Mux.scala 27:72] wire _T_2606 = btb_rd_addr_f == 8'hf7; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_247; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_247; // @[lib.scala 374:16] wire [21:0] _T_2871 = _T_2606 ? btb_bank0_rd_data_way0_out_247 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3126 = _T_3125 | _T_2871; // @[Mux.scala 27:72] wire _T_2608 = btb_rd_addr_f == 8'hf8; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_248; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_248; // @[lib.scala 374:16] wire [21:0] _T_2872 = _T_2608 ? btb_bank0_rd_data_way0_out_248 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3127 = _T_3126 | _T_2872; // @[Mux.scala 27:72] wire _T_2610 = btb_rd_addr_f == 8'hf9; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_249; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_249; // @[lib.scala 374:16] wire [21:0] _T_2873 = _T_2610 ? btb_bank0_rd_data_way0_out_249 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3128 = _T_3127 | _T_2873; // @[Mux.scala 27:72] wire _T_2612 = btb_rd_addr_f == 8'hfa; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_250; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_250; // @[lib.scala 374:16] wire [21:0] _T_2874 = _T_2612 ? btb_bank0_rd_data_way0_out_250 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3129 = _T_3128 | _T_2874; // @[Mux.scala 27:72] wire _T_2614 = btb_rd_addr_f == 8'hfb; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_251; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_251; // @[lib.scala 374:16] wire [21:0] _T_2875 = _T_2614 ? btb_bank0_rd_data_way0_out_251 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3130 = _T_3129 | _T_2875; // @[Mux.scala 27:72] wire _T_2616 = btb_rd_addr_f == 8'hfc; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_252; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_252; // @[lib.scala 374:16] wire [21:0] _T_2876 = _T_2616 ? btb_bank0_rd_data_way0_out_252 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3131 = _T_3130 | _T_2876; // @[Mux.scala 27:72] wire _T_2618 = btb_rd_addr_f == 8'hfd; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_253; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_253; // @[lib.scala 374:16] wire [21:0] _T_2877 = _T_2618 ? btb_bank0_rd_data_way0_out_253 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3132 = _T_3131 | _T_2877; // @[Mux.scala 27:72] wire _T_2620 = btb_rd_addr_f == 8'hfe; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_254; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_254; // @[lib.scala 374:16] wire [21:0] _T_2878 = _T_2620 ? btb_bank0_rd_data_way0_out_254 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3133 = _T_3132 | _T_2878; // @[Mux.scala 27:72] wire _T_2622 = btb_rd_addr_f == 8'hff; // @[ifu_bp_ctl.scala 418:77] - reg [21:0] btb_bank0_rd_data_way0_out_255; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way0_out_255; // @[lib.scala 374:16] wire [21:0] _T_2879 = _T_2622 ? btb_bank0_rd_data_way0_out_255 : 22'h0; // @[Mux.scala 27:72] wire [21:0] btb_bank0_rd_data_way0_f = _T_3133 | _T_2879; // @[Mux.scala 27:72] - wire [4:0] _T_25 = io_ifc_fetch_addr_f[13:9] ^ io_ifc_fetch_addr_f[18:14]; // @[el2_lib.scala 182:111] - wire [4:0] fetch_rd_tag_f = _T_25 ^ io_ifc_fetch_addr_f[23:19]; // @[el2_lib.scala 182:111] + wire [4:0] _T_25 = io_ifc_fetch_addr_f[13:9] ^ io_ifc_fetch_addr_f[18:14]; // @[lib.scala 42:111] + wire [4:0] fetch_rd_tag_f = _T_25 ^ io_ifc_fetch_addr_f[23:19]; // @[lib.scala 42:111] wire _T_46 = btb_bank0_rd_data_way0_f[21:17] == fetch_rd_tag_f; // @[ifu_bp_ctl.scala 127:97] wire _T_47 = btb_bank0_rd_data_way0_f[0] & _T_46; // @[ifu_bp_ctl.scala 127:55] reg dec_tlu_way_wb_f; // @[ifu_bp_ctl.scala 118:59] @@ -16224,771 +16224,771 @@ module ifu_bp_ctl( wire _T_88 = tag_match_way0_f & _T_87; // @[ifu_bp_ctl.scala 143:56] wire [1:0] tag_match_way0_expanded_f = {_T_83,_T_88}; // @[Cat.scala 29:58] wire [21:0] _T_127 = tag_match_way0_expanded_f[1] ? btb_bank0_rd_data_way0_f : 22'h0; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_0; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_0; // @[lib.scala 374:16] wire [21:0] _T_3648 = _T_2112 ? btb_bank0_rd_data_way1_out_0 : 22'h0; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_1; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_1; // @[lib.scala 374:16] wire [21:0] _T_3649 = _T_2114 ? btb_bank0_rd_data_way1_out_1 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3904 = _T_3648 | _T_3649; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_2; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_2; // @[lib.scala 374:16] wire [21:0] _T_3650 = _T_2116 ? btb_bank0_rd_data_way1_out_2 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3905 = _T_3904 | _T_3650; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_3; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_3; // @[lib.scala 374:16] wire [21:0] _T_3651 = _T_2118 ? btb_bank0_rd_data_way1_out_3 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3906 = _T_3905 | _T_3651; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_4; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_4; // @[lib.scala 374:16] wire [21:0] _T_3652 = _T_2120 ? btb_bank0_rd_data_way1_out_4 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3907 = _T_3906 | _T_3652; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_5; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_5; // @[lib.scala 374:16] wire [21:0] _T_3653 = _T_2122 ? btb_bank0_rd_data_way1_out_5 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3908 = _T_3907 | _T_3653; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_6; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_6; // @[lib.scala 374:16] wire [21:0] _T_3654 = _T_2124 ? btb_bank0_rd_data_way1_out_6 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3909 = _T_3908 | _T_3654; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_7; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_7; // @[lib.scala 374:16] wire [21:0] _T_3655 = _T_2126 ? btb_bank0_rd_data_way1_out_7 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3910 = _T_3909 | _T_3655; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_8; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_8; // @[lib.scala 374:16] wire [21:0] _T_3656 = _T_2128 ? btb_bank0_rd_data_way1_out_8 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3911 = _T_3910 | _T_3656; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_9; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_9; // @[lib.scala 374:16] wire [21:0] _T_3657 = _T_2130 ? btb_bank0_rd_data_way1_out_9 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3912 = _T_3911 | _T_3657; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_10; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_10; // @[lib.scala 374:16] wire [21:0] _T_3658 = _T_2132 ? btb_bank0_rd_data_way1_out_10 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3913 = _T_3912 | _T_3658; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_11; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_11; // @[lib.scala 374:16] wire [21:0] _T_3659 = _T_2134 ? btb_bank0_rd_data_way1_out_11 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3914 = _T_3913 | _T_3659; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_12; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_12; // @[lib.scala 374:16] wire [21:0] _T_3660 = _T_2136 ? btb_bank0_rd_data_way1_out_12 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3915 = _T_3914 | _T_3660; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_13; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_13; // @[lib.scala 374:16] wire [21:0] _T_3661 = _T_2138 ? btb_bank0_rd_data_way1_out_13 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3916 = _T_3915 | _T_3661; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_14; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_14; // @[lib.scala 374:16] wire [21:0] _T_3662 = _T_2140 ? btb_bank0_rd_data_way1_out_14 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3917 = _T_3916 | _T_3662; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_15; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_15; // @[lib.scala 374:16] wire [21:0] _T_3663 = _T_2142 ? btb_bank0_rd_data_way1_out_15 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3918 = _T_3917 | _T_3663; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_16; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_16; // @[lib.scala 374:16] wire [21:0] _T_3664 = _T_2144 ? btb_bank0_rd_data_way1_out_16 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3919 = _T_3918 | _T_3664; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_17; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_17; // @[lib.scala 374:16] wire [21:0] _T_3665 = _T_2146 ? btb_bank0_rd_data_way1_out_17 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3920 = _T_3919 | _T_3665; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_18; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_18; // @[lib.scala 374:16] wire [21:0] _T_3666 = _T_2148 ? btb_bank0_rd_data_way1_out_18 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3921 = _T_3920 | _T_3666; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_19; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_19; // @[lib.scala 374:16] wire [21:0] _T_3667 = _T_2150 ? btb_bank0_rd_data_way1_out_19 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3922 = _T_3921 | _T_3667; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_20; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_20; // @[lib.scala 374:16] wire [21:0] _T_3668 = _T_2152 ? btb_bank0_rd_data_way1_out_20 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3923 = _T_3922 | _T_3668; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_21; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_21; // @[lib.scala 374:16] wire [21:0] _T_3669 = _T_2154 ? btb_bank0_rd_data_way1_out_21 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3924 = _T_3923 | _T_3669; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_22; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_22; // @[lib.scala 374:16] wire [21:0] _T_3670 = _T_2156 ? btb_bank0_rd_data_way1_out_22 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3925 = _T_3924 | _T_3670; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_23; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_23; // @[lib.scala 374:16] wire [21:0] _T_3671 = _T_2158 ? btb_bank0_rd_data_way1_out_23 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3926 = _T_3925 | _T_3671; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_24; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_24; // @[lib.scala 374:16] wire [21:0] _T_3672 = _T_2160 ? btb_bank0_rd_data_way1_out_24 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3927 = _T_3926 | _T_3672; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_25; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_25; // @[lib.scala 374:16] wire [21:0] _T_3673 = _T_2162 ? btb_bank0_rd_data_way1_out_25 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3928 = _T_3927 | _T_3673; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_26; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_26; // @[lib.scala 374:16] wire [21:0] _T_3674 = _T_2164 ? btb_bank0_rd_data_way1_out_26 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3929 = _T_3928 | _T_3674; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_27; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_27; // @[lib.scala 374:16] wire [21:0] _T_3675 = _T_2166 ? btb_bank0_rd_data_way1_out_27 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3930 = _T_3929 | _T_3675; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_28; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_28; // @[lib.scala 374:16] wire [21:0] _T_3676 = _T_2168 ? btb_bank0_rd_data_way1_out_28 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3931 = _T_3930 | _T_3676; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_29; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_29; // @[lib.scala 374:16] wire [21:0] _T_3677 = _T_2170 ? btb_bank0_rd_data_way1_out_29 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3932 = _T_3931 | _T_3677; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_30; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_30; // @[lib.scala 374:16] wire [21:0] _T_3678 = _T_2172 ? btb_bank0_rd_data_way1_out_30 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3933 = _T_3932 | _T_3678; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_31; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_31; // @[lib.scala 374:16] wire [21:0] _T_3679 = _T_2174 ? btb_bank0_rd_data_way1_out_31 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3934 = _T_3933 | _T_3679; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_32; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_32; // @[lib.scala 374:16] wire [21:0] _T_3680 = _T_2176 ? btb_bank0_rd_data_way1_out_32 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3935 = _T_3934 | _T_3680; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_33; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_33; // @[lib.scala 374:16] wire [21:0] _T_3681 = _T_2178 ? btb_bank0_rd_data_way1_out_33 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3936 = _T_3935 | _T_3681; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_34; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_34; // @[lib.scala 374:16] wire [21:0] _T_3682 = _T_2180 ? btb_bank0_rd_data_way1_out_34 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3937 = _T_3936 | _T_3682; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_35; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_35; // @[lib.scala 374:16] wire [21:0] _T_3683 = _T_2182 ? btb_bank0_rd_data_way1_out_35 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3938 = _T_3937 | _T_3683; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_36; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_36; // @[lib.scala 374:16] wire [21:0] _T_3684 = _T_2184 ? btb_bank0_rd_data_way1_out_36 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3939 = _T_3938 | _T_3684; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_37; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_37; // @[lib.scala 374:16] wire [21:0] _T_3685 = _T_2186 ? btb_bank0_rd_data_way1_out_37 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3940 = _T_3939 | _T_3685; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_38; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_38; // @[lib.scala 374:16] wire [21:0] _T_3686 = _T_2188 ? btb_bank0_rd_data_way1_out_38 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3941 = _T_3940 | _T_3686; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_39; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_39; // @[lib.scala 374:16] wire [21:0] _T_3687 = _T_2190 ? btb_bank0_rd_data_way1_out_39 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3942 = _T_3941 | _T_3687; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_40; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_40; // @[lib.scala 374:16] wire [21:0] _T_3688 = _T_2192 ? btb_bank0_rd_data_way1_out_40 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3943 = _T_3942 | _T_3688; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_41; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_41; // @[lib.scala 374:16] wire [21:0] _T_3689 = _T_2194 ? btb_bank0_rd_data_way1_out_41 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3944 = _T_3943 | _T_3689; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_42; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_42; // @[lib.scala 374:16] wire [21:0] _T_3690 = _T_2196 ? btb_bank0_rd_data_way1_out_42 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3945 = _T_3944 | _T_3690; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_43; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_43; // @[lib.scala 374:16] wire [21:0] _T_3691 = _T_2198 ? btb_bank0_rd_data_way1_out_43 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3946 = _T_3945 | _T_3691; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_44; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_44; // @[lib.scala 374:16] wire [21:0] _T_3692 = _T_2200 ? btb_bank0_rd_data_way1_out_44 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3947 = _T_3946 | _T_3692; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_45; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_45; // @[lib.scala 374:16] wire [21:0] _T_3693 = _T_2202 ? btb_bank0_rd_data_way1_out_45 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3948 = _T_3947 | _T_3693; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_46; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_46; // @[lib.scala 374:16] wire [21:0] _T_3694 = _T_2204 ? btb_bank0_rd_data_way1_out_46 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3949 = _T_3948 | _T_3694; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_47; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_47; // @[lib.scala 374:16] wire [21:0] _T_3695 = _T_2206 ? btb_bank0_rd_data_way1_out_47 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3950 = _T_3949 | _T_3695; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_48; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_48; // @[lib.scala 374:16] wire [21:0] _T_3696 = _T_2208 ? btb_bank0_rd_data_way1_out_48 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3951 = _T_3950 | _T_3696; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_49; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_49; // @[lib.scala 374:16] wire [21:0] _T_3697 = _T_2210 ? btb_bank0_rd_data_way1_out_49 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3952 = _T_3951 | _T_3697; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_50; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_50; // @[lib.scala 374:16] wire [21:0] _T_3698 = _T_2212 ? btb_bank0_rd_data_way1_out_50 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3953 = _T_3952 | _T_3698; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_51; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_51; // @[lib.scala 374:16] wire [21:0] _T_3699 = _T_2214 ? btb_bank0_rd_data_way1_out_51 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3954 = _T_3953 | _T_3699; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_52; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_52; // @[lib.scala 374:16] wire [21:0] _T_3700 = _T_2216 ? btb_bank0_rd_data_way1_out_52 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3955 = _T_3954 | _T_3700; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_53; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_53; // @[lib.scala 374:16] wire [21:0] _T_3701 = _T_2218 ? btb_bank0_rd_data_way1_out_53 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3956 = _T_3955 | _T_3701; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_54; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_54; // @[lib.scala 374:16] wire [21:0] _T_3702 = _T_2220 ? btb_bank0_rd_data_way1_out_54 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3957 = _T_3956 | _T_3702; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_55; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_55; // @[lib.scala 374:16] wire [21:0] _T_3703 = _T_2222 ? btb_bank0_rd_data_way1_out_55 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3958 = _T_3957 | _T_3703; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_56; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_56; // @[lib.scala 374:16] wire [21:0] _T_3704 = _T_2224 ? btb_bank0_rd_data_way1_out_56 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3959 = _T_3958 | _T_3704; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_57; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_57; // @[lib.scala 374:16] wire [21:0] _T_3705 = _T_2226 ? btb_bank0_rd_data_way1_out_57 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3960 = _T_3959 | _T_3705; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_58; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_58; // @[lib.scala 374:16] wire [21:0] _T_3706 = _T_2228 ? btb_bank0_rd_data_way1_out_58 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3961 = _T_3960 | _T_3706; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_59; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_59; // @[lib.scala 374:16] wire [21:0] _T_3707 = _T_2230 ? btb_bank0_rd_data_way1_out_59 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3962 = _T_3961 | _T_3707; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_60; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_60; // @[lib.scala 374:16] wire [21:0] _T_3708 = _T_2232 ? btb_bank0_rd_data_way1_out_60 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3963 = _T_3962 | _T_3708; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_61; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_61; // @[lib.scala 374:16] wire [21:0] _T_3709 = _T_2234 ? btb_bank0_rd_data_way1_out_61 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3964 = _T_3963 | _T_3709; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_62; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_62; // @[lib.scala 374:16] wire [21:0] _T_3710 = _T_2236 ? btb_bank0_rd_data_way1_out_62 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3965 = _T_3964 | _T_3710; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_63; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_63; // @[lib.scala 374:16] wire [21:0] _T_3711 = _T_2238 ? btb_bank0_rd_data_way1_out_63 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3966 = _T_3965 | _T_3711; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_64; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_64; // @[lib.scala 374:16] wire [21:0] _T_3712 = _T_2240 ? btb_bank0_rd_data_way1_out_64 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3967 = _T_3966 | _T_3712; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_65; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_65; // @[lib.scala 374:16] wire [21:0] _T_3713 = _T_2242 ? btb_bank0_rd_data_way1_out_65 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3968 = _T_3967 | _T_3713; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_66; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_66; // @[lib.scala 374:16] wire [21:0] _T_3714 = _T_2244 ? btb_bank0_rd_data_way1_out_66 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3969 = _T_3968 | _T_3714; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_67; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_67; // @[lib.scala 374:16] wire [21:0] _T_3715 = _T_2246 ? btb_bank0_rd_data_way1_out_67 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3970 = _T_3969 | _T_3715; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_68; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_68; // @[lib.scala 374:16] wire [21:0] _T_3716 = _T_2248 ? btb_bank0_rd_data_way1_out_68 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3971 = _T_3970 | _T_3716; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_69; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_69; // @[lib.scala 374:16] wire [21:0] _T_3717 = _T_2250 ? btb_bank0_rd_data_way1_out_69 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3972 = _T_3971 | _T_3717; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_70; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_70; // @[lib.scala 374:16] wire [21:0] _T_3718 = _T_2252 ? btb_bank0_rd_data_way1_out_70 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3973 = _T_3972 | _T_3718; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_71; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_71; // @[lib.scala 374:16] wire [21:0] _T_3719 = _T_2254 ? btb_bank0_rd_data_way1_out_71 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3974 = _T_3973 | _T_3719; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_72; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_72; // @[lib.scala 374:16] wire [21:0] _T_3720 = _T_2256 ? btb_bank0_rd_data_way1_out_72 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3975 = _T_3974 | _T_3720; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_73; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_73; // @[lib.scala 374:16] wire [21:0] _T_3721 = _T_2258 ? btb_bank0_rd_data_way1_out_73 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3976 = _T_3975 | _T_3721; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_74; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_74; // @[lib.scala 374:16] wire [21:0] _T_3722 = _T_2260 ? btb_bank0_rd_data_way1_out_74 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3977 = _T_3976 | _T_3722; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_75; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_75; // @[lib.scala 374:16] wire [21:0] _T_3723 = _T_2262 ? btb_bank0_rd_data_way1_out_75 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3978 = _T_3977 | _T_3723; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_76; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_76; // @[lib.scala 374:16] wire [21:0] _T_3724 = _T_2264 ? btb_bank0_rd_data_way1_out_76 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3979 = _T_3978 | _T_3724; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_77; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_77; // @[lib.scala 374:16] wire [21:0] _T_3725 = _T_2266 ? btb_bank0_rd_data_way1_out_77 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3980 = _T_3979 | _T_3725; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_78; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_78; // @[lib.scala 374:16] wire [21:0] _T_3726 = _T_2268 ? btb_bank0_rd_data_way1_out_78 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3981 = _T_3980 | _T_3726; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_79; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_79; // @[lib.scala 374:16] wire [21:0] _T_3727 = _T_2270 ? btb_bank0_rd_data_way1_out_79 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3982 = _T_3981 | _T_3727; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_80; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_80; // @[lib.scala 374:16] wire [21:0] _T_3728 = _T_2272 ? btb_bank0_rd_data_way1_out_80 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3983 = _T_3982 | _T_3728; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_81; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_81; // @[lib.scala 374:16] wire [21:0] _T_3729 = _T_2274 ? btb_bank0_rd_data_way1_out_81 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3984 = _T_3983 | _T_3729; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_82; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_82; // @[lib.scala 374:16] wire [21:0] _T_3730 = _T_2276 ? btb_bank0_rd_data_way1_out_82 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3985 = _T_3984 | _T_3730; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_83; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_83; // @[lib.scala 374:16] wire [21:0] _T_3731 = _T_2278 ? btb_bank0_rd_data_way1_out_83 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3986 = _T_3985 | _T_3731; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_84; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_84; // @[lib.scala 374:16] wire [21:0] _T_3732 = _T_2280 ? btb_bank0_rd_data_way1_out_84 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3987 = _T_3986 | _T_3732; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_85; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_85; // @[lib.scala 374:16] wire [21:0] _T_3733 = _T_2282 ? btb_bank0_rd_data_way1_out_85 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3988 = _T_3987 | _T_3733; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_86; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_86; // @[lib.scala 374:16] wire [21:0] _T_3734 = _T_2284 ? btb_bank0_rd_data_way1_out_86 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3989 = _T_3988 | _T_3734; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_87; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_87; // @[lib.scala 374:16] wire [21:0] _T_3735 = _T_2286 ? btb_bank0_rd_data_way1_out_87 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3990 = _T_3989 | _T_3735; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_88; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_88; // @[lib.scala 374:16] wire [21:0] _T_3736 = _T_2288 ? btb_bank0_rd_data_way1_out_88 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3991 = _T_3990 | _T_3736; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_89; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_89; // @[lib.scala 374:16] wire [21:0] _T_3737 = _T_2290 ? btb_bank0_rd_data_way1_out_89 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3992 = _T_3991 | _T_3737; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_90; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_90; // @[lib.scala 374:16] wire [21:0] _T_3738 = _T_2292 ? btb_bank0_rd_data_way1_out_90 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3993 = _T_3992 | _T_3738; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_91; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_91; // @[lib.scala 374:16] wire [21:0] _T_3739 = _T_2294 ? btb_bank0_rd_data_way1_out_91 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3994 = _T_3993 | _T_3739; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_92; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_92; // @[lib.scala 374:16] wire [21:0] _T_3740 = _T_2296 ? btb_bank0_rd_data_way1_out_92 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3995 = _T_3994 | _T_3740; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_93; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_93; // @[lib.scala 374:16] wire [21:0] _T_3741 = _T_2298 ? btb_bank0_rd_data_way1_out_93 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3996 = _T_3995 | _T_3741; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_94; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_94; // @[lib.scala 374:16] wire [21:0] _T_3742 = _T_2300 ? btb_bank0_rd_data_way1_out_94 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3997 = _T_3996 | _T_3742; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_95; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_95; // @[lib.scala 374:16] wire [21:0] _T_3743 = _T_2302 ? btb_bank0_rd_data_way1_out_95 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3998 = _T_3997 | _T_3743; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_96; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_96; // @[lib.scala 374:16] wire [21:0] _T_3744 = _T_2304 ? btb_bank0_rd_data_way1_out_96 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3999 = _T_3998 | _T_3744; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_97; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_97; // @[lib.scala 374:16] wire [21:0] _T_3745 = _T_2306 ? btb_bank0_rd_data_way1_out_97 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4000 = _T_3999 | _T_3745; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_98; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_98; // @[lib.scala 374:16] wire [21:0] _T_3746 = _T_2308 ? btb_bank0_rd_data_way1_out_98 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4001 = _T_4000 | _T_3746; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_99; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_99; // @[lib.scala 374:16] wire [21:0] _T_3747 = _T_2310 ? btb_bank0_rd_data_way1_out_99 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4002 = _T_4001 | _T_3747; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_100; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_100; // @[lib.scala 374:16] wire [21:0] _T_3748 = _T_2312 ? btb_bank0_rd_data_way1_out_100 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4003 = _T_4002 | _T_3748; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_101; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_101; // @[lib.scala 374:16] wire [21:0] _T_3749 = _T_2314 ? btb_bank0_rd_data_way1_out_101 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4004 = _T_4003 | _T_3749; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_102; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_102; // @[lib.scala 374:16] wire [21:0] _T_3750 = _T_2316 ? btb_bank0_rd_data_way1_out_102 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4005 = _T_4004 | _T_3750; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_103; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_103; // @[lib.scala 374:16] wire [21:0] _T_3751 = _T_2318 ? btb_bank0_rd_data_way1_out_103 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4006 = _T_4005 | _T_3751; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_104; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_104; // @[lib.scala 374:16] wire [21:0] _T_3752 = _T_2320 ? btb_bank0_rd_data_way1_out_104 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4007 = _T_4006 | _T_3752; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_105; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_105; // @[lib.scala 374:16] wire [21:0] _T_3753 = _T_2322 ? btb_bank0_rd_data_way1_out_105 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4008 = _T_4007 | _T_3753; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_106; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_106; // @[lib.scala 374:16] wire [21:0] _T_3754 = _T_2324 ? btb_bank0_rd_data_way1_out_106 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4009 = _T_4008 | _T_3754; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_107; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_107; // @[lib.scala 374:16] wire [21:0] _T_3755 = _T_2326 ? btb_bank0_rd_data_way1_out_107 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4010 = _T_4009 | _T_3755; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_108; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_108; // @[lib.scala 374:16] wire [21:0] _T_3756 = _T_2328 ? btb_bank0_rd_data_way1_out_108 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4011 = _T_4010 | _T_3756; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_109; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_109; // @[lib.scala 374:16] wire [21:0] _T_3757 = _T_2330 ? btb_bank0_rd_data_way1_out_109 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4012 = _T_4011 | _T_3757; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_110; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_110; // @[lib.scala 374:16] wire [21:0] _T_3758 = _T_2332 ? btb_bank0_rd_data_way1_out_110 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4013 = _T_4012 | _T_3758; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_111; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_111; // @[lib.scala 374:16] wire [21:0] _T_3759 = _T_2334 ? btb_bank0_rd_data_way1_out_111 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4014 = _T_4013 | _T_3759; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_112; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_112; // @[lib.scala 374:16] wire [21:0] _T_3760 = _T_2336 ? btb_bank0_rd_data_way1_out_112 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4015 = _T_4014 | _T_3760; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_113; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_113; // @[lib.scala 374:16] wire [21:0] _T_3761 = _T_2338 ? btb_bank0_rd_data_way1_out_113 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4016 = _T_4015 | _T_3761; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_114; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_114; // @[lib.scala 374:16] wire [21:0] _T_3762 = _T_2340 ? btb_bank0_rd_data_way1_out_114 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4017 = _T_4016 | _T_3762; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_115; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_115; // @[lib.scala 374:16] wire [21:0] _T_3763 = _T_2342 ? btb_bank0_rd_data_way1_out_115 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4018 = _T_4017 | _T_3763; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_116; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_116; // @[lib.scala 374:16] wire [21:0] _T_3764 = _T_2344 ? btb_bank0_rd_data_way1_out_116 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4019 = _T_4018 | _T_3764; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_117; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_117; // @[lib.scala 374:16] wire [21:0] _T_3765 = _T_2346 ? btb_bank0_rd_data_way1_out_117 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4020 = _T_4019 | _T_3765; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_118; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_118; // @[lib.scala 374:16] wire [21:0] _T_3766 = _T_2348 ? btb_bank0_rd_data_way1_out_118 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4021 = _T_4020 | _T_3766; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_119; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_119; // @[lib.scala 374:16] wire [21:0] _T_3767 = _T_2350 ? btb_bank0_rd_data_way1_out_119 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4022 = _T_4021 | _T_3767; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_120; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_120; // @[lib.scala 374:16] wire [21:0] _T_3768 = _T_2352 ? btb_bank0_rd_data_way1_out_120 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4023 = _T_4022 | _T_3768; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_121; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_121; // @[lib.scala 374:16] wire [21:0] _T_3769 = _T_2354 ? btb_bank0_rd_data_way1_out_121 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4024 = _T_4023 | _T_3769; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_122; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_122; // @[lib.scala 374:16] wire [21:0] _T_3770 = _T_2356 ? btb_bank0_rd_data_way1_out_122 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4025 = _T_4024 | _T_3770; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_123; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_123; // @[lib.scala 374:16] wire [21:0] _T_3771 = _T_2358 ? btb_bank0_rd_data_way1_out_123 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4026 = _T_4025 | _T_3771; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_124; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_124; // @[lib.scala 374:16] wire [21:0] _T_3772 = _T_2360 ? btb_bank0_rd_data_way1_out_124 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4027 = _T_4026 | _T_3772; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_125; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_125; // @[lib.scala 374:16] wire [21:0] _T_3773 = _T_2362 ? btb_bank0_rd_data_way1_out_125 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4028 = _T_4027 | _T_3773; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_126; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_126; // @[lib.scala 374:16] wire [21:0] _T_3774 = _T_2364 ? btb_bank0_rd_data_way1_out_126 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4029 = _T_4028 | _T_3774; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_127; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_127; // @[lib.scala 374:16] wire [21:0] _T_3775 = _T_2366 ? btb_bank0_rd_data_way1_out_127 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4030 = _T_4029 | _T_3775; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_128; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_128; // @[lib.scala 374:16] wire [21:0] _T_3776 = _T_2368 ? btb_bank0_rd_data_way1_out_128 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4031 = _T_4030 | _T_3776; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_129; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_129; // @[lib.scala 374:16] wire [21:0] _T_3777 = _T_2370 ? btb_bank0_rd_data_way1_out_129 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4032 = _T_4031 | _T_3777; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_130; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_130; // @[lib.scala 374:16] wire [21:0] _T_3778 = _T_2372 ? btb_bank0_rd_data_way1_out_130 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4033 = _T_4032 | _T_3778; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_131; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_131; // @[lib.scala 374:16] wire [21:0] _T_3779 = _T_2374 ? btb_bank0_rd_data_way1_out_131 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4034 = _T_4033 | _T_3779; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_132; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_132; // @[lib.scala 374:16] wire [21:0] _T_3780 = _T_2376 ? btb_bank0_rd_data_way1_out_132 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4035 = _T_4034 | _T_3780; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_133; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_133; // @[lib.scala 374:16] wire [21:0] _T_3781 = _T_2378 ? btb_bank0_rd_data_way1_out_133 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4036 = _T_4035 | _T_3781; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_134; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_134; // @[lib.scala 374:16] wire [21:0] _T_3782 = _T_2380 ? btb_bank0_rd_data_way1_out_134 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4037 = _T_4036 | _T_3782; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_135; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_135; // @[lib.scala 374:16] wire [21:0] _T_3783 = _T_2382 ? btb_bank0_rd_data_way1_out_135 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4038 = _T_4037 | _T_3783; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_136; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_136; // @[lib.scala 374:16] wire [21:0] _T_3784 = _T_2384 ? btb_bank0_rd_data_way1_out_136 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4039 = _T_4038 | _T_3784; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_137; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_137; // @[lib.scala 374:16] wire [21:0] _T_3785 = _T_2386 ? btb_bank0_rd_data_way1_out_137 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4040 = _T_4039 | _T_3785; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_138; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_138; // @[lib.scala 374:16] wire [21:0] _T_3786 = _T_2388 ? btb_bank0_rd_data_way1_out_138 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4041 = _T_4040 | _T_3786; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_139; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_139; // @[lib.scala 374:16] wire [21:0] _T_3787 = _T_2390 ? btb_bank0_rd_data_way1_out_139 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4042 = _T_4041 | _T_3787; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_140; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_140; // @[lib.scala 374:16] wire [21:0] _T_3788 = _T_2392 ? btb_bank0_rd_data_way1_out_140 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4043 = _T_4042 | _T_3788; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_141; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_141; // @[lib.scala 374:16] wire [21:0] _T_3789 = _T_2394 ? btb_bank0_rd_data_way1_out_141 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4044 = _T_4043 | _T_3789; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_142; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_142; // @[lib.scala 374:16] wire [21:0] _T_3790 = _T_2396 ? btb_bank0_rd_data_way1_out_142 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4045 = _T_4044 | _T_3790; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_143; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_143; // @[lib.scala 374:16] wire [21:0] _T_3791 = _T_2398 ? btb_bank0_rd_data_way1_out_143 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4046 = _T_4045 | _T_3791; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_144; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_144; // @[lib.scala 374:16] wire [21:0] _T_3792 = _T_2400 ? btb_bank0_rd_data_way1_out_144 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4047 = _T_4046 | _T_3792; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_145; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_145; // @[lib.scala 374:16] wire [21:0] _T_3793 = _T_2402 ? btb_bank0_rd_data_way1_out_145 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4048 = _T_4047 | _T_3793; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_146; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_146; // @[lib.scala 374:16] wire [21:0] _T_3794 = _T_2404 ? btb_bank0_rd_data_way1_out_146 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4049 = _T_4048 | _T_3794; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_147; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_147; // @[lib.scala 374:16] wire [21:0] _T_3795 = _T_2406 ? btb_bank0_rd_data_way1_out_147 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4050 = _T_4049 | _T_3795; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_148; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_148; // @[lib.scala 374:16] wire [21:0] _T_3796 = _T_2408 ? btb_bank0_rd_data_way1_out_148 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4051 = _T_4050 | _T_3796; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_149; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_149; // @[lib.scala 374:16] wire [21:0] _T_3797 = _T_2410 ? btb_bank0_rd_data_way1_out_149 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4052 = _T_4051 | _T_3797; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_150; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_150; // @[lib.scala 374:16] wire [21:0] _T_3798 = _T_2412 ? btb_bank0_rd_data_way1_out_150 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4053 = _T_4052 | _T_3798; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_151; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_151; // @[lib.scala 374:16] wire [21:0] _T_3799 = _T_2414 ? btb_bank0_rd_data_way1_out_151 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4054 = _T_4053 | _T_3799; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_152; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_152; // @[lib.scala 374:16] wire [21:0] _T_3800 = _T_2416 ? btb_bank0_rd_data_way1_out_152 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4055 = _T_4054 | _T_3800; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_153; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_153; // @[lib.scala 374:16] wire [21:0] _T_3801 = _T_2418 ? btb_bank0_rd_data_way1_out_153 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4056 = _T_4055 | _T_3801; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_154; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_154; // @[lib.scala 374:16] wire [21:0] _T_3802 = _T_2420 ? btb_bank0_rd_data_way1_out_154 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4057 = _T_4056 | _T_3802; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_155; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_155; // @[lib.scala 374:16] wire [21:0] _T_3803 = _T_2422 ? btb_bank0_rd_data_way1_out_155 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4058 = _T_4057 | _T_3803; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_156; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_156; // @[lib.scala 374:16] wire [21:0] _T_3804 = _T_2424 ? btb_bank0_rd_data_way1_out_156 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4059 = _T_4058 | _T_3804; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_157; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_157; // @[lib.scala 374:16] wire [21:0] _T_3805 = _T_2426 ? btb_bank0_rd_data_way1_out_157 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4060 = _T_4059 | _T_3805; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_158; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_158; // @[lib.scala 374:16] wire [21:0] _T_3806 = _T_2428 ? btb_bank0_rd_data_way1_out_158 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4061 = _T_4060 | _T_3806; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_159; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_159; // @[lib.scala 374:16] wire [21:0] _T_3807 = _T_2430 ? btb_bank0_rd_data_way1_out_159 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4062 = _T_4061 | _T_3807; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_160; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_160; // @[lib.scala 374:16] wire [21:0] _T_3808 = _T_2432 ? btb_bank0_rd_data_way1_out_160 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4063 = _T_4062 | _T_3808; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_161; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_161; // @[lib.scala 374:16] wire [21:0] _T_3809 = _T_2434 ? btb_bank0_rd_data_way1_out_161 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4064 = _T_4063 | _T_3809; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_162; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_162; // @[lib.scala 374:16] wire [21:0] _T_3810 = _T_2436 ? btb_bank0_rd_data_way1_out_162 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4065 = _T_4064 | _T_3810; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_163; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_163; // @[lib.scala 374:16] wire [21:0] _T_3811 = _T_2438 ? btb_bank0_rd_data_way1_out_163 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4066 = _T_4065 | _T_3811; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_164; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_164; // @[lib.scala 374:16] wire [21:0] _T_3812 = _T_2440 ? btb_bank0_rd_data_way1_out_164 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4067 = _T_4066 | _T_3812; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_165; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_165; // @[lib.scala 374:16] wire [21:0] _T_3813 = _T_2442 ? btb_bank0_rd_data_way1_out_165 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4068 = _T_4067 | _T_3813; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_166; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_166; // @[lib.scala 374:16] wire [21:0] _T_3814 = _T_2444 ? btb_bank0_rd_data_way1_out_166 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4069 = _T_4068 | _T_3814; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_167; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_167; // @[lib.scala 374:16] wire [21:0] _T_3815 = _T_2446 ? btb_bank0_rd_data_way1_out_167 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4070 = _T_4069 | _T_3815; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_168; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_168; // @[lib.scala 374:16] wire [21:0] _T_3816 = _T_2448 ? btb_bank0_rd_data_way1_out_168 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4071 = _T_4070 | _T_3816; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_169; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_169; // @[lib.scala 374:16] wire [21:0] _T_3817 = _T_2450 ? btb_bank0_rd_data_way1_out_169 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4072 = _T_4071 | _T_3817; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_170; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_170; // @[lib.scala 374:16] wire [21:0] _T_3818 = _T_2452 ? btb_bank0_rd_data_way1_out_170 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4073 = _T_4072 | _T_3818; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_171; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_171; // @[lib.scala 374:16] wire [21:0] _T_3819 = _T_2454 ? btb_bank0_rd_data_way1_out_171 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4074 = _T_4073 | _T_3819; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_172; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_172; // @[lib.scala 374:16] wire [21:0] _T_3820 = _T_2456 ? btb_bank0_rd_data_way1_out_172 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4075 = _T_4074 | _T_3820; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_173; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_173; // @[lib.scala 374:16] wire [21:0] _T_3821 = _T_2458 ? btb_bank0_rd_data_way1_out_173 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4076 = _T_4075 | _T_3821; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_174; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_174; // @[lib.scala 374:16] wire [21:0] _T_3822 = _T_2460 ? btb_bank0_rd_data_way1_out_174 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4077 = _T_4076 | _T_3822; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_175; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_175; // @[lib.scala 374:16] wire [21:0] _T_3823 = _T_2462 ? btb_bank0_rd_data_way1_out_175 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4078 = _T_4077 | _T_3823; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_176; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_176; // @[lib.scala 374:16] wire [21:0] _T_3824 = _T_2464 ? btb_bank0_rd_data_way1_out_176 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4079 = _T_4078 | _T_3824; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_177; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_177; // @[lib.scala 374:16] wire [21:0] _T_3825 = _T_2466 ? btb_bank0_rd_data_way1_out_177 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4080 = _T_4079 | _T_3825; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_178; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_178; // @[lib.scala 374:16] wire [21:0] _T_3826 = _T_2468 ? btb_bank0_rd_data_way1_out_178 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4081 = _T_4080 | _T_3826; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_179; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_179; // @[lib.scala 374:16] wire [21:0] _T_3827 = _T_2470 ? btb_bank0_rd_data_way1_out_179 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4082 = _T_4081 | _T_3827; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_180; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_180; // @[lib.scala 374:16] wire [21:0] _T_3828 = _T_2472 ? btb_bank0_rd_data_way1_out_180 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4083 = _T_4082 | _T_3828; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_181; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_181; // @[lib.scala 374:16] wire [21:0] _T_3829 = _T_2474 ? btb_bank0_rd_data_way1_out_181 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4084 = _T_4083 | _T_3829; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_182; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_182; // @[lib.scala 374:16] wire [21:0] _T_3830 = _T_2476 ? btb_bank0_rd_data_way1_out_182 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4085 = _T_4084 | _T_3830; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_183; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_183; // @[lib.scala 374:16] wire [21:0] _T_3831 = _T_2478 ? btb_bank0_rd_data_way1_out_183 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4086 = _T_4085 | _T_3831; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_184; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_184; // @[lib.scala 374:16] wire [21:0] _T_3832 = _T_2480 ? btb_bank0_rd_data_way1_out_184 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4087 = _T_4086 | _T_3832; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_185; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_185; // @[lib.scala 374:16] wire [21:0] _T_3833 = _T_2482 ? btb_bank0_rd_data_way1_out_185 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4088 = _T_4087 | _T_3833; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_186; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_186; // @[lib.scala 374:16] wire [21:0] _T_3834 = _T_2484 ? btb_bank0_rd_data_way1_out_186 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4089 = _T_4088 | _T_3834; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_187; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_187; // @[lib.scala 374:16] wire [21:0] _T_3835 = _T_2486 ? btb_bank0_rd_data_way1_out_187 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4090 = _T_4089 | _T_3835; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_188; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_188; // @[lib.scala 374:16] wire [21:0] _T_3836 = _T_2488 ? btb_bank0_rd_data_way1_out_188 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4091 = _T_4090 | _T_3836; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_189; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_189; // @[lib.scala 374:16] wire [21:0] _T_3837 = _T_2490 ? btb_bank0_rd_data_way1_out_189 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4092 = _T_4091 | _T_3837; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_190; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_190; // @[lib.scala 374:16] wire [21:0] _T_3838 = _T_2492 ? btb_bank0_rd_data_way1_out_190 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4093 = _T_4092 | _T_3838; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_191; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_191; // @[lib.scala 374:16] wire [21:0] _T_3839 = _T_2494 ? btb_bank0_rd_data_way1_out_191 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4094 = _T_4093 | _T_3839; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_192; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_192; // @[lib.scala 374:16] wire [21:0] _T_3840 = _T_2496 ? btb_bank0_rd_data_way1_out_192 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4095 = _T_4094 | _T_3840; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_193; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_193; // @[lib.scala 374:16] wire [21:0] _T_3841 = _T_2498 ? btb_bank0_rd_data_way1_out_193 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4096 = _T_4095 | _T_3841; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_194; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_194; // @[lib.scala 374:16] wire [21:0] _T_3842 = _T_2500 ? btb_bank0_rd_data_way1_out_194 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4097 = _T_4096 | _T_3842; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_195; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_195; // @[lib.scala 374:16] wire [21:0] _T_3843 = _T_2502 ? btb_bank0_rd_data_way1_out_195 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4098 = _T_4097 | _T_3843; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_196; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_196; // @[lib.scala 374:16] wire [21:0] _T_3844 = _T_2504 ? btb_bank0_rd_data_way1_out_196 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4099 = _T_4098 | _T_3844; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_197; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_197; // @[lib.scala 374:16] wire [21:0] _T_3845 = _T_2506 ? btb_bank0_rd_data_way1_out_197 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4100 = _T_4099 | _T_3845; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_198; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_198; // @[lib.scala 374:16] wire [21:0] _T_3846 = _T_2508 ? btb_bank0_rd_data_way1_out_198 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4101 = _T_4100 | _T_3846; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_199; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_199; // @[lib.scala 374:16] wire [21:0] _T_3847 = _T_2510 ? btb_bank0_rd_data_way1_out_199 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4102 = _T_4101 | _T_3847; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_200; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_200; // @[lib.scala 374:16] wire [21:0] _T_3848 = _T_2512 ? btb_bank0_rd_data_way1_out_200 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4103 = _T_4102 | _T_3848; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_201; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_201; // @[lib.scala 374:16] wire [21:0] _T_3849 = _T_2514 ? btb_bank0_rd_data_way1_out_201 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4104 = _T_4103 | _T_3849; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_202; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_202; // @[lib.scala 374:16] wire [21:0] _T_3850 = _T_2516 ? btb_bank0_rd_data_way1_out_202 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4105 = _T_4104 | _T_3850; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_203; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_203; // @[lib.scala 374:16] wire [21:0] _T_3851 = _T_2518 ? btb_bank0_rd_data_way1_out_203 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4106 = _T_4105 | _T_3851; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_204; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_204; // @[lib.scala 374:16] wire [21:0] _T_3852 = _T_2520 ? btb_bank0_rd_data_way1_out_204 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4107 = _T_4106 | _T_3852; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_205; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_205; // @[lib.scala 374:16] wire [21:0] _T_3853 = _T_2522 ? btb_bank0_rd_data_way1_out_205 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4108 = _T_4107 | _T_3853; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_206; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_206; // @[lib.scala 374:16] wire [21:0] _T_3854 = _T_2524 ? btb_bank0_rd_data_way1_out_206 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4109 = _T_4108 | _T_3854; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_207; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_207; // @[lib.scala 374:16] wire [21:0] _T_3855 = _T_2526 ? btb_bank0_rd_data_way1_out_207 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4110 = _T_4109 | _T_3855; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_208; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_208; // @[lib.scala 374:16] wire [21:0] _T_3856 = _T_2528 ? btb_bank0_rd_data_way1_out_208 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4111 = _T_4110 | _T_3856; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_209; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_209; // @[lib.scala 374:16] wire [21:0] _T_3857 = _T_2530 ? btb_bank0_rd_data_way1_out_209 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4112 = _T_4111 | _T_3857; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_210; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_210; // @[lib.scala 374:16] wire [21:0] _T_3858 = _T_2532 ? btb_bank0_rd_data_way1_out_210 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4113 = _T_4112 | _T_3858; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_211; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_211; // @[lib.scala 374:16] wire [21:0] _T_3859 = _T_2534 ? btb_bank0_rd_data_way1_out_211 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4114 = _T_4113 | _T_3859; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_212; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_212; // @[lib.scala 374:16] wire [21:0] _T_3860 = _T_2536 ? btb_bank0_rd_data_way1_out_212 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4115 = _T_4114 | _T_3860; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_213; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_213; // @[lib.scala 374:16] wire [21:0] _T_3861 = _T_2538 ? btb_bank0_rd_data_way1_out_213 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4116 = _T_4115 | _T_3861; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_214; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_214; // @[lib.scala 374:16] wire [21:0] _T_3862 = _T_2540 ? btb_bank0_rd_data_way1_out_214 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4117 = _T_4116 | _T_3862; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_215; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_215; // @[lib.scala 374:16] wire [21:0] _T_3863 = _T_2542 ? btb_bank0_rd_data_way1_out_215 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4118 = _T_4117 | _T_3863; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_216; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_216; // @[lib.scala 374:16] wire [21:0] _T_3864 = _T_2544 ? btb_bank0_rd_data_way1_out_216 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4119 = _T_4118 | _T_3864; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_217; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_217; // @[lib.scala 374:16] wire [21:0] _T_3865 = _T_2546 ? btb_bank0_rd_data_way1_out_217 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4120 = _T_4119 | _T_3865; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_218; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_218; // @[lib.scala 374:16] wire [21:0] _T_3866 = _T_2548 ? btb_bank0_rd_data_way1_out_218 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4121 = _T_4120 | _T_3866; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_219; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_219; // @[lib.scala 374:16] wire [21:0] _T_3867 = _T_2550 ? btb_bank0_rd_data_way1_out_219 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4122 = _T_4121 | _T_3867; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_220; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_220; // @[lib.scala 374:16] wire [21:0] _T_3868 = _T_2552 ? btb_bank0_rd_data_way1_out_220 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4123 = _T_4122 | _T_3868; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_221; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_221; // @[lib.scala 374:16] wire [21:0] _T_3869 = _T_2554 ? btb_bank0_rd_data_way1_out_221 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4124 = _T_4123 | _T_3869; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_222; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_222; // @[lib.scala 374:16] wire [21:0] _T_3870 = _T_2556 ? btb_bank0_rd_data_way1_out_222 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4125 = _T_4124 | _T_3870; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_223; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_223; // @[lib.scala 374:16] wire [21:0] _T_3871 = _T_2558 ? btb_bank0_rd_data_way1_out_223 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4126 = _T_4125 | _T_3871; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_224; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_224; // @[lib.scala 374:16] wire [21:0] _T_3872 = _T_2560 ? btb_bank0_rd_data_way1_out_224 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4127 = _T_4126 | _T_3872; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_225; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_225; // @[lib.scala 374:16] wire [21:0] _T_3873 = _T_2562 ? btb_bank0_rd_data_way1_out_225 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4128 = _T_4127 | _T_3873; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_226; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_226; // @[lib.scala 374:16] wire [21:0] _T_3874 = _T_2564 ? btb_bank0_rd_data_way1_out_226 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4129 = _T_4128 | _T_3874; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_227; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_227; // @[lib.scala 374:16] wire [21:0] _T_3875 = _T_2566 ? btb_bank0_rd_data_way1_out_227 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4130 = _T_4129 | _T_3875; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_228; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_228; // @[lib.scala 374:16] wire [21:0] _T_3876 = _T_2568 ? btb_bank0_rd_data_way1_out_228 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4131 = _T_4130 | _T_3876; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_229; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_229; // @[lib.scala 374:16] wire [21:0] _T_3877 = _T_2570 ? btb_bank0_rd_data_way1_out_229 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4132 = _T_4131 | _T_3877; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_230; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_230; // @[lib.scala 374:16] wire [21:0] _T_3878 = _T_2572 ? btb_bank0_rd_data_way1_out_230 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4133 = _T_4132 | _T_3878; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_231; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_231; // @[lib.scala 374:16] wire [21:0] _T_3879 = _T_2574 ? btb_bank0_rd_data_way1_out_231 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4134 = _T_4133 | _T_3879; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_232; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_232; // @[lib.scala 374:16] wire [21:0] _T_3880 = _T_2576 ? btb_bank0_rd_data_way1_out_232 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4135 = _T_4134 | _T_3880; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_233; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_233; // @[lib.scala 374:16] wire [21:0] _T_3881 = _T_2578 ? btb_bank0_rd_data_way1_out_233 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4136 = _T_4135 | _T_3881; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_234; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_234; // @[lib.scala 374:16] wire [21:0] _T_3882 = _T_2580 ? btb_bank0_rd_data_way1_out_234 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4137 = _T_4136 | _T_3882; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_235; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_235; // @[lib.scala 374:16] wire [21:0] _T_3883 = _T_2582 ? btb_bank0_rd_data_way1_out_235 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4138 = _T_4137 | _T_3883; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_236; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_236; // @[lib.scala 374:16] wire [21:0] _T_3884 = _T_2584 ? btb_bank0_rd_data_way1_out_236 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4139 = _T_4138 | _T_3884; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_237; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_237; // @[lib.scala 374:16] wire [21:0] _T_3885 = _T_2586 ? btb_bank0_rd_data_way1_out_237 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4140 = _T_4139 | _T_3885; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_238; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_238; // @[lib.scala 374:16] wire [21:0] _T_3886 = _T_2588 ? btb_bank0_rd_data_way1_out_238 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4141 = _T_4140 | _T_3886; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_239; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_239; // @[lib.scala 374:16] wire [21:0] _T_3887 = _T_2590 ? btb_bank0_rd_data_way1_out_239 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4142 = _T_4141 | _T_3887; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_240; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_240; // @[lib.scala 374:16] wire [21:0] _T_3888 = _T_2592 ? btb_bank0_rd_data_way1_out_240 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4143 = _T_4142 | _T_3888; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_241; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_241; // @[lib.scala 374:16] wire [21:0] _T_3889 = _T_2594 ? btb_bank0_rd_data_way1_out_241 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4144 = _T_4143 | _T_3889; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_242; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_242; // @[lib.scala 374:16] wire [21:0] _T_3890 = _T_2596 ? btb_bank0_rd_data_way1_out_242 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4145 = _T_4144 | _T_3890; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_243; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_243; // @[lib.scala 374:16] wire [21:0] _T_3891 = _T_2598 ? btb_bank0_rd_data_way1_out_243 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4146 = _T_4145 | _T_3891; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_244; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_244; // @[lib.scala 374:16] wire [21:0] _T_3892 = _T_2600 ? btb_bank0_rd_data_way1_out_244 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4147 = _T_4146 | _T_3892; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_245; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_245; // @[lib.scala 374:16] wire [21:0] _T_3893 = _T_2602 ? btb_bank0_rd_data_way1_out_245 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4148 = _T_4147 | _T_3893; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_246; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_246; // @[lib.scala 374:16] wire [21:0] _T_3894 = _T_2604 ? btb_bank0_rd_data_way1_out_246 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4149 = _T_4148 | _T_3894; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_247; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_247; // @[lib.scala 374:16] wire [21:0] _T_3895 = _T_2606 ? btb_bank0_rd_data_way1_out_247 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4150 = _T_4149 | _T_3895; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_248; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_248; // @[lib.scala 374:16] wire [21:0] _T_3896 = _T_2608 ? btb_bank0_rd_data_way1_out_248 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4151 = _T_4150 | _T_3896; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_249; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_249; // @[lib.scala 374:16] wire [21:0] _T_3897 = _T_2610 ? btb_bank0_rd_data_way1_out_249 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4152 = _T_4151 | _T_3897; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_250; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_250; // @[lib.scala 374:16] wire [21:0] _T_3898 = _T_2612 ? btb_bank0_rd_data_way1_out_250 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4153 = _T_4152 | _T_3898; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_251; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_251; // @[lib.scala 374:16] wire [21:0] _T_3899 = _T_2614 ? btb_bank0_rd_data_way1_out_251 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4154 = _T_4153 | _T_3899; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_252; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_252; // @[lib.scala 374:16] wire [21:0] _T_3900 = _T_2616 ? btb_bank0_rd_data_way1_out_252 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4155 = _T_4154 | _T_3900; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_253; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_253; // @[lib.scala 374:16] wire [21:0] _T_3901 = _T_2618 ? btb_bank0_rd_data_way1_out_253 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4156 = _T_4155 | _T_3901; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_254; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_254; // @[lib.scala 374:16] wire [21:0] _T_3902 = _T_2620 ? btb_bank0_rd_data_way1_out_254 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4157 = _T_4156 | _T_3902; // @[Mux.scala 27:72] - reg [21:0] btb_bank0_rd_data_way1_out_255; // @[el2_lib.scala 514:16] + reg [21:0] btb_bank0_rd_data_way1_out_255; // @[lib.scala 374:16] wire [21:0] _T_3903 = _T_2622 ? btb_bank0_rd_data_way1_out_255 : 22'h0; // @[Mux.scala 27:72] wire [21:0] btb_bank0_rd_data_way1_f = _T_4157 | _T_3903; // @[Mux.scala 27:72] wire _T_55 = btb_bank0_rd_data_way1_f[21:17] == fetch_rd_tag_f; // @[ifu_bp_ctl.scala 131:97] @@ -17771,8 +17771,8 @@ module ifu_bp_ctl( wire _T_4670 = btb_rd_addr_p1_f == 8'hff; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4927 = _T_4670 ? btb_bank0_rd_data_way0_out_255 : 22'h0; // @[Mux.scala 27:72] wire [21:0] btb_bank0_rd_data_way0_p1_f = _T_5181 | _T_4927; // @[Mux.scala 27:72] - wire [4:0] _T_31 = _T_8[13:9] ^ _T_8[18:14]; // @[el2_lib.scala 182:111] - wire [4:0] fetch_rd_tag_p1_f = _T_31 ^ _T_8[23:19]; // @[el2_lib.scala 182:111] + wire [4:0] _T_31 = _T_8[13:9] ^ _T_8[18:14]; // @[lib.scala 42:111] + wire [4:0] fetch_rd_tag_p1_f = _T_31 ^ _T_8[23:19]; // @[lib.scala 42:111] wire _T_64 = btb_bank0_rd_data_way0_p1_f[21:17] == fetch_rd_tag_p1_f; // @[ifu_bp_ctl.scala 135:106] wire _T_65 = btb_bank0_rd_data_way0_p1_f[0] & _T_64; // @[ifu_bp_ctl.scala 135:61] wire _T_20 = io_exu_bp_exu_i0_br_index_r == btb_rd_addr_p1_f; // @[ifu_bp_ctl.scala 103:75] @@ -18325,7 +18325,7 @@ module ifu_bp_ctl( wire [1:0] bht_force_taken_f = {_T_243,_T_246}; // @[Cat.scala 29:58] wire [9:0] _T_570 = {btb_rd_addr_f,2'h0}; // @[Cat.scala 29:58] reg [7:0] fghr; // @[ifu_bp_ctl.scala 323:44] - wire [7:0] bht_rd_addr_f = _T_570[9:2] ^ fghr; // @[el2_lib.scala 196:35] + wire [7:0] bht_rd_addr_f = _T_570[9:2] ^ fghr; // @[lib.scala 56:35] wire _T_21408 = bht_rd_addr_f == 8'h0; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_0; // @[Reg.scala 27:20] wire [1:0] _T_21920 = _T_21408 ? bht_bank_rd_data_out_1_0 : 2'h0; // @[Mux.scala 27:72] @@ -19351,7 +19351,7 @@ module ifu_bp_ctl( wire [1:0] bht_bank1_rd_data_f = _T_22429 | _T_22175; // @[Mux.scala 27:72] wire [1:0] _T_260 = _T_144 ? bht_bank1_rd_data_f : 2'h0; // @[Mux.scala 27:72] wire [9:0] _T_573 = {btb_rd_addr_p1_f,2'h0}; // @[Cat.scala 29:58] - wire [7:0] bht_rd_addr_hashed_p1_f = _T_573[9:2] ^ fghr; // @[el2_lib.scala 196:35] + wire [7:0] bht_rd_addr_hashed_p1_f = _T_573[9:2] ^ fghr; // @[lib.scala 56:35] wire _T_22432 = bht_rd_addr_hashed_p1_f == 8'h0; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_0; // @[Reg.scala 27:20] wire [1:0] _T_22944 = _T_22432 ? bht_bank_rd_data_out_0_0 : 2'h0; // @[Mux.scala 27:72] @@ -20944,7 +20944,7 @@ module ifu_bp_ctl( wire [255:0] _T_181 = tag_match_way0_p1_f ? fetch_wrlru_p1_b0 : 256'h0; // @[Mux.scala 27:72] wire [255:0] _T_182 = _T_179 | _T_180; // @[Mux.scala 27:72] wire [255:0] _T_183 = _T_182 | _T_181; // @[Mux.scala 27:72] - reg [255:0] btb_lru_b0_f; // @[el2_lib.scala 514:16] + reg [255:0] btb_lru_b0_f; // @[lib.scala 374:16] wire [255:0] _T_185 = btb_lru_b0_hold & btb_lru_b0_f; // @[ifu_bp_ctl.scala 220:102] wire [255:0] _T_187 = fetch_wrindex_dec & btb_lru_b0_f; // @[ifu_bp_ctl.scala 223:78] wire _T_188 = |_T_187; // @[ifu_bp_ctl.scala 223:94] @@ -21030,7 +21030,7 @@ module ifu_bp_ctl( wire btb_fg_crossing_f = _T_372 & btb_rd_pc4_f; // @[ifu_bp_ctl.scala 339:59] wire bp_total_branch_offset_f = bloc_f[1] ^ btb_rd_pc4_f; // @[ifu_bp_ctl.scala 340:43] wire _T_376 = io_ifc_fetch_req_f & _T_276; // @[ifu_bp_ctl.scala 342:85] - reg [29:0] ifc_fetch_adder_prior; // @[el2_lib.scala 514:16] + reg [29:0] ifc_fetch_adder_prior; // @[lib.scala 374:16] wire _T_381 = ~btb_fg_crossing_f; // @[ifu_bp_ctl.scala 348:32] wire _T_382 = ~use_fa_plus; // @[ifu_bp_ctl.scala 348:53] wire _T_383 = _T_381 & _T_382; // @[ifu_bp_ctl.scala 348:51] @@ -21041,14 +21041,14 @@ module ifu_bp_ctl( wire [29:0] adder_pc_in_f = _T_389 | _T_388; // @[Mux.scala 27:72] wire [31:0] _T_393 = {adder_pc_in_f,bp_total_branch_offset_f,1'h0}; // @[Cat.scala 29:58] wire [12:0] _T_394 = {btb_rd_tgt_f,1'h0}; // @[Cat.scala 29:58] - wire [12:0] _T_397 = _T_393[12:1] + _T_394[12:1]; // @[el2_lib.scala 208:31] - wire [18:0] _T_400 = _T_393[31:13] + 19'h1; // @[el2_lib.scala 209:27] - wire [18:0] _T_403 = _T_393[31:13] - 19'h1; // @[el2_lib.scala 210:27] - wire _T_406 = ~_T_397[12]; // @[el2_lib.scala 212:28] - wire _T_407 = _T_394[12] ^ _T_406; // @[el2_lib.scala 212:26] - wire _T_410 = ~_T_394[12]; // @[el2_lib.scala 213:20] - wire _T_412 = _T_410 & _T_397[12]; // @[el2_lib.scala 213:26] - wire _T_416 = _T_394[12] & _T_406; // @[el2_lib.scala 214:26] + wire [12:0] _T_397 = _T_393[12:1] + _T_394[12:1]; // @[lib.scala 68:31] + wire [18:0] _T_400 = _T_393[31:13] + 19'h1; // @[lib.scala 69:27] + wire [18:0] _T_403 = _T_393[31:13] - 19'h1; // @[lib.scala 70:27] + wire _T_406 = ~_T_397[12]; // @[lib.scala 72:28] + wire _T_407 = _T_394[12] ^ _T_406; // @[lib.scala 72:26] + wire _T_410 = ~_T_394[12]; // @[lib.scala 73:20] + wire _T_412 = _T_410 & _T_397[12]; // @[lib.scala 73:26] + wire _T_416 = _T_394[12] & _T_406; // @[lib.scala 74:26] wire [18:0] _T_418 = _T_407 ? _T_393[31:13] : 19'h0; // @[Mux.scala 27:72] wire [18:0] _T_419 = _T_412 ? _T_400 : 19'h0; // @[Mux.scala 27:72] wire [18:0] _T_420 = _T_416 ? _T_403 : 19'h0; // @[Mux.scala 27:72] @@ -21057,15 +21057,15 @@ module ifu_bp_ctl( wire [31:0] bp_btb_target_adder_f = {_T_422,_T_397[11:0],1'h0}; // @[Cat.scala 29:58] wire _T_426 = ~btb_rd_call_f; // @[ifu_bp_ctl.scala 357:49] wire _T_427 = btb_rd_ret_f & _T_426; // @[ifu_bp_ctl.scala 357:47] - reg [31:0] rets_out_0; // @[el2_lib.scala 514:16] + reg [31:0] rets_out_0; // @[lib.scala 374:16] wire _T_429 = _T_427 & rets_out_0[0]; // @[ifu_bp_ctl.scala 357:64] wire [12:0] _T_440 = {11'h0,_T_369,1'h0}; // @[Cat.scala 29:58] - wire [12:0] _T_443 = _T_393[12:1] + _T_440[12:1]; // @[el2_lib.scala 208:31] - wire _T_452 = ~_T_443[12]; // @[el2_lib.scala 212:28] - wire _T_453 = _T_440[12] ^ _T_452; // @[el2_lib.scala 212:26] - wire _T_456 = ~_T_440[12]; // @[el2_lib.scala 213:20] - wire _T_458 = _T_456 & _T_443[12]; // @[el2_lib.scala 213:26] - wire _T_462 = _T_440[12] & _T_452; // @[el2_lib.scala 214:26] + wire [12:0] _T_443 = _T_393[12:1] + _T_440[12:1]; // @[lib.scala 68:31] + wire _T_452 = ~_T_443[12]; // @[lib.scala 72:28] + wire _T_453 = _T_440[12] ^ _T_452; // @[lib.scala 72:26] + wire _T_456 = ~_T_440[12]; // @[lib.scala 73:20] + wire _T_458 = _T_456 & _T_443[12]; // @[lib.scala 73:26] + wire _T_462 = _T_440[12] & _T_452; // @[lib.scala 74:26] wire [18:0] _T_464 = _T_453 ? _T_393[31:13] : 19'h0; // @[Mux.scala 27:72] wire [18:0] _T_465 = _T_458 ? _T_400 : 19'h0; // @[Mux.scala 27:72] wire [18:0] _T_466 = _T_462 ? _T_403 : 19'h0; // @[Mux.scala 27:72] @@ -21081,25 +21081,25 @@ module ifu_bp_ctl( wire rs_hold = _T_476 & _T_477; // @[ifu_bp_ctl.scala 365:26] wire [31:0] _T_480 = {bp_rs_call_target_f[31:1],1'h1}; // @[Cat.scala 29:58] wire [31:0] _T_482 = rs_push ? _T_480 : 32'h0; // @[Mux.scala 27:72] - reg [31:0] rets_out_1; // @[el2_lib.scala 514:16] + reg [31:0] rets_out_1; // @[lib.scala 374:16] wire [31:0] _T_483 = rs_pop ? rets_out_1 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_487 = rs_push ? rets_out_0 : 32'h0; // @[Mux.scala 27:72] - reg [31:0] rets_out_2; // @[el2_lib.scala 514:16] + reg [31:0] rets_out_2; // @[lib.scala 374:16] wire [31:0] _T_488 = rs_pop ? rets_out_2 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_492 = rs_push ? rets_out_1 : 32'h0; // @[Mux.scala 27:72] - reg [31:0] rets_out_3; // @[el2_lib.scala 514:16] + reg [31:0] rets_out_3; // @[lib.scala 374:16] wire [31:0] _T_493 = rs_pop ? rets_out_3 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_497 = rs_push ? rets_out_2 : 32'h0; // @[Mux.scala 27:72] - reg [31:0] rets_out_4; // @[el2_lib.scala 514:16] + reg [31:0] rets_out_4; // @[lib.scala 374:16] wire [31:0] _T_498 = rs_pop ? rets_out_4 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_502 = rs_push ? rets_out_3 : 32'h0; // @[Mux.scala 27:72] - reg [31:0] rets_out_5; // @[el2_lib.scala 514:16] + reg [31:0] rets_out_5; // @[lib.scala 374:16] wire [31:0] _T_503 = rs_pop ? rets_out_5 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_507 = rs_push ? rets_out_4 : 32'h0; // @[Mux.scala 27:72] - reg [31:0] rets_out_6; // @[el2_lib.scala 514:16] + reg [31:0] rets_out_6; // @[lib.scala 374:16] wire [31:0] _T_508 = rs_pop ? rets_out_6 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_512 = rs_push ? rets_out_5 : 32'h0; // @[Mux.scala 27:72] - reg [31:0] rets_out_7; // @[el2_lib.scala 514:16] + reg [31:0] rets_out_7; // @[lib.scala 374:16] wire [31:0] _T_513 = rs_pop ? rets_out_7 : 32'h0; // @[Mux.scala 27:72] wire _T_531 = ~dec_tlu_error_wb; // @[ifu_bp_ctl.scala 380:35] wire btb_valid = exu_mp_valid & _T_531; // @[ifu_bp_ctl.scala 380:32] @@ -21134,9 +21134,9 @@ module ifu_bp_ctl( wire [1:0] _T_563 = {io_dec_bp_dec_tlu_br0_r_pkt_bits_middle,_T_562}; // @[Cat.scala 29:58] wire [1:0] bht_wr_en2 = _T_561 & _T_563; // @[ifu_bp_ctl.scala 397:46] wire [9:0] _T_564 = {io_exu_bp_exu_mp_index,2'h0}; // @[Cat.scala 29:58] - wire [7:0] bht_wr_addr0 = _T_564[9:2] ^ io_exu_bp_exu_mp_eghr; // @[el2_lib.scala 196:35] + wire [7:0] bht_wr_addr0 = _T_564[9:2] ^ io_exu_bp_exu_mp_eghr; // @[lib.scala 56:35] wire [9:0] _T_567 = {io_exu_bp_exu_i0_br_index_r,2'h0}; // @[Cat.scala 29:58] - wire [7:0] bht_wr_addr2 = _T_567[9:2] ^ io_exu_bp_exu_i0_br_fghr_r; // @[el2_lib.scala 196:35] + wire [7:0] bht_wr_addr2 = _T_567[9:2] ^ io_exu_bp_exu_i0_br_fghr_r; // @[lib.scala 56:35] wire _T_576 = btb_wr_addr == 8'h0; // @[ifu_bp_ctl.scala 415:95] wire _T_579 = btb_wr_addr == 8'h1; // @[ifu_bp_ctl.scala 415:95] wire _T_582 = btb_wr_addr == 8'h2; // @[ifu_bp_ctl.scala 415:95] @@ -23121,3325 +23121,3325 @@ module ifu_bp_ctl( wire bht_bank_sel_1_15_14 = _T_19845 | _T_11156; // @[ifu_bp_ctl.scala 443:223] wire _T_19862 = _T_15778 & _T_6375; // @[ifu_bp_ctl.scala 443:110] wire bht_bank_sel_1_15_15 = _T_19862 | _T_11165; // @[ifu_bp_ctl.scala 443:223] - rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en), .io_scan_mode(rvclkhdr_io_scan_mode) ); - rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_1 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_1_io_l1clk), .io_clk(rvclkhdr_1_io_clk), .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_2_io_l1clk), .io_clk(rvclkhdr_2_io_clk), .io_en(rvclkhdr_2_io_en), .io_scan_mode(rvclkhdr_2_io_scan_mode) ); - rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_3_io_l1clk), .io_clk(rvclkhdr_3_io_clk), .io_en(rvclkhdr_3_io_en), .io_scan_mode(rvclkhdr_3_io_scan_mode) ); - rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_4_io_l1clk), .io_clk(rvclkhdr_4_io_clk), .io_en(rvclkhdr_4_io_en), .io_scan_mode(rvclkhdr_4_io_scan_mode) ); - rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_5 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_5_io_l1clk), .io_clk(rvclkhdr_5_io_clk), .io_en(rvclkhdr_5_io_en), .io_scan_mode(rvclkhdr_5_io_scan_mode) ); - rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_6 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_6_io_l1clk), .io_clk(rvclkhdr_6_io_clk), .io_en(rvclkhdr_6_io_en), .io_scan_mode(rvclkhdr_6_io_scan_mode) ); - rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_7 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_7_io_l1clk), .io_clk(rvclkhdr_7_io_clk), .io_en(rvclkhdr_7_io_en), .io_scan_mode(rvclkhdr_7_io_scan_mode) ); - rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_8 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_8_io_l1clk), .io_clk(rvclkhdr_8_io_clk), .io_en(rvclkhdr_8_io_en), .io_scan_mode(rvclkhdr_8_io_scan_mode) ); - rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_9 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_9_io_l1clk), .io_clk(rvclkhdr_9_io_clk), .io_en(rvclkhdr_9_io_en), .io_scan_mode(rvclkhdr_9_io_scan_mode) ); - rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_10 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_10_io_l1clk), .io_clk(rvclkhdr_10_io_clk), .io_en(rvclkhdr_10_io_en), .io_scan_mode(rvclkhdr_10_io_scan_mode) ); - rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_11 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_11_io_l1clk), .io_clk(rvclkhdr_11_io_clk), .io_en(rvclkhdr_11_io_en), .io_scan_mode(rvclkhdr_11_io_scan_mode) ); - rvclkhdr rvclkhdr_12 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_12 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_12_io_l1clk), .io_clk(rvclkhdr_12_io_clk), .io_en(rvclkhdr_12_io_en), .io_scan_mode(rvclkhdr_12_io_scan_mode) ); - rvclkhdr rvclkhdr_13 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_13 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_13_io_l1clk), .io_clk(rvclkhdr_13_io_clk), .io_en(rvclkhdr_13_io_en), .io_scan_mode(rvclkhdr_13_io_scan_mode) ); - rvclkhdr rvclkhdr_14 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_14 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_14_io_l1clk), .io_clk(rvclkhdr_14_io_clk), .io_en(rvclkhdr_14_io_en), .io_scan_mode(rvclkhdr_14_io_scan_mode) ); - rvclkhdr rvclkhdr_15 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_15 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_15_io_l1clk), .io_clk(rvclkhdr_15_io_clk), .io_en(rvclkhdr_15_io_en), .io_scan_mode(rvclkhdr_15_io_scan_mode) ); - rvclkhdr rvclkhdr_16 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_16 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_16_io_l1clk), .io_clk(rvclkhdr_16_io_clk), .io_en(rvclkhdr_16_io_en), .io_scan_mode(rvclkhdr_16_io_scan_mode) ); - rvclkhdr rvclkhdr_17 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_17 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_17_io_l1clk), .io_clk(rvclkhdr_17_io_clk), .io_en(rvclkhdr_17_io_en), .io_scan_mode(rvclkhdr_17_io_scan_mode) ); - rvclkhdr rvclkhdr_18 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_18 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_18_io_l1clk), .io_clk(rvclkhdr_18_io_clk), .io_en(rvclkhdr_18_io_en), .io_scan_mode(rvclkhdr_18_io_scan_mode) ); - rvclkhdr rvclkhdr_19 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_19 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_19_io_l1clk), .io_clk(rvclkhdr_19_io_clk), .io_en(rvclkhdr_19_io_en), .io_scan_mode(rvclkhdr_19_io_scan_mode) ); - rvclkhdr rvclkhdr_20 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_20 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_20_io_l1clk), .io_clk(rvclkhdr_20_io_clk), .io_en(rvclkhdr_20_io_en), .io_scan_mode(rvclkhdr_20_io_scan_mode) ); - rvclkhdr rvclkhdr_21 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_21 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_21_io_l1clk), .io_clk(rvclkhdr_21_io_clk), .io_en(rvclkhdr_21_io_en), .io_scan_mode(rvclkhdr_21_io_scan_mode) ); - rvclkhdr rvclkhdr_22 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_22 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_22_io_l1clk), .io_clk(rvclkhdr_22_io_clk), .io_en(rvclkhdr_22_io_en), .io_scan_mode(rvclkhdr_22_io_scan_mode) ); - rvclkhdr rvclkhdr_23 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_23 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_23_io_l1clk), .io_clk(rvclkhdr_23_io_clk), .io_en(rvclkhdr_23_io_en), .io_scan_mode(rvclkhdr_23_io_scan_mode) ); - rvclkhdr rvclkhdr_24 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_24 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_24_io_l1clk), .io_clk(rvclkhdr_24_io_clk), .io_en(rvclkhdr_24_io_en), .io_scan_mode(rvclkhdr_24_io_scan_mode) ); - rvclkhdr rvclkhdr_25 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_25 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_25_io_l1clk), .io_clk(rvclkhdr_25_io_clk), .io_en(rvclkhdr_25_io_en), .io_scan_mode(rvclkhdr_25_io_scan_mode) ); - rvclkhdr rvclkhdr_26 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_26 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_26_io_l1clk), .io_clk(rvclkhdr_26_io_clk), .io_en(rvclkhdr_26_io_en), .io_scan_mode(rvclkhdr_26_io_scan_mode) ); - rvclkhdr rvclkhdr_27 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_27 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_27_io_l1clk), .io_clk(rvclkhdr_27_io_clk), .io_en(rvclkhdr_27_io_en), .io_scan_mode(rvclkhdr_27_io_scan_mode) ); - rvclkhdr rvclkhdr_28 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_28 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_28_io_l1clk), .io_clk(rvclkhdr_28_io_clk), .io_en(rvclkhdr_28_io_en), .io_scan_mode(rvclkhdr_28_io_scan_mode) ); - rvclkhdr rvclkhdr_29 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_29 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_29_io_l1clk), .io_clk(rvclkhdr_29_io_clk), .io_en(rvclkhdr_29_io_en), .io_scan_mode(rvclkhdr_29_io_scan_mode) ); - rvclkhdr rvclkhdr_30 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_30 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_30_io_l1clk), .io_clk(rvclkhdr_30_io_clk), .io_en(rvclkhdr_30_io_en), .io_scan_mode(rvclkhdr_30_io_scan_mode) ); - rvclkhdr rvclkhdr_31 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_31 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_31_io_l1clk), .io_clk(rvclkhdr_31_io_clk), .io_en(rvclkhdr_31_io_en), .io_scan_mode(rvclkhdr_31_io_scan_mode) ); - rvclkhdr rvclkhdr_32 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_32 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_32_io_l1clk), .io_clk(rvclkhdr_32_io_clk), .io_en(rvclkhdr_32_io_en), .io_scan_mode(rvclkhdr_32_io_scan_mode) ); - rvclkhdr rvclkhdr_33 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_33 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_33_io_l1clk), .io_clk(rvclkhdr_33_io_clk), .io_en(rvclkhdr_33_io_en), .io_scan_mode(rvclkhdr_33_io_scan_mode) ); - rvclkhdr rvclkhdr_34 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_34 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_34_io_l1clk), .io_clk(rvclkhdr_34_io_clk), .io_en(rvclkhdr_34_io_en), .io_scan_mode(rvclkhdr_34_io_scan_mode) ); - rvclkhdr rvclkhdr_35 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_35 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_35_io_l1clk), .io_clk(rvclkhdr_35_io_clk), .io_en(rvclkhdr_35_io_en), .io_scan_mode(rvclkhdr_35_io_scan_mode) ); - rvclkhdr rvclkhdr_36 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_36 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_36_io_l1clk), .io_clk(rvclkhdr_36_io_clk), .io_en(rvclkhdr_36_io_en), .io_scan_mode(rvclkhdr_36_io_scan_mode) ); - rvclkhdr rvclkhdr_37 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_37 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_37_io_l1clk), .io_clk(rvclkhdr_37_io_clk), .io_en(rvclkhdr_37_io_en), .io_scan_mode(rvclkhdr_37_io_scan_mode) ); - rvclkhdr rvclkhdr_38 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_38 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_38_io_l1clk), .io_clk(rvclkhdr_38_io_clk), .io_en(rvclkhdr_38_io_en), .io_scan_mode(rvclkhdr_38_io_scan_mode) ); - rvclkhdr rvclkhdr_39 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_39 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_39_io_l1clk), .io_clk(rvclkhdr_39_io_clk), .io_en(rvclkhdr_39_io_en), .io_scan_mode(rvclkhdr_39_io_scan_mode) ); - rvclkhdr rvclkhdr_40 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_40 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_40_io_l1clk), .io_clk(rvclkhdr_40_io_clk), .io_en(rvclkhdr_40_io_en), .io_scan_mode(rvclkhdr_40_io_scan_mode) ); - rvclkhdr rvclkhdr_41 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_41 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_41_io_l1clk), .io_clk(rvclkhdr_41_io_clk), .io_en(rvclkhdr_41_io_en), .io_scan_mode(rvclkhdr_41_io_scan_mode) ); - rvclkhdr rvclkhdr_42 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_42 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_42_io_l1clk), .io_clk(rvclkhdr_42_io_clk), .io_en(rvclkhdr_42_io_en), .io_scan_mode(rvclkhdr_42_io_scan_mode) ); - rvclkhdr rvclkhdr_43 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_43 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_43_io_l1clk), .io_clk(rvclkhdr_43_io_clk), .io_en(rvclkhdr_43_io_en), .io_scan_mode(rvclkhdr_43_io_scan_mode) ); - rvclkhdr rvclkhdr_44 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_44 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_44_io_l1clk), .io_clk(rvclkhdr_44_io_clk), .io_en(rvclkhdr_44_io_en), .io_scan_mode(rvclkhdr_44_io_scan_mode) ); - rvclkhdr rvclkhdr_45 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_45 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_45_io_l1clk), .io_clk(rvclkhdr_45_io_clk), .io_en(rvclkhdr_45_io_en), .io_scan_mode(rvclkhdr_45_io_scan_mode) ); - rvclkhdr rvclkhdr_46 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_46 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_46_io_l1clk), .io_clk(rvclkhdr_46_io_clk), .io_en(rvclkhdr_46_io_en), .io_scan_mode(rvclkhdr_46_io_scan_mode) ); - rvclkhdr rvclkhdr_47 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_47 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_47_io_l1clk), .io_clk(rvclkhdr_47_io_clk), .io_en(rvclkhdr_47_io_en), .io_scan_mode(rvclkhdr_47_io_scan_mode) ); - rvclkhdr rvclkhdr_48 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_48 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_48_io_l1clk), .io_clk(rvclkhdr_48_io_clk), .io_en(rvclkhdr_48_io_en), .io_scan_mode(rvclkhdr_48_io_scan_mode) ); - rvclkhdr rvclkhdr_49 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_49 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_49_io_l1clk), .io_clk(rvclkhdr_49_io_clk), .io_en(rvclkhdr_49_io_en), .io_scan_mode(rvclkhdr_49_io_scan_mode) ); - rvclkhdr rvclkhdr_50 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_50 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_50_io_l1clk), .io_clk(rvclkhdr_50_io_clk), .io_en(rvclkhdr_50_io_en), .io_scan_mode(rvclkhdr_50_io_scan_mode) ); - rvclkhdr rvclkhdr_51 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_51 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_51_io_l1clk), .io_clk(rvclkhdr_51_io_clk), .io_en(rvclkhdr_51_io_en), .io_scan_mode(rvclkhdr_51_io_scan_mode) ); - rvclkhdr rvclkhdr_52 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_52 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_52_io_l1clk), .io_clk(rvclkhdr_52_io_clk), .io_en(rvclkhdr_52_io_en), .io_scan_mode(rvclkhdr_52_io_scan_mode) ); - rvclkhdr rvclkhdr_53 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_53 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_53_io_l1clk), .io_clk(rvclkhdr_53_io_clk), .io_en(rvclkhdr_53_io_en), .io_scan_mode(rvclkhdr_53_io_scan_mode) ); - rvclkhdr rvclkhdr_54 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_54 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_54_io_l1clk), .io_clk(rvclkhdr_54_io_clk), .io_en(rvclkhdr_54_io_en), .io_scan_mode(rvclkhdr_54_io_scan_mode) ); - rvclkhdr rvclkhdr_55 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_55 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_55_io_l1clk), .io_clk(rvclkhdr_55_io_clk), .io_en(rvclkhdr_55_io_en), .io_scan_mode(rvclkhdr_55_io_scan_mode) ); - rvclkhdr rvclkhdr_56 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_56 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_56_io_l1clk), .io_clk(rvclkhdr_56_io_clk), .io_en(rvclkhdr_56_io_en), .io_scan_mode(rvclkhdr_56_io_scan_mode) ); - rvclkhdr rvclkhdr_57 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_57 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_57_io_l1clk), .io_clk(rvclkhdr_57_io_clk), .io_en(rvclkhdr_57_io_en), .io_scan_mode(rvclkhdr_57_io_scan_mode) ); - rvclkhdr rvclkhdr_58 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_58 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_58_io_l1clk), .io_clk(rvclkhdr_58_io_clk), .io_en(rvclkhdr_58_io_en), .io_scan_mode(rvclkhdr_58_io_scan_mode) ); - rvclkhdr rvclkhdr_59 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_59 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_59_io_l1clk), .io_clk(rvclkhdr_59_io_clk), .io_en(rvclkhdr_59_io_en), .io_scan_mode(rvclkhdr_59_io_scan_mode) ); - rvclkhdr rvclkhdr_60 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_60 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_60_io_l1clk), .io_clk(rvclkhdr_60_io_clk), .io_en(rvclkhdr_60_io_en), .io_scan_mode(rvclkhdr_60_io_scan_mode) ); - rvclkhdr rvclkhdr_61 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_61 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_61_io_l1clk), .io_clk(rvclkhdr_61_io_clk), .io_en(rvclkhdr_61_io_en), .io_scan_mode(rvclkhdr_61_io_scan_mode) ); - rvclkhdr rvclkhdr_62 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_62 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_62_io_l1clk), .io_clk(rvclkhdr_62_io_clk), .io_en(rvclkhdr_62_io_en), .io_scan_mode(rvclkhdr_62_io_scan_mode) ); - rvclkhdr rvclkhdr_63 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_63 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_63_io_l1clk), .io_clk(rvclkhdr_63_io_clk), .io_en(rvclkhdr_63_io_en), .io_scan_mode(rvclkhdr_63_io_scan_mode) ); - rvclkhdr rvclkhdr_64 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_64 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_64_io_l1clk), .io_clk(rvclkhdr_64_io_clk), .io_en(rvclkhdr_64_io_en), .io_scan_mode(rvclkhdr_64_io_scan_mode) ); - rvclkhdr rvclkhdr_65 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_65 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_65_io_l1clk), .io_clk(rvclkhdr_65_io_clk), .io_en(rvclkhdr_65_io_en), .io_scan_mode(rvclkhdr_65_io_scan_mode) ); - rvclkhdr rvclkhdr_66 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_66 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_66_io_l1clk), .io_clk(rvclkhdr_66_io_clk), .io_en(rvclkhdr_66_io_en), .io_scan_mode(rvclkhdr_66_io_scan_mode) ); - rvclkhdr rvclkhdr_67 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_67 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_67_io_l1clk), .io_clk(rvclkhdr_67_io_clk), .io_en(rvclkhdr_67_io_en), .io_scan_mode(rvclkhdr_67_io_scan_mode) ); - rvclkhdr rvclkhdr_68 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_68 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_68_io_l1clk), .io_clk(rvclkhdr_68_io_clk), .io_en(rvclkhdr_68_io_en), .io_scan_mode(rvclkhdr_68_io_scan_mode) ); - rvclkhdr rvclkhdr_69 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_69 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_69_io_l1clk), .io_clk(rvclkhdr_69_io_clk), .io_en(rvclkhdr_69_io_en), .io_scan_mode(rvclkhdr_69_io_scan_mode) ); - rvclkhdr rvclkhdr_70 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_70 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_70_io_l1clk), .io_clk(rvclkhdr_70_io_clk), .io_en(rvclkhdr_70_io_en), .io_scan_mode(rvclkhdr_70_io_scan_mode) ); - rvclkhdr rvclkhdr_71 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_71 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_71_io_l1clk), .io_clk(rvclkhdr_71_io_clk), .io_en(rvclkhdr_71_io_en), .io_scan_mode(rvclkhdr_71_io_scan_mode) ); - rvclkhdr rvclkhdr_72 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_72 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_72_io_l1clk), .io_clk(rvclkhdr_72_io_clk), .io_en(rvclkhdr_72_io_en), .io_scan_mode(rvclkhdr_72_io_scan_mode) ); - rvclkhdr rvclkhdr_73 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_73 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_73_io_l1clk), .io_clk(rvclkhdr_73_io_clk), .io_en(rvclkhdr_73_io_en), .io_scan_mode(rvclkhdr_73_io_scan_mode) ); - rvclkhdr rvclkhdr_74 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_74 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_74_io_l1clk), .io_clk(rvclkhdr_74_io_clk), .io_en(rvclkhdr_74_io_en), .io_scan_mode(rvclkhdr_74_io_scan_mode) ); - rvclkhdr rvclkhdr_75 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_75 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_75_io_l1clk), .io_clk(rvclkhdr_75_io_clk), .io_en(rvclkhdr_75_io_en), .io_scan_mode(rvclkhdr_75_io_scan_mode) ); - rvclkhdr rvclkhdr_76 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_76 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_76_io_l1clk), .io_clk(rvclkhdr_76_io_clk), .io_en(rvclkhdr_76_io_en), .io_scan_mode(rvclkhdr_76_io_scan_mode) ); - rvclkhdr rvclkhdr_77 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_77 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_77_io_l1clk), .io_clk(rvclkhdr_77_io_clk), .io_en(rvclkhdr_77_io_en), .io_scan_mode(rvclkhdr_77_io_scan_mode) ); - rvclkhdr rvclkhdr_78 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_78 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_78_io_l1clk), .io_clk(rvclkhdr_78_io_clk), .io_en(rvclkhdr_78_io_en), .io_scan_mode(rvclkhdr_78_io_scan_mode) ); - rvclkhdr rvclkhdr_79 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_79 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_79_io_l1clk), .io_clk(rvclkhdr_79_io_clk), .io_en(rvclkhdr_79_io_en), .io_scan_mode(rvclkhdr_79_io_scan_mode) ); - rvclkhdr rvclkhdr_80 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_80 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_80_io_l1clk), .io_clk(rvclkhdr_80_io_clk), .io_en(rvclkhdr_80_io_en), .io_scan_mode(rvclkhdr_80_io_scan_mode) ); - rvclkhdr rvclkhdr_81 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_81 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_81_io_l1clk), .io_clk(rvclkhdr_81_io_clk), .io_en(rvclkhdr_81_io_en), .io_scan_mode(rvclkhdr_81_io_scan_mode) ); - rvclkhdr rvclkhdr_82 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_82 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_82_io_l1clk), .io_clk(rvclkhdr_82_io_clk), .io_en(rvclkhdr_82_io_en), .io_scan_mode(rvclkhdr_82_io_scan_mode) ); - rvclkhdr rvclkhdr_83 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_83 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_83_io_l1clk), .io_clk(rvclkhdr_83_io_clk), .io_en(rvclkhdr_83_io_en), .io_scan_mode(rvclkhdr_83_io_scan_mode) ); - rvclkhdr rvclkhdr_84 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_84 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_84_io_l1clk), .io_clk(rvclkhdr_84_io_clk), .io_en(rvclkhdr_84_io_en), .io_scan_mode(rvclkhdr_84_io_scan_mode) ); - rvclkhdr rvclkhdr_85 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_85 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_85_io_l1clk), .io_clk(rvclkhdr_85_io_clk), .io_en(rvclkhdr_85_io_en), .io_scan_mode(rvclkhdr_85_io_scan_mode) ); - rvclkhdr rvclkhdr_86 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_86 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_86_io_l1clk), .io_clk(rvclkhdr_86_io_clk), .io_en(rvclkhdr_86_io_en), .io_scan_mode(rvclkhdr_86_io_scan_mode) ); - rvclkhdr rvclkhdr_87 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_87 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_87_io_l1clk), .io_clk(rvclkhdr_87_io_clk), .io_en(rvclkhdr_87_io_en), .io_scan_mode(rvclkhdr_87_io_scan_mode) ); - rvclkhdr rvclkhdr_88 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_88 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_88_io_l1clk), .io_clk(rvclkhdr_88_io_clk), .io_en(rvclkhdr_88_io_en), .io_scan_mode(rvclkhdr_88_io_scan_mode) ); - rvclkhdr rvclkhdr_89 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_89 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_89_io_l1clk), .io_clk(rvclkhdr_89_io_clk), .io_en(rvclkhdr_89_io_en), .io_scan_mode(rvclkhdr_89_io_scan_mode) ); - rvclkhdr rvclkhdr_90 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_90 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_90_io_l1clk), .io_clk(rvclkhdr_90_io_clk), .io_en(rvclkhdr_90_io_en), .io_scan_mode(rvclkhdr_90_io_scan_mode) ); - rvclkhdr rvclkhdr_91 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_91 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_91_io_l1clk), .io_clk(rvclkhdr_91_io_clk), .io_en(rvclkhdr_91_io_en), .io_scan_mode(rvclkhdr_91_io_scan_mode) ); - rvclkhdr rvclkhdr_92 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_92 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_92_io_l1clk), .io_clk(rvclkhdr_92_io_clk), .io_en(rvclkhdr_92_io_en), .io_scan_mode(rvclkhdr_92_io_scan_mode) ); - rvclkhdr rvclkhdr_93 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_93 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_93_io_l1clk), .io_clk(rvclkhdr_93_io_clk), .io_en(rvclkhdr_93_io_en), .io_scan_mode(rvclkhdr_93_io_scan_mode) ); - rvclkhdr rvclkhdr_94 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_94 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_94_io_l1clk), .io_clk(rvclkhdr_94_io_clk), .io_en(rvclkhdr_94_io_en), .io_scan_mode(rvclkhdr_94_io_scan_mode) ); - rvclkhdr rvclkhdr_95 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_95 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_95_io_l1clk), .io_clk(rvclkhdr_95_io_clk), .io_en(rvclkhdr_95_io_en), .io_scan_mode(rvclkhdr_95_io_scan_mode) ); - rvclkhdr rvclkhdr_96 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_96 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_96_io_l1clk), .io_clk(rvclkhdr_96_io_clk), .io_en(rvclkhdr_96_io_en), .io_scan_mode(rvclkhdr_96_io_scan_mode) ); - rvclkhdr rvclkhdr_97 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_97 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_97_io_l1clk), .io_clk(rvclkhdr_97_io_clk), .io_en(rvclkhdr_97_io_en), .io_scan_mode(rvclkhdr_97_io_scan_mode) ); - rvclkhdr rvclkhdr_98 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_98 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_98_io_l1clk), .io_clk(rvclkhdr_98_io_clk), .io_en(rvclkhdr_98_io_en), .io_scan_mode(rvclkhdr_98_io_scan_mode) ); - rvclkhdr rvclkhdr_99 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_99 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_99_io_l1clk), .io_clk(rvclkhdr_99_io_clk), .io_en(rvclkhdr_99_io_en), .io_scan_mode(rvclkhdr_99_io_scan_mode) ); - rvclkhdr rvclkhdr_100 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_100 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_100_io_l1clk), .io_clk(rvclkhdr_100_io_clk), .io_en(rvclkhdr_100_io_en), .io_scan_mode(rvclkhdr_100_io_scan_mode) ); - rvclkhdr rvclkhdr_101 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_101 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_101_io_l1clk), .io_clk(rvclkhdr_101_io_clk), .io_en(rvclkhdr_101_io_en), .io_scan_mode(rvclkhdr_101_io_scan_mode) ); - rvclkhdr rvclkhdr_102 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_102 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_102_io_l1clk), .io_clk(rvclkhdr_102_io_clk), .io_en(rvclkhdr_102_io_en), .io_scan_mode(rvclkhdr_102_io_scan_mode) ); - rvclkhdr rvclkhdr_103 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_103 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_103_io_l1clk), .io_clk(rvclkhdr_103_io_clk), .io_en(rvclkhdr_103_io_en), .io_scan_mode(rvclkhdr_103_io_scan_mode) ); - rvclkhdr rvclkhdr_104 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_104 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_104_io_l1clk), .io_clk(rvclkhdr_104_io_clk), .io_en(rvclkhdr_104_io_en), .io_scan_mode(rvclkhdr_104_io_scan_mode) ); - rvclkhdr rvclkhdr_105 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_105 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_105_io_l1clk), .io_clk(rvclkhdr_105_io_clk), .io_en(rvclkhdr_105_io_en), .io_scan_mode(rvclkhdr_105_io_scan_mode) ); - rvclkhdr rvclkhdr_106 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_106 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_106_io_l1clk), .io_clk(rvclkhdr_106_io_clk), .io_en(rvclkhdr_106_io_en), .io_scan_mode(rvclkhdr_106_io_scan_mode) ); - rvclkhdr rvclkhdr_107 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_107 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_107_io_l1clk), .io_clk(rvclkhdr_107_io_clk), .io_en(rvclkhdr_107_io_en), .io_scan_mode(rvclkhdr_107_io_scan_mode) ); - rvclkhdr rvclkhdr_108 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_108 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_108_io_l1clk), .io_clk(rvclkhdr_108_io_clk), .io_en(rvclkhdr_108_io_en), .io_scan_mode(rvclkhdr_108_io_scan_mode) ); - rvclkhdr rvclkhdr_109 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_109 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_109_io_l1clk), .io_clk(rvclkhdr_109_io_clk), .io_en(rvclkhdr_109_io_en), .io_scan_mode(rvclkhdr_109_io_scan_mode) ); - rvclkhdr rvclkhdr_110 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_110 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_110_io_l1clk), .io_clk(rvclkhdr_110_io_clk), .io_en(rvclkhdr_110_io_en), .io_scan_mode(rvclkhdr_110_io_scan_mode) ); - rvclkhdr rvclkhdr_111 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_111 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_111_io_l1clk), .io_clk(rvclkhdr_111_io_clk), .io_en(rvclkhdr_111_io_en), .io_scan_mode(rvclkhdr_111_io_scan_mode) ); - rvclkhdr rvclkhdr_112 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_112 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_112_io_l1clk), .io_clk(rvclkhdr_112_io_clk), .io_en(rvclkhdr_112_io_en), .io_scan_mode(rvclkhdr_112_io_scan_mode) ); - rvclkhdr rvclkhdr_113 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_113 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_113_io_l1clk), .io_clk(rvclkhdr_113_io_clk), .io_en(rvclkhdr_113_io_en), .io_scan_mode(rvclkhdr_113_io_scan_mode) ); - rvclkhdr rvclkhdr_114 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_114 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_114_io_l1clk), .io_clk(rvclkhdr_114_io_clk), .io_en(rvclkhdr_114_io_en), .io_scan_mode(rvclkhdr_114_io_scan_mode) ); - rvclkhdr rvclkhdr_115 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_115 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_115_io_l1clk), .io_clk(rvclkhdr_115_io_clk), .io_en(rvclkhdr_115_io_en), .io_scan_mode(rvclkhdr_115_io_scan_mode) ); - rvclkhdr rvclkhdr_116 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_116 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_116_io_l1clk), .io_clk(rvclkhdr_116_io_clk), .io_en(rvclkhdr_116_io_en), .io_scan_mode(rvclkhdr_116_io_scan_mode) ); - rvclkhdr rvclkhdr_117 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_117 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_117_io_l1clk), .io_clk(rvclkhdr_117_io_clk), .io_en(rvclkhdr_117_io_en), .io_scan_mode(rvclkhdr_117_io_scan_mode) ); - rvclkhdr rvclkhdr_118 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_118 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_118_io_l1clk), .io_clk(rvclkhdr_118_io_clk), .io_en(rvclkhdr_118_io_en), .io_scan_mode(rvclkhdr_118_io_scan_mode) ); - rvclkhdr rvclkhdr_119 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_119 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_119_io_l1clk), .io_clk(rvclkhdr_119_io_clk), .io_en(rvclkhdr_119_io_en), .io_scan_mode(rvclkhdr_119_io_scan_mode) ); - rvclkhdr rvclkhdr_120 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_120 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_120_io_l1clk), .io_clk(rvclkhdr_120_io_clk), .io_en(rvclkhdr_120_io_en), .io_scan_mode(rvclkhdr_120_io_scan_mode) ); - rvclkhdr rvclkhdr_121 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_121 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_121_io_l1clk), .io_clk(rvclkhdr_121_io_clk), .io_en(rvclkhdr_121_io_en), .io_scan_mode(rvclkhdr_121_io_scan_mode) ); - rvclkhdr rvclkhdr_122 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_122 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_122_io_l1clk), .io_clk(rvclkhdr_122_io_clk), .io_en(rvclkhdr_122_io_en), .io_scan_mode(rvclkhdr_122_io_scan_mode) ); - rvclkhdr rvclkhdr_123 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_123 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_123_io_l1clk), .io_clk(rvclkhdr_123_io_clk), .io_en(rvclkhdr_123_io_en), .io_scan_mode(rvclkhdr_123_io_scan_mode) ); - rvclkhdr rvclkhdr_124 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_124 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_124_io_l1clk), .io_clk(rvclkhdr_124_io_clk), .io_en(rvclkhdr_124_io_en), .io_scan_mode(rvclkhdr_124_io_scan_mode) ); - rvclkhdr rvclkhdr_125 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_125 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_125_io_l1clk), .io_clk(rvclkhdr_125_io_clk), .io_en(rvclkhdr_125_io_en), .io_scan_mode(rvclkhdr_125_io_scan_mode) ); - rvclkhdr rvclkhdr_126 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_126 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_126_io_l1clk), .io_clk(rvclkhdr_126_io_clk), .io_en(rvclkhdr_126_io_en), .io_scan_mode(rvclkhdr_126_io_scan_mode) ); - rvclkhdr rvclkhdr_127 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_127 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_127_io_l1clk), .io_clk(rvclkhdr_127_io_clk), .io_en(rvclkhdr_127_io_en), .io_scan_mode(rvclkhdr_127_io_scan_mode) ); - rvclkhdr rvclkhdr_128 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_128 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_128_io_l1clk), .io_clk(rvclkhdr_128_io_clk), .io_en(rvclkhdr_128_io_en), .io_scan_mode(rvclkhdr_128_io_scan_mode) ); - rvclkhdr rvclkhdr_129 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_129 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_129_io_l1clk), .io_clk(rvclkhdr_129_io_clk), .io_en(rvclkhdr_129_io_en), .io_scan_mode(rvclkhdr_129_io_scan_mode) ); - rvclkhdr rvclkhdr_130 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_130 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_130_io_l1clk), .io_clk(rvclkhdr_130_io_clk), .io_en(rvclkhdr_130_io_en), .io_scan_mode(rvclkhdr_130_io_scan_mode) ); - rvclkhdr rvclkhdr_131 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_131 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_131_io_l1clk), .io_clk(rvclkhdr_131_io_clk), .io_en(rvclkhdr_131_io_en), .io_scan_mode(rvclkhdr_131_io_scan_mode) ); - rvclkhdr rvclkhdr_132 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_132 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_132_io_l1clk), .io_clk(rvclkhdr_132_io_clk), .io_en(rvclkhdr_132_io_en), .io_scan_mode(rvclkhdr_132_io_scan_mode) ); - rvclkhdr rvclkhdr_133 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_133 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_133_io_l1clk), .io_clk(rvclkhdr_133_io_clk), .io_en(rvclkhdr_133_io_en), .io_scan_mode(rvclkhdr_133_io_scan_mode) ); - rvclkhdr rvclkhdr_134 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_134 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_134_io_l1clk), .io_clk(rvclkhdr_134_io_clk), .io_en(rvclkhdr_134_io_en), .io_scan_mode(rvclkhdr_134_io_scan_mode) ); - rvclkhdr rvclkhdr_135 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_135 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_135_io_l1clk), .io_clk(rvclkhdr_135_io_clk), .io_en(rvclkhdr_135_io_en), .io_scan_mode(rvclkhdr_135_io_scan_mode) ); - rvclkhdr rvclkhdr_136 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_136 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_136_io_l1clk), .io_clk(rvclkhdr_136_io_clk), .io_en(rvclkhdr_136_io_en), .io_scan_mode(rvclkhdr_136_io_scan_mode) ); - rvclkhdr rvclkhdr_137 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_137 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_137_io_l1clk), .io_clk(rvclkhdr_137_io_clk), .io_en(rvclkhdr_137_io_en), .io_scan_mode(rvclkhdr_137_io_scan_mode) ); - rvclkhdr rvclkhdr_138 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_138 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_138_io_l1clk), .io_clk(rvclkhdr_138_io_clk), .io_en(rvclkhdr_138_io_en), .io_scan_mode(rvclkhdr_138_io_scan_mode) ); - rvclkhdr rvclkhdr_139 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_139 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_139_io_l1clk), .io_clk(rvclkhdr_139_io_clk), .io_en(rvclkhdr_139_io_en), .io_scan_mode(rvclkhdr_139_io_scan_mode) ); - rvclkhdr rvclkhdr_140 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_140 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_140_io_l1clk), .io_clk(rvclkhdr_140_io_clk), .io_en(rvclkhdr_140_io_en), .io_scan_mode(rvclkhdr_140_io_scan_mode) ); - rvclkhdr rvclkhdr_141 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_141 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_141_io_l1clk), .io_clk(rvclkhdr_141_io_clk), .io_en(rvclkhdr_141_io_en), .io_scan_mode(rvclkhdr_141_io_scan_mode) ); - rvclkhdr rvclkhdr_142 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_142 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_142_io_l1clk), .io_clk(rvclkhdr_142_io_clk), .io_en(rvclkhdr_142_io_en), .io_scan_mode(rvclkhdr_142_io_scan_mode) ); - rvclkhdr rvclkhdr_143 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_143 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_143_io_l1clk), .io_clk(rvclkhdr_143_io_clk), .io_en(rvclkhdr_143_io_en), .io_scan_mode(rvclkhdr_143_io_scan_mode) ); - rvclkhdr rvclkhdr_144 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_144 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_144_io_l1clk), .io_clk(rvclkhdr_144_io_clk), .io_en(rvclkhdr_144_io_en), .io_scan_mode(rvclkhdr_144_io_scan_mode) ); - rvclkhdr rvclkhdr_145 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_145 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_145_io_l1clk), .io_clk(rvclkhdr_145_io_clk), .io_en(rvclkhdr_145_io_en), .io_scan_mode(rvclkhdr_145_io_scan_mode) ); - rvclkhdr rvclkhdr_146 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_146 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_146_io_l1clk), .io_clk(rvclkhdr_146_io_clk), .io_en(rvclkhdr_146_io_en), .io_scan_mode(rvclkhdr_146_io_scan_mode) ); - rvclkhdr rvclkhdr_147 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_147 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_147_io_l1clk), .io_clk(rvclkhdr_147_io_clk), .io_en(rvclkhdr_147_io_en), .io_scan_mode(rvclkhdr_147_io_scan_mode) ); - rvclkhdr rvclkhdr_148 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_148 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_148_io_l1clk), .io_clk(rvclkhdr_148_io_clk), .io_en(rvclkhdr_148_io_en), .io_scan_mode(rvclkhdr_148_io_scan_mode) ); - rvclkhdr rvclkhdr_149 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_149 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_149_io_l1clk), .io_clk(rvclkhdr_149_io_clk), .io_en(rvclkhdr_149_io_en), .io_scan_mode(rvclkhdr_149_io_scan_mode) ); - rvclkhdr rvclkhdr_150 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_150 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_150_io_l1clk), .io_clk(rvclkhdr_150_io_clk), .io_en(rvclkhdr_150_io_en), .io_scan_mode(rvclkhdr_150_io_scan_mode) ); - rvclkhdr rvclkhdr_151 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_151 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_151_io_l1clk), .io_clk(rvclkhdr_151_io_clk), .io_en(rvclkhdr_151_io_en), .io_scan_mode(rvclkhdr_151_io_scan_mode) ); - rvclkhdr rvclkhdr_152 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_152 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_152_io_l1clk), .io_clk(rvclkhdr_152_io_clk), .io_en(rvclkhdr_152_io_en), .io_scan_mode(rvclkhdr_152_io_scan_mode) ); - rvclkhdr rvclkhdr_153 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_153 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_153_io_l1clk), .io_clk(rvclkhdr_153_io_clk), .io_en(rvclkhdr_153_io_en), .io_scan_mode(rvclkhdr_153_io_scan_mode) ); - rvclkhdr rvclkhdr_154 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_154 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_154_io_l1clk), .io_clk(rvclkhdr_154_io_clk), .io_en(rvclkhdr_154_io_en), .io_scan_mode(rvclkhdr_154_io_scan_mode) ); - rvclkhdr rvclkhdr_155 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_155 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_155_io_l1clk), .io_clk(rvclkhdr_155_io_clk), .io_en(rvclkhdr_155_io_en), .io_scan_mode(rvclkhdr_155_io_scan_mode) ); - rvclkhdr rvclkhdr_156 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_156 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_156_io_l1clk), .io_clk(rvclkhdr_156_io_clk), .io_en(rvclkhdr_156_io_en), .io_scan_mode(rvclkhdr_156_io_scan_mode) ); - rvclkhdr rvclkhdr_157 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_157 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_157_io_l1clk), .io_clk(rvclkhdr_157_io_clk), .io_en(rvclkhdr_157_io_en), .io_scan_mode(rvclkhdr_157_io_scan_mode) ); - rvclkhdr rvclkhdr_158 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_158 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_158_io_l1clk), .io_clk(rvclkhdr_158_io_clk), .io_en(rvclkhdr_158_io_en), .io_scan_mode(rvclkhdr_158_io_scan_mode) ); - rvclkhdr rvclkhdr_159 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_159 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_159_io_l1clk), .io_clk(rvclkhdr_159_io_clk), .io_en(rvclkhdr_159_io_en), .io_scan_mode(rvclkhdr_159_io_scan_mode) ); - rvclkhdr rvclkhdr_160 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_160 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_160_io_l1clk), .io_clk(rvclkhdr_160_io_clk), .io_en(rvclkhdr_160_io_en), .io_scan_mode(rvclkhdr_160_io_scan_mode) ); - rvclkhdr rvclkhdr_161 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_161 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_161_io_l1clk), .io_clk(rvclkhdr_161_io_clk), .io_en(rvclkhdr_161_io_en), .io_scan_mode(rvclkhdr_161_io_scan_mode) ); - rvclkhdr rvclkhdr_162 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_162 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_162_io_l1clk), .io_clk(rvclkhdr_162_io_clk), .io_en(rvclkhdr_162_io_en), .io_scan_mode(rvclkhdr_162_io_scan_mode) ); - rvclkhdr rvclkhdr_163 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_163 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_163_io_l1clk), .io_clk(rvclkhdr_163_io_clk), .io_en(rvclkhdr_163_io_en), .io_scan_mode(rvclkhdr_163_io_scan_mode) ); - rvclkhdr rvclkhdr_164 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_164 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_164_io_l1clk), .io_clk(rvclkhdr_164_io_clk), .io_en(rvclkhdr_164_io_en), .io_scan_mode(rvclkhdr_164_io_scan_mode) ); - rvclkhdr rvclkhdr_165 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_165 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_165_io_l1clk), .io_clk(rvclkhdr_165_io_clk), .io_en(rvclkhdr_165_io_en), .io_scan_mode(rvclkhdr_165_io_scan_mode) ); - rvclkhdr rvclkhdr_166 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_166 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_166_io_l1clk), .io_clk(rvclkhdr_166_io_clk), .io_en(rvclkhdr_166_io_en), .io_scan_mode(rvclkhdr_166_io_scan_mode) ); - rvclkhdr rvclkhdr_167 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_167 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_167_io_l1clk), .io_clk(rvclkhdr_167_io_clk), .io_en(rvclkhdr_167_io_en), .io_scan_mode(rvclkhdr_167_io_scan_mode) ); - rvclkhdr rvclkhdr_168 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_168 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_168_io_l1clk), .io_clk(rvclkhdr_168_io_clk), .io_en(rvclkhdr_168_io_en), .io_scan_mode(rvclkhdr_168_io_scan_mode) ); - rvclkhdr rvclkhdr_169 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_169 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_169_io_l1clk), .io_clk(rvclkhdr_169_io_clk), .io_en(rvclkhdr_169_io_en), .io_scan_mode(rvclkhdr_169_io_scan_mode) ); - rvclkhdr rvclkhdr_170 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_170 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_170_io_l1clk), .io_clk(rvclkhdr_170_io_clk), .io_en(rvclkhdr_170_io_en), .io_scan_mode(rvclkhdr_170_io_scan_mode) ); - rvclkhdr rvclkhdr_171 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_171 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_171_io_l1clk), .io_clk(rvclkhdr_171_io_clk), .io_en(rvclkhdr_171_io_en), .io_scan_mode(rvclkhdr_171_io_scan_mode) ); - rvclkhdr rvclkhdr_172 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_172 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_172_io_l1clk), .io_clk(rvclkhdr_172_io_clk), .io_en(rvclkhdr_172_io_en), .io_scan_mode(rvclkhdr_172_io_scan_mode) ); - rvclkhdr rvclkhdr_173 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_173 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_173_io_l1clk), .io_clk(rvclkhdr_173_io_clk), .io_en(rvclkhdr_173_io_en), .io_scan_mode(rvclkhdr_173_io_scan_mode) ); - rvclkhdr rvclkhdr_174 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_174 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_174_io_l1clk), .io_clk(rvclkhdr_174_io_clk), .io_en(rvclkhdr_174_io_en), .io_scan_mode(rvclkhdr_174_io_scan_mode) ); - rvclkhdr rvclkhdr_175 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_175 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_175_io_l1clk), .io_clk(rvclkhdr_175_io_clk), .io_en(rvclkhdr_175_io_en), .io_scan_mode(rvclkhdr_175_io_scan_mode) ); - rvclkhdr rvclkhdr_176 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_176 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_176_io_l1clk), .io_clk(rvclkhdr_176_io_clk), .io_en(rvclkhdr_176_io_en), .io_scan_mode(rvclkhdr_176_io_scan_mode) ); - rvclkhdr rvclkhdr_177 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_177 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_177_io_l1clk), .io_clk(rvclkhdr_177_io_clk), .io_en(rvclkhdr_177_io_en), .io_scan_mode(rvclkhdr_177_io_scan_mode) ); - rvclkhdr rvclkhdr_178 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_178 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_178_io_l1clk), .io_clk(rvclkhdr_178_io_clk), .io_en(rvclkhdr_178_io_en), .io_scan_mode(rvclkhdr_178_io_scan_mode) ); - rvclkhdr rvclkhdr_179 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_179 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_179_io_l1clk), .io_clk(rvclkhdr_179_io_clk), .io_en(rvclkhdr_179_io_en), .io_scan_mode(rvclkhdr_179_io_scan_mode) ); - rvclkhdr rvclkhdr_180 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_180 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_180_io_l1clk), .io_clk(rvclkhdr_180_io_clk), .io_en(rvclkhdr_180_io_en), .io_scan_mode(rvclkhdr_180_io_scan_mode) ); - rvclkhdr rvclkhdr_181 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_181 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_181_io_l1clk), .io_clk(rvclkhdr_181_io_clk), .io_en(rvclkhdr_181_io_en), .io_scan_mode(rvclkhdr_181_io_scan_mode) ); - rvclkhdr rvclkhdr_182 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_182 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_182_io_l1clk), .io_clk(rvclkhdr_182_io_clk), .io_en(rvclkhdr_182_io_en), .io_scan_mode(rvclkhdr_182_io_scan_mode) ); - rvclkhdr rvclkhdr_183 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_183 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_183_io_l1clk), .io_clk(rvclkhdr_183_io_clk), .io_en(rvclkhdr_183_io_en), .io_scan_mode(rvclkhdr_183_io_scan_mode) ); - rvclkhdr rvclkhdr_184 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_184 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_184_io_l1clk), .io_clk(rvclkhdr_184_io_clk), .io_en(rvclkhdr_184_io_en), .io_scan_mode(rvclkhdr_184_io_scan_mode) ); - rvclkhdr rvclkhdr_185 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_185 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_185_io_l1clk), .io_clk(rvclkhdr_185_io_clk), .io_en(rvclkhdr_185_io_en), .io_scan_mode(rvclkhdr_185_io_scan_mode) ); - rvclkhdr rvclkhdr_186 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_186 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_186_io_l1clk), .io_clk(rvclkhdr_186_io_clk), .io_en(rvclkhdr_186_io_en), .io_scan_mode(rvclkhdr_186_io_scan_mode) ); - rvclkhdr rvclkhdr_187 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_187 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_187_io_l1clk), .io_clk(rvclkhdr_187_io_clk), .io_en(rvclkhdr_187_io_en), .io_scan_mode(rvclkhdr_187_io_scan_mode) ); - rvclkhdr rvclkhdr_188 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_188 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_188_io_l1clk), .io_clk(rvclkhdr_188_io_clk), .io_en(rvclkhdr_188_io_en), .io_scan_mode(rvclkhdr_188_io_scan_mode) ); - rvclkhdr rvclkhdr_189 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_189 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_189_io_l1clk), .io_clk(rvclkhdr_189_io_clk), .io_en(rvclkhdr_189_io_en), .io_scan_mode(rvclkhdr_189_io_scan_mode) ); - rvclkhdr rvclkhdr_190 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_190 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_190_io_l1clk), .io_clk(rvclkhdr_190_io_clk), .io_en(rvclkhdr_190_io_en), .io_scan_mode(rvclkhdr_190_io_scan_mode) ); - rvclkhdr rvclkhdr_191 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_191 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_191_io_l1clk), .io_clk(rvclkhdr_191_io_clk), .io_en(rvclkhdr_191_io_en), .io_scan_mode(rvclkhdr_191_io_scan_mode) ); - rvclkhdr rvclkhdr_192 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_192 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_192_io_l1clk), .io_clk(rvclkhdr_192_io_clk), .io_en(rvclkhdr_192_io_en), .io_scan_mode(rvclkhdr_192_io_scan_mode) ); - rvclkhdr rvclkhdr_193 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_193 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_193_io_l1clk), .io_clk(rvclkhdr_193_io_clk), .io_en(rvclkhdr_193_io_en), .io_scan_mode(rvclkhdr_193_io_scan_mode) ); - rvclkhdr rvclkhdr_194 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_194 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_194_io_l1clk), .io_clk(rvclkhdr_194_io_clk), .io_en(rvclkhdr_194_io_en), .io_scan_mode(rvclkhdr_194_io_scan_mode) ); - rvclkhdr rvclkhdr_195 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_195 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_195_io_l1clk), .io_clk(rvclkhdr_195_io_clk), .io_en(rvclkhdr_195_io_en), .io_scan_mode(rvclkhdr_195_io_scan_mode) ); - rvclkhdr rvclkhdr_196 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_196 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_196_io_l1clk), .io_clk(rvclkhdr_196_io_clk), .io_en(rvclkhdr_196_io_en), .io_scan_mode(rvclkhdr_196_io_scan_mode) ); - rvclkhdr rvclkhdr_197 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_197 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_197_io_l1clk), .io_clk(rvclkhdr_197_io_clk), .io_en(rvclkhdr_197_io_en), .io_scan_mode(rvclkhdr_197_io_scan_mode) ); - rvclkhdr rvclkhdr_198 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_198 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_198_io_l1clk), .io_clk(rvclkhdr_198_io_clk), .io_en(rvclkhdr_198_io_en), .io_scan_mode(rvclkhdr_198_io_scan_mode) ); - rvclkhdr rvclkhdr_199 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_199 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_199_io_l1clk), .io_clk(rvclkhdr_199_io_clk), .io_en(rvclkhdr_199_io_en), .io_scan_mode(rvclkhdr_199_io_scan_mode) ); - rvclkhdr rvclkhdr_200 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_200 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_200_io_l1clk), .io_clk(rvclkhdr_200_io_clk), .io_en(rvclkhdr_200_io_en), .io_scan_mode(rvclkhdr_200_io_scan_mode) ); - rvclkhdr rvclkhdr_201 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_201 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_201_io_l1clk), .io_clk(rvclkhdr_201_io_clk), .io_en(rvclkhdr_201_io_en), .io_scan_mode(rvclkhdr_201_io_scan_mode) ); - rvclkhdr rvclkhdr_202 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_202 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_202_io_l1clk), .io_clk(rvclkhdr_202_io_clk), .io_en(rvclkhdr_202_io_en), .io_scan_mode(rvclkhdr_202_io_scan_mode) ); - rvclkhdr rvclkhdr_203 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_203 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_203_io_l1clk), .io_clk(rvclkhdr_203_io_clk), .io_en(rvclkhdr_203_io_en), .io_scan_mode(rvclkhdr_203_io_scan_mode) ); - rvclkhdr rvclkhdr_204 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_204 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_204_io_l1clk), .io_clk(rvclkhdr_204_io_clk), .io_en(rvclkhdr_204_io_en), .io_scan_mode(rvclkhdr_204_io_scan_mode) ); - rvclkhdr rvclkhdr_205 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_205 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_205_io_l1clk), .io_clk(rvclkhdr_205_io_clk), .io_en(rvclkhdr_205_io_en), .io_scan_mode(rvclkhdr_205_io_scan_mode) ); - rvclkhdr rvclkhdr_206 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_206 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_206_io_l1clk), .io_clk(rvclkhdr_206_io_clk), .io_en(rvclkhdr_206_io_en), .io_scan_mode(rvclkhdr_206_io_scan_mode) ); - rvclkhdr rvclkhdr_207 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_207 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_207_io_l1clk), .io_clk(rvclkhdr_207_io_clk), .io_en(rvclkhdr_207_io_en), .io_scan_mode(rvclkhdr_207_io_scan_mode) ); - rvclkhdr rvclkhdr_208 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_208 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_208_io_l1clk), .io_clk(rvclkhdr_208_io_clk), .io_en(rvclkhdr_208_io_en), .io_scan_mode(rvclkhdr_208_io_scan_mode) ); - rvclkhdr rvclkhdr_209 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_209 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_209_io_l1clk), .io_clk(rvclkhdr_209_io_clk), .io_en(rvclkhdr_209_io_en), .io_scan_mode(rvclkhdr_209_io_scan_mode) ); - rvclkhdr rvclkhdr_210 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_210 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_210_io_l1clk), .io_clk(rvclkhdr_210_io_clk), .io_en(rvclkhdr_210_io_en), .io_scan_mode(rvclkhdr_210_io_scan_mode) ); - rvclkhdr rvclkhdr_211 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_211 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_211_io_l1clk), .io_clk(rvclkhdr_211_io_clk), .io_en(rvclkhdr_211_io_en), .io_scan_mode(rvclkhdr_211_io_scan_mode) ); - rvclkhdr rvclkhdr_212 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_212 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_212_io_l1clk), .io_clk(rvclkhdr_212_io_clk), .io_en(rvclkhdr_212_io_en), .io_scan_mode(rvclkhdr_212_io_scan_mode) ); - rvclkhdr rvclkhdr_213 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_213 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_213_io_l1clk), .io_clk(rvclkhdr_213_io_clk), .io_en(rvclkhdr_213_io_en), .io_scan_mode(rvclkhdr_213_io_scan_mode) ); - rvclkhdr rvclkhdr_214 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_214 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_214_io_l1clk), .io_clk(rvclkhdr_214_io_clk), .io_en(rvclkhdr_214_io_en), .io_scan_mode(rvclkhdr_214_io_scan_mode) ); - rvclkhdr rvclkhdr_215 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_215 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_215_io_l1clk), .io_clk(rvclkhdr_215_io_clk), .io_en(rvclkhdr_215_io_en), .io_scan_mode(rvclkhdr_215_io_scan_mode) ); - rvclkhdr rvclkhdr_216 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_216 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_216_io_l1clk), .io_clk(rvclkhdr_216_io_clk), .io_en(rvclkhdr_216_io_en), .io_scan_mode(rvclkhdr_216_io_scan_mode) ); - rvclkhdr rvclkhdr_217 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_217 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_217_io_l1clk), .io_clk(rvclkhdr_217_io_clk), .io_en(rvclkhdr_217_io_en), .io_scan_mode(rvclkhdr_217_io_scan_mode) ); - rvclkhdr rvclkhdr_218 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_218 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_218_io_l1clk), .io_clk(rvclkhdr_218_io_clk), .io_en(rvclkhdr_218_io_en), .io_scan_mode(rvclkhdr_218_io_scan_mode) ); - rvclkhdr rvclkhdr_219 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_219 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_219_io_l1clk), .io_clk(rvclkhdr_219_io_clk), .io_en(rvclkhdr_219_io_en), .io_scan_mode(rvclkhdr_219_io_scan_mode) ); - rvclkhdr rvclkhdr_220 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_220 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_220_io_l1clk), .io_clk(rvclkhdr_220_io_clk), .io_en(rvclkhdr_220_io_en), .io_scan_mode(rvclkhdr_220_io_scan_mode) ); - rvclkhdr rvclkhdr_221 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_221 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_221_io_l1clk), .io_clk(rvclkhdr_221_io_clk), .io_en(rvclkhdr_221_io_en), .io_scan_mode(rvclkhdr_221_io_scan_mode) ); - rvclkhdr rvclkhdr_222 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_222 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_222_io_l1clk), .io_clk(rvclkhdr_222_io_clk), .io_en(rvclkhdr_222_io_en), .io_scan_mode(rvclkhdr_222_io_scan_mode) ); - rvclkhdr rvclkhdr_223 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_223 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_223_io_l1clk), .io_clk(rvclkhdr_223_io_clk), .io_en(rvclkhdr_223_io_en), .io_scan_mode(rvclkhdr_223_io_scan_mode) ); - rvclkhdr rvclkhdr_224 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_224 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_224_io_l1clk), .io_clk(rvclkhdr_224_io_clk), .io_en(rvclkhdr_224_io_en), .io_scan_mode(rvclkhdr_224_io_scan_mode) ); - rvclkhdr rvclkhdr_225 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_225 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_225_io_l1clk), .io_clk(rvclkhdr_225_io_clk), .io_en(rvclkhdr_225_io_en), .io_scan_mode(rvclkhdr_225_io_scan_mode) ); - rvclkhdr rvclkhdr_226 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_226 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_226_io_l1clk), .io_clk(rvclkhdr_226_io_clk), .io_en(rvclkhdr_226_io_en), .io_scan_mode(rvclkhdr_226_io_scan_mode) ); - rvclkhdr rvclkhdr_227 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_227 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_227_io_l1clk), .io_clk(rvclkhdr_227_io_clk), .io_en(rvclkhdr_227_io_en), .io_scan_mode(rvclkhdr_227_io_scan_mode) ); - rvclkhdr rvclkhdr_228 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_228 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_228_io_l1clk), .io_clk(rvclkhdr_228_io_clk), .io_en(rvclkhdr_228_io_en), .io_scan_mode(rvclkhdr_228_io_scan_mode) ); - rvclkhdr rvclkhdr_229 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_229 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_229_io_l1clk), .io_clk(rvclkhdr_229_io_clk), .io_en(rvclkhdr_229_io_en), .io_scan_mode(rvclkhdr_229_io_scan_mode) ); - rvclkhdr rvclkhdr_230 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_230 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_230_io_l1clk), .io_clk(rvclkhdr_230_io_clk), .io_en(rvclkhdr_230_io_en), .io_scan_mode(rvclkhdr_230_io_scan_mode) ); - rvclkhdr rvclkhdr_231 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_231 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_231_io_l1clk), .io_clk(rvclkhdr_231_io_clk), .io_en(rvclkhdr_231_io_en), .io_scan_mode(rvclkhdr_231_io_scan_mode) ); - rvclkhdr rvclkhdr_232 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_232 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_232_io_l1clk), .io_clk(rvclkhdr_232_io_clk), .io_en(rvclkhdr_232_io_en), .io_scan_mode(rvclkhdr_232_io_scan_mode) ); - rvclkhdr rvclkhdr_233 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_233 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_233_io_l1clk), .io_clk(rvclkhdr_233_io_clk), .io_en(rvclkhdr_233_io_en), .io_scan_mode(rvclkhdr_233_io_scan_mode) ); - rvclkhdr rvclkhdr_234 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_234 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_234_io_l1clk), .io_clk(rvclkhdr_234_io_clk), .io_en(rvclkhdr_234_io_en), .io_scan_mode(rvclkhdr_234_io_scan_mode) ); - rvclkhdr rvclkhdr_235 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_235 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_235_io_l1clk), .io_clk(rvclkhdr_235_io_clk), .io_en(rvclkhdr_235_io_en), .io_scan_mode(rvclkhdr_235_io_scan_mode) ); - rvclkhdr rvclkhdr_236 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_236 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_236_io_l1clk), .io_clk(rvclkhdr_236_io_clk), .io_en(rvclkhdr_236_io_en), .io_scan_mode(rvclkhdr_236_io_scan_mode) ); - rvclkhdr rvclkhdr_237 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_237 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_237_io_l1clk), .io_clk(rvclkhdr_237_io_clk), .io_en(rvclkhdr_237_io_en), .io_scan_mode(rvclkhdr_237_io_scan_mode) ); - rvclkhdr rvclkhdr_238 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_238 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_238_io_l1clk), .io_clk(rvclkhdr_238_io_clk), .io_en(rvclkhdr_238_io_en), .io_scan_mode(rvclkhdr_238_io_scan_mode) ); - rvclkhdr rvclkhdr_239 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_239 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_239_io_l1clk), .io_clk(rvclkhdr_239_io_clk), .io_en(rvclkhdr_239_io_en), .io_scan_mode(rvclkhdr_239_io_scan_mode) ); - rvclkhdr rvclkhdr_240 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_240 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_240_io_l1clk), .io_clk(rvclkhdr_240_io_clk), .io_en(rvclkhdr_240_io_en), .io_scan_mode(rvclkhdr_240_io_scan_mode) ); - rvclkhdr rvclkhdr_241 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_241 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_241_io_l1clk), .io_clk(rvclkhdr_241_io_clk), .io_en(rvclkhdr_241_io_en), .io_scan_mode(rvclkhdr_241_io_scan_mode) ); - rvclkhdr rvclkhdr_242 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_242 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_242_io_l1clk), .io_clk(rvclkhdr_242_io_clk), .io_en(rvclkhdr_242_io_en), .io_scan_mode(rvclkhdr_242_io_scan_mode) ); - rvclkhdr rvclkhdr_243 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_243 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_243_io_l1clk), .io_clk(rvclkhdr_243_io_clk), .io_en(rvclkhdr_243_io_en), .io_scan_mode(rvclkhdr_243_io_scan_mode) ); - rvclkhdr rvclkhdr_244 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_244 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_244_io_l1clk), .io_clk(rvclkhdr_244_io_clk), .io_en(rvclkhdr_244_io_en), .io_scan_mode(rvclkhdr_244_io_scan_mode) ); - rvclkhdr rvclkhdr_245 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_245 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_245_io_l1clk), .io_clk(rvclkhdr_245_io_clk), .io_en(rvclkhdr_245_io_en), .io_scan_mode(rvclkhdr_245_io_scan_mode) ); - rvclkhdr rvclkhdr_246 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_246 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_246_io_l1clk), .io_clk(rvclkhdr_246_io_clk), .io_en(rvclkhdr_246_io_en), .io_scan_mode(rvclkhdr_246_io_scan_mode) ); - rvclkhdr rvclkhdr_247 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_247 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_247_io_l1clk), .io_clk(rvclkhdr_247_io_clk), .io_en(rvclkhdr_247_io_en), .io_scan_mode(rvclkhdr_247_io_scan_mode) ); - rvclkhdr rvclkhdr_248 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_248 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_248_io_l1clk), .io_clk(rvclkhdr_248_io_clk), .io_en(rvclkhdr_248_io_en), .io_scan_mode(rvclkhdr_248_io_scan_mode) ); - rvclkhdr rvclkhdr_249 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_249 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_249_io_l1clk), .io_clk(rvclkhdr_249_io_clk), .io_en(rvclkhdr_249_io_en), .io_scan_mode(rvclkhdr_249_io_scan_mode) ); - rvclkhdr rvclkhdr_250 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_250 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_250_io_l1clk), .io_clk(rvclkhdr_250_io_clk), .io_en(rvclkhdr_250_io_en), .io_scan_mode(rvclkhdr_250_io_scan_mode) ); - rvclkhdr rvclkhdr_251 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_251 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_251_io_l1clk), .io_clk(rvclkhdr_251_io_clk), .io_en(rvclkhdr_251_io_en), .io_scan_mode(rvclkhdr_251_io_scan_mode) ); - rvclkhdr rvclkhdr_252 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_252 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_252_io_l1clk), .io_clk(rvclkhdr_252_io_clk), .io_en(rvclkhdr_252_io_en), .io_scan_mode(rvclkhdr_252_io_scan_mode) ); - rvclkhdr rvclkhdr_253 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_253 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_253_io_l1clk), .io_clk(rvclkhdr_253_io_clk), .io_en(rvclkhdr_253_io_en), .io_scan_mode(rvclkhdr_253_io_scan_mode) ); - rvclkhdr rvclkhdr_254 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_254 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_254_io_l1clk), .io_clk(rvclkhdr_254_io_clk), .io_en(rvclkhdr_254_io_en), .io_scan_mode(rvclkhdr_254_io_scan_mode) ); - rvclkhdr rvclkhdr_255 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_255 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_255_io_l1clk), .io_clk(rvclkhdr_255_io_clk), .io_en(rvclkhdr_255_io_en), .io_scan_mode(rvclkhdr_255_io_scan_mode) ); - rvclkhdr rvclkhdr_256 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_256 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_256_io_l1clk), .io_clk(rvclkhdr_256_io_clk), .io_en(rvclkhdr_256_io_en), .io_scan_mode(rvclkhdr_256_io_scan_mode) ); - rvclkhdr rvclkhdr_257 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_257 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_257_io_l1clk), .io_clk(rvclkhdr_257_io_clk), .io_en(rvclkhdr_257_io_en), .io_scan_mode(rvclkhdr_257_io_scan_mode) ); - rvclkhdr rvclkhdr_258 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_258 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_258_io_l1clk), .io_clk(rvclkhdr_258_io_clk), .io_en(rvclkhdr_258_io_en), .io_scan_mode(rvclkhdr_258_io_scan_mode) ); - rvclkhdr rvclkhdr_259 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_259 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_259_io_l1clk), .io_clk(rvclkhdr_259_io_clk), .io_en(rvclkhdr_259_io_en), .io_scan_mode(rvclkhdr_259_io_scan_mode) ); - rvclkhdr rvclkhdr_260 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_260 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_260_io_l1clk), .io_clk(rvclkhdr_260_io_clk), .io_en(rvclkhdr_260_io_en), .io_scan_mode(rvclkhdr_260_io_scan_mode) ); - rvclkhdr rvclkhdr_261 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_261 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_261_io_l1clk), .io_clk(rvclkhdr_261_io_clk), .io_en(rvclkhdr_261_io_en), .io_scan_mode(rvclkhdr_261_io_scan_mode) ); - rvclkhdr rvclkhdr_262 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_262 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_262_io_l1clk), .io_clk(rvclkhdr_262_io_clk), .io_en(rvclkhdr_262_io_en), .io_scan_mode(rvclkhdr_262_io_scan_mode) ); - rvclkhdr rvclkhdr_263 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_263 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_263_io_l1clk), .io_clk(rvclkhdr_263_io_clk), .io_en(rvclkhdr_263_io_en), .io_scan_mode(rvclkhdr_263_io_scan_mode) ); - rvclkhdr rvclkhdr_264 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_264 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_264_io_l1clk), .io_clk(rvclkhdr_264_io_clk), .io_en(rvclkhdr_264_io_en), .io_scan_mode(rvclkhdr_264_io_scan_mode) ); - rvclkhdr rvclkhdr_265 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_265 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_265_io_l1clk), .io_clk(rvclkhdr_265_io_clk), .io_en(rvclkhdr_265_io_en), .io_scan_mode(rvclkhdr_265_io_scan_mode) ); - rvclkhdr rvclkhdr_266 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_266 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_266_io_l1clk), .io_clk(rvclkhdr_266_io_clk), .io_en(rvclkhdr_266_io_en), .io_scan_mode(rvclkhdr_266_io_scan_mode) ); - rvclkhdr rvclkhdr_267 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_267 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_267_io_l1clk), .io_clk(rvclkhdr_267_io_clk), .io_en(rvclkhdr_267_io_en), .io_scan_mode(rvclkhdr_267_io_scan_mode) ); - rvclkhdr rvclkhdr_268 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_268 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_268_io_l1clk), .io_clk(rvclkhdr_268_io_clk), .io_en(rvclkhdr_268_io_en), .io_scan_mode(rvclkhdr_268_io_scan_mode) ); - rvclkhdr rvclkhdr_269 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_269 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_269_io_l1clk), .io_clk(rvclkhdr_269_io_clk), .io_en(rvclkhdr_269_io_en), .io_scan_mode(rvclkhdr_269_io_scan_mode) ); - rvclkhdr rvclkhdr_270 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_270 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_270_io_l1clk), .io_clk(rvclkhdr_270_io_clk), .io_en(rvclkhdr_270_io_en), .io_scan_mode(rvclkhdr_270_io_scan_mode) ); - rvclkhdr rvclkhdr_271 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_271 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_271_io_l1clk), .io_clk(rvclkhdr_271_io_clk), .io_en(rvclkhdr_271_io_en), .io_scan_mode(rvclkhdr_271_io_scan_mode) ); - rvclkhdr rvclkhdr_272 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_272 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_272_io_l1clk), .io_clk(rvclkhdr_272_io_clk), .io_en(rvclkhdr_272_io_en), .io_scan_mode(rvclkhdr_272_io_scan_mode) ); - rvclkhdr rvclkhdr_273 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_273 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_273_io_l1clk), .io_clk(rvclkhdr_273_io_clk), .io_en(rvclkhdr_273_io_en), .io_scan_mode(rvclkhdr_273_io_scan_mode) ); - rvclkhdr rvclkhdr_274 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_274 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_274_io_l1clk), .io_clk(rvclkhdr_274_io_clk), .io_en(rvclkhdr_274_io_en), .io_scan_mode(rvclkhdr_274_io_scan_mode) ); - rvclkhdr rvclkhdr_275 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_275 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_275_io_l1clk), .io_clk(rvclkhdr_275_io_clk), .io_en(rvclkhdr_275_io_en), .io_scan_mode(rvclkhdr_275_io_scan_mode) ); - rvclkhdr rvclkhdr_276 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_276 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_276_io_l1clk), .io_clk(rvclkhdr_276_io_clk), .io_en(rvclkhdr_276_io_en), .io_scan_mode(rvclkhdr_276_io_scan_mode) ); - rvclkhdr rvclkhdr_277 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_277 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_277_io_l1clk), .io_clk(rvclkhdr_277_io_clk), .io_en(rvclkhdr_277_io_en), .io_scan_mode(rvclkhdr_277_io_scan_mode) ); - rvclkhdr rvclkhdr_278 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_278 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_278_io_l1clk), .io_clk(rvclkhdr_278_io_clk), .io_en(rvclkhdr_278_io_en), .io_scan_mode(rvclkhdr_278_io_scan_mode) ); - rvclkhdr rvclkhdr_279 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_279 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_279_io_l1clk), .io_clk(rvclkhdr_279_io_clk), .io_en(rvclkhdr_279_io_en), .io_scan_mode(rvclkhdr_279_io_scan_mode) ); - rvclkhdr rvclkhdr_280 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_280 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_280_io_l1clk), .io_clk(rvclkhdr_280_io_clk), .io_en(rvclkhdr_280_io_en), .io_scan_mode(rvclkhdr_280_io_scan_mode) ); - rvclkhdr rvclkhdr_281 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_281 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_281_io_l1clk), .io_clk(rvclkhdr_281_io_clk), .io_en(rvclkhdr_281_io_en), .io_scan_mode(rvclkhdr_281_io_scan_mode) ); - rvclkhdr rvclkhdr_282 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_282 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_282_io_l1clk), .io_clk(rvclkhdr_282_io_clk), .io_en(rvclkhdr_282_io_en), .io_scan_mode(rvclkhdr_282_io_scan_mode) ); - rvclkhdr rvclkhdr_283 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_283 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_283_io_l1clk), .io_clk(rvclkhdr_283_io_clk), .io_en(rvclkhdr_283_io_en), .io_scan_mode(rvclkhdr_283_io_scan_mode) ); - rvclkhdr rvclkhdr_284 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_284 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_284_io_l1clk), .io_clk(rvclkhdr_284_io_clk), .io_en(rvclkhdr_284_io_en), .io_scan_mode(rvclkhdr_284_io_scan_mode) ); - rvclkhdr rvclkhdr_285 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_285 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_285_io_l1clk), .io_clk(rvclkhdr_285_io_clk), .io_en(rvclkhdr_285_io_en), .io_scan_mode(rvclkhdr_285_io_scan_mode) ); - rvclkhdr rvclkhdr_286 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_286 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_286_io_l1clk), .io_clk(rvclkhdr_286_io_clk), .io_en(rvclkhdr_286_io_en), .io_scan_mode(rvclkhdr_286_io_scan_mode) ); - rvclkhdr rvclkhdr_287 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_287 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_287_io_l1clk), .io_clk(rvclkhdr_287_io_clk), .io_en(rvclkhdr_287_io_en), .io_scan_mode(rvclkhdr_287_io_scan_mode) ); - rvclkhdr rvclkhdr_288 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_288 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_288_io_l1clk), .io_clk(rvclkhdr_288_io_clk), .io_en(rvclkhdr_288_io_en), .io_scan_mode(rvclkhdr_288_io_scan_mode) ); - rvclkhdr rvclkhdr_289 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_289 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_289_io_l1clk), .io_clk(rvclkhdr_289_io_clk), .io_en(rvclkhdr_289_io_en), .io_scan_mode(rvclkhdr_289_io_scan_mode) ); - rvclkhdr rvclkhdr_290 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_290 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_290_io_l1clk), .io_clk(rvclkhdr_290_io_clk), .io_en(rvclkhdr_290_io_en), .io_scan_mode(rvclkhdr_290_io_scan_mode) ); - rvclkhdr rvclkhdr_291 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_291 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_291_io_l1clk), .io_clk(rvclkhdr_291_io_clk), .io_en(rvclkhdr_291_io_en), .io_scan_mode(rvclkhdr_291_io_scan_mode) ); - rvclkhdr rvclkhdr_292 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_292 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_292_io_l1clk), .io_clk(rvclkhdr_292_io_clk), .io_en(rvclkhdr_292_io_en), .io_scan_mode(rvclkhdr_292_io_scan_mode) ); - rvclkhdr rvclkhdr_293 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_293 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_293_io_l1clk), .io_clk(rvclkhdr_293_io_clk), .io_en(rvclkhdr_293_io_en), .io_scan_mode(rvclkhdr_293_io_scan_mode) ); - rvclkhdr rvclkhdr_294 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_294 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_294_io_l1clk), .io_clk(rvclkhdr_294_io_clk), .io_en(rvclkhdr_294_io_en), .io_scan_mode(rvclkhdr_294_io_scan_mode) ); - rvclkhdr rvclkhdr_295 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_295 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_295_io_l1clk), .io_clk(rvclkhdr_295_io_clk), .io_en(rvclkhdr_295_io_en), .io_scan_mode(rvclkhdr_295_io_scan_mode) ); - rvclkhdr rvclkhdr_296 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_296 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_296_io_l1clk), .io_clk(rvclkhdr_296_io_clk), .io_en(rvclkhdr_296_io_en), .io_scan_mode(rvclkhdr_296_io_scan_mode) ); - rvclkhdr rvclkhdr_297 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_297 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_297_io_l1clk), .io_clk(rvclkhdr_297_io_clk), .io_en(rvclkhdr_297_io_en), .io_scan_mode(rvclkhdr_297_io_scan_mode) ); - rvclkhdr rvclkhdr_298 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_298 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_298_io_l1clk), .io_clk(rvclkhdr_298_io_clk), .io_en(rvclkhdr_298_io_en), .io_scan_mode(rvclkhdr_298_io_scan_mode) ); - rvclkhdr rvclkhdr_299 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_299 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_299_io_l1clk), .io_clk(rvclkhdr_299_io_clk), .io_en(rvclkhdr_299_io_en), .io_scan_mode(rvclkhdr_299_io_scan_mode) ); - rvclkhdr rvclkhdr_300 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_300 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_300_io_l1clk), .io_clk(rvclkhdr_300_io_clk), .io_en(rvclkhdr_300_io_en), .io_scan_mode(rvclkhdr_300_io_scan_mode) ); - rvclkhdr rvclkhdr_301 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_301 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_301_io_l1clk), .io_clk(rvclkhdr_301_io_clk), .io_en(rvclkhdr_301_io_en), .io_scan_mode(rvclkhdr_301_io_scan_mode) ); - rvclkhdr rvclkhdr_302 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_302 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_302_io_l1clk), .io_clk(rvclkhdr_302_io_clk), .io_en(rvclkhdr_302_io_en), .io_scan_mode(rvclkhdr_302_io_scan_mode) ); - rvclkhdr rvclkhdr_303 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_303 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_303_io_l1clk), .io_clk(rvclkhdr_303_io_clk), .io_en(rvclkhdr_303_io_en), .io_scan_mode(rvclkhdr_303_io_scan_mode) ); - rvclkhdr rvclkhdr_304 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_304 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_304_io_l1clk), .io_clk(rvclkhdr_304_io_clk), .io_en(rvclkhdr_304_io_en), .io_scan_mode(rvclkhdr_304_io_scan_mode) ); - rvclkhdr rvclkhdr_305 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_305 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_305_io_l1clk), .io_clk(rvclkhdr_305_io_clk), .io_en(rvclkhdr_305_io_en), .io_scan_mode(rvclkhdr_305_io_scan_mode) ); - rvclkhdr rvclkhdr_306 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_306 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_306_io_l1clk), .io_clk(rvclkhdr_306_io_clk), .io_en(rvclkhdr_306_io_en), .io_scan_mode(rvclkhdr_306_io_scan_mode) ); - rvclkhdr rvclkhdr_307 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_307 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_307_io_l1clk), .io_clk(rvclkhdr_307_io_clk), .io_en(rvclkhdr_307_io_en), .io_scan_mode(rvclkhdr_307_io_scan_mode) ); - rvclkhdr rvclkhdr_308 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_308 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_308_io_l1clk), .io_clk(rvclkhdr_308_io_clk), .io_en(rvclkhdr_308_io_en), .io_scan_mode(rvclkhdr_308_io_scan_mode) ); - rvclkhdr rvclkhdr_309 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_309 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_309_io_l1clk), .io_clk(rvclkhdr_309_io_clk), .io_en(rvclkhdr_309_io_en), .io_scan_mode(rvclkhdr_309_io_scan_mode) ); - rvclkhdr rvclkhdr_310 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_310 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_310_io_l1clk), .io_clk(rvclkhdr_310_io_clk), .io_en(rvclkhdr_310_io_en), .io_scan_mode(rvclkhdr_310_io_scan_mode) ); - rvclkhdr rvclkhdr_311 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_311 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_311_io_l1clk), .io_clk(rvclkhdr_311_io_clk), .io_en(rvclkhdr_311_io_en), .io_scan_mode(rvclkhdr_311_io_scan_mode) ); - rvclkhdr rvclkhdr_312 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_312 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_312_io_l1clk), .io_clk(rvclkhdr_312_io_clk), .io_en(rvclkhdr_312_io_en), .io_scan_mode(rvclkhdr_312_io_scan_mode) ); - rvclkhdr rvclkhdr_313 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_313 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_313_io_l1clk), .io_clk(rvclkhdr_313_io_clk), .io_en(rvclkhdr_313_io_en), .io_scan_mode(rvclkhdr_313_io_scan_mode) ); - rvclkhdr rvclkhdr_314 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_314 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_314_io_l1clk), .io_clk(rvclkhdr_314_io_clk), .io_en(rvclkhdr_314_io_en), .io_scan_mode(rvclkhdr_314_io_scan_mode) ); - rvclkhdr rvclkhdr_315 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_315 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_315_io_l1clk), .io_clk(rvclkhdr_315_io_clk), .io_en(rvclkhdr_315_io_en), .io_scan_mode(rvclkhdr_315_io_scan_mode) ); - rvclkhdr rvclkhdr_316 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_316 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_316_io_l1clk), .io_clk(rvclkhdr_316_io_clk), .io_en(rvclkhdr_316_io_en), .io_scan_mode(rvclkhdr_316_io_scan_mode) ); - rvclkhdr rvclkhdr_317 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_317 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_317_io_l1clk), .io_clk(rvclkhdr_317_io_clk), .io_en(rvclkhdr_317_io_en), .io_scan_mode(rvclkhdr_317_io_scan_mode) ); - rvclkhdr rvclkhdr_318 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_318 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_318_io_l1clk), .io_clk(rvclkhdr_318_io_clk), .io_en(rvclkhdr_318_io_en), .io_scan_mode(rvclkhdr_318_io_scan_mode) ); - rvclkhdr rvclkhdr_319 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_319 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_319_io_l1clk), .io_clk(rvclkhdr_319_io_clk), .io_en(rvclkhdr_319_io_en), .io_scan_mode(rvclkhdr_319_io_scan_mode) ); - rvclkhdr rvclkhdr_320 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_320 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_320_io_l1clk), .io_clk(rvclkhdr_320_io_clk), .io_en(rvclkhdr_320_io_en), .io_scan_mode(rvclkhdr_320_io_scan_mode) ); - rvclkhdr rvclkhdr_321 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_321 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_321_io_l1clk), .io_clk(rvclkhdr_321_io_clk), .io_en(rvclkhdr_321_io_en), .io_scan_mode(rvclkhdr_321_io_scan_mode) ); - rvclkhdr rvclkhdr_322 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_322 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_322_io_l1clk), .io_clk(rvclkhdr_322_io_clk), .io_en(rvclkhdr_322_io_en), .io_scan_mode(rvclkhdr_322_io_scan_mode) ); - rvclkhdr rvclkhdr_323 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_323 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_323_io_l1clk), .io_clk(rvclkhdr_323_io_clk), .io_en(rvclkhdr_323_io_en), .io_scan_mode(rvclkhdr_323_io_scan_mode) ); - rvclkhdr rvclkhdr_324 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_324 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_324_io_l1clk), .io_clk(rvclkhdr_324_io_clk), .io_en(rvclkhdr_324_io_en), .io_scan_mode(rvclkhdr_324_io_scan_mode) ); - rvclkhdr rvclkhdr_325 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_325 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_325_io_l1clk), .io_clk(rvclkhdr_325_io_clk), .io_en(rvclkhdr_325_io_en), .io_scan_mode(rvclkhdr_325_io_scan_mode) ); - rvclkhdr rvclkhdr_326 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_326 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_326_io_l1clk), .io_clk(rvclkhdr_326_io_clk), .io_en(rvclkhdr_326_io_en), .io_scan_mode(rvclkhdr_326_io_scan_mode) ); - rvclkhdr rvclkhdr_327 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_327 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_327_io_l1clk), .io_clk(rvclkhdr_327_io_clk), .io_en(rvclkhdr_327_io_en), .io_scan_mode(rvclkhdr_327_io_scan_mode) ); - rvclkhdr rvclkhdr_328 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_328 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_328_io_l1clk), .io_clk(rvclkhdr_328_io_clk), .io_en(rvclkhdr_328_io_en), .io_scan_mode(rvclkhdr_328_io_scan_mode) ); - rvclkhdr rvclkhdr_329 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_329 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_329_io_l1clk), .io_clk(rvclkhdr_329_io_clk), .io_en(rvclkhdr_329_io_en), .io_scan_mode(rvclkhdr_329_io_scan_mode) ); - rvclkhdr rvclkhdr_330 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_330 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_330_io_l1clk), .io_clk(rvclkhdr_330_io_clk), .io_en(rvclkhdr_330_io_en), .io_scan_mode(rvclkhdr_330_io_scan_mode) ); - rvclkhdr rvclkhdr_331 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_331 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_331_io_l1clk), .io_clk(rvclkhdr_331_io_clk), .io_en(rvclkhdr_331_io_en), .io_scan_mode(rvclkhdr_331_io_scan_mode) ); - rvclkhdr rvclkhdr_332 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_332 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_332_io_l1clk), .io_clk(rvclkhdr_332_io_clk), .io_en(rvclkhdr_332_io_en), .io_scan_mode(rvclkhdr_332_io_scan_mode) ); - rvclkhdr rvclkhdr_333 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_333 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_333_io_l1clk), .io_clk(rvclkhdr_333_io_clk), .io_en(rvclkhdr_333_io_en), .io_scan_mode(rvclkhdr_333_io_scan_mode) ); - rvclkhdr rvclkhdr_334 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_334 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_334_io_l1clk), .io_clk(rvclkhdr_334_io_clk), .io_en(rvclkhdr_334_io_en), .io_scan_mode(rvclkhdr_334_io_scan_mode) ); - rvclkhdr rvclkhdr_335 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_335 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_335_io_l1clk), .io_clk(rvclkhdr_335_io_clk), .io_en(rvclkhdr_335_io_en), .io_scan_mode(rvclkhdr_335_io_scan_mode) ); - rvclkhdr rvclkhdr_336 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_336 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_336_io_l1clk), .io_clk(rvclkhdr_336_io_clk), .io_en(rvclkhdr_336_io_en), .io_scan_mode(rvclkhdr_336_io_scan_mode) ); - rvclkhdr rvclkhdr_337 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_337 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_337_io_l1clk), .io_clk(rvclkhdr_337_io_clk), .io_en(rvclkhdr_337_io_en), .io_scan_mode(rvclkhdr_337_io_scan_mode) ); - rvclkhdr rvclkhdr_338 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_338 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_338_io_l1clk), .io_clk(rvclkhdr_338_io_clk), .io_en(rvclkhdr_338_io_en), .io_scan_mode(rvclkhdr_338_io_scan_mode) ); - rvclkhdr rvclkhdr_339 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_339 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_339_io_l1clk), .io_clk(rvclkhdr_339_io_clk), .io_en(rvclkhdr_339_io_en), .io_scan_mode(rvclkhdr_339_io_scan_mode) ); - rvclkhdr rvclkhdr_340 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_340 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_340_io_l1clk), .io_clk(rvclkhdr_340_io_clk), .io_en(rvclkhdr_340_io_en), .io_scan_mode(rvclkhdr_340_io_scan_mode) ); - rvclkhdr rvclkhdr_341 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_341 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_341_io_l1clk), .io_clk(rvclkhdr_341_io_clk), .io_en(rvclkhdr_341_io_en), .io_scan_mode(rvclkhdr_341_io_scan_mode) ); - rvclkhdr rvclkhdr_342 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_342 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_342_io_l1clk), .io_clk(rvclkhdr_342_io_clk), .io_en(rvclkhdr_342_io_en), .io_scan_mode(rvclkhdr_342_io_scan_mode) ); - rvclkhdr rvclkhdr_343 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_343 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_343_io_l1clk), .io_clk(rvclkhdr_343_io_clk), .io_en(rvclkhdr_343_io_en), .io_scan_mode(rvclkhdr_343_io_scan_mode) ); - rvclkhdr rvclkhdr_344 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_344 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_344_io_l1clk), .io_clk(rvclkhdr_344_io_clk), .io_en(rvclkhdr_344_io_en), .io_scan_mode(rvclkhdr_344_io_scan_mode) ); - rvclkhdr rvclkhdr_345 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_345 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_345_io_l1clk), .io_clk(rvclkhdr_345_io_clk), .io_en(rvclkhdr_345_io_en), .io_scan_mode(rvclkhdr_345_io_scan_mode) ); - rvclkhdr rvclkhdr_346 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_346 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_346_io_l1clk), .io_clk(rvclkhdr_346_io_clk), .io_en(rvclkhdr_346_io_en), .io_scan_mode(rvclkhdr_346_io_scan_mode) ); - rvclkhdr rvclkhdr_347 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_347 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_347_io_l1clk), .io_clk(rvclkhdr_347_io_clk), .io_en(rvclkhdr_347_io_en), .io_scan_mode(rvclkhdr_347_io_scan_mode) ); - rvclkhdr rvclkhdr_348 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_348 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_348_io_l1clk), .io_clk(rvclkhdr_348_io_clk), .io_en(rvclkhdr_348_io_en), .io_scan_mode(rvclkhdr_348_io_scan_mode) ); - rvclkhdr rvclkhdr_349 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_349 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_349_io_l1clk), .io_clk(rvclkhdr_349_io_clk), .io_en(rvclkhdr_349_io_en), .io_scan_mode(rvclkhdr_349_io_scan_mode) ); - rvclkhdr rvclkhdr_350 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_350 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_350_io_l1clk), .io_clk(rvclkhdr_350_io_clk), .io_en(rvclkhdr_350_io_en), .io_scan_mode(rvclkhdr_350_io_scan_mode) ); - rvclkhdr rvclkhdr_351 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_351 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_351_io_l1clk), .io_clk(rvclkhdr_351_io_clk), .io_en(rvclkhdr_351_io_en), .io_scan_mode(rvclkhdr_351_io_scan_mode) ); - rvclkhdr rvclkhdr_352 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_352 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_352_io_l1clk), .io_clk(rvclkhdr_352_io_clk), .io_en(rvclkhdr_352_io_en), .io_scan_mode(rvclkhdr_352_io_scan_mode) ); - rvclkhdr rvclkhdr_353 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_353 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_353_io_l1clk), .io_clk(rvclkhdr_353_io_clk), .io_en(rvclkhdr_353_io_en), .io_scan_mode(rvclkhdr_353_io_scan_mode) ); - rvclkhdr rvclkhdr_354 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_354 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_354_io_l1clk), .io_clk(rvclkhdr_354_io_clk), .io_en(rvclkhdr_354_io_en), .io_scan_mode(rvclkhdr_354_io_scan_mode) ); - rvclkhdr rvclkhdr_355 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_355 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_355_io_l1clk), .io_clk(rvclkhdr_355_io_clk), .io_en(rvclkhdr_355_io_en), .io_scan_mode(rvclkhdr_355_io_scan_mode) ); - rvclkhdr rvclkhdr_356 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_356 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_356_io_l1clk), .io_clk(rvclkhdr_356_io_clk), .io_en(rvclkhdr_356_io_en), .io_scan_mode(rvclkhdr_356_io_scan_mode) ); - rvclkhdr rvclkhdr_357 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_357 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_357_io_l1clk), .io_clk(rvclkhdr_357_io_clk), .io_en(rvclkhdr_357_io_en), .io_scan_mode(rvclkhdr_357_io_scan_mode) ); - rvclkhdr rvclkhdr_358 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_358 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_358_io_l1clk), .io_clk(rvclkhdr_358_io_clk), .io_en(rvclkhdr_358_io_en), .io_scan_mode(rvclkhdr_358_io_scan_mode) ); - rvclkhdr rvclkhdr_359 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_359 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_359_io_l1clk), .io_clk(rvclkhdr_359_io_clk), .io_en(rvclkhdr_359_io_en), .io_scan_mode(rvclkhdr_359_io_scan_mode) ); - rvclkhdr rvclkhdr_360 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_360 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_360_io_l1clk), .io_clk(rvclkhdr_360_io_clk), .io_en(rvclkhdr_360_io_en), .io_scan_mode(rvclkhdr_360_io_scan_mode) ); - rvclkhdr rvclkhdr_361 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_361 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_361_io_l1clk), .io_clk(rvclkhdr_361_io_clk), .io_en(rvclkhdr_361_io_en), .io_scan_mode(rvclkhdr_361_io_scan_mode) ); - rvclkhdr rvclkhdr_362 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_362 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_362_io_l1clk), .io_clk(rvclkhdr_362_io_clk), .io_en(rvclkhdr_362_io_en), .io_scan_mode(rvclkhdr_362_io_scan_mode) ); - rvclkhdr rvclkhdr_363 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_363 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_363_io_l1clk), .io_clk(rvclkhdr_363_io_clk), .io_en(rvclkhdr_363_io_en), .io_scan_mode(rvclkhdr_363_io_scan_mode) ); - rvclkhdr rvclkhdr_364 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_364 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_364_io_l1clk), .io_clk(rvclkhdr_364_io_clk), .io_en(rvclkhdr_364_io_en), .io_scan_mode(rvclkhdr_364_io_scan_mode) ); - rvclkhdr rvclkhdr_365 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_365 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_365_io_l1clk), .io_clk(rvclkhdr_365_io_clk), .io_en(rvclkhdr_365_io_en), .io_scan_mode(rvclkhdr_365_io_scan_mode) ); - rvclkhdr rvclkhdr_366 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_366 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_366_io_l1clk), .io_clk(rvclkhdr_366_io_clk), .io_en(rvclkhdr_366_io_en), .io_scan_mode(rvclkhdr_366_io_scan_mode) ); - rvclkhdr rvclkhdr_367 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_367 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_367_io_l1clk), .io_clk(rvclkhdr_367_io_clk), .io_en(rvclkhdr_367_io_en), .io_scan_mode(rvclkhdr_367_io_scan_mode) ); - rvclkhdr rvclkhdr_368 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_368 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_368_io_l1clk), .io_clk(rvclkhdr_368_io_clk), .io_en(rvclkhdr_368_io_en), .io_scan_mode(rvclkhdr_368_io_scan_mode) ); - rvclkhdr rvclkhdr_369 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_369 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_369_io_l1clk), .io_clk(rvclkhdr_369_io_clk), .io_en(rvclkhdr_369_io_en), .io_scan_mode(rvclkhdr_369_io_scan_mode) ); - rvclkhdr rvclkhdr_370 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_370 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_370_io_l1clk), .io_clk(rvclkhdr_370_io_clk), .io_en(rvclkhdr_370_io_en), .io_scan_mode(rvclkhdr_370_io_scan_mode) ); - rvclkhdr rvclkhdr_371 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_371 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_371_io_l1clk), .io_clk(rvclkhdr_371_io_clk), .io_en(rvclkhdr_371_io_en), .io_scan_mode(rvclkhdr_371_io_scan_mode) ); - rvclkhdr rvclkhdr_372 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_372 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_372_io_l1clk), .io_clk(rvclkhdr_372_io_clk), .io_en(rvclkhdr_372_io_en), .io_scan_mode(rvclkhdr_372_io_scan_mode) ); - rvclkhdr rvclkhdr_373 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_373 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_373_io_l1clk), .io_clk(rvclkhdr_373_io_clk), .io_en(rvclkhdr_373_io_en), .io_scan_mode(rvclkhdr_373_io_scan_mode) ); - rvclkhdr rvclkhdr_374 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_374 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_374_io_l1clk), .io_clk(rvclkhdr_374_io_clk), .io_en(rvclkhdr_374_io_en), .io_scan_mode(rvclkhdr_374_io_scan_mode) ); - rvclkhdr rvclkhdr_375 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_375 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_375_io_l1clk), .io_clk(rvclkhdr_375_io_clk), .io_en(rvclkhdr_375_io_en), .io_scan_mode(rvclkhdr_375_io_scan_mode) ); - rvclkhdr rvclkhdr_376 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_376 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_376_io_l1clk), .io_clk(rvclkhdr_376_io_clk), .io_en(rvclkhdr_376_io_en), .io_scan_mode(rvclkhdr_376_io_scan_mode) ); - rvclkhdr rvclkhdr_377 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_377 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_377_io_l1clk), .io_clk(rvclkhdr_377_io_clk), .io_en(rvclkhdr_377_io_en), .io_scan_mode(rvclkhdr_377_io_scan_mode) ); - rvclkhdr rvclkhdr_378 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_378 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_378_io_l1clk), .io_clk(rvclkhdr_378_io_clk), .io_en(rvclkhdr_378_io_en), .io_scan_mode(rvclkhdr_378_io_scan_mode) ); - rvclkhdr rvclkhdr_379 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_379 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_379_io_l1clk), .io_clk(rvclkhdr_379_io_clk), .io_en(rvclkhdr_379_io_en), .io_scan_mode(rvclkhdr_379_io_scan_mode) ); - rvclkhdr rvclkhdr_380 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_380 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_380_io_l1clk), .io_clk(rvclkhdr_380_io_clk), .io_en(rvclkhdr_380_io_en), .io_scan_mode(rvclkhdr_380_io_scan_mode) ); - rvclkhdr rvclkhdr_381 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_381 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_381_io_l1clk), .io_clk(rvclkhdr_381_io_clk), .io_en(rvclkhdr_381_io_en), .io_scan_mode(rvclkhdr_381_io_scan_mode) ); - rvclkhdr rvclkhdr_382 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_382 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_382_io_l1clk), .io_clk(rvclkhdr_382_io_clk), .io_en(rvclkhdr_382_io_en), .io_scan_mode(rvclkhdr_382_io_scan_mode) ); - rvclkhdr rvclkhdr_383 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_383 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_383_io_l1clk), .io_clk(rvclkhdr_383_io_clk), .io_en(rvclkhdr_383_io_en), .io_scan_mode(rvclkhdr_383_io_scan_mode) ); - rvclkhdr rvclkhdr_384 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_384 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_384_io_l1clk), .io_clk(rvclkhdr_384_io_clk), .io_en(rvclkhdr_384_io_en), .io_scan_mode(rvclkhdr_384_io_scan_mode) ); - rvclkhdr rvclkhdr_385 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_385 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_385_io_l1clk), .io_clk(rvclkhdr_385_io_clk), .io_en(rvclkhdr_385_io_en), .io_scan_mode(rvclkhdr_385_io_scan_mode) ); - rvclkhdr rvclkhdr_386 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_386 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_386_io_l1clk), .io_clk(rvclkhdr_386_io_clk), .io_en(rvclkhdr_386_io_en), .io_scan_mode(rvclkhdr_386_io_scan_mode) ); - rvclkhdr rvclkhdr_387 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_387 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_387_io_l1clk), .io_clk(rvclkhdr_387_io_clk), .io_en(rvclkhdr_387_io_en), .io_scan_mode(rvclkhdr_387_io_scan_mode) ); - rvclkhdr rvclkhdr_388 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_388 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_388_io_l1clk), .io_clk(rvclkhdr_388_io_clk), .io_en(rvclkhdr_388_io_en), .io_scan_mode(rvclkhdr_388_io_scan_mode) ); - rvclkhdr rvclkhdr_389 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_389 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_389_io_l1clk), .io_clk(rvclkhdr_389_io_clk), .io_en(rvclkhdr_389_io_en), .io_scan_mode(rvclkhdr_389_io_scan_mode) ); - rvclkhdr rvclkhdr_390 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_390 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_390_io_l1clk), .io_clk(rvclkhdr_390_io_clk), .io_en(rvclkhdr_390_io_en), .io_scan_mode(rvclkhdr_390_io_scan_mode) ); - rvclkhdr rvclkhdr_391 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_391 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_391_io_l1clk), .io_clk(rvclkhdr_391_io_clk), .io_en(rvclkhdr_391_io_en), .io_scan_mode(rvclkhdr_391_io_scan_mode) ); - rvclkhdr rvclkhdr_392 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_392 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_392_io_l1clk), .io_clk(rvclkhdr_392_io_clk), .io_en(rvclkhdr_392_io_en), .io_scan_mode(rvclkhdr_392_io_scan_mode) ); - rvclkhdr rvclkhdr_393 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_393 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_393_io_l1clk), .io_clk(rvclkhdr_393_io_clk), .io_en(rvclkhdr_393_io_en), .io_scan_mode(rvclkhdr_393_io_scan_mode) ); - rvclkhdr rvclkhdr_394 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_394 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_394_io_l1clk), .io_clk(rvclkhdr_394_io_clk), .io_en(rvclkhdr_394_io_en), .io_scan_mode(rvclkhdr_394_io_scan_mode) ); - rvclkhdr rvclkhdr_395 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_395 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_395_io_l1clk), .io_clk(rvclkhdr_395_io_clk), .io_en(rvclkhdr_395_io_en), .io_scan_mode(rvclkhdr_395_io_scan_mode) ); - rvclkhdr rvclkhdr_396 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_396 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_396_io_l1clk), .io_clk(rvclkhdr_396_io_clk), .io_en(rvclkhdr_396_io_en), .io_scan_mode(rvclkhdr_396_io_scan_mode) ); - rvclkhdr rvclkhdr_397 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_397 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_397_io_l1clk), .io_clk(rvclkhdr_397_io_clk), .io_en(rvclkhdr_397_io_en), .io_scan_mode(rvclkhdr_397_io_scan_mode) ); - rvclkhdr rvclkhdr_398 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_398 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_398_io_l1clk), .io_clk(rvclkhdr_398_io_clk), .io_en(rvclkhdr_398_io_en), .io_scan_mode(rvclkhdr_398_io_scan_mode) ); - rvclkhdr rvclkhdr_399 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_399 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_399_io_l1clk), .io_clk(rvclkhdr_399_io_clk), .io_en(rvclkhdr_399_io_en), .io_scan_mode(rvclkhdr_399_io_scan_mode) ); - rvclkhdr rvclkhdr_400 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_400 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_400_io_l1clk), .io_clk(rvclkhdr_400_io_clk), .io_en(rvclkhdr_400_io_en), .io_scan_mode(rvclkhdr_400_io_scan_mode) ); - rvclkhdr rvclkhdr_401 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_401 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_401_io_l1clk), .io_clk(rvclkhdr_401_io_clk), .io_en(rvclkhdr_401_io_en), .io_scan_mode(rvclkhdr_401_io_scan_mode) ); - rvclkhdr rvclkhdr_402 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_402 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_402_io_l1clk), .io_clk(rvclkhdr_402_io_clk), .io_en(rvclkhdr_402_io_en), .io_scan_mode(rvclkhdr_402_io_scan_mode) ); - rvclkhdr rvclkhdr_403 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_403 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_403_io_l1clk), .io_clk(rvclkhdr_403_io_clk), .io_en(rvclkhdr_403_io_en), .io_scan_mode(rvclkhdr_403_io_scan_mode) ); - rvclkhdr rvclkhdr_404 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_404 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_404_io_l1clk), .io_clk(rvclkhdr_404_io_clk), .io_en(rvclkhdr_404_io_en), .io_scan_mode(rvclkhdr_404_io_scan_mode) ); - rvclkhdr rvclkhdr_405 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_405 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_405_io_l1clk), .io_clk(rvclkhdr_405_io_clk), .io_en(rvclkhdr_405_io_en), .io_scan_mode(rvclkhdr_405_io_scan_mode) ); - rvclkhdr rvclkhdr_406 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_406 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_406_io_l1clk), .io_clk(rvclkhdr_406_io_clk), .io_en(rvclkhdr_406_io_en), .io_scan_mode(rvclkhdr_406_io_scan_mode) ); - rvclkhdr rvclkhdr_407 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_407 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_407_io_l1clk), .io_clk(rvclkhdr_407_io_clk), .io_en(rvclkhdr_407_io_en), .io_scan_mode(rvclkhdr_407_io_scan_mode) ); - rvclkhdr rvclkhdr_408 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_408 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_408_io_l1clk), .io_clk(rvclkhdr_408_io_clk), .io_en(rvclkhdr_408_io_en), .io_scan_mode(rvclkhdr_408_io_scan_mode) ); - rvclkhdr rvclkhdr_409 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_409 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_409_io_l1clk), .io_clk(rvclkhdr_409_io_clk), .io_en(rvclkhdr_409_io_en), .io_scan_mode(rvclkhdr_409_io_scan_mode) ); - rvclkhdr rvclkhdr_410 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_410 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_410_io_l1clk), .io_clk(rvclkhdr_410_io_clk), .io_en(rvclkhdr_410_io_en), .io_scan_mode(rvclkhdr_410_io_scan_mode) ); - rvclkhdr rvclkhdr_411 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_411 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_411_io_l1clk), .io_clk(rvclkhdr_411_io_clk), .io_en(rvclkhdr_411_io_en), .io_scan_mode(rvclkhdr_411_io_scan_mode) ); - rvclkhdr rvclkhdr_412 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_412 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_412_io_l1clk), .io_clk(rvclkhdr_412_io_clk), .io_en(rvclkhdr_412_io_en), .io_scan_mode(rvclkhdr_412_io_scan_mode) ); - rvclkhdr rvclkhdr_413 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_413 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_413_io_l1clk), .io_clk(rvclkhdr_413_io_clk), .io_en(rvclkhdr_413_io_en), .io_scan_mode(rvclkhdr_413_io_scan_mode) ); - rvclkhdr rvclkhdr_414 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_414 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_414_io_l1clk), .io_clk(rvclkhdr_414_io_clk), .io_en(rvclkhdr_414_io_en), .io_scan_mode(rvclkhdr_414_io_scan_mode) ); - rvclkhdr rvclkhdr_415 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_415 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_415_io_l1clk), .io_clk(rvclkhdr_415_io_clk), .io_en(rvclkhdr_415_io_en), .io_scan_mode(rvclkhdr_415_io_scan_mode) ); - rvclkhdr rvclkhdr_416 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_416 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_416_io_l1clk), .io_clk(rvclkhdr_416_io_clk), .io_en(rvclkhdr_416_io_en), .io_scan_mode(rvclkhdr_416_io_scan_mode) ); - rvclkhdr rvclkhdr_417 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_417 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_417_io_l1clk), .io_clk(rvclkhdr_417_io_clk), .io_en(rvclkhdr_417_io_en), .io_scan_mode(rvclkhdr_417_io_scan_mode) ); - rvclkhdr rvclkhdr_418 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_418 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_418_io_l1clk), .io_clk(rvclkhdr_418_io_clk), .io_en(rvclkhdr_418_io_en), .io_scan_mode(rvclkhdr_418_io_scan_mode) ); - rvclkhdr rvclkhdr_419 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_419 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_419_io_l1clk), .io_clk(rvclkhdr_419_io_clk), .io_en(rvclkhdr_419_io_en), .io_scan_mode(rvclkhdr_419_io_scan_mode) ); - rvclkhdr rvclkhdr_420 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_420 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_420_io_l1clk), .io_clk(rvclkhdr_420_io_clk), .io_en(rvclkhdr_420_io_en), .io_scan_mode(rvclkhdr_420_io_scan_mode) ); - rvclkhdr rvclkhdr_421 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_421 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_421_io_l1clk), .io_clk(rvclkhdr_421_io_clk), .io_en(rvclkhdr_421_io_en), .io_scan_mode(rvclkhdr_421_io_scan_mode) ); - rvclkhdr rvclkhdr_422 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_422 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_422_io_l1clk), .io_clk(rvclkhdr_422_io_clk), .io_en(rvclkhdr_422_io_en), .io_scan_mode(rvclkhdr_422_io_scan_mode) ); - rvclkhdr rvclkhdr_423 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_423 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_423_io_l1clk), .io_clk(rvclkhdr_423_io_clk), .io_en(rvclkhdr_423_io_en), .io_scan_mode(rvclkhdr_423_io_scan_mode) ); - rvclkhdr rvclkhdr_424 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_424 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_424_io_l1clk), .io_clk(rvclkhdr_424_io_clk), .io_en(rvclkhdr_424_io_en), .io_scan_mode(rvclkhdr_424_io_scan_mode) ); - rvclkhdr rvclkhdr_425 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_425 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_425_io_l1clk), .io_clk(rvclkhdr_425_io_clk), .io_en(rvclkhdr_425_io_en), .io_scan_mode(rvclkhdr_425_io_scan_mode) ); - rvclkhdr rvclkhdr_426 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_426 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_426_io_l1clk), .io_clk(rvclkhdr_426_io_clk), .io_en(rvclkhdr_426_io_en), .io_scan_mode(rvclkhdr_426_io_scan_mode) ); - rvclkhdr rvclkhdr_427 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_427 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_427_io_l1clk), .io_clk(rvclkhdr_427_io_clk), .io_en(rvclkhdr_427_io_en), .io_scan_mode(rvclkhdr_427_io_scan_mode) ); - rvclkhdr rvclkhdr_428 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_428 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_428_io_l1clk), .io_clk(rvclkhdr_428_io_clk), .io_en(rvclkhdr_428_io_en), .io_scan_mode(rvclkhdr_428_io_scan_mode) ); - rvclkhdr rvclkhdr_429 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_429 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_429_io_l1clk), .io_clk(rvclkhdr_429_io_clk), .io_en(rvclkhdr_429_io_en), .io_scan_mode(rvclkhdr_429_io_scan_mode) ); - rvclkhdr rvclkhdr_430 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_430 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_430_io_l1clk), .io_clk(rvclkhdr_430_io_clk), .io_en(rvclkhdr_430_io_en), .io_scan_mode(rvclkhdr_430_io_scan_mode) ); - rvclkhdr rvclkhdr_431 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_431 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_431_io_l1clk), .io_clk(rvclkhdr_431_io_clk), .io_en(rvclkhdr_431_io_en), .io_scan_mode(rvclkhdr_431_io_scan_mode) ); - rvclkhdr rvclkhdr_432 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_432 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_432_io_l1clk), .io_clk(rvclkhdr_432_io_clk), .io_en(rvclkhdr_432_io_en), .io_scan_mode(rvclkhdr_432_io_scan_mode) ); - rvclkhdr rvclkhdr_433 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_433 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_433_io_l1clk), .io_clk(rvclkhdr_433_io_clk), .io_en(rvclkhdr_433_io_en), .io_scan_mode(rvclkhdr_433_io_scan_mode) ); - rvclkhdr rvclkhdr_434 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_434 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_434_io_l1clk), .io_clk(rvclkhdr_434_io_clk), .io_en(rvclkhdr_434_io_en), .io_scan_mode(rvclkhdr_434_io_scan_mode) ); - rvclkhdr rvclkhdr_435 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_435 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_435_io_l1clk), .io_clk(rvclkhdr_435_io_clk), .io_en(rvclkhdr_435_io_en), .io_scan_mode(rvclkhdr_435_io_scan_mode) ); - rvclkhdr rvclkhdr_436 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_436 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_436_io_l1clk), .io_clk(rvclkhdr_436_io_clk), .io_en(rvclkhdr_436_io_en), .io_scan_mode(rvclkhdr_436_io_scan_mode) ); - rvclkhdr rvclkhdr_437 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_437 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_437_io_l1clk), .io_clk(rvclkhdr_437_io_clk), .io_en(rvclkhdr_437_io_en), .io_scan_mode(rvclkhdr_437_io_scan_mode) ); - rvclkhdr rvclkhdr_438 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_438 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_438_io_l1clk), .io_clk(rvclkhdr_438_io_clk), .io_en(rvclkhdr_438_io_en), .io_scan_mode(rvclkhdr_438_io_scan_mode) ); - rvclkhdr rvclkhdr_439 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_439 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_439_io_l1clk), .io_clk(rvclkhdr_439_io_clk), .io_en(rvclkhdr_439_io_en), .io_scan_mode(rvclkhdr_439_io_scan_mode) ); - rvclkhdr rvclkhdr_440 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_440 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_440_io_l1clk), .io_clk(rvclkhdr_440_io_clk), .io_en(rvclkhdr_440_io_en), .io_scan_mode(rvclkhdr_440_io_scan_mode) ); - rvclkhdr rvclkhdr_441 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_441 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_441_io_l1clk), .io_clk(rvclkhdr_441_io_clk), .io_en(rvclkhdr_441_io_en), .io_scan_mode(rvclkhdr_441_io_scan_mode) ); - rvclkhdr rvclkhdr_442 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_442 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_442_io_l1clk), .io_clk(rvclkhdr_442_io_clk), .io_en(rvclkhdr_442_io_en), .io_scan_mode(rvclkhdr_442_io_scan_mode) ); - rvclkhdr rvclkhdr_443 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_443 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_443_io_l1clk), .io_clk(rvclkhdr_443_io_clk), .io_en(rvclkhdr_443_io_en), .io_scan_mode(rvclkhdr_443_io_scan_mode) ); - rvclkhdr rvclkhdr_444 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_444 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_444_io_l1clk), .io_clk(rvclkhdr_444_io_clk), .io_en(rvclkhdr_444_io_en), .io_scan_mode(rvclkhdr_444_io_scan_mode) ); - rvclkhdr rvclkhdr_445 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_445 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_445_io_l1clk), .io_clk(rvclkhdr_445_io_clk), .io_en(rvclkhdr_445_io_en), .io_scan_mode(rvclkhdr_445_io_scan_mode) ); - rvclkhdr rvclkhdr_446 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_446 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_446_io_l1clk), .io_clk(rvclkhdr_446_io_clk), .io_en(rvclkhdr_446_io_en), .io_scan_mode(rvclkhdr_446_io_scan_mode) ); - rvclkhdr rvclkhdr_447 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_447 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_447_io_l1clk), .io_clk(rvclkhdr_447_io_clk), .io_en(rvclkhdr_447_io_en), .io_scan_mode(rvclkhdr_447_io_scan_mode) ); - rvclkhdr rvclkhdr_448 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_448 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_448_io_l1clk), .io_clk(rvclkhdr_448_io_clk), .io_en(rvclkhdr_448_io_en), .io_scan_mode(rvclkhdr_448_io_scan_mode) ); - rvclkhdr rvclkhdr_449 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_449 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_449_io_l1clk), .io_clk(rvclkhdr_449_io_clk), .io_en(rvclkhdr_449_io_en), .io_scan_mode(rvclkhdr_449_io_scan_mode) ); - rvclkhdr rvclkhdr_450 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_450 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_450_io_l1clk), .io_clk(rvclkhdr_450_io_clk), .io_en(rvclkhdr_450_io_en), .io_scan_mode(rvclkhdr_450_io_scan_mode) ); - rvclkhdr rvclkhdr_451 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_451 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_451_io_l1clk), .io_clk(rvclkhdr_451_io_clk), .io_en(rvclkhdr_451_io_en), .io_scan_mode(rvclkhdr_451_io_scan_mode) ); - rvclkhdr rvclkhdr_452 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_452 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_452_io_l1clk), .io_clk(rvclkhdr_452_io_clk), .io_en(rvclkhdr_452_io_en), .io_scan_mode(rvclkhdr_452_io_scan_mode) ); - rvclkhdr rvclkhdr_453 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_453 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_453_io_l1clk), .io_clk(rvclkhdr_453_io_clk), .io_en(rvclkhdr_453_io_en), .io_scan_mode(rvclkhdr_453_io_scan_mode) ); - rvclkhdr rvclkhdr_454 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_454 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_454_io_l1clk), .io_clk(rvclkhdr_454_io_clk), .io_en(rvclkhdr_454_io_en), .io_scan_mode(rvclkhdr_454_io_scan_mode) ); - rvclkhdr rvclkhdr_455 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_455 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_455_io_l1clk), .io_clk(rvclkhdr_455_io_clk), .io_en(rvclkhdr_455_io_en), .io_scan_mode(rvclkhdr_455_io_scan_mode) ); - rvclkhdr rvclkhdr_456 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_456 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_456_io_l1clk), .io_clk(rvclkhdr_456_io_clk), .io_en(rvclkhdr_456_io_en), .io_scan_mode(rvclkhdr_456_io_scan_mode) ); - rvclkhdr rvclkhdr_457 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_457 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_457_io_l1clk), .io_clk(rvclkhdr_457_io_clk), .io_en(rvclkhdr_457_io_en), .io_scan_mode(rvclkhdr_457_io_scan_mode) ); - rvclkhdr rvclkhdr_458 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_458 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_458_io_l1clk), .io_clk(rvclkhdr_458_io_clk), .io_en(rvclkhdr_458_io_en), .io_scan_mode(rvclkhdr_458_io_scan_mode) ); - rvclkhdr rvclkhdr_459 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_459 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_459_io_l1clk), .io_clk(rvclkhdr_459_io_clk), .io_en(rvclkhdr_459_io_en), .io_scan_mode(rvclkhdr_459_io_scan_mode) ); - rvclkhdr rvclkhdr_460 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_460 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_460_io_l1clk), .io_clk(rvclkhdr_460_io_clk), .io_en(rvclkhdr_460_io_en), .io_scan_mode(rvclkhdr_460_io_scan_mode) ); - rvclkhdr rvclkhdr_461 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_461 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_461_io_l1clk), .io_clk(rvclkhdr_461_io_clk), .io_en(rvclkhdr_461_io_en), .io_scan_mode(rvclkhdr_461_io_scan_mode) ); - rvclkhdr rvclkhdr_462 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_462 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_462_io_l1clk), .io_clk(rvclkhdr_462_io_clk), .io_en(rvclkhdr_462_io_en), .io_scan_mode(rvclkhdr_462_io_scan_mode) ); - rvclkhdr rvclkhdr_463 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_463 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_463_io_l1clk), .io_clk(rvclkhdr_463_io_clk), .io_en(rvclkhdr_463_io_en), .io_scan_mode(rvclkhdr_463_io_scan_mode) ); - rvclkhdr rvclkhdr_464 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_464 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_464_io_l1clk), .io_clk(rvclkhdr_464_io_clk), .io_en(rvclkhdr_464_io_en), .io_scan_mode(rvclkhdr_464_io_scan_mode) ); - rvclkhdr rvclkhdr_465 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_465 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_465_io_l1clk), .io_clk(rvclkhdr_465_io_clk), .io_en(rvclkhdr_465_io_en), .io_scan_mode(rvclkhdr_465_io_scan_mode) ); - rvclkhdr rvclkhdr_466 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_466 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_466_io_l1clk), .io_clk(rvclkhdr_466_io_clk), .io_en(rvclkhdr_466_io_en), .io_scan_mode(rvclkhdr_466_io_scan_mode) ); - rvclkhdr rvclkhdr_467 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_467 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_467_io_l1clk), .io_clk(rvclkhdr_467_io_clk), .io_en(rvclkhdr_467_io_en), .io_scan_mode(rvclkhdr_467_io_scan_mode) ); - rvclkhdr rvclkhdr_468 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_468 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_468_io_l1clk), .io_clk(rvclkhdr_468_io_clk), .io_en(rvclkhdr_468_io_en), .io_scan_mode(rvclkhdr_468_io_scan_mode) ); - rvclkhdr rvclkhdr_469 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_469 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_469_io_l1clk), .io_clk(rvclkhdr_469_io_clk), .io_en(rvclkhdr_469_io_en), .io_scan_mode(rvclkhdr_469_io_scan_mode) ); - rvclkhdr rvclkhdr_470 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_470 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_470_io_l1clk), .io_clk(rvclkhdr_470_io_clk), .io_en(rvclkhdr_470_io_en), .io_scan_mode(rvclkhdr_470_io_scan_mode) ); - rvclkhdr rvclkhdr_471 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_471 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_471_io_l1clk), .io_clk(rvclkhdr_471_io_clk), .io_en(rvclkhdr_471_io_en), .io_scan_mode(rvclkhdr_471_io_scan_mode) ); - rvclkhdr rvclkhdr_472 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_472 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_472_io_l1clk), .io_clk(rvclkhdr_472_io_clk), .io_en(rvclkhdr_472_io_en), .io_scan_mode(rvclkhdr_472_io_scan_mode) ); - rvclkhdr rvclkhdr_473 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_473 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_473_io_l1clk), .io_clk(rvclkhdr_473_io_clk), .io_en(rvclkhdr_473_io_en), .io_scan_mode(rvclkhdr_473_io_scan_mode) ); - rvclkhdr rvclkhdr_474 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_474 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_474_io_l1clk), .io_clk(rvclkhdr_474_io_clk), .io_en(rvclkhdr_474_io_en), .io_scan_mode(rvclkhdr_474_io_scan_mode) ); - rvclkhdr rvclkhdr_475 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_475 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_475_io_l1clk), .io_clk(rvclkhdr_475_io_clk), .io_en(rvclkhdr_475_io_en), .io_scan_mode(rvclkhdr_475_io_scan_mode) ); - rvclkhdr rvclkhdr_476 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_476 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_476_io_l1clk), .io_clk(rvclkhdr_476_io_clk), .io_en(rvclkhdr_476_io_en), .io_scan_mode(rvclkhdr_476_io_scan_mode) ); - rvclkhdr rvclkhdr_477 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_477 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_477_io_l1clk), .io_clk(rvclkhdr_477_io_clk), .io_en(rvclkhdr_477_io_en), .io_scan_mode(rvclkhdr_477_io_scan_mode) ); - rvclkhdr rvclkhdr_478 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_478 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_478_io_l1clk), .io_clk(rvclkhdr_478_io_clk), .io_en(rvclkhdr_478_io_en), .io_scan_mode(rvclkhdr_478_io_scan_mode) ); - rvclkhdr rvclkhdr_479 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_479 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_479_io_l1clk), .io_clk(rvclkhdr_479_io_clk), .io_en(rvclkhdr_479_io_en), .io_scan_mode(rvclkhdr_479_io_scan_mode) ); - rvclkhdr rvclkhdr_480 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_480 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_480_io_l1clk), .io_clk(rvclkhdr_480_io_clk), .io_en(rvclkhdr_480_io_en), .io_scan_mode(rvclkhdr_480_io_scan_mode) ); - rvclkhdr rvclkhdr_481 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_481 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_481_io_l1clk), .io_clk(rvclkhdr_481_io_clk), .io_en(rvclkhdr_481_io_en), .io_scan_mode(rvclkhdr_481_io_scan_mode) ); - rvclkhdr rvclkhdr_482 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_482 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_482_io_l1clk), .io_clk(rvclkhdr_482_io_clk), .io_en(rvclkhdr_482_io_en), .io_scan_mode(rvclkhdr_482_io_scan_mode) ); - rvclkhdr rvclkhdr_483 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_483 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_483_io_l1clk), .io_clk(rvclkhdr_483_io_clk), .io_en(rvclkhdr_483_io_en), .io_scan_mode(rvclkhdr_483_io_scan_mode) ); - rvclkhdr rvclkhdr_484 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_484 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_484_io_l1clk), .io_clk(rvclkhdr_484_io_clk), .io_en(rvclkhdr_484_io_en), .io_scan_mode(rvclkhdr_484_io_scan_mode) ); - rvclkhdr rvclkhdr_485 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_485 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_485_io_l1clk), .io_clk(rvclkhdr_485_io_clk), .io_en(rvclkhdr_485_io_en), .io_scan_mode(rvclkhdr_485_io_scan_mode) ); - rvclkhdr rvclkhdr_486 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_486 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_486_io_l1clk), .io_clk(rvclkhdr_486_io_clk), .io_en(rvclkhdr_486_io_en), .io_scan_mode(rvclkhdr_486_io_scan_mode) ); - rvclkhdr rvclkhdr_487 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_487 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_487_io_l1clk), .io_clk(rvclkhdr_487_io_clk), .io_en(rvclkhdr_487_io_en), .io_scan_mode(rvclkhdr_487_io_scan_mode) ); - rvclkhdr rvclkhdr_488 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_488 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_488_io_l1clk), .io_clk(rvclkhdr_488_io_clk), .io_en(rvclkhdr_488_io_en), .io_scan_mode(rvclkhdr_488_io_scan_mode) ); - rvclkhdr rvclkhdr_489 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_489 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_489_io_l1clk), .io_clk(rvclkhdr_489_io_clk), .io_en(rvclkhdr_489_io_en), .io_scan_mode(rvclkhdr_489_io_scan_mode) ); - rvclkhdr rvclkhdr_490 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_490 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_490_io_l1clk), .io_clk(rvclkhdr_490_io_clk), .io_en(rvclkhdr_490_io_en), .io_scan_mode(rvclkhdr_490_io_scan_mode) ); - rvclkhdr rvclkhdr_491 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_491 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_491_io_l1clk), .io_clk(rvclkhdr_491_io_clk), .io_en(rvclkhdr_491_io_en), .io_scan_mode(rvclkhdr_491_io_scan_mode) ); - rvclkhdr rvclkhdr_492 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_492 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_492_io_l1clk), .io_clk(rvclkhdr_492_io_clk), .io_en(rvclkhdr_492_io_en), .io_scan_mode(rvclkhdr_492_io_scan_mode) ); - rvclkhdr rvclkhdr_493 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_493 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_493_io_l1clk), .io_clk(rvclkhdr_493_io_clk), .io_en(rvclkhdr_493_io_en), .io_scan_mode(rvclkhdr_493_io_scan_mode) ); - rvclkhdr rvclkhdr_494 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_494 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_494_io_l1clk), .io_clk(rvclkhdr_494_io_clk), .io_en(rvclkhdr_494_io_en), .io_scan_mode(rvclkhdr_494_io_scan_mode) ); - rvclkhdr rvclkhdr_495 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_495 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_495_io_l1clk), .io_clk(rvclkhdr_495_io_clk), .io_en(rvclkhdr_495_io_en), .io_scan_mode(rvclkhdr_495_io_scan_mode) ); - rvclkhdr rvclkhdr_496 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_496 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_496_io_l1clk), .io_clk(rvclkhdr_496_io_clk), .io_en(rvclkhdr_496_io_en), .io_scan_mode(rvclkhdr_496_io_scan_mode) ); - rvclkhdr rvclkhdr_497 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_497 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_497_io_l1clk), .io_clk(rvclkhdr_497_io_clk), .io_en(rvclkhdr_497_io_en), .io_scan_mode(rvclkhdr_497_io_scan_mode) ); - rvclkhdr rvclkhdr_498 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_498 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_498_io_l1clk), .io_clk(rvclkhdr_498_io_clk), .io_en(rvclkhdr_498_io_en), .io_scan_mode(rvclkhdr_498_io_scan_mode) ); - rvclkhdr rvclkhdr_499 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_499 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_499_io_l1clk), .io_clk(rvclkhdr_499_io_clk), .io_en(rvclkhdr_499_io_en), .io_scan_mode(rvclkhdr_499_io_scan_mode) ); - rvclkhdr rvclkhdr_500 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_500 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_500_io_l1clk), .io_clk(rvclkhdr_500_io_clk), .io_en(rvclkhdr_500_io_en), .io_scan_mode(rvclkhdr_500_io_scan_mode) ); - rvclkhdr rvclkhdr_501 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_501 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_501_io_l1clk), .io_clk(rvclkhdr_501_io_clk), .io_en(rvclkhdr_501_io_en), .io_scan_mode(rvclkhdr_501_io_scan_mode) ); - rvclkhdr rvclkhdr_502 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_502 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_502_io_l1clk), .io_clk(rvclkhdr_502_io_clk), .io_en(rvclkhdr_502_io_en), .io_scan_mode(rvclkhdr_502_io_scan_mode) ); - rvclkhdr rvclkhdr_503 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_503 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_503_io_l1clk), .io_clk(rvclkhdr_503_io_clk), .io_en(rvclkhdr_503_io_en), .io_scan_mode(rvclkhdr_503_io_scan_mode) ); - rvclkhdr rvclkhdr_504 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_504 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_504_io_l1clk), .io_clk(rvclkhdr_504_io_clk), .io_en(rvclkhdr_504_io_en), .io_scan_mode(rvclkhdr_504_io_scan_mode) ); - rvclkhdr rvclkhdr_505 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_505 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_505_io_l1clk), .io_clk(rvclkhdr_505_io_clk), .io_en(rvclkhdr_505_io_en), .io_scan_mode(rvclkhdr_505_io_scan_mode) ); - rvclkhdr rvclkhdr_506 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_506 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_506_io_l1clk), .io_clk(rvclkhdr_506_io_clk), .io_en(rvclkhdr_506_io_en), .io_scan_mode(rvclkhdr_506_io_scan_mode) ); - rvclkhdr rvclkhdr_507 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_507 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_507_io_l1clk), .io_clk(rvclkhdr_507_io_clk), .io_en(rvclkhdr_507_io_en), .io_scan_mode(rvclkhdr_507_io_scan_mode) ); - rvclkhdr rvclkhdr_508 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_508 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_508_io_l1clk), .io_clk(rvclkhdr_508_io_clk), .io_en(rvclkhdr_508_io_en), .io_scan_mode(rvclkhdr_508_io_scan_mode) ); - rvclkhdr rvclkhdr_509 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_509 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_509_io_l1clk), .io_clk(rvclkhdr_509_io_clk), .io_en(rvclkhdr_509_io_en), .io_scan_mode(rvclkhdr_509_io_scan_mode) ); - rvclkhdr rvclkhdr_510 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_510 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_510_io_l1clk), .io_clk(rvclkhdr_510_io_clk), .io_en(rvclkhdr_510_io_en), .io_scan_mode(rvclkhdr_510_io_scan_mode) ); - rvclkhdr rvclkhdr_511 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_511 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_511_io_l1clk), .io_clk(rvclkhdr_511_io_clk), .io_en(rvclkhdr_511_io_en), .io_scan_mode(rvclkhdr_511_io_scan_mode) ); - rvclkhdr rvclkhdr_512 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_512 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_512_io_l1clk), .io_clk(rvclkhdr_512_io_clk), .io_en(rvclkhdr_512_io_en), .io_scan_mode(rvclkhdr_512_io_scan_mode) ); - rvclkhdr rvclkhdr_513 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_513 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_513_io_l1clk), .io_clk(rvclkhdr_513_io_clk), .io_en(rvclkhdr_513_io_en), .io_scan_mode(rvclkhdr_513_io_scan_mode) ); - rvclkhdr rvclkhdr_514 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_514 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_514_io_l1clk), .io_clk(rvclkhdr_514_io_clk), .io_en(rvclkhdr_514_io_en), .io_scan_mode(rvclkhdr_514_io_scan_mode) ); - rvclkhdr rvclkhdr_515 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_515 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_515_io_l1clk), .io_clk(rvclkhdr_515_io_clk), .io_en(rvclkhdr_515_io_en), .io_scan_mode(rvclkhdr_515_io_scan_mode) ); - rvclkhdr rvclkhdr_516 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_516 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_516_io_l1clk), .io_clk(rvclkhdr_516_io_clk), .io_en(rvclkhdr_516_io_en), .io_scan_mode(rvclkhdr_516_io_scan_mode) ); - rvclkhdr rvclkhdr_517 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_517 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_517_io_l1clk), .io_clk(rvclkhdr_517_io_clk), .io_en(rvclkhdr_517_io_en), .io_scan_mode(rvclkhdr_517_io_scan_mode) ); - rvclkhdr rvclkhdr_518 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_518 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_518_io_l1clk), .io_clk(rvclkhdr_518_io_clk), .io_en(rvclkhdr_518_io_en), .io_scan_mode(rvclkhdr_518_io_scan_mode) ); - rvclkhdr rvclkhdr_519 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_519 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_519_io_l1clk), .io_clk(rvclkhdr_519_io_clk), .io_en(rvclkhdr_519_io_en), .io_scan_mode(rvclkhdr_519_io_scan_mode) ); - rvclkhdr rvclkhdr_520 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_520 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_520_io_l1clk), .io_clk(rvclkhdr_520_io_clk), .io_en(rvclkhdr_520_io_en), .io_scan_mode(rvclkhdr_520_io_scan_mode) ); - rvclkhdr rvclkhdr_521 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_521 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_521_io_l1clk), .io_clk(rvclkhdr_521_io_clk), .io_en(rvclkhdr_521_io_en), .io_scan_mode(rvclkhdr_521_io_scan_mode) ); - rvclkhdr rvclkhdr_522 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_522 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_522_io_l1clk), .io_clk(rvclkhdr_522_io_clk), .io_en(rvclkhdr_522_io_en), .io_scan_mode(rvclkhdr_522_io_scan_mode) ); - rvclkhdr rvclkhdr_523 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_523 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_523_io_l1clk), .io_clk(rvclkhdr_523_io_clk), .io_en(rvclkhdr_523_io_en), .io_scan_mode(rvclkhdr_523_io_scan_mode) ); - rvclkhdr rvclkhdr_524 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_524 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_524_io_l1clk), .io_clk(rvclkhdr_524_io_clk), .io_en(rvclkhdr_524_io_en), .io_scan_mode(rvclkhdr_524_io_scan_mode) ); - rvclkhdr rvclkhdr_525 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_525 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_525_io_l1clk), .io_clk(rvclkhdr_525_io_clk), .io_en(rvclkhdr_525_io_en), .io_scan_mode(rvclkhdr_525_io_scan_mode) ); - rvclkhdr rvclkhdr_526 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_526 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_526_io_l1clk), .io_clk(rvclkhdr_526_io_clk), .io_en(rvclkhdr_526_io_en), .io_scan_mode(rvclkhdr_526_io_scan_mode) ); - rvclkhdr rvclkhdr_527 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_527 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_527_io_l1clk), .io_clk(rvclkhdr_527_io_clk), .io_en(rvclkhdr_527_io_en), .io_scan_mode(rvclkhdr_527_io_scan_mode) ); - rvclkhdr rvclkhdr_528 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_528 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_528_io_l1clk), .io_clk(rvclkhdr_528_io_clk), .io_en(rvclkhdr_528_io_en), .io_scan_mode(rvclkhdr_528_io_scan_mode) ); - rvclkhdr rvclkhdr_529 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_529 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_529_io_l1clk), .io_clk(rvclkhdr_529_io_clk), .io_en(rvclkhdr_529_io_en), .io_scan_mode(rvclkhdr_529_io_scan_mode) ); - rvclkhdr rvclkhdr_530 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_530 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_530_io_l1clk), .io_clk(rvclkhdr_530_io_clk), .io_en(rvclkhdr_530_io_en), .io_scan_mode(rvclkhdr_530_io_scan_mode) ); - rvclkhdr rvclkhdr_531 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_531 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_531_io_l1clk), .io_clk(rvclkhdr_531_io_clk), .io_en(rvclkhdr_531_io_en), .io_scan_mode(rvclkhdr_531_io_scan_mode) ); - rvclkhdr rvclkhdr_532 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_532 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_532_io_l1clk), .io_clk(rvclkhdr_532_io_clk), .io_en(rvclkhdr_532_io_en), .io_scan_mode(rvclkhdr_532_io_scan_mode) ); - rvclkhdr rvclkhdr_533 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_533 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_533_io_l1clk), .io_clk(rvclkhdr_533_io_clk), .io_en(rvclkhdr_533_io_en), .io_scan_mode(rvclkhdr_533_io_scan_mode) ); - rvclkhdr rvclkhdr_534 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_534 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_534_io_l1clk), .io_clk(rvclkhdr_534_io_clk), .io_en(rvclkhdr_534_io_en), .io_scan_mode(rvclkhdr_534_io_scan_mode) ); - rvclkhdr rvclkhdr_535 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_535 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_535_io_l1clk), .io_clk(rvclkhdr_535_io_clk), .io_en(rvclkhdr_535_io_en), .io_scan_mode(rvclkhdr_535_io_scan_mode) ); - rvclkhdr rvclkhdr_536 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_536 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_536_io_l1clk), .io_clk(rvclkhdr_536_io_clk), .io_en(rvclkhdr_536_io_en), .io_scan_mode(rvclkhdr_536_io_scan_mode) ); - rvclkhdr rvclkhdr_537 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_537 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_537_io_l1clk), .io_clk(rvclkhdr_537_io_clk), .io_en(rvclkhdr_537_io_en), .io_scan_mode(rvclkhdr_537_io_scan_mode) ); - rvclkhdr rvclkhdr_538 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_538 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_538_io_l1clk), .io_clk(rvclkhdr_538_io_clk), .io_en(rvclkhdr_538_io_en), .io_scan_mode(rvclkhdr_538_io_scan_mode) ); - rvclkhdr rvclkhdr_539 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_539 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_539_io_l1clk), .io_clk(rvclkhdr_539_io_clk), .io_en(rvclkhdr_539_io_en), .io_scan_mode(rvclkhdr_539_io_scan_mode) ); - rvclkhdr rvclkhdr_540 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_540 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_540_io_l1clk), .io_clk(rvclkhdr_540_io_clk), .io_en(rvclkhdr_540_io_en), .io_scan_mode(rvclkhdr_540_io_scan_mode) ); - rvclkhdr rvclkhdr_541 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_541 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_541_io_l1clk), .io_clk(rvclkhdr_541_io_clk), .io_en(rvclkhdr_541_io_en), .io_scan_mode(rvclkhdr_541_io_scan_mode) ); - rvclkhdr rvclkhdr_542 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_542 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_542_io_l1clk), .io_clk(rvclkhdr_542_io_clk), .io_en(rvclkhdr_542_io_en), .io_scan_mode(rvclkhdr_542_io_scan_mode) ); - rvclkhdr rvclkhdr_543 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_543 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_543_io_l1clk), .io_clk(rvclkhdr_543_io_clk), .io_en(rvclkhdr_543_io_en), .io_scan_mode(rvclkhdr_543_io_scan_mode) ); - rvclkhdr rvclkhdr_544 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_544 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_544_io_l1clk), .io_clk(rvclkhdr_544_io_clk), .io_en(rvclkhdr_544_io_en), .io_scan_mode(rvclkhdr_544_io_scan_mode) ); - rvclkhdr rvclkhdr_545 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_545 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_545_io_l1clk), .io_clk(rvclkhdr_545_io_clk), .io_en(rvclkhdr_545_io_en), .io_scan_mode(rvclkhdr_545_io_scan_mode) ); - rvclkhdr rvclkhdr_546 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_546 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_546_io_l1clk), .io_clk(rvclkhdr_546_io_clk), .io_en(rvclkhdr_546_io_en), .io_scan_mode(rvclkhdr_546_io_scan_mode) ); - rvclkhdr rvclkhdr_547 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_547 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_547_io_l1clk), .io_clk(rvclkhdr_547_io_clk), .io_en(rvclkhdr_547_io_en), .io_scan_mode(rvclkhdr_547_io_scan_mode) ); - rvclkhdr rvclkhdr_548 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_548 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_548_io_l1clk), .io_clk(rvclkhdr_548_io_clk), .io_en(rvclkhdr_548_io_en), .io_scan_mode(rvclkhdr_548_io_scan_mode) ); - rvclkhdr rvclkhdr_549 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_549 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_549_io_l1clk), .io_clk(rvclkhdr_549_io_clk), .io_en(rvclkhdr_549_io_en), .io_scan_mode(rvclkhdr_549_io_scan_mode) ); - rvclkhdr rvclkhdr_550 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_550 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_550_io_l1clk), .io_clk(rvclkhdr_550_io_clk), .io_en(rvclkhdr_550_io_en), .io_scan_mode(rvclkhdr_550_io_scan_mode) ); - rvclkhdr rvclkhdr_551 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_551 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_551_io_l1clk), .io_clk(rvclkhdr_551_io_clk), .io_en(rvclkhdr_551_io_en), .io_scan_mode(rvclkhdr_551_io_scan_mode) ); - rvclkhdr rvclkhdr_552 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_552 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_552_io_l1clk), .io_clk(rvclkhdr_552_io_clk), .io_en(rvclkhdr_552_io_en), .io_scan_mode(rvclkhdr_552_io_scan_mode) ); - rvclkhdr rvclkhdr_553 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_553 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_553_io_l1clk), .io_clk(rvclkhdr_553_io_clk), .io_en(rvclkhdr_553_io_en), @@ -26456,1668 +26456,1668 @@ module ifu_bp_ctl( assign io_ifu_bp_pc4_f = {_T_286,_T_289}; // @[ifu_bp_ctl.scala 328:19] assign io_ifu_bp_valid_f = bht_valid_f & _T_345; // @[ifu_bp_ctl.scala 330:21] assign io_ifu_bp_poffset_f = btb_sel_data_f[15:4]; // @[ifu_bp_ctl.scala 344:23] - assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_io_en = io_ifc_fetch_req_f | exu_mp_valid; // @[el2_lib.scala 511:17] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_1_io_en = _T_376 & io_ic_hit_f; // @[el2_lib.scala 511:17] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_2_io_en = ~rs_hold; // @[el2_lib.scala 511:17] - assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_3_io_en = rs_push | rs_pop; // @[el2_lib.scala 511:17] - assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_4_io_en = rs_push | rs_pop; // @[el2_lib.scala 511:17] - assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_5_io_en = rs_push | rs_pop; // @[el2_lib.scala 511:17] - assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_6_io_en = rs_push | rs_pop; // @[el2_lib.scala 511:17] - assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_7_io_en = rs_push | rs_pop; // @[el2_lib.scala 511:17] - assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_8_io_en = rs_push | rs_pop; // @[el2_lib.scala 511:17] - assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_9_io_en = _T_473 & io_ifu_bp_hit_taken_f; // @[el2_lib.scala 511:17] - assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_10_io_en = _T_576 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_11_io_en = _T_579 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_12_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_12_io_en = _T_582 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_13_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_13_io_en = _T_585 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_14_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_14_io_en = _T_588 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_15_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_15_io_en = _T_591 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_16_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_16_io_en = _T_594 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_17_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_17_io_en = _T_597 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_18_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_18_io_en = _T_600 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_19_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_19_io_en = _T_603 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_19_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_20_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_20_io_en = _T_606 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_20_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_21_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_21_io_en = _T_609 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_21_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_22_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_22_io_en = _T_612 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_22_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_23_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_23_io_en = _T_615 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_23_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_24_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_24_io_en = _T_618 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_24_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_25_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_25_io_en = _T_621 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_25_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_26_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_26_io_en = _T_624 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_26_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_27_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_27_io_en = _T_627 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_27_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_28_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_28_io_en = _T_630 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_28_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_29_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_29_io_en = _T_633 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_29_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_30_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_30_io_en = _T_636 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_30_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_31_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_31_io_en = _T_639 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_31_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_32_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_32_io_en = _T_642 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_32_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_33_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_33_io_en = _T_645 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_33_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_34_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_34_io_en = _T_648 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_34_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_35_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_35_io_en = _T_651 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_35_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_36_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_36_io_en = _T_654 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_36_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_37_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_37_io_en = _T_657 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_37_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_38_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_38_io_en = _T_660 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_38_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_39_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_39_io_en = _T_663 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_39_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_40_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_40_io_en = _T_666 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_40_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_41_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_41_io_en = _T_669 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_41_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_42_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_42_io_en = _T_672 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_42_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_43_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_43_io_en = _T_675 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_43_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_44_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_44_io_en = _T_678 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_44_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_45_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_45_io_en = _T_681 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_45_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_46_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_46_io_en = _T_684 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_46_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_47_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_47_io_en = _T_687 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_47_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_48_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_48_io_en = _T_690 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_48_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_49_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_49_io_en = _T_693 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_49_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_50_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_50_io_en = _T_696 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_50_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_51_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_51_io_en = _T_699 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_51_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_52_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_52_io_en = _T_702 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_52_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_53_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_53_io_en = _T_705 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_53_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_54_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_54_io_en = _T_708 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_54_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_55_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_55_io_en = _T_711 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_55_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_56_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_56_io_en = _T_714 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_56_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_57_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_57_io_en = _T_717 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_57_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_58_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_58_io_en = _T_720 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_58_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_59_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_59_io_en = _T_723 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_59_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_60_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_60_io_en = _T_726 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_60_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_61_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_61_io_en = _T_729 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_61_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_62_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_62_io_en = _T_732 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_62_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_63_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_63_io_en = _T_735 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_63_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_64_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_64_io_en = _T_738 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_64_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_65_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_65_io_en = _T_741 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_65_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_66_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_66_io_en = _T_744 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_66_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_67_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_67_io_en = _T_747 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_67_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_68_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_68_io_en = _T_750 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_68_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_69_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_69_io_en = _T_753 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_69_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_70_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_70_io_en = _T_756 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_70_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_71_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_71_io_en = _T_759 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_71_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_72_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_72_io_en = _T_762 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_72_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_73_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_73_io_en = _T_765 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_73_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_74_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_74_io_en = _T_768 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_74_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_75_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_75_io_en = _T_771 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_75_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_76_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_76_io_en = _T_774 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_76_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_77_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_77_io_en = _T_777 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_77_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_78_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_78_io_en = _T_780 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_78_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_79_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_79_io_en = _T_783 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_79_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_80_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_80_io_en = _T_786 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_80_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_81_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_81_io_en = _T_789 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_81_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_82_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_82_io_en = _T_792 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_82_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_83_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_83_io_en = _T_795 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_83_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_84_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_84_io_en = _T_798 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_84_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_85_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_85_io_en = _T_801 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_85_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_86_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_86_io_en = _T_804 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_86_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_87_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_87_io_en = _T_807 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_87_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_88_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_88_io_en = _T_810 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_88_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_89_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_89_io_en = _T_813 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_89_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_90_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_90_io_en = _T_816 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_90_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_91_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_91_io_en = _T_819 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_91_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_92_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_92_io_en = _T_822 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_92_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_93_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_93_io_en = _T_825 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_93_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_94_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_94_io_en = _T_828 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_94_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_95_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_95_io_en = _T_831 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_95_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_96_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_96_io_en = _T_834 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_96_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_97_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_97_io_en = _T_837 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_97_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_98_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_98_io_en = _T_840 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_98_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_99_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_99_io_en = _T_843 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_99_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_100_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_100_io_en = _T_846 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_100_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_101_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_101_io_en = _T_849 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_101_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_102_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_102_io_en = _T_852 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_102_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_103_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_103_io_en = _T_855 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_103_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_104_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_104_io_en = _T_858 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_104_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_105_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_105_io_en = _T_861 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_105_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_106_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_106_io_en = _T_864 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_106_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_107_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_107_io_en = _T_867 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_107_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_108_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_108_io_en = _T_870 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_108_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_109_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_109_io_en = _T_873 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_109_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_110_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_110_io_en = _T_876 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_110_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_111_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_111_io_en = _T_879 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_111_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_112_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_112_io_en = _T_882 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_112_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_113_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_113_io_en = _T_885 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_113_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_114_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_114_io_en = _T_888 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_114_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_115_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_115_io_en = _T_891 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_115_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_116_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_116_io_en = _T_894 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_116_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_117_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_117_io_en = _T_897 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_117_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_118_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_118_io_en = _T_900 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_118_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_119_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_119_io_en = _T_903 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_119_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_120_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_120_io_en = _T_906 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_120_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_121_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_121_io_en = _T_909 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_121_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_122_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_122_io_en = _T_912 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_122_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_123_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_123_io_en = _T_915 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_123_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_124_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_124_io_en = _T_918 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_124_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_125_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_125_io_en = _T_921 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_125_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_126_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_126_io_en = _T_924 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_126_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_127_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_127_io_en = _T_927 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_127_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_128_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_128_io_en = _T_930 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_128_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_129_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_129_io_en = _T_933 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_129_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_130_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_130_io_en = _T_936 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_130_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_131_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_131_io_en = _T_939 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_131_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_132_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_132_io_en = _T_942 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_132_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_133_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_133_io_en = _T_945 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_133_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_134_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_134_io_en = _T_948 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_134_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_135_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_135_io_en = _T_951 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_135_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_136_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_136_io_en = _T_954 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_136_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_137_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_137_io_en = _T_957 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_137_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_138_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_138_io_en = _T_960 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_138_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_139_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_139_io_en = _T_963 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_139_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_140_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_140_io_en = _T_966 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_140_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_141_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_141_io_en = _T_969 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_141_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_142_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_142_io_en = _T_972 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_142_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_143_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_143_io_en = _T_975 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_143_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_144_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_144_io_en = _T_978 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_144_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_145_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_145_io_en = _T_981 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_145_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_146_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_146_io_en = _T_984 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_146_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_147_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_147_io_en = _T_987 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_147_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_148_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_148_io_en = _T_990 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_148_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_149_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_149_io_en = _T_993 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_149_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_150_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_150_io_en = _T_996 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_150_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_151_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_151_io_en = _T_999 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_151_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_152_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_152_io_en = _T_1002 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_152_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_153_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_153_io_en = _T_1005 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_153_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_154_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_154_io_en = _T_1008 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_154_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_155_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_155_io_en = _T_1011 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_155_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_156_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_156_io_en = _T_1014 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_156_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_157_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_157_io_en = _T_1017 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_157_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_158_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_158_io_en = _T_1020 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_158_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_159_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_159_io_en = _T_1023 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_159_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_160_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_160_io_en = _T_1026 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_160_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_161_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_161_io_en = _T_1029 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_161_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_162_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_162_io_en = _T_1032 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_162_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_163_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_163_io_en = _T_1035 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_163_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_164_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_164_io_en = _T_1038 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_164_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_165_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_165_io_en = _T_1041 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_165_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_166_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_166_io_en = _T_1044 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_166_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_167_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_167_io_en = _T_1047 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_167_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_168_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_168_io_en = _T_1050 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_168_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_169_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_169_io_en = _T_1053 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_169_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_170_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_170_io_en = _T_1056 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_170_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_171_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_171_io_en = _T_1059 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_171_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_172_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_172_io_en = _T_1062 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_172_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_173_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_173_io_en = _T_1065 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_173_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_174_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_174_io_en = _T_1068 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_174_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_175_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_175_io_en = _T_1071 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_175_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_176_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_176_io_en = _T_1074 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_176_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_177_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_177_io_en = _T_1077 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_177_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_178_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_178_io_en = _T_1080 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_178_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_179_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_179_io_en = _T_1083 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_179_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_180_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_180_io_en = _T_1086 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_180_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_181_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_181_io_en = _T_1089 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_181_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_182_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_182_io_en = _T_1092 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_182_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_183_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_183_io_en = _T_1095 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_183_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_184_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_184_io_en = _T_1098 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_184_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_185_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_185_io_en = _T_1101 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_185_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_186_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_186_io_en = _T_1104 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_186_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_187_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_187_io_en = _T_1107 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_187_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_188_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_188_io_en = _T_1110 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_188_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_189_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_189_io_en = _T_1113 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_189_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_190_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_190_io_en = _T_1116 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_190_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_191_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_191_io_en = _T_1119 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_191_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_192_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_192_io_en = _T_1122 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_192_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_193_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_193_io_en = _T_1125 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_193_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_194_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_194_io_en = _T_1128 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_194_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_195_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_195_io_en = _T_1131 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_195_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_196_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_196_io_en = _T_1134 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_196_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_197_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_197_io_en = _T_1137 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_197_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_198_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_198_io_en = _T_1140 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_198_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_199_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_199_io_en = _T_1143 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_199_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_200_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_200_io_en = _T_1146 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_200_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_201_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_201_io_en = _T_1149 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_201_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_202_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_202_io_en = _T_1152 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_202_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_203_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_203_io_en = _T_1155 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_203_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_204_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_204_io_en = _T_1158 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_204_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_205_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_205_io_en = _T_1161 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_205_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_206_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_206_io_en = _T_1164 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_206_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_207_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_207_io_en = _T_1167 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_207_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_208_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_208_io_en = _T_1170 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_208_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_209_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_209_io_en = _T_1173 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_209_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_210_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_210_io_en = _T_1176 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_210_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_211_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_211_io_en = _T_1179 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_211_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_212_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_212_io_en = _T_1182 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_212_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_213_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_213_io_en = _T_1185 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_213_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_214_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_214_io_en = _T_1188 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_214_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_215_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_215_io_en = _T_1191 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_215_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_216_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_216_io_en = _T_1194 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_216_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_217_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_217_io_en = _T_1197 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_217_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_218_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_218_io_en = _T_1200 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_218_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_219_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_219_io_en = _T_1203 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_219_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_220_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_220_io_en = _T_1206 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_220_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_221_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_221_io_en = _T_1209 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_221_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_222_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_222_io_en = _T_1212 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_222_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_223_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_223_io_en = _T_1215 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_223_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_224_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_224_io_en = _T_1218 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_224_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_225_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_225_io_en = _T_1221 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_225_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_226_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_226_io_en = _T_1224 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_226_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_227_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_227_io_en = _T_1227 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_227_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_228_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_228_io_en = _T_1230 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_228_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_229_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_229_io_en = _T_1233 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_229_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_230_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_230_io_en = _T_1236 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_230_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_231_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_231_io_en = _T_1239 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_231_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_232_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_232_io_en = _T_1242 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_232_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_233_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_233_io_en = _T_1245 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_233_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_234_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_234_io_en = _T_1248 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_234_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_235_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_235_io_en = _T_1251 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_235_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_236_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_236_io_en = _T_1254 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_236_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_237_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_237_io_en = _T_1257 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_237_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_238_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_238_io_en = _T_1260 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_238_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_239_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_239_io_en = _T_1263 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_239_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_240_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_240_io_en = _T_1266 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_240_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_241_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_241_io_en = _T_1269 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_241_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_242_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_242_io_en = _T_1272 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_242_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_243_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_243_io_en = _T_1275 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_243_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_244_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_244_io_en = _T_1278 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_244_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_245_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_245_io_en = _T_1281 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_245_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_246_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_246_io_en = _T_1284 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_246_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_247_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_247_io_en = _T_1287 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_247_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_248_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_248_io_en = _T_1290 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_248_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_249_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_249_io_en = _T_1293 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_249_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_250_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_250_io_en = _T_1296 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_250_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_251_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_251_io_en = _T_1299 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_251_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_252_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_252_io_en = _T_1302 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_252_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_253_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_253_io_en = _T_1305 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_253_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_254_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_254_io_en = _T_1308 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_254_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_255_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_255_io_en = _T_1311 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_255_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_256_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_256_io_en = _T_1314 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_256_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_257_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_257_io_en = _T_1317 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_257_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_258_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_258_io_en = _T_1320 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_258_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_259_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_259_io_en = _T_1323 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_259_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_260_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_260_io_en = _T_1326 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_260_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_261_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_261_io_en = _T_1329 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_261_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_262_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_262_io_en = _T_1332 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_262_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_263_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_263_io_en = _T_1335 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_263_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_264_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_264_io_en = _T_1338 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_264_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_265_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_265_io_en = _T_1341 & btb_wr_en_way0; // @[el2_lib.scala 511:17] - assign rvclkhdr_265_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_266_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_266_io_en = _T_576 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_266_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_267_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_267_io_en = _T_579 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_267_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_268_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_268_io_en = _T_582 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_268_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_269_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_269_io_en = _T_585 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_269_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_270_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_270_io_en = _T_588 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_270_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_271_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_271_io_en = _T_591 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_271_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_272_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_272_io_en = _T_594 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_272_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_273_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_273_io_en = _T_597 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_273_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_274_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_274_io_en = _T_600 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_274_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_275_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_275_io_en = _T_603 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_275_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_276_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_276_io_en = _T_606 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_276_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_277_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_277_io_en = _T_609 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_277_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_278_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_278_io_en = _T_612 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_278_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_279_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_279_io_en = _T_615 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_279_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_280_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_280_io_en = _T_618 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_280_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_281_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_281_io_en = _T_621 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_281_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_282_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_282_io_en = _T_624 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_282_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_283_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_283_io_en = _T_627 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_283_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_284_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_284_io_en = _T_630 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_284_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_285_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_285_io_en = _T_633 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_285_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_286_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_286_io_en = _T_636 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_286_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_287_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_287_io_en = _T_639 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_287_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_288_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_288_io_en = _T_642 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_288_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_289_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_289_io_en = _T_645 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_289_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_290_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_290_io_en = _T_648 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_290_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_291_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_291_io_en = _T_651 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_291_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_292_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_292_io_en = _T_654 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_292_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_293_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_293_io_en = _T_657 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_293_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_294_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_294_io_en = _T_660 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_294_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_295_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_295_io_en = _T_663 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_295_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_296_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_296_io_en = _T_666 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_296_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_297_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_297_io_en = _T_669 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_297_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_298_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_298_io_en = _T_672 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_298_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_299_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_299_io_en = _T_675 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_299_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_300_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_300_io_en = _T_678 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_300_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_301_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_301_io_en = _T_681 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_301_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_302_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_302_io_en = _T_684 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_302_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_303_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_303_io_en = _T_687 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_303_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_304_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_304_io_en = _T_690 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_304_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_305_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_305_io_en = _T_693 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_305_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_306_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_306_io_en = _T_696 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_306_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_307_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_307_io_en = _T_699 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_307_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_308_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_308_io_en = _T_702 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_308_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_309_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_309_io_en = _T_705 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_309_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_310_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_310_io_en = _T_708 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_310_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_311_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_311_io_en = _T_711 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_311_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_312_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_312_io_en = _T_714 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_312_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_313_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_313_io_en = _T_717 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_313_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_314_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_314_io_en = _T_720 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_314_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_315_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_315_io_en = _T_723 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_315_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_316_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_316_io_en = _T_726 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_316_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_317_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_317_io_en = _T_729 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_317_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_318_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_318_io_en = _T_732 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_318_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_319_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_319_io_en = _T_735 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_319_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_320_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_320_io_en = _T_738 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_320_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_321_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_321_io_en = _T_741 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_321_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_322_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_322_io_en = _T_744 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_322_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_323_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_323_io_en = _T_747 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_323_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_324_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_324_io_en = _T_750 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_324_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_325_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_325_io_en = _T_753 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_325_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_326_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_326_io_en = _T_756 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_326_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_327_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_327_io_en = _T_759 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_327_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_328_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_328_io_en = _T_762 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_328_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_329_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_329_io_en = _T_765 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_329_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_330_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_330_io_en = _T_768 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_330_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_331_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_331_io_en = _T_771 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_331_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_332_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_332_io_en = _T_774 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_332_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_333_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_333_io_en = _T_777 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_333_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_334_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_334_io_en = _T_780 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_334_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_335_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_335_io_en = _T_783 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_335_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_336_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_336_io_en = _T_786 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_336_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_337_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_337_io_en = _T_789 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_337_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_338_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_338_io_en = _T_792 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_338_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_339_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_339_io_en = _T_795 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_339_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_340_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_340_io_en = _T_798 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_340_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_341_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_341_io_en = _T_801 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_341_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_342_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_342_io_en = _T_804 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_342_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_343_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_343_io_en = _T_807 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_343_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_344_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_344_io_en = _T_810 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_344_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_345_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_345_io_en = _T_813 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_345_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_346_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_346_io_en = _T_816 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_346_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_347_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_347_io_en = _T_819 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_347_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_348_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_348_io_en = _T_822 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_348_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_349_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_349_io_en = _T_825 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_349_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_350_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_350_io_en = _T_828 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_350_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_351_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_351_io_en = _T_831 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_351_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_352_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_352_io_en = _T_834 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_352_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_353_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_353_io_en = _T_837 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_353_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_354_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_354_io_en = _T_840 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_354_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_355_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_355_io_en = _T_843 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_355_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_356_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_356_io_en = _T_846 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_356_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_357_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_357_io_en = _T_849 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_357_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_358_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_358_io_en = _T_852 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_358_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_359_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_359_io_en = _T_855 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_359_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_360_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_360_io_en = _T_858 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_360_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_361_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_361_io_en = _T_861 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_361_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_362_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_362_io_en = _T_864 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_362_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_363_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_363_io_en = _T_867 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_363_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_364_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_364_io_en = _T_870 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_364_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_365_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_365_io_en = _T_873 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_365_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_366_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_366_io_en = _T_876 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_366_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_367_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_367_io_en = _T_879 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_367_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_368_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_368_io_en = _T_882 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_368_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_369_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_369_io_en = _T_885 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_369_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_370_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_370_io_en = _T_888 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_370_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_371_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_371_io_en = _T_891 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_371_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_372_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_372_io_en = _T_894 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_372_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_373_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_373_io_en = _T_897 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_373_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_374_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_374_io_en = _T_900 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_374_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_375_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_375_io_en = _T_903 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_375_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_376_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_376_io_en = _T_906 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_376_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_377_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_377_io_en = _T_909 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_377_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_378_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_378_io_en = _T_912 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_378_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_379_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_379_io_en = _T_915 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_379_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_380_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_380_io_en = _T_918 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_380_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_381_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_381_io_en = _T_921 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_381_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_382_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_382_io_en = _T_924 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_382_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_383_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_383_io_en = _T_927 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_383_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_384_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_384_io_en = _T_930 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_384_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_385_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_385_io_en = _T_933 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_385_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_386_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_386_io_en = _T_936 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_386_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_387_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_387_io_en = _T_939 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_387_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_388_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_388_io_en = _T_942 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_388_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_389_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_389_io_en = _T_945 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_389_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_390_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_390_io_en = _T_948 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_390_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_391_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_391_io_en = _T_951 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_391_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_392_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_392_io_en = _T_954 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_392_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_393_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_393_io_en = _T_957 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_393_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_394_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_394_io_en = _T_960 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_394_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_395_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_395_io_en = _T_963 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_395_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_396_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_396_io_en = _T_966 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_396_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_397_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_397_io_en = _T_969 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_397_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_398_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_398_io_en = _T_972 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_398_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_399_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_399_io_en = _T_975 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_399_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_400_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_400_io_en = _T_978 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_400_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_401_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_401_io_en = _T_981 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_401_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_402_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_402_io_en = _T_984 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_402_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_403_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_403_io_en = _T_987 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_403_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_404_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_404_io_en = _T_990 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_404_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_405_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_405_io_en = _T_993 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_405_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_406_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_406_io_en = _T_996 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_406_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_407_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_407_io_en = _T_999 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_407_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_408_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_408_io_en = _T_1002 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_408_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_409_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_409_io_en = _T_1005 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_409_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_410_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_410_io_en = _T_1008 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_410_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_411_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_411_io_en = _T_1011 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_411_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_412_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_412_io_en = _T_1014 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_412_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_413_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_413_io_en = _T_1017 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_413_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_414_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_414_io_en = _T_1020 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_414_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_415_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_415_io_en = _T_1023 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_415_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_416_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_416_io_en = _T_1026 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_416_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_417_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_417_io_en = _T_1029 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_417_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_418_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_418_io_en = _T_1032 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_418_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_419_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_419_io_en = _T_1035 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_419_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_420_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_420_io_en = _T_1038 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_420_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_421_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_421_io_en = _T_1041 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_421_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_422_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_422_io_en = _T_1044 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_422_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_423_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_423_io_en = _T_1047 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_423_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_424_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_424_io_en = _T_1050 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_424_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_425_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_425_io_en = _T_1053 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_425_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_426_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_426_io_en = _T_1056 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_426_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_427_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_427_io_en = _T_1059 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_427_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_428_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_428_io_en = _T_1062 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_428_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_429_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_429_io_en = _T_1065 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_429_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_430_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_430_io_en = _T_1068 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_430_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_431_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_431_io_en = _T_1071 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_431_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_432_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_432_io_en = _T_1074 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_432_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_433_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_433_io_en = _T_1077 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_433_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_434_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_434_io_en = _T_1080 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_434_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_435_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_435_io_en = _T_1083 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_435_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_436_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_436_io_en = _T_1086 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_436_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_437_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_437_io_en = _T_1089 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_437_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_438_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_438_io_en = _T_1092 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_438_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_439_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_439_io_en = _T_1095 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_439_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_440_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_440_io_en = _T_1098 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_440_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_441_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_441_io_en = _T_1101 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_441_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_442_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_442_io_en = _T_1104 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_442_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_443_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_443_io_en = _T_1107 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_443_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_444_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_444_io_en = _T_1110 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_444_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_445_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_445_io_en = _T_1113 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_445_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_446_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_446_io_en = _T_1116 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_446_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_447_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_447_io_en = _T_1119 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_447_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_448_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_448_io_en = _T_1122 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_448_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_449_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_449_io_en = _T_1125 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_449_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_450_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_450_io_en = _T_1128 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_450_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_451_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_451_io_en = _T_1131 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_451_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_452_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_452_io_en = _T_1134 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_452_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_453_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_453_io_en = _T_1137 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_453_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_454_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_454_io_en = _T_1140 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_454_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_455_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_455_io_en = _T_1143 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_455_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_456_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_456_io_en = _T_1146 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_456_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_457_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_457_io_en = _T_1149 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_457_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_458_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_458_io_en = _T_1152 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_458_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_459_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_459_io_en = _T_1155 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_459_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_460_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_460_io_en = _T_1158 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_460_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_461_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_461_io_en = _T_1161 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_461_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_462_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_462_io_en = _T_1164 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_462_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_463_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_463_io_en = _T_1167 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_463_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_464_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_464_io_en = _T_1170 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_464_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_465_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_465_io_en = _T_1173 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_465_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_466_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_466_io_en = _T_1176 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_466_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_467_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_467_io_en = _T_1179 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_467_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_468_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_468_io_en = _T_1182 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_468_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_469_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_469_io_en = _T_1185 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_469_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_470_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_470_io_en = _T_1188 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_470_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_471_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_471_io_en = _T_1191 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_471_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_472_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_472_io_en = _T_1194 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_472_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_473_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_473_io_en = _T_1197 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_473_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_474_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_474_io_en = _T_1200 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_474_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_475_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_475_io_en = _T_1203 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_475_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_476_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_476_io_en = _T_1206 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_476_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_477_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_477_io_en = _T_1209 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_477_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_478_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_478_io_en = _T_1212 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_478_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_479_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_479_io_en = _T_1215 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_479_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_480_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_480_io_en = _T_1218 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_480_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_481_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_481_io_en = _T_1221 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_481_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_482_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_482_io_en = _T_1224 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_482_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_483_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_483_io_en = _T_1227 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_483_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_484_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_484_io_en = _T_1230 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_484_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_485_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_485_io_en = _T_1233 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_485_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_486_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_486_io_en = _T_1236 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_486_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_487_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_487_io_en = _T_1239 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_487_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_488_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_488_io_en = _T_1242 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_488_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_489_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_489_io_en = _T_1245 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_489_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_490_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_490_io_en = _T_1248 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_490_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_491_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_491_io_en = _T_1251 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_491_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_492_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_492_io_en = _T_1254 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_492_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_493_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_493_io_en = _T_1257 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_493_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_494_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_494_io_en = _T_1260 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_494_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_495_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_495_io_en = _T_1263 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_495_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_496_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_496_io_en = _T_1266 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_496_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_497_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_497_io_en = _T_1269 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_497_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_498_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_498_io_en = _T_1272 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_498_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_499_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_499_io_en = _T_1275 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_499_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_500_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_500_io_en = _T_1278 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_500_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_501_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_501_io_en = _T_1281 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_501_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_502_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_502_io_en = _T_1284 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_502_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_503_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_503_io_en = _T_1287 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_503_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_504_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_504_io_en = _T_1290 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_504_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_505_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_505_io_en = _T_1293 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_505_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_506_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_506_io_en = _T_1296 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_506_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_507_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_507_io_en = _T_1299 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_507_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_508_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_508_io_en = _T_1302 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_508_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_509_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_509_io_en = _T_1305 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_509_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_510_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_510_io_en = _T_1308 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_510_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_511_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_511_io_en = _T_1311 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_511_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_512_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_512_io_en = _T_1314 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_512_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_513_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_513_io_en = _T_1317 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_513_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_514_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_514_io_en = _T_1320 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_514_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_515_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_515_io_en = _T_1323 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_515_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_516_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_516_io_en = _T_1326 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_516_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_517_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_517_io_en = _T_1329 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_517_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_518_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_518_io_en = _T_1332 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_518_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_519_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_519_io_en = _T_1335 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_519_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_520_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_520_io_en = _T_1338 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_520_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_521_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_521_io_en = _T_1341 & btb_wr_en_way1; // @[el2_lib.scala 511:17] - assign rvclkhdr_521_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_522_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_522_io_en = _T_6212 | _T_6217; // @[el2_lib.scala 485:16] - assign rvclkhdr_522_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_523_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_523_io_en = _T_6223 | _T_6228; // @[el2_lib.scala 485:16] - assign rvclkhdr_523_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_524_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_524_io_en = _T_6234 | _T_6239; // @[el2_lib.scala 485:16] - assign rvclkhdr_524_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_525_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_525_io_en = _T_6245 | _T_6250; // @[el2_lib.scala 485:16] - assign rvclkhdr_525_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_526_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_526_io_en = _T_6256 | _T_6261; // @[el2_lib.scala 485:16] - assign rvclkhdr_526_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_527_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_527_io_en = _T_6267 | _T_6272; // @[el2_lib.scala 485:16] - assign rvclkhdr_527_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_528_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_528_io_en = _T_6278 | _T_6283; // @[el2_lib.scala 485:16] - assign rvclkhdr_528_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_529_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_529_io_en = _T_6289 | _T_6294; // @[el2_lib.scala 485:16] - assign rvclkhdr_529_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_530_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_530_io_en = _T_6300 | _T_6305; // @[el2_lib.scala 485:16] - assign rvclkhdr_530_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_531_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_531_io_en = _T_6311 | _T_6316; // @[el2_lib.scala 485:16] - assign rvclkhdr_531_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_532_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_532_io_en = _T_6322 | _T_6327; // @[el2_lib.scala 485:16] - assign rvclkhdr_532_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_533_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_533_io_en = _T_6333 | _T_6338; // @[el2_lib.scala 485:16] - assign rvclkhdr_533_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_534_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_534_io_en = _T_6344 | _T_6349; // @[el2_lib.scala 485:16] - assign rvclkhdr_534_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_535_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_535_io_en = _T_6355 | _T_6360; // @[el2_lib.scala 485:16] - assign rvclkhdr_535_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_536_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_536_io_en = _T_6366 | _T_6371; // @[el2_lib.scala 485:16] - assign rvclkhdr_536_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_537_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_537_io_en = _T_6377 | _T_6382; // @[el2_lib.scala 485:16] - assign rvclkhdr_537_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_538_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_538_io_en = _T_6388 | _T_6393; // @[el2_lib.scala 485:16] - assign rvclkhdr_538_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_539_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_539_io_en = _T_6399 | _T_6404; // @[el2_lib.scala 485:16] - assign rvclkhdr_539_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_540_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_540_io_en = _T_6410 | _T_6415; // @[el2_lib.scala 485:16] - assign rvclkhdr_540_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_541_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_541_io_en = _T_6421 | _T_6426; // @[el2_lib.scala 485:16] - assign rvclkhdr_541_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_542_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_542_io_en = _T_6432 | _T_6437; // @[el2_lib.scala 485:16] - assign rvclkhdr_542_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_543_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_543_io_en = _T_6443 | _T_6448; // @[el2_lib.scala 485:16] - assign rvclkhdr_543_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_544_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_544_io_en = _T_6454 | _T_6459; // @[el2_lib.scala 485:16] - assign rvclkhdr_544_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_545_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_545_io_en = _T_6465 | _T_6470; // @[el2_lib.scala 485:16] - assign rvclkhdr_545_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_546_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_546_io_en = _T_6476 | _T_6481; // @[el2_lib.scala 485:16] - assign rvclkhdr_546_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_547_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_547_io_en = _T_6487 | _T_6492; // @[el2_lib.scala 485:16] - assign rvclkhdr_547_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_548_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_548_io_en = _T_6498 | _T_6503; // @[el2_lib.scala 485:16] - assign rvclkhdr_548_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_549_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_549_io_en = _T_6509 | _T_6514; // @[el2_lib.scala 485:16] - assign rvclkhdr_549_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_550_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_550_io_en = _T_6520 | _T_6525; // @[el2_lib.scala 485:16] - assign rvclkhdr_550_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_551_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_551_io_en = _T_6531 | _T_6536; // @[el2_lib.scala 485:16] - assign rvclkhdr_551_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_552_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_552_io_en = _T_6542 | _T_6547; // @[el2_lib.scala 485:16] - assign rvclkhdr_552_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_553_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_553_io_en = _T_6553 | _T_6558; // @[el2_lib.scala 485:16] - assign rvclkhdr_553_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_io_en = io_ifc_fetch_req_f | exu_mp_valid; // @[lib.scala 371:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_1_io_en = _T_376 & io_ic_hit_f; // @[lib.scala 371:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_2_io_en = ~rs_hold; // @[lib.scala 371:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_3_io_en = rs_push | rs_pop; // @[lib.scala 371:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_4_io_en = rs_push | rs_pop; // @[lib.scala 371:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_5_io_en = rs_push | rs_pop; // @[lib.scala 371:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_6_io_en = rs_push | rs_pop; // @[lib.scala 371:17] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_7_io_en = rs_push | rs_pop; // @[lib.scala 371:17] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_8_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_8_io_en = rs_push | rs_pop; // @[lib.scala 371:17] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_9_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_9_io_en = _T_473 & io_ifu_bp_hit_taken_f; // @[lib.scala 371:17] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_10_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_10_io_en = _T_576 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_11_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_11_io_en = _T_579 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_12_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_12_io_en = _T_582 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_13_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_13_io_en = _T_585 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_14_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_14_io_en = _T_588 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_15_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_15_io_en = _T_591 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_16_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_16_io_en = _T_594 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_17_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_17_io_en = _T_597 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_18_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_18_io_en = _T_600 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_19_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_19_io_en = _T_603 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_19_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_20_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_20_io_en = _T_606 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_20_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_21_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_21_io_en = _T_609 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_21_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_22_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_22_io_en = _T_612 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_22_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_23_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_23_io_en = _T_615 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_23_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_24_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_24_io_en = _T_618 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_24_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_25_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_25_io_en = _T_621 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_25_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_26_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_26_io_en = _T_624 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_26_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_27_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_27_io_en = _T_627 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_27_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_28_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_28_io_en = _T_630 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_28_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_29_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_29_io_en = _T_633 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_29_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_30_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_30_io_en = _T_636 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_30_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_31_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_31_io_en = _T_639 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_31_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_32_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_32_io_en = _T_642 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_32_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_33_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_33_io_en = _T_645 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_33_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_34_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_34_io_en = _T_648 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_34_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_35_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_35_io_en = _T_651 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_35_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_36_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_36_io_en = _T_654 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_36_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_37_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_37_io_en = _T_657 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_37_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_38_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_38_io_en = _T_660 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_38_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_39_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_39_io_en = _T_663 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_39_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_40_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_40_io_en = _T_666 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_40_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_41_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_41_io_en = _T_669 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_41_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_42_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_42_io_en = _T_672 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_42_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_43_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_43_io_en = _T_675 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_43_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_44_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_44_io_en = _T_678 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_44_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_45_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_45_io_en = _T_681 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_45_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_46_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_46_io_en = _T_684 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_46_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_47_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_47_io_en = _T_687 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_47_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_48_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_48_io_en = _T_690 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_48_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_49_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_49_io_en = _T_693 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_49_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_50_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_50_io_en = _T_696 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_50_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_51_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_51_io_en = _T_699 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_51_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_52_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_52_io_en = _T_702 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_52_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_53_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_53_io_en = _T_705 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_53_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_54_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_54_io_en = _T_708 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_54_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_55_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_55_io_en = _T_711 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_55_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_56_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_56_io_en = _T_714 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_56_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_57_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_57_io_en = _T_717 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_57_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_58_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_58_io_en = _T_720 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_58_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_59_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_59_io_en = _T_723 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_59_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_60_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_60_io_en = _T_726 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_60_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_61_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_61_io_en = _T_729 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_61_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_62_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_62_io_en = _T_732 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_62_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_63_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_63_io_en = _T_735 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_63_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_64_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_64_io_en = _T_738 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_64_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_65_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_65_io_en = _T_741 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_65_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_66_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_66_io_en = _T_744 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_66_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_67_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_67_io_en = _T_747 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_67_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_68_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_68_io_en = _T_750 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_68_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_69_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_69_io_en = _T_753 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_69_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_70_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_70_io_en = _T_756 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_70_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_71_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_71_io_en = _T_759 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_71_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_72_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_72_io_en = _T_762 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_72_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_73_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_73_io_en = _T_765 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_73_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_74_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_74_io_en = _T_768 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_74_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_75_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_75_io_en = _T_771 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_75_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_76_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_76_io_en = _T_774 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_76_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_77_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_77_io_en = _T_777 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_77_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_78_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_78_io_en = _T_780 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_78_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_79_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_79_io_en = _T_783 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_79_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_80_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_80_io_en = _T_786 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_80_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_81_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_81_io_en = _T_789 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_81_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_82_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_82_io_en = _T_792 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_82_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_83_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_83_io_en = _T_795 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_83_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_84_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_84_io_en = _T_798 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_84_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_85_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_85_io_en = _T_801 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_85_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_86_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_86_io_en = _T_804 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_86_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_87_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_87_io_en = _T_807 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_87_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_88_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_88_io_en = _T_810 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_88_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_89_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_89_io_en = _T_813 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_89_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_90_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_90_io_en = _T_816 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_90_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_91_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_91_io_en = _T_819 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_91_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_92_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_92_io_en = _T_822 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_92_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_93_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_93_io_en = _T_825 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_93_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_94_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_94_io_en = _T_828 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_94_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_95_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_95_io_en = _T_831 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_95_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_96_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_96_io_en = _T_834 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_96_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_97_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_97_io_en = _T_837 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_97_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_98_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_98_io_en = _T_840 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_98_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_99_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_99_io_en = _T_843 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_99_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_100_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_100_io_en = _T_846 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_100_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_101_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_101_io_en = _T_849 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_101_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_102_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_102_io_en = _T_852 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_102_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_103_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_103_io_en = _T_855 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_103_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_104_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_104_io_en = _T_858 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_104_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_105_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_105_io_en = _T_861 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_105_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_106_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_106_io_en = _T_864 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_106_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_107_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_107_io_en = _T_867 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_107_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_108_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_108_io_en = _T_870 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_108_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_109_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_109_io_en = _T_873 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_109_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_110_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_110_io_en = _T_876 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_110_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_111_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_111_io_en = _T_879 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_111_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_112_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_112_io_en = _T_882 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_112_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_113_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_113_io_en = _T_885 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_113_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_114_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_114_io_en = _T_888 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_114_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_115_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_115_io_en = _T_891 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_115_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_116_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_116_io_en = _T_894 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_116_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_117_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_117_io_en = _T_897 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_117_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_118_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_118_io_en = _T_900 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_118_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_119_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_119_io_en = _T_903 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_119_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_120_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_120_io_en = _T_906 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_120_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_121_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_121_io_en = _T_909 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_121_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_122_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_122_io_en = _T_912 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_122_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_123_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_123_io_en = _T_915 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_123_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_124_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_124_io_en = _T_918 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_124_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_125_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_125_io_en = _T_921 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_125_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_126_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_126_io_en = _T_924 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_126_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_127_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_127_io_en = _T_927 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_127_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_128_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_128_io_en = _T_930 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_128_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_129_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_129_io_en = _T_933 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_129_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_130_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_130_io_en = _T_936 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_130_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_131_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_131_io_en = _T_939 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_131_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_132_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_132_io_en = _T_942 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_132_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_133_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_133_io_en = _T_945 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_133_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_134_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_134_io_en = _T_948 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_134_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_135_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_135_io_en = _T_951 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_135_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_136_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_136_io_en = _T_954 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_136_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_137_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_137_io_en = _T_957 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_137_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_138_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_138_io_en = _T_960 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_138_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_139_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_139_io_en = _T_963 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_139_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_140_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_140_io_en = _T_966 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_140_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_141_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_141_io_en = _T_969 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_141_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_142_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_142_io_en = _T_972 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_142_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_143_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_143_io_en = _T_975 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_143_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_144_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_144_io_en = _T_978 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_144_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_145_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_145_io_en = _T_981 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_145_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_146_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_146_io_en = _T_984 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_146_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_147_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_147_io_en = _T_987 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_147_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_148_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_148_io_en = _T_990 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_148_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_149_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_149_io_en = _T_993 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_149_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_150_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_150_io_en = _T_996 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_150_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_151_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_151_io_en = _T_999 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_151_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_152_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_152_io_en = _T_1002 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_152_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_153_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_153_io_en = _T_1005 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_153_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_154_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_154_io_en = _T_1008 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_154_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_155_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_155_io_en = _T_1011 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_155_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_156_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_156_io_en = _T_1014 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_156_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_157_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_157_io_en = _T_1017 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_157_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_158_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_158_io_en = _T_1020 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_158_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_159_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_159_io_en = _T_1023 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_159_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_160_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_160_io_en = _T_1026 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_160_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_161_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_161_io_en = _T_1029 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_161_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_162_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_162_io_en = _T_1032 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_162_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_163_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_163_io_en = _T_1035 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_163_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_164_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_164_io_en = _T_1038 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_164_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_165_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_165_io_en = _T_1041 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_165_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_166_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_166_io_en = _T_1044 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_166_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_167_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_167_io_en = _T_1047 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_167_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_168_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_168_io_en = _T_1050 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_168_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_169_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_169_io_en = _T_1053 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_169_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_170_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_170_io_en = _T_1056 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_170_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_171_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_171_io_en = _T_1059 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_171_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_172_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_172_io_en = _T_1062 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_172_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_173_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_173_io_en = _T_1065 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_173_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_174_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_174_io_en = _T_1068 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_174_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_175_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_175_io_en = _T_1071 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_175_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_176_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_176_io_en = _T_1074 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_176_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_177_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_177_io_en = _T_1077 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_177_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_178_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_178_io_en = _T_1080 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_178_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_179_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_179_io_en = _T_1083 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_179_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_180_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_180_io_en = _T_1086 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_180_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_181_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_181_io_en = _T_1089 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_181_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_182_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_182_io_en = _T_1092 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_182_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_183_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_183_io_en = _T_1095 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_183_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_184_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_184_io_en = _T_1098 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_184_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_185_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_185_io_en = _T_1101 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_185_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_186_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_186_io_en = _T_1104 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_186_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_187_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_187_io_en = _T_1107 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_187_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_188_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_188_io_en = _T_1110 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_188_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_189_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_189_io_en = _T_1113 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_189_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_190_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_190_io_en = _T_1116 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_190_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_191_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_191_io_en = _T_1119 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_191_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_192_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_192_io_en = _T_1122 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_192_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_193_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_193_io_en = _T_1125 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_193_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_194_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_194_io_en = _T_1128 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_194_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_195_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_195_io_en = _T_1131 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_195_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_196_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_196_io_en = _T_1134 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_196_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_197_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_197_io_en = _T_1137 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_197_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_198_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_198_io_en = _T_1140 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_198_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_199_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_199_io_en = _T_1143 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_199_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_200_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_200_io_en = _T_1146 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_200_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_201_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_201_io_en = _T_1149 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_201_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_202_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_202_io_en = _T_1152 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_202_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_203_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_203_io_en = _T_1155 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_203_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_204_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_204_io_en = _T_1158 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_204_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_205_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_205_io_en = _T_1161 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_205_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_206_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_206_io_en = _T_1164 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_206_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_207_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_207_io_en = _T_1167 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_207_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_208_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_208_io_en = _T_1170 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_208_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_209_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_209_io_en = _T_1173 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_209_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_210_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_210_io_en = _T_1176 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_210_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_211_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_211_io_en = _T_1179 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_211_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_212_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_212_io_en = _T_1182 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_212_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_213_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_213_io_en = _T_1185 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_213_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_214_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_214_io_en = _T_1188 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_214_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_215_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_215_io_en = _T_1191 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_215_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_216_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_216_io_en = _T_1194 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_216_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_217_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_217_io_en = _T_1197 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_217_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_218_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_218_io_en = _T_1200 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_218_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_219_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_219_io_en = _T_1203 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_219_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_220_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_220_io_en = _T_1206 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_220_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_221_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_221_io_en = _T_1209 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_221_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_222_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_222_io_en = _T_1212 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_222_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_223_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_223_io_en = _T_1215 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_223_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_224_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_224_io_en = _T_1218 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_224_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_225_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_225_io_en = _T_1221 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_225_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_226_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_226_io_en = _T_1224 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_226_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_227_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_227_io_en = _T_1227 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_227_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_228_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_228_io_en = _T_1230 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_228_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_229_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_229_io_en = _T_1233 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_229_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_230_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_230_io_en = _T_1236 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_230_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_231_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_231_io_en = _T_1239 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_231_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_232_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_232_io_en = _T_1242 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_232_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_233_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_233_io_en = _T_1245 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_233_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_234_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_234_io_en = _T_1248 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_234_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_235_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_235_io_en = _T_1251 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_235_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_236_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_236_io_en = _T_1254 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_236_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_237_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_237_io_en = _T_1257 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_237_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_238_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_238_io_en = _T_1260 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_238_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_239_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_239_io_en = _T_1263 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_239_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_240_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_240_io_en = _T_1266 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_240_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_241_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_241_io_en = _T_1269 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_241_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_242_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_242_io_en = _T_1272 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_242_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_243_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_243_io_en = _T_1275 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_243_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_244_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_244_io_en = _T_1278 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_244_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_245_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_245_io_en = _T_1281 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_245_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_246_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_246_io_en = _T_1284 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_246_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_247_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_247_io_en = _T_1287 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_247_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_248_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_248_io_en = _T_1290 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_248_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_249_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_249_io_en = _T_1293 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_249_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_250_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_250_io_en = _T_1296 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_250_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_251_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_251_io_en = _T_1299 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_251_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_252_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_252_io_en = _T_1302 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_252_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_253_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_253_io_en = _T_1305 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_253_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_254_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_254_io_en = _T_1308 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_254_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_255_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_255_io_en = _T_1311 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_255_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_256_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_256_io_en = _T_1314 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_256_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_257_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_257_io_en = _T_1317 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_257_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_258_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_258_io_en = _T_1320 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_258_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_259_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_259_io_en = _T_1323 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_259_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_260_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_260_io_en = _T_1326 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_260_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_261_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_261_io_en = _T_1329 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_261_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_262_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_262_io_en = _T_1332 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_262_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_263_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_263_io_en = _T_1335 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_263_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_264_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_264_io_en = _T_1338 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_264_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_265_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_265_io_en = _T_1341 & btb_wr_en_way0; // @[lib.scala 371:17] + assign rvclkhdr_265_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_266_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_266_io_en = _T_576 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_266_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_267_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_267_io_en = _T_579 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_267_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_268_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_268_io_en = _T_582 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_268_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_269_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_269_io_en = _T_585 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_269_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_270_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_270_io_en = _T_588 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_270_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_271_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_271_io_en = _T_591 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_271_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_272_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_272_io_en = _T_594 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_272_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_273_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_273_io_en = _T_597 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_273_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_274_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_274_io_en = _T_600 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_274_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_275_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_275_io_en = _T_603 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_275_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_276_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_276_io_en = _T_606 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_276_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_277_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_277_io_en = _T_609 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_277_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_278_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_278_io_en = _T_612 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_278_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_279_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_279_io_en = _T_615 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_279_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_280_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_280_io_en = _T_618 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_280_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_281_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_281_io_en = _T_621 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_281_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_282_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_282_io_en = _T_624 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_282_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_283_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_283_io_en = _T_627 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_283_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_284_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_284_io_en = _T_630 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_284_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_285_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_285_io_en = _T_633 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_285_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_286_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_286_io_en = _T_636 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_286_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_287_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_287_io_en = _T_639 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_287_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_288_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_288_io_en = _T_642 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_288_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_289_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_289_io_en = _T_645 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_289_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_290_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_290_io_en = _T_648 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_290_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_291_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_291_io_en = _T_651 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_291_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_292_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_292_io_en = _T_654 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_292_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_293_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_293_io_en = _T_657 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_293_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_294_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_294_io_en = _T_660 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_294_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_295_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_295_io_en = _T_663 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_295_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_296_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_296_io_en = _T_666 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_296_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_297_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_297_io_en = _T_669 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_297_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_298_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_298_io_en = _T_672 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_298_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_299_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_299_io_en = _T_675 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_299_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_300_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_300_io_en = _T_678 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_300_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_301_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_301_io_en = _T_681 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_301_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_302_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_302_io_en = _T_684 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_302_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_303_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_303_io_en = _T_687 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_303_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_304_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_304_io_en = _T_690 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_304_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_305_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_305_io_en = _T_693 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_305_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_306_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_306_io_en = _T_696 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_306_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_307_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_307_io_en = _T_699 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_307_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_308_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_308_io_en = _T_702 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_308_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_309_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_309_io_en = _T_705 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_309_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_310_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_310_io_en = _T_708 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_310_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_311_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_311_io_en = _T_711 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_311_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_312_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_312_io_en = _T_714 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_312_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_313_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_313_io_en = _T_717 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_313_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_314_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_314_io_en = _T_720 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_314_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_315_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_315_io_en = _T_723 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_315_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_316_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_316_io_en = _T_726 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_316_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_317_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_317_io_en = _T_729 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_317_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_318_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_318_io_en = _T_732 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_318_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_319_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_319_io_en = _T_735 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_319_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_320_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_320_io_en = _T_738 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_320_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_321_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_321_io_en = _T_741 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_321_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_322_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_322_io_en = _T_744 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_322_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_323_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_323_io_en = _T_747 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_323_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_324_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_324_io_en = _T_750 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_324_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_325_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_325_io_en = _T_753 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_325_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_326_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_326_io_en = _T_756 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_326_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_327_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_327_io_en = _T_759 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_327_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_328_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_328_io_en = _T_762 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_328_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_329_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_329_io_en = _T_765 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_329_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_330_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_330_io_en = _T_768 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_330_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_331_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_331_io_en = _T_771 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_331_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_332_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_332_io_en = _T_774 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_332_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_333_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_333_io_en = _T_777 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_333_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_334_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_334_io_en = _T_780 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_334_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_335_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_335_io_en = _T_783 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_335_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_336_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_336_io_en = _T_786 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_336_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_337_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_337_io_en = _T_789 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_337_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_338_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_338_io_en = _T_792 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_338_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_339_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_339_io_en = _T_795 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_339_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_340_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_340_io_en = _T_798 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_340_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_341_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_341_io_en = _T_801 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_341_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_342_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_342_io_en = _T_804 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_342_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_343_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_343_io_en = _T_807 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_343_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_344_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_344_io_en = _T_810 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_344_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_345_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_345_io_en = _T_813 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_345_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_346_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_346_io_en = _T_816 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_346_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_347_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_347_io_en = _T_819 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_347_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_348_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_348_io_en = _T_822 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_348_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_349_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_349_io_en = _T_825 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_349_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_350_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_350_io_en = _T_828 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_350_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_351_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_351_io_en = _T_831 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_351_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_352_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_352_io_en = _T_834 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_352_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_353_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_353_io_en = _T_837 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_353_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_354_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_354_io_en = _T_840 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_354_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_355_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_355_io_en = _T_843 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_355_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_356_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_356_io_en = _T_846 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_356_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_357_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_357_io_en = _T_849 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_357_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_358_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_358_io_en = _T_852 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_358_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_359_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_359_io_en = _T_855 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_359_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_360_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_360_io_en = _T_858 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_360_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_361_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_361_io_en = _T_861 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_361_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_362_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_362_io_en = _T_864 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_362_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_363_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_363_io_en = _T_867 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_363_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_364_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_364_io_en = _T_870 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_364_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_365_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_365_io_en = _T_873 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_365_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_366_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_366_io_en = _T_876 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_366_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_367_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_367_io_en = _T_879 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_367_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_368_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_368_io_en = _T_882 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_368_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_369_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_369_io_en = _T_885 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_369_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_370_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_370_io_en = _T_888 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_370_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_371_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_371_io_en = _T_891 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_371_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_372_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_372_io_en = _T_894 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_372_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_373_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_373_io_en = _T_897 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_373_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_374_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_374_io_en = _T_900 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_374_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_375_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_375_io_en = _T_903 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_375_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_376_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_376_io_en = _T_906 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_376_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_377_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_377_io_en = _T_909 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_377_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_378_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_378_io_en = _T_912 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_378_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_379_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_379_io_en = _T_915 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_379_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_380_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_380_io_en = _T_918 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_380_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_381_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_381_io_en = _T_921 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_381_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_382_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_382_io_en = _T_924 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_382_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_383_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_383_io_en = _T_927 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_383_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_384_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_384_io_en = _T_930 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_384_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_385_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_385_io_en = _T_933 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_385_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_386_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_386_io_en = _T_936 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_386_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_387_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_387_io_en = _T_939 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_387_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_388_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_388_io_en = _T_942 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_388_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_389_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_389_io_en = _T_945 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_389_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_390_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_390_io_en = _T_948 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_390_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_391_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_391_io_en = _T_951 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_391_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_392_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_392_io_en = _T_954 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_392_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_393_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_393_io_en = _T_957 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_393_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_394_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_394_io_en = _T_960 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_394_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_395_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_395_io_en = _T_963 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_395_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_396_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_396_io_en = _T_966 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_396_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_397_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_397_io_en = _T_969 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_397_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_398_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_398_io_en = _T_972 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_398_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_399_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_399_io_en = _T_975 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_399_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_400_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_400_io_en = _T_978 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_400_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_401_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_401_io_en = _T_981 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_401_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_402_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_402_io_en = _T_984 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_402_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_403_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_403_io_en = _T_987 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_403_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_404_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_404_io_en = _T_990 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_404_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_405_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_405_io_en = _T_993 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_405_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_406_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_406_io_en = _T_996 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_406_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_407_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_407_io_en = _T_999 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_407_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_408_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_408_io_en = _T_1002 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_408_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_409_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_409_io_en = _T_1005 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_409_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_410_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_410_io_en = _T_1008 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_410_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_411_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_411_io_en = _T_1011 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_411_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_412_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_412_io_en = _T_1014 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_412_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_413_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_413_io_en = _T_1017 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_413_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_414_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_414_io_en = _T_1020 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_414_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_415_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_415_io_en = _T_1023 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_415_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_416_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_416_io_en = _T_1026 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_416_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_417_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_417_io_en = _T_1029 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_417_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_418_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_418_io_en = _T_1032 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_418_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_419_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_419_io_en = _T_1035 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_419_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_420_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_420_io_en = _T_1038 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_420_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_421_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_421_io_en = _T_1041 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_421_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_422_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_422_io_en = _T_1044 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_422_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_423_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_423_io_en = _T_1047 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_423_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_424_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_424_io_en = _T_1050 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_424_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_425_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_425_io_en = _T_1053 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_425_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_426_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_426_io_en = _T_1056 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_426_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_427_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_427_io_en = _T_1059 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_427_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_428_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_428_io_en = _T_1062 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_428_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_429_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_429_io_en = _T_1065 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_429_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_430_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_430_io_en = _T_1068 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_430_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_431_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_431_io_en = _T_1071 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_431_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_432_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_432_io_en = _T_1074 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_432_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_433_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_433_io_en = _T_1077 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_433_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_434_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_434_io_en = _T_1080 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_434_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_435_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_435_io_en = _T_1083 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_435_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_436_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_436_io_en = _T_1086 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_436_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_437_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_437_io_en = _T_1089 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_437_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_438_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_438_io_en = _T_1092 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_438_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_439_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_439_io_en = _T_1095 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_439_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_440_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_440_io_en = _T_1098 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_440_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_441_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_441_io_en = _T_1101 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_441_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_442_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_442_io_en = _T_1104 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_442_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_443_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_443_io_en = _T_1107 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_443_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_444_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_444_io_en = _T_1110 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_444_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_445_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_445_io_en = _T_1113 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_445_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_446_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_446_io_en = _T_1116 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_446_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_447_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_447_io_en = _T_1119 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_447_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_448_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_448_io_en = _T_1122 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_448_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_449_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_449_io_en = _T_1125 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_449_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_450_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_450_io_en = _T_1128 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_450_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_451_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_451_io_en = _T_1131 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_451_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_452_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_452_io_en = _T_1134 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_452_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_453_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_453_io_en = _T_1137 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_453_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_454_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_454_io_en = _T_1140 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_454_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_455_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_455_io_en = _T_1143 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_455_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_456_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_456_io_en = _T_1146 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_456_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_457_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_457_io_en = _T_1149 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_457_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_458_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_458_io_en = _T_1152 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_458_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_459_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_459_io_en = _T_1155 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_459_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_460_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_460_io_en = _T_1158 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_460_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_461_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_461_io_en = _T_1161 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_461_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_462_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_462_io_en = _T_1164 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_462_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_463_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_463_io_en = _T_1167 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_463_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_464_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_464_io_en = _T_1170 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_464_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_465_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_465_io_en = _T_1173 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_465_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_466_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_466_io_en = _T_1176 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_466_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_467_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_467_io_en = _T_1179 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_467_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_468_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_468_io_en = _T_1182 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_468_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_469_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_469_io_en = _T_1185 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_469_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_470_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_470_io_en = _T_1188 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_470_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_471_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_471_io_en = _T_1191 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_471_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_472_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_472_io_en = _T_1194 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_472_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_473_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_473_io_en = _T_1197 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_473_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_474_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_474_io_en = _T_1200 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_474_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_475_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_475_io_en = _T_1203 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_475_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_476_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_476_io_en = _T_1206 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_476_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_477_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_477_io_en = _T_1209 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_477_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_478_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_478_io_en = _T_1212 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_478_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_479_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_479_io_en = _T_1215 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_479_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_480_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_480_io_en = _T_1218 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_480_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_481_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_481_io_en = _T_1221 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_481_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_482_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_482_io_en = _T_1224 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_482_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_483_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_483_io_en = _T_1227 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_483_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_484_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_484_io_en = _T_1230 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_484_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_485_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_485_io_en = _T_1233 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_485_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_486_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_486_io_en = _T_1236 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_486_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_487_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_487_io_en = _T_1239 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_487_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_488_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_488_io_en = _T_1242 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_488_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_489_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_489_io_en = _T_1245 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_489_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_490_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_490_io_en = _T_1248 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_490_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_491_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_491_io_en = _T_1251 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_491_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_492_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_492_io_en = _T_1254 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_492_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_493_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_493_io_en = _T_1257 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_493_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_494_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_494_io_en = _T_1260 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_494_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_495_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_495_io_en = _T_1263 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_495_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_496_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_496_io_en = _T_1266 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_496_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_497_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_497_io_en = _T_1269 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_497_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_498_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_498_io_en = _T_1272 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_498_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_499_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_499_io_en = _T_1275 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_499_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_500_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_500_io_en = _T_1278 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_500_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_501_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_501_io_en = _T_1281 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_501_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_502_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_502_io_en = _T_1284 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_502_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_503_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_503_io_en = _T_1287 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_503_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_504_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_504_io_en = _T_1290 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_504_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_505_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_505_io_en = _T_1293 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_505_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_506_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_506_io_en = _T_1296 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_506_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_507_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_507_io_en = _T_1299 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_507_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_508_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_508_io_en = _T_1302 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_508_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_509_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_509_io_en = _T_1305 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_509_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_510_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_510_io_en = _T_1308 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_510_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_511_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_511_io_en = _T_1311 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_511_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_512_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_512_io_en = _T_1314 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_512_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_513_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_513_io_en = _T_1317 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_513_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_514_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_514_io_en = _T_1320 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_514_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_515_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_515_io_en = _T_1323 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_515_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_516_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_516_io_en = _T_1326 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_516_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_517_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_517_io_en = _T_1329 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_517_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_518_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_518_io_en = _T_1332 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_518_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_519_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_519_io_en = _T_1335 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_519_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_520_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_520_io_en = _T_1338 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_520_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_521_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_521_io_en = _T_1341 & btb_wr_en_way1; // @[lib.scala 371:17] + assign rvclkhdr_521_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_522_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_522_io_en = _T_6212 | _T_6217; // @[lib.scala 345:16] + assign rvclkhdr_522_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_523_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_523_io_en = _T_6223 | _T_6228; // @[lib.scala 345:16] + assign rvclkhdr_523_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_524_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_524_io_en = _T_6234 | _T_6239; // @[lib.scala 345:16] + assign rvclkhdr_524_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_525_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_525_io_en = _T_6245 | _T_6250; // @[lib.scala 345:16] + assign rvclkhdr_525_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_526_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_526_io_en = _T_6256 | _T_6261; // @[lib.scala 345:16] + assign rvclkhdr_526_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_527_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_527_io_en = _T_6267 | _T_6272; // @[lib.scala 345:16] + assign rvclkhdr_527_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_528_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_528_io_en = _T_6278 | _T_6283; // @[lib.scala 345:16] + assign rvclkhdr_528_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_529_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_529_io_en = _T_6289 | _T_6294; // @[lib.scala 345:16] + assign rvclkhdr_529_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_530_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_530_io_en = _T_6300 | _T_6305; // @[lib.scala 345:16] + assign rvclkhdr_530_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_531_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_531_io_en = _T_6311 | _T_6316; // @[lib.scala 345:16] + assign rvclkhdr_531_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_532_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_532_io_en = _T_6322 | _T_6327; // @[lib.scala 345:16] + assign rvclkhdr_532_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_533_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_533_io_en = _T_6333 | _T_6338; // @[lib.scala 345:16] + assign rvclkhdr_533_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_534_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_534_io_en = _T_6344 | _T_6349; // @[lib.scala 345:16] + assign rvclkhdr_534_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_535_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_535_io_en = _T_6355 | _T_6360; // @[lib.scala 345:16] + assign rvclkhdr_535_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_536_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_536_io_en = _T_6366 | _T_6371; // @[lib.scala 345:16] + assign rvclkhdr_536_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_537_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_537_io_en = _T_6377 | _T_6382; // @[lib.scala 345:16] + assign rvclkhdr_537_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_538_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_538_io_en = _T_6388 | _T_6393; // @[lib.scala 345:16] + assign rvclkhdr_538_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_539_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_539_io_en = _T_6399 | _T_6404; // @[lib.scala 345:16] + assign rvclkhdr_539_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_540_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_540_io_en = _T_6410 | _T_6415; // @[lib.scala 345:16] + assign rvclkhdr_540_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_541_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_541_io_en = _T_6421 | _T_6426; // @[lib.scala 345:16] + assign rvclkhdr_541_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_542_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_542_io_en = _T_6432 | _T_6437; // @[lib.scala 345:16] + assign rvclkhdr_542_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_543_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_543_io_en = _T_6443 | _T_6448; // @[lib.scala 345:16] + assign rvclkhdr_543_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_544_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_544_io_en = _T_6454 | _T_6459; // @[lib.scala 345:16] + assign rvclkhdr_544_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_545_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_545_io_en = _T_6465 | _T_6470; // @[lib.scala 345:16] + assign rvclkhdr_545_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_546_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_546_io_en = _T_6476 | _T_6481; // @[lib.scala 345:16] + assign rvclkhdr_546_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_547_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_547_io_en = _T_6487 | _T_6492; // @[lib.scala 345:16] + assign rvclkhdr_547_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_548_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_548_io_en = _T_6498 | _T_6503; // @[lib.scala 345:16] + assign rvclkhdr_548_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_549_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_549_io_en = _T_6509 | _T_6514; // @[lib.scala 345:16] + assign rvclkhdr_549_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_550_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_550_io_en = _T_6520 | _T_6525; // @[lib.scala 345:16] + assign rvclkhdr_550_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_551_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_551_io_en = _T_6531 | _T_6536; // @[lib.scala 345:16] + assign rvclkhdr_551_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_552_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_552_io_en = _T_6542 | _T_6547; // @[lib.scala 345:16] + assign rvclkhdr_552_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_553_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_553_io_en = _T_6553 | _T_6558; // @[lib.scala 345:16] + assign rvclkhdr_553_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -43256,54 +43256,54 @@ module ifu_aln_ctl( reg [63:0] _RAND_19; reg [63:0] _RAND_20; `endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_8_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_8_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_9_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_9_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_10_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_10_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_11_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_11_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_io_en; // @[lib.scala 368:23] + wire rvclkhdr_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_en; // @[lib.scala 368:23] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_en; // @[lib.scala 368:23] + wire rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_en; // @[lib.scala 368:23] + wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_en; // @[lib.scala 368:23] + wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_5_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_en; // @[lib.scala 368:23] + wire rvclkhdr_5_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_6_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_6_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_6_io_en; // @[lib.scala 368:23] + wire rvclkhdr_6_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_7_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_7_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_7_io_en; // @[lib.scala 368:23] + wire rvclkhdr_7_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_8_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_8_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_8_io_en; // @[lib.scala 368:23] + wire rvclkhdr_8_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_9_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_9_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_9_io_en; // @[lib.scala 368:23] + wire rvclkhdr_9_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_10_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_10_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_10_io_en; // @[lib.scala 368:23] + wire rvclkhdr_10_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_11_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_11_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_11_io_en; // @[lib.scala 368:23] + wire rvclkhdr_11_io_scan_mode; // @[lib.scala 368:23] wire [15:0] decompressed_io_din; // @[ifu_aln_ctl.scala 352:28] wire [31:0] decompressed_io_dout; // @[ifu_aln_ctl.scala 352:28] reg error_stall; // @[ifu_aln_ctl.scala 102:51] @@ -43330,11 +43330,11 @@ module ifu_aln_ctl( wire _T_202 = ~q0ptr; // @[ifu_aln_ctl.scala 175:26] wire [1:0] q0sel = {q0ptr,_T_202}; // @[Cat.scala 29:58] wire [2:0] qren = {_T_188,_T_187,_T_186}; // @[Cat.scala 29:58] - reg [31:0] q1; // @[el2_lib.scala 514:16] - reg [31:0] q0; // @[el2_lib.scala 514:16] + reg [31:0] q1; // @[lib.scala 374:16] + reg [31:0] q0; // @[lib.scala 374:16] wire [63:0] _T_479 = {q1,q0}; // @[Cat.scala 29:58] wire [63:0] _T_486 = qren[0] ? _T_479 : 64'h0; // @[Mux.scala 27:72] - reg [31:0] q2; // @[el2_lib.scala 514:16] + reg [31:0] q2; // @[lib.scala 374:16] wire [63:0] _T_482 = {q2,q1}; // @[Cat.scala 29:58] wire [63:0] _T_487 = qren[1] ? _T_482 : 64'h0; // @[Mux.scala 27:72] wire [63:0] _T_489 = _T_486 | _T_487; // @[Mux.scala 27:72] @@ -43394,7 +43394,7 @@ module ifu_aln_ctl( wire _T_357 = _T_355 & _T_356; // @[ifu_aln_ctl.scala 257:50] wire _T_358 = _T_357 & ifvalid; // @[ifu_aln_ctl.scala 257:62] wire fetch_to_f2 = _T_354 | _T_358; // @[ifu_aln_ctl.scala 256:74] - reg [30:0] f2pc; // @[el2_lib.scala 514:16] + reg [30:0] f2pc; // @[lib.scala 374:16] wire _T_335 = ~sf1_valid; // @[ifu_aln_ctl.scala 252:39] wire _T_336 = _T_351 & _T_335; // @[ifu_aln_ctl.scala 252:37] wire _T_337 = _T_336 & f2_valid; // @[ifu_aln_ctl.scala 252:50] @@ -43407,13 +43407,13 @@ module ifu_aln_ctl( wire _T_349 = _T_348 & ifvalid; // @[ifu_aln_ctl.scala 254:62] wire fetch_to_f1 = _T_344 | _T_349; // @[ifu_aln_ctl.scala 253:74] wire _T_25 = fetch_to_f1 | _T_353; // @[ifu_aln_ctl.scala 134:33] - reg [30:0] f1pc; // @[el2_lib.scala 514:16] + reg [30:0] f1pc; // @[lib.scala 374:16] wire _T_332 = _T_336 & _T_356; // @[ifu_aln_ctl.scala 251:50] wire fetch_to_f0 = _T_332 & ifvalid; // @[ifu_aln_ctl.scala 251:62] wire _T_27 = fetch_to_f0 | _T_337; // @[ifu_aln_ctl.scala 135:33] wire _T_28 = _T_27 | _T_352; // @[ifu_aln_ctl.scala 135:47] wire _T_29 = _T_28 | shift_2B; // @[ifu_aln_ctl.scala 135:61] - reg [30:0] f0pc; // @[el2_lib.scala 514:16] + reg [30:0] f0pc; // @[lib.scala 374:16] wire _T_35 = wrptr == 2'h2; // @[ifu_aln_ctl.scala 139:21] wire _T_36 = _T_35 & ifvalid; // @[ifu_aln_ctl.scala 139:29] wire _T_37 = wrptr == 2'h1; // @[ifu_aln_ctl.scala 139:46] @@ -43421,12 +43421,12 @@ module ifu_aln_ctl( wire _T_39 = wrptr == 2'h0; // @[ifu_aln_ctl.scala 139:71] wire _T_40 = _T_39 & ifvalid; // @[ifu_aln_ctl.scala 139:79] wire [2:0] qwen = {_T_36,_T_38,_T_40}; // @[Cat.scala 29:58] - reg [11:0] brdata2; // @[el2_lib.scala 514:16] - reg [11:0] brdata1; // @[el2_lib.scala 514:16] - reg [11:0] brdata0; // @[el2_lib.scala 514:16] - reg [54:0] misc2; // @[el2_lib.scala 514:16] - reg [54:0] misc1; // @[el2_lib.scala 514:16] - reg [54:0] misc0; // @[el2_lib.scala 514:16] + reg [11:0] brdata2; // @[lib.scala 374:16] + reg [11:0] brdata1; // @[lib.scala 374:16] + reg [11:0] brdata0; // @[lib.scala 374:16] + reg [54:0] misc2; // @[lib.scala 374:16] + reg [54:0] misc1; // @[lib.scala 374:16] + reg [54:0] misc0; // @[lib.scala 374:16] wire _T_44 = qren[0] & io_ifu_fb_consume1; // @[ifu_aln_ctl.scala 143:34] wire _T_46 = _T_44 & _T_1; // @[ifu_aln_ctl.scala 143:55] wire _T_49 = qren[1] & io_ifu_fb_consume1; // @[ifu_aln_ctl.scala 144:14] @@ -43658,14 +43658,14 @@ module ifu_aln_ctl( wire _T_691 = first2B & aligndbecc[0]; // @[Mux.scala 27:72] wire [31:0] _T_696 = first4B ? aligndata : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_697 = first2B ? decompressed_io_dout : 32'h0; // @[Mux.scala 27:72] - wire [7:0] _T_702 = f0pc[8:1] ^ f0pc[16:9]; // @[el2_lib.scala 191:47] - wire [7:0] firstpc_hash = _T_702 ^ f0pc[24:17]; // @[el2_lib.scala 191:85] - wire [7:0] _T_706 = secondpc[8:1] ^ secondpc[16:9]; // @[el2_lib.scala 191:47] - wire [7:0] secondpc_hash = _T_706 ^ secondpc[24:17]; // @[el2_lib.scala 191:85] - wire [4:0] _T_712 = f0pc[13:9] ^ f0pc[18:14]; // @[el2_lib.scala 182:111] - wire [4:0] firstbrtag_hash = _T_712 ^ f0pc[23:19]; // @[el2_lib.scala 182:111] - wire [4:0] _T_717 = secondpc[13:9] ^ secondpc[18:14]; // @[el2_lib.scala 182:111] - wire [4:0] secondbrtag_hash = _T_717 ^ secondpc[23:19]; // @[el2_lib.scala 182:111] + wire [7:0] _T_702 = f0pc[8:1] ^ f0pc[16:9]; // @[lib.scala 51:47] + wire [7:0] firstpc_hash = _T_702 ^ f0pc[24:17]; // @[lib.scala 51:85] + wire [7:0] _T_706 = secondpc[8:1] ^ secondpc[16:9]; // @[lib.scala 51:47] + wire [7:0] secondpc_hash = _T_706 ^ secondpc[24:17]; // @[lib.scala 51:85] + wire [4:0] _T_712 = f0pc[13:9] ^ f0pc[18:14]; // @[lib.scala 42:111] + wire [4:0] firstbrtag_hash = _T_712 ^ f0pc[23:19]; // @[lib.scala 42:111] + wire [4:0] _T_717 = secondpc[13:9] ^ secondpc[18:14]; // @[lib.scala 42:111] + wire [4:0] secondbrtag_hash = _T_717 ^ secondpc[23:19]; // @[lib.scala 42:111] wire _T_719 = first2B & alignbrend[0]; // @[ifu_aln_ctl.scala 365:45] wire _T_721 = first4B & alignbrend[1]; // @[ifu_aln_ctl.scala 365:73] wire _T_722 = _T_719 | _T_721; // @[ifu_aln_ctl.scala 365:62] @@ -43688,73 +43688,73 @@ module ifu_aln_ctl( wire _T_770 = ~i0_brp_pc4; // @[ifu_aln_ctl.scala 385:139] wire _T_771 = io_dec_aln_aln_ib_i0_brp_valid & _T_770; // @[ifu_aln_ctl.scala 385:137] wire _T_772 = _T_771 & first4B; // @[ifu_aln_ctl.scala 385:151] - rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en), .io_scan_mode(rvclkhdr_io_scan_mode) ); - rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_1 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_1_io_l1clk), .io_clk(rvclkhdr_1_io_clk), .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_2_io_l1clk), .io_clk(rvclkhdr_2_io_clk), .io_en(rvclkhdr_2_io_en), .io_scan_mode(rvclkhdr_2_io_scan_mode) ); - rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_3_io_l1clk), .io_clk(rvclkhdr_3_io_clk), .io_en(rvclkhdr_3_io_en), .io_scan_mode(rvclkhdr_3_io_scan_mode) ); - rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_4_io_l1clk), .io_clk(rvclkhdr_4_io_clk), .io_en(rvclkhdr_4_io_en), .io_scan_mode(rvclkhdr_4_io_scan_mode) ); - rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_5 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_5_io_l1clk), .io_clk(rvclkhdr_5_io_clk), .io_en(rvclkhdr_5_io_en), .io_scan_mode(rvclkhdr_5_io_scan_mode) ); - rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_6 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_6_io_l1clk), .io_clk(rvclkhdr_6_io_clk), .io_en(rvclkhdr_6_io_en), .io_scan_mode(rvclkhdr_6_io_scan_mode) ); - rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_7 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_7_io_l1clk), .io_clk(rvclkhdr_7_io_clk), .io_en(rvclkhdr_7_io_en), .io_scan_mode(rvclkhdr_7_io_scan_mode) ); - rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_8 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_8_io_l1clk), .io_clk(rvclkhdr_8_io_clk), .io_en(rvclkhdr_8_io_en), .io_scan_mode(rvclkhdr_8_io_scan_mode) ); - rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_9 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_9_io_l1clk), .io_clk(rvclkhdr_9_io_clk), .io_en(rvclkhdr_9_io_en), .io_scan_mode(rvclkhdr_9_io_scan_mode) ); - rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_10 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_10_io_l1clk), .io_clk(rvclkhdr_10_io_clk), .io_en(rvclkhdr_10_io_en), .io_scan_mode(rvclkhdr_10_io_scan_mode) ); - rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_11 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_11_io_l1clk), .io_clk(rvclkhdr_11_io_clk), .io_en(rvclkhdr_11_io_en), @@ -43787,42 +43787,42 @@ module ifu_aln_ctl( assign io_dec_aln_ifu_pmu_instr_aligned = io_dec_aln_aln_dec_dec_i0_decode_d & _T_785; // @[ifu_aln_ctl.scala 397:36] assign io_ifu_fb_consume1 = _T_312 & _T_1; // @[ifu_aln_ctl.scala 241:22] assign io_ifu_fb_consume2 = _T_315 & _T_1; // @[ifu_aln_ctl.scala 242:22] - assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_io_en = _T_354 | _T_358; // @[el2_lib.scala 511:17] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_1_io_en = _T_25 | f1_shift_2B; // @[el2_lib.scala 511:17] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_2_io_en = _T_29 | shift_4B; // @[el2_lib.scala 511:17] - assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_3_io_en = qwen[2]; // @[el2_lib.scala 511:17] - assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_4_io_en = qwen[1]; // @[el2_lib.scala 511:17] - assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_5_io_en = qwen[0]; // @[el2_lib.scala 511:17] - assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_6_io_en = qwen[2]; // @[el2_lib.scala 511:17] - assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_7_io_en = qwen[1]; // @[el2_lib.scala 511:17] - assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_8_io_en = qwen[0]; // @[el2_lib.scala 511:17] - assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_9_io_en = qwen[2]; // @[el2_lib.scala 511:17] - assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_10_io_en = qwen[1]; // @[el2_lib.scala 511:17] - assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_11_io_en = qwen[0]; // @[el2_lib.scala 511:17] - assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_io_en = _T_354 | _T_358; // @[lib.scala 371:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_1_io_en = _T_25 | f1_shift_2B; // @[lib.scala 371:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_2_io_en = _T_29 | shift_4B; // @[lib.scala 371:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_3_io_en = qwen[2]; // @[lib.scala 371:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_4_io_en = qwen[1]; // @[lib.scala 371:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_5_io_en = qwen[0]; // @[lib.scala 371:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_6_io_en = qwen[2]; // @[lib.scala 371:17] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_7_io_en = qwen[1]; // @[lib.scala 371:17] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_8_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_8_io_en = qwen[0]; // @[lib.scala 371:17] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_9_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_9_io_en = qwen[2]; // @[lib.scala 371:17] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_10_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_10_io_en = qwen[1]; // @[lib.scala 371:17] + assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_11_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_11_io_en = qwen[0]; // @[lib.scala 371:17] + assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign decompressed_io_din = aligndata[15:0]; // @[ifu_aln_ctl.scala 393:23] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE @@ -44158,10 +44158,10 @@ module ifu_ifc_ctl( reg [31:0] _RAND_5; reg [31:0] _RAND_6; `endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_io_en; // @[lib.scala 368:23] + wire rvclkhdr_io_scan_mode; // @[lib.scala 368:23] reg dma_iccm_stall_any_f; // @[ifu_ifc_ctl.scala 63:58] wire dma_stall = io_ic_dma_active | dma_iccm_stall_any_f; // @[ifu_ifc_ctl.scala 62:36] reg miss_a; // @[ifu_ifc_ctl.scala 65:44] @@ -44264,8 +44264,8 @@ module ifu_ifc_ctl( wire _T_139 = _T_138 | dma_stall; // @[ifu_ifc_ctl.scala 131:84] wire _T_140 = io_ifc_fetch_req_bf_raw & _T_139; // @[ifu_ifc_ctl.scala 130:68] wire [31:0] _T_142 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58] - wire iccm_acc_in_region_bf = _T_142[31:28] == 4'he; // @[el2_lib.scala 224:47] - wire iccm_acc_in_range_bf = _T_142[31:16] == 16'hee00; // @[el2_lib.scala 227:29] + wire iccm_acc_in_region_bf = _T_142[31:28] == 4'he; // @[lib.scala 84:47] + wire iccm_acc_in_range_bf = _T_142[31:16] == 16'hee00; // @[lib.scala 87:29] wire _T_145 = ~io_ifc_iccm_access_bf; // @[ifu_ifc_ctl.scala 138:30] wire _T_148 = fb_full_f & _T_36; // @[ifu_ifc_ctl.scala 139:16] wire _T_149 = _T_145 | _T_148; // @[ifu_ifc_ctl.scala 138:53] @@ -44278,8 +44278,8 @@ module ifu_ifc_ctl( wire [4:0] _T_160 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58] wire [31:0] _T_161 = io_dec_ifc_dec_tlu_mrac_ff >> _T_160; // @[ifu_ifc_ctl.scala 143:61] reg _T_164; // @[ifu_ifc_ctl.scala 145:57] - reg [30:0] _T_166; // @[el2_lib.scala 514:16] - rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] + reg [30:0] _T_166; // @[lib.scala 374:16] + rvclkhdr rvclkhdr ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en), @@ -44295,9 +44295,9 @@ module ifu_ifc_ctl( assign io_ifc_iccm_access_bf = _T_142[31:16] == 16'hee00; // @[ifu_ifc_ctl.scala 137:25] assign io_ifc_region_acc_fault_bf = _T_157 & iccm_acc_in_region_bf; // @[ifu_ifc_ctl.scala 142:30] assign io_ifc_dma_access_ok = _T_155 | dma_iccm_stall_any_f; // @[ifu_ifc_ctl.scala 138:24] - assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_io_en = io_exu_flush_final | io_ifc_fetch_req_f; // @[el2_lib.scala 511:17] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_io_en = io_exu_flush_final | io_ifc_fetch_req_f; // @[lib.scala 371:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -46243,10 +46243,10 @@ module dec_decode_ctl( reg [31:0] _RAND_89; reg [31:0] _RAND_90; `endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_io_en; // @[lib.scala 343:22] + wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] wire [31:0] i0_dec_io_ins; // @[dec_decode_ctl.scala 362:22] wire i0_dec_io_out_alu; // @[dec_decode_ctl.scala 362:22] wire i0_dec_io_out_rs1; // @[dec_decode_ctl.scala 362:22] @@ -46298,82 +46298,82 @@ module dec_decode_ctl( wire i0_dec_io_out_fence_i; // @[dec_decode_ctl.scala 362:22] wire i0_dec_io_out_pm_alu; // @[dec_decode_ctl.scala 362:22] wire i0_dec_io_out_legal; // @[dec_decode_ctl.scala 362:22] - wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 518:23] - wire rvclkhdr_5_io_clk; // @[el2_lib.scala 518:23] - wire rvclkhdr_5_io_en; // @[el2_lib.scala 518:23] - wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 518:23] - wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 518:23] - wire rvclkhdr_6_io_clk; // @[el2_lib.scala 518:23] - wire rvclkhdr_6_io_en; // @[el2_lib.scala 518:23] - wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 518:23] - wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 518:23] - wire rvclkhdr_7_io_clk; // @[el2_lib.scala 518:23] - wire rvclkhdr_7_io_en; // @[el2_lib.scala 518:23] - wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 518:23] - wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 518:23] - wire rvclkhdr_8_io_clk; // @[el2_lib.scala 518:23] - wire rvclkhdr_8_io_en; // @[el2_lib.scala 518:23] - wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 518:23] - wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 518:23] - wire rvclkhdr_9_io_clk; // @[el2_lib.scala 518:23] - wire rvclkhdr_9_io_en; // @[el2_lib.scala 518:23] - wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 518:23] - wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_10_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_10_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_11_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_11_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_12_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_12_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_12_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_12_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_13_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_13_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_13_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_13_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_14_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_14_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_14_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_14_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_15_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_15_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_15_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_15_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_16_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_16_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_16_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_16_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_17_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_17_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_17_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_17_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_18_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_18_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_18_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_18_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_19_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_19_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_19_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_19_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_en; // @[lib.scala 368:23] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_en; // @[lib.scala 368:23] + wire rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_en; // @[lib.scala 368:23] + wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_en; // @[lib.scala 368:23] + wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_5_io_l1clk; // @[lib.scala 378:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 378:23] + wire rvclkhdr_5_io_en; // @[lib.scala 378:23] + wire rvclkhdr_5_io_scan_mode; // @[lib.scala 378:23] + wire rvclkhdr_6_io_l1clk; // @[lib.scala 378:23] + wire rvclkhdr_6_io_clk; // @[lib.scala 378:23] + wire rvclkhdr_6_io_en; // @[lib.scala 378:23] + wire rvclkhdr_6_io_scan_mode; // @[lib.scala 378:23] + wire rvclkhdr_7_io_l1clk; // @[lib.scala 378:23] + wire rvclkhdr_7_io_clk; // @[lib.scala 378:23] + wire rvclkhdr_7_io_en; // @[lib.scala 378:23] + wire rvclkhdr_7_io_scan_mode; // @[lib.scala 378:23] + wire rvclkhdr_8_io_l1clk; // @[lib.scala 378:23] + wire rvclkhdr_8_io_clk; // @[lib.scala 378:23] + wire rvclkhdr_8_io_en; // @[lib.scala 378:23] + wire rvclkhdr_8_io_scan_mode; // @[lib.scala 378:23] + wire rvclkhdr_9_io_l1clk; // @[lib.scala 378:23] + wire rvclkhdr_9_io_clk; // @[lib.scala 378:23] + wire rvclkhdr_9_io_en; // @[lib.scala 378:23] + wire rvclkhdr_9_io_scan_mode; // @[lib.scala 378:23] + wire rvclkhdr_10_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_10_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_10_io_en; // @[lib.scala 368:23] + wire rvclkhdr_10_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_11_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_11_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_11_io_en; // @[lib.scala 368:23] + wire rvclkhdr_11_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_12_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_12_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_12_io_en; // @[lib.scala 368:23] + wire rvclkhdr_12_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_13_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_13_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_13_io_en; // @[lib.scala 368:23] + wire rvclkhdr_13_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_14_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_14_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_14_io_en; // @[lib.scala 368:23] + wire rvclkhdr_14_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_15_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_15_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_15_io_en; // @[lib.scala 368:23] + wire rvclkhdr_15_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_16_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_16_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_16_io_en; // @[lib.scala 368:23] + wire rvclkhdr_16_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_17_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_17_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_17_io_en; // @[lib.scala 368:23] + wire rvclkhdr_17_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_18_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_18_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_18_io_en; // @[lib.scala 368:23] + wire rvclkhdr_18_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_19_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_19_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_19_io_en; // @[lib.scala 368:23] + wire rvclkhdr_19_io_scan_mode; // @[lib.scala 368:23] reg tlu_wr_pause_r1; // @[dec_decode_ctl.scala 469:55] wire _T_1 = io_dec_tlu_wr_pause_r ^ tlu_wr_pause_r1; // @[dec_decode_ctl.scala 181:51] reg tlu_wr_pause_r2; // @[dec_decode_ctl.scala 470:55] @@ -46397,7 +46397,7 @@ module dec_decode_ctl( wire _T_415 = io_dec_tlu_wr_pause_r | pause_stall; // @[dec_decode_ctl.scala 466:44] wire _T_408 = ~io_dec_tlu_flush_pause_r; // @[dec_decode_ctl.scala 465:49] wire _T_409 = io_dec_tlu_flush_lower_r & _T_408; // @[dec_decode_ctl.scala 465:47] - reg [31:0] write_csr_data; // @[el2_lib.scala 514:16] + reg [31:0] write_csr_data; // @[lib.scala 374:16] wire [31:0] _T_412 = {31'h0,write_csr_data[0]}; // @[Cat.scala 29:58] wire _T_413 = write_csr_data == _T_412; // @[dec_decode_ctl.scala 465:109] wire _T_414 = pause_stall & _T_413; // @[dec_decode_ctl.scala 465:91] @@ -46483,7 +46483,7 @@ module dec_decode_ctl( wire _T_508 = i0_postsync | _T_507; // @[dec_decode_ctl.scala 540:62] wire _T_509 = io_dec_aln_dec_i0_decode_d & _T_508; // @[dec_decode_ctl.scala 540:47] reg postsync_stall; // @[dec_decode_ctl.scala 538:53] - reg x_d_valid; // @[el2_lib.scala 524:16] + reg x_d_valid; // @[lib.scala 384:16] wire _T_510 = postsync_stall & x_d_valid; // @[dec_decode_ctl.scala 540:96] wire ps_stall_in = _T_509 | _T_510; // @[dec_decode_ctl.scala 540:77] wire _T_12 = ps_stall_in ^ postsync_stall; // @[dec_decode_ctl.scala 187:32] @@ -46627,26 +46627,26 @@ module dec_decode_ctl( wire [2:0] _T_86 = _GEN_128 | _T_83; // @[Mux.scala 27:72] wire [3:0] _GEN_129 = {{1'd0}, _T_86}; // @[Mux.scala 27:72] wire [3:0] cam_wen = _GEN_129 | _T_84; // @[Mux.scala 27:72] - reg x_d_bits_i0load; // @[el2_lib.scala 524:16] - reg [4:0] x_d_bits_i0rd; // @[el2_lib.scala 524:16] + reg x_d_bits_i0load; // @[lib.scala 384:16] + reg [4:0] x_d_bits_i0rd; // @[lib.scala 384:16] wire [4:0] nonblock_load_rd = x_d_bits_i0load ? x_d_bits_i0rd : 5'h0; // @[dec_decode_ctl.scala 284:31] reg [2:0] _T_704; // @[dec_decode_ctl.scala 622:80] wire [3:0] i0_pipe_en = {io_dec_aln_dec_i0_decode_d,_T_704}; // @[Cat.scala 29:58] wire _T_710 = |i0_pipe_en[2:1]; // @[dec_decode_ctl.scala 625:49] wire i0_r_ctl_en = _T_710 | io_clk_override; // @[dec_decode_ctl.scala 625:53] reg nonblock_load_valid_m_delay; // @[Reg.scala 27:20] - reg r_d_bits_i0load; // @[el2_lib.scala 524:16] + reg r_d_bits_i0load; // @[lib.scala 384:16] wire i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_bits_i0load; // @[dec_decode_ctl.scala 289:56] wire [2:0] _GEN_130 = {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_inv_tag_r}; // @[dec_decode_ctl.scala 291:66] wire _T_91 = _GEN_130 == cam_raw_0_bits_tag; // @[dec_decode_ctl.scala 291:66] wire _T_92 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_91; // @[dec_decode_ctl.scala 291:45] wire cam_inv_reset_val_0 = _T_92 & cam_0_valid; // @[dec_decode_ctl.scala 291:87] - reg r_d_bits_i0v; // @[el2_lib.scala 524:16] + reg r_d_bits_i0v; // @[lib.scala 384:16] wire _T_746 = ~io_dec_tlu_flush_lower_wb; // @[dec_decode_ctl.scala 657:51] wire r_d_in_bits_i0v = r_d_bits_i0v & _T_746; // @[dec_decode_ctl.scala 657:49] wire _T_757 = ~io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 665:47] wire i0_wen_r = r_d_in_bits_i0v & _T_757; // @[dec_decode_ctl.scala 665:45] - reg [4:0] r_d_bits_i0rd; // @[el2_lib.scala 524:16] + reg [4:0] r_d_bits_i0rd; // @[lib.scala 384:16] reg [4:0] cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 317:47] wire _T_103 = r_d_bits_i0rd == cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 304:85] wire _T_104 = i0_wen_r & _T_103; // @[dec_decode_ctl.scala 304:64] @@ -46796,7 +46796,7 @@ module dec_decode_ctl( reg _T_339; // @[dec_decode_ctl.scala 402:69] wire lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[dec_decode_ctl.scala 544:40] wire _T_905 = i0_dp_load | i0_dp_store; // @[dec_decode_ctl.scala 758:43] - reg x_d_bits_i0v; // @[el2_lib.scala 524:16] + reg x_d_bits_i0v; // @[lib.scala 384:16] wire _T_879 = io_decode_exu_dec_i0_rs1_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 738:59] wire _T_880 = x_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 738:91] wire i0_rs1_depend_i0_x = _T_879 & _T_880; // @[dec_decode_ctl.scala 738:74] @@ -46824,10 +46824,10 @@ module dec_decode_ctl( wire i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_899_load; // @[dec_decode_ctl.scala 746:24] wire store_data_bypass_d = _T_910 & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 759:63] wire _T_349 = i0_dp_csr_clr | i0_dp_csr_set; // @[dec_decode_ctl.scala 433:42] - reg r_d_bits_csrwen; // @[el2_lib.scala 524:16] - reg r_d_valid; // @[el2_lib.scala 524:16] + reg r_d_bits_csrwen; // @[lib.scala 384:16] + reg r_d_valid; // @[lib.scala 384:16] wire _T_352 = r_d_bits_csrwen & r_d_valid; // @[dec_decode_ctl.scala 441:39] - reg [11:0] r_d_bits_csrwaddr; // @[el2_lib.scala 524:16] + reg [11:0] r_d_bits_csrwaddr; // @[lib.scala 384:16] wire _T_355 = r_d_bits_csrwaddr == 12'h300; // @[dec_decode_ctl.scala 444:50] wire _T_356 = r_d_bits_csrwaddr == 12'h304; // @[dec_decode_ctl.scala 444:85] wire _T_357 = _T_355 | _T_356; // @[dec_decode_ctl.scala 444:64] @@ -46840,8 +46840,8 @@ module dec_decode_ctl( reg csr_write_x; // @[dec_decode_ctl.scala 449:53] reg csr_imm_x; // @[dec_decode_ctl.scala 450:51] wire i0_x_data_en = i0_pipe_en[3] | io_clk_override; // @[dec_decode_ctl.scala 627:50] - reg [4:0] csrimm_x; // @[el2_lib.scala 514:16] - reg [31:0] csr_rddata_x; // @[el2_lib.scala 514:16] + reg [4:0] csrimm_x; // @[lib.scala 374:16] + reg [31:0] csr_rddata_x; // @[lib.scala 374:16] wire [31:0] _T_394 = {27'h0,csrimm_x}; // @[Cat.scala 29:58] wire _T_396 = ~csr_imm_x; // @[dec_decode_ctl.scala 458:5] wire [31:0] _T_397 = csr_imm_x ? _T_394 : 32'h0; // @[Mux.scala 27:72] @@ -46863,13 +46863,13 @@ module dec_decode_ctl( wire _T_429 = _T_428 | csr_write_x; // @[dec_decode_ctl.scala 477:46] wire _T_430 = _T_429 & csr_read_x; // @[dec_decode_ctl.scala 477:61] wire _T_431 = _T_430 | io_dec_tlu_wr_pause_r; // @[dec_decode_ctl.scala 477:75] - reg r_d_bits_csrwonly; // @[el2_lib.scala 524:16] + reg r_d_bits_csrwonly; // @[lib.scala 384:16] wire _T_767 = r_d_bits_i0v & r_d_bits_i0load; // @[dec_decode_ctl.scala 680:42] - reg [31:0] i0_result_r_raw; // @[el2_lib.scala 514:16] + reg [31:0] i0_result_r_raw; // @[lib.scala 374:16] wire [31:0] i0_result_corr_r = _T_767 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 680:27] - reg x_d_bits_csrwonly; // @[el2_lib.scala 524:16] + reg x_d_bits_csrwonly; // @[lib.scala 384:16] wire _T_435 = x_d_bits_csrwonly | r_d_bits_csrwonly; // @[dec_decode_ctl.scala 486:43] - reg wbd_bits_csrwonly; // @[el2_lib.scala 524:16] + reg wbd_bits_csrwonly; // @[lib.scala 384:16] wire prior_csr_write = _T_435 | wbd_bits_csrwonly; // @[dec_decode_ctl.scala 486:63] wire debug_fence_raw = io_dec_debug_fence_d & io_dbg_dctl_dbg_cmd_wrdata[1]; // @[dec_decode_ctl.scala 489:48] wire debug_fence = debug_fence_raw | debug_fence_i; // @[dec_decode_ctl.scala 490:40] @@ -46879,7 +46879,7 @@ module dec_decode_ctl( wire i0_presync = _T_441 | io_dec_tlu_pipelining_disable; // @[dec_decode_ctl.scala 493:91] wire [31:0] _T_465 = {16'h0,io_dec_aln_ifu_i0_cinst}; // @[Cat.scala 29:58] wire _T_467 = ~illegal_lockout; // @[dec_decode_ctl.scala 505:44] - reg [31:0] _T_468; // @[el2_lib.scala 514:16] + reg [31:0] _T_468; // @[lib.scala 374:16] wire i0_div_prior_div_stall = i0_dp_div & io_dec_div_active; // @[dec_decode_ctl.scala 509:42] wire _T_473 = i0_dp_csr_read & prior_csr_write; // @[dec_decode_ctl.scala 511:40] wire _T_474 = _T_473 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 511:59] @@ -46924,32 +46924,32 @@ module dec_decode_ctl( wire [3:0] _T_525 = {io_dec_aln_dec_i0_decode_d,io_dec_aln_dec_i0_decode_d,io_dec_aln_dec_i0_decode_d,io_dec_aln_dec_i0_decode_d}; // @[Cat.scala 29:58] wire _T_707 = |i0_pipe_en[3:2]; // @[dec_decode_ctl.scala 624:49] wire i0_x_ctl_en = _T_707 | io_clk_override; // @[dec_decode_ctl.scala 624:53] - reg x_t_legal; // @[el2_lib.scala 524:16] - reg x_t_icaf; // @[el2_lib.scala 524:16] - reg x_t_icaf_f1; // @[el2_lib.scala 524:16] - reg [1:0] x_t_icaf_type; // @[el2_lib.scala 524:16] - reg x_t_fence_i; // @[el2_lib.scala 524:16] - reg [3:0] x_t_i0trigger; // @[el2_lib.scala 524:16] - reg [3:0] x_t_pmu_i0_itype; // @[el2_lib.scala 524:16] - reg x_t_pmu_i0_br_unpred; // @[el2_lib.scala 524:16] + reg x_t_legal; // @[lib.scala 384:16] + reg x_t_icaf; // @[lib.scala 384:16] + reg x_t_icaf_f1; // @[lib.scala 384:16] + reg [1:0] x_t_icaf_type; // @[lib.scala 384:16] + reg x_t_fence_i; // @[lib.scala 384:16] + reg [3:0] x_t_i0trigger; // @[lib.scala 384:16] + reg [3:0] x_t_pmu_i0_itype; // @[lib.scala 384:16] + reg x_t_pmu_i0_br_unpred; // @[lib.scala 384:16] wire [3:0] _T_533 = {io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb}; // @[Cat.scala 29:58] wire [3:0] _T_534 = ~_T_533; // @[dec_decode_ctl.scala 569:39] - reg r_t_legal; // @[el2_lib.scala 524:16] - reg r_t_icaf; // @[el2_lib.scala 524:16] - reg r_t_icaf_f1; // @[el2_lib.scala 524:16] - reg [1:0] r_t_icaf_type; // @[el2_lib.scala 524:16] - reg r_t_fence_i; // @[el2_lib.scala 524:16] - reg [3:0] r_t_i0trigger; // @[el2_lib.scala 524:16] - reg [3:0] r_t_pmu_i0_itype; // @[el2_lib.scala 524:16] - reg r_t_pmu_i0_br_unpred; // @[el2_lib.scala 524:16] + reg r_t_legal; // @[lib.scala 384:16] + reg r_t_icaf; // @[lib.scala 384:16] + reg r_t_icaf_f1; // @[lib.scala 384:16] + reg [1:0] r_t_icaf_type; // @[lib.scala 384:16] + reg r_t_fence_i; // @[lib.scala 384:16] + reg [3:0] r_t_i0trigger; // @[lib.scala 384:16] + reg [3:0] r_t_pmu_i0_itype; // @[lib.scala 384:16] + reg r_t_pmu_i0_br_unpred; // @[lib.scala 384:16] reg [3:0] lsu_trigger_match_r; // @[dec_decode_ctl.scala 572:36] reg lsu_pmu_misaligned_r; // @[dec_decode_ctl.scala 573:37] - reg r_d_bits_i0store; // @[el2_lib.scala 524:16] + reg r_d_bits_i0store; // @[lib.scala 384:16] wire _T_539 = r_d_bits_i0load | r_d_bits_i0store; // @[dec_decode_ctl.scala 577:61] wire [3:0] _T_543 = {_T_539,_T_539,_T_539,_T_539}; // @[Cat.scala 29:58] wire [3:0] _T_544 = _T_543 & lsu_trigger_match_r; // @[dec_decode_ctl.scala 577:82] wire [3:0] _T_545 = _T_544 | r_t_i0trigger; // @[dec_decode_ctl.scala 577:105] - reg r_d_bits_i0div; // @[el2_lib.scala 524:16] + reg r_d_bits_i0div; // @[lib.scala 384:16] wire _T_548 = r_d_bits_i0div & r_d_valid; // @[dec_decode_ctl.scala 583:58] wire _T_559 = i0r_rs1 != 5'h0; // @[dec_decode_ctl.scala 594:60] wire _T_561 = i0r_rs2 != 5'h0; // @[dec_decode_ctl.scala 595:60] @@ -46986,10 +46986,10 @@ module dec_decode_ctl( reg i0_r_c_alu; // @[Reg.scala 15:16] wire _T_713 = |i0_pipe_en[1:0]; // @[dec_decode_ctl.scala 626:49] wire i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[dec_decode_ctl.scala 628:50] - reg x_d_bits_i0store; // @[el2_lib.scala 524:16] - reg x_d_bits_i0div; // @[el2_lib.scala 524:16] - reg x_d_bits_csrwen; // @[el2_lib.scala 524:16] - reg [11:0] x_d_bits_csrwaddr; // @[el2_lib.scala 524:16] + reg x_d_bits_i0store; // @[lib.scala 384:16] + reg x_d_bits_i0div; // @[lib.scala 384:16] + reg x_d_bits_csrwen; // @[lib.scala 384:16] + reg [11:0] x_d_bits_csrwaddr; // @[lib.scala 384:16] wire _T_736 = x_d_bits_i0v & _T_746; // @[dec_decode_ctl.scala 650:47] wire _T_740 = x_d_valid & _T_746; // @[dec_decode_ctl.scala 651:33] wire _T_759 = ~r_d_bits_i0div; // @[dec_decode_ctl.scala 666:49] @@ -46998,7 +46998,7 @@ module dec_decode_ctl( wire _T_764 = x_d_bits_i0v & x_d_bits_i0load; // @[dec_decode_ctl.scala 675:47] wire _T_771 = io_decode_exu_i0_ap_predict_nt & _T_564; // @[dec_decode_ctl.scala 681:71] wire [11:0] _T_784 = {10'h0,io_dec_i0_pc4_d,i0_ap_pc2}; // @[Cat.scala 29:58] - reg [11:0] last_br_immed_x; // @[el2_lib.scala 514:16] + reg [11:0] last_br_immed_x; // @[lib.scala 374:16] wire _T_802 = x_d_bits_i0div & x_d_valid; // @[dec_decode_ctl.scala 689:45] wire div_e1_to_r = _T_802 | _T_548; // @[dec_decode_ctl.scala 689:58] wire _T_805 = x_d_bits_i0rd == 5'h0; // @[dec_decode_ctl.scala 691:77] @@ -47022,23 +47022,23 @@ module dec_decode_ctl( wire _T_823 = _T_821 & _T_822; // @[dec_decode_ctl.scala 703:79] reg _T_824; // @[dec_decode_ctl.scala 705:54] reg [4:0] _T_833; // @[Reg.scala 27:20] - reg [31:0] i0_inst_x; // @[el2_lib.scala 514:16] - reg [31:0] i0_inst_r; // @[el2_lib.scala 514:16] - reg [31:0] i0_inst_wb; // @[el2_lib.scala 514:16] - reg [31:0] _T_840; // @[el2_lib.scala 514:16] - reg [30:0] i0_pc_wb; // @[el2_lib.scala 514:16] - reg [30:0] _T_843; // @[el2_lib.scala 514:16] - reg [30:0] dec_i0_pc_r; // @[el2_lib.scala 514:16] + reg [31:0] i0_inst_x; // @[lib.scala 374:16] + reg [31:0] i0_inst_r; // @[lib.scala 374:16] + reg [31:0] i0_inst_wb; // @[lib.scala 374:16] + reg [31:0] _T_840; // @[lib.scala 374:16] + reg [30:0] i0_pc_wb; // @[lib.scala 374:16] + reg [30:0] _T_843; // @[lib.scala 374:16] + reg [30:0] dec_i0_pc_r; // @[lib.scala 374:16] wire [31:0] _T_845 = {io_dec_alu_exu_i0_pc_x,1'h0}; // @[Cat.scala 29:58] wire [12:0] _T_846 = {last_br_immed_x,1'h0}; // @[Cat.scala 29:58] - wire [12:0] _T_849 = _T_845[12:1] + _T_846[12:1]; // @[el2_lib.scala 208:31] - wire [18:0] _T_852 = _T_845[31:13] + 19'h1; // @[el2_lib.scala 209:27] - wire [18:0] _T_855 = _T_845[31:13] - 19'h1; // @[el2_lib.scala 210:27] - wire _T_858 = ~_T_849[12]; // @[el2_lib.scala 212:28] - wire _T_859 = _T_846[12] ^ _T_858; // @[el2_lib.scala 212:26] - wire _T_862 = ~_T_846[12]; // @[el2_lib.scala 213:20] - wire _T_864 = _T_862 & _T_849[12]; // @[el2_lib.scala 213:26] - wire _T_868 = _T_846[12] & _T_858; // @[el2_lib.scala 214:26] + wire [12:0] _T_849 = _T_845[12:1] + _T_846[12:1]; // @[lib.scala 68:31] + wire [18:0] _T_852 = _T_845[31:13] + 19'h1; // @[lib.scala 69:27] + wire [18:0] _T_855 = _T_845[31:13] - 19'h1; // @[lib.scala 70:27] + wire _T_858 = ~_T_849[12]; // @[lib.scala 72:28] + wire _T_859 = _T_846[12] ^ _T_858; // @[lib.scala 72:26] + wire _T_862 = ~_T_846[12]; // @[lib.scala 73:20] + wire _T_864 = _T_862 & _T_849[12]; // @[lib.scala 73:26] + wire _T_868 = _T_846[12] & _T_858; // @[lib.scala 74:26] wire [18:0] _T_870 = _T_859 ? _T_845[31:13] : 19'h0; // @[Mux.scala 27:72] wire [18:0] _T_871 = _T_864 ? _T_852 : 19'h0; // @[Mux.scala 27:72] wire [18:0] _T_872 = _T_868 ? _T_855 : 19'h0; // @[Mux.scala 27:72] @@ -47107,7 +47107,7 @@ module dec_decode_ctl( wire [11:0] _T_1008 = {io_dec_i0_instr_d[31:25],i0r_rd}; // @[Cat.scala 29:58] wire [11:0] _T_1009 = _T_999 ? io_dec_i0_instr_d[31:20] : 12'h0; // @[Mux.scala 27:72] wire [11:0] _T_1010 = _T_1004 ? _T_1008 : 12'h0; // @[Mux.scala 27:72] - rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en), @@ -47166,115 +47166,115 @@ module dec_decode_ctl( .io_out_pm_alu(i0_dec_io_out_pm_alu), .io_out_legal(i0_dec_io_out_legal) ); - rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_1 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_1_io_l1clk), .io_clk(rvclkhdr_1_io_clk), .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_2_io_l1clk), .io_clk(rvclkhdr_2_io_clk), .io_en(rvclkhdr_2_io_en), .io_scan_mode(rvclkhdr_2_io_scan_mode) ); - rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_3_io_l1clk), .io_clk(rvclkhdr_3_io_clk), .io_en(rvclkhdr_3_io_en), .io_scan_mode(rvclkhdr_3_io_scan_mode) ); - rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_4_io_l1clk), .io_clk(rvclkhdr_4_io_clk), .io_en(rvclkhdr_4_io_en), .io_scan_mode(rvclkhdr_4_io_scan_mode) ); - rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 518:23] + rvclkhdr rvclkhdr_5 ( // @[lib.scala 378:23] .io_l1clk(rvclkhdr_5_io_l1clk), .io_clk(rvclkhdr_5_io_clk), .io_en(rvclkhdr_5_io_en), .io_scan_mode(rvclkhdr_5_io_scan_mode) ); - rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 518:23] + rvclkhdr rvclkhdr_6 ( // @[lib.scala 378:23] .io_l1clk(rvclkhdr_6_io_l1clk), .io_clk(rvclkhdr_6_io_clk), .io_en(rvclkhdr_6_io_en), .io_scan_mode(rvclkhdr_6_io_scan_mode) ); - rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 518:23] + rvclkhdr rvclkhdr_7 ( // @[lib.scala 378:23] .io_l1clk(rvclkhdr_7_io_l1clk), .io_clk(rvclkhdr_7_io_clk), .io_en(rvclkhdr_7_io_en), .io_scan_mode(rvclkhdr_7_io_scan_mode) ); - rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 518:23] + rvclkhdr rvclkhdr_8 ( // @[lib.scala 378:23] .io_l1clk(rvclkhdr_8_io_l1clk), .io_clk(rvclkhdr_8_io_clk), .io_en(rvclkhdr_8_io_en), .io_scan_mode(rvclkhdr_8_io_scan_mode) ); - rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 518:23] + rvclkhdr rvclkhdr_9 ( // @[lib.scala 378:23] .io_l1clk(rvclkhdr_9_io_l1clk), .io_clk(rvclkhdr_9_io_clk), .io_en(rvclkhdr_9_io_en), .io_scan_mode(rvclkhdr_9_io_scan_mode) ); - rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_10 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_10_io_l1clk), .io_clk(rvclkhdr_10_io_clk), .io_en(rvclkhdr_10_io_en), .io_scan_mode(rvclkhdr_10_io_scan_mode) ); - rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_11 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_11_io_l1clk), .io_clk(rvclkhdr_11_io_clk), .io_en(rvclkhdr_11_io_en), .io_scan_mode(rvclkhdr_11_io_scan_mode) ); - rvclkhdr rvclkhdr_12 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_12 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_12_io_l1clk), .io_clk(rvclkhdr_12_io_clk), .io_en(rvclkhdr_12_io_en), .io_scan_mode(rvclkhdr_12_io_scan_mode) ); - rvclkhdr rvclkhdr_13 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_13 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_13_io_l1clk), .io_clk(rvclkhdr_13_io_clk), .io_en(rvclkhdr_13_io_en), .io_scan_mode(rvclkhdr_13_io_scan_mode) ); - rvclkhdr rvclkhdr_14 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_14 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_14_io_l1clk), .io_clk(rvclkhdr_14_io_clk), .io_en(rvclkhdr_14_io_en), .io_scan_mode(rvclkhdr_14_io_scan_mode) ); - rvclkhdr rvclkhdr_15 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_15 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_15_io_l1clk), .io_clk(rvclkhdr_15_io_clk), .io_en(rvclkhdr_15_io_en), .io_scan_mode(rvclkhdr_15_io_scan_mode) ); - rvclkhdr rvclkhdr_16 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_16 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_16_io_l1clk), .io_clk(rvclkhdr_16_io_clk), .io_en(rvclkhdr_16_io_en), .io_scan_mode(rvclkhdr_16_io_scan_mode) ); - rvclkhdr rvclkhdr_17 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_17 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_17_io_l1clk), .io_clk(rvclkhdr_17_io_clk), .io_en(rvclkhdr_17_io_en), .io_scan_mode(rvclkhdr_17_io_scan_mode) ); - rvclkhdr rvclkhdr_18 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_18 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_18_io_l1clk), .io_clk(rvclkhdr_18_io_clk), .io_en(rvclkhdr_18_io_en), .io_scan_mode(rvclkhdr_18_io_scan_mode) ); - rvclkhdr rvclkhdr_19 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_19 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_19_io_l1clk), .io_clk(rvclkhdr_19_io_clk), .io_en(rvclkhdr_19_io_en), @@ -47386,67 +47386,67 @@ module dec_decode_ctl( assign io_dec_pause_state_cg = pause_stall & _T_423; // @[dec_decode_ctl.scala 472:25] assign io_dec_div_active = _T_824; // @[dec_decode_ctl.scala 705:21] assign io_dec_aln_dec_i0_decode_d = _T_493 & _T_470; // @[dec_decode_ctl.scala 522:30 dec_decode_ctl.scala 588:30] - assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_io_en = _T_15 | _T_16; // @[el2_lib.scala 485:16] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_io_en = _T_15 | _T_16; // @[lib.scala 345:16] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] assign i0_dec_io_ins = io_dec_i0_instr_d; // @[dec_decode_ctl.scala 363:16] - assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_1_io_en = i0_pipe_en[3] | io_clk_override; // @[el2_lib.scala 511:17] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_2_io_en = i0_pipe_en[3] | io_clk_override; // @[el2_lib.scala 511:17] - assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_3_io_en = _T_431 | pause_stall; // @[el2_lib.scala 511:17] - assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_4_io_en = shift_illegal & _T_467; // @[el2_lib.scala 511:17] - assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 520:18] - assign rvclkhdr_5_io_en = _T_707 | io_clk_override; // @[el2_lib.scala 521:17] - assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24] - assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 520:18] - assign rvclkhdr_6_io_en = _T_707 | io_clk_override; // @[el2_lib.scala 521:17] - assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24] - assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 520:18] - assign rvclkhdr_7_io_en = _T_707 | io_clk_override; // @[el2_lib.scala 521:17] - assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24] - assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 520:18] - assign rvclkhdr_8_io_en = _T_710 | io_clk_override; // @[el2_lib.scala 521:17] - assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24] - assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 520:18] - assign rvclkhdr_9_io_en = _T_713 | io_clk_override; // @[el2_lib.scala 521:17] - assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24] - assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_10_io_en = i0_pipe_en[2] | io_clk_override; // @[el2_lib.scala 511:17] - assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_11_io_en = i0_pipe_en[3] | io_clk_override; // @[el2_lib.scala 511:17] - assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_12_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_12_io_en = i0_legal_decode_d & i0_dp_div; // @[el2_lib.scala 511:17] - assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_13_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_13_io_en = i0_pipe_en[3] | io_clk_override; // @[el2_lib.scala 511:17] - assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_14_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_14_io_en = i0_pipe_en[2] | io_clk_override; // @[el2_lib.scala 511:17] - assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_15_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_15_io_en = i0_pipe_en[1] | io_clk_override; // @[el2_lib.scala 511:17] - assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_16_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_16_io_en = i0_pipe_en[0] | io_clk_override; // @[el2_lib.scala 511:17] - assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_17_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_17_io_en = i0_pipe_en[1] | io_clk_override; // @[el2_lib.scala 511:17] - assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_18_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_18_io_en = i0_pipe_en[0] | io_clk_override; // @[el2_lib.scala 511:17] - assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_19_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_19_io_en = i0_pipe_en[2] | io_clk_override; // @[el2_lib.scala 511:17] - assign rvclkhdr_19_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_1_io_en = i0_pipe_en[3] | io_clk_override; // @[lib.scala 371:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_2_io_en = i0_pipe_en[3] | io_clk_override; // @[lib.scala 371:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_3_io_en = _T_431 | pause_stall; // @[lib.scala 371:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_4_io_en = shift_illegal & _T_467; // @[lib.scala 371:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 380:18] + assign rvclkhdr_5_io_en = _T_707 | io_clk_override; // @[lib.scala 381:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 382:24] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 380:18] + assign rvclkhdr_6_io_en = _T_707 | io_clk_override; // @[lib.scala 381:17] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 382:24] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 380:18] + assign rvclkhdr_7_io_en = _T_707 | io_clk_override; // @[lib.scala 381:17] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 382:24] + assign rvclkhdr_8_io_clk = clock; // @[lib.scala 380:18] + assign rvclkhdr_8_io_en = _T_710 | io_clk_override; // @[lib.scala 381:17] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 382:24] + assign rvclkhdr_9_io_clk = clock; // @[lib.scala 380:18] + assign rvclkhdr_9_io_en = _T_713 | io_clk_override; // @[lib.scala 381:17] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 382:24] + assign rvclkhdr_10_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_10_io_en = i0_pipe_en[2] | io_clk_override; // @[lib.scala 371:17] + assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_11_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_11_io_en = i0_pipe_en[3] | io_clk_override; // @[lib.scala 371:17] + assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_12_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_12_io_en = i0_legal_decode_d & i0_dp_div; // @[lib.scala 371:17] + assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_13_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_13_io_en = i0_pipe_en[3] | io_clk_override; // @[lib.scala 371:17] + assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_14_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_14_io_en = i0_pipe_en[2] | io_clk_override; // @[lib.scala 371:17] + assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_15_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_15_io_en = i0_pipe_en[1] | io_clk_override; // @[lib.scala 371:17] + assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_16_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_16_io_en = i0_pipe_en[0] | io_clk_override; // @[lib.scala 371:17] + assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_17_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_17_io_en = i0_pipe_en[1] | io_clk_override; // @[lib.scala 371:17] + assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_18_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_18_io_en = i0_pipe_en[0] | io_clk_override; // @[lib.scala 371:17] + assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_19_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_19_io_en = i0_pipe_en[2] | io_clk_override; // @[lib.scala 371:17] + assign rvclkhdr_19_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -48649,130 +48649,130 @@ module dec_gpr_ctl( reg [31:0] _RAND_29; reg [31:0] _RAND_30; `endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_8_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_8_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_9_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_9_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_10_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_10_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_11_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_11_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_12_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_12_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_12_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_12_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_13_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_13_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_13_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_13_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_14_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_14_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_14_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_14_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_15_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_15_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_15_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_15_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_16_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_16_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_16_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_16_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_17_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_17_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_17_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_17_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_18_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_18_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_18_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_18_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_19_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_19_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_19_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_19_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_20_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_20_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_20_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_20_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_21_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_21_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_21_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_21_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_22_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_22_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_22_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_22_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_23_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_23_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_23_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_23_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_24_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_24_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_24_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_24_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_25_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_25_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_25_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_25_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_26_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_26_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_26_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_26_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_27_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_27_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_27_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_27_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_28_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_28_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_28_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_28_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_29_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_29_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_29_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_29_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_30_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_30_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_30_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_30_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_io_en; // @[lib.scala 368:23] + wire rvclkhdr_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_en; // @[lib.scala 368:23] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_en; // @[lib.scala 368:23] + wire rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_en; // @[lib.scala 368:23] + wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_en; // @[lib.scala 368:23] + wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_5_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_en; // @[lib.scala 368:23] + wire rvclkhdr_5_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_6_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_6_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_6_io_en; // @[lib.scala 368:23] + wire rvclkhdr_6_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_7_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_7_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_7_io_en; // @[lib.scala 368:23] + wire rvclkhdr_7_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_8_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_8_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_8_io_en; // @[lib.scala 368:23] + wire rvclkhdr_8_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_9_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_9_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_9_io_en; // @[lib.scala 368:23] + wire rvclkhdr_9_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_10_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_10_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_10_io_en; // @[lib.scala 368:23] + wire rvclkhdr_10_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_11_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_11_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_11_io_en; // @[lib.scala 368:23] + wire rvclkhdr_11_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_12_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_12_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_12_io_en; // @[lib.scala 368:23] + wire rvclkhdr_12_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_13_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_13_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_13_io_en; // @[lib.scala 368:23] + wire rvclkhdr_13_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_14_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_14_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_14_io_en; // @[lib.scala 368:23] + wire rvclkhdr_14_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_15_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_15_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_15_io_en; // @[lib.scala 368:23] + wire rvclkhdr_15_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_16_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_16_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_16_io_en; // @[lib.scala 368:23] + wire rvclkhdr_16_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_17_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_17_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_17_io_en; // @[lib.scala 368:23] + wire rvclkhdr_17_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_18_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_18_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_18_io_en; // @[lib.scala 368:23] + wire rvclkhdr_18_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_19_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_19_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_19_io_en; // @[lib.scala 368:23] + wire rvclkhdr_19_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_20_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_20_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_20_io_en; // @[lib.scala 368:23] + wire rvclkhdr_20_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_21_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_21_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_21_io_en; // @[lib.scala 368:23] + wire rvclkhdr_21_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_22_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_22_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_22_io_en; // @[lib.scala 368:23] + wire rvclkhdr_22_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_23_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_23_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_23_io_en; // @[lib.scala 368:23] + wire rvclkhdr_23_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_24_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_24_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_24_io_en; // @[lib.scala 368:23] + wire rvclkhdr_24_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_25_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_25_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_25_io_en; // @[lib.scala 368:23] + wire rvclkhdr_25_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_26_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_26_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_26_io_en; // @[lib.scala 368:23] + wire rvclkhdr_26_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_27_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_27_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_27_io_en; // @[lib.scala 368:23] + wire rvclkhdr_27_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_28_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_28_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_28_io_en; // @[lib.scala 368:23] + wire rvclkhdr_28_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_29_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_29_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_29_io_en; // @[lib.scala 368:23] + wire rvclkhdr_29_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_30_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_30_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_30_io_en; // @[lib.scala 368:23] + wire rvclkhdr_30_io_scan_mode; // @[lib.scala 368:23] wire _T = io_waddr0 == 5'h1; // @[dec_gpr_ctl.scala 52:45] wire w0v_1 = io_wen0 & _T; // @[dec_gpr_ctl.scala 52:33] wire _T_2 = io_waddr1 == 5'h1; // @[dec_gpr_ctl.scala 53:45] @@ -49190,37 +49190,37 @@ module dec_gpr_ctl( wire [27:0] _T_616 = {w2v_27,w2v_26,w2v_25,w2v_24,w2v_23,w2v_22,w2v_21,w2v_20,w2v_19,_T_607}; // @[Cat.scala 29:58] wire [31:0] _T_620 = {w2v_31,w2v_30,w2v_29,w2v_28,_T_616}; // @[Cat.scala 29:58] wire [31:0] gpr_wr_en = _T_589 | _T_620; // @[dec_gpr_ctl.scala 57:95] - reg [31:0] gpr_out_1; // @[el2_lib.scala 514:16] - reg [31:0] gpr_out_2; // @[el2_lib.scala 514:16] - reg [31:0] gpr_out_3; // @[el2_lib.scala 514:16] - reg [31:0] gpr_out_4; // @[el2_lib.scala 514:16] - reg [31:0] gpr_out_5; // @[el2_lib.scala 514:16] - reg [31:0] gpr_out_6; // @[el2_lib.scala 514:16] - reg [31:0] gpr_out_7; // @[el2_lib.scala 514:16] - reg [31:0] gpr_out_8; // @[el2_lib.scala 514:16] - reg [31:0] gpr_out_9; // @[el2_lib.scala 514:16] - reg [31:0] gpr_out_10; // @[el2_lib.scala 514:16] - reg [31:0] gpr_out_11; // @[el2_lib.scala 514:16] - reg [31:0] gpr_out_12; // @[el2_lib.scala 514:16] - reg [31:0] gpr_out_13; // @[el2_lib.scala 514:16] - reg [31:0] gpr_out_14; // @[el2_lib.scala 514:16] - reg [31:0] gpr_out_15; // @[el2_lib.scala 514:16] - reg [31:0] gpr_out_16; // @[el2_lib.scala 514:16] - reg [31:0] gpr_out_17; // @[el2_lib.scala 514:16] - reg [31:0] gpr_out_18; // @[el2_lib.scala 514:16] - reg [31:0] gpr_out_19; // @[el2_lib.scala 514:16] - reg [31:0] gpr_out_20; // @[el2_lib.scala 514:16] - reg [31:0] gpr_out_21; // @[el2_lib.scala 514:16] - reg [31:0] gpr_out_22; // @[el2_lib.scala 514:16] - reg [31:0] gpr_out_23; // @[el2_lib.scala 514:16] - reg [31:0] gpr_out_24; // @[el2_lib.scala 514:16] - reg [31:0] gpr_out_25; // @[el2_lib.scala 514:16] - reg [31:0] gpr_out_26; // @[el2_lib.scala 514:16] - reg [31:0] gpr_out_27; // @[el2_lib.scala 514:16] - reg [31:0] gpr_out_28; // @[el2_lib.scala 514:16] - reg [31:0] gpr_out_29; // @[el2_lib.scala 514:16] - reg [31:0] gpr_out_30; // @[el2_lib.scala 514:16] - reg [31:0] gpr_out_31; // @[el2_lib.scala 514:16] + reg [31:0] gpr_out_1; // @[lib.scala 374:16] + reg [31:0] gpr_out_2; // @[lib.scala 374:16] + reg [31:0] gpr_out_3; // @[lib.scala 374:16] + reg [31:0] gpr_out_4; // @[lib.scala 374:16] + reg [31:0] gpr_out_5; // @[lib.scala 374:16] + reg [31:0] gpr_out_6; // @[lib.scala 374:16] + reg [31:0] gpr_out_7; // @[lib.scala 374:16] + reg [31:0] gpr_out_8; // @[lib.scala 374:16] + reg [31:0] gpr_out_9; // @[lib.scala 374:16] + reg [31:0] gpr_out_10; // @[lib.scala 374:16] + reg [31:0] gpr_out_11; // @[lib.scala 374:16] + reg [31:0] gpr_out_12; // @[lib.scala 374:16] + reg [31:0] gpr_out_13; // @[lib.scala 374:16] + reg [31:0] gpr_out_14; // @[lib.scala 374:16] + reg [31:0] gpr_out_15; // @[lib.scala 374:16] + reg [31:0] gpr_out_16; // @[lib.scala 374:16] + reg [31:0] gpr_out_17; // @[lib.scala 374:16] + reg [31:0] gpr_out_18; // @[lib.scala 374:16] + reg [31:0] gpr_out_19; // @[lib.scala 374:16] + reg [31:0] gpr_out_20; // @[lib.scala 374:16] + reg [31:0] gpr_out_21; // @[lib.scala 374:16] + reg [31:0] gpr_out_22; // @[lib.scala 374:16] + reg [31:0] gpr_out_23; // @[lib.scala 374:16] + reg [31:0] gpr_out_24; // @[lib.scala 374:16] + reg [31:0] gpr_out_25; // @[lib.scala 374:16] + reg [31:0] gpr_out_26; // @[lib.scala 374:16] + reg [31:0] gpr_out_27; // @[lib.scala 374:16] + reg [31:0] gpr_out_28; // @[lib.scala 374:16] + reg [31:0] gpr_out_29; // @[lib.scala 374:16] + reg [31:0] gpr_out_30; // @[lib.scala 374:16] + reg [31:0] gpr_out_31; // @[lib.scala 374:16] wire _T_684 = io_raddr0 == 5'h1; // @[dec_gpr_ctl.scala 64:72] wire _T_686 = io_raddr0 == 5'h2; // @[dec_gpr_ctl.scala 64:72] wire _T_688 = io_raddr0 == 5'h3; // @[dec_gpr_ctl.scala 64:72] @@ -49403,187 +49403,187 @@ module dec_gpr_ctl( wire [31:0] _T_927 = _T_926 | _T_897; // @[Mux.scala 27:72] wire [31:0] _T_928 = _T_927 | _T_898; // @[Mux.scala 27:72] wire [31:0] _T_929 = _T_928 | _T_899; // @[Mux.scala 27:72] - rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en), .io_scan_mode(rvclkhdr_io_scan_mode) ); - rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_1 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_1_io_l1clk), .io_clk(rvclkhdr_1_io_clk), .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_2_io_l1clk), .io_clk(rvclkhdr_2_io_clk), .io_en(rvclkhdr_2_io_en), .io_scan_mode(rvclkhdr_2_io_scan_mode) ); - rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_3_io_l1clk), .io_clk(rvclkhdr_3_io_clk), .io_en(rvclkhdr_3_io_en), .io_scan_mode(rvclkhdr_3_io_scan_mode) ); - rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_4_io_l1clk), .io_clk(rvclkhdr_4_io_clk), .io_en(rvclkhdr_4_io_en), .io_scan_mode(rvclkhdr_4_io_scan_mode) ); - rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_5 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_5_io_l1clk), .io_clk(rvclkhdr_5_io_clk), .io_en(rvclkhdr_5_io_en), .io_scan_mode(rvclkhdr_5_io_scan_mode) ); - rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_6 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_6_io_l1clk), .io_clk(rvclkhdr_6_io_clk), .io_en(rvclkhdr_6_io_en), .io_scan_mode(rvclkhdr_6_io_scan_mode) ); - rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_7 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_7_io_l1clk), .io_clk(rvclkhdr_7_io_clk), .io_en(rvclkhdr_7_io_en), .io_scan_mode(rvclkhdr_7_io_scan_mode) ); - rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_8 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_8_io_l1clk), .io_clk(rvclkhdr_8_io_clk), .io_en(rvclkhdr_8_io_en), .io_scan_mode(rvclkhdr_8_io_scan_mode) ); - rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_9 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_9_io_l1clk), .io_clk(rvclkhdr_9_io_clk), .io_en(rvclkhdr_9_io_en), .io_scan_mode(rvclkhdr_9_io_scan_mode) ); - rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_10 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_10_io_l1clk), .io_clk(rvclkhdr_10_io_clk), .io_en(rvclkhdr_10_io_en), .io_scan_mode(rvclkhdr_10_io_scan_mode) ); - rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_11 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_11_io_l1clk), .io_clk(rvclkhdr_11_io_clk), .io_en(rvclkhdr_11_io_en), .io_scan_mode(rvclkhdr_11_io_scan_mode) ); - rvclkhdr rvclkhdr_12 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_12 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_12_io_l1clk), .io_clk(rvclkhdr_12_io_clk), .io_en(rvclkhdr_12_io_en), .io_scan_mode(rvclkhdr_12_io_scan_mode) ); - rvclkhdr rvclkhdr_13 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_13 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_13_io_l1clk), .io_clk(rvclkhdr_13_io_clk), .io_en(rvclkhdr_13_io_en), .io_scan_mode(rvclkhdr_13_io_scan_mode) ); - rvclkhdr rvclkhdr_14 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_14 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_14_io_l1clk), .io_clk(rvclkhdr_14_io_clk), .io_en(rvclkhdr_14_io_en), .io_scan_mode(rvclkhdr_14_io_scan_mode) ); - rvclkhdr rvclkhdr_15 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_15 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_15_io_l1clk), .io_clk(rvclkhdr_15_io_clk), .io_en(rvclkhdr_15_io_en), .io_scan_mode(rvclkhdr_15_io_scan_mode) ); - rvclkhdr rvclkhdr_16 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_16 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_16_io_l1clk), .io_clk(rvclkhdr_16_io_clk), .io_en(rvclkhdr_16_io_en), .io_scan_mode(rvclkhdr_16_io_scan_mode) ); - rvclkhdr rvclkhdr_17 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_17 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_17_io_l1clk), .io_clk(rvclkhdr_17_io_clk), .io_en(rvclkhdr_17_io_en), .io_scan_mode(rvclkhdr_17_io_scan_mode) ); - rvclkhdr rvclkhdr_18 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_18 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_18_io_l1clk), .io_clk(rvclkhdr_18_io_clk), .io_en(rvclkhdr_18_io_en), .io_scan_mode(rvclkhdr_18_io_scan_mode) ); - rvclkhdr rvclkhdr_19 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_19 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_19_io_l1clk), .io_clk(rvclkhdr_19_io_clk), .io_en(rvclkhdr_19_io_en), .io_scan_mode(rvclkhdr_19_io_scan_mode) ); - rvclkhdr rvclkhdr_20 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_20 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_20_io_l1clk), .io_clk(rvclkhdr_20_io_clk), .io_en(rvclkhdr_20_io_en), .io_scan_mode(rvclkhdr_20_io_scan_mode) ); - rvclkhdr rvclkhdr_21 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_21 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_21_io_l1clk), .io_clk(rvclkhdr_21_io_clk), .io_en(rvclkhdr_21_io_en), .io_scan_mode(rvclkhdr_21_io_scan_mode) ); - rvclkhdr rvclkhdr_22 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_22 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_22_io_l1clk), .io_clk(rvclkhdr_22_io_clk), .io_en(rvclkhdr_22_io_en), .io_scan_mode(rvclkhdr_22_io_scan_mode) ); - rvclkhdr rvclkhdr_23 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_23 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_23_io_l1clk), .io_clk(rvclkhdr_23_io_clk), .io_en(rvclkhdr_23_io_en), .io_scan_mode(rvclkhdr_23_io_scan_mode) ); - rvclkhdr rvclkhdr_24 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_24 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_24_io_l1clk), .io_clk(rvclkhdr_24_io_clk), .io_en(rvclkhdr_24_io_en), .io_scan_mode(rvclkhdr_24_io_scan_mode) ); - rvclkhdr rvclkhdr_25 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_25 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_25_io_l1clk), .io_clk(rvclkhdr_25_io_clk), .io_en(rvclkhdr_25_io_en), .io_scan_mode(rvclkhdr_25_io_scan_mode) ); - rvclkhdr rvclkhdr_26 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_26 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_26_io_l1clk), .io_clk(rvclkhdr_26_io_clk), .io_en(rvclkhdr_26_io_en), .io_scan_mode(rvclkhdr_26_io_scan_mode) ); - rvclkhdr rvclkhdr_27 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_27 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_27_io_l1clk), .io_clk(rvclkhdr_27_io_clk), .io_en(rvclkhdr_27_io_en), .io_scan_mode(rvclkhdr_27_io_scan_mode) ); - rvclkhdr rvclkhdr_28 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_28 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_28_io_l1clk), .io_clk(rvclkhdr_28_io_clk), .io_en(rvclkhdr_28_io_en), .io_scan_mode(rvclkhdr_28_io_scan_mode) ); - rvclkhdr rvclkhdr_29 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_29 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_29_io_l1clk), .io_clk(rvclkhdr_29_io_clk), .io_en(rvclkhdr_29_io_en), .io_scan_mode(rvclkhdr_29_io_scan_mode) ); - rvclkhdr rvclkhdr_30 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_30 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_30_io_l1clk), .io_clk(rvclkhdr_30_io_clk), .io_en(rvclkhdr_30_io_en), @@ -49591,99 +49591,99 @@ module dec_gpr_ctl( ); assign io_gpr_exu_gpr_i0_rs1_d = _T_805 | _T_776; // @[dec_gpr_ctl.scala 48:32 dec_gpr_ctl.scala 64:32] assign io_gpr_exu_gpr_i0_rs2_d = _T_929 | _T_900; // @[dec_gpr_ctl.scala 49:32 dec_gpr_ctl.scala 65:32] - assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_io_en = gpr_wr_en[1]; // @[el2_lib.scala 511:17] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_1_io_en = gpr_wr_en[2]; // @[el2_lib.scala 511:17] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_2_io_en = gpr_wr_en[3]; // @[el2_lib.scala 511:17] - assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_3_io_en = gpr_wr_en[4]; // @[el2_lib.scala 511:17] - assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_4_io_en = gpr_wr_en[5]; // @[el2_lib.scala 511:17] - assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_5_io_en = gpr_wr_en[6]; // @[el2_lib.scala 511:17] - assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_6_io_en = gpr_wr_en[7]; // @[el2_lib.scala 511:17] - assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_7_io_en = gpr_wr_en[8]; // @[el2_lib.scala 511:17] - assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_8_io_en = gpr_wr_en[9]; // @[el2_lib.scala 511:17] - assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_9_io_en = gpr_wr_en[10]; // @[el2_lib.scala 511:17] - assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_10_io_en = gpr_wr_en[11]; // @[el2_lib.scala 511:17] - assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_11_io_en = gpr_wr_en[12]; // @[el2_lib.scala 511:17] - assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_12_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_12_io_en = gpr_wr_en[13]; // @[el2_lib.scala 511:17] - assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_13_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_13_io_en = gpr_wr_en[14]; // @[el2_lib.scala 511:17] - assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_14_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_14_io_en = gpr_wr_en[15]; // @[el2_lib.scala 511:17] - assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_15_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_15_io_en = gpr_wr_en[16]; // @[el2_lib.scala 511:17] - assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_16_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_16_io_en = gpr_wr_en[17]; // @[el2_lib.scala 511:17] - assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_17_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_17_io_en = gpr_wr_en[18]; // @[el2_lib.scala 511:17] - assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_18_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_18_io_en = gpr_wr_en[19]; // @[el2_lib.scala 511:17] - assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_19_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_19_io_en = gpr_wr_en[20]; // @[el2_lib.scala 511:17] - assign rvclkhdr_19_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_20_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_20_io_en = gpr_wr_en[21]; // @[el2_lib.scala 511:17] - assign rvclkhdr_20_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_21_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_21_io_en = gpr_wr_en[22]; // @[el2_lib.scala 511:17] - assign rvclkhdr_21_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_22_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_22_io_en = gpr_wr_en[23]; // @[el2_lib.scala 511:17] - assign rvclkhdr_22_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_23_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_23_io_en = gpr_wr_en[24]; // @[el2_lib.scala 511:17] - assign rvclkhdr_23_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_24_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_24_io_en = gpr_wr_en[25]; // @[el2_lib.scala 511:17] - assign rvclkhdr_24_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_25_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_25_io_en = gpr_wr_en[26]; // @[el2_lib.scala 511:17] - assign rvclkhdr_25_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_26_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_26_io_en = gpr_wr_en[27]; // @[el2_lib.scala 511:17] - assign rvclkhdr_26_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_27_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_27_io_en = gpr_wr_en[28]; // @[el2_lib.scala 511:17] - assign rvclkhdr_27_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_28_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_28_io_en = gpr_wr_en[29]; // @[el2_lib.scala 511:17] - assign rvclkhdr_28_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_29_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_29_io_en = gpr_wr_en[30]; // @[el2_lib.scala 511:17] - assign rvclkhdr_29_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_30_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_30_io_en = gpr_wr_en[31]; // @[el2_lib.scala 511:17] - assign rvclkhdr_30_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_io_en = gpr_wr_en[1]; // @[lib.scala 371:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_1_io_en = gpr_wr_en[2]; // @[lib.scala 371:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_2_io_en = gpr_wr_en[3]; // @[lib.scala 371:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_3_io_en = gpr_wr_en[4]; // @[lib.scala 371:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_4_io_en = gpr_wr_en[5]; // @[lib.scala 371:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_5_io_en = gpr_wr_en[6]; // @[lib.scala 371:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_6_io_en = gpr_wr_en[7]; // @[lib.scala 371:17] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_7_io_en = gpr_wr_en[8]; // @[lib.scala 371:17] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_8_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_8_io_en = gpr_wr_en[9]; // @[lib.scala 371:17] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_9_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_9_io_en = gpr_wr_en[10]; // @[lib.scala 371:17] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_10_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_10_io_en = gpr_wr_en[11]; // @[lib.scala 371:17] + assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_11_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_11_io_en = gpr_wr_en[12]; // @[lib.scala 371:17] + assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_12_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_12_io_en = gpr_wr_en[13]; // @[lib.scala 371:17] + assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_13_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_13_io_en = gpr_wr_en[14]; // @[lib.scala 371:17] + assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_14_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_14_io_en = gpr_wr_en[15]; // @[lib.scala 371:17] + assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_15_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_15_io_en = gpr_wr_en[16]; // @[lib.scala 371:17] + assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_16_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_16_io_en = gpr_wr_en[17]; // @[lib.scala 371:17] + assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_17_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_17_io_en = gpr_wr_en[18]; // @[lib.scala 371:17] + assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_18_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_18_io_en = gpr_wr_en[19]; // @[lib.scala 371:17] + assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_19_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_19_io_en = gpr_wr_en[20]; // @[lib.scala 371:17] + assign rvclkhdr_19_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_20_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_20_io_en = gpr_wr_en[21]; // @[lib.scala 371:17] + assign rvclkhdr_20_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_21_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_21_io_en = gpr_wr_en[22]; // @[lib.scala 371:17] + assign rvclkhdr_21_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_22_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_22_io_en = gpr_wr_en[23]; // @[lib.scala 371:17] + assign rvclkhdr_22_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_23_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_23_io_en = gpr_wr_en[24]; // @[lib.scala 371:17] + assign rvclkhdr_23_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_24_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_24_io_en = gpr_wr_en[25]; // @[lib.scala 371:17] + assign rvclkhdr_24_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_25_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_25_io_en = gpr_wr_en[26]; // @[lib.scala 371:17] + assign rvclkhdr_25_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_26_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_26_io_en = gpr_wr_en[27]; // @[lib.scala 371:17] + assign rvclkhdr_26_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_27_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_27_io_en = gpr_wr_en[28]; // @[lib.scala 371:17] + assign rvclkhdr_27_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_28_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_28_io_en = gpr_wr_en[29]; // @[lib.scala 371:17] + assign rvclkhdr_28_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_29_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_29_io_en = gpr_wr_en[30]; // @[lib.scala 371:17] + assign rvclkhdr_29_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_30_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_30_io_en = gpr_wr_en[31]; // @[lib.scala 371:17] + assign rvclkhdr_30_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -50131,28 +50131,28 @@ module dec_timer_ctl( reg [31:0] _RAND_6; reg [31:0] _RAND_7; `endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23] - reg [31:0] mitcnt0; // @[el2_lib.scala 514:16] - reg [31:0] mitb0_b; // @[el2_lib.scala 514:16] + wire rvclkhdr_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_io_en; // @[lib.scala 368:23] + wire rvclkhdr_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_en; // @[lib.scala 368:23] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_en; // @[lib.scala 368:23] + wire rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_en; // @[lib.scala 368:23] + wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] + reg [31:0] mitcnt0; // @[lib.scala 374:16] + reg [31:0] mitb0_b; // @[lib.scala 374:16] wire [31:0] mitb0 = ~mitb0_b; // @[dec_tlu_ctl.scala 2712:22] wire mit0_match_ns = mitcnt0 >= mitb0; // @[dec_tlu_ctl.scala 2673:36] - reg [31:0] mitcnt1; // @[el2_lib.scala 514:16] - reg [31:0] mitb1_b; // @[el2_lib.scala 514:16] + reg [31:0] mitcnt1; // @[lib.scala 374:16] + reg [31:0] mitb1_b; // @[lib.scala 374:16] wire [31:0] mitb1 = ~mitb1_b; // @[dec_tlu_ctl.scala 2721:18] wire mit1_match_ns = mitcnt1 >= mitb1; // @[dec_tlu_ctl.scala 2674:36] wire _T = io_dec_csr_wraddr_r == 12'h7d2; // @[dec_tlu_ctl.scala 2684:72] @@ -50211,25 +50211,25 @@ module dec_timer_ctl( wire [31:0] _T_92 = _T_91 | _T_87; // @[Mux.scala 27:72] wire [31:0] _T_93 = _T_92 | _T_88; // @[Mux.scala 27:72] wire [31:0] _T_94 = _T_93 | _T_89; // @[Mux.scala 27:72] - rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en), .io_scan_mode(rvclkhdr_io_scan_mode) ); - rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_1 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_1_io_l1clk), .io_clk(rvclkhdr_1_io_clk), .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_2_io_l1clk), .io_clk(rvclkhdr_2_io_clk), .io_en(rvclkhdr_2_io_en), .io_scan_mode(rvclkhdr_2_io_scan_mode) ); - rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_3_io_l1clk), .io_clk(rvclkhdr_3_io_clk), .io_en(rvclkhdr_3_io_en), @@ -50239,18 +50239,18 @@ module dec_timer_ctl( assign io_dec_timer_read_d = _T_72 | io_csr_mitctl1; // @[dec_tlu_ctl.scala 2753:33] assign io_dec_timer_t0_pulse = mitcnt0 >= mitb0; // @[dec_tlu_ctl.scala 2676:31] assign io_dec_timer_t1_pulse = mitcnt1 >= mitb1; // @[dec_tlu_ctl.scala 2677:31] - assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_io_en = _T_15 | mit0_match_ns; // @[el2_lib.scala 511:17] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_1_io_en = _T_39 | mit1_match_ns; // @[el2_lib.scala 511:17] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_2_io_en = io_dec_csr_wen_r_mod & _T_43; // @[el2_lib.scala 511:17] - assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_3_io_en = io_dec_csr_wen_r_mod & _T_47; // @[el2_lib.scala 511:17] - assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_io_en = _T_15 | mit0_match_ns; // @[lib.scala 371:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_1_io_en = _T_39 | mit1_match_ns; // @[lib.scala 371:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_2_io_en = io_dec_csr_wen_r_mod & _T_43; // @[lib.scala 371:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_3_io_en = io_dec_csr_wen_r_mod & _T_47; // @[lib.scala 371:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -50746,158 +50746,158 @@ module csr_tlu( reg [31:0] _RAND_72; reg [31:0] _RAND_73; `endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_8_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_8_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_9_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_9_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_10_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_10_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_11_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_11_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_12_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_12_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_12_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_12_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_13_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_13_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_13_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_13_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_14_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_14_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_14_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_14_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_15_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_15_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_15_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_15_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_16_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_16_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_16_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_16_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_17_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_17_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_17_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_17_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_18_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_18_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_18_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_18_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_19_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_19_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_19_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_19_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_20_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_20_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_20_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_20_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_21_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_21_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_21_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_21_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_22_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_22_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_22_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_22_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_23_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_23_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_23_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_23_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_24_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_24_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_24_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_24_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_25_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_25_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_25_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_25_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_26_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_26_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_26_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_26_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_27_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_27_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_27_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_27_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_28_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_28_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_28_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_28_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_29_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_29_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_29_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_29_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_30_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_30_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_30_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_30_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_31_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_31_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_31_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_31_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_32_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_32_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_32_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_32_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_33_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_33_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_33_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_33_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_34_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_34_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_34_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_34_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_io_en; // @[lib.scala 368:23] + wire rvclkhdr_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_en; // @[lib.scala 368:23] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_en; // @[lib.scala 368:23] + wire rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_en; // @[lib.scala 368:23] + wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_en; // @[lib.scala 368:23] + wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_5_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_en; // @[lib.scala 368:23] + wire rvclkhdr_5_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_6_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_6_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_6_io_en; // @[lib.scala 368:23] + wire rvclkhdr_6_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_7_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_7_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_7_io_en; // @[lib.scala 368:23] + wire rvclkhdr_7_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_8_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_8_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_8_io_en; // @[lib.scala 368:23] + wire rvclkhdr_8_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_9_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_9_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_9_io_en; // @[lib.scala 368:23] + wire rvclkhdr_9_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_10_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_10_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_10_io_en; // @[lib.scala 368:23] + wire rvclkhdr_10_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_11_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_11_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_11_io_en; // @[lib.scala 368:23] + wire rvclkhdr_11_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_12_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_12_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_12_io_en; // @[lib.scala 368:23] + wire rvclkhdr_12_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_13_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_13_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_13_io_en; // @[lib.scala 368:23] + wire rvclkhdr_13_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_14_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_14_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_14_io_en; // @[lib.scala 368:23] + wire rvclkhdr_14_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_15_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_15_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_15_io_en; // @[lib.scala 368:23] + wire rvclkhdr_15_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_16_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_16_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_16_io_en; // @[lib.scala 368:23] + wire rvclkhdr_16_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_17_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_17_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_17_io_en; // @[lib.scala 368:23] + wire rvclkhdr_17_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_18_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_18_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_18_io_en; // @[lib.scala 368:23] + wire rvclkhdr_18_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_19_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_19_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_19_io_en; // @[lib.scala 368:23] + wire rvclkhdr_19_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_20_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_20_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_20_io_en; // @[lib.scala 368:23] + wire rvclkhdr_20_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_21_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_21_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_21_io_en; // @[lib.scala 368:23] + wire rvclkhdr_21_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_22_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_22_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_22_io_en; // @[lib.scala 368:23] + wire rvclkhdr_22_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_23_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_23_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_23_io_en; // @[lib.scala 368:23] + wire rvclkhdr_23_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_24_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_24_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_24_io_en; // @[lib.scala 368:23] + wire rvclkhdr_24_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_25_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_25_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_25_io_en; // @[lib.scala 368:23] + wire rvclkhdr_25_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_26_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_26_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_26_io_en; // @[lib.scala 368:23] + wire rvclkhdr_26_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_27_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_27_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_27_io_en; // @[lib.scala 368:23] + wire rvclkhdr_27_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_28_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_28_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_28_io_en; // @[lib.scala 368:23] + wire rvclkhdr_28_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_29_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_29_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_29_io_en; // @[lib.scala 368:23] + wire rvclkhdr_29_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_30_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_30_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_30_io_en; // @[lib.scala 368:23] + wire rvclkhdr_30_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_31_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_31_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_31_io_en; // @[lib.scala 368:23] + wire rvclkhdr_31_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_32_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_32_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_32_io_en; // @[lib.scala 368:23] + wire rvclkhdr_32_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_33_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_33_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_33_io_en; // @[lib.scala 368:23] + wire rvclkhdr_33_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_34_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_34_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_34_io_en; // @[lib.scala 343:22] + wire rvclkhdr_34_io_scan_mode; // @[lib.scala 343:22] wire _T = ~io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 1450:45] wire _T_1 = io_dec_csr_wen_r & _T; // @[dec_tlu_ctl.scala 1450:43] wire _T_2 = ~io_rfpc_i0_r; // @[dec_tlu_ctl.scala 1450:68] wire _T_5 = io_dec_csr_wraddr_r == 12'h300; // @[dec_tlu_ctl.scala 1451:71] wire wr_mstatus_r = io_dec_csr_wen_r_mod & _T_5; // @[dec_tlu_ctl.scala 1451:42] - wire _T_498 = io_dec_csr_wraddr_r == 12'h7c6; // @[dec_tlu_ctl.scala 1837:68] - wire wr_mpmc_r = io_dec_csr_wen_r_mod & _T_498; // @[dec_tlu_ctl.scala 1837:39] - wire _T_510 = ~io_dec_csr_wrdata_r[1]; // @[dec_tlu_ctl.scala 1845:37] + wire _T_488 = io_dec_csr_wraddr_r == 12'h7c6; // @[dec_tlu_ctl.scala 1837:68] + wire wr_mpmc_r = io_dec_csr_wen_r_mod & _T_488; // @[dec_tlu_ctl.scala 1837:39] + wire _T_500 = ~io_dec_csr_wrdata_r[1]; // @[dec_tlu_ctl.scala 1845:37] reg mpmc_b; // @[dec_tlu_ctl.scala 1847:44] wire mpmc = ~mpmc_b; // @[dec_tlu_ctl.scala 1850:10] - wire _T_511 = ~mpmc; // @[dec_tlu_ctl.scala 1845:62] - wire mpmc_b_ns = wr_mpmc_r ? _T_510 : _T_511; // @[dec_tlu_ctl.scala 1845:18] + wire _T_501 = ~mpmc; // @[dec_tlu_ctl.scala 1845:62] + wire mpmc_b_ns = wr_mpmc_r ? _T_500 : _T_501; // @[dec_tlu_ctl.scala 1845:18] wire _T_6 = ~mpmc_b_ns; // @[dec_tlu_ctl.scala 1454:28] wire set_mie_pmu_fw_halt = _T_6 & io_fw_halt_req; // @[dec_tlu_ctl.scala 1454:39] wire _T_7 = ~wr_mstatus_r; // @[dec_tlu_ctl.scala 1457:5] @@ -50930,26 +50930,26 @@ module csr_tlu( wire _T_54 = _T_52 | io_dcsr[11]; // @[dec_tlu_ctl.scala 1465:81] reg [1:0] _T_56; // @[dec_tlu_ctl.scala 1467:11] wire _T_58 = io_dec_csr_wraddr_r == 12'h305; // @[dec_tlu_ctl.scala 1476:69] - reg [30:0] _T_62; // @[el2_lib.scala 514:16] - reg [31:0] mdccmect; // @[el2_lib.scala 514:16] - wire [62:0] _T_574 = 63'hffffffff << mdccmect[31:27]; // @[dec_tlu_ctl.scala 1897:41] - wire [31:0] _T_576 = {5'h0,mdccmect[26:0]}; // @[Cat.scala 29:58] - wire [62:0] _GEN_9 = {{31'd0}, _T_576}; // @[dec_tlu_ctl.scala 1897:61] - wire [62:0] _T_577 = _T_574 & _GEN_9; // @[dec_tlu_ctl.scala 1897:61] - wire mdccme_ce_req = |_T_577; // @[dec_tlu_ctl.scala 1897:94] - reg [31:0] miccmect; // @[el2_lib.scala 514:16] - wire [62:0] _T_554 = 63'hffffffff << miccmect[31:27]; // @[dec_tlu_ctl.scala 1882:40] - wire [31:0] _T_556 = {5'h0,miccmect[26:0]}; // @[Cat.scala 29:58] - wire [62:0] _GEN_10 = {{31'd0}, _T_556}; // @[dec_tlu_ctl.scala 1882:60] - wire [62:0] _T_557 = _T_554 & _GEN_10; // @[dec_tlu_ctl.scala 1882:60] - wire miccme_ce_req = |_T_557; // @[dec_tlu_ctl.scala 1882:93] + reg [30:0] _T_62; // @[lib.scala 374:16] + reg [31:0] mdccmect; // @[lib.scala 374:16] + wire [62:0] _T_564 = 63'hffffffff << mdccmect[31:27]; // @[dec_tlu_ctl.scala 1897:41] + wire [31:0] _T_566 = {5'h0,mdccmect[26:0]}; // @[Cat.scala 29:58] + wire [62:0] _GEN_9 = {{31'd0}, _T_566}; // @[dec_tlu_ctl.scala 1897:61] + wire [62:0] _T_567 = _T_564 & _GEN_9; // @[dec_tlu_ctl.scala 1897:61] + wire mdccme_ce_req = |_T_567; // @[dec_tlu_ctl.scala 1897:94] + reg [31:0] miccmect; // @[lib.scala 374:16] + wire [62:0] _T_544 = 63'hffffffff << miccmect[31:27]; // @[dec_tlu_ctl.scala 1882:40] + wire [31:0] _T_546 = {5'h0,miccmect[26:0]}; // @[Cat.scala 29:58] + wire [62:0] _GEN_10 = {{31'd0}, _T_546}; // @[dec_tlu_ctl.scala 1882:60] + wire [62:0] _T_547 = _T_544 & _GEN_10; // @[dec_tlu_ctl.scala 1882:60] + wire miccme_ce_req = |_T_547; // @[dec_tlu_ctl.scala 1882:93] wire _T_63 = mdccme_ce_req | miccme_ce_req; // @[dec_tlu_ctl.scala 1490:30] - reg [31:0] micect; // @[el2_lib.scala 514:16] - wire [62:0] _T_532 = 63'hffffffff << micect[31:27]; // @[dec_tlu_ctl.scala 1867:39] - wire [31:0] _T_534 = {5'h0,micect[26:0]}; // @[Cat.scala 29:58] - wire [62:0] _GEN_11 = {{31'd0}, _T_534}; // @[dec_tlu_ctl.scala 1867:57] - wire [62:0] _T_535 = _T_532 & _GEN_11; // @[dec_tlu_ctl.scala 1867:57] - wire mice_ce_req = |_T_535; // @[dec_tlu_ctl.scala 1867:88] + reg [31:0] micect; // @[lib.scala 374:16] + wire [62:0] _T_522 = 63'hffffffff << micect[31:27]; // @[dec_tlu_ctl.scala 1867:39] + wire [31:0] _T_524 = {5'h0,micect[26:0]}; // @[Cat.scala 29:58] + wire [62:0] _GEN_11 = {{31'd0}, _T_524}; // @[dec_tlu_ctl.scala 1867:57] + wire [62:0] _T_525 = _T_522 & _GEN_11; // @[dec_tlu_ctl.scala 1867:57] + wire mice_ce_req = |_T_525; // @[dec_tlu_ctl.scala 1867:88] wire ce_int = _T_63 | mice_ce_req; // @[dec_tlu_ctl.scala 1490:46] wire [2:0] _T_65 = {io_mexintpend,io_timer_int_sync,io_soft_int_sync}; // @[Cat.scala 29:58] wire [2:0] _T_67 = {ce_int,io_dec_timer_t0_pulse,io_dec_timer_t1_pulse}; // @[Cat.scala 29:58] @@ -50970,7 +50970,7 @@ module csr_tlu( wire _T_89 = _T_87 | mcountinhibit[0]; // @[dec_tlu_ctl.scala 1520:121] wire mcyclel_cout_in = ~_T_89; // @[dec_tlu_ctl.scala 1520:24] wire [31:0] _T_90 = {31'h0,mcyclel_cout_in}; // @[Cat.scala 29:58] - reg [31:0] mcyclel; // @[el2_lib.scala 514:16] + reg [31:0] mcyclel; // @[lib.scala 374:16] wire [32:0] mcyclel_inc = mcyclel + _T_90; // @[dec_tlu_ctl.scala 1524:25] wire mcyclel_cout = mcyclel_inc[32]; // @[dec_tlu_ctl.scala 1526:32] wire _T_101 = io_dec_csr_wraddr_r == 12'hb80; // @[dec_tlu_ctl.scala 1534:68] @@ -50978,7 +50978,7 @@ module csr_tlu( wire _T_98 = ~wr_mcycleh_r; // @[dec_tlu_ctl.scala 1528:71] reg mcyclel_cout_f; // @[dec_tlu_ctl.scala 1528:54] wire [31:0] _T_103 = {31'h0,mcyclel_cout_f}; // @[Cat.scala 29:58] - reg [31:0] mcycleh; // @[el2_lib.scala 514:16] + reg [31:0] mcycleh; // @[lib.scala 374:16] wire [31:0] mcycleh_inc = mcycleh + _T_103; // @[dec_tlu_ctl.scala 1536:28] wire _T_109 = io_ebreak_r | io_ecall_r; // @[dec_tlu_ctl.scala 1553:72] wire _T_110 = _T_109 | io_ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 1553:85] @@ -50989,7 +50989,7 @@ module csr_tlu( wire _T_117 = io_dec_csr_wraddr_r == 12'hb02; // @[dec_tlu_ctl.scala 1555:73] wire wr_minstretl_r = io_dec_csr_wen_r_mod & _T_117; // @[dec_tlu_ctl.scala 1555:44] wire [31:0] _T_118 = {31'h0,i0_valid_no_ebreak_ecall_r}; // @[Cat.scala 29:58] - reg [31:0] minstretl; // @[el2_lib.scala 514:16] + reg [31:0] minstretl; // @[lib.scala 374:16] wire [32:0] minstretl_inc = minstretl + _T_118; // @[dec_tlu_ctl.scala 1557:29] wire minstretl_cout = minstretl_inc[32]; // @[dec_tlu_ctl.scala 1558:36] reg minstret_enable_f; // @[dec_tlu_ctl.scala 1563:56] @@ -50998,10 +50998,10 @@ module csr_tlu( wire _T_125 = ~wr_minstreth_r; // @[dec_tlu_ctl.scala 1564:75] reg minstretl_cout_f; // @[dec_tlu_ctl.scala 1564:56] wire [31:0] _T_131 = {31'h0,minstretl_cout_f}; // @[Cat.scala 29:58] - reg [31:0] minstreth; // @[el2_lib.scala 514:16] + reg [31:0] minstreth; // @[lib.scala 374:16] wire [31:0] minstreth_inc = minstreth + _T_131; // @[dec_tlu_ctl.scala 1575:29] wire _T_139 = io_dec_csr_wraddr_r == 12'h340; // @[dec_tlu_ctl.scala 1586:72] - reg [31:0] mscratch; // @[el2_lib.scala 514:16] + reg [31:0] mscratch; // @[lib.scala 374:16] wire _T_142 = ~io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 1597:22] wire _T_143 = ~io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 1597:47] wire _T_144 = _T_142 & _T_143; // @[dec_tlu_ctl.scala 1597:45] @@ -51021,11 +51021,11 @@ module csr_tlu( wire [30:0] _T_160 = _T_156 | _T_157; // @[Mux.scala 27:72] wire [30:0] _T_161 = _T_160 | _T_158; // @[Mux.scala 27:72] wire _T_164 = sel_exu_npc_r | sel_flush_npc_r; // @[dec_tlu_ctl.scala 1607:48] - reg [30:0] _T_167; // @[el2_lib.scala 514:16] + reg [30:0] _T_167; // @[lib.scala 374:16] wire pc0_valid_r = _T_142 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 1610:44] wire _T_170 = ~pc0_valid_r; // @[dec_tlu_ctl.scala 1614:22] wire [30:0] _T_171 = pc0_valid_r ? io_dec_tlu_i0_pc_r : 31'h0; // @[Mux.scala 27:72] - reg [30:0] pc_r_d1; // @[el2_lib.scala 514:16] + reg [30:0] pc_r_d1; // @[lib.scala 374:16] wire [30:0] _T_172 = _T_170 ? pc_r_d1 : 31'h0; // @[Mux.scala 27:72] wire [30:0] pc_r = _T_171 | _T_172; // @[Mux.scala 27:72] wire _T_176 = io_dec_csr_wraddr_r == 12'h341; // @[dec_tlu_ctl.scala 1618:68] @@ -51138,426 +51138,430 @@ module csr_tlu( wire [31:0] _T_320 = _T_319 | _T_315; // @[Mux.scala 27:72] wire [31:0] _T_321 = _T_320 | _T_316; // @[Mux.scala 27:72] wire _T_325 = io_dec_csr_wraddr_r == 12'h7f8; // @[dec_tlu_ctl.scala 1713:68] - reg [8:0] mcgc; // @[el2_lib.scala 514:16] + reg [8:0] mcgc; // @[lib.scala 374:16] wire _T_337 = io_dec_csr_wraddr_r == 12'h7f9; // @[dec_tlu_ctl.scala 1743:68] - reg [14:0] mfdc_int; // @[el2_lib.scala 514:16] - wire [2:0] _T_341 = ~io_dec_csr_wrdata_r[18:16]; // @[dec_tlu_ctl.scala 1752:20] - wire _T_344 = ~io_dec_csr_wrdata_r[6]; // @[dec_tlu_ctl.scala 1752:75] - wire [6:0] _T_346 = {_T_344,io_dec_csr_wrdata_r[5:0]}; // @[Cat.scala 29:58] - wire [7:0] _T_347 = {_T_341,io_dec_csr_wrdata_r[11:7]}; // @[Cat.scala 29:58] - wire [2:0] _T_350 = ~mfdc_int[14:12]; // @[dec_tlu_ctl.scala 1753:20] - wire _T_353 = ~mfdc_int[6]; // @[dec_tlu_ctl.scala 1753:63] - wire [18:0] mfdc = {_T_350,4'h0,mfdc_int[11:7],_T_353,mfdc_int[5:0]}; // @[Cat.scala 29:58] - wire _T_367 = io_dec_csr_wraddr_r == 12'h7c2; // @[dec_tlu_ctl.scala 1776:77] - wire _T_368 = io_dec_csr_wen_r_mod & _T_367; // @[dec_tlu_ctl.scala 1776:48] - wire _T_370 = _T_368 & _T_297; // @[dec_tlu_ctl.scala 1776:87] - wire _T_371 = ~io_take_ext_int_start; // @[dec_tlu_ctl.scala 1776:113] - wire _T_374 = io_dec_csr_wraddr_r == 12'h7c0; // @[dec_tlu_ctl.scala 1783:68] - wire _T_378 = ~io_dec_csr_wrdata_r[31]; // @[dec_tlu_ctl.scala 1786:71] - wire _T_379 = io_dec_csr_wrdata_r[30] & _T_378; // @[dec_tlu_ctl.scala 1786:69] - wire _T_383 = ~io_dec_csr_wrdata_r[29]; // @[dec_tlu_ctl.scala 1787:73] - wire _T_384 = io_dec_csr_wrdata_r[28] & _T_383; // @[dec_tlu_ctl.scala 1787:71] - wire _T_388 = ~io_dec_csr_wrdata_r[27]; // @[dec_tlu_ctl.scala 1788:73] - wire _T_389 = io_dec_csr_wrdata_r[26] & _T_388; // @[dec_tlu_ctl.scala 1788:71] - wire _T_393 = ~io_dec_csr_wrdata_r[25]; // @[dec_tlu_ctl.scala 1789:73] - wire _T_394 = io_dec_csr_wrdata_r[24] & _T_393; // @[dec_tlu_ctl.scala 1789:71] - wire _T_398 = ~io_dec_csr_wrdata_r[23]; // @[dec_tlu_ctl.scala 1790:73] - wire _T_399 = io_dec_csr_wrdata_r[22] & _T_398; // @[dec_tlu_ctl.scala 1790:71] - wire _T_403 = ~io_dec_csr_wrdata_r[21]; // @[dec_tlu_ctl.scala 1791:73] - wire _T_404 = io_dec_csr_wrdata_r[20] & _T_403; // @[dec_tlu_ctl.scala 1791:71] - wire _T_408 = ~io_dec_csr_wrdata_r[19]; // @[dec_tlu_ctl.scala 1792:73] - wire _T_409 = io_dec_csr_wrdata_r[18] & _T_408; // @[dec_tlu_ctl.scala 1792:71] - wire _T_413 = ~io_dec_csr_wrdata_r[17]; // @[dec_tlu_ctl.scala 1793:73] - wire _T_414 = io_dec_csr_wrdata_r[16] & _T_413; // @[dec_tlu_ctl.scala 1793:71] - wire _T_418 = ~io_dec_csr_wrdata_r[15]; // @[dec_tlu_ctl.scala 1794:73] - wire _T_419 = io_dec_csr_wrdata_r[14] & _T_418; // @[dec_tlu_ctl.scala 1794:71] - wire _T_423 = ~io_dec_csr_wrdata_r[13]; // @[dec_tlu_ctl.scala 1795:73] - wire _T_424 = io_dec_csr_wrdata_r[12] & _T_423; // @[dec_tlu_ctl.scala 1795:71] - wire _T_428 = ~io_dec_csr_wrdata_r[11]; // @[dec_tlu_ctl.scala 1796:73] - wire _T_429 = io_dec_csr_wrdata_r[10] & _T_428; // @[dec_tlu_ctl.scala 1796:71] - wire _T_433 = ~io_dec_csr_wrdata_r[9]; // @[dec_tlu_ctl.scala 1797:73] - wire _T_434 = io_dec_csr_wrdata_r[8] & _T_433; // @[dec_tlu_ctl.scala 1797:70] - wire _T_438 = ~io_dec_csr_wrdata_r[7]; // @[dec_tlu_ctl.scala 1798:73] - wire _T_439 = io_dec_csr_wrdata_r[6] & _T_438; // @[dec_tlu_ctl.scala 1798:70] - wire _T_443 = ~io_dec_csr_wrdata_r[5]; // @[dec_tlu_ctl.scala 1799:73] - wire _T_444 = io_dec_csr_wrdata_r[4] & _T_443; // @[dec_tlu_ctl.scala 1799:70] - wire _T_448 = ~io_dec_csr_wrdata_r[3]; // @[dec_tlu_ctl.scala 1800:73] - wire _T_449 = io_dec_csr_wrdata_r[2] & _T_448; // @[dec_tlu_ctl.scala 1800:70] - wire _T_454 = io_dec_csr_wrdata_r[0] & _T_510; // @[dec_tlu_ctl.scala 1801:70] - wire [7:0] _T_461 = {io_dec_csr_wrdata_r[7],_T_439,io_dec_csr_wrdata_r[5],_T_444,io_dec_csr_wrdata_r[3],_T_449,io_dec_csr_wrdata_r[1],_T_454}; // @[Cat.scala 29:58] - wire [15:0] _T_469 = {io_dec_csr_wrdata_r[15],_T_419,io_dec_csr_wrdata_r[13],_T_424,io_dec_csr_wrdata_r[11],_T_429,io_dec_csr_wrdata_r[9],_T_434,_T_461}; // @[Cat.scala 29:58] - wire [7:0] _T_476 = {io_dec_csr_wrdata_r[23],_T_399,io_dec_csr_wrdata_r[21],_T_404,io_dec_csr_wrdata_r[19],_T_409,io_dec_csr_wrdata_r[17],_T_414}; // @[Cat.scala 29:58] - wire [15:0] _T_484 = {io_dec_csr_wrdata_r[31],_T_379,io_dec_csr_wrdata_r[29],_T_384,io_dec_csr_wrdata_r[27],_T_389,io_dec_csr_wrdata_r[25],_T_394,_T_476}; // @[Cat.scala 29:58] - reg [31:0] mrac; // @[el2_lib.scala 514:16] - wire _T_487 = io_dec_csr_wraddr_r == 12'hbc0; // @[dec_tlu_ctl.scala 1814:69] - wire wr_mdeau_r = io_dec_csr_wen_r_mod & _T_487; // @[dec_tlu_ctl.scala 1814:40] - wire _T_488 = ~wr_mdeau_r; // @[dec_tlu_ctl.scala 1824:59] - wire _T_489 = io_mdseac_locked_f & _T_488; // @[dec_tlu_ctl.scala 1824:57] - wire _T_491 = io_lsu_imprecise_error_store_any | io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 1826:49] - wire _T_492 = ~io_nmi_int_detected_f; // @[dec_tlu_ctl.scala 1826:86] - wire _T_493 = _T_491 & _T_492; // @[dec_tlu_ctl.scala 1826:84] - wire _T_494 = ~io_mdseac_locked_f; // @[dec_tlu_ctl.scala 1826:111] - wire mdseac_en = _T_493 & _T_494; // @[dec_tlu_ctl.scala 1826:109] - reg [31:0] mdseac; // @[el2_lib.scala 514:16] - wire _T_500 = wr_mpmc_r & io_dec_csr_wrdata_r[0]; // @[dec_tlu_ctl.scala 1841:30] - wire _T_501 = ~io_internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 1841:57] - wire _T_502 = _T_500 & _T_501; // @[dec_tlu_ctl.scala 1841:55] - wire _T_503 = ~io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 1841:89] - wire _T_516 = io_dec_csr_wrdata_r[31:27] > 5'h1a; // @[dec_tlu_ctl.scala 1859:48] - wire [4:0] csr_sat = _T_516 ? 5'h1a : io_dec_csr_wrdata_r[31:27]; // @[dec_tlu_ctl.scala 1859:19] - wire _T_519 = io_dec_csr_wraddr_r == 12'h7f0; // @[dec_tlu_ctl.scala 1861:70] - wire wr_micect_r = io_dec_csr_wen_r_mod & _T_519; // @[dec_tlu_ctl.scala 1861:41] - wire [26:0] _T_520 = {26'h0,io_ic_perr_r_d1}; // @[Cat.scala 29:58] - wire [31:0] _GEN_14 = {{5'd0}, _T_520}; // @[dec_tlu_ctl.scala 1862:23] - wire [31:0] _T_522 = micect + _GEN_14; // @[dec_tlu_ctl.scala 1862:23] - wire [31:0] _T_525 = {csr_sat,io_dec_csr_wrdata_r[26:0]}; // @[Cat.scala 29:58] - wire [26:0] micect_inc = _T_522[26:0]; // @[dec_tlu_ctl.scala 1862:13] - wire [31:0] _T_527 = {micect[31:27],micect_inc}; // @[Cat.scala 29:58] - wire _T_538 = io_dec_csr_wraddr_r == 12'h7f1; // @[dec_tlu_ctl.scala 1876:76] - wire wr_miccmect_r = io_dec_csr_wen_r_mod & _T_538; // @[dec_tlu_ctl.scala 1876:47] - wire _T_540 = io_iccm_sbecc_r_d1 | io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 1877:70] - wire [26:0] _T_541 = {26'h0,_T_540}; // @[Cat.scala 29:58] - wire [26:0] miccmect_inc = miccmect[26:0] + _T_541; // @[dec_tlu_ctl.scala 1877:33] - wire [31:0] _T_548 = {miccmect[31:27],miccmect_inc}; // @[Cat.scala 29:58] - wire _T_549 = wr_miccmect_r | io_iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 1880:48] - wire _T_560 = io_dec_csr_wraddr_r == 12'h7f2; // @[dec_tlu_ctl.scala 1891:76] - wire wr_mdccmect_r = io_dec_csr_wen_r_mod & _T_560; // @[dec_tlu_ctl.scala 1891:47] - wire [26:0] _T_562 = {26'h0,io_lsu_single_ecc_error_r_d1}; // @[Cat.scala 29:58] - wire [26:0] mdccmect_inc = mdccmect[26:0] + _T_562; // @[dec_tlu_ctl.scala 1892:33] - wire [31:0] _T_569 = {mdccmect[31:27],mdccmect_inc}; // @[Cat.scala 29:58] - wire _T_580 = io_dec_csr_wraddr_r == 12'h7ce; // @[dec_tlu_ctl.scala 1907:69] - wire wr_mfdht_r = io_dec_csr_wen_r_mod & _T_580; // @[dec_tlu_ctl.scala 1907:40] + reg [14:0] mfdc_int; // @[lib.scala 374:16] + wire [2:0] _T_341 = ~io_dec_csr_wrdata_r[18:16]; // @[dec_tlu_ctl.scala 1756:19] + wire [2:0] _T_345 = ~mfdc_int[14:12]; // @[dec_tlu_ctl.scala 1757:19] + wire [18:0] mfdc = {_T_345,4'h0,mfdc_int[11:0]}; // @[Cat.scala 29:58] + wire _T_357 = io_dec_csr_wraddr_r == 12'h7c2; // @[dec_tlu_ctl.scala 1776:77] + wire _T_358 = io_dec_csr_wen_r_mod & _T_357; // @[dec_tlu_ctl.scala 1776:48] + wire _T_360 = _T_358 & _T_297; // @[dec_tlu_ctl.scala 1776:87] + wire _T_361 = ~io_take_ext_int_start; // @[dec_tlu_ctl.scala 1776:113] + wire _T_364 = io_dec_csr_wraddr_r == 12'h7c0; // @[dec_tlu_ctl.scala 1783:68] + wire _T_368 = ~io_dec_csr_wrdata_r[31]; // @[dec_tlu_ctl.scala 1786:71] + wire _T_369 = io_dec_csr_wrdata_r[30] & _T_368; // @[dec_tlu_ctl.scala 1786:69] + wire _T_373 = ~io_dec_csr_wrdata_r[29]; // @[dec_tlu_ctl.scala 1787:73] + wire _T_374 = io_dec_csr_wrdata_r[28] & _T_373; // @[dec_tlu_ctl.scala 1787:71] + wire _T_378 = ~io_dec_csr_wrdata_r[27]; // @[dec_tlu_ctl.scala 1788:73] + wire _T_379 = io_dec_csr_wrdata_r[26] & _T_378; // @[dec_tlu_ctl.scala 1788:71] + wire _T_383 = ~io_dec_csr_wrdata_r[25]; // @[dec_tlu_ctl.scala 1789:73] + wire _T_384 = io_dec_csr_wrdata_r[24] & _T_383; // @[dec_tlu_ctl.scala 1789:71] + wire _T_388 = ~io_dec_csr_wrdata_r[23]; // @[dec_tlu_ctl.scala 1790:73] + wire _T_389 = io_dec_csr_wrdata_r[22] & _T_388; // @[dec_tlu_ctl.scala 1790:71] + wire _T_393 = ~io_dec_csr_wrdata_r[21]; // @[dec_tlu_ctl.scala 1791:73] + wire _T_394 = io_dec_csr_wrdata_r[20] & _T_393; // @[dec_tlu_ctl.scala 1791:71] + wire _T_398 = ~io_dec_csr_wrdata_r[19]; // @[dec_tlu_ctl.scala 1792:73] + wire _T_399 = io_dec_csr_wrdata_r[18] & _T_398; // @[dec_tlu_ctl.scala 1792:71] + wire _T_403 = ~io_dec_csr_wrdata_r[17]; // @[dec_tlu_ctl.scala 1793:73] + wire _T_404 = io_dec_csr_wrdata_r[16] & _T_403; // @[dec_tlu_ctl.scala 1793:71] + wire _T_408 = ~io_dec_csr_wrdata_r[15]; // @[dec_tlu_ctl.scala 1794:73] + wire _T_409 = io_dec_csr_wrdata_r[14] & _T_408; // @[dec_tlu_ctl.scala 1794:71] + wire _T_413 = ~io_dec_csr_wrdata_r[13]; // @[dec_tlu_ctl.scala 1795:73] + wire _T_414 = io_dec_csr_wrdata_r[12] & _T_413; // @[dec_tlu_ctl.scala 1795:71] + wire _T_418 = ~io_dec_csr_wrdata_r[11]; // @[dec_tlu_ctl.scala 1796:73] + wire _T_419 = io_dec_csr_wrdata_r[10] & _T_418; // @[dec_tlu_ctl.scala 1796:71] + wire _T_423 = ~io_dec_csr_wrdata_r[9]; // @[dec_tlu_ctl.scala 1797:73] + wire _T_424 = io_dec_csr_wrdata_r[8] & _T_423; // @[dec_tlu_ctl.scala 1797:70] + wire _T_428 = ~io_dec_csr_wrdata_r[7]; // @[dec_tlu_ctl.scala 1798:73] + wire _T_429 = io_dec_csr_wrdata_r[6] & _T_428; // @[dec_tlu_ctl.scala 1798:70] + wire _T_433 = ~io_dec_csr_wrdata_r[5]; // @[dec_tlu_ctl.scala 1799:73] + wire _T_434 = io_dec_csr_wrdata_r[4] & _T_433; // @[dec_tlu_ctl.scala 1799:70] + wire _T_438 = ~io_dec_csr_wrdata_r[3]; // @[dec_tlu_ctl.scala 1800:73] + wire _T_439 = io_dec_csr_wrdata_r[2] & _T_438; // @[dec_tlu_ctl.scala 1800:70] + wire _T_444 = io_dec_csr_wrdata_r[0] & _T_500; // @[dec_tlu_ctl.scala 1801:70] + wire [7:0] _T_451 = {io_dec_csr_wrdata_r[7],_T_429,io_dec_csr_wrdata_r[5],_T_434,io_dec_csr_wrdata_r[3],_T_439,io_dec_csr_wrdata_r[1],_T_444}; // @[Cat.scala 29:58] + wire [15:0] _T_459 = {io_dec_csr_wrdata_r[15],_T_409,io_dec_csr_wrdata_r[13],_T_414,io_dec_csr_wrdata_r[11],_T_419,io_dec_csr_wrdata_r[9],_T_424,_T_451}; // @[Cat.scala 29:58] + wire [7:0] _T_466 = {io_dec_csr_wrdata_r[23],_T_389,io_dec_csr_wrdata_r[21],_T_394,io_dec_csr_wrdata_r[19],_T_399,io_dec_csr_wrdata_r[17],_T_404}; // @[Cat.scala 29:58] + wire [15:0] _T_474 = {io_dec_csr_wrdata_r[31],_T_369,io_dec_csr_wrdata_r[29],_T_374,io_dec_csr_wrdata_r[27],_T_379,io_dec_csr_wrdata_r[25],_T_384,_T_466}; // @[Cat.scala 29:58] + reg [31:0] mrac; // @[lib.scala 374:16] + wire _T_477 = io_dec_csr_wraddr_r == 12'hbc0; // @[dec_tlu_ctl.scala 1814:69] + wire wr_mdeau_r = io_dec_csr_wen_r_mod & _T_477; // @[dec_tlu_ctl.scala 1814:40] + wire _T_478 = ~wr_mdeau_r; // @[dec_tlu_ctl.scala 1824:59] + wire _T_479 = io_mdseac_locked_f & _T_478; // @[dec_tlu_ctl.scala 1824:57] + wire _T_481 = io_lsu_imprecise_error_store_any | io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 1826:49] + wire _T_482 = ~io_nmi_int_detected_f; // @[dec_tlu_ctl.scala 1826:86] + wire _T_483 = _T_481 & _T_482; // @[dec_tlu_ctl.scala 1826:84] + wire _T_484 = ~io_mdseac_locked_f; // @[dec_tlu_ctl.scala 1826:111] + wire mdseac_en = _T_483 & _T_484; // @[dec_tlu_ctl.scala 1826:109] + reg [31:0] mdseac; // @[lib.scala 374:16] + wire _T_490 = wr_mpmc_r & io_dec_csr_wrdata_r[0]; // @[dec_tlu_ctl.scala 1841:30] + wire _T_491 = ~io_internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 1841:57] + wire _T_492 = _T_490 & _T_491; // @[dec_tlu_ctl.scala 1841:55] + wire _T_493 = ~io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 1841:89] + wire _T_506 = io_dec_csr_wrdata_r[31:27] > 5'h1a; // @[dec_tlu_ctl.scala 1859:48] + wire [4:0] csr_sat = _T_506 ? 5'h1a : io_dec_csr_wrdata_r[31:27]; // @[dec_tlu_ctl.scala 1859:19] + wire _T_509 = io_dec_csr_wraddr_r == 12'h7f0; // @[dec_tlu_ctl.scala 1861:70] + wire wr_micect_r = io_dec_csr_wen_r_mod & _T_509; // @[dec_tlu_ctl.scala 1861:41] + wire [26:0] _T_510 = {26'h0,io_ic_perr_r_d1}; // @[Cat.scala 29:58] + wire [31:0] _GEN_14 = {{5'd0}, _T_510}; // @[dec_tlu_ctl.scala 1862:23] + wire [31:0] _T_512 = micect + _GEN_14; // @[dec_tlu_ctl.scala 1862:23] + wire [31:0] _T_515 = {csr_sat,io_dec_csr_wrdata_r[26:0]}; // @[Cat.scala 29:58] + wire [26:0] micect_inc = _T_512[26:0]; // @[dec_tlu_ctl.scala 1862:13] + wire [31:0] _T_517 = {micect[31:27],micect_inc}; // @[Cat.scala 29:58] + wire _T_528 = io_dec_csr_wraddr_r == 12'h7f1; // @[dec_tlu_ctl.scala 1876:76] + wire wr_miccmect_r = io_dec_csr_wen_r_mod & _T_528; // @[dec_tlu_ctl.scala 1876:47] + wire _T_530 = io_iccm_sbecc_r_d1 | io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 1877:70] + wire [26:0] _T_531 = {26'h0,_T_530}; // @[Cat.scala 29:58] + wire [26:0] miccmect_inc = miccmect[26:0] + _T_531; // @[dec_tlu_ctl.scala 1877:33] + wire [31:0] _T_538 = {miccmect[31:27],miccmect_inc}; // @[Cat.scala 29:58] + wire _T_539 = wr_miccmect_r | io_iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 1880:48] + wire _T_550 = io_dec_csr_wraddr_r == 12'h7f2; // @[dec_tlu_ctl.scala 1891:76] + wire wr_mdccmect_r = io_dec_csr_wen_r_mod & _T_550; // @[dec_tlu_ctl.scala 1891:47] + wire [26:0] _T_552 = {26'h0,io_lsu_single_ecc_error_r_d1}; // @[Cat.scala 29:58] + wire [26:0] mdccmect_inc = mdccmect[26:0] + _T_552; // @[dec_tlu_ctl.scala 1892:33] + wire [31:0] _T_559 = {mdccmect[31:27],mdccmect_inc}; // @[Cat.scala 29:58] + wire _T_570 = io_dec_csr_wraddr_r == 12'h7ce; // @[dec_tlu_ctl.scala 1907:69] + wire wr_mfdht_r = io_dec_csr_wen_r_mod & _T_570; // @[dec_tlu_ctl.scala 1907:40] reg [5:0] mfdht; // @[dec_tlu_ctl.scala 1911:43] - wire _T_585 = io_dec_csr_wraddr_r == 12'h7cf; // @[dec_tlu_ctl.scala 1920:69] - wire wr_mfdhs_r = io_dec_csr_wen_r_mod & _T_585; // @[dec_tlu_ctl.scala 1920:40] - wire _T_588 = ~io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1923:43] - wire _T_589 = io_dbg_tlu_halted & _T_588; // @[dec_tlu_ctl.scala 1923:41] - wire _T_591 = ~io_lsu_idle_any_f; // @[dec_tlu_ctl.scala 1923:78] - wire _T_592 = ~io_ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 1923:98] - wire [1:0] _T_593 = {_T_591,_T_592}; // @[Cat.scala 29:58] + wire _T_575 = io_dec_csr_wraddr_r == 12'h7cf; // @[dec_tlu_ctl.scala 1920:69] + wire wr_mfdhs_r = io_dec_csr_wen_r_mod & _T_575; // @[dec_tlu_ctl.scala 1920:40] + wire _T_578 = ~io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1923:43] + wire _T_579 = io_dbg_tlu_halted & _T_578; // @[dec_tlu_ctl.scala 1923:41] + wire _T_581 = ~io_lsu_idle_any_f; // @[dec_tlu_ctl.scala 1923:78] + wire _T_582 = ~io_ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 1923:98] + wire [1:0] _T_583 = {_T_581,_T_582}; // @[Cat.scala 29:58] reg [1:0] mfdhs; // @[Reg.scala 27:20] - wire _T_595 = wr_mfdhs_r | io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 1925:71] + wire _T_585 = wr_mfdhs_r | io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 1925:71] reg [31:0] force_halt_ctr_f; // @[Reg.scala 27:20] - wire [31:0] _T_600 = force_halt_ctr_f + 32'h1; // @[dec_tlu_ctl.scala 1927:74] - wire [62:0] _T_607 = 63'hffffffff << mfdht[5:1]; // @[dec_tlu_ctl.scala 1932:71] + wire [31:0] _T_590 = force_halt_ctr_f + 32'h1; // @[dec_tlu_ctl.scala 1927:74] + wire [62:0] _T_597 = 63'hffffffff << mfdht[5:1]; // @[dec_tlu_ctl.scala 1932:71] wire [62:0] _GEN_15 = {{31'd0}, force_halt_ctr_f}; // @[dec_tlu_ctl.scala 1932:48] - wire [62:0] _T_608 = _GEN_15 & _T_607; // @[dec_tlu_ctl.scala 1932:48] - wire _T_609 = |_T_608; // @[dec_tlu_ctl.scala 1932:87] - wire _T_612 = io_dec_csr_wraddr_r == 12'hbc8; // @[dec_tlu_ctl.scala 1940:69] - reg [21:0] meivt; // @[el2_lib.scala 514:16] - wire _T_631 = io_dec_csr_wraddr_r == 12'hbca; // @[dec_tlu_ctl.scala 1991:69] - wire _T_632 = io_dec_csr_wen_r_mod & _T_631; // @[dec_tlu_ctl.scala 1991:40] - wire wr_meicpct_r = _T_632 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1991:83] - reg [7:0] meihap; // @[el2_lib.scala 514:16] - wire _T_618 = io_dec_csr_wraddr_r == 12'hbcc; // @[dec_tlu_ctl.scala 1964:72] - wire wr_meicurpl_r = io_dec_csr_wen_r_mod & _T_618; // @[dec_tlu_ctl.scala 1964:43] + wire [62:0] _T_598 = _GEN_15 & _T_597; // @[dec_tlu_ctl.scala 1932:48] + wire _T_599 = |_T_598; // @[dec_tlu_ctl.scala 1932:87] + wire _T_602 = io_dec_csr_wraddr_r == 12'hbc8; // @[dec_tlu_ctl.scala 1940:69] + reg [21:0] meivt; // @[lib.scala 374:16] + wire _T_621 = io_dec_csr_wraddr_r == 12'hbca; // @[dec_tlu_ctl.scala 1991:69] + wire _T_622 = io_dec_csr_wen_r_mod & _T_621; // @[dec_tlu_ctl.scala 1991:40] + wire wr_meicpct_r = _T_622 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1991:83] + reg [7:0] meihap; // @[lib.scala 374:16] + wire _T_608 = io_dec_csr_wraddr_r == 12'hbcc; // @[dec_tlu_ctl.scala 1964:72] + wire wr_meicurpl_r = io_dec_csr_wen_r_mod & _T_608; // @[dec_tlu_ctl.scala 1964:43] reg [3:0] meicurpl; // @[dec_tlu_ctl.scala 1967:46] - wire _T_623 = io_dec_csr_wraddr_r == 12'hbcb; // @[dec_tlu_ctl.scala 1979:73] - wire _T_624 = io_dec_csr_wen_r_mod & _T_623; // @[dec_tlu_ctl.scala 1979:44] - wire wr_meicidpl_r = _T_624 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1979:88] + wire _T_613 = io_dec_csr_wraddr_r == 12'hbcb; // @[dec_tlu_ctl.scala 1979:73] + wire _T_614 = io_dec_csr_wen_r_mod & _T_613; // @[dec_tlu_ctl.scala 1979:44] + wire wr_meicidpl_r = _T_614 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1979:88] reg [3:0] meicidpl; // @[dec_tlu_ctl.scala 1984:44] - wire _T_635 = io_dec_csr_wraddr_r == 12'hbc9; // @[dec_tlu_ctl.scala 2000:69] - wire wr_meipt_r = io_dec_csr_wen_r_mod & _T_635; // @[dec_tlu_ctl.scala 2000:40] + wire _T_625 = io_dec_csr_wraddr_r == 12'hbc9; // @[dec_tlu_ctl.scala 2000:69] + wire wr_meipt_r = io_dec_csr_wen_r_mod & _T_625; // @[dec_tlu_ctl.scala 2000:40] reg [3:0] meipt; // @[dec_tlu_ctl.scala 2003:43] - wire _T_639 = io_trigger_hit_r_d1 & io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 2031:89] - wire trigger_hit_for_dscr_cause_r_d1 = io_trigger_hit_dmode_r_d1 | _T_639; // @[dec_tlu_ctl.scala 2031:66] - wire _T_640 = ~io_ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 2034:31] - wire _T_641 = io_dcsr_single_step_done_f & _T_640; // @[dec_tlu_ctl.scala 2034:29] - wire _T_642 = ~trigger_hit_for_dscr_cause_r_d1; // @[dec_tlu_ctl.scala 2034:63] - wire _T_643 = _T_641 & _T_642; // @[dec_tlu_ctl.scala 2034:61] - wire _T_644 = ~io_debug_halt_req; // @[dec_tlu_ctl.scala 2034:98] - wire _T_645 = _T_643 & _T_644; // @[dec_tlu_ctl.scala 2034:96] - wire _T_648 = io_debug_halt_req & _T_640; // @[dec_tlu_ctl.scala 2035:46] - wire _T_650 = _T_648 & _T_642; // @[dec_tlu_ctl.scala 2035:78] - wire _T_653 = io_ebreak_to_debug_mode_r_d1 & _T_642; // @[dec_tlu_ctl.scala 2036:75] - wire [2:0] _T_656 = _T_645 ? 3'h4 : 3'h0; // @[Mux.scala 27:72] - wire [2:0] _T_657 = _T_650 ? 3'h3 : 3'h0; // @[Mux.scala 27:72] - wire [2:0] _T_658 = _T_653 ? 3'h1 : 3'h0; // @[Mux.scala 27:72] - wire [2:0] _T_659 = trigger_hit_for_dscr_cause_r_d1 ? 3'h2 : 3'h0; // @[Mux.scala 27:72] - wire [2:0] _T_660 = _T_656 | _T_657; // @[Mux.scala 27:72] - wire [2:0] _T_661 = _T_660 | _T_658; // @[Mux.scala 27:72] - wire [2:0] dcsr_cause = _T_661 | _T_659; // @[Mux.scala 27:72] - wire _T_663 = io_allow_dbg_halt_csr_write & io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 2039:46] - wire _T_665 = io_dec_csr_wraddr_r == 12'h7b0; // @[dec_tlu_ctl.scala 2039:98] - wire wr_dcsr_r = _T_663 & _T_665; // @[dec_tlu_ctl.scala 2039:69] - wire _T_667 = io_dcsr[8:6] == 3'h3; // @[dec_tlu_ctl.scala 2045:75] - wire dcsr_cause_upgradeable = io_internal_dbg_halt_mode_f & _T_667; // @[dec_tlu_ctl.scala 2045:59] - wire _T_668 = ~io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 2046:59] - wire _T_669 = _T_668 | dcsr_cause_upgradeable; // @[dec_tlu_ctl.scala 2046:78] - wire enter_debug_halt_req_le = io_enter_debug_halt_req & _T_669; // @[dec_tlu_ctl.scala 2046:56] + wire _T_629 = io_trigger_hit_r_d1 & io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 2031:89] + wire trigger_hit_for_dscr_cause_r_d1 = io_trigger_hit_dmode_r_d1 | _T_629; // @[dec_tlu_ctl.scala 2031:66] + wire _T_630 = ~io_ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 2034:31] + wire _T_631 = io_dcsr_single_step_done_f & _T_630; // @[dec_tlu_ctl.scala 2034:29] + wire _T_632 = ~trigger_hit_for_dscr_cause_r_d1; // @[dec_tlu_ctl.scala 2034:63] + wire _T_633 = _T_631 & _T_632; // @[dec_tlu_ctl.scala 2034:61] + wire _T_634 = ~io_debug_halt_req; // @[dec_tlu_ctl.scala 2034:98] + wire _T_635 = _T_633 & _T_634; // @[dec_tlu_ctl.scala 2034:96] + wire _T_638 = io_debug_halt_req & _T_630; // @[dec_tlu_ctl.scala 2035:46] + wire _T_640 = _T_638 & _T_632; // @[dec_tlu_ctl.scala 2035:78] + wire _T_643 = io_ebreak_to_debug_mode_r_d1 & _T_632; // @[dec_tlu_ctl.scala 2036:75] + wire [2:0] _T_646 = _T_635 ? 3'h4 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_647 = _T_640 ? 3'h3 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_648 = _T_643 ? 3'h1 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_649 = trigger_hit_for_dscr_cause_r_d1 ? 3'h2 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_650 = _T_646 | _T_647; // @[Mux.scala 27:72] + wire [2:0] _T_651 = _T_650 | _T_648; // @[Mux.scala 27:72] + wire [2:0] dcsr_cause = _T_651 | _T_649; // @[Mux.scala 27:72] + wire _T_653 = io_allow_dbg_halt_csr_write & io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 2039:46] + wire _T_655 = io_dec_csr_wraddr_r == 12'h7b0; // @[dec_tlu_ctl.scala 2039:98] + wire wr_dcsr_r = _T_653 & _T_655; // @[dec_tlu_ctl.scala 2039:69] + wire _T_657 = io_dcsr[8:6] == 3'h3; // @[dec_tlu_ctl.scala 2045:75] + wire dcsr_cause_upgradeable = io_internal_dbg_halt_mode_f & _T_657; // @[dec_tlu_ctl.scala 2045:59] + wire _T_658 = ~io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 2046:59] + wire _T_659 = _T_658 | dcsr_cause_upgradeable; // @[dec_tlu_ctl.scala 2046:78] + wire enter_debug_halt_req_le = io_enter_debug_halt_req & _T_659; // @[dec_tlu_ctl.scala 2046:56] wire nmi_in_debug_mode = io_nmi_int_detected_f & io_internal_dbg_halt_mode_f; // @[dec_tlu_ctl.scala 2048:48] - wire [15:0] _T_675 = {io_dcsr[15:9],dcsr_cause,io_dcsr[5:2],2'h3}; // @[Cat.scala 29:58] - wire _T_681 = nmi_in_debug_mode | io_dcsr[3]; // @[dec_tlu_ctl.scala 2050:145] - wire [15:0] _T_690 = {io_dec_csr_wrdata_r[15],3'h0,io_dec_csr_wrdata_r[11:10],1'h0,io_dcsr[8:6],2'h0,_T_681,io_dec_csr_wrdata_r[2],2'h3}; // @[Cat.scala 29:58] - wire [15:0] _T_695 = {io_dcsr[15:4],nmi_in_debug_mode,io_dcsr[2],2'h3}; // @[Cat.scala 29:58] - wire _T_697 = enter_debug_halt_req_le | wr_dcsr_r; // @[dec_tlu_ctl.scala 2052:54] - wire _T_698 = _T_697 | io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 2052:66] - reg [15:0] _T_701; // @[el2_lib.scala 514:16] - wire _T_704 = io_dec_csr_wraddr_r == 12'h7b1; // @[dec_tlu_ctl.scala 2060:97] - wire wr_dpc_r = _T_663 & _T_704; // @[dec_tlu_ctl.scala 2060:68] - wire _T_707 = ~io_request_debug_mode_done; // @[dec_tlu_ctl.scala 2061:67] - wire dpc_capture_npc = _T_589 & _T_707; // @[dec_tlu_ctl.scala 2061:65] - wire _T_708 = ~io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2065:21] - wire _T_709 = ~dpc_capture_npc; // @[dec_tlu_ctl.scala 2065:39] - wire _T_710 = _T_708 & _T_709; // @[dec_tlu_ctl.scala 2065:37] - wire _T_711 = _T_710 & wr_dpc_r; // @[dec_tlu_ctl.scala 2065:56] - wire _T_716 = _T_708 & dpc_capture_npc; // @[dec_tlu_ctl.scala 2067:49] - wire [30:0] _T_718 = _T_711 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72] - wire [30:0] _T_719 = io_request_debug_mode_r ? pc_r : 31'h0; // @[Mux.scala 27:72] - wire [30:0] _T_720 = _T_716 ? io_npc_r : 31'h0; // @[Mux.scala 27:72] - wire [30:0] _T_721 = _T_718 | _T_719; // @[Mux.scala 27:72] - wire _T_723 = wr_dpc_r | io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2069:36] - reg [30:0] _T_726; // @[el2_lib.scala 514:16] - wire [2:0] _T_730 = {io_dec_csr_wrdata_r[24],io_dec_csr_wrdata_r[21:20]}; // @[Cat.scala 29:58] - wire _T_733 = io_dec_csr_wraddr_r == 12'h7c8; // @[dec_tlu_ctl.scala 2084:102] - reg [16:0] dicawics; // @[el2_lib.scala 514:16] - wire _T_737 = io_dec_csr_wraddr_r == 12'h7c9; // @[dec_tlu_ctl.scala 2102:100] - wire wr_dicad0_r = _T_663 & _T_737; // @[dec_tlu_ctl.scala 2102:71] - reg [70:0] dicad0; // @[el2_lib.scala 514:16] - wire _T_743 = io_dec_csr_wraddr_r == 12'h7cc; // @[dec_tlu_ctl.scala 2115:101] - wire wr_dicad0h_r = _T_663 & _T_743; // @[dec_tlu_ctl.scala 2115:72] - reg [31:0] dicad0h; // @[el2_lib.scala 514:16] - wire _T_751 = io_dec_csr_wraddr_r == 12'h7ca; // @[dec_tlu_ctl.scala 2127:100] - wire _T_752 = _T_663 & _T_751; // @[dec_tlu_ctl.scala 2127:71] - wire _T_756 = _T_752 | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2131:78] - reg [31:0] _T_758; // @[Reg.scala 27:20] - wire [31:0] dicad1 = {25'h0,_T_758[6:0]}; // @[Cat.scala 29:58] - wire [38:0] _T_763 = {dicad1[6:0],dicad0h}; // @[Cat.scala 29:58] - wire _T_765 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 2159:52] - wire _T_766 = _T_765 & io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 2159:75] - wire _T_767 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 2159:98] - wire _T_768 = _T_766 & _T_767; // @[dec_tlu_ctl.scala 2159:96] - wire _T_770 = io_dec_csr_rdaddr_d == 12'h7cb; // @[dec_tlu_ctl.scala 2159:149] - wire _T_773 = io_dec_csr_wraddr_r == 12'h7cb; // @[dec_tlu_ctl.scala 2160:104] + wire [15:0] _T_665 = {io_dcsr[15:9],dcsr_cause,io_dcsr[5:2],2'h3}; // @[Cat.scala 29:58] + wire _T_671 = nmi_in_debug_mode | io_dcsr[3]; // @[dec_tlu_ctl.scala 2050:145] + wire [15:0] _T_680 = {io_dec_csr_wrdata_r[15],3'h0,io_dec_csr_wrdata_r[11:10],1'h0,io_dcsr[8:6],2'h0,_T_671,io_dec_csr_wrdata_r[2],2'h3}; // @[Cat.scala 29:58] + wire [15:0] _T_685 = {io_dcsr[15:4],nmi_in_debug_mode,io_dcsr[2],2'h3}; // @[Cat.scala 29:58] + wire _T_687 = enter_debug_halt_req_le | wr_dcsr_r; // @[dec_tlu_ctl.scala 2052:54] + wire _T_688 = _T_687 | io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 2052:66] + reg [15:0] _T_691; // @[lib.scala 374:16] + wire _T_694 = io_dec_csr_wraddr_r == 12'h7b1; // @[dec_tlu_ctl.scala 2060:97] + wire wr_dpc_r = _T_653 & _T_694; // @[dec_tlu_ctl.scala 2060:68] + wire _T_697 = ~io_request_debug_mode_done; // @[dec_tlu_ctl.scala 2061:67] + wire dpc_capture_npc = _T_579 & _T_697; // @[dec_tlu_ctl.scala 2061:65] + wire _T_698 = ~io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2065:21] + wire _T_699 = ~dpc_capture_npc; // @[dec_tlu_ctl.scala 2065:39] + wire _T_700 = _T_698 & _T_699; // @[dec_tlu_ctl.scala 2065:37] + wire _T_701 = _T_700 & wr_dpc_r; // @[dec_tlu_ctl.scala 2065:56] + wire _T_706 = _T_698 & dpc_capture_npc; // @[dec_tlu_ctl.scala 2067:49] + wire [30:0] _T_708 = _T_701 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_709 = io_request_debug_mode_r ? pc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_710 = _T_706 ? io_npc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_711 = _T_708 | _T_709; // @[Mux.scala 27:72] + wire _T_713 = wr_dpc_r | io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2069:36] + reg [30:0] _T_716; // @[lib.scala 374:16] + wire [2:0] _T_720 = {io_dec_csr_wrdata_r[24],io_dec_csr_wrdata_r[21:20]}; // @[Cat.scala 29:58] + wire _T_723 = io_dec_csr_wraddr_r == 12'h7c8; // @[dec_tlu_ctl.scala 2084:102] + reg [16:0] dicawics; // @[lib.scala 374:16] + wire _T_727 = io_dec_csr_wraddr_r == 12'h7c9; // @[dec_tlu_ctl.scala 2102:100] + wire wr_dicad0_r = _T_653 & _T_727; // @[dec_tlu_ctl.scala 2102:71] + reg [70:0] dicad0; // @[lib.scala 374:16] + wire _T_733 = io_dec_csr_wraddr_r == 12'h7cc; // @[dec_tlu_ctl.scala 2115:101] + wire wr_dicad0h_r = _T_653 & _T_733; // @[dec_tlu_ctl.scala 2115:72] + reg [31:0] dicad0h; // @[lib.scala 374:16] + wire _T_741 = io_dec_csr_wraddr_r == 12'h7ca; // @[dec_tlu_ctl.scala 2142:100] + wire _T_742 = _T_653 & _T_741; // @[dec_tlu_ctl.scala 2142:71] + wire _T_747 = _T_742 | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2146:77] + reg [3:0] _T_749; // @[Reg.scala 27:20] + wire [31:0] dicad1 = {28'h0,_T_749}; // @[Cat.scala 29:58] + wire [69:0] _T_756 = {2'h0,dicad1[3:0],dicad0h,dicad0[31:0]}; // @[Cat.scala 29:58] + wire _T_757 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 2159:52] + wire _T_758 = _T_757 & io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 2159:75] + wire _T_759 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 2159:98] + wire _T_760 = _T_758 & _T_759; // @[dec_tlu_ctl.scala 2159:96] + wire _T_762 = io_dec_csr_rdaddr_d == 12'h7cb; // @[dec_tlu_ctl.scala 2159:149] + wire _T_765 = io_dec_csr_wraddr_r == 12'h7cb; // @[dec_tlu_ctl.scala 2160:104] reg icache_rd_valid_f; // @[dec_tlu_ctl.scala 2162:58] reg icache_wr_valid_f; // @[dec_tlu_ctl.scala 2163:58] - wire _T_775 = io_dec_csr_wraddr_r == 12'h7a0; // @[dec_tlu_ctl.scala 2174:69] - wire wr_mtsel_r = io_dec_csr_wen_r_mod & _T_775; // @[dec_tlu_ctl.scala 2174:40] + wire _T_767 = io_dec_csr_wraddr_r == 12'h7a0; // @[dec_tlu_ctl.scala 2174:69] + wire wr_mtsel_r = io_dec_csr_wen_r_mod & _T_767; // @[dec_tlu_ctl.scala 2174:40] reg [1:0] mtsel; // @[dec_tlu_ctl.scala 2177:43] - wire tdata_load = io_dec_csr_wrdata_r[0] & _T_408; // @[dec_tlu_ctl.scala 2212:42] - wire tdata_opcode = io_dec_csr_wrdata_r[2] & _T_408; // @[dec_tlu_ctl.scala 2214:44] - wire _T_786 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2216:46] - wire tdata_action = _T_786 & io_dec_csr_wrdata_r[12]; // @[dec_tlu_ctl.scala 2216:69] - wire [9:0] tdata_wrdata_r = {_T_786,io_dec_csr_wrdata_r[20:19],tdata_action,io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7:6],tdata_opcode,io_dec_csr_wrdata_r[1],tdata_load}; // @[Cat.scala 29:58] - wire _T_801 = io_dec_csr_wraddr_r == 12'h7a1; // @[dec_tlu_ctl.scala 2222:99] - wire _T_802 = io_dec_csr_wen_r_mod & _T_801; // @[dec_tlu_ctl.scala 2222:70] - wire _T_803 = mtsel == 2'h0; // @[dec_tlu_ctl.scala 2222:121] - wire _T_804 = _T_802 & _T_803; // @[dec_tlu_ctl.scala 2222:112] - wire _T_806 = ~io_mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 2222:138] - wire _T_807 = _T_806 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] - wire wr_mtdata1_t_r_0 = _T_804 & _T_807; // @[dec_tlu_ctl.scala 2222:135] - wire _T_812 = mtsel == 2'h1; // @[dec_tlu_ctl.scala 2222:121] - wire _T_813 = _T_802 & _T_812; // @[dec_tlu_ctl.scala 2222:112] - wire _T_815 = ~io_mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 2222:138] - wire _T_816 = _T_815 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] - wire wr_mtdata1_t_r_1 = _T_813 & _T_816; // @[dec_tlu_ctl.scala 2222:135] - wire _T_821 = mtsel == 2'h2; // @[dec_tlu_ctl.scala 2222:121] - wire _T_822 = _T_802 & _T_821; // @[dec_tlu_ctl.scala 2222:112] - wire _T_824 = ~io_mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 2222:138] - wire _T_825 = _T_824 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] - wire wr_mtdata1_t_r_2 = _T_822 & _T_825; // @[dec_tlu_ctl.scala 2222:135] - wire _T_830 = mtsel == 2'h3; // @[dec_tlu_ctl.scala 2222:121] - wire _T_831 = _T_802 & _T_830; // @[dec_tlu_ctl.scala 2222:112] - wire _T_833 = ~io_mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 2222:138] - wire _T_834 = _T_833 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] - wire wr_mtdata1_t_r_3 = _T_831 & _T_834; // @[dec_tlu_ctl.scala 2222:135] - wire _T_840 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[dec_tlu_ctl.scala 2223:139] - wire [9:0] _T_843 = {io_mtdata1_t_0[9],_T_840,io_mtdata1_t_0[7:0]}; // @[Cat.scala 29:58] - wire _T_849 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[dec_tlu_ctl.scala 2223:139] - wire [9:0] _T_852 = {io_mtdata1_t_1[9],_T_849,io_mtdata1_t_1[7:0]}; // @[Cat.scala 29:58] - wire _T_858 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[dec_tlu_ctl.scala 2223:139] - wire [9:0] _T_861 = {io_mtdata1_t_2[9],_T_858,io_mtdata1_t_2[7:0]}; // @[Cat.scala 29:58] - wire _T_867 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[dec_tlu_ctl.scala 2223:139] - wire [9:0] _T_870 = {io_mtdata1_t_3[9],_T_867,io_mtdata1_t_3[7:0]}; // @[Cat.scala 29:58] - reg [9:0] _T_872; // @[dec_tlu_ctl.scala 2225:74] - reg [9:0] _T_873; // @[dec_tlu_ctl.scala 2225:74] - reg [9:0] _T_874; // @[dec_tlu_ctl.scala 2225:74] - reg [9:0] _T_875; // @[dec_tlu_ctl.scala 2225:74] - wire [31:0] _T_890 = {4'h2,io_mtdata1_t_0[9],6'h1f,io_mtdata1_t_0[8:7],6'h0,io_mtdata1_t_0[6:5],3'h0,io_mtdata1_t_0[4:3],3'h0,io_mtdata1_t_0[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_905 = {4'h2,io_mtdata1_t_1[9],6'h1f,io_mtdata1_t_1[8:7],6'h0,io_mtdata1_t_1[6:5],3'h0,io_mtdata1_t_1[4:3],3'h0,io_mtdata1_t_1[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_920 = {4'h2,io_mtdata1_t_2[9],6'h1f,io_mtdata1_t_2[8:7],6'h0,io_mtdata1_t_2[6:5],3'h0,io_mtdata1_t_2[4:3],3'h0,io_mtdata1_t_2[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_935 = {4'h2,io_mtdata1_t_3[9],6'h1f,io_mtdata1_t_3[8:7],6'h0,io_mtdata1_t_3[6:5],3'h0,io_mtdata1_t_3[4:3],3'h0,io_mtdata1_t_3[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_936 = _T_803 ? _T_890 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_937 = _T_812 ? _T_905 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_938 = _T_821 ? _T_920 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_939 = _T_830 ? _T_935 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_940 = _T_936 | _T_937; // @[Mux.scala 27:72] - wire [31:0] _T_941 = _T_940 | _T_938; // @[Mux.scala 27:72] - wire [31:0] mtdata1_tsel_out = _T_941 | _T_939; // @[Mux.scala 27:72] - wire _T_968 = io_dec_csr_wraddr_r == 12'h7a2; // @[dec_tlu_ctl.scala 2242:98] - wire _T_969 = io_dec_csr_wen_r_mod & _T_968; // @[dec_tlu_ctl.scala 2242:69] - wire _T_971 = _T_969 & _T_803; // @[dec_tlu_ctl.scala 2242:111] - wire _T_980 = _T_969 & _T_812; // @[dec_tlu_ctl.scala 2242:111] - wire _T_989 = _T_969 & _T_821; // @[dec_tlu_ctl.scala 2242:111] - wire _T_998 = _T_969 & _T_830; // @[dec_tlu_ctl.scala 2242:111] - reg [31:0] mtdata2_t_0; // @[el2_lib.scala 514:16] - reg [31:0] mtdata2_t_1; // @[el2_lib.scala 514:16] - reg [31:0] mtdata2_t_2; // @[el2_lib.scala 514:16] - reg [31:0] mtdata2_t_3; // @[el2_lib.scala 514:16] - wire [31:0] _T_1015 = _T_803 ? mtdata2_t_0 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1016 = _T_812 ? mtdata2_t_1 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1017 = _T_821 ? mtdata2_t_2 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1018 = _T_830 ? mtdata2_t_3 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1019 = _T_1015 | _T_1016; // @[Mux.scala 27:72] - wire [31:0] _T_1020 = _T_1019 | _T_1017; // @[Mux.scala 27:72] - wire [31:0] mtdata2_tsel_out = _T_1020 | _T_1018; // @[Mux.scala 27:72] - wire [3:0] _T_1023 = io_tlu_i0_commit_cmt ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1023; // @[dec_tlu_ctl.scala 2267:59] - wire _T_1025 = ~mcountinhibit[3]; // @[dec_tlu_ctl.scala 2273:24] + wire tdata_load = io_dec_csr_wrdata_r[0] & _T_398; // @[dec_tlu_ctl.scala 2212:42] + wire tdata_opcode = io_dec_csr_wrdata_r[2] & _T_398; // @[dec_tlu_ctl.scala 2214:44] + wire _T_778 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2216:46] + wire tdata_action = _T_778 & io_dec_csr_wrdata_r[12]; // @[dec_tlu_ctl.scala 2216:69] + wire [9:0] tdata_wrdata_r = {_T_778,io_dec_csr_wrdata_r[20:19],tdata_action,io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7:6],tdata_opcode,io_dec_csr_wrdata_r[1],tdata_load}; // @[Cat.scala 29:58] + wire _T_793 = io_dec_csr_wraddr_r == 12'h7a1; // @[dec_tlu_ctl.scala 2222:99] + wire _T_794 = io_dec_csr_wen_r_mod & _T_793; // @[dec_tlu_ctl.scala 2222:70] + wire _T_795 = mtsel == 2'h0; // @[dec_tlu_ctl.scala 2222:121] + wire _T_796 = _T_794 & _T_795; // @[dec_tlu_ctl.scala 2222:112] + wire _T_798 = ~io_mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 2222:138] + wire _T_799 = _T_798 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] + wire wr_mtdata1_t_r_0 = _T_796 & _T_799; // @[dec_tlu_ctl.scala 2222:135] + wire _T_804 = mtsel == 2'h1; // @[dec_tlu_ctl.scala 2222:121] + wire _T_805 = _T_794 & _T_804; // @[dec_tlu_ctl.scala 2222:112] + wire _T_807 = ~io_mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 2222:138] + wire _T_808 = _T_807 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] + wire wr_mtdata1_t_r_1 = _T_805 & _T_808; // @[dec_tlu_ctl.scala 2222:135] + wire _T_813 = mtsel == 2'h2; // @[dec_tlu_ctl.scala 2222:121] + wire _T_814 = _T_794 & _T_813; // @[dec_tlu_ctl.scala 2222:112] + wire _T_816 = ~io_mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 2222:138] + wire _T_817 = _T_816 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] + wire wr_mtdata1_t_r_2 = _T_814 & _T_817; // @[dec_tlu_ctl.scala 2222:135] + wire _T_822 = mtsel == 2'h3; // @[dec_tlu_ctl.scala 2222:121] + wire _T_823 = _T_794 & _T_822; // @[dec_tlu_ctl.scala 2222:112] + wire _T_825 = ~io_mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 2222:138] + wire _T_826 = _T_825 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] + wire wr_mtdata1_t_r_3 = _T_823 & _T_826; // @[dec_tlu_ctl.scala 2222:135] + wire _T_832 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[dec_tlu_ctl.scala 2223:139] + wire [9:0] _T_835 = {io_mtdata1_t_0[9],_T_832,io_mtdata1_t_0[7:0]}; // @[Cat.scala 29:58] + wire _T_841 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[dec_tlu_ctl.scala 2223:139] + wire [9:0] _T_844 = {io_mtdata1_t_1[9],_T_841,io_mtdata1_t_1[7:0]}; // @[Cat.scala 29:58] + wire _T_850 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[dec_tlu_ctl.scala 2223:139] + wire [9:0] _T_853 = {io_mtdata1_t_2[9],_T_850,io_mtdata1_t_2[7:0]}; // @[Cat.scala 29:58] + wire _T_859 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[dec_tlu_ctl.scala 2223:139] + wire [9:0] _T_862 = {io_mtdata1_t_3[9],_T_859,io_mtdata1_t_3[7:0]}; // @[Cat.scala 29:58] + reg [9:0] _T_864; // @[dec_tlu_ctl.scala 2225:74] + reg [9:0] _T_865; // @[dec_tlu_ctl.scala 2225:74] + reg [9:0] _T_866; // @[dec_tlu_ctl.scala 2225:74] + reg [9:0] _T_867; // @[dec_tlu_ctl.scala 2225:74] + wire [31:0] _T_882 = {4'h2,io_mtdata1_t_0[9],6'h1f,io_mtdata1_t_0[8:7],6'h0,io_mtdata1_t_0[6:5],3'h0,io_mtdata1_t_0[4:3],3'h0,io_mtdata1_t_0[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_897 = {4'h2,io_mtdata1_t_1[9],6'h1f,io_mtdata1_t_1[8:7],6'h0,io_mtdata1_t_1[6:5],3'h0,io_mtdata1_t_1[4:3],3'h0,io_mtdata1_t_1[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_912 = {4'h2,io_mtdata1_t_2[9],6'h1f,io_mtdata1_t_2[8:7],6'h0,io_mtdata1_t_2[6:5],3'h0,io_mtdata1_t_2[4:3],3'h0,io_mtdata1_t_2[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_927 = {4'h2,io_mtdata1_t_3[9],6'h1f,io_mtdata1_t_3[8:7],6'h0,io_mtdata1_t_3[6:5],3'h0,io_mtdata1_t_3[4:3],3'h0,io_mtdata1_t_3[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_928 = _T_795 ? _T_882 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_929 = _T_804 ? _T_897 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_930 = _T_813 ? _T_912 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_931 = _T_822 ? _T_927 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_932 = _T_928 | _T_929; // @[Mux.scala 27:72] + wire [31:0] _T_933 = _T_932 | _T_930; // @[Mux.scala 27:72] + wire [31:0] mtdata1_tsel_out = _T_933 | _T_931; // @[Mux.scala 27:72] + wire _T_960 = io_dec_csr_wraddr_r == 12'h7a2; // @[dec_tlu_ctl.scala 2242:98] + wire _T_961 = io_dec_csr_wen_r_mod & _T_960; // @[dec_tlu_ctl.scala 2242:69] + wire _T_963 = _T_961 & _T_795; // @[dec_tlu_ctl.scala 2242:111] + wire _T_972 = _T_961 & _T_804; // @[dec_tlu_ctl.scala 2242:111] + wire _T_981 = _T_961 & _T_813; // @[dec_tlu_ctl.scala 2242:111] + wire _T_990 = _T_961 & _T_822; // @[dec_tlu_ctl.scala 2242:111] + reg [31:0] mtdata2_t_0; // @[lib.scala 374:16] + reg [31:0] mtdata2_t_1; // @[lib.scala 374:16] + reg [31:0] mtdata2_t_2; // @[lib.scala 374:16] + reg [31:0] mtdata2_t_3; // @[lib.scala 374:16] + wire [31:0] _T_1007 = _T_795 ? mtdata2_t_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1008 = _T_804 ? mtdata2_t_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1009 = _T_813 ? mtdata2_t_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1010 = _T_822 ? mtdata2_t_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1011 = _T_1007 | _T_1008; // @[Mux.scala 27:72] + wire [31:0] _T_1012 = _T_1011 | _T_1009; // @[Mux.scala 27:72] + wire [31:0] mtdata2_tsel_out = _T_1012 | _T_1010; // @[Mux.scala 27:72] + wire [3:0] _T_1015 = io_tlu_i0_commit_cmt ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1015; // @[dec_tlu_ctl.scala 2267:59] + wire _T_1017 = ~mcountinhibit[3]; // @[dec_tlu_ctl.scala 2273:24] reg [9:0] mhpme3; // @[Reg.scala 27:20] - wire _T_1026 = mhpme3 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1028 = mhpme3 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1030 = mhpme3 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1032 = mhpme3 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1034 = ~io_illegal_r; // @[dec_tlu_ctl.scala 2277:96] - wire _T_1035 = io_tlu_i0_commit_cmt & _T_1034; // @[dec_tlu_ctl.scala 2277:94] - wire _T_1036 = mhpme3 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1038 = ~io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2278:96] - wire _T_1039 = io_tlu_i0_commit_cmt & _T_1038; // @[dec_tlu_ctl.scala 2278:94] - wire _T_1041 = _T_1039 & _T_1034; // @[dec_tlu_ctl.scala 2278:115] - wire _T_1042 = mhpme3 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1044 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2279:94] - wire _T_1046 = _T_1044 & _T_1034; // @[dec_tlu_ctl.scala 2279:115] - wire _T_1047 = mhpme3 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1049 = mhpme3 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1051 = mhpme3 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1053 = mhpme3 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1055 = pmu_i0_itype_qual == 4'h1; // @[dec_tlu_ctl.scala 2283:91] - wire _T_1056 = mhpme3 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1058 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2284:105] - wire _T_1059 = mhpme3 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1061 = pmu_i0_itype_qual == 4'h2; // @[dec_tlu_ctl.scala 2285:91] - wire _T_1062 = mhpme3 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1064 = pmu_i0_itype_qual == 4'h3; // @[dec_tlu_ctl.scala 2286:91] - wire _T_1065 = mhpme3 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1068 = _T_1061 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2287:100] - wire _T_1069 = mhpme3 == 10'he; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1073 = _T_1064 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2288:101] - wire _T_1074 = mhpme3 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1076 = pmu_i0_itype_qual == 4'h4; // @[dec_tlu_ctl.scala 2289:89] - wire _T_1077 = mhpme3 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1079 = pmu_i0_itype_qual == 4'h5; // @[dec_tlu_ctl.scala 2290:89] - wire _T_1080 = mhpme3 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1082 = pmu_i0_itype_qual == 4'h6; // @[dec_tlu_ctl.scala 2291:89] - wire _T_1083 = mhpme3 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1085 = pmu_i0_itype_qual == 4'h7; // @[dec_tlu_ctl.scala 2292:89] - wire _T_1086 = mhpme3 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1088 = pmu_i0_itype_qual == 4'h8; // @[dec_tlu_ctl.scala 2293:89] - wire _T_1089 = mhpme3 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1091 = pmu_i0_itype_qual == 4'h9; // @[dec_tlu_ctl.scala 2294:89] - wire _T_1092 = mhpme3 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1094 = pmu_i0_itype_qual == 4'ha; // @[dec_tlu_ctl.scala 2295:89] - wire _T_1095 = mhpme3 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1097 = pmu_i0_itype_qual == 4'hb; // @[dec_tlu_ctl.scala 2296:89] - wire _T_1098 = mhpme3 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1100 = pmu_i0_itype_qual == 4'hc; // @[dec_tlu_ctl.scala 2297:89] - wire _T_1101 = mhpme3 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1103 = pmu_i0_itype_qual == 4'hd; // @[dec_tlu_ctl.scala 2298:89] - wire _T_1104 = pmu_i0_itype_qual == 4'he; // @[dec_tlu_ctl.scala 2298:122] - wire _T_1105 = _T_1103 | _T_1104; // @[dec_tlu_ctl.scala 2298:101] - wire _T_1106 = mhpme3 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1108 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2299:95] - wire _T_1109 = mhpme3 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1111 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2300:97] - wire _T_1112 = mhpme3 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1114 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2301:110] - wire _T_1115 = mhpme3 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1119 = mhpme3 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] - wire _T_1121 = mhpme3 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1123 = mhpme3 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1125 = mhpme3 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1127 = mhpme3 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1129 = mhpme3 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1131 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 2309:98] - wire _T_1132 = _T_1131 | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 2309:120] - wire _T_1133 = mhpme3 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1135 = io_take_timer_int | io_take_int_timer0_int; // @[dec_tlu_ctl.scala 2310:92] - wire _T_1136 = _T_1135 | io_take_int_timer1_int; // @[dec_tlu_ctl.scala 2310:117] - wire _T_1137 = mhpme3 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1139 = mhpme3 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1141 = mhpme3 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1143 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2313:97] - wire _T_1144 = _T_1143 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2313:129] - wire _T_1145 = mhpme3 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1147 = mhpme3 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] - wire _T_1149 = mhpme3 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] - wire _T_1151 = mhpme3 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] - wire _T_1153 = mhpme3 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] - wire _T_1155 = mhpme3 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] - wire _T_1157 = mhpme3 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] - wire _T_1159 = mhpme3 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] - wire _T_1163 = ~io_mstatus[0]; // @[dec_tlu_ctl.scala 2321:73] - wire _T_1164 = mhpme3 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] - wire [5:0] _T_1171 = io_mip & mie; // @[dec_tlu_ctl.scala 2322:113] - wire _T_1172 = |_T_1171; // @[dec_tlu_ctl.scala 2322:125] - wire _T_1173 = _T_1163 & _T_1172; // @[dec_tlu_ctl.scala 2322:98] - wire _T_1174 = mhpme3 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] - wire _T_1176 = pmu_i0_itype_qual == 4'hf; // @[dec_tlu_ctl.scala 2323:91] - wire _T_1177 = mhpme3 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] - wire _T_1179 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 2324:94] - wire _T_1180 = mhpme3 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] - wire _T_1182 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 2325:94] - wire _T_1183 = mhpme3 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] - wire _T_1185 = mhpme3 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] - wire _T_1187 = mhpme3 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] - wire _T_1189 = mhpme3 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] - wire _T_1191 = mhpme3 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] - wire _T_1194 = _T_1028 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_1195 = _T_1030 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_1196 = _T_1032 & _T_1035; // @[Mux.scala 27:72] - wire _T_1197 = _T_1036 & _T_1041; // @[Mux.scala 27:72] - wire _T_1198 = _T_1042 & _T_1046; // @[Mux.scala 27:72] - wire _T_1199 = _T_1047 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_1200 = _T_1049 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_1201 = _T_1051 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_1202 = _T_1053 & _T_1055; // @[Mux.scala 27:72] - wire _T_1203 = _T_1056 & _T_1058; // @[Mux.scala 27:72] - wire _T_1204 = _T_1059 & _T_1061; // @[Mux.scala 27:72] - wire _T_1205 = _T_1062 & _T_1064; // @[Mux.scala 27:72] - wire _T_1206 = _T_1065 & _T_1068; // @[Mux.scala 27:72] - wire _T_1207 = _T_1069 & _T_1073; // @[Mux.scala 27:72] - wire _T_1208 = _T_1074 & _T_1076; // @[Mux.scala 27:72] - wire _T_1209 = _T_1077 & _T_1079; // @[Mux.scala 27:72] - wire _T_1210 = _T_1080 & _T_1082; // @[Mux.scala 27:72] - wire _T_1211 = _T_1083 & _T_1085; // @[Mux.scala 27:72] - wire _T_1212 = _T_1086 & _T_1088; // @[Mux.scala 27:72] - wire _T_1213 = _T_1089 & _T_1091; // @[Mux.scala 27:72] - wire _T_1214 = _T_1092 & _T_1094; // @[Mux.scala 27:72] - wire _T_1215 = _T_1095 & _T_1097; // @[Mux.scala 27:72] - wire _T_1216 = _T_1098 & _T_1100; // @[Mux.scala 27:72] - wire _T_1217 = _T_1101 & _T_1105; // @[Mux.scala 27:72] - wire _T_1218 = _T_1106 & _T_1108; // @[Mux.scala 27:72] - wire _T_1219 = _T_1109 & _T_1111; // @[Mux.scala 27:72] - wire _T_1220 = _T_1112 & _T_1114; // @[Mux.scala 27:72] - wire _T_1221 = _T_1115 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_1223 = _T_1119 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_1224 = _T_1121 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_1225 = _T_1123 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_1226 = _T_1125 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_1227 = _T_1127 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_1228 = _T_1129 & _T_1132; // @[Mux.scala 27:72] - wire _T_1229 = _T_1133 & _T_1136; // @[Mux.scala 27:72] - wire _T_1230 = _T_1137 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_1231 = _T_1139 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_1232 = _T_1141 & _T_1144; // @[Mux.scala 27:72] - wire _T_1233 = _T_1145 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1234 = _T_1147 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1235 = _T_1149 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_1236 = _T_1151 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1237 = _T_1153 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1238 = _T_1155 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1239 = _T_1157 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1240 = _T_1159 & _T_1163; // @[Mux.scala 27:72] - wire _T_1241 = _T_1164 & _T_1173; // @[Mux.scala 27:72] - wire _T_1242 = _T_1174 & _T_1176; // @[Mux.scala 27:72] - wire _T_1243 = _T_1177 & _T_1179; // @[Mux.scala 27:72] - wire _T_1244 = _T_1180 & _T_1182; // @[Mux.scala 27:72] - wire _T_1245 = _T_1183 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_1246 = _T_1185 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_1247 = _T_1187 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_1248 = _T_1189 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_1249 = _T_1191 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_1250 = _T_1026 | _T_1194; // @[Mux.scala 27:72] + wire _T_1018 = mhpme3 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1020 = mhpme3 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1022 = mhpme3 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1024 = mhpme3 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1026 = ~io_illegal_r; // @[dec_tlu_ctl.scala 2277:96] + wire _T_1027 = io_tlu_i0_commit_cmt & _T_1026; // @[dec_tlu_ctl.scala 2277:94] + wire _T_1028 = mhpme3 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1030 = ~io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2278:96] + wire _T_1031 = io_tlu_i0_commit_cmt & _T_1030; // @[dec_tlu_ctl.scala 2278:94] + wire _T_1033 = _T_1031 & _T_1026; // @[dec_tlu_ctl.scala 2278:115] + wire _T_1034 = mhpme3 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1036 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2279:94] + wire _T_1038 = _T_1036 & _T_1026; // @[dec_tlu_ctl.scala 2279:115] + wire _T_1039 = mhpme3 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1041 = mhpme3 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1043 = mhpme3 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1045 = mhpme3 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1047 = pmu_i0_itype_qual == 4'h1; // @[dec_tlu_ctl.scala 2283:91] + wire _T_1048 = mhpme3 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1050 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2284:105] + wire _T_1051 = mhpme3 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1053 = pmu_i0_itype_qual == 4'h2; // @[dec_tlu_ctl.scala 2285:91] + wire _T_1054 = mhpme3 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1056 = pmu_i0_itype_qual == 4'h3; // @[dec_tlu_ctl.scala 2286:91] + wire _T_1057 = mhpme3 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1060 = _T_1053 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2287:100] + wire _T_1061 = mhpme3 == 10'he; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1065 = _T_1056 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2288:101] + wire _T_1066 = mhpme3 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1068 = pmu_i0_itype_qual == 4'h4; // @[dec_tlu_ctl.scala 2289:89] + wire _T_1069 = mhpme3 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1071 = pmu_i0_itype_qual == 4'h5; // @[dec_tlu_ctl.scala 2290:89] + wire _T_1072 = mhpme3 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1074 = pmu_i0_itype_qual == 4'h6; // @[dec_tlu_ctl.scala 2291:89] + wire _T_1075 = mhpme3 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1077 = pmu_i0_itype_qual == 4'h7; // @[dec_tlu_ctl.scala 2292:89] + wire _T_1078 = mhpme3 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1080 = pmu_i0_itype_qual == 4'h8; // @[dec_tlu_ctl.scala 2293:89] + wire _T_1081 = mhpme3 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1083 = pmu_i0_itype_qual == 4'h9; // @[dec_tlu_ctl.scala 2294:89] + wire _T_1084 = mhpme3 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1086 = pmu_i0_itype_qual == 4'ha; // @[dec_tlu_ctl.scala 2295:89] + wire _T_1087 = mhpme3 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1089 = pmu_i0_itype_qual == 4'hb; // @[dec_tlu_ctl.scala 2296:89] + wire _T_1090 = mhpme3 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1092 = pmu_i0_itype_qual == 4'hc; // @[dec_tlu_ctl.scala 2297:89] + wire _T_1093 = mhpme3 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1095 = pmu_i0_itype_qual == 4'hd; // @[dec_tlu_ctl.scala 2298:89] + wire _T_1096 = pmu_i0_itype_qual == 4'he; // @[dec_tlu_ctl.scala 2298:122] + wire _T_1097 = _T_1095 | _T_1096; // @[dec_tlu_ctl.scala 2298:101] + wire _T_1098 = mhpme3 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1100 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2299:95] + wire _T_1101 = mhpme3 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1103 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2300:97] + wire _T_1104 = mhpme3 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1106 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2301:110] + wire _T_1107 = mhpme3 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1111 = mhpme3 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] + wire _T_1113 = mhpme3 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1115 = mhpme3 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1117 = mhpme3 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1119 = mhpme3 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1121 = mhpme3 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1123 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 2309:98] + wire _T_1124 = _T_1123 | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 2309:120] + wire _T_1125 = mhpme3 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1127 = io_take_timer_int | io_take_int_timer0_int; // @[dec_tlu_ctl.scala 2310:92] + wire _T_1128 = _T_1127 | io_take_int_timer1_int; // @[dec_tlu_ctl.scala 2310:117] + wire _T_1129 = mhpme3 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1131 = mhpme3 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1133 = mhpme3 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1135 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2313:97] + wire _T_1136 = _T_1135 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2313:129] + wire _T_1137 = mhpme3 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] + wire _T_1139 = mhpme3 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] + wire _T_1141 = mhpme3 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] + wire _T_1143 = mhpme3 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] + wire _T_1145 = mhpme3 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] + wire _T_1147 = mhpme3 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] + wire _T_1149 = mhpme3 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] + wire _T_1151 = mhpme3 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] + wire _T_1155 = ~io_mstatus[0]; // @[dec_tlu_ctl.scala 2321:73] + wire _T_1156 = mhpme3 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] + wire [5:0] _T_1163 = io_mip & mie; // @[dec_tlu_ctl.scala 2322:113] + wire _T_1164 = |_T_1163; // @[dec_tlu_ctl.scala 2322:125] + wire _T_1165 = _T_1155 & _T_1164; // @[dec_tlu_ctl.scala 2322:98] + wire _T_1166 = mhpme3 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] + wire _T_1168 = pmu_i0_itype_qual == 4'hf; // @[dec_tlu_ctl.scala 2323:91] + wire _T_1169 = mhpme3 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] + wire _T_1171 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 2324:94] + wire _T_1172 = mhpme3 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] + wire _T_1174 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 2325:94] + wire _T_1175 = mhpme3 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] + wire _T_1177 = mhpme3 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] + wire _T_1179 = mhpme3 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] + wire _T_1181 = mhpme3 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] + wire _T_1183 = mhpme3 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] + wire _T_1186 = _T_1020 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1187 = _T_1022 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1188 = _T_1024 & _T_1027; // @[Mux.scala 27:72] + wire _T_1189 = _T_1028 & _T_1033; // @[Mux.scala 27:72] + wire _T_1190 = _T_1034 & _T_1038; // @[Mux.scala 27:72] + wire _T_1191 = _T_1039 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1192 = _T_1041 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1193 = _T_1043 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1194 = _T_1045 & _T_1047; // @[Mux.scala 27:72] + wire _T_1195 = _T_1048 & _T_1050; // @[Mux.scala 27:72] + wire _T_1196 = _T_1051 & _T_1053; // @[Mux.scala 27:72] + wire _T_1197 = _T_1054 & _T_1056; // @[Mux.scala 27:72] + wire _T_1198 = _T_1057 & _T_1060; // @[Mux.scala 27:72] + wire _T_1199 = _T_1061 & _T_1065; // @[Mux.scala 27:72] + wire _T_1200 = _T_1066 & _T_1068; // @[Mux.scala 27:72] + wire _T_1201 = _T_1069 & _T_1071; // @[Mux.scala 27:72] + wire _T_1202 = _T_1072 & _T_1074; // @[Mux.scala 27:72] + wire _T_1203 = _T_1075 & _T_1077; // @[Mux.scala 27:72] + wire _T_1204 = _T_1078 & _T_1080; // @[Mux.scala 27:72] + wire _T_1205 = _T_1081 & _T_1083; // @[Mux.scala 27:72] + wire _T_1206 = _T_1084 & _T_1086; // @[Mux.scala 27:72] + wire _T_1207 = _T_1087 & _T_1089; // @[Mux.scala 27:72] + wire _T_1208 = _T_1090 & _T_1092; // @[Mux.scala 27:72] + wire _T_1209 = _T_1093 & _T_1097; // @[Mux.scala 27:72] + wire _T_1210 = _T_1098 & _T_1100; // @[Mux.scala 27:72] + wire _T_1211 = _T_1101 & _T_1103; // @[Mux.scala 27:72] + wire _T_1212 = _T_1104 & _T_1106; // @[Mux.scala 27:72] + wire _T_1213 = _T_1107 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1215 = _T_1111 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1216 = _T_1113 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1217 = _T_1115 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1218 = _T_1117 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1219 = _T_1119 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1220 = _T_1121 & _T_1124; // @[Mux.scala 27:72] + wire _T_1221 = _T_1125 & _T_1128; // @[Mux.scala 27:72] + wire _T_1222 = _T_1129 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1223 = _T_1131 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1224 = _T_1133 & _T_1136; // @[Mux.scala 27:72] + wire _T_1225 = _T_1137 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1226 = _T_1139 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1227 = _T_1141 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1228 = _T_1143 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1229 = _T_1145 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1230 = _T_1147 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1231 = _T_1149 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1232 = _T_1151 & _T_1155; // @[Mux.scala 27:72] + wire _T_1233 = _T_1156 & _T_1165; // @[Mux.scala 27:72] + wire _T_1234 = _T_1166 & _T_1168; // @[Mux.scala 27:72] + wire _T_1235 = _T_1169 & _T_1171; // @[Mux.scala 27:72] + wire _T_1236 = _T_1172 & _T_1174; // @[Mux.scala 27:72] + wire _T_1237 = _T_1175 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1238 = _T_1177 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1239 = _T_1179 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1240 = _T_1181 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1241 = _T_1183 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1242 = _T_1018 | _T_1186; // @[Mux.scala 27:72] + wire _T_1243 = _T_1242 | _T_1187; // @[Mux.scala 27:72] + wire _T_1244 = _T_1243 | _T_1188; // @[Mux.scala 27:72] + wire _T_1245 = _T_1244 | _T_1189; // @[Mux.scala 27:72] + wire _T_1246 = _T_1245 | _T_1190; // @[Mux.scala 27:72] + wire _T_1247 = _T_1246 | _T_1191; // @[Mux.scala 27:72] + wire _T_1248 = _T_1247 | _T_1192; // @[Mux.scala 27:72] + wire _T_1249 = _T_1248 | _T_1193; // @[Mux.scala 27:72] + wire _T_1250 = _T_1249 | _T_1194; // @[Mux.scala 27:72] wire _T_1251 = _T_1250 | _T_1195; // @[Mux.scala 27:72] wire _T_1252 = _T_1251 | _T_1196; // @[Mux.scala 27:72] wire _T_1253 = _T_1252 | _T_1197; // @[Mux.scala 27:72] @@ -51577,7 +51581,7 @@ module csr_tlu( wire _T_1267 = _T_1266 | _T_1211; // @[Mux.scala 27:72] wire _T_1268 = _T_1267 | _T_1212; // @[Mux.scala 27:72] wire _T_1269 = _T_1268 | _T_1213; // @[Mux.scala 27:72] - wire _T_1270 = _T_1269 | _T_1214; // @[Mux.scala 27:72] + wire _T_1270 = _T_1269 | _T_1193; // @[Mux.scala 27:72] wire _T_1271 = _T_1270 | _T_1215; // @[Mux.scala 27:72] wire _T_1272 = _T_1271 | _T_1216; // @[Mux.scala 27:72] wire _T_1273 = _T_1272 | _T_1217; // @[Mux.scala 27:72] @@ -51585,7 +51589,7 @@ module csr_tlu( wire _T_1275 = _T_1274 | _T_1219; // @[Mux.scala 27:72] wire _T_1276 = _T_1275 | _T_1220; // @[Mux.scala 27:72] wire _T_1277 = _T_1276 | _T_1221; // @[Mux.scala 27:72] - wire _T_1278 = _T_1277 | _T_1201; // @[Mux.scala 27:72] + wire _T_1278 = _T_1277 | _T_1222; // @[Mux.scala 27:72] wire _T_1279 = _T_1278 | _T_1223; // @[Mux.scala 27:72] wire _T_1280 = _T_1279 | _T_1224; // @[Mux.scala 27:72] wire _T_1281 = _T_1280 | _T_1225; // @[Mux.scala 27:72] @@ -51605,129 +51609,129 @@ module csr_tlu( wire _T_1295 = _T_1294 | _T_1239; // @[Mux.scala 27:72] wire _T_1296 = _T_1295 | _T_1240; // @[Mux.scala 27:72] wire _T_1297 = _T_1296 | _T_1241; // @[Mux.scala 27:72] - wire _T_1298 = _T_1297 | _T_1242; // @[Mux.scala 27:72] - wire _T_1299 = _T_1298 | _T_1243; // @[Mux.scala 27:72] - wire _T_1300 = _T_1299 | _T_1244; // @[Mux.scala 27:72] - wire _T_1301 = _T_1300 | _T_1245; // @[Mux.scala 27:72] - wire _T_1302 = _T_1301 | _T_1246; // @[Mux.scala 27:72] - wire _T_1303 = _T_1302 | _T_1247; // @[Mux.scala 27:72] - wire _T_1304 = _T_1303 | _T_1248; // @[Mux.scala 27:72] - wire _T_1305 = _T_1304 | _T_1249; // @[Mux.scala 27:72] - wire mhpmc_inc_r_0 = _T_1025 & _T_1305; // @[dec_tlu_ctl.scala 2273:44] - wire _T_1309 = ~mcountinhibit[4]; // @[dec_tlu_ctl.scala 2273:24] + wire mhpmc_inc_r_0 = _T_1017 & _T_1297; // @[dec_tlu_ctl.scala 2273:44] + wire _T_1301 = ~mcountinhibit[4]; // @[dec_tlu_ctl.scala 2273:24] reg [9:0] mhpme4; // @[Reg.scala 27:20] - wire _T_1310 = mhpme4 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1312 = mhpme4 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1314 = mhpme4 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1316 = mhpme4 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1320 = mhpme4 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1326 = mhpme4 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1331 = mhpme4 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1333 = mhpme4 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1335 = mhpme4 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1337 = mhpme4 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1340 = mhpme4 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1343 = mhpme4 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1346 = mhpme4 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1349 = mhpme4 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1353 = mhpme4 == 10'he; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1358 = mhpme4 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1361 = mhpme4 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1364 = mhpme4 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1367 = mhpme4 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1370 = mhpme4 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1373 = mhpme4 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1376 = mhpme4 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1379 = mhpme4 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1382 = mhpme4 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1385 = mhpme4 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1390 = mhpme4 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1393 = mhpme4 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1396 = mhpme4 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1399 = mhpme4 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1403 = mhpme4 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] - wire _T_1405 = mhpme4 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1407 = mhpme4 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1409 = mhpme4 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1411 = mhpme4 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1413 = mhpme4 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1417 = mhpme4 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1421 = mhpme4 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1423 = mhpme4 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1425 = mhpme4 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1429 = mhpme4 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1431 = mhpme4 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] - wire _T_1433 = mhpme4 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] - wire _T_1435 = mhpme4 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] - wire _T_1437 = mhpme4 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] - wire _T_1439 = mhpme4 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] - wire _T_1441 = mhpme4 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] - wire _T_1443 = mhpme4 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] - wire _T_1448 = mhpme4 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] - wire _T_1458 = mhpme4 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] - wire _T_1461 = mhpme4 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] - wire _T_1464 = mhpme4 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] - wire _T_1467 = mhpme4 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] - wire _T_1469 = mhpme4 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] - wire _T_1471 = mhpme4 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] - wire _T_1473 = mhpme4 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] - wire _T_1475 = mhpme4 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] - wire _T_1478 = _T_1312 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_1479 = _T_1314 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_1480 = _T_1316 & _T_1035; // @[Mux.scala 27:72] - wire _T_1481 = _T_1320 & _T_1041; // @[Mux.scala 27:72] - wire _T_1482 = _T_1326 & _T_1046; // @[Mux.scala 27:72] - wire _T_1483 = _T_1331 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_1484 = _T_1333 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_1485 = _T_1335 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_1486 = _T_1337 & _T_1055; // @[Mux.scala 27:72] - wire _T_1487 = _T_1340 & _T_1058; // @[Mux.scala 27:72] - wire _T_1488 = _T_1343 & _T_1061; // @[Mux.scala 27:72] - wire _T_1489 = _T_1346 & _T_1064; // @[Mux.scala 27:72] - wire _T_1490 = _T_1349 & _T_1068; // @[Mux.scala 27:72] - wire _T_1491 = _T_1353 & _T_1073; // @[Mux.scala 27:72] - wire _T_1492 = _T_1358 & _T_1076; // @[Mux.scala 27:72] - wire _T_1493 = _T_1361 & _T_1079; // @[Mux.scala 27:72] - wire _T_1494 = _T_1364 & _T_1082; // @[Mux.scala 27:72] - wire _T_1495 = _T_1367 & _T_1085; // @[Mux.scala 27:72] - wire _T_1496 = _T_1370 & _T_1088; // @[Mux.scala 27:72] - wire _T_1497 = _T_1373 & _T_1091; // @[Mux.scala 27:72] - wire _T_1498 = _T_1376 & _T_1094; // @[Mux.scala 27:72] - wire _T_1499 = _T_1379 & _T_1097; // @[Mux.scala 27:72] - wire _T_1500 = _T_1382 & _T_1100; // @[Mux.scala 27:72] - wire _T_1501 = _T_1385 & _T_1105; // @[Mux.scala 27:72] - wire _T_1502 = _T_1390 & _T_1108; // @[Mux.scala 27:72] - wire _T_1503 = _T_1393 & _T_1111; // @[Mux.scala 27:72] - wire _T_1504 = _T_1396 & _T_1114; // @[Mux.scala 27:72] - wire _T_1505 = _T_1399 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_1507 = _T_1403 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_1508 = _T_1405 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_1509 = _T_1407 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_1510 = _T_1409 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_1511 = _T_1411 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_1512 = _T_1413 & _T_1132; // @[Mux.scala 27:72] - wire _T_1513 = _T_1417 & _T_1136; // @[Mux.scala 27:72] - wire _T_1514 = _T_1421 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_1515 = _T_1423 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_1516 = _T_1425 & _T_1144; // @[Mux.scala 27:72] - wire _T_1517 = _T_1429 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1518 = _T_1431 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1519 = _T_1433 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_1520 = _T_1435 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1521 = _T_1437 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1522 = _T_1439 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1523 = _T_1441 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1524 = _T_1443 & _T_1163; // @[Mux.scala 27:72] - wire _T_1525 = _T_1448 & _T_1173; // @[Mux.scala 27:72] - wire _T_1526 = _T_1458 & _T_1176; // @[Mux.scala 27:72] - wire _T_1527 = _T_1461 & _T_1179; // @[Mux.scala 27:72] - wire _T_1528 = _T_1464 & _T_1182; // @[Mux.scala 27:72] - wire _T_1529 = _T_1467 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_1530 = _T_1469 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_1531 = _T_1471 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_1532 = _T_1473 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_1533 = _T_1475 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_1534 = _T_1310 | _T_1478; // @[Mux.scala 27:72] + wire _T_1302 = mhpme4 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1304 = mhpme4 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1306 = mhpme4 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1308 = mhpme4 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1312 = mhpme4 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1318 = mhpme4 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1323 = mhpme4 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1325 = mhpme4 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1327 = mhpme4 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1329 = mhpme4 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1332 = mhpme4 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1335 = mhpme4 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1338 = mhpme4 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1341 = mhpme4 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1345 = mhpme4 == 10'he; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1350 = mhpme4 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1353 = mhpme4 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1356 = mhpme4 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1359 = mhpme4 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1362 = mhpme4 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1365 = mhpme4 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1368 = mhpme4 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1371 = mhpme4 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1374 = mhpme4 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1377 = mhpme4 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1382 = mhpme4 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1385 = mhpme4 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1388 = mhpme4 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1391 = mhpme4 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1395 = mhpme4 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] + wire _T_1397 = mhpme4 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1399 = mhpme4 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1401 = mhpme4 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1403 = mhpme4 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1405 = mhpme4 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1409 = mhpme4 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1413 = mhpme4 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1415 = mhpme4 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1417 = mhpme4 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1421 = mhpme4 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] + wire _T_1423 = mhpme4 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] + wire _T_1425 = mhpme4 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] + wire _T_1427 = mhpme4 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] + wire _T_1429 = mhpme4 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] + wire _T_1431 = mhpme4 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] + wire _T_1433 = mhpme4 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] + wire _T_1435 = mhpme4 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] + wire _T_1440 = mhpme4 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] + wire _T_1450 = mhpme4 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] + wire _T_1453 = mhpme4 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] + wire _T_1456 = mhpme4 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] + wire _T_1459 = mhpme4 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] + wire _T_1461 = mhpme4 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] + wire _T_1463 = mhpme4 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] + wire _T_1465 = mhpme4 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] + wire _T_1467 = mhpme4 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] + wire _T_1470 = _T_1304 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1471 = _T_1306 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1472 = _T_1308 & _T_1027; // @[Mux.scala 27:72] + wire _T_1473 = _T_1312 & _T_1033; // @[Mux.scala 27:72] + wire _T_1474 = _T_1318 & _T_1038; // @[Mux.scala 27:72] + wire _T_1475 = _T_1323 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1476 = _T_1325 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1477 = _T_1327 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1478 = _T_1329 & _T_1047; // @[Mux.scala 27:72] + wire _T_1479 = _T_1332 & _T_1050; // @[Mux.scala 27:72] + wire _T_1480 = _T_1335 & _T_1053; // @[Mux.scala 27:72] + wire _T_1481 = _T_1338 & _T_1056; // @[Mux.scala 27:72] + wire _T_1482 = _T_1341 & _T_1060; // @[Mux.scala 27:72] + wire _T_1483 = _T_1345 & _T_1065; // @[Mux.scala 27:72] + wire _T_1484 = _T_1350 & _T_1068; // @[Mux.scala 27:72] + wire _T_1485 = _T_1353 & _T_1071; // @[Mux.scala 27:72] + wire _T_1486 = _T_1356 & _T_1074; // @[Mux.scala 27:72] + wire _T_1487 = _T_1359 & _T_1077; // @[Mux.scala 27:72] + wire _T_1488 = _T_1362 & _T_1080; // @[Mux.scala 27:72] + wire _T_1489 = _T_1365 & _T_1083; // @[Mux.scala 27:72] + wire _T_1490 = _T_1368 & _T_1086; // @[Mux.scala 27:72] + wire _T_1491 = _T_1371 & _T_1089; // @[Mux.scala 27:72] + wire _T_1492 = _T_1374 & _T_1092; // @[Mux.scala 27:72] + wire _T_1493 = _T_1377 & _T_1097; // @[Mux.scala 27:72] + wire _T_1494 = _T_1382 & _T_1100; // @[Mux.scala 27:72] + wire _T_1495 = _T_1385 & _T_1103; // @[Mux.scala 27:72] + wire _T_1496 = _T_1388 & _T_1106; // @[Mux.scala 27:72] + wire _T_1497 = _T_1391 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1499 = _T_1395 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1500 = _T_1397 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1501 = _T_1399 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1502 = _T_1401 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1503 = _T_1403 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1504 = _T_1405 & _T_1124; // @[Mux.scala 27:72] + wire _T_1505 = _T_1409 & _T_1128; // @[Mux.scala 27:72] + wire _T_1506 = _T_1413 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1507 = _T_1415 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1508 = _T_1417 & _T_1136; // @[Mux.scala 27:72] + wire _T_1509 = _T_1421 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1510 = _T_1423 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1511 = _T_1425 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1512 = _T_1427 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1513 = _T_1429 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1514 = _T_1431 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1515 = _T_1433 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1516 = _T_1435 & _T_1155; // @[Mux.scala 27:72] + wire _T_1517 = _T_1440 & _T_1165; // @[Mux.scala 27:72] + wire _T_1518 = _T_1450 & _T_1168; // @[Mux.scala 27:72] + wire _T_1519 = _T_1453 & _T_1171; // @[Mux.scala 27:72] + wire _T_1520 = _T_1456 & _T_1174; // @[Mux.scala 27:72] + wire _T_1521 = _T_1459 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1522 = _T_1461 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1523 = _T_1463 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1524 = _T_1465 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1525 = _T_1467 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1526 = _T_1302 | _T_1470; // @[Mux.scala 27:72] + wire _T_1527 = _T_1526 | _T_1471; // @[Mux.scala 27:72] + wire _T_1528 = _T_1527 | _T_1472; // @[Mux.scala 27:72] + wire _T_1529 = _T_1528 | _T_1473; // @[Mux.scala 27:72] + wire _T_1530 = _T_1529 | _T_1474; // @[Mux.scala 27:72] + wire _T_1531 = _T_1530 | _T_1475; // @[Mux.scala 27:72] + wire _T_1532 = _T_1531 | _T_1476; // @[Mux.scala 27:72] + wire _T_1533 = _T_1532 | _T_1477; // @[Mux.scala 27:72] + wire _T_1534 = _T_1533 | _T_1478; // @[Mux.scala 27:72] wire _T_1535 = _T_1534 | _T_1479; // @[Mux.scala 27:72] wire _T_1536 = _T_1535 | _T_1480; // @[Mux.scala 27:72] wire _T_1537 = _T_1536 | _T_1481; // @[Mux.scala 27:72] @@ -51747,7 +51751,7 @@ module csr_tlu( wire _T_1551 = _T_1550 | _T_1495; // @[Mux.scala 27:72] wire _T_1552 = _T_1551 | _T_1496; // @[Mux.scala 27:72] wire _T_1553 = _T_1552 | _T_1497; // @[Mux.scala 27:72] - wire _T_1554 = _T_1553 | _T_1498; // @[Mux.scala 27:72] + wire _T_1554 = _T_1553 | _T_1477; // @[Mux.scala 27:72] wire _T_1555 = _T_1554 | _T_1499; // @[Mux.scala 27:72] wire _T_1556 = _T_1555 | _T_1500; // @[Mux.scala 27:72] wire _T_1557 = _T_1556 | _T_1501; // @[Mux.scala 27:72] @@ -51755,7 +51759,7 @@ module csr_tlu( wire _T_1559 = _T_1558 | _T_1503; // @[Mux.scala 27:72] wire _T_1560 = _T_1559 | _T_1504; // @[Mux.scala 27:72] wire _T_1561 = _T_1560 | _T_1505; // @[Mux.scala 27:72] - wire _T_1562 = _T_1561 | _T_1485; // @[Mux.scala 27:72] + wire _T_1562 = _T_1561 | _T_1506; // @[Mux.scala 27:72] wire _T_1563 = _T_1562 | _T_1507; // @[Mux.scala 27:72] wire _T_1564 = _T_1563 | _T_1508; // @[Mux.scala 27:72] wire _T_1565 = _T_1564 | _T_1509; // @[Mux.scala 27:72] @@ -51775,129 +51779,129 @@ module csr_tlu( wire _T_1579 = _T_1578 | _T_1523; // @[Mux.scala 27:72] wire _T_1580 = _T_1579 | _T_1524; // @[Mux.scala 27:72] wire _T_1581 = _T_1580 | _T_1525; // @[Mux.scala 27:72] - wire _T_1582 = _T_1581 | _T_1526; // @[Mux.scala 27:72] - wire _T_1583 = _T_1582 | _T_1527; // @[Mux.scala 27:72] - wire _T_1584 = _T_1583 | _T_1528; // @[Mux.scala 27:72] - wire _T_1585 = _T_1584 | _T_1529; // @[Mux.scala 27:72] - wire _T_1586 = _T_1585 | _T_1530; // @[Mux.scala 27:72] - wire _T_1587 = _T_1586 | _T_1531; // @[Mux.scala 27:72] - wire _T_1588 = _T_1587 | _T_1532; // @[Mux.scala 27:72] - wire _T_1589 = _T_1588 | _T_1533; // @[Mux.scala 27:72] - wire mhpmc_inc_r_1 = _T_1309 & _T_1589; // @[dec_tlu_ctl.scala 2273:44] - wire _T_1593 = ~mcountinhibit[5]; // @[dec_tlu_ctl.scala 2273:24] + wire mhpmc_inc_r_1 = _T_1301 & _T_1581; // @[dec_tlu_ctl.scala 2273:44] + wire _T_1585 = ~mcountinhibit[5]; // @[dec_tlu_ctl.scala 2273:24] reg [9:0] mhpme5; // @[Reg.scala 27:20] - wire _T_1594 = mhpme5 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1596 = mhpme5 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1598 = mhpme5 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1600 = mhpme5 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1604 = mhpme5 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1610 = mhpme5 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1615 = mhpme5 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1617 = mhpme5 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1619 = mhpme5 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1621 = mhpme5 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1624 = mhpme5 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1627 = mhpme5 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1630 = mhpme5 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1633 = mhpme5 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1637 = mhpme5 == 10'he; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1642 = mhpme5 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1645 = mhpme5 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1648 = mhpme5 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1651 = mhpme5 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1654 = mhpme5 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1657 = mhpme5 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1660 = mhpme5 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1663 = mhpme5 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1666 = mhpme5 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1669 = mhpme5 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1674 = mhpme5 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1677 = mhpme5 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1680 = mhpme5 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1683 = mhpme5 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1687 = mhpme5 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] - wire _T_1689 = mhpme5 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1691 = mhpme5 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1693 = mhpme5 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1695 = mhpme5 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1697 = mhpme5 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1701 = mhpme5 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1705 = mhpme5 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1707 = mhpme5 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1709 = mhpme5 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1713 = mhpme5 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1715 = mhpme5 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] - wire _T_1717 = mhpme5 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] - wire _T_1719 = mhpme5 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] - wire _T_1721 = mhpme5 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] - wire _T_1723 = mhpme5 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] - wire _T_1725 = mhpme5 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] - wire _T_1727 = mhpme5 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] - wire _T_1732 = mhpme5 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] - wire _T_1742 = mhpme5 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] - wire _T_1745 = mhpme5 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] - wire _T_1748 = mhpme5 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] - wire _T_1751 = mhpme5 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] - wire _T_1753 = mhpme5 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] - wire _T_1755 = mhpme5 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] - wire _T_1757 = mhpme5 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] - wire _T_1759 = mhpme5 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] - wire _T_1762 = _T_1596 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_1763 = _T_1598 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_1764 = _T_1600 & _T_1035; // @[Mux.scala 27:72] - wire _T_1765 = _T_1604 & _T_1041; // @[Mux.scala 27:72] - wire _T_1766 = _T_1610 & _T_1046; // @[Mux.scala 27:72] - wire _T_1767 = _T_1615 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_1768 = _T_1617 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_1769 = _T_1619 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_1770 = _T_1621 & _T_1055; // @[Mux.scala 27:72] - wire _T_1771 = _T_1624 & _T_1058; // @[Mux.scala 27:72] - wire _T_1772 = _T_1627 & _T_1061; // @[Mux.scala 27:72] - wire _T_1773 = _T_1630 & _T_1064; // @[Mux.scala 27:72] - wire _T_1774 = _T_1633 & _T_1068; // @[Mux.scala 27:72] - wire _T_1775 = _T_1637 & _T_1073; // @[Mux.scala 27:72] - wire _T_1776 = _T_1642 & _T_1076; // @[Mux.scala 27:72] - wire _T_1777 = _T_1645 & _T_1079; // @[Mux.scala 27:72] - wire _T_1778 = _T_1648 & _T_1082; // @[Mux.scala 27:72] - wire _T_1779 = _T_1651 & _T_1085; // @[Mux.scala 27:72] - wire _T_1780 = _T_1654 & _T_1088; // @[Mux.scala 27:72] - wire _T_1781 = _T_1657 & _T_1091; // @[Mux.scala 27:72] - wire _T_1782 = _T_1660 & _T_1094; // @[Mux.scala 27:72] - wire _T_1783 = _T_1663 & _T_1097; // @[Mux.scala 27:72] - wire _T_1784 = _T_1666 & _T_1100; // @[Mux.scala 27:72] - wire _T_1785 = _T_1669 & _T_1105; // @[Mux.scala 27:72] - wire _T_1786 = _T_1674 & _T_1108; // @[Mux.scala 27:72] - wire _T_1787 = _T_1677 & _T_1111; // @[Mux.scala 27:72] - wire _T_1788 = _T_1680 & _T_1114; // @[Mux.scala 27:72] - wire _T_1789 = _T_1683 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_1791 = _T_1687 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_1792 = _T_1689 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_1793 = _T_1691 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_1794 = _T_1693 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_1795 = _T_1695 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_1796 = _T_1697 & _T_1132; // @[Mux.scala 27:72] - wire _T_1797 = _T_1701 & _T_1136; // @[Mux.scala 27:72] - wire _T_1798 = _T_1705 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_1799 = _T_1707 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_1800 = _T_1709 & _T_1144; // @[Mux.scala 27:72] - wire _T_1801 = _T_1713 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1802 = _T_1715 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1803 = _T_1717 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_1804 = _T_1719 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1805 = _T_1721 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1806 = _T_1723 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1807 = _T_1725 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1808 = _T_1727 & _T_1163; // @[Mux.scala 27:72] - wire _T_1809 = _T_1732 & _T_1173; // @[Mux.scala 27:72] - wire _T_1810 = _T_1742 & _T_1176; // @[Mux.scala 27:72] - wire _T_1811 = _T_1745 & _T_1179; // @[Mux.scala 27:72] - wire _T_1812 = _T_1748 & _T_1182; // @[Mux.scala 27:72] - wire _T_1813 = _T_1751 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_1814 = _T_1753 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_1815 = _T_1755 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_1816 = _T_1757 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_1817 = _T_1759 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_1818 = _T_1594 | _T_1762; // @[Mux.scala 27:72] + wire _T_1586 = mhpme5 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1588 = mhpme5 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1590 = mhpme5 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1592 = mhpme5 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1596 = mhpme5 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1602 = mhpme5 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1607 = mhpme5 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1609 = mhpme5 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1611 = mhpme5 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1613 = mhpme5 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1616 = mhpme5 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1619 = mhpme5 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1622 = mhpme5 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1625 = mhpme5 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1629 = mhpme5 == 10'he; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1634 = mhpme5 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1637 = mhpme5 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1640 = mhpme5 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1643 = mhpme5 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1646 = mhpme5 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1649 = mhpme5 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1652 = mhpme5 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1655 = mhpme5 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1658 = mhpme5 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1661 = mhpme5 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1666 = mhpme5 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1669 = mhpme5 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1672 = mhpme5 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1675 = mhpme5 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1679 = mhpme5 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] + wire _T_1681 = mhpme5 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1683 = mhpme5 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1685 = mhpme5 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1687 = mhpme5 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1689 = mhpme5 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1693 = mhpme5 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1697 = mhpme5 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1699 = mhpme5 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1701 = mhpme5 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1705 = mhpme5 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] + wire _T_1707 = mhpme5 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] + wire _T_1709 = mhpme5 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] + wire _T_1711 = mhpme5 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] + wire _T_1713 = mhpme5 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] + wire _T_1715 = mhpme5 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] + wire _T_1717 = mhpme5 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] + wire _T_1719 = mhpme5 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] + wire _T_1724 = mhpme5 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] + wire _T_1734 = mhpme5 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] + wire _T_1737 = mhpme5 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] + wire _T_1740 = mhpme5 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] + wire _T_1743 = mhpme5 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] + wire _T_1745 = mhpme5 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] + wire _T_1747 = mhpme5 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] + wire _T_1749 = mhpme5 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] + wire _T_1751 = mhpme5 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] + wire _T_1754 = _T_1588 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1755 = _T_1590 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1756 = _T_1592 & _T_1027; // @[Mux.scala 27:72] + wire _T_1757 = _T_1596 & _T_1033; // @[Mux.scala 27:72] + wire _T_1758 = _T_1602 & _T_1038; // @[Mux.scala 27:72] + wire _T_1759 = _T_1607 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1760 = _T_1609 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1761 = _T_1611 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1762 = _T_1613 & _T_1047; // @[Mux.scala 27:72] + wire _T_1763 = _T_1616 & _T_1050; // @[Mux.scala 27:72] + wire _T_1764 = _T_1619 & _T_1053; // @[Mux.scala 27:72] + wire _T_1765 = _T_1622 & _T_1056; // @[Mux.scala 27:72] + wire _T_1766 = _T_1625 & _T_1060; // @[Mux.scala 27:72] + wire _T_1767 = _T_1629 & _T_1065; // @[Mux.scala 27:72] + wire _T_1768 = _T_1634 & _T_1068; // @[Mux.scala 27:72] + wire _T_1769 = _T_1637 & _T_1071; // @[Mux.scala 27:72] + wire _T_1770 = _T_1640 & _T_1074; // @[Mux.scala 27:72] + wire _T_1771 = _T_1643 & _T_1077; // @[Mux.scala 27:72] + wire _T_1772 = _T_1646 & _T_1080; // @[Mux.scala 27:72] + wire _T_1773 = _T_1649 & _T_1083; // @[Mux.scala 27:72] + wire _T_1774 = _T_1652 & _T_1086; // @[Mux.scala 27:72] + wire _T_1775 = _T_1655 & _T_1089; // @[Mux.scala 27:72] + wire _T_1776 = _T_1658 & _T_1092; // @[Mux.scala 27:72] + wire _T_1777 = _T_1661 & _T_1097; // @[Mux.scala 27:72] + wire _T_1778 = _T_1666 & _T_1100; // @[Mux.scala 27:72] + wire _T_1779 = _T_1669 & _T_1103; // @[Mux.scala 27:72] + wire _T_1780 = _T_1672 & _T_1106; // @[Mux.scala 27:72] + wire _T_1781 = _T_1675 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1783 = _T_1679 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1784 = _T_1681 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1785 = _T_1683 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1786 = _T_1685 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1787 = _T_1687 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1788 = _T_1689 & _T_1124; // @[Mux.scala 27:72] + wire _T_1789 = _T_1693 & _T_1128; // @[Mux.scala 27:72] + wire _T_1790 = _T_1697 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1791 = _T_1699 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1792 = _T_1701 & _T_1136; // @[Mux.scala 27:72] + wire _T_1793 = _T_1705 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1794 = _T_1707 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1795 = _T_1709 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1796 = _T_1711 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1797 = _T_1713 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1798 = _T_1715 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1799 = _T_1717 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1800 = _T_1719 & _T_1155; // @[Mux.scala 27:72] + wire _T_1801 = _T_1724 & _T_1165; // @[Mux.scala 27:72] + wire _T_1802 = _T_1734 & _T_1168; // @[Mux.scala 27:72] + wire _T_1803 = _T_1737 & _T_1171; // @[Mux.scala 27:72] + wire _T_1804 = _T_1740 & _T_1174; // @[Mux.scala 27:72] + wire _T_1805 = _T_1743 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1806 = _T_1745 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1807 = _T_1747 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1808 = _T_1749 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1809 = _T_1751 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1810 = _T_1586 | _T_1754; // @[Mux.scala 27:72] + wire _T_1811 = _T_1810 | _T_1755; // @[Mux.scala 27:72] + wire _T_1812 = _T_1811 | _T_1756; // @[Mux.scala 27:72] + wire _T_1813 = _T_1812 | _T_1757; // @[Mux.scala 27:72] + wire _T_1814 = _T_1813 | _T_1758; // @[Mux.scala 27:72] + wire _T_1815 = _T_1814 | _T_1759; // @[Mux.scala 27:72] + wire _T_1816 = _T_1815 | _T_1760; // @[Mux.scala 27:72] + wire _T_1817 = _T_1816 | _T_1761; // @[Mux.scala 27:72] + wire _T_1818 = _T_1817 | _T_1762; // @[Mux.scala 27:72] wire _T_1819 = _T_1818 | _T_1763; // @[Mux.scala 27:72] wire _T_1820 = _T_1819 | _T_1764; // @[Mux.scala 27:72] wire _T_1821 = _T_1820 | _T_1765; // @[Mux.scala 27:72] @@ -51917,7 +51921,7 @@ module csr_tlu( wire _T_1835 = _T_1834 | _T_1779; // @[Mux.scala 27:72] wire _T_1836 = _T_1835 | _T_1780; // @[Mux.scala 27:72] wire _T_1837 = _T_1836 | _T_1781; // @[Mux.scala 27:72] - wire _T_1838 = _T_1837 | _T_1782; // @[Mux.scala 27:72] + wire _T_1838 = _T_1837 | _T_1761; // @[Mux.scala 27:72] wire _T_1839 = _T_1838 | _T_1783; // @[Mux.scala 27:72] wire _T_1840 = _T_1839 | _T_1784; // @[Mux.scala 27:72] wire _T_1841 = _T_1840 | _T_1785; // @[Mux.scala 27:72] @@ -51925,7 +51929,7 @@ module csr_tlu( wire _T_1843 = _T_1842 | _T_1787; // @[Mux.scala 27:72] wire _T_1844 = _T_1843 | _T_1788; // @[Mux.scala 27:72] wire _T_1845 = _T_1844 | _T_1789; // @[Mux.scala 27:72] - wire _T_1846 = _T_1845 | _T_1769; // @[Mux.scala 27:72] + wire _T_1846 = _T_1845 | _T_1790; // @[Mux.scala 27:72] wire _T_1847 = _T_1846 | _T_1791; // @[Mux.scala 27:72] wire _T_1848 = _T_1847 | _T_1792; // @[Mux.scala 27:72] wire _T_1849 = _T_1848 | _T_1793; // @[Mux.scala 27:72] @@ -51945,129 +51949,129 @@ module csr_tlu( wire _T_1863 = _T_1862 | _T_1807; // @[Mux.scala 27:72] wire _T_1864 = _T_1863 | _T_1808; // @[Mux.scala 27:72] wire _T_1865 = _T_1864 | _T_1809; // @[Mux.scala 27:72] - wire _T_1866 = _T_1865 | _T_1810; // @[Mux.scala 27:72] - wire _T_1867 = _T_1866 | _T_1811; // @[Mux.scala 27:72] - wire _T_1868 = _T_1867 | _T_1812; // @[Mux.scala 27:72] - wire _T_1869 = _T_1868 | _T_1813; // @[Mux.scala 27:72] - wire _T_1870 = _T_1869 | _T_1814; // @[Mux.scala 27:72] - wire _T_1871 = _T_1870 | _T_1815; // @[Mux.scala 27:72] - wire _T_1872 = _T_1871 | _T_1816; // @[Mux.scala 27:72] - wire _T_1873 = _T_1872 | _T_1817; // @[Mux.scala 27:72] - wire mhpmc_inc_r_2 = _T_1593 & _T_1873; // @[dec_tlu_ctl.scala 2273:44] - wire _T_1877 = ~mcountinhibit[6]; // @[dec_tlu_ctl.scala 2273:24] + wire mhpmc_inc_r_2 = _T_1585 & _T_1865; // @[dec_tlu_ctl.scala 2273:44] + wire _T_1869 = ~mcountinhibit[6]; // @[dec_tlu_ctl.scala 2273:24] reg [9:0] mhpme6; // @[Reg.scala 27:20] - wire _T_1878 = mhpme6 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1880 = mhpme6 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1882 = mhpme6 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1884 = mhpme6 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1888 = mhpme6 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1894 = mhpme6 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1899 = mhpme6 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1901 = mhpme6 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1903 = mhpme6 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1905 = mhpme6 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1908 = mhpme6 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1911 = mhpme6 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1914 = mhpme6 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1917 = mhpme6 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1921 = mhpme6 == 10'he; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1926 = mhpme6 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1929 = mhpme6 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1932 = mhpme6 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1935 = mhpme6 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1938 = mhpme6 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1941 = mhpme6 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1944 = mhpme6 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1947 = mhpme6 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1950 = mhpme6 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1953 = mhpme6 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1958 = mhpme6 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1961 = mhpme6 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1964 = mhpme6 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1967 = mhpme6 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1971 = mhpme6 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] - wire _T_1973 = mhpme6 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1975 = mhpme6 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1977 = mhpme6 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1979 = mhpme6 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1981 = mhpme6 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1985 = mhpme6 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1989 = mhpme6 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1991 = mhpme6 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1993 = mhpme6 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1997 = mhpme6 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1999 = mhpme6 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] - wire _T_2001 = mhpme6 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] - wire _T_2003 = mhpme6 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] - wire _T_2005 = mhpme6 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] - wire _T_2007 = mhpme6 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] - wire _T_2009 = mhpme6 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] - wire _T_2011 = mhpme6 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] - wire _T_2016 = mhpme6 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] - wire _T_2026 = mhpme6 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] - wire _T_2029 = mhpme6 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] - wire _T_2032 = mhpme6 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] - wire _T_2035 = mhpme6 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] - wire _T_2037 = mhpme6 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] - wire _T_2039 = mhpme6 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] - wire _T_2041 = mhpme6 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] - wire _T_2043 = mhpme6 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] - wire _T_2046 = _T_1880 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_2047 = _T_1882 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_2048 = _T_1884 & _T_1035; // @[Mux.scala 27:72] - wire _T_2049 = _T_1888 & _T_1041; // @[Mux.scala 27:72] - wire _T_2050 = _T_1894 & _T_1046; // @[Mux.scala 27:72] - wire _T_2051 = _T_1899 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_2052 = _T_1901 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_2053 = _T_1903 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_2054 = _T_1905 & _T_1055; // @[Mux.scala 27:72] - wire _T_2055 = _T_1908 & _T_1058; // @[Mux.scala 27:72] - wire _T_2056 = _T_1911 & _T_1061; // @[Mux.scala 27:72] - wire _T_2057 = _T_1914 & _T_1064; // @[Mux.scala 27:72] - wire _T_2058 = _T_1917 & _T_1068; // @[Mux.scala 27:72] - wire _T_2059 = _T_1921 & _T_1073; // @[Mux.scala 27:72] - wire _T_2060 = _T_1926 & _T_1076; // @[Mux.scala 27:72] - wire _T_2061 = _T_1929 & _T_1079; // @[Mux.scala 27:72] - wire _T_2062 = _T_1932 & _T_1082; // @[Mux.scala 27:72] - wire _T_2063 = _T_1935 & _T_1085; // @[Mux.scala 27:72] - wire _T_2064 = _T_1938 & _T_1088; // @[Mux.scala 27:72] - wire _T_2065 = _T_1941 & _T_1091; // @[Mux.scala 27:72] - wire _T_2066 = _T_1944 & _T_1094; // @[Mux.scala 27:72] - wire _T_2067 = _T_1947 & _T_1097; // @[Mux.scala 27:72] - wire _T_2068 = _T_1950 & _T_1100; // @[Mux.scala 27:72] - wire _T_2069 = _T_1953 & _T_1105; // @[Mux.scala 27:72] - wire _T_2070 = _T_1958 & _T_1108; // @[Mux.scala 27:72] - wire _T_2071 = _T_1961 & _T_1111; // @[Mux.scala 27:72] - wire _T_2072 = _T_1964 & _T_1114; // @[Mux.scala 27:72] - wire _T_2073 = _T_1967 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_2075 = _T_1971 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_2076 = _T_1973 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_2077 = _T_1975 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_2078 = _T_1977 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_2079 = _T_1979 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_2080 = _T_1981 & _T_1132; // @[Mux.scala 27:72] - wire _T_2081 = _T_1985 & _T_1136; // @[Mux.scala 27:72] - wire _T_2082 = _T_1989 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_2083 = _T_1991 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_2084 = _T_1993 & _T_1144; // @[Mux.scala 27:72] - wire _T_2085 = _T_1997 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_2086 = _T_1999 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_2087 = _T_2001 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_2088 = _T_2003 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_2089 = _T_2005 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_2090 = _T_2007 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_2091 = _T_2009 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_2092 = _T_2011 & _T_1163; // @[Mux.scala 27:72] - wire _T_2093 = _T_2016 & _T_1173; // @[Mux.scala 27:72] - wire _T_2094 = _T_2026 & _T_1176; // @[Mux.scala 27:72] - wire _T_2095 = _T_2029 & _T_1179; // @[Mux.scala 27:72] - wire _T_2096 = _T_2032 & _T_1182; // @[Mux.scala 27:72] - wire _T_2097 = _T_2035 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_2098 = _T_2037 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_2099 = _T_2039 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_2100 = _T_2041 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_2101 = _T_2043 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_2102 = _T_1878 | _T_2046; // @[Mux.scala 27:72] + wire _T_1870 = mhpme6 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1872 = mhpme6 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1874 = mhpme6 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1876 = mhpme6 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1880 = mhpme6 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1886 = mhpme6 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1891 = mhpme6 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1893 = mhpme6 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1895 = mhpme6 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1897 = mhpme6 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1900 = mhpme6 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1903 = mhpme6 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1906 = mhpme6 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1909 = mhpme6 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1913 = mhpme6 == 10'he; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1918 = mhpme6 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1921 = mhpme6 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1924 = mhpme6 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1927 = mhpme6 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1930 = mhpme6 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1933 = mhpme6 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1936 = mhpme6 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1939 = mhpme6 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1942 = mhpme6 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1945 = mhpme6 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1950 = mhpme6 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1953 = mhpme6 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1956 = mhpme6 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1959 = mhpme6 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1963 = mhpme6 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] + wire _T_1965 = mhpme6 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1967 = mhpme6 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1969 = mhpme6 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1971 = mhpme6 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1973 = mhpme6 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1977 = mhpme6 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1981 = mhpme6 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1983 = mhpme6 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1985 = mhpme6 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1989 = mhpme6 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] + wire _T_1991 = mhpme6 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] + wire _T_1993 = mhpme6 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] + wire _T_1995 = mhpme6 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] + wire _T_1997 = mhpme6 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] + wire _T_1999 = mhpme6 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] + wire _T_2001 = mhpme6 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] + wire _T_2003 = mhpme6 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] + wire _T_2008 = mhpme6 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] + wire _T_2018 = mhpme6 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] + wire _T_2021 = mhpme6 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] + wire _T_2024 = mhpme6 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] + wire _T_2027 = mhpme6 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] + wire _T_2029 = mhpme6 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] + wire _T_2031 = mhpme6 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] + wire _T_2033 = mhpme6 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] + wire _T_2035 = mhpme6 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] + wire _T_2038 = _T_1872 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_2039 = _T_1874 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_2040 = _T_1876 & _T_1027; // @[Mux.scala 27:72] + wire _T_2041 = _T_1880 & _T_1033; // @[Mux.scala 27:72] + wire _T_2042 = _T_1886 & _T_1038; // @[Mux.scala 27:72] + wire _T_2043 = _T_1891 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_2044 = _T_1893 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_2045 = _T_1895 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_2046 = _T_1897 & _T_1047; // @[Mux.scala 27:72] + wire _T_2047 = _T_1900 & _T_1050; // @[Mux.scala 27:72] + wire _T_2048 = _T_1903 & _T_1053; // @[Mux.scala 27:72] + wire _T_2049 = _T_1906 & _T_1056; // @[Mux.scala 27:72] + wire _T_2050 = _T_1909 & _T_1060; // @[Mux.scala 27:72] + wire _T_2051 = _T_1913 & _T_1065; // @[Mux.scala 27:72] + wire _T_2052 = _T_1918 & _T_1068; // @[Mux.scala 27:72] + wire _T_2053 = _T_1921 & _T_1071; // @[Mux.scala 27:72] + wire _T_2054 = _T_1924 & _T_1074; // @[Mux.scala 27:72] + wire _T_2055 = _T_1927 & _T_1077; // @[Mux.scala 27:72] + wire _T_2056 = _T_1930 & _T_1080; // @[Mux.scala 27:72] + wire _T_2057 = _T_1933 & _T_1083; // @[Mux.scala 27:72] + wire _T_2058 = _T_1936 & _T_1086; // @[Mux.scala 27:72] + wire _T_2059 = _T_1939 & _T_1089; // @[Mux.scala 27:72] + wire _T_2060 = _T_1942 & _T_1092; // @[Mux.scala 27:72] + wire _T_2061 = _T_1945 & _T_1097; // @[Mux.scala 27:72] + wire _T_2062 = _T_1950 & _T_1100; // @[Mux.scala 27:72] + wire _T_2063 = _T_1953 & _T_1103; // @[Mux.scala 27:72] + wire _T_2064 = _T_1956 & _T_1106; // @[Mux.scala 27:72] + wire _T_2065 = _T_1959 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_2067 = _T_1963 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_2068 = _T_1965 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_2069 = _T_1967 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_2070 = _T_1969 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_2071 = _T_1971 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_2072 = _T_1973 & _T_1124; // @[Mux.scala 27:72] + wire _T_2073 = _T_1977 & _T_1128; // @[Mux.scala 27:72] + wire _T_2074 = _T_1981 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_2075 = _T_1983 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_2076 = _T_1985 & _T_1136; // @[Mux.scala 27:72] + wire _T_2077 = _T_1989 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_2078 = _T_1991 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_2079 = _T_1993 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_2080 = _T_1995 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_2081 = _T_1997 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_2082 = _T_1999 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_2083 = _T_2001 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_2084 = _T_2003 & _T_1155; // @[Mux.scala 27:72] + wire _T_2085 = _T_2008 & _T_1165; // @[Mux.scala 27:72] + wire _T_2086 = _T_2018 & _T_1168; // @[Mux.scala 27:72] + wire _T_2087 = _T_2021 & _T_1171; // @[Mux.scala 27:72] + wire _T_2088 = _T_2024 & _T_1174; // @[Mux.scala 27:72] + wire _T_2089 = _T_2027 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_2090 = _T_2029 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_2091 = _T_2031 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_2092 = _T_2033 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_2093 = _T_2035 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_2094 = _T_1870 | _T_2038; // @[Mux.scala 27:72] + wire _T_2095 = _T_2094 | _T_2039; // @[Mux.scala 27:72] + wire _T_2096 = _T_2095 | _T_2040; // @[Mux.scala 27:72] + wire _T_2097 = _T_2096 | _T_2041; // @[Mux.scala 27:72] + wire _T_2098 = _T_2097 | _T_2042; // @[Mux.scala 27:72] + wire _T_2099 = _T_2098 | _T_2043; // @[Mux.scala 27:72] + wire _T_2100 = _T_2099 | _T_2044; // @[Mux.scala 27:72] + wire _T_2101 = _T_2100 | _T_2045; // @[Mux.scala 27:72] + wire _T_2102 = _T_2101 | _T_2046; // @[Mux.scala 27:72] wire _T_2103 = _T_2102 | _T_2047; // @[Mux.scala 27:72] wire _T_2104 = _T_2103 | _T_2048; // @[Mux.scala 27:72] wire _T_2105 = _T_2104 | _T_2049; // @[Mux.scala 27:72] @@ -52087,7 +52091,7 @@ module csr_tlu( wire _T_2119 = _T_2118 | _T_2063; // @[Mux.scala 27:72] wire _T_2120 = _T_2119 | _T_2064; // @[Mux.scala 27:72] wire _T_2121 = _T_2120 | _T_2065; // @[Mux.scala 27:72] - wire _T_2122 = _T_2121 | _T_2066; // @[Mux.scala 27:72] + wire _T_2122 = _T_2121 | _T_2045; // @[Mux.scala 27:72] wire _T_2123 = _T_2122 | _T_2067; // @[Mux.scala 27:72] wire _T_2124 = _T_2123 | _T_2068; // @[Mux.scala 27:72] wire _T_2125 = _T_2124 | _T_2069; // @[Mux.scala 27:72] @@ -52095,7 +52099,7 @@ module csr_tlu( wire _T_2127 = _T_2126 | _T_2071; // @[Mux.scala 27:72] wire _T_2128 = _T_2127 | _T_2072; // @[Mux.scala 27:72] wire _T_2129 = _T_2128 | _T_2073; // @[Mux.scala 27:72] - wire _T_2130 = _T_2129 | _T_2053; // @[Mux.scala 27:72] + wire _T_2130 = _T_2129 | _T_2074; // @[Mux.scala 27:72] wire _T_2131 = _T_2130 | _T_2075; // @[Mux.scala 27:72] wire _T_2132 = _T_2131 | _T_2076; // @[Mux.scala 27:72] wire _T_2133 = _T_2132 | _T_2077; // @[Mux.scala 27:72] @@ -52115,194 +52119,194 @@ module csr_tlu( wire _T_2147 = _T_2146 | _T_2091; // @[Mux.scala 27:72] wire _T_2148 = _T_2147 | _T_2092; // @[Mux.scala 27:72] wire _T_2149 = _T_2148 | _T_2093; // @[Mux.scala 27:72] - wire _T_2150 = _T_2149 | _T_2094; // @[Mux.scala 27:72] - wire _T_2151 = _T_2150 | _T_2095; // @[Mux.scala 27:72] - wire _T_2152 = _T_2151 | _T_2096; // @[Mux.scala 27:72] - wire _T_2153 = _T_2152 | _T_2097; // @[Mux.scala 27:72] - wire _T_2154 = _T_2153 | _T_2098; // @[Mux.scala 27:72] - wire _T_2155 = _T_2154 | _T_2099; // @[Mux.scala 27:72] - wire _T_2156 = _T_2155 | _T_2100; // @[Mux.scala 27:72] - wire _T_2157 = _T_2156 | _T_2101; // @[Mux.scala 27:72] - wire mhpmc_inc_r_3 = _T_1877 & _T_2157; // @[dec_tlu_ctl.scala 2273:44] + wire mhpmc_inc_r_3 = _T_1869 & _T_2149; // @[dec_tlu_ctl.scala 2273:44] reg mhpmc_inc_r_d1_0; // @[dec_tlu_ctl.scala 2334:53] reg mhpmc_inc_r_d1_1; // @[dec_tlu_ctl.scala 2335:53] reg mhpmc_inc_r_d1_2; // @[dec_tlu_ctl.scala 2336:53] reg mhpmc_inc_r_d1_3; // @[dec_tlu_ctl.scala 2337:53] reg perfcnt_halted_d1; // @[dec_tlu_ctl.scala 2338:56] wire perfcnt_halted = _T_85 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2341:67] - wire _T_2169 = ~_T_85; // @[dec_tlu_ctl.scala 2342:37] - wire [3:0] _T_2171 = _T_2169 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_2178 = {mhpme6[9],mhpme5[9],mhpme4[9],mhpme3[9]}; // @[Cat.scala 29:58] - wire [3:0] perfcnt_during_sleep = _T_2171 & _T_2178; // @[dec_tlu_ctl.scala 2342:86] - wire _T_2180 = ~perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2344:67] - wire _T_2181 = perfcnt_halted_d1 & _T_2180; // @[dec_tlu_ctl.scala 2344:65] - wire _T_2182 = ~_T_2181; // @[dec_tlu_ctl.scala 2344:45] - wire _T_2185 = ~perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2345:67] - wire _T_2186 = perfcnt_halted_d1 & _T_2185; // @[dec_tlu_ctl.scala 2345:65] - wire _T_2187 = ~_T_2186; // @[dec_tlu_ctl.scala 2345:45] - wire _T_2190 = ~perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2346:67] - wire _T_2191 = perfcnt_halted_d1 & _T_2190; // @[dec_tlu_ctl.scala 2346:65] - wire _T_2192 = ~_T_2191; // @[dec_tlu_ctl.scala 2346:45] - wire _T_2195 = ~perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2347:67] - wire _T_2196 = perfcnt_halted_d1 & _T_2195; // @[dec_tlu_ctl.scala 2347:65] - wire _T_2197 = ~_T_2196; // @[dec_tlu_ctl.scala 2347:45] - wire _T_2200 = io_dec_csr_wraddr_r == 12'hb03; // @[dec_tlu_ctl.scala 2353:72] - wire mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_2200; // @[dec_tlu_ctl.scala 2353:43] - wire _T_2201 = ~perfcnt_halted; // @[dec_tlu_ctl.scala 2354:23] - wire _T_2203 = _T_2201 | perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2354:39] - wire _T_2204 = |mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 2354:86] - wire mhpmc3_wr_en1 = _T_2203 & _T_2204; // @[dec_tlu_ctl.scala 2354:66] - reg [31:0] mhpmc3h; // @[el2_lib.scala 514:16] - reg [31:0] mhpmc3; // @[el2_lib.scala 514:16] - wire [63:0] _T_2207 = {mhpmc3h,mhpmc3}; // @[Cat.scala 29:58] - wire [63:0] _T_2208 = {63'h0,mhpmc_inc_r_0}; // @[Cat.scala 29:58] - wire [63:0] mhpmc3_incr = _T_2207 + _T_2208; // @[dec_tlu_ctl.scala 2358:49] - wire _T_2216 = io_dec_csr_wraddr_r == 12'hb83; // @[dec_tlu_ctl.scala 2363:73] - wire mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_2216; // @[dec_tlu_ctl.scala 2363:44] - wire _T_2222 = io_dec_csr_wraddr_r == 12'hb04; // @[dec_tlu_ctl.scala 2372:72] - wire mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_2222; // @[dec_tlu_ctl.scala 2372:43] - wire _T_2225 = _T_2201 | perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2373:39] - wire _T_2226 = |mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 2373:86] - wire mhpmc4_wr_en1 = _T_2225 & _T_2226; // @[dec_tlu_ctl.scala 2373:66] - reg [31:0] mhpmc4h; // @[el2_lib.scala 514:16] - reg [31:0] mhpmc4; // @[el2_lib.scala 514:16] - wire [63:0] _T_2229 = {mhpmc4h,mhpmc4}; // @[Cat.scala 29:58] - wire [63:0] _T_2230 = {63'h0,mhpmc_inc_r_1}; // @[Cat.scala 29:58] - wire [63:0] mhpmc4_incr = _T_2229 + _T_2230; // @[dec_tlu_ctl.scala 2378:49] - wire _T_2239 = io_dec_csr_wraddr_r == 12'hb84; // @[dec_tlu_ctl.scala 2382:73] - wire mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_2239; // @[dec_tlu_ctl.scala 2382:44] - wire _T_2245 = io_dec_csr_wraddr_r == 12'hb05; // @[dec_tlu_ctl.scala 2391:72] - wire mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_2245; // @[dec_tlu_ctl.scala 2391:43] - wire _T_2248 = _T_2201 | perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2392:39] - wire _T_2249 = |mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 2392:86] - wire mhpmc5_wr_en1 = _T_2248 & _T_2249; // @[dec_tlu_ctl.scala 2392:66] - reg [31:0] mhpmc5h; // @[el2_lib.scala 514:16] - reg [31:0] mhpmc5; // @[el2_lib.scala 514:16] - wire [63:0] _T_2252 = {mhpmc5h,mhpmc5}; // @[Cat.scala 29:58] - wire [63:0] _T_2253 = {63'h0,mhpmc_inc_r_2}; // @[Cat.scala 29:58] - wire [63:0] mhpmc5_incr = _T_2252 + _T_2253; // @[dec_tlu_ctl.scala 2395:49] - wire _T_2261 = io_dec_csr_wraddr_r == 12'hb85; // @[dec_tlu_ctl.scala 2400:73] - wire mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_2261; // @[dec_tlu_ctl.scala 2400:44] - wire _T_2267 = io_dec_csr_wraddr_r == 12'hb06; // @[dec_tlu_ctl.scala 2409:72] - wire mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_2267; // @[dec_tlu_ctl.scala 2409:43] - wire _T_2270 = _T_2201 | perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2410:39] - wire _T_2271 = |mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 2410:86] - wire mhpmc6_wr_en1 = _T_2270 & _T_2271; // @[dec_tlu_ctl.scala 2410:66] - reg [31:0] mhpmc6h; // @[el2_lib.scala 514:16] - reg [31:0] mhpmc6; // @[el2_lib.scala 514:16] - wire [63:0] _T_2274 = {mhpmc6h,mhpmc6}; // @[Cat.scala 29:58] - wire [63:0] _T_2275 = {63'h0,mhpmc_inc_r_3}; // @[Cat.scala 29:58] - wire [63:0] mhpmc6_incr = _T_2274 + _T_2275; // @[dec_tlu_ctl.scala 2413:49] - wire _T_2283 = io_dec_csr_wraddr_r == 12'hb86; // @[dec_tlu_ctl.scala 2418:73] - wire mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_2283; // @[dec_tlu_ctl.scala 2418:44] - wire _T_2289 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[dec_tlu_ctl.scala 2429:56] - wire _T_2291 = |io_dec_csr_wrdata_r[31:10]; // @[dec_tlu_ctl.scala 2429:102] - wire _T_2292 = _T_2289 | _T_2291; // @[dec_tlu_ctl.scala 2429:71] - wire _T_2295 = io_dec_csr_wraddr_r == 12'h323; // @[dec_tlu_ctl.scala 2431:70] - wire wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_2295; // @[dec_tlu_ctl.scala 2431:41] - wire _T_2299 = io_dec_csr_wraddr_r == 12'h324; // @[dec_tlu_ctl.scala 2438:70] - wire wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_2299; // @[dec_tlu_ctl.scala 2438:41] - wire _T_2303 = io_dec_csr_wraddr_r == 12'h325; // @[dec_tlu_ctl.scala 2445:70] - wire wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_2303; // @[dec_tlu_ctl.scala 2445:41] - wire _T_2307 = io_dec_csr_wraddr_r == 12'h326; // @[dec_tlu_ctl.scala 2452:70] - wire wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_2307; // @[dec_tlu_ctl.scala 2452:41] - wire _T_2311 = io_dec_csr_wraddr_r == 12'h320; // @[dec_tlu_ctl.scala 2469:77] - wire wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_2311; // @[dec_tlu_ctl.scala 2469:48] - wire _T_2323 = io_i0_valid_wb | io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 2484:51] - wire _T_2324 = _T_2323 | io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 2484:78] - wire _T_2325 = _T_2324 | io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 2484:104] - wire _T_2326 = _T_2325 | io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 2484:130] - wire _T_2327 = _T_2326 | io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 2485:32] - reg _T_2330; // @[dec_tlu_ctl.scala 2487:62] - wire _T_2331 = io_i0_exception_valid_r_d1 | io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 2488:91] - wire _T_2332 = ~io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 2488:137] - wire _T_2333 = io_trigger_hit_r_d1 & _T_2332; // @[dec_tlu_ctl.scala 2488:135] - reg _T_2335; // @[dec_tlu_ctl.scala 2488:62] - reg [4:0] _T_2336; // @[dec_tlu_ctl.scala 2489:62] - reg _T_2337; // @[dec_tlu_ctl.scala 2490:62] - wire [31:0] _T_2343 = {io_core_id,4'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2352 = {21'h3,3'h0,io_mstatus[1],3'h0,io_mstatus[0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2357 = {io_mtvec[30:1],1'h0,io_mtvec[0]}; // @[Cat.scala 29:58] - wire [31:0] _T_2370 = {1'h0,io_mip[5:3],16'h0,io_mip[2],3'h0,io_mip[1],3'h0,io_mip[0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2383 = {1'h0,mie[5:3],16'h0,mie[2],3'h0,mie[1],3'h0,mie[0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2395 = {io_mepc,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2400 = {28'h0,mscause}; // @[Cat.scala 29:58] - wire [31:0] _T_2408 = {meivt,10'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2411 = {meivt,meihap,2'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2414 = {28'h0,meicurpl}; // @[Cat.scala 29:58] - wire [31:0] _T_2417 = {28'h0,meicidpl}; // @[Cat.scala 29:58] - wire [31:0] _T_2420 = {28'h0,meipt}; // @[Cat.scala 29:58] - wire [31:0] _T_2423 = {23'h0,mcgc}; // @[Cat.scala 29:58] - wire [31:0] _T_2426 = {13'h0,_T_350,4'h0,mfdc_int[11:7],_T_353,mfdc_int[5:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_2430 = {16'h4000,io_dcsr[15:2],2'h3}; // @[Cat.scala 29:58] - wire [31:0] _T_2432 = {io_dpc,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2448 = {7'h0,dicawics[16],2'h0,dicawics[15:14],3'h0,dicawics[13:0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2451 = {30'h0,mtsel}; // @[Cat.scala 29:58] - wire [31:0] _T_2480 = {26'h0,mfdht}; // @[Cat.scala 29:58] - wire [31:0] _T_2483 = {30'h0,mfdhs}; // @[Cat.scala 29:58] - wire [31:0] _T_2486 = {22'h0,mhpme3}; // @[Cat.scala 29:58] - wire [31:0] _T_2489 = {22'h0,mhpme4}; // @[Cat.scala 29:58] - wire [31:0] _T_2492 = {22'h0,mhpme5}; // @[Cat.scala 29:58] - wire [31:0] _T_2495 = {22'h0,mhpme6}; // @[Cat.scala 29:58] - wire [31:0] _T_2498 = {25'h0,temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] - wire [31:0] _T_2501 = {30'h0,mpmc,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2504 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2505 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2506 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2507 = io_csr_pkt_csr_mimpid ? 32'h2 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2508 = io_csr_pkt_csr_mhartid ? _T_2343 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2509 = io_csr_pkt_csr_mstatus ? _T_2352 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2510 = io_csr_pkt_csr_mtvec ? _T_2357 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2511 = io_csr_pkt_csr_mip ? _T_2370 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2512 = io_csr_pkt_csr_mie ? _T_2383 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2513 = io_csr_pkt_csr_mcyclel ? mcyclel : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2514 = io_csr_pkt_csr_mcycleh ? mcycleh_inc : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2515 = io_csr_pkt_csr_minstretl ? minstretl : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2516 = io_csr_pkt_csr_minstreth ? minstreth_inc : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2517 = io_csr_pkt_csr_mscratch ? mscratch : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2518 = io_csr_pkt_csr_mepc ? _T_2395 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2519 = io_csr_pkt_csr_mcause ? mcause : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2520 = io_csr_pkt_csr_mscause ? _T_2400 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2521 = io_csr_pkt_csr_mtval ? mtval : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2522 = io_csr_pkt_csr_mrac ? mrac : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2523 = io_csr_pkt_csr_mdseac ? mdseac : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2524 = io_csr_pkt_csr_meivt ? _T_2408 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2525 = io_csr_pkt_csr_meihap ? _T_2411 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2526 = io_csr_pkt_csr_meicurpl ? _T_2414 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2527 = io_csr_pkt_csr_meicidpl ? _T_2417 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2528 = io_csr_pkt_csr_meipt ? _T_2420 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2529 = io_csr_pkt_csr_mcgc ? _T_2423 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2530 = io_csr_pkt_csr_mfdc ? _T_2426 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2531 = io_csr_pkt_csr_dcsr ? _T_2430 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2532 = io_csr_pkt_csr_dpc ? _T_2432 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2533 = io_csr_pkt_csr_dicad0 ? dicad0[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2534 = io_csr_pkt_csr_dicad0h ? dicad0h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2535 = io_csr_pkt_csr_dicad1 ? dicad1 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2536 = io_csr_pkt_csr_dicawics ? _T_2448 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2537 = io_csr_pkt_csr_mtsel ? _T_2451 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2538 = io_csr_pkt_csr_mtdata1 ? mtdata1_tsel_out : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2539 = io_csr_pkt_csr_mtdata2 ? mtdata2_tsel_out : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2540 = io_csr_pkt_csr_micect ? micect : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2541 = io_csr_pkt_csr_miccmect ? miccmect : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2542 = io_csr_pkt_csr_mdccmect ? mdccmect : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2543 = io_csr_pkt_csr_mhpmc3 ? mhpmc3 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2544 = io_csr_pkt_csr_mhpmc4 ? mhpmc4 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2545 = io_csr_pkt_csr_mhpmc5 ? mhpmc5 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2546 = io_csr_pkt_csr_mhpmc6 ? mhpmc6 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2547 = io_csr_pkt_csr_mhpmc3h ? mhpmc3h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2548 = io_csr_pkt_csr_mhpmc4h ? mhpmc4h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2549 = io_csr_pkt_csr_mhpmc5h ? mhpmc5h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2550 = io_csr_pkt_csr_mhpmc6h ? mhpmc6h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2551 = io_csr_pkt_csr_mfdht ? _T_2480 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2552 = io_csr_pkt_csr_mfdhs ? _T_2483 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2553 = io_csr_pkt_csr_mhpme3 ? _T_2486 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2554 = io_csr_pkt_csr_mhpme4 ? _T_2489 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2555 = io_csr_pkt_csr_mhpme5 ? _T_2492 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2556 = io_csr_pkt_csr_mhpme6 ? _T_2495 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2557 = io_csr_pkt_csr_mcountinhibit ? _T_2498 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2558 = io_csr_pkt_csr_mpmc ? _T_2501 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2559 = io_dec_timer_read_d ? io_dec_timer_rddata_d : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2560 = _T_2504 | _T_2505; // @[Mux.scala 27:72] + wire _T_2161 = ~_T_85; // @[dec_tlu_ctl.scala 2342:37] + wire [3:0] _T_2163 = _T_2161 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_2170 = {mhpme6[9],mhpme5[9],mhpme4[9],mhpme3[9]}; // @[Cat.scala 29:58] + wire [3:0] perfcnt_during_sleep = _T_2163 & _T_2170; // @[dec_tlu_ctl.scala 2342:86] + wire _T_2172 = ~perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2344:67] + wire _T_2173 = perfcnt_halted_d1 & _T_2172; // @[dec_tlu_ctl.scala 2344:65] + wire _T_2174 = ~_T_2173; // @[dec_tlu_ctl.scala 2344:45] + wire _T_2177 = ~perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2345:67] + wire _T_2178 = perfcnt_halted_d1 & _T_2177; // @[dec_tlu_ctl.scala 2345:65] + wire _T_2179 = ~_T_2178; // @[dec_tlu_ctl.scala 2345:45] + wire _T_2182 = ~perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2346:67] + wire _T_2183 = perfcnt_halted_d1 & _T_2182; // @[dec_tlu_ctl.scala 2346:65] + wire _T_2184 = ~_T_2183; // @[dec_tlu_ctl.scala 2346:45] + wire _T_2187 = ~perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2347:67] + wire _T_2188 = perfcnt_halted_d1 & _T_2187; // @[dec_tlu_ctl.scala 2347:65] + wire _T_2189 = ~_T_2188; // @[dec_tlu_ctl.scala 2347:45] + wire _T_2192 = io_dec_csr_wraddr_r == 12'hb03; // @[dec_tlu_ctl.scala 2353:72] + wire mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_2192; // @[dec_tlu_ctl.scala 2353:43] + wire _T_2193 = ~perfcnt_halted; // @[dec_tlu_ctl.scala 2354:23] + wire _T_2195 = _T_2193 | perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2354:39] + wire _T_2196 = |mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 2354:86] + wire mhpmc3_wr_en1 = _T_2195 & _T_2196; // @[dec_tlu_ctl.scala 2354:66] + reg [31:0] mhpmc3h; // @[lib.scala 374:16] + reg [31:0] mhpmc3; // @[lib.scala 374:16] + wire [63:0] _T_2199 = {mhpmc3h,mhpmc3}; // @[Cat.scala 29:58] + wire [63:0] _T_2200 = {63'h0,mhpmc_inc_r_0}; // @[Cat.scala 29:58] + wire [63:0] mhpmc3_incr = _T_2199 + _T_2200; // @[dec_tlu_ctl.scala 2358:49] + wire _T_2208 = io_dec_csr_wraddr_r == 12'hb83; // @[dec_tlu_ctl.scala 2363:73] + wire mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_2208; // @[dec_tlu_ctl.scala 2363:44] + wire _T_2214 = io_dec_csr_wraddr_r == 12'hb04; // @[dec_tlu_ctl.scala 2372:72] + wire mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_2214; // @[dec_tlu_ctl.scala 2372:43] + wire _T_2217 = _T_2193 | perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2373:39] + wire _T_2218 = |mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 2373:86] + wire mhpmc4_wr_en1 = _T_2217 & _T_2218; // @[dec_tlu_ctl.scala 2373:66] + reg [31:0] mhpmc4h; // @[lib.scala 374:16] + reg [31:0] mhpmc4; // @[lib.scala 374:16] + wire [63:0] _T_2221 = {mhpmc4h,mhpmc4}; // @[Cat.scala 29:58] + wire [63:0] _T_2222 = {63'h0,mhpmc_inc_r_1}; // @[Cat.scala 29:58] + wire [63:0] mhpmc4_incr = _T_2221 + _T_2222; // @[dec_tlu_ctl.scala 2378:49] + wire _T_2231 = io_dec_csr_wraddr_r == 12'hb84; // @[dec_tlu_ctl.scala 2382:73] + wire mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_2231; // @[dec_tlu_ctl.scala 2382:44] + wire _T_2237 = io_dec_csr_wraddr_r == 12'hb05; // @[dec_tlu_ctl.scala 2391:72] + wire mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_2237; // @[dec_tlu_ctl.scala 2391:43] + wire _T_2240 = _T_2193 | perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2392:39] + wire _T_2241 = |mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 2392:86] + wire mhpmc5_wr_en1 = _T_2240 & _T_2241; // @[dec_tlu_ctl.scala 2392:66] + reg [31:0] mhpmc5h; // @[lib.scala 374:16] + reg [31:0] mhpmc5; // @[lib.scala 374:16] + wire [63:0] _T_2244 = {mhpmc5h,mhpmc5}; // @[Cat.scala 29:58] + wire [63:0] _T_2245 = {63'h0,mhpmc_inc_r_2}; // @[Cat.scala 29:58] + wire [63:0] mhpmc5_incr = _T_2244 + _T_2245; // @[dec_tlu_ctl.scala 2395:49] + wire _T_2253 = io_dec_csr_wraddr_r == 12'hb85; // @[dec_tlu_ctl.scala 2400:73] + wire mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_2253; // @[dec_tlu_ctl.scala 2400:44] + wire _T_2259 = io_dec_csr_wraddr_r == 12'hb06; // @[dec_tlu_ctl.scala 2409:72] + wire mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_2259; // @[dec_tlu_ctl.scala 2409:43] + wire _T_2262 = _T_2193 | perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2410:39] + wire _T_2263 = |mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 2410:86] + wire mhpmc6_wr_en1 = _T_2262 & _T_2263; // @[dec_tlu_ctl.scala 2410:66] + reg [31:0] mhpmc6h; // @[lib.scala 374:16] + reg [31:0] mhpmc6; // @[lib.scala 374:16] + wire [63:0] _T_2266 = {mhpmc6h,mhpmc6}; // @[Cat.scala 29:58] + wire [63:0] _T_2267 = {63'h0,mhpmc_inc_r_3}; // @[Cat.scala 29:58] + wire [63:0] mhpmc6_incr = _T_2266 + _T_2267; // @[dec_tlu_ctl.scala 2413:49] + wire _T_2275 = io_dec_csr_wraddr_r == 12'hb86; // @[dec_tlu_ctl.scala 2418:73] + wire mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_2275; // @[dec_tlu_ctl.scala 2418:44] + wire _T_2281 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[dec_tlu_ctl.scala 2429:56] + wire _T_2283 = |io_dec_csr_wrdata_r[31:10]; // @[dec_tlu_ctl.scala 2429:102] + wire _T_2284 = _T_2281 | _T_2283; // @[dec_tlu_ctl.scala 2429:71] + wire _T_2287 = io_dec_csr_wraddr_r == 12'h323; // @[dec_tlu_ctl.scala 2431:70] + wire wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_2287; // @[dec_tlu_ctl.scala 2431:41] + wire _T_2291 = io_dec_csr_wraddr_r == 12'h324; // @[dec_tlu_ctl.scala 2438:70] + wire wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_2291; // @[dec_tlu_ctl.scala 2438:41] + wire _T_2295 = io_dec_csr_wraddr_r == 12'h325; // @[dec_tlu_ctl.scala 2445:70] + wire wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_2295; // @[dec_tlu_ctl.scala 2445:41] + wire _T_2299 = io_dec_csr_wraddr_r == 12'h326; // @[dec_tlu_ctl.scala 2452:70] + wire wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_2299; // @[dec_tlu_ctl.scala 2452:41] + wire _T_2303 = io_dec_csr_wraddr_r == 12'h320; // @[dec_tlu_ctl.scala 2469:77] + wire wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_2303; // @[dec_tlu_ctl.scala 2469:48] + wire _T_2315 = io_i0_valid_wb | io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 2484:51] + wire _T_2316 = _T_2315 | io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 2484:78] + wire _T_2317 = _T_2316 | io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 2484:104] + wire _T_2318 = _T_2317 | io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 2484:130] + wire _T_2319 = _T_2318 | io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 2485:32] + reg _T_2322; // @[dec_tlu_ctl.scala 2487:62] + wire _T_2323 = io_i0_exception_valid_r_d1 | io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 2488:91] + wire _T_2324 = ~io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 2488:137] + wire _T_2325 = io_trigger_hit_r_d1 & _T_2324; // @[dec_tlu_ctl.scala 2488:135] + reg _T_2327; // @[dec_tlu_ctl.scala 2488:62] + reg [4:0] _T_2328; // @[dec_tlu_ctl.scala 2489:62] + reg _T_2329; // @[dec_tlu_ctl.scala 2490:62] + wire [31:0] _T_2335 = {io_core_id,4'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2344 = {21'h3,3'h0,io_mstatus[1],3'h0,io_mstatus[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2349 = {io_mtvec[30:1],1'h0,io_mtvec[0]}; // @[Cat.scala 29:58] + wire [31:0] _T_2362 = {1'h0,io_mip[5:3],16'h0,io_mip[2],3'h0,io_mip[1],3'h0,io_mip[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2375 = {1'h0,mie[5:3],16'h0,mie[2],3'h0,mie[1],3'h0,mie[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2387 = {io_mepc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2392 = {28'h0,mscause}; // @[Cat.scala 29:58] + wire [31:0] _T_2400 = {meivt,10'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2403 = {meivt,meihap,2'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2406 = {28'h0,meicurpl}; // @[Cat.scala 29:58] + wire [31:0] _T_2409 = {28'h0,meicidpl}; // @[Cat.scala 29:58] + wire [31:0] _T_2412 = {28'h0,meipt}; // @[Cat.scala 29:58] + wire [31:0] _T_2415 = {23'h0,mcgc}; // @[Cat.scala 29:58] + wire [31:0] _T_2418 = {13'h0,_T_345,4'h0,mfdc_int[11:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_2422 = {16'h4000,io_dcsr[15:2],2'h3}; // @[Cat.scala 29:58] + wire [31:0] _T_2424 = {io_dpc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2440 = {7'h0,dicawics[16],2'h0,dicawics[15:14],3'h0,dicawics[13:0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2443 = {30'h0,mtsel}; // @[Cat.scala 29:58] + wire [31:0] _T_2472 = {26'h0,mfdht}; // @[Cat.scala 29:58] + wire [31:0] _T_2475 = {30'h0,mfdhs}; // @[Cat.scala 29:58] + wire [31:0] _T_2478 = {22'h0,mhpme3}; // @[Cat.scala 29:58] + wire [31:0] _T_2481 = {22'h0,mhpme4}; // @[Cat.scala 29:58] + wire [31:0] _T_2484 = {22'h0,mhpme5}; // @[Cat.scala 29:58] + wire [31:0] _T_2487 = {22'h0,mhpme6}; // @[Cat.scala 29:58] + wire [31:0] _T_2490 = {25'h0,temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] + wire [31:0] _T_2493 = {30'h0,mpmc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2496 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2497 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2498 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2499 = io_csr_pkt_csr_mimpid ? 32'h2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2500 = io_csr_pkt_csr_mhartid ? _T_2335 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2501 = io_csr_pkt_csr_mstatus ? _T_2344 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2502 = io_csr_pkt_csr_mtvec ? _T_2349 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2503 = io_csr_pkt_csr_mip ? _T_2362 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2504 = io_csr_pkt_csr_mie ? _T_2375 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2505 = io_csr_pkt_csr_mcyclel ? mcyclel : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2506 = io_csr_pkt_csr_mcycleh ? mcycleh_inc : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2507 = io_csr_pkt_csr_minstretl ? minstretl : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2508 = io_csr_pkt_csr_minstreth ? minstreth_inc : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2509 = io_csr_pkt_csr_mscratch ? mscratch : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2510 = io_csr_pkt_csr_mepc ? _T_2387 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2511 = io_csr_pkt_csr_mcause ? mcause : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2512 = io_csr_pkt_csr_mscause ? _T_2392 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2513 = io_csr_pkt_csr_mtval ? mtval : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2514 = io_csr_pkt_csr_mrac ? mrac : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2515 = io_csr_pkt_csr_mdseac ? mdseac : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2516 = io_csr_pkt_csr_meivt ? _T_2400 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2517 = io_csr_pkt_csr_meihap ? _T_2403 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2518 = io_csr_pkt_csr_meicurpl ? _T_2406 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2519 = io_csr_pkt_csr_meicidpl ? _T_2409 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2520 = io_csr_pkt_csr_meipt ? _T_2412 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2521 = io_csr_pkt_csr_mcgc ? _T_2415 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2522 = io_csr_pkt_csr_mfdc ? _T_2418 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2523 = io_csr_pkt_csr_dcsr ? _T_2422 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2524 = io_csr_pkt_csr_dpc ? _T_2424 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2525 = io_csr_pkt_csr_dicad0 ? dicad0[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2526 = io_csr_pkt_csr_dicad0h ? dicad0h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2527 = io_csr_pkt_csr_dicad1 ? dicad1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2528 = io_csr_pkt_csr_dicawics ? _T_2440 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2529 = io_csr_pkt_csr_mtsel ? _T_2443 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2530 = io_csr_pkt_csr_mtdata1 ? mtdata1_tsel_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2531 = io_csr_pkt_csr_mtdata2 ? mtdata2_tsel_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2532 = io_csr_pkt_csr_micect ? micect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2533 = io_csr_pkt_csr_miccmect ? miccmect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2534 = io_csr_pkt_csr_mdccmect ? mdccmect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2535 = io_csr_pkt_csr_mhpmc3 ? mhpmc3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2536 = io_csr_pkt_csr_mhpmc4 ? mhpmc4 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2537 = io_csr_pkt_csr_mhpmc5 ? mhpmc5 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2538 = io_csr_pkt_csr_mhpmc6 ? mhpmc6 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2539 = io_csr_pkt_csr_mhpmc3h ? mhpmc3h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2540 = io_csr_pkt_csr_mhpmc4h ? mhpmc4h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2541 = io_csr_pkt_csr_mhpmc5h ? mhpmc5h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2542 = io_csr_pkt_csr_mhpmc6h ? mhpmc6h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2543 = io_csr_pkt_csr_mfdht ? _T_2472 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2544 = io_csr_pkt_csr_mfdhs ? _T_2475 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2545 = io_csr_pkt_csr_mhpme3 ? _T_2478 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2546 = io_csr_pkt_csr_mhpme4 ? _T_2481 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2547 = io_csr_pkt_csr_mhpme5 ? _T_2484 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2548 = io_csr_pkt_csr_mhpme6 ? _T_2487 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2549 = io_csr_pkt_csr_mcountinhibit ? _T_2490 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2550 = io_csr_pkt_csr_mpmc ? _T_2493 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2551 = io_dec_timer_read_d ? io_dec_timer_rddata_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2552 = _T_2496 | _T_2497; // @[Mux.scala 27:72] + wire [31:0] _T_2553 = _T_2552 | _T_2498; // @[Mux.scala 27:72] + wire [31:0] _T_2554 = _T_2553 | _T_2499; // @[Mux.scala 27:72] + wire [31:0] _T_2555 = _T_2554 | _T_2500; // @[Mux.scala 27:72] + wire [31:0] _T_2556 = _T_2555 | _T_2501; // @[Mux.scala 27:72] + wire [31:0] _T_2557 = _T_2556 | _T_2502; // @[Mux.scala 27:72] + wire [31:0] _T_2558 = _T_2557 | _T_2503; // @[Mux.scala 27:72] + wire [31:0] _T_2559 = _T_2558 | _T_2504; // @[Mux.scala 27:72] + wire [31:0] _T_2560 = _T_2559 | _T_2505; // @[Mux.scala 27:72] wire [31:0] _T_2561 = _T_2560 | _T_2506; // @[Mux.scala 27:72] wire [31:0] _T_2562 = _T_2561 | _T_2507; // @[Mux.scala 27:72] wire [31:0] _T_2563 = _T_2562 | _T_2508; // @[Mux.scala 27:72] @@ -52348,225 +52352,217 @@ module csr_tlu( wire [31:0] _T_2603 = _T_2602 | _T_2548; // @[Mux.scala 27:72] wire [31:0] _T_2604 = _T_2603 | _T_2549; // @[Mux.scala 27:72] wire [31:0] _T_2605 = _T_2604 | _T_2550; // @[Mux.scala 27:72] - wire [31:0] _T_2606 = _T_2605 | _T_2551; // @[Mux.scala 27:72] - wire [31:0] _T_2607 = _T_2606 | _T_2552; // @[Mux.scala 27:72] - wire [31:0] _T_2608 = _T_2607 | _T_2553; // @[Mux.scala 27:72] - wire [31:0] _T_2609 = _T_2608 | _T_2554; // @[Mux.scala 27:72] - wire [31:0] _T_2610 = _T_2609 | _T_2555; // @[Mux.scala 27:72] - wire [31:0] _T_2611 = _T_2610 | _T_2556; // @[Mux.scala 27:72] - wire [31:0] _T_2612 = _T_2611 | _T_2557; // @[Mux.scala 27:72] - wire [31:0] _T_2613 = _T_2612 | _T_2558; // @[Mux.scala 27:72] - rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en), .io_scan_mode(rvclkhdr_io_scan_mode) ); - rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_1 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_1_io_l1clk), .io_clk(rvclkhdr_1_io_clk), .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_2_io_l1clk), .io_clk(rvclkhdr_2_io_clk), .io_en(rvclkhdr_2_io_en), .io_scan_mode(rvclkhdr_2_io_scan_mode) ); - rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_3_io_l1clk), .io_clk(rvclkhdr_3_io_clk), .io_en(rvclkhdr_3_io_en), .io_scan_mode(rvclkhdr_3_io_scan_mode) ); - rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_4_io_l1clk), .io_clk(rvclkhdr_4_io_clk), .io_en(rvclkhdr_4_io_en), .io_scan_mode(rvclkhdr_4_io_scan_mode) ); - rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_5 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_5_io_l1clk), .io_clk(rvclkhdr_5_io_clk), .io_en(rvclkhdr_5_io_en), .io_scan_mode(rvclkhdr_5_io_scan_mode) ); - rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_6 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_6_io_l1clk), .io_clk(rvclkhdr_6_io_clk), .io_en(rvclkhdr_6_io_en), .io_scan_mode(rvclkhdr_6_io_scan_mode) ); - rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_7 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_7_io_l1clk), .io_clk(rvclkhdr_7_io_clk), .io_en(rvclkhdr_7_io_en), .io_scan_mode(rvclkhdr_7_io_scan_mode) ); - rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_8 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_8_io_l1clk), .io_clk(rvclkhdr_8_io_clk), .io_en(rvclkhdr_8_io_en), .io_scan_mode(rvclkhdr_8_io_scan_mode) ); - rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_9 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_9_io_l1clk), .io_clk(rvclkhdr_9_io_clk), .io_en(rvclkhdr_9_io_en), .io_scan_mode(rvclkhdr_9_io_scan_mode) ); - rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_10 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_10_io_l1clk), .io_clk(rvclkhdr_10_io_clk), .io_en(rvclkhdr_10_io_en), .io_scan_mode(rvclkhdr_10_io_scan_mode) ); - rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_11 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_11_io_l1clk), .io_clk(rvclkhdr_11_io_clk), .io_en(rvclkhdr_11_io_en), .io_scan_mode(rvclkhdr_11_io_scan_mode) ); - rvclkhdr rvclkhdr_12 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_12 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_12_io_l1clk), .io_clk(rvclkhdr_12_io_clk), .io_en(rvclkhdr_12_io_en), .io_scan_mode(rvclkhdr_12_io_scan_mode) ); - rvclkhdr rvclkhdr_13 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_13 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_13_io_l1clk), .io_clk(rvclkhdr_13_io_clk), .io_en(rvclkhdr_13_io_en), .io_scan_mode(rvclkhdr_13_io_scan_mode) ); - rvclkhdr rvclkhdr_14 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_14 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_14_io_l1clk), .io_clk(rvclkhdr_14_io_clk), .io_en(rvclkhdr_14_io_en), .io_scan_mode(rvclkhdr_14_io_scan_mode) ); - rvclkhdr rvclkhdr_15 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_15 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_15_io_l1clk), .io_clk(rvclkhdr_15_io_clk), .io_en(rvclkhdr_15_io_en), .io_scan_mode(rvclkhdr_15_io_scan_mode) ); - rvclkhdr rvclkhdr_16 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_16 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_16_io_l1clk), .io_clk(rvclkhdr_16_io_clk), .io_en(rvclkhdr_16_io_en), .io_scan_mode(rvclkhdr_16_io_scan_mode) ); - rvclkhdr rvclkhdr_17 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_17 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_17_io_l1clk), .io_clk(rvclkhdr_17_io_clk), .io_en(rvclkhdr_17_io_en), .io_scan_mode(rvclkhdr_17_io_scan_mode) ); - rvclkhdr rvclkhdr_18 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_18 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_18_io_l1clk), .io_clk(rvclkhdr_18_io_clk), .io_en(rvclkhdr_18_io_en), .io_scan_mode(rvclkhdr_18_io_scan_mode) ); - rvclkhdr rvclkhdr_19 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_19 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_19_io_l1clk), .io_clk(rvclkhdr_19_io_clk), .io_en(rvclkhdr_19_io_en), .io_scan_mode(rvclkhdr_19_io_scan_mode) ); - rvclkhdr rvclkhdr_20 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_20 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_20_io_l1clk), .io_clk(rvclkhdr_20_io_clk), .io_en(rvclkhdr_20_io_en), .io_scan_mode(rvclkhdr_20_io_scan_mode) ); - rvclkhdr rvclkhdr_21 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_21 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_21_io_l1clk), .io_clk(rvclkhdr_21_io_clk), .io_en(rvclkhdr_21_io_en), .io_scan_mode(rvclkhdr_21_io_scan_mode) ); - rvclkhdr rvclkhdr_22 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_22 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_22_io_l1clk), .io_clk(rvclkhdr_22_io_clk), .io_en(rvclkhdr_22_io_en), .io_scan_mode(rvclkhdr_22_io_scan_mode) ); - rvclkhdr rvclkhdr_23 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_23 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_23_io_l1clk), .io_clk(rvclkhdr_23_io_clk), .io_en(rvclkhdr_23_io_en), .io_scan_mode(rvclkhdr_23_io_scan_mode) ); - rvclkhdr rvclkhdr_24 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_24 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_24_io_l1clk), .io_clk(rvclkhdr_24_io_clk), .io_en(rvclkhdr_24_io_en), .io_scan_mode(rvclkhdr_24_io_scan_mode) ); - rvclkhdr rvclkhdr_25 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_25 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_25_io_l1clk), .io_clk(rvclkhdr_25_io_clk), .io_en(rvclkhdr_25_io_en), .io_scan_mode(rvclkhdr_25_io_scan_mode) ); - rvclkhdr rvclkhdr_26 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_26 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_26_io_l1clk), .io_clk(rvclkhdr_26_io_clk), .io_en(rvclkhdr_26_io_en), .io_scan_mode(rvclkhdr_26_io_scan_mode) ); - rvclkhdr rvclkhdr_27 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_27 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_27_io_l1clk), .io_clk(rvclkhdr_27_io_clk), .io_en(rvclkhdr_27_io_en), .io_scan_mode(rvclkhdr_27_io_scan_mode) ); - rvclkhdr rvclkhdr_28 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_28 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_28_io_l1clk), .io_clk(rvclkhdr_28_io_clk), .io_en(rvclkhdr_28_io_en), .io_scan_mode(rvclkhdr_28_io_scan_mode) ); - rvclkhdr rvclkhdr_29 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_29 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_29_io_l1clk), .io_clk(rvclkhdr_29_io_clk), .io_en(rvclkhdr_29_io_en), .io_scan_mode(rvclkhdr_29_io_scan_mode) ); - rvclkhdr rvclkhdr_30 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_30 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_30_io_l1clk), .io_clk(rvclkhdr_30_io_clk), .io_en(rvclkhdr_30_io_en), .io_scan_mode(rvclkhdr_30_io_scan_mode) ); - rvclkhdr rvclkhdr_31 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_31 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_31_io_l1clk), .io_clk(rvclkhdr_31_io_clk), .io_en(rvclkhdr_31_io_en), .io_scan_mode(rvclkhdr_31_io_scan_mode) ); - rvclkhdr rvclkhdr_32 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_32 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_32_io_l1clk), .io_clk(rvclkhdr_32_io_clk), .io_en(rvclkhdr_32_io_en), .io_scan_mode(rvclkhdr_32_io_scan_mode) ); - rvclkhdr rvclkhdr_33 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_33 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_33_io_l1clk), .io_clk(rvclkhdr_33_io_clk), .io_en(rvclkhdr_33_io_en), .io_scan_mode(rvclkhdr_33_io_scan_mode) ); - rvclkhdr rvclkhdr_34 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_34 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_34_io_l1clk), .io_clk(rvclkhdr_34_io_clk), .io_en(rvclkhdr_34_io_en), .io_scan_mode(rvclkhdr_34_io_scan_mode) ); - assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {_T_763,dicad0[31:0]}; // @[dec_tlu_ctl.scala 2154:64] + assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {{1'd0}, _T_756}; // @[dec_tlu_ctl.scala 2155:47] assign io_dec_tlu_ic_diag_pkt_icache_dicawics = dicawics; // @[dec_tlu_ctl.scala 2157:41] assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = icache_rd_valid_f; // @[dec_tlu_ctl.scala 2165:41] assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = icache_wr_valid_f; // @[dec_tlu_ctl.scala 2166:41] @@ -52598,24 +52594,24 @@ module csr_tlu( assign io_trigger_pkt_any_3_execute = io_mtdata1_t_3[2]; // @[dec_tlu_ctl.scala 2234:40] assign io_trigger_pkt_any_3_m = io_mtdata1_t_3[3]; // @[dec_tlu_ctl.scala 2235:40] assign io_trigger_pkt_any_3_tdata2 = mtdata2_t_3; // @[dec_tlu_ctl.scala 2248:51] - assign io_dec_tlu_int_valid_wb1 = _T_2337; // @[dec_tlu_ctl.scala 2490:30] - assign io_dec_tlu_i0_exc_valid_wb1 = _T_2335; // @[dec_tlu_ctl.scala 2488:30] - assign io_dec_tlu_i0_valid_wb1 = _T_2330; // @[dec_tlu_ctl.scala 2487:30] + assign io_dec_tlu_int_valid_wb1 = _T_2329; // @[dec_tlu_ctl.scala 2490:30] + assign io_dec_tlu_i0_exc_valid_wb1 = _T_2327; // @[dec_tlu_ctl.scala 2488:30] + assign io_dec_tlu_i0_valid_wb1 = _T_2322; // @[dec_tlu_ctl.scala 2487:30] assign io_dec_tlu_mtval_wb1 = mtval; // @[dec_tlu_ctl.scala 2492:24] - assign io_dec_tlu_exc_cause_wb1 = _T_2336; // @[dec_tlu_ctl.scala 2489:30] - assign io_dec_tlu_perfcnt0 = mhpmc_inc_r_d1_0 & _T_2182; // @[dec_tlu_ctl.scala 2344:22] - assign io_dec_tlu_perfcnt1 = mhpmc_inc_r_d1_1 & _T_2187; // @[dec_tlu_ctl.scala 2345:22] - assign io_dec_tlu_perfcnt2 = mhpmc_inc_r_d1_2 & _T_2192; // @[dec_tlu_ctl.scala 2346:22] - assign io_dec_tlu_perfcnt3 = mhpmc_inc_r_d1_3 & _T_2197; // @[dec_tlu_ctl.scala 2347:22] + assign io_dec_tlu_exc_cause_wb1 = _T_2328; // @[dec_tlu_ctl.scala 2489:30] + assign io_dec_tlu_perfcnt0 = mhpmc_inc_r_d1_0 & _T_2174; // @[dec_tlu_ctl.scala 2344:22] + assign io_dec_tlu_perfcnt1 = mhpmc_inc_r_d1_1 & _T_2179; // @[dec_tlu_ctl.scala 2345:22] + assign io_dec_tlu_perfcnt2 = mhpmc_inc_r_d1_2 & _T_2184; // @[dec_tlu_ctl.scala 2346:22] + assign io_dec_tlu_perfcnt3 = mhpmc_inc_r_d1_3 & _T_2189; // @[dec_tlu_ctl.scala 2347:22] assign io_dec_tlu_misc_clk_override = mcgc[8]; // @[dec_tlu_ctl.scala 1717:31] assign io_dec_tlu_dec_clk_override = mcgc[7]; // @[dec_tlu_ctl.scala 1718:31] assign io_dec_tlu_lsu_clk_override = mcgc[4]; // @[dec_tlu_ctl.scala 1720:31] assign io_dec_tlu_pic_clk_override = mcgc[2]; // @[dec_tlu_ctl.scala 1722:31] assign io_dec_tlu_dccm_clk_override = mcgc[1]; // @[dec_tlu_ctl.scala 1723:31] assign io_dec_tlu_icm_clk_override = mcgc[0]; // @[dec_tlu_ctl.scala 1724:31] - assign io_dec_csr_rddata_d = _T_2613 | _T_2559; // @[dec_tlu_ctl.scala 2497:21] + assign io_dec_csr_rddata_d = _T_2605 | _T_2551; // @[dec_tlu_ctl.scala 2497:21] assign io_dec_tlu_pipelining_disable = mfdc[0]; // @[dec_tlu_ctl.scala 1767:39] - assign io_dec_tlu_wr_pause_r = _T_370 & _T_371; // @[dec_tlu_ctl.scala 1776:24] + assign io_dec_tlu_wr_pause_r = _T_360 & _T_361; // @[dec_tlu_ctl.scala 1776:24] assign io_dec_tlu_meipt = meipt; // @[dec_tlu_ctl.scala 2005:19] assign io_dec_tlu_meicurpl = meicurpl; // @[dec_tlu_ctl.scala 1969:22] assign io_dec_tlu_meihap = {meivt,meihap}; // @[dec_tlu_ctl.scala 1955:20] @@ -52627,128 +52623,128 @@ module csr_tlu( assign io_dec_tlu_external_ldfwd_disable = mfdc[11]; // @[dec_tlu_ctl.scala 1762:39] assign io_dec_tlu_dma_qos_prty = mfdc[18:16]; // @[dec_tlu_ctl.scala 1761:39] assign io_dec_csr_wen_r_mod = _T_1 & _T_2; // @[dec_tlu_ctl.scala 1450:23] - assign io_fw_halt_req = _T_502 & _T_503; // @[dec_tlu_ctl.scala 1841:17] + assign io_fw_halt_req = _T_492 & _T_493; // @[dec_tlu_ctl.scala 1841:17] assign io_mstatus = _T_56; // @[dec_tlu_ctl.scala 1466:13] assign io_mstatus_mie_ns = io_mstatus[0] & _T_54; // @[dec_tlu_ctl.scala 1465:20] - assign io_dcsr = _T_701; // @[dec_tlu_ctl.scala 2052:10] + assign io_dcsr = _T_691; // @[dec_tlu_ctl.scala 2052:10] assign io_mtvec = _T_62; // @[dec_tlu_ctl.scala 1478:11] assign io_mip = _T_68; // @[dec_tlu_ctl.scala 1493:9] assign io_mie_ns = wr_mie_r ? _T_78 : mie; // @[dec_tlu_ctl.scala 1507:12] assign io_npc_r = _T_161 | _T_159; // @[dec_tlu_ctl.scala 1601:11] assign io_npc_r_d1 = _T_167; // @[dec_tlu_ctl.scala 1607:14] assign io_mepc = _T_196; // @[dec_tlu_ctl.scala 1626:10] - assign io_mdseac_locked_ns = mdseac_en | _T_489; // @[dec_tlu_ctl.scala 1824:22] - assign io_force_halt = mfdht[0] & _T_609; // @[dec_tlu_ctl.scala 1932:16] - assign io_dpc = _T_726; // @[dec_tlu_ctl.scala 2069:9] - assign io_mtdata1_t_0 = _T_872; // @[dec_tlu_ctl.scala 2225:39] - assign io_mtdata1_t_1 = _T_873; // @[dec_tlu_ctl.scala 2225:39] - assign io_mtdata1_t_2 = _T_874; // @[dec_tlu_ctl.scala 2225:39] - assign io_mtdata1_t_3 = _T_875; // @[dec_tlu_ctl.scala 2225:39] - assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_io_en = io_dec_csr_wen_r_mod & _T_58; // @[el2_lib.scala 511:17] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_1_io_en = wr_mcyclel_r | mcyclel_cout_in; // @[el2_lib.scala 511:17] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_2_io_en = wr_mcycleh_r | mcyclel_cout_f; // @[el2_lib.scala 511:17] - assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_3_io_en = i0_valid_no_ebreak_ecall_r | wr_minstretl_r; // @[el2_lib.scala 511:17] - assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_4_io_en = minstret_enable_f | wr_minstreth_r; // @[el2_lib.scala 511:17] - assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_5_io_en = io_dec_csr_wen_r_mod & _T_139; // @[el2_lib.scala 511:17] - assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_6_io_en = _T_164 | io_reset_delayed; // @[el2_lib.scala 511:17] - assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_7_io_en = _T_142 & io_dec_tlu_i0_valid_r; // @[el2_lib.scala 511:17] - assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_8_io_en = io_dec_csr_wen_r_mod & _T_325; // @[el2_lib.scala 511:17] - assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_9_io_en = io_dec_csr_wen_r_mod & _T_337; // @[el2_lib.scala 511:17] - assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_10_io_en = io_dec_csr_wen_r_mod & _T_374; // @[el2_lib.scala 511:17] - assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_11_io_en = _T_493 & _T_494; // @[el2_lib.scala 511:17] - assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_12_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_12_io_en = wr_micect_r | io_ic_perr_r_d1; // @[el2_lib.scala 511:17] - assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_13_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_13_io_en = _T_549 | io_iccm_dma_sb_error; // @[el2_lib.scala 511:17] - assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_14_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_14_io_en = wr_mdccmect_r | io_lsu_single_ecc_error_r_d1; // @[el2_lib.scala 511:17] - assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_15_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_15_io_en = io_dec_csr_wen_r_mod & _T_612; // @[el2_lib.scala 511:17] - assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_16_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_16_io_en = _T_632 | io_take_ext_int_start; // @[el2_lib.scala 511:17] - assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_17_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_17_io_en = _T_698 | io_take_nmi; // @[el2_lib.scala 511:17] - assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_18_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_18_io_en = _T_723 | dpc_capture_npc; // @[el2_lib.scala 511:17] - assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_19_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_19_io_en = _T_663 & _T_733; // @[el2_lib.scala 511:17] - assign rvclkhdr_19_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_20_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_20_io_en = wr_dicad0_r | io_ifu_ic_debug_rd_data_valid; // @[el2_lib.scala 511:17] - assign rvclkhdr_20_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_21_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_21_io_en = wr_dicad0h_r | io_ifu_ic_debug_rd_data_valid; // @[el2_lib.scala 511:17] - assign rvclkhdr_21_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_22_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_22_io_en = _T_971 & _T_807; // @[el2_lib.scala 511:17] - assign rvclkhdr_22_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_23_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_23_io_en = _T_980 & _T_816; // @[el2_lib.scala 511:17] - assign rvclkhdr_23_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_24_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_24_io_en = _T_989 & _T_825; // @[el2_lib.scala 511:17] - assign rvclkhdr_24_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_25_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_25_io_en = _T_998 & _T_834; // @[el2_lib.scala 511:17] - assign rvclkhdr_25_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_26_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_26_io_en = mhpmc3_wr_en0 | mhpmc3_wr_en1; // @[el2_lib.scala 511:17] - assign rvclkhdr_26_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_27_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_27_io_en = mhpmc3h_wr_en0 | mhpmc3_wr_en1; // @[el2_lib.scala 511:17] - assign rvclkhdr_27_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_28_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_28_io_en = mhpmc4_wr_en0 | mhpmc4_wr_en1; // @[el2_lib.scala 511:17] - assign rvclkhdr_28_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_29_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_29_io_en = mhpmc4h_wr_en0 | mhpmc4_wr_en1; // @[el2_lib.scala 511:17] - assign rvclkhdr_29_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_30_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_30_io_en = mhpmc5_wr_en0 | mhpmc5_wr_en1; // @[el2_lib.scala 511:17] - assign rvclkhdr_30_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_31_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_31_io_en = mhpmc5h_wr_en0 | mhpmc5_wr_en1; // @[el2_lib.scala 511:17] - assign rvclkhdr_31_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_32_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_32_io_en = mhpmc6_wr_en0 | mhpmc6_wr_en1; // @[el2_lib.scala 511:17] - assign rvclkhdr_32_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_33_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_33_io_en = mhpmc6h_wr_en0 | mhpmc6_wr_en1; // @[el2_lib.scala 511:17] - assign rvclkhdr_33_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_34_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_34_io_en = _T_2327 | io_clk_override; // @[el2_lib.scala 485:16] - assign rvclkhdr_34_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign io_mdseac_locked_ns = mdseac_en | _T_479; // @[dec_tlu_ctl.scala 1824:22] + assign io_force_halt = mfdht[0] & _T_599; // @[dec_tlu_ctl.scala 1932:16] + assign io_dpc = _T_716; // @[dec_tlu_ctl.scala 2069:9] + assign io_mtdata1_t_0 = _T_864; // @[dec_tlu_ctl.scala 2225:39] + assign io_mtdata1_t_1 = _T_865; // @[dec_tlu_ctl.scala 2225:39] + assign io_mtdata1_t_2 = _T_866; // @[dec_tlu_ctl.scala 2225:39] + assign io_mtdata1_t_3 = _T_867; // @[dec_tlu_ctl.scala 2225:39] + assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_io_en = io_dec_csr_wen_r_mod & _T_58; // @[lib.scala 371:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_1_io_en = wr_mcyclel_r | mcyclel_cout_in; // @[lib.scala 371:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_2_io_en = wr_mcycleh_r | mcyclel_cout_f; // @[lib.scala 371:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_3_io_en = i0_valid_no_ebreak_ecall_r | wr_minstretl_r; // @[lib.scala 371:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_4_io_en = minstret_enable_f | wr_minstreth_r; // @[lib.scala 371:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_5_io_en = io_dec_csr_wen_r_mod & _T_139; // @[lib.scala 371:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_6_io_en = _T_164 | io_reset_delayed; // @[lib.scala 371:17] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_7_io_en = _T_142 & io_dec_tlu_i0_valid_r; // @[lib.scala 371:17] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_8_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_8_io_en = io_dec_csr_wen_r_mod & _T_325; // @[lib.scala 371:17] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_9_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_9_io_en = io_dec_csr_wen_r_mod & _T_337; // @[lib.scala 371:17] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_10_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_10_io_en = io_dec_csr_wen_r_mod & _T_364; // @[lib.scala 371:17] + assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_11_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_11_io_en = _T_483 & _T_484; // @[lib.scala 371:17] + assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_12_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_12_io_en = wr_micect_r | io_ic_perr_r_d1; // @[lib.scala 371:17] + assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_13_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_13_io_en = _T_539 | io_iccm_dma_sb_error; // @[lib.scala 371:17] + assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_14_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_14_io_en = wr_mdccmect_r | io_lsu_single_ecc_error_r_d1; // @[lib.scala 371:17] + assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_15_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_15_io_en = io_dec_csr_wen_r_mod & _T_602; // @[lib.scala 371:17] + assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_16_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_16_io_en = _T_622 | io_take_ext_int_start; // @[lib.scala 371:17] + assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_17_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_17_io_en = _T_688 | io_take_nmi; // @[lib.scala 371:17] + assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_18_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_18_io_en = _T_713 | dpc_capture_npc; // @[lib.scala 371:17] + assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_19_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_19_io_en = _T_653 & _T_723; // @[lib.scala 371:17] + assign rvclkhdr_19_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_20_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_20_io_en = wr_dicad0_r | io_ifu_ic_debug_rd_data_valid; // @[lib.scala 371:17] + assign rvclkhdr_20_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_21_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_21_io_en = wr_dicad0h_r | io_ifu_ic_debug_rd_data_valid; // @[lib.scala 371:17] + assign rvclkhdr_21_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_22_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_22_io_en = _T_963 & _T_799; // @[lib.scala 371:17] + assign rvclkhdr_22_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_23_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_23_io_en = _T_972 & _T_808; // @[lib.scala 371:17] + assign rvclkhdr_23_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_24_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_24_io_en = _T_981 & _T_817; // @[lib.scala 371:17] + assign rvclkhdr_24_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_25_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_25_io_en = _T_990 & _T_826; // @[lib.scala 371:17] + assign rvclkhdr_25_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_26_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_26_io_en = mhpmc3_wr_en0 | mhpmc3_wr_en1; // @[lib.scala 371:17] + assign rvclkhdr_26_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_27_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_27_io_en = mhpmc3h_wr_en0 | mhpmc3_wr_en1; // @[lib.scala 371:17] + assign rvclkhdr_27_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_28_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_28_io_en = mhpmc4_wr_en0 | mhpmc4_wr_en1; // @[lib.scala 371:17] + assign rvclkhdr_28_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_29_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_29_io_en = mhpmc4h_wr_en0 | mhpmc4_wr_en1; // @[lib.scala 371:17] + assign rvclkhdr_29_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_30_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_30_io_en = mhpmc5_wr_en0 | mhpmc5_wr_en1; // @[lib.scala 371:17] + assign rvclkhdr_30_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_31_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_31_io_en = mhpmc5h_wr_en0 | mhpmc5_wr_en1; // @[lib.scala 371:17] + assign rvclkhdr_31_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_32_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_32_io_en = mhpmc6_wr_en0 | mhpmc6_wr_en1; // @[lib.scala 371:17] + assign rvclkhdr_32_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_33_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_33_io_en = mhpmc6h_wr_en0 | mhpmc6_wr_en1; // @[lib.scala 371:17] + assign rvclkhdr_33_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_34_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_34_io_en = _T_2319 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_34_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -52857,9 +52853,9 @@ initial begin _RAND_35 = {1{`RANDOM}}; meipt = _RAND_35[3:0]; _RAND_36 = {1{`RANDOM}}; - _T_701 = _RAND_36[15:0]; + _T_691 = _RAND_36[15:0]; _RAND_37 = {1{`RANDOM}}; - _T_726 = _RAND_37[30:0]; + _T_716 = _RAND_37[30:0]; _RAND_38 = {1{`RANDOM}}; dicawics = _RAND_38[16:0]; _RAND_39 = {3{`RANDOM}}; @@ -52867,7 +52863,7 @@ initial begin _RAND_40 = {1{`RANDOM}}; dicad0h = _RAND_40[31:0]; _RAND_41 = {1{`RANDOM}}; - _T_758 = _RAND_41[31:0]; + _T_749 = _RAND_41[3:0]; _RAND_42 = {1{`RANDOM}}; icache_rd_valid_f = _RAND_42[0:0]; _RAND_43 = {1{`RANDOM}}; @@ -52875,13 +52871,13 @@ initial begin _RAND_44 = {1{`RANDOM}}; mtsel = _RAND_44[1:0]; _RAND_45 = {1{`RANDOM}}; - _T_872 = _RAND_45[9:0]; + _T_864 = _RAND_45[9:0]; _RAND_46 = {1{`RANDOM}}; - _T_873 = _RAND_46[9:0]; + _T_865 = _RAND_46[9:0]; _RAND_47 = {1{`RANDOM}}; - _T_874 = _RAND_47[9:0]; + _T_866 = _RAND_47[9:0]; _RAND_48 = {1{`RANDOM}}; - _T_875 = _RAND_48[9:0]; + _T_867 = _RAND_48[9:0]; _RAND_49 = {1{`RANDOM}}; mtdata2_t_0 = _RAND_49[31:0]; _RAND_50 = {1{`RANDOM}}; @@ -52925,13 +52921,13 @@ initial begin _RAND_69 = {1{`RANDOM}}; mhpmc6 = _RAND_69[31:0]; _RAND_70 = {1{`RANDOM}}; - _T_2330 = _RAND_70[0:0]; + _T_2322 = _RAND_70[0:0]; _RAND_71 = {1{`RANDOM}}; - _T_2335 = _RAND_71[0:0]; + _T_2327 = _RAND_71[0:0]; _RAND_72 = {1{`RANDOM}}; - _T_2336 = _RAND_72[4:0]; + _T_2328 = _RAND_72[4:0]; _RAND_73 = {1{`RANDOM}}; - _T_2337 = _RAND_73[0:0]; + _T_2329 = _RAND_73[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin mpmc_b = 1'h0; @@ -53042,10 +53038,10 @@ initial begin meipt = 4'h0; end if (reset) begin - _T_701 = 16'h0; + _T_691 = 16'h0; end if (reset) begin - _T_726 = 31'h0; + _T_716 = 31'h0; end if (reset) begin dicawics = 17'h0; @@ -53057,7 +53053,7 @@ initial begin dicad0h = 32'h0; end if (reset) begin - _T_758 = 32'h0; + _T_749 = 4'h0; end if (reset) begin icache_rd_valid_f = 1'h0; @@ -53069,16 +53065,16 @@ initial begin mtsel = 2'h0; end if (reset) begin - _T_872 = 10'h0; + _T_864 = 10'h0; end if (reset) begin - _T_873 = 10'h0; + _T_865 = 10'h0; end if (reset) begin - _T_874 = 10'h0; + _T_866 = 10'h0; end if (reset) begin - _T_875 = 10'h0; + _T_867 = 10'h0; end if (reset) begin mtdata2_t_0 = 32'h0; @@ -53144,16 +53140,16 @@ initial begin mhpmc6 = 32'h0; end if (reset) begin - _T_2330 = 1'h0; + _T_2322 = 1'h0; end if (reset) begin - _T_2335 = 1'h0; + _T_2327 = 1'h0; end if (reset) begin - _T_2336 = 5'h0; + _T_2328 = 5'h0; end if (reset) begin - _T_2337 = 1'h0; + _T_2329 = 1'h0; end `endif // RANDOMIZE end // initial @@ -53165,9 +53161,9 @@ end // initial if (reset) begin mpmc_b <= 1'h0; end else if (wr_mpmc_r) begin - mpmc_b <= _T_510; + mpmc_b <= _T_500; end else begin - mpmc_b <= _T_511; + mpmc_b <= _T_501; end end always @(posedge io_free_clk or posedge reset) begin @@ -53188,27 +53184,27 @@ end // initial if (reset) begin mdccmect <= 32'h0; end else if (wr_mdccmect_r) begin - mdccmect <= _T_525; + mdccmect <= _T_515; end else begin - mdccmect <= _T_569; + mdccmect <= _T_559; end end always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin if (reset) begin miccmect <= 32'h0; end else if (wr_miccmect_r) begin - miccmect <= _T_525; + miccmect <= _T_515; end else begin - miccmect <= _T_548; + miccmect <= _T_538; end end always @(posedge rvclkhdr_12_io_l1clk or posedge reset) begin if (reset) begin micect <= 32'h0; end else if (wr_micect_r) begin - micect <= _T_525; + micect <= _T_515; end else begin - micect <= _T_527; + micect <= _T_517; end end always @(posedge io_free_clk or posedge reset) begin @@ -53356,14 +53352,14 @@ end // initial if (reset) begin mfdc_int <= 15'h0; end else begin - mfdc_int <= {_T_347,_T_346}; + mfdc_int <= {_T_341,io_dec_csr_wrdata_r[11:0]}; end end always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin if (reset) begin mrac <= 32'h0; end else begin - mrac <= {_T_484,_T_469}; + mrac <= {_T_474,_T_459}; end end always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin @@ -53383,11 +53379,11 @@ end // initial always @(posedge io_active_clk or posedge reset) begin if (reset) begin mfdhs <= 2'h0; - end else if (_T_595) begin + end else if (_T_585) begin if (wr_mfdhs_r) begin mfdhs <= io_dec_csr_wrdata_r[1:0]; - end else if (_T_589) begin - mfdhs <= _T_593; + end else if (_T_579) begin + mfdhs <= _T_583; end end end @@ -53396,7 +53392,7 @@ end // initial force_halt_ctr_f <= 32'h0; end else if (mfdht[0]) begin if (io_debug_halt_req_f) begin - force_halt_ctr_f <= _T_600; + force_halt_ctr_f <= _T_590; end else if (io_dbg_tlu_halted_f) begin force_halt_ctr_f <= 32'h0; end @@ -53441,27 +53437,27 @@ end // initial end always @(posedge rvclkhdr_17_io_l1clk or posedge reset) begin if (reset) begin - _T_701 <= 16'h0; + _T_691 <= 16'h0; end else if (enter_debug_halt_req_le) begin - _T_701 <= _T_675; + _T_691 <= _T_665; end else if (wr_dcsr_r) begin - _T_701 <= _T_690; + _T_691 <= _T_680; end else begin - _T_701 <= _T_695; + _T_691 <= _T_685; end end always @(posedge rvclkhdr_18_io_l1clk or posedge reset) begin if (reset) begin - _T_726 <= 31'h0; + _T_716 <= 31'h0; end else begin - _T_726 <= _T_721 | _T_720; + _T_716 <= _T_711 | _T_710; end end always @(posedge rvclkhdr_19_io_l1clk or posedge reset) begin if (reset) begin dicawics <= 17'h0; end else begin - dicawics <= {_T_730,io_dec_csr_wrdata_r[16:3]}; + dicawics <= {_T_720,io_dec_csr_wrdata_r[16:3]}; end end always @(posedge rvclkhdr_20_io_l1clk or posedge reset) begin @@ -53484,12 +53480,12 @@ end // initial end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_758 <= 32'h0; - end else if (_T_756) begin - if (_T_752) begin - _T_758 <= io_dec_csr_wrdata_r; + _T_749 <= 4'h0; + end else if (_T_747) begin + if (_T_742) begin + _T_749 <= io_dec_csr_wrdata_r[3:0]; end else begin - _T_758 <= {{25'd0}, io_ifu_ic_debug_rd_data[70:64]}; + _T_749 <= io_ifu_ic_debug_rd_data[67:64]; end end end @@ -53497,14 +53493,14 @@ end // initial if (reset) begin icache_rd_valid_f <= 1'h0; end else begin - icache_rd_valid_f <= _T_768 & _T_770; + icache_rd_valid_f <= _T_760 & _T_762; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin icache_wr_valid_f <= 1'h0; end else begin - icache_wr_valid_f <= _T_663 & _T_773; + icache_wr_valid_f <= _T_653 & _T_765; end end always @(posedge io_csr_wr_clk or posedge reset) begin @@ -53516,38 +53512,38 @@ end // initial end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_872 <= 10'h0; + _T_864 <= 10'h0; end else if (wr_mtdata1_t_r_0) begin - _T_872 <= tdata_wrdata_r; + _T_864 <= tdata_wrdata_r; end else begin - _T_872 <= _T_843; + _T_864 <= _T_835; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_873 <= 10'h0; + _T_865 <= 10'h0; end else if (wr_mtdata1_t_r_1) begin - _T_873 <= tdata_wrdata_r; + _T_865 <= tdata_wrdata_r; end else begin - _T_873 <= _T_852; + _T_865 <= _T_844; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_874 <= 10'h0; + _T_866 <= 10'h0; end else if (wr_mtdata1_t_r_2) begin - _T_874 <= tdata_wrdata_r; + _T_866 <= tdata_wrdata_r; end else begin - _T_874 <= _T_861; + _T_866 <= _T_853; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_875 <= 10'h0; + _T_867 <= 10'h0; end else if (wr_mtdata1_t_r_3) begin - _T_875 <= tdata_wrdata_r; + _T_867 <= tdata_wrdata_r; end else begin - _T_875 <= _T_870; + _T_867 <= _T_862; end end always @(posedge rvclkhdr_22_io_l1clk or posedge reset) begin @@ -53582,7 +53578,7 @@ end // initial if (reset) begin mhpme3 <= 10'h0; end else if (wr_mhpme3_r) begin - if (_T_2292) begin + if (_T_2284) begin mhpme3 <= 10'h204; end else begin mhpme3 <= io_dec_csr_wrdata_r[9:0]; @@ -53593,7 +53589,7 @@ end // initial if (reset) begin mhpme4 <= 10'h0; end else if (wr_mhpme4_r) begin - if (_T_2292) begin + if (_T_2284) begin mhpme4 <= 10'h204; end else begin mhpme4 <= io_dec_csr_wrdata_r[9:0]; @@ -53604,7 +53600,7 @@ end // initial if (reset) begin mhpme5 <= 10'h0; end else if (wr_mhpme5_r) begin - if (_T_2292) begin + if (_T_2284) begin mhpme5 <= 10'h204; end else begin mhpme5 <= io_dec_csr_wrdata_r[9:0]; @@ -53615,7 +53611,7 @@ end // initial if (reset) begin mhpme6 <= 10'h0; end else if (wr_mhpme6_r) begin - if (_T_2292) begin + if (_T_2284) begin mhpme6 <= 10'h204; end else begin mhpme6 <= io_dec_csr_wrdata_r[9:0]; @@ -53626,28 +53622,28 @@ end // initial if (reset) begin mhpmc_inc_r_d1_0 <= 1'h0; end else begin - mhpmc_inc_r_d1_0 <= _T_1025 & _T_1305; + mhpmc_inc_r_d1_0 <= _T_1017 & _T_1297; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin mhpmc_inc_r_d1_1 <= 1'h0; end else begin - mhpmc_inc_r_d1_1 <= _T_1309 & _T_1589; + mhpmc_inc_r_d1_1 <= _T_1301 & _T_1581; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin mhpmc_inc_r_d1_2 <= 1'h0; end else begin - mhpmc_inc_r_d1_2 <= _T_1593 & _T_1873; + mhpmc_inc_r_d1_2 <= _T_1585 & _T_1865; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin mhpmc_inc_r_d1_3 <= 1'h0; end else begin - mhpmc_inc_r_d1_3 <= _T_1877 & _T_2157; + mhpmc_inc_r_d1_3 <= _T_1869 & _T_2149; end end always @(posedge io_free_clk or posedge reset) begin @@ -53731,30 +53727,30 @@ end // initial end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2330 <= 1'h0; + _T_2322 <= 1'h0; end else begin - _T_2330 <= io_i0_valid_wb; + _T_2322 <= io_i0_valid_wb; end end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2335 <= 1'h0; + _T_2327 <= 1'h0; end else begin - _T_2335 <= _T_2331 | _T_2333; + _T_2327 <= _T_2323 | _T_2325; end end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2336 <= 5'h0; + _T_2328 <= 5'h0; end else begin - _T_2336 <= io_exc_cause_wb; + _T_2328 <= io_exc_cause_wb; end end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2337 <= 1'h0; + _T_2329 <= 1'h0; end else begin - _T_2337 <= io_interrupt_valid_r_d1; + _T_2329 <= io_interrupt_valid_r_d1; end end endmodule @@ -54489,22 +54485,22 @@ module dec_tlu_ctl( wire int_timers_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 274:30] wire int_timers_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 274:30] wire int_timers_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 274:30] - wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_1_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_1_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_2_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_2_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_3_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_3_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_io_en; // @[lib.scala 343:22] + wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_en; // @[lib.scala 343:22] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_2_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_2_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_2_io_en; // @[lib.scala 343:22] + wire rvclkhdr_2_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_3_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_3_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_3_io_en; // @[lib.scala 343:22] + wire rvclkhdr_3_io_scan_mode; // @[lib.scala 343:22] wire csr_clock; // @[dec_tlu_ctl.scala 817:15] wire csr_reset; // @[dec_tlu_ctl.scala 817:15] wire csr_io_free_clk; // @[dec_tlu_ctl.scala 817:15] @@ -54848,8 +54844,8 @@ module dec_tlu_ctl( reg mpc_halt_state_f; // @[dec_tlu_ctl.scala 361:89] wire [2:0] _T_3 = {io_i_cpu_run_req,io_mpc_debug_halt_req,io_mpc_debug_run_req}; // @[Cat.scala 29:58] wire [3:0] _T_6 = {io_nmi_int,io_timer_int,io_soft_int,io_i_cpu_halt_req}; // @[Cat.scala 29:58] - reg [6:0] _T_8; // @[el2_lib.scala 177:81] - reg [6:0] syncro_ff; // @[el2_lib.scala 177:58] + reg [6:0] _T_8; // @[lib.scala 37:81] + reg [6:0] syncro_ff; // @[lib.scala 37:58] wire nmi_int_sync = syncro_ff[6]; // @[dec_tlu_ctl.scala 301:67] wire i_cpu_halt_req_sync = syncro_ff[3]; // @[dec_tlu_ctl.scala 304:59] wire i_cpu_run_req_sync = syncro_ff[2]; // @[dec_tlu_ctl.scala 305:59] @@ -55568,25 +55564,25 @@ module dec_tlu_ctl( .io_dec_timer_t0_pulse(int_timers_io_dec_timer_t0_pulse), .io_dec_timer_t1_pulse(int_timers_io_dec_timer_t1_pulse) ); - rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en), .io_scan_mode(rvclkhdr_io_scan_mode) ); - rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_1_io_l1clk), .io_clk(rvclkhdr_1_io_clk), .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_2 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_2_io_l1clk), .io_clk(rvclkhdr_2_io_clk), .io_en(rvclkhdr_2_io_en), .io_scan_mode(rvclkhdr_2_io_scan_mode) ); - rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_3 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_3_io_l1clk), .io_clk(rvclkhdr_3_io_clk), .io_en(rvclkhdr_3_io_en), @@ -56046,18 +56042,18 @@ module dec_tlu_ctl( assign int_timers_io_dec_pause_state = io_dec_pause_state; // @[dec_tlu_ctl.scala 287:49] assign int_timers_io_dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 288:49] assign int_timers_io_internal_dbg_halt_timers = debug_mode_status & _T_665; // @[dec_tlu_ctl.scala 289:47] - assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_io_en = dec_csr_wen_r_mod | io_dec_tlu_dec_clk_override; // @[el2_lib.scala 485:16] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_1_io_en = _T_11 | io_dec_tlu_dec_clk_override; // @[el2_lib.scala 485:16] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_2_io_en = e4e5_valid | io_dec_tlu_dec_clk_override; // @[el2_lib.scala 485:16] - assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_3_io_en = e4e5_valid | flush_clkvalid; // @[el2_lib.scala 485:16] - assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_io_en = dec_csr_wen_r_mod | io_dec_tlu_dec_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_1_io_en = _T_11 | io_dec_tlu_dec_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_2_io_en = e4e5_valid | io_dec_tlu_dec_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_3_io_en = e4e5_valid | flush_clkvalid; // @[lib.scala 345:16] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] assign csr_clock = clock; assign csr_reset = reset; assign csr_io_free_clk = io_free_clk; // @[dec_tlu_ctl.scala 818:44] @@ -57253,548 +57249,548 @@ module dec_trigger( wire [31:0] _T_146 = {io_dec_i0_pc_d,io_trigger_pkt_any_3_tdata2[0]}; // @[Cat.scala 29:58] wire [31:0] dec_i0_match_data_3 = _T_144 & _T_146; // @[dec_trigger.scala 14:127] wire _T_148 = io_trigger_pkt_any_0_execute & io_trigger_pkt_any_0_m; // @[dec_trigger.scala 15:83] - wire _T_151 = &io_trigger_pkt_any_0_tdata2; // @[el2_lib.scala 241:45] - wire _T_152 = ~_T_151; // @[el2_lib.scala 241:39] - wire _T_153 = io_trigger_pkt_any_0_match_pkt & _T_152; // @[el2_lib.scala 241:37] - wire _T_156 = io_trigger_pkt_any_0_tdata2[0] == dec_i0_match_data_0[0]; // @[el2_lib.scala 242:52] - wire _T_157 = _T_153 | _T_156; // @[el2_lib.scala 242:41] - wire _T_159 = &io_trigger_pkt_any_0_tdata2[0]; // @[el2_lib.scala 244:36] - wire _T_160 = _T_159 & _T_153; // @[el2_lib.scala 244:41] - wire _T_163 = io_trigger_pkt_any_0_tdata2[1] == dec_i0_match_data_0[1]; // @[el2_lib.scala 244:78] - wire _T_164 = _T_160 | _T_163; // @[el2_lib.scala 244:23] - wire _T_166 = &io_trigger_pkt_any_0_tdata2[1:0]; // @[el2_lib.scala 244:36] - wire _T_167 = _T_166 & _T_153; // @[el2_lib.scala 244:41] - wire _T_170 = io_trigger_pkt_any_0_tdata2[2] == dec_i0_match_data_0[2]; // @[el2_lib.scala 244:78] - wire _T_171 = _T_167 | _T_170; // @[el2_lib.scala 244:23] - wire _T_173 = &io_trigger_pkt_any_0_tdata2[2:0]; // @[el2_lib.scala 244:36] - wire _T_174 = _T_173 & _T_153; // @[el2_lib.scala 244:41] - wire _T_177 = io_trigger_pkt_any_0_tdata2[3] == dec_i0_match_data_0[3]; // @[el2_lib.scala 244:78] - wire _T_178 = _T_174 | _T_177; // @[el2_lib.scala 244:23] - wire _T_180 = &io_trigger_pkt_any_0_tdata2[3:0]; // @[el2_lib.scala 244:36] - wire _T_181 = _T_180 & _T_153; // @[el2_lib.scala 244:41] - wire _T_184 = io_trigger_pkt_any_0_tdata2[4] == dec_i0_match_data_0[4]; // @[el2_lib.scala 244:78] - wire _T_185 = _T_181 | _T_184; // @[el2_lib.scala 244:23] - wire _T_187 = &io_trigger_pkt_any_0_tdata2[4:0]; // @[el2_lib.scala 244:36] - wire _T_188 = _T_187 & _T_153; // @[el2_lib.scala 244:41] - wire _T_191 = io_trigger_pkt_any_0_tdata2[5] == dec_i0_match_data_0[5]; // @[el2_lib.scala 244:78] - wire _T_192 = _T_188 | _T_191; // @[el2_lib.scala 244:23] - wire _T_194 = &io_trigger_pkt_any_0_tdata2[5:0]; // @[el2_lib.scala 244:36] - wire _T_195 = _T_194 & _T_153; // @[el2_lib.scala 244:41] - wire _T_198 = io_trigger_pkt_any_0_tdata2[6] == dec_i0_match_data_0[6]; // @[el2_lib.scala 244:78] - wire _T_199 = _T_195 | _T_198; // @[el2_lib.scala 244:23] - wire _T_201 = &io_trigger_pkt_any_0_tdata2[6:0]; // @[el2_lib.scala 244:36] - wire _T_202 = _T_201 & _T_153; // @[el2_lib.scala 244:41] - wire _T_205 = io_trigger_pkt_any_0_tdata2[7] == dec_i0_match_data_0[7]; // @[el2_lib.scala 244:78] - wire _T_206 = _T_202 | _T_205; // @[el2_lib.scala 244:23] - wire _T_208 = &io_trigger_pkt_any_0_tdata2[7:0]; // @[el2_lib.scala 244:36] - wire _T_209 = _T_208 & _T_153; // @[el2_lib.scala 244:41] - wire _T_212 = io_trigger_pkt_any_0_tdata2[8] == dec_i0_match_data_0[8]; // @[el2_lib.scala 244:78] - wire _T_213 = _T_209 | _T_212; // @[el2_lib.scala 244:23] - wire _T_215 = &io_trigger_pkt_any_0_tdata2[8:0]; // @[el2_lib.scala 244:36] - wire _T_216 = _T_215 & _T_153; // @[el2_lib.scala 244:41] - wire _T_219 = io_trigger_pkt_any_0_tdata2[9] == dec_i0_match_data_0[9]; // @[el2_lib.scala 244:78] - wire _T_220 = _T_216 | _T_219; // @[el2_lib.scala 244:23] - wire _T_222 = &io_trigger_pkt_any_0_tdata2[9:0]; // @[el2_lib.scala 244:36] - wire _T_223 = _T_222 & _T_153; // @[el2_lib.scala 244:41] - wire _T_226 = io_trigger_pkt_any_0_tdata2[10] == dec_i0_match_data_0[10]; // @[el2_lib.scala 244:78] - wire _T_227 = _T_223 | _T_226; // @[el2_lib.scala 244:23] - wire _T_229 = &io_trigger_pkt_any_0_tdata2[10:0]; // @[el2_lib.scala 244:36] - wire _T_230 = _T_229 & _T_153; // @[el2_lib.scala 244:41] - wire _T_233 = io_trigger_pkt_any_0_tdata2[11] == dec_i0_match_data_0[11]; // @[el2_lib.scala 244:78] - wire _T_234 = _T_230 | _T_233; // @[el2_lib.scala 244:23] - wire _T_236 = &io_trigger_pkt_any_0_tdata2[11:0]; // @[el2_lib.scala 244:36] - wire _T_237 = _T_236 & _T_153; // @[el2_lib.scala 244:41] - wire _T_240 = io_trigger_pkt_any_0_tdata2[12] == dec_i0_match_data_0[12]; // @[el2_lib.scala 244:78] - wire _T_241 = _T_237 | _T_240; // @[el2_lib.scala 244:23] - wire _T_243 = &io_trigger_pkt_any_0_tdata2[12:0]; // @[el2_lib.scala 244:36] - wire _T_244 = _T_243 & _T_153; // @[el2_lib.scala 244:41] - wire _T_247 = io_trigger_pkt_any_0_tdata2[13] == dec_i0_match_data_0[13]; // @[el2_lib.scala 244:78] - wire _T_248 = _T_244 | _T_247; // @[el2_lib.scala 244:23] - wire _T_250 = &io_trigger_pkt_any_0_tdata2[13:0]; // @[el2_lib.scala 244:36] - wire _T_251 = _T_250 & _T_153; // @[el2_lib.scala 244:41] - wire _T_254 = io_trigger_pkt_any_0_tdata2[14] == dec_i0_match_data_0[14]; // @[el2_lib.scala 244:78] - wire _T_255 = _T_251 | _T_254; // @[el2_lib.scala 244:23] - wire _T_257 = &io_trigger_pkt_any_0_tdata2[14:0]; // @[el2_lib.scala 244:36] - wire _T_258 = _T_257 & _T_153; // @[el2_lib.scala 244:41] - wire _T_261 = io_trigger_pkt_any_0_tdata2[15] == dec_i0_match_data_0[15]; // @[el2_lib.scala 244:78] - wire _T_262 = _T_258 | _T_261; // @[el2_lib.scala 244:23] - wire _T_264 = &io_trigger_pkt_any_0_tdata2[15:0]; // @[el2_lib.scala 244:36] - wire _T_265 = _T_264 & _T_153; // @[el2_lib.scala 244:41] - wire _T_268 = io_trigger_pkt_any_0_tdata2[16] == dec_i0_match_data_0[16]; // @[el2_lib.scala 244:78] - wire _T_269 = _T_265 | _T_268; // @[el2_lib.scala 244:23] - wire _T_271 = &io_trigger_pkt_any_0_tdata2[16:0]; // @[el2_lib.scala 244:36] - wire _T_272 = _T_271 & _T_153; // @[el2_lib.scala 244:41] - wire _T_275 = io_trigger_pkt_any_0_tdata2[17] == dec_i0_match_data_0[17]; // @[el2_lib.scala 244:78] - wire _T_276 = _T_272 | _T_275; // @[el2_lib.scala 244:23] - wire _T_278 = &io_trigger_pkt_any_0_tdata2[17:0]; // @[el2_lib.scala 244:36] - wire _T_279 = _T_278 & _T_153; // @[el2_lib.scala 244:41] - wire _T_282 = io_trigger_pkt_any_0_tdata2[18] == dec_i0_match_data_0[18]; // @[el2_lib.scala 244:78] - wire _T_283 = _T_279 | _T_282; // @[el2_lib.scala 244:23] - wire _T_285 = &io_trigger_pkt_any_0_tdata2[18:0]; // @[el2_lib.scala 244:36] - wire _T_286 = _T_285 & _T_153; // @[el2_lib.scala 244:41] - wire _T_289 = io_trigger_pkt_any_0_tdata2[19] == dec_i0_match_data_0[19]; // @[el2_lib.scala 244:78] - wire _T_290 = _T_286 | _T_289; // @[el2_lib.scala 244:23] - wire _T_292 = &io_trigger_pkt_any_0_tdata2[19:0]; // @[el2_lib.scala 244:36] - wire _T_293 = _T_292 & _T_153; // @[el2_lib.scala 244:41] - wire _T_296 = io_trigger_pkt_any_0_tdata2[20] == dec_i0_match_data_0[20]; // @[el2_lib.scala 244:78] - wire _T_297 = _T_293 | _T_296; // @[el2_lib.scala 244:23] - wire _T_299 = &io_trigger_pkt_any_0_tdata2[20:0]; // @[el2_lib.scala 244:36] - wire _T_300 = _T_299 & _T_153; // @[el2_lib.scala 244:41] - wire _T_303 = io_trigger_pkt_any_0_tdata2[21] == dec_i0_match_data_0[21]; // @[el2_lib.scala 244:78] - wire _T_304 = _T_300 | _T_303; // @[el2_lib.scala 244:23] - wire _T_306 = &io_trigger_pkt_any_0_tdata2[21:0]; // @[el2_lib.scala 244:36] - wire _T_307 = _T_306 & _T_153; // @[el2_lib.scala 244:41] - wire _T_310 = io_trigger_pkt_any_0_tdata2[22] == dec_i0_match_data_0[22]; // @[el2_lib.scala 244:78] - wire _T_311 = _T_307 | _T_310; // @[el2_lib.scala 244:23] - wire _T_313 = &io_trigger_pkt_any_0_tdata2[22:0]; // @[el2_lib.scala 244:36] - wire _T_314 = _T_313 & _T_153; // @[el2_lib.scala 244:41] - wire _T_317 = io_trigger_pkt_any_0_tdata2[23] == dec_i0_match_data_0[23]; // @[el2_lib.scala 244:78] - wire _T_318 = _T_314 | _T_317; // @[el2_lib.scala 244:23] - wire _T_320 = &io_trigger_pkt_any_0_tdata2[23:0]; // @[el2_lib.scala 244:36] - wire _T_321 = _T_320 & _T_153; // @[el2_lib.scala 244:41] - wire _T_324 = io_trigger_pkt_any_0_tdata2[24] == dec_i0_match_data_0[24]; // @[el2_lib.scala 244:78] - wire _T_325 = _T_321 | _T_324; // @[el2_lib.scala 244:23] - wire _T_327 = &io_trigger_pkt_any_0_tdata2[24:0]; // @[el2_lib.scala 244:36] - wire _T_328 = _T_327 & _T_153; // @[el2_lib.scala 244:41] - wire _T_331 = io_trigger_pkt_any_0_tdata2[25] == dec_i0_match_data_0[25]; // @[el2_lib.scala 244:78] - wire _T_332 = _T_328 | _T_331; // @[el2_lib.scala 244:23] - wire _T_334 = &io_trigger_pkt_any_0_tdata2[25:0]; // @[el2_lib.scala 244:36] - wire _T_335 = _T_334 & _T_153; // @[el2_lib.scala 244:41] - wire _T_338 = io_trigger_pkt_any_0_tdata2[26] == dec_i0_match_data_0[26]; // @[el2_lib.scala 244:78] - wire _T_339 = _T_335 | _T_338; // @[el2_lib.scala 244:23] - wire _T_341 = &io_trigger_pkt_any_0_tdata2[26:0]; // @[el2_lib.scala 244:36] - wire _T_342 = _T_341 & _T_153; // @[el2_lib.scala 244:41] - wire _T_345 = io_trigger_pkt_any_0_tdata2[27] == dec_i0_match_data_0[27]; // @[el2_lib.scala 244:78] - wire _T_346 = _T_342 | _T_345; // @[el2_lib.scala 244:23] - wire _T_348 = &io_trigger_pkt_any_0_tdata2[27:0]; // @[el2_lib.scala 244:36] - wire _T_349 = _T_348 & _T_153; // @[el2_lib.scala 244:41] - wire _T_352 = io_trigger_pkt_any_0_tdata2[28] == dec_i0_match_data_0[28]; // @[el2_lib.scala 244:78] - wire _T_353 = _T_349 | _T_352; // @[el2_lib.scala 244:23] - wire _T_355 = &io_trigger_pkt_any_0_tdata2[28:0]; // @[el2_lib.scala 244:36] - wire _T_356 = _T_355 & _T_153; // @[el2_lib.scala 244:41] - wire _T_359 = io_trigger_pkt_any_0_tdata2[29] == dec_i0_match_data_0[29]; // @[el2_lib.scala 244:78] - wire _T_360 = _T_356 | _T_359; // @[el2_lib.scala 244:23] - wire _T_362 = &io_trigger_pkt_any_0_tdata2[29:0]; // @[el2_lib.scala 244:36] - wire _T_363 = _T_362 & _T_153; // @[el2_lib.scala 244:41] - wire _T_366 = io_trigger_pkt_any_0_tdata2[30] == dec_i0_match_data_0[30]; // @[el2_lib.scala 244:78] - wire _T_367 = _T_363 | _T_366; // @[el2_lib.scala 244:23] - wire _T_369 = &io_trigger_pkt_any_0_tdata2[30:0]; // @[el2_lib.scala 244:36] - wire _T_370 = _T_369 & _T_153; // @[el2_lib.scala 244:41] - wire _T_373 = io_trigger_pkt_any_0_tdata2[31] == dec_i0_match_data_0[31]; // @[el2_lib.scala 244:78] - wire _T_374 = _T_370 | _T_373; // @[el2_lib.scala 244:23] - wire [7:0] _T_381 = {_T_206,_T_199,_T_192,_T_185,_T_178,_T_171,_T_164,_T_157}; // @[el2_lib.scala 245:14] - wire [15:0] _T_389 = {_T_262,_T_255,_T_248,_T_241,_T_234,_T_227,_T_220,_T_213,_T_381}; // @[el2_lib.scala 245:14] - wire [7:0] _T_396 = {_T_318,_T_311,_T_304,_T_297,_T_290,_T_283,_T_276,_T_269}; // @[el2_lib.scala 245:14] - wire [31:0] _T_405 = {_T_374,_T_367,_T_360,_T_353,_T_346,_T_339,_T_332,_T_325,_T_396,_T_389}; // @[el2_lib.scala 245:14] - wire _T_406 = &_T_405; // @[el2_lib.scala 245:25] + wire _T_151 = &io_trigger_pkt_any_0_tdata2; // @[lib.scala 101:45] + wire _T_152 = ~_T_151; // @[lib.scala 101:39] + wire _T_153 = io_trigger_pkt_any_0_match_pkt & _T_152; // @[lib.scala 101:37] + wire _T_156 = io_trigger_pkt_any_0_tdata2[0] == dec_i0_match_data_0[0]; // @[lib.scala 102:52] + wire _T_157 = _T_153 | _T_156; // @[lib.scala 102:41] + wire _T_159 = &io_trigger_pkt_any_0_tdata2[0]; // @[lib.scala 104:36] + wire _T_160 = _T_159 & _T_153; // @[lib.scala 104:41] + wire _T_163 = io_trigger_pkt_any_0_tdata2[1] == dec_i0_match_data_0[1]; // @[lib.scala 104:78] + wire _T_164 = _T_160 | _T_163; // @[lib.scala 104:23] + wire _T_166 = &io_trigger_pkt_any_0_tdata2[1:0]; // @[lib.scala 104:36] + wire _T_167 = _T_166 & _T_153; // @[lib.scala 104:41] + wire _T_170 = io_trigger_pkt_any_0_tdata2[2] == dec_i0_match_data_0[2]; // @[lib.scala 104:78] + wire _T_171 = _T_167 | _T_170; // @[lib.scala 104:23] + wire _T_173 = &io_trigger_pkt_any_0_tdata2[2:0]; // @[lib.scala 104:36] + wire _T_174 = _T_173 & _T_153; // @[lib.scala 104:41] + wire _T_177 = io_trigger_pkt_any_0_tdata2[3] == dec_i0_match_data_0[3]; // @[lib.scala 104:78] + wire _T_178 = _T_174 | _T_177; // @[lib.scala 104:23] + wire _T_180 = &io_trigger_pkt_any_0_tdata2[3:0]; // @[lib.scala 104:36] + wire _T_181 = _T_180 & _T_153; // @[lib.scala 104:41] + wire _T_184 = io_trigger_pkt_any_0_tdata2[4] == dec_i0_match_data_0[4]; // @[lib.scala 104:78] + wire _T_185 = _T_181 | _T_184; // @[lib.scala 104:23] + wire _T_187 = &io_trigger_pkt_any_0_tdata2[4:0]; // @[lib.scala 104:36] + wire _T_188 = _T_187 & _T_153; // @[lib.scala 104:41] + wire _T_191 = io_trigger_pkt_any_0_tdata2[5] == dec_i0_match_data_0[5]; // @[lib.scala 104:78] + wire _T_192 = _T_188 | _T_191; // @[lib.scala 104:23] + wire _T_194 = &io_trigger_pkt_any_0_tdata2[5:0]; // @[lib.scala 104:36] + wire _T_195 = _T_194 & _T_153; // @[lib.scala 104:41] + wire _T_198 = io_trigger_pkt_any_0_tdata2[6] == dec_i0_match_data_0[6]; // @[lib.scala 104:78] + wire _T_199 = _T_195 | _T_198; // @[lib.scala 104:23] + wire _T_201 = &io_trigger_pkt_any_0_tdata2[6:0]; // @[lib.scala 104:36] + wire _T_202 = _T_201 & _T_153; // @[lib.scala 104:41] + wire _T_205 = io_trigger_pkt_any_0_tdata2[7] == dec_i0_match_data_0[7]; // @[lib.scala 104:78] + wire _T_206 = _T_202 | _T_205; // @[lib.scala 104:23] + wire _T_208 = &io_trigger_pkt_any_0_tdata2[7:0]; // @[lib.scala 104:36] + wire _T_209 = _T_208 & _T_153; // @[lib.scala 104:41] + wire _T_212 = io_trigger_pkt_any_0_tdata2[8] == dec_i0_match_data_0[8]; // @[lib.scala 104:78] + wire _T_213 = _T_209 | _T_212; // @[lib.scala 104:23] + wire _T_215 = &io_trigger_pkt_any_0_tdata2[8:0]; // @[lib.scala 104:36] + wire _T_216 = _T_215 & _T_153; // @[lib.scala 104:41] + wire _T_219 = io_trigger_pkt_any_0_tdata2[9] == dec_i0_match_data_0[9]; // @[lib.scala 104:78] + wire _T_220 = _T_216 | _T_219; // @[lib.scala 104:23] + wire _T_222 = &io_trigger_pkt_any_0_tdata2[9:0]; // @[lib.scala 104:36] + wire _T_223 = _T_222 & _T_153; // @[lib.scala 104:41] + wire _T_226 = io_trigger_pkt_any_0_tdata2[10] == dec_i0_match_data_0[10]; // @[lib.scala 104:78] + wire _T_227 = _T_223 | _T_226; // @[lib.scala 104:23] + wire _T_229 = &io_trigger_pkt_any_0_tdata2[10:0]; // @[lib.scala 104:36] + wire _T_230 = _T_229 & _T_153; // @[lib.scala 104:41] + wire _T_233 = io_trigger_pkt_any_0_tdata2[11] == dec_i0_match_data_0[11]; // @[lib.scala 104:78] + wire _T_234 = _T_230 | _T_233; // @[lib.scala 104:23] + wire _T_236 = &io_trigger_pkt_any_0_tdata2[11:0]; // @[lib.scala 104:36] + wire _T_237 = _T_236 & _T_153; // @[lib.scala 104:41] + wire _T_240 = io_trigger_pkt_any_0_tdata2[12] == dec_i0_match_data_0[12]; // @[lib.scala 104:78] + wire _T_241 = _T_237 | _T_240; // @[lib.scala 104:23] + wire _T_243 = &io_trigger_pkt_any_0_tdata2[12:0]; // @[lib.scala 104:36] + wire _T_244 = _T_243 & _T_153; // @[lib.scala 104:41] + wire _T_247 = io_trigger_pkt_any_0_tdata2[13] == dec_i0_match_data_0[13]; // @[lib.scala 104:78] + wire _T_248 = _T_244 | _T_247; // @[lib.scala 104:23] + wire _T_250 = &io_trigger_pkt_any_0_tdata2[13:0]; // @[lib.scala 104:36] + wire _T_251 = _T_250 & _T_153; // @[lib.scala 104:41] + wire _T_254 = io_trigger_pkt_any_0_tdata2[14] == dec_i0_match_data_0[14]; // @[lib.scala 104:78] + wire _T_255 = _T_251 | _T_254; // @[lib.scala 104:23] + wire _T_257 = &io_trigger_pkt_any_0_tdata2[14:0]; // @[lib.scala 104:36] + wire _T_258 = _T_257 & _T_153; // @[lib.scala 104:41] + wire _T_261 = io_trigger_pkt_any_0_tdata2[15] == dec_i0_match_data_0[15]; // @[lib.scala 104:78] + wire _T_262 = _T_258 | _T_261; // @[lib.scala 104:23] + wire _T_264 = &io_trigger_pkt_any_0_tdata2[15:0]; // @[lib.scala 104:36] + wire _T_265 = _T_264 & _T_153; // @[lib.scala 104:41] + wire _T_268 = io_trigger_pkt_any_0_tdata2[16] == dec_i0_match_data_0[16]; // @[lib.scala 104:78] + wire _T_269 = _T_265 | _T_268; // @[lib.scala 104:23] + wire _T_271 = &io_trigger_pkt_any_0_tdata2[16:0]; // @[lib.scala 104:36] + wire _T_272 = _T_271 & _T_153; // @[lib.scala 104:41] + wire _T_275 = io_trigger_pkt_any_0_tdata2[17] == dec_i0_match_data_0[17]; // @[lib.scala 104:78] + wire _T_276 = _T_272 | _T_275; // @[lib.scala 104:23] + wire _T_278 = &io_trigger_pkt_any_0_tdata2[17:0]; // @[lib.scala 104:36] + wire _T_279 = _T_278 & _T_153; // @[lib.scala 104:41] + wire _T_282 = io_trigger_pkt_any_0_tdata2[18] == dec_i0_match_data_0[18]; // @[lib.scala 104:78] + wire _T_283 = _T_279 | _T_282; // @[lib.scala 104:23] + wire _T_285 = &io_trigger_pkt_any_0_tdata2[18:0]; // @[lib.scala 104:36] + wire _T_286 = _T_285 & _T_153; // @[lib.scala 104:41] + wire _T_289 = io_trigger_pkt_any_0_tdata2[19] == dec_i0_match_data_0[19]; // @[lib.scala 104:78] + wire _T_290 = _T_286 | _T_289; // @[lib.scala 104:23] + wire _T_292 = &io_trigger_pkt_any_0_tdata2[19:0]; // @[lib.scala 104:36] + wire _T_293 = _T_292 & _T_153; // @[lib.scala 104:41] + wire _T_296 = io_trigger_pkt_any_0_tdata2[20] == dec_i0_match_data_0[20]; // @[lib.scala 104:78] + wire _T_297 = _T_293 | _T_296; // @[lib.scala 104:23] + wire _T_299 = &io_trigger_pkt_any_0_tdata2[20:0]; // @[lib.scala 104:36] + wire _T_300 = _T_299 & _T_153; // @[lib.scala 104:41] + wire _T_303 = io_trigger_pkt_any_0_tdata2[21] == dec_i0_match_data_0[21]; // @[lib.scala 104:78] + wire _T_304 = _T_300 | _T_303; // @[lib.scala 104:23] + wire _T_306 = &io_trigger_pkt_any_0_tdata2[21:0]; // @[lib.scala 104:36] + wire _T_307 = _T_306 & _T_153; // @[lib.scala 104:41] + wire _T_310 = io_trigger_pkt_any_0_tdata2[22] == dec_i0_match_data_0[22]; // @[lib.scala 104:78] + wire _T_311 = _T_307 | _T_310; // @[lib.scala 104:23] + wire _T_313 = &io_trigger_pkt_any_0_tdata2[22:0]; // @[lib.scala 104:36] + wire _T_314 = _T_313 & _T_153; // @[lib.scala 104:41] + wire _T_317 = io_trigger_pkt_any_0_tdata2[23] == dec_i0_match_data_0[23]; // @[lib.scala 104:78] + wire _T_318 = _T_314 | _T_317; // @[lib.scala 104:23] + wire _T_320 = &io_trigger_pkt_any_0_tdata2[23:0]; // @[lib.scala 104:36] + wire _T_321 = _T_320 & _T_153; // @[lib.scala 104:41] + wire _T_324 = io_trigger_pkt_any_0_tdata2[24] == dec_i0_match_data_0[24]; // @[lib.scala 104:78] + wire _T_325 = _T_321 | _T_324; // @[lib.scala 104:23] + wire _T_327 = &io_trigger_pkt_any_0_tdata2[24:0]; // @[lib.scala 104:36] + wire _T_328 = _T_327 & _T_153; // @[lib.scala 104:41] + wire _T_331 = io_trigger_pkt_any_0_tdata2[25] == dec_i0_match_data_0[25]; // @[lib.scala 104:78] + wire _T_332 = _T_328 | _T_331; // @[lib.scala 104:23] + wire _T_334 = &io_trigger_pkt_any_0_tdata2[25:0]; // @[lib.scala 104:36] + wire _T_335 = _T_334 & _T_153; // @[lib.scala 104:41] + wire _T_338 = io_trigger_pkt_any_0_tdata2[26] == dec_i0_match_data_0[26]; // @[lib.scala 104:78] + wire _T_339 = _T_335 | _T_338; // @[lib.scala 104:23] + wire _T_341 = &io_trigger_pkt_any_0_tdata2[26:0]; // @[lib.scala 104:36] + wire _T_342 = _T_341 & _T_153; // @[lib.scala 104:41] + wire _T_345 = io_trigger_pkt_any_0_tdata2[27] == dec_i0_match_data_0[27]; // @[lib.scala 104:78] + wire _T_346 = _T_342 | _T_345; // @[lib.scala 104:23] + wire _T_348 = &io_trigger_pkt_any_0_tdata2[27:0]; // @[lib.scala 104:36] + wire _T_349 = _T_348 & _T_153; // @[lib.scala 104:41] + wire _T_352 = io_trigger_pkt_any_0_tdata2[28] == dec_i0_match_data_0[28]; // @[lib.scala 104:78] + wire _T_353 = _T_349 | _T_352; // @[lib.scala 104:23] + wire _T_355 = &io_trigger_pkt_any_0_tdata2[28:0]; // @[lib.scala 104:36] + wire _T_356 = _T_355 & _T_153; // @[lib.scala 104:41] + wire _T_359 = io_trigger_pkt_any_0_tdata2[29] == dec_i0_match_data_0[29]; // @[lib.scala 104:78] + wire _T_360 = _T_356 | _T_359; // @[lib.scala 104:23] + wire _T_362 = &io_trigger_pkt_any_0_tdata2[29:0]; // @[lib.scala 104:36] + wire _T_363 = _T_362 & _T_153; // @[lib.scala 104:41] + wire _T_366 = io_trigger_pkt_any_0_tdata2[30] == dec_i0_match_data_0[30]; // @[lib.scala 104:78] + wire _T_367 = _T_363 | _T_366; // @[lib.scala 104:23] + wire _T_369 = &io_trigger_pkt_any_0_tdata2[30:0]; // @[lib.scala 104:36] + wire _T_370 = _T_369 & _T_153; // @[lib.scala 104:41] + wire _T_373 = io_trigger_pkt_any_0_tdata2[31] == dec_i0_match_data_0[31]; // @[lib.scala 104:78] + wire _T_374 = _T_370 | _T_373; // @[lib.scala 104:23] + wire [7:0] _T_381 = {_T_206,_T_199,_T_192,_T_185,_T_178,_T_171,_T_164,_T_157}; // @[lib.scala 105:14] + wire [15:0] _T_389 = {_T_262,_T_255,_T_248,_T_241,_T_234,_T_227,_T_220,_T_213,_T_381}; // @[lib.scala 105:14] + wire [7:0] _T_396 = {_T_318,_T_311,_T_304,_T_297,_T_290,_T_283,_T_276,_T_269}; // @[lib.scala 105:14] + wire [31:0] _T_405 = {_T_374,_T_367,_T_360,_T_353,_T_346,_T_339,_T_332,_T_325,_T_396,_T_389}; // @[lib.scala 105:14] + wire _T_406 = &_T_405; // @[lib.scala 105:25] wire _T_407 = _T_148 & _T_406; // @[dec_trigger.scala 15:109] wire _T_408 = io_trigger_pkt_any_1_execute & io_trigger_pkt_any_1_m; // @[dec_trigger.scala 15:83] - wire _T_411 = &io_trigger_pkt_any_1_tdata2; // @[el2_lib.scala 241:45] - wire _T_412 = ~_T_411; // @[el2_lib.scala 241:39] - wire _T_413 = io_trigger_pkt_any_1_match_pkt & _T_412; // @[el2_lib.scala 241:37] - wire _T_416 = io_trigger_pkt_any_1_tdata2[0] == dec_i0_match_data_1[0]; // @[el2_lib.scala 242:52] - wire _T_417 = _T_413 | _T_416; // @[el2_lib.scala 242:41] - wire _T_419 = &io_trigger_pkt_any_1_tdata2[0]; // @[el2_lib.scala 244:36] - wire _T_420 = _T_419 & _T_413; // @[el2_lib.scala 244:41] - wire _T_423 = io_trigger_pkt_any_1_tdata2[1] == dec_i0_match_data_1[1]; // @[el2_lib.scala 244:78] - wire _T_424 = _T_420 | _T_423; // @[el2_lib.scala 244:23] - wire _T_426 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[el2_lib.scala 244:36] - wire _T_427 = _T_426 & _T_413; // @[el2_lib.scala 244:41] - wire _T_430 = io_trigger_pkt_any_1_tdata2[2] == dec_i0_match_data_1[2]; // @[el2_lib.scala 244:78] - wire _T_431 = _T_427 | _T_430; // @[el2_lib.scala 244:23] - wire _T_433 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[el2_lib.scala 244:36] - wire _T_434 = _T_433 & _T_413; // @[el2_lib.scala 244:41] - wire _T_437 = io_trigger_pkt_any_1_tdata2[3] == dec_i0_match_data_1[3]; // @[el2_lib.scala 244:78] - wire _T_438 = _T_434 | _T_437; // @[el2_lib.scala 244:23] - wire _T_440 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[el2_lib.scala 244:36] - wire _T_441 = _T_440 & _T_413; // @[el2_lib.scala 244:41] - wire _T_444 = io_trigger_pkt_any_1_tdata2[4] == dec_i0_match_data_1[4]; // @[el2_lib.scala 244:78] - wire _T_445 = _T_441 | _T_444; // @[el2_lib.scala 244:23] - wire _T_447 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[el2_lib.scala 244:36] - wire _T_448 = _T_447 & _T_413; // @[el2_lib.scala 244:41] - wire _T_451 = io_trigger_pkt_any_1_tdata2[5] == dec_i0_match_data_1[5]; // @[el2_lib.scala 244:78] - wire _T_452 = _T_448 | _T_451; // @[el2_lib.scala 244:23] - wire _T_454 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[el2_lib.scala 244:36] - wire _T_455 = _T_454 & _T_413; // @[el2_lib.scala 244:41] - wire _T_458 = io_trigger_pkt_any_1_tdata2[6] == dec_i0_match_data_1[6]; // @[el2_lib.scala 244:78] - wire _T_459 = _T_455 | _T_458; // @[el2_lib.scala 244:23] - wire _T_461 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[el2_lib.scala 244:36] - wire _T_462 = _T_461 & _T_413; // @[el2_lib.scala 244:41] - wire _T_465 = io_trigger_pkt_any_1_tdata2[7] == dec_i0_match_data_1[7]; // @[el2_lib.scala 244:78] - wire _T_466 = _T_462 | _T_465; // @[el2_lib.scala 244:23] - wire _T_468 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[el2_lib.scala 244:36] - wire _T_469 = _T_468 & _T_413; // @[el2_lib.scala 244:41] - wire _T_472 = io_trigger_pkt_any_1_tdata2[8] == dec_i0_match_data_1[8]; // @[el2_lib.scala 244:78] - wire _T_473 = _T_469 | _T_472; // @[el2_lib.scala 244:23] - wire _T_475 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[el2_lib.scala 244:36] - wire _T_476 = _T_475 & _T_413; // @[el2_lib.scala 244:41] - wire _T_479 = io_trigger_pkt_any_1_tdata2[9] == dec_i0_match_data_1[9]; // @[el2_lib.scala 244:78] - wire _T_480 = _T_476 | _T_479; // @[el2_lib.scala 244:23] - wire _T_482 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[el2_lib.scala 244:36] - wire _T_483 = _T_482 & _T_413; // @[el2_lib.scala 244:41] - wire _T_486 = io_trigger_pkt_any_1_tdata2[10] == dec_i0_match_data_1[10]; // @[el2_lib.scala 244:78] - wire _T_487 = _T_483 | _T_486; // @[el2_lib.scala 244:23] - wire _T_489 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[el2_lib.scala 244:36] - wire _T_490 = _T_489 & _T_413; // @[el2_lib.scala 244:41] - wire _T_493 = io_trigger_pkt_any_1_tdata2[11] == dec_i0_match_data_1[11]; // @[el2_lib.scala 244:78] - wire _T_494 = _T_490 | _T_493; // @[el2_lib.scala 244:23] - wire _T_496 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[el2_lib.scala 244:36] - wire _T_497 = _T_496 & _T_413; // @[el2_lib.scala 244:41] - wire _T_500 = io_trigger_pkt_any_1_tdata2[12] == dec_i0_match_data_1[12]; // @[el2_lib.scala 244:78] - wire _T_501 = _T_497 | _T_500; // @[el2_lib.scala 244:23] - wire _T_503 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[el2_lib.scala 244:36] - wire _T_504 = _T_503 & _T_413; // @[el2_lib.scala 244:41] - wire _T_507 = io_trigger_pkt_any_1_tdata2[13] == dec_i0_match_data_1[13]; // @[el2_lib.scala 244:78] - wire _T_508 = _T_504 | _T_507; // @[el2_lib.scala 244:23] - wire _T_510 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[el2_lib.scala 244:36] - wire _T_511 = _T_510 & _T_413; // @[el2_lib.scala 244:41] - wire _T_514 = io_trigger_pkt_any_1_tdata2[14] == dec_i0_match_data_1[14]; // @[el2_lib.scala 244:78] - wire _T_515 = _T_511 | _T_514; // @[el2_lib.scala 244:23] - wire _T_517 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[el2_lib.scala 244:36] - wire _T_518 = _T_517 & _T_413; // @[el2_lib.scala 244:41] - wire _T_521 = io_trigger_pkt_any_1_tdata2[15] == dec_i0_match_data_1[15]; // @[el2_lib.scala 244:78] - wire _T_522 = _T_518 | _T_521; // @[el2_lib.scala 244:23] - wire _T_524 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[el2_lib.scala 244:36] - wire _T_525 = _T_524 & _T_413; // @[el2_lib.scala 244:41] - wire _T_528 = io_trigger_pkt_any_1_tdata2[16] == dec_i0_match_data_1[16]; // @[el2_lib.scala 244:78] - wire _T_529 = _T_525 | _T_528; // @[el2_lib.scala 244:23] - wire _T_531 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[el2_lib.scala 244:36] - wire _T_532 = _T_531 & _T_413; // @[el2_lib.scala 244:41] - wire _T_535 = io_trigger_pkt_any_1_tdata2[17] == dec_i0_match_data_1[17]; // @[el2_lib.scala 244:78] - wire _T_536 = _T_532 | _T_535; // @[el2_lib.scala 244:23] - wire _T_538 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[el2_lib.scala 244:36] - wire _T_539 = _T_538 & _T_413; // @[el2_lib.scala 244:41] - wire _T_542 = io_trigger_pkt_any_1_tdata2[18] == dec_i0_match_data_1[18]; // @[el2_lib.scala 244:78] - wire _T_543 = _T_539 | _T_542; // @[el2_lib.scala 244:23] - wire _T_545 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[el2_lib.scala 244:36] - wire _T_546 = _T_545 & _T_413; // @[el2_lib.scala 244:41] - wire _T_549 = io_trigger_pkt_any_1_tdata2[19] == dec_i0_match_data_1[19]; // @[el2_lib.scala 244:78] - wire _T_550 = _T_546 | _T_549; // @[el2_lib.scala 244:23] - wire _T_552 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[el2_lib.scala 244:36] - wire _T_553 = _T_552 & _T_413; // @[el2_lib.scala 244:41] - wire _T_556 = io_trigger_pkt_any_1_tdata2[20] == dec_i0_match_data_1[20]; // @[el2_lib.scala 244:78] - wire _T_557 = _T_553 | _T_556; // @[el2_lib.scala 244:23] - wire _T_559 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[el2_lib.scala 244:36] - wire _T_560 = _T_559 & _T_413; // @[el2_lib.scala 244:41] - wire _T_563 = io_trigger_pkt_any_1_tdata2[21] == dec_i0_match_data_1[21]; // @[el2_lib.scala 244:78] - wire _T_564 = _T_560 | _T_563; // @[el2_lib.scala 244:23] - wire _T_566 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[el2_lib.scala 244:36] - wire _T_567 = _T_566 & _T_413; // @[el2_lib.scala 244:41] - wire _T_570 = io_trigger_pkt_any_1_tdata2[22] == dec_i0_match_data_1[22]; // @[el2_lib.scala 244:78] - wire _T_571 = _T_567 | _T_570; // @[el2_lib.scala 244:23] - wire _T_573 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[el2_lib.scala 244:36] - wire _T_574 = _T_573 & _T_413; // @[el2_lib.scala 244:41] - wire _T_577 = io_trigger_pkt_any_1_tdata2[23] == dec_i0_match_data_1[23]; // @[el2_lib.scala 244:78] - wire _T_578 = _T_574 | _T_577; // @[el2_lib.scala 244:23] - wire _T_580 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[el2_lib.scala 244:36] - wire _T_581 = _T_580 & _T_413; // @[el2_lib.scala 244:41] - wire _T_584 = io_trigger_pkt_any_1_tdata2[24] == dec_i0_match_data_1[24]; // @[el2_lib.scala 244:78] - wire _T_585 = _T_581 | _T_584; // @[el2_lib.scala 244:23] - wire _T_587 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[el2_lib.scala 244:36] - wire _T_588 = _T_587 & _T_413; // @[el2_lib.scala 244:41] - wire _T_591 = io_trigger_pkt_any_1_tdata2[25] == dec_i0_match_data_1[25]; // @[el2_lib.scala 244:78] - wire _T_592 = _T_588 | _T_591; // @[el2_lib.scala 244:23] - wire _T_594 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[el2_lib.scala 244:36] - wire _T_595 = _T_594 & _T_413; // @[el2_lib.scala 244:41] - wire _T_598 = io_trigger_pkt_any_1_tdata2[26] == dec_i0_match_data_1[26]; // @[el2_lib.scala 244:78] - wire _T_599 = _T_595 | _T_598; // @[el2_lib.scala 244:23] - wire _T_601 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[el2_lib.scala 244:36] - wire _T_602 = _T_601 & _T_413; // @[el2_lib.scala 244:41] - wire _T_605 = io_trigger_pkt_any_1_tdata2[27] == dec_i0_match_data_1[27]; // @[el2_lib.scala 244:78] - wire _T_606 = _T_602 | _T_605; // @[el2_lib.scala 244:23] - wire _T_608 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[el2_lib.scala 244:36] - wire _T_609 = _T_608 & _T_413; // @[el2_lib.scala 244:41] - wire _T_612 = io_trigger_pkt_any_1_tdata2[28] == dec_i0_match_data_1[28]; // @[el2_lib.scala 244:78] - wire _T_613 = _T_609 | _T_612; // @[el2_lib.scala 244:23] - wire _T_615 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[el2_lib.scala 244:36] - wire _T_616 = _T_615 & _T_413; // @[el2_lib.scala 244:41] - wire _T_619 = io_trigger_pkt_any_1_tdata2[29] == dec_i0_match_data_1[29]; // @[el2_lib.scala 244:78] - wire _T_620 = _T_616 | _T_619; // @[el2_lib.scala 244:23] - wire _T_622 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[el2_lib.scala 244:36] - wire _T_623 = _T_622 & _T_413; // @[el2_lib.scala 244:41] - wire _T_626 = io_trigger_pkt_any_1_tdata2[30] == dec_i0_match_data_1[30]; // @[el2_lib.scala 244:78] - wire _T_627 = _T_623 | _T_626; // @[el2_lib.scala 244:23] - wire _T_629 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[el2_lib.scala 244:36] - wire _T_630 = _T_629 & _T_413; // @[el2_lib.scala 244:41] - wire _T_633 = io_trigger_pkt_any_1_tdata2[31] == dec_i0_match_data_1[31]; // @[el2_lib.scala 244:78] - wire _T_634 = _T_630 | _T_633; // @[el2_lib.scala 244:23] - wire [7:0] _T_641 = {_T_466,_T_459,_T_452,_T_445,_T_438,_T_431,_T_424,_T_417}; // @[el2_lib.scala 245:14] - wire [15:0] _T_649 = {_T_522,_T_515,_T_508,_T_501,_T_494,_T_487,_T_480,_T_473,_T_641}; // @[el2_lib.scala 245:14] - wire [7:0] _T_656 = {_T_578,_T_571,_T_564,_T_557,_T_550,_T_543,_T_536,_T_529}; // @[el2_lib.scala 245:14] - wire [31:0] _T_665 = {_T_634,_T_627,_T_620,_T_613,_T_606,_T_599,_T_592,_T_585,_T_656,_T_649}; // @[el2_lib.scala 245:14] - wire _T_666 = &_T_665; // @[el2_lib.scala 245:25] + wire _T_411 = &io_trigger_pkt_any_1_tdata2; // @[lib.scala 101:45] + wire _T_412 = ~_T_411; // @[lib.scala 101:39] + wire _T_413 = io_trigger_pkt_any_1_match_pkt & _T_412; // @[lib.scala 101:37] + wire _T_416 = io_trigger_pkt_any_1_tdata2[0] == dec_i0_match_data_1[0]; // @[lib.scala 102:52] + wire _T_417 = _T_413 | _T_416; // @[lib.scala 102:41] + wire _T_419 = &io_trigger_pkt_any_1_tdata2[0]; // @[lib.scala 104:36] + wire _T_420 = _T_419 & _T_413; // @[lib.scala 104:41] + wire _T_423 = io_trigger_pkt_any_1_tdata2[1] == dec_i0_match_data_1[1]; // @[lib.scala 104:78] + wire _T_424 = _T_420 | _T_423; // @[lib.scala 104:23] + wire _T_426 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[lib.scala 104:36] + wire _T_427 = _T_426 & _T_413; // @[lib.scala 104:41] + wire _T_430 = io_trigger_pkt_any_1_tdata2[2] == dec_i0_match_data_1[2]; // @[lib.scala 104:78] + wire _T_431 = _T_427 | _T_430; // @[lib.scala 104:23] + wire _T_433 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[lib.scala 104:36] + wire _T_434 = _T_433 & _T_413; // @[lib.scala 104:41] + wire _T_437 = io_trigger_pkt_any_1_tdata2[3] == dec_i0_match_data_1[3]; // @[lib.scala 104:78] + wire _T_438 = _T_434 | _T_437; // @[lib.scala 104:23] + wire _T_440 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[lib.scala 104:36] + wire _T_441 = _T_440 & _T_413; // @[lib.scala 104:41] + wire _T_444 = io_trigger_pkt_any_1_tdata2[4] == dec_i0_match_data_1[4]; // @[lib.scala 104:78] + wire _T_445 = _T_441 | _T_444; // @[lib.scala 104:23] + wire _T_447 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[lib.scala 104:36] + wire _T_448 = _T_447 & _T_413; // @[lib.scala 104:41] + wire _T_451 = io_trigger_pkt_any_1_tdata2[5] == dec_i0_match_data_1[5]; // @[lib.scala 104:78] + wire _T_452 = _T_448 | _T_451; // @[lib.scala 104:23] + wire _T_454 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[lib.scala 104:36] + wire _T_455 = _T_454 & _T_413; // @[lib.scala 104:41] + wire _T_458 = io_trigger_pkt_any_1_tdata2[6] == dec_i0_match_data_1[6]; // @[lib.scala 104:78] + wire _T_459 = _T_455 | _T_458; // @[lib.scala 104:23] + wire _T_461 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[lib.scala 104:36] + wire _T_462 = _T_461 & _T_413; // @[lib.scala 104:41] + wire _T_465 = io_trigger_pkt_any_1_tdata2[7] == dec_i0_match_data_1[7]; // @[lib.scala 104:78] + wire _T_466 = _T_462 | _T_465; // @[lib.scala 104:23] + wire _T_468 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[lib.scala 104:36] + wire _T_469 = _T_468 & _T_413; // @[lib.scala 104:41] + wire _T_472 = io_trigger_pkt_any_1_tdata2[8] == dec_i0_match_data_1[8]; // @[lib.scala 104:78] + wire _T_473 = _T_469 | _T_472; // @[lib.scala 104:23] + wire _T_475 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[lib.scala 104:36] + wire _T_476 = _T_475 & _T_413; // @[lib.scala 104:41] + wire _T_479 = io_trigger_pkt_any_1_tdata2[9] == dec_i0_match_data_1[9]; // @[lib.scala 104:78] + wire _T_480 = _T_476 | _T_479; // @[lib.scala 104:23] + wire _T_482 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[lib.scala 104:36] + wire _T_483 = _T_482 & _T_413; // @[lib.scala 104:41] + wire _T_486 = io_trigger_pkt_any_1_tdata2[10] == dec_i0_match_data_1[10]; // @[lib.scala 104:78] + wire _T_487 = _T_483 | _T_486; // @[lib.scala 104:23] + wire _T_489 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[lib.scala 104:36] + wire _T_490 = _T_489 & _T_413; // @[lib.scala 104:41] + wire _T_493 = io_trigger_pkt_any_1_tdata2[11] == dec_i0_match_data_1[11]; // @[lib.scala 104:78] + wire _T_494 = _T_490 | _T_493; // @[lib.scala 104:23] + wire _T_496 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[lib.scala 104:36] + wire _T_497 = _T_496 & _T_413; // @[lib.scala 104:41] + wire _T_500 = io_trigger_pkt_any_1_tdata2[12] == dec_i0_match_data_1[12]; // @[lib.scala 104:78] + wire _T_501 = _T_497 | _T_500; // @[lib.scala 104:23] + wire _T_503 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[lib.scala 104:36] + wire _T_504 = _T_503 & _T_413; // @[lib.scala 104:41] + wire _T_507 = io_trigger_pkt_any_1_tdata2[13] == dec_i0_match_data_1[13]; // @[lib.scala 104:78] + wire _T_508 = _T_504 | _T_507; // @[lib.scala 104:23] + wire _T_510 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[lib.scala 104:36] + wire _T_511 = _T_510 & _T_413; // @[lib.scala 104:41] + wire _T_514 = io_trigger_pkt_any_1_tdata2[14] == dec_i0_match_data_1[14]; // @[lib.scala 104:78] + wire _T_515 = _T_511 | _T_514; // @[lib.scala 104:23] + wire _T_517 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[lib.scala 104:36] + wire _T_518 = _T_517 & _T_413; // @[lib.scala 104:41] + wire _T_521 = io_trigger_pkt_any_1_tdata2[15] == dec_i0_match_data_1[15]; // @[lib.scala 104:78] + wire _T_522 = _T_518 | _T_521; // @[lib.scala 104:23] + wire _T_524 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[lib.scala 104:36] + wire _T_525 = _T_524 & _T_413; // @[lib.scala 104:41] + wire _T_528 = io_trigger_pkt_any_1_tdata2[16] == dec_i0_match_data_1[16]; // @[lib.scala 104:78] + wire _T_529 = _T_525 | _T_528; // @[lib.scala 104:23] + wire _T_531 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[lib.scala 104:36] + wire _T_532 = _T_531 & _T_413; // @[lib.scala 104:41] + wire _T_535 = io_trigger_pkt_any_1_tdata2[17] == dec_i0_match_data_1[17]; // @[lib.scala 104:78] + wire _T_536 = _T_532 | _T_535; // @[lib.scala 104:23] + wire _T_538 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[lib.scala 104:36] + wire _T_539 = _T_538 & _T_413; // @[lib.scala 104:41] + wire _T_542 = io_trigger_pkt_any_1_tdata2[18] == dec_i0_match_data_1[18]; // @[lib.scala 104:78] + wire _T_543 = _T_539 | _T_542; // @[lib.scala 104:23] + wire _T_545 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[lib.scala 104:36] + wire _T_546 = _T_545 & _T_413; // @[lib.scala 104:41] + wire _T_549 = io_trigger_pkt_any_1_tdata2[19] == dec_i0_match_data_1[19]; // @[lib.scala 104:78] + wire _T_550 = _T_546 | _T_549; // @[lib.scala 104:23] + wire _T_552 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[lib.scala 104:36] + wire _T_553 = _T_552 & _T_413; // @[lib.scala 104:41] + wire _T_556 = io_trigger_pkt_any_1_tdata2[20] == dec_i0_match_data_1[20]; // @[lib.scala 104:78] + wire _T_557 = _T_553 | _T_556; // @[lib.scala 104:23] + wire _T_559 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[lib.scala 104:36] + wire _T_560 = _T_559 & _T_413; // @[lib.scala 104:41] + wire _T_563 = io_trigger_pkt_any_1_tdata2[21] == dec_i0_match_data_1[21]; // @[lib.scala 104:78] + wire _T_564 = _T_560 | _T_563; // @[lib.scala 104:23] + wire _T_566 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[lib.scala 104:36] + wire _T_567 = _T_566 & _T_413; // @[lib.scala 104:41] + wire _T_570 = io_trigger_pkt_any_1_tdata2[22] == dec_i0_match_data_1[22]; // @[lib.scala 104:78] + wire _T_571 = _T_567 | _T_570; // @[lib.scala 104:23] + wire _T_573 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[lib.scala 104:36] + wire _T_574 = _T_573 & _T_413; // @[lib.scala 104:41] + wire _T_577 = io_trigger_pkt_any_1_tdata2[23] == dec_i0_match_data_1[23]; // @[lib.scala 104:78] + wire _T_578 = _T_574 | _T_577; // @[lib.scala 104:23] + wire _T_580 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[lib.scala 104:36] + wire _T_581 = _T_580 & _T_413; // @[lib.scala 104:41] + wire _T_584 = io_trigger_pkt_any_1_tdata2[24] == dec_i0_match_data_1[24]; // @[lib.scala 104:78] + wire _T_585 = _T_581 | _T_584; // @[lib.scala 104:23] + wire _T_587 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[lib.scala 104:36] + wire _T_588 = _T_587 & _T_413; // @[lib.scala 104:41] + wire _T_591 = io_trigger_pkt_any_1_tdata2[25] == dec_i0_match_data_1[25]; // @[lib.scala 104:78] + wire _T_592 = _T_588 | _T_591; // @[lib.scala 104:23] + wire _T_594 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[lib.scala 104:36] + wire _T_595 = _T_594 & _T_413; // @[lib.scala 104:41] + wire _T_598 = io_trigger_pkt_any_1_tdata2[26] == dec_i0_match_data_1[26]; // @[lib.scala 104:78] + wire _T_599 = _T_595 | _T_598; // @[lib.scala 104:23] + wire _T_601 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[lib.scala 104:36] + wire _T_602 = _T_601 & _T_413; // @[lib.scala 104:41] + wire _T_605 = io_trigger_pkt_any_1_tdata2[27] == dec_i0_match_data_1[27]; // @[lib.scala 104:78] + wire _T_606 = _T_602 | _T_605; // @[lib.scala 104:23] + wire _T_608 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[lib.scala 104:36] + wire _T_609 = _T_608 & _T_413; // @[lib.scala 104:41] + wire _T_612 = io_trigger_pkt_any_1_tdata2[28] == dec_i0_match_data_1[28]; // @[lib.scala 104:78] + wire _T_613 = _T_609 | _T_612; // @[lib.scala 104:23] + wire _T_615 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[lib.scala 104:36] + wire _T_616 = _T_615 & _T_413; // @[lib.scala 104:41] + wire _T_619 = io_trigger_pkt_any_1_tdata2[29] == dec_i0_match_data_1[29]; // @[lib.scala 104:78] + wire _T_620 = _T_616 | _T_619; // @[lib.scala 104:23] + wire _T_622 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[lib.scala 104:36] + wire _T_623 = _T_622 & _T_413; // @[lib.scala 104:41] + wire _T_626 = io_trigger_pkt_any_1_tdata2[30] == dec_i0_match_data_1[30]; // @[lib.scala 104:78] + wire _T_627 = _T_623 | _T_626; // @[lib.scala 104:23] + wire _T_629 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[lib.scala 104:36] + wire _T_630 = _T_629 & _T_413; // @[lib.scala 104:41] + wire _T_633 = io_trigger_pkt_any_1_tdata2[31] == dec_i0_match_data_1[31]; // @[lib.scala 104:78] + wire _T_634 = _T_630 | _T_633; // @[lib.scala 104:23] + wire [7:0] _T_641 = {_T_466,_T_459,_T_452,_T_445,_T_438,_T_431,_T_424,_T_417}; // @[lib.scala 105:14] + wire [15:0] _T_649 = {_T_522,_T_515,_T_508,_T_501,_T_494,_T_487,_T_480,_T_473,_T_641}; // @[lib.scala 105:14] + wire [7:0] _T_656 = {_T_578,_T_571,_T_564,_T_557,_T_550,_T_543,_T_536,_T_529}; // @[lib.scala 105:14] + wire [31:0] _T_665 = {_T_634,_T_627,_T_620,_T_613,_T_606,_T_599,_T_592,_T_585,_T_656,_T_649}; // @[lib.scala 105:14] + wire _T_666 = &_T_665; // @[lib.scala 105:25] wire _T_667 = _T_408 & _T_666; // @[dec_trigger.scala 15:109] wire _T_668 = io_trigger_pkt_any_2_execute & io_trigger_pkt_any_2_m; // @[dec_trigger.scala 15:83] - wire _T_671 = &io_trigger_pkt_any_2_tdata2; // @[el2_lib.scala 241:45] - wire _T_672 = ~_T_671; // @[el2_lib.scala 241:39] - wire _T_673 = io_trigger_pkt_any_2_match_pkt & _T_672; // @[el2_lib.scala 241:37] - wire _T_676 = io_trigger_pkt_any_2_tdata2[0] == dec_i0_match_data_2[0]; // @[el2_lib.scala 242:52] - wire _T_677 = _T_673 | _T_676; // @[el2_lib.scala 242:41] - wire _T_679 = &io_trigger_pkt_any_2_tdata2[0]; // @[el2_lib.scala 244:36] - wire _T_680 = _T_679 & _T_673; // @[el2_lib.scala 244:41] - wire _T_683 = io_trigger_pkt_any_2_tdata2[1] == dec_i0_match_data_2[1]; // @[el2_lib.scala 244:78] - wire _T_684 = _T_680 | _T_683; // @[el2_lib.scala 244:23] - wire _T_686 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[el2_lib.scala 244:36] - wire _T_687 = _T_686 & _T_673; // @[el2_lib.scala 244:41] - wire _T_690 = io_trigger_pkt_any_2_tdata2[2] == dec_i0_match_data_2[2]; // @[el2_lib.scala 244:78] - wire _T_691 = _T_687 | _T_690; // @[el2_lib.scala 244:23] - wire _T_693 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[el2_lib.scala 244:36] - wire _T_694 = _T_693 & _T_673; // @[el2_lib.scala 244:41] - wire _T_697 = io_trigger_pkt_any_2_tdata2[3] == dec_i0_match_data_2[3]; // @[el2_lib.scala 244:78] - wire _T_698 = _T_694 | _T_697; // @[el2_lib.scala 244:23] - wire _T_700 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[el2_lib.scala 244:36] - wire _T_701 = _T_700 & _T_673; // @[el2_lib.scala 244:41] - wire _T_704 = io_trigger_pkt_any_2_tdata2[4] == dec_i0_match_data_2[4]; // @[el2_lib.scala 244:78] - wire _T_705 = _T_701 | _T_704; // @[el2_lib.scala 244:23] - wire _T_707 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[el2_lib.scala 244:36] - wire _T_708 = _T_707 & _T_673; // @[el2_lib.scala 244:41] - wire _T_711 = io_trigger_pkt_any_2_tdata2[5] == dec_i0_match_data_2[5]; // @[el2_lib.scala 244:78] - wire _T_712 = _T_708 | _T_711; // @[el2_lib.scala 244:23] - wire _T_714 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[el2_lib.scala 244:36] - wire _T_715 = _T_714 & _T_673; // @[el2_lib.scala 244:41] - wire _T_718 = io_trigger_pkt_any_2_tdata2[6] == dec_i0_match_data_2[6]; // @[el2_lib.scala 244:78] - wire _T_719 = _T_715 | _T_718; // @[el2_lib.scala 244:23] - wire _T_721 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[el2_lib.scala 244:36] - wire _T_722 = _T_721 & _T_673; // @[el2_lib.scala 244:41] - wire _T_725 = io_trigger_pkt_any_2_tdata2[7] == dec_i0_match_data_2[7]; // @[el2_lib.scala 244:78] - wire _T_726 = _T_722 | _T_725; // @[el2_lib.scala 244:23] - wire _T_728 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[el2_lib.scala 244:36] - wire _T_729 = _T_728 & _T_673; // @[el2_lib.scala 244:41] - wire _T_732 = io_trigger_pkt_any_2_tdata2[8] == dec_i0_match_data_2[8]; // @[el2_lib.scala 244:78] - wire _T_733 = _T_729 | _T_732; // @[el2_lib.scala 244:23] - wire _T_735 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[el2_lib.scala 244:36] - wire _T_736 = _T_735 & _T_673; // @[el2_lib.scala 244:41] - wire _T_739 = io_trigger_pkt_any_2_tdata2[9] == dec_i0_match_data_2[9]; // @[el2_lib.scala 244:78] - wire _T_740 = _T_736 | _T_739; // @[el2_lib.scala 244:23] - wire _T_742 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[el2_lib.scala 244:36] - wire _T_743 = _T_742 & _T_673; // @[el2_lib.scala 244:41] - wire _T_746 = io_trigger_pkt_any_2_tdata2[10] == dec_i0_match_data_2[10]; // @[el2_lib.scala 244:78] - wire _T_747 = _T_743 | _T_746; // @[el2_lib.scala 244:23] - wire _T_749 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[el2_lib.scala 244:36] - wire _T_750 = _T_749 & _T_673; // @[el2_lib.scala 244:41] - wire _T_753 = io_trigger_pkt_any_2_tdata2[11] == dec_i0_match_data_2[11]; // @[el2_lib.scala 244:78] - wire _T_754 = _T_750 | _T_753; // @[el2_lib.scala 244:23] - wire _T_756 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[el2_lib.scala 244:36] - wire _T_757 = _T_756 & _T_673; // @[el2_lib.scala 244:41] - wire _T_760 = io_trigger_pkt_any_2_tdata2[12] == dec_i0_match_data_2[12]; // @[el2_lib.scala 244:78] - wire _T_761 = _T_757 | _T_760; // @[el2_lib.scala 244:23] - wire _T_763 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[el2_lib.scala 244:36] - wire _T_764 = _T_763 & _T_673; // @[el2_lib.scala 244:41] - wire _T_767 = io_trigger_pkt_any_2_tdata2[13] == dec_i0_match_data_2[13]; // @[el2_lib.scala 244:78] - wire _T_768 = _T_764 | _T_767; // @[el2_lib.scala 244:23] - wire _T_770 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[el2_lib.scala 244:36] - wire _T_771 = _T_770 & _T_673; // @[el2_lib.scala 244:41] - wire _T_774 = io_trigger_pkt_any_2_tdata2[14] == dec_i0_match_data_2[14]; // @[el2_lib.scala 244:78] - wire _T_775 = _T_771 | _T_774; // @[el2_lib.scala 244:23] - wire _T_777 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[el2_lib.scala 244:36] - wire _T_778 = _T_777 & _T_673; // @[el2_lib.scala 244:41] - wire _T_781 = io_trigger_pkt_any_2_tdata2[15] == dec_i0_match_data_2[15]; // @[el2_lib.scala 244:78] - wire _T_782 = _T_778 | _T_781; // @[el2_lib.scala 244:23] - wire _T_784 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[el2_lib.scala 244:36] - wire _T_785 = _T_784 & _T_673; // @[el2_lib.scala 244:41] - wire _T_788 = io_trigger_pkt_any_2_tdata2[16] == dec_i0_match_data_2[16]; // @[el2_lib.scala 244:78] - wire _T_789 = _T_785 | _T_788; // @[el2_lib.scala 244:23] - wire _T_791 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[el2_lib.scala 244:36] - wire _T_792 = _T_791 & _T_673; // @[el2_lib.scala 244:41] - wire _T_795 = io_trigger_pkt_any_2_tdata2[17] == dec_i0_match_data_2[17]; // @[el2_lib.scala 244:78] - wire _T_796 = _T_792 | _T_795; // @[el2_lib.scala 244:23] - wire _T_798 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[el2_lib.scala 244:36] - wire _T_799 = _T_798 & _T_673; // @[el2_lib.scala 244:41] - wire _T_802 = io_trigger_pkt_any_2_tdata2[18] == dec_i0_match_data_2[18]; // @[el2_lib.scala 244:78] - wire _T_803 = _T_799 | _T_802; // @[el2_lib.scala 244:23] - wire _T_805 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[el2_lib.scala 244:36] - wire _T_806 = _T_805 & _T_673; // @[el2_lib.scala 244:41] - wire _T_809 = io_trigger_pkt_any_2_tdata2[19] == dec_i0_match_data_2[19]; // @[el2_lib.scala 244:78] - wire _T_810 = _T_806 | _T_809; // @[el2_lib.scala 244:23] - wire _T_812 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[el2_lib.scala 244:36] - wire _T_813 = _T_812 & _T_673; // @[el2_lib.scala 244:41] - wire _T_816 = io_trigger_pkt_any_2_tdata2[20] == dec_i0_match_data_2[20]; // @[el2_lib.scala 244:78] - wire _T_817 = _T_813 | _T_816; // @[el2_lib.scala 244:23] - wire _T_819 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[el2_lib.scala 244:36] - wire _T_820 = _T_819 & _T_673; // @[el2_lib.scala 244:41] - wire _T_823 = io_trigger_pkt_any_2_tdata2[21] == dec_i0_match_data_2[21]; // @[el2_lib.scala 244:78] - wire _T_824 = _T_820 | _T_823; // @[el2_lib.scala 244:23] - wire _T_826 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[el2_lib.scala 244:36] - wire _T_827 = _T_826 & _T_673; // @[el2_lib.scala 244:41] - wire _T_830 = io_trigger_pkt_any_2_tdata2[22] == dec_i0_match_data_2[22]; // @[el2_lib.scala 244:78] - wire _T_831 = _T_827 | _T_830; // @[el2_lib.scala 244:23] - wire _T_833 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[el2_lib.scala 244:36] - wire _T_834 = _T_833 & _T_673; // @[el2_lib.scala 244:41] - wire _T_837 = io_trigger_pkt_any_2_tdata2[23] == dec_i0_match_data_2[23]; // @[el2_lib.scala 244:78] - wire _T_838 = _T_834 | _T_837; // @[el2_lib.scala 244:23] - wire _T_840 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[el2_lib.scala 244:36] - wire _T_841 = _T_840 & _T_673; // @[el2_lib.scala 244:41] - wire _T_844 = io_trigger_pkt_any_2_tdata2[24] == dec_i0_match_data_2[24]; // @[el2_lib.scala 244:78] - wire _T_845 = _T_841 | _T_844; // @[el2_lib.scala 244:23] - wire _T_847 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[el2_lib.scala 244:36] - wire _T_848 = _T_847 & _T_673; // @[el2_lib.scala 244:41] - wire _T_851 = io_trigger_pkt_any_2_tdata2[25] == dec_i0_match_data_2[25]; // @[el2_lib.scala 244:78] - wire _T_852 = _T_848 | _T_851; // @[el2_lib.scala 244:23] - wire _T_854 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[el2_lib.scala 244:36] - wire _T_855 = _T_854 & _T_673; // @[el2_lib.scala 244:41] - wire _T_858 = io_trigger_pkt_any_2_tdata2[26] == dec_i0_match_data_2[26]; // @[el2_lib.scala 244:78] - wire _T_859 = _T_855 | _T_858; // @[el2_lib.scala 244:23] - wire _T_861 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[el2_lib.scala 244:36] - wire _T_862 = _T_861 & _T_673; // @[el2_lib.scala 244:41] - wire _T_865 = io_trigger_pkt_any_2_tdata2[27] == dec_i0_match_data_2[27]; // @[el2_lib.scala 244:78] - wire _T_866 = _T_862 | _T_865; // @[el2_lib.scala 244:23] - wire _T_868 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[el2_lib.scala 244:36] - wire _T_869 = _T_868 & _T_673; // @[el2_lib.scala 244:41] - wire _T_872 = io_trigger_pkt_any_2_tdata2[28] == dec_i0_match_data_2[28]; // @[el2_lib.scala 244:78] - wire _T_873 = _T_869 | _T_872; // @[el2_lib.scala 244:23] - wire _T_875 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[el2_lib.scala 244:36] - wire _T_876 = _T_875 & _T_673; // @[el2_lib.scala 244:41] - wire _T_879 = io_trigger_pkt_any_2_tdata2[29] == dec_i0_match_data_2[29]; // @[el2_lib.scala 244:78] - wire _T_880 = _T_876 | _T_879; // @[el2_lib.scala 244:23] - wire _T_882 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[el2_lib.scala 244:36] - wire _T_883 = _T_882 & _T_673; // @[el2_lib.scala 244:41] - wire _T_886 = io_trigger_pkt_any_2_tdata2[30] == dec_i0_match_data_2[30]; // @[el2_lib.scala 244:78] - wire _T_887 = _T_883 | _T_886; // @[el2_lib.scala 244:23] - wire _T_889 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[el2_lib.scala 244:36] - wire _T_890 = _T_889 & _T_673; // @[el2_lib.scala 244:41] - wire _T_893 = io_trigger_pkt_any_2_tdata2[31] == dec_i0_match_data_2[31]; // @[el2_lib.scala 244:78] - wire _T_894 = _T_890 | _T_893; // @[el2_lib.scala 244:23] - wire [7:0] _T_901 = {_T_726,_T_719,_T_712,_T_705,_T_698,_T_691,_T_684,_T_677}; // @[el2_lib.scala 245:14] - wire [15:0] _T_909 = {_T_782,_T_775,_T_768,_T_761,_T_754,_T_747,_T_740,_T_733,_T_901}; // @[el2_lib.scala 245:14] - wire [7:0] _T_916 = {_T_838,_T_831,_T_824,_T_817,_T_810,_T_803,_T_796,_T_789}; // @[el2_lib.scala 245:14] - wire [31:0] _T_925 = {_T_894,_T_887,_T_880,_T_873,_T_866,_T_859,_T_852,_T_845,_T_916,_T_909}; // @[el2_lib.scala 245:14] - wire _T_926 = &_T_925; // @[el2_lib.scala 245:25] + wire _T_671 = &io_trigger_pkt_any_2_tdata2; // @[lib.scala 101:45] + wire _T_672 = ~_T_671; // @[lib.scala 101:39] + wire _T_673 = io_trigger_pkt_any_2_match_pkt & _T_672; // @[lib.scala 101:37] + wire _T_676 = io_trigger_pkt_any_2_tdata2[0] == dec_i0_match_data_2[0]; // @[lib.scala 102:52] + wire _T_677 = _T_673 | _T_676; // @[lib.scala 102:41] + wire _T_679 = &io_trigger_pkt_any_2_tdata2[0]; // @[lib.scala 104:36] + wire _T_680 = _T_679 & _T_673; // @[lib.scala 104:41] + wire _T_683 = io_trigger_pkt_any_2_tdata2[1] == dec_i0_match_data_2[1]; // @[lib.scala 104:78] + wire _T_684 = _T_680 | _T_683; // @[lib.scala 104:23] + wire _T_686 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[lib.scala 104:36] + wire _T_687 = _T_686 & _T_673; // @[lib.scala 104:41] + wire _T_690 = io_trigger_pkt_any_2_tdata2[2] == dec_i0_match_data_2[2]; // @[lib.scala 104:78] + wire _T_691 = _T_687 | _T_690; // @[lib.scala 104:23] + wire _T_693 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[lib.scala 104:36] + wire _T_694 = _T_693 & _T_673; // @[lib.scala 104:41] + wire _T_697 = io_trigger_pkt_any_2_tdata2[3] == dec_i0_match_data_2[3]; // @[lib.scala 104:78] + wire _T_698 = _T_694 | _T_697; // @[lib.scala 104:23] + wire _T_700 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[lib.scala 104:36] + wire _T_701 = _T_700 & _T_673; // @[lib.scala 104:41] + wire _T_704 = io_trigger_pkt_any_2_tdata2[4] == dec_i0_match_data_2[4]; // @[lib.scala 104:78] + wire _T_705 = _T_701 | _T_704; // @[lib.scala 104:23] + wire _T_707 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[lib.scala 104:36] + wire _T_708 = _T_707 & _T_673; // @[lib.scala 104:41] + wire _T_711 = io_trigger_pkt_any_2_tdata2[5] == dec_i0_match_data_2[5]; // @[lib.scala 104:78] + wire _T_712 = _T_708 | _T_711; // @[lib.scala 104:23] + wire _T_714 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[lib.scala 104:36] + wire _T_715 = _T_714 & _T_673; // @[lib.scala 104:41] + wire _T_718 = io_trigger_pkt_any_2_tdata2[6] == dec_i0_match_data_2[6]; // @[lib.scala 104:78] + wire _T_719 = _T_715 | _T_718; // @[lib.scala 104:23] + wire _T_721 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[lib.scala 104:36] + wire _T_722 = _T_721 & _T_673; // @[lib.scala 104:41] + wire _T_725 = io_trigger_pkt_any_2_tdata2[7] == dec_i0_match_data_2[7]; // @[lib.scala 104:78] + wire _T_726 = _T_722 | _T_725; // @[lib.scala 104:23] + wire _T_728 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[lib.scala 104:36] + wire _T_729 = _T_728 & _T_673; // @[lib.scala 104:41] + wire _T_732 = io_trigger_pkt_any_2_tdata2[8] == dec_i0_match_data_2[8]; // @[lib.scala 104:78] + wire _T_733 = _T_729 | _T_732; // @[lib.scala 104:23] + wire _T_735 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[lib.scala 104:36] + wire _T_736 = _T_735 & _T_673; // @[lib.scala 104:41] + wire _T_739 = io_trigger_pkt_any_2_tdata2[9] == dec_i0_match_data_2[9]; // @[lib.scala 104:78] + wire _T_740 = _T_736 | _T_739; // @[lib.scala 104:23] + wire _T_742 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[lib.scala 104:36] + wire _T_743 = _T_742 & _T_673; // @[lib.scala 104:41] + wire _T_746 = io_trigger_pkt_any_2_tdata2[10] == dec_i0_match_data_2[10]; // @[lib.scala 104:78] + wire _T_747 = _T_743 | _T_746; // @[lib.scala 104:23] + wire _T_749 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[lib.scala 104:36] + wire _T_750 = _T_749 & _T_673; // @[lib.scala 104:41] + wire _T_753 = io_trigger_pkt_any_2_tdata2[11] == dec_i0_match_data_2[11]; // @[lib.scala 104:78] + wire _T_754 = _T_750 | _T_753; // @[lib.scala 104:23] + wire _T_756 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[lib.scala 104:36] + wire _T_757 = _T_756 & _T_673; // @[lib.scala 104:41] + wire _T_760 = io_trigger_pkt_any_2_tdata2[12] == dec_i0_match_data_2[12]; // @[lib.scala 104:78] + wire _T_761 = _T_757 | _T_760; // @[lib.scala 104:23] + wire _T_763 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[lib.scala 104:36] + wire _T_764 = _T_763 & _T_673; // @[lib.scala 104:41] + wire _T_767 = io_trigger_pkt_any_2_tdata2[13] == dec_i0_match_data_2[13]; // @[lib.scala 104:78] + wire _T_768 = _T_764 | _T_767; // @[lib.scala 104:23] + wire _T_770 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[lib.scala 104:36] + wire _T_771 = _T_770 & _T_673; // @[lib.scala 104:41] + wire _T_774 = io_trigger_pkt_any_2_tdata2[14] == dec_i0_match_data_2[14]; // @[lib.scala 104:78] + wire _T_775 = _T_771 | _T_774; // @[lib.scala 104:23] + wire _T_777 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[lib.scala 104:36] + wire _T_778 = _T_777 & _T_673; // @[lib.scala 104:41] + wire _T_781 = io_trigger_pkt_any_2_tdata2[15] == dec_i0_match_data_2[15]; // @[lib.scala 104:78] + wire _T_782 = _T_778 | _T_781; // @[lib.scala 104:23] + wire _T_784 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[lib.scala 104:36] + wire _T_785 = _T_784 & _T_673; // @[lib.scala 104:41] + wire _T_788 = io_trigger_pkt_any_2_tdata2[16] == dec_i0_match_data_2[16]; // @[lib.scala 104:78] + wire _T_789 = _T_785 | _T_788; // @[lib.scala 104:23] + wire _T_791 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[lib.scala 104:36] + wire _T_792 = _T_791 & _T_673; // @[lib.scala 104:41] + wire _T_795 = io_trigger_pkt_any_2_tdata2[17] == dec_i0_match_data_2[17]; // @[lib.scala 104:78] + wire _T_796 = _T_792 | _T_795; // @[lib.scala 104:23] + wire _T_798 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[lib.scala 104:36] + wire _T_799 = _T_798 & _T_673; // @[lib.scala 104:41] + wire _T_802 = io_trigger_pkt_any_2_tdata2[18] == dec_i0_match_data_2[18]; // @[lib.scala 104:78] + wire _T_803 = _T_799 | _T_802; // @[lib.scala 104:23] + wire _T_805 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[lib.scala 104:36] + wire _T_806 = _T_805 & _T_673; // @[lib.scala 104:41] + wire _T_809 = io_trigger_pkt_any_2_tdata2[19] == dec_i0_match_data_2[19]; // @[lib.scala 104:78] + wire _T_810 = _T_806 | _T_809; // @[lib.scala 104:23] + wire _T_812 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[lib.scala 104:36] + wire _T_813 = _T_812 & _T_673; // @[lib.scala 104:41] + wire _T_816 = io_trigger_pkt_any_2_tdata2[20] == dec_i0_match_data_2[20]; // @[lib.scala 104:78] + wire _T_817 = _T_813 | _T_816; // @[lib.scala 104:23] + wire _T_819 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[lib.scala 104:36] + wire _T_820 = _T_819 & _T_673; // @[lib.scala 104:41] + wire _T_823 = io_trigger_pkt_any_2_tdata2[21] == dec_i0_match_data_2[21]; // @[lib.scala 104:78] + wire _T_824 = _T_820 | _T_823; // @[lib.scala 104:23] + wire _T_826 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[lib.scala 104:36] + wire _T_827 = _T_826 & _T_673; // @[lib.scala 104:41] + wire _T_830 = io_trigger_pkt_any_2_tdata2[22] == dec_i0_match_data_2[22]; // @[lib.scala 104:78] + wire _T_831 = _T_827 | _T_830; // @[lib.scala 104:23] + wire _T_833 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[lib.scala 104:36] + wire _T_834 = _T_833 & _T_673; // @[lib.scala 104:41] + wire _T_837 = io_trigger_pkt_any_2_tdata2[23] == dec_i0_match_data_2[23]; // @[lib.scala 104:78] + wire _T_838 = _T_834 | _T_837; // @[lib.scala 104:23] + wire _T_840 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[lib.scala 104:36] + wire _T_841 = _T_840 & _T_673; // @[lib.scala 104:41] + wire _T_844 = io_trigger_pkt_any_2_tdata2[24] == dec_i0_match_data_2[24]; // @[lib.scala 104:78] + wire _T_845 = _T_841 | _T_844; // @[lib.scala 104:23] + wire _T_847 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[lib.scala 104:36] + wire _T_848 = _T_847 & _T_673; // @[lib.scala 104:41] + wire _T_851 = io_trigger_pkt_any_2_tdata2[25] == dec_i0_match_data_2[25]; // @[lib.scala 104:78] + wire _T_852 = _T_848 | _T_851; // @[lib.scala 104:23] + wire _T_854 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[lib.scala 104:36] + wire _T_855 = _T_854 & _T_673; // @[lib.scala 104:41] + wire _T_858 = io_trigger_pkt_any_2_tdata2[26] == dec_i0_match_data_2[26]; // @[lib.scala 104:78] + wire _T_859 = _T_855 | _T_858; // @[lib.scala 104:23] + wire _T_861 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[lib.scala 104:36] + wire _T_862 = _T_861 & _T_673; // @[lib.scala 104:41] + wire _T_865 = io_trigger_pkt_any_2_tdata2[27] == dec_i0_match_data_2[27]; // @[lib.scala 104:78] + wire _T_866 = _T_862 | _T_865; // @[lib.scala 104:23] + wire _T_868 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[lib.scala 104:36] + wire _T_869 = _T_868 & _T_673; // @[lib.scala 104:41] + wire _T_872 = io_trigger_pkt_any_2_tdata2[28] == dec_i0_match_data_2[28]; // @[lib.scala 104:78] + wire _T_873 = _T_869 | _T_872; // @[lib.scala 104:23] + wire _T_875 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[lib.scala 104:36] + wire _T_876 = _T_875 & _T_673; // @[lib.scala 104:41] + wire _T_879 = io_trigger_pkt_any_2_tdata2[29] == dec_i0_match_data_2[29]; // @[lib.scala 104:78] + wire _T_880 = _T_876 | _T_879; // @[lib.scala 104:23] + wire _T_882 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[lib.scala 104:36] + wire _T_883 = _T_882 & _T_673; // @[lib.scala 104:41] + wire _T_886 = io_trigger_pkt_any_2_tdata2[30] == dec_i0_match_data_2[30]; // @[lib.scala 104:78] + wire _T_887 = _T_883 | _T_886; // @[lib.scala 104:23] + wire _T_889 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[lib.scala 104:36] + wire _T_890 = _T_889 & _T_673; // @[lib.scala 104:41] + wire _T_893 = io_trigger_pkt_any_2_tdata2[31] == dec_i0_match_data_2[31]; // @[lib.scala 104:78] + wire _T_894 = _T_890 | _T_893; // @[lib.scala 104:23] + wire [7:0] _T_901 = {_T_726,_T_719,_T_712,_T_705,_T_698,_T_691,_T_684,_T_677}; // @[lib.scala 105:14] + wire [15:0] _T_909 = {_T_782,_T_775,_T_768,_T_761,_T_754,_T_747,_T_740,_T_733,_T_901}; // @[lib.scala 105:14] + wire [7:0] _T_916 = {_T_838,_T_831,_T_824,_T_817,_T_810,_T_803,_T_796,_T_789}; // @[lib.scala 105:14] + wire [31:0] _T_925 = {_T_894,_T_887,_T_880,_T_873,_T_866,_T_859,_T_852,_T_845,_T_916,_T_909}; // @[lib.scala 105:14] + wire _T_926 = &_T_925; // @[lib.scala 105:25] wire _T_927 = _T_668 & _T_926; // @[dec_trigger.scala 15:109] wire _T_928 = io_trigger_pkt_any_3_execute & io_trigger_pkt_any_3_m; // @[dec_trigger.scala 15:83] - wire _T_931 = &io_trigger_pkt_any_3_tdata2; // @[el2_lib.scala 241:45] - wire _T_932 = ~_T_931; // @[el2_lib.scala 241:39] - wire _T_933 = io_trigger_pkt_any_3_match_pkt & _T_932; // @[el2_lib.scala 241:37] - wire _T_936 = io_trigger_pkt_any_3_tdata2[0] == dec_i0_match_data_3[0]; // @[el2_lib.scala 242:52] - wire _T_937 = _T_933 | _T_936; // @[el2_lib.scala 242:41] - wire _T_939 = &io_trigger_pkt_any_3_tdata2[0]; // @[el2_lib.scala 244:36] - wire _T_940 = _T_939 & _T_933; // @[el2_lib.scala 244:41] - wire _T_943 = io_trigger_pkt_any_3_tdata2[1] == dec_i0_match_data_3[1]; // @[el2_lib.scala 244:78] - wire _T_944 = _T_940 | _T_943; // @[el2_lib.scala 244:23] - wire _T_946 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[el2_lib.scala 244:36] - wire _T_947 = _T_946 & _T_933; // @[el2_lib.scala 244:41] - wire _T_950 = io_trigger_pkt_any_3_tdata2[2] == dec_i0_match_data_3[2]; // @[el2_lib.scala 244:78] - wire _T_951 = _T_947 | _T_950; // @[el2_lib.scala 244:23] - wire _T_953 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[el2_lib.scala 244:36] - wire _T_954 = _T_953 & _T_933; // @[el2_lib.scala 244:41] - wire _T_957 = io_trigger_pkt_any_3_tdata2[3] == dec_i0_match_data_3[3]; // @[el2_lib.scala 244:78] - wire _T_958 = _T_954 | _T_957; // @[el2_lib.scala 244:23] - wire _T_960 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[el2_lib.scala 244:36] - wire _T_961 = _T_960 & _T_933; // @[el2_lib.scala 244:41] - wire _T_964 = io_trigger_pkt_any_3_tdata2[4] == dec_i0_match_data_3[4]; // @[el2_lib.scala 244:78] - wire _T_965 = _T_961 | _T_964; // @[el2_lib.scala 244:23] - wire _T_967 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[el2_lib.scala 244:36] - wire _T_968 = _T_967 & _T_933; // @[el2_lib.scala 244:41] - wire _T_971 = io_trigger_pkt_any_3_tdata2[5] == dec_i0_match_data_3[5]; // @[el2_lib.scala 244:78] - wire _T_972 = _T_968 | _T_971; // @[el2_lib.scala 244:23] - wire _T_974 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[el2_lib.scala 244:36] - wire _T_975 = _T_974 & _T_933; // @[el2_lib.scala 244:41] - wire _T_978 = io_trigger_pkt_any_3_tdata2[6] == dec_i0_match_data_3[6]; // @[el2_lib.scala 244:78] - wire _T_979 = _T_975 | _T_978; // @[el2_lib.scala 244:23] - wire _T_981 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[el2_lib.scala 244:36] - wire _T_982 = _T_981 & _T_933; // @[el2_lib.scala 244:41] - wire _T_985 = io_trigger_pkt_any_3_tdata2[7] == dec_i0_match_data_3[7]; // @[el2_lib.scala 244:78] - wire _T_986 = _T_982 | _T_985; // @[el2_lib.scala 244:23] - wire _T_988 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[el2_lib.scala 244:36] - wire _T_989 = _T_988 & _T_933; // @[el2_lib.scala 244:41] - wire _T_992 = io_trigger_pkt_any_3_tdata2[8] == dec_i0_match_data_3[8]; // @[el2_lib.scala 244:78] - wire _T_993 = _T_989 | _T_992; // @[el2_lib.scala 244:23] - wire _T_995 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[el2_lib.scala 244:36] - wire _T_996 = _T_995 & _T_933; // @[el2_lib.scala 244:41] - wire _T_999 = io_trigger_pkt_any_3_tdata2[9] == dec_i0_match_data_3[9]; // @[el2_lib.scala 244:78] - wire _T_1000 = _T_996 | _T_999; // @[el2_lib.scala 244:23] - wire _T_1002 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[el2_lib.scala 244:36] - wire _T_1003 = _T_1002 & _T_933; // @[el2_lib.scala 244:41] - wire _T_1006 = io_trigger_pkt_any_3_tdata2[10] == dec_i0_match_data_3[10]; // @[el2_lib.scala 244:78] - wire _T_1007 = _T_1003 | _T_1006; // @[el2_lib.scala 244:23] - wire _T_1009 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[el2_lib.scala 244:36] - wire _T_1010 = _T_1009 & _T_933; // @[el2_lib.scala 244:41] - wire _T_1013 = io_trigger_pkt_any_3_tdata2[11] == dec_i0_match_data_3[11]; // @[el2_lib.scala 244:78] - wire _T_1014 = _T_1010 | _T_1013; // @[el2_lib.scala 244:23] - wire _T_1016 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[el2_lib.scala 244:36] - wire _T_1017 = _T_1016 & _T_933; // @[el2_lib.scala 244:41] - wire _T_1020 = io_trigger_pkt_any_3_tdata2[12] == dec_i0_match_data_3[12]; // @[el2_lib.scala 244:78] - wire _T_1021 = _T_1017 | _T_1020; // @[el2_lib.scala 244:23] - wire _T_1023 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[el2_lib.scala 244:36] - wire _T_1024 = _T_1023 & _T_933; // @[el2_lib.scala 244:41] - wire _T_1027 = io_trigger_pkt_any_3_tdata2[13] == dec_i0_match_data_3[13]; // @[el2_lib.scala 244:78] - wire _T_1028 = _T_1024 | _T_1027; // @[el2_lib.scala 244:23] - wire _T_1030 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[el2_lib.scala 244:36] - wire _T_1031 = _T_1030 & _T_933; // @[el2_lib.scala 244:41] - wire _T_1034 = io_trigger_pkt_any_3_tdata2[14] == dec_i0_match_data_3[14]; // @[el2_lib.scala 244:78] - wire _T_1035 = _T_1031 | _T_1034; // @[el2_lib.scala 244:23] - wire _T_1037 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[el2_lib.scala 244:36] - wire _T_1038 = _T_1037 & _T_933; // @[el2_lib.scala 244:41] - wire _T_1041 = io_trigger_pkt_any_3_tdata2[15] == dec_i0_match_data_3[15]; // @[el2_lib.scala 244:78] - wire _T_1042 = _T_1038 | _T_1041; // @[el2_lib.scala 244:23] - wire _T_1044 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[el2_lib.scala 244:36] - wire _T_1045 = _T_1044 & _T_933; // @[el2_lib.scala 244:41] - wire _T_1048 = io_trigger_pkt_any_3_tdata2[16] == dec_i0_match_data_3[16]; // @[el2_lib.scala 244:78] - wire _T_1049 = _T_1045 | _T_1048; // @[el2_lib.scala 244:23] - wire _T_1051 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[el2_lib.scala 244:36] - wire _T_1052 = _T_1051 & _T_933; // @[el2_lib.scala 244:41] - wire _T_1055 = io_trigger_pkt_any_3_tdata2[17] == dec_i0_match_data_3[17]; // @[el2_lib.scala 244:78] - wire _T_1056 = _T_1052 | _T_1055; // @[el2_lib.scala 244:23] - wire _T_1058 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[el2_lib.scala 244:36] - wire _T_1059 = _T_1058 & _T_933; // @[el2_lib.scala 244:41] - wire _T_1062 = io_trigger_pkt_any_3_tdata2[18] == dec_i0_match_data_3[18]; // @[el2_lib.scala 244:78] - wire _T_1063 = _T_1059 | _T_1062; // @[el2_lib.scala 244:23] - wire _T_1065 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[el2_lib.scala 244:36] - wire _T_1066 = _T_1065 & _T_933; // @[el2_lib.scala 244:41] - wire _T_1069 = io_trigger_pkt_any_3_tdata2[19] == dec_i0_match_data_3[19]; // @[el2_lib.scala 244:78] - wire _T_1070 = _T_1066 | _T_1069; // @[el2_lib.scala 244:23] - wire _T_1072 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[el2_lib.scala 244:36] - wire _T_1073 = _T_1072 & _T_933; // @[el2_lib.scala 244:41] - wire _T_1076 = io_trigger_pkt_any_3_tdata2[20] == dec_i0_match_data_3[20]; // @[el2_lib.scala 244:78] - wire _T_1077 = _T_1073 | _T_1076; // @[el2_lib.scala 244:23] - wire _T_1079 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[el2_lib.scala 244:36] - wire _T_1080 = _T_1079 & _T_933; // @[el2_lib.scala 244:41] - wire _T_1083 = io_trigger_pkt_any_3_tdata2[21] == dec_i0_match_data_3[21]; // @[el2_lib.scala 244:78] - wire _T_1084 = _T_1080 | _T_1083; // @[el2_lib.scala 244:23] - wire _T_1086 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[el2_lib.scala 244:36] - wire _T_1087 = _T_1086 & _T_933; // @[el2_lib.scala 244:41] - wire _T_1090 = io_trigger_pkt_any_3_tdata2[22] == dec_i0_match_data_3[22]; // @[el2_lib.scala 244:78] - wire _T_1091 = _T_1087 | _T_1090; // @[el2_lib.scala 244:23] - wire _T_1093 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[el2_lib.scala 244:36] - wire _T_1094 = _T_1093 & _T_933; // @[el2_lib.scala 244:41] - wire _T_1097 = io_trigger_pkt_any_3_tdata2[23] == dec_i0_match_data_3[23]; // @[el2_lib.scala 244:78] - wire _T_1098 = _T_1094 | _T_1097; // @[el2_lib.scala 244:23] - wire _T_1100 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[el2_lib.scala 244:36] - wire _T_1101 = _T_1100 & _T_933; // @[el2_lib.scala 244:41] - wire _T_1104 = io_trigger_pkt_any_3_tdata2[24] == dec_i0_match_data_3[24]; // @[el2_lib.scala 244:78] - wire _T_1105 = _T_1101 | _T_1104; // @[el2_lib.scala 244:23] - wire _T_1107 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[el2_lib.scala 244:36] - wire _T_1108 = _T_1107 & _T_933; // @[el2_lib.scala 244:41] - wire _T_1111 = io_trigger_pkt_any_3_tdata2[25] == dec_i0_match_data_3[25]; // @[el2_lib.scala 244:78] - wire _T_1112 = _T_1108 | _T_1111; // @[el2_lib.scala 244:23] - wire _T_1114 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[el2_lib.scala 244:36] - wire _T_1115 = _T_1114 & _T_933; // @[el2_lib.scala 244:41] - wire _T_1118 = io_trigger_pkt_any_3_tdata2[26] == dec_i0_match_data_3[26]; // @[el2_lib.scala 244:78] - wire _T_1119 = _T_1115 | _T_1118; // @[el2_lib.scala 244:23] - wire _T_1121 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[el2_lib.scala 244:36] - wire _T_1122 = _T_1121 & _T_933; // @[el2_lib.scala 244:41] - wire _T_1125 = io_trigger_pkt_any_3_tdata2[27] == dec_i0_match_data_3[27]; // @[el2_lib.scala 244:78] - wire _T_1126 = _T_1122 | _T_1125; // @[el2_lib.scala 244:23] - wire _T_1128 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[el2_lib.scala 244:36] - wire _T_1129 = _T_1128 & _T_933; // @[el2_lib.scala 244:41] - wire _T_1132 = io_trigger_pkt_any_3_tdata2[28] == dec_i0_match_data_3[28]; // @[el2_lib.scala 244:78] - wire _T_1133 = _T_1129 | _T_1132; // @[el2_lib.scala 244:23] - wire _T_1135 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[el2_lib.scala 244:36] - wire _T_1136 = _T_1135 & _T_933; // @[el2_lib.scala 244:41] - wire _T_1139 = io_trigger_pkt_any_3_tdata2[29] == dec_i0_match_data_3[29]; // @[el2_lib.scala 244:78] - wire _T_1140 = _T_1136 | _T_1139; // @[el2_lib.scala 244:23] - wire _T_1142 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[el2_lib.scala 244:36] - wire _T_1143 = _T_1142 & _T_933; // @[el2_lib.scala 244:41] - wire _T_1146 = io_trigger_pkt_any_3_tdata2[30] == dec_i0_match_data_3[30]; // @[el2_lib.scala 244:78] - wire _T_1147 = _T_1143 | _T_1146; // @[el2_lib.scala 244:23] - wire _T_1149 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[el2_lib.scala 244:36] - wire _T_1150 = _T_1149 & _T_933; // @[el2_lib.scala 244:41] - wire _T_1153 = io_trigger_pkt_any_3_tdata2[31] == dec_i0_match_data_3[31]; // @[el2_lib.scala 244:78] - wire _T_1154 = _T_1150 | _T_1153; // @[el2_lib.scala 244:23] - wire [7:0] _T_1161 = {_T_986,_T_979,_T_972,_T_965,_T_958,_T_951,_T_944,_T_937}; // @[el2_lib.scala 245:14] - wire [15:0] _T_1169 = {_T_1042,_T_1035,_T_1028,_T_1021,_T_1014,_T_1007,_T_1000,_T_993,_T_1161}; // @[el2_lib.scala 245:14] - wire [7:0] _T_1176 = {_T_1098,_T_1091,_T_1084,_T_1077,_T_1070,_T_1063,_T_1056,_T_1049}; // @[el2_lib.scala 245:14] - wire [31:0] _T_1185 = {_T_1154,_T_1147,_T_1140,_T_1133,_T_1126,_T_1119,_T_1112,_T_1105,_T_1176,_T_1169}; // @[el2_lib.scala 245:14] - wire _T_1186 = &_T_1185; // @[el2_lib.scala 245:25] + wire _T_931 = &io_trigger_pkt_any_3_tdata2; // @[lib.scala 101:45] + wire _T_932 = ~_T_931; // @[lib.scala 101:39] + wire _T_933 = io_trigger_pkt_any_3_match_pkt & _T_932; // @[lib.scala 101:37] + wire _T_936 = io_trigger_pkt_any_3_tdata2[0] == dec_i0_match_data_3[0]; // @[lib.scala 102:52] + wire _T_937 = _T_933 | _T_936; // @[lib.scala 102:41] + wire _T_939 = &io_trigger_pkt_any_3_tdata2[0]; // @[lib.scala 104:36] + wire _T_940 = _T_939 & _T_933; // @[lib.scala 104:41] + wire _T_943 = io_trigger_pkt_any_3_tdata2[1] == dec_i0_match_data_3[1]; // @[lib.scala 104:78] + wire _T_944 = _T_940 | _T_943; // @[lib.scala 104:23] + wire _T_946 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[lib.scala 104:36] + wire _T_947 = _T_946 & _T_933; // @[lib.scala 104:41] + wire _T_950 = io_trigger_pkt_any_3_tdata2[2] == dec_i0_match_data_3[2]; // @[lib.scala 104:78] + wire _T_951 = _T_947 | _T_950; // @[lib.scala 104:23] + wire _T_953 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[lib.scala 104:36] + wire _T_954 = _T_953 & _T_933; // @[lib.scala 104:41] + wire _T_957 = io_trigger_pkt_any_3_tdata2[3] == dec_i0_match_data_3[3]; // @[lib.scala 104:78] + wire _T_958 = _T_954 | _T_957; // @[lib.scala 104:23] + wire _T_960 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[lib.scala 104:36] + wire _T_961 = _T_960 & _T_933; // @[lib.scala 104:41] + wire _T_964 = io_trigger_pkt_any_3_tdata2[4] == dec_i0_match_data_3[4]; // @[lib.scala 104:78] + wire _T_965 = _T_961 | _T_964; // @[lib.scala 104:23] + wire _T_967 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[lib.scala 104:36] + wire _T_968 = _T_967 & _T_933; // @[lib.scala 104:41] + wire _T_971 = io_trigger_pkt_any_3_tdata2[5] == dec_i0_match_data_3[5]; // @[lib.scala 104:78] + wire _T_972 = _T_968 | _T_971; // @[lib.scala 104:23] + wire _T_974 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[lib.scala 104:36] + wire _T_975 = _T_974 & _T_933; // @[lib.scala 104:41] + wire _T_978 = io_trigger_pkt_any_3_tdata2[6] == dec_i0_match_data_3[6]; // @[lib.scala 104:78] + wire _T_979 = _T_975 | _T_978; // @[lib.scala 104:23] + wire _T_981 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[lib.scala 104:36] + wire _T_982 = _T_981 & _T_933; // @[lib.scala 104:41] + wire _T_985 = io_trigger_pkt_any_3_tdata2[7] == dec_i0_match_data_3[7]; // @[lib.scala 104:78] + wire _T_986 = _T_982 | _T_985; // @[lib.scala 104:23] + wire _T_988 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[lib.scala 104:36] + wire _T_989 = _T_988 & _T_933; // @[lib.scala 104:41] + wire _T_992 = io_trigger_pkt_any_3_tdata2[8] == dec_i0_match_data_3[8]; // @[lib.scala 104:78] + wire _T_993 = _T_989 | _T_992; // @[lib.scala 104:23] + wire _T_995 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[lib.scala 104:36] + wire _T_996 = _T_995 & _T_933; // @[lib.scala 104:41] + wire _T_999 = io_trigger_pkt_any_3_tdata2[9] == dec_i0_match_data_3[9]; // @[lib.scala 104:78] + wire _T_1000 = _T_996 | _T_999; // @[lib.scala 104:23] + wire _T_1002 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[lib.scala 104:36] + wire _T_1003 = _T_1002 & _T_933; // @[lib.scala 104:41] + wire _T_1006 = io_trigger_pkt_any_3_tdata2[10] == dec_i0_match_data_3[10]; // @[lib.scala 104:78] + wire _T_1007 = _T_1003 | _T_1006; // @[lib.scala 104:23] + wire _T_1009 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[lib.scala 104:36] + wire _T_1010 = _T_1009 & _T_933; // @[lib.scala 104:41] + wire _T_1013 = io_trigger_pkt_any_3_tdata2[11] == dec_i0_match_data_3[11]; // @[lib.scala 104:78] + wire _T_1014 = _T_1010 | _T_1013; // @[lib.scala 104:23] + wire _T_1016 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[lib.scala 104:36] + wire _T_1017 = _T_1016 & _T_933; // @[lib.scala 104:41] + wire _T_1020 = io_trigger_pkt_any_3_tdata2[12] == dec_i0_match_data_3[12]; // @[lib.scala 104:78] + wire _T_1021 = _T_1017 | _T_1020; // @[lib.scala 104:23] + wire _T_1023 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[lib.scala 104:36] + wire _T_1024 = _T_1023 & _T_933; // @[lib.scala 104:41] + wire _T_1027 = io_trigger_pkt_any_3_tdata2[13] == dec_i0_match_data_3[13]; // @[lib.scala 104:78] + wire _T_1028 = _T_1024 | _T_1027; // @[lib.scala 104:23] + wire _T_1030 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[lib.scala 104:36] + wire _T_1031 = _T_1030 & _T_933; // @[lib.scala 104:41] + wire _T_1034 = io_trigger_pkt_any_3_tdata2[14] == dec_i0_match_data_3[14]; // @[lib.scala 104:78] + wire _T_1035 = _T_1031 | _T_1034; // @[lib.scala 104:23] + wire _T_1037 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[lib.scala 104:36] + wire _T_1038 = _T_1037 & _T_933; // @[lib.scala 104:41] + wire _T_1041 = io_trigger_pkt_any_3_tdata2[15] == dec_i0_match_data_3[15]; // @[lib.scala 104:78] + wire _T_1042 = _T_1038 | _T_1041; // @[lib.scala 104:23] + wire _T_1044 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[lib.scala 104:36] + wire _T_1045 = _T_1044 & _T_933; // @[lib.scala 104:41] + wire _T_1048 = io_trigger_pkt_any_3_tdata2[16] == dec_i0_match_data_3[16]; // @[lib.scala 104:78] + wire _T_1049 = _T_1045 | _T_1048; // @[lib.scala 104:23] + wire _T_1051 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[lib.scala 104:36] + wire _T_1052 = _T_1051 & _T_933; // @[lib.scala 104:41] + wire _T_1055 = io_trigger_pkt_any_3_tdata2[17] == dec_i0_match_data_3[17]; // @[lib.scala 104:78] + wire _T_1056 = _T_1052 | _T_1055; // @[lib.scala 104:23] + wire _T_1058 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[lib.scala 104:36] + wire _T_1059 = _T_1058 & _T_933; // @[lib.scala 104:41] + wire _T_1062 = io_trigger_pkt_any_3_tdata2[18] == dec_i0_match_data_3[18]; // @[lib.scala 104:78] + wire _T_1063 = _T_1059 | _T_1062; // @[lib.scala 104:23] + wire _T_1065 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[lib.scala 104:36] + wire _T_1066 = _T_1065 & _T_933; // @[lib.scala 104:41] + wire _T_1069 = io_trigger_pkt_any_3_tdata2[19] == dec_i0_match_data_3[19]; // @[lib.scala 104:78] + wire _T_1070 = _T_1066 | _T_1069; // @[lib.scala 104:23] + wire _T_1072 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[lib.scala 104:36] + wire _T_1073 = _T_1072 & _T_933; // @[lib.scala 104:41] + wire _T_1076 = io_trigger_pkt_any_3_tdata2[20] == dec_i0_match_data_3[20]; // @[lib.scala 104:78] + wire _T_1077 = _T_1073 | _T_1076; // @[lib.scala 104:23] + wire _T_1079 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[lib.scala 104:36] + wire _T_1080 = _T_1079 & _T_933; // @[lib.scala 104:41] + wire _T_1083 = io_trigger_pkt_any_3_tdata2[21] == dec_i0_match_data_3[21]; // @[lib.scala 104:78] + wire _T_1084 = _T_1080 | _T_1083; // @[lib.scala 104:23] + wire _T_1086 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[lib.scala 104:36] + wire _T_1087 = _T_1086 & _T_933; // @[lib.scala 104:41] + wire _T_1090 = io_trigger_pkt_any_3_tdata2[22] == dec_i0_match_data_3[22]; // @[lib.scala 104:78] + wire _T_1091 = _T_1087 | _T_1090; // @[lib.scala 104:23] + wire _T_1093 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[lib.scala 104:36] + wire _T_1094 = _T_1093 & _T_933; // @[lib.scala 104:41] + wire _T_1097 = io_trigger_pkt_any_3_tdata2[23] == dec_i0_match_data_3[23]; // @[lib.scala 104:78] + wire _T_1098 = _T_1094 | _T_1097; // @[lib.scala 104:23] + wire _T_1100 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[lib.scala 104:36] + wire _T_1101 = _T_1100 & _T_933; // @[lib.scala 104:41] + wire _T_1104 = io_trigger_pkt_any_3_tdata2[24] == dec_i0_match_data_3[24]; // @[lib.scala 104:78] + wire _T_1105 = _T_1101 | _T_1104; // @[lib.scala 104:23] + wire _T_1107 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[lib.scala 104:36] + wire _T_1108 = _T_1107 & _T_933; // @[lib.scala 104:41] + wire _T_1111 = io_trigger_pkt_any_3_tdata2[25] == dec_i0_match_data_3[25]; // @[lib.scala 104:78] + wire _T_1112 = _T_1108 | _T_1111; // @[lib.scala 104:23] + wire _T_1114 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[lib.scala 104:36] + wire _T_1115 = _T_1114 & _T_933; // @[lib.scala 104:41] + wire _T_1118 = io_trigger_pkt_any_3_tdata2[26] == dec_i0_match_data_3[26]; // @[lib.scala 104:78] + wire _T_1119 = _T_1115 | _T_1118; // @[lib.scala 104:23] + wire _T_1121 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[lib.scala 104:36] + wire _T_1122 = _T_1121 & _T_933; // @[lib.scala 104:41] + wire _T_1125 = io_trigger_pkt_any_3_tdata2[27] == dec_i0_match_data_3[27]; // @[lib.scala 104:78] + wire _T_1126 = _T_1122 | _T_1125; // @[lib.scala 104:23] + wire _T_1128 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[lib.scala 104:36] + wire _T_1129 = _T_1128 & _T_933; // @[lib.scala 104:41] + wire _T_1132 = io_trigger_pkt_any_3_tdata2[28] == dec_i0_match_data_3[28]; // @[lib.scala 104:78] + wire _T_1133 = _T_1129 | _T_1132; // @[lib.scala 104:23] + wire _T_1135 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[lib.scala 104:36] + wire _T_1136 = _T_1135 & _T_933; // @[lib.scala 104:41] + wire _T_1139 = io_trigger_pkt_any_3_tdata2[29] == dec_i0_match_data_3[29]; // @[lib.scala 104:78] + wire _T_1140 = _T_1136 | _T_1139; // @[lib.scala 104:23] + wire _T_1142 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[lib.scala 104:36] + wire _T_1143 = _T_1142 & _T_933; // @[lib.scala 104:41] + wire _T_1146 = io_trigger_pkt_any_3_tdata2[30] == dec_i0_match_data_3[30]; // @[lib.scala 104:78] + wire _T_1147 = _T_1143 | _T_1146; // @[lib.scala 104:23] + wire _T_1149 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[lib.scala 104:36] + wire _T_1150 = _T_1149 & _T_933; // @[lib.scala 104:41] + wire _T_1153 = io_trigger_pkt_any_3_tdata2[31] == dec_i0_match_data_3[31]; // @[lib.scala 104:78] + wire _T_1154 = _T_1150 | _T_1153; // @[lib.scala 104:23] + wire [7:0] _T_1161 = {_T_986,_T_979,_T_972,_T_965,_T_958,_T_951,_T_944,_T_937}; // @[lib.scala 105:14] + wire [15:0] _T_1169 = {_T_1042,_T_1035,_T_1028,_T_1021,_T_1014,_T_1007,_T_1000,_T_993,_T_1161}; // @[lib.scala 105:14] + wire [7:0] _T_1176 = {_T_1098,_T_1091,_T_1084,_T_1077,_T_1070,_T_1063,_T_1056,_T_1049}; // @[lib.scala 105:14] + wire [31:0] _T_1185 = {_T_1154,_T_1147,_T_1140,_T_1133,_T_1126,_T_1119,_T_1112,_T_1105,_T_1176,_T_1169}; // @[lib.scala 105:14] + wire _T_1186 = &_T_1185; // @[lib.scala 105:25] wire _T_1187 = _T_928 & _T_1186; // @[dec_trigger.scala 15:109] wire [2:0] _T_1189 = {_T_1187,_T_927,_T_667}; // @[Cat.scala 29:58] assign io_dec_i0_trigger_match_d = {_T_1189,_T_407}; // @[dec_trigger.scala 15:29] @@ -59467,14 +59463,14 @@ module dbg( wire _T_4 = io_dmi_reg_en | sb_state_en; // @[dbg.scala 96:37] wire _T_5 = sb_state != 4'h0; // @[dbg.scala 96:63] wire _T_6 = _T_4 | _T_5; // @[dbg.scala 96:51] - wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_1_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_1_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_io_en; // @[lib.scala 343:22] + wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_en; // @[lib.scala 343:22] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] wire _T_9 = dmcontrol_reg[0] | io_scan_mode; // @[dbg.scala 100:65] wire dbg_dm_rst_l = io_dbg_rst_l & _T_9; // @[dbg.scala 100:94] wire _T_11 = io_dbg_rst_l & _T_9; // @[dbg.scala 102:38] @@ -59539,16 +59535,16 @@ module dbg( wire [31:0] _T_99 = sbdata1_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_100 = _T_99 & io_dmi_reg_wdata; // @[dbg.scala 149:49] wire [31:0] _T_104 = _T_95 & sb_bus_rdata[63:32]; // @[dbg.scala 150:33] - wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23] - reg [31:0] sbdata0_reg; // @[el2_lib.scala 514:16] - wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23] - reg [31:0] sbdata1_reg; // @[el2_lib.scala 514:16] + wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_en; // @[lib.scala 368:23] + wire rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23] + reg [31:0] sbdata0_reg; // @[lib.scala 374:16] + wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_en; // @[lib.scala 368:23] + wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] + reg [31:0] sbdata1_reg; // @[lib.scala 374:16] wire sbaddress0_reg_wren0 = _T_81 & _T_25; // @[dbg.scala 160:63] wire [31:0] _T_108 = sbaddress0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_109 = _T_108 & io_dmi_reg_wdata; // @[dbg.scala 162:59] @@ -59556,11 +59552,11 @@ module dbg( wire [31:0] _T_112 = {28'h0,sbaddress0_incr}; // @[Cat.scala 29:58] wire [31:0] _T_114 = sbaddress0_reg + _T_112; // @[dbg.scala 163:54] wire [31:0] _T_115 = _T_111 & _T_114; // @[dbg.scala 163:36] - wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23] - reg [31:0] _T_116; // @[el2_lib.scala 514:16] + wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_en; // @[lib.scala 368:23] + wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] + reg [31:0] _T_116; // @[lib.scala 374:16] wire sbreadonaddr_access = sbaddress0_reg_wren0 & sbcs_reg[20]; // @[dbg.scala 168:94] wire _T_121 = ~io_dmi_reg_wr_en; // @[dbg.scala 169:45] wire _T_122 = io_dmi_reg_en & _T_121; // @[dbg.scala 169:43] @@ -59662,11 +59658,11 @@ module dbg( wire command_wren = _T_215 & _T_270; // @[dbg.scala 240:87] wire [19:0] _T_274 = {3'h0,io_dmi_reg_wdata[16:0]}; // @[Cat.scala 29:58] wire [11:0] _T_276 = {io_dmi_reg_wdata[31:24],1'h0,io_dmi_reg_wdata[22:20]}; // @[Cat.scala 29:58] - wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 508:23] - reg [31:0] command_reg; // @[el2_lib.scala 514:16] + wire rvclkhdr_5_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_en; // @[lib.scala 368:23] + wire rvclkhdr_5_io_scan_mode; // @[lib.scala 368:23] + reg [31:0] command_reg; // @[lib.scala 374:16] wire _T_279 = _T_81 & _T_197; // @[dbg.scala 246:58] wire data0_reg_wren0 = _T_279 & _T_270; // @[dbg.scala 246:89] wire _T_281 = dbg_state == 3'h4; // @[dbg.scala 247:59] @@ -59677,20 +59673,20 @@ module dbg( wire [31:0] _T_287 = _T_286 & io_dmi_reg_wdata; // @[dbg.scala 250:45] wire [31:0] _T_289 = data0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_290 = _T_289 & io_core_dbg_rddata; // @[dbg.scala 250:92] - wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 508:23] - reg [31:0] data0_reg; // @[el2_lib.scala 514:16] + wire rvclkhdr_6_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_6_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_6_io_en; // @[lib.scala 368:23] + wire rvclkhdr_6_io_scan_mode; // @[lib.scala 368:23] + reg [31:0] data0_reg; // @[lib.scala 374:16] wire _T_292 = io_dmi_reg_addr == 7'h5; // @[dbg.scala 255:77] wire _T_293 = _T_81 & _T_292; // @[dbg.scala 255:58] wire data1_reg_wren = _T_293 & _T_270; // @[dbg.scala 255:89] wire [31:0] _T_296 = data1_reg_wren ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 508:23] - reg [31:0] _T_297; // @[el2_lib.scala 514:16] + wire rvclkhdr_7_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_7_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_7_io_en; // @[lib.scala 368:23] + wire rvclkhdr_7_io_scan_mode; // @[lib.scala 368:23] + reg [31:0] _T_297; // @[lib.scala 374:16] wire [2:0] dbg_nxtstate; wire _T_298 = 3'h0 == dbg_state; // @[Conditional.scala 37:30] wire _T_300 = dmstatus_reg[9] | io_dec_tlu_mpc_halted_only; // @[dbg.scala 270:43] @@ -59889,49 +59885,49 @@ module dbg( wire [63:0] _T_668 = _T_589 & _T_667; // @[dbg.scala 448:45] wire [63:0] _T_669 = _T_658 | _T_668; // @[dbg.scala 447:129] wire [63:0] _T_675 = _T_597 & io_sb_axi_r_bits_data; // @[dbg.scala 449:45] - rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en), .io_scan_mode(rvclkhdr_io_scan_mode) ); - rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_1_io_l1clk), .io_clk(rvclkhdr_1_io_clk), .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_2_io_l1clk), .io_clk(rvclkhdr_2_io_clk), .io_en(rvclkhdr_2_io_en), .io_scan_mode(rvclkhdr_2_io_scan_mode) ); - rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_3_io_l1clk), .io_clk(rvclkhdr_3_io_clk), .io_en(rvclkhdr_3_io_en), .io_scan_mode(rvclkhdr_3_io_scan_mode) ); - rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_4_io_l1clk), .io_clk(rvclkhdr_4_io_clk), .io_en(rvclkhdr_4_io_en), .io_scan_mode(rvclkhdr_4_io_scan_mode) ); - rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_5 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_5_io_l1clk), .io_clk(rvclkhdr_5_io_clk), .io_en(rvclkhdr_5_io_en), .io_scan_mode(rvclkhdr_5_io_scan_mode) ); - rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_6 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_6_io_l1clk), .io_clk(rvclkhdr_6_io_clk), .io_en(rvclkhdr_6_io_en), .io_scan_mode(rvclkhdr_6_io_scan_mode) ); - rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_7 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_7_io_l1clk), .io_clk(rvclkhdr_7_io_clk), .io_en(rvclkhdr_7_io_en), @@ -59991,31 +59987,31 @@ module dbg( assign sbcs_sbbusy_din = 4'h0 == sb_state; // @[dbg.scala 341:19 dbg.scala 350:23 dbg.scala 398:23] assign data1_reg = _T_297; // @[dbg.scala 257:13] assign sbcs_reg = {_T_42,_T_38}; // @[dbg.scala 130:12] - assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_io_en = _T_3 | io_clk_override; // @[el2_lib.scala 485:16] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_1_io_en = _T_6 | io_clk_override; // @[el2_lib.scala 485:16] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_2_io_en = sbdata0_reg_wren0 | sbdata0_reg_wren1; // @[el2_lib.scala 511:17] - assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_3_io_en = sbdata1_reg_wren0 | sbdata0_reg_wren1; // @[el2_lib.scala 511:17] - assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_4_io_en = sbaddress0_reg_wren0 | sbaddress0_reg_wren1; // @[el2_lib.scala 511:17] - assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_io_en = _T_3 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_1_io_en = _T_6 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_2_io_en = sbdata0_reg_wren0 | sbdata0_reg_wren1; // @[lib.scala 371:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_3_io_en = sbdata1_reg_wren0 | sbdata0_reg_wren1; // @[lib.scala 371:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_4_io_en = sbaddress0_reg_wren0 | sbaddress0_reg_wren1; // @[lib.scala 371:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign abstractcs_reg = {_T_265,_T_263}; // @[dbg.scala 238:18] - assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_5_io_en = _T_215 & _T_270; // @[el2_lib.scala 511:17] - assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_6_io_en = data0_reg_wren0 | data0_reg_wren1; // @[el2_lib.scala 511:17] - assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_7_io_en = _T_293 & _T_270; // @[el2_lib.scala 511:17] - assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_5_io_en = _T_215 & _T_270; // @[lib.scala 371:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_6_io_en = data0_reg_wren0 | data0_reg_wren1; // @[lib.scala 371:17] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_7_io_en = _T_293 & _T_270; // @[lib.scala 371:17] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign dbg_nxtstate = _T_298 ? _T_301 : _GEN_33; // @[dbg.scala 262:16 dbg.scala 270:20 dbg.scala 275:20 dbg.scala 280:20 dbg.scala 291:20 dbg.scala 296:20 dbg.scala 301:20 dbg.scala 308:20] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE @@ -60498,16 +60494,16 @@ module exu_alu_ctl( reg [31:0] _RAND_0; reg [31:0] _RAND_1; `endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] - reg [30:0] _T_1; // @[el2_lib.scala 514:16] - reg [31:0] _T_3; // @[el2_lib.scala 514:16] + wire rvclkhdr_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_io_en; // @[lib.scala 368:23] + wire rvclkhdr_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_en; // @[lib.scala 368:23] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 368:23] + reg [30:0] _T_1; // @[lib.scala 374:16] + reg [31:0] _T_3; // @[lib.scala 374:16] wire [31:0] _T_5 = ~io_b_in; // @[exu_alu_ctl.scala 34:40] wire [31:0] bm = io_i0_ap_sub ? _T_5 : io_b_in; // @[exu_alu_ctl.scala 34:17] wire [32:0] _T_8 = {1'h0,io_a_in}; // @[Cat.scala 29:58] @@ -60586,14 +60582,14 @@ module exu_alu_ctl( wire slt_one = io_i0_ap_slt & lt; // @[exu_alu_ctl.scala 77:43] wire [31:0] _T_217 = {io_dec_i0_pc_d,1'h0}; // @[Cat.scala 29:58] wire [12:0] _T_218 = {io_dec_alu_dec_i0_br_immed_d,1'h0}; // @[Cat.scala 29:58] - wire [12:0] _T_221 = _T_217[12:1] + _T_218[12:1]; // @[el2_lib.scala 208:31] - wire [18:0] _T_224 = _T_217[31:13] + 19'h1; // @[el2_lib.scala 209:27] - wire [18:0] _T_227 = _T_217[31:13] - 19'h1; // @[el2_lib.scala 210:27] - wire _T_230 = ~_T_221[12]; // @[el2_lib.scala 212:28] - wire _T_231 = _T_218[12] ^ _T_230; // @[el2_lib.scala 212:26] - wire _T_234 = ~_T_218[12]; // @[el2_lib.scala 213:20] - wire _T_236 = _T_234 & _T_221[12]; // @[el2_lib.scala 213:26] - wire _T_240 = _T_218[12] & _T_230; // @[el2_lib.scala 214:26] + wire [12:0] _T_221 = _T_217[12:1] + _T_218[12:1]; // @[lib.scala 68:31] + wire [18:0] _T_224 = _T_217[31:13] + 19'h1; // @[lib.scala 69:27] + wire [18:0] _T_227 = _T_217[31:13] - 19'h1; // @[lib.scala 70:27] + wire _T_230 = ~_T_221[12]; // @[lib.scala 72:28] + wire _T_231 = _T_218[12] ^ _T_230; // @[lib.scala 72:26] + wire _T_234 = ~_T_218[12]; // @[lib.scala 73:20] + wire _T_236 = _T_234 & _T_221[12]; // @[lib.scala 73:26] + wire _T_240 = _T_218[12] & _T_230; // @[lib.scala 74:26] wire [18:0] _T_242 = _T_231 ? _T_217[31:13] : 19'h0; // @[Mux.scala 27:72] wire [18:0] _T_243 = _T_236 ? _T_224 : 19'h0; // @[Mux.scala 27:72] wire [18:0] _T_244 = _T_240 ? _T_227 : 19'h0; // @[Mux.scala 27:72] @@ -60648,13 +60644,13 @@ module exu_alu_ctl( wire _T_323 = _T_320 | _T_322; // @[exu_alu_ctl.scala 117:47] wire _T_327 = _T_300 & _T_302; // @[exu_alu_ctl.scala 120:56] wire _T_328 = cond_mispredict | target_mispredict; // @[exu_alu_ctl.scala 120:103] - rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en), .io_scan_mode(rvclkhdr_io_scan_mode) ); - rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_1 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_1_io_l1clk), .io_clk(rvclkhdr_1_io_clk), .io_en(rvclkhdr_1_io_en), @@ -60679,12 +60675,12 @@ module exu_alu_ctl( assign io_predict_p_out_bits_pret = io_pp_in_bits_pret; // @[exu_alu_ctl.scala 119:30] assign io_predict_p_out_bits_pja = io_pp_in_bits_pja; // @[exu_alu_ctl.scala 119:30] assign io_predict_p_out_bits_way = io_pp_in_bits_way; // @[exu_alu_ctl.scala 119:30] - assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_io_en = io_enable; // @[el2_lib.scala 511:17] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_1_io_en = io_enable; // @[el2_lib.scala 511:17] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_io_en = io_enable; // @[lib.scala 371:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_1_io_en = io_enable; // @[lib.scala 371:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -60769,55 +60765,55 @@ module exu_mul_ctl( reg [63:0] _RAND_1; reg [63:0] _RAND_2; `endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 528:23] - wire rvclkhdr_1_io_clk; // @[el2_lib.scala 528:23] - wire rvclkhdr_1_io_en; // @[el2_lib.scala 528:23] - wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 528:23] - wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 528:23] - wire rvclkhdr_2_io_clk; // @[el2_lib.scala 528:23] - wire rvclkhdr_2_io_en; // @[el2_lib.scala 528:23] - wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 528:23] + wire rvclkhdr_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_io_en; // @[lib.scala 368:23] + wire rvclkhdr_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 388:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 388:23] + wire rvclkhdr_1_io_en; // @[lib.scala 388:23] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 388:23] + wire rvclkhdr_2_io_l1clk; // @[lib.scala 388:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 388:23] + wire rvclkhdr_2_io_en; // @[lib.scala 388:23] + wire rvclkhdr_2_io_scan_mode; // @[lib.scala 388:23] wire _T_1 = io_mul_p_bits_rs1_sign & io_rs1_in[31]; // @[exu_mul_ctl.scala 26:44] wire _T_5 = io_mul_p_bits_rs2_sign & io_rs2_in[31]; // @[exu_mul_ctl.scala 27:44] - reg low_x; // @[el2_lib.scala 514:16] - reg [32:0] rs1_x; // @[el2_lib.scala 534:16] - reg [32:0] rs2_x; // @[el2_lib.scala 534:16] + reg low_x; // @[lib.scala 374:16] + reg [32:0] rs1_x; // @[lib.scala 394:16] + reg [32:0] rs2_x; // @[lib.scala 394:16] wire [65:0] prod_x = $signed(rs1_x) * $signed(rs2_x); // @[exu_mul_ctl.scala 33:20] wire _T_16 = ~low_x; // @[exu_mul_ctl.scala 34:29] wire [31:0] _T_20 = _T_16 ? prod_x[63:32] : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_21 = low_x ? prod_x[31:0] : 32'h0; // @[Mux.scala 27:72] - rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en), .io_scan_mode(rvclkhdr_io_scan_mode) ); - rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 528:23] + rvclkhdr rvclkhdr_1 ( // @[lib.scala 388:23] .io_l1clk(rvclkhdr_1_io_l1clk), .io_clk(rvclkhdr_1_io_clk), .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 528:23] + rvclkhdr rvclkhdr_2 ( // @[lib.scala 388:23] .io_l1clk(rvclkhdr_2_io_l1clk), .io_clk(rvclkhdr_2_io_clk), .io_en(rvclkhdr_2_io_en), .io_scan_mode(rvclkhdr_2_io_scan_mode) ); assign io_result_x = _T_20 | _T_21; // @[exu_mul_ctl.scala 34:15] - assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_io_en = io_mul_p_valid; // @[el2_lib.scala 511:17] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 530:18] - assign rvclkhdr_1_io_en = io_mul_p_valid; // @[el2_lib.scala 531:17] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 532:24] - assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 530:18] - assign rvclkhdr_2_io_en = io_mul_p_valid; // @[el2_lib.scala 531:17] - assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 532:24] + assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_io_en = io_mul_p_valid; // @[lib.scala 371:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 390:18] + assign rvclkhdr_1_io_en = io_mul_p_valid; // @[lib.scala 391:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 392:24] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 390:18] + assign rvclkhdr_2_io_en = io_mul_p_valid; // @[lib.scala 391:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 392:24] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -60927,28 +60923,28 @@ module exu_div_ctl( reg [31:0] _RAND_13; reg [31:0] _RAND_14; `endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_io_en; // @[lib.scala 343:22] + wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_en; // @[lib.scala 368:23] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_en; // @[lib.scala 368:23] + wire rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_en; // @[lib.scala 368:23] + wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] wire _T = ~io_dec_div_dec_div_cancel; // @[exu_div_ctl.scala 46:30] reg valid_ff_x; // @[exu_div_ctl.scala 195:26] wire valid_x = valid_ff_x & _T; // @[exu_div_ctl.scala 46:28] - reg [32:0] q_ff; // @[el2_lib.scala 514:16] + reg [32:0] q_ff; // @[lib.scala 374:16] wire _T_2 = q_ff[31:4] == 28'h0; // @[exu_div_ctl.scala 52:34] - reg [32:0] m_ff; // @[el2_lib.scala 514:16] + reg [32:0] m_ff; // @[lib.scala 374:16] wire _T_4 = m_ff[31:4] == 28'h0; // @[exu_div_ctl.scala 52:57] wire _T_5 = _T_2 & _T_4; // @[exu_div_ctl.scala 52:43] wire _T_7 = m_ff[31:0] != 32'h0; // @[exu_div_ctl.scala 52:80] @@ -61205,108 +61201,108 @@ module exu_div_ctl( wire _T_715 = run_state & _T_714; // @[exu_div_ctl.scala 162:16] reg dividend_neg_ff; // @[Reg.scala 27:20] wire _T_738 = sign_ff & dividend_neg_ff; // @[exu_div_ctl.scala 166:32] - wire _T_923 = |q_ff[30:0]; // @[el2_lib.scala 543:35] - wire _T_925 = ~q_ff[31]; // @[el2_lib.scala 543:40] - wire _T_927 = _T_923 ? _T_925 : q_ff[31]; // @[el2_lib.scala 543:23] - wire _T_917 = |q_ff[29:0]; // @[el2_lib.scala 543:35] - wire _T_919 = ~q_ff[30]; // @[el2_lib.scala 543:40] - wire _T_921 = _T_917 ? _T_919 : q_ff[30]; // @[el2_lib.scala 543:23] - wire _T_911 = |q_ff[28:0]; // @[el2_lib.scala 543:35] - wire _T_913 = ~q_ff[29]; // @[el2_lib.scala 543:40] - wire _T_915 = _T_911 ? _T_913 : q_ff[29]; // @[el2_lib.scala 543:23] - wire _T_905 = |q_ff[27:0]; // @[el2_lib.scala 543:35] - wire _T_907 = ~q_ff[28]; // @[el2_lib.scala 543:40] - wire _T_909 = _T_905 ? _T_907 : q_ff[28]; // @[el2_lib.scala 543:23] - wire _T_899 = |q_ff[26:0]; // @[el2_lib.scala 543:35] - wire _T_901 = ~q_ff[27]; // @[el2_lib.scala 543:40] - wire _T_903 = _T_899 ? _T_901 : q_ff[27]; // @[el2_lib.scala 543:23] - wire _T_893 = |q_ff[25:0]; // @[el2_lib.scala 543:35] - wire _T_895 = ~q_ff[26]; // @[el2_lib.scala 543:40] - wire _T_897 = _T_893 ? _T_895 : q_ff[26]; // @[el2_lib.scala 543:23] - wire _T_887 = |q_ff[24:0]; // @[el2_lib.scala 543:35] - wire _T_889 = ~q_ff[25]; // @[el2_lib.scala 543:40] - wire _T_891 = _T_887 ? _T_889 : q_ff[25]; // @[el2_lib.scala 543:23] - wire _T_881 = |q_ff[23:0]; // @[el2_lib.scala 543:35] - wire _T_883 = ~q_ff[24]; // @[el2_lib.scala 543:40] - wire _T_885 = _T_881 ? _T_883 : q_ff[24]; // @[el2_lib.scala 543:23] - wire _T_875 = |q_ff[22:0]; // @[el2_lib.scala 543:35] - wire _T_877 = ~q_ff[23]; // @[el2_lib.scala 543:40] - wire _T_879 = _T_875 ? _T_877 : q_ff[23]; // @[el2_lib.scala 543:23] - wire _T_869 = |q_ff[21:0]; // @[el2_lib.scala 543:35] - wire _T_871 = ~q_ff[22]; // @[el2_lib.scala 543:40] - wire _T_873 = _T_869 ? _T_871 : q_ff[22]; // @[el2_lib.scala 543:23] - wire _T_863 = |q_ff[20:0]; // @[el2_lib.scala 543:35] - wire _T_865 = ~q_ff[21]; // @[el2_lib.scala 543:40] - wire _T_867 = _T_863 ? _T_865 : q_ff[21]; // @[el2_lib.scala 543:23] - wire _T_857 = |q_ff[19:0]; // @[el2_lib.scala 543:35] - wire _T_859 = ~q_ff[20]; // @[el2_lib.scala 543:40] - wire _T_861 = _T_857 ? _T_859 : q_ff[20]; // @[el2_lib.scala 543:23] - wire _T_851 = |q_ff[18:0]; // @[el2_lib.scala 543:35] - wire _T_853 = ~q_ff[19]; // @[el2_lib.scala 543:40] - wire _T_855 = _T_851 ? _T_853 : q_ff[19]; // @[el2_lib.scala 543:23] - wire _T_845 = |q_ff[17:0]; // @[el2_lib.scala 543:35] - wire _T_847 = ~q_ff[18]; // @[el2_lib.scala 543:40] - wire _T_849 = _T_845 ? _T_847 : q_ff[18]; // @[el2_lib.scala 543:23] - wire _T_839 = |q_ff[16:0]; // @[el2_lib.scala 543:35] - wire _T_841 = ~q_ff[17]; // @[el2_lib.scala 543:40] - wire _T_843 = _T_839 ? _T_841 : q_ff[17]; // @[el2_lib.scala 543:23] - wire _T_833 = |q_ff[15:0]; // @[el2_lib.scala 543:35] - wire _T_835 = ~q_ff[16]; // @[el2_lib.scala 543:40] - wire _T_837 = _T_833 ? _T_835 : q_ff[16]; // @[el2_lib.scala 543:23] - wire [7:0] _T_948 = {_T_879,_T_873,_T_867,_T_861,_T_855,_T_849,_T_843,_T_837}; // @[el2_lib.scala 545:14] - wire _T_827 = |q_ff[14:0]; // @[el2_lib.scala 543:35] - wire _T_829 = ~q_ff[15]; // @[el2_lib.scala 543:40] - wire _T_831 = _T_827 ? _T_829 : q_ff[15]; // @[el2_lib.scala 543:23] - wire _T_821 = |q_ff[13:0]; // @[el2_lib.scala 543:35] - wire _T_823 = ~q_ff[14]; // @[el2_lib.scala 543:40] - wire _T_825 = _T_821 ? _T_823 : q_ff[14]; // @[el2_lib.scala 543:23] - wire _T_815 = |q_ff[12:0]; // @[el2_lib.scala 543:35] - wire _T_817 = ~q_ff[13]; // @[el2_lib.scala 543:40] - wire _T_819 = _T_815 ? _T_817 : q_ff[13]; // @[el2_lib.scala 543:23] - wire _T_809 = |q_ff[11:0]; // @[el2_lib.scala 543:35] - wire _T_811 = ~q_ff[12]; // @[el2_lib.scala 543:40] - wire _T_813 = _T_809 ? _T_811 : q_ff[12]; // @[el2_lib.scala 543:23] - wire _T_803 = |q_ff[10:0]; // @[el2_lib.scala 543:35] - wire _T_805 = ~q_ff[11]; // @[el2_lib.scala 543:40] - wire _T_807 = _T_803 ? _T_805 : q_ff[11]; // @[el2_lib.scala 543:23] - wire _T_797 = |q_ff[9:0]; // @[el2_lib.scala 543:35] - wire _T_799 = ~q_ff[10]; // @[el2_lib.scala 543:40] - wire _T_801 = _T_797 ? _T_799 : q_ff[10]; // @[el2_lib.scala 543:23] - wire _T_791 = |q_ff[8:0]; // @[el2_lib.scala 543:35] - wire _T_793 = ~q_ff[9]; // @[el2_lib.scala 543:40] - wire _T_795 = _T_791 ? _T_793 : q_ff[9]; // @[el2_lib.scala 543:23] - wire _T_785 = |q_ff[7:0]; // @[el2_lib.scala 543:35] - wire _T_787 = ~q_ff[8]; // @[el2_lib.scala 543:40] - wire _T_789 = _T_785 ? _T_787 : q_ff[8]; // @[el2_lib.scala 543:23] - wire _T_779 = |q_ff[6:0]; // @[el2_lib.scala 543:35] - wire _T_781 = ~q_ff[7]; // @[el2_lib.scala 543:40] - wire _T_783 = _T_779 ? _T_781 : q_ff[7]; // @[el2_lib.scala 543:23] - wire _T_773 = |q_ff[5:0]; // @[el2_lib.scala 543:35] - wire _T_775 = ~q_ff[6]; // @[el2_lib.scala 543:40] - wire _T_777 = _T_773 ? _T_775 : q_ff[6]; // @[el2_lib.scala 543:23] - wire _T_767 = |q_ff[4:0]; // @[el2_lib.scala 543:35] - wire _T_769 = ~q_ff[5]; // @[el2_lib.scala 543:40] - wire _T_771 = _T_767 ? _T_769 : q_ff[5]; // @[el2_lib.scala 543:23] - wire _T_761 = |q_ff[3:0]; // @[el2_lib.scala 543:35] - wire _T_763 = ~q_ff[4]; // @[el2_lib.scala 543:40] - wire _T_765 = _T_761 ? _T_763 : q_ff[4]; // @[el2_lib.scala 543:23] - wire _T_755 = |q_ff[2:0]; // @[el2_lib.scala 543:35] - wire _T_757 = ~q_ff[3]; // @[el2_lib.scala 543:40] - wire _T_759 = _T_755 ? _T_757 : q_ff[3]; // @[el2_lib.scala 543:23] - wire _T_749 = |q_ff[1:0]; // @[el2_lib.scala 543:35] - wire _T_751 = ~q_ff[2]; // @[el2_lib.scala 543:40] - wire _T_753 = _T_749 ? _T_751 : q_ff[2]; // @[el2_lib.scala 543:23] - wire _T_743 = |q_ff[0]; // @[el2_lib.scala 543:35] - wire _T_745 = ~q_ff[1]; // @[el2_lib.scala 543:40] - wire _T_747 = _T_743 ? _T_745 : q_ff[1]; // @[el2_lib.scala 543:23] - wire [6:0] _T_933 = {_T_783,_T_777,_T_771,_T_765,_T_759,_T_753,_T_747}; // @[el2_lib.scala 545:14] - wire [14:0] _T_941 = {_T_831,_T_825,_T_819,_T_813,_T_807,_T_801,_T_795,_T_789,_T_933}; // @[el2_lib.scala 545:14] - wire [30:0] _T_957 = {_T_927,_T_921,_T_915,_T_909,_T_903,_T_897,_T_891,_T_885,_T_948,_T_941}; // @[el2_lib.scala 545:14] + wire _T_923 = |q_ff[30:0]; // @[lib.scala 403:35] + wire _T_925 = ~q_ff[31]; // @[lib.scala 403:40] + wire _T_927 = _T_923 ? _T_925 : q_ff[31]; // @[lib.scala 403:23] + wire _T_917 = |q_ff[29:0]; // @[lib.scala 403:35] + wire _T_919 = ~q_ff[30]; // @[lib.scala 403:40] + wire _T_921 = _T_917 ? _T_919 : q_ff[30]; // @[lib.scala 403:23] + wire _T_911 = |q_ff[28:0]; // @[lib.scala 403:35] + wire _T_913 = ~q_ff[29]; // @[lib.scala 403:40] + wire _T_915 = _T_911 ? _T_913 : q_ff[29]; // @[lib.scala 403:23] + wire _T_905 = |q_ff[27:0]; // @[lib.scala 403:35] + wire _T_907 = ~q_ff[28]; // @[lib.scala 403:40] + wire _T_909 = _T_905 ? _T_907 : q_ff[28]; // @[lib.scala 403:23] + wire _T_899 = |q_ff[26:0]; // @[lib.scala 403:35] + wire _T_901 = ~q_ff[27]; // @[lib.scala 403:40] + wire _T_903 = _T_899 ? _T_901 : q_ff[27]; // @[lib.scala 403:23] + wire _T_893 = |q_ff[25:0]; // @[lib.scala 403:35] + wire _T_895 = ~q_ff[26]; // @[lib.scala 403:40] + wire _T_897 = _T_893 ? _T_895 : q_ff[26]; // @[lib.scala 403:23] + wire _T_887 = |q_ff[24:0]; // @[lib.scala 403:35] + wire _T_889 = ~q_ff[25]; // @[lib.scala 403:40] + wire _T_891 = _T_887 ? _T_889 : q_ff[25]; // @[lib.scala 403:23] + wire _T_881 = |q_ff[23:0]; // @[lib.scala 403:35] + wire _T_883 = ~q_ff[24]; // @[lib.scala 403:40] + wire _T_885 = _T_881 ? _T_883 : q_ff[24]; // @[lib.scala 403:23] + wire _T_875 = |q_ff[22:0]; // @[lib.scala 403:35] + wire _T_877 = ~q_ff[23]; // @[lib.scala 403:40] + wire _T_879 = _T_875 ? _T_877 : q_ff[23]; // @[lib.scala 403:23] + wire _T_869 = |q_ff[21:0]; // @[lib.scala 403:35] + wire _T_871 = ~q_ff[22]; // @[lib.scala 403:40] + wire _T_873 = _T_869 ? _T_871 : q_ff[22]; // @[lib.scala 403:23] + wire _T_863 = |q_ff[20:0]; // @[lib.scala 403:35] + wire _T_865 = ~q_ff[21]; // @[lib.scala 403:40] + wire _T_867 = _T_863 ? _T_865 : q_ff[21]; // @[lib.scala 403:23] + wire _T_857 = |q_ff[19:0]; // @[lib.scala 403:35] + wire _T_859 = ~q_ff[20]; // @[lib.scala 403:40] + wire _T_861 = _T_857 ? _T_859 : q_ff[20]; // @[lib.scala 403:23] + wire _T_851 = |q_ff[18:0]; // @[lib.scala 403:35] + wire _T_853 = ~q_ff[19]; // @[lib.scala 403:40] + wire _T_855 = _T_851 ? _T_853 : q_ff[19]; // @[lib.scala 403:23] + wire _T_845 = |q_ff[17:0]; // @[lib.scala 403:35] + wire _T_847 = ~q_ff[18]; // @[lib.scala 403:40] + wire _T_849 = _T_845 ? _T_847 : q_ff[18]; // @[lib.scala 403:23] + wire _T_839 = |q_ff[16:0]; // @[lib.scala 403:35] + wire _T_841 = ~q_ff[17]; // @[lib.scala 403:40] + wire _T_843 = _T_839 ? _T_841 : q_ff[17]; // @[lib.scala 403:23] + wire _T_833 = |q_ff[15:0]; // @[lib.scala 403:35] + wire _T_835 = ~q_ff[16]; // @[lib.scala 403:40] + wire _T_837 = _T_833 ? _T_835 : q_ff[16]; // @[lib.scala 403:23] + wire [7:0] _T_948 = {_T_879,_T_873,_T_867,_T_861,_T_855,_T_849,_T_843,_T_837}; // @[lib.scala 405:14] + wire _T_827 = |q_ff[14:0]; // @[lib.scala 403:35] + wire _T_829 = ~q_ff[15]; // @[lib.scala 403:40] + wire _T_831 = _T_827 ? _T_829 : q_ff[15]; // @[lib.scala 403:23] + wire _T_821 = |q_ff[13:0]; // @[lib.scala 403:35] + wire _T_823 = ~q_ff[14]; // @[lib.scala 403:40] + wire _T_825 = _T_821 ? _T_823 : q_ff[14]; // @[lib.scala 403:23] + wire _T_815 = |q_ff[12:0]; // @[lib.scala 403:35] + wire _T_817 = ~q_ff[13]; // @[lib.scala 403:40] + wire _T_819 = _T_815 ? _T_817 : q_ff[13]; // @[lib.scala 403:23] + wire _T_809 = |q_ff[11:0]; // @[lib.scala 403:35] + wire _T_811 = ~q_ff[12]; // @[lib.scala 403:40] + wire _T_813 = _T_809 ? _T_811 : q_ff[12]; // @[lib.scala 403:23] + wire _T_803 = |q_ff[10:0]; // @[lib.scala 403:35] + wire _T_805 = ~q_ff[11]; // @[lib.scala 403:40] + wire _T_807 = _T_803 ? _T_805 : q_ff[11]; // @[lib.scala 403:23] + wire _T_797 = |q_ff[9:0]; // @[lib.scala 403:35] + wire _T_799 = ~q_ff[10]; // @[lib.scala 403:40] + wire _T_801 = _T_797 ? _T_799 : q_ff[10]; // @[lib.scala 403:23] + wire _T_791 = |q_ff[8:0]; // @[lib.scala 403:35] + wire _T_793 = ~q_ff[9]; // @[lib.scala 403:40] + wire _T_795 = _T_791 ? _T_793 : q_ff[9]; // @[lib.scala 403:23] + wire _T_785 = |q_ff[7:0]; // @[lib.scala 403:35] + wire _T_787 = ~q_ff[8]; // @[lib.scala 403:40] + wire _T_789 = _T_785 ? _T_787 : q_ff[8]; // @[lib.scala 403:23] + wire _T_779 = |q_ff[6:0]; // @[lib.scala 403:35] + wire _T_781 = ~q_ff[7]; // @[lib.scala 403:40] + wire _T_783 = _T_779 ? _T_781 : q_ff[7]; // @[lib.scala 403:23] + wire _T_773 = |q_ff[5:0]; // @[lib.scala 403:35] + wire _T_775 = ~q_ff[6]; // @[lib.scala 403:40] + wire _T_777 = _T_773 ? _T_775 : q_ff[6]; // @[lib.scala 403:23] + wire _T_767 = |q_ff[4:0]; // @[lib.scala 403:35] + wire _T_769 = ~q_ff[5]; // @[lib.scala 403:40] + wire _T_771 = _T_767 ? _T_769 : q_ff[5]; // @[lib.scala 403:23] + wire _T_761 = |q_ff[3:0]; // @[lib.scala 403:35] + wire _T_763 = ~q_ff[4]; // @[lib.scala 403:40] + wire _T_765 = _T_761 ? _T_763 : q_ff[4]; // @[lib.scala 403:23] + wire _T_755 = |q_ff[2:0]; // @[lib.scala 403:35] + wire _T_757 = ~q_ff[3]; // @[lib.scala 403:40] + wire _T_759 = _T_755 ? _T_757 : q_ff[3]; // @[lib.scala 403:23] + wire _T_749 = |q_ff[1:0]; // @[lib.scala 403:35] + wire _T_751 = ~q_ff[2]; // @[lib.scala 403:40] + wire _T_753 = _T_749 ? _T_751 : q_ff[2]; // @[lib.scala 403:23] + wire _T_743 = |q_ff[0]; // @[lib.scala 403:35] + wire _T_745 = ~q_ff[1]; // @[lib.scala 403:40] + wire _T_747 = _T_743 ? _T_745 : q_ff[1]; // @[lib.scala 403:23] + wire [6:0] _T_933 = {_T_783,_T_777,_T_771,_T_765,_T_759,_T_753,_T_747}; // @[lib.scala 405:14] + wire [14:0] _T_941 = {_T_831,_T_825,_T_819,_T_813,_T_807,_T_801,_T_795,_T_789,_T_933}; // @[lib.scala 405:14] + wire [30:0] _T_957 = {_T_927,_T_921,_T_915,_T_909,_T_903,_T_897,_T_891,_T_885,_T_948,_T_941}; // @[lib.scala 405:14] wire [31:0] _T_959 = {_T_957,q_ff[0]}; // @[Cat.scala 29:58] wire [31:0] dividend_eff = _T_738 ? _T_959 : q_ff[31:0]; // @[exu_div_ctl.scala 166:22] wire [32:0] _T_995 = run_state ? 33'h1ffffffff : 33'h0; // @[Bitwise.scala 72:12] wire _T_1007 = _T_685 & rem_ff; // @[exu_div_ctl.scala 182:41] - reg [32:0] a_ff; // @[el2_lib.scala 514:16] + reg [32:0] a_ff; // @[lib.scala 374:16] wire rem_correct = _T_1007 & a_ff[32]; // @[exu_div_ctl.scala 182:50] wire [32:0] _T_980 = rem_correct ? a_ff : 33'h0; // @[Mux.scala 27:72] wire _T_968 = ~rem_correct; // @[exu_div_ctl.scala 173:6] @@ -61356,103 +61352,103 @@ module exu_div_ctl( wire _T_1010 = dividend_neg_ff ^ divisor_neg_ff; // @[exu_div_ctl.scala 183:50] wire _T_1011 = sign_ff & _T_1010; // @[exu_div_ctl.scala 183:31] wire [31:0] q_ff_eff = _T_1011 ? _T_959 : q_ff[31:0]; // @[exu_div_ctl.scala 183:21] - wire _T_1239 = |a_ff[0]; // @[el2_lib.scala 543:35] - wire _T_1241 = ~a_ff[1]; // @[el2_lib.scala 543:40] - wire _T_1243 = _T_1239 ? _T_1241 : a_ff[1]; // @[el2_lib.scala 543:23] - wire _T_1245 = |a_ff[1:0]; // @[el2_lib.scala 543:35] - wire _T_1247 = ~a_ff[2]; // @[el2_lib.scala 543:40] - wire _T_1249 = _T_1245 ? _T_1247 : a_ff[2]; // @[el2_lib.scala 543:23] - wire _T_1251 = |a_ff[2:0]; // @[el2_lib.scala 543:35] - wire _T_1253 = ~a_ff[3]; // @[el2_lib.scala 543:40] - wire _T_1255 = _T_1251 ? _T_1253 : a_ff[3]; // @[el2_lib.scala 543:23] - wire _T_1257 = |a_ff[3:0]; // @[el2_lib.scala 543:35] - wire _T_1259 = ~a_ff[4]; // @[el2_lib.scala 543:40] - wire _T_1261 = _T_1257 ? _T_1259 : a_ff[4]; // @[el2_lib.scala 543:23] - wire _T_1263 = |a_ff[4:0]; // @[el2_lib.scala 543:35] - wire _T_1265 = ~a_ff[5]; // @[el2_lib.scala 543:40] - wire _T_1267 = _T_1263 ? _T_1265 : a_ff[5]; // @[el2_lib.scala 543:23] - wire _T_1269 = |a_ff[5:0]; // @[el2_lib.scala 543:35] - wire _T_1271 = ~a_ff[6]; // @[el2_lib.scala 543:40] - wire _T_1273 = _T_1269 ? _T_1271 : a_ff[6]; // @[el2_lib.scala 543:23] - wire _T_1275 = |a_ff[6:0]; // @[el2_lib.scala 543:35] - wire _T_1277 = ~a_ff[7]; // @[el2_lib.scala 543:40] - wire _T_1279 = _T_1275 ? _T_1277 : a_ff[7]; // @[el2_lib.scala 543:23] - wire _T_1281 = |a_ff[7:0]; // @[el2_lib.scala 543:35] - wire _T_1283 = ~a_ff[8]; // @[el2_lib.scala 543:40] - wire _T_1285 = _T_1281 ? _T_1283 : a_ff[8]; // @[el2_lib.scala 543:23] - wire _T_1287 = |a_ff[8:0]; // @[el2_lib.scala 543:35] - wire _T_1289 = ~a_ff[9]; // @[el2_lib.scala 543:40] - wire _T_1291 = _T_1287 ? _T_1289 : a_ff[9]; // @[el2_lib.scala 543:23] - wire _T_1293 = |a_ff[9:0]; // @[el2_lib.scala 543:35] - wire _T_1295 = ~a_ff[10]; // @[el2_lib.scala 543:40] - wire _T_1297 = _T_1293 ? _T_1295 : a_ff[10]; // @[el2_lib.scala 543:23] - wire _T_1299 = |a_ff[10:0]; // @[el2_lib.scala 543:35] - wire _T_1301 = ~a_ff[11]; // @[el2_lib.scala 543:40] - wire _T_1303 = _T_1299 ? _T_1301 : a_ff[11]; // @[el2_lib.scala 543:23] - wire _T_1305 = |a_ff[11:0]; // @[el2_lib.scala 543:35] - wire _T_1307 = ~a_ff[12]; // @[el2_lib.scala 543:40] - wire _T_1309 = _T_1305 ? _T_1307 : a_ff[12]; // @[el2_lib.scala 543:23] - wire _T_1311 = |a_ff[12:0]; // @[el2_lib.scala 543:35] - wire _T_1313 = ~a_ff[13]; // @[el2_lib.scala 543:40] - wire _T_1315 = _T_1311 ? _T_1313 : a_ff[13]; // @[el2_lib.scala 543:23] - wire _T_1317 = |a_ff[13:0]; // @[el2_lib.scala 543:35] - wire _T_1319 = ~a_ff[14]; // @[el2_lib.scala 543:40] - wire _T_1321 = _T_1317 ? _T_1319 : a_ff[14]; // @[el2_lib.scala 543:23] - wire _T_1323 = |a_ff[14:0]; // @[el2_lib.scala 543:35] - wire _T_1325 = ~a_ff[15]; // @[el2_lib.scala 543:40] - wire _T_1327 = _T_1323 ? _T_1325 : a_ff[15]; // @[el2_lib.scala 543:23] - wire _T_1329 = |a_ff[15:0]; // @[el2_lib.scala 543:35] - wire _T_1331 = ~a_ff[16]; // @[el2_lib.scala 543:40] - wire _T_1333 = _T_1329 ? _T_1331 : a_ff[16]; // @[el2_lib.scala 543:23] - wire _T_1335 = |a_ff[16:0]; // @[el2_lib.scala 543:35] - wire _T_1337 = ~a_ff[17]; // @[el2_lib.scala 543:40] - wire _T_1339 = _T_1335 ? _T_1337 : a_ff[17]; // @[el2_lib.scala 543:23] - wire _T_1341 = |a_ff[17:0]; // @[el2_lib.scala 543:35] - wire _T_1343 = ~a_ff[18]; // @[el2_lib.scala 543:40] - wire _T_1345 = _T_1341 ? _T_1343 : a_ff[18]; // @[el2_lib.scala 543:23] - wire _T_1347 = |a_ff[18:0]; // @[el2_lib.scala 543:35] - wire _T_1349 = ~a_ff[19]; // @[el2_lib.scala 543:40] - wire _T_1351 = _T_1347 ? _T_1349 : a_ff[19]; // @[el2_lib.scala 543:23] - wire _T_1353 = |a_ff[19:0]; // @[el2_lib.scala 543:35] - wire _T_1355 = ~a_ff[20]; // @[el2_lib.scala 543:40] - wire _T_1357 = _T_1353 ? _T_1355 : a_ff[20]; // @[el2_lib.scala 543:23] - wire _T_1359 = |a_ff[20:0]; // @[el2_lib.scala 543:35] - wire _T_1361 = ~a_ff[21]; // @[el2_lib.scala 543:40] - wire _T_1363 = _T_1359 ? _T_1361 : a_ff[21]; // @[el2_lib.scala 543:23] - wire _T_1365 = |a_ff[21:0]; // @[el2_lib.scala 543:35] - wire _T_1367 = ~a_ff[22]; // @[el2_lib.scala 543:40] - wire _T_1369 = _T_1365 ? _T_1367 : a_ff[22]; // @[el2_lib.scala 543:23] - wire _T_1371 = |a_ff[22:0]; // @[el2_lib.scala 543:35] - wire _T_1373 = ~a_ff[23]; // @[el2_lib.scala 543:40] - wire _T_1375 = _T_1371 ? _T_1373 : a_ff[23]; // @[el2_lib.scala 543:23] - wire _T_1377 = |a_ff[23:0]; // @[el2_lib.scala 543:35] - wire _T_1379 = ~a_ff[24]; // @[el2_lib.scala 543:40] - wire _T_1381 = _T_1377 ? _T_1379 : a_ff[24]; // @[el2_lib.scala 543:23] - wire _T_1383 = |a_ff[24:0]; // @[el2_lib.scala 543:35] - wire _T_1385 = ~a_ff[25]; // @[el2_lib.scala 543:40] - wire _T_1387 = _T_1383 ? _T_1385 : a_ff[25]; // @[el2_lib.scala 543:23] - wire _T_1389 = |a_ff[25:0]; // @[el2_lib.scala 543:35] - wire _T_1391 = ~a_ff[26]; // @[el2_lib.scala 543:40] - wire _T_1393 = _T_1389 ? _T_1391 : a_ff[26]; // @[el2_lib.scala 543:23] - wire _T_1395 = |a_ff[26:0]; // @[el2_lib.scala 543:35] - wire _T_1397 = ~a_ff[27]; // @[el2_lib.scala 543:40] - wire _T_1399 = _T_1395 ? _T_1397 : a_ff[27]; // @[el2_lib.scala 543:23] - wire _T_1401 = |a_ff[27:0]; // @[el2_lib.scala 543:35] - wire _T_1403 = ~a_ff[28]; // @[el2_lib.scala 543:40] - wire _T_1405 = _T_1401 ? _T_1403 : a_ff[28]; // @[el2_lib.scala 543:23] - wire _T_1407 = |a_ff[28:0]; // @[el2_lib.scala 543:35] - wire _T_1409 = ~a_ff[29]; // @[el2_lib.scala 543:40] - wire _T_1411 = _T_1407 ? _T_1409 : a_ff[29]; // @[el2_lib.scala 543:23] - wire _T_1413 = |a_ff[29:0]; // @[el2_lib.scala 543:35] - wire _T_1415 = ~a_ff[30]; // @[el2_lib.scala 543:40] - wire _T_1417 = _T_1413 ? _T_1415 : a_ff[30]; // @[el2_lib.scala 543:23] - wire _T_1419 = |a_ff[30:0]; // @[el2_lib.scala 543:35] - wire _T_1421 = ~a_ff[31]; // @[el2_lib.scala 543:40] - wire _T_1423 = _T_1419 ? _T_1421 : a_ff[31]; // @[el2_lib.scala 543:23] - wire [6:0] _T_1429 = {_T_1279,_T_1273,_T_1267,_T_1261,_T_1255,_T_1249,_T_1243}; // @[el2_lib.scala 545:14] - wire [14:0] _T_1437 = {_T_1327,_T_1321,_T_1315,_T_1309,_T_1303,_T_1297,_T_1291,_T_1285,_T_1429}; // @[el2_lib.scala 545:14] - wire [7:0] _T_1444 = {_T_1375,_T_1369,_T_1363,_T_1357,_T_1351,_T_1345,_T_1339,_T_1333}; // @[el2_lib.scala 545:14] - wire [30:0] _T_1453 = {_T_1423,_T_1417,_T_1411,_T_1405,_T_1399,_T_1393,_T_1387,_T_1381,_T_1444,_T_1437}; // @[el2_lib.scala 545:14] + wire _T_1239 = |a_ff[0]; // @[lib.scala 403:35] + wire _T_1241 = ~a_ff[1]; // @[lib.scala 403:40] + wire _T_1243 = _T_1239 ? _T_1241 : a_ff[1]; // @[lib.scala 403:23] + wire _T_1245 = |a_ff[1:0]; // @[lib.scala 403:35] + wire _T_1247 = ~a_ff[2]; // @[lib.scala 403:40] + wire _T_1249 = _T_1245 ? _T_1247 : a_ff[2]; // @[lib.scala 403:23] + wire _T_1251 = |a_ff[2:0]; // @[lib.scala 403:35] + wire _T_1253 = ~a_ff[3]; // @[lib.scala 403:40] + wire _T_1255 = _T_1251 ? _T_1253 : a_ff[3]; // @[lib.scala 403:23] + wire _T_1257 = |a_ff[3:0]; // @[lib.scala 403:35] + wire _T_1259 = ~a_ff[4]; // @[lib.scala 403:40] + wire _T_1261 = _T_1257 ? _T_1259 : a_ff[4]; // @[lib.scala 403:23] + wire _T_1263 = |a_ff[4:0]; // @[lib.scala 403:35] + wire _T_1265 = ~a_ff[5]; // @[lib.scala 403:40] + wire _T_1267 = _T_1263 ? _T_1265 : a_ff[5]; // @[lib.scala 403:23] + wire _T_1269 = |a_ff[5:0]; // @[lib.scala 403:35] + wire _T_1271 = ~a_ff[6]; // @[lib.scala 403:40] + wire _T_1273 = _T_1269 ? _T_1271 : a_ff[6]; // @[lib.scala 403:23] + wire _T_1275 = |a_ff[6:0]; // @[lib.scala 403:35] + wire _T_1277 = ~a_ff[7]; // @[lib.scala 403:40] + wire _T_1279 = _T_1275 ? _T_1277 : a_ff[7]; // @[lib.scala 403:23] + wire _T_1281 = |a_ff[7:0]; // @[lib.scala 403:35] + wire _T_1283 = ~a_ff[8]; // @[lib.scala 403:40] + wire _T_1285 = _T_1281 ? _T_1283 : a_ff[8]; // @[lib.scala 403:23] + wire _T_1287 = |a_ff[8:0]; // @[lib.scala 403:35] + wire _T_1289 = ~a_ff[9]; // @[lib.scala 403:40] + wire _T_1291 = _T_1287 ? _T_1289 : a_ff[9]; // @[lib.scala 403:23] + wire _T_1293 = |a_ff[9:0]; // @[lib.scala 403:35] + wire _T_1295 = ~a_ff[10]; // @[lib.scala 403:40] + wire _T_1297 = _T_1293 ? _T_1295 : a_ff[10]; // @[lib.scala 403:23] + wire _T_1299 = |a_ff[10:0]; // @[lib.scala 403:35] + wire _T_1301 = ~a_ff[11]; // @[lib.scala 403:40] + wire _T_1303 = _T_1299 ? _T_1301 : a_ff[11]; // @[lib.scala 403:23] + wire _T_1305 = |a_ff[11:0]; // @[lib.scala 403:35] + wire _T_1307 = ~a_ff[12]; // @[lib.scala 403:40] + wire _T_1309 = _T_1305 ? _T_1307 : a_ff[12]; // @[lib.scala 403:23] + wire _T_1311 = |a_ff[12:0]; // @[lib.scala 403:35] + wire _T_1313 = ~a_ff[13]; // @[lib.scala 403:40] + wire _T_1315 = _T_1311 ? _T_1313 : a_ff[13]; // @[lib.scala 403:23] + wire _T_1317 = |a_ff[13:0]; // @[lib.scala 403:35] + wire _T_1319 = ~a_ff[14]; // @[lib.scala 403:40] + wire _T_1321 = _T_1317 ? _T_1319 : a_ff[14]; // @[lib.scala 403:23] + wire _T_1323 = |a_ff[14:0]; // @[lib.scala 403:35] + wire _T_1325 = ~a_ff[15]; // @[lib.scala 403:40] + wire _T_1327 = _T_1323 ? _T_1325 : a_ff[15]; // @[lib.scala 403:23] + wire _T_1329 = |a_ff[15:0]; // @[lib.scala 403:35] + wire _T_1331 = ~a_ff[16]; // @[lib.scala 403:40] + wire _T_1333 = _T_1329 ? _T_1331 : a_ff[16]; // @[lib.scala 403:23] + wire _T_1335 = |a_ff[16:0]; // @[lib.scala 403:35] + wire _T_1337 = ~a_ff[17]; // @[lib.scala 403:40] + wire _T_1339 = _T_1335 ? _T_1337 : a_ff[17]; // @[lib.scala 403:23] + wire _T_1341 = |a_ff[17:0]; // @[lib.scala 403:35] + wire _T_1343 = ~a_ff[18]; // @[lib.scala 403:40] + wire _T_1345 = _T_1341 ? _T_1343 : a_ff[18]; // @[lib.scala 403:23] + wire _T_1347 = |a_ff[18:0]; // @[lib.scala 403:35] + wire _T_1349 = ~a_ff[19]; // @[lib.scala 403:40] + wire _T_1351 = _T_1347 ? _T_1349 : a_ff[19]; // @[lib.scala 403:23] + wire _T_1353 = |a_ff[19:0]; // @[lib.scala 403:35] + wire _T_1355 = ~a_ff[20]; // @[lib.scala 403:40] + wire _T_1357 = _T_1353 ? _T_1355 : a_ff[20]; // @[lib.scala 403:23] + wire _T_1359 = |a_ff[20:0]; // @[lib.scala 403:35] + wire _T_1361 = ~a_ff[21]; // @[lib.scala 403:40] + wire _T_1363 = _T_1359 ? _T_1361 : a_ff[21]; // @[lib.scala 403:23] + wire _T_1365 = |a_ff[21:0]; // @[lib.scala 403:35] + wire _T_1367 = ~a_ff[22]; // @[lib.scala 403:40] + wire _T_1369 = _T_1365 ? _T_1367 : a_ff[22]; // @[lib.scala 403:23] + wire _T_1371 = |a_ff[22:0]; // @[lib.scala 403:35] + wire _T_1373 = ~a_ff[23]; // @[lib.scala 403:40] + wire _T_1375 = _T_1371 ? _T_1373 : a_ff[23]; // @[lib.scala 403:23] + wire _T_1377 = |a_ff[23:0]; // @[lib.scala 403:35] + wire _T_1379 = ~a_ff[24]; // @[lib.scala 403:40] + wire _T_1381 = _T_1377 ? _T_1379 : a_ff[24]; // @[lib.scala 403:23] + wire _T_1383 = |a_ff[24:0]; // @[lib.scala 403:35] + wire _T_1385 = ~a_ff[25]; // @[lib.scala 403:40] + wire _T_1387 = _T_1383 ? _T_1385 : a_ff[25]; // @[lib.scala 403:23] + wire _T_1389 = |a_ff[25:0]; // @[lib.scala 403:35] + wire _T_1391 = ~a_ff[26]; // @[lib.scala 403:40] + wire _T_1393 = _T_1389 ? _T_1391 : a_ff[26]; // @[lib.scala 403:23] + wire _T_1395 = |a_ff[26:0]; // @[lib.scala 403:35] + wire _T_1397 = ~a_ff[27]; // @[lib.scala 403:40] + wire _T_1399 = _T_1395 ? _T_1397 : a_ff[27]; // @[lib.scala 403:23] + wire _T_1401 = |a_ff[27:0]; // @[lib.scala 403:35] + wire _T_1403 = ~a_ff[28]; // @[lib.scala 403:40] + wire _T_1405 = _T_1401 ? _T_1403 : a_ff[28]; // @[lib.scala 403:23] + wire _T_1407 = |a_ff[28:0]; // @[lib.scala 403:35] + wire _T_1409 = ~a_ff[29]; // @[lib.scala 403:40] + wire _T_1411 = _T_1407 ? _T_1409 : a_ff[29]; // @[lib.scala 403:23] + wire _T_1413 = |a_ff[29:0]; // @[lib.scala 403:35] + wire _T_1415 = ~a_ff[30]; // @[lib.scala 403:40] + wire _T_1417 = _T_1413 ? _T_1415 : a_ff[30]; // @[lib.scala 403:23] + wire _T_1419 = |a_ff[30:0]; // @[lib.scala 403:35] + wire _T_1421 = ~a_ff[31]; // @[lib.scala 403:40] + wire _T_1423 = _T_1419 ? _T_1421 : a_ff[31]; // @[lib.scala 403:23] + wire [6:0] _T_1429 = {_T_1279,_T_1273,_T_1267,_T_1261,_T_1255,_T_1249,_T_1243}; // @[lib.scala 405:14] + wire [14:0] _T_1437 = {_T_1327,_T_1321,_T_1315,_T_1309,_T_1303,_T_1297,_T_1291,_T_1285,_T_1429}; // @[lib.scala 405:14] + wire [7:0] _T_1444 = {_T_1375,_T_1369,_T_1363,_T_1357,_T_1351,_T_1345,_T_1339,_T_1333}; // @[lib.scala 405:14] + wire [30:0] _T_1453 = {_T_1423,_T_1417,_T_1411,_T_1405,_T_1399,_T_1393,_T_1387,_T_1381,_T_1444,_T_1437}; // @[lib.scala 405:14] wire [31:0] _T_1455 = {_T_1453,a_ff[0]}; // @[Cat.scala 29:58] wire [31:0] a_ff_eff = _T_738 ? _T_1455 : a_ff[31:0]; // @[exu_div_ctl.scala 184:21] reg smallnum_case_ff; // @[exu_div_ctl.scala 203:32] @@ -61465,25 +61461,25 @@ module exu_div_ctl( wire [31:0] _T_1466 = _T_1462 ? q_ff_eff : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1467 = _T_1464 | _T_1465; // @[Mux.scala 27:72] wire _T_1499 = _T_709 & io_divisor[31]; // @[exu_div_ctl.scala 210:52] - rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en), .io_scan_mode(rvclkhdr_io_scan_mode) ); - rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_1 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_1_io_l1clk), .io_clk(rvclkhdr_1_io_clk), .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_2_io_l1clk), .io_clk(rvclkhdr_2_io_clk), .io_en(rvclkhdr_2_io_en), .io_scan_mode(rvclkhdr_2_io_scan_mode) ); - rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_3_io_l1clk), .io_clk(rvclkhdr_3_io_clk), .io_en(rvclkhdr_3_io_en), @@ -61491,18 +61487,18 @@ module exu_div_ctl( ); assign io_exu_div_result = _T_1467 | _T_1466; // @[exu_div_ctl.scala 186:21] assign io_exu_div_wren = finish_ff & _T; // @[exu_div_ctl.scala 156:20] - assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_io_en = _T_688 | finish_ff; // @[el2_lib.scala 485:16] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_1_io_en = io_dec_div_div_p_valid | _T_737; // @[el2_lib.scala 511:17] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_2_io_en = _T_990 | rem_correct; // @[el2_lib.scala 511:17] - assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_3_io_en = io_dec_div_div_p_valid; // @[el2_lib.scala 511:17] - assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_io_en = _T_688 | finish_ff; // @[lib.scala 345:16] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_1_io_en = io_dec_div_div_p_valid | _T_737; // @[lib.scala 371:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_2_io_en = _T_990 | rem_correct; // @[lib.scala 371:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_3_io_en = io_dec_div_div_p_valid; // @[lib.scala 371:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -61871,78 +61867,78 @@ module exu( reg [31:0] _RAND_36; reg [31:0] _RAND_37; `endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 518:23] - wire rvclkhdr_2_io_clk; // @[el2_lib.scala 518:23] - wire rvclkhdr_2_io_en; // @[el2_lib.scala 518:23] - wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 518:23] - wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_8_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_8_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_9_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_9_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 518:23] - wire rvclkhdr_10_io_clk; // @[el2_lib.scala 518:23] - wire rvclkhdr_10_io_en; // @[el2_lib.scala 518:23] - wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 518:23] - wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_11_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_11_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_12_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_12_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_12_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_12_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_13_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_13_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_13_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_13_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_14_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_14_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_14_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_14_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_15_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_15_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_15_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_15_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_16_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_16_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_16_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_16_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_17_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_17_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_17_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_17_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_io_en; // @[lib.scala 368:23] + wire rvclkhdr_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_en; // @[lib.scala 368:23] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_2_io_l1clk; // @[lib.scala 378:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 378:23] + wire rvclkhdr_2_io_en; // @[lib.scala 378:23] + wire rvclkhdr_2_io_scan_mode; // @[lib.scala 378:23] + wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_en; // @[lib.scala 368:23] + wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_en; // @[lib.scala 368:23] + wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_5_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_en; // @[lib.scala 368:23] + wire rvclkhdr_5_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_6_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_6_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_6_io_en; // @[lib.scala 368:23] + wire rvclkhdr_6_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_7_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_7_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_7_io_en; // @[lib.scala 368:23] + wire rvclkhdr_7_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_8_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_8_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_8_io_en; // @[lib.scala 368:23] + wire rvclkhdr_8_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_9_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_9_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_9_io_en; // @[lib.scala 368:23] + wire rvclkhdr_9_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_10_io_l1clk; // @[lib.scala 378:23] + wire rvclkhdr_10_io_clk; // @[lib.scala 378:23] + wire rvclkhdr_10_io_en; // @[lib.scala 378:23] + wire rvclkhdr_10_io_scan_mode; // @[lib.scala 378:23] + wire rvclkhdr_11_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_11_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_11_io_en; // @[lib.scala 368:23] + wire rvclkhdr_11_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_12_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_12_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_12_io_en; // @[lib.scala 368:23] + wire rvclkhdr_12_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_13_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_13_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_13_io_en; // @[lib.scala 368:23] + wire rvclkhdr_13_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_14_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_14_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_14_io_en; // @[lib.scala 368:23] + wire rvclkhdr_14_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_15_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_15_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_15_io_en; // @[lib.scala 368:23] + wire rvclkhdr_15_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_16_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_16_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_16_io_en; // @[lib.scala 368:23] + wire rvclkhdr_16_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_17_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_17_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_17_io_en; // @[lib.scala 368:23] + wire rvclkhdr_17_io_scan_mode; // @[lib.scala 368:23] wire i_alu_clock; // @[exu.scala 144:19] wire i_alu_reset; // @[exu.scala 144:19] wire i_alu_io_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 144:19] @@ -62027,48 +62023,48 @@ module exu( wire i_div_io_dec_div_div_p_bits_rem; // @[exu.scala 169:19] wire i_div_io_dec_div_dec_div_cancel; // @[exu.scala 169:19] wire [15:0] _T = {io_dec_exu_decode_exu_i0_predict_fghr_d,io_dec_exu_decode_exu_i0_predict_index_d}; // @[Cat.scala 29:58] - reg [30:0] i0_flush_path_x; // @[el2_lib.scala 514:16] - reg [31:0] _T_3; // @[el2_lib.scala 514:16] - reg i0_predict_p_x_valid; // @[el2_lib.scala 524:16] - reg i0_predict_p_x_bits_misp; // @[el2_lib.scala 524:16] - reg i0_predict_p_x_bits_ataken; // @[el2_lib.scala 524:16] - reg i0_predict_p_x_bits_boffset; // @[el2_lib.scala 524:16] - reg i0_predict_p_x_bits_pc4; // @[el2_lib.scala 524:16] - reg [1:0] i0_predict_p_x_bits_hist; // @[el2_lib.scala 524:16] - reg [11:0] i0_predict_p_x_bits_toffset; // @[el2_lib.scala 524:16] - reg i0_predict_p_x_bits_br_error; // @[el2_lib.scala 524:16] - reg i0_predict_p_x_bits_br_start_error; // @[el2_lib.scala 524:16] - reg i0_predict_p_x_bits_pcall; // @[el2_lib.scala 524:16] - reg i0_predict_p_x_bits_pret; // @[el2_lib.scala 524:16] - reg i0_predict_p_x_bits_pja; // @[el2_lib.scala 524:16] - reg i0_predict_p_x_bits_way; // @[el2_lib.scala 524:16] - reg [20:0] predpipe_x; // @[el2_lib.scala 514:16] - reg [20:0] predpipe_r; // @[el2_lib.scala 514:16] - reg [7:0] ghr_x; // @[el2_lib.scala 514:16] - reg i0_pred_correct_upper_x; // @[el2_lib.scala 514:16] - reg i0_flush_upper_x; // @[el2_lib.scala 514:16] - reg i0_taken_x; // @[el2_lib.scala 514:16] - reg i0_valid_x; // @[el2_lib.scala 514:16] - reg i0_pp_r_valid; // @[el2_lib.scala 524:16] - reg i0_pp_r_bits_misp; // @[el2_lib.scala 524:16] - reg i0_pp_r_bits_ataken; // @[el2_lib.scala 524:16] - reg i0_pp_r_bits_boffset; // @[el2_lib.scala 524:16] - reg i0_pp_r_bits_pc4; // @[el2_lib.scala 524:16] - reg [1:0] i0_pp_r_bits_hist; // @[el2_lib.scala 524:16] - reg i0_pp_r_bits_br_error; // @[el2_lib.scala 524:16] - reg i0_pp_r_bits_br_start_error; // @[el2_lib.scala 524:16] - reg i0_pp_r_bits_way; // @[el2_lib.scala 524:16] - reg [5:0] pred_temp1; // @[el2_lib.scala 514:16] - reg i0_pred_correct_upper_r; // @[el2_lib.scala 514:16] - reg [30:0] i0_flush_path_upper_r; // @[el2_lib.scala 514:16] - reg [24:0] pred_temp2; // @[el2_lib.scala 514:16] + reg [30:0] i0_flush_path_x; // @[lib.scala 374:16] + reg [31:0] _T_3; // @[lib.scala 374:16] + reg i0_predict_p_x_valid; // @[lib.scala 384:16] + reg i0_predict_p_x_bits_misp; // @[lib.scala 384:16] + reg i0_predict_p_x_bits_ataken; // @[lib.scala 384:16] + reg i0_predict_p_x_bits_boffset; // @[lib.scala 384:16] + reg i0_predict_p_x_bits_pc4; // @[lib.scala 384:16] + reg [1:0] i0_predict_p_x_bits_hist; // @[lib.scala 384:16] + reg [11:0] i0_predict_p_x_bits_toffset; // @[lib.scala 384:16] + reg i0_predict_p_x_bits_br_error; // @[lib.scala 384:16] + reg i0_predict_p_x_bits_br_start_error; // @[lib.scala 384:16] + reg i0_predict_p_x_bits_pcall; // @[lib.scala 384:16] + reg i0_predict_p_x_bits_pret; // @[lib.scala 384:16] + reg i0_predict_p_x_bits_pja; // @[lib.scala 384:16] + reg i0_predict_p_x_bits_way; // @[lib.scala 384:16] + reg [20:0] predpipe_x; // @[lib.scala 374:16] + reg [20:0] predpipe_r; // @[lib.scala 374:16] + reg [7:0] ghr_x; // @[lib.scala 374:16] + reg i0_pred_correct_upper_x; // @[lib.scala 374:16] + reg i0_flush_upper_x; // @[lib.scala 374:16] + reg i0_taken_x; // @[lib.scala 374:16] + reg i0_valid_x; // @[lib.scala 374:16] + reg i0_pp_r_valid; // @[lib.scala 384:16] + reg i0_pp_r_bits_misp; // @[lib.scala 384:16] + reg i0_pp_r_bits_ataken; // @[lib.scala 384:16] + reg i0_pp_r_bits_boffset; // @[lib.scala 384:16] + reg i0_pp_r_bits_pc4; // @[lib.scala 384:16] + reg [1:0] i0_pp_r_bits_hist; // @[lib.scala 384:16] + reg i0_pp_r_bits_br_error; // @[lib.scala 384:16] + reg i0_pp_r_bits_br_start_error; // @[lib.scala 384:16] + reg i0_pp_r_bits_way; // @[lib.scala 384:16] + reg [5:0] pred_temp1; // @[lib.scala 374:16] + reg i0_pred_correct_upper_r; // @[lib.scala 374:16] + reg [30:0] i0_flush_path_upper_r; // @[lib.scala 374:16] + reg [24:0] pred_temp2; // @[lib.scala 374:16] wire [30:0] _T_23 = {pred_temp2,pred_temp1}; // @[Cat.scala 29:58] wire _T_149 = ~io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[exu.scala 194:6] wire i0_predict_p_d_valid = i_alu_io_predict_p_out_valid; // @[exu.scala 43:53 exu.scala 159:41] wire _T_145 = i0_predict_p_d_valid & io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 187:54] wire i0_valid_d = _T_145 & _T_149; // @[exu.scala 187:95] wire _T_150 = _T_149 & i0_valid_d; // @[exu.scala 194:48] - reg [7:0] ghr_d; // @[el2_lib.scala 514:16] + reg [7:0] ghr_d; // @[lib.scala 374:16] wire i0_predict_p_d_bits_ataken = i_alu_io_predict_p_out_bits_ataken; // @[exu.scala 43:53 exu.scala 159:41] wire i0_taken_d = i0_predict_p_d_bits_ataken & io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 188:59] wire [7:0] _T_153 = {ghr_d[6:0],i0_taken_d}; // @[Cat.scala 29:58] @@ -62080,10 +62076,10 @@ module exu( wire [7:0] _T_161 = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r ? ghr_x : 8'h0; // @[Mux.scala 27:72] wire [7:0] ghr_d_ns = _T_162 | _T_161; // @[Mux.scala 27:72] wire _T_39 = ghr_d_ns != ghr_d; // @[exu.scala 91:39] - reg mul_valid_x; // @[el2_lib.scala 514:16] + reg mul_valid_x; // @[lib.scala 374:16] wire _T_40 = io_dec_exu_decode_exu_mul_p_valid != mul_valid_x; // @[exu.scala 91:89] wire _T_41 = _T_39 | _T_40; // @[exu.scala 91:50] - reg flush_lower_ff; // @[el2_lib.scala 514:16] + reg flush_lower_ff; // @[lib.scala 374:16] wire _T_42 = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r != flush_lower_ff; // @[exu.scala 91:151] wire i0_rs1_bypass_en_d = io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[0] | io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d[1]; // @[exu.scala 92:84] wire i0_rs2_bypass_en_d = io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[0] | io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d[1]; // @[exu.scala 93:84] @@ -62137,109 +62133,109 @@ module exu( wire [31:0] pred_correct_npc_r = {{1'd0}, _T_23}; // @[exu.scala 47:51 exu.scala 78:41] wire [31:0] _T_188 = i0_pred_correct_upper_r ? pred_correct_npc_r : {{1'd0}, i0_flush_path_upper_r}; // @[exu.scala 233:72] wire [31:0] i0_rs2_d = _T_92; // @[Mux.scala 27:72 Mux.scala 27:72] - rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en), .io_scan_mode(rvclkhdr_io_scan_mode) ); - rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_1 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_1_io_l1clk), .io_clk(rvclkhdr_1_io_clk), .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 518:23] + rvclkhdr rvclkhdr_2 ( // @[lib.scala 378:23] .io_l1clk(rvclkhdr_2_io_l1clk), .io_clk(rvclkhdr_2_io_clk), .io_en(rvclkhdr_2_io_en), .io_scan_mode(rvclkhdr_2_io_scan_mode) ); - rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_3_io_l1clk), .io_clk(rvclkhdr_3_io_clk), .io_en(rvclkhdr_3_io_en), .io_scan_mode(rvclkhdr_3_io_scan_mode) ); - rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_4_io_l1clk), .io_clk(rvclkhdr_4_io_clk), .io_en(rvclkhdr_4_io_en), .io_scan_mode(rvclkhdr_4_io_scan_mode) ); - rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_5 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_5_io_l1clk), .io_clk(rvclkhdr_5_io_clk), .io_en(rvclkhdr_5_io_en), .io_scan_mode(rvclkhdr_5_io_scan_mode) ); - rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_6 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_6_io_l1clk), .io_clk(rvclkhdr_6_io_clk), .io_en(rvclkhdr_6_io_en), .io_scan_mode(rvclkhdr_6_io_scan_mode) ); - rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_7 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_7_io_l1clk), .io_clk(rvclkhdr_7_io_clk), .io_en(rvclkhdr_7_io_en), .io_scan_mode(rvclkhdr_7_io_scan_mode) ); - rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_8 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_8_io_l1clk), .io_clk(rvclkhdr_8_io_clk), .io_en(rvclkhdr_8_io_en), .io_scan_mode(rvclkhdr_8_io_scan_mode) ); - rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_9 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_9_io_l1clk), .io_clk(rvclkhdr_9_io_clk), .io_en(rvclkhdr_9_io_en), .io_scan_mode(rvclkhdr_9_io_scan_mode) ); - rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 518:23] + rvclkhdr rvclkhdr_10 ( // @[lib.scala 378:23] .io_l1clk(rvclkhdr_10_io_l1clk), .io_clk(rvclkhdr_10_io_clk), .io_en(rvclkhdr_10_io_en), .io_scan_mode(rvclkhdr_10_io_scan_mode) ); - rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_11 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_11_io_l1clk), .io_clk(rvclkhdr_11_io_clk), .io_en(rvclkhdr_11_io_en), .io_scan_mode(rvclkhdr_11_io_scan_mode) ); - rvclkhdr rvclkhdr_12 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_12 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_12_io_l1clk), .io_clk(rvclkhdr_12_io_clk), .io_en(rvclkhdr_12_io_en), .io_scan_mode(rvclkhdr_12_io_scan_mode) ); - rvclkhdr rvclkhdr_13 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_13 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_13_io_l1clk), .io_clk(rvclkhdr_13_io_clk), .io_en(rvclkhdr_13_io_en), .io_scan_mode(rvclkhdr_13_io_scan_mode) ); - rvclkhdr rvclkhdr_14 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_14 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_14_io_l1clk), .io_clk(rvclkhdr_14_io_clk), .io_en(rvclkhdr_14_io_en), .io_scan_mode(rvclkhdr_14_io_scan_mode) ); - rvclkhdr rvclkhdr_15 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_15 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_15_io_l1clk), .io_clk(rvclkhdr_15_io_clk), .io_en(rvclkhdr_15_io_en), .io_scan_mode(rvclkhdr_15_io_scan_mode) ); - rvclkhdr rvclkhdr_16 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_16 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_16_io_l1clk), .io_clk(rvclkhdr_16_io_clk), .io_en(rvclkhdr_16_io_en), .io_scan_mode(rvclkhdr_16_io_scan_mode) ); - rvclkhdr rvclkhdr_17 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_17 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_17_io_l1clk), .io_clk(rvclkhdr_17_io_clk), .io_en(rvclkhdr_17_io_en), @@ -62370,60 +62366,60 @@ module exu( assign io_lsu_exu_exu_lsu_rs1_d = _T_106 | _T_105; // @[exu.scala 119:27] assign io_lsu_exu_exu_lsu_rs2_d = _T_117 | _T_118; // @[exu.scala 125:27] assign io_exu_flush_path_final = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r ? io_dec_exu_tlu_exu_dec_tlu_flush_path_r : i0_flush_path_d; // @[exu.scala 232:50] - assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_io_en = io_dec_exu_decode_exu_dec_data_en[1]; // @[el2_lib.scala 511:17] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_1_io_en = io_dec_exu_decode_exu_dec_data_en[1]; // @[el2_lib.scala 511:17] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 520:18] - assign rvclkhdr_2_io_en = io_dec_exu_decode_exu_dec_data_en[1]; // @[el2_lib.scala 521:17] - assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24] - assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_3_io_en = io_dec_exu_decode_exu_dec_data_en[1]; // @[el2_lib.scala 511:17] - assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_4_io_en = io_dec_exu_decode_exu_dec_data_en[0]; // @[el2_lib.scala 511:17] - assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_5_io_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[el2_lib.scala 511:17] - assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_6_io_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[el2_lib.scala 511:17] - assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_7_io_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[el2_lib.scala 511:17] - assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_8_io_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[el2_lib.scala 511:17] - assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_9_io_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[el2_lib.scala 511:17] - assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 520:18] - assign rvclkhdr_10_io_en = io_dec_exu_decode_exu_dec_ctl_en[0]; // @[el2_lib.scala 521:17] - assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24] - assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_11_io_en = io_dec_exu_decode_exu_dec_ctl_en[0]; // @[el2_lib.scala 511:17] - assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_12_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_12_io_en = io_dec_exu_decode_exu_dec_ctl_en[0]; // @[el2_lib.scala 511:17] - assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_13_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_13_io_en = io_dec_exu_decode_exu_dec_data_en[0]; // @[el2_lib.scala 511:17] - assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_14_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_14_io_en = io_dec_exu_decode_exu_dec_data_en[0]; // @[el2_lib.scala 511:17] - assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_15_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_15_io_en = _T_41 | _T_42; // @[el2_lib.scala 511:17] - assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_16_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_16_io_en = _T_41 | _T_42; // @[el2_lib.scala 511:17] - assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_17_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_17_io_en = _T_41 | _T_42; // @[el2_lib.scala 511:17] - assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_io_en = io_dec_exu_decode_exu_dec_data_en[1]; // @[lib.scala 371:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_1_io_en = io_dec_exu_decode_exu_dec_data_en[1]; // @[lib.scala 371:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 380:18] + assign rvclkhdr_2_io_en = io_dec_exu_decode_exu_dec_data_en[1]; // @[lib.scala 381:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 382:24] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_3_io_en = io_dec_exu_decode_exu_dec_data_en[1]; // @[lib.scala 371:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_4_io_en = io_dec_exu_decode_exu_dec_data_en[0]; // @[lib.scala 371:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_5_io_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[lib.scala 371:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_6_io_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[lib.scala 371:17] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_7_io_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[lib.scala 371:17] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_8_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_8_io_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[lib.scala 371:17] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_9_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_9_io_en = io_dec_exu_decode_exu_dec_ctl_en[1]; // @[lib.scala 371:17] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_10_io_clk = clock; // @[lib.scala 380:18] + assign rvclkhdr_10_io_en = io_dec_exu_decode_exu_dec_ctl_en[0]; // @[lib.scala 381:17] + assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 382:24] + assign rvclkhdr_11_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_11_io_en = io_dec_exu_decode_exu_dec_ctl_en[0]; // @[lib.scala 371:17] + assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_12_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_12_io_en = io_dec_exu_decode_exu_dec_ctl_en[0]; // @[lib.scala 371:17] + assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_13_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_13_io_en = io_dec_exu_decode_exu_dec_data_en[0]; // @[lib.scala 371:17] + assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_14_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_14_io_en = io_dec_exu_decode_exu_dec_data_en[0]; // @[lib.scala 371:17] + assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_15_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_15_io_en = _T_41 | _T_42; // @[lib.scala 371:17] + assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_16_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_16_io_en = _T_41 | _T_42; // @[lib.scala 371:17] + assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_17_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_17_io_en = _T_41 | _T_42; // @[lib.scala 371:17] + assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign i_alu_clock = clock; assign i_alu_reset = reset; assign i_alu_io_dec_alu_dec_i0_alu_decode_d = io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 145:20] @@ -63014,13 +63010,13 @@ module lsu_addrcheck( `ifdef RANDOMIZE_REG_INIT reg [31:0] _RAND_0; `endif // RANDOMIZE_REG_INIT - wire start_addr_in_dccm_region_d = io_start_addr_d[31:28] == 4'hf; // @[el2_lib.scala 496:49] - wire start_addr_in_dccm_d = io_start_addr_d[31:16] == 16'hf004; // @[el2_lib.scala 501:39] - wire end_addr_in_dccm_region_d = io_end_addr_d[31:28] == 4'hf; // @[el2_lib.scala 496:49] - wire end_addr_in_dccm_d = io_end_addr_d[31:16] == 16'hf004; // @[el2_lib.scala 501:39] + wire start_addr_in_dccm_region_d = io_start_addr_d[31:28] == 4'hf; // @[lib.scala 356:49] + wire start_addr_in_dccm_d = io_start_addr_d[31:16] == 16'hf004; // @[lib.scala 361:39] + wire end_addr_in_dccm_region_d = io_end_addr_d[31:28] == 4'hf; // @[lib.scala 356:49] + wire end_addr_in_dccm_d = io_end_addr_d[31:16] == 16'hf004; // @[lib.scala 361:39] wire addr_in_iccm = io_start_addr_d[31:28] == 4'he; // @[lsu_addrcheck.scala 42:45] - wire start_addr_in_pic_d = io_start_addr_d[31:15] == 17'h1e018; // @[el2_lib.scala 501:39] - wire end_addr_in_pic_d = io_end_addr_d[31:15] == 17'h1e018; // @[el2_lib.scala 501:39] + wire start_addr_in_pic_d = io_start_addr_d[31:15] == 17'h1e018; // @[lib.scala 361:39] + wire end_addr_in_pic_d = io_end_addr_d[31:15] == 17'h1e018; // @[lib.scala 361:39] wire start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_in_dccm_region_d; // @[lsu_addrcheck.scala 54:60] wire _T_17 = io_rs1_region_d == 4'hf; // @[lsu_addrcheck.scala 55:54] wire base_reg_dccm_or_pic = _T_17 | _T_17; // @[lsu_addrcheck.scala 55:73] @@ -63345,23 +63341,23 @@ module lsu_lsc_ctl( wire [31:0] rs1_d = io_lsu_pkt_d_bits_load_ldst_bypass_d ? io_lsu_result_m : lsu_rs1_d; // @[lsu_lsc_ctl.scala 99:28] wire [12:0] _T_6 = {1'h0,rs1_d[11:0]}; // @[Cat.scala 29:58] wire [12:0] _T_8 = {1'h0,lsu_offset_d}; // @[Cat.scala 29:58] - wire [12:0] _T_10 = _T_6 + _T_8; // @[el2_lib.scala 232:39] - wire _T_13 = lsu_offset_d[11] ^ _T_10[12]; // @[el2_lib.scala 233:46] - wire _T_14 = ~_T_13; // @[el2_lib.scala 233:33] + wire [12:0] _T_10 = _T_6 + _T_8; // @[lib.scala 92:39] + wire _T_13 = lsu_offset_d[11] ^ _T_10[12]; // @[lib.scala 93:46] + wire _T_14 = ~_T_13; // @[lib.scala 93:33] wire [19:0] _T_16 = _T_14 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12] - wire [19:0] _T_18 = _T_16 & rs1_d[31:12]; // @[el2_lib.scala 233:58] - wire _T_20 = ~lsu_offset_d[11]; // @[el2_lib.scala 234:18] - wire _T_22 = _T_20 & _T_10[12]; // @[el2_lib.scala 234:30] + wire [19:0] _T_18 = _T_16 & rs1_d[31:12]; // @[lib.scala 93:58] + wire _T_20 = ~lsu_offset_d[11]; // @[lib.scala 94:18] + wire _T_22 = _T_20 & _T_10[12]; // @[lib.scala 94:30] wire [19:0] _T_24 = _T_22 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12] - wire [19:0] _T_27 = rs1_d[31:12] + 20'h1; // @[el2_lib.scala 234:54] - wire [19:0] _T_28 = _T_24 & _T_27; // @[el2_lib.scala 234:41] - wire [19:0] _T_29 = _T_18 | _T_28; // @[el2_lib.scala 233:72] - wire _T_32 = ~_T_10[12]; // @[el2_lib.scala 235:31] - wire _T_33 = lsu_offset_d[11] & _T_32; // @[el2_lib.scala 235:29] + wire [19:0] _T_27 = rs1_d[31:12] + 20'h1; // @[lib.scala 94:54] + wire [19:0] _T_28 = _T_24 & _T_27; // @[lib.scala 94:41] + wire [19:0] _T_29 = _T_18 | _T_28; // @[lib.scala 93:72] + wire _T_32 = ~_T_10[12]; // @[lib.scala 95:31] + wire _T_33 = lsu_offset_d[11] & _T_32; // @[lib.scala 95:29] wire [19:0] _T_35 = _T_33 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12] - wire [19:0] _T_38 = rs1_d[31:12] - 20'h1; // @[el2_lib.scala 235:54] - wire [19:0] _T_39 = _T_35 & _T_38; // @[el2_lib.scala 235:41] - wire [19:0] _T_40 = _T_29 | _T_39; // @[el2_lib.scala 234:61] + wire [19:0] _T_38 = rs1_d[31:12] - 20'h1; // @[lib.scala 95:54] + wire [19:0] _T_39 = _T_35 & _T_38; // @[lib.scala 95:41] + wire [19:0] _T_40 = _T_29 | _T_39; // @[lib.scala 94:61] wire [2:0] _T_43 = io_lsu_pkt_d_bits_half ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] wire [2:0] _T_44 = _T_43 & 3'h1; // @[lsu_lsc_ctl.scala 104:58] wire [2:0] _T_46 = io_lsu_pkt_d_bits_word ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] @@ -64317,14 +64313,14 @@ module lsu_dccm_ctl( reg [31:0] _RAND_7; reg [31:0] _RAND_8; `endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_io_en; // @[lib.scala 368:23] + wire rvclkhdr_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_en; // @[lib.scala 368:23] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 368:23] wire [63:0] picm_rd_data_m = {io_lsu_pic_picm_rd_data,io_lsu_pic_picm_rd_data}; // @[Cat.scala 29:58] wire [63:0] dccm_rdata_corr_m = {io_sec_data_hi_m,io_sec_data_lo_m}; // @[Cat.scala 29:58] wire [63:0] dccm_rdata_m = {io_dccm_rdata_hi_m,io_dccm_rdata_lo_m}; // @[Cat.scala 29:58] @@ -64697,8 +64693,8 @@ module lsu_dccm_ctl( reg lsu_double_ecc_error_r_ff; // @[lsu_dccm_ctl.scala 167:74] reg ld_single_ecc_error_hi_r_ff; // @[lsu_dccm_ctl.scala 168:74] reg ld_single_ecc_error_lo_r_ff; // @[lsu_dccm_ctl.scala 169:74] - reg [15:0] ld_sec_addr_hi_r_ff; // @[el2_lib.scala 514:16] - reg [15:0] ld_sec_addr_lo_r_ff; // @[el2_lib.scala 514:16] + reg [15:0] ld_sec_addr_hi_r_ff; // @[lib.scala 374:16] + reg [15:0] ld_sec_addr_lo_r_ff; // @[lib.scala 374:16] wire _T_830 = io_lsu_pkt_d_bits_word | io_lsu_pkt_d_bits_dword; // @[lsu_dccm_ctl.scala 173:125] wire _T_831 = ~_T_830; // @[lsu_dccm_ctl.scala 173:100] wire _T_833 = io_lsu_addr_d[1:0] != 2'h0; // @[lsu_dccm_ctl.scala 173:174] @@ -65180,13 +65176,13 @@ module lsu_dccm_ctl( wire [14:0] _T_1874 = io_dma_pic_wen ? io_dma_dccm_ctl_dma_mem_addr[14:0] : io_lsu_addr_r[14:0]; // @[lsu_dccm_ctl.scala 274:93] wire [31:0] _T_1875 = {17'h0,_T_1874}; // @[Cat.scala 29:58] reg _T_1882; // @[lsu_dccm_ctl.scala 279:61] - rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en), .io_scan_mode(rvclkhdr_io_scan_mode) ); - rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_1 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_1_io_l1clk), .io_clk(rvclkhdr_1_io_clk), .io_en(rvclkhdr_1_io_en), @@ -65226,12 +65222,12 @@ module lsu_dccm_ctl( assign io_lsu_pic_picm_rdaddr = 32'hf00c0000 | _T_1868; // @[lsu_dccm_ctl.scala 273:35] assign io_lsu_pic_picm_wraddr = 32'hf00c0000 | _T_1875; // @[lsu_dccm_ctl.scala 274:35] assign io_lsu_pic_picm_wr_data = io_dma_pic_wen ? io_dma_dccm_ctl_dma_mem_wdata[31:0] : io_store_datafn_lo_r; // @[lsu_dccm_ctl.scala 276:35] - assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_io_en = io_ld_single_ecc_error_r; // @[el2_lib.scala 511:17] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_1_io_en = io_ld_single_ecc_error_r; // @[el2_lib.scala 511:17] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_io_en = io_ld_single_ecc_error_r; // @[lib.scala 371:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_1_io_en = io_ld_single_ecc_error_r; // @[lib.scala 371:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -65455,38 +65451,38 @@ module lsu_stbuf( reg [31:0] _RAND_22; reg [31:0] _RAND_23; `endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_io_en; // @[lib.scala 368:23] + wire rvclkhdr_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_en; // @[lib.scala 368:23] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_en; // @[lib.scala 368:23] + wire rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_en; // @[lib.scala 368:23] + wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_en; // @[lib.scala 368:23] + wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_5_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_en; // @[lib.scala 368:23] + wire rvclkhdr_5_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_6_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_6_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_6_io_en; // @[lib.scala 368:23] + wire rvclkhdr_6_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_7_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_7_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_7_io_en; // @[lib.scala 368:23] + wire rvclkhdr_7_io_scan_mode; // @[lib.scala 368:23] wire [1:0] _T_5 = io_lsu_pkt_r_bits_half ? 2'h3 : 2'h0; // @[Mux.scala 27:72] wire [3:0] _T_6 = io_lsu_pkt_r_bits_word ? 4'hf : 4'h0; // @[Mux.scala 27:72] wire [7:0] _T_7 = io_lsu_pkt_r_bits_dword ? 8'hff : 8'h0; // @[Mux.scala 27:72] @@ -65510,7 +65506,7 @@ module lsu_stbuf( reg [1:0] WrPtr; // @[Reg.scala 27:20] wire [1:0] WrPtrPlus1 = WrPtr + 2'h1; // @[lsu_stbuf.scala 125:26] wire [1:0] WrPtrPlus2 = WrPtr + 2'h2; // @[lsu_stbuf.scala 126:26] - reg [15:0] stbuf_addr_0; // @[el2_lib.scala 514:16] + reg [15:0] stbuf_addr_0; // @[lib.scala 374:16] wire _T_27 = stbuf_addr_0[15:2] == io_lsu_addr_r[15:2]; // @[lsu_stbuf.scala 130:120] reg _T_588; // @[lsu_stbuf.scala 163:88] reg _T_580; // @[lsu_stbuf.scala 163:88] @@ -65537,21 +65533,21 @@ module lsu_stbuf( wire [3:0] stbuf_reset = {_T_215,_T_211,_T_207,_T_203}; // @[Cat.scala 29:58] wire _T_34 = ~stbuf_reset[0]; // @[lsu_stbuf.scala 130:218] wire _T_35 = _T_32 & _T_34; // @[lsu_stbuf.scala 130:216] - reg [15:0] stbuf_addr_1; // @[el2_lib.scala 514:16] + reg [15:0] stbuf_addr_1; // @[lib.scala 374:16] wire _T_38 = stbuf_addr_1[15:2] == io_lsu_addr_r[15:2]; // @[lsu_stbuf.scala 130:120] wire _T_40 = _T_38 & stbuf_vld[1]; // @[lsu_stbuf.scala 130:179] wire _T_42 = ~stbuf_dma_kill[1]; // @[lsu_stbuf.scala 130:197] wire _T_43 = _T_40 & _T_42; // @[lsu_stbuf.scala 130:195] wire _T_45 = ~stbuf_reset[1]; // @[lsu_stbuf.scala 130:218] wire _T_46 = _T_43 & _T_45; // @[lsu_stbuf.scala 130:216] - reg [15:0] stbuf_addr_2; // @[el2_lib.scala 514:16] + reg [15:0] stbuf_addr_2; // @[lib.scala 374:16] wire _T_49 = stbuf_addr_2[15:2] == io_lsu_addr_r[15:2]; // @[lsu_stbuf.scala 130:120] wire _T_51 = _T_49 & stbuf_vld[2]; // @[lsu_stbuf.scala 130:179] wire _T_53 = ~stbuf_dma_kill[2]; // @[lsu_stbuf.scala 130:197] wire _T_54 = _T_51 & _T_53; // @[lsu_stbuf.scala 130:195] wire _T_56 = ~stbuf_reset[2]; // @[lsu_stbuf.scala 130:218] wire _T_57 = _T_54 & _T_56; // @[lsu_stbuf.scala 130:216] - reg [15:0] stbuf_addr_3; // @[el2_lib.scala 514:16] + reg [15:0] stbuf_addr_3; // @[lib.scala 374:16] wire _T_60 = stbuf_addr_3[15:2] == io_lsu_addr_r[15:2]; // @[lsu_stbuf.scala 130:120] wire _T_62 = _T_60 & stbuf_vld[3]; // @[lsu_stbuf.scala 130:179] wire _T_64 = ~stbuf_dma_kill[3]; // @[lsu_stbuf.scala 130:197] @@ -65668,28 +65664,28 @@ module lsu_stbuf( wire [3:0] stbuf_byteenin_3 = sel_lo[3] ? _T_286 : _T_287; // @[lsu_stbuf.scala 145:58] wire _T_291 = ~stbuf_byteen_0[0]; // @[lsu_stbuf.scala 147:67] wire _T_293 = _T_291 | store_byteen_lo_r[0]; // @[lsu_stbuf.scala 147:87] - reg [31:0] stbuf_data_0; // @[el2_lib.scala 514:16] + reg [31:0] stbuf_data_0; // @[lib.scala 374:16] wire [7:0] _T_296 = _T_293 ? io_store_datafn_lo_r[7:0] : stbuf_data_0[7:0]; // @[lsu_stbuf.scala 147:66] wire _T_300 = _T_291 | store_byteen_hi_r[0]; // @[lsu_stbuf.scala 148:29] wire [7:0] _T_303 = _T_300 ? io_store_datafn_hi_r[7:0] : stbuf_data_0[7:0]; // @[lsu_stbuf.scala 148:8] wire [7:0] datain1_0 = sel_lo[0] ? _T_296 : _T_303; // @[lsu_stbuf.scala 147:51] wire _T_307 = ~stbuf_byteen_1[0]; // @[lsu_stbuf.scala 147:67] wire _T_309 = _T_307 | store_byteen_lo_r[0]; // @[lsu_stbuf.scala 147:87] - reg [31:0] stbuf_data_1; // @[el2_lib.scala 514:16] + reg [31:0] stbuf_data_1; // @[lib.scala 374:16] wire [7:0] _T_312 = _T_309 ? io_store_datafn_lo_r[7:0] : stbuf_data_1[7:0]; // @[lsu_stbuf.scala 147:66] wire _T_316 = _T_307 | store_byteen_hi_r[0]; // @[lsu_stbuf.scala 148:29] wire [7:0] _T_319 = _T_316 ? io_store_datafn_hi_r[7:0] : stbuf_data_1[7:0]; // @[lsu_stbuf.scala 148:8] wire [7:0] datain1_1 = sel_lo[1] ? _T_312 : _T_319; // @[lsu_stbuf.scala 147:51] wire _T_323 = ~stbuf_byteen_2[0]; // @[lsu_stbuf.scala 147:67] wire _T_325 = _T_323 | store_byteen_lo_r[0]; // @[lsu_stbuf.scala 147:87] - reg [31:0] stbuf_data_2; // @[el2_lib.scala 514:16] + reg [31:0] stbuf_data_2; // @[lib.scala 374:16] wire [7:0] _T_328 = _T_325 ? io_store_datafn_lo_r[7:0] : stbuf_data_2[7:0]; // @[lsu_stbuf.scala 147:66] wire _T_332 = _T_323 | store_byteen_hi_r[0]; // @[lsu_stbuf.scala 148:29] wire [7:0] _T_335 = _T_332 ? io_store_datafn_hi_r[7:0] : stbuf_data_2[7:0]; // @[lsu_stbuf.scala 148:8] wire [7:0] datain1_2 = sel_lo[2] ? _T_328 : _T_335; // @[lsu_stbuf.scala 147:51] wire _T_339 = ~stbuf_byteen_3[0]; // @[lsu_stbuf.scala 147:67] wire _T_341 = _T_339 | store_byteen_lo_r[0]; // @[lsu_stbuf.scala 147:87] - reg [31:0] stbuf_data_3; // @[el2_lib.scala 514:16] + reg [31:0] stbuf_data_3; // @[lib.scala 374:16] wire [7:0] _T_344 = _T_341 ? io_store_datafn_lo_r[7:0] : stbuf_data_3[7:0]; // @[lsu_stbuf.scala 147:66] wire _T_348 = _T_339 | store_byteen_hi_r[0]; // @[lsu_stbuf.scala 148:29] wire [7:0] _T_351 = _T_348 ? io_store_datafn_hi_r[7:0] : stbuf_data_3[7:0]; // @[lsu_stbuf.scala 148:8] @@ -66120,49 +66116,49 @@ module lsu_stbuf( wire [7:0] stbuf_fwdpipe4_hi = ld_byte_rhit_hi[3] ? ld_fwddata_rpipe_hi[31:24] : stbuf_fwddata_hi_pre_m[31:24]; // @[lsu_stbuf.scala 265:30] wire [15:0] _T_1312 = {stbuf_fwdpipe2_hi,stbuf_fwdpipe1_hi}; // @[Cat.scala 29:58] wire [15:0] _T_1313 = {stbuf_fwdpipe4_hi,stbuf_fwdpipe3_hi}; // @[Cat.scala 29:58] - rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en), .io_scan_mode(rvclkhdr_io_scan_mode) ); - rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_1 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_1_io_l1clk), .io_clk(rvclkhdr_1_io_clk), .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_2_io_l1clk), .io_clk(rvclkhdr_2_io_clk), .io_en(rvclkhdr_2_io_en), .io_scan_mode(rvclkhdr_2_io_scan_mode) ); - rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_3_io_l1clk), .io_clk(rvclkhdr_3_io_clk), .io_en(rvclkhdr_3_io_en), .io_scan_mode(rvclkhdr_3_io_scan_mode) ); - rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_4_io_l1clk), .io_clk(rvclkhdr_4_io_clk), .io_en(rvclkhdr_4_io_en), .io_scan_mode(rvclkhdr_4_io_scan_mode) ); - rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_5 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_5_io_l1clk), .io_clk(rvclkhdr_5_io_clk), .io_en(rvclkhdr_5_io_en), .io_scan_mode(rvclkhdr_5_io_scan_mode) ); - rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_6 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_6_io_l1clk), .io_clk(rvclkhdr_6_io_clk), .io_en(rvclkhdr_6_io_en), .io_scan_mode(rvclkhdr_6_io_scan_mode) ); - rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_7 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_7_io_l1clk), .io_clk(rvclkhdr_7_io_clk), .io_en(rvclkhdr_7_io_en), @@ -66179,30 +66175,30 @@ module lsu_stbuf( assign io_stbuf_fwddata_lo_m = {_T_1298,_T_1297}; // @[lsu_stbuf.scala 59:43 lsu_stbuf.scala 260:25] assign io_stbuf_fwdbyteen_hi_m = {_T_1272,_T_1264}; // @[lsu_stbuf.scala 60:37 lsu_stbuf.scala 252:27] assign io_stbuf_fwdbyteen_lo_m = {_T_1283,_T_1275}; // @[lsu_stbuf.scala 61:37 lsu_stbuf.scala 253:27] - assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_io_en = stbuf_wr_en[0]; // @[el2_lib.scala 511:17] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_1_io_en = stbuf_wr_en[0]; // @[el2_lib.scala 511:17] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_2_io_en = stbuf_wr_en[1]; // @[el2_lib.scala 511:17] - assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_3_io_en = stbuf_wr_en[1]; // @[el2_lib.scala 511:17] - assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_4_io_en = stbuf_wr_en[2]; // @[el2_lib.scala 511:17] - assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_5_io_en = stbuf_wr_en[2]; // @[el2_lib.scala 511:17] - assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_6_io_en = stbuf_wr_en[3]; // @[el2_lib.scala 511:17] - assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_7_io_en = stbuf_wr_en[3]; // @[el2_lib.scala 511:17] - assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_io_en = stbuf_wr_en[0]; // @[lib.scala 371:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_1_io_en = stbuf_wr_en[0]; // @[lib.scala 371:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_2_io_en = stbuf_wr_en[1]; // @[lib.scala 371:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_3_io_en = stbuf_wr_en[1]; // @[lib.scala 371:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_4_io_en = stbuf_wr_en[2]; // @[lib.scala 371:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_5_io_en = stbuf_wr_en[2]; // @[lib.scala 371:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_6_io_en = stbuf_wr_en[3]; // @[lib.scala 371:17] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_7_io_en = stbuf_wr_en[3]; // @[lib.scala 371:17] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -66598,42 +66594,42 @@ module lsu_ecc( reg [31:0] _RAND_6; reg [31:0] _RAND_7; `endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] - wire _T_96 = ^io_dccm_rdata_hi_m; // @[el2_lib.scala 333:30] - wire _T_97 = ^io_dccm_data_ecc_hi_m; // @[el2_lib.scala 333:44] - wire _T_98 = _T_96 ^ _T_97; // @[el2_lib.scala 333:35] - wire [5:0] _T_106 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[26]}; // @[el2_lib.scala 333:76] - wire _T_107 = ^_T_106; // @[el2_lib.scala 333:83] - wire _T_108 = io_dccm_data_ecc_hi_m[5] ^ _T_107; // @[el2_lib.scala 333:71] - wire [6:0] _T_115 = {io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[11]}; // @[el2_lib.scala 333:103] - wire [14:0] _T_123 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_115}; // @[el2_lib.scala 333:103] - wire _T_124 = ^_T_123; // @[el2_lib.scala 333:110] - wire _T_125 = io_dccm_data_ecc_hi_m[4] ^ _T_124; // @[el2_lib.scala 333:98] - wire [6:0] _T_132 = {io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[4]}; // @[el2_lib.scala 333:130] - wire [14:0] _T_140 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_132}; // @[el2_lib.scala 333:130] - wire _T_141 = ^_T_140; // @[el2_lib.scala 333:137] - wire _T_142 = io_dccm_data_ecc_hi_m[3] ^ _T_141; // @[el2_lib.scala 333:125] - wire [8:0] _T_151 = {io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[1]}; // @[el2_lib.scala 333:157] - wire [17:0] _T_160 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_151}; // @[el2_lib.scala 333:157] - wire _T_161 = ^_T_160; // @[el2_lib.scala 333:164] - wire _T_162 = io_dccm_data_ecc_hi_m[2] ^ _T_161; // @[el2_lib.scala 333:152] - wire [8:0] _T_171 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[0]}; // @[el2_lib.scala 333:184] - wire [17:0] _T_180 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_171}; // @[el2_lib.scala 333:184] - wire _T_181 = ^_T_180; // @[el2_lib.scala 333:191] - wire _T_182 = io_dccm_data_ecc_hi_m[1] ^ _T_181; // @[el2_lib.scala 333:179] - wire [8:0] _T_191 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[11],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[4],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[1],io_dccm_rdata_hi_m[0]}; // @[el2_lib.scala 333:211] - wire [17:0] _T_200 = {io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[26],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[15],_T_191}; // @[el2_lib.scala 333:211] - wire _T_201 = ^_T_200; // @[el2_lib.scala 333:218] - wire _T_202 = io_dccm_data_ecc_hi_m[0] ^ _T_201; // @[el2_lib.scala 333:206] + wire rvclkhdr_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_io_en; // @[lib.scala 368:23] + wire rvclkhdr_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_en; // @[lib.scala 368:23] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 368:23] + wire _T_96 = ^io_dccm_rdata_hi_m; // @[lib.scala 193:30] + wire _T_97 = ^io_dccm_data_ecc_hi_m; // @[lib.scala 193:44] + wire _T_98 = _T_96 ^ _T_97; // @[lib.scala 193:35] + wire [5:0] _T_106 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[26]}; // @[lib.scala 193:76] + wire _T_107 = ^_T_106; // @[lib.scala 193:83] + wire _T_108 = io_dccm_data_ecc_hi_m[5] ^ _T_107; // @[lib.scala 193:71] + wire [6:0] _T_115 = {io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[11]}; // @[lib.scala 193:103] + wire [14:0] _T_123 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_115}; // @[lib.scala 193:103] + wire _T_124 = ^_T_123; // @[lib.scala 193:110] + wire _T_125 = io_dccm_data_ecc_hi_m[4] ^ _T_124; // @[lib.scala 193:98] + wire [6:0] _T_132 = {io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[4]}; // @[lib.scala 193:130] + wire [14:0] _T_140 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_132}; // @[lib.scala 193:130] + wire _T_141 = ^_T_140; // @[lib.scala 193:137] + wire _T_142 = io_dccm_data_ecc_hi_m[3] ^ _T_141; // @[lib.scala 193:125] + wire [8:0] _T_151 = {io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[1]}; // @[lib.scala 193:157] + wire [17:0] _T_160 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_151}; // @[lib.scala 193:157] + wire _T_161 = ^_T_160; // @[lib.scala 193:164] + wire _T_162 = io_dccm_data_ecc_hi_m[2] ^ _T_161; // @[lib.scala 193:152] + wire [8:0] _T_171 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[0]}; // @[lib.scala 193:184] + wire [17:0] _T_180 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_171}; // @[lib.scala 193:184] + wire _T_181 = ^_T_180; // @[lib.scala 193:191] + wire _T_182 = io_dccm_data_ecc_hi_m[1] ^ _T_181; // @[lib.scala 193:179] + wire [8:0] _T_191 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[11],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[4],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[1],io_dccm_rdata_hi_m[0]}; // @[lib.scala 193:211] + wire [17:0] _T_200 = {io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[26],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[15],_T_191}; // @[lib.scala 193:211] + wire _T_201 = ^_T_200; // @[lib.scala 193:218] + wire _T_202 = io_dccm_data_ecc_hi_m[0] ^ _T_201; // @[lib.scala 193:206] wire [6:0] _T_208 = {_T_98,_T_108,_T_125,_T_142,_T_162,_T_182,_T_202}; // @[Cat.scala 29:58] - wire _T_209 = _T_208 != 7'h0; // @[el2_lib.scala 334:44] + wire _T_209 = _T_208 != 7'h0; // @[lib.scala 194:44] wire _T_1131 = ~io_dec_tlu_core_ecc_disable; // @[lsu_ecc.scala 107:73] wire _T_1138 = io_lsu_pkt_m_bits_load | io_lsu_pkt_m_bits_store; // @[lsu_ecc.scala 125:65] wire _T_1139 = io_lsu_pkt_m_valid & _T_1138; // @[lsu_ecc.scala 125:39] @@ -66643,338 +66639,338 @@ module lsu_ecc( wire _T_1144 = ldst_dual_m | io_lsu_pkt_m_bits_dma; // @[lsu_ecc.scala 127:48] wire _T_1145 = is_ldst_m & _T_1144; // @[lsu_ecc.scala 127:33] wire is_ldst_hi_m = _T_1145 & _T_1131; // @[lsu_ecc.scala 127:73] - wire _T_210 = is_ldst_hi_m & _T_209; // @[el2_lib.scala 334:32] - wire single_ecc_error_hi_any = _T_210 & _T_208[6]; // @[el2_lib.scala 334:53] - wire _T_215 = ~_T_208[6]; // @[el2_lib.scala 335:55] - wire double_ecc_error_hi_any = _T_210 & _T_215; // @[el2_lib.scala 335:53] - wire _T_218 = _T_208[5:0] == 6'h1; // @[el2_lib.scala 339:41] - wire _T_220 = _T_208[5:0] == 6'h2; // @[el2_lib.scala 339:41] - wire _T_222 = _T_208[5:0] == 6'h3; // @[el2_lib.scala 339:41] - wire _T_224 = _T_208[5:0] == 6'h4; // @[el2_lib.scala 339:41] - wire _T_226 = _T_208[5:0] == 6'h5; // @[el2_lib.scala 339:41] - wire _T_228 = _T_208[5:0] == 6'h6; // @[el2_lib.scala 339:41] - wire _T_230 = _T_208[5:0] == 6'h7; // @[el2_lib.scala 339:41] - wire _T_232 = _T_208[5:0] == 6'h8; // @[el2_lib.scala 339:41] - wire _T_234 = _T_208[5:0] == 6'h9; // @[el2_lib.scala 339:41] - wire _T_236 = _T_208[5:0] == 6'ha; // @[el2_lib.scala 339:41] - wire _T_238 = _T_208[5:0] == 6'hb; // @[el2_lib.scala 339:41] - wire _T_240 = _T_208[5:0] == 6'hc; // @[el2_lib.scala 339:41] - wire _T_242 = _T_208[5:0] == 6'hd; // @[el2_lib.scala 339:41] - wire _T_244 = _T_208[5:0] == 6'he; // @[el2_lib.scala 339:41] - wire _T_246 = _T_208[5:0] == 6'hf; // @[el2_lib.scala 339:41] - wire _T_248 = _T_208[5:0] == 6'h10; // @[el2_lib.scala 339:41] - wire _T_250 = _T_208[5:0] == 6'h11; // @[el2_lib.scala 339:41] - wire _T_252 = _T_208[5:0] == 6'h12; // @[el2_lib.scala 339:41] - wire _T_254 = _T_208[5:0] == 6'h13; // @[el2_lib.scala 339:41] - wire _T_256 = _T_208[5:0] == 6'h14; // @[el2_lib.scala 339:41] - wire _T_258 = _T_208[5:0] == 6'h15; // @[el2_lib.scala 339:41] - wire _T_260 = _T_208[5:0] == 6'h16; // @[el2_lib.scala 339:41] - wire _T_262 = _T_208[5:0] == 6'h17; // @[el2_lib.scala 339:41] - wire _T_264 = _T_208[5:0] == 6'h18; // @[el2_lib.scala 339:41] - wire _T_266 = _T_208[5:0] == 6'h19; // @[el2_lib.scala 339:41] - wire _T_268 = _T_208[5:0] == 6'h1a; // @[el2_lib.scala 339:41] - wire _T_270 = _T_208[5:0] == 6'h1b; // @[el2_lib.scala 339:41] - wire _T_272 = _T_208[5:0] == 6'h1c; // @[el2_lib.scala 339:41] - wire _T_274 = _T_208[5:0] == 6'h1d; // @[el2_lib.scala 339:41] - wire _T_276 = _T_208[5:0] == 6'h1e; // @[el2_lib.scala 339:41] - wire _T_278 = _T_208[5:0] == 6'h1f; // @[el2_lib.scala 339:41] - wire _T_280 = _T_208[5:0] == 6'h20; // @[el2_lib.scala 339:41] - wire _T_282 = _T_208[5:0] == 6'h21; // @[el2_lib.scala 339:41] - wire _T_284 = _T_208[5:0] == 6'h22; // @[el2_lib.scala 339:41] - wire _T_286 = _T_208[5:0] == 6'h23; // @[el2_lib.scala 339:41] - wire _T_288 = _T_208[5:0] == 6'h24; // @[el2_lib.scala 339:41] - wire _T_290 = _T_208[5:0] == 6'h25; // @[el2_lib.scala 339:41] - wire _T_292 = _T_208[5:0] == 6'h26; // @[el2_lib.scala 339:41] - wire _T_294 = _T_208[5:0] == 6'h27; // @[el2_lib.scala 339:41] + wire _T_210 = is_ldst_hi_m & _T_209; // @[lib.scala 194:32] + wire single_ecc_error_hi_any = _T_210 & _T_208[6]; // @[lib.scala 194:53] + wire _T_215 = ~_T_208[6]; // @[lib.scala 195:55] + wire double_ecc_error_hi_any = _T_210 & _T_215; // @[lib.scala 195:53] + wire _T_218 = _T_208[5:0] == 6'h1; // @[lib.scala 199:41] + wire _T_220 = _T_208[5:0] == 6'h2; // @[lib.scala 199:41] + wire _T_222 = _T_208[5:0] == 6'h3; // @[lib.scala 199:41] + wire _T_224 = _T_208[5:0] == 6'h4; // @[lib.scala 199:41] + wire _T_226 = _T_208[5:0] == 6'h5; // @[lib.scala 199:41] + wire _T_228 = _T_208[5:0] == 6'h6; // @[lib.scala 199:41] + wire _T_230 = _T_208[5:0] == 6'h7; // @[lib.scala 199:41] + wire _T_232 = _T_208[5:0] == 6'h8; // @[lib.scala 199:41] + wire _T_234 = _T_208[5:0] == 6'h9; // @[lib.scala 199:41] + wire _T_236 = _T_208[5:0] == 6'ha; // @[lib.scala 199:41] + wire _T_238 = _T_208[5:0] == 6'hb; // @[lib.scala 199:41] + wire _T_240 = _T_208[5:0] == 6'hc; // @[lib.scala 199:41] + wire _T_242 = _T_208[5:0] == 6'hd; // @[lib.scala 199:41] + wire _T_244 = _T_208[5:0] == 6'he; // @[lib.scala 199:41] + wire _T_246 = _T_208[5:0] == 6'hf; // @[lib.scala 199:41] + wire _T_248 = _T_208[5:0] == 6'h10; // @[lib.scala 199:41] + wire _T_250 = _T_208[5:0] == 6'h11; // @[lib.scala 199:41] + wire _T_252 = _T_208[5:0] == 6'h12; // @[lib.scala 199:41] + wire _T_254 = _T_208[5:0] == 6'h13; // @[lib.scala 199:41] + wire _T_256 = _T_208[5:0] == 6'h14; // @[lib.scala 199:41] + wire _T_258 = _T_208[5:0] == 6'h15; // @[lib.scala 199:41] + wire _T_260 = _T_208[5:0] == 6'h16; // @[lib.scala 199:41] + wire _T_262 = _T_208[5:0] == 6'h17; // @[lib.scala 199:41] + wire _T_264 = _T_208[5:0] == 6'h18; // @[lib.scala 199:41] + wire _T_266 = _T_208[5:0] == 6'h19; // @[lib.scala 199:41] + wire _T_268 = _T_208[5:0] == 6'h1a; // @[lib.scala 199:41] + wire _T_270 = _T_208[5:0] == 6'h1b; // @[lib.scala 199:41] + wire _T_272 = _T_208[5:0] == 6'h1c; // @[lib.scala 199:41] + wire _T_274 = _T_208[5:0] == 6'h1d; // @[lib.scala 199:41] + wire _T_276 = _T_208[5:0] == 6'h1e; // @[lib.scala 199:41] + wire _T_278 = _T_208[5:0] == 6'h1f; // @[lib.scala 199:41] + wire _T_280 = _T_208[5:0] == 6'h20; // @[lib.scala 199:41] + wire _T_282 = _T_208[5:0] == 6'h21; // @[lib.scala 199:41] + wire _T_284 = _T_208[5:0] == 6'h22; // @[lib.scala 199:41] + wire _T_286 = _T_208[5:0] == 6'h23; // @[lib.scala 199:41] + wire _T_288 = _T_208[5:0] == 6'h24; // @[lib.scala 199:41] + wire _T_290 = _T_208[5:0] == 6'h25; // @[lib.scala 199:41] + wire _T_292 = _T_208[5:0] == 6'h26; // @[lib.scala 199:41] + wire _T_294 = _T_208[5:0] == 6'h27; // @[lib.scala 199:41] wire [7:0] _T_309 = {io_dccm_data_ecc_hi_m[3],io_dccm_rdata_hi_m[3:1],io_dccm_data_ecc_hi_m[2],io_dccm_rdata_hi_m[0],io_dccm_data_ecc_hi_m[1:0]}; // @[Cat.scala 29:58] wire [38:0] _T_315 = {io_dccm_data_ecc_hi_m[6],io_dccm_rdata_hi_m[31:26],io_dccm_data_ecc_hi_m[5],io_dccm_rdata_hi_m[25:11],io_dccm_data_ecc_hi_m[4],io_dccm_rdata_hi_m[10:4],_T_309}; // @[Cat.scala 29:58] - wire [9:0] _T_333 = {_T_254,_T_252,_T_250,_T_248,_T_246,_T_244,_T_242,_T_240,_T_238,_T_236}; // @[el2_lib.scala 342:69] - wire [18:0] _T_334 = {_T_333,_T_234,_T_232,_T_230,_T_228,_T_226,_T_224,_T_222,_T_220,_T_218}; // @[el2_lib.scala 342:69] - wire [9:0] _T_343 = {_T_274,_T_272,_T_270,_T_268,_T_266,_T_264,_T_262,_T_260,_T_258,_T_256}; // @[el2_lib.scala 342:69] - wire [9:0] _T_352 = {_T_294,_T_292,_T_290,_T_288,_T_286,_T_284,_T_282,_T_280,_T_278,_T_276}; // @[el2_lib.scala 342:69] - wire [38:0] _T_354 = {_T_352,_T_343,_T_334}; // @[el2_lib.scala 342:69] - wire [38:0] _T_355 = _T_354 ^ _T_315; // @[el2_lib.scala 342:76] - wire [38:0] _T_356 = single_ecc_error_hi_any ? _T_355 : _T_315; // @[el2_lib.scala 342:31] + wire [9:0] _T_333 = {_T_254,_T_252,_T_250,_T_248,_T_246,_T_244,_T_242,_T_240,_T_238,_T_236}; // @[lib.scala 202:69] + wire [18:0] _T_334 = {_T_333,_T_234,_T_232,_T_230,_T_228,_T_226,_T_224,_T_222,_T_220,_T_218}; // @[lib.scala 202:69] + wire [9:0] _T_343 = {_T_274,_T_272,_T_270,_T_268,_T_266,_T_264,_T_262,_T_260,_T_258,_T_256}; // @[lib.scala 202:69] + wire [9:0] _T_352 = {_T_294,_T_292,_T_290,_T_288,_T_286,_T_284,_T_282,_T_280,_T_278,_T_276}; // @[lib.scala 202:69] + wire [38:0] _T_354 = {_T_352,_T_343,_T_334}; // @[lib.scala 202:69] + wire [38:0] _T_355 = _T_354 ^ _T_315; // @[lib.scala 202:76] + wire [38:0] _T_356 = single_ecc_error_hi_any ? _T_355 : _T_315; // @[lib.scala 202:31] wire [3:0] _T_362 = {_T_356[6:4],_T_356[2]}; // @[Cat.scala 29:58] wire [27:0] _T_364 = {_T_356[37:32],_T_356[30:16],_T_356[14:8]}; // @[Cat.scala 29:58] - wire _T_474 = ^io_dccm_rdata_lo_m; // @[el2_lib.scala 333:30] - wire _T_475 = ^io_dccm_data_ecc_lo_m; // @[el2_lib.scala 333:44] - wire _T_476 = _T_474 ^ _T_475; // @[el2_lib.scala 333:35] - wire [5:0] _T_484 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[26]}; // @[el2_lib.scala 333:76] - wire _T_485 = ^_T_484; // @[el2_lib.scala 333:83] - wire _T_486 = io_dccm_data_ecc_lo_m[5] ^ _T_485; // @[el2_lib.scala 333:71] - wire [6:0] _T_493 = {io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[11]}; // @[el2_lib.scala 333:103] - wire [14:0] _T_501 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_493}; // @[el2_lib.scala 333:103] - wire _T_502 = ^_T_501; // @[el2_lib.scala 333:110] - wire _T_503 = io_dccm_data_ecc_lo_m[4] ^ _T_502; // @[el2_lib.scala 333:98] - wire [6:0] _T_510 = {io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[4]}; // @[el2_lib.scala 333:130] - wire [14:0] _T_518 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_510}; // @[el2_lib.scala 333:130] - wire _T_519 = ^_T_518; // @[el2_lib.scala 333:137] - wire _T_520 = io_dccm_data_ecc_lo_m[3] ^ _T_519; // @[el2_lib.scala 333:125] - wire [8:0] _T_529 = {io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[1]}; // @[el2_lib.scala 333:157] - wire [17:0] _T_538 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_529}; // @[el2_lib.scala 333:157] - wire _T_539 = ^_T_538; // @[el2_lib.scala 333:164] - wire _T_540 = io_dccm_data_ecc_lo_m[2] ^ _T_539; // @[el2_lib.scala 333:152] - wire [8:0] _T_549 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[0]}; // @[el2_lib.scala 333:184] - wire [17:0] _T_558 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_549}; // @[el2_lib.scala 333:184] - wire _T_559 = ^_T_558; // @[el2_lib.scala 333:191] - wire _T_560 = io_dccm_data_ecc_lo_m[1] ^ _T_559; // @[el2_lib.scala 333:179] - wire [8:0] _T_569 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[11],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[4],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[1],io_dccm_rdata_lo_m[0]}; // @[el2_lib.scala 333:211] - wire [17:0] _T_578 = {io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[26],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[15],_T_569}; // @[el2_lib.scala 333:211] - wire _T_579 = ^_T_578; // @[el2_lib.scala 333:218] - wire _T_580 = io_dccm_data_ecc_lo_m[0] ^ _T_579; // @[el2_lib.scala 333:206] + wire _T_474 = ^io_dccm_rdata_lo_m; // @[lib.scala 193:30] + wire _T_475 = ^io_dccm_data_ecc_lo_m; // @[lib.scala 193:44] + wire _T_476 = _T_474 ^ _T_475; // @[lib.scala 193:35] + wire [5:0] _T_484 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[26]}; // @[lib.scala 193:76] + wire _T_485 = ^_T_484; // @[lib.scala 193:83] + wire _T_486 = io_dccm_data_ecc_lo_m[5] ^ _T_485; // @[lib.scala 193:71] + wire [6:0] _T_493 = {io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[11]}; // @[lib.scala 193:103] + wire [14:0] _T_501 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_493}; // @[lib.scala 193:103] + wire _T_502 = ^_T_501; // @[lib.scala 193:110] + wire _T_503 = io_dccm_data_ecc_lo_m[4] ^ _T_502; // @[lib.scala 193:98] + wire [6:0] _T_510 = {io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[4]}; // @[lib.scala 193:130] + wire [14:0] _T_518 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_510}; // @[lib.scala 193:130] + wire _T_519 = ^_T_518; // @[lib.scala 193:137] + wire _T_520 = io_dccm_data_ecc_lo_m[3] ^ _T_519; // @[lib.scala 193:125] + wire [8:0] _T_529 = {io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[1]}; // @[lib.scala 193:157] + wire [17:0] _T_538 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_529}; // @[lib.scala 193:157] + wire _T_539 = ^_T_538; // @[lib.scala 193:164] + wire _T_540 = io_dccm_data_ecc_lo_m[2] ^ _T_539; // @[lib.scala 193:152] + wire [8:0] _T_549 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[0]}; // @[lib.scala 193:184] + wire [17:0] _T_558 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_549}; // @[lib.scala 193:184] + wire _T_559 = ^_T_558; // @[lib.scala 193:191] + wire _T_560 = io_dccm_data_ecc_lo_m[1] ^ _T_559; // @[lib.scala 193:179] + wire [8:0] _T_569 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[11],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[4],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[1],io_dccm_rdata_lo_m[0]}; // @[lib.scala 193:211] + wire [17:0] _T_578 = {io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[26],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[15],_T_569}; // @[lib.scala 193:211] + wire _T_579 = ^_T_578; // @[lib.scala 193:218] + wire _T_580 = io_dccm_data_ecc_lo_m[0] ^ _T_579; // @[lib.scala 193:206] wire [6:0] _T_586 = {_T_476,_T_486,_T_503,_T_520,_T_540,_T_560,_T_580}; // @[Cat.scala 29:58] - wire _T_587 = _T_586 != 7'h0; // @[el2_lib.scala 334:44] + wire _T_587 = _T_586 != 7'h0; // @[lib.scala 194:44] wire is_ldst_lo_m = is_ldst_m & _T_1131; // @[lsu_ecc.scala 126:33] - wire _T_588 = is_ldst_lo_m & _T_587; // @[el2_lib.scala 334:32] - wire single_ecc_error_lo_any = _T_588 & _T_586[6]; // @[el2_lib.scala 334:53] - wire _T_593 = ~_T_586[6]; // @[el2_lib.scala 335:55] - wire double_ecc_error_lo_any = _T_588 & _T_593; // @[el2_lib.scala 335:53] - wire _T_596 = _T_586[5:0] == 6'h1; // @[el2_lib.scala 339:41] - wire _T_598 = _T_586[5:0] == 6'h2; // @[el2_lib.scala 339:41] - wire _T_600 = _T_586[5:0] == 6'h3; // @[el2_lib.scala 339:41] - wire _T_602 = _T_586[5:0] == 6'h4; // @[el2_lib.scala 339:41] - wire _T_604 = _T_586[5:0] == 6'h5; // @[el2_lib.scala 339:41] - wire _T_606 = _T_586[5:0] == 6'h6; // @[el2_lib.scala 339:41] - wire _T_608 = _T_586[5:0] == 6'h7; // @[el2_lib.scala 339:41] - wire _T_610 = _T_586[5:0] == 6'h8; // @[el2_lib.scala 339:41] - wire _T_612 = _T_586[5:0] == 6'h9; // @[el2_lib.scala 339:41] - wire _T_614 = _T_586[5:0] == 6'ha; // @[el2_lib.scala 339:41] - wire _T_616 = _T_586[5:0] == 6'hb; // @[el2_lib.scala 339:41] - wire _T_618 = _T_586[5:0] == 6'hc; // @[el2_lib.scala 339:41] - wire _T_620 = _T_586[5:0] == 6'hd; // @[el2_lib.scala 339:41] - wire _T_622 = _T_586[5:0] == 6'he; // @[el2_lib.scala 339:41] - wire _T_624 = _T_586[5:0] == 6'hf; // @[el2_lib.scala 339:41] - wire _T_626 = _T_586[5:0] == 6'h10; // @[el2_lib.scala 339:41] - wire _T_628 = _T_586[5:0] == 6'h11; // @[el2_lib.scala 339:41] - wire _T_630 = _T_586[5:0] == 6'h12; // @[el2_lib.scala 339:41] - wire _T_632 = _T_586[5:0] == 6'h13; // @[el2_lib.scala 339:41] - wire _T_634 = _T_586[5:0] == 6'h14; // @[el2_lib.scala 339:41] - wire _T_636 = _T_586[5:0] == 6'h15; // @[el2_lib.scala 339:41] - wire _T_638 = _T_586[5:0] == 6'h16; // @[el2_lib.scala 339:41] - wire _T_640 = _T_586[5:0] == 6'h17; // @[el2_lib.scala 339:41] - wire _T_642 = _T_586[5:0] == 6'h18; // @[el2_lib.scala 339:41] - wire _T_644 = _T_586[5:0] == 6'h19; // @[el2_lib.scala 339:41] - wire _T_646 = _T_586[5:0] == 6'h1a; // @[el2_lib.scala 339:41] - wire _T_648 = _T_586[5:0] == 6'h1b; // @[el2_lib.scala 339:41] - wire _T_650 = _T_586[5:0] == 6'h1c; // @[el2_lib.scala 339:41] - wire _T_652 = _T_586[5:0] == 6'h1d; // @[el2_lib.scala 339:41] - wire _T_654 = _T_586[5:0] == 6'h1e; // @[el2_lib.scala 339:41] - wire _T_656 = _T_586[5:0] == 6'h1f; // @[el2_lib.scala 339:41] - wire _T_658 = _T_586[5:0] == 6'h20; // @[el2_lib.scala 339:41] - wire _T_660 = _T_586[5:0] == 6'h21; // @[el2_lib.scala 339:41] - wire _T_662 = _T_586[5:0] == 6'h22; // @[el2_lib.scala 339:41] - wire _T_664 = _T_586[5:0] == 6'h23; // @[el2_lib.scala 339:41] - wire _T_666 = _T_586[5:0] == 6'h24; // @[el2_lib.scala 339:41] - wire _T_668 = _T_586[5:0] == 6'h25; // @[el2_lib.scala 339:41] - wire _T_670 = _T_586[5:0] == 6'h26; // @[el2_lib.scala 339:41] - wire _T_672 = _T_586[5:0] == 6'h27; // @[el2_lib.scala 339:41] + wire _T_588 = is_ldst_lo_m & _T_587; // @[lib.scala 194:32] + wire single_ecc_error_lo_any = _T_588 & _T_586[6]; // @[lib.scala 194:53] + wire _T_593 = ~_T_586[6]; // @[lib.scala 195:55] + wire double_ecc_error_lo_any = _T_588 & _T_593; // @[lib.scala 195:53] + wire _T_596 = _T_586[5:0] == 6'h1; // @[lib.scala 199:41] + wire _T_598 = _T_586[5:0] == 6'h2; // @[lib.scala 199:41] + wire _T_600 = _T_586[5:0] == 6'h3; // @[lib.scala 199:41] + wire _T_602 = _T_586[5:0] == 6'h4; // @[lib.scala 199:41] + wire _T_604 = _T_586[5:0] == 6'h5; // @[lib.scala 199:41] + wire _T_606 = _T_586[5:0] == 6'h6; // @[lib.scala 199:41] + wire _T_608 = _T_586[5:0] == 6'h7; // @[lib.scala 199:41] + wire _T_610 = _T_586[5:0] == 6'h8; // @[lib.scala 199:41] + wire _T_612 = _T_586[5:0] == 6'h9; // @[lib.scala 199:41] + wire _T_614 = _T_586[5:0] == 6'ha; // @[lib.scala 199:41] + wire _T_616 = _T_586[5:0] == 6'hb; // @[lib.scala 199:41] + wire _T_618 = _T_586[5:0] == 6'hc; // @[lib.scala 199:41] + wire _T_620 = _T_586[5:0] == 6'hd; // @[lib.scala 199:41] + wire _T_622 = _T_586[5:0] == 6'he; // @[lib.scala 199:41] + wire _T_624 = _T_586[5:0] == 6'hf; // @[lib.scala 199:41] + wire _T_626 = _T_586[5:0] == 6'h10; // @[lib.scala 199:41] + wire _T_628 = _T_586[5:0] == 6'h11; // @[lib.scala 199:41] + wire _T_630 = _T_586[5:0] == 6'h12; // @[lib.scala 199:41] + wire _T_632 = _T_586[5:0] == 6'h13; // @[lib.scala 199:41] + wire _T_634 = _T_586[5:0] == 6'h14; // @[lib.scala 199:41] + wire _T_636 = _T_586[5:0] == 6'h15; // @[lib.scala 199:41] + wire _T_638 = _T_586[5:0] == 6'h16; // @[lib.scala 199:41] + wire _T_640 = _T_586[5:0] == 6'h17; // @[lib.scala 199:41] + wire _T_642 = _T_586[5:0] == 6'h18; // @[lib.scala 199:41] + wire _T_644 = _T_586[5:0] == 6'h19; // @[lib.scala 199:41] + wire _T_646 = _T_586[5:0] == 6'h1a; // @[lib.scala 199:41] + wire _T_648 = _T_586[5:0] == 6'h1b; // @[lib.scala 199:41] + wire _T_650 = _T_586[5:0] == 6'h1c; // @[lib.scala 199:41] + wire _T_652 = _T_586[5:0] == 6'h1d; // @[lib.scala 199:41] + wire _T_654 = _T_586[5:0] == 6'h1e; // @[lib.scala 199:41] + wire _T_656 = _T_586[5:0] == 6'h1f; // @[lib.scala 199:41] + wire _T_658 = _T_586[5:0] == 6'h20; // @[lib.scala 199:41] + wire _T_660 = _T_586[5:0] == 6'h21; // @[lib.scala 199:41] + wire _T_662 = _T_586[5:0] == 6'h22; // @[lib.scala 199:41] + wire _T_664 = _T_586[5:0] == 6'h23; // @[lib.scala 199:41] + wire _T_666 = _T_586[5:0] == 6'h24; // @[lib.scala 199:41] + wire _T_668 = _T_586[5:0] == 6'h25; // @[lib.scala 199:41] + wire _T_670 = _T_586[5:0] == 6'h26; // @[lib.scala 199:41] + wire _T_672 = _T_586[5:0] == 6'h27; // @[lib.scala 199:41] wire [7:0] _T_687 = {io_dccm_data_ecc_lo_m[3],io_dccm_rdata_lo_m[3:1],io_dccm_data_ecc_lo_m[2],io_dccm_rdata_lo_m[0],io_dccm_data_ecc_lo_m[1:0]}; // @[Cat.scala 29:58] wire [38:0] _T_693 = {io_dccm_data_ecc_lo_m[6],io_dccm_rdata_lo_m[31:26],io_dccm_data_ecc_lo_m[5],io_dccm_rdata_lo_m[25:11],io_dccm_data_ecc_lo_m[4],io_dccm_rdata_lo_m[10:4],_T_687}; // @[Cat.scala 29:58] - wire [9:0] _T_711 = {_T_632,_T_630,_T_628,_T_626,_T_624,_T_622,_T_620,_T_618,_T_616,_T_614}; // @[el2_lib.scala 342:69] - wire [18:0] _T_712 = {_T_711,_T_612,_T_610,_T_608,_T_606,_T_604,_T_602,_T_600,_T_598,_T_596}; // @[el2_lib.scala 342:69] - wire [9:0] _T_721 = {_T_652,_T_650,_T_648,_T_646,_T_644,_T_642,_T_640,_T_638,_T_636,_T_634}; // @[el2_lib.scala 342:69] - wire [9:0] _T_730 = {_T_672,_T_670,_T_668,_T_666,_T_664,_T_662,_T_660,_T_658,_T_656,_T_654}; // @[el2_lib.scala 342:69] - wire [38:0] _T_732 = {_T_730,_T_721,_T_712}; // @[el2_lib.scala 342:69] - wire [38:0] _T_733 = _T_732 ^ _T_693; // @[el2_lib.scala 342:76] - wire [38:0] _T_734 = single_ecc_error_lo_any ? _T_733 : _T_693; // @[el2_lib.scala 342:31] + wire [9:0] _T_711 = {_T_632,_T_630,_T_628,_T_626,_T_624,_T_622,_T_620,_T_618,_T_616,_T_614}; // @[lib.scala 202:69] + wire [18:0] _T_712 = {_T_711,_T_612,_T_610,_T_608,_T_606,_T_604,_T_602,_T_600,_T_598,_T_596}; // @[lib.scala 202:69] + wire [9:0] _T_721 = {_T_652,_T_650,_T_648,_T_646,_T_644,_T_642,_T_640,_T_638,_T_636,_T_634}; // @[lib.scala 202:69] + wire [9:0] _T_730 = {_T_672,_T_670,_T_668,_T_666,_T_664,_T_662,_T_660,_T_658,_T_656,_T_654}; // @[lib.scala 202:69] + wire [38:0] _T_732 = {_T_730,_T_721,_T_712}; // @[lib.scala 202:69] + wire [38:0] _T_733 = _T_732 ^ _T_693; // @[lib.scala 202:76] + wire [38:0] _T_734 = single_ecc_error_lo_any ? _T_733 : _T_693; // @[lib.scala 202:31] wire [3:0] _T_740 = {_T_734[6:4],_T_734[2]}; // @[Cat.scala 29:58] wire [27:0] _T_742 = {_T_734[37:32],_T_734[30:16],_T_734[14:8]}; // @[Cat.scala 29:58] wire [31:0] _T_1158 = io_dma_dccm_wen ? io_dma_dccm_wdata_lo : io_stbuf_data_any; // @[lsu_ecc.scala 149:87] wire [31:0] dccm_wdata_lo_any = io_ld_single_ecc_error_r_ff ? io_sec_data_lo_r_ff : _T_1158; // @[lsu_ecc.scala 149:27] - wire _T_774 = dccm_wdata_lo_any[0] ^ dccm_wdata_lo_any[1]; // @[el2_lib.scala 259:74] - wire _T_775 = _T_774 ^ dccm_wdata_lo_any[3]; // @[el2_lib.scala 259:74] - wire _T_776 = _T_775 ^ dccm_wdata_lo_any[4]; // @[el2_lib.scala 259:74] - wire _T_777 = _T_776 ^ dccm_wdata_lo_any[6]; // @[el2_lib.scala 259:74] - wire _T_778 = _T_777 ^ dccm_wdata_lo_any[8]; // @[el2_lib.scala 259:74] - wire _T_779 = _T_778 ^ dccm_wdata_lo_any[10]; // @[el2_lib.scala 259:74] - wire _T_780 = _T_779 ^ dccm_wdata_lo_any[11]; // @[el2_lib.scala 259:74] - wire _T_781 = _T_780 ^ dccm_wdata_lo_any[13]; // @[el2_lib.scala 259:74] - wire _T_782 = _T_781 ^ dccm_wdata_lo_any[15]; // @[el2_lib.scala 259:74] - wire _T_783 = _T_782 ^ dccm_wdata_lo_any[17]; // @[el2_lib.scala 259:74] - wire _T_784 = _T_783 ^ dccm_wdata_lo_any[19]; // @[el2_lib.scala 259:74] - wire _T_785 = _T_784 ^ dccm_wdata_lo_any[21]; // @[el2_lib.scala 259:74] - wire _T_786 = _T_785 ^ dccm_wdata_lo_any[23]; // @[el2_lib.scala 259:74] - wire _T_787 = _T_786 ^ dccm_wdata_lo_any[25]; // @[el2_lib.scala 259:74] - wire _T_788 = _T_787 ^ dccm_wdata_lo_any[26]; // @[el2_lib.scala 259:74] - wire _T_789 = _T_788 ^ dccm_wdata_lo_any[28]; // @[el2_lib.scala 259:74] - wire _T_790 = _T_789 ^ dccm_wdata_lo_any[30]; // @[el2_lib.scala 259:74] - wire _T_809 = dccm_wdata_lo_any[0] ^ dccm_wdata_lo_any[2]; // @[el2_lib.scala 259:74] - wire _T_810 = _T_809 ^ dccm_wdata_lo_any[3]; // @[el2_lib.scala 259:74] - wire _T_811 = _T_810 ^ dccm_wdata_lo_any[5]; // @[el2_lib.scala 259:74] - wire _T_812 = _T_811 ^ dccm_wdata_lo_any[6]; // @[el2_lib.scala 259:74] - wire _T_813 = _T_812 ^ dccm_wdata_lo_any[9]; // @[el2_lib.scala 259:74] - wire _T_814 = _T_813 ^ dccm_wdata_lo_any[10]; // @[el2_lib.scala 259:74] - wire _T_815 = _T_814 ^ dccm_wdata_lo_any[12]; // @[el2_lib.scala 259:74] - wire _T_816 = _T_815 ^ dccm_wdata_lo_any[13]; // @[el2_lib.scala 259:74] - wire _T_817 = _T_816 ^ dccm_wdata_lo_any[16]; // @[el2_lib.scala 259:74] - wire _T_818 = _T_817 ^ dccm_wdata_lo_any[17]; // @[el2_lib.scala 259:74] - wire _T_819 = _T_818 ^ dccm_wdata_lo_any[20]; // @[el2_lib.scala 259:74] - wire _T_820 = _T_819 ^ dccm_wdata_lo_any[21]; // @[el2_lib.scala 259:74] - wire _T_821 = _T_820 ^ dccm_wdata_lo_any[24]; // @[el2_lib.scala 259:74] - wire _T_822 = _T_821 ^ dccm_wdata_lo_any[25]; // @[el2_lib.scala 259:74] - wire _T_823 = _T_822 ^ dccm_wdata_lo_any[27]; // @[el2_lib.scala 259:74] - wire _T_824 = _T_823 ^ dccm_wdata_lo_any[28]; // @[el2_lib.scala 259:74] - wire _T_825 = _T_824 ^ dccm_wdata_lo_any[31]; // @[el2_lib.scala 259:74] - wire _T_844 = dccm_wdata_lo_any[1] ^ dccm_wdata_lo_any[2]; // @[el2_lib.scala 259:74] - wire _T_845 = _T_844 ^ dccm_wdata_lo_any[3]; // @[el2_lib.scala 259:74] - wire _T_846 = _T_845 ^ dccm_wdata_lo_any[7]; // @[el2_lib.scala 259:74] - wire _T_847 = _T_846 ^ dccm_wdata_lo_any[8]; // @[el2_lib.scala 259:74] - wire _T_848 = _T_847 ^ dccm_wdata_lo_any[9]; // @[el2_lib.scala 259:74] - wire _T_849 = _T_848 ^ dccm_wdata_lo_any[10]; // @[el2_lib.scala 259:74] - wire _T_850 = _T_849 ^ dccm_wdata_lo_any[14]; // @[el2_lib.scala 259:74] - wire _T_851 = _T_850 ^ dccm_wdata_lo_any[15]; // @[el2_lib.scala 259:74] - wire _T_852 = _T_851 ^ dccm_wdata_lo_any[16]; // @[el2_lib.scala 259:74] - wire _T_853 = _T_852 ^ dccm_wdata_lo_any[17]; // @[el2_lib.scala 259:74] - wire _T_854 = _T_853 ^ dccm_wdata_lo_any[22]; // @[el2_lib.scala 259:74] - wire _T_855 = _T_854 ^ dccm_wdata_lo_any[23]; // @[el2_lib.scala 259:74] - wire _T_856 = _T_855 ^ dccm_wdata_lo_any[24]; // @[el2_lib.scala 259:74] - wire _T_857 = _T_856 ^ dccm_wdata_lo_any[25]; // @[el2_lib.scala 259:74] - wire _T_858 = _T_857 ^ dccm_wdata_lo_any[29]; // @[el2_lib.scala 259:74] - wire _T_859 = _T_858 ^ dccm_wdata_lo_any[30]; // @[el2_lib.scala 259:74] - wire _T_860 = _T_859 ^ dccm_wdata_lo_any[31]; // @[el2_lib.scala 259:74] - wire _T_876 = dccm_wdata_lo_any[4] ^ dccm_wdata_lo_any[5]; // @[el2_lib.scala 259:74] - wire _T_877 = _T_876 ^ dccm_wdata_lo_any[6]; // @[el2_lib.scala 259:74] - wire _T_878 = _T_877 ^ dccm_wdata_lo_any[7]; // @[el2_lib.scala 259:74] - wire _T_879 = _T_878 ^ dccm_wdata_lo_any[8]; // @[el2_lib.scala 259:74] - wire _T_880 = _T_879 ^ dccm_wdata_lo_any[9]; // @[el2_lib.scala 259:74] - wire _T_881 = _T_880 ^ dccm_wdata_lo_any[10]; // @[el2_lib.scala 259:74] - wire _T_882 = _T_881 ^ dccm_wdata_lo_any[18]; // @[el2_lib.scala 259:74] - wire _T_883 = _T_882 ^ dccm_wdata_lo_any[19]; // @[el2_lib.scala 259:74] - wire _T_884 = _T_883 ^ dccm_wdata_lo_any[20]; // @[el2_lib.scala 259:74] - wire _T_885 = _T_884 ^ dccm_wdata_lo_any[21]; // @[el2_lib.scala 259:74] - wire _T_886 = _T_885 ^ dccm_wdata_lo_any[22]; // @[el2_lib.scala 259:74] - wire _T_887 = _T_886 ^ dccm_wdata_lo_any[23]; // @[el2_lib.scala 259:74] - wire _T_888 = _T_887 ^ dccm_wdata_lo_any[24]; // @[el2_lib.scala 259:74] - wire _T_889 = _T_888 ^ dccm_wdata_lo_any[25]; // @[el2_lib.scala 259:74] - wire _T_905 = dccm_wdata_lo_any[11] ^ dccm_wdata_lo_any[12]; // @[el2_lib.scala 259:74] - wire _T_906 = _T_905 ^ dccm_wdata_lo_any[13]; // @[el2_lib.scala 259:74] - wire _T_907 = _T_906 ^ dccm_wdata_lo_any[14]; // @[el2_lib.scala 259:74] - wire _T_908 = _T_907 ^ dccm_wdata_lo_any[15]; // @[el2_lib.scala 259:74] - wire _T_909 = _T_908 ^ dccm_wdata_lo_any[16]; // @[el2_lib.scala 259:74] - wire _T_910 = _T_909 ^ dccm_wdata_lo_any[17]; // @[el2_lib.scala 259:74] - wire _T_911 = _T_910 ^ dccm_wdata_lo_any[18]; // @[el2_lib.scala 259:74] - wire _T_912 = _T_911 ^ dccm_wdata_lo_any[19]; // @[el2_lib.scala 259:74] - wire _T_913 = _T_912 ^ dccm_wdata_lo_any[20]; // @[el2_lib.scala 259:74] - wire _T_914 = _T_913 ^ dccm_wdata_lo_any[21]; // @[el2_lib.scala 259:74] - wire _T_915 = _T_914 ^ dccm_wdata_lo_any[22]; // @[el2_lib.scala 259:74] - wire _T_916 = _T_915 ^ dccm_wdata_lo_any[23]; // @[el2_lib.scala 259:74] - wire _T_917 = _T_916 ^ dccm_wdata_lo_any[24]; // @[el2_lib.scala 259:74] - wire _T_918 = _T_917 ^ dccm_wdata_lo_any[25]; // @[el2_lib.scala 259:74] - wire _T_925 = dccm_wdata_lo_any[26] ^ dccm_wdata_lo_any[27]; // @[el2_lib.scala 259:74] - wire _T_926 = _T_925 ^ dccm_wdata_lo_any[28]; // @[el2_lib.scala 259:74] - wire _T_927 = _T_926 ^ dccm_wdata_lo_any[29]; // @[el2_lib.scala 259:74] - wire _T_928 = _T_927 ^ dccm_wdata_lo_any[30]; // @[el2_lib.scala 259:74] - wire _T_929 = _T_928 ^ dccm_wdata_lo_any[31]; // @[el2_lib.scala 259:74] + wire _T_774 = dccm_wdata_lo_any[0] ^ dccm_wdata_lo_any[1]; // @[lib.scala 119:74] + wire _T_775 = _T_774 ^ dccm_wdata_lo_any[3]; // @[lib.scala 119:74] + wire _T_776 = _T_775 ^ dccm_wdata_lo_any[4]; // @[lib.scala 119:74] + wire _T_777 = _T_776 ^ dccm_wdata_lo_any[6]; // @[lib.scala 119:74] + wire _T_778 = _T_777 ^ dccm_wdata_lo_any[8]; // @[lib.scala 119:74] + wire _T_779 = _T_778 ^ dccm_wdata_lo_any[10]; // @[lib.scala 119:74] + wire _T_780 = _T_779 ^ dccm_wdata_lo_any[11]; // @[lib.scala 119:74] + wire _T_781 = _T_780 ^ dccm_wdata_lo_any[13]; // @[lib.scala 119:74] + wire _T_782 = _T_781 ^ dccm_wdata_lo_any[15]; // @[lib.scala 119:74] + wire _T_783 = _T_782 ^ dccm_wdata_lo_any[17]; // @[lib.scala 119:74] + wire _T_784 = _T_783 ^ dccm_wdata_lo_any[19]; // @[lib.scala 119:74] + wire _T_785 = _T_784 ^ dccm_wdata_lo_any[21]; // @[lib.scala 119:74] + wire _T_786 = _T_785 ^ dccm_wdata_lo_any[23]; // @[lib.scala 119:74] + wire _T_787 = _T_786 ^ dccm_wdata_lo_any[25]; // @[lib.scala 119:74] + wire _T_788 = _T_787 ^ dccm_wdata_lo_any[26]; // @[lib.scala 119:74] + wire _T_789 = _T_788 ^ dccm_wdata_lo_any[28]; // @[lib.scala 119:74] + wire _T_790 = _T_789 ^ dccm_wdata_lo_any[30]; // @[lib.scala 119:74] + wire _T_809 = dccm_wdata_lo_any[0] ^ dccm_wdata_lo_any[2]; // @[lib.scala 119:74] + wire _T_810 = _T_809 ^ dccm_wdata_lo_any[3]; // @[lib.scala 119:74] + wire _T_811 = _T_810 ^ dccm_wdata_lo_any[5]; // @[lib.scala 119:74] + wire _T_812 = _T_811 ^ dccm_wdata_lo_any[6]; // @[lib.scala 119:74] + wire _T_813 = _T_812 ^ dccm_wdata_lo_any[9]; // @[lib.scala 119:74] + wire _T_814 = _T_813 ^ dccm_wdata_lo_any[10]; // @[lib.scala 119:74] + wire _T_815 = _T_814 ^ dccm_wdata_lo_any[12]; // @[lib.scala 119:74] + wire _T_816 = _T_815 ^ dccm_wdata_lo_any[13]; // @[lib.scala 119:74] + wire _T_817 = _T_816 ^ dccm_wdata_lo_any[16]; // @[lib.scala 119:74] + wire _T_818 = _T_817 ^ dccm_wdata_lo_any[17]; // @[lib.scala 119:74] + wire _T_819 = _T_818 ^ dccm_wdata_lo_any[20]; // @[lib.scala 119:74] + wire _T_820 = _T_819 ^ dccm_wdata_lo_any[21]; // @[lib.scala 119:74] + wire _T_821 = _T_820 ^ dccm_wdata_lo_any[24]; // @[lib.scala 119:74] + wire _T_822 = _T_821 ^ dccm_wdata_lo_any[25]; // @[lib.scala 119:74] + wire _T_823 = _T_822 ^ dccm_wdata_lo_any[27]; // @[lib.scala 119:74] + wire _T_824 = _T_823 ^ dccm_wdata_lo_any[28]; // @[lib.scala 119:74] + wire _T_825 = _T_824 ^ dccm_wdata_lo_any[31]; // @[lib.scala 119:74] + wire _T_844 = dccm_wdata_lo_any[1] ^ dccm_wdata_lo_any[2]; // @[lib.scala 119:74] + wire _T_845 = _T_844 ^ dccm_wdata_lo_any[3]; // @[lib.scala 119:74] + wire _T_846 = _T_845 ^ dccm_wdata_lo_any[7]; // @[lib.scala 119:74] + wire _T_847 = _T_846 ^ dccm_wdata_lo_any[8]; // @[lib.scala 119:74] + wire _T_848 = _T_847 ^ dccm_wdata_lo_any[9]; // @[lib.scala 119:74] + wire _T_849 = _T_848 ^ dccm_wdata_lo_any[10]; // @[lib.scala 119:74] + wire _T_850 = _T_849 ^ dccm_wdata_lo_any[14]; // @[lib.scala 119:74] + wire _T_851 = _T_850 ^ dccm_wdata_lo_any[15]; // @[lib.scala 119:74] + wire _T_852 = _T_851 ^ dccm_wdata_lo_any[16]; // @[lib.scala 119:74] + wire _T_853 = _T_852 ^ dccm_wdata_lo_any[17]; // @[lib.scala 119:74] + wire _T_854 = _T_853 ^ dccm_wdata_lo_any[22]; // @[lib.scala 119:74] + wire _T_855 = _T_854 ^ dccm_wdata_lo_any[23]; // @[lib.scala 119:74] + wire _T_856 = _T_855 ^ dccm_wdata_lo_any[24]; // @[lib.scala 119:74] + wire _T_857 = _T_856 ^ dccm_wdata_lo_any[25]; // @[lib.scala 119:74] + wire _T_858 = _T_857 ^ dccm_wdata_lo_any[29]; // @[lib.scala 119:74] + wire _T_859 = _T_858 ^ dccm_wdata_lo_any[30]; // @[lib.scala 119:74] + wire _T_860 = _T_859 ^ dccm_wdata_lo_any[31]; // @[lib.scala 119:74] + wire _T_876 = dccm_wdata_lo_any[4] ^ dccm_wdata_lo_any[5]; // @[lib.scala 119:74] + wire _T_877 = _T_876 ^ dccm_wdata_lo_any[6]; // @[lib.scala 119:74] + wire _T_878 = _T_877 ^ dccm_wdata_lo_any[7]; // @[lib.scala 119:74] + wire _T_879 = _T_878 ^ dccm_wdata_lo_any[8]; // @[lib.scala 119:74] + wire _T_880 = _T_879 ^ dccm_wdata_lo_any[9]; // @[lib.scala 119:74] + wire _T_881 = _T_880 ^ dccm_wdata_lo_any[10]; // @[lib.scala 119:74] + wire _T_882 = _T_881 ^ dccm_wdata_lo_any[18]; // @[lib.scala 119:74] + wire _T_883 = _T_882 ^ dccm_wdata_lo_any[19]; // @[lib.scala 119:74] + wire _T_884 = _T_883 ^ dccm_wdata_lo_any[20]; // @[lib.scala 119:74] + wire _T_885 = _T_884 ^ dccm_wdata_lo_any[21]; // @[lib.scala 119:74] + wire _T_886 = _T_885 ^ dccm_wdata_lo_any[22]; // @[lib.scala 119:74] + wire _T_887 = _T_886 ^ dccm_wdata_lo_any[23]; // @[lib.scala 119:74] + wire _T_888 = _T_887 ^ dccm_wdata_lo_any[24]; // @[lib.scala 119:74] + wire _T_889 = _T_888 ^ dccm_wdata_lo_any[25]; // @[lib.scala 119:74] + wire _T_905 = dccm_wdata_lo_any[11] ^ dccm_wdata_lo_any[12]; // @[lib.scala 119:74] + wire _T_906 = _T_905 ^ dccm_wdata_lo_any[13]; // @[lib.scala 119:74] + wire _T_907 = _T_906 ^ dccm_wdata_lo_any[14]; // @[lib.scala 119:74] + wire _T_908 = _T_907 ^ dccm_wdata_lo_any[15]; // @[lib.scala 119:74] + wire _T_909 = _T_908 ^ dccm_wdata_lo_any[16]; // @[lib.scala 119:74] + wire _T_910 = _T_909 ^ dccm_wdata_lo_any[17]; // @[lib.scala 119:74] + wire _T_911 = _T_910 ^ dccm_wdata_lo_any[18]; // @[lib.scala 119:74] + wire _T_912 = _T_911 ^ dccm_wdata_lo_any[19]; // @[lib.scala 119:74] + wire _T_913 = _T_912 ^ dccm_wdata_lo_any[20]; // @[lib.scala 119:74] + wire _T_914 = _T_913 ^ dccm_wdata_lo_any[21]; // @[lib.scala 119:74] + wire _T_915 = _T_914 ^ dccm_wdata_lo_any[22]; // @[lib.scala 119:74] + wire _T_916 = _T_915 ^ dccm_wdata_lo_any[23]; // @[lib.scala 119:74] + wire _T_917 = _T_916 ^ dccm_wdata_lo_any[24]; // @[lib.scala 119:74] + wire _T_918 = _T_917 ^ dccm_wdata_lo_any[25]; // @[lib.scala 119:74] + wire _T_925 = dccm_wdata_lo_any[26] ^ dccm_wdata_lo_any[27]; // @[lib.scala 119:74] + wire _T_926 = _T_925 ^ dccm_wdata_lo_any[28]; // @[lib.scala 119:74] + wire _T_927 = _T_926 ^ dccm_wdata_lo_any[29]; // @[lib.scala 119:74] + wire _T_928 = _T_927 ^ dccm_wdata_lo_any[30]; // @[lib.scala 119:74] + wire _T_929 = _T_928 ^ dccm_wdata_lo_any[31]; // @[lib.scala 119:74] wire [5:0] _T_934 = {_T_929,_T_918,_T_889,_T_860,_T_825,_T_790}; // @[Cat.scala 29:58] - wire _T_935 = ^dccm_wdata_lo_any; // @[el2_lib.scala 267:13] - wire _T_936 = ^_T_934; // @[el2_lib.scala 267:23] - wire _T_937 = _T_935 ^ _T_936; // @[el2_lib.scala 267:18] + wire _T_935 = ^dccm_wdata_lo_any; // @[lib.scala 127:13] + wire _T_936 = ^_T_934; // @[lib.scala 127:23] + wire _T_937 = _T_935 ^ _T_936; // @[lib.scala 127:18] wire [31:0] _T_1162 = io_dma_dccm_wen ? io_dma_dccm_wdata_hi : io_stbuf_data_any; // @[lsu_ecc.scala 150:87] wire [31:0] dccm_wdata_hi_any = io_ld_single_ecc_error_r_ff ? io_sec_data_hi_r_ff : _T_1162; // @[lsu_ecc.scala 150:27] - wire _T_956 = dccm_wdata_hi_any[0] ^ dccm_wdata_hi_any[1]; // @[el2_lib.scala 259:74] - wire _T_957 = _T_956 ^ dccm_wdata_hi_any[3]; // @[el2_lib.scala 259:74] - wire _T_958 = _T_957 ^ dccm_wdata_hi_any[4]; // @[el2_lib.scala 259:74] - wire _T_959 = _T_958 ^ dccm_wdata_hi_any[6]; // @[el2_lib.scala 259:74] - wire _T_960 = _T_959 ^ dccm_wdata_hi_any[8]; // @[el2_lib.scala 259:74] - wire _T_961 = _T_960 ^ dccm_wdata_hi_any[10]; // @[el2_lib.scala 259:74] - wire _T_962 = _T_961 ^ dccm_wdata_hi_any[11]; // @[el2_lib.scala 259:74] - wire _T_963 = _T_962 ^ dccm_wdata_hi_any[13]; // @[el2_lib.scala 259:74] - wire _T_964 = _T_963 ^ dccm_wdata_hi_any[15]; // @[el2_lib.scala 259:74] - wire _T_965 = _T_964 ^ dccm_wdata_hi_any[17]; // @[el2_lib.scala 259:74] - wire _T_966 = _T_965 ^ dccm_wdata_hi_any[19]; // @[el2_lib.scala 259:74] - wire _T_967 = _T_966 ^ dccm_wdata_hi_any[21]; // @[el2_lib.scala 259:74] - wire _T_968 = _T_967 ^ dccm_wdata_hi_any[23]; // @[el2_lib.scala 259:74] - wire _T_969 = _T_968 ^ dccm_wdata_hi_any[25]; // @[el2_lib.scala 259:74] - wire _T_970 = _T_969 ^ dccm_wdata_hi_any[26]; // @[el2_lib.scala 259:74] - wire _T_971 = _T_970 ^ dccm_wdata_hi_any[28]; // @[el2_lib.scala 259:74] - wire _T_972 = _T_971 ^ dccm_wdata_hi_any[30]; // @[el2_lib.scala 259:74] - wire _T_991 = dccm_wdata_hi_any[0] ^ dccm_wdata_hi_any[2]; // @[el2_lib.scala 259:74] - wire _T_992 = _T_991 ^ dccm_wdata_hi_any[3]; // @[el2_lib.scala 259:74] - wire _T_993 = _T_992 ^ dccm_wdata_hi_any[5]; // @[el2_lib.scala 259:74] - wire _T_994 = _T_993 ^ dccm_wdata_hi_any[6]; // @[el2_lib.scala 259:74] - wire _T_995 = _T_994 ^ dccm_wdata_hi_any[9]; // @[el2_lib.scala 259:74] - wire _T_996 = _T_995 ^ dccm_wdata_hi_any[10]; // @[el2_lib.scala 259:74] - wire _T_997 = _T_996 ^ dccm_wdata_hi_any[12]; // @[el2_lib.scala 259:74] - wire _T_998 = _T_997 ^ dccm_wdata_hi_any[13]; // @[el2_lib.scala 259:74] - wire _T_999 = _T_998 ^ dccm_wdata_hi_any[16]; // @[el2_lib.scala 259:74] - wire _T_1000 = _T_999 ^ dccm_wdata_hi_any[17]; // @[el2_lib.scala 259:74] - wire _T_1001 = _T_1000 ^ dccm_wdata_hi_any[20]; // @[el2_lib.scala 259:74] - wire _T_1002 = _T_1001 ^ dccm_wdata_hi_any[21]; // @[el2_lib.scala 259:74] - wire _T_1003 = _T_1002 ^ dccm_wdata_hi_any[24]; // @[el2_lib.scala 259:74] - wire _T_1004 = _T_1003 ^ dccm_wdata_hi_any[25]; // @[el2_lib.scala 259:74] - wire _T_1005 = _T_1004 ^ dccm_wdata_hi_any[27]; // @[el2_lib.scala 259:74] - wire _T_1006 = _T_1005 ^ dccm_wdata_hi_any[28]; // @[el2_lib.scala 259:74] - wire _T_1007 = _T_1006 ^ dccm_wdata_hi_any[31]; // @[el2_lib.scala 259:74] - wire _T_1026 = dccm_wdata_hi_any[1] ^ dccm_wdata_hi_any[2]; // @[el2_lib.scala 259:74] - wire _T_1027 = _T_1026 ^ dccm_wdata_hi_any[3]; // @[el2_lib.scala 259:74] - wire _T_1028 = _T_1027 ^ dccm_wdata_hi_any[7]; // @[el2_lib.scala 259:74] - wire _T_1029 = _T_1028 ^ dccm_wdata_hi_any[8]; // @[el2_lib.scala 259:74] - wire _T_1030 = _T_1029 ^ dccm_wdata_hi_any[9]; // @[el2_lib.scala 259:74] - wire _T_1031 = _T_1030 ^ dccm_wdata_hi_any[10]; // @[el2_lib.scala 259:74] - wire _T_1032 = _T_1031 ^ dccm_wdata_hi_any[14]; // @[el2_lib.scala 259:74] - wire _T_1033 = _T_1032 ^ dccm_wdata_hi_any[15]; // @[el2_lib.scala 259:74] - wire _T_1034 = _T_1033 ^ dccm_wdata_hi_any[16]; // @[el2_lib.scala 259:74] - wire _T_1035 = _T_1034 ^ dccm_wdata_hi_any[17]; // @[el2_lib.scala 259:74] - wire _T_1036 = _T_1035 ^ dccm_wdata_hi_any[22]; // @[el2_lib.scala 259:74] - wire _T_1037 = _T_1036 ^ dccm_wdata_hi_any[23]; // @[el2_lib.scala 259:74] - wire _T_1038 = _T_1037 ^ dccm_wdata_hi_any[24]; // @[el2_lib.scala 259:74] - wire _T_1039 = _T_1038 ^ dccm_wdata_hi_any[25]; // @[el2_lib.scala 259:74] - wire _T_1040 = _T_1039 ^ dccm_wdata_hi_any[29]; // @[el2_lib.scala 259:74] - wire _T_1041 = _T_1040 ^ dccm_wdata_hi_any[30]; // @[el2_lib.scala 259:74] - wire _T_1042 = _T_1041 ^ dccm_wdata_hi_any[31]; // @[el2_lib.scala 259:74] - wire _T_1058 = dccm_wdata_hi_any[4] ^ dccm_wdata_hi_any[5]; // @[el2_lib.scala 259:74] - wire _T_1059 = _T_1058 ^ dccm_wdata_hi_any[6]; // @[el2_lib.scala 259:74] - wire _T_1060 = _T_1059 ^ dccm_wdata_hi_any[7]; // @[el2_lib.scala 259:74] - wire _T_1061 = _T_1060 ^ dccm_wdata_hi_any[8]; // @[el2_lib.scala 259:74] - wire _T_1062 = _T_1061 ^ dccm_wdata_hi_any[9]; // @[el2_lib.scala 259:74] - wire _T_1063 = _T_1062 ^ dccm_wdata_hi_any[10]; // @[el2_lib.scala 259:74] - wire _T_1064 = _T_1063 ^ dccm_wdata_hi_any[18]; // @[el2_lib.scala 259:74] - wire _T_1065 = _T_1064 ^ dccm_wdata_hi_any[19]; // @[el2_lib.scala 259:74] - wire _T_1066 = _T_1065 ^ dccm_wdata_hi_any[20]; // @[el2_lib.scala 259:74] - wire _T_1067 = _T_1066 ^ dccm_wdata_hi_any[21]; // @[el2_lib.scala 259:74] - wire _T_1068 = _T_1067 ^ dccm_wdata_hi_any[22]; // @[el2_lib.scala 259:74] - wire _T_1069 = _T_1068 ^ dccm_wdata_hi_any[23]; // @[el2_lib.scala 259:74] - wire _T_1070 = _T_1069 ^ dccm_wdata_hi_any[24]; // @[el2_lib.scala 259:74] - wire _T_1071 = _T_1070 ^ dccm_wdata_hi_any[25]; // @[el2_lib.scala 259:74] - wire _T_1087 = dccm_wdata_hi_any[11] ^ dccm_wdata_hi_any[12]; // @[el2_lib.scala 259:74] - wire _T_1088 = _T_1087 ^ dccm_wdata_hi_any[13]; // @[el2_lib.scala 259:74] - wire _T_1089 = _T_1088 ^ dccm_wdata_hi_any[14]; // @[el2_lib.scala 259:74] - wire _T_1090 = _T_1089 ^ dccm_wdata_hi_any[15]; // @[el2_lib.scala 259:74] - wire _T_1091 = _T_1090 ^ dccm_wdata_hi_any[16]; // @[el2_lib.scala 259:74] - wire _T_1092 = _T_1091 ^ dccm_wdata_hi_any[17]; // @[el2_lib.scala 259:74] - wire _T_1093 = _T_1092 ^ dccm_wdata_hi_any[18]; // @[el2_lib.scala 259:74] - wire _T_1094 = _T_1093 ^ dccm_wdata_hi_any[19]; // @[el2_lib.scala 259:74] - wire _T_1095 = _T_1094 ^ dccm_wdata_hi_any[20]; // @[el2_lib.scala 259:74] - wire _T_1096 = _T_1095 ^ dccm_wdata_hi_any[21]; // @[el2_lib.scala 259:74] - wire _T_1097 = _T_1096 ^ dccm_wdata_hi_any[22]; // @[el2_lib.scala 259:74] - wire _T_1098 = _T_1097 ^ dccm_wdata_hi_any[23]; // @[el2_lib.scala 259:74] - wire _T_1099 = _T_1098 ^ dccm_wdata_hi_any[24]; // @[el2_lib.scala 259:74] - wire _T_1100 = _T_1099 ^ dccm_wdata_hi_any[25]; // @[el2_lib.scala 259:74] - wire _T_1107 = dccm_wdata_hi_any[26] ^ dccm_wdata_hi_any[27]; // @[el2_lib.scala 259:74] - wire _T_1108 = _T_1107 ^ dccm_wdata_hi_any[28]; // @[el2_lib.scala 259:74] - wire _T_1109 = _T_1108 ^ dccm_wdata_hi_any[29]; // @[el2_lib.scala 259:74] - wire _T_1110 = _T_1109 ^ dccm_wdata_hi_any[30]; // @[el2_lib.scala 259:74] - wire _T_1111 = _T_1110 ^ dccm_wdata_hi_any[31]; // @[el2_lib.scala 259:74] + wire _T_956 = dccm_wdata_hi_any[0] ^ dccm_wdata_hi_any[1]; // @[lib.scala 119:74] + wire _T_957 = _T_956 ^ dccm_wdata_hi_any[3]; // @[lib.scala 119:74] + wire _T_958 = _T_957 ^ dccm_wdata_hi_any[4]; // @[lib.scala 119:74] + wire _T_959 = _T_958 ^ dccm_wdata_hi_any[6]; // @[lib.scala 119:74] + wire _T_960 = _T_959 ^ dccm_wdata_hi_any[8]; // @[lib.scala 119:74] + wire _T_961 = _T_960 ^ dccm_wdata_hi_any[10]; // @[lib.scala 119:74] + wire _T_962 = _T_961 ^ dccm_wdata_hi_any[11]; // @[lib.scala 119:74] + wire _T_963 = _T_962 ^ dccm_wdata_hi_any[13]; // @[lib.scala 119:74] + wire _T_964 = _T_963 ^ dccm_wdata_hi_any[15]; // @[lib.scala 119:74] + wire _T_965 = _T_964 ^ dccm_wdata_hi_any[17]; // @[lib.scala 119:74] + wire _T_966 = _T_965 ^ dccm_wdata_hi_any[19]; // @[lib.scala 119:74] + wire _T_967 = _T_966 ^ dccm_wdata_hi_any[21]; // @[lib.scala 119:74] + wire _T_968 = _T_967 ^ dccm_wdata_hi_any[23]; // @[lib.scala 119:74] + wire _T_969 = _T_968 ^ dccm_wdata_hi_any[25]; // @[lib.scala 119:74] + wire _T_970 = _T_969 ^ dccm_wdata_hi_any[26]; // @[lib.scala 119:74] + wire _T_971 = _T_970 ^ dccm_wdata_hi_any[28]; // @[lib.scala 119:74] + wire _T_972 = _T_971 ^ dccm_wdata_hi_any[30]; // @[lib.scala 119:74] + wire _T_991 = dccm_wdata_hi_any[0] ^ dccm_wdata_hi_any[2]; // @[lib.scala 119:74] + wire _T_992 = _T_991 ^ dccm_wdata_hi_any[3]; // @[lib.scala 119:74] + wire _T_993 = _T_992 ^ dccm_wdata_hi_any[5]; // @[lib.scala 119:74] + wire _T_994 = _T_993 ^ dccm_wdata_hi_any[6]; // @[lib.scala 119:74] + wire _T_995 = _T_994 ^ dccm_wdata_hi_any[9]; // @[lib.scala 119:74] + wire _T_996 = _T_995 ^ dccm_wdata_hi_any[10]; // @[lib.scala 119:74] + wire _T_997 = _T_996 ^ dccm_wdata_hi_any[12]; // @[lib.scala 119:74] + wire _T_998 = _T_997 ^ dccm_wdata_hi_any[13]; // @[lib.scala 119:74] + wire _T_999 = _T_998 ^ dccm_wdata_hi_any[16]; // @[lib.scala 119:74] + wire _T_1000 = _T_999 ^ dccm_wdata_hi_any[17]; // @[lib.scala 119:74] + wire _T_1001 = _T_1000 ^ dccm_wdata_hi_any[20]; // @[lib.scala 119:74] + wire _T_1002 = _T_1001 ^ dccm_wdata_hi_any[21]; // @[lib.scala 119:74] + wire _T_1003 = _T_1002 ^ dccm_wdata_hi_any[24]; // @[lib.scala 119:74] + wire _T_1004 = _T_1003 ^ dccm_wdata_hi_any[25]; // @[lib.scala 119:74] + wire _T_1005 = _T_1004 ^ dccm_wdata_hi_any[27]; // @[lib.scala 119:74] + wire _T_1006 = _T_1005 ^ dccm_wdata_hi_any[28]; // @[lib.scala 119:74] + wire _T_1007 = _T_1006 ^ dccm_wdata_hi_any[31]; // @[lib.scala 119:74] + wire _T_1026 = dccm_wdata_hi_any[1] ^ dccm_wdata_hi_any[2]; // @[lib.scala 119:74] + wire _T_1027 = _T_1026 ^ dccm_wdata_hi_any[3]; // @[lib.scala 119:74] + wire _T_1028 = _T_1027 ^ dccm_wdata_hi_any[7]; // @[lib.scala 119:74] + wire _T_1029 = _T_1028 ^ dccm_wdata_hi_any[8]; // @[lib.scala 119:74] + wire _T_1030 = _T_1029 ^ dccm_wdata_hi_any[9]; // @[lib.scala 119:74] + wire _T_1031 = _T_1030 ^ dccm_wdata_hi_any[10]; // @[lib.scala 119:74] + wire _T_1032 = _T_1031 ^ dccm_wdata_hi_any[14]; // @[lib.scala 119:74] + wire _T_1033 = _T_1032 ^ dccm_wdata_hi_any[15]; // @[lib.scala 119:74] + wire _T_1034 = _T_1033 ^ dccm_wdata_hi_any[16]; // @[lib.scala 119:74] + wire _T_1035 = _T_1034 ^ dccm_wdata_hi_any[17]; // @[lib.scala 119:74] + wire _T_1036 = _T_1035 ^ dccm_wdata_hi_any[22]; // @[lib.scala 119:74] + wire _T_1037 = _T_1036 ^ dccm_wdata_hi_any[23]; // @[lib.scala 119:74] + wire _T_1038 = _T_1037 ^ dccm_wdata_hi_any[24]; // @[lib.scala 119:74] + wire _T_1039 = _T_1038 ^ dccm_wdata_hi_any[25]; // @[lib.scala 119:74] + wire _T_1040 = _T_1039 ^ dccm_wdata_hi_any[29]; // @[lib.scala 119:74] + wire _T_1041 = _T_1040 ^ dccm_wdata_hi_any[30]; // @[lib.scala 119:74] + wire _T_1042 = _T_1041 ^ dccm_wdata_hi_any[31]; // @[lib.scala 119:74] + wire _T_1058 = dccm_wdata_hi_any[4] ^ dccm_wdata_hi_any[5]; // @[lib.scala 119:74] + wire _T_1059 = _T_1058 ^ dccm_wdata_hi_any[6]; // @[lib.scala 119:74] + wire _T_1060 = _T_1059 ^ dccm_wdata_hi_any[7]; // @[lib.scala 119:74] + wire _T_1061 = _T_1060 ^ dccm_wdata_hi_any[8]; // @[lib.scala 119:74] + wire _T_1062 = _T_1061 ^ dccm_wdata_hi_any[9]; // @[lib.scala 119:74] + wire _T_1063 = _T_1062 ^ dccm_wdata_hi_any[10]; // @[lib.scala 119:74] + wire _T_1064 = _T_1063 ^ dccm_wdata_hi_any[18]; // @[lib.scala 119:74] + wire _T_1065 = _T_1064 ^ dccm_wdata_hi_any[19]; // @[lib.scala 119:74] + wire _T_1066 = _T_1065 ^ dccm_wdata_hi_any[20]; // @[lib.scala 119:74] + wire _T_1067 = _T_1066 ^ dccm_wdata_hi_any[21]; // @[lib.scala 119:74] + wire _T_1068 = _T_1067 ^ dccm_wdata_hi_any[22]; // @[lib.scala 119:74] + wire _T_1069 = _T_1068 ^ dccm_wdata_hi_any[23]; // @[lib.scala 119:74] + wire _T_1070 = _T_1069 ^ dccm_wdata_hi_any[24]; // @[lib.scala 119:74] + wire _T_1071 = _T_1070 ^ dccm_wdata_hi_any[25]; // @[lib.scala 119:74] + wire _T_1087 = dccm_wdata_hi_any[11] ^ dccm_wdata_hi_any[12]; // @[lib.scala 119:74] + wire _T_1088 = _T_1087 ^ dccm_wdata_hi_any[13]; // @[lib.scala 119:74] + wire _T_1089 = _T_1088 ^ dccm_wdata_hi_any[14]; // @[lib.scala 119:74] + wire _T_1090 = _T_1089 ^ dccm_wdata_hi_any[15]; // @[lib.scala 119:74] + wire _T_1091 = _T_1090 ^ dccm_wdata_hi_any[16]; // @[lib.scala 119:74] + wire _T_1092 = _T_1091 ^ dccm_wdata_hi_any[17]; // @[lib.scala 119:74] + wire _T_1093 = _T_1092 ^ dccm_wdata_hi_any[18]; // @[lib.scala 119:74] + wire _T_1094 = _T_1093 ^ dccm_wdata_hi_any[19]; // @[lib.scala 119:74] + wire _T_1095 = _T_1094 ^ dccm_wdata_hi_any[20]; // @[lib.scala 119:74] + wire _T_1096 = _T_1095 ^ dccm_wdata_hi_any[21]; // @[lib.scala 119:74] + wire _T_1097 = _T_1096 ^ dccm_wdata_hi_any[22]; // @[lib.scala 119:74] + wire _T_1098 = _T_1097 ^ dccm_wdata_hi_any[23]; // @[lib.scala 119:74] + wire _T_1099 = _T_1098 ^ dccm_wdata_hi_any[24]; // @[lib.scala 119:74] + wire _T_1100 = _T_1099 ^ dccm_wdata_hi_any[25]; // @[lib.scala 119:74] + wire _T_1107 = dccm_wdata_hi_any[26] ^ dccm_wdata_hi_any[27]; // @[lib.scala 119:74] + wire _T_1108 = _T_1107 ^ dccm_wdata_hi_any[28]; // @[lib.scala 119:74] + wire _T_1109 = _T_1108 ^ dccm_wdata_hi_any[29]; // @[lib.scala 119:74] + wire _T_1110 = _T_1109 ^ dccm_wdata_hi_any[30]; // @[lib.scala 119:74] + wire _T_1111 = _T_1110 ^ dccm_wdata_hi_any[31]; // @[lib.scala 119:74] wire [5:0] _T_1116 = {_T_1111,_T_1100,_T_1071,_T_1042,_T_1007,_T_972}; // @[Cat.scala 29:58] - wire _T_1117 = ^dccm_wdata_hi_any; // @[el2_lib.scala 267:13] - wire _T_1118 = ^_T_1116; // @[el2_lib.scala 267:23] - wire _T_1119 = _T_1117 ^ _T_1118; // @[el2_lib.scala 267:18] + wire _T_1117 = ^dccm_wdata_hi_any; // @[lib.scala 127:13] + wire _T_1118 = ^_T_1116; // @[lib.scala 127:23] + wire _T_1119 = _T_1117 ^ _T_1118; // @[lib.scala 127:18] reg _T_1150; // @[lsu_ecc.scala 141:72] reg _T_1151; // @[lsu_ecc.scala 142:72] reg _T_1152; // @[lsu_ecc.scala 143:72] reg _T_1153; // @[lsu_ecc.scala 144:72] reg [31:0] _T_1154; // @[lsu_ecc.scala 145:72] reg [31:0] _T_1155; // @[lsu_ecc.scala 146:72] - reg [31:0] _T_1164; // @[el2_lib.scala 514:16] - reg [31:0] _T_1165; // @[el2_lib.scala 514:16] - rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] + reg [31:0] _T_1164; // @[lib.scala 374:16] + reg [31:0] _T_1165; // @[lib.scala 374:16] + rvclkhdr rvclkhdr ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en), .io_scan_mode(rvclkhdr_io_scan_mode) ); - rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_1 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_1_io_l1clk), .io_clk(rvclkhdr_1_io_clk), .io_en(rvclkhdr_1_io_en), @@ -66997,12 +66993,12 @@ module lsu_ecc( assign io_lsu_double_ecc_error_r = _T_1151; // @[lsu_ecc.scala 121:31 lsu_ecc.scala 142:62] assign io_lsu_single_ecc_error_m = single_ecc_error_hi_any | single_ecc_error_lo_any; // @[lsu_ecc.scala 92:30 lsu_ecc.scala 138:33] assign io_lsu_double_ecc_error_m = double_ecc_error_hi_any | double_ecc_error_lo_any; // @[lsu_ecc.scala 93:30 lsu_ecc.scala 139:33] - assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_io_en = io_ld_single_ecc_error_r; // @[el2_lib.scala 511:17] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_1_io_en = io_ld_single_ecc_error_r; // @[el2_lib.scala 511:17] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_io_en = io_ld_single_ecc_error_r; // @[lib.scala 371:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_1_io_en = io_ld_single_ecc_error_r; // @[lib.scala 371:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -67206,560 +67202,560 @@ module lsu_trigger( wire _T_44 = _T_42 & _T_12; // @[lsu_trigger.scala 19:58] wire _T_45 = _T_41 | _T_44; // @[lsu_trigger.scala 18:152] wire _T_46 = _T_40 & _T_45; // @[lsu_trigger.scala 18:94] - wire _T_49 = &io_trigger_pkt_any_0_tdata2; // @[el2_lib.scala 241:45] - wire _T_50 = ~_T_49; // @[el2_lib.scala 241:39] - wire _T_51 = io_trigger_pkt_any_0_match_pkt & _T_50; // @[el2_lib.scala 241:37] - wire _T_54 = io_trigger_pkt_any_0_tdata2[0] == lsu_match_data_0[0]; // @[el2_lib.scala 242:52] - wire _T_55 = _T_51 | _T_54; // @[el2_lib.scala 242:41] - wire _T_57 = &io_trigger_pkt_any_0_tdata2[0]; // @[el2_lib.scala 244:36] - wire _T_58 = _T_57 & _T_51; // @[el2_lib.scala 244:41] - wire _T_61 = io_trigger_pkt_any_0_tdata2[1] == lsu_match_data_0[1]; // @[el2_lib.scala 244:78] - wire _T_62 = _T_58 | _T_61; // @[el2_lib.scala 244:23] - wire _T_64 = &io_trigger_pkt_any_0_tdata2[1:0]; // @[el2_lib.scala 244:36] - wire _T_65 = _T_64 & _T_51; // @[el2_lib.scala 244:41] - wire _T_68 = io_trigger_pkt_any_0_tdata2[2] == lsu_match_data_0[2]; // @[el2_lib.scala 244:78] - wire _T_69 = _T_65 | _T_68; // @[el2_lib.scala 244:23] - wire _T_71 = &io_trigger_pkt_any_0_tdata2[2:0]; // @[el2_lib.scala 244:36] - wire _T_72 = _T_71 & _T_51; // @[el2_lib.scala 244:41] - wire _T_75 = io_trigger_pkt_any_0_tdata2[3] == lsu_match_data_0[3]; // @[el2_lib.scala 244:78] - wire _T_76 = _T_72 | _T_75; // @[el2_lib.scala 244:23] - wire _T_78 = &io_trigger_pkt_any_0_tdata2[3:0]; // @[el2_lib.scala 244:36] - wire _T_79 = _T_78 & _T_51; // @[el2_lib.scala 244:41] - wire _T_82 = io_trigger_pkt_any_0_tdata2[4] == lsu_match_data_0[4]; // @[el2_lib.scala 244:78] - wire _T_83 = _T_79 | _T_82; // @[el2_lib.scala 244:23] - wire _T_85 = &io_trigger_pkt_any_0_tdata2[4:0]; // @[el2_lib.scala 244:36] - wire _T_86 = _T_85 & _T_51; // @[el2_lib.scala 244:41] - wire _T_89 = io_trigger_pkt_any_0_tdata2[5] == lsu_match_data_0[5]; // @[el2_lib.scala 244:78] - wire _T_90 = _T_86 | _T_89; // @[el2_lib.scala 244:23] - wire _T_92 = &io_trigger_pkt_any_0_tdata2[5:0]; // @[el2_lib.scala 244:36] - wire _T_93 = _T_92 & _T_51; // @[el2_lib.scala 244:41] - wire _T_96 = io_trigger_pkt_any_0_tdata2[6] == lsu_match_data_0[6]; // @[el2_lib.scala 244:78] - wire _T_97 = _T_93 | _T_96; // @[el2_lib.scala 244:23] - wire _T_99 = &io_trigger_pkt_any_0_tdata2[6:0]; // @[el2_lib.scala 244:36] - wire _T_100 = _T_99 & _T_51; // @[el2_lib.scala 244:41] - wire _T_103 = io_trigger_pkt_any_0_tdata2[7] == lsu_match_data_0[7]; // @[el2_lib.scala 244:78] - wire _T_104 = _T_100 | _T_103; // @[el2_lib.scala 244:23] - wire _T_106 = &io_trigger_pkt_any_0_tdata2[7:0]; // @[el2_lib.scala 244:36] - wire _T_107 = _T_106 & _T_51; // @[el2_lib.scala 244:41] - wire _T_110 = io_trigger_pkt_any_0_tdata2[8] == lsu_match_data_0[8]; // @[el2_lib.scala 244:78] - wire _T_111 = _T_107 | _T_110; // @[el2_lib.scala 244:23] - wire _T_113 = &io_trigger_pkt_any_0_tdata2[8:0]; // @[el2_lib.scala 244:36] - wire _T_114 = _T_113 & _T_51; // @[el2_lib.scala 244:41] - wire _T_117 = io_trigger_pkt_any_0_tdata2[9] == lsu_match_data_0[9]; // @[el2_lib.scala 244:78] - wire _T_118 = _T_114 | _T_117; // @[el2_lib.scala 244:23] - wire _T_120 = &io_trigger_pkt_any_0_tdata2[9:0]; // @[el2_lib.scala 244:36] - wire _T_121 = _T_120 & _T_51; // @[el2_lib.scala 244:41] - wire _T_124 = io_trigger_pkt_any_0_tdata2[10] == lsu_match_data_0[10]; // @[el2_lib.scala 244:78] - wire _T_125 = _T_121 | _T_124; // @[el2_lib.scala 244:23] - wire _T_127 = &io_trigger_pkt_any_0_tdata2[10:0]; // @[el2_lib.scala 244:36] - wire _T_128 = _T_127 & _T_51; // @[el2_lib.scala 244:41] - wire _T_131 = io_trigger_pkt_any_0_tdata2[11] == lsu_match_data_0[11]; // @[el2_lib.scala 244:78] - wire _T_132 = _T_128 | _T_131; // @[el2_lib.scala 244:23] - wire _T_134 = &io_trigger_pkt_any_0_tdata2[11:0]; // @[el2_lib.scala 244:36] - wire _T_135 = _T_134 & _T_51; // @[el2_lib.scala 244:41] - wire _T_138 = io_trigger_pkt_any_0_tdata2[12] == lsu_match_data_0[12]; // @[el2_lib.scala 244:78] - wire _T_139 = _T_135 | _T_138; // @[el2_lib.scala 244:23] - wire _T_141 = &io_trigger_pkt_any_0_tdata2[12:0]; // @[el2_lib.scala 244:36] - wire _T_142 = _T_141 & _T_51; // @[el2_lib.scala 244:41] - wire _T_145 = io_trigger_pkt_any_0_tdata2[13] == lsu_match_data_0[13]; // @[el2_lib.scala 244:78] - wire _T_146 = _T_142 | _T_145; // @[el2_lib.scala 244:23] - wire _T_148 = &io_trigger_pkt_any_0_tdata2[13:0]; // @[el2_lib.scala 244:36] - wire _T_149 = _T_148 & _T_51; // @[el2_lib.scala 244:41] - wire _T_152 = io_trigger_pkt_any_0_tdata2[14] == lsu_match_data_0[14]; // @[el2_lib.scala 244:78] - wire _T_153 = _T_149 | _T_152; // @[el2_lib.scala 244:23] - wire _T_155 = &io_trigger_pkt_any_0_tdata2[14:0]; // @[el2_lib.scala 244:36] - wire _T_156 = _T_155 & _T_51; // @[el2_lib.scala 244:41] - wire _T_159 = io_trigger_pkt_any_0_tdata2[15] == lsu_match_data_0[15]; // @[el2_lib.scala 244:78] - wire _T_160 = _T_156 | _T_159; // @[el2_lib.scala 244:23] - wire _T_162 = &io_trigger_pkt_any_0_tdata2[15:0]; // @[el2_lib.scala 244:36] - wire _T_163 = _T_162 & _T_51; // @[el2_lib.scala 244:41] - wire _T_166 = io_trigger_pkt_any_0_tdata2[16] == lsu_match_data_0[16]; // @[el2_lib.scala 244:78] - wire _T_167 = _T_163 | _T_166; // @[el2_lib.scala 244:23] - wire _T_169 = &io_trigger_pkt_any_0_tdata2[16:0]; // @[el2_lib.scala 244:36] - wire _T_170 = _T_169 & _T_51; // @[el2_lib.scala 244:41] - wire _T_173 = io_trigger_pkt_any_0_tdata2[17] == lsu_match_data_0[17]; // @[el2_lib.scala 244:78] - wire _T_174 = _T_170 | _T_173; // @[el2_lib.scala 244:23] - wire _T_176 = &io_trigger_pkt_any_0_tdata2[17:0]; // @[el2_lib.scala 244:36] - wire _T_177 = _T_176 & _T_51; // @[el2_lib.scala 244:41] - wire _T_180 = io_trigger_pkt_any_0_tdata2[18] == lsu_match_data_0[18]; // @[el2_lib.scala 244:78] - wire _T_181 = _T_177 | _T_180; // @[el2_lib.scala 244:23] - wire _T_183 = &io_trigger_pkt_any_0_tdata2[18:0]; // @[el2_lib.scala 244:36] - wire _T_184 = _T_183 & _T_51; // @[el2_lib.scala 244:41] - wire _T_187 = io_trigger_pkt_any_0_tdata2[19] == lsu_match_data_0[19]; // @[el2_lib.scala 244:78] - wire _T_188 = _T_184 | _T_187; // @[el2_lib.scala 244:23] - wire _T_190 = &io_trigger_pkt_any_0_tdata2[19:0]; // @[el2_lib.scala 244:36] - wire _T_191 = _T_190 & _T_51; // @[el2_lib.scala 244:41] - wire _T_194 = io_trigger_pkt_any_0_tdata2[20] == lsu_match_data_0[20]; // @[el2_lib.scala 244:78] - wire _T_195 = _T_191 | _T_194; // @[el2_lib.scala 244:23] - wire _T_197 = &io_trigger_pkt_any_0_tdata2[20:0]; // @[el2_lib.scala 244:36] - wire _T_198 = _T_197 & _T_51; // @[el2_lib.scala 244:41] - wire _T_201 = io_trigger_pkt_any_0_tdata2[21] == lsu_match_data_0[21]; // @[el2_lib.scala 244:78] - wire _T_202 = _T_198 | _T_201; // @[el2_lib.scala 244:23] - wire _T_204 = &io_trigger_pkt_any_0_tdata2[21:0]; // @[el2_lib.scala 244:36] - wire _T_205 = _T_204 & _T_51; // @[el2_lib.scala 244:41] - wire _T_208 = io_trigger_pkt_any_0_tdata2[22] == lsu_match_data_0[22]; // @[el2_lib.scala 244:78] - wire _T_209 = _T_205 | _T_208; // @[el2_lib.scala 244:23] - wire _T_211 = &io_trigger_pkt_any_0_tdata2[22:0]; // @[el2_lib.scala 244:36] - wire _T_212 = _T_211 & _T_51; // @[el2_lib.scala 244:41] - wire _T_215 = io_trigger_pkt_any_0_tdata2[23] == lsu_match_data_0[23]; // @[el2_lib.scala 244:78] - wire _T_216 = _T_212 | _T_215; // @[el2_lib.scala 244:23] - wire _T_218 = &io_trigger_pkt_any_0_tdata2[23:0]; // @[el2_lib.scala 244:36] - wire _T_219 = _T_218 & _T_51; // @[el2_lib.scala 244:41] - wire _T_222 = io_trigger_pkt_any_0_tdata2[24] == lsu_match_data_0[24]; // @[el2_lib.scala 244:78] - wire _T_223 = _T_219 | _T_222; // @[el2_lib.scala 244:23] - wire _T_225 = &io_trigger_pkt_any_0_tdata2[24:0]; // @[el2_lib.scala 244:36] - wire _T_226 = _T_225 & _T_51; // @[el2_lib.scala 244:41] - wire _T_229 = io_trigger_pkt_any_0_tdata2[25] == lsu_match_data_0[25]; // @[el2_lib.scala 244:78] - wire _T_230 = _T_226 | _T_229; // @[el2_lib.scala 244:23] - wire _T_232 = &io_trigger_pkt_any_0_tdata2[25:0]; // @[el2_lib.scala 244:36] - wire _T_233 = _T_232 & _T_51; // @[el2_lib.scala 244:41] - wire _T_236 = io_trigger_pkt_any_0_tdata2[26] == lsu_match_data_0[26]; // @[el2_lib.scala 244:78] - wire _T_237 = _T_233 | _T_236; // @[el2_lib.scala 244:23] - wire _T_239 = &io_trigger_pkt_any_0_tdata2[26:0]; // @[el2_lib.scala 244:36] - wire _T_240 = _T_239 & _T_51; // @[el2_lib.scala 244:41] - wire _T_243 = io_trigger_pkt_any_0_tdata2[27] == lsu_match_data_0[27]; // @[el2_lib.scala 244:78] - wire _T_244 = _T_240 | _T_243; // @[el2_lib.scala 244:23] - wire _T_246 = &io_trigger_pkt_any_0_tdata2[27:0]; // @[el2_lib.scala 244:36] - wire _T_247 = _T_246 & _T_51; // @[el2_lib.scala 244:41] - wire _T_250 = io_trigger_pkt_any_0_tdata2[28] == lsu_match_data_0[28]; // @[el2_lib.scala 244:78] - wire _T_251 = _T_247 | _T_250; // @[el2_lib.scala 244:23] - wire _T_253 = &io_trigger_pkt_any_0_tdata2[28:0]; // @[el2_lib.scala 244:36] - wire _T_254 = _T_253 & _T_51; // @[el2_lib.scala 244:41] - wire _T_257 = io_trigger_pkt_any_0_tdata2[29] == lsu_match_data_0[29]; // @[el2_lib.scala 244:78] - wire _T_258 = _T_254 | _T_257; // @[el2_lib.scala 244:23] - wire _T_260 = &io_trigger_pkt_any_0_tdata2[29:0]; // @[el2_lib.scala 244:36] - wire _T_261 = _T_260 & _T_51; // @[el2_lib.scala 244:41] - wire _T_264 = io_trigger_pkt_any_0_tdata2[30] == lsu_match_data_0[30]; // @[el2_lib.scala 244:78] - wire _T_265 = _T_261 | _T_264; // @[el2_lib.scala 244:23] - wire _T_267 = &io_trigger_pkt_any_0_tdata2[30:0]; // @[el2_lib.scala 244:36] - wire _T_268 = _T_267 & _T_51; // @[el2_lib.scala 244:41] - wire _T_271 = io_trigger_pkt_any_0_tdata2[31] == lsu_match_data_0[31]; // @[el2_lib.scala 244:78] - wire _T_272 = _T_268 | _T_271; // @[el2_lib.scala 244:23] - wire [7:0] _T_279 = {_T_104,_T_97,_T_90,_T_83,_T_76,_T_69,_T_62,_T_55}; // @[el2_lib.scala 245:14] - wire [15:0] _T_287 = {_T_160,_T_153,_T_146,_T_139,_T_132,_T_125,_T_118,_T_111,_T_279}; // @[el2_lib.scala 245:14] - wire [7:0] _T_294 = {_T_216,_T_209,_T_202,_T_195,_T_188,_T_181,_T_174,_T_167}; // @[el2_lib.scala 245:14] - wire [31:0] _T_303 = {_T_272,_T_265,_T_258,_T_251,_T_244,_T_237,_T_230,_T_223,_T_294,_T_287}; // @[el2_lib.scala 245:14] - wire _T_304 = &_T_303; // @[el2_lib.scala 245:25] + wire _T_49 = &io_trigger_pkt_any_0_tdata2; // @[lib.scala 101:45] + wire _T_50 = ~_T_49; // @[lib.scala 101:39] + wire _T_51 = io_trigger_pkt_any_0_match_pkt & _T_50; // @[lib.scala 101:37] + wire _T_54 = io_trigger_pkt_any_0_tdata2[0] == lsu_match_data_0[0]; // @[lib.scala 102:52] + wire _T_55 = _T_51 | _T_54; // @[lib.scala 102:41] + wire _T_57 = &io_trigger_pkt_any_0_tdata2[0]; // @[lib.scala 104:36] + wire _T_58 = _T_57 & _T_51; // @[lib.scala 104:41] + wire _T_61 = io_trigger_pkt_any_0_tdata2[1] == lsu_match_data_0[1]; // @[lib.scala 104:78] + wire _T_62 = _T_58 | _T_61; // @[lib.scala 104:23] + wire _T_64 = &io_trigger_pkt_any_0_tdata2[1:0]; // @[lib.scala 104:36] + wire _T_65 = _T_64 & _T_51; // @[lib.scala 104:41] + wire _T_68 = io_trigger_pkt_any_0_tdata2[2] == lsu_match_data_0[2]; // @[lib.scala 104:78] + wire _T_69 = _T_65 | _T_68; // @[lib.scala 104:23] + wire _T_71 = &io_trigger_pkt_any_0_tdata2[2:0]; // @[lib.scala 104:36] + wire _T_72 = _T_71 & _T_51; // @[lib.scala 104:41] + wire _T_75 = io_trigger_pkt_any_0_tdata2[3] == lsu_match_data_0[3]; // @[lib.scala 104:78] + wire _T_76 = _T_72 | _T_75; // @[lib.scala 104:23] + wire _T_78 = &io_trigger_pkt_any_0_tdata2[3:0]; // @[lib.scala 104:36] + wire _T_79 = _T_78 & _T_51; // @[lib.scala 104:41] + wire _T_82 = io_trigger_pkt_any_0_tdata2[4] == lsu_match_data_0[4]; // @[lib.scala 104:78] + wire _T_83 = _T_79 | _T_82; // @[lib.scala 104:23] + wire _T_85 = &io_trigger_pkt_any_0_tdata2[4:0]; // @[lib.scala 104:36] + wire _T_86 = _T_85 & _T_51; // @[lib.scala 104:41] + wire _T_89 = io_trigger_pkt_any_0_tdata2[5] == lsu_match_data_0[5]; // @[lib.scala 104:78] + wire _T_90 = _T_86 | _T_89; // @[lib.scala 104:23] + wire _T_92 = &io_trigger_pkt_any_0_tdata2[5:0]; // @[lib.scala 104:36] + wire _T_93 = _T_92 & _T_51; // @[lib.scala 104:41] + wire _T_96 = io_trigger_pkt_any_0_tdata2[6] == lsu_match_data_0[6]; // @[lib.scala 104:78] + wire _T_97 = _T_93 | _T_96; // @[lib.scala 104:23] + wire _T_99 = &io_trigger_pkt_any_0_tdata2[6:0]; // @[lib.scala 104:36] + wire _T_100 = _T_99 & _T_51; // @[lib.scala 104:41] + wire _T_103 = io_trigger_pkt_any_0_tdata2[7] == lsu_match_data_0[7]; // @[lib.scala 104:78] + wire _T_104 = _T_100 | _T_103; // @[lib.scala 104:23] + wire _T_106 = &io_trigger_pkt_any_0_tdata2[7:0]; // @[lib.scala 104:36] + wire _T_107 = _T_106 & _T_51; // @[lib.scala 104:41] + wire _T_110 = io_trigger_pkt_any_0_tdata2[8] == lsu_match_data_0[8]; // @[lib.scala 104:78] + wire _T_111 = _T_107 | _T_110; // @[lib.scala 104:23] + wire _T_113 = &io_trigger_pkt_any_0_tdata2[8:0]; // @[lib.scala 104:36] + wire _T_114 = _T_113 & _T_51; // @[lib.scala 104:41] + wire _T_117 = io_trigger_pkt_any_0_tdata2[9] == lsu_match_data_0[9]; // @[lib.scala 104:78] + wire _T_118 = _T_114 | _T_117; // @[lib.scala 104:23] + wire _T_120 = &io_trigger_pkt_any_0_tdata2[9:0]; // @[lib.scala 104:36] + wire _T_121 = _T_120 & _T_51; // @[lib.scala 104:41] + wire _T_124 = io_trigger_pkt_any_0_tdata2[10] == lsu_match_data_0[10]; // @[lib.scala 104:78] + wire _T_125 = _T_121 | _T_124; // @[lib.scala 104:23] + wire _T_127 = &io_trigger_pkt_any_0_tdata2[10:0]; // @[lib.scala 104:36] + wire _T_128 = _T_127 & _T_51; // @[lib.scala 104:41] + wire _T_131 = io_trigger_pkt_any_0_tdata2[11] == lsu_match_data_0[11]; // @[lib.scala 104:78] + wire _T_132 = _T_128 | _T_131; // @[lib.scala 104:23] + wire _T_134 = &io_trigger_pkt_any_0_tdata2[11:0]; // @[lib.scala 104:36] + wire _T_135 = _T_134 & _T_51; // @[lib.scala 104:41] + wire _T_138 = io_trigger_pkt_any_0_tdata2[12] == lsu_match_data_0[12]; // @[lib.scala 104:78] + wire _T_139 = _T_135 | _T_138; // @[lib.scala 104:23] + wire _T_141 = &io_trigger_pkt_any_0_tdata2[12:0]; // @[lib.scala 104:36] + wire _T_142 = _T_141 & _T_51; // @[lib.scala 104:41] + wire _T_145 = io_trigger_pkt_any_0_tdata2[13] == lsu_match_data_0[13]; // @[lib.scala 104:78] + wire _T_146 = _T_142 | _T_145; // @[lib.scala 104:23] + wire _T_148 = &io_trigger_pkt_any_0_tdata2[13:0]; // @[lib.scala 104:36] + wire _T_149 = _T_148 & _T_51; // @[lib.scala 104:41] + wire _T_152 = io_trigger_pkt_any_0_tdata2[14] == lsu_match_data_0[14]; // @[lib.scala 104:78] + wire _T_153 = _T_149 | _T_152; // @[lib.scala 104:23] + wire _T_155 = &io_trigger_pkt_any_0_tdata2[14:0]; // @[lib.scala 104:36] + wire _T_156 = _T_155 & _T_51; // @[lib.scala 104:41] + wire _T_159 = io_trigger_pkt_any_0_tdata2[15] == lsu_match_data_0[15]; // @[lib.scala 104:78] + wire _T_160 = _T_156 | _T_159; // @[lib.scala 104:23] + wire _T_162 = &io_trigger_pkt_any_0_tdata2[15:0]; // @[lib.scala 104:36] + wire _T_163 = _T_162 & _T_51; // @[lib.scala 104:41] + wire _T_166 = io_trigger_pkt_any_0_tdata2[16] == lsu_match_data_0[16]; // @[lib.scala 104:78] + wire _T_167 = _T_163 | _T_166; // @[lib.scala 104:23] + wire _T_169 = &io_trigger_pkt_any_0_tdata2[16:0]; // @[lib.scala 104:36] + wire _T_170 = _T_169 & _T_51; // @[lib.scala 104:41] + wire _T_173 = io_trigger_pkt_any_0_tdata2[17] == lsu_match_data_0[17]; // @[lib.scala 104:78] + wire _T_174 = _T_170 | _T_173; // @[lib.scala 104:23] + wire _T_176 = &io_trigger_pkt_any_0_tdata2[17:0]; // @[lib.scala 104:36] + wire _T_177 = _T_176 & _T_51; // @[lib.scala 104:41] + wire _T_180 = io_trigger_pkt_any_0_tdata2[18] == lsu_match_data_0[18]; // @[lib.scala 104:78] + wire _T_181 = _T_177 | _T_180; // @[lib.scala 104:23] + wire _T_183 = &io_trigger_pkt_any_0_tdata2[18:0]; // @[lib.scala 104:36] + wire _T_184 = _T_183 & _T_51; // @[lib.scala 104:41] + wire _T_187 = io_trigger_pkt_any_0_tdata2[19] == lsu_match_data_0[19]; // @[lib.scala 104:78] + wire _T_188 = _T_184 | _T_187; // @[lib.scala 104:23] + wire _T_190 = &io_trigger_pkt_any_0_tdata2[19:0]; // @[lib.scala 104:36] + wire _T_191 = _T_190 & _T_51; // @[lib.scala 104:41] + wire _T_194 = io_trigger_pkt_any_0_tdata2[20] == lsu_match_data_0[20]; // @[lib.scala 104:78] + wire _T_195 = _T_191 | _T_194; // @[lib.scala 104:23] + wire _T_197 = &io_trigger_pkt_any_0_tdata2[20:0]; // @[lib.scala 104:36] + wire _T_198 = _T_197 & _T_51; // @[lib.scala 104:41] + wire _T_201 = io_trigger_pkt_any_0_tdata2[21] == lsu_match_data_0[21]; // @[lib.scala 104:78] + wire _T_202 = _T_198 | _T_201; // @[lib.scala 104:23] + wire _T_204 = &io_trigger_pkt_any_0_tdata2[21:0]; // @[lib.scala 104:36] + wire _T_205 = _T_204 & _T_51; // @[lib.scala 104:41] + wire _T_208 = io_trigger_pkt_any_0_tdata2[22] == lsu_match_data_0[22]; // @[lib.scala 104:78] + wire _T_209 = _T_205 | _T_208; // @[lib.scala 104:23] + wire _T_211 = &io_trigger_pkt_any_0_tdata2[22:0]; // @[lib.scala 104:36] + wire _T_212 = _T_211 & _T_51; // @[lib.scala 104:41] + wire _T_215 = io_trigger_pkt_any_0_tdata2[23] == lsu_match_data_0[23]; // @[lib.scala 104:78] + wire _T_216 = _T_212 | _T_215; // @[lib.scala 104:23] + wire _T_218 = &io_trigger_pkt_any_0_tdata2[23:0]; // @[lib.scala 104:36] + wire _T_219 = _T_218 & _T_51; // @[lib.scala 104:41] + wire _T_222 = io_trigger_pkt_any_0_tdata2[24] == lsu_match_data_0[24]; // @[lib.scala 104:78] + wire _T_223 = _T_219 | _T_222; // @[lib.scala 104:23] + wire _T_225 = &io_trigger_pkt_any_0_tdata2[24:0]; // @[lib.scala 104:36] + wire _T_226 = _T_225 & _T_51; // @[lib.scala 104:41] + wire _T_229 = io_trigger_pkt_any_0_tdata2[25] == lsu_match_data_0[25]; // @[lib.scala 104:78] + wire _T_230 = _T_226 | _T_229; // @[lib.scala 104:23] + wire _T_232 = &io_trigger_pkt_any_0_tdata2[25:0]; // @[lib.scala 104:36] + wire _T_233 = _T_232 & _T_51; // @[lib.scala 104:41] + wire _T_236 = io_trigger_pkt_any_0_tdata2[26] == lsu_match_data_0[26]; // @[lib.scala 104:78] + wire _T_237 = _T_233 | _T_236; // @[lib.scala 104:23] + wire _T_239 = &io_trigger_pkt_any_0_tdata2[26:0]; // @[lib.scala 104:36] + wire _T_240 = _T_239 & _T_51; // @[lib.scala 104:41] + wire _T_243 = io_trigger_pkt_any_0_tdata2[27] == lsu_match_data_0[27]; // @[lib.scala 104:78] + wire _T_244 = _T_240 | _T_243; // @[lib.scala 104:23] + wire _T_246 = &io_trigger_pkt_any_0_tdata2[27:0]; // @[lib.scala 104:36] + wire _T_247 = _T_246 & _T_51; // @[lib.scala 104:41] + wire _T_250 = io_trigger_pkt_any_0_tdata2[28] == lsu_match_data_0[28]; // @[lib.scala 104:78] + wire _T_251 = _T_247 | _T_250; // @[lib.scala 104:23] + wire _T_253 = &io_trigger_pkt_any_0_tdata2[28:0]; // @[lib.scala 104:36] + wire _T_254 = _T_253 & _T_51; // @[lib.scala 104:41] + wire _T_257 = io_trigger_pkt_any_0_tdata2[29] == lsu_match_data_0[29]; // @[lib.scala 104:78] + wire _T_258 = _T_254 | _T_257; // @[lib.scala 104:23] + wire _T_260 = &io_trigger_pkt_any_0_tdata2[29:0]; // @[lib.scala 104:36] + wire _T_261 = _T_260 & _T_51; // @[lib.scala 104:41] + wire _T_264 = io_trigger_pkt_any_0_tdata2[30] == lsu_match_data_0[30]; // @[lib.scala 104:78] + wire _T_265 = _T_261 | _T_264; // @[lib.scala 104:23] + wire _T_267 = &io_trigger_pkt_any_0_tdata2[30:0]; // @[lib.scala 104:36] + wire _T_268 = _T_267 & _T_51; // @[lib.scala 104:41] + wire _T_271 = io_trigger_pkt_any_0_tdata2[31] == lsu_match_data_0[31]; // @[lib.scala 104:78] + wire _T_272 = _T_268 | _T_271; // @[lib.scala 104:23] + wire [7:0] _T_279 = {_T_104,_T_97,_T_90,_T_83,_T_76,_T_69,_T_62,_T_55}; // @[lib.scala 105:14] + wire [15:0] _T_287 = {_T_160,_T_153,_T_146,_T_139,_T_132,_T_125,_T_118,_T_111,_T_279}; // @[lib.scala 105:14] + wire [7:0] _T_294 = {_T_216,_T_209,_T_202,_T_195,_T_188,_T_181,_T_174,_T_167}; // @[lib.scala 105:14] + wire [31:0] _T_303 = {_T_272,_T_265,_T_258,_T_251,_T_244,_T_237,_T_230,_T_223,_T_294,_T_287}; // @[lib.scala 105:14] + wire _T_304 = &_T_303; // @[lib.scala 105:25] wire _T_305 = _T_46 & _T_304; // @[lsu_trigger.scala 19:92] wire _T_308 = io_trigger_pkt_any_1_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 18:126] wire _T_309 = io_trigger_pkt_any_1_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 19:33] wire _T_311 = _T_309 & _T_19; // @[lsu_trigger.scala 19:58] wire _T_312 = _T_308 | _T_311; // @[lsu_trigger.scala 18:152] wire _T_313 = _T_40 & _T_312; // @[lsu_trigger.scala 18:94] - wire _T_316 = &io_trigger_pkt_any_1_tdata2; // @[el2_lib.scala 241:45] - wire _T_317 = ~_T_316; // @[el2_lib.scala 241:39] - wire _T_318 = io_trigger_pkt_any_1_match_pkt & _T_317; // @[el2_lib.scala 241:37] - wire _T_321 = io_trigger_pkt_any_1_tdata2[0] == lsu_match_data_1[0]; // @[el2_lib.scala 242:52] - wire _T_322 = _T_318 | _T_321; // @[el2_lib.scala 242:41] - wire _T_324 = &io_trigger_pkt_any_1_tdata2[0]; // @[el2_lib.scala 244:36] - wire _T_325 = _T_324 & _T_318; // @[el2_lib.scala 244:41] - wire _T_328 = io_trigger_pkt_any_1_tdata2[1] == lsu_match_data_1[1]; // @[el2_lib.scala 244:78] - wire _T_329 = _T_325 | _T_328; // @[el2_lib.scala 244:23] - wire _T_331 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[el2_lib.scala 244:36] - wire _T_332 = _T_331 & _T_318; // @[el2_lib.scala 244:41] - wire _T_335 = io_trigger_pkt_any_1_tdata2[2] == lsu_match_data_1[2]; // @[el2_lib.scala 244:78] - wire _T_336 = _T_332 | _T_335; // @[el2_lib.scala 244:23] - wire _T_338 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[el2_lib.scala 244:36] - wire _T_339 = _T_338 & _T_318; // @[el2_lib.scala 244:41] - wire _T_342 = io_trigger_pkt_any_1_tdata2[3] == lsu_match_data_1[3]; // @[el2_lib.scala 244:78] - wire _T_343 = _T_339 | _T_342; // @[el2_lib.scala 244:23] - wire _T_345 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[el2_lib.scala 244:36] - wire _T_346 = _T_345 & _T_318; // @[el2_lib.scala 244:41] - wire _T_349 = io_trigger_pkt_any_1_tdata2[4] == lsu_match_data_1[4]; // @[el2_lib.scala 244:78] - wire _T_350 = _T_346 | _T_349; // @[el2_lib.scala 244:23] - wire _T_352 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[el2_lib.scala 244:36] - wire _T_353 = _T_352 & _T_318; // @[el2_lib.scala 244:41] - wire _T_356 = io_trigger_pkt_any_1_tdata2[5] == lsu_match_data_1[5]; // @[el2_lib.scala 244:78] - wire _T_357 = _T_353 | _T_356; // @[el2_lib.scala 244:23] - wire _T_359 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[el2_lib.scala 244:36] - wire _T_360 = _T_359 & _T_318; // @[el2_lib.scala 244:41] - wire _T_363 = io_trigger_pkt_any_1_tdata2[6] == lsu_match_data_1[6]; // @[el2_lib.scala 244:78] - wire _T_364 = _T_360 | _T_363; // @[el2_lib.scala 244:23] - wire _T_366 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[el2_lib.scala 244:36] - wire _T_367 = _T_366 & _T_318; // @[el2_lib.scala 244:41] - wire _T_370 = io_trigger_pkt_any_1_tdata2[7] == lsu_match_data_1[7]; // @[el2_lib.scala 244:78] - wire _T_371 = _T_367 | _T_370; // @[el2_lib.scala 244:23] - wire _T_373 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[el2_lib.scala 244:36] - wire _T_374 = _T_373 & _T_318; // @[el2_lib.scala 244:41] - wire _T_377 = io_trigger_pkt_any_1_tdata2[8] == lsu_match_data_1[8]; // @[el2_lib.scala 244:78] - wire _T_378 = _T_374 | _T_377; // @[el2_lib.scala 244:23] - wire _T_380 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[el2_lib.scala 244:36] - wire _T_381 = _T_380 & _T_318; // @[el2_lib.scala 244:41] - wire _T_384 = io_trigger_pkt_any_1_tdata2[9] == lsu_match_data_1[9]; // @[el2_lib.scala 244:78] - wire _T_385 = _T_381 | _T_384; // @[el2_lib.scala 244:23] - wire _T_387 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[el2_lib.scala 244:36] - wire _T_388 = _T_387 & _T_318; // @[el2_lib.scala 244:41] - wire _T_391 = io_trigger_pkt_any_1_tdata2[10] == lsu_match_data_1[10]; // @[el2_lib.scala 244:78] - wire _T_392 = _T_388 | _T_391; // @[el2_lib.scala 244:23] - wire _T_394 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[el2_lib.scala 244:36] - wire _T_395 = _T_394 & _T_318; // @[el2_lib.scala 244:41] - wire _T_398 = io_trigger_pkt_any_1_tdata2[11] == lsu_match_data_1[11]; // @[el2_lib.scala 244:78] - wire _T_399 = _T_395 | _T_398; // @[el2_lib.scala 244:23] - wire _T_401 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[el2_lib.scala 244:36] - wire _T_402 = _T_401 & _T_318; // @[el2_lib.scala 244:41] - wire _T_405 = io_trigger_pkt_any_1_tdata2[12] == lsu_match_data_1[12]; // @[el2_lib.scala 244:78] - wire _T_406 = _T_402 | _T_405; // @[el2_lib.scala 244:23] - wire _T_408 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[el2_lib.scala 244:36] - wire _T_409 = _T_408 & _T_318; // @[el2_lib.scala 244:41] - wire _T_412 = io_trigger_pkt_any_1_tdata2[13] == lsu_match_data_1[13]; // @[el2_lib.scala 244:78] - wire _T_413 = _T_409 | _T_412; // @[el2_lib.scala 244:23] - wire _T_415 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[el2_lib.scala 244:36] - wire _T_416 = _T_415 & _T_318; // @[el2_lib.scala 244:41] - wire _T_419 = io_trigger_pkt_any_1_tdata2[14] == lsu_match_data_1[14]; // @[el2_lib.scala 244:78] - wire _T_420 = _T_416 | _T_419; // @[el2_lib.scala 244:23] - wire _T_422 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[el2_lib.scala 244:36] - wire _T_423 = _T_422 & _T_318; // @[el2_lib.scala 244:41] - wire _T_426 = io_trigger_pkt_any_1_tdata2[15] == lsu_match_data_1[15]; // @[el2_lib.scala 244:78] - wire _T_427 = _T_423 | _T_426; // @[el2_lib.scala 244:23] - wire _T_429 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[el2_lib.scala 244:36] - wire _T_430 = _T_429 & _T_318; // @[el2_lib.scala 244:41] - wire _T_433 = io_trigger_pkt_any_1_tdata2[16] == lsu_match_data_1[16]; // @[el2_lib.scala 244:78] - wire _T_434 = _T_430 | _T_433; // @[el2_lib.scala 244:23] - wire _T_436 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[el2_lib.scala 244:36] - wire _T_437 = _T_436 & _T_318; // @[el2_lib.scala 244:41] - wire _T_440 = io_trigger_pkt_any_1_tdata2[17] == lsu_match_data_1[17]; // @[el2_lib.scala 244:78] - wire _T_441 = _T_437 | _T_440; // @[el2_lib.scala 244:23] - wire _T_443 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[el2_lib.scala 244:36] - wire _T_444 = _T_443 & _T_318; // @[el2_lib.scala 244:41] - wire _T_447 = io_trigger_pkt_any_1_tdata2[18] == lsu_match_data_1[18]; // @[el2_lib.scala 244:78] - wire _T_448 = _T_444 | _T_447; // @[el2_lib.scala 244:23] - wire _T_450 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[el2_lib.scala 244:36] - wire _T_451 = _T_450 & _T_318; // @[el2_lib.scala 244:41] - wire _T_454 = io_trigger_pkt_any_1_tdata2[19] == lsu_match_data_1[19]; // @[el2_lib.scala 244:78] - wire _T_455 = _T_451 | _T_454; // @[el2_lib.scala 244:23] - wire _T_457 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[el2_lib.scala 244:36] - wire _T_458 = _T_457 & _T_318; // @[el2_lib.scala 244:41] - wire _T_461 = io_trigger_pkt_any_1_tdata2[20] == lsu_match_data_1[20]; // @[el2_lib.scala 244:78] - wire _T_462 = _T_458 | _T_461; // @[el2_lib.scala 244:23] - wire _T_464 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[el2_lib.scala 244:36] - wire _T_465 = _T_464 & _T_318; // @[el2_lib.scala 244:41] - wire _T_468 = io_trigger_pkt_any_1_tdata2[21] == lsu_match_data_1[21]; // @[el2_lib.scala 244:78] - wire _T_469 = _T_465 | _T_468; // @[el2_lib.scala 244:23] - wire _T_471 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[el2_lib.scala 244:36] - wire _T_472 = _T_471 & _T_318; // @[el2_lib.scala 244:41] - wire _T_475 = io_trigger_pkt_any_1_tdata2[22] == lsu_match_data_1[22]; // @[el2_lib.scala 244:78] - wire _T_476 = _T_472 | _T_475; // @[el2_lib.scala 244:23] - wire _T_478 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[el2_lib.scala 244:36] - wire _T_479 = _T_478 & _T_318; // @[el2_lib.scala 244:41] - wire _T_482 = io_trigger_pkt_any_1_tdata2[23] == lsu_match_data_1[23]; // @[el2_lib.scala 244:78] - wire _T_483 = _T_479 | _T_482; // @[el2_lib.scala 244:23] - wire _T_485 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[el2_lib.scala 244:36] - wire _T_486 = _T_485 & _T_318; // @[el2_lib.scala 244:41] - wire _T_489 = io_trigger_pkt_any_1_tdata2[24] == lsu_match_data_1[24]; // @[el2_lib.scala 244:78] - wire _T_490 = _T_486 | _T_489; // @[el2_lib.scala 244:23] - wire _T_492 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[el2_lib.scala 244:36] - wire _T_493 = _T_492 & _T_318; // @[el2_lib.scala 244:41] - wire _T_496 = io_trigger_pkt_any_1_tdata2[25] == lsu_match_data_1[25]; // @[el2_lib.scala 244:78] - wire _T_497 = _T_493 | _T_496; // @[el2_lib.scala 244:23] - wire _T_499 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[el2_lib.scala 244:36] - wire _T_500 = _T_499 & _T_318; // @[el2_lib.scala 244:41] - wire _T_503 = io_trigger_pkt_any_1_tdata2[26] == lsu_match_data_1[26]; // @[el2_lib.scala 244:78] - wire _T_504 = _T_500 | _T_503; // @[el2_lib.scala 244:23] - wire _T_506 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[el2_lib.scala 244:36] - wire _T_507 = _T_506 & _T_318; // @[el2_lib.scala 244:41] - wire _T_510 = io_trigger_pkt_any_1_tdata2[27] == lsu_match_data_1[27]; // @[el2_lib.scala 244:78] - wire _T_511 = _T_507 | _T_510; // @[el2_lib.scala 244:23] - wire _T_513 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[el2_lib.scala 244:36] - wire _T_514 = _T_513 & _T_318; // @[el2_lib.scala 244:41] - wire _T_517 = io_trigger_pkt_any_1_tdata2[28] == lsu_match_data_1[28]; // @[el2_lib.scala 244:78] - wire _T_518 = _T_514 | _T_517; // @[el2_lib.scala 244:23] - wire _T_520 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[el2_lib.scala 244:36] - wire _T_521 = _T_520 & _T_318; // @[el2_lib.scala 244:41] - wire _T_524 = io_trigger_pkt_any_1_tdata2[29] == lsu_match_data_1[29]; // @[el2_lib.scala 244:78] - wire _T_525 = _T_521 | _T_524; // @[el2_lib.scala 244:23] - wire _T_527 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[el2_lib.scala 244:36] - wire _T_528 = _T_527 & _T_318; // @[el2_lib.scala 244:41] - wire _T_531 = io_trigger_pkt_any_1_tdata2[30] == lsu_match_data_1[30]; // @[el2_lib.scala 244:78] - wire _T_532 = _T_528 | _T_531; // @[el2_lib.scala 244:23] - wire _T_534 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[el2_lib.scala 244:36] - wire _T_535 = _T_534 & _T_318; // @[el2_lib.scala 244:41] - wire _T_538 = io_trigger_pkt_any_1_tdata2[31] == lsu_match_data_1[31]; // @[el2_lib.scala 244:78] - wire _T_539 = _T_535 | _T_538; // @[el2_lib.scala 244:23] - wire [7:0] _T_546 = {_T_371,_T_364,_T_357,_T_350,_T_343,_T_336,_T_329,_T_322}; // @[el2_lib.scala 245:14] - wire [15:0] _T_554 = {_T_427,_T_420,_T_413,_T_406,_T_399,_T_392,_T_385,_T_378,_T_546}; // @[el2_lib.scala 245:14] - wire [7:0] _T_561 = {_T_483,_T_476,_T_469,_T_462,_T_455,_T_448,_T_441,_T_434}; // @[el2_lib.scala 245:14] - wire [31:0] _T_570 = {_T_539,_T_532,_T_525,_T_518,_T_511,_T_504,_T_497,_T_490,_T_561,_T_554}; // @[el2_lib.scala 245:14] - wire _T_571 = &_T_570; // @[el2_lib.scala 245:25] + wire _T_316 = &io_trigger_pkt_any_1_tdata2; // @[lib.scala 101:45] + wire _T_317 = ~_T_316; // @[lib.scala 101:39] + wire _T_318 = io_trigger_pkt_any_1_match_pkt & _T_317; // @[lib.scala 101:37] + wire _T_321 = io_trigger_pkt_any_1_tdata2[0] == lsu_match_data_1[0]; // @[lib.scala 102:52] + wire _T_322 = _T_318 | _T_321; // @[lib.scala 102:41] + wire _T_324 = &io_trigger_pkt_any_1_tdata2[0]; // @[lib.scala 104:36] + wire _T_325 = _T_324 & _T_318; // @[lib.scala 104:41] + wire _T_328 = io_trigger_pkt_any_1_tdata2[1] == lsu_match_data_1[1]; // @[lib.scala 104:78] + wire _T_329 = _T_325 | _T_328; // @[lib.scala 104:23] + wire _T_331 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[lib.scala 104:36] + wire _T_332 = _T_331 & _T_318; // @[lib.scala 104:41] + wire _T_335 = io_trigger_pkt_any_1_tdata2[2] == lsu_match_data_1[2]; // @[lib.scala 104:78] + wire _T_336 = _T_332 | _T_335; // @[lib.scala 104:23] + wire _T_338 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[lib.scala 104:36] + wire _T_339 = _T_338 & _T_318; // @[lib.scala 104:41] + wire _T_342 = io_trigger_pkt_any_1_tdata2[3] == lsu_match_data_1[3]; // @[lib.scala 104:78] + wire _T_343 = _T_339 | _T_342; // @[lib.scala 104:23] + wire _T_345 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[lib.scala 104:36] + wire _T_346 = _T_345 & _T_318; // @[lib.scala 104:41] + wire _T_349 = io_trigger_pkt_any_1_tdata2[4] == lsu_match_data_1[4]; // @[lib.scala 104:78] + wire _T_350 = _T_346 | _T_349; // @[lib.scala 104:23] + wire _T_352 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[lib.scala 104:36] + wire _T_353 = _T_352 & _T_318; // @[lib.scala 104:41] + wire _T_356 = io_trigger_pkt_any_1_tdata2[5] == lsu_match_data_1[5]; // @[lib.scala 104:78] + wire _T_357 = _T_353 | _T_356; // @[lib.scala 104:23] + wire _T_359 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[lib.scala 104:36] + wire _T_360 = _T_359 & _T_318; // @[lib.scala 104:41] + wire _T_363 = io_trigger_pkt_any_1_tdata2[6] == lsu_match_data_1[6]; // @[lib.scala 104:78] + wire _T_364 = _T_360 | _T_363; // @[lib.scala 104:23] + wire _T_366 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[lib.scala 104:36] + wire _T_367 = _T_366 & _T_318; // @[lib.scala 104:41] + wire _T_370 = io_trigger_pkt_any_1_tdata2[7] == lsu_match_data_1[7]; // @[lib.scala 104:78] + wire _T_371 = _T_367 | _T_370; // @[lib.scala 104:23] + wire _T_373 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[lib.scala 104:36] + wire _T_374 = _T_373 & _T_318; // @[lib.scala 104:41] + wire _T_377 = io_trigger_pkt_any_1_tdata2[8] == lsu_match_data_1[8]; // @[lib.scala 104:78] + wire _T_378 = _T_374 | _T_377; // @[lib.scala 104:23] + wire _T_380 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[lib.scala 104:36] + wire _T_381 = _T_380 & _T_318; // @[lib.scala 104:41] + wire _T_384 = io_trigger_pkt_any_1_tdata2[9] == lsu_match_data_1[9]; // @[lib.scala 104:78] + wire _T_385 = _T_381 | _T_384; // @[lib.scala 104:23] + wire _T_387 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[lib.scala 104:36] + wire _T_388 = _T_387 & _T_318; // @[lib.scala 104:41] + wire _T_391 = io_trigger_pkt_any_1_tdata2[10] == lsu_match_data_1[10]; // @[lib.scala 104:78] + wire _T_392 = _T_388 | _T_391; // @[lib.scala 104:23] + wire _T_394 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[lib.scala 104:36] + wire _T_395 = _T_394 & _T_318; // @[lib.scala 104:41] + wire _T_398 = io_trigger_pkt_any_1_tdata2[11] == lsu_match_data_1[11]; // @[lib.scala 104:78] + wire _T_399 = _T_395 | _T_398; // @[lib.scala 104:23] + wire _T_401 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[lib.scala 104:36] + wire _T_402 = _T_401 & _T_318; // @[lib.scala 104:41] + wire _T_405 = io_trigger_pkt_any_1_tdata2[12] == lsu_match_data_1[12]; // @[lib.scala 104:78] + wire _T_406 = _T_402 | _T_405; // @[lib.scala 104:23] + wire _T_408 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[lib.scala 104:36] + wire _T_409 = _T_408 & _T_318; // @[lib.scala 104:41] + wire _T_412 = io_trigger_pkt_any_1_tdata2[13] == lsu_match_data_1[13]; // @[lib.scala 104:78] + wire _T_413 = _T_409 | _T_412; // @[lib.scala 104:23] + wire _T_415 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[lib.scala 104:36] + wire _T_416 = _T_415 & _T_318; // @[lib.scala 104:41] + wire _T_419 = io_trigger_pkt_any_1_tdata2[14] == lsu_match_data_1[14]; // @[lib.scala 104:78] + wire _T_420 = _T_416 | _T_419; // @[lib.scala 104:23] + wire _T_422 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[lib.scala 104:36] + wire _T_423 = _T_422 & _T_318; // @[lib.scala 104:41] + wire _T_426 = io_trigger_pkt_any_1_tdata2[15] == lsu_match_data_1[15]; // @[lib.scala 104:78] + wire _T_427 = _T_423 | _T_426; // @[lib.scala 104:23] + wire _T_429 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[lib.scala 104:36] + wire _T_430 = _T_429 & _T_318; // @[lib.scala 104:41] + wire _T_433 = io_trigger_pkt_any_1_tdata2[16] == lsu_match_data_1[16]; // @[lib.scala 104:78] + wire _T_434 = _T_430 | _T_433; // @[lib.scala 104:23] + wire _T_436 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[lib.scala 104:36] + wire _T_437 = _T_436 & _T_318; // @[lib.scala 104:41] + wire _T_440 = io_trigger_pkt_any_1_tdata2[17] == lsu_match_data_1[17]; // @[lib.scala 104:78] + wire _T_441 = _T_437 | _T_440; // @[lib.scala 104:23] + wire _T_443 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[lib.scala 104:36] + wire _T_444 = _T_443 & _T_318; // @[lib.scala 104:41] + wire _T_447 = io_trigger_pkt_any_1_tdata2[18] == lsu_match_data_1[18]; // @[lib.scala 104:78] + wire _T_448 = _T_444 | _T_447; // @[lib.scala 104:23] + wire _T_450 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[lib.scala 104:36] + wire _T_451 = _T_450 & _T_318; // @[lib.scala 104:41] + wire _T_454 = io_trigger_pkt_any_1_tdata2[19] == lsu_match_data_1[19]; // @[lib.scala 104:78] + wire _T_455 = _T_451 | _T_454; // @[lib.scala 104:23] + wire _T_457 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[lib.scala 104:36] + wire _T_458 = _T_457 & _T_318; // @[lib.scala 104:41] + wire _T_461 = io_trigger_pkt_any_1_tdata2[20] == lsu_match_data_1[20]; // @[lib.scala 104:78] + wire _T_462 = _T_458 | _T_461; // @[lib.scala 104:23] + wire _T_464 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[lib.scala 104:36] + wire _T_465 = _T_464 & _T_318; // @[lib.scala 104:41] + wire _T_468 = io_trigger_pkt_any_1_tdata2[21] == lsu_match_data_1[21]; // @[lib.scala 104:78] + wire _T_469 = _T_465 | _T_468; // @[lib.scala 104:23] + wire _T_471 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[lib.scala 104:36] + wire _T_472 = _T_471 & _T_318; // @[lib.scala 104:41] + wire _T_475 = io_trigger_pkt_any_1_tdata2[22] == lsu_match_data_1[22]; // @[lib.scala 104:78] + wire _T_476 = _T_472 | _T_475; // @[lib.scala 104:23] + wire _T_478 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[lib.scala 104:36] + wire _T_479 = _T_478 & _T_318; // @[lib.scala 104:41] + wire _T_482 = io_trigger_pkt_any_1_tdata2[23] == lsu_match_data_1[23]; // @[lib.scala 104:78] + wire _T_483 = _T_479 | _T_482; // @[lib.scala 104:23] + wire _T_485 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[lib.scala 104:36] + wire _T_486 = _T_485 & _T_318; // @[lib.scala 104:41] + wire _T_489 = io_trigger_pkt_any_1_tdata2[24] == lsu_match_data_1[24]; // @[lib.scala 104:78] + wire _T_490 = _T_486 | _T_489; // @[lib.scala 104:23] + wire _T_492 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[lib.scala 104:36] + wire _T_493 = _T_492 & _T_318; // @[lib.scala 104:41] + wire _T_496 = io_trigger_pkt_any_1_tdata2[25] == lsu_match_data_1[25]; // @[lib.scala 104:78] + wire _T_497 = _T_493 | _T_496; // @[lib.scala 104:23] + wire _T_499 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[lib.scala 104:36] + wire _T_500 = _T_499 & _T_318; // @[lib.scala 104:41] + wire _T_503 = io_trigger_pkt_any_1_tdata2[26] == lsu_match_data_1[26]; // @[lib.scala 104:78] + wire _T_504 = _T_500 | _T_503; // @[lib.scala 104:23] + wire _T_506 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[lib.scala 104:36] + wire _T_507 = _T_506 & _T_318; // @[lib.scala 104:41] + wire _T_510 = io_trigger_pkt_any_1_tdata2[27] == lsu_match_data_1[27]; // @[lib.scala 104:78] + wire _T_511 = _T_507 | _T_510; // @[lib.scala 104:23] + wire _T_513 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[lib.scala 104:36] + wire _T_514 = _T_513 & _T_318; // @[lib.scala 104:41] + wire _T_517 = io_trigger_pkt_any_1_tdata2[28] == lsu_match_data_1[28]; // @[lib.scala 104:78] + wire _T_518 = _T_514 | _T_517; // @[lib.scala 104:23] + wire _T_520 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[lib.scala 104:36] + wire _T_521 = _T_520 & _T_318; // @[lib.scala 104:41] + wire _T_524 = io_trigger_pkt_any_1_tdata2[29] == lsu_match_data_1[29]; // @[lib.scala 104:78] + wire _T_525 = _T_521 | _T_524; // @[lib.scala 104:23] + wire _T_527 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[lib.scala 104:36] + wire _T_528 = _T_527 & _T_318; // @[lib.scala 104:41] + wire _T_531 = io_trigger_pkt_any_1_tdata2[30] == lsu_match_data_1[30]; // @[lib.scala 104:78] + wire _T_532 = _T_528 | _T_531; // @[lib.scala 104:23] + wire _T_534 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[lib.scala 104:36] + wire _T_535 = _T_534 & _T_318; // @[lib.scala 104:41] + wire _T_538 = io_trigger_pkt_any_1_tdata2[31] == lsu_match_data_1[31]; // @[lib.scala 104:78] + wire _T_539 = _T_535 | _T_538; // @[lib.scala 104:23] + wire [7:0] _T_546 = {_T_371,_T_364,_T_357,_T_350,_T_343,_T_336,_T_329,_T_322}; // @[lib.scala 105:14] + wire [15:0] _T_554 = {_T_427,_T_420,_T_413,_T_406,_T_399,_T_392,_T_385,_T_378,_T_546}; // @[lib.scala 105:14] + wire [7:0] _T_561 = {_T_483,_T_476,_T_469,_T_462,_T_455,_T_448,_T_441,_T_434}; // @[lib.scala 105:14] + wire [31:0] _T_570 = {_T_539,_T_532,_T_525,_T_518,_T_511,_T_504,_T_497,_T_490,_T_561,_T_554}; // @[lib.scala 105:14] + wire _T_571 = &_T_570; // @[lib.scala 105:25] wire _T_572 = _T_313 & _T_571; // @[lsu_trigger.scala 19:92] wire _T_575 = io_trigger_pkt_any_2_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 18:126] wire _T_576 = io_trigger_pkt_any_2_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 19:33] wire _T_578 = _T_576 & _T_26; // @[lsu_trigger.scala 19:58] wire _T_579 = _T_575 | _T_578; // @[lsu_trigger.scala 18:152] wire _T_580 = _T_40 & _T_579; // @[lsu_trigger.scala 18:94] - wire _T_583 = &io_trigger_pkt_any_2_tdata2; // @[el2_lib.scala 241:45] - wire _T_584 = ~_T_583; // @[el2_lib.scala 241:39] - wire _T_585 = io_trigger_pkt_any_2_match_pkt & _T_584; // @[el2_lib.scala 241:37] - wire _T_588 = io_trigger_pkt_any_2_tdata2[0] == lsu_match_data_2[0]; // @[el2_lib.scala 242:52] - wire _T_589 = _T_585 | _T_588; // @[el2_lib.scala 242:41] - wire _T_591 = &io_trigger_pkt_any_2_tdata2[0]; // @[el2_lib.scala 244:36] - wire _T_592 = _T_591 & _T_585; // @[el2_lib.scala 244:41] - wire _T_595 = io_trigger_pkt_any_2_tdata2[1] == lsu_match_data_2[1]; // @[el2_lib.scala 244:78] - wire _T_596 = _T_592 | _T_595; // @[el2_lib.scala 244:23] - wire _T_598 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[el2_lib.scala 244:36] - wire _T_599 = _T_598 & _T_585; // @[el2_lib.scala 244:41] - wire _T_602 = io_trigger_pkt_any_2_tdata2[2] == lsu_match_data_2[2]; // @[el2_lib.scala 244:78] - wire _T_603 = _T_599 | _T_602; // @[el2_lib.scala 244:23] - wire _T_605 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[el2_lib.scala 244:36] - wire _T_606 = _T_605 & _T_585; // @[el2_lib.scala 244:41] - wire _T_609 = io_trigger_pkt_any_2_tdata2[3] == lsu_match_data_2[3]; // @[el2_lib.scala 244:78] - wire _T_610 = _T_606 | _T_609; // @[el2_lib.scala 244:23] - wire _T_612 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[el2_lib.scala 244:36] - wire _T_613 = _T_612 & _T_585; // @[el2_lib.scala 244:41] - wire _T_616 = io_trigger_pkt_any_2_tdata2[4] == lsu_match_data_2[4]; // @[el2_lib.scala 244:78] - wire _T_617 = _T_613 | _T_616; // @[el2_lib.scala 244:23] - wire _T_619 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[el2_lib.scala 244:36] - wire _T_620 = _T_619 & _T_585; // @[el2_lib.scala 244:41] - wire _T_623 = io_trigger_pkt_any_2_tdata2[5] == lsu_match_data_2[5]; // @[el2_lib.scala 244:78] - wire _T_624 = _T_620 | _T_623; // @[el2_lib.scala 244:23] - wire _T_626 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[el2_lib.scala 244:36] - wire _T_627 = _T_626 & _T_585; // @[el2_lib.scala 244:41] - wire _T_630 = io_trigger_pkt_any_2_tdata2[6] == lsu_match_data_2[6]; // @[el2_lib.scala 244:78] - wire _T_631 = _T_627 | _T_630; // @[el2_lib.scala 244:23] - wire _T_633 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[el2_lib.scala 244:36] - wire _T_634 = _T_633 & _T_585; // @[el2_lib.scala 244:41] - wire _T_637 = io_trigger_pkt_any_2_tdata2[7] == lsu_match_data_2[7]; // @[el2_lib.scala 244:78] - wire _T_638 = _T_634 | _T_637; // @[el2_lib.scala 244:23] - wire _T_640 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[el2_lib.scala 244:36] - wire _T_641 = _T_640 & _T_585; // @[el2_lib.scala 244:41] - wire _T_644 = io_trigger_pkt_any_2_tdata2[8] == lsu_match_data_2[8]; // @[el2_lib.scala 244:78] - wire _T_645 = _T_641 | _T_644; // @[el2_lib.scala 244:23] - wire _T_647 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[el2_lib.scala 244:36] - wire _T_648 = _T_647 & _T_585; // @[el2_lib.scala 244:41] - wire _T_651 = io_trigger_pkt_any_2_tdata2[9] == lsu_match_data_2[9]; // @[el2_lib.scala 244:78] - wire _T_652 = _T_648 | _T_651; // @[el2_lib.scala 244:23] - wire _T_654 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[el2_lib.scala 244:36] - wire _T_655 = _T_654 & _T_585; // @[el2_lib.scala 244:41] - wire _T_658 = io_trigger_pkt_any_2_tdata2[10] == lsu_match_data_2[10]; // @[el2_lib.scala 244:78] - wire _T_659 = _T_655 | _T_658; // @[el2_lib.scala 244:23] - wire _T_661 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[el2_lib.scala 244:36] - wire _T_662 = _T_661 & _T_585; // @[el2_lib.scala 244:41] - wire _T_665 = io_trigger_pkt_any_2_tdata2[11] == lsu_match_data_2[11]; // @[el2_lib.scala 244:78] - wire _T_666 = _T_662 | _T_665; // @[el2_lib.scala 244:23] - wire _T_668 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[el2_lib.scala 244:36] - wire _T_669 = _T_668 & _T_585; // @[el2_lib.scala 244:41] - wire _T_672 = io_trigger_pkt_any_2_tdata2[12] == lsu_match_data_2[12]; // @[el2_lib.scala 244:78] - wire _T_673 = _T_669 | _T_672; // @[el2_lib.scala 244:23] - wire _T_675 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[el2_lib.scala 244:36] - wire _T_676 = _T_675 & _T_585; // @[el2_lib.scala 244:41] - wire _T_679 = io_trigger_pkt_any_2_tdata2[13] == lsu_match_data_2[13]; // @[el2_lib.scala 244:78] - wire _T_680 = _T_676 | _T_679; // @[el2_lib.scala 244:23] - wire _T_682 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[el2_lib.scala 244:36] - wire _T_683 = _T_682 & _T_585; // @[el2_lib.scala 244:41] - wire _T_686 = io_trigger_pkt_any_2_tdata2[14] == lsu_match_data_2[14]; // @[el2_lib.scala 244:78] - wire _T_687 = _T_683 | _T_686; // @[el2_lib.scala 244:23] - wire _T_689 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[el2_lib.scala 244:36] - wire _T_690 = _T_689 & _T_585; // @[el2_lib.scala 244:41] - wire _T_693 = io_trigger_pkt_any_2_tdata2[15] == lsu_match_data_2[15]; // @[el2_lib.scala 244:78] - wire _T_694 = _T_690 | _T_693; // @[el2_lib.scala 244:23] - wire _T_696 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[el2_lib.scala 244:36] - wire _T_697 = _T_696 & _T_585; // @[el2_lib.scala 244:41] - wire _T_700 = io_trigger_pkt_any_2_tdata2[16] == lsu_match_data_2[16]; // @[el2_lib.scala 244:78] - wire _T_701 = _T_697 | _T_700; // @[el2_lib.scala 244:23] - wire _T_703 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[el2_lib.scala 244:36] - wire _T_704 = _T_703 & _T_585; // @[el2_lib.scala 244:41] - wire _T_707 = io_trigger_pkt_any_2_tdata2[17] == lsu_match_data_2[17]; // @[el2_lib.scala 244:78] - wire _T_708 = _T_704 | _T_707; // @[el2_lib.scala 244:23] - wire _T_710 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[el2_lib.scala 244:36] - wire _T_711 = _T_710 & _T_585; // @[el2_lib.scala 244:41] - wire _T_714 = io_trigger_pkt_any_2_tdata2[18] == lsu_match_data_2[18]; // @[el2_lib.scala 244:78] - wire _T_715 = _T_711 | _T_714; // @[el2_lib.scala 244:23] - wire _T_717 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[el2_lib.scala 244:36] - wire _T_718 = _T_717 & _T_585; // @[el2_lib.scala 244:41] - wire _T_721 = io_trigger_pkt_any_2_tdata2[19] == lsu_match_data_2[19]; // @[el2_lib.scala 244:78] - wire _T_722 = _T_718 | _T_721; // @[el2_lib.scala 244:23] - wire _T_724 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[el2_lib.scala 244:36] - wire _T_725 = _T_724 & _T_585; // @[el2_lib.scala 244:41] - wire _T_728 = io_trigger_pkt_any_2_tdata2[20] == lsu_match_data_2[20]; // @[el2_lib.scala 244:78] - wire _T_729 = _T_725 | _T_728; // @[el2_lib.scala 244:23] - wire _T_731 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[el2_lib.scala 244:36] - wire _T_732 = _T_731 & _T_585; // @[el2_lib.scala 244:41] - wire _T_735 = io_trigger_pkt_any_2_tdata2[21] == lsu_match_data_2[21]; // @[el2_lib.scala 244:78] - wire _T_736 = _T_732 | _T_735; // @[el2_lib.scala 244:23] - wire _T_738 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[el2_lib.scala 244:36] - wire _T_739 = _T_738 & _T_585; // @[el2_lib.scala 244:41] - wire _T_742 = io_trigger_pkt_any_2_tdata2[22] == lsu_match_data_2[22]; // @[el2_lib.scala 244:78] - wire _T_743 = _T_739 | _T_742; // @[el2_lib.scala 244:23] - wire _T_745 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[el2_lib.scala 244:36] - wire _T_746 = _T_745 & _T_585; // @[el2_lib.scala 244:41] - wire _T_749 = io_trigger_pkt_any_2_tdata2[23] == lsu_match_data_2[23]; // @[el2_lib.scala 244:78] - wire _T_750 = _T_746 | _T_749; // @[el2_lib.scala 244:23] - wire _T_752 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[el2_lib.scala 244:36] - wire _T_753 = _T_752 & _T_585; // @[el2_lib.scala 244:41] - wire _T_756 = io_trigger_pkt_any_2_tdata2[24] == lsu_match_data_2[24]; // @[el2_lib.scala 244:78] - wire _T_757 = _T_753 | _T_756; // @[el2_lib.scala 244:23] - wire _T_759 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[el2_lib.scala 244:36] - wire _T_760 = _T_759 & _T_585; // @[el2_lib.scala 244:41] - wire _T_763 = io_trigger_pkt_any_2_tdata2[25] == lsu_match_data_2[25]; // @[el2_lib.scala 244:78] - wire _T_764 = _T_760 | _T_763; // @[el2_lib.scala 244:23] - wire _T_766 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[el2_lib.scala 244:36] - wire _T_767 = _T_766 & _T_585; // @[el2_lib.scala 244:41] - wire _T_770 = io_trigger_pkt_any_2_tdata2[26] == lsu_match_data_2[26]; // @[el2_lib.scala 244:78] - wire _T_771 = _T_767 | _T_770; // @[el2_lib.scala 244:23] - wire _T_773 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[el2_lib.scala 244:36] - wire _T_774 = _T_773 & _T_585; // @[el2_lib.scala 244:41] - wire _T_777 = io_trigger_pkt_any_2_tdata2[27] == lsu_match_data_2[27]; // @[el2_lib.scala 244:78] - wire _T_778 = _T_774 | _T_777; // @[el2_lib.scala 244:23] - wire _T_780 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[el2_lib.scala 244:36] - wire _T_781 = _T_780 & _T_585; // @[el2_lib.scala 244:41] - wire _T_784 = io_trigger_pkt_any_2_tdata2[28] == lsu_match_data_2[28]; // @[el2_lib.scala 244:78] - wire _T_785 = _T_781 | _T_784; // @[el2_lib.scala 244:23] - wire _T_787 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[el2_lib.scala 244:36] - wire _T_788 = _T_787 & _T_585; // @[el2_lib.scala 244:41] - wire _T_791 = io_trigger_pkt_any_2_tdata2[29] == lsu_match_data_2[29]; // @[el2_lib.scala 244:78] - wire _T_792 = _T_788 | _T_791; // @[el2_lib.scala 244:23] - wire _T_794 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[el2_lib.scala 244:36] - wire _T_795 = _T_794 & _T_585; // @[el2_lib.scala 244:41] - wire _T_798 = io_trigger_pkt_any_2_tdata2[30] == lsu_match_data_2[30]; // @[el2_lib.scala 244:78] - wire _T_799 = _T_795 | _T_798; // @[el2_lib.scala 244:23] - wire _T_801 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[el2_lib.scala 244:36] - wire _T_802 = _T_801 & _T_585; // @[el2_lib.scala 244:41] - wire _T_805 = io_trigger_pkt_any_2_tdata2[31] == lsu_match_data_2[31]; // @[el2_lib.scala 244:78] - wire _T_806 = _T_802 | _T_805; // @[el2_lib.scala 244:23] - wire [7:0] _T_813 = {_T_638,_T_631,_T_624,_T_617,_T_610,_T_603,_T_596,_T_589}; // @[el2_lib.scala 245:14] - wire [15:0] _T_821 = {_T_694,_T_687,_T_680,_T_673,_T_666,_T_659,_T_652,_T_645,_T_813}; // @[el2_lib.scala 245:14] - wire [7:0] _T_828 = {_T_750,_T_743,_T_736,_T_729,_T_722,_T_715,_T_708,_T_701}; // @[el2_lib.scala 245:14] - wire [31:0] _T_837 = {_T_806,_T_799,_T_792,_T_785,_T_778,_T_771,_T_764,_T_757,_T_828,_T_821}; // @[el2_lib.scala 245:14] - wire _T_838 = &_T_837; // @[el2_lib.scala 245:25] + wire _T_583 = &io_trigger_pkt_any_2_tdata2; // @[lib.scala 101:45] + wire _T_584 = ~_T_583; // @[lib.scala 101:39] + wire _T_585 = io_trigger_pkt_any_2_match_pkt & _T_584; // @[lib.scala 101:37] + wire _T_588 = io_trigger_pkt_any_2_tdata2[0] == lsu_match_data_2[0]; // @[lib.scala 102:52] + wire _T_589 = _T_585 | _T_588; // @[lib.scala 102:41] + wire _T_591 = &io_trigger_pkt_any_2_tdata2[0]; // @[lib.scala 104:36] + wire _T_592 = _T_591 & _T_585; // @[lib.scala 104:41] + wire _T_595 = io_trigger_pkt_any_2_tdata2[1] == lsu_match_data_2[1]; // @[lib.scala 104:78] + wire _T_596 = _T_592 | _T_595; // @[lib.scala 104:23] + wire _T_598 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[lib.scala 104:36] + wire _T_599 = _T_598 & _T_585; // @[lib.scala 104:41] + wire _T_602 = io_trigger_pkt_any_2_tdata2[2] == lsu_match_data_2[2]; // @[lib.scala 104:78] + wire _T_603 = _T_599 | _T_602; // @[lib.scala 104:23] + wire _T_605 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[lib.scala 104:36] + wire _T_606 = _T_605 & _T_585; // @[lib.scala 104:41] + wire _T_609 = io_trigger_pkt_any_2_tdata2[3] == lsu_match_data_2[3]; // @[lib.scala 104:78] + wire _T_610 = _T_606 | _T_609; // @[lib.scala 104:23] + wire _T_612 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[lib.scala 104:36] + wire _T_613 = _T_612 & _T_585; // @[lib.scala 104:41] + wire _T_616 = io_trigger_pkt_any_2_tdata2[4] == lsu_match_data_2[4]; // @[lib.scala 104:78] + wire _T_617 = _T_613 | _T_616; // @[lib.scala 104:23] + wire _T_619 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[lib.scala 104:36] + wire _T_620 = _T_619 & _T_585; // @[lib.scala 104:41] + wire _T_623 = io_trigger_pkt_any_2_tdata2[5] == lsu_match_data_2[5]; // @[lib.scala 104:78] + wire _T_624 = _T_620 | _T_623; // @[lib.scala 104:23] + wire _T_626 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[lib.scala 104:36] + wire _T_627 = _T_626 & _T_585; // @[lib.scala 104:41] + wire _T_630 = io_trigger_pkt_any_2_tdata2[6] == lsu_match_data_2[6]; // @[lib.scala 104:78] + wire _T_631 = _T_627 | _T_630; // @[lib.scala 104:23] + wire _T_633 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[lib.scala 104:36] + wire _T_634 = _T_633 & _T_585; // @[lib.scala 104:41] + wire _T_637 = io_trigger_pkt_any_2_tdata2[7] == lsu_match_data_2[7]; // @[lib.scala 104:78] + wire _T_638 = _T_634 | _T_637; // @[lib.scala 104:23] + wire _T_640 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[lib.scala 104:36] + wire _T_641 = _T_640 & _T_585; // @[lib.scala 104:41] + wire _T_644 = io_trigger_pkt_any_2_tdata2[8] == lsu_match_data_2[8]; // @[lib.scala 104:78] + wire _T_645 = _T_641 | _T_644; // @[lib.scala 104:23] + wire _T_647 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[lib.scala 104:36] + wire _T_648 = _T_647 & _T_585; // @[lib.scala 104:41] + wire _T_651 = io_trigger_pkt_any_2_tdata2[9] == lsu_match_data_2[9]; // @[lib.scala 104:78] + wire _T_652 = _T_648 | _T_651; // @[lib.scala 104:23] + wire _T_654 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[lib.scala 104:36] + wire _T_655 = _T_654 & _T_585; // @[lib.scala 104:41] + wire _T_658 = io_trigger_pkt_any_2_tdata2[10] == lsu_match_data_2[10]; // @[lib.scala 104:78] + wire _T_659 = _T_655 | _T_658; // @[lib.scala 104:23] + wire _T_661 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[lib.scala 104:36] + wire _T_662 = _T_661 & _T_585; // @[lib.scala 104:41] + wire _T_665 = io_trigger_pkt_any_2_tdata2[11] == lsu_match_data_2[11]; // @[lib.scala 104:78] + wire _T_666 = _T_662 | _T_665; // @[lib.scala 104:23] + wire _T_668 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[lib.scala 104:36] + wire _T_669 = _T_668 & _T_585; // @[lib.scala 104:41] + wire _T_672 = io_trigger_pkt_any_2_tdata2[12] == lsu_match_data_2[12]; // @[lib.scala 104:78] + wire _T_673 = _T_669 | _T_672; // @[lib.scala 104:23] + wire _T_675 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[lib.scala 104:36] + wire _T_676 = _T_675 & _T_585; // @[lib.scala 104:41] + wire _T_679 = io_trigger_pkt_any_2_tdata2[13] == lsu_match_data_2[13]; // @[lib.scala 104:78] + wire _T_680 = _T_676 | _T_679; // @[lib.scala 104:23] + wire _T_682 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[lib.scala 104:36] + wire _T_683 = _T_682 & _T_585; // @[lib.scala 104:41] + wire _T_686 = io_trigger_pkt_any_2_tdata2[14] == lsu_match_data_2[14]; // @[lib.scala 104:78] + wire _T_687 = _T_683 | _T_686; // @[lib.scala 104:23] + wire _T_689 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[lib.scala 104:36] + wire _T_690 = _T_689 & _T_585; // @[lib.scala 104:41] + wire _T_693 = io_trigger_pkt_any_2_tdata2[15] == lsu_match_data_2[15]; // @[lib.scala 104:78] + wire _T_694 = _T_690 | _T_693; // @[lib.scala 104:23] + wire _T_696 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[lib.scala 104:36] + wire _T_697 = _T_696 & _T_585; // @[lib.scala 104:41] + wire _T_700 = io_trigger_pkt_any_2_tdata2[16] == lsu_match_data_2[16]; // @[lib.scala 104:78] + wire _T_701 = _T_697 | _T_700; // @[lib.scala 104:23] + wire _T_703 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[lib.scala 104:36] + wire _T_704 = _T_703 & _T_585; // @[lib.scala 104:41] + wire _T_707 = io_trigger_pkt_any_2_tdata2[17] == lsu_match_data_2[17]; // @[lib.scala 104:78] + wire _T_708 = _T_704 | _T_707; // @[lib.scala 104:23] + wire _T_710 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[lib.scala 104:36] + wire _T_711 = _T_710 & _T_585; // @[lib.scala 104:41] + wire _T_714 = io_trigger_pkt_any_2_tdata2[18] == lsu_match_data_2[18]; // @[lib.scala 104:78] + wire _T_715 = _T_711 | _T_714; // @[lib.scala 104:23] + wire _T_717 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[lib.scala 104:36] + wire _T_718 = _T_717 & _T_585; // @[lib.scala 104:41] + wire _T_721 = io_trigger_pkt_any_2_tdata2[19] == lsu_match_data_2[19]; // @[lib.scala 104:78] + wire _T_722 = _T_718 | _T_721; // @[lib.scala 104:23] + wire _T_724 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[lib.scala 104:36] + wire _T_725 = _T_724 & _T_585; // @[lib.scala 104:41] + wire _T_728 = io_trigger_pkt_any_2_tdata2[20] == lsu_match_data_2[20]; // @[lib.scala 104:78] + wire _T_729 = _T_725 | _T_728; // @[lib.scala 104:23] + wire _T_731 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[lib.scala 104:36] + wire _T_732 = _T_731 & _T_585; // @[lib.scala 104:41] + wire _T_735 = io_trigger_pkt_any_2_tdata2[21] == lsu_match_data_2[21]; // @[lib.scala 104:78] + wire _T_736 = _T_732 | _T_735; // @[lib.scala 104:23] + wire _T_738 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[lib.scala 104:36] + wire _T_739 = _T_738 & _T_585; // @[lib.scala 104:41] + wire _T_742 = io_trigger_pkt_any_2_tdata2[22] == lsu_match_data_2[22]; // @[lib.scala 104:78] + wire _T_743 = _T_739 | _T_742; // @[lib.scala 104:23] + wire _T_745 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[lib.scala 104:36] + wire _T_746 = _T_745 & _T_585; // @[lib.scala 104:41] + wire _T_749 = io_trigger_pkt_any_2_tdata2[23] == lsu_match_data_2[23]; // @[lib.scala 104:78] + wire _T_750 = _T_746 | _T_749; // @[lib.scala 104:23] + wire _T_752 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[lib.scala 104:36] + wire _T_753 = _T_752 & _T_585; // @[lib.scala 104:41] + wire _T_756 = io_trigger_pkt_any_2_tdata2[24] == lsu_match_data_2[24]; // @[lib.scala 104:78] + wire _T_757 = _T_753 | _T_756; // @[lib.scala 104:23] + wire _T_759 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[lib.scala 104:36] + wire _T_760 = _T_759 & _T_585; // @[lib.scala 104:41] + wire _T_763 = io_trigger_pkt_any_2_tdata2[25] == lsu_match_data_2[25]; // @[lib.scala 104:78] + wire _T_764 = _T_760 | _T_763; // @[lib.scala 104:23] + wire _T_766 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[lib.scala 104:36] + wire _T_767 = _T_766 & _T_585; // @[lib.scala 104:41] + wire _T_770 = io_trigger_pkt_any_2_tdata2[26] == lsu_match_data_2[26]; // @[lib.scala 104:78] + wire _T_771 = _T_767 | _T_770; // @[lib.scala 104:23] + wire _T_773 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[lib.scala 104:36] + wire _T_774 = _T_773 & _T_585; // @[lib.scala 104:41] + wire _T_777 = io_trigger_pkt_any_2_tdata2[27] == lsu_match_data_2[27]; // @[lib.scala 104:78] + wire _T_778 = _T_774 | _T_777; // @[lib.scala 104:23] + wire _T_780 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[lib.scala 104:36] + wire _T_781 = _T_780 & _T_585; // @[lib.scala 104:41] + wire _T_784 = io_trigger_pkt_any_2_tdata2[28] == lsu_match_data_2[28]; // @[lib.scala 104:78] + wire _T_785 = _T_781 | _T_784; // @[lib.scala 104:23] + wire _T_787 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[lib.scala 104:36] + wire _T_788 = _T_787 & _T_585; // @[lib.scala 104:41] + wire _T_791 = io_trigger_pkt_any_2_tdata2[29] == lsu_match_data_2[29]; // @[lib.scala 104:78] + wire _T_792 = _T_788 | _T_791; // @[lib.scala 104:23] + wire _T_794 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[lib.scala 104:36] + wire _T_795 = _T_794 & _T_585; // @[lib.scala 104:41] + wire _T_798 = io_trigger_pkt_any_2_tdata2[30] == lsu_match_data_2[30]; // @[lib.scala 104:78] + wire _T_799 = _T_795 | _T_798; // @[lib.scala 104:23] + wire _T_801 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[lib.scala 104:36] + wire _T_802 = _T_801 & _T_585; // @[lib.scala 104:41] + wire _T_805 = io_trigger_pkt_any_2_tdata2[31] == lsu_match_data_2[31]; // @[lib.scala 104:78] + wire _T_806 = _T_802 | _T_805; // @[lib.scala 104:23] + wire [7:0] _T_813 = {_T_638,_T_631,_T_624,_T_617,_T_610,_T_603,_T_596,_T_589}; // @[lib.scala 105:14] + wire [15:0] _T_821 = {_T_694,_T_687,_T_680,_T_673,_T_666,_T_659,_T_652,_T_645,_T_813}; // @[lib.scala 105:14] + wire [7:0] _T_828 = {_T_750,_T_743,_T_736,_T_729,_T_722,_T_715,_T_708,_T_701}; // @[lib.scala 105:14] + wire [31:0] _T_837 = {_T_806,_T_799,_T_792,_T_785,_T_778,_T_771,_T_764,_T_757,_T_828,_T_821}; // @[lib.scala 105:14] + wire _T_838 = &_T_837; // @[lib.scala 105:25] wire _T_839 = _T_580 & _T_838; // @[lsu_trigger.scala 19:92] wire _T_842 = io_trigger_pkt_any_3_store & io_lsu_pkt_m_bits_store; // @[lsu_trigger.scala 18:126] wire _T_843 = io_trigger_pkt_any_3_load & io_lsu_pkt_m_bits_load; // @[lsu_trigger.scala 19:33] wire _T_845 = _T_843 & _T_33; // @[lsu_trigger.scala 19:58] wire _T_846 = _T_842 | _T_845; // @[lsu_trigger.scala 18:152] wire _T_847 = _T_40 & _T_846; // @[lsu_trigger.scala 18:94] - wire _T_850 = &io_trigger_pkt_any_3_tdata2; // @[el2_lib.scala 241:45] - wire _T_851 = ~_T_850; // @[el2_lib.scala 241:39] - wire _T_852 = io_trigger_pkt_any_3_match_pkt & _T_851; // @[el2_lib.scala 241:37] - wire _T_855 = io_trigger_pkt_any_3_tdata2[0] == lsu_match_data_3[0]; // @[el2_lib.scala 242:52] - wire _T_856 = _T_852 | _T_855; // @[el2_lib.scala 242:41] - wire _T_858 = &io_trigger_pkt_any_3_tdata2[0]; // @[el2_lib.scala 244:36] - wire _T_859 = _T_858 & _T_852; // @[el2_lib.scala 244:41] - wire _T_862 = io_trigger_pkt_any_3_tdata2[1] == lsu_match_data_3[1]; // @[el2_lib.scala 244:78] - wire _T_863 = _T_859 | _T_862; // @[el2_lib.scala 244:23] - wire _T_865 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[el2_lib.scala 244:36] - wire _T_866 = _T_865 & _T_852; // @[el2_lib.scala 244:41] - wire _T_869 = io_trigger_pkt_any_3_tdata2[2] == lsu_match_data_3[2]; // @[el2_lib.scala 244:78] - wire _T_870 = _T_866 | _T_869; // @[el2_lib.scala 244:23] - wire _T_872 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[el2_lib.scala 244:36] - wire _T_873 = _T_872 & _T_852; // @[el2_lib.scala 244:41] - wire _T_876 = io_trigger_pkt_any_3_tdata2[3] == lsu_match_data_3[3]; // @[el2_lib.scala 244:78] - wire _T_877 = _T_873 | _T_876; // @[el2_lib.scala 244:23] - wire _T_879 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[el2_lib.scala 244:36] - wire _T_880 = _T_879 & _T_852; // @[el2_lib.scala 244:41] - wire _T_883 = io_trigger_pkt_any_3_tdata2[4] == lsu_match_data_3[4]; // @[el2_lib.scala 244:78] - wire _T_884 = _T_880 | _T_883; // @[el2_lib.scala 244:23] - wire _T_886 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[el2_lib.scala 244:36] - wire _T_887 = _T_886 & _T_852; // @[el2_lib.scala 244:41] - wire _T_890 = io_trigger_pkt_any_3_tdata2[5] == lsu_match_data_3[5]; // @[el2_lib.scala 244:78] - wire _T_891 = _T_887 | _T_890; // @[el2_lib.scala 244:23] - wire _T_893 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[el2_lib.scala 244:36] - wire _T_894 = _T_893 & _T_852; // @[el2_lib.scala 244:41] - wire _T_897 = io_trigger_pkt_any_3_tdata2[6] == lsu_match_data_3[6]; // @[el2_lib.scala 244:78] - wire _T_898 = _T_894 | _T_897; // @[el2_lib.scala 244:23] - wire _T_900 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[el2_lib.scala 244:36] - wire _T_901 = _T_900 & _T_852; // @[el2_lib.scala 244:41] - wire _T_904 = io_trigger_pkt_any_3_tdata2[7] == lsu_match_data_3[7]; // @[el2_lib.scala 244:78] - wire _T_905 = _T_901 | _T_904; // @[el2_lib.scala 244:23] - wire _T_907 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[el2_lib.scala 244:36] - wire _T_908 = _T_907 & _T_852; // @[el2_lib.scala 244:41] - wire _T_911 = io_trigger_pkt_any_3_tdata2[8] == lsu_match_data_3[8]; // @[el2_lib.scala 244:78] - wire _T_912 = _T_908 | _T_911; // @[el2_lib.scala 244:23] - wire _T_914 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[el2_lib.scala 244:36] - wire _T_915 = _T_914 & _T_852; // @[el2_lib.scala 244:41] - wire _T_918 = io_trigger_pkt_any_3_tdata2[9] == lsu_match_data_3[9]; // @[el2_lib.scala 244:78] - wire _T_919 = _T_915 | _T_918; // @[el2_lib.scala 244:23] - wire _T_921 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[el2_lib.scala 244:36] - wire _T_922 = _T_921 & _T_852; // @[el2_lib.scala 244:41] - wire _T_925 = io_trigger_pkt_any_3_tdata2[10] == lsu_match_data_3[10]; // @[el2_lib.scala 244:78] - wire _T_926 = _T_922 | _T_925; // @[el2_lib.scala 244:23] - wire _T_928 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[el2_lib.scala 244:36] - wire _T_929 = _T_928 & _T_852; // @[el2_lib.scala 244:41] - wire _T_932 = io_trigger_pkt_any_3_tdata2[11] == lsu_match_data_3[11]; // @[el2_lib.scala 244:78] - wire _T_933 = _T_929 | _T_932; // @[el2_lib.scala 244:23] - wire _T_935 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[el2_lib.scala 244:36] - wire _T_936 = _T_935 & _T_852; // @[el2_lib.scala 244:41] - wire _T_939 = io_trigger_pkt_any_3_tdata2[12] == lsu_match_data_3[12]; // @[el2_lib.scala 244:78] - wire _T_940 = _T_936 | _T_939; // @[el2_lib.scala 244:23] - wire _T_942 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[el2_lib.scala 244:36] - wire _T_943 = _T_942 & _T_852; // @[el2_lib.scala 244:41] - wire _T_946 = io_trigger_pkt_any_3_tdata2[13] == lsu_match_data_3[13]; // @[el2_lib.scala 244:78] - wire _T_947 = _T_943 | _T_946; // @[el2_lib.scala 244:23] - wire _T_949 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[el2_lib.scala 244:36] - wire _T_950 = _T_949 & _T_852; // @[el2_lib.scala 244:41] - wire _T_953 = io_trigger_pkt_any_3_tdata2[14] == lsu_match_data_3[14]; // @[el2_lib.scala 244:78] - wire _T_954 = _T_950 | _T_953; // @[el2_lib.scala 244:23] - wire _T_956 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[el2_lib.scala 244:36] - wire _T_957 = _T_956 & _T_852; // @[el2_lib.scala 244:41] - wire _T_960 = io_trigger_pkt_any_3_tdata2[15] == lsu_match_data_3[15]; // @[el2_lib.scala 244:78] - wire _T_961 = _T_957 | _T_960; // @[el2_lib.scala 244:23] - wire _T_963 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[el2_lib.scala 244:36] - wire _T_964 = _T_963 & _T_852; // @[el2_lib.scala 244:41] - wire _T_967 = io_trigger_pkt_any_3_tdata2[16] == lsu_match_data_3[16]; // @[el2_lib.scala 244:78] - wire _T_968 = _T_964 | _T_967; // @[el2_lib.scala 244:23] - wire _T_970 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[el2_lib.scala 244:36] - wire _T_971 = _T_970 & _T_852; // @[el2_lib.scala 244:41] - wire _T_974 = io_trigger_pkt_any_3_tdata2[17] == lsu_match_data_3[17]; // @[el2_lib.scala 244:78] - wire _T_975 = _T_971 | _T_974; // @[el2_lib.scala 244:23] - wire _T_977 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[el2_lib.scala 244:36] - wire _T_978 = _T_977 & _T_852; // @[el2_lib.scala 244:41] - wire _T_981 = io_trigger_pkt_any_3_tdata2[18] == lsu_match_data_3[18]; // @[el2_lib.scala 244:78] - wire _T_982 = _T_978 | _T_981; // @[el2_lib.scala 244:23] - wire _T_984 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[el2_lib.scala 244:36] - wire _T_985 = _T_984 & _T_852; // @[el2_lib.scala 244:41] - wire _T_988 = io_trigger_pkt_any_3_tdata2[19] == lsu_match_data_3[19]; // @[el2_lib.scala 244:78] - wire _T_989 = _T_985 | _T_988; // @[el2_lib.scala 244:23] - wire _T_991 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[el2_lib.scala 244:36] - wire _T_992 = _T_991 & _T_852; // @[el2_lib.scala 244:41] - wire _T_995 = io_trigger_pkt_any_3_tdata2[20] == lsu_match_data_3[20]; // @[el2_lib.scala 244:78] - wire _T_996 = _T_992 | _T_995; // @[el2_lib.scala 244:23] - wire _T_998 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[el2_lib.scala 244:36] - wire _T_999 = _T_998 & _T_852; // @[el2_lib.scala 244:41] - wire _T_1002 = io_trigger_pkt_any_3_tdata2[21] == lsu_match_data_3[21]; // @[el2_lib.scala 244:78] - wire _T_1003 = _T_999 | _T_1002; // @[el2_lib.scala 244:23] - wire _T_1005 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[el2_lib.scala 244:36] - wire _T_1006 = _T_1005 & _T_852; // @[el2_lib.scala 244:41] - wire _T_1009 = io_trigger_pkt_any_3_tdata2[22] == lsu_match_data_3[22]; // @[el2_lib.scala 244:78] - wire _T_1010 = _T_1006 | _T_1009; // @[el2_lib.scala 244:23] - wire _T_1012 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[el2_lib.scala 244:36] - wire _T_1013 = _T_1012 & _T_852; // @[el2_lib.scala 244:41] - wire _T_1016 = io_trigger_pkt_any_3_tdata2[23] == lsu_match_data_3[23]; // @[el2_lib.scala 244:78] - wire _T_1017 = _T_1013 | _T_1016; // @[el2_lib.scala 244:23] - wire _T_1019 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[el2_lib.scala 244:36] - wire _T_1020 = _T_1019 & _T_852; // @[el2_lib.scala 244:41] - wire _T_1023 = io_trigger_pkt_any_3_tdata2[24] == lsu_match_data_3[24]; // @[el2_lib.scala 244:78] - wire _T_1024 = _T_1020 | _T_1023; // @[el2_lib.scala 244:23] - wire _T_1026 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[el2_lib.scala 244:36] - wire _T_1027 = _T_1026 & _T_852; // @[el2_lib.scala 244:41] - wire _T_1030 = io_trigger_pkt_any_3_tdata2[25] == lsu_match_data_3[25]; // @[el2_lib.scala 244:78] - wire _T_1031 = _T_1027 | _T_1030; // @[el2_lib.scala 244:23] - wire _T_1033 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[el2_lib.scala 244:36] - wire _T_1034 = _T_1033 & _T_852; // @[el2_lib.scala 244:41] - wire _T_1037 = io_trigger_pkt_any_3_tdata2[26] == lsu_match_data_3[26]; // @[el2_lib.scala 244:78] - wire _T_1038 = _T_1034 | _T_1037; // @[el2_lib.scala 244:23] - wire _T_1040 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[el2_lib.scala 244:36] - wire _T_1041 = _T_1040 & _T_852; // @[el2_lib.scala 244:41] - wire _T_1044 = io_trigger_pkt_any_3_tdata2[27] == lsu_match_data_3[27]; // @[el2_lib.scala 244:78] - wire _T_1045 = _T_1041 | _T_1044; // @[el2_lib.scala 244:23] - wire _T_1047 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[el2_lib.scala 244:36] - wire _T_1048 = _T_1047 & _T_852; // @[el2_lib.scala 244:41] - wire _T_1051 = io_trigger_pkt_any_3_tdata2[28] == lsu_match_data_3[28]; // @[el2_lib.scala 244:78] - wire _T_1052 = _T_1048 | _T_1051; // @[el2_lib.scala 244:23] - wire _T_1054 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[el2_lib.scala 244:36] - wire _T_1055 = _T_1054 & _T_852; // @[el2_lib.scala 244:41] - wire _T_1058 = io_trigger_pkt_any_3_tdata2[29] == lsu_match_data_3[29]; // @[el2_lib.scala 244:78] - wire _T_1059 = _T_1055 | _T_1058; // @[el2_lib.scala 244:23] - wire _T_1061 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[el2_lib.scala 244:36] - wire _T_1062 = _T_1061 & _T_852; // @[el2_lib.scala 244:41] - wire _T_1065 = io_trigger_pkt_any_3_tdata2[30] == lsu_match_data_3[30]; // @[el2_lib.scala 244:78] - wire _T_1066 = _T_1062 | _T_1065; // @[el2_lib.scala 244:23] - wire _T_1068 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[el2_lib.scala 244:36] - wire _T_1069 = _T_1068 & _T_852; // @[el2_lib.scala 244:41] - wire _T_1072 = io_trigger_pkt_any_3_tdata2[31] == lsu_match_data_3[31]; // @[el2_lib.scala 244:78] - wire _T_1073 = _T_1069 | _T_1072; // @[el2_lib.scala 244:23] - wire [7:0] _T_1080 = {_T_905,_T_898,_T_891,_T_884,_T_877,_T_870,_T_863,_T_856}; // @[el2_lib.scala 245:14] - wire [15:0] _T_1088 = {_T_961,_T_954,_T_947,_T_940,_T_933,_T_926,_T_919,_T_912,_T_1080}; // @[el2_lib.scala 245:14] - wire [7:0] _T_1095 = {_T_1017,_T_1010,_T_1003,_T_996,_T_989,_T_982,_T_975,_T_968}; // @[el2_lib.scala 245:14] - wire [31:0] _T_1104 = {_T_1073,_T_1066,_T_1059,_T_1052,_T_1045,_T_1038,_T_1031,_T_1024,_T_1095,_T_1088}; // @[el2_lib.scala 245:14] - wire _T_1105 = &_T_1104; // @[el2_lib.scala 245:25] + wire _T_850 = &io_trigger_pkt_any_3_tdata2; // @[lib.scala 101:45] + wire _T_851 = ~_T_850; // @[lib.scala 101:39] + wire _T_852 = io_trigger_pkt_any_3_match_pkt & _T_851; // @[lib.scala 101:37] + wire _T_855 = io_trigger_pkt_any_3_tdata2[0] == lsu_match_data_3[0]; // @[lib.scala 102:52] + wire _T_856 = _T_852 | _T_855; // @[lib.scala 102:41] + wire _T_858 = &io_trigger_pkt_any_3_tdata2[0]; // @[lib.scala 104:36] + wire _T_859 = _T_858 & _T_852; // @[lib.scala 104:41] + wire _T_862 = io_trigger_pkt_any_3_tdata2[1] == lsu_match_data_3[1]; // @[lib.scala 104:78] + wire _T_863 = _T_859 | _T_862; // @[lib.scala 104:23] + wire _T_865 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[lib.scala 104:36] + wire _T_866 = _T_865 & _T_852; // @[lib.scala 104:41] + wire _T_869 = io_trigger_pkt_any_3_tdata2[2] == lsu_match_data_3[2]; // @[lib.scala 104:78] + wire _T_870 = _T_866 | _T_869; // @[lib.scala 104:23] + wire _T_872 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[lib.scala 104:36] + wire _T_873 = _T_872 & _T_852; // @[lib.scala 104:41] + wire _T_876 = io_trigger_pkt_any_3_tdata2[3] == lsu_match_data_3[3]; // @[lib.scala 104:78] + wire _T_877 = _T_873 | _T_876; // @[lib.scala 104:23] + wire _T_879 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[lib.scala 104:36] + wire _T_880 = _T_879 & _T_852; // @[lib.scala 104:41] + wire _T_883 = io_trigger_pkt_any_3_tdata2[4] == lsu_match_data_3[4]; // @[lib.scala 104:78] + wire _T_884 = _T_880 | _T_883; // @[lib.scala 104:23] + wire _T_886 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[lib.scala 104:36] + wire _T_887 = _T_886 & _T_852; // @[lib.scala 104:41] + wire _T_890 = io_trigger_pkt_any_3_tdata2[5] == lsu_match_data_3[5]; // @[lib.scala 104:78] + wire _T_891 = _T_887 | _T_890; // @[lib.scala 104:23] + wire _T_893 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[lib.scala 104:36] + wire _T_894 = _T_893 & _T_852; // @[lib.scala 104:41] + wire _T_897 = io_trigger_pkt_any_3_tdata2[6] == lsu_match_data_3[6]; // @[lib.scala 104:78] + wire _T_898 = _T_894 | _T_897; // @[lib.scala 104:23] + wire _T_900 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[lib.scala 104:36] + wire _T_901 = _T_900 & _T_852; // @[lib.scala 104:41] + wire _T_904 = io_trigger_pkt_any_3_tdata2[7] == lsu_match_data_3[7]; // @[lib.scala 104:78] + wire _T_905 = _T_901 | _T_904; // @[lib.scala 104:23] + wire _T_907 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[lib.scala 104:36] + wire _T_908 = _T_907 & _T_852; // @[lib.scala 104:41] + wire _T_911 = io_trigger_pkt_any_3_tdata2[8] == lsu_match_data_3[8]; // @[lib.scala 104:78] + wire _T_912 = _T_908 | _T_911; // @[lib.scala 104:23] + wire _T_914 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[lib.scala 104:36] + wire _T_915 = _T_914 & _T_852; // @[lib.scala 104:41] + wire _T_918 = io_trigger_pkt_any_3_tdata2[9] == lsu_match_data_3[9]; // @[lib.scala 104:78] + wire _T_919 = _T_915 | _T_918; // @[lib.scala 104:23] + wire _T_921 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[lib.scala 104:36] + wire _T_922 = _T_921 & _T_852; // @[lib.scala 104:41] + wire _T_925 = io_trigger_pkt_any_3_tdata2[10] == lsu_match_data_3[10]; // @[lib.scala 104:78] + wire _T_926 = _T_922 | _T_925; // @[lib.scala 104:23] + wire _T_928 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[lib.scala 104:36] + wire _T_929 = _T_928 & _T_852; // @[lib.scala 104:41] + wire _T_932 = io_trigger_pkt_any_3_tdata2[11] == lsu_match_data_3[11]; // @[lib.scala 104:78] + wire _T_933 = _T_929 | _T_932; // @[lib.scala 104:23] + wire _T_935 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[lib.scala 104:36] + wire _T_936 = _T_935 & _T_852; // @[lib.scala 104:41] + wire _T_939 = io_trigger_pkt_any_3_tdata2[12] == lsu_match_data_3[12]; // @[lib.scala 104:78] + wire _T_940 = _T_936 | _T_939; // @[lib.scala 104:23] + wire _T_942 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[lib.scala 104:36] + wire _T_943 = _T_942 & _T_852; // @[lib.scala 104:41] + wire _T_946 = io_trigger_pkt_any_3_tdata2[13] == lsu_match_data_3[13]; // @[lib.scala 104:78] + wire _T_947 = _T_943 | _T_946; // @[lib.scala 104:23] + wire _T_949 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[lib.scala 104:36] + wire _T_950 = _T_949 & _T_852; // @[lib.scala 104:41] + wire _T_953 = io_trigger_pkt_any_3_tdata2[14] == lsu_match_data_3[14]; // @[lib.scala 104:78] + wire _T_954 = _T_950 | _T_953; // @[lib.scala 104:23] + wire _T_956 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[lib.scala 104:36] + wire _T_957 = _T_956 & _T_852; // @[lib.scala 104:41] + wire _T_960 = io_trigger_pkt_any_3_tdata2[15] == lsu_match_data_3[15]; // @[lib.scala 104:78] + wire _T_961 = _T_957 | _T_960; // @[lib.scala 104:23] + wire _T_963 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[lib.scala 104:36] + wire _T_964 = _T_963 & _T_852; // @[lib.scala 104:41] + wire _T_967 = io_trigger_pkt_any_3_tdata2[16] == lsu_match_data_3[16]; // @[lib.scala 104:78] + wire _T_968 = _T_964 | _T_967; // @[lib.scala 104:23] + wire _T_970 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[lib.scala 104:36] + wire _T_971 = _T_970 & _T_852; // @[lib.scala 104:41] + wire _T_974 = io_trigger_pkt_any_3_tdata2[17] == lsu_match_data_3[17]; // @[lib.scala 104:78] + wire _T_975 = _T_971 | _T_974; // @[lib.scala 104:23] + wire _T_977 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[lib.scala 104:36] + wire _T_978 = _T_977 & _T_852; // @[lib.scala 104:41] + wire _T_981 = io_trigger_pkt_any_3_tdata2[18] == lsu_match_data_3[18]; // @[lib.scala 104:78] + wire _T_982 = _T_978 | _T_981; // @[lib.scala 104:23] + wire _T_984 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[lib.scala 104:36] + wire _T_985 = _T_984 & _T_852; // @[lib.scala 104:41] + wire _T_988 = io_trigger_pkt_any_3_tdata2[19] == lsu_match_data_3[19]; // @[lib.scala 104:78] + wire _T_989 = _T_985 | _T_988; // @[lib.scala 104:23] + wire _T_991 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[lib.scala 104:36] + wire _T_992 = _T_991 & _T_852; // @[lib.scala 104:41] + wire _T_995 = io_trigger_pkt_any_3_tdata2[20] == lsu_match_data_3[20]; // @[lib.scala 104:78] + wire _T_996 = _T_992 | _T_995; // @[lib.scala 104:23] + wire _T_998 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[lib.scala 104:36] + wire _T_999 = _T_998 & _T_852; // @[lib.scala 104:41] + wire _T_1002 = io_trigger_pkt_any_3_tdata2[21] == lsu_match_data_3[21]; // @[lib.scala 104:78] + wire _T_1003 = _T_999 | _T_1002; // @[lib.scala 104:23] + wire _T_1005 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[lib.scala 104:36] + wire _T_1006 = _T_1005 & _T_852; // @[lib.scala 104:41] + wire _T_1009 = io_trigger_pkt_any_3_tdata2[22] == lsu_match_data_3[22]; // @[lib.scala 104:78] + wire _T_1010 = _T_1006 | _T_1009; // @[lib.scala 104:23] + wire _T_1012 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[lib.scala 104:36] + wire _T_1013 = _T_1012 & _T_852; // @[lib.scala 104:41] + wire _T_1016 = io_trigger_pkt_any_3_tdata2[23] == lsu_match_data_3[23]; // @[lib.scala 104:78] + wire _T_1017 = _T_1013 | _T_1016; // @[lib.scala 104:23] + wire _T_1019 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[lib.scala 104:36] + wire _T_1020 = _T_1019 & _T_852; // @[lib.scala 104:41] + wire _T_1023 = io_trigger_pkt_any_3_tdata2[24] == lsu_match_data_3[24]; // @[lib.scala 104:78] + wire _T_1024 = _T_1020 | _T_1023; // @[lib.scala 104:23] + wire _T_1026 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[lib.scala 104:36] + wire _T_1027 = _T_1026 & _T_852; // @[lib.scala 104:41] + wire _T_1030 = io_trigger_pkt_any_3_tdata2[25] == lsu_match_data_3[25]; // @[lib.scala 104:78] + wire _T_1031 = _T_1027 | _T_1030; // @[lib.scala 104:23] + wire _T_1033 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[lib.scala 104:36] + wire _T_1034 = _T_1033 & _T_852; // @[lib.scala 104:41] + wire _T_1037 = io_trigger_pkt_any_3_tdata2[26] == lsu_match_data_3[26]; // @[lib.scala 104:78] + wire _T_1038 = _T_1034 | _T_1037; // @[lib.scala 104:23] + wire _T_1040 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[lib.scala 104:36] + wire _T_1041 = _T_1040 & _T_852; // @[lib.scala 104:41] + wire _T_1044 = io_trigger_pkt_any_3_tdata2[27] == lsu_match_data_3[27]; // @[lib.scala 104:78] + wire _T_1045 = _T_1041 | _T_1044; // @[lib.scala 104:23] + wire _T_1047 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[lib.scala 104:36] + wire _T_1048 = _T_1047 & _T_852; // @[lib.scala 104:41] + wire _T_1051 = io_trigger_pkt_any_3_tdata2[28] == lsu_match_data_3[28]; // @[lib.scala 104:78] + wire _T_1052 = _T_1048 | _T_1051; // @[lib.scala 104:23] + wire _T_1054 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[lib.scala 104:36] + wire _T_1055 = _T_1054 & _T_852; // @[lib.scala 104:41] + wire _T_1058 = io_trigger_pkt_any_3_tdata2[29] == lsu_match_data_3[29]; // @[lib.scala 104:78] + wire _T_1059 = _T_1055 | _T_1058; // @[lib.scala 104:23] + wire _T_1061 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[lib.scala 104:36] + wire _T_1062 = _T_1061 & _T_852; // @[lib.scala 104:41] + wire _T_1065 = io_trigger_pkt_any_3_tdata2[30] == lsu_match_data_3[30]; // @[lib.scala 104:78] + wire _T_1066 = _T_1062 | _T_1065; // @[lib.scala 104:23] + wire _T_1068 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[lib.scala 104:36] + wire _T_1069 = _T_1068 & _T_852; // @[lib.scala 104:41] + wire _T_1072 = io_trigger_pkt_any_3_tdata2[31] == lsu_match_data_3[31]; // @[lib.scala 104:78] + wire _T_1073 = _T_1069 | _T_1072; // @[lib.scala 104:23] + wire [7:0] _T_1080 = {_T_905,_T_898,_T_891,_T_884,_T_877,_T_870,_T_863,_T_856}; // @[lib.scala 105:14] + wire [15:0] _T_1088 = {_T_961,_T_954,_T_947,_T_940,_T_933,_T_926,_T_919,_T_912,_T_1080}; // @[lib.scala 105:14] + wire [7:0] _T_1095 = {_T_1017,_T_1010,_T_1003,_T_996,_T_989,_T_982,_T_975,_T_968}; // @[lib.scala 105:14] + wire [31:0] _T_1104 = {_T_1073,_T_1066,_T_1059,_T_1052,_T_1045,_T_1038,_T_1031,_T_1024,_T_1095,_T_1088}; // @[lib.scala 105:14] + wire _T_1105 = &_T_1104; // @[lib.scala 105:25] wire _T_1106 = _T_847 & _T_1105; // @[lsu_trigger.scala 19:92] wire [2:0] _T_1108 = {_T_1106,_T_839,_T_572}; // @[Cat.scala 29:58] assign io_lsu_trigger_match_m = {_T_1108,_T_305}; // @[lsu_trigger.scala 18:26] @@ -67804,54 +67800,54 @@ module lsu_clkdomain( reg [31:0] _RAND_2; reg [31:0] _RAND_3; `endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_1_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_1_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_2_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_2_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_3_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_3_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_4_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_4_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_5_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_5_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_6_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_6_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_7_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_7_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_8_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_8_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_9_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_9_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_10_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_10_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_11_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_11_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_io_en; // @[lib.scala 343:22] + wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_en; // @[lib.scala 343:22] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_2_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_2_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_2_io_en; // @[lib.scala 343:22] + wire rvclkhdr_2_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_3_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_3_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_3_io_en; // @[lib.scala 343:22] + wire rvclkhdr_3_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_4_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_4_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_4_io_en; // @[lib.scala 343:22] + wire rvclkhdr_4_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_5_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_5_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_5_io_en; // @[lib.scala 343:22] + wire rvclkhdr_5_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_6_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_6_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_6_io_en; // @[lib.scala 343:22] + wire rvclkhdr_6_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_7_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_7_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_7_io_en; // @[lib.scala 343:22] + wire rvclkhdr_7_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_8_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_8_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_8_io_en; // @[lib.scala 343:22] + wire rvclkhdr_8_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_9_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_9_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_9_io_en; // @[lib.scala 343:22] + wire rvclkhdr_9_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_10_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_10_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_10_io_en; // @[lib.scala 343:22] + wire rvclkhdr_10_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_11_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_11_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_11_io_en; // @[lib.scala 343:22] + wire rvclkhdr_11_io_scan_mode; // @[lib.scala 343:22] wire _T = io_lsu_p_valid | io_dma_dccm_req; // @[lsu_clkdomain.scala 62:51] reg lsu_c1_d_clken_q; // @[lsu_clkdomain.scala 81:67] wire _T_1 = io_lsu_pkt_d_valid | lsu_c1_d_clken_q; // @[lsu_clkdomain.scala 63:51] @@ -67879,73 +67875,73 @@ module lsu_clkdomain( wire lsu_free_c1_clken = _T_19 | io_clk_override; // @[lsu_clkdomain.scala 76:169] reg lsu_free_c1_clken_q; // @[lsu_clkdomain.scala 80:60] wire _T_20 = lsu_free_c1_clken | lsu_free_c1_clken_q; // @[lsu_clkdomain.scala 77:50] - rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en), .io_scan_mode(rvclkhdr_io_scan_mode) ); - rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_1_io_l1clk), .io_clk(rvclkhdr_1_io_clk), .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_2 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_2_io_l1clk), .io_clk(rvclkhdr_2_io_clk), .io_en(rvclkhdr_2_io_en), .io_scan_mode(rvclkhdr_2_io_scan_mode) ); - rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_3 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_3_io_l1clk), .io_clk(rvclkhdr_3_io_clk), .io_en(rvclkhdr_3_io_en), .io_scan_mode(rvclkhdr_3_io_scan_mode) ); - rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_4 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_4_io_l1clk), .io_clk(rvclkhdr_4_io_clk), .io_en(rvclkhdr_4_io_en), .io_scan_mode(rvclkhdr_4_io_scan_mode) ); - rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_5 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_5_io_l1clk), .io_clk(rvclkhdr_5_io_clk), .io_en(rvclkhdr_5_io_en), .io_scan_mode(rvclkhdr_5_io_scan_mode) ); - rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_6 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_6_io_l1clk), .io_clk(rvclkhdr_6_io_clk), .io_en(rvclkhdr_6_io_en), .io_scan_mode(rvclkhdr_6_io_scan_mode) ); - rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_7 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_7_io_l1clk), .io_clk(rvclkhdr_7_io_clk), .io_en(rvclkhdr_7_io_en), .io_scan_mode(rvclkhdr_7_io_scan_mode) ); - rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_8 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_8_io_l1clk), .io_clk(rvclkhdr_8_io_clk), .io_en(rvclkhdr_8_io_en), .io_scan_mode(rvclkhdr_8_io_scan_mode) ); - rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_9 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_9_io_l1clk), .io_clk(rvclkhdr_9_io_clk), .io_en(rvclkhdr_9_io_en), .io_scan_mode(rvclkhdr_9_io_scan_mode) ); - rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_10 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_10_io_l1clk), .io_clk(rvclkhdr_10_io_clk), .io_en(rvclkhdr_10_io_en), .io_scan_mode(rvclkhdr_10_io_scan_mode) ); - rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_11 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_11_io_l1clk), .io_clk(rvclkhdr_11_io_clk), .io_en(rvclkhdr_11_io_en), @@ -67963,42 +67959,42 @@ module lsu_clkdomain( assign io_lsu_bus_buf_c1_clk = rvclkhdr_9_io_l1clk; // @[lsu_clkdomain.scala 94:26] assign io_lsu_busm_clk = rvclkhdr_10_io_l1clk; // @[lsu_clkdomain.scala 95:26] assign io_lsu_free_c2_clk = rvclkhdr_11_io_l1clk; // @[lsu_clkdomain.scala 96:26] - assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_io_en = _T_1 | io_clk_override; // @[el2_lib.scala 485:16] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_1_io_en = _T_2 | io_clk_override; // @[el2_lib.scala 485:16] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_2_io_en = _T_3 | io_clk_override; // @[el2_lib.scala 485:16] - assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_3_io_en = _T_4 | io_clk_override; // @[el2_lib.scala 485:16] - assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_4_io_en = _T_5 | io_clk_override; // @[el2_lib.scala 485:16] - assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_5_io_en = _T_6 | io_clk_override; // @[el2_lib.scala 485:16] - assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_6_io_en = _T_8 | io_clk_override; // @[el2_lib.scala 485:16] - assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_7_io_en = io_lsu_busreq_r | io_clk_override; // @[el2_lib.scala 485:16] - assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_8_io_en = _T_10 & io_lsu_bus_clk_en; // @[el2_lib.scala 485:16] - assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_9_io_en = _T_12 | io_clk_override; // @[el2_lib.scala 485:16] - assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_10_io_en = io_lsu_bus_clk_en; // @[el2_lib.scala 485:16] - assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_11_io_en = _T_20 | io_clk_override; // @[el2_lib.scala 485:16] - assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_io_en = _T_1 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_1_io_en = _T_2 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_2_io_en = _T_3 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_3_io_en = _T_4 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_4_io_en = _T_5 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_5_io_en = _T_6 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_6_io_en = _T_8 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_7_io_en = io_lsu_busreq_r | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_8_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_8_io_en = _T_10 & io_lsu_bus_clk_en; // @[lib.scala 345:16] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_9_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_9_io_en = _T_12 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_10_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_10_io_en = io_lsu_bus_clk_en; // @[lib.scala 345:16] + assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_11_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_11_io_en = _T_20 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -68292,57 +68288,57 @@ module lsu_bus_buffer( reg [31:0] _RAND_105; reg [31:0] _RAND_106; `endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_8_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_8_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_9_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_9_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_10_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_10_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_11_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_11_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_io_en; // @[lib.scala 368:23] + wire rvclkhdr_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_en; // @[lib.scala 368:23] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_en; // @[lib.scala 368:23] + wire rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_en; // @[lib.scala 368:23] + wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_en; // @[lib.scala 368:23] + wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_5_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_en; // @[lib.scala 368:23] + wire rvclkhdr_5_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_6_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_6_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_6_io_en; // @[lib.scala 368:23] + wire rvclkhdr_6_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_7_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_7_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_7_io_en; // @[lib.scala 368:23] + wire rvclkhdr_7_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_8_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_8_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_8_io_en; // @[lib.scala 368:23] + wire rvclkhdr_8_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_9_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_9_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_9_io_en; // @[lib.scala 368:23] + wire rvclkhdr_9_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_10_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_10_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_10_io_en; // @[lib.scala 368:23] + wire rvclkhdr_10_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_11_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_11_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_11_io_en; // @[lib.scala 368:23] + wire rvclkhdr_11_io_scan_mode; // @[lib.scala 368:23] wire [3:0] ldst_byteen_hi_m = io_ldst_byteen_ext_m[7:4]; // @[lsu_bus_buffer.scala 73:46] wire [3:0] ldst_byteen_lo_m = io_ldst_byteen_ext_m[3:0]; // @[lsu_bus_buffer.scala 74:46] - reg [31:0] buf_addr_0; // @[el2_lib.scala 514:16] + reg [31:0] buf_addr_0; // @[lib.scala 374:16] wire _T_2 = io_lsu_addr_m[31:2] == buf_addr_0[31:2]; // @[lsu_bus_buffer.scala 76:74] reg _T_4360; // @[Reg.scala 27:20] reg _T_4357; // @[Reg.scala 27:20] @@ -68354,21 +68350,21 @@ module lsu_bus_buffer( wire _T_5 = buf_state_0 != 3'h0; // @[lsu_bus_buffer.scala 76:129] wire _T_6 = _T_4 & _T_5; // @[lsu_bus_buffer.scala 76:113] wire ld_addr_hitvec_lo_0 = _T_6 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 76:141] - reg [31:0] buf_addr_1; // @[el2_lib.scala 514:16] + reg [31:0] buf_addr_1; // @[lib.scala 374:16] wire _T_9 = io_lsu_addr_m[31:2] == buf_addr_1[31:2]; // @[lsu_bus_buffer.scala 76:74] wire _T_11 = _T_9 & buf_write[1]; // @[lsu_bus_buffer.scala 76:98] reg [2:0] buf_state_1; // @[Reg.scala 27:20] wire _T_12 = buf_state_1 != 3'h0; // @[lsu_bus_buffer.scala 76:129] wire _T_13 = _T_11 & _T_12; // @[lsu_bus_buffer.scala 76:113] wire ld_addr_hitvec_lo_1 = _T_13 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 76:141] - reg [31:0] buf_addr_2; // @[el2_lib.scala 514:16] + reg [31:0] buf_addr_2; // @[lib.scala 374:16] wire _T_16 = io_lsu_addr_m[31:2] == buf_addr_2[31:2]; // @[lsu_bus_buffer.scala 76:74] wire _T_18 = _T_16 & buf_write[2]; // @[lsu_bus_buffer.scala 76:98] reg [2:0] buf_state_2; // @[Reg.scala 27:20] wire _T_19 = buf_state_2 != 3'h0; // @[lsu_bus_buffer.scala 76:129] wire _T_20 = _T_18 & _T_19; // @[lsu_bus_buffer.scala 76:113] wire ld_addr_hitvec_lo_2 = _T_20 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 76:141] - reg [31:0] buf_addr_3; // @[el2_lib.scala 514:16] + reg [31:0] buf_addr_3; // @[lib.scala 374:16] wire _T_23 = io_lsu_addr_m[31:2] == buf_addr_3[31:2]; // @[lsu_bus_buffer.scala 76:74] wire _T_25 = _T_23 & buf_write[3]; // @[lsu_bus_buffer.scala 76:98] reg [2:0] buf_state_3; // @[Reg.scala 27:20] @@ -68488,7 +68484,7 @@ module lsu_bus_buffer( wire _T_256 = |_T_255; // @[lsu_bus_buffer.scala 146:144] wire _T_257 = ~_T_256; // @[lsu_bus_buffer.scala 146:99] wire _T_258 = ld_byte_hitvec_lo_0[3] & _T_257; // @[lsu_bus_buffer.scala 146:97] - reg [31:0] ibuf_addr; // @[el2_lib.scala 514:16] + reg [31:0] ibuf_addr; // @[lib.scala 374:16] wire _T_512 = io_lsu_addr_m[31:2] == ibuf_addr[31:2]; // @[lsu_bus_buffer.scala 152:51] reg ibuf_write; // @[Reg.scala 27:20] wire _T_513 = _T_512 & ibuf_write; // @[lsu_bus_buffer.scala 152:73] @@ -68809,16 +68805,16 @@ module lsu_bus_buffer( wire [7:0] _T_553 = ld_byte_ibuf_hit_hi[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] wire [31:0] ld_fwddata_buf_hi_initial = {_T_553,_T_550,_T_547,_T_544}; // @[Cat.scala 29:58] wire [7:0] _T_558 = ld_byte_hitvecfn_lo_3[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - reg [31:0] buf_data_0; // @[el2_lib.scala 514:16] + reg [31:0] buf_data_0; // @[lib.scala 374:16] wire [7:0] _T_560 = _T_558 & buf_data_0[31:24]; // @[lsu_bus_buffer.scala 165:91] wire [7:0] _T_563 = ld_byte_hitvecfn_lo_3[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - reg [31:0] buf_data_1; // @[el2_lib.scala 514:16] + reg [31:0] buf_data_1; // @[lib.scala 374:16] wire [7:0] _T_565 = _T_563 & buf_data_1[31:24]; // @[lsu_bus_buffer.scala 165:91] wire [7:0] _T_568 = ld_byte_hitvecfn_lo_3[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - reg [31:0] buf_data_2; // @[el2_lib.scala 514:16] + reg [31:0] buf_data_2; // @[lib.scala 374:16] wire [7:0] _T_570 = _T_568 & buf_data_2[31:24]; // @[lsu_bus_buffer.scala 165:91] wire [7:0] _T_573 = ld_byte_hitvecfn_lo_3[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - reg [31:0] buf_data_3; // @[el2_lib.scala 514:16] + reg [31:0] buf_data_3; // @[lib.scala 374:16] wire [7:0] _T_575 = _T_573 & buf_data_3[31:24]; // @[lsu_bus_buffer.scala 165:91] wire [7:0] _T_576 = _T_560 | _T_565; // @[lsu_bus_buffer.scala 165:123] wire [7:0] _T_577 = _T_576 | _T_570; // @[lsu_bus_buffer.scala 165:123] @@ -68857,7 +68853,7 @@ module lsu_bus_buffer( wire [7:0] _T_646 = _T_645 | _T_639; // @[lsu_bus_buffer.scala 168:97] wire [7:0] _T_647 = _T_646 | _T_644; // @[lsu_bus_buffer.scala 168:97] wire [31:0] _T_650 = {_T_578,_T_601,_T_624,_T_647}; // @[Cat.scala 29:58] - reg [31:0] ibuf_data; // @[el2_lib.scala 514:16] + reg [31:0] ibuf_data; // @[lib.scala 374:16] wire [31:0] _T_651 = ld_fwddata_buf_lo_initial & ibuf_data; // @[lsu_bus_buffer.scala 169:32] wire [7:0] _T_655 = ld_byte_hitvecfn_hi_3[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] wire [7:0] _T_657 = _T_655 & buf_data_0[31:24]; // @[lsu_bus_buffer.scala 171:91] @@ -69308,7 +69304,7 @@ module lsu_bus_buffer( wire _T_1234 = _T_1230 & _T_1233; // @[lsu_bus_buffer.scala 288:29] wire _T_1235 = ~obuf_wr_wait; // @[lsu_bus_buffer.scala 288:77] wire _T_1236 = _T_1234 & _T_1235; // @[lsu_bus_buffer.scala 288:75] - reg [31:0] obuf_addr; // @[el2_lib.scala 514:16] + reg [31:0] obuf_addr; // @[lib.scala 374:16] wire _T_4804 = obuf_addr[31:3] == buf_addr_0[31:3]; // @[lsu_bus_buffer.scala 554:56] wire _T_4805 = obuf_valid & _T_4804; // @[lsu_bus_buffer.scala 554:38] wire _T_4807 = obuf_tag1 == 2'h0; // @[lsu_bus_buffer.scala 554:126] @@ -69565,7 +69561,7 @@ module lsu_bus_buffer( wire _T_1840 = ~obuf_rst; // @[lsu_bus_buffer.scala 346:93] reg [1:0] obuf_sz; // @[Reg.scala 27:20] reg [7:0] obuf_byteen; // @[Reg.scala 27:20] - reg [63:0] obuf_data; // @[el2_lib.scala 514:16] + reg [63:0] obuf_data; // @[lib.scala 374:16] wire _T_1853 = buf_state_0 == 3'h0; // @[lsu_bus_buffer.scala 364:65] wire _T_1854 = ibuf_tag == 2'h0; // @[lsu_bus_buffer.scala 365:30] wire _T_1855 = ibuf_valid & _T_1854; // @[lsu_bus_buffer.scala 365:19] @@ -70704,73 +70700,73 @@ module lsu_bus_buffer( wire _T_4983 = ~io_flush_r; // @[lsu_bus_buffer.scala 617:75] wire _T_4984 = io_lsu_busreq_m & _T_4983; // @[lsu_bus_buffer.scala 617:73] reg _T_4987; // @[lsu_bus_buffer.scala 617:56] - rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en), .io_scan_mode(rvclkhdr_io_scan_mode) ); - rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_1 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_1_io_l1clk), .io_clk(rvclkhdr_1_io_clk), .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_2_io_l1clk), .io_clk(rvclkhdr_2_io_clk), .io_en(rvclkhdr_2_io_en), .io_scan_mode(rvclkhdr_2_io_scan_mode) ); - rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_3_io_l1clk), .io_clk(rvclkhdr_3_io_clk), .io_en(rvclkhdr_3_io_en), .io_scan_mode(rvclkhdr_3_io_scan_mode) ); - rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_4_io_l1clk), .io_clk(rvclkhdr_4_io_clk), .io_en(rvclkhdr_4_io_en), .io_scan_mode(rvclkhdr_4_io_scan_mode) ); - rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_5 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_5_io_l1clk), .io_clk(rvclkhdr_5_io_clk), .io_en(rvclkhdr_5_io_en), .io_scan_mode(rvclkhdr_5_io_scan_mode) ); - rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_6 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_6_io_l1clk), .io_clk(rvclkhdr_6_io_clk), .io_en(rvclkhdr_6_io_en), .io_scan_mode(rvclkhdr_6_io_scan_mode) ); - rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_7 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_7_io_l1clk), .io_clk(rvclkhdr_7_io_clk), .io_en(rvclkhdr_7_io_en), .io_scan_mode(rvclkhdr_7_io_scan_mode) ); - rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_8 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_8_io_l1clk), .io_clk(rvclkhdr_8_io_clk), .io_en(rvclkhdr_8_io_en), .io_scan_mode(rvclkhdr_8_io_scan_mode) ); - rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_9 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_9_io_l1clk), .io_clk(rvclkhdr_9_io_clk), .io_en(rvclkhdr_9_io_en), .io_scan_mode(rvclkhdr_9_io_scan_mode) ); - rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_10 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_10_io_l1clk), .io_clk(rvclkhdr_10_io_clk), .io_en(rvclkhdr_10_io_en), .io_scan_mode(rvclkhdr_10_io_scan_mode) ); - rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_11 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_11_io_l1clk), .io_clk(rvclkhdr_11_io_clk), .io_en(rvclkhdr_11_io_en), @@ -70816,42 +70812,42 @@ module lsu_bus_buffer( assign io_ld_byte_hit_buf_hi = {_T_84,_T_73}; // @[lsu_bus_buffer.scala 139:25] assign io_ld_fwddata_buf_lo = _T_650 | _T_651; // @[lsu_bus_buffer.scala 165:24] assign io_ld_fwddata_buf_hi = _T_747 | _T_748; // @[lsu_bus_buffer.scala 171:24] - assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_io_en = _T_853 & _T_854; // @[el2_lib.scala 511:17] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_1_io_en = _T_853 & _T_854; // @[el2_lib.scala 511:17] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_2_io_en = _T_1240 & io_lsu_bus_clk_en; // @[el2_lib.scala 511:17] - assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_3_io_en = _T_1240 & io_lsu_bus_clk_en; // @[el2_lib.scala 511:17] - assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_4_io_en = _T_3528 & buf_state_en_0; // @[el2_lib.scala 511:17] - assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_5_io_en = _T_3721 & buf_state_en_1; // @[el2_lib.scala 511:17] - assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_6_io_en = _T_3914 & buf_state_en_2; // @[el2_lib.scala 511:17] - assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_7_io_en = _T_4107 & buf_state_en_3; // @[el2_lib.scala 511:17] - assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_8_io_en = _T_3528 ? buf_state_en_0 : _GEN_70; // @[el2_lib.scala 511:17] - assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_9_io_en = _T_3721 ? buf_state_en_1 : _GEN_146; // @[el2_lib.scala 511:17] - assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_10_io_en = _T_3914 ? buf_state_en_2 : _GEN_222; // @[el2_lib.scala 511:17] - assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_11_io_en = _T_4107 ? buf_state_en_3 : _GEN_298; // @[el2_lib.scala 511:17] - assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_io_en = _T_853 & _T_854; // @[lib.scala 371:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_1_io_en = _T_853 & _T_854; // @[lib.scala 371:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_2_io_en = _T_1240 & io_lsu_bus_clk_en; // @[lib.scala 371:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_3_io_en = _T_1240 & io_lsu_bus_clk_en; // @[lib.scala 371:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_4_io_en = _T_3528 & buf_state_en_0; // @[lib.scala 371:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_5_io_en = _T_3721 & buf_state_en_1; // @[lib.scala 371:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_6_io_en = _T_3914 & buf_state_en_2; // @[lib.scala 371:17] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_7_io_en = _T_4107 & buf_state_en_3; // @[lib.scala 371:17] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_8_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_8_io_en = _T_3528 ? buf_state_en_0 : _GEN_70; // @[lib.scala 371:17] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_9_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_9_io_en = _T_3721 ? buf_state_en_1 : _GEN_146; // @[lib.scala 371:17] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_10_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_10_io_en = _T_3914 ? buf_state_en_2 : _GEN_222; // @[lib.scala 371:17] + assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_11_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_11_io_en = _T_4107 ? buf_state_en_3 : _GEN_298; // @[lib.scala 371:17] + assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -74944,26 +74940,26 @@ module pic_ctrl( reg [31:0] _RAND_135; reg [31:0] _RAND_136; `endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_1_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_1_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_2_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_2_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_3_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_3_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_4_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_4_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_io_en; // @[lib.scala 343:22] + wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_en; // @[lib.scala 343:22] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_2_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_2_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_2_io_en; // @[lib.scala 343:22] + wire rvclkhdr_2_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_3_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_3_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_3_io_en; // @[lib.scala 343:22] + wire rvclkhdr_3_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_4_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_4_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_4_io_en; // @[lib.scala 343:22] + wire rvclkhdr_4_io_scan_mode; // @[lib.scala 343:22] wire pic_raddr_c1_clk = rvclkhdr_io_l1clk; // @[pic_ctrl.scala 95:42 pic_ctrl.scala 132:21] reg [31:0] picm_raddr_ff; // @[pic_ctrl.scala 101:56] wire pic_data_c1_clk = rvclkhdr_1_io_l1clk; // @[pic_ctrl.scala 96:42 pic_ctrl.scala 133:21] @@ -74997,8 +74993,8 @@ module pic_ctrl( wire _T_26 = waddr_config_gw_base_match & picm_wren_ff; // @[pic_ctrl.scala 129:59] wire _T_27 = raddr_config_gw_base_match & picm_rden_ff; // @[pic_ctrl.scala 129:108] wire _T_28 = _T_26 | _T_27; // @[pic_ctrl.scala 129:76] - reg [30:0] _T_33; // @[el2_lib.scala 177:81] - reg [30:0] _T_34; // @[el2_lib.scala 177:58] + reg [30:0] _T_33; // @[lib.scala 37:81] + reg [30:0] _T_34; // @[lib.scala 37:58] wire [31:0] extintsrc_req_sync = {_T_34,io_extintsrc_req[0]}; // @[Cat.scala 29:58] wire _T_37 = picm_waddr_ff[6:2] == 5'h1; // @[pic_ctrl.scala 141:139] wire _T_38 = waddr_intpriority_base_match & _T_37; // @[pic_ctrl.scala 141:106] @@ -76670,31 +76666,31 @@ module pic_ctrl( wire [7:0] level_intpend_id_5_31 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] wire [7:0] level_intpend_id_5_32 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] wire [7:0] level_intpend_id_5_33 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] - rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en), .io_scan_mode(rvclkhdr_io_scan_mode) ); - rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_1_io_l1clk), .io_clk(rvclkhdr_1_io_clk), .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_2 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_2_io_l1clk), .io_clk(rvclkhdr_2_io_clk), .io_en(rvclkhdr_2_io_en), .io_scan_mode(rvclkhdr_2_io_scan_mode) ); - rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_3 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_3_io_l1clk), .io_clk(rvclkhdr_3_io_clk), .io_en(rvclkhdr_3_io_en), .io_scan_mode(rvclkhdr_3_io_scan_mode) ); - rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_4 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_4_io_l1clk), .io_clk(rvclkhdr_4_io_clk), .io_en(rvclkhdr_4_io_en), @@ -76705,21 +76701,21 @@ module pic_ctrl( assign io_dec_pic_pic_pl = _T_1643; // @[pic_ctrl.scala 263:44] assign io_dec_pic_mhwakeup = _T_1652; // @[pic_ctrl.scala 270:23] assign io_dec_pic_mexintpend = _T_1650; // @[pic_ctrl.scala 267:25] - assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_io_en = _T_19 | io_clk_override; // @[el2_lib.scala 485:16] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_1_io_en = io_lsu_pic_picm_wren | io_clk_override; // @[el2_lib.scala 485:16] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_2_io_en = _T_22 | io_clk_override; // @[el2_lib.scala 485:16] - assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_3_io_en = _T_25 | io_clk_override; // @[el2_lib.scala 485:16] - assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_4_io_en = _T_28 | io_clk_override; // @[el2_lib.scala 485:16] - assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_io_en = _T_19 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_1_io_en = io_lsu_pic_picm_wren | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_2_io_en = _T_22 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_3_io_en = _T_25 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_4_io_en = _T_28 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -78565,46 +78561,46 @@ module dma_ctrl( reg [31:0] _RAND_77; reg [31:0] _RAND_78; `endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_8_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_8_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_9_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_9_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_io_en; // @[lib.scala 368:23] + wire rvclkhdr_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_1_io_en; // @[lib.scala 368:23] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_en; // @[lib.scala 368:23] + wire rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_en; // @[lib.scala 368:23] + wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_en; // @[lib.scala 368:23] + wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_5_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_en; // @[lib.scala 368:23] + wire rvclkhdr_5_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_6_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_6_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_6_io_en; // @[lib.scala 368:23] + wire rvclkhdr_6_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_7_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_7_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_7_io_en; // @[lib.scala 368:23] + wire rvclkhdr_7_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_8_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_8_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_8_io_en; // @[lib.scala 368:23] + wire rvclkhdr_8_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_9_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_9_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_9_io_en; // @[lib.scala 368:23] + wire rvclkhdr_9_io_scan_mode; // @[lib.scala 368:23] wire dma_buffer_c1cgc_io_l1clk; // @[dma_ctrl.scala 392:32] wire dma_buffer_c1cgc_io_clk; // @[dma_ctrl.scala 392:32] wire dma_buffer_c1cgc_io_en; // @[dma_ctrl.scala 392:32] @@ -78617,32 +78613,32 @@ module dma_ctrl( wire dma_bus_cgc_io_clk; // @[dma_ctrl.scala 404:27] wire dma_bus_cgc_io_en; // @[dma_ctrl.scala 404:27] wire dma_bus_cgc_io_scan_mode; // @[dma_ctrl.scala 404:27] - wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_10_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_10_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_11_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_11_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 508:23] - wire rvclkhdr_12_io_l1clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_12_io_clk; // @[el2_lib.scala 508:23] - wire rvclkhdr_12_io_en; // @[el2_lib.scala 508:23] - wire rvclkhdr_12_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_10_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_10_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_10_io_en; // @[lib.scala 368:23] + wire rvclkhdr_10_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_11_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_11_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_11_io_en; // @[lib.scala 368:23] + wire rvclkhdr_11_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_12_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_12_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_12_io_en; // @[lib.scala 368:23] + wire rvclkhdr_12_io_scan_mode; // @[lib.scala 368:23] wire dma_free_clk = dma_free_cgc_io_l1clk; // @[dma_ctrl.scala 175:26 dma_ctrl.scala 402:29] reg [2:0] RdPtr; // @[Reg.scala 27:20] - reg [31:0] fifo_addr_4; // @[el2_lib.scala 514:16] - reg [31:0] fifo_addr_3; // @[el2_lib.scala 514:16] - reg [31:0] fifo_addr_2; // @[el2_lib.scala 514:16] - reg [31:0] fifo_addr_1; // @[el2_lib.scala 514:16] - reg [31:0] fifo_addr_0; // @[el2_lib.scala 514:16] + reg [31:0] fifo_addr_4; // @[lib.scala 374:16] + reg [31:0] fifo_addr_3; // @[lib.scala 374:16] + reg [31:0] fifo_addr_2; // @[lib.scala 374:16] + reg [31:0] fifo_addr_1; // @[lib.scala 374:16] + reg [31:0] fifo_addr_0; // @[lib.scala 374:16] wire [31:0] _GEN_60 = 3'h1 == RdPtr ? fifo_addr_1 : fifo_addr_0; // @[dma_ctrl.scala 358:20] wire [31:0] _GEN_61 = 3'h2 == RdPtr ? fifo_addr_2 : _GEN_60; // @[dma_ctrl.scala 358:20] wire [31:0] _GEN_62 = 3'h3 == RdPtr ? fifo_addr_3 : _GEN_61; // @[dma_ctrl.scala 358:20] wire [31:0] dma_mem_addr_int = 3'h4 == RdPtr ? fifo_addr_4 : _GEN_62; // @[dma_ctrl.scala 358:20] - wire dma_mem_addr_in_dccm = dma_mem_addr_int[31:16] == 16'hf004; // @[el2_lib.scala 501:39] - wire dma_mem_addr_in_pic = dma_mem_addr_int[31:15] == 17'h1e018; // @[el2_lib.scala 501:39] - wire dma_mem_addr_in_iccm = dma_mem_addr_int[31:16] == 16'hee00; // @[el2_lib.scala 501:39] + wire dma_mem_addr_in_dccm = dma_mem_addr_int[31:16] == 16'hf004; // @[lib.scala 361:39] + wire dma_mem_addr_in_pic = dma_mem_addr_int[31:15] == 17'h1e018; // @[lib.scala 361:39] + wire dma_mem_addr_in_iccm = dma_mem_addr_int[31:16] == 16'hee00; // @[lib.scala 361:39] wire dma_bus_clk = dma_bus_cgc_io_l1clk; // @[dma_ctrl.scala 177:25 dma_ctrl.scala 408:28] reg wrbuf_vld; // @[dma_ctrl.scala 418:59] reg wrbuf_data_vld; // @[dma_ctrl.scala 420:59] @@ -78651,8 +78647,8 @@ module dma_ctrl( wire _T_1241 = _T_1240 & rdbuf_vld; // @[dma_ctrl.scala 476:60] reg axi_mstr_priority; // @[Reg.scala 27:20] wire axi_mstr_sel = _T_1241 ? axi_mstr_priority : _T_1240; // @[dma_ctrl.scala 476:31] - reg [31:0] wrbuf_addr; // @[el2_lib.scala 514:16] - reg [31:0] rdbuf_addr; // @[el2_lib.scala 514:16] + reg [31:0] wrbuf_addr; // @[lib.scala 374:16] + reg [31:0] rdbuf_addr; // @[lib.scala 374:16] wire [31:0] bus_cmd_addr = axi_mstr_sel ? wrbuf_addr : rdbuf_addr; // @[dma_ctrl.scala 466:43] wire [2:0] _GEN_90 = {{2'd0}, io_dbg_dma_dbg_ib_dbg_cmd_addr[2]}; // @[dma_ctrl.scala 202:91] wire [3:0] _T_17 = 3'h4 * _GEN_90; // @[dma_ctrl.scala 202:91] @@ -78965,7 +78961,7 @@ module dma_ctrl( wire _T_491 = fifo_error_en[0] & _T_269; // @[dma_ctrl.scala 231:77] wire [63:0] _T_493 = {32'h0,fifo_addr_0}; // @[Cat.scala 29:58] wire [3:0] _T_498 = {io_dbg_dma_dbg_dctl_dbg_cmd_wrdata,io_dbg_dma_dbg_dctl_dbg_cmd_wrdata}; // @[Cat.scala 29:58] - reg [63:0] wrbuf_data; // @[el2_lib.scala 514:16] + reg [63:0] wrbuf_data; // @[lib.scala 374:16] wire [63:0] _T_500 = io_dbg_dma_dbg_ib_dbg_cmd_valid ? {{60'd0}, _T_498} : wrbuf_data; // @[dma_ctrl.scala 231:347] wire _T_506 = fifo_error_en[1] & _T_276; // @[dma_ctrl.scala 231:77] wire [63:0] _T_508 = {32'h0,fifo_addr_1}; // @[Cat.scala 29:58] @@ -79024,11 +79020,11 @@ module dma_ctrl( reg _T_856; // @[Reg.scala 27:20] reg _T_858; // @[Reg.scala 27:20] wire [4:0] fifo_write = {_T_858,_T_856,_T_854,_T_852,_T_850}; // @[Cat.scala 29:58] - reg [63:0] fifo_data_0; // @[el2_lib.scala 514:16] - reg [63:0] fifo_data_1; // @[el2_lib.scala 514:16] - reg [63:0] fifo_data_2; // @[el2_lib.scala 514:16] - reg [63:0] fifo_data_3; // @[el2_lib.scala 514:16] - reg [63:0] fifo_data_4; // @[el2_lib.scala 514:16] + reg [63:0] fifo_data_0; // @[lib.scala 374:16] + reg [63:0] fifo_data_1; // @[lib.scala 374:16] + reg [63:0] fifo_data_2; // @[lib.scala 374:16] + reg [63:0] fifo_data_3; // @[lib.scala 374:16] + reg [63:0] fifo_data_4; // @[lib.scala 374:16] reg fifo_tag_0; // @[Reg.scala 27:20] reg wrbuf_tag; // @[Reg.scala 27:20] reg rdbuf_tag; // @[Reg.scala 27:20] @@ -79140,61 +79136,61 @@ module dma_ctrl( wire _GEN_87 = 3'h2 == RspPtr ? fifo_tag_2 : _GEN_86; // @[dma_ctrl.scala 495:33] wire _GEN_88 = 3'h3 == RspPtr ? fifo_tag_3 : _GEN_87; // @[dma_ctrl.scala 495:33] wire _T_1261 = ~axi_rsp_write; // @[dma_ctrl.scala 497:46] - rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en), .io_scan_mode(rvclkhdr_io_scan_mode) ); - rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_1 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_1_io_l1clk), .io_clk(rvclkhdr_1_io_clk), .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_2_io_l1clk), .io_clk(rvclkhdr_2_io_clk), .io_en(rvclkhdr_2_io_en), .io_scan_mode(rvclkhdr_2_io_scan_mode) ); - rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_3_io_l1clk), .io_clk(rvclkhdr_3_io_clk), .io_en(rvclkhdr_3_io_en), .io_scan_mode(rvclkhdr_3_io_scan_mode) ); - rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_4_io_l1clk), .io_clk(rvclkhdr_4_io_clk), .io_en(rvclkhdr_4_io_en), .io_scan_mode(rvclkhdr_4_io_scan_mode) ); - rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_5 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_5_io_l1clk), .io_clk(rvclkhdr_5_io_clk), .io_en(rvclkhdr_5_io_en), .io_scan_mode(rvclkhdr_5_io_scan_mode) ); - rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_6 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_6_io_l1clk), .io_clk(rvclkhdr_6_io_clk), .io_en(rvclkhdr_6_io_en), .io_scan_mode(rvclkhdr_6_io_scan_mode) ); - rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_7 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_7_io_l1clk), .io_clk(rvclkhdr_7_io_clk), .io_en(rvclkhdr_7_io_en), .io_scan_mode(rvclkhdr_7_io_scan_mode) ); - rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_8 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_8_io_l1clk), .io_clk(rvclkhdr_8_io_clk), .io_en(rvclkhdr_8_io_en), .io_scan_mode(rvclkhdr_8_io_scan_mode) ); - rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_9 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_9_io_l1clk), .io_clk(rvclkhdr_9_io_clk), .io_en(rvclkhdr_9_io_en), @@ -79218,19 +79214,19 @@ module dma_ctrl( .io_en(dma_bus_cgc_io_en), .io_scan_mode(dma_bus_cgc_io_scan_mode) ); - rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_10 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_10_io_l1clk), .io_clk(rvclkhdr_10_io_clk), .io_en(rvclkhdr_10_io_en), .io_scan_mode(rvclkhdr_10_io_scan_mode) ); - rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_11 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_11_io_l1clk), .io_clk(rvclkhdr_11_io_clk), .io_en(rvclkhdr_11_io_en), .io_scan_mode(rvclkhdr_11_io_scan_mode) ); - rvclkhdr rvclkhdr_12 ( // @[el2_lib.scala 508:23] + rvclkhdr rvclkhdr_12 ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_12_io_l1clk), .io_clk(rvclkhdr_12_io_clk), .io_en(rvclkhdr_12_io_en), @@ -79272,36 +79268,36 @@ module dma_ctrl( assign io_ifu_dma_dma_mem_ctl_dma_mem_write = io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 511:40] assign io_ifu_dma_dma_mem_ctl_dma_mem_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[dma_ctrl.scala 510:40] assign io_ifu_dma_dma_mem_ctl_dma_mem_tag = io_lsu_dma_dma_mem_tag; // @[dma_ctrl.scala 512:38] - assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_io_en = fifo_cmd_en[0]; // @[el2_lib.scala 511:17] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_1_io_en = fifo_cmd_en[1]; // @[el2_lib.scala 511:17] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_2_io_en = fifo_cmd_en[2]; // @[el2_lib.scala 511:17] - assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_3_io_en = fifo_cmd_en[3]; // @[el2_lib.scala 511:17] - assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_4_io_en = fifo_cmd_en[4]; // @[el2_lib.scala 511:17] - assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_5_io_en = fifo_data_en[0]; // @[el2_lib.scala 511:17] - assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_6_io_en = fifo_data_en[1]; // @[el2_lib.scala 511:17] - assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_7_io_en = fifo_data_en[2]; // @[el2_lib.scala 511:17] - assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_8_io_en = fifo_data_en[3]; // @[el2_lib.scala 511:17] - assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_9_io_en = fifo_data_en[4]; // @[el2_lib.scala 511:17] - assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_io_en = fifo_cmd_en[0]; // @[lib.scala 371:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_1_io_en = fifo_cmd_en[1]; // @[lib.scala 371:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_2_io_en = fifo_cmd_en[2]; // @[lib.scala 371:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_3_io_en = fifo_cmd_en[3]; // @[lib.scala 371:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_4_io_en = fifo_cmd_en[4]; // @[lib.scala 371:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_5_io_en = fifo_data_en[0]; // @[lib.scala 371:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_6_io_en = fifo_data_en[1]; // @[lib.scala 371:17] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_7_io_en = fifo_data_en[2]; // @[lib.scala 371:17] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_8_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_8_io_en = fifo_data_en[3]; // @[lib.scala 371:17] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_9_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_9_io_en = fifo_data_en[4]; // @[lib.scala 371:17] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign dma_buffer_c1cgc_io_clk = clock; // @[dma_ctrl.scala 395:33] assign dma_buffer_c1cgc_io_en = _T_1193 | io_clk_override; // @[dma_ctrl.scala 393:33] assign dma_buffer_c1cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 394:33] @@ -79311,15 +79307,15 @@ module dma_ctrl( assign dma_bus_cgc_io_clk = clock; // @[dma_ctrl.scala 407:28] assign dma_bus_cgc_io_en = io_dma_bus_clk_en; // @[dma_ctrl.scala 405:28] assign dma_bus_cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 406:28] - assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_10_io_en = wrbuf_en & io_dma_bus_clk_en; // @[el2_lib.scala 511:17] - assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_11_io_en = wrbuf_data_en & io_dma_bus_clk_en; // @[el2_lib.scala 511:17] - assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] - assign rvclkhdr_12_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_12_io_en = rdbuf_en & io_dma_bus_clk_en; // @[el2_lib.scala 511:17] - assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_10_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_10_io_en = wrbuf_en & io_dma_bus_clk_en; // @[lib.scala 371:17] + assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_11_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_11_io_en = wrbuf_data_en & io_dma_bus_clk_en; // @[lib.scala 371:17] + assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_12_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_12_io_en = rdbuf_en & io_dma_bus_clk_en; // @[lib.scala 371:17] + assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -81398,14 +81394,14 @@ module quasar( wire dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 164:24] wire [63:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 164:24] wire [2:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 164:24] - wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22] - wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_1_io_clk; // @[el2_lib.scala 483:22] - wire rvclkhdr_1_io_en; // @[el2_lib.scala 483:22] - wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_io_en; // @[lib.scala 343:22] + wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_en; // @[lib.scala 343:22] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] wire _T_1 = dbg_io_dbg_core_rst_l; // @[quasar.scala 166:67] wire _T_2 = _T_1 | io_scan_mode; // @[quasar.scala 166:70] wire _T_5 = ~dec_io_dec_pause_state_cg; // @[quasar.scala 167:23] @@ -82210,13 +82206,13 @@ module quasar( .io_ifu_dma_dma_mem_ctl_dma_mem_wdata(dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_wdata), .io_ifu_dma_dma_mem_ctl_dma_mem_tag(dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_tag) ); - rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en), .io_scan_mode(rvclkhdr_io_scan_mode) ); - rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 483:22] + rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_1_io_l1clk), .io_clk(rvclkhdr_1_io_clk), .io_en(rvclkhdr_1_io_en), @@ -82710,12 +82706,12 @@ module quasar( assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 284:18] assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 284:18] assign dma_ctrl_io_lsu_dma_dccm_ready = lsu_io_lsu_dma_dccm_ready; // @[quasar.scala 284:18] - assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_io_en = 1'h1; // @[el2_lib.scala 485:16] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] - assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_1_io_en = _T_6 | dec_io_dec_tlu_misc_clk_override; // @[el2_lib.scala 485:16] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_io_en = 1'h1; // @[lib.scala 345:16] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_1_io_en = _T_6 | dec_io_dec_tlu_misc_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] endmodule module quasar_wrapper( input clock, diff --git a/src/main/scala/dbg/dbg.scala b/src/main/scala/dbg/dbg.scala index f57c8aff..174f4a84 100644 --- a/src/main/scala/dbg/dbg.scala +++ b/src/main/scala/dbg/dbg.scala @@ -456,6 +456,6 @@ class dbg extends Module with lib with RequireAsyncReset { io.dbg_dma.dbg_ib.dbg_cmd_type := io.dbg_dec.dbg_ib.dbg_cmd_type } -object dbg_main extends App { - println((new chisel3.stage.ChiselStage).emitVerilog(new dbg())) -} +//object dbg_main extends App { +// println((new chisel3.stage.ChiselStage).emitVerilog(new dbg())) +//} diff --git a/src/main/scala/exu/exu.scala b/src/main/scala/exu/exu.scala index 73a47350..6be097e2 100644 --- a/src/main/scala/exu/exu.scala +++ b/src/main/scala/exu/exu.scala @@ -233,6 +233,6 @@ class exu extends Module with lib with RequireAsyncReset{ io.dec_exu.tlu_exu.exu_npc_r := Mux(i0_pred_correct_upper_r===1.U, pred_correct_npc_r, i0_flush_path_upper_r) } -object exu_main extends App { - println((new chisel3.stage.ChiselStage).emitVerilog(new exu())) -} +//object exu_main extends App { +// println((new chisel3.stage.ChiselStage).emitVerilog(new exu())) +//} diff --git a/src/main/scala/ifu/ifu.scala b/src/main/scala/ifu/ifu.scala index 230a8d2b..716c4469 100644 --- a/src/main/scala/ifu/ifu.scala +++ b/src/main/scala/ifu/ifu.scala @@ -118,6 +118,6 @@ class ifu extends Module with lib with RequireAsyncReset { io.iccm_dma_sb_error := mem_ctl.io.iccm_dma_sb_error } -object ifu_main extends App { - println((new chisel3.stage.ChiselStage).emitVerilog(new ifu())) -} +//object ifu_main extends App { +// println((new chisel3.stage.ChiselStage).emitVerilog(new ifu())) +//} diff --git a/src/main/scala/lib/ahb_to_axi4.scala b/src/main/scala/lib/ahb_to_axi4.scala index ebb66118..87be1234 100644 --- a/src/main/scala/lib/ahb_to_axi4.scala +++ b/src/main/scala/lib/ahb_to_axi4.scala @@ -79,7 +79,7 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset { io.ahb_hreadyout := 0.U io.ahb_hresp := 0.U } -object AHB_main extends App { - println("Generate Verilog") - println((new chisel3.stage.ChiselStage).emitVerilog(new ahb_to_axi4())) -} \ No newline at end of file +//object AHB_main extends App { +// println("Generate Verilog") + // println((new chisel3.stage.ChiselStage).emitVerilog(new ahb_to_axi4())) +//} \ No newline at end of file diff --git a/src/main/scala/lib/axi4_to_ahb.scala b/src/main/scala/lib/axi4_to_ahb.scala index 25bd76ff..642ce81a 100644 --- a/src/main/scala/lib/axi4_to_ahb.scala +++ b/src/main/scala/lib/axi4_to_ahb.scala @@ -437,7 +437,7 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { ahbm_data_clk := rvclkhdr(clock, ahbm_data_clken, io.scan_mode) } -object AXImain extends App { - println("Generate Verilog") - println((new chisel3.stage.ChiselStage).emitVerilog(new axi4_to_ahb())) -} \ No newline at end of file +//object AXImain extends App { + // println("Generate Verilog") +// println((new chisel3.stage.ChiselStage).emitVerilog(new axi4_to_ahb())) +//} \ No newline at end of file diff --git a/src/main/scala/lib/beh_lib.scala b/src/main/scala/lib/beh_lib.scala deleted file mode 100644 index 3e0c52a4..00000000 --- a/src/main/scala/lib/beh_lib.scala +++ /dev/null @@ -1,361 +0,0 @@ -package lib -import chisel3._ -import chisel3.util._ - - - -class rvdff(WIDTH:Int=1,SHORT:Int=0) extends Module{ - val io = IO(new Bundle{ -val din = Input(UInt(WIDTH.W)) -val dout = Output(UInt(WIDTH.W)) -}) - -val flop = RegNext(io.din,0.U) - -if(SHORT == 1) -{io.dout := io.din} -else -{io.dout := flop} -} - -class rvdffsc extends Module with lib { - val io = IO(new Bundle{ - val din = Input(UInt(32.W)) - val en = Input(Bool()) - val clear = Input(Bool()) - val out = Output(UInt()) - }) - io.out := RegEnable(io.din & Fill(io.din.getWidth, ~io.clear), 0.U, io.en) -} - -class rvdffs extends Module with lib { - val io = IO(new Bundle{ - val din = Input(UInt(32.W)) - val en = Input(Bool()) - val clear = Input(Bool()) - val out = Output(UInt()) - }) - io.out := RegEnable(io.din, 0.U, io.en) -} - -class rvsyncss(WIDTH:Int = 251,SHORT:Int = 0) extends Module with RequireAsyncReset{ //Done for verification and testing - val io = IO(new Bundle{ - val din = Input(UInt(WIDTH.W)) - val dout = Output(UInt(WIDTH.W)) - }) - val sync_ff1 = RegNext(io.din,0.U) //RegNext(io.in,init) - val sync_ff2 = RegNext(sync_ff1,0.U) - if(SHORT == 1) - { io.dout := io.din } - else - { io.dout := sync_ff2 } -} - - - -class rvlsadder extends Module{ //Done for verification and testing - val io = IO(new Bundle{ - val rs1 = Input(UInt(32.W)) - val offset = Input(UInt(12.W)) - val dout = Output(UInt(32.W)) - }) - val w1 = Cat("b0".U,io.rs1(11,0)) + Cat("b0".U,io.offset(11,0)) //w1[12] =cout offset[11]=sign - - val dout_upper = ((Fill(20, ~(io.offset(11) ^ w1(12)))) & io.rs1(31,12)) | - ((Fill(20, ~io.offset(11) ^ w1(12))) & (io.rs1(31,12)+1.U)) | - ((Fill(20, io.offset(11) ^ ~w1(12))) & (io.rs1(31,12)-1.U)) - - io.dout := Cat(dout_upper,w1(11,0)) -} - - - - -class rvbsadder extends Module{ //Done for verification and testing - val io = IO(new Bundle{ - val pc = Input(UInt(32.W)) // lsb is not using in code - val offset = Input(UInt(13.W)) // lsb is not using in code - val dout = Output(UInt(31.W)) - }) - val w1 = Cat("b0".U,io.pc(12,1)) + Cat("b0".U,io.offset(12,1)) //w1[12] =cout offset[12]=sign - - val dout_upper = ((Fill(19, ~(io.offset(12) ^ w1(12))))& io.pc(31,13)) | - ((Fill(19, ~io.offset(12) ^ w1(12))) & (io.pc(31,13)+1.U)) | - ((Fill(19, io.offset(12) ^ ~w1(12))) & (io.pc(31,13)-1.U)) - io.dout := Cat(dout_upper,w1(11,0)) -} - - - - -class rvtwoscomp(WIDTH:Int=32) extends Module{ //Done for verification and testing - val io = IO(new Bundle{ - val din = Input(UInt(WIDTH.W)) - val dout = Output(UInt(WIDTH.W)) - }) - - - val temp = Wire(Vec(WIDTH-1,UInt(1.W))) - val i:Int = 1 - - for(i <- 1 to WIDTH-1){ - val done = io.din(i-1,0).orR - temp(i-1) := Mux(done ,~io.din(i),io.din(i)) - } - io.dout := Cat(temp.asUInt,io.din(0)) -} - - -class rvmaskandmatch(WIDTH:Int=32) extends Module{ //Done for verification and testing - val io = IO(new Bundle{ - val mask = Input(UInt(WIDTH.W)) - val data = Input(UInt(WIDTH.W)) - val masken = Input(UInt(1.W)) - val match_out = Output(UInt(1.W)) - }) - - val matchvec = Wire(Vec(WIDTH,UInt(1.W))) - val masken_or_fullmask = io.masken.asBool & ~io.mask(WIDTH-1,0).andR - - matchvec(0) := masken_or_fullmask | (io.mask(0) === io.data(0)).asUInt - - for(i <- 1 to WIDTH-1) - {matchvec(i) := Mux(io.mask(i-1,0).andR & masken_or_fullmask,"b1".U,(io.mask(i) === io.data(i)).asUInt)} - io.match_out := matchvec.asUInt -} - - - - -class rvrangecheck(CCM_SADR:Int=0, CCM_SIZE:Int=128) extends Module{ - val io = IO(new Bundle{ - val addr = Input(UInt(32.W)) - val in_range = Output(UInt(1.W)) - val in_region = Output(UInt(1.W)) - }) - val REGION_BITS = 4 - val MASK_BITS = 10 + log2Ceil(CCM_SIZE) - - val start_addr = Wire(UInt(32.W)) - start_addr := CCM_SIZE.U - val region = start_addr(31,(32-REGION_BITS)) - - io.in_region := (io.addr(31,(32-REGION_BITS)) === region(REGION_BITS-1,0)).asUInt - if(CCM_SIZE == 48) - io.in_range := (io.addr(31,MASK_BITS) === start_addr(31,MASK_BITS)).asUInt & ~(io.addr(MASK_BITS-1,MASK_BITS-2).andR.asUInt) - else - io.in_range := (io.addr(31,MASK_BITS) === start_addr(31,MASK_BITS)).asUInt -} - - - -// DONE -class rveven_paritygen(WIDTH:Int= 16) extends Module{ //Done for verification and testing - val io = IO(new Bundle{ - val data_in = Input (UInt(WIDTH.W)) - val parity_out = Output(UInt(1.W)) - }) - io.parity_out := io.data_in.xorR.asUInt -} // DONE - - -// DONE -class rveven_paritycheck(WIDTH:Int= 16) extends Module{ //Done for verification and testing - val io = IO(new Bundle{ - val data_in = Input (UInt(WIDTH.W)) - val parity_in = Input (UInt(1.W)) - val parity_err = Output(UInt(1.W)) - }) - io.parity_err := (io.data_in.xorR.asUInt) ^ io.parity_in -} // DONE - - - -class rvecc_encode extends Module{ //Done for verification and testing - val io = IO(new Bundle{ - val din = Input(UInt(32.W)) - val ecc_out = Output(UInt(7.W)) - }) - val mask0 = Array(0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,1,0,1,1) - val mask1 = Array(1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,1,1,0,1) - val mask2 = Array(1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,0) - val mask3 = Array(0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,0,0,0,0) - val mask4 = Array(0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0) - val mask5 = Array(1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) - val w0 = Wire(Vec(18,UInt(1.W))) - val w1 = Wire(Vec(18,UInt(1.W))) - val w2 = Wire(Vec(18,UInt(1.W))) - val w3 = Wire(Vec(15,UInt(1.W))) - val w4 = Wire(Vec(15,UInt(1.W))) - val w5 = Wire(Vec(6, UInt(1.W))) - var j = 0;var k = 0;var m = 0; - var x = 0;var y = 0;var z = 0 - - for(i <- 0 to 31) - { - if(mask0(i)==1) {w0(j) := io.din(i); j = j +1 } - if(mask1(i)==1) {w1(k) := io.din(i); k = k +1 } - if(mask2(i)==1) {w2(m) := io.din(i); m = m +1 } - if(mask3(i)==1) {w3(x) := io.din(i); x = x +1 } - if(mask4(i)==1) {w4(y) := io.din(i); y = y +1 } - if(mask5(i)==1) {w5(z) := io.din(i); z = z +1 } - } - val w6 = Cat((w0.asUInt.xorR),(w1.asUInt.xorR),(w2.asUInt.xorR),(w3.asUInt.xorR),(w4.asUInt.xorR),(w5.asUInt.xorR)) - io.ecc_out := Cat(io.din.xorR ^ w6.xorR, w6) -} - - -// Make generator and then make it a method -class rvecc_decode extends Module{ //Done for verification and testing - val io = IO(new Bundle{ - val en = Input(UInt(1.W)) - val din = Input(UInt(32.W)) - val ecc_in = Input(UInt(7.W)) - val sed_ded = Input(UInt(1.W)) - val ecc_out = Output(UInt(7.W)) - val dout = Output(UInt(32.W)) - val single_ecc_error = Output(UInt(1.W)) - val double_ecc_error = Output(UInt(1.W)) - }) - val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0) - val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1) - val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1) - val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0) - val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0) - val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1) - - val w0 = Wire(Vec(18,UInt(1.W))) - val w1 = Wire(Vec(18,UInt(1.W))) - val w2 = Wire(Vec(18,UInt(1.W))) - val w3 = Wire(Vec(15,UInt(1.W))) - val w4 = Wire(Vec(15,UInt(1.W))) - val w5 = Wire(Vec(6,UInt(1.W))) - - var j = 0;var k = 0;var m = 0; var n =0; - var x = 0;var y = 0; - - for(i <- 0 to 31) - { - if(mask0(i)==1) {w0(j) := io.din(i); j = j +1 } - if(mask1(i)==1) {w1(k) := io.din(i); k = k +1 } - if(mask2(i)==1) {w2(m) := io.din(i); m = m +1 } - if(mask3(i)==1) {w3(n) := io.din(i); n = n +1 } - if(mask4(i)==1) {w4(x) := io.din(i); x = x +1 } - if(mask5(i)==1) {w5(y) := io.din(i); y = y +1 } - } - - val ecc_check = Cat((io.din.xorR ^ io.ecc_in.xorR) & ~io.sed_ded ,io.ecc_in(5)^(w5.asUInt.xorR),io.ecc_in(4)^(w4.asUInt.xorR),io.ecc_in(3)^(w3.asUInt.xorR),io.ecc_in(2)^(w2.asUInt.xorR),io.ecc_in(1)^(w1.asUInt.xorR),io.ecc_in(0)^(w0.asUInt.xorR)) - io.ecc_out := ecc_check - - io.single_ecc_error := io.en & (ecc_check!= 0.U) & ((io.din.xorR ^ io.ecc_in.xorR) & ~io.sed_ded) - io.double_ecc_error := io.en & (ecc_check!= 0.U) & ((io.din.xorR ^ io.ecc_in.xorR) & ~io.sed_ded) - val error_mask = Wire(Vec(39,UInt(1.W))) - - for(i <- 1 until 40){ - error_mask(i-1) := ecc_check(5,0) === i.asUInt - } - val din_plus_parity = Cat(io.ecc_in(6), io.din(31,26), io.ecc_in(5), io.din(25,11), io.ecc_in(4), io.din(10,4), io.ecc_in(3), io.din(3,1), io.ecc_in(2), io.din(0), io.ecc_in(1,0)) - val dout_plus_parity = Mux(io.single_ecc_error.asBool, (error_mask.asUInt ^ din_plus_parity), din_plus_parity) - - io.dout := Cat(dout_plus_parity(37,32),dout_plus_parity(30,16), dout_plus_parity(14,8), dout_plus_parity(6,4), dout_plus_parity(2)) - io.ecc_out := Cat(dout_plus_parity(38) ^ (ecc_check(6,0) === "b1000000".U), dout_plus_parity(31), dout_plus_parity(15), dout_plus_parity(7), dout_plus_parity(3), dout_plus_parity(1,0)) -} - - - - - - -class rvecc_encode_64 extends Module{ //Done for verification and testing - val io = IO(new Bundle{ - val din = Input(UInt(64.W)) - val ecc_out = Output(UInt(7.W)) - }) - val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1) - val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1) - val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1) - val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0) - val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0) - val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0) - val mask6 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1) - - val w0 = Wire(Vec(35,UInt(1.W))) - val w1 = Wire(Vec(35,UInt(1.W))) - val w2 = Wire(Vec(35,UInt(1.W))) - val w3 = Wire(Vec(31,UInt(1.W))) - val w4 = Wire(Vec(31,UInt(1.W))) - val w5 = Wire(Vec(31,UInt(1.W))) - val w6 = Wire(Vec(7, UInt(1.W))) - - var j = 0;var k = 0;var m = 0; var n =0; - var x = 0;var y = 0;var z = 0 - - for(i <- 0 to 63) - { - if(mask0(i)==1) {w0(j) := io.din(i); j = j +1 } - if(mask1(i)==1) {w1(k) := io.din(i); k = k +1 } - if(mask2(i)==1) {w2(m) := io.din(i); m = m +1 } - if(mask3(i)==1) {w3(n) := io.din(i); n = n +1 } - if(mask4(i)==1) {w4(x) := io.din(i); x = x +1 } - if(mask5(i)==1) {w5(y) := io.din(i); y = y +1 } - if(mask6(i)==1) {w6(z) := io.din(i); z = z +1 } - } - io.ecc_out := Cat((w0.asUInt.xorR),(w1.asUInt.xorR),(w2.asUInt.xorR),(w3.asUInt.xorR),(w4.asUInt.xorR),(w5.asUInt.xorR),(w6.asUInt.xorR)) -} - - - - - -class rvecc_decode_64 extends Module{ //Done for verification and testing - val io = IO(new Bundle{ - val en = Input(UInt(1.W)) - val din = Input(UInt(64.W)) - val ecc_in = Input(UInt(7.W)) - val ecc_error = Output(UInt(1.W)) - }) - val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1) - val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1) - val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1) - val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0) - val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0) - val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0) - val mask6 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1) - - val w0 = Wire(Vec(35,UInt(1.W))) - val w1 = Wire(Vec(35,UInt(1.W))) - val w2 = Wire(Vec(35,UInt(1.W))) - val w3 = Wire(Vec(31,UInt(1.W))) - val w4 = Wire(Vec(31,UInt(1.W))) - val w5 = Wire(Vec(31,UInt(1.W))) - val w6 = Wire(Vec(7, UInt(1.W))) - - var j = 0;var k = 0;var m = 0; var n =0; - var x = 0;var y = 0;var z = 0 - - for(i <- 0 to 63) - { - if(mask0(i)==1) {w0(j) := io.din(i); j = j +1 } - if(mask1(i)==1) {w1(k) := io.din(i); k = k +1 } - if(mask2(i)==1) {w2(m) := io.din(i); m = m +1 } - if(mask3(i)==1) {w3(n) := io.din(i); n = n +1 } - if(mask4(i)==1) {w4(x) := io.din(i); x = x +1 } - if(mask5(i)==1) {w5(y) := io.din(i); y = y +1 } - if(mask6(i)==1) {w6(z) := io.din(i); z = z +1 } - } - - val ecc_check = Cat((io.ecc_in(6) ^ w5.asUInt.xorR) ,io.ecc_in(5)^(w5.asUInt.xorR),io.ecc_in(4)^(w4.asUInt.xorR),io.ecc_in(3)^(w3.asUInt.xorR),io.ecc_in(2)^(w2.asUInt.xorR),io.ecc_in(1)^(w1.asUInt.xorR),io.ecc_in(0)^(w0.asUInt.xorR)) - io.ecc_error := io.en & (ecc_check(6,0) != 0.U) - - - object rvsyncss { - def apply(din:UInt,clk:Clock) =withClock(clk){RegNext(withClock(clk){RegNext(din,0.U)},0.U)} - } -} - - - - - - - diff --git a/src/main/scala/lib/el2_lib.scala b/src/main/scala/lib/lib.scala similarity index 72% rename from src/main/scala/lib/el2_lib.scala rename to src/main/scala/lib/lib.scala index 5b8bf45e..cc4f7ca1 100644 --- a/src/main/scala/lib/el2_lib.scala +++ b/src/main/scala/lib/lib.scala @@ -1,178 +1,38 @@ package lib import chisel3._ import chisel3.util._ -import mem.quasar.{DCCM_ENABLE, ICACHE_ECC, ICACHE_WAYPACK, ICCM_ENABLE, bool2int} -trait param { - val BHT_ADDR_HI = 9 - val BHT_ADDR_LO = 2 - val BHT_ARRAY_DEPTH = 256 - val BHT_GHR_HASH_1 = false - val BHT_GHR_SIZE = 8 - val BHT_SIZE = 512 - val BTB_ADDR_HI = 9 - val BTB_ADDR_LO = 2 - val BTB_ARRAY_DEPTH = 256 - val BTB_BTAG_FOLD = false - val BTB_BTAG_SIZE = 5 - val BTB_FOLD2_INDEX_HASH = false - val BTB_INDEX1_HI = 9 - val BTB_INDEX1_LO = 2 - val BTB_INDEX2_HI = 17 - val BTB_INDEX2_LO = 10 - val BTB_INDEX3_HI = 25 - val BTB_INDEX3_LO = 18 - val BTB_SIZE = 512 - val BUILD_AHB_LITE = false - val BUILD_AXI4 = true - val BUILD_AXI_NATIVE = true - val BUS_PRTY_DEFAULT = 3 - val DATA_ACCESS_ADDR0 = 0x00000000 //.U(32.W) - val DATA_ACCESS_ADDR1 = 0xC0000000 //.U(32.W) - val DATA_ACCESS_ADDR2 = 0xA0000000 //.U(32.W) - val DATA_ACCESS_ADDR3 = 0x80000000 //.U(32.W) - val DATA_ACCESS_ADDR4 = 0x00000000 //.U(32.W) - val DATA_ACCESS_ADDR5 = 0x00000000 //.U(32.W) - val DATA_ACCESS_ADDR6 = 0x00000000 //.U(32.W) - val DATA_ACCESS_ADDR7 = 0x00000000 //.U(32.W) - val DATA_ACCESS_ENABLE0 = true //.U(1.W) - val DATA_ACCESS_ENABLE1 = true //.U(1.W) - val DATA_ACCESS_ENABLE2 = true //.U(1.W) - val DATA_ACCESS_ENABLE3 = true //.U(1.W) - val DATA_ACCESS_ENABLE4 = false //.U(1.W) - val DATA_ACCESS_ENABLE5 = false //.U(1.W) - val DATA_ACCESS_ENABLE6 = false //.U(1.W) - val DATA_ACCESS_ENABLE7 = false //.U(1.W) - val DATA_ACCESS_MASK0 = 0x7FFFFFFF //.U(32.W) - val DATA_ACCESS_MASK1 = 0x3FFFFFFF //.U(32.W) - val DATA_ACCESS_MASK2 = 0x1FFFFFFF //.U(32.W) - val DATA_ACCESS_MASK3 = 0x0FFFFFFF //.U(32.W) - val DATA_ACCESS_MASK4 = 0xFFFFFFFF //.U(32.W) - val DATA_ACCESS_MASK5 = 0xFFFFFFFF //.U(32.W) - val DATA_ACCESS_MASK6 = 0xFFFFFFFF //.U(32.W) - val DATA_ACCESS_MASK7 = 0xFFFFFFFF //.U(32.W) - val DCCM_BANK_BITS = 2 //.U(3.W) - val DCCM_BITS = 16 //.U(5.W) - val DCCM_BYTE_WIDTH = 4 //.U(3.W) - val DCCM_DATA_WIDTH = 32 //.U(6.W) - val DCCM_ECC_WIDTH = 7 //.U(3.W) - val DCCM_ENABLE = true //.U(1.W) - val DCCM_FDATA_WIDTH = 0x27 //.U(6.W) - val DCCM_INDEX_BITS = 0xC //.U(4.W) - val DCCM_NUM_BANKS = 0x04 //.U(5.W) - val DCCM_REGION = 15 //.U(4.W) - val DCCM_SADR = 0xF0040000 - val DCCM_SIZE = 0x040 - val DCCM_WIDTH_BITS = 2 //.U(2.W) - val DMA_BUF_DEPTH = 5 //.U(3.W) - val DMA_BUS_ID = true //.U(1.W) - val DMA_BUS_PRTY = 0x2 //.U(2.W) - val DMA_BUS_TAG = 0x1 //.U(4.W) - val FAST_INTERRUPT_REDIRECT= 0x1 //.U(1.W) - val ICACHE_2BANKS = 1 - val ICACHE_BANK_BITS = 1 - val ICACHE_BANK_HI = 3 - val ICACHE_BANK_LO = 3 - val ICACHE_BANK_WIDTH = 8 - val ICACHE_BANKS_WAY = 2 - val ICACHE_BEAT_ADDR_HI = 5 - val ICACHE_BEAT_BITS = 3 - val ICACHE_DATA_DEPTH = 512 - val ICACHE_DATA_INDEX_LO = 4 - val ICACHE_DATA_WIDTH = 64 - val ICACHE_ECC = true - val ICACHE_ENABLE = true - val ICACHE_FDATA_WIDTH = 71 - val ICACHE_INDEX_HI = 12 - val ICACHE_LN_SZ = 64 - val ICACHE_NUM_BEATS = 8 - val ICACHE_NUM_WAYS = 2 - val ICACHE_ONLY = false - val ICACHE_SCND_LAST = 6 - val ICACHE_SIZE = 16 - val ICACHE_STATUS_BITS = 1 - val ICACHE_TAG_DEPTH = 128 - val ICACHE_TAG_INDEX_LO = 6 - val ICACHE_TAG_LO = 13 - val ICACHE_WAYPACK = false - val ICCM_BANK_BITS = 2 - val ICCM_BANK_HI = 3 //.U(5.W) - val ICCM_BANK_INDEX_LO = 4 //.U(5.W) - val ICCM_BITS = 16 //.U(5.W) - val ICCM_ENABLE = true //.U(1.W) - val ICCM_ICACHE = true //.U(1.W) - val ICCM_INDEX_BITS = 0xC //.U(4.W) - val ICCM_NUM_BANKS = 0x04 //.U(5.W) - val ICCM_ONLY = false //.U(1.W) - val ICCM_REGION = 0xE //.U(4.W) - val ICCM_SADR = 0xEE000000 //.U(32.W) - val ICCM_SIZE = 0x040 //.U(10.W) - val IFU_BUS_ID = 0x1 //.U(1.W) - val IFU_BUS_PRTY = 0x2 //.U(2.W) - val IFU_BUS_TAG = 0x3 //.U(4.W) - val INST_ACCESS_ADDR0 = 0x00000000 //.U(32.W) - val INST_ACCESS_ADDR1 = 0xC0000000 //.U(32.W) - val INST_ACCESS_ADDR2 = 0xA0000000 //.U(32.W) - val INST_ACCESS_ADDR3 = 0x80000000 //.U(32.W) - val INST_ACCESS_ADDR4 = 0x00000000 //.U(32.W) - val INST_ACCESS_ADDR5 = 0x00000000 //.U(32.W) - val INST_ACCESS_ADDR6 = 0x00000000 //.U(32.W) - val INST_ACCESS_ADDR7 = 0x00000000 //.U(32.W) - val INST_ACCESS_ENABLE0 = 0x1 //.U(1.W) - val INST_ACCESS_ENABLE1 = 0x1 //.U(1.W) - val INST_ACCESS_ENABLE2 = 0x1 //.U(1.W) - val INST_ACCESS_ENABLE3 = 0x1 //.U(1.W) - val INST_ACCESS_ENABLE4 = 0x0 //.U(1.W) - val INST_ACCESS_ENABLE5 = 0x0 //.U(1.W) - val INST_ACCESS_ENABLE6 = 0x0 //.U(1.W) - val INST_ACCESS_ENABLE7 = 0x0 //.U(1.W) - val INST_ACCESS_MASK0 = 0x7FFFFFFF //.U(32.W) - val INST_ACCESS_MASK1 = 0x3FFFFFFF //.U(32.W) - val INST_ACCESS_MASK2 = 0x1FFFFFFF //.U(32.W) - val INST_ACCESS_MASK3 = 0x0FFFFFFF //.U(32.W) - val INST_ACCESS_MASK4 = 0xFFFFFFFF //.U(32.W) - val INST_ACCESS_MASK5 = 0xFFFFFFFF //.U(32.W) - val INST_ACCESS_MASK6 = 0xFFFFFFFF //.U(32.W) - val INST_ACCESS_MASK7 = 0xFFFFFFFF //.U(32.W) - val LOAD_TO_USE_PLUS1 = 0x0 //.U(1.W) - val LSU2DMA = 0x0 //.U(1.W) - val LSU_BUS_ID = 0x1 //.U(1.W) - val LSU_BUS_PRTY = 0x2 //.U(2.W) - val LSU_BUS_TAG = 0x3 //.U(4.W) - val LSU_NUM_NBLOAD = 0x04 //.U(5.W) - val LSU_NUM_NBLOAD_WIDTH = 0x2 //.U(3.W) - val LSU_SB_BITS = 0x10 //.U(5.W) - val LSU_STBUF_DEPTH = 0x4 //.U(4.W) - val NO_ICCM_NO_ICACHE = false //.U(1.W) - val PIC_2CYCLE = 0x0 //.U(1.W) - val PIC_BASE_ADDR = 0xF00C0000 //.U(32.W) - val PIC_BITS = 0x0F //.U(5.W) - val PIC_INT_WORDS = 0x1 //.U(4.W) - val PIC_REGION = 0xF //.U(4.W) - val PIC_SIZE = 0x020 //.U(9.W) - val PIC_TOTAL_INT = 0x1F //.U(8.W) - val PIC_TOTAL_INT_PLUS1 = 0x020 //.U(9.W) - val RET_STACK_SIZE = 0x8 //.U(4.W) - val SB_BUS_ID = 0x1 //.U(1.W) - val SB_BUS_PRTY = 0x2 //.U(2.W) - val SB_BUS_TAG = 0x1 //.U(4.W) - val TIMER_LEGAL_EN = 0x1 //.U(1.W) -} - +import include._ trait lib extends param{ + implicit def int2boolean(b:Int) = if (b==1) true else false + + implicit def uint2bool(b:UInt) = b.asBool() + + implicit def aslong(b:Int) = 0xFFFFFFFFL & b + def repl(b:Int, a:UInt) = VecInit.tabulate(b)(i => a).reduce(Cat(_,_)) + // def bridge_gen(tag: Int, ahb_type: Boolean) = if(BUILD_AXI4) flip(tag, ahb_type) else ahb_bridge_gen(ahb_type) + +// def flip(tag: Int , ahb_type: Boolean) = if(ahb_type) Flipped(new axi_channels(tag)) else new axi_channels(tag) + +// def ahb_bridge_gen(ahb_type: Boolean) = if(ahb_type) new Bundle{ +// val sig = Flipped(new ahb_channel()) + // val hsel = Input(Bool()) + // val hreadyin = Input(Bool())} +// else new ahb_channel() + def MEM_CAL : (Int, Int, Int, Int)= (ICACHE_WAYPACK, ICACHE_ECC) match{ - case(false,false) => (68, 22, 68, 22) - case(false,true) => (71, 26, 71, 26) - case(true,false) => (68*ICACHE_NUM_WAYS, 22*ICACHE_NUM_WAYS, 68, 22) - case(true,true) => (71*ICACHE_NUM_WAYS, 26*ICACHE_NUM_WAYS, 71, 26) + case(0,0) => (68, 22, 68, 22) + case(0,1) => (71, 26, 71, 26) + case(1,0) => (68*ICACHE_NUM_WAYS, 22*ICACHE_NUM_WAYS, 68, 22) + case(1,1) => (71*ICACHE_NUM_WAYS, 26*ICACHE_NUM_WAYS, 71, 26) } + val DATA_MEM_LINE = MEM_CAL val Tag_Word = MEM_CAL._4 - implicit def bool2int(b:Boolean) = if (b) 1 else 0 - implicit def aslong(b:Int) = 0xFFFFFFFFL & b + object rvsyncss { def apply(din:UInt,clk:Clock) =withClock(clk){RegNext(withClock(clk){RegNext(din,0.U)},0.U)} } diff --git a/src/main/scala/lib/param.scala b/src/main/scala/lib/param.scala new file mode 100644 index 00000000..0917162d --- /dev/null +++ b/src/main/scala/lib/param.scala @@ -0,0 +1,158 @@ +package lib +import chisel3._ +import chisel3.util._ +trait param { + val BHT_ADDR_HI = 0x9 + val BHT_ADDR_LO = 0x2 + val BHT_ARRAY_DEPTH = 0x100 + val BHT_GHR_HASH_1 = 0x0 + val BHT_GHR_SIZE = 0x8 + val BHT_SIZE = 0x200 + val BTB_ADDR_HI = 0x09 + val BTB_ADDR_LO = 0x2 + val BTB_ARRAY_DEPTH = 0x100 + val BTB_BTAG_FOLD = 0x0 + val BTB_BTAG_SIZE = 0x5 + val BTB_FOLD2_INDEX_HASH = 0x0 + val BTB_INDEX1_HI = 0x09 + val BTB_INDEX1_LO = 0x02 + val BTB_INDEX2_HI = 0x11 + val BTB_INDEX2_LO = 0x0A + val BTB_INDEX3_HI = 0x19 + val BTB_INDEX3_LO = 0x12 + val BTB_SIZE = 0x200 + val BUILD_AHB_LITE = 0x0 + val BUILD_AXI4 = 0x1 + val BUILD_AXI_NATIVE = 0x1 + val BUS_PRTY_DEFAULT = 0x3 + val DATA_ACCESS_ADDR0 = 0x00000000 + val DATA_ACCESS_ADDR1 = 0xC0000000 + val DATA_ACCESS_ADDR2 = 0xA0000000 + val DATA_ACCESS_ADDR3 = 0x80000000 + val DATA_ACCESS_ADDR4 = 0x00000000 + val DATA_ACCESS_ADDR5 = 0x00000000 + val DATA_ACCESS_ADDR6 = 0x00000000 + val DATA_ACCESS_ADDR7 = 0x00000000 + val DATA_ACCESS_ENABLE0 = 0x1 + val DATA_ACCESS_ENABLE1 = 0x1 + val DATA_ACCESS_ENABLE2 = 0x1 + val DATA_ACCESS_ENABLE3 = 0x1 + val DATA_ACCESS_ENABLE4 = 0x0 + val DATA_ACCESS_ENABLE5 = 0x0 + val DATA_ACCESS_ENABLE6 = 0x0 + val DATA_ACCESS_ENABLE7 = 0x0 + val DATA_ACCESS_MASK0 = 0x7FFFFFFF + val DATA_ACCESS_MASK1 = 0x3FFFFFFF + val DATA_ACCESS_MASK2 = 0x1FFFFFFF + val DATA_ACCESS_MASK3 = 0x0FFFFFFF + val DATA_ACCESS_MASK4 = 0xFFFFFFFF + val DATA_ACCESS_MASK5 = 0xFFFFFFFF + val DATA_ACCESS_MASK6 = 0xFFFFFFFF + val DATA_ACCESS_MASK7 = 0xFFFFFFFF + val DCCM_BANK_BITS = 0x2 + val DCCM_BITS = 0x10 + val DCCM_BYTE_WIDTH = 0x4 + val DCCM_DATA_WIDTH = 0x20 + val DCCM_ECC_WIDTH = 0x7 + val DCCM_ENABLE = 0x1 + val DCCM_FDATA_WIDTH = 0x27 + val DCCM_INDEX_BITS = 0xC + val DCCM_NUM_BANKS = 0x04 + val DCCM_REGION = 0xF + val DCCM_SADR = 0xF0040000 + val DCCM_SIZE = 0x040 + val DCCM_WIDTH_BITS = 0x2 + val DMA_BUF_DEPTH = 0x5 + val DMA_BUS_ID = 0x1 + val DMA_BUS_PRTY = 0x2 + val DMA_BUS_TAG = 0x1 + val FAST_INTERRUPT_REDIRECT = 0x1 + val ICACHE_2BANKS = 0x1 + val ICACHE_BANK_BITS = 0x1 + val ICACHE_BANK_HI = 0x3 + val ICACHE_BANK_LO = 0x3 + val ICACHE_BANK_WIDTH = 0x8 + val ICACHE_BANKS_WAY = 0x2 + val ICACHE_BEAT_ADDR_HI = 0x5 + val ICACHE_BEAT_BITS = 0x3 + val ICACHE_DATA_DEPTH = 0x0200 + val ICACHE_DATA_INDEX_LO = 0x4 + val ICACHE_DATA_WIDTH = 0x40 + val ICACHE_ECC = 0x1 + val ICACHE_ENABLE = 0x1 + val ICACHE_FDATA_WIDTH = 0x47 + val ICACHE_INDEX_HI = 0x0C + val ICACHE_LN_SZ = 0x40 + val ICACHE_NUM_BEATS = 0x8 + val ICACHE_NUM_WAYS = 0x2 + val ICACHE_ONLY = 0x0 + val ICACHE_SCND_LAST = 0x6 + val ICACHE_SIZE = 0x010 + val ICACHE_STATUS_BITS = 0x1 + val ICACHE_TAG_DEPTH = 0x0080 + val ICACHE_TAG_INDEX_LO = 0x6 + val ICACHE_TAG_LO = 0x0D + val ICACHE_WAYPACK = 0x0 + val ICCM_BANK_BITS = 0x2 + val ICCM_BANK_HI = 0x03 + val ICCM_BANK_INDEX_LO = 0x04 + val ICCM_BITS = 0x10 + val ICCM_ENABLE = 0x1 + val ICCM_ICACHE = 0x1 + val ICCM_INDEX_BITS = 0xC + val ICCM_NUM_BANKS = 0x04 + val ICCM_ONLY = 0x0 + val ICCM_REGION = 0xE + val ICCM_SADR = 0xEE000000 + val ICCM_SIZE = 0x040 + val IFU_BUS_ID = 0x1 + val IFU_BUS_PRTY = 0x2 + val IFU_BUS_TAG = 0x3 + val INST_ACCESS_ADDR0 = 0x00000000 + val INST_ACCESS_ADDR1 = 0xC0000000 + val INST_ACCESS_ADDR2 = 0xA0000000 + val INST_ACCESS_ADDR3 = 0x80000000 + val INST_ACCESS_ADDR4 = 0x00000000 + val INST_ACCESS_ADDR5 = 0x00000000 + val INST_ACCESS_ADDR6 = 0x00000000 + val INST_ACCESS_ADDR7 = 0x00000000 + val INST_ACCESS_ENABLE0 = 0x1 + val INST_ACCESS_ENABLE1 = 0x1 + val INST_ACCESS_ENABLE2 = 0x1 + val INST_ACCESS_ENABLE3 = 0x1 + val INST_ACCESS_ENABLE4 = 0x0 + val INST_ACCESS_ENABLE5 = 0x0 + val INST_ACCESS_ENABLE6 = 0x0 + val INST_ACCESS_ENABLE7 = 0x0 + val INST_ACCESS_MASK0 = 0x7FFFFFFF + val INST_ACCESS_MASK1 = 0x3FFFFFFF + val INST_ACCESS_MASK2 = 0x1FFFFFFF + val INST_ACCESS_MASK3 = 0x0FFFFFFF + val INST_ACCESS_MASK4 = 0xFFFFFFFF + val INST_ACCESS_MASK5 = 0xFFFFFFFF + val INST_ACCESS_MASK6 = 0xFFFFFFFF + val INST_ACCESS_MASK7 = 0xFFFFFFFF + val LOAD_TO_USE_PLUS1 = 0x0 + val LSU2DMA = 0x0 + val LSU_BUS_ID = 0x1 + val LSU_BUS_PRTY = 0x2 + val LSU_BUS_TAG = 0x3 + val LSU_NUM_NBLOAD = 0x04 + val LSU_NUM_NBLOAD_WIDTH = 0x2 + val LSU_SB_BITS = 0x10 + val LSU_STBUF_DEPTH = 0x4 + val NO_ICCM_NO_ICACHE = 0x0 + val PIC_2CYCLE = 0x0 + val PIC_BASE_ADDR = 0xF00C0000 + val PIC_BITS = 0x0F + val PIC_INT_WORDS = 0x1 + val PIC_REGION = 0xF + val PIC_SIZE = 0x020 + val PIC_TOTAL_INT = 0x1F + val PIC_TOTAL_INT_PLUS1 = 0x020 + val RET_STACK_SIZE = 0x8 + val SB_BUS_ID = 0x1 + val SB_BUS_PRTY = 0x2 + val SB_BUS_TAG = 0x1 + val TIMER_LEGAL_EN = 0x1 +} diff --git a/src/main/scala/lsu/lsu.scala b/src/main/scala/lsu/lsu.scala index d3494a4a..7a72d2cc 100644 --- a/src/main/scala/lsu/lsu.scala +++ b/src/main/scala/lsu/lsu.scala @@ -6,7 +6,7 @@ import chisel3.util._ import include._ import mem._ -class lsu extends Module with RequireAsyncReset with param with lib { +class lsu extends Module with RequireAsyncReset with lib { val io = IO (new Bundle { val clk_override = Input(Bool()) val lsu_dma = new lsu_dma @@ -319,6 +319,6 @@ class lsu extends Module with RequireAsyncReset with param with lib { withClock(clkdomain.io.lsu_c2_r_clk){lsu_raw_fwd_lo_r := RegNext(lsu_raw_fwd_lo_m,0.U)} } -object lsu_top extends App { - println((new chisel3.stage.ChiselStage).emitVerilog(new lsu())) -} \ No newline at end of file +//object lsu_top extends App { + // println((new chisel3.stage.ChiselStage).emitVerilog(new lsu())) +//} \ No newline at end of file diff --git a/src/main/scala/lsu/lsu_bus_buffer.scala b/src/main/scala/lsu/lsu_bus_buffer.scala index 38741796..54cd5040 100644 --- a/src/main/scala/lsu/lsu_bus_buffer.scala +++ b/src/main/scala/lsu/lsu_bus_buffer.scala @@ -618,6 +618,6 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib { lsu_nonblock_load_valid_r := withClock(io.lsu_c2_r_clk){RegNext(io.dctl_busbuff.lsu_nonblock_load_valid_m, false.B)} } -object bus_buffer extends App { - println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_bus_buffer())) -} \ No newline at end of file +//object bus_buffer extends App { +// println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_bus_buffer())) +//} \ No newline at end of file diff --git a/src/main/scala/mem.scala b/src/main/scala/mem.scala index 3cb753d3..435f3871 100644 --- a/src/main/scala/mem.scala +++ b/src/main/scala/mem.scala @@ -28,37 +28,6 @@ class Mem_bundle extends Bundle with lib { val iccm = Flipped(new iccm_mem()) val ic = Flipped (new ic_mem()) val scan_mode = Input(Bool()) - // val iccm_rw_addr = Input(UInt((ICCM_BITS-1).W)) - // val iccm_buf_correct_ecc = Input(Bool()) - // val iccm_correction_state = Input(Bool()) -// val iccm_wren = Input(Bool()) -// val iccm_rden = Input(Bool()) -// val iccm_wr_size = Input(UInt(3.W)) - // val iccm_wr_data = Input(UInt(78.W)) - // val ic_rw_addr = Input(UInt(31.W)) - // val ic_tag_valid = Input(UInt(ICACHE_NUM_WAYS.W)) - // val ic_wr_en = Input(UInt(ICACHE_NUM_WAYS.W)) - // val ic_rd_en = Input(Bool()) - // val ic_premux_data = Input(UInt(64.W)) -// val ic_sel_premux_data = Input(Bool()) - // val ic_wr_data = Input(Vec(ICACHE_BANKS_WAY, UInt(71.W))) - // val ic_debug_wr_data = Input(UInt(71.W)) - // val ic_debug_addr = Input(UInt((ICACHE_INDEX_HI-2).W)) - // val ic_debug_rd_en = Input(Bool()) - // val ic_debug_wr_en = Input(Bool()) -// val ic_debug_tag_array = Input(Bool()) - // val ic_debug_way = Input(UInt(ICACHE_NUM_WAYS.W)) -// val scan_mode = Input(Bool()) -// val iccm_rd_data_ecc = Output(UInt(78.W)) -// val ic_rd_data = Output(UInt(64.W)) - // val ictag_debug_rd_data = Output(UInt(26.W)) -// val ic_eccerr = Output(UInt(ICACHE_BANKS_WAY.W)) -// val ic_parerr = Output(UInt(ICACHE_BANKS_WAY.W)) -// val ic_rd_hit = Output(UInt(ICACHE_NUM_WAYS.W)) - // val ic_tag_perr = Output(Bool()) - // val ic_debug_rd_data = Output(UInt(71.W)) - // val iccm_rd_data = Output(UInt(64.W)) - } object quasar extends lib { class mem extends BlackBox(Map("DCCM_BITS" -> DCCM_BITS, @@ -67,16 +36,16 @@ object quasar extends lib { "ICACHE_NUM_WAYS" -> ICACHE_NUM_WAYS, "ICACHE_BANKS_WAY" -> ICACHE_BANKS_WAY, "ICACHE_INDEX_HI" -> ICACHE_INDEX_HI, - "DCCM_ENABLE" -> bool2int(DCCM_ENABLE), - "ICACHE_ENABLE" -> bool2int(ICCM_ENABLE), - "ICCM_ENABLE" -> bool2int(ICCM_ENABLE), + "DCCM_ENABLE" -> DCCM_ENABLE, + "ICACHE_ENABLE" -> ICCM_ENABLE, + "ICCM_ENABLE" -> ICCM_ENABLE, "ICACHE_TAG_INDEX_LO" -> ICACHE_TAG_INDEX_LO, "ICACHE_DATA_INDEX_LO" -> ICACHE_DATA_INDEX_LO, "ICACHE_TAG_LO" -> ICACHE_TAG_LO, "ICACHE_BANK_LO" -> ICACHE_BANK_LO, "ICACHE_BANK_HI" -> ICACHE_BANK_HI, - "ICACHE_WAYPACK" -> bool2int(ICACHE_WAYPACK), - "ICACHE_ECC" -> bool2int(ICACHE_ECC), + "ICACHE_WAYPACK" -> ICACHE_WAYPACK, + "ICACHE_ECC" -> ICACHE_ECC, "ICACHE_DATA_DEPTH" -> ICACHE_DATA_DEPTH, "ICACHE_BANK_BITS" -> ICACHE_BANK_BITS, "ICACHE_BEAT_ADDR_HI" -> ICACHE_BEAT_ADDR_HI, @@ -99,8 +68,4 @@ class blackbox_mem extends Module with lib { val io = IO(new Mem_bundle) val it = Module(new quasar.mem) io <> it.io -} - -object mem extends App { - println((new chisel3.stage.ChiselStage).emitVerilog(new blackbox_mem)) -} +} \ No newline at end of file diff --git a/src/main/scala/pic_ctrl.scala b/src/main/scala/pic_ctrl.scala index 195085d7..d7aedaaa 100644 --- a/src/main/scala/pic_ctrl.scala +++ b/src/main/scala/pic_ctrl.scala @@ -165,7 +165,7 @@ class pic_ctrl extends Module with RequireAsyncReset with lib { - if (PIC_2CYCLE == 1) { + if (PIC_2CYCLE) { val level_intpend_w_prior_en = Wire(Vec((NUM_LEVELS/2)+1, Vec(PIC_TOTAL_INT_PLUS1+3, UInt(INTPRIORITY_BITS.W)))) //PIC_TOTAL_INT_PLUS1+3 should be there val level_intpend_id = Wire(Vec((NUM_LEVELS/2)+1, Vec(PIC_TOTAL_INT_PLUS1+3, UInt(ID_BITS.W)))) //PIC_TOTAL_INT_PLUS1+3 should be there for(i<-0 until (NUM_LEVELS/2)+1; j<-0 until PIC_TOTAL_INT_PLUS1+3){ //PIC_TOTAL_INT_PLUS1+3 should be there @@ -406,7 +406,6 @@ class pic_ctrl extends Module with RequireAsyncReset with lib { } -object pic_main extends App{ - println("Generating Verilog...") - println((new chisel3.stage.ChiselStage).emitVerilog(new pic_ctrl())) -} \ No newline at end of file +//object pic_gen extends App { +// println((new chisel3.stage.ChiselStage).emitVerilog(new pic_ctrl())) +//} diff --git a/src/main/scala/snapshot/el2_param.scala b/src/main/scala/snapshot/el2_param.scala deleted file mode 100644 index 40978129..00000000 --- a/src/main/scala/snapshot/el2_param.scala +++ /dev/null @@ -1,158 +0,0 @@ -package snapshot -import chisel3._ - -object pt{ - val BHT_ADDR_HI = "h9".U(4.W) - val BHT_ADDR_LO = "h2".U(2.W) - val BHT_ARRAY_DEPTH = "h100".U(11.W) - val BHT_GHR_HASH_1 = "h0".U(1.W) - val BHT_GHR_SIZE = "8h".U(4.W) - val BHT_SIZE = "h200".U(12.W) - val BTB_ADDR_HI = "h09".U(5.W) - val BTB_ADDR_LO = "h2".U(2.W) - val BTB_ARRAY_DEPTH = "h100".U(9.W) - val BTB_BTAG_FOLD = "h0".U(1.W) - val BTB_BTAG_SIZE = "h5".U(4.W) - val BTB_FOLD2_INDEX_HASH = "h0".U(1.W) - val BTB_INDEX1_HI = "h09".U(5.W) - val BTB_INDEX1_LO = "h02".U(5.W) - val BTB_INDEX2_HI = "h11".U(5.W) - val BTB_INDEX2_LO = "h0A".U(5.W) - val BTB_INDEX3_HI = "h19".U(5.W) - val BTB_INDEX3_LO = "h12".U(5.W) - val BTB_SIZE = "h200".U(10.W) - val BUILD_AHB_LITE = "h0".U(1.W) - val BUILD_AXI4 = "h1".U(1.W) - val BUILD_AXI_NATIVE = "h1".U(1.W) - val BUS_PRTY_DEFAULT = "h3".U(2.W) - val DATA_ACCESS_ADDR0 = "h00000000".U(32.W) - val DATA_ACCESS_ADDR1 = "hC0000000".U(32.W) - val DATA_ACCESS_ADDR2 = "hA0000000".U(32.W) - val DATA_ACCESS_ADDR3 = "h80000000".U(32.W) - val DATA_ACCESS_ADDR4 = "h00000000".U(32.W) - val DATA_ACCESS_ADDR5 = "h00000000".U(32.W) - val DATA_ACCESS_ADDR6 = "h00000000".U(32.W) - val DATA_ACCESS_ADDR7 = "h00000000".U(32.W) - val DATA_ACCESS_ENABLE0 = "h1".U(1.W) - val DATA_ACCESS_ENABLE1 = "h1".U(1.W) - val DATA_ACCESS_ENABLE2 = "h1".U(1.W) - val DATA_ACCESS_ENABLE3 = "h1".U(1.W) - val DATA_ACCESS_ENABLE4 = "h0".U(1.W) - val DATA_ACCESS_ENABLE5 = "h0".U(1.W) - val DATA_ACCESS_ENABLE6 = "h0".U(1.W) - val DATA_ACCESS_ENABLE7 = "h0".U(1.W) - val DATA_ACCESS_MASK0 = "h7FFFFFFF".U(32.W) - val DATA_ACCESS_MASK1 = "h3FFFFFFF".U(32.W) - val DATA_ACCESS_MASK2 = "h1FFFFFFF".U(32.W) - val DATA_ACCESS_MASK3 = "h0FFFFFFF".U(32.W) - val DATA_ACCESS_MASK4 = "hFFFFFFFF".U(32.W) - val DATA_ACCESS_MASK5 = "hFFFFFFFF".U(32.W) - val DATA_ACCESS_MASK6 = "hFFFFFFFF".U(32.W) - val DATA_ACCESS_MASK7 = "hFFFFFFFF".U(32.W) - val DCCM_BANK_BITS = "h2".U(3.W) - val DCCM_BITS = "h10".U(5.W) - val DCCM_BYTE_WIDTH = "h4".U(3.W) - val DCCM_DATA_WIDTH = "h20".U(6.W) - val DCCM_ECC_WIDTH = "h7".U(3.W) - val DCCM_ENABLE = "h1".U(1.W) - val DCCM_FDATA_WIDTH = "h27".U(6.W) - val DCCM_INDEX_BITS = "hC".U(4.W) - val DCCM_NUM_BANKS = "h04".U(5.W) - val DCCM_REGION = "hF".U(4.W) - val DCCM_SADR = "hF0040000".U(32.W) - val DCCM_SIZE = "h040".U(10.W) - val DCCM_WIDTH_BITS = "h2".U(2.W) - val DMA_BUF_DEPTH = "h5".U(3.W) - val DMA_BUS_ID = "h1".U(1.W) - val DMA_BUS_PRTY = "h2".U(2.W) - val DMA_BUS_TAG = "h1".U(4.W) - val FAST_INTERRUPT_REDIRECT= "h1".U(1.W) - val ICACHE_2BANKS = "h1".U(1.W) - val ICACHE_BANK_BITS = "h1".U(3.W) - val ICACHE_BANK_HI = "h3".U(3.W) - val ICACHE_BANK_LO = "h3".U(2.W) - val ICACHE_BANK_WIDTH = "h8".U(4.W) - val ICACHE_BANKS_WAY = "h2".U(3.W) - val ICACHE_BEAT_ADDR_HI = "h5".U(4.W) - val ICACHE_BEAT_BITS = "h3".U(4.W) - val ICACHE_DATA_DEPTH = "h0200".U(14.W) - val ICACHE_DATA_INDEX_LO = "h4".U(3.W) - val ICACHE_DATA_WIDTH = "h40".U(7.W) - val ICACHE_ECC = "h1".U(1.W) - val ICACHE_ENABLE = "h1".U(1.W) - val ICACHE_FDATA_WIDTH = "h47".U(7.W) - val ICACHE_INDEX_HI = "h0C".U(5.W) - val ICACHE_LN_SZ = "h40".U(7.W) - val ICACHE_NUM_BEATS = "h8".U(4.W) - val ICACHE_NUM_WAYS = "h2".U(3.W) - val ICACHE_ONLY = "h0".U(1.W) - val ICACHE_SCND_LAST = "h6".U(4.W) - val ICACHE_SIZE = "h010".U(9.W) - val ICACHE_STATUS_BITS = "h1".U(3.W) - val ICACHE_TAG_DEPTH = "h0080".U(13.W) - val ICACHE_TAG_INDEX_LO = "h6".U(3.W) - val ICACHE_TAG_LO = "h0D".U(5.W) - val ICACHE_WAYPACK = "h0".U(1.W) - val ICCM_BANK_BITS = "h2".U(3.W) - val ICCM_BANK_HI = "h03".U(5.W) - val ICCM_BANK_INDEX_LO = "h04".U(5.W) - val ICCM_BITS = "h10".U(5.W) - val ICCM_ENABLE = "h1".U(1.W) - val ICCM_ICACHE = "h1".U(1.W) - val ICCM_INDEX_BITS = "hC".U(4.W) - val ICCM_NUM_BANKS = "h04".U(5.W) - val ICCM_ONLY = "h0".U(1.W) - val ICCM_REGION = "hE".U(4.W) - val ICCM_SADR = "hEE000000".U(32.W) - val ICCM_SIZE = "h040".U(10.W) - val IFU_BUS_ID = "h1".U(1.W) - val IFU_BUS_PRTY = "h2".U(2.W) - val IFU_BUS_TAG = "h3".U(4.W) - val INST_ACCESS_ADDR0 = "h00000000".U(32.W) - val INST_ACCESS_ADDR1 = "hC0000000".U(32.W) - val INST_ACCESS_ADDR2 = "hA0000000".U(32.W) - val INST_ACCESS_ADDR3 = "h80000000".U(32.W) - val INST_ACCESS_ADDR4 = "h00000000".U(32.W) - val INST_ACCESS_ADDR5 = "h00000000".U(32.W) - val INST_ACCESS_ADDR6 = "h00000000".U(32.W) - val INST_ACCESS_ADDR7 = "h00000000".U(32.W) - val INST_ACCESS_ENABLE0 = "h1".U(1.W) - val INST_ACCESS_ENABLE1 = "h1".U(1.W) - val INST_ACCESS_ENABLE2 = "h1".U(1.W) - val INST_ACCESS_ENABLE3 = "h1".U(1.W) - val INST_ACCESS_ENABLE4 = "h0".U(1.W) - val INST_ACCESS_ENABLE5 = "h0".U(1.W) - val INST_ACCESS_ENABLE6 = "h0".U(1.W) - val INST_ACCESS_ENABLE7 = "h0".U(1.W) - val INST_ACCESS_MASK0 = "h7FFFFFFF".U(32.W) - val INST_ACCESS_MASK1 = "h3FFFFFFF".U(32.W) - val INST_ACCESS_MASK2 = "h1FFFFFFF".U(32.W) - val INST_ACCESS_MASK3 = "h0FFFFFFF".U(32.W) - val INST_ACCESS_MASK4 = "hFFFFFFFF".U(32.W) - val INST_ACCESS_MASK5 = "hFFFFFFFF".U(32.W) - val INST_ACCESS_MASK6 = "hFFFFFFFF".U(32.W) - val INST_ACCESS_MASK7 = "hFFFFFFFF".U(32.W) - val LOAD_TO_USE_PLUS1 = "h0".U(1.W) - val LSU2DMA = "h0".U(1.W) - val LSU_BUS_ID = "h1".U(1.W) - val LSU_BUS_PRTY = "h2".U(2.W) - val LSU_BUS_TAG = "h3".U(4.W) - val LSU_NUM_NBLOAD = "h04".U(5.W) - val LSU_NUM_NBLOAD_WIDTH = "h2".U(3.W) - val LSU_SB_BITS = "h10".U(5.W) - val LSU_STBUF_DEPTH = "h4".U(4.W) - val NO_ICCM_NO_ICACHE = "h0".U(1.W) - val PIC_2CYCLE = "h0".U(1.W) - val PIC_BASE_ADDR = "hF00C0000".U(32.W) - val PIC_BITS = "h0F".U(5.W) - val PIC_INT_WORDS = "h1".U(4.W) - val PIC_REGION = "hF".U(4.W) - val PIC_SIZE = "h020".U(9.W) - val PIC_TOTAL_INT = "h1F".U(8.W) - val PIC_TOTAL_INT_PLUS1 = "h020".U(9.W) - val RET_STACK_SIZE = "h8".U(4.W) - val SB_BUS_ID = "h1".U(1.W) - val SB_BUS_PRTY = "h2".U(2.W) - val SB_BUS_TAG = "h1".U(4.W) - val TIMER_LEGAL_EN = "h1".U(1.W) -} diff --git a/target/scala-2.12/classes/dbg/dbg.class b/target/scala-2.12/classes/dbg/dbg.class index c8a0d0b5..888c1889 100644 Binary files a/target/scala-2.12/classes/dbg/dbg.class and b/target/scala-2.12/classes/dbg/dbg.class differ diff --git a/target/scala-2.12/classes/dbg/dbg_main$.class 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