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axi to ahb update

This commit is contained in:
​Laraib Khan 2020-11-30 15:31:49 +05:00
parent ad3359da87
commit 3c00117ccf
4 changed files with 996 additions and 305 deletions
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494
axi4_to_ahb.fir
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@ -144,6 +144,102 @@ circuit axi4_to_ahb :
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_6 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_6 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_6 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_7 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_7 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_7 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_8 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_8 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_8 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_9 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_9 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_9 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
module axi4_to_ahb :
input clock : Clock
input reset : AsyncReset
@ -1082,207 +1178,221 @@ circuit axi4_to_ahb :
node _T_617 = and(_T_616, io.ahb_hready) @[axi4_to_ahb.scala 349:52]
node _T_618 = and(_T_617, io.ahb_hwrite) @[axi4_to_ahb.scala 349:68]
last_addr_en <= _T_618 @[axi4_to_ahb.scala 349:16]
node _T_619 = and(UInt<1>("h01"), wrbuf_rst) @[axi4_to_ahb.scala 352:58]
node _T_620 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 352:114]
reg _T_621 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_620 : @[Reg.scala 28:19]
_T_621 <= _T_619 @[Reg.scala 28:23]
node _T_619 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 352:68]
node _T_620 = mux(_T_619, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 352:52]
node _T_621 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 352:88]
node _T_622 = and(_T_620, _T_621) @[axi4_to_ahb.scala 352:86]
reg _T_623 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 352:48]
_T_623 <= _T_622 @[axi4_to_ahb.scala 352:48]
wrbuf_vld <= _T_623 @[axi4_to_ahb.scala 352:18]
node _T_624 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 353:73]
node _T_625 = mux(_T_624, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 353:52]
node _T_626 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 353:99]
node _T_627 = and(_T_625, _T_626) @[axi4_to_ahb.scala 353:97]
reg _T_628 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 353:48]
_T_628 <= _T_627 @[axi4_to_ahb.scala 353:48]
wrbuf_data_vld <= _T_628 @[axi4_to_ahb.scala 353:18]
node _T_629 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 355:57]
node _T_630 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 355:91]
reg _T_631 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_630 : @[Reg.scala 28:19]
_T_631 <= _T_629 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
wrbuf_vld <= _T_621 @[axi4_to_ahb.scala 352:18]
node _T_622 = and(UInt<1>("h01"), wrbuf_rst) @[axi4_to_ahb.scala 353:58]
node _T_623 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 353:119]
reg _T_624 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_623 : @[Reg.scala 28:19]
_T_624 <= _T_622 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
wrbuf_data_vld <= _T_624 @[axi4_to_ahb.scala 353:18]
node _T_625 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 355:57]
node _T_626 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 355:91]
reg _T_627 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_626 : @[Reg.scala 28:19]
_T_627 <= _T_625 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
wrbuf_tag <= _T_627 @[axi4_to_ahb.scala 355:13]
node _T_628 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 356:60]
node _T_629 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 356:88]
reg _T_630 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_629 : @[Reg.scala 28:19]
_T_630 <= _T_628 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
wrbuf_size <= _T_630 @[axi4_to_ahb.scala 356:14]
node _T_631 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 358:62]
reg _T_632 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_631 : @[Reg.scala 28:19]
_T_632 <= io.axi_awaddr @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
wrbuf_addr <= _T_632 @[axi4_to_ahb.scala 358:14]
node _T_633 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 359:66]
reg _T_634 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
wrbuf_tag <= _T_631 @[axi4_to_ahb.scala 355:13]
node _T_632 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 356:60]
node _T_633 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 356:88]
reg _T_634 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_633 : @[Reg.scala 28:19]
_T_634 <= io.axi_wdata @[Reg.scala 28:23]
_T_634 <= _T_632 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
wrbuf_data <= _T_634 @[axi4_to_ahb.scala 359:14]
node _T_635 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 362:27]
node _T_636 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 362:60]
reg _T_637 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_636 : @[Reg.scala 28:19]
_T_637 <= _T_635 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
wrbuf_byteen <= _T_637 @[axi4_to_ahb.scala 361:16]
node _T_638 = bits(io.ahb_haddr, 31, 0) @[axi4_to_ahb.scala 365:27]
node _T_639 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 365:60]
reg _T_640 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_639 : @[Reg.scala 28:19]
_T_640 <= _T_638 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
last_bus_addr <= _T_640 @[axi4_to_ahb.scala 364:17]
node _T_641 = bits(buf_rst, 0, 0) @[Bitwise.scala 72:15]
node _T_642 = mux(_T_641, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_643 = and(buf_nxtstate, _T_642) @[axi4_to_ahb.scala 369:28]
node _T_644 = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 369:92]
reg _T_645 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_644 : @[Reg.scala 28:19]
_T_645 <= _T_643 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
buf_state <= _T_645 @[axi4_to_ahb.scala 368:13]
node _T_646 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 373:50]
reg _T_647 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_646 : @[Reg.scala 28:19]
_T_647 <= buf_write_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
buf_write <= _T_647 @[axi4_to_ahb.scala 372:13]
node _T_648 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 376:25]
node _T_649 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 376:60]
reg _T_650 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_649 : @[Reg.scala 28:19]
_T_650 <= _T_648 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
buf_tag <= _T_650 @[axi4_to_ahb.scala 375:11]
node _T_651 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 379:36]
node _T_652 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 379:61]
node _T_653 = bits(_T_652, 0, 0) @[axi4_to_ahb.scala 379:78]
reg _T_654 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_653 : @[Reg.scala 28:19]
_T_654 <= _T_651 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
buf_addr <= _T_654 @[axi4_to_ahb.scala 379:12]
node _T_655 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 382:23]
node _T_656 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 382:52]
reg _T_657 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_656 : @[Reg.scala 28:19]
_T_657 <= _T_655 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
buf_size <= _T_657 @[axi4_to_ahb.scala 381:12]
node _T_658 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 385:52]
reg _T_659 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_658 : @[Reg.scala 28:19]
_T_659 <= buf_aligned_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
buf_aligned <= _T_659 @[axi4_to_ahb.scala 384:15]
node _T_660 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 388:25]
node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 388:54]
reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_661 : @[Reg.scala 28:19]
_T_662 <= _T_660 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
buf_byteen <= _T_662 @[axi4_to_ahb.scala 387:14]
node _T_663 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 391:36]
node _T_664 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 391:66]
node _T_665 = bits(_T_664, 0, 0) @[axi4_to_ahb.scala 391:89]
reg _T_666 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_665 : @[Reg.scala 28:19]
_T_666 <= _T_663 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
buf_data <= _T_666 @[axi4_to_ahb.scala 391:12]
node _T_667 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 394:50]
reg _T_668 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_667 : @[Reg.scala 28:19]
_T_668 <= buf_write @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
slvbuf_write <= _T_668 @[axi4_to_ahb.scala 393:16]
node _T_669 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 397:22]
node _T_670 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 397:60]
reg _T_671 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_670 : @[Reg.scala 28:19]
_T_671 <= _T_669 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
slvbuf_tag <= _T_671 @[axi4_to_ahb.scala 396:14]
node _T_672 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 400:59]
reg _T_673 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_672 : @[Reg.scala 28:19]
_T_673 <= slvbuf_error_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
slvbuf_error <= _T_673 @[axi4_to_ahb.scala 399:16]
node _T_674 = and(UInt<1>("h01"), cmd_done_rst) @[axi4_to_ahb.scala 404:22]
node _T_675 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 404:81]
reg _T_676 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_675 : @[Reg.scala 28:19]
_T_676 <= _T_674 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
cmd_doneQ <= _T_676 @[axi4_to_ahb.scala 403:13]
node _T_677 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 408:31]
node _T_678 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 408:70]
reg _T_679 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_678 : @[Reg.scala 28:19]
_T_679 <= _T_677 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
buf_cmd_byte_ptrQ <= _T_679 @[axi4_to_ahb.scala 407:21]
reg _T_680 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 413:12]
_T_680 <= io.ahb_hready @[axi4_to_ahb.scala 413:12]
ahb_hready_q <= _T_680 @[axi4_to_ahb.scala 412:16]
node _T_681 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 416:26]
reg _T_682 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 416:12]
_T_682 <= _T_681 @[axi4_to_ahb.scala 416:12]
ahb_htrans_q <= _T_682 @[axi4_to_ahb.scala 415:16]
reg _T_683 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 419:12]
_T_683 <= io.ahb_hwrite @[axi4_to_ahb.scala 419:12]
ahb_hwrite_q <= _T_683 @[axi4_to_ahb.scala 418:16]
reg _T_684 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 422:12]
_T_684 <= io.ahb_hresp @[axi4_to_ahb.scala 422:12]
ahb_hresp_q <= _T_684 @[axi4_to_ahb.scala 421:15]
node _T_685 = bits(io.ahb_hrdata, 63, 0) @[axi4_to_ahb.scala 425:26]
reg _T_686 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 425:12]
_T_686 <= _T_685 @[axi4_to_ahb.scala 425:12]
ahb_hrdata_q <= _T_686 @[axi4_to_ahb.scala 424:16]
node _T_687 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 428:43]
node _T_688 = or(_T_687, io.clk_override) @[axi4_to_ahb.scala 428:58]
node _T_689 = and(io.bus_clk_en, _T_688) @[axi4_to_ahb.scala 428:30]
buf_clken <= _T_689 @[axi4_to_ahb.scala 428:13]
node _T_690 = bits(io.ahb_htrans, 1, 1) @[axi4_to_ahb.scala 429:69]
node _T_691 = and(io.ahb_hready, _T_690) @[axi4_to_ahb.scala 429:54]
node _T_692 = or(_T_691, io.clk_override) @[axi4_to_ahb.scala 429:74]
node _T_693 = and(io.bus_clk_en, _T_692) @[axi4_to_ahb.scala 429:36]
ahbm_addr_clken <= _T_693 @[axi4_to_ahb.scala 429:19]
node _T_694 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 430:50]
node _T_695 = or(_T_694, io.clk_override) @[axi4_to_ahb.scala 430:60]
node _T_696 = and(io.bus_clk_en, _T_695) @[axi4_to_ahb.scala 430:36]
ahbm_data_clken <= _T_696 @[axi4_to_ahb.scala 430:19]
inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 483:22]
wrbuf_size <= _T_634 @[axi4_to_ahb.scala 356:14]
node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 358:48]
inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 508:23]
rvclkhdr_2.clock <= clock
rvclkhdr_2.reset <= reset
rvclkhdr_2.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr_2.io.en <= buf_clken @[el2_lib.scala 485:16]
rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
buf_clk <= rvclkhdr_2.io.l1clk @[axi4_to_ahb.scala 433:11]
inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 483:22]
rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_2.io.en <= _T_635 @[el2_lib.scala 511:17]
rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_636 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_636 <= io.axi_awaddr @[el2_lib.scala 514:16]
wrbuf_addr <= _T_636 @[axi4_to_ahb.scala 358:14]
node _T_637 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 359:52]
inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23]
rvclkhdr_3.clock <= clock
rvclkhdr_3.reset <= reset
rvclkhdr_3.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr_3.io.en <= io.bus_clk_en @[el2_lib.scala 485:16]
rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
ahbm_clk <= rvclkhdr_3.io.l1clk @[axi4_to_ahb.scala 434:12]
inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 483:22]
rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_3.io.en <= _T_637 @[el2_lib.scala 511:17]
rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_638 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_638 <= io.axi_wdata @[el2_lib.scala 514:16]
wrbuf_data <= _T_638 @[axi4_to_ahb.scala 359:14]
node _T_639 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 362:27]
node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 362:60]
reg _T_641 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_640 : @[Reg.scala 28:19]
_T_641 <= _T_639 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
wrbuf_byteen <= _T_641 @[axi4_to_ahb.scala 361:16]
node _T_642 = bits(io.ahb_haddr, 31, 0) @[axi4_to_ahb.scala 365:27]
node _T_643 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 365:60]
reg _T_644 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_643 : @[Reg.scala 28:19]
_T_644 <= _T_642 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
last_bus_addr <= _T_644 @[axi4_to_ahb.scala 364:17]
node _T_645 = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 369:36]
node _T_646 = mux(_T_645, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 369:16]
node _T_647 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 369:65]
node _T_648 = and(_T_646, _T_647) @[axi4_to_ahb.scala 369:63]
reg _T_649 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 369:12]
_T_649 <= _T_648 @[axi4_to_ahb.scala 369:12]
buf_state <= _T_649 @[axi4_to_ahb.scala 368:13]
node _T_650 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 373:50]
reg _T_651 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_650 : @[Reg.scala 28:19]
_T_651 <= buf_write_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
buf_write <= _T_651 @[axi4_to_ahb.scala 372:13]
node _T_652 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 376:25]
node _T_653 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 376:60]
reg _T_654 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_653 : @[Reg.scala 28:19]
_T_654 <= _T_652 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
buf_tag <= _T_654 @[axi4_to_ahb.scala 375:11]
node _T_655 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 379:33]
node _T_656 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 379:52]
node _T_657 = bits(_T_656, 0, 0) @[axi4_to_ahb.scala 379:69]
inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 508:23]
rvclkhdr_4.clock <= clock
rvclkhdr_4.reset <= reset
rvclkhdr_4.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr_4.io.en <= ahbm_addr_clken @[el2_lib.scala 485:16]
rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
ahbm_addr_clk <= rvclkhdr_4.io.l1clk @[axi4_to_ahb.scala 435:17]
inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 483:22]
rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_4.io.en <= _T_657 @[el2_lib.scala 511:17]
rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_658 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_658 <= _T_655 @[el2_lib.scala 514:16]
buf_addr <= _T_658 @[axi4_to_ahb.scala 379:12]
node _T_659 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 382:23]
node _T_660 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 382:52]
reg _T_661 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_660 : @[Reg.scala 28:19]
_T_661 <= _T_659 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
buf_size <= _T_661 @[axi4_to_ahb.scala 381:12]
node _T_662 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 385:52]
reg _T_663 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_662 : @[Reg.scala 28:19]
_T_663 <= buf_aligned_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
buf_aligned <= _T_663 @[axi4_to_ahb.scala 384:15]
node _T_664 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 388:25]
node _T_665 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 388:54]
reg _T_666 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_665 : @[Reg.scala 28:19]
_T_666 <= _T_664 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
buf_byteen <= _T_666 @[axi4_to_ahb.scala 387:14]
node _T_667 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 391:33]
node _T_668 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 391:57]
node _T_669 = bits(_T_668, 0, 0) @[axi4_to_ahb.scala 391:80]
inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 508:23]
rvclkhdr_5.clock <= clock
rvclkhdr_5.reset <= reset
rvclkhdr_5.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr_5.io.en <= ahbm_data_clken @[el2_lib.scala 485:16]
rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
ahbm_data_clk <= rvclkhdr_5.io.l1clk @[axi4_to_ahb.scala 436:17]
rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_5.io.en <= _T_669 @[el2_lib.scala 511:17]
rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_670 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_670 <= _T_667 @[el2_lib.scala 514:16]
buf_data <= _T_670 @[axi4_to_ahb.scala 391:12]
node _T_671 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 394:50]
reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_671 : @[Reg.scala 28:19]
_T_672 <= buf_write @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
slvbuf_write <= _T_672 @[axi4_to_ahb.scala 393:16]
node _T_673 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 397:22]
node _T_674 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 397:60]
reg _T_675 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_674 : @[Reg.scala 28:19]
_T_675 <= _T_673 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
slvbuf_tag <= _T_675 @[axi4_to_ahb.scala 396:14]
node _T_676 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 400:59]
reg _T_677 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_676 : @[Reg.scala 28:19]
_T_677 <= slvbuf_error_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
slvbuf_error <= _T_677 @[axi4_to_ahb.scala 399:16]
node _T_678 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 404:32]
node _T_679 = mux(_T_678, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 404:16]
node _T_680 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 404:52]
node _T_681 = and(_T_679, _T_680) @[axi4_to_ahb.scala 404:50]
reg _T_682 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 404:12]
_T_682 <= _T_681 @[axi4_to_ahb.scala 404:12]
cmd_doneQ <= _T_682 @[axi4_to_ahb.scala 403:13]
node _T_683 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 408:31]
node _T_684 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 408:70]
reg _T_685 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_684 : @[Reg.scala 28:19]
_T_685 <= _T_683 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
buf_cmd_byte_ptrQ <= _T_685 @[axi4_to_ahb.scala 407:21]
reg _T_686 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 413:12]
_T_686 <= io.ahb_hready @[axi4_to_ahb.scala 413:12]
ahb_hready_q <= _T_686 @[axi4_to_ahb.scala 412:16]
node _T_687 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 416:26]
reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 416:12]
_T_688 <= _T_687 @[axi4_to_ahb.scala 416:12]
ahb_htrans_q <= _T_688 @[axi4_to_ahb.scala 415:16]
reg _T_689 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 419:12]
_T_689 <= io.ahb_hwrite @[axi4_to_ahb.scala 419:12]
ahb_hwrite_q <= _T_689 @[axi4_to_ahb.scala 418:16]
reg _T_690 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 422:12]
_T_690 <= io.ahb_hresp @[axi4_to_ahb.scala 422:12]
ahb_hresp_q <= _T_690 @[axi4_to_ahb.scala 421:15]
node _T_691 = bits(io.ahb_hrdata, 63, 0) @[axi4_to_ahb.scala 425:26]
reg _T_692 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 425:12]
_T_692 <= _T_691 @[axi4_to_ahb.scala 425:12]
ahb_hrdata_q <= _T_692 @[axi4_to_ahb.scala 424:16]
node _T_693 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 428:43]
node _T_694 = or(_T_693, io.clk_override) @[axi4_to_ahb.scala 428:58]
node _T_695 = and(io.bus_clk_en, _T_694) @[axi4_to_ahb.scala 428:30]
buf_clken <= _T_695 @[axi4_to_ahb.scala 428:13]
node _T_696 = bits(io.ahb_htrans, 1, 1) @[axi4_to_ahb.scala 429:69]
node _T_697 = and(io.ahb_hready, _T_696) @[axi4_to_ahb.scala 429:54]
node _T_698 = or(_T_697, io.clk_override) @[axi4_to_ahb.scala 429:74]
node _T_699 = and(io.bus_clk_en, _T_698) @[axi4_to_ahb.scala 429:36]
ahbm_addr_clken <= _T_699 @[axi4_to_ahb.scala 429:19]
node _T_700 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 430:50]
node _T_701 = or(_T_700, io.clk_override) @[axi4_to_ahb.scala 430:60]
node _T_702 = and(io.bus_clk_en, _T_701) @[axi4_to_ahb.scala 430:36]
ahbm_data_clken <= _T_702 @[axi4_to_ahb.scala 430:19]
inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 483:22]
rvclkhdr_6.clock <= clock
rvclkhdr_6.reset <= reset
rvclkhdr_6.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr_6.io.en <= buf_clken @[el2_lib.scala 485:16]
rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 433:11]
inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 483:22]
rvclkhdr_7.clock <= clock
rvclkhdr_7.reset <= reset
rvclkhdr_7.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr_7.io.en <= io.bus_clk_en @[el2_lib.scala 485:16]
rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 434:12]
inst rvclkhdr_8 of rvclkhdr_8 @[el2_lib.scala 483:22]
rvclkhdr_8.clock <= clock
rvclkhdr_8.reset <= reset
rvclkhdr_8.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr_8.io.en <= ahbm_addr_clken @[el2_lib.scala 485:16]
rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 435:17]
inst rvclkhdr_9 of rvclkhdr_9 @[el2_lib.scala 483:22]
rvclkhdr_9.clock <= clock
rvclkhdr_9.reset <= reset
rvclkhdr_9.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr_9.io.en <= ahbm_data_clken @[el2_lib.scala 485:16]
rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 436:17]

783
axi4_to_ahb.v
View File

@ -71,11 +71,25 @@ module axi4_to_ahb(
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [63:0] _RAND_6;
reg [63:0] _RAND_7;
reg [63:0] _RAND_8;
reg [31:0] _RAND_6;
reg [31:0] _RAND_7;
reg [31:0] _RAND_8;
reg [31:0] _RAND_9;
reg [31:0] _RAND_10;
reg [31:0] _RAND_11;
reg [31:0] _RAND_12;
reg [63:0] _RAND_13;
reg [31:0] _RAND_14;
reg [31:0] _RAND_15;
reg [31:0] _RAND_16;
reg [31:0] _RAND_17;
reg [63:0] _RAND_18;
reg [63:0] _RAND_19;
reg [31:0] _RAND_20;
reg [31:0] _RAND_21;
reg [31:0] _RAND_22;
reg [31:0] _RAND_23;
reg [31:0] _RAND_24;
`endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22]
@ -85,27 +99,61 @@ module axi4_to_ahb(
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_1_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_2_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_2_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_3_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_3_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_4_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_4_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_5_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_5_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23]
wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23]
wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23]
wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23]
wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23]
wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23]
wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_5_io_clk; // @[el2_lib.scala 508:23]
wire rvclkhdr_5_io_en; // @[el2_lib.scala 508:23]
wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 508:23]
wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_6_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_6_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_7_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_7_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_8_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_8_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_9_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_9_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 483:22]
reg [2:0] buf_state; // @[axi4_to_ahb.scala 62:26]
reg [2:0] buf_nxtstate; // @[axi4_to_ahb.scala 63:29]
wire wrbuf_en = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 183:30]
wire _T = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 183:30]
wire _T_63 = 3'h0 == buf_state; // @[Conditional.scala 37:30]
wire _T_115 = 3'h1 == buf_state; // @[Conditional.scala 37:30]
wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 153:22 axi4_to_ahb.scala 434:12]
reg ahb_hready_q; // @[axi4_to_ahb.scala 413:12]
reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 416:12]
wire _T_129 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 244:59]
wire _T_130 = ahb_hready_q & _T_129; // @[axi4_to_ahb.scala 244:37]
wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 154:27 axi4_to_ahb.scala 435:17]
reg ahb_hwrite_q; // @[axi4_to_ahb.scala 419:12]
wire _T_131 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 244:73]
wire _T_132 = _T_130 & _T_131; // @[axi4_to_ahb.scala 244:71]
wire _T_133 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 244:104]
wire _T_134 = _T_132 & _T_133; // @[axi4_to_ahb.scala 244:88]
wire _T_145 = 3'h6 == buf_state; // @[Conditional.scala 37:30]
reg ahb_hresp_q; // @[axi4_to_ahb.scala 422:12]
wire _T_146 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 252:39]
wire _T_147 = ahb_hready_q & _T_146; // @[axi4_to_ahb.scala 252:37]
wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 83:21 axi4_to_ahb.scala 216:11]
reg wrbuf_vld; // @[Reg.scala 27:20]
reg wrbuf_data_vld; // @[Reg.scala 27:20]
reg wrbuf_vld; // @[axi4_to_ahb.scala 352:48]
reg wrbuf_data_vld; // @[axi4_to_ahb.scala 353:48]
wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 193:27]
wire master_valid = wr_cmd_vld | io_axi_arvalid; // @[axi4_to_ahb.scala 194:30]
wire [1:0] _T_28 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 196:20]
@ -113,24 +161,101 @@ module axi4_to_ahb(
wire _T_149 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 252:89]
wire _T_150 = master_valid & _T_149; // @[axi4_to_ahb.scala 252:70]
wire _T_151 = ~_T_150; // @[axi4_to_ahb.scala 252:55]
wire wrbuf_data_en = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 184:34]
wire _T_152 = _T_147 & _T_151; // @[axi4_to_ahb.scala 252:53]
wire _T_180 = 3'h7 == buf_state; // @[Conditional.scala 37:30]
wire _T_191 = 3'h3 == buf_state; // @[Conditional.scala 37:30]
wire _T_193 = 3'h2 == buf_state; // @[Conditional.scala 37:30]
wire _T_286 = 3'h4 == buf_state; // @[Conditional.scala 37:30]
reg cmd_doneQ; // @[axi4_to_ahb.scala 404:12]
wire _T_289 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 298:35]
wire _T_290 = _T_289 | ahb_hresp_q; // @[axi4_to_ahb.scala 298:51]
wire _T_292 = _T_290 & _T_146; // @[axi4_to_ahb.scala 298:66]
wire slave_ready = io_axi_bready & io_axi_rready; // @[axi4_to_ahb.scala 211:32]
wire _T_293 = _T_292 & slave_ready; // @[axi4_to_ahb.scala 298:81]
wire _GEN_4 = _T_286 & _T_293; // @[Conditional.scala 39:67]
wire _GEN_26 = _T_193 ? 1'h0 : _GEN_4; // @[Conditional.scala 39:67]
wire _GEN_45 = _T_191 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67]
wire _GEN_62 = _T_180 ? 1'h0 : _GEN_45; // @[Conditional.scala 39:67]
wire _GEN_66 = _T_145 ? _T_152 : _GEN_62; // @[Conditional.scala 39:67]
wire _GEN_86 = _T_115 ? _T_134 : _GEN_66; // @[Conditional.scala 39:67]
wire master_ready = _T_63 | _GEN_86; // @[Conditional.scala 40:58]
wire wrbuf_en = _T & master_ready; // @[axi4_to_ahb.scala 183:47]
wire _T_2 = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 184:34]
wire wrbuf_data_en = _T_2 & master_ready; // @[axi4_to_ahb.scala 184:50]
wire _T_4 = master_valid & master_ready; // @[axi4_to_ahb.scala 185:34]
wire wrbuf_cmd_sent = _T_4 & _T_149; // @[axi4_to_ahb.scala 185:49]
wire _T_8 = ~wrbuf_en; // @[axi4_to_ahb.scala 186:33]
wire wrbuf_rst = _T_150 & _T_8; // @[axi4_to_ahb.scala 186:31]
wire _T_11 = wrbuf_vld & _T_151; // @[axi4_to_ahb.scala 188:33]
wire _T_15 = wrbuf_data_vld & _T_151; // @[axi4_to_ahb.scala 189:37]
reg [31:0] wrbuf_addr; // @[Reg.scala 27:20]
wire wrbuf_rst = wrbuf_cmd_sent & _T_8; // @[axi4_to_ahb.scala 186:31]
wire _T_10 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 188:35]
wire _T_11 = wrbuf_vld & _T_10; // @[axi4_to_ahb.scala 188:33]
wire _T_12 = ~_T_11; // @[axi4_to_ahb.scala 188:21]
wire _T_15 = wrbuf_data_vld & _T_10; // @[axi4_to_ahb.scala 189:37]
wire _T_16 = ~_T_15; // @[axi4_to_ahb.scala 189:20]
wire _T_19 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 190:21]
reg wrbuf_tag; // @[Reg.scala 27:20]
reg [31:0] wrbuf_addr; // @[el2_lib.scala 514:16]
wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_araddr; // @[axi4_to_ahb.scala 197:21]
reg [2:0] wrbuf_size; // @[Reg.scala 27:20]
wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_arsize; // @[axi4_to_ahb.scala 198:21]
reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20]
reg [63:0] wrbuf_data; // @[Reg.scala 27:20]
wire buf_clk = rvclkhdr_2_io_l1clk; // @[axi4_to_ahb.scala 151:21 axi4_to_ahb.scala 433:11]
reg [63:0] buf_data; // @[Reg.scala 27:20]
wire ahbm_data_clk = rvclkhdr_5_io_l1clk; // @[axi4_to_ahb.scala 155:27 axi4_to_ahb.scala 436:17]
reg [63:0] wrbuf_data; // @[el2_lib.scala 514:16]
wire _T_161 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 255:37]
wire _T_194 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 287:33]
wire _T_197 = _T_194 & _T_129; // @[axi4_to_ahb.scala 287:48]
wire _GEN_15 = _T_286 & _T_197; // @[Conditional.scala 39:67]
wire _GEN_19 = _T_193 ? _T_197 : _GEN_15; // @[Conditional.scala 39:67]
wire _GEN_40 = _T_191 ? 1'h0 : _GEN_19; // @[Conditional.scala 39:67]
wire _GEN_59 = _T_180 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67]
wire _GEN_79 = _T_145 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67]
wire _GEN_95 = _T_115 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67]
wire trxn_done = _T_63 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58]
wire _T_449 = 3'h5 == buf_state; // @[Conditional.scala 37:30]
wire _GEN_1 = _T_449 & slave_ready; // @[Conditional.scala 39:67]
wire _GEN_3 = _T_286 ? _T_290 : _GEN_1; // @[Conditional.scala 39:67]
wire _GEN_20 = _T_193 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67]
wire _GEN_35 = _T_191 ? _T_161 : _GEN_20; // @[Conditional.scala 39:67]
wire _GEN_51 = _T_180 ? _T_132 : _GEN_35; // @[Conditional.scala 39:67]
wire _GEN_69 = _T_145 ? _T_161 : _GEN_51; // @[Conditional.scala 39:67]
wire _GEN_83 = _T_115 ? _T_132 : _GEN_69; // @[Conditional.scala 39:67]
wire buf_state_en = _T_63 ? _T_4 : _GEN_83; // @[Conditional.scala 40:58]
wire _T_163 = buf_state_en & _T_146; // @[axi4_to_ahb.scala 259:39]
wire _T_366 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 308:55]
wire _T_367 = buf_state_en & _T_366; // @[axi4_to_ahb.scala 308:39]
wire _GEN_14 = _T_286 ? _T_367 : _T_449; // @[Conditional.scala 39:67]
wire _GEN_33 = _T_193 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67]
wire _GEN_49 = _T_191 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67]
wire _GEN_52 = _T_180 ? buf_state_en : _GEN_49; // @[Conditional.scala 39:67]
wire _GEN_73 = _T_145 ? _T_163 : _GEN_52; // @[Conditional.scala 39:67]
wire _GEN_94 = _T_115 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67]
wire slave_valid_pre = _T_63 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58]
wire _T_39 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 203:32]
wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 151:21 axi4_to_ahb.scala 433:11]
reg slvbuf_write; // @[Reg.scala 27:20]
wire [1:0] _T_601 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 345:23]
reg slvbuf_error; // @[Reg.scala 27:20]
wire [1:0] _T_603 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_604 = _T_603 & 2'h2; // @[axi4_to_ahb.scala 345:88]
wire [3:0] slave_opc = {_T_601,_T_604}; // @[Cat.scala 29:58]
wire [1:0] _T_44 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 204:49]
reg slvbuf_tag; // @[Reg.scala 27:20]
wire _T_49 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 207:65]
reg [31:0] last_bus_addr; // @[Reg.scala 27:20]
wire [63:0] _T_608 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58]
wire _T_609 = buf_state == 3'h5; // @[axi4_to_ahb.scala 346:91]
reg [63:0] buf_data; // @[el2_lib.scala 514:16]
wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 155:27 axi4_to_ahb.scala 436:17]
reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 425:12]
wire _T_60 = wrbuf_en | wrbuf_data_en; // @[axi4_to_ahb.scala 214:74]
wire [63:0] _T_612 = _T_609 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 346:79]
wire _T_60 = _T | _T_2; // @[axi4_to_ahb.scala 214:74]
wire _GEN_8 = _T_286 & _T_149; // @[Conditional.scala 39:67]
wire _GEN_29 = _T_193 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67]
wire _GEN_46 = _T_191 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67]
wire _GEN_63 = _T_180 ? 1'h0 : _GEN_46; // @[Conditional.scala 39:67]
wire _GEN_81 = _T_145 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67]
wire _GEN_97 = _T_115 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67]
wire buf_write_in = _T_63 ? _T_149 : _GEN_97; // @[Conditional.scala 40:58]
wire _T_69 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 230:54]
wire buf_data_wr_en = master_valid & _T_69; // @[axi4_to_ahb.scala 230:38]
wire _T_70 = buf_state_en & _T_69; // @[axi4_to_ahb.scala 230:38]
wire [2:0] _T_100 = wrbuf_byteen[7] ? 3'h7 : 3'h0; // @[Mux.scala 98:16]
wire [2:0] _T_101 = wrbuf_byteen[6] ? 3'h6 : _T_100; // @[Mux.scala 98:16]
wire [2:0] _T_102 = wrbuf_byteen[5] ? 3'h5 : _T_101; // @[Mux.scala 98:16]
@ -139,10 +264,111 @@ module axi4_to_ahb(
wire [2:0] _T_105 = wrbuf_byteen[2] ? 3'h2 : _T_104; // @[Mux.scala 98:16]
wire [2:0] _T_106 = wrbuf_byteen[1] ? 3'h1 : _T_105; // @[Mux.scala 98:16]
wire [2:0] _T_107 = wrbuf_byteen[0] ? 3'h0 : _T_106; // @[Mux.scala 98:16]
wire [2:0] buf_cmd_byte_ptr = _T_149 ? _T_107 : master_addr[2:0]; // @[axi4_to_ahb.scala 233:30]
wire [1:0] _T_113 = master_valid ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [2:0] _T_109 = buf_write_in ? _T_107 : master_addr[2:0]; // @[axi4_to_ahb.scala 233:30]
wire _T_110 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 235:51]
wire _T_135 = master_ready & master_valid; // @[axi4_to_ahb.scala 246:33]
wire _T_168 = _T_135 & _T_133; // @[axi4_to_ahb.scala 261:48]
wire _T_169 = _T_168 & buf_state_en; // @[axi4_to_ahb.scala 261:79]
wire _T_357 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 306:33]
wire _T_359 = _T_357 & _T_69; // @[axi4_to_ahb.scala 306:48]
wire _GEN_12 = _T_286 & _T_359; // @[Conditional.scala 39:67]
wire _GEN_32 = _T_193 ? 1'h0 : _GEN_12; // @[Conditional.scala 39:67]
wire _GEN_48 = _T_191 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67]
wire _GEN_65 = _T_180 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67]
wire _GEN_75 = _T_145 ? _T_169 : _GEN_65; // @[Conditional.scala 39:67]
wire _GEN_88 = _T_115 ? _T_135 : _GEN_75; // @[Conditional.scala 39:67]
wire bypass_en = _T_63 ? buf_state_en : _GEN_88; // @[Conditional.scala 40:58]
wire [1:0] _T_113 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_114 = _T_113 & 2'h2; // @[axi4_to_ahb.scala 236:45]
wire _T_117 = master_opc == 3'h0; // @[axi4_to_ahb.scala 240:61]
reg [31:0] buf_addr; // @[Reg.scala 27:20]
wire _T_118 = master_valid & _T_117; // @[axi4_to_ahb.scala 240:41]
wire _T_126 = ~master_valid; // @[axi4_to_ahb.scala 242:34]
wire _T_127 = buf_state_en & _T_126; // @[axi4_to_ahb.scala 242:32]
reg [31:0] buf_addr; // @[el2_lib.scala 514:16]
wire [2:0] _T_139 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 247:30]
wire _T_140 = ~buf_state_en; // @[axi4_to_ahb.scala 248:44]
wire _T_141 = _T_140 | bypass_en; // @[axi4_to_ahb.scala 248:58]
wire [1:0] _T_143 = _T_141 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_144 = 2'h2 & _T_143; // @[axi4_to_ahb.scala 248:32]
wire _T_156 = _T_4 & _T_117; // @[axi4_to_ahb.scala 253:49]
wire _T_308 = _T_69 | _T_110; // @[axi4_to_ahb.scala 303:62]
wire _T_309 = buf_state_en & _T_308; // @[axi4_to_ahb.scala 303:33]
wire _GEN_9 = _T_286 & _T_309; // @[Conditional.scala 39:67]
wire _GEN_30 = _T_193 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67]
wire _GEN_47 = _T_191 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67]
wire _GEN_64 = _T_180 ? 1'h0 : _GEN_47; // @[Conditional.scala 39:67]
wire _GEN_67 = _T_145 ? _T_156 : _GEN_64; // @[Conditional.scala 39:67]
wire _GEN_87 = _T_115 ? master_ready : _GEN_67; // @[Conditional.scala 39:67]
wire buf_wr_en = _T_63 ? buf_state_en : _GEN_87; // @[Conditional.scala 40:58]
wire _T_174 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 263:59]
wire _T_175 = _T_174 & buf_state_en; // @[axi4_to_ahb.scala 263:74]
wire _T_176 = ~_T_175; // @[axi4_to_ahb.scala 263:43]
wire [1:0] _T_178 = _T_176 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_179 = 2'h2 & _T_178; // @[axi4_to_ahb.scala 263:32]
wire [1:0] _T_189 = _T_140 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_190 = 2'h2 & _T_189; // @[axi4_to_ahb.scala 273:37]
reg [2:0] buf_cmd_byte_ptrQ; // @[Reg.scala 27:20]
wire [2:0] _T_236 = trxn_done ? 3'h0 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 291:30]
wire _T_356 = ahb_hresp_q | _T_130; // @[axi4_to_ahb.scala 305:32]
wire _GEN_11 = _T_286 & _T_356; // @[Conditional.scala 39:67]
wire _GEN_24 = _T_193 ? trxn_done : _GEN_11; // @[Conditional.scala 39:67]
wire _GEN_43 = _T_191 ? 1'h0 : _GEN_24; // @[Conditional.scala 39:67]
wire _GEN_61 = _T_180 ? 1'h0 : _GEN_43; // @[Conditional.scala 39:67]
wire _GEN_74 = _T_145 ? _T_127 : _GEN_61; // @[Conditional.scala 39:67]
wire _GEN_84 = _T_115 ? _T_127 : _GEN_74; // @[Conditional.scala 39:67]
wire cmd_done = _T_63 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58]
wire _T_281 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 293:43]
wire _T_282 = ~_T_281; // @[axi4_to_ahb.scala 293:32]
wire [1:0] _T_284 = _T_282 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_285 = _T_284 & 2'h2; // @[axi4_to_ahb.scala 293:57]
wire _T_294 = ~slave_ready; // @[axi4_to_ahb.scala 299:42]
wire _T_295 = ahb_hresp_q | _T_294; // @[axi4_to_ahb.scala 299:40]
wire _T_362 = _T_282 | bypass_en; // @[axi4_to_ahb.scala 307:57]
wire [1:0] _T_364 = _T_362 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_365 = _T_364 & 2'h2; // @[axi4_to_ahb.scala 307:71]
wire _T_372 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 310:40]
wire [2:0] _T_448 = bypass_en ? _T_107 : _T_236; // @[axi4_to_ahb.scala 313:30]
wire _GEN_6 = _T_286 & ahb_hresp_q; // @[Conditional.scala 39:67]
wire _GEN_7 = _T_286 ? buf_state_en : _T_449; // @[Conditional.scala 39:67]
wire _GEN_10 = _T_286 & buf_wr_en; // @[Conditional.scala 39:67]
wire [1:0] _GEN_13 = _T_286 ? _T_365 : 2'h0; // @[Conditional.scala 39:67]
wire _GEN_16 = _T_286 & _T_372; // @[Conditional.scala 39:67]
wire [2:0] _GEN_17 = _T_286 ? _T_448 : 3'h0; // @[Conditional.scala 39:67]
wire _GEN_21 = _T_193 ? buf_state_en : _GEN_16; // @[Conditional.scala 39:67]
wire _GEN_22 = _T_193 & buf_state_en; // @[Conditional.scala 39:67]
wire [2:0] _GEN_23 = _T_193 ? _T_236 : _GEN_17; // @[Conditional.scala 39:67]
wire [1:0] _GEN_25 = _T_193 ? _T_285 : _GEN_13; // @[Conditional.scala 39:67]
wire _GEN_28 = _T_193 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67]
wire _GEN_31 = _T_193 ? 1'h0 : _GEN_10; // @[Conditional.scala 39:67]
wire _GEN_36 = _T_191 ? buf_state_en : _GEN_31; // @[Conditional.scala 39:67]
wire _GEN_38 = _T_191 ? buf_state_en : _GEN_28; // @[Conditional.scala 39:67]
wire _GEN_39 = _T_191 ? buf_state_en : _GEN_22; // @[Conditional.scala 39:67]
wire _GEN_41 = _T_191 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67]
wire [2:0] _GEN_42 = _T_191 ? 3'h0 : _GEN_23; // @[Conditional.scala 39:67]
wire [1:0] _GEN_44 = _T_191 ? 2'h0 : _GEN_25; // @[Conditional.scala 39:67]
wire _GEN_53 = _T_180 ? buf_state_en : _GEN_39; // @[Conditional.scala 39:67]
wire [2:0] _GEN_54 = _T_180 ? buf_addr[2:0] : _GEN_42; // @[Conditional.scala 39:67]
wire [1:0] _GEN_55 = _T_180 ? _T_190 : _GEN_44; // @[Conditional.scala 39:67]
wire _GEN_56 = _T_180 ? 1'h0 : _GEN_36; // @[Conditional.scala 39:67]
wire _GEN_58 = _T_180 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67]
wire _GEN_60 = _T_180 ? 1'h0 : _GEN_41; // @[Conditional.scala 39:67]
wire _GEN_70 = _T_145 ? buf_state_en : _GEN_56; // @[Conditional.scala 39:67]
wire _GEN_72 = _T_145 ? buf_state_en : _GEN_58; // @[Conditional.scala 39:67]
wire [2:0] _GEN_76 = _T_145 ? _T_139 : _GEN_54; // @[Conditional.scala 39:67]
wire [1:0] _GEN_77 = _T_145 ? _T_179 : _GEN_55; // @[Conditional.scala 39:67]
wire _GEN_78 = _T_145 ? buf_wr_en : _GEN_53; // @[Conditional.scala 39:67]
wire _GEN_80 = _T_145 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67]
wire _GEN_85 = _T_115 ? buf_state_en : _GEN_78; // @[Conditional.scala 39:67]
wire [2:0] _GEN_89 = _T_115 ? _T_139 : _GEN_76; // @[Conditional.scala 39:67]
wire [1:0] _GEN_90 = _T_115 ? _T_144 : _GEN_77; // @[Conditional.scala 39:67]
wire _GEN_91 = _T_115 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67]
wire _GEN_93 = _T_115 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67]
wire _GEN_96 = _T_115 ? 1'h0 : _GEN_80; // @[Conditional.scala 39:67]
wire buf_data_wr_en = _T_63 ? _T_70 : _GEN_91; // @[Conditional.scala 40:58]
wire buf_cmd_byte_ptr_en = _T_63 ? buf_state_en : _GEN_96; // @[Conditional.scala 40:58]
wire [2:0] buf_cmd_byte_ptr = _T_63 ? _T_109 : _GEN_89; // @[Conditional.scala 40:58]
wire slvbuf_wr_en = _T_63 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58]
wire slvbuf_error_en = _T_63 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58]
wire _T_540 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 331:24]
wire _T_541 = _T_117 | _T_540; // @[axi4_to_ahb.scala 330:51]
wire _T_543 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 331:57]
@ -168,6 +394,7 @@ module axi4_to_ahb(
wire _T_452 = buf_aligned_in & _T_149; // @[axi4_to_ahb.scala 325:55]
wire [2:0] _T_489 = _T_452 ? 3'h0 : master_addr[2:0]; // @[axi4_to_ahb.scala 325:38]
wire [34:0] _T_490 = {master_addr,_T_489}; // @[Cat.scala 29:58]
wire _T_493 = buf_state == 3'h3; // @[axi4_to_ahb.scala 328:33]
wire _T_499 = buf_aligned_in & _T_549; // @[axi4_to_ahb.scala 329:38]
wire _T_502 = _T_499 & _T_149; // @[axi4_to_ahb.scala 329:72]
wire [1:0] _T_536 = _T_502 ? 2'h0 : master_size[1:0]; // @[axi4_to_ahb.scala 329:21]
@ -180,12 +407,22 @@ module axi4_to_ahb(
wire _T_593 = ~io_axi_arprot[2]; // @[axi4_to_ahb.scala 340:33]
wire [1:0] _T_594 = {1'h1,_T_593}; // @[Cat.scala 29:58]
reg buf_write; // @[Reg.scala 27:20]
wire [31:0] buf_addr_in = _T_490[31:0]; // @[axi4_to_ahb.scala 325:15]
wire _T_652 = master_valid & io_bus_clk_en; // @[axi4_to_ahb.scala 379:61]
wire _T_664 = buf_data_wr_en & io_bus_clk_en; // @[axi4_to_ahb.scala 391:66]
wire _T_688 = master_valid | io_clk_override; // @[axi4_to_ahb.scala 428:58]
wire _T_691 = io_ahb_hready & io_ahb_htrans[1]; // @[axi4_to_ahb.scala 429:54]
wire _T_692 = _T_691 | io_clk_override; // @[axi4_to_ahb.scala 429:74]
wire _T_616 = io_ahb_htrans != 2'h0; // @[axi4_to_ahb.scala 349:40]
wire _T_617 = _T_616 & io_ahb_hready; // @[axi4_to_ahb.scala 349:52]
wire last_addr_en = _T_617 & io_ahb_hwrite; // @[axi4_to_ahb.scala 349:68]
wire _T_620 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 352:52]
wire _T_621 = ~wrbuf_rst; // @[axi4_to_ahb.scala 352:88]
wire _T_625 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 353:52]
wire [2:0] _T_646 = buf_state_en ? buf_nxtstate : buf_state; // @[axi4_to_ahb.scala 369:16]
reg [2:0] _T_649; // @[axi4_to_ahb.scala 369:12]
reg buf_tag; // @[Reg.scala 27:20]
wire _T_680 = ~slave_valid_pre; // @[axi4_to_ahb.scala 404:52]
wire _T_693 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 428:43]
wire _T_694 = _T_693 | io_clk_override; // @[axi4_to_ahb.scala 428:58]
wire _T_697 = io_ahb_hready & io_ahb_htrans[1]; // @[axi4_to_ahb.scala 429:54]
wire _T_698 = _T_697 | io_clk_override; // @[axi4_to_ahb.scala 429:74]
wire _T_700 = buf_state != 3'h0; // @[axi4_to_ahb.scala 430:50]
wire _T_701 = _T_700 | io_clk_override; // @[axi4_to_ahb.scala 430:60]
rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk),
@ -198,48 +435,72 @@ module axi4_to_ahb(
.io_en(rvclkhdr_1_io_en),
.io_scan_mode(rvclkhdr_1_io_scan_mode)
);
rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 483:22]
rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23]
.io_l1clk(rvclkhdr_2_io_l1clk),
.io_clk(rvclkhdr_2_io_clk),
.io_en(rvclkhdr_2_io_en),
.io_scan_mode(rvclkhdr_2_io_scan_mode)
);
rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 483:22]
rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23]
.io_l1clk(rvclkhdr_3_io_l1clk),
.io_clk(rvclkhdr_3_io_clk),
.io_en(rvclkhdr_3_io_en),
.io_scan_mode(rvclkhdr_3_io_scan_mode)
);
rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 483:22]
rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23]
.io_l1clk(rvclkhdr_4_io_l1clk),
.io_clk(rvclkhdr_4_io_clk),
.io_en(rvclkhdr_4_io_en),
.io_scan_mode(rvclkhdr_4_io_scan_mode)
);
rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 483:22]
rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 508:23]
.io_l1clk(rvclkhdr_5_io_l1clk),
.io_clk(rvclkhdr_5_io_clk),
.io_en(rvclkhdr_5_io_en),
.io_scan_mode(rvclkhdr_5_io_scan_mode)
);
assign io_axi_awready = ~_T_11; // @[axi4_to_ahb.scala 188:18]
assign io_axi_wready = ~_T_15; // @[axi4_to_ahb.scala 189:17]
assign io_axi_bvalid = 1'h0; // @[axi4_to_ahb.scala 203:17]
assign io_axi_bresp = 2'h0; // @[axi4_to_ahb.scala 204:16]
assign io_axi_bid = 1'h0; // @[axi4_to_ahb.scala 205:14]
assign io_axi_arready = ~wr_cmd_vld; // @[axi4_to_ahb.scala 190:18]
assign io_axi_rvalid = 1'h0; // @[axi4_to_ahb.scala 207:17]
assign io_axi_rid = 1'h0; // @[axi4_to_ahb.scala 209:14]
assign io_axi_rdata = ahb_hrdata_q; // @[axi4_to_ahb.scala 210:16]
assign io_axi_rresp = 2'h0; // @[axi4_to_ahb.scala 208:16]
rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_6_io_l1clk),
.io_clk(rvclkhdr_6_io_clk),
.io_en(rvclkhdr_6_io_en),
.io_scan_mode(rvclkhdr_6_io_scan_mode)
);
rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_7_io_l1clk),
.io_clk(rvclkhdr_7_io_clk),
.io_en(rvclkhdr_7_io_en),
.io_scan_mode(rvclkhdr_7_io_scan_mode)
);
rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_8_io_l1clk),
.io_clk(rvclkhdr_8_io_clk),
.io_en(rvclkhdr_8_io_en),
.io_scan_mode(rvclkhdr_8_io_scan_mode)
);
rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_9_io_l1clk),
.io_clk(rvclkhdr_9_io_clk),
.io_en(rvclkhdr_9_io_en),
.io_scan_mode(rvclkhdr_9_io_scan_mode)
);
assign io_axi_awready = _T_12 & master_ready; // @[axi4_to_ahb.scala 188:18]
assign io_axi_wready = _T_16 & master_ready; // @[axi4_to_ahb.scala 189:17]
assign io_axi_bvalid = _T_39 & slave_opc[3]; // @[axi4_to_ahb.scala 203:17]
assign io_axi_bresp = slave_opc[0] ? 2'h2 : _T_44; // @[axi4_to_ahb.scala 204:16]
assign io_axi_bid = slvbuf_tag; // @[axi4_to_ahb.scala 205:14]
assign io_axi_arready = _T_19 & master_ready; // @[axi4_to_ahb.scala 190:18]
assign io_axi_rvalid = _T_39 & _T_49; // @[axi4_to_ahb.scala 207:17]
assign io_axi_rid = slvbuf_tag; // @[axi4_to_ahb.scala 209:14]
assign io_axi_rdata = slvbuf_error ? _T_608 : _T_612; // @[axi4_to_ahb.scala 210:16]
assign io_axi_rresp = slave_opc[0] ? 2'h2 : _T_44; // @[axi4_to_ahb.scala 208:16]
assign io_axi_rlast = 1'h1; // @[axi4_to_ahb.scala 191:16]
assign io_ahb_haddr = master_valid ? _T_575 : _T_578; // @[axi4_to_ahb.scala 335:16]
assign io_ahb_haddr = bypass_en ? _T_575 : _T_578; // @[axi4_to_ahb.scala 335:16]
assign io_ahb_hburst = 3'h0; // @[axi4_to_ahb.scala 338:17]
assign io_ahb_hmastlock = 1'h0; // @[axi4_to_ahb.scala 339:20]
assign io_ahb_hprot = {{2'd0}, _T_594}; // @[axi4_to_ahb.scala 340:16]
assign io_ahb_hsize = master_valid ? _T_585 : 3'h0; // @[axi4_to_ahb.scala 336:16]
assign io_ahb_htrans = _T_113 & 2'h2; // @[axi4_to_ahb.scala 220:17 axi4_to_ahb.scala 236:21 axi4_to_ahb.scala 248:21 axi4_to_ahb.scala 263:21 axi4_to_ahb.scala 273:21 axi4_to_ahb.scala 293:21 axi4_to_ahb.scala 307:21]
assign io_ahb_hwrite = master_valid ? _T_149 : buf_write; // @[axi4_to_ahb.scala 341:17]
assign io_ahb_hsize = bypass_en ? _T_585 : 3'h0; // @[axi4_to_ahb.scala 336:16]
assign io_ahb_htrans = _T_63 ? _T_114 : _GEN_90; // @[axi4_to_ahb.scala 220:17 axi4_to_ahb.scala 236:21 axi4_to_ahb.scala 248:21 axi4_to_ahb.scala 263:21 axi4_to_ahb.scala 273:21 axi4_to_ahb.scala 293:21 axi4_to_ahb.scala 307:21]
assign io_ahb_hwrite = bypass_en ? _T_149 : buf_write; // @[axi4_to_ahb.scala 341:17]
assign io_ahb_hwdata = buf_data; // @[axi4_to_ahb.scala 342:17]
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16]
@ -247,18 +508,30 @@ module axi4_to_ahb(
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_1_io_en = io_bus_clk_en & _T_60; // @[el2_lib.scala 485:16]
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_2_io_en = io_bus_clk_en & _T_688; // @[el2_lib.scala 485:16]
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_3_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16]
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_4_io_en = io_bus_clk_en & _T_692; // @[el2_lib.scala 485:16]
assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_5_io_en = io_bus_clk_en & io_clk_override; // @[el2_lib.scala 485:16]
assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18]
assign rvclkhdr_2_io_en = _T & master_ready; // @[el2_lib.scala 511:17]
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18]
assign rvclkhdr_3_io_en = _T_2 & master_ready; // @[el2_lib.scala 511:17]
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18]
assign rvclkhdr_4_io_en = buf_wr_en & io_bus_clk_en; // @[el2_lib.scala 511:17]
assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 510:18]
assign rvclkhdr_5_io_en = buf_data_wr_en & io_bus_clk_en; // @[el2_lib.scala 511:17]
assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_6_io_en = io_bus_clk_en & _T_694; // @[el2_lib.scala 485:16]
assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_7_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16]
assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_8_io_en = io_bus_clk_en & _T_698; // @[el2_lib.scala 485:16]
assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_9_io_en = io_bus_clk_en & _T_701; // @[el2_lib.scala 485:16]
assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
@ -295,37 +568,86 @@ initial begin
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
buf_nxtstate = _RAND_0[2:0];
buf_state = _RAND_0[2:0];
_RAND_1 = {1{`RANDOM}};
wrbuf_vld = _RAND_1[0:0];
buf_nxtstate = _RAND_1[2:0];
_RAND_2 = {1{`RANDOM}};
wrbuf_data_vld = _RAND_2[0:0];
ahb_hready_q = _RAND_2[0:0];
_RAND_3 = {1{`RANDOM}};
wrbuf_addr = _RAND_3[31:0];
ahb_htrans_q = _RAND_3[1:0];
_RAND_4 = {1{`RANDOM}};
wrbuf_size = _RAND_4[2:0];
ahb_hwrite_q = _RAND_4[0:0];
_RAND_5 = {1{`RANDOM}};
wrbuf_byteen = _RAND_5[7:0];
_RAND_6 = {2{`RANDOM}};
wrbuf_data = _RAND_6[63:0];
_RAND_7 = {2{`RANDOM}};
buf_data = _RAND_7[63:0];
_RAND_8 = {2{`RANDOM}};
ahb_hrdata_q = _RAND_8[63:0];
ahb_hresp_q = _RAND_5[0:0];
_RAND_6 = {1{`RANDOM}};
wrbuf_vld = _RAND_6[0:0];
_RAND_7 = {1{`RANDOM}};
wrbuf_data_vld = _RAND_7[0:0];
_RAND_8 = {1{`RANDOM}};
cmd_doneQ = _RAND_8[0:0];
_RAND_9 = {1{`RANDOM}};
buf_addr = _RAND_9[31:0];
wrbuf_tag = _RAND_9[0:0];
_RAND_10 = {1{`RANDOM}};
buf_write = _RAND_10[0:0];
wrbuf_addr = _RAND_10[31:0];
_RAND_11 = {1{`RANDOM}};
wrbuf_size = _RAND_11[2:0];
_RAND_12 = {1{`RANDOM}};
wrbuf_byteen = _RAND_12[7:0];
_RAND_13 = {2{`RANDOM}};
wrbuf_data = _RAND_13[63:0];
_RAND_14 = {1{`RANDOM}};
slvbuf_write = _RAND_14[0:0];
_RAND_15 = {1{`RANDOM}};
slvbuf_error = _RAND_15[0:0];
_RAND_16 = {1{`RANDOM}};
slvbuf_tag = _RAND_16[0:0];
_RAND_17 = {1{`RANDOM}};
last_bus_addr = _RAND_17[31:0];
_RAND_18 = {2{`RANDOM}};
buf_data = _RAND_18[63:0];
_RAND_19 = {2{`RANDOM}};
ahb_hrdata_q = _RAND_19[63:0];
_RAND_20 = {1{`RANDOM}};
buf_addr = _RAND_20[31:0];
_RAND_21 = {1{`RANDOM}};
buf_cmd_byte_ptrQ = _RAND_21[2:0];
_RAND_22 = {1{`RANDOM}};
buf_write = _RAND_22[0:0];
_RAND_23 = {1{`RANDOM}};
_T_649 = _RAND_23[2:0];
_RAND_24 = {1{`RANDOM}};
buf_tag = _RAND_24[0:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
buf_state = 3'h0;
end
if (reset) begin
buf_nxtstate = 3'h0;
end
if (reset) begin
ahb_hready_q = 1'h0;
end
if (reset) begin
ahb_htrans_q = 2'h0;
end
if (reset) begin
ahb_hwrite_q = 1'h0;
end
if (reset) begin
ahb_hresp_q = 1'h0;
end
if (reset) begin
wrbuf_vld = 1'h0;
end
if (reset) begin
wrbuf_data_vld = 1'h0;
end
if (reset) begin
cmd_doneQ = 1'h0;
end
if (reset) begin
wrbuf_tag = 1'h0;
end
if (reset) begin
wrbuf_addr = 32'h0;
end
@ -338,6 +660,18 @@ initial begin
if (reset) begin
wrbuf_data = 64'h0;
end
if (reset) begin
slvbuf_write = 1'h0;
end
if (reset) begin
slvbuf_error = 1'h0;
end
if (reset) begin
slvbuf_tag = 1'h0;
end
if (reset) begin
last_bus_addr = 32'h0;
end
if (reset) begin
buf_data = 64'h0;
end
@ -347,42 +681,136 @@ initial begin
if (reset) begin
buf_addr = 32'h0;
end
if (reset) begin
buf_cmd_byte_ptrQ = 3'h0;
end
if (reset) begin
buf_write = 1'h0;
end
if (reset) begin
_T_649 = 3'h0;
end
if (reset) begin
buf_tag = 1'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock or posedge reset) begin
if (reset) begin
buf_state <= 3'h0;
end else begin
buf_state <= _T_649;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
buf_nxtstate <= 3'h0;
end else if (_T_149) begin
end else if (_T_63) begin
if (buf_write_in) begin
buf_nxtstate <= 3'h2;
end else begin
buf_nxtstate <= 3'h1;
end
end else if (_T_115) begin
if (_T_118) begin
buf_nxtstate <= 3'h6;
end else begin
buf_nxtstate <= 3'h3;
end
end else if (_T_145) begin
if (ahb_hresp_q) begin
buf_nxtstate <= 3'h7;
end else if (buf_wr_en) begin
buf_nxtstate <= 3'h6;
end else begin
buf_nxtstate <= 3'h3;
end
end else if (_T_180) begin
buf_nxtstate <= 3'h3;
end else if (_T_191) begin
buf_nxtstate <= 3'h5;
end else if (_T_193) begin
buf_nxtstate <= 3'h4;
end else if (_T_286) begin
if (_T_295) begin
buf_nxtstate <= 3'h5;
end else if (_T_4) begin
if (_T_149) begin
buf_nxtstate <= 3'h2;
end else begin
buf_nxtstate <= 3'h1;
end
end else begin
buf_nxtstate <= 3'h0;
end
end else if (_T_449) begin
buf_nxtstate <= 3'h0;
end
end
always @(posedge ahbm_clk or posedge reset) begin
if (reset) begin
ahb_hready_q <= 1'h0;
end else begin
ahb_hready_q <= io_ahb_hready;
end
end
always @(posedge ahbm_clk or posedge reset) begin
if (reset) begin
ahb_htrans_q <= 2'h0;
end else begin
ahb_htrans_q <= io_ahb_htrans;
end
end
always @(posedge ahbm_addr_clk or posedge reset) begin
if (reset) begin
ahb_hwrite_q <= 1'h0;
end else begin
ahb_hwrite_q <= io_ahb_hwrite;
end
end
always @(posedge ahbm_clk or posedge reset) begin
if (reset) begin
ahb_hresp_q <= 1'h0;
end else begin
ahb_hresp_q <= io_ahb_hresp;
end
end
always @(posedge bus_clk or posedge reset) begin
if (reset) begin
wrbuf_vld <= 1'h0;
end else if (wrbuf_en) begin
wrbuf_vld <= wrbuf_rst;
end else begin
wrbuf_vld <= _T_620 & _T_621;
end
end
always @(posedge bus_clk or posedge reset) begin
if (reset) begin
wrbuf_data_vld <= 1'h0;
end else if (wrbuf_data_en) begin
wrbuf_data_vld <= wrbuf_rst;
end else begin
wrbuf_data_vld <= _T_625 & _T_621;
end
end
always @(posedge clock or posedge reset) begin
always @(posedge ahbm_clk or posedge reset) begin
if (reset) begin
cmd_doneQ <= 1'h0;
end else begin
cmd_doneQ <= _T_281 & _T_680;
end
end
always @(posedge bus_clk or posedge reset) begin
if (reset) begin
wrbuf_tag <= 1'h0;
end else if (wrbuf_en) begin
wrbuf_tag <= io_axi_awid;
end
end
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
if (reset) begin
wrbuf_addr <= 32'h0;
end else if (wrbuf_en) begin
end else begin
wrbuf_addr <= io_axi_awaddr;
end
end
@ -400,17 +828,61 @@ end // initial
wrbuf_byteen <= io_axi_wstrb;
end
end
always @(posedge clock or posedge reset) begin
always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
if (reset) begin
wrbuf_data <= 64'h0;
end else if (wrbuf_data_en) begin
end else begin
wrbuf_data <= io_axi_wdata;
end
end
always @(posedge clock or posedge reset) begin
always @(posedge buf_clk or posedge reset) begin
if (reset) begin
slvbuf_write <= 1'h0;
end else if (slvbuf_wr_en) begin
slvbuf_write <= buf_write;
end
end
always @(posedge ahbm_clk or posedge reset) begin
if (reset) begin
slvbuf_error <= 1'h0;
end else if (slvbuf_error_en) begin
if (_T_63) begin
slvbuf_error <= 1'h0;
end else if (_T_115) begin
slvbuf_error <= 1'h0;
end else if (_T_145) begin
slvbuf_error <= ahb_hresp_q;
end else if (_T_180) begin
slvbuf_error <= 1'h0;
end else if (_T_191) begin
slvbuf_error <= ahb_hresp_q;
end else if (_T_193) begin
slvbuf_error <= 1'h0;
end else begin
slvbuf_error <= _GEN_6;
end
end
end
always @(posedge buf_clk or posedge reset) begin
if (reset) begin
slvbuf_tag <= 1'h0;
end else if (slvbuf_wr_en) begin
slvbuf_tag <= buf_tag;
end
end
always @(posedge ahbm_clk or posedge reset) begin
if (reset) begin
last_bus_addr <= 32'h0;
end else if (last_addr_en) begin
last_bus_addr <= io_ahb_haddr;
end
end
always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin
if (reset) begin
buf_data <= 64'h0;
end else if (_T_664) begin
end else if (_T_493) begin
buf_data <= ahb_hrdata_q;
end else begin
buf_data <= wrbuf_data;
end
end
@ -421,18 +893,127 @@ end // initial
ahb_hrdata_q <= io_ahb_hrdata;
end
end
always @(posedge clock or posedge reset) begin
always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin
if (reset) begin
buf_addr <= 32'h0;
end else if (_T_652) begin
buf_addr <= buf_addr_in;
end else begin
buf_addr <= _T_490[31:0];
end
end
always @(posedge ahbm_clk or posedge reset) begin
if (reset) begin
buf_cmd_byte_ptrQ <= 3'h0;
end else if (buf_cmd_byte_ptr_en) begin
if (_T_63) begin
if (buf_write_in) begin
if (wrbuf_byteen[0]) begin
buf_cmd_byte_ptrQ <= 3'h0;
end else if (wrbuf_byteen[1]) begin
buf_cmd_byte_ptrQ <= 3'h1;
end else if (wrbuf_byteen[2]) begin
buf_cmd_byte_ptrQ <= 3'h2;
end else if (wrbuf_byteen[3]) begin
buf_cmd_byte_ptrQ <= 3'h3;
end else if (wrbuf_byteen[4]) begin
buf_cmd_byte_ptrQ <= 3'h4;
end else if (wrbuf_byteen[5]) begin
buf_cmd_byte_ptrQ <= 3'h5;
end else if (wrbuf_byteen[6]) begin
buf_cmd_byte_ptrQ <= 3'h6;
end else if (wrbuf_byteen[7]) begin
buf_cmd_byte_ptrQ <= 3'h7;
end else begin
buf_cmd_byte_ptrQ <= 3'h0;
end
end else begin
buf_cmd_byte_ptrQ <= master_addr[2:0];
end
end else if (_T_115) begin
if (bypass_en) begin
buf_cmd_byte_ptrQ <= master_addr[2:0];
end else begin
buf_cmd_byte_ptrQ <= buf_addr[2:0];
end
end else if (_T_145) begin
if (bypass_en) begin
buf_cmd_byte_ptrQ <= master_addr[2:0];
end else begin
buf_cmd_byte_ptrQ <= buf_addr[2:0];
end
end else if (_T_180) begin
buf_cmd_byte_ptrQ <= buf_addr[2:0];
end else if (_T_191) begin
buf_cmd_byte_ptrQ <= 3'h0;
end else if (_T_193) begin
if (trxn_done) begin
buf_cmd_byte_ptrQ <= 3'h0;
end
end else if (_T_286) begin
if (bypass_en) begin
if (wrbuf_byteen[0]) begin
buf_cmd_byte_ptrQ <= 3'h0;
end else if (wrbuf_byteen[1]) begin
buf_cmd_byte_ptrQ <= 3'h1;
end else if (wrbuf_byteen[2]) begin
buf_cmd_byte_ptrQ <= 3'h2;
end else if (wrbuf_byteen[3]) begin
buf_cmd_byte_ptrQ <= 3'h3;
end else if (wrbuf_byteen[4]) begin
buf_cmd_byte_ptrQ <= 3'h4;
end else if (wrbuf_byteen[5]) begin
buf_cmd_byte_ptrQ <= 3'h5;
end else if (wrbuf_byteen[6]) begin
buf_cmd_byte_ptrQ <= 3'h6;
end else if (wrbuf_byteen[7]) begin
buf_cmd_byte_ptrQ <= 3'h7;
end else begin
buf_cmd_byte_ptrQ <= 3'h0;
end
end else if (trxn_done) begin
buf_cmd_byte_ptrQ <= 3'h0;
end
end else begin
buf_cmd_byte_ptrQ <= 3'h0;
end
end
end
always @(posedge buf_clk or posedge reset) begin
if (reset) begin
buf_write <= 1'h0;
end else if (master_valid) begin
end else if (buf_wr_en) begin
if (_T_63) begin
buf_write <= _T_149;
end else if (_T_115) begin
buf_write <= 1'h0;
end else if (_T_145) begin
buf_write <= 1'h0;
end else if (_T_180) begin
buf_write <= 1'h0;
end else if (_T_191) begin
buf_write <= 1'h0;
end else if (_T_193) begin
buf_write <= 1'h0;
end else begin
buf_write <= _GEN_8;
end
end
end
always @(posedge ahbm_clk or posedge reset) begin
if (reset) begin
_T_649 <= 3'h0;
end else begin
_T_649 <= _T_646 & 3'h1;
end
end
always @(posedge buf_clk or posedge reset) begin
if (reset) begin
buf_tag <= 1'h0;
end else if (buf_wr_en) begin
if (wr_cmd_vld) begin
buf_tag <= wrbuf_tag;
end else begin
buf_tag <= io_axi_arid;
end
end
end
endmodule

16
src/main/scala/lib/axi4_to_ahb.scala
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@ -349,14 +349,14 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
last_addr_en := (io.ahb_htrans(1, 0) =/= "b0".U) & io.ahb_hready & io.ahb_hwrite
//rvdffsc
wrbuf_vld := withClock(bus_clk) {RegEnable("b1".U & Fill("b1".U.getWidth, wrbuf_rst), 0.U, wrbuf_en.asBool())}
wrbuf_data_vld := withClock(bus_clk) {RegEnable("b1".U & Fill("b1".U.getWidth, wrbuf_rst), 0.U, wrbuf_data_en.asBool())}
wrbuf_vld := withClock(bus_clk) {RegNext(Mux(wrbuf_en.asBool(),1.U,wrbuf_vld) & !wrbuf_rst, 0.U)}
wrbuf_data_vld := withClock(bus_clk) {RegNext(Mux(wrbuf_data_en.asBool(),1.U, wrbuf_data_vld) & !wrbuf_rst, 0.U)}
//rvdffs
wrbuf_tag := withClock(bus_clk) {RegEnable(io.axi_awid(TAG - 1, 0), 0.U, wrbuf_en.asBool())}
wrbuf_size := withClock(bus_clk) {RegEnable(io.axi_awsize(2, 0), 0.U, wrbuf_en.asBool())}
//rvdffe
wrbuf_addr := RegEnable(io.axi_awaddr, 0.U, wrbuf_en.asBool())
wrbuf_data := RegEnable(io.axi_wdata, 0.U, wrbuf_data_en.asBool())
wrbuf_addr := rvdffe(io.axi_awaddr, wrbuf_en.asBool,clock,io.scan_mode)
wrbuf_data := rvdffe(io.axi_wdata, wrbuf_data_en.asBool,clock,io.scan_mode)
//rvdffs
wrbuf_byteen := withClock(bus_clk) {
RegEnable(io.axi_wstrb(7, 0), 0.U, wrbuf_data_en.asBool())
@ -366,7 +366,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
}
//sc
buf_state := withClock(ahbm_clk) {
RegEnable(buf_nxtstate & Fill(buf_nxtstate.getWidth, buf_rst), 0.U, buf_state_en.asBool())
RegNext(Mux(buf_state_en.asBool(),buf_nxtstate,buf_state) & !buf_rst, 0.U)
}
//s
buf_write := withClock(buf_clk) {
@ -376,7 +376,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
RegEnable(buf_tag_in(TAG - 1, 0), 0.U, buf_wr_en.asBool())
}
//e
buf_addr := RegEnable(buf_addr_in(31, 0), 0.U, (buf_wr_en & io.bus_clk_en).asBool)
buf_addr := rvdffe(buf_addr_in(31, 0),(buf_wr_en & io.bus_clk_en).asBool,clock,io.scan_mode)
//s
buf_size := withClock(buf_clk) {
RegEnable(buf_size(1, 0), 0.U, buf_wr_en.asBool())
@ -388,7 +388,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
RegEnable(buf_byteen(7, 0), 0.U, buf_wr_en.asBool())
}
//e
buf_data := RegEnable(buf_data_in(63, 0), 0.U, (buf_data_wr_en & io.bus_clk_en).asBool())
buf_data := rvdffe(buf_data_in(63, 0),(buf_data_wr_en & io.bus_clk_en).asBool(),clock,io.scan_mode)
//s
slvbuf_write := withClock(buf_clk) {
RegEnable(buf_write, 0.U, slvbuf_wr_en.asBool())
@ -401,7 +401,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
}
//sc
cmd_doneQ := withClock(ahbm_clk) {
RegEnable("b1".U & Fill("b1".U.getWidth, cmd_done_rst), 0.U, cmd_done.asBool())
RegNext(Mux(cmd_done.asBool(),1.U,cmd_doneQ) & !cmd_done_rst, 0.U)
}
//rvdffs
buf_cmd_byte_ptrQ := withClock(ahbm_clk) {

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target/scala-2.12/classes/lib/axi4_to_ahb.class
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