Hard-coded values

el2_ifu_iccm_mem.fir

@@ -501,8 +501,10 @@ circuit el2_ifu_iccm_mem :
       _T_371 <= redundant_data1_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
     redundant_data[1] <= _T_371 @[el2_ifu_iccm_mem.scala 100:21]
-    reg iccm_rd_addr_lo_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 102:34]
+    reg iccm_rd_addr_lo_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    iccm_rd_addr_lo_q <= io.iccm_rw_addr @[el2_ifu_iccm_mem.scala 102:34]
+    when UInt<1>("h01") : @[Reg.scala 28:19]
+      iccm_rd_addr_lo_q <= io.iccm_rw_addr @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
     node _T_372 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 103:48]
     reg iccm_rd_addr_hi_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 103:34]
     iccm_rd_addr_hi_q <= _T_372 @[el2_ifu_iccm_mem.scala 103:34]

el2_ifu_iccm_mem.v

@@ -74,8 +74,8 @@ module el2_ifu_iccm_mem(
   reg [11:0] _T_88__T_111_addr_pipe_0;
   wire  _T_1 = io_iccm_wr_size[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 24:43]
   wire [1:0] addr_inc = _T_1 ? 2'h2 : 2'h1; // @[el2_ifu_iccm_mem.scala 24:21]
-  wire [14:0] _GEN_31 = {{13'd0}, addr_inc}; // @[el2_ifu_iccm_mem.scala 25:54]
+  wire [14:0] _GEN_32 = {{13'd0}, addr_inc}; // @[el2_ifu_iccm_mem.scala 25:54]
-  wire [14:0] addr_bank_inc = io_iccm_rw_addr + _GEN_31; // @[el2_ifu_iccm_mem.scala 25:54]
+  wire [14:0] addr_bank_inc = io_iccm_rw_addr + _GEN_32; // @[el2_ifu_iccm_mem.scala 25:54]
   wire [38:0] iccm_bank_wr_data_0 = io_iccm_wr_data[38:0]; // @[el2_ifu_iccm_mem.scala 29:50]
   wire [38:0] iccm_bank_wr_data_1 = io_iccm_wr_data[77:39]; // @[el2_ifu_iccm_mem.scala 30:54]
   wire  _T_10 = io_iccm_rw_addr[2:1] == 2'h0; // @[el2_ifu_iccm_mem.scala 33:100]
@@ -235,7 +235,7 @@ module el2_ifu_iccm_mem(
   wire  redundant_data1_en = _T_356 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 96:121]
   wire  _T_365 = redundant_address_1[0] & _T_1; // @[el2_ifu_iccm_mem.scala 98:104]
   wire  _T_366 = _T_349 | _T_365; // @[el2_ifu_iccm_mem.scala 98:78]
-  reg [14:0] iccm_rd_addr_lo_q; // @[el2_ifu_iccm_mem.scala 102:34]
+  reg [14:0] iccm_rd_addr_lo_q; // @[Reg.scala 27:20]
   reg [1:0] iccm_rd_addr_hi_q; // @[el2_ifu_iccm_mem.scala 103:34]
   wire  _T_373 = iccm_rd_addr_hi_q == 2'h0; // @[el2_ifu_iccm_mem.scala 105:86]
   wire  _T_375 = iccm_rd_addr_hi_q == 2'h1; // @[el2_ifu_iccm_mem.scala 105:86]

src/main/scala/ifu/el2_ifu_iccm_mem.scala

@@ -99,7 +99,7 @@ class el2_ifu_iccm_mem extends Module with el2_lib {
     io.iccm_wr_data(77,39), io.iccm_wr_data(38,0))
   redundant_data(1) := RegEnable(redundant_data1_in, 0.U, redundant_data1_en.asBool)
 
-  val iccm_rd_addr_lo_q = RegNext(io.iccm_rw_addr, 0.U)
+  val iccm_rd_addr_lo_q = RegEnable(io.iccm_rw_addr, 0.U, 1.U.asBool)
   val iccm_rd_addr_hi_q = RegNext(addr_bank_inc(ICCM_BANK_HI-1,1), 0.U)
 
   val iccm_rd_data_pre = Cat(Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_hi_q===i.U)->iccm_bank_dout_fn(i)(31,0))),