clock enable updated

This commit is contained in:
​Laraib Khan 2021-02-02 15:10:04 +05:00
parent 2b0f57e6bf
commit 3de7adb50f
11 changed files with 6082 additions and 5537 deletions

View File

@ -15400,8 +15400,6 @@ circuit lsu :
lsu_raw_fwd_lo_r <= UInt<1>("h00")
wire lsu_raw_fwd_hi_r : UInt<1>
lsu_raw_fwd_hi_r <= UInt<1>("h00")
wire lsu_busm_clken : UInt<1>
lsu_busm_clken <= UInt<1>("h00")
wire lsu_bus_obuf_c1_clken : UInt<1>
lsu_bus_obuf_c1_clken <= UInt<1>("h00")
wire lsu_busreq_r : UInt<1>
@ -15940,8 +15938,8 @@ circuit lsu :
bus_intf.io.clk_override <= io.clk_override @[lsu.scala 315:49]
bus_intf.io.lsu_c1_r_clk <= clkdomain.io.lsu_c1_r_clk @[lsu.scala 316:49]
bus_intf.io.lsu_c2_r_clk <= clkdomain.io.lsu_c2_r_clk @[lsu.scala 317:49]
bus_intf.io.lsu_busm_clken <= lsu_busm_clken @[lsu.scala 318:49]
bus_intf.io.lsu_bus_obuf_c1_clken <= lsu_bus_obuf_c1_clken @[lsu.scala 319:49]
bus_intf.io.lsu_busm_clken <= clkdomain.io.lsu_busm_clken @[lsu.scala 318:49]
bus_intf.io.lsu_bus_obuf_c1_clken <= clkdomain.io.lsu_bus_obuf_c1_clken @[lsu.scala 319:49]
bus_intf.io.lsu_bus_ibuf_c1_clk <= clkdomain.io.lsu_bus_ibuf_c1_clk @[lsu.scala 320:49]
bus_intf.io.lsu_bus_obuf_c1_clk <= clkdomain.io.lsu_bus_obuf_c1_clk @[lsu.scala 321:49]
bus_intf.io.lsu_bus_buf_c1_clk <= clkdomain.io.lsu_bus_buf_c1_clk @[lsu.scala 322:49]

909
lsu.v

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File diff suppressed because it is too large Load Diff

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@ -404,6 +404,3 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
f1_shift_2B := f0val(0) & !f0val(1) & shift_4B
}
object aln_main extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new ifu_aln_ctl()))
}

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@ -56,7 +56,7 @@ class lsu extends Module with RequireAsyncReset with param with lib {
val dma_mem_tag_m = WireInit(0.U(3.W))
val lsu_raw_fwd_lo_r = WireInit(0.U(1.W))
val lsu_raw_fwd_hi_r = WireInit(0.U(1.W))
val lsu_busm_clken = WireInit(0.U(1.W))
// val lsu_busm_clken = WireInit(0.U(1.W))
val lsu_bus_obuf_c1_clken = WireInit(0.U(1.W))
// val lsu_addr_d = WireInit(0.U(32.W))
// val lsu_addr_m = WireInit(0.U(32.W))
@ -315,8 +315,8 @@ class lsu extends Module with RequireAsyncReset with param with lib {
bus_intf.io.clk_override := io.clk_override
bus_intf.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk
bus_intf.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk
bus_intf.io.lsu_busm_clken := lsu_busm_clken
bus_intf.io.lsu_bus_obuf_c1_clken := lsu_bus_obuf_c1_clken
bus_intf.io.lsu_busm_clken := clkdomain.io.lsu_busm_clken
bus_intf.io.lsu_bus_obuf_c1_clken := clkdomain.io.lsu_bus_obuf_c1_clken
bus_intf.io.lsu_bus_ibuf_c1_clk := clkdomain.io.lsu_bus_ibuf_c1_clk
bus_intf.io.lsu_bus_obuf_c1_clk := clkdomain.io.lsu_bus_obuf_c1_clk
bus_intf.io.lsu_bus_buf_c1_clk := clkdomain.io.lsu_bus_buf_c1_clk