diff --git a/axi4_to_ahb.anno.json b/axi4_to_ahb.anno.json
new file mode 100644
index 00000000..5f4d08b6
--- /dev/null
+++ b/axi4_to_ahb.anno.json
@@ -0,0 +1,113 @@
+[
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_bvalid",
+    "sources":[
+      "~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
+      "~axi4_to_ahb|axi4_to_ahb>io_axi_rready",
+      "~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_htrans",
+    "sources":[
+      "~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
+      "~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
+      "~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_wready",
+    "sources":[
+      "~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
+      "~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
+      "~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_hwrite",
+    "sources":[
+      "~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
+      "~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
+      "~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_haddr",
+    "sources":[
+      "~axi4_to_ahb|axi4_to_ahb>io_axi_araddr",
+      "~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
+      "~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
+      "~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_hsize",
+    "sources":[
+      "~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
+      "~axi4_to_ahb|axi4_to_ahb>io_axi_arsize",
+      "~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
+      "~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_awready",
+    "sources":[
+      "~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
+      "~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
+      "~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_arready",
+    "sources":[
+      "~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
+      "~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
+      "~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_rvalid",
+    "sources":[
+      "~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
+      "~axi4_to_ahb|axi4_to_ahb>io_axi_rready",
+      "~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_hprot",
+    "sources":[
+      "~axi4_to_ahb|axi4_to_ahb>io_axi_arprot"
+    ]
+  },
+  {
+    "class":"firrtl.EmitCircuitAnnotation",
+    "emitter":"firrtl.VerilogEmitter"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxResourceAnno",
+    "target":"axi4_to_ahb.TEC_RV_ICG",
+    "resourceId":"/vsrc/TEC_RV_ICG.v"
+  },
+  {
+    "class":"firrtl.options.TargetDirAnnotation",
+    "directory":"."
+  },
+  {
+    "class":"firrtl.options.OutputAnnotationFileAnnotation",
+    "file":"axi4_to_ahb"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
+    "targetDir":"."
+  }
+]
\ No newline at end of file
diff --git a/axi4_to_ahb.fir b/axi4_to_ahb.fir
new file mode 100644
index 00000000..751b4fa9
--- /dev/null
+++ b/axi4_to_ahb.fir
@@ -0,0 +1,1288 @@
+;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
+circuit axi4_to_ahb : 
+  extmodule TEC_RV_ICG : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG @[el2_lib.scala 474:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
+    
+  extmodule TEC_RV_ICG_1 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_1 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_1 @[el2_lib.scala 474:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
+    
+  extmodule TEC_RV_ICG_2 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_2 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_2 @[el2_lib.scala 474:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
+    
+  extmodule TEC_RV_ICG_3 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_3 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_3 @[el2_lib.scala 474:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
+    
+  extmodule TEC_RV_ICG_4 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_4 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_4 @[el2_lib.scala 474:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
+    
+  extmodule TEC_RV_ICG_5 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_5 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_5 @[el2_lib.scala 474:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
+    
+  module axi4_to_ahb : 
+    input clock : Clock
+    input reset : AsyncReset
+    output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awvalid : UInt<1>, flip axi_awid : UInt<1>, flip axi_awaddr : UInt<32>, flip axi_awsize : UInt<3>, flip axi_awprot : UInt<3>, flip axi_wvalid : UInt<1>, flip axi_wdata : UInt<64>, flip axi_wstrb : UInt<8>, flip axi_wlast : UInt<1>, flip axi_bready : UInt<1>, flip axi_arvalid : UInt<1>, flip axi_arid : UInt<1>, flip axi_araddr : UInt<32>, flip axi_arsize : UInt<3>, flip axi_arprot : UInt<3>, flip axi_rready : UInt<1>, flip ahb_hrdata : UInt<64>, flip ahb_hready : UInt<1>, flip ahb_hresp : UInt<1>, axi_awready : UInt<1>, axi_wready : UInt<1>, axi_bvalid : UInt<1>, axi_bresp : UInt<2>, axi_bid : UInt<1>, axi_arready : UInt<1>, axi_rvalid : UInt<1>, axi_rid : UInt<1>, axi_rdata : UInt<32>, axi_rresp : UInt<2>, axi_rlast : UInt<1>, ahb_haddr : UInt<32>, ahb_hburst : UInt<3>, ahb_hmastlock : UInt<1>, ahb_hprot : UInt<4>, ahb_hsize : UInt<3>, ahb_htrans : UInt<2>, ahb_hwrite : UInt<1>, ahb_hwdata : UInt<64>}
+    
+    reg state : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[axi4_to_ahb.scala 61:22]
+    reg buf_state : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[axi4_to_ahb.scala 62:26]
+    reg buf_nxtstate : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[axi4_to_ahb.scala 63:29]
+    wire slave_valid : UInt<1>
+    slave_valid <= UInt<1>("h00")
+    wire slave_ready : UInt<1>
+    slave_ready <= UInt<1>("h00")
+    wire slave_tag : UInt<1>
+    slave_tag <= UInt<1>("h00")
+    wire slave_rdata : UInt<64>
+    slave_rdata <= UInt<64>("h00")
+    wire slave_opc : UInt<4>
+    slave_opc <= UInt<4>("h00")
+    wire wrbuf_en : UInt<1>
+    wrbuf_en <= UInt<1>("h00")
+    wire wrbuf_data_en : UInt<1>
+    wrbuf_data_en <= UInt<1>("h00")
+    wire wrbuf_cmd_sent : UInt<1>
+    wrbuf_cmd_sent <= UInt<1>("h00")
+    wire wrbuf_rst : UInt<1>
+    wrbuf_rst <= UInt<1>("h00")
+    wire wrbuf_vld : UInt<1>
+    wrbuf_vld <= UInt<1>("h00")
+    wire wrbuf_data_vld : UInt<1>
+    wrbuf_data_vld <= UInt<1>("h00")
+    wire wrbuf_tag : UInt<1>
+    wrbuf_tag <= UInt<1>("h00")
+    wire wrbuf_size : UInt<3>
+    wrbuf_size <= UInt<3>("h00")
+    wire wrbuf_addr : UInt<32>
+    wrbuf_addr <= UInt<32>("h00")
+    wire wrbuf_data : UInt<64>
+    wrbuf_data <= UInt<64>("h00")
+    wire wrbuf_byteen : UInt<8>
+    wrbuf_byteen <= UInt<8>("h00")
+    wire bus_write_clk_en : UInt<1>
+    bus_write_clk_en <= UInt<1>("h00")
+    wire bus_clk : Clock @[axi4_to_ahb.scala 83:21]
+    wire bus_write_clk : Clock @[axi4_to_ahb.scala 84:27]
+    wire master_valid : UInt<1>
+    master_valid <= UInt<1>("h00")
+    wire master_ready : UInt<1>
+    master_ready <= UInt<1>("h00")
+    wire master_tag : UInt<1>
+    master_tag <= UInt<1>("h00")
+    wire master_addr : UInt<32>
+    master_addr <= UInt<32>("h00")
+    wire master_wdata : UInt<64>
+    master_wdata <= UInt<64>("h00")
+    wire master_size : UInt<3>
+    master_size <= UInt<3>("h00")
+    wire master_opc : UInt<3>
+    master_opc <= UInt<3>("h00")
+    wire master_byteen : UInt<8>
+    master_byteen <= UInt<8>("h00")
+    wire buf_addr : UInt<32>
+    buf_addr <= UInt<32>("h00")
+    wire buf_size : UInt<2>
+    buf_size <= UInt<2>("h00")
+    wire buf_write : UInt<1>
+    buf_write <= UInt<1>("h00")
+    wire buf_byteen : UInt<8>
+    buf_byteen <= UInt<8>("h00")
+    wire buf_aligned : UInt<1>
+    buf_aligned <= UInt<1>("h00")
+    wire buf_data : UInt<64>
+    buf_data <= UInt<64>("h00")
+    wire buf_tag : UInt<1>
+    buf_tag <= UInt<1>("h00")
+    wire buf_rst : UInt<1>
+    buf_rst <= UInt<1>("h00")
+    wire buf_tag_in : UInt<1>
+    buf_tag_in <= UInt<1>("h00")
+    wire buf_addr_in : UInt<32>
+    buf_addr_in <= UInt<32>("h00")
+    wire buf_byteen_in : UInt<8>
+    buf_byteen_in <= UInt<8>("h00")
+    wire buf_data_in : UInt<64>
+    buf_data_in <= UInt<64>("h00")
+    wire buf_write_in : UInt<1>
+    buf_write_in <= UInt<1>("h00")
+    wire buf_aligned_in : UInt<1>
+    buf_aligned_in <= UInt<1>("h00")
+    wire buf_size_in : UInt<3>
+    buf_size_in <= UInt<3>("h00")
+    wire buf_state_en : UInt<1>
+    buf_state_en <= UInt<1>("h00")
+    wire buf_wr_en : UInt<1>
+    buf_wr_en <= UInt<1>("h00")
+    wire buf_data_wr_en : UInt<1>
+    buf_data_wr_en <= UInt<1>("h00")
+    wire slvbuf_error_en : UInt<1>
+    slvbuf_error_en <= UInt<1>("h00")
+    wire wr_cmd_vld : UInt<1>
+    wr_cmd_vld <= UInt<1>("h00")
+    wire cmd_done_rst : UInt<1>
+    cmd_done_rst <= UInt<1>("h00")
+    wire cmd_done : UInt<1>
+    cmd_done <= UInt<1>("h00")
+    wire cmd_doneQ : UInt<1>
+    cmd_doneQ <= UInt<1>("h00")
+    wire trxn_done : UInt<1>
+    trxn_done <= UInt<1>("h00")
+    wire buf_cmd_byte_ptr : UInt<3>
+    buf_cmd_byte_ptr <= UInt<3>("h00")
+    wire buf_cmd_byte_ptrQ : UInt<3>
+    buf_cmd_byte_ptrQ <= UInt<3>("h00")
+    wire buf_cmd_nxtbyte_ptr : UInt<3>
+    buf_cmd_nxtbyte_ptr <= UInt<3>("h00")
+    wire buf_cmd_byte_ptr_en : UInt<1>
+    buf_cmd_byte_ptr_en <= UInt<1>("h00")
+    wire found : UInt<1>
+    found <= UInt<1>("h00")
+    wire slave_valid_pre : UInt<1>
+    slave_valid_pre <= UInt<1>("h00")
+    wire ahb_hready_q : UInt<1>
+    ahb_hready_q <= UInt<1>("h00")
+    wire ahb_hresp_q : UInt<1>
+    ahb_hresp_q <= UInt<1>("h00")
+    wire ahb_htrans_q : UInt<2>
+    ahb_htrans_q <= UInt<2>("h00")
+    wire ahb_hwrite_q : UInt<1>
+    ahb_hwrite_q <= UInt<1>("h00")
+    wire ahb_hrdata_q : UInt<64>
+    ahb_hrdata_q <= UInt<64>("h00")
+    wire slvbuf_write : UInt<1>
+    slvbuf_write <= UInt<1>("h00")
+    wire slvbuf_error : UInt<1>
+    slvbuf_error <= UInt<1>("h00")
+    wire slvbuf_tag : UInt<1>
+    slvbuf_tag <= UInt<1>("h00")
+    wire slvbuf_error_in : UInt<1>
+    slvbuf_error_in <= UInt<1>("h00")
+    wire slvbuf_wr_en : UInt<1>
+    slvbuf_wr_en <= UInt<1>("h00")
+    wire bypass_en : UInt<1>
+    bypass_en <= UInt<1>("h00")
+    wire rd_bypass_idle : UInt<1>
+    rd_bypass_idle <= UInt<1>("h00")
+    wire last_addr_en : UInt<1>
+    last_addr_en <= UInt<1>("h00")
+    wire last_bus_addr : UInt<32>
+    last_bus_addr <= UInt<32>("h00")
+    wire buf_clken : UInt<1>
+    buf_clken <= UInt<1>("h00")
+    wire slvbuf_clken : UInt<1>
+    slvbuf_clken <= UInt<1>("h00")
+    wire ahbm_addr_clken : UInt<1>
+    ahbm_addr_clken <= UInt<1>("h00")
+    wire ahbm_data_clken : UInt<1>
+    ahbm_data_clken <= UInt<1>("h00")
+    wire buf_clk : Clock @[axi4_to_ahb.scala 151:21]
+    wire ahbm_clk : Clock @[axi4_to_ahb.scala 153:22]
+    wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 154:27]
+    wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 155:27]
+    node _T = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 183:30]
+    node _T_1 = and(_T, master_ready) @[axi4_to_ahb.scala 183:47]
+    wrbuf_en <= _T_1 @[axi4_to_ahb.scala 183:12]
+    node _T_2 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 184:34]
+    node _T_3 = and(_T_2, master_ready) @[axi4_to_ahb.scala 184:50]
+    wrbuf_data_en <= _T_3 @[axi4_to_ahb.scala 184:17]
+    node _T_4 = and(master_valid, master_ready) @[axi4_to_ahb.scala 185:34]
+    node _T_5 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 185:62]
+    node _T_6 = eq(_T_5, UInt<1>("h01")) @[axi4_to_ahb.scala 185:69]
+    node _T_7 = and(_T_4, _T_6) @[axi4_to_ahb.scala 185:49]
+    wrbuf_cmd_sent <= _T_7 @[axi4_to_ahb.scala 185:18]
+    node _T_8 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 186:33]
+    node _T_9 = and(wrbuf_cmd_sent, _T_8) @[axi4_to_ahb.scala 186:31]
+    wrbuf_rst <= _T_9 @[axi4_to_ahb.scala 186:13]
+    node _T_10 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 188:35]
+    node _T_11 = and(wrbuf_vld, _T_10) @[axi4_to_ahb.scala 188:33]
+    node _T_12 = eq(_T_11, UInt<1>("h00")) @[axi4_to_ahb.scala 188:21]
+    node _T_13 = and(_T_12, master_ready) @[axi4_to_ahb.scala 188:52]
+    io.axi_awready <= _T_13 @[axi4_to_ahb.scala 188:18]
+    node _T_14 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 189:39]
+    node _T_15 = and(wrbuf_data_vld, _T_14) @[axi4_to_ahb.scala 189:37]
+    node _T_16 = eq(_T_15, UInt<1>("h00")) @[axi4_to_ahb.scala 189:20]
+    node _T_17 = and(_T_16, master_ready) @[axi4_to_ahb.scala 189:56]
+    io.axi_wready <= _T_17 @[axi4_to_ahb.scala 189:17]
+    node _T_18 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 190:33]
+    node _T_19 = eq(_T_18, UInt<1>("h00")) @[axi4_to_ahb.scala 190:21]
+    node _T_20 = and(_T_19, master_ready) @[axi4_to_ahb.scala 190:51]
+    io.axi_arready <= _T_20 @[axi4_to_ahb.scala 190:18]
+    io.axi_rlast <= UInt<1>("h01") @[axi4_to_ahb.scala 191:16]
+    node _T_21 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 193:27]
+    wr_cmd_vld <= _T_21 @[axi4_to_ahb.scala 193:14]
+    node _T_22 = or(wr_cmd_vld, io.axi_arvalid) @[axi4_to_ahb.scala 194:30]
+    master_valid <= _T_22 @[axi4_to_ahb.scala 194:16]
+    node _T_23 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 195:38]
+    node _T_24 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 195:51]
+    node _T_25 = bits(io.axi_arid, 0, 0) @[axi4_to_ahb.scala 195:76]
+    node _T_26 = mux(_T_23, _T_24, _T_25) @[axi4_to_ahb.scala 195:20]
+    master_tag <= _T_26 @[axi4_to_ahb.scala 195:14]
+    node _T_27 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 196:38]
+    node _T_28 = mux(_T_27, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 196:20]
+    master_opc <= _T_28 @[axi4_to_ahb.scala 196:14]
+    node _T_29 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 197:39]
+    node _T_30 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 197:53]
+    node _T_31 = bits(io.axi_araddr, 31, 0) @[axi4_to_ahb.scala 197:75]
+    node _T_32 = mux(_T_29, _T_30, _T_31) @[axi4_to_ahb.scala 197:21]
+    master_addr <= _T_32 @[axi4_to_ahb.scala 197:15]
+    node _T_33 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 198:39]
+    node _T_34 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 198:53]
+    node _T_35 = bits(io.axi_arsize, 2, 0) @[axi4_to_ahb.scala 198:74]
+    node _T_36 = mux(_T_33, _T_34, _T_35) @[axi4_to_ahb.scala 198:21]
+    master_size <= _T_36 @[axi4_to_ahb.scala 198:15]
+    node _T_37 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 199:32]
+    master_byteen <= _T_37 @[axi4_to_ahb.scala 199:17]
+    node _T_38 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 200:29]
+    master_wdata <= _T_38 @[axi4_to_ahb.scala 200:16]
+    node _T_39 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 203:32]
+    node _T_40 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 203:57]
+    node _T_41 = and(_T_39, _T_40) @[axi4_to_ahb.scala 203:46]
+    io.axi_bvalid <= _T_41 @[axi4_to_ahb.scala 203:17]
+    node _T_42 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 204:32]
+    node _T_43 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 204:59]
+    node _T_44 = mux(_T_43, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 204:49]
+    node _T_45 = mux(_T_42, UInt<2>("h02"), _T_44) @[axi4_to_ahb.scala 204:22]
+    io.axi_bresp <= _T_45 @[axi4_to_ahb.scala 204:16]
+    node _T_46 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 205:26]
+    io.axi_bid <= _T_46 @[axi4_to_ahb.scala 205:14]
+    node _T_47 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 207:32]
+    node _T_48 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 207:58]
+    node _T_49 = eq(_T_48, UInt<1>("h00")) @[axi4_to_ahb.scala 207:65]
+    node _T_50 = and(_T_47, _T_49) @[axi4_to_ahb.scala 207:46]
+    io.axi_rvalid <= _T_50 @[axi4_to_ahb.scala 207:17]
+    node _T_51 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 208:32]
+    node _T_52 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 208:59]
+    node _T_53 = mux(_T_52, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 208:49]
+    node _T_54 = mux(_T_51, UInt<2>("h02"), _T_53) @[axi4_to_ahb.scala 208:22]
+    io.axi_rresp <= _T_54 @[axi4_to_ahb.scala 208:16]
+    node _T_55 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 209:26]
+    io.axi_rid <= _T_55 @[axi4_to_ahb.scala 209:14]
+    node _T_56 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 210:30]
+    io.axi_rdata <= _T_56 @[axi4_to_ahb.scala 210:16]
+    node _T_57 = and(io.axi_bready, io.axi_rready) @[axi4_to_ahb.scala 211:32]
+    slave_ready <= _T_57 @[axi4_to_ahb.scala 211:15]
+    node _T_58 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 214:56]
+    node _T_59 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 214:91]
+    node _T_60 = or(_T_58, _T_59) @[axi4_to_ahb.scala 214:74]
+    node _T_61 = and(io.bus_clk_en, _T_60) @[axi4_to_ahb.scala 214:37]
+    bus_write_clk_en <= _T_61 @[axi4_to_ahb.scala 214:20]
+    inst rvclkhdr of rvclkhdr @[el2_lib.scala 483:22]
+    rvclkhdr.clock <= clock
+    rvclkhdr.reset <= reset
+    rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17]
+    rvclkhdr.io.en <= io.bus_clk_en @[el2_lib.scala 485:16]
+    rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
+    bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 216:11]
+    node _T_62 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 217:59]
+    inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 483:22]
+    rvclkhdr_1.clock <= clock
+    rvclkhdr_1.reset <= reset
+    rvclkhdr_1.io.clk <= clock @[el2_lib.scala 484:17]
+    rvclkhdr_1.io.en <= _T_62 @[el2_lib.scala 485:16]
+    rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
+    bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 217:17]
+    io.ahb_htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 220:17]
+    master_ready <= UInt<1>("h00") @[axi4_to_ahb.scala 221:16]
+    buf_state_en <= UInt<1>("h00") @[axi4_to_ahb.scala 222:16]
+    node _T_63 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30]
+    when _T_63 : @[Conditional.scala 40:58]
+      master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 225:20]
+      node _T_64 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 226:34]
+      node _T_65 = eq(_T_64, UInt<1>("h01")) @[axi4_to_ahb.scala 226:41]
+      buf_write_in <= _T_65 @[axi4_to_ahb.scala 226:20]
+      node _T_66 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 227:46]
+      node _T_67 = mux(_T_66, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 227:26]
+      buf_nxtstate <= _T_67 @[axi4_to_ahb.scala 227:20]
+      node _T_68 = and(master_valid, master_ready) @[axi4_to_ahb.scala 228:36]
+      buf_state_en <= _T_68 @[axi4_to_ahb.scala 228:20]
+      buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 229:17]
+      node _T_69 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 230:54]
+      node _T_70 = and(buf_state_en, _T_69) @[axi4_to_ahb.scala 230:38]
+      buf_data_wr_en <= _T_70 @[axi4_to_ahb.scala 230:22]
+      buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 231:27]
+      node _T_71 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 233:50]
+      node _T_72 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 233:92]
+      node _T_73 = add(UInt<1>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 177:52]
+      node _T_74 = tail(_T_73, 1) @[axi4_to_ahb.scala 177:52]
+      node _T_75 = mux(UInt<1>("h00"), _T_74, UInt<1>("h00")) @[axi4_to_ahb.scala 177:24]
+      node _T_76 = bits(_T_72, 0, 0) @[axi4_to_ahb.scala 178:44]
+      node _T_77 = geq(UInt<1>("h00"), _T_75) @[axi4_to_ahb.scala 178:62]
+      node _T_78 = and(_T_76, _T_77) @[axi4_to_ahb.scala 178:48]
+      node _T_79 = bits(_T_72, 1, 1) @[axi4_to_ahb.scala 178:44]
+      node _T_80 = geq(UInt<1>("h01"), _T_75) @[axi4_to_ahb.scala 178:62]
+      node _T_81 = and(_T_79, _T_80) @[axi4_to_ahb.scala 178:48]
+      node _T_82 = bits(_T_72, 2, 2) @[axi4_to_ahb.scala 178:44]
+      node _T_83 = geq(UInt<2>("h02"), _T_75) @[axi4_to_ahb.scala 178:62]
+      node _T_84 = and(_T_82, _T_83) @[axi4_to_ahb.scala 178:48]
+      node _T_85 = bits(_T_72, 3, 3) @[axi4_to_ahb.scala 178:44]
+      node _T_86 = geq(UInt<2>("h03"), _T_75) @[axi4_to_ahb.scala 178:62]
+      node _T_87 = and(_T_85, _T_86) @[axi4_to_ahb.scala 178:48]
+      node _T_88 = bits(_T_72, 4, 4) @[axi4_to_ahb.scala 178:44]
+      node _T_89 = geq(UInt<3>("h04"), _T_75) @[axi4_to_ahb.scala 178:62]
+      node _T_90 = and(_T_88, _T_89) @[axi4_to_ahb.scala 178:48]
+      node _T_91 = bits(_T_72, 5, 5) @[axi4_to_ahb.scala 178:44]
+      node _T_92 = geq(UInt<3>("h05"), _T_75) @[axi4_to_ahb.scala 178:62]
+      node _T_93 = and(_T_91, _T_92) @[axi4_to_ahb.scala 178:48]
+      node _T_94 = bits(_T_72, 6, 6) @[axi4_to_ahb.scala 178:44]
+      node _T_95 = geq(UInt<3>("h06"), _T_75) @[axi4_to_ahb.scala 178:62]
+      node _T_96 = and(_T_94, _T_95) @[axi4_to_ahb.scala 178:48]
+      node _T_97 = bits(_T_72, 7, 7) @[axi4_to_ahb.scala 178:44]
+      node _T_98 = geq(UInt<3>("h07"), _T_75) @[axi4_to_ahb.scala 178:62]
+      node _T_99 = and(_T_97, _T_98) @[axi4_to_ahb.scala 178:48]
+      node _T_100 = mux(_T_99, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16]
+      node _T_101 = mux(_T_96, UInt<3>("h06"), _T_100) @[Mux.scala 98:16]
+      node _T_102 = mux(_T_93, UInt<3>("h05"), _T_101) @[Mux.scala 98:16]
+      node _T_103 = mux(_T_90, UInt<3>("h04"), _T_102) @[Mux.scala 98:16]
+      node _T_104 = mux(_T_87, UInt<2>("h03"), _T_103) @[Mux.scala 98:16]
+      node _T_105 = mux(_T_84, UInt<2>("h02"), _T_104) @[Mux.scala 98:16]
+      node _T_106 = mux(_T_81, UInt<1>("h01"), _T_105) @[Mux.scala 98:16]
+      node _T_107 = mux(_T_78, UInt<1>("h00"), _T_106) @[Mux.scala 98:16]
+      node _T_108 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 233:141]
+      node _T_109 = mux(_T_71, _T_107, _T_108) @[axi4_to_ahb.scala 233:30]
+      buf_cmd_byte_ptr <= _T_109 @[axi4_to_ahb.scala 233:24]
+      bypass_en <= buf_state_en @[axi4_to_ahb.scala 234:17]
+      node _T_110 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 235:51]
+      node _T_111 = and(bypass_en, _T_110) @[axi4_to_ahb.scala 235:35]
+      rd_bypass_idle <= _T_111 @[axi4_to_ahb.scala 235:22]
+      node _T_112 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15]
+      node _T_113 = mux(_T_112, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+      node _T_114 = and(_T_113, UInt<2>("h02")) @[axi4_to_ahb.scala 236:45]
+      io.ahb_htrans <= _T_114 @[axi4_to_ahb.scala 236:21]
+      skip @[Conditional.scala 40:58]
+    else : @[Conditional.scala 39:67]
+      node _T_115 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30]
+      when _T_115 : @[Conditional.scala 39:67]
+        node _T_116 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 240:54]
+        node _T_117 = eq(_T_116, UInt<1>("h00")) @[axi4_to_ahb.scala 240:61]
+        node _T_118 = and(master_valid, _T_117) @[axi4_to_ahb.scala 240:41]
+        node _T_119 = bits(_T_118, 0, 0) @[axi4_to_ahb.scala 240:82]
+        node _T_120 = mux(_T_119, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 240:26]
+        buf_nxtstate <= _T_120 @[axi4_to_ahb.scala 240:20]
+        node _T_121 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 241:51]
+        node _T_122 = neq(_T_121, UInt<1>("h00")) @[axi4_to_ahb.scala 241:58]
+        node _T_123 = and(ahb_hready_q, _T_122) @[axi4_to_ahb.scala 241:36]
+        node _T_124 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 241:72]
+        node _T_125 = and(_T_123, _T_124) @[axi4_to_ahb.scala 241:70]
+        buf_state_en <= _T_125 @[axi4_to_ahb.scala 241:20]
+        node _T_126 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 242:34]
+        node _T_127 = and(buf_state_en, _T_126) @[axi4_to_ahb.scala 242:32]
+        cmd_done <= _T_127 @[axi4_to_ahb.scala 242:16]
+        slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 243:20]
+        node _T_128 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 244:52]
+        node _T_129 = neq(_T_128, UInt<1>("h00")) @[axi4_to_ahb.scala 244:59]
+        node _T_130 = and(ahb_hready_q, _T_129) @[axi4_to_ahb.scala 244:37]
+        node _T_131 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 244:73]
+        node _T_132 = and(_T_130, _T_131) @[axi4_to_ahb.scala 244:71]
+        node _T_133 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 244:104]
+        node _T_134 = and(_T_132, _T_133) @[axi4_to_ahb.scala 244:88]
+        master_ready <= _T_134 @[axi4_to_ahb.scala 244:20]
+        buf_wr_en <= master_ready @[axi4_to_ahb.scala 245:17]
+        node _T_135 = and(master_ready, master_valid) @[axi4_to_ahb.scala 246:33]
+        bypass_en <= _T_135 @[axi4_to_ahb.scala 246:17]
+        node _T_136 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 247:47]
+        node _T_137 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 247:62]
+        node _T_138 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 247:78]
+        node _T_139 = mux(_T_136, _T_137, _T_138) @[axi4_to_ahb.scala 247:30]
+        buf_cmd_byte_ptr <= _T_139 @[axi4_to_ahb.scala 247:24]
+        node _T_140 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 248:44]
+        node _T_141 = or(_T_140, bypass_en) @[axi4_to_ahb.scala 248:58]
+        node _T_142 = bits(_T_141, 0, 0) @[Bitwise.scala 72:15]
+        node _T_143 = mux(_T_142, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+        node _T_144 = and(UInt<2>("h02"), _T_143) @[axi4_to_ahb.scala 248:32]
+        io.ahb_htrans <= _T_144 @[axi4_to_ahb.scala 248:21]
+        skip @[Conditional.scala 39:67]
+      else : @[Conditional.scala 39:67]
+        node _T_145 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30]
+        when _T_145 : @[Conditional.scala 39:67]
+          node _T_146 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 252:39]
+          node _T_147 = and(ahb_hready_q, _T_146) @[axi4_to_ahb.scala 252:37]
+          node _T_148 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 252:82]
+          node _T_149 = eq(_T_148, UInt<1>("h01")) @[axi4_to_ahb.scala 252:89]
+          node _T_150 = and(master_valid, _T_149) @[axi4_to_ahb.scala 252:70]
+          node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 252:55]
+          node _T_152 = and(_T_147, _T_151) @[axi4_to_ahb.scala 252:53]
+          master_ready <= _T_152 @[axi4_to_ahb.scala 252:20]
+          node _T_153 = and(master_valid, master_ready) @[axi4_to_ahb.scala 253:34]
+          node _T_154 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 253:62]
+          node _T_155 = eq(_T_154, UInt<1>("h00")) @[axi4_to_ahb.scala 253:69]
+          node _T_156 = and(_T_153, _T_155) @[axi4_to_ahb.scala 253:49]
+          buf_wr_en <= _T_156 @[axi4_to_ahb.scala 253:17]
+          node _T_157 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 254:45]
+          node _T_158 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 254:84]
+          node _T_159 = mux(_T_158, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 254:67]
+          node _T_160 = mux(_T_157, UInt<3>("h07"), _T_159) @[axi4_to_ahb.scala 254:26]
+          buf_nxtstate <= _T_160 @[axi4_to_ahb.scala 254:20]
+          node _T_161 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 255:37]
+          buf_state_en <= _T_161 @[axi4_to_ahb.scala 255:20]
+          buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 256:22]
+          slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 257:23]
+          slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 258:23]
+          node _T_162 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 259:41]
+          node _T_163 = and(buf_state_en, _T_162) @[axi4_to_ahb.scala 259:39]
+          slave_valid_pre <= _T_163 @[axi4_to_ahb.scala 259:23]
+          node _T_164 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 260:34]
+          node _T_165 = and(buf_state_en, _T_164) @[axi4_to_ahb.scala 260:32]
+          cmd_done <= _T_165 @[axi4_to_ahb.scala 260:16]
+          node _T_166 = and(master_ready, master_valid) @[axi4_to_ahb.scala 261:33]
+          node _T_167 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 261:64]
+          node _T_168 = and(_T_166, _T_167) @[axi4_to_ahb.scala 261:48]
+          node _T_169 = and(_T_168, buf_state_en) @[axi4_to_ahb.scala 261:79]
+          bypass_en <= _T_169 @[axi4_to_ahb.scala 261:17]
+          node _T_170 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 262:47]
+          node _T_171 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 262:62]
+          node _T_172 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 262:78]
+          node _T_173 = mux(_T_170, _T_171, _T_172) @[axi4_to_ahb.scala 262:30]
+          buf_cmd_byte_ptr <= _T_173 @[axi4_to_ahb.scala 262:24]
+          node _T_174 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 263:59]
+          node _T_175 = and(_T_174, buf_state_en) @[axi4_to_ahb.scala 263:74]
+          node _T_176 = eq(_T_175, UInt<1>("h00")) @[axi4_to_ahb.scala 263:43]
+          node _T_177 = bits(_T_176, 0, 0) @[Bitwise.scala 72:15]
+          node _T_178 = mux(_T_177, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+          node _T_179 = and(UInt<2>("h02"), _T_178) @[axi4_to_ahb.scala 263:32]
+          io.ahb_htrans <= _T_179 @[axi4_to_ahb.scala 263:21]
+          slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 264:20]
+          skip @[Conditional.scala 39:67]
+        else : @[Conditional.scala 39:67]
+          node _T_180 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30]
+          when _T_180 : @[Conditional.scala 39:67]
+            buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 268:20]
+            node _T_181 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 269:51]
+            node _T_182 = neq(_T_181, UInt<1>("h00")) @[axi4_to_ahb.scala 269:58]
+            node _T_183 = and(ahb_hready_q, _T_182) @[axi4_to_ahb.scala 269:36]
+            node _T_184 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 269:72]
+            node _T_185 = and(_T_183, _T_184) @[axi4_to_ahb.scala 269:70]
+            buf_state_en <= _T_185 @[axi4_to_ahb.scala 269:20]
+            slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 270:23]
+            slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 271:20]
+            node _T_186 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 272:35]
+            buf_cmd_byte_ptr <= _T_186 @[axi4_to_ahb.scala 272:24]
+            node _T_187 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 273:47]
+            node _T_188 = bits(_T_187, 0, 0) @[Bitwise.scala 72:15]
+            node _T_189 = mux(_T_188, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+            node _T_190 = and(UInt<2>("h02"), _T_189) @[axi4_to_ahb.scala 273:37]
+            io.ahb_htrans <= _T_190 @[axi4_to_ahb.scala 273:21]
+            skip @[Conditional.scala 39:67]
+          else : @[Conditional.scala 39:67]
+            node _T_191 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30]
+            when _T_191 : @[Conditional.scala 39:67]
+              buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 277:20]
+              node _T_192 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 278:37]
+              buf_state_en <= _T_192 @[axi4_to_ahb.scala 278:20]
+              buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 279:22]
+              slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 280:23]
+              slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 281:23]
+              slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 282:20]
+              skip @[Conditional.scala 39:67]
+            else : @[Conditional.scala 39:67]
+              node _T_193 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30]
+              when _T_193 : @[Conditional.scala 39:67]
+                buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 286:20]
+                node _T_194 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 287:33]
+                node _T_195 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 287:63]
+                node _T_196 = neq(_T_195, UInt<1>("h00")) @[axi4_to_ahb.scala 287:70]
+                node _T_197 = and(_T_194, _T_196) @[axi4_to_ahb.scala 287:48]
+                trxn_done <= _T_197 @[axi4_to_ahb.scala 287:17]
+                buf_state_en <= trxn_done @[axi4_to_ahb.scala 288:20]
+                buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 289:27]
+                slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 290:20]
+                node _T_198 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 291:47]
+                node _T_199 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 291:85]
+                node _T_200 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 291:103]
+                node _T_201 = add(_T_199, UInt<1>("h01")) @[axi4_to_ahb.scala 177:52]
+                node _T_202 = tail(_T_201, 1) @[axi4_to_ahb.scala 177:52]
+                node _T_203 = mux(UInt<1>("h01"), _T_202, _T_199) @[axi4_to_ahb.scala 177:24]
+                node _T_204 = bits(_T_200, 0, 0) @[axi4_to_ahb.scala 178:44]
+                node _T_205 = geq(UInt<1>("h00"), _T_203) @[axi4_to_ahb.scala 178:62]
+                node _T_206 = and(_T_204, _T_205) @[axi4_to_ahb.scala 178:48]
+                node _T_207 = bits(_T_200, 1, 1) @[axi4_to_ahb.scala 178:44]
+                node _T_208 = geq(UInt<1>("h01"), _T_203) @[axi4_to_ahb.scala 178:62]
+                node _T_209 = and(_T_207, _T_208) @[axi4_to_ahb.scala 178:48]
+                node _T_210 = bits(_T_200, 2, 2) @[axi4_to_ahb.scala 178:44]
+                node _T_211 = geq(UInt<2>("h02"), _T_203) @[axi4_to_ahb.scala 178:62]
+                node _T_212 = and(_T_210, _T_211) @[axi4_to_ahb.scala 178:48]
+                node _T_213 = bits(_T_200, 3, 3) @[axi4_to_ahb.scala 178:44]
+                node _T_214 = geq(UInt<2>("h03"), _T_203) @[axi4_to_ahb.scala 178:62]
+                node _T_215 = and(_T_213, _T_214) @[axi4_to_ahb.scala 178:48]
+                node _T_216 = bits(_T_200, 4, 4) @[axi4_to_ahb.scala 178:44]
+                node _T_217 = geq(UInt<3>("h04"), _T_203) @[axi4_to_ahb.scala 178:62]
+                node _T_218 = and(_T_216, _T_217) @[axi4_to_ahb.scala 178:48]
+                node _T_219 = bits(_T_200, 5, 5) @[axi4_to_ahb.scala 178:44]
+                node _T_220 = geq(UInt<3>("h05"), _T_203) @[axi4_to_ahb.scala 178:62]
+                node _T_221 = and(_T_219, _T_220) @[axi4_to_ahb.scala 178:48]
+                node _T_222 = bits(_T_200, 6, 6) @[axi4_to_ahb.scala 178:44]
+                node _T_223 = geq(UInt<3>("h06"), _T_203) @[axi4_to_ahb.scala 178:62]
+                node _T_224 = and(_T_222, _T_223) @[axi4_to_ahb.scala 178:48]
+                node _T_225 = bits(_T_200, 7, 7) @[axi4_to_ahb.scala 178:44]
+                node _T_226 = geq(UInt<3>("h07"), _T_203) @[axi4_to_ahb.scala 178:62]
+                node _T_227 = and(_T_225, _T_226) @[axi4_to_ahb.scala 178:48]
+                node _T_228 = mux(_T_227, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16]
+                node _T_229 = mux(_T_224, UInt<3>("h06"), _T_228) @[Mux.scala 98:16]
+                node _T_230 = mux(_T_221, UInt<3>("h05"), _T_229) @[Mux.scala 98:16]
+                node _T_231 = mux(_T_218, UInt<3>("h04"), _T_230) @[Mux.scala 98:16]
+                node _T_232 = mux(_T_215, UInt<2>("h03"), _T_231) @[Mux.scala 98:16]
+                node _T_233 = mux(_T_212, UInt<2>("h02"), _T_232) @[Mux.scala 98:16]
+                node _T_234 = mux(_T_209, UInt<1>("h01"), _T_233) @[Mux.scala 98:16]
+                node _T_235 = mux(_T_206, UInt<1>("h00"), _T_234) @[Mux.scala 98:16]
+                node _T_236 = mux(_T_198, _T_235, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 291:30]
+                buf_cmd_byte_ptr <= _T_236 @[axi4_to_ahb.scala 291:24]
+                node _T_237 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 292:65]
+                node _T_238 = or(buf_aligned, _T_237) @[axi4_to_ahb.scala 292:44]
+                node _T_239 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 292:127]
+                node _T_240 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 292:145]
+                node _T_241 = add(_T_239, UInt<1>("h01")) @[axi4_to_ahb.scala 177:52]
+                node _T_242 = tail(_T_241, 1) @[axi4_to_ahb.scala 177:52]
+                node _T_243 = mux(UInt<1>("h01"), _T_242, _T_239) @[axi4_to_ahb.scala 177:24]
+                node _T_244 = bits(_T_240, 0, 0) @[axi4_to_ahb.scala 178:44]
+                node _T_245 = geq(UInt<1>("h00"), _T_243) @[axi4_to_ahb.scala 178:62]
+                node _T_246 = and(_T_244, _T_245) @[axi4_to_ahb.scala 178:48]
+                node _T_247 = bits(_T_240, 1, 1) @[axi4_to_ahb.scala 178:44]
+                node _T_248 = geq(UInt<1>("h01"), _T_243) @[axi4_to_ahb.scala 178:62]
+                node _T_249 = and(_T_247, _T_248) @[axi4_to_ahb.scala 178:48]
+                node _T_250 = bits(_T_240, 2, 2) @[axi4_to_ahb.scala 178:44]
+                node _T_251 = geq(UInt<2>("h02"), _T_243) @[axi4_to_ahb.scala 178:62]
+                node _T_252 = and(_T_250, _T_251) @[axi4_to_ahb.scala 178:48]
+                node _T_253 = bits(_T_240, 3, 3) @[axi4_to_ahb.scala 178:44]
+                node _T_254 = geq(UInt<2>("h03"), _T_243) @[axi4_to_ahb.scala 178:62]
+                node _T_255 = and(_T_253, _T_254) @[axi4_to_ahb.scala 178:48]
+                node _T_256 = bits(_T_240, 4, 4) @[axi4_to_ahb.scala 178:44]
+                node _T_257 = geq(UInt<3>("h04"), _T_243) @[axi4_to_ahb.scala 178:62]
+                node _T_258 = and(_T_256, _T_257) @[axi4_to_ahb.scala 178:48]
+                node _T_259 = bits(_T_240, 5, 5) @[axi4_to_ahb.scala 178:44]
+                node _T_260 = geq(UInt<3>("h05"), _T_243) @[axi4_to_ahb.scala 178:62]
+                node _T_261 = and(_T_259, _T_260) @[axi4_to_ahb.scala 178:48]
+                node _T_262 = bits(_T_240, 6, 6) @[axi4_to_ahb.scala 178:44]
+                node _T_263 = geq(UInt<3>("h06"), _T_243) @[axi4_to_ahb.scala 178:62]
+                node _T_264 = and(_T_262, _T_263) @[axi4_to_ahb.scala 178:48]
+                node _T_265 = bits(_T_240, 7, 7) @[axi4_to_ahb.scala 178:44]
+                node _T_266 = geq(UInt<3>("h07"), _T_243) @[axi4_to_ahb.scala 178:62]
+                node _T_267 = and(_T_265, _T_266) @[axi4_to_ahb.scala 178:48]
+                node _T_268 = mux(_T_267, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16]
+                node _T_269 = mux(_T_264, UInt<3>("h06"), _T_268) @[Mux.scala 98:16]
+                node _T_270 = mux(_T_261, UInt<3>("h05"), _T_269) @[Mux.scala 98:16]
+                node _T_271 = mux(_T_258, UInt<3>("h04"), _T_270) @[Mux.scala 98:16]
+                node _T_272 = mux(_T_255, UInt<2>("h03"), _T_271) @[Mux.scala 98:16]
+                node _T_273 = mux(_T_252, UInt<2>("h02"), _T_272) @[Mux.scala 98:16]
+                node _T_274 = mux(_T_249, UInt<1>("h01"), _T_273) @[Mux.scala 98:16]
+                node _T_275 = mux(_T_246, UInt<1>("h00"), _T_274) @[Mux.scala 98:16]
+                node _T_276 = dshr(buf_byteen, _T_275) @[axi4_to_ahb.scala 292:92]
+                node _T_277 = bits(_T_276, 0, 0) @[axi4_to_ahb.scala 292:92]
+                node _T_278 = eq(_T_277, UInt<1>("h00")) @[axi4_to_ahb.scala 292:163]
+                node _T_279 = or(_T_238, _T_278) @[axi4_to_ahb.scala 292:79]
+                node _T_280 = and(trxn_done, _T_279) @[axi4_to_ahb.scala 292:29]
+                cmd_done <= _T_280 @[axi4_to_ahb.scala 292:16]
+                node _T_281 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 293:43]
+                node _T_282 = eq(_T_281, UInt<1>("h00")) @[axi4_to_ahb.scala 293:32]
+                node _T_283 = bits(_T_282, 0, 0) @[Bitwise.scala 72:15]
+                node _T_284 = mux(_T_283, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+                node _T_285 = and(_T_284, UInt<2>("h02")) @[axi4_to_ahb.scala 293:57]
+                io.ahb_htrans <= _T_285 @[axi4_to_ahb.scala 293:21]
+                skip @[Conditional.scala 39:67]
+              else : @[Conditional.scala 39:67]
+                node _T_286 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30]
+                when _T_286 : @[Conditional.scala 39:67]
+                  node _T_287 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 297:34]
+                  node _T_288 = or(_T_287, ahb_hresp_q) @[axi4_to_ahb.scala 297:50]
+                  buf_state_en <= _T_288 @[axi4_to_ahb.scala 297:20]
+                  node _T_289 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 298:35]
+                  node _T_290 = or(_T_289, ahb_hresp_q) @[axi4_to_ahb.scala 298:51]
+                  node _T_291 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 298:68]
+                  node _T_292 = and(_T_290, _T_291) @[axi4_to_ahb.scala 298:66]
+                  node _T_293 = and(_T_292, slave_ready) @[axi4_to_ahb.scala 298:81]
+                  master_ready <= _T_293 @[axi4_to_ahb.scala 298:20]
+                  node _T_294 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 299:42]
+                  node _T_295 = or(ahb_hresp_q, _T_294) @[axi4_to_ahb.scala 299:40]
+                  node _T_296 = bits(_T_295, 0, 0) @[axi4_to_ahb.scala 299:62]
+                  node _T_297 = and(master_valid, master_ready) @[axi4_to_ahb.scala 299:90]
+                  node _T_298 = bits(_T_297, 0, 0) @[axi4_to_ahb.scala 299:112]
+                  node _T_299 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 299:131]
+                  node _T_300 = eq(_T_299, UInt<1>("h01")) @[axi4_to_ahb.scala 299:138]
+                  node _T_301 = mux(_T_300, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 299:119]
+                  node _T_302 = mux(_T_298, _T_301, UInt<3>("h00")) @[axi4_to_ahb.scala 299:75]
+                  node _T_303 = mux(_T_296, UInt<3>("h05"), _T_302) @[axi4_to_ahb.scala 299:26]
+                  buf_nxtstate <= _T_303 @[axi4_to_ahb.scala 299:20]
+                  slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 300:23]
+                  slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 301:23]
+                  node _T_304 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 302:34]
+                  node _T_305 = eq(_T_304, UInt<1>("h01")) @[axi4_to_ahb.scala 302:41]
+                  buf_write_in <= _T_305 @[axi4_to_ahb.scala 302:20]
+                  node _T_306 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 303:50]
+                  node _T_307 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 303:78]
+                  node _T_308 = or(_T_306, _T_307) @[axi4_to_ahb.scala 303:62]
+                  node _T_309 = and(buf_state_en, _T_308) @[axi4_to_ahb.scala 303:33]
+                  buf_wr_en <= _T_309 @[axi4_to_ahb.scala 303:17]
+                  buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 304:22]
+                  node _T_310 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 305:63]
+                  node _T_311 = neq(_T_310, UInt<1>("h00")) @[axi4_to_ahb.scala 305:70]
+                  node _T_312 = and(ahb_hready_q, _T_311) @[axi4_to_ahb.scala 305:48]
+                  node _T_313 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 305:104]
+                  node _T_314 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 305:166]
+                  node _T_315 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 305:184]
+                  node _T_316 = add(_T_314, UInt<1>("h01")) @[axi4_to_ahb.scala 177:52]
+                  node _T_317 = tail(_T_316, 1) @[axi4_to_ahb.scala 177:52]
+                  node _T_318 = mux(UInt<1>("h01"), _T_317, _T_314) @[axi4_to_ahb.scala 177:24]
+                  node _T_319 = bits(_T_315, 0, 0) @[axi4_to_ahb.scala 178:44]
+                  node _T_320 = geq(UInt<1>("h00"), _T_318) @[axi4_to_ahb.scala 178:62]
+                  node _T_321 = and(_T_319, _T_320) @[axi4_to_ahb.scala 178:48]
+                  node _T_322 = bits(_T_315, 1, 1) @[axi4_to_ahb.scala 178:44]
+                  node _T_323 = geq(UInt<1>("h01"), _T_318) @[axi4_to_ahb.scala 178:62]
+                  node _T_324 = and(_T_322, _T_323) @[axi4_to_ahb.scala 178:48]
+                  node _T_325 = bits(_T_315, 2, 2) @[axi4_to_ahb.scala 178:44]
+                  node _T_326 = geq(UInt<2>("h02"), _T_318) @[axi4_to_ahb.scala 178:62]
+                  node _T_327 = and(_T_325, _T_326) @[axi4_to_ahb.scala 178:48]
+                  node _T_328 = bits(_T_315, 3, 3) @[axi4_to_ahb.scala 178:44]
+                  node _T_329 = geq(UInt<2>("h03"), _T_318) @[axi4_to_ahb.scala 178:62]
+                  node _T_330 = and(_T_328, _T_329) @[axi4_to_ahb.scala 178:48]
+                  node _T_331 = bits(_T_315, 4, 4) @[axi4_to_ahb.scala 178:44]
+                  node _T_332 = geq(UInt<3>("h04"), _T_318) @[axi4_to_ahb.scala 178:62]
+                  node _T_333 = and(_T_331, _T_332) @[axi4_to_ahb.scala 178:48]
+                  node _T_334 = bits(_T_315, 5, 5) @[axi4_to_ahb.scala 178:44]
+                  node _T_335 = geq(UInt<3>("h05"), _T_318) @[axi4_to_ahb.scala 178:62]
+                  node _T_336 = and(_T_334, _T_335) @[axi4_to_ahb.scala 178:48]
+                  node _T_337 = bits(_T_315, 6, 6) @[axi4_to_ahb.scala 178:44]
+                  node _T_338 = geq(UInt<3>("h06"), _T_318) @[axi4_to_ahb.scala 178:62]
+                  node _T_339 = and(_T_337, _T_338) @[axi4_to_ahb.scala 178:48]
+                  node _T_340 = bits(_T_315, 7, 7) @[axi4_to_ahb.scala 178:44]
+                  node _T_341 = geq(UInt<3>("h07"), _T_318) @[axi4_to_ahb.scala 178:62]
+                  node _T_342 = and(_T_340, _T_341) @[axi4_to_ahb.scala 178:48]
+                  node _T_343 = mux(_T_342, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16]
+                  node _T_344 = mux(_T_339, UInt<3>("h06"), _T_343) @[Mux.scala 98:16]
+                  node _T_345 = mux(_T_336, UInt<3>("h05"), _T_344) @[Mux.scala 98:16]
+                  node _T_346 = mux(_T_333, UInt<3>("h04"), _T_345) @[Mux.scala 98:16]
+                  node _T_347 = mux(_T_330, UInt<2>("h03"), _T_346) @[Mux.scala 98:16]
+                  node _T_348 = mux(_T_327, UInt<2>("h02"), _T_347) @[Mux.scala 98:16]
+                  node _T_349 = mux(_T_324, UInt<1>("h01"), _T_348) @[Mux.scala 98:16]
+                  node _T_350 = mux(_T_321, UInt<1>("h00"), _T_349) @[Mux.scala 98:16]
+                  node _T_351 = dshr(buf_byteen, _T_350) @[axi4_to_ahb.scala 305:131]
+                  node _T_352 = bits(_T_351, 0, 0) @[axi4_to_ahb.scala 305:131]
+                  node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 305:202]
+                  node _T_354 = or(_T_313, _T_353) @[axi4_to_ahb.scala 305:118]
+                  node _T_355 = and(_T_312, _T_354) @[axi4_to_ahb.scala 305:82]
+                  node _T_356 = or(ahb_hresp_q, _T_355) @[axi4_to_ahb.scala 305:32]
+                  cmd_done <= _T_356 @[axi4_to_ahb.scala 305:16]
+                  node _T_357 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 306:33]
+                  node _T_358 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 306:64]
+                  node _T_359 = and(_T_357, _T_358) @[axi4_to_ahb.scala 306:48]
+                  bypass_en <= _T_359 @[axi4_to_ahb.scala 306:17]
+                  node _T_360 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 307:44]
+                  node _T_361 = eq(_T_360, UInt<1>("h00")) @[axi4_to_ahb.scala 307:33]
+                  node _T_362 = or(_T_361, bypass_en) @[axi4_to_ahb.scala 307:57]
+                  node _T_363 = bits(_T_362, 0, 0) @[Bitwise.scala 72:15]
+                  node _T_364 = mux(_T_363, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+                  node _T_365 = and(_T_364, UInt<2>("h02")) @[axi4_to_ahb.scala 307:71]
+                  io.ahb_htrans <= _T_365 @[axi4_to_ahb.scala 307:21]
+                  node _T_366 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 308:55]
+                  node _T_367 = and(buf_state_en, _T_366) @[axi4_to_ahb.scala 308:39]
+                  slave_valid_pre <= _T_367 @[axi4_to_ahb.scala 308:23]
+                  node _T_368 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 309:33]
+                  node _T_369 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 309:63]
+                  node _T_370 = neq(_T_369, UInt<1>("h00")) @[axi4_to_ahb.scala 309:70]
+                  node _T_371 = and(_T_368, _T_370) @[axi4_to_ahb.scala 309:48]
+                  trxn_done <= _T_371 @[axi4_to_ahb.scala 309:17]
+                  node _T_372 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 310:40]
+                  buf_cmd_byte_ptr_en <= _T_372 @[axi4_to_ahb.scala 310:27]
+                  node _T_373 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+                  node _T_374 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 313:85]
+                  node _T_375 = add(_T_373, UInt<1>("h01")) @[axi4_to_ahb.scala 177:52]
+                  node _T_376 = tail(_T_375, 1) @[axi4_to_ahb.scala 177:52]
+                  node _T_377 = mux(UInt<1>("h00"), _T_376, _T_373) @[axi4_to_ahb.scala 177:24]
+                  node _T_378 = bits(_T_374, 0, 0) @[axi4_to_ahb.scala 178:44]
+                  node _T_379 = geq(UInt<1>("h00"), _T_377) @[axi4_to_ahb.scala 178:62]
+                  node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 178:48]
+                  node _T_381 = bits(_T_374, 1, 1) @[axi4_to_ahb.scala 178:44]
+                  node _T_382 = geq(UInt<1>("h01"), _T_377) @[axi4_to_ahb.scala 178:62]
+                  node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 178:48]
+                  node _T_384 = bits(_T_374, 2, 2) @[axi4_to_ahb.scala 178:44]
+                  node _T_385 = geq(UInt<2>("h02"), _T_377) @[axi4_to_ahb.scala 178:62]
+                  node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 178:48]
+                  node _T_387 = bits(_T_374, 3, 3) @[axi4_to_ahb.scala 178:44]
+                  node _T_388 = geq(UInt<2>("h03"), _T_377) @[axi4_to_ahb.scala 178:62]
+                  node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 178:48]
+                  node _T_390 = bits(_T_374, 4, 4) @[axi4_to_ahb.scala 178:44]
+                  node _T_391 = geq(UInt<3>("h04"), _T_377) @[axi4_to_ahb.scala 178:62]
+                  node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 178:48]
+                  node _T_393 = bits(_T_374, 5, 5) @[axi4_to_ahb.scala 178:44]
+                  node _T_394 = geq(UInt<3>("h05"), _T_377) @[axi4_to_ahb.scala 178:62]
+                  node _T_395 = and(_T_393, _T_394) @[axi4_to_ahb.scala 178:48]
+                  node _T_396 = bits(_T_374, 6, 6) @[axi4_to_ahb.scala 178:44]
+                  node _T_397 = geq(UInt<3>("h06"), _T_377) @[axi4_to_ahb.scala 178:62]
+                  node _T_398 = and(_T_396, _T_397) @[axi4_to_ahb.scala 178:48]
+                  node _T_399 = bits(_T_374, 7, 7) @[axi4_to_ahb.scala 178:44]
+                  node _T_400 = geq(UInt<3>("h07"), _T_377) @[axi4_to_ahb.scala 178:62]
+                  node _T_401 = and(_T_399, _T_400) @[axi4_to_ahb.scala 178:48]
+                  node _T_402 = mux(_T_401, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16]
+                  node _T_403 = mux(_T_398, UInt<3>("h06"), _T_402) @[Mux.scala 98:16]
+                  node _T_404 = mux(_T_395, UInt<3>("h05"), _T_403) @[Mux.scala 98:16]
+                  node _T_405 = mux(_T_392, UInt<3>("h04"), _T_404) @[Mux.scala 98:16]
+                  node _T_406 = mux(_T_389, UInt<2>("h03"), _T_405) @[Mux.scala 98:16]
+                  node _T_407 = mux(_T_386, UInt<2>("h02"), _T_406) @[Mux.scala 98:16]
+                  node _T_408 = mux(_T_383, UInt<1>("h01"), _T_407) @[Mux.scala 98:16]
+                  node _T_409 = mux(_T_380, UInt<1>("h00"), _T_408) @[Mux.scala 98:16]
+                  node _T_410 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 313:151]
+                  node _T_411 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 313:169]
+                  node _T_412 = add(_T_410, UInt<1>("h01")) @[axi4_to_ahb.scala 177:52]
+                  node _T_413 = tail(_T_412, 1) @[axi4_to_ahb.scala 177:52]
+                  node _T_414 = mux(UInt<1>("h01"), _T_413, _T_410) @[axi4_to_ahb.scala 177:24]
+                  node _T_415 = bits(_T_411, 0, 0) @[axi4_to_ahb.scala 178:44]
+                  node _T_416 = geq(UInt<1>("h00"), _T_414) @[axi4_to_ahb.scala 178:62]
+                  node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 178:48]
+                  node _T_418 = bits(_T_411, 1, 1) @[axi4_to_ahb.scala 178:44]
+                  node _T_419 = geq(UInt<1>("h01"), _T_414) @[axi4_to_ahb.scala 178:62]
+                  node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 178:48]
+                  node _T_421 = bits(_T_411, 2, 2) @[axi4_to_ahb.scala 178:44]
+                  node _T_422 = geq(UInt<2>("h02"), _T_414) @[axi4_to_ahb.scala 178:62]
+                  node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 178:48]
+                  node _T_424 = bits(_T_411, 3, 3) @[axi4_to_ahb.scala 178:44]
+                  node _T_425 = geq(UInt<2>("h03"), _T_414) @[axi4_to_ahb.scala 178:62]
+                  node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 178:48]
+                  node _T_427 = bits(_T_411, 4, 4) @[axi4_to_ahb.scala 178:44]
+                  node _T_428 = geq(UInt<3>("h04"), _T_414) @[axi4_to_ahb.scala 178:62]
+                  node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 178:48]
+                  node _T_430 = bits(_T_411, 5, 5) @[axi4_to_ahb.scala 178:44]
+                  node _T_431 = geq(UInt<3>("h05"), _T_414) @[axi4_to_ahb.scala 178:62]
+                  node _T_432 = and(_T_430, _T_431) @[axi4_to_ahb.scala 178:48]
+                  node _T_433 = bits(_T_411, 6, 6) @[axi4_to_ahb.scala 178:44]
+                  node _T_434 = geq(UInt<3>("h06"), _T_414) @[axi4_to_ahb.scala 178:62]
+                  node _T_435 = and(_T_433, _T_434) @[axi4_to_ahb.scala 178:48]
+                  node _T_436 = bits(_T_411, 7, 7) @[axi4_to_ahb.scala 178:44]
+                  node _T_437 = geq(UInt<3>("h07"), _T_414) @[axi4_to_ahb.scala 178:62]
+                  node _T_438 = and(_T_436, _T_437) @[axi4_to_ahb.scala 178:48]
+                  node _T_439 = mux(_T_438, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16]
+                  node _T_440 = mux(_T_435, UInt<3>("h06"), _T_439) @[Mux.scala 98:16]
+                  node _T_441 = mux(_T_432, UInt<3>("h05"), _T_440) @[Mux.scala 98:16]
+                  node _T_442 = mux(_T_429, UInt<3>("h04"), _T_441) @[Mux.scala 98:16]
+                  node _T_443 = mux(_T_426, UInt<2>("h03"), _T_442) @[Mux.scala 98:16]
+                  node _T_444 = mux(_T_423, UInt<2>("h02"), _T_443) @[Mux.scala 98:16]
+                  node _T_445 = mux(_T_420, UInt<1>("h01"), _T_444) @[Mux.scala 98:16]
+                  node _T_446 = mux(_T_417, UInt<1>("h00"), _T_445) @[Mux.scala 98:16]
+                  node _T_447 = mux(trxn_done, _T_446, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 313:106]
+                  node _T_448 = mux(bypass_en, _T_409, _T_447) @[axi4_to_ahb.scala 313:30]
+                  buf_cmd_byte_ptr <= _T_448 @[axi4_to_ahb.scala 313:24]
+                  skip @[Conditional.scala 39:67]
+                else : @[Conditional.scala 39:67]
+                  node _T_449 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30]
+                  when _T_449 : @[Conditional.scala 39:67]
+                    buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 316:20]
+                    buf_state_en <= slave_ready @[axi4_to_ahb.scala 317:20]
+                    slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 318:23]
+                    slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 319:23]
+                    skip @[Conditional.scala 39:67]
+    buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 323:11]
+    cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 324:16]
+    node _T_450 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 325:68]
+    node _T_451 = eq(_T_450, UInt<1>("h01")) @[axi4_to_ahb.scala 325:75]
+    node _T_452 = and(buf_aligned_in, _T_451) @[axi4_to_ahb.scala 325:55]
+    node _T_453 = bits(_T_452, 0, 0) @[axi4_to_ahb.scala 325:95]
+    node _T_454 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 325:127]
+    wire _T_455 : UInt<8>
+    _T_455 <= UInt<8>("h00")
+    node _T_456 = bits(_T_455, 7, 0) @[axi4_to_ahb.scala 169:44]
+    node _T_457 = eq(_T_456, UInt<8>("h0ff")) @[axi4_to_ahb.scala 169:51]
+    node _T_458 = bits(_T_455, 7, 0) @[axi4_to_ahb.scala 169:75]
+    node _T_459 = eq(_T_458, UInt<4>("h0f")) @[axi4_to_ahb.scala 169:82]
+    node _T_460 = or(_T_457, _T_459) @[axi4_to_ahb.scala 169:64]
+    node _T_461 = bits(_T_455, 7, 0) @[axi4_to_ahb.scala 169:106]
+    node _T_462 = eq(_T_461, UInt<2>("h03")) @[axi4_to_ahb.scala 169:113]
+    node _T_463 = or(_T_460, _T_462) @[axi4_to_ahb.scala 169:95]
+    node _T_464 = bits(_T_463, 0, 0) @[Bitwise.scala 72:15]
+    node _T_465 = mux(_T_464, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+    node _T_466 = and(UInt<1>("h00"), _T_465) @[axi4_to_ahb.scala 169:24]
+    node _T_467 = bits(_T_455, 7, 0) @[axi4_to_ahb.scala 170:35]
+    node _T_468 = eq(_T_467, UInt<4>("h0c")) @[axi4_to_ahb.scala 170:42]
+    node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15]
+    node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+    node _T_471 = and(UInt<2>("h02"), _T_470) @[axi4_to_ahb.scala 170:15]
+    node _T_472 = or(_T_466, _T_471) @[axi4_to_ahb.scala 169:128]
+    node _T_473 = bits(_T_455, 7, 0) @[axi4_to_ahb.scala 171:36]
+    node _T_474 = eq(_T_473, UInt<8>("h0f0")) @[axi4_to_ahb.scala 171:43]
+    node _T_475 = bits(_T_455, 7, 0) @[axi4_to_ahb.scala 171:67]
+    node _T_476 = eq(_T_475, UInt<2>("h03")) @[axi4_to_ahb.scala 171:74]
+    node _T_477 = or(_T_474, _T_476) @[axi4_to_ahb.scala 171:56]
+    node _T_478 = bits(_T_477, 0, 0) @[Bitwise.scala 72:15]
+    node _T_479 = mux(_T_478, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+    node _T_480 = and(UInt<3>("h04"), _T_479) @[axi4_to_ahb.scala 171:15]
+    node _T_481 = bits(_T_455, 7, 0) @[axi4_to_ahb.scala 172:37]
+    node _T_482 = eq(_T_481, UInt<8>("h0c0")) @[axi4_to_ahb.scala 172:44]
+    node _T_483 = bits(_T_482, 0, 0) @[Bitwise.scala 72:15]
+    node _T_484 = mux(_T_483, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+    node _T_485 = and(UInt<3>("h06"), _T_484) @[axi4_to_ahb.scala 172:17]
+    node _T_486 = or(_T_480, _T_485) @[axi4_to_ahb.scala 171:90]
+    node _T_487 = or(_T_472, _T_486) @[axi4_to_ahb.scala 170:58]
+    node _T_488 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 325:147]
+    node _T_489 = mux(_T_453, _T_487, _T_488) @[axi4_to_ahb.scala 325:38]
+    node _T_490 = cat(master_addr, _T_489) @[Cat.scala 29:58]
+    buf_addr_in <= _T_490 @[axi4_to_ahb.scala 325:15]
+    node _T_491 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 326:27]
+    buf_tag_in <= _T_491 @[axi4_to_ahb.scala 326:14]
+    node _T_492 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 327:32]
+    buf_byteen_in <= _T_492 @[axi4_to_ahb.scala 327:17]
+    node _T_493 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 328:33]
+    node _T_494 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 328:59]
+    node _T_495 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 328:80]
+    node _T_496 = mux(_T_493, _T_494, _T_495) @[axi4_to_ahb.scala 328:21]
+    buf_data_in <= _T_496 @[axi4_to_ahb.scala 328:15]
+    node _T_497 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 329:52]
+    node _T_498 = eq(_T_497, UInt<2>("h03")) @[axi4_to_ahb.scala 329:59]
+    node _T_499 = and(buf_aligned_in, _T_498) @[axi4_to_ahb.scala 329:38]
+    node _T_500 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 329:85]
+    node _T_501 = eq(_T_500, UInt<1>("h01")) @[axi4_to_ahb.scala 329:92]
+    node _T_502 = and(_T_499, _T_501) @[axi4_to_ahb.scala 329:72]
+    node _T_503 = bits(_T_502, 0, 0) @[axi4_to_ahb.scala 329:112]
+    node _T_504 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 329:144]
+    wire _T_505 : UInt<8>
+    _T_505 <= UInt<8>("h00")
+    node _T_506 = bits(_T_505, 7, 0) @[axi4_to_ahb.scala 161:43]
+    node _T_507 = eq(_T_506, UInt<8>("h0ff")) @[axi4_to_ahb.scala 161:50]
+    node _T_508 = bits(_T_507, 0, 0) @[Bitwise.scala 72:15]
+    node _T_509 = mux(_T_508, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+    node _T_510 = and(UInt<2>("h03"), _T_509) @[axi4_to_ahb.scala 161:25]
+    node _T_511 = bits(_T_505, 7, 0) @[axi4_to_ahb.scala 162:34]
+    node _T_512 = eq(_T_511, UInt<8>("h0f0")) @[axi4_to_ahb.scala 162:41]
+    node _T_513 = bits(_T_505, 7, 0) @[axi4_to_ahb.scala 162:63]
+    node _T_514 = eq(_T_513, UInt<4>("h0f")) @[axi4_to_ahb.scala 162:70]
+    node _T_515 = or(_T_512, _T_514) @[axi4_to_ahb.scala 162:54]
+    node _T_516 = bits(_T_515, 0, 0) @[Bitwise.scala 72:15]
+    node _T_517 = mux(_T_516, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+    node _T_518 = and(UInt<2>("h02"), _T_517) @[axi4_to_ahb.scala 162:16]
+    node _T_519 = or(_T_510, _T_518) @[axi4_to_ahb.scala 161:65]
+    node _T_520 = bits(_T_505, 7, 0) @[axi4_to_ahb.scala 163:34]
+    node _T_521 = eq(_T_520, UInt<8>("h0c0")) @[axi4_to_ahb.scala 163:41]
+    node _T_522 = bits(_T_505, 7, 0) @[axi4_to_ahb.scala 163:63]
+    node _T_523 = eq(_T_522, UInt<6>("h030")) @[axi4_to_ahb.scala 163:70]
+    node _T_524 = or(_T_521, _T_523) @[axi4_to_ahb.scala 163:54]
+    node _T_525 = bits(_T_505, 7, 0) @[axi4_to_ahb.scala 163:92]
+    node _T_526 = eq(_T_525, UInt<4>("h0c")) @[axi4_to_ahb.scala 163:99]
+    node _T_527 = or(_T_524, _T_526) @[axi4_to_ahb.scala 163:83]
+    node _T_528 = bits(_T_505, 7, 0) @[axi4_to_ahb.scala 163:121]
+    node _T_529 = eq(_T_528, UInt<2>("h03")) @[axi4_to_ahb.scala 163:128]
+    node _T_530 = or(_T_527, _T_529) @[axi4_to_ahb.scala 163:112]
+    node _T_531 = bits(_T_530, 0, 0) @[Bitwise.scala 72:15]
+    node _T_532 = mux(_T_531, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+    node _T_533 = and(UInt<1>("h01"), _T_532) @[axi4_to_ahb.scala 163:16]
+    node _T_534 = or(_T_519, _T_533) @[axi4_to_ahb.scala 162:86]
+    node _T_535 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 329:164]
+    node _T_536 = mux(_T_503, _T_534, _T_535) @[axi4_to_ahb.scala 329:21]
+    buf_size_in <= _T_536 @[axi4_to_ahb.scala 329:15]
+    node _T_537 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 330:32]
+    node _T_538 = eq(_T_537, UInt<1>("h00")) @[axi4_to_ahb.scala 330:39]
+    node _T_539 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 331:17]
+    node _T_540 = eq(_T_539, UInt<1>("h00")) @[axi4_to_ahb.scala 331:24]
+    node _T_541 = or(_T_538, _T_540) @[axi4_to_ahb.scala 330:51]
+    node _T_542 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 331:50]
+    node _T_543 = eq(_T_542, UInt<1>("h01")) @[axi4_to_ahb.scala 331:57]
+    node _T_544 = or(_T_541, _T_543) @[axi4_to_ahb.scala 331:36]
+    node _T_545 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 331:84]
+    node _T_546 = eq(_T_545, UInt<2>("h02")) @[axi4_to_ahb.scala 331:91]
+    node _T_547 = or(_T_544, _T_546) @[axi4_to_ahb.scala 331:70]
+    node _T_548 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 332:18]
+    node _T_549 = eq(_T_548, UInt<2>("h03")) @[axi4_to_ahb.scala 332:25]
+    node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 332:55]
+    node _T_551 = eq(_T_550, UInt<2>("h03")) @[axi4_to_ahb.scala 332:62]
+    node _T_552 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 332:90]
+    node _T_553 = eq(_T_552, UInt<4>("h0c")) @[axi4_to_ahb.scala 332:97]
+    node _T_554 = or(_T_551, _T_553) @[axi4_to_ahb.scala 332:74]
+    node _T_555 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 332:125]
+    node _T_556 = eq(_T_555, UInt<6>("h030")) @[axi4_to_ahb.scala 332:132]
+    node _T_557 = or(_T_554, _T_556) @[axi4_to_ahb.scala 332:109]
+    node _T_558 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 332:161]
+    node _T_559 = eq(_T_558, UInt<8>("h0c0")) @[axi4_to_ahb.scala 332:168]
+    node _T_560 = or(_T_557, _T_559) @[axi4_to_ahb.scala 332:145]
+    node _T_561 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 333:21]
+    node _T_562 = eq(_T_561, UInt<4>("h0f")) @[axi4_to_ahb.scala 333:28]
+    node _T_563 = or(_T_560, _T_562) @[axi4_to_ahb.scala 332:181]
+    node _T_564 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 333:56]
+    node _T_565 = eq(_T_564, UInt<8>("h0f0")) @[axi4_to_ahb.scala 333:63]
+    node _T_566 = or(_T_563, _T_565) @[axi4_to_ahb.scala 333:40]
+    node _T_567 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 333:92]
+    node _T_568 = eq(_T_567, UInt<8>("h0ff")) @[axi4_to_ahb.scala 333:99]
+    node _T_569 = or(_T_566, _T_568) @[axi4_to_ahb.scala 333:76]
+    node _T_570 = and(_T_549, _T_569) @[axi4_to_ahb.scala 332:38]
+    node _T_571 = or(_T_547, _T_570) @[axi4_to_ahb.scala 331:104]
+    buf_aligned_in <= _T_571 @[axi4_to_ahb.scala 330:18]
+    node _T_572 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 335:39]
+    node _T_573 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 335:58]
+    node _T_574 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 335:83]
+    node _T_575 = cat(_T_573, _T_574) @[Cat.scala 29:58]
+    node _T_576 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 335:104]
+    node _T_577 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 335:129]
+    node _T_578 = cat(_T_576, _T_577) @[Cat.scala 29:58]
+    node _T_579 = mux(_T_572, _T_575, _T_578) @[axi4_to_ahb.scala 335:22]
+    io.ahb_haddr <= _T_579 @[axi4_to_ahb.scala 335:16]
+    node _T_580 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 336:39]
+    node _T_581 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15]
+    node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+    node _T_583 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 336:93]
+    node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 336:80]
+    node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58]
+    node _T_586 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15]
+    node _T_587 = mux(_T_586, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+    node _T_588 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 336:148]
+    node _T_589 = and(_T_587, _T_588) @[axi4_to_ahb.scala 336:138]
+    node _T_590 = cat(UInt<1>("h00"), _T_589) @[Cat.scala 29:58]
+    node _T_591 = mux(_T_580, _T_585, _T_590) @[axi4_to_ahb.scala 336:22]
+    io.ahb_hsize <= _T_591 @[axi4_to_ahb.scala 336:16]
+    io.ahb_hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 338:17]
+    io.ahb_hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 339:20]
+    node _T_592 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 340:47]
+    node _T_593 = not(_T_592) @[axi4_to_ahb.scala 340:33]
+    node _T_594 = cat(UInt<1>("h01"), _T_593) @[Cat.scala 29:58]
+    io.ahb_hprot <= _T_594 @[axi4_to_ahb.scala 340:16]
+    node _T_595 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 341:40]
+    node _T_596 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 341:55]
+    node _T_597 = eq(_T_596, UInt<1>("h01")) @[axi4_to_ahb.scala 341:62]
+    node _T_598 = mux(_T_595, _T_597, buf_write) @[axi4_to_ahb.scala 341:23]
+    io.ahb_hwrite <= _T_598 @[axi4_to_ahb.scala 341:17]
+    node _T_599 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 342:28]
+    io.ahb_hwdata <= _T_599 @[axi4_to_ahb.scala 342:17]
+    slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 344:15]
+    node _T_600 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 345:43]
+    node _T_601 = mux(_T_600, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 345:23]
+    node _T_602 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15]
+    node _T_603 = mux(_T_602, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+    node _T_604 = and(_T_603, UInt<2>("h02")) @[axi4_to_ahb.scala 345:88]
+    node _T_605 = cat(_T_601, _T_604) @[Cat.scala 29:58]
+    slave_opc <= _T_605 @[axi4_to_ahb.scala 345:13]
+    node _T_606 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 346:41]
+    node _T_607 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 346:66]
+    node _T_608 = cat(_T_607, _T_607) @[Cat.scala 29:58]
+    node _T_609 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 346:91]
+    node _T_610 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 346:110]
+    node _T_611 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 346:131]
+    node _T_612 = mux(_T_609, _T_610, _T_611) @[axi4_to_ahb.scala 346:79]
+    node _T_613 = mux(_T_606, _T_608, _T_612) @[axi4_to_ahb.scala 346:21]
+    slave_rdata <= _T_613 @[axi4_to_ahb.scala 346:15]
+    node _T_614 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 347:26]
+    slave_tag <= _T_614 @[axi4_to_ahb.scala 347:13]
+    node _T_615 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 349:33]
+    node _T_616 = neq(_T_615, UInt<1>("h00")) @[axi4_to_ahb.scala 349:40]
+    node _T_617 = and(_T_616, io.ahb_hready) @[axi4_to_ahb.scala 349:52]
+    node _T_618 = and(_T_617, io.ahb_hwrite) @[axi4_to_ahb.scala 349:68]
+    last_addr_en <= _T_618 @[axi4_to_ahb.scala 349:16]
+    node _T_619 = and(UInt<1>("h01"), wrbuf_rst) @[axi4_to_ahb.scala 352:58]
+    node _T_620 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 352:114]
+    reg _T_621 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_620 : @[Reg.scala 28:19]
+      _T_621 <= _T_619 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    wrbuf_vld <= _T_621 @[axi4_to_ahb.scala 352:18]
+    node _T_622 = and(UInt<1>("h01"), wrbuf_rst) @[axi4_to_ahb.scala 353:58]
+    node _T_623 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 353:119]
+    reg _T_624 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_623 : @[Reg.scala 28:19]
+      _T_624 <= _T_622 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    wrbuf_data_vld <= _T_624 @[axi4_to_ahb.scala 353:18]
+    node _T_625 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 355:57]
+    node _T_626 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 355:91]
+    reg _T_627 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_626 : @[Reg.scala 28:19]
+      _T_627 <= _T_625 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    wrbuf_tag <= _T_627 @[axi4_to_ahb.scala 355:13]
+    node _T_628 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 356:60]
+    node _T_629 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 356:88]
+    reg _T_630 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_629 : @[Reg.scala 28:19]
+      _T_630 <= _T_628 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    wrbuf_size <= _T_630 @[axi4_to_ahb.scala 356:14]
+    node _T_631 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 358:62]
+    reg _T_632 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_631 : @[Reg.scala 28:19]
+      _T_632 <= io.axi_awaddr @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    wrbuf_addr <= _T_632 @[axi4_to_ahb.scala 358:14]
+    node _T_633 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 359:66]
+    reg _T_634 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_633 : @[Reg.scala 28:19]
+      _T_634 <= io.axi_wdata @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    wrbuf_data <= _T_634 @[axi4_to_ahb.scala 359:14]
+    node _T_635 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 362:27]
+    node _T_636 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 362:60]
+    reg _T_637 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_636 : @[Reg.scala 28:19]
+      _T_637 <= _T_635 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    wrbuf_byteen <= _T_637 @[axi4_to_ahb.scala 361:16]
+    node _T_638 = bits(io.ahb_haddr, 31, 0) @[axi4_to_ahb.scala 365:27]
+    node _T_639 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 365:60]
+    reg _T_640 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_639 : @[Reg.scala 28:19]
+      _T_640 <= _T_638 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    last_bus_addr <= _T_640 @[axi4_to_ahb.scala 364:17]
+    node _T_641 = bits(buf_rst, 0, 0) @[Bitwise.scala 72:15]
+    node _T_642 = mux(_T_641, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+    node _T_643 = and(buf_nxtstate, _T_642) @[axi4_to_ahb.scala 369:28]
+    node _T_644 = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 369:92]
+    reg _T_645 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_644 : @[Reg.scala 28:19]
+      _T_645 <= _T_643 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    buf_state <= _T_645 @[axi4_to_ahb.scala 368:13]
+    node _T_646 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 373:50]
+    reg _T_647 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_646 : @[Reg.scala 28:19]
+      _T_647 <= buf_write_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    buf_write <= _T_647 @[axi4_to_ahb.scala 372:13]
+    node _T_648 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 376:25]
+    node _T_649 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 376:60]
+    reg _T_650 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_649 : @[Reg.scala 28:19]
+      _T_650 <= _T_648 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    buf_tag <= _T_650 @[axi4_to_ahb.scala 375:11]
+    node _T_651 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 379:36]
+    node _T_652 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 379:61]
+    node _T_653 = bits(_T_652, 0, 0) @[axi4_to_ahb.scala 379:78]
+    reg _T_654 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_653 : @[Reg.scala 28:19]
+      _T_654 <= _T_651 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    buf_addr <= _T_654 @[axi4_to_ahb.scala 379:12]
+    node _T_655 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 382:23]
+    node _T_656 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 382:52]
+    reg _T_657 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_656 : @[Reg.scala 28:19]
+      _T_657 <= _T_655 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    buf_size <= _T_657 @[axi4_to_ahb.scala 381:12]
+    node _T_658 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 385:52]
+    reg _T_659 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_658 : @[Reg.scala 28:19]
+      _T_659 <= buf_aligned_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    buf_aligned <= _T_659 @[axi4_to_ahb.scala 384:15]
+    node _T_660 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 388:25]
+    node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 388:54]
+    reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_661 : @[Reg.scala 28:19]
+      _T_662 <= _T_660 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    buf_byteen <= _T_662 @[axi4_to_ahb.scala 387:14]
+    node _T_663 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 391:36]
+    node _T_664 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 391:66]
+    node _T_665 = bits(_T_664, 0, 0) @[axi4_to_ahb.scala 391:89]
+    reg _T_666 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_665 : @[Reg.scala 28:19]
+      _T_666 <= _T_663 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    buf_data <= _T_666 @[axi4_to_ahb.scala 391:12]
+    node _T_667 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 394:50]
+    reg _T_668 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_667 : @[Reg.scala 28:19]
+      _T_668 <= buf_write @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    slvbuf_write <= _T_668 @[axi4_to_ahb.scala 393:16]
+    node _T_669 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 397:22]
+    node _T_670 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 397:60]
+    reg _T_671 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_670 : @[Reg.scala 28:19]
+      _T_671 <= _T_669 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    slvbuf_tag <= _T_671 @[axi4_to_ahb.scala 396:14]
+    node _T_672 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 400:59]
+    reg _T_673 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_672 : @[Reg.scala 28:19]
+      _T_673 <= slvbuf_error_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    slvbuf_error <= _T_673 @[axi4_to_ahb.scala 399:16]
+    node _T_674 = and(UInt<1>("h01"), cmd_done_rst) @[axi4_to_ahb.scala 404:22]
+    node _T_675 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 404:81]
+    reg _T_676 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_675 : @[Reg.scala 28:19]
+      _T_676 <= _T_674 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    cmd_doneQ <= _T_676 @[axi4_to_ahb.scala 403:13]
+    node _T_677 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 408:31]
+    node _T_678 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 408:70]
+    reg _T_679 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_678 : @[Reg.scala 28:19]
+      _T_679 <= _T_677 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    buf_cmd_byte_ptrQ <= _T_679 @[axi4_to_ahb.scala 407:21]
+    reg _T_680 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 413:12]
+    _T_680 <= io.ahb_hready @[axi4_to_ahb.scala 413:12]
+    ahb_hready_q <= _T_680 @[axi4_to_ahb.scala 412:16]
+    node _T_681 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 416:26]
+    reg _T_682 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 416:12]
+    _T_682 <= _T_681 @[axi4_to_ahb.scala 416:12]
+    ahb_htrans_q <= _T_682 @[axi4_to_ahb.scala 415:16]
+    reg _T_683 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 419:12]
+    _T_683 <= io.ahb_hwrite @[axi4_to_ahb.scala 419:12]
+    ahb_hwrite_q <= _T_683 @[axi4_to_ahb.scala 418:16]
+    reg _T_684 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 422:12]
+    _T_684 <= io.ahb_hresp @[axi4_to_ahb.scala 422:12]
+    ahb_hresp_q <= _T_684 @[axi4_to_ahb.scala 421:15]
+    node _T_685 = bits(io.ahb_hrdata, 63, 0) @[axi4_to_ahb.scala 425:26]
+    reg _T_686 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 425:12]
+    _T_686 <= _T_685 @[axi4_to_ahb.scala 425:12]
+    ahb_hrdata_q <= _T_686 @[axi4_to_ahb.scala 424:16]
+    node _T_687 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 428:43]
+    node _T_688 = or(_T_687, io.clk_override) @[axi4_to_ahb.scala 428:58]
+    node _T_689 = and(io.bus_clk_en, _T_688) @[axi4_to_ahb.scala 428:30]
+    buf_clken <= _T_689 @[axi4_to_ahb.scala 428:13]
+    node _T_690 = bits(io.ahb_htrans, 1, 1) @[axi4_to_ahb.scala 429:69]
+    node _T_691 = and(io.ahb_hready, _T_690) @[axi4_to_ahb.scala 429:54]
+    node _T_692 = or(_T_691, io.clk_override) @[axi4_to_ahb.scala 429:74]
+    node _T_693 = and(io.bus_clk_en, _T_692) @[axi4_to_ahb.scala 429:36]
+    ahbm_addr_clken <= _T_693 @[axi4_to_ahb.scala 429:19]
+    node _T_694 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 430:50]
+    node _T_695 = or(_T_694, io.clk_override) @[axi4_to_ahb.scala 430:60]
+    node _T_696 = and(io.bus_clk_en, _T_695) @[axi4_to_ahb.scala 430:36]
+    ahbm_data_clken <= _T_696 @[axi4_to_ahb.scala 430:19]
+    inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 483:22]
+    rvclkhdr_2.clock <= clock
+    rvclkhdr_2.reset <= reset
+    rvclkhdr_2.io.clk <= clock @[el2_lib.scala 484:17]
+    rvclkhdr_2.io.en <= buf_clken @[el2_lib.scala 485:16]
+    rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
+    buf_clk <= rvclkhdr_2.io.l1clk @[axi4_to_ahb.scala 433:11]
+    inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 483:22]
+    rvclkhdr_3.clock <= clock
+    rvclkhdr_3.reset <= reset
+    rvclkhdr_3.io.clk <= clock @[el2_lib.scala 484:17]
+    rvclkhdr_3.io.en <= io.bus_clk_en @[el2_lib.scala 485:16]
+    rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
+    ahbm_clk <= rvclkhdr_3.io.l1clk @[axi4_to_ahb.scala 434:12]
+    inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 483:22]
+    rvclkhdr_4.clock <= clock
+    rvclkhdr_4.reset <= reset
+    rvclkhdr_4.io.clk <= clock @[el2_lib.scala 484:17]
+    rvclkhdr_4.io.en <= ahbm_addr_clken @[el2_lib.scala 485:16]
+    rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
+    ahbm_addr_clk <= rvclkhdr_4.io.l1clk @[axi4_to_ahb.scala 435:17]
+    inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 483:22]
+    rvclkhdr_5.clock <= clock
+    rvclkhdr_5.reset <= reset
+    rvclkhdr_5.io.clk <= clock @[el2_lib.scala 484:17]
+    rvclkhdr_5.io.en <= ahbm_data_clken @[el2_lib.scala 485:16]
+    rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
+    ahbm_data_clk <= rvclkhdr_5.io.l1clk @[axi4_to_ahb.scala 436:17]
+    
diff --git a/axi4_to_ahb.v b/axi4_to_ahb.v
new file mode 100644
index 00000000..f9bcf2e9
--- /dev/null
+++ b/axi4_to_ahb.v
@@ -0,0 +1,438 @@
+module rvclkhdr(
+  output  io_l1clk,
+  input   io_clk,
+  input   io_en,
+  input   io_scan_mode
+);
+  wire  clkhdr_Q; // @[el2_lib.scala 474:26]
+  wire  clkhdr_CK; // @[el2_lib.scala 474:26]
+  wire  clkhdr_EN; // @[el2_lib.scala 474:26]
+  wire  clkhdr_SE; // @[el2_lib.scala 474:26]
+  TEC_RV_ICG clkhdr ( // @[el2_lib.scala 474:26]
+    .Q(clkhdr_Q),
+    .CK(clkhdr_CK),
+    .EN(clkhdr_EN),
+    .SE(clkhdr_SE)
+  );
+  assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14]
+  assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18]
+  assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18]
+  assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18]
+endmodule
+module axi4_to_ahb(
+  input         clock,
+  input         reset,
+  input         io_scan_mode,
+  input         io_bus_clk_en,
+  input         io_clk_override,
+  input         io_axi_awvalid,
+  input         io_axi_awid,
+  input  [31:0] io_axi_awaddr,
+  input  [2:0]  io_axi_awsize,
+  input  [2:0]  io_axi_awprot,
+  input         io_axi_wvalid,
+  input  [63:0] io_axi_wdata,
+  input  [7:0]  io_axi_wstrb,
+  input         io_axi_wlast,
+  input         io_axi_bready,
+  input         io_axi_arvalid,
+  input         io_axi_arid,
+  input  [31:0] io_axi_araddr,
+  input  [2:0]  io_axi_arsize,
+  input  [2:0]  io_axi_arprot,
+  input         io_axi_rready,
+  input  [63:0] io_ahb_hrdata,
+  input         io_ahb_hready,
+  input         io_ahb_hresp,
+  output        io_axi_awready,
+  output        io_axi_wready,
+  output        io_axi_bvalid,
+  output [1:0]  io_axi_bresp,
+  output        io_axi_bid,
+  output        io_axi_arready,
+  output        io_axi_rvalid,
+  output        io_axi_rid,
+  output [31:0] io_axi_rdata,
+  output [1:0]  io_axi_rresp,
+  output        io_axi_rlast,
+  output [31:0] io_ahb_haddr,
+  output [2:0]  io_ahb_hburst,
+  output        io_ahb_hmastlock,
+  output [3:0]  io_ahb_hprot,
+  output [2:0]  io_ahb_hsize,
+  output [1:0]  io_ahb_htrans,
+  output        io_ahb_hwrite,
+  output [63:0] io_ahb_hwdata
+);
+`ifdef RANDOMIZE_REG_INIT
+  reg [31:0] _RAND_0;
+  reg [31:0] _RAND_1;
+  reg [31:0] _RAND_2;
+  reg [31:0] _RAND_3;
+  reg [31:0] _RAND_4;
+  reg [31:0] _RAND_5;
+  reg [63:0] _RAND_6;
+  reg [63:0] _RAND_7;
+  reg [63:0] _RAND_8;
+  reg [31:0] _RAND_9;
+  reg [31:0] _RAND_10;
+`endif // RANDOMIZE_REG_INIT
+  wire  rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22]
+  wire  rvclkhdr_io_clk; // @[el2_lib.scala 483:22]
+  wire  rvclkhdr_io_en; // @[el2_lib.scala 483:22]
+  wire  rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22]
+  wire  rvclkhdr_1_io_l1clk; // @[el2_lib.scala 483:22]
+  wire  rvclkhdr_1_io_clk; // @[el2_lib.scala 483:22]
+  wire  rvclkhdr_1_io_en; // @[el2_lib.scala 483:22]
+  wire  rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 483:22]
+  wire  rvclkhdr_2_io_l1clk; // @[el2_lib.scala 483:22]
+  wire  rvclkhdr_2_io_clk; // @[el2_lib.scala 483:22]
+  wire  rvclkhdr_2_io_en; // @[el2_lib.scala 483:22]
+  wire  rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 483:22]
+  wire  rvclkhdr_3_io_l1clk; // @[el2_lib.scala 483:22]
+  wire  rvclkhdr_3_io_clk; // @[el2_lib.scala 483:22]
+  wire  rvclkhdr_3_io_en; // @[el2_lib.scala 483:22]
+  wire  rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 483:22]
+  wire  rvclkhdr_4_io_l1clk; // @[el2_lib.scala 483:22]
+  wire  rvclkhdr_4_io_clk; // @[el2_lib.scala 483:22]
+  wire  rvclkhdr_4_io_en; // @[el2_lib.scala 483:22]
+  wire  rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 483:22]
+  wire  rvclkhdr_5_io_l1clk; // @[el2_lib.scala 483:22]
+  wire  rvclkhdr_5_io_clk; // @[el2_lib.scala 483:22]
+  wire  rvclkhdr_5_io_en; // @[el2_lib.scala 483:22]
+  wire  rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 483:22]
+  reg [2:0] buf_nxtstate; // @[axi4_to_ahb.scala 63:29]
+  wire  wrbuf_en = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 183:30]
+  wire  bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 83:21 axi4_to_ahb.scala 216:11]
+  reg  wrbuf_vld; // @[Reg.scala 27:20]
+  reg  wrbuf_data_vld; // @[Reg.scala 27:20]
+  wire  wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 193:27]
+  wire  master_valid = wr_cmd_vld | io_axi_arvalid; // @[axi4_to_ahb.scala 194:30]
+  wire [1:0] _T_28 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 196:20]
+  wire [2:0] master_opc = {{1'd0}, _T_28}; // @[axi4_to_ahb.scala 196:14]
+  wire  _T_149 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 252:89]
+  wire  _T_150 = master_valid & _T_149; // @[axi4_to_ahb.scala 252:70]
+  wire  _T_151 = ~_T_150; // @[axi4_to_ahb.scala 252:55]
+  wire  wrbuf_data_en = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 184:34]
+  wire  _T_8 = ~wrbuf_en; // @[axi4_to_ahb.scala 186:33]
+  wire  wrbuf_rst = _T_150 & _T_8; // @[axi4_to_ahb.scala 186:31]
+  wire  _T_11 = wrbuf_vld & _T_151; // @[axi4_to_ahb.scala 188:33]
+  wire  _T_15 = wrbuf_data_vld & _T_151; // @[axi4_to_ahb.scala 189:37]
+  reg [31:0] wrbuf_addr; // @[Reg.scala 27:20]
+  wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_araddr; // @[axi4_to_ahb.scala 197:21]
+  reg [2:0] wrbuf_size; // @[Reg.scala 27:20]
+  wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_arsize; // @[axi4_to_ahb.scala 198:21]
+  reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20]
+  reg [63:0] wrbuf_data; // @[Reg.scala 27:20]
+  wire  buf_clk = rvclkhdr_2_io_l1clk; // @[axi4_to_ahb.scala 151:21 axi4_to_ahb.scala 433:11]
+  reg [63:0] buf_data; // @[Reg.scala 27:20]
+  wire  ahbm_data_clk = rvclkhdr_5_io_l1clk; // @[axi4_to_ahb.scala 155:27 axi4_to_ahb.scala 436:17]
+  reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 425:12]
+  wire  _T_60 = wrbuf_en | wrbuf_data_en; // @[axi4_to_ahb.scala 214:74]
+  wire  _T_69 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 230:54]
+  wire  buf_data_wr_en = master_valid & _T_69; // @[axi4_to_ahb.scala 230:38]
+  wire [2:0] _T_100 = wrbuf_byteen[7] ? 3'h7 : 3'h0; // @[Mux.scala 98:16]
+  wire [2:0] _T_101 = wrbuf_byteen[6] ? 3'h6 : _T_100; // @[Mux.scala 98:16]
+  wire [2:0] _T_102 = wrbuf_byteen[5] ? 3'h5 : _T_101; // @[Mux.scala 98:16]
+  wire [2:0] _T_103 = wrbuf_byteen[4] ? 3'h4 : _T_102; // @[Mux.scala 98:16]
+  wire [2:0] _T_104 = wrbuf_byteen[3] ? 3'h3 : _T_103; // @[Mux.scala 98:16]
+  wire [2:0] _T_105 = wrbuf_byteen[2] ? 3'h2 : _T_104; // @[Mux.scala 98:16]
+  wire [2:0] _T_106 = wrbuf_byteen[1] ? 3'h1 : _T_105; // @[Mux.scala 98:16]
+  wire [2:0] _T_107 = wrbuf_byteen[0] ? 3'h0 : _T_106; // @[Mux.scala 98:16]
+  wire [2:0] buf_cmd_byte_ptr = _T_149 ? _T_107 : master_addr[2:0]; // @[axi4_to_ahb.scala 233:30]
+  wire [1:0] _T_113 = master_valid ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  wire  _T_117 = master_opc == 3'h0; // @[axi4_to_ahb.scala 240:61]
+  reg [31:0] buf_addr; // @[Reg.scala 27:20]
+  wire  _T_540 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 331:24]
+  wire  _T_541 = _T_117 | _T_540; // @[axi4_to_ahb.scala 330:51]
+  wire  _T_543 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 331:57]
+  wire  _T_544 = _T_541 | _T_543; // @[axi4_to_ahb.scala 331:36]
+  wire  _T_546 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 331:91]
+  wire  _T_547 = _T_544 | _T_546; // @[axi4_to_ahb.scala 331:70]
+  wire  _T_549 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 332:25]
+  wire  _T_551 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 332:62]
+  wire  _T_553 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 332:97]
+  wire  _T_554 = _T_551 | _T_553; // @[axi4_to_ahb.scala 332:74]
+  wire  _T_556 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 332:132]
+  wire  _T_557 = _T_554 | _T_556; // @[axi4_to_ahb.scala 332:109]
+  wire  _T_559 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 332:168]
+  wire  _T_560 = _T_557 | _T_559; // @[axi4_to_ahb.scala 332:145]
+  wire  _T_562 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 333:28]
+  wire  _T_563 = _T_560 | _T_562; // @[axi4_to_ahb.scala 332:181]
+  wire  _T_565 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 333:63]
+  wire  _T_566 = _T_563 | _T_565; // @[axi4_to_ahb.scala 333:40]
+  wire  _T_568 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 333:99]
+  wire  _T_569 = _T_566 | _T_568; // @[axi4_to_ahb.scala 333:76]
+  wire  _T_570 = _T_549 & _T_569; // @[axi4_to_ahb.scala 332:38]
+  wire  buf_aligned_in = _T_547 | _T_570; // @[axi4_to_ahb.scala 331:104]
+  wire  _T_452 = buf_aligned_in & _T_149; // @[axi4_to_ahb.scala 325:55]
+  wire [2:0] _T_489 = _T_452 ? 3'h0 : master_addr[2:0]; // @[axi4_to_ahb.scala 325:38]
+  wire [34:0] _T_490 = {master_addr,_T_489}; // @[Cat.scala 29:58]
+  wire  _T_499 = buf_aligned_in & _T_549; // @[axi4_to_ahb.scala 329:38]
+  wire  _T_502 = _T_499 & _T_149; // @[axi4_to_ahb.scala 329:72]
+  wire [1:0] _T_536 = _T_502 ? 2'h0 : master_size[1:0]; // @[axi4_to_ahb.scala 329:21]
+  wire [31:0] _T_575 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58]
+  wire [31:0] _T_578 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58]
+  wire [1:0] _T_582 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  wire [2:0] buf_size_in = {{1'd0}, _T_536}; // @[axi4_to_ahb.scala 329:15]
+  wire [1:0] _T_584 = _T_582 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 336:80]
+  wire [2:0] _T_585 = {1'h0,_T_584}; // @[Cat.scala 29:58]
+  wire  _T_593 = ~io_axi_arprot[2]; // @[axi4_to_ahb.scala 340:33]
+  wire [1:0] _T_594 = {1'h1,_T_593}; // @[Cat.scala 29:58]
+  reg  buf_write; // @[Reg.scala 27:20]
+  wire [31:0] buf_addr_in = _T_490[31:0]; // @[axi4_to_ahb.scala 325:15]
+  wire  _T_652 = master_valid & io_bus_clk_en; // @[axi4_to_ahb.scala 379:61]
+  wire  _T_664 = buf_data_wr_en & io_bus_clk_en; // @[axi4_to_ahb.scala 391:66]
+  wire  _T_688 = master_valid | io_clk_override; // @[axi4_to_ahb.scala 428:58]
+  wire  _T_691 = io_ahb_hready & io_ahb_htrans[1]; // @[axi4_to_ahb.scala 429:54]
+  wire  _T_692 = _T_691 | io_clk_override; // @[axi4_to_ahb.scala 429:74]
+  rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22]
+    .io_l1clk(rvclkhdr_io_l1clk),
+    .io_clk(rvclkhdr_io_clk),
+    .io_en(rvclkhdr_io_en),
+    .io_scan_mode(rvclkhdr_io_scan_mode)
+  );
+  rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 483:22]
+    .io_l1clk(rvclkhdr_1_io_l1clk),
+    .io_clk(rvclkhdr_1_io_clk),
+    .io_en(rvclkhdr_1_io_en),
+    .io_scan_mode(rvclkhdr_1_io_scan_mode)
+  );
+  rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 483:22]
+    .io_l1clk(rvclkhdr_2_io_l1clk),
+    .io_clk(rvclkhdr_2_io_clk),
+    .io_en(rvclkhdr_2_io_en),
+    .io_scan_mode(rvclkhdr_2_io_scan_mode)
+  );
+  rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 483:22]
+    .io_l1clk(rvclkhdr_3_io_l1clk),
+    .io_clk(rvclkhdr_3_io_clk),
+    .io_en(rvclkhdr_3_io_en),
+    .io_scan_mode(rvclkhdr_3_io_scan_mode)
+  );
+  rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 483:22]
+    .io_l1clk(rvclkhdr_4_io_l1clk),
+    .io_clk(rvclkhdr_4_io_clk),
+    .io_en(rvclkhdr_4_io_en),
+    .io_scan_mode(rvclkhdr_4_io_scan_mode)
+  );
+  rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 483:22]
+    .io_l1clk(rvclkhdr_5_io_l1clk),
+    .io_clk(rvclkhdr_5_io_clk),
+    .io_en(rvclkhdr_5_io_en),
+    .io_scan_mode(rvclkhdr_5_io_scan_mode)
+  );
+  assign io_axi_awready = ~_T_11; // @[axi4_to_ahb.scala 188:18]
+  assign io_axi_wready = ~_T_15; // @[axi4_to_ahb.scala 189:17]
+  assign io_axi_bvalid = 1'h0; // @[axi4_to_ahb.scala 203:17]
+  assign io_axi_bresp = 2'h0; // @[axi4_to_ahb.scala 204:16]
+  assign io_axi_bid = 1'h0; // @[axi4_to_ahb.scala 205:14]
+  assign io_axi_arready = ~wr_cmd_vld; // @[axi4_to_ahb.scala 190:18]
+  assign io_axi_rvalid = 1'h0; // @[axi4_to_ahb.scala 207:17]
+  assign io_axi_rid = 1'h0; // @[axi4_to_ahb.scala 209:14]
+  assign io_axi_rdata = ahb_hrdata_q[31:0]; // @[axi4_to_ahb.scala 210:16]
+  assign io_axi_rresp = 2'h0; // @[axi4_to_ahb.scala 208:16]
+  assign io_axi_rlast = 1'h1; // @[axi4_to_ahb.scala 191:16]
+  assign io_ahb_haddr = master_valid ? _T_575 : _T_578; // @[axi4_to_ahb.scala 335:16]
+  assign io_ahb_hburst = 3'h0; // @[axi4_to_ahb.scala 338:17]
+  assign io_ahb_hmastlock = 1'h0; // @[axi4_to_ahb.scala 339:20]
+  assign io_ahb_hprot = {{2'd0}, _T_594}; // @[axi4_to_ahb.scala 340:16]
+  assign io_ahb_hsize = master_valid ? _T_585 : 3'h0; // @[axi4_to_ahb.scala 336:16]
+  assign io_ahb_htrans = _T_113 & 2'h2; // @[axi4_to_ahb.scala 220:17 axi4_to_ahb.scala 236:21 axi4_to_ahb.scala 248:21 axi4_to_ahb.scala 263:21 axi4_to_ahb.scala 273:21 axi4_to_ahb.scala 293:21 axi4_to_ahb.scala 307:21]
+  assign io_ahb_hwrite = master_valid ? _T_149 : buf_write; // @[axi4_to_ahb.scala 341:17]
+  assign io_ahb_hwdata = buf_data; // @[axi4_to_ahb.scala 342:17]
+  assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17]
+  assign rvclkhdr_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16]
+  assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
+  assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 484:17]
+  assign rvclkhdr_1_io_en = io_bus_clk_en & _T_60; // @[el2_lib.scala 485:16]
+  assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
+  assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 484:17]
+  assign rvclkhdr_2_io_en = io_bus_clk_en & _T_688; // @[el2_lib.scala 485:16]
+  assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
+  assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 484:17]
+  assign rvclkhdr_3_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16]
+  assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
+  assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 484:17]
+  assign rvclkhdr_4_io_en = io_bus_clk_en & _T_692; // @[el2_lib.scala 485:16]
+  assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
+  assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 484:17]
+  assign rvclkhdr_5_io_en = io_bus_clk_en & io_clk_override; // @[el2_lib.scala 485:16]
+  assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+  integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+  `ifdef RANDOMIZE
+    `ifdef INIT_RANDOM
+      `INIT_RANDOM
+    `endif
+    `ifndef VERILATOR
+      `ifdef RANDOMIZE_DELAY
+        #`RANDOMIZE_DELAY begin end
+      `else
+        #0.002 begin end
+      `endif
+    `endif
+`ifdef RANDOMIZE_REG_INIT
+  _RAND_0 = {1{`RANDOM}};
+  buf_nxtstate = _RAND_0[2:0];
+  _RAND_1 = {1{`RANDOM}};
+  wrbuf_vld = _RAND_1[0:0];
+  _RAND_2 = {1{`RANDOM}};
+  wrbuf_data_vld = _RAND_2[0:0];
+  _RAND_3 = {1{`RANDOM}};
+  wrbuf_addr = _RAND_3[31:0];
+  _RAND_4 = {1{`RANDOM}};
+  wrbuf_size = _RAND_4[2:0];
+  _RAND_5 = {1{`RANDOM}};
+  wrbuf_byteen = _RAND_5[7:0];
+  _RAND_6 = {2{`RANDOM}};
+  wrbuf_data = _RAND_6[63:0];
+  _RAND_7 = {2{`RANDOM}};
+  buf_data = _RAND_7[63:0];
+  _RAND_8 = {2{`RANDOM}};
+  ahb_hrdata_q = _RAND_8[63:0];
+  _RAND_9 = {1{`RANDOM}};
+  buf_addr = _RAND_9[31:0];
+  _RAND_10 = {1{`RANDOM}};
+  buf_write = _RAND_10[0:0];
+`endif // RANDOMIZE_REG_INIT
+  if (reset) begin
+    buf_nxtstate = 3'h0;
+  end
+  if (reset) begin
+    wrbuf_vld = 1'h0;
+  end
+  if (reset) begin
+    wrbuf_data_vld = 1'h0;
+  end
+  if (reset) begin
+    wrbuf_addr = 32'h0;
+  end
+  if (reset) begin
+    wrbuf_size = 3'h0;
+  end
+  if (reset) begin
+    wrbuf_byteen = 8'h0;
+  end
+  if (reset) begin
+    wrbuf_data = 64'h0;
+  end
+  if (reset) begin
+    buf_data = 64'h0;
+  end
+  if (reset) begin
+    ahb_hrdata_q = 64'h0;
+  end
+  if (reset) begin
+    buf_addr = 32'h0;
+  end
+  if (reset) begin
+    buf_write = 1'h0;
+  end
+  `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      buf_nxtstate <= 3'h0;
+    end else if (_T_149) begin
+      buf_nxtstate <= 3'h2;
+    end else begin
+      buf_nxtstate <= 3'h1;
+    end
+  end
+  always @(posedge bus_clk or posedge reset) begin
+    if (reset) begin
+      wrbuf_vld <= 1'h0;
+    end else if (wrbuf_en) begin
+      wrbuf_vld <= wrbuf_rst;
+    end
+  end
+  always @(posedge bus_clk or posedge reset) begin
+    if (reset) begin
+      wrbuf_data_vld <= 1'h0;
+    end else if (wrbuf_data_en) begin
+      wrbuf_data_vld <= wrbuf_rst;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      wrbuf_addr <= 32'h0;
+    end else if (wrbuf_en) begin
+      wrbuf_addr <= io_axi_awaddr;
+    end
+  end
+  always @(posedge bus_clk or posedge reset) begin
+    if (reset) begin
+      wrbuf_size <= 3'h0;
+    end else if (wrbuf_en) begin
+      wrbuf_size <= io_axi_awsize;
+    end
+  end
+  always @(posedge bus_clk or posedge reset) begin
+    if (reset) begin
+      wrbuf_byteen <= 8'h0;
+    end else if (wrbuf_data_en) begin
+      wrbuf_byteen <= io_axi_wstrb;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      wrbuf_data <= 64'h0;
+    end else if (wrbuf_data_en) begin
+      wrbuf_data <= io_axi_wdata;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      buf_data <= 64'h0;
+    end else if (_T_664) begin
+      buf_data <= wrbuf_data;
+    end
+  end
+  always @(posedge ahbm_data_clk or posedge reset) begin
+    if (reset) begin
+      ahb_hrdata_q <= 64'h0;
+    end else begin
+      ahb_hrdata_q <= io_ahb_hrdata;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      buf_addr <= 32'h0;
+    end else if (_T_652) begin
+      buf_addr <= buf_addr_in;
+    end
+  end
+  always @(posedge buf_clk or posedge reset) begin
+    if (reset) begin
+      buf_write <= 1'h0;
+    end else if (master_valid) begin
+      buf_write <= _T_149;
+    end
+  end
+endmodule
diff --git a/dmi_wrapper.anno.json b/dmi_wrapper.anno.json
new file mode 100644
index 00000000..a82cb7f9
--- /dev/null
+++ b/dmi_wrapper.anno.json
@@ -0,0 +1,18 @@
+[
+  {
+    "class":"firrtl.EmitCircuitAnnotation",
+    "emitter":"firrtl.VerilogEmitter"
+  },
+  {
+    "class":"firrtl.options.TargetDirAnnotation",
+    "directory":"."
+  },
+  {
+    "class":"firrtl.options.OutputAnnotationFileAnnotation",
+    "file":"dmi_wrapper"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
+    "targetDir":"."
+  }
+]
\ No newline at end of file
diff --git a/dmi_wrapper.fir b/dmi_wrapper.fir
new file mode 100644
index 00000000..879c4a7b
--- /dev/null
+++ b/dmi_wrapper.fir
@@ -0,0 +1,349 @@
+;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
+circuit dmi_wrapper : 
+  module rvjtag_tap : 
+    input clock : Clock
+    input reset : AsyncReset
+    output io : {flip trst : AsyncReset, flip tck : Clock, flip tms : UInt<1>, flip tdi : UInt<1>, dmi_reset : UInt<1>, dmi_hard_reset : UInt<1>, flip rd_status : UInt<2>, flip dmi_stat : UInt<2>, flip idle : UInt<3>, flip version : UInt<4>, flip jtag_id : UInt<31>, flip rd_data : UInt<32>, tdo : UInt<1>, tdoEnable : UInt<1>, wr_en : UInt<1>, rd_en : UInt<1>, wr_data : UInt<32>, wr_addr : UInt<0>}
+    
+    wire nsr : UInt<41>
+    nsr <= UInt<41>("h00")
+    reg sr : UInt, io.tck with : (reset => (io.trst, UInt<1>("h00"))) @[rvjtag_tap.scala 32:55]
+    sr <= nsr @[rvjtag_tap.scala 32:55]
+    wire dr : UInt<41>
+    dr <= UInt<41>("h00")
+    wire nstate : UInt<4>
+    nstate <= UInt<4>("h00")
+    reg state : UInt, io.tck with : (reset => (io.trst, UInt<4>("h00"))) @[rvjtag_tap.scala 39:57]
+    state <= nstate @[rvjtag_tap.scala 39:57]
+    wire ir : UInt<5>
+    ir <= UInt<5>("h00")
+    wire jtag_reset : UInt<1>
+    jtag_reset <= UInt<1>("h00")
+    wire shift_dr : UInt<1>
+    shift_dr <= UInt<1>("h00")
+    wire pause_dr : UInt<1>
+    pause_dr <= UInt<1>("h00")
+    wire update_dr : UInt<1>
+    update_dr <= UInt<1>("h00")
+    wire capture_dr : UInt<1>
+    capture_dr <= UInt<1>("h00")
+    wire shift_ir : UInt<1>
+    shift_ir <= UInt<1>("h00")
+    wire pause_ir : UInt<1>
+    pause_ir <= UInt<1>("h00")
+    wire update_ir : UInt<1>
+    update_ir <= UInt<1>("h00")
+    wire capture_ir : UInt<1>
+    capture_ir <= UInt<1>("h00")
+    wire dr_en : UInt<2>
+    dr_en <= UInt<1>("h00")
+    wire devid_sel : UInt<1>
+    devid_sel <= UInt<1>("h00")
+    node _T = eq(UInt<4>("h00"), state) @[Conditional.scala 37:30]
+    when _T : @[Conditional.scala 40:58]
+      node _T_1 = mux(io.tms, UInt<4>("h00"), UInt<4>("h01")) @[rvjtag_tap.scala 55:46]
+      nstate <= _T_1 @[rvjtag_tap.scala 55:40]
+      jtag_reset <= UInt<1>("h01") @[rvjtag_tap.scala 56:18]
+      skip @[Conditional.scala 40:58]
+    else : @[Conditional.scala 39:67]
+      node _T_2 = eq(UInt<4>("h01"), state) @[Conditional.scala 37:30]
+      when _T_2 : @[Conditional.scala 39:67]
+        node _T_3 = mux(io.tms, UInt<4>("h02"), UInt<4>("h01")) @[rvjtag_tap.scala 57:47]
+        nstate <= _T_3 @[rvjtag_tap.scala 57:41]
+        skip @[Conditional.scala 39:67]
+      else : @[Conditional.scala 39:67]
+        node _T_4 = eq(UInt<4>("h02"), state) @[Conditional.scala 37:30]
+        when _T_4 : @[Conditional.scala 39:67]
+          node _T_5 = mux(io.tms, UInt<4>("h09"), UInt<4>("h03")) @[rvjtag_tap.scala 58:47]
+          nstate <= _T_5 @[rvjtag_tap.scala 58:41]
+          skip @[Conditional.scala 39:67]
+        else : @[Conditional.scala 39:67]
+          node _T_6 = eq(UInt<4>("h03"), state) @[Conditional.scala 37:30]
+          when _T_6 : @[Conditional.scala 39:67]
+            node _T_7 = mux(io.tms, UInt<4>("h05"), UInt<4>("h04")) @[rvjtag_tap.scala 59:47]
+            nstate <= _T_7 @[rvjtag_tap.scala 59:41]
+            capture_dr <= UInt<1>("h01") @[rvjtag_tap.scala 60:18]
+            skip @[Conditional.scala 39:67]
+          else : @[Conditional.scala 39:67]
+            node _T_8 = eq(UInt<4>("h04"), state) @[Conditional.scala 37:30]
+            when _T_8 : @[Conditional.scala 39:67]
+              node _T_9 = mux(io.tms, UInt<4>("h05"), UInt<4>("h04")) @[rvjtag_tap.scala 61:47]
+              nstate <= _T_9 @[rvjtag_tap.scala 61:41]
+              shift_dr <= UInt<1>("h01") @[rvjtag_tap.scala 62:16]
+              skip @[Conditional.scala 39:67]
+            else : @[Conditional.scala 39:67]
+              node _T_10 = eq(UInt<4>("h05"), state) @[Conditional.scala 37:30]
+              when _T_10 : @[Conditional.scala 39:67]
+                node _T_11 = mux(io.tms, UInt<4>("h08"), UInt<4>("h06")) @[rvjtag_tap.scala 63:47]
+                nstate <= _T_11 @[rvjtag_tap.scala 63:41]
+                skip @[Conditional.scala 39:67]
+              else : @[Conditional.scala 39:67]
+                node _T_12 = eq(UInt<4>("h06"), state) @[Conditional.scala 37:30]
+                when _T_12 : @[Conditional.scala 39:67]
+                  node _T_13 = mux(io.tms, UInt<4>("h07"), UInt<4>("h06")) @[rvjtag_tap.scala 64:47]
+                  nstate <= _T_13 @[rvjtag_tap.scala 64:41]
+                  pause_dr <= UInt<1>("h01") @[rvjtag_tap.scala 65:16]
+                  skip @[Conditional.scala 39:67]
+                else : @[Conditional.scala 39:67]
+                  node _T_14 = eq(UInt<4>("h07"), state) @[Conditional.scala 37:30]
+                  when _T_14 : @[Conditional.scala 39:67]
+                    node _T_15 = mux(io.tms, UInt<4>("h08"), UInt<4>("h04")) @[rvjtag_tap.scala 66:47]
+                    nstate <= _T_15 @[rvjtag_tap.scala 66:41]
+                    skip @[Conditional.scala 39:67]
+                  else : @[Conditional.scala 39:67]
+                    node _T_16 = eq(UInt<4>("h08"), state) @[Conditional.scala 37:30]
+                    when _T_16 : @[Conditional.scala 39:67]
+                      node _T_17 = mux(io.tms, UInt<4>("h02"), UInt<4>("h01")) @[rvjtag_tap.scala 67:47]
+                      nstate <= _T_17 @[rvjtag_tap.scala 67:41]
+                      update_dr <= UInt<1>("h01") @[rvjtag_tap.scala 68:17]
+                      skip @[Conditional.scala 39:67]
+                    else : @[Conditional.scala 39:67]
+                      node _T_18 = eq(UInt<4>("h09"), state) @[Conditional.scala 37:30]
+                      when _T_18 : @[Conditional.scala 39:67]
+                        node _T_19 = mux(io.tms, UInt<4>("h00"), UInt<4>("h0a")) @[rvjtag_tap.scala 69:47]
+                        nstate <= _T_19 @[rvjtag_tap.scala 69:41]
+                        skip @[Conditional.scala 39:67]
+                      else : @[Conditional.scala 39:67]
+                        node _T_20 = eq(UInt<4>("h0a"), state) @[Conditional.scala 37:30]
+                        when _T_20 : @[Conditional.scala 39:67]
+                          node _T_21 = mux(io.tms, UInt<4>("h0c"), UInt<4>("h0b")) @[rvjtag_tap.scala 70:47]
+                          nstate <= _T_21 @[rvjtag_tap.scala 70:41]
+                          capture_ir <= UInt<1>("h01") @[rvjtag_tap.scala 71:18]
+                          skip @[Conditional.scala 39:67]
+                        else : @[Conditional.scala 39:67]
+                          node _T_22 = eq(UInt<4>("h0b"), state) @[Conditional.scala 37:30]
+                          when _T_22 : @[Conditional.scala 39:67]
+                            node _T_23 = mux(io.tms, UInt<4>("h0c"), UInt<4>("h0b")) @[rvjtag_tap.scala 72:47]
+                            nstate <= _T_23 @[rvjtag_tap.scala 72:41]
+                            shift_ir <= UInt<1>("h01") @[rvjtag_tap.scala 73:16]
+                            skip @[Conditional.scala 39:67]
+                          else : @[Conditional.scala 39:67]
+                            node _T_24 = eq(UInt<4>("h0c"), state) @[Conditional.scala 37:30]
+                            when _T_24 : @[Conditional.scala 39:67]
+                              node _T_25 = mux(io.tms, UInt<4>("h0f"), UInt<4>("h0d")) @[rvjtag_tap.scala 74:47]
+                              nstate <= _T_25 @[rvjtag_tap.scala 74:41]
+                              skip @[Conditional.scala 39:67]
+                            else : @[Conditional.scala 39:67]
+                              node _T_26 = eq(UInt<4>("h0d"), state) @[Conditional.scala 37:30]
+                              when _T_26 : @[Conditional.scala 39:67]
+                                node _T_27 = mux(io.tms, UInt<4>("h0e"), UInt<4>("h0d")) @[rvjtag_tap.scala 75:47]
+                                nstate <= _T_27 @[rvjtag_tap.scala 75:41]
+                                pause_ir <= UInt<1>("h01") @[rvjtag_tap.scala 76:16]
+                                skip @[Conditional.scala 39:67]
+                              else : @[Conditional.scala 39:67]
+                                node _T_28 = eq(UInt<4>("h0e"), state) @[Conditional.scala 37:30]
+                                when _T_28 : @[Conditional.scala 39:67]
+                                  node _T_29 = mux(io.tms, UInt<4>("h0f"), UInt<4>("h0b")) @[rvjtag_tap.scala 77:47]
+                                  nstate <= _T_29 @[rvjtag_tap.scala 77:41]
+                                  skip @[Conditional.scala 39:67]
+                                else : @[Conditional.scala 39:67]
+                                  node _T_30 = eq(UInt<4>("h0f"), state) @[Conditional.scala 37:30]
+                                  when _T_30 : @[Conditional.scala 39:67]
+                                    node _T_31 = mux(io.tms, UInt<4>("h02"), UInt<4>("h01")) @[rvjtag_tap.scala 78:47]
+                                    nstate <= _T_31 @[rvjtag_tap.scala 78:41]
+                                    update_ir <= UInt<1>("h01") @[rvjtag_tap.scala 79:17]
+                                    skip @[Conditional.scala 39:67]
+    node _T_32 = or(shift_dr, shift_ir) @[rvjtag_tap.scala 81:28]
+    io.tdoEnable <= _T_32 @[rvjtag_tap.scala 81:16]
+    node _T_33 = bits(sr, 4, 0) @[rvjtag_tap.scala 85:93]
+    node _T_34 = eq(_T_33, UInt<1>("h00")) @[rvjtag_tap.scala 85:98]
+    node _T_35 = bits(_T_34, 0, 0) @[rvjtag_tap.scala 85:106]
+    node _T_36 = bits(sr, 4, 0) @[rvjtag_tap.scala 85:123]
+    node _T_37 = mux(_T_35, UInt<5>("h01f"), _T_36) @[rvjtag_tap.scala 85:89]
+    node _T_38 = mux(update_ir, _T_37, UInt<1>("h00")) @[rvjtag_tap.scala 85:75]
+    node _T_39 = mux(jtag_reset, UInt<1>("h01"), _T_38) @[rvjtag_tap.scala 85:56]
+    reg _T_40 : UInt, io.tck with : (reset => (io.trst, UInt<1>("h01"))) @[rvjtag_tap.scala 85:52]
+    _T_40 <= _T_39 @[rvjtag_tap.scala 85:52]
+    ir <= _T_40 @[rvjtag_tap.scala 85:6]
+    node _T_41 = eq(ir, UInt<5>("h01")) @[rvjtag_tap.scala 86:18]
+    devid_sel <= _T_41 @[rvjtag_tap.scala 86:13]
+    node _T_42 = eq(ir, UInt<5>("h011")) @[rvjtag_tap.scala 87:22]
+    node _T_43 = eq(ir, UInt<5>("h010")) @[rvjtag_tap.scala 87:32]
+    node _T_44 = cat(_T_42, _T_43) @[Cat.scala 29:58]
+    dr_en <= _T_44 @[rvjtag_tap.scala 87:13]
+    node _T_45 = eq(shift_dr, UInt<1>("h01")) @[rvjtag_tap.scala 92:16]
+    when _T_45 : @[rvjtag_tap.scala 92:23]
+      node _T_46 = bits(dr_en, 1, 1) @[rvjtag_tap.scala 93:15]
+      node _T_47 = eq(_T_46, UInt<1>("h01")) @[rvjtag_tap.scala 93:18]
+      when _T_47 : @[rvjtag_tap.scala 93:28]
+        node _T_48 = bits(sr, 40, 1) @[rvjtag_tap.scala 93:49]
+        node _T_49 = cat(io.tdi, _T_48) @[Cat.scala 29:58]
+        nsr <= _T_49 @[rvjtag_tap.scala 93:33]
+        skip @[rvjtag_tap.scala 93:28]
+      else : @[rvjtag_tap.scala 94:54]
+        node _T_50 = bits(dr_en, 0, 0) @[rvjtag_tap.scala 94:22]
+        node _T_51 = eq(_T_50, UInt<1>("h01")) @[rvjtag_tap.scala 94:25]
+        node _T_52 = eq(devid_sel, UInt<1>("h01")) @[rvjtag_tap.scala 94:44]
+        node _T_53 = or(_T_51, _T_52) @[rvjtag_tap.scala 94:32]
+        when _T_53 : @[rvjtag_tap.scala 94:54]
+          node _T_54 = mux(UInt<1>("h00"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12]
+          node _T_55 = bits(sr, 31, 1) @[rvjtag_tap.scala 94:106]
+          node _T_56 = cat(_T_54, io.tdi) @[Cat.scala 29:58]
+          node _T_57 = cat(_T_56, _T_55) @[Cat.scala 29:58]
+          nsr <= _T_57 @[rvjtag_tap.scala 94:59]
+          skip @[rvjtag_tap.scala 94:54]
+        else : @[rvjtag_tap.scala 95:17]
+          node _T_58 = mux(UInt<1>("h00"), UInt<40>("h0ffffffffff"), UInt<40>("h00")) @[Bitwise.scala 72:12]
+          node _T_59 = cat(_T_58, io.tdi) @[Cat.scala 29:58]
+          nsr <= _T_59 @[rvjtag_tap.scala 95:22]
+          skip @[rvjtag_tap.scala 95:17]
+      skip @[rvjtag_tap.scala 92:23]
+    else : @[rvjtag_tap.scala 97:33]
+      node _T_60 = eq(capture_dr, UInt<1>("h01")) @[rvjtag_tap.scala 97:26]
+      when _T_60 : @[rvjtag_tap.scala 97:33]
+        node _T_61 = bits(dr_en, 0, 0) @[rvjtag_tap.scala 98:17]
+        when _T_61 : @[rvjtag_tap.scala 98:21]
+          node _T_62 = mux(UInt<1>("h00"), UInt<26>("h03ffffff"), UInt<26>("h00")) @[Bitwise.scala 72:12]
+          node _T_63 = cat(UInt<6>("h07"), io.version) @[Cat.scala 29:58]
+          node _T_64 = cat(_T_62, io.idle) @[Cat.scala 29:58]
+          node _T_65 = cat(_T_64, io.dmi_stat) @[Cat.scala 29:58]
+          node _T_66 = cat(_T_65, _T_63) @[Cat.scala 29:58]
+          nsr <= _T_66 @[rvjtag_tap.scala 98:26]
+          skip @[rvjtag_tap.scala 98:21]
+        else : @[rvjtag_tap.scala 99:28]
+          node _T_67 = bits(dr_en, 1, 1) @[rvjtag_tap.scala 99:24]
+          when _T_67 : @[rvjtag_tap.scala 99:28]
+            node _T_68 = mux(UInt<1>("h00"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12]
+            node _T_69 = cat(_T_68, io.rd_data) @[Cat.scala 29:58]
+            node _T_70 = cat(_T_69, io.rd_status) @[Cat.scala 29:58]
+            nsr <= _T_70 @[rvjtag_tap.scala 99:33]
+            skip @[rvjtag_tap.scala 99:28]
+          else : @[rvjtag_tap.scala 100:29]
+            when devid_sel : @[rvjtag_tap.scala 100:29]
+              node _T_71 = mux(UInt<1>("h00"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12]
+              node _T_72 = cat(_T_71, io.jtag_id) @[Cat.scala 29:58]
+              node _T_73 = cat(_T_72, UInt<1>("h01")) @[Cat.scala 29:58]
+              nsr <= _T_73 @[rvjtag_tap.scala 100:34]
+              skip @[rvjtag_tap.scala 100:29]
+        skip @[rvjtag_tap.scala 97:33]
+      else : @[rvjtag_tap.scala 102:30]
+        node _T_74 = eq(shift_ir, UInt<1>("h01")) @[rvjtag_tap.scala 102:23]
+        when _T_74 : @[rvjtag_tap.scala 102:30]
+          node _T_75 = mux(UInt<1>("h00"), UInt<36>("h0fffffffff"), UInt<36>("h00")) @[Bitwise.scala 72:12]
+          node _T_76 = bits(sr, 4, 1) @[rvjtag_tap.scala 102:78]
+          node _T_77 = cat(_T_75, io.tdi) @[Cat.scala 29:58]
+          node _T_78 = cat(_T_77, _T_76) @[Cat.scala 29:58]
+          nsr <= _T_78 @[rvjtag_tap.scala 102:35]
+          skip @[rvjtag_tap.scala 102:30]
+        else : @[rvjtag_tap.scala 103:32]
+          node _T_79 = eq(capture_ir, UInt<1>("h01")) @[rvjtag_tap.scala 103:25]
+          when _T_79 : @[rvjtag_tap.scala 103:32]
+            node _T_80 = mux(UInt<1>("h00"), UInt<40>("h0ffffffffff"), UInt<40>("h00")) @[Bitwise.scala 72:12]
+            node _T_81 = cat(_T_80, UInt<1>("h01")) @[Cat.scala 29:58]
+            nsr <= _T_81 @[rvjtag_tap.scala 103:37]
+            skip @[rvjtag_tap.scala 103:32]
+    node _T_82 = bits(sr, 0, 0) @[rvjtag_tap.scala 106:40]
+    reg _T_83 : UInt<1>, io.tck with : (reset => (reset, UInt<1>("h00"))) @[rvjtag_tap.scala 106:37]
+    _T_83 <= _T_82 @[rvjtag_tap.scala 106:37]
+    io.tdo <= _T_83 @[rvjtag_tap.scala 106:28]
+    node _T_84 = bits(dr_en, 0, 0) @[rvjtag_tap.scala 108:89]
+    node _T_85 = bits(_T_84, 0, 0) @[rvjtag_tap.scala 108:99]
+    node _T_86 = and(update_dr, _T_85) @[rvjtag_tap.scala 108:82]
+    node _T_87 = bits(sr, 17, 17) @[rvjtag_tap.scala 108:104]
+    node _T_88 = mux(_T_86, _T_87, UInt<1>("h00")) @[rvjtag_tap.scala 108:71]
+    reg _T_89 : UInt, io.tck with : (reset => (io.trst, UInt<1>("h00"))) @[rvjtag_tap.scala 108:67]
+    _T_89 <= _T_88 @[rvjtag_tap.scala 108:67]
+    io.dmi_hard_reset <= _T_89 @[rvjtag_tap.scala 108:57]
+    node _T_90 = bits(dr_en, 0, 0) @[rvjtag_tap.scala 109:84]
+    node _T_91 = bits(_T_90, 0, 0) @[rvjtag_tap.scala 109:94]
+    node _T_92 = and(update_dr, _T_91) @[rvjtag_tap.scala 109:77]
+    node _T_93 = bits(sr, 16, 16) @[rvjtag_tap.scala 109:99]
+    node _T_94 = mux(_T_92, _T_93, UInt<1>("h00")) @[rvjtag_tap.scala 109:66]
+    reg _T_95 : UInt, io.tck with : (reset => (io.trst, UInt<1>("h00"))) @[rvjtag_tap.scala 109:62]
+    _T_95 <= _T_94 @[rvjtag_tap.scala 109:62]
+    io.dmi_reset <= _T_95 @[rvjtag_tap.scala 109:52]
+    node _T_96 = bits(dr_en, 1, 1) @[rvjtag_tap.scala 111:74]
+    node _T_97 = bits(_T_96, 0, 0) @[rvjtag_tap.scala 111:84]
+    node _T_98 = and(update_dr, _T_97) @[rvjtag_tap.scala 111:67]
+    node _T_99 = bits(dr, 40, 2) @[rvjtag_tap.scala 111:96]
+    node _T_100 = cat(_T_99, UInt<2>("h00")) @[Cat.scala 29:58]
+    node _T_101 = mux(_T_98, sr, _T_100) @[rvjtag_tap.scala 111:56]
+    reg _T_102 : UInt, io.tck with : (reset => (io.trst, UInt<1>("h00"))) @[rvjtag_tap.scala 111:52]
+    _T_102 <= _T_101 @[rvjtag_tap.scala 111:52]
+    dr <= _T_102 @[rvjtag_tap.scala 111:42]
+    node _T_103 = bits(dr, 0, 0) @[rvjtag_tap.scala 113:19]
+    io.rd_en <= _T_103 @[rvjtag_tap.scala 113:14]
+    node _T_104 = bits(dr, 1, 1) @[rvjtag_tap.scala 114:19]
+    io.wr_en <= _T_104 @[rvjtag_tap.scala 114:14]
+    node _T_105 = bits(dr, 33, 2) @[rvjtag_tap.scala 115:19]
+    io.wr_data <= _T_105 @[rvjtag_tap.scala 115:14]
+    node _T_106 = bits(dr, 40, 34) @[rvjtag_tap.scala 116:19]
+    io.wr_addr <= _T_106 @[rvjtag_tap.scala 116:14]
+    
+  module dmi_jtag_to_core_sync : 
+    input clock : Clock
+    input reset : AsyncReset
+    output io : {flip rd_en : UInt<1>, flip wr_en : UInt<1>, reg_en : UInt<1>, reg_wr_en : UInt<1>}
+    
+    wire c_rd_en : UInt<1>
+    c_rd_en <= UInt<1>("h00")
+    wire c_wr_en : UInt<1>
+    c_wr_en <= UInt<1>("h00")
+    wire rden : UInt<3>
+    rden <= UInt<3>("h00")
+    wire wren : UInt<3>
+    wren <= UInt<3>("h00")
+    node _T = bits(rden, 1, 0) @[dmi_jtag_to_core_sync.scala 26:27]
+    node _T_1 = cat(_T, io.rd_en) @[Cat.scala 29:58]
+    reg _T_2 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[dmi_jtag_to_core_sync.scala 26:18]
+    _T_2 <= _T_1 @[dmi_jtag_to_core_sync.scala 26:18]
+    rden <= _T_2 @[dmi_jtag_to_core_sync.scala 26:8]
+    node _T_3 = bits(wren, 1, 0) @[dmi_jtag_to_core_sync.scala 27:27]
+    node _T_4 = cat(_T_3, io.wr_en) @[Cat.scala 29:58]
+    reg _T_5 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[dmi_jtag_to_core_sync.scala 27:18]
+    _T_5 <= _T_4 @[dmi_jtag_to_core_sync.scala 27:18]
+    wren <= _T_5 @[dmi_jtag_to_core_sync.scala 27:8]
+    node _T_6 = bits(rden, 1, 1) @[dmi_jtag_to_core_sync.scala 28:18]
+    node _T_7 = bits(rden, 2, 2) @[dmi_jtag_to_core_sync.scala 28:29]
+    node _T_8 = eq(_T_7, UInt<1>("h00")) @[dmi_jtag_to_core_sync.scala 28:24]
+    node _T_9 = and(_T_6, _T_8) @[dmi_jtag_to_core_sync.scala 28:22]
+    c_rd_en <= _T_9 @[dmi_jtag_to_core_sync.scala 28:11]
+    node _T_10 = bits(wren, 1, 1) @[dmi_jtag_to_core_sync.scala 29:18]
+    node _T_11 = bits(wren, 2, 2) @[dmi_jtag_to_core_sync.scala 29:29]
+    node _T_12 = eq(_T_11, UInt<1>("h00")) @[dmi_jtag_to_core_sync.scala 29:24]
+    node _T_13 = and(_T_10, _T_12) @[dmi_jtag_to_core_sync.scala 29:22]
+    c_wr_en <= _T_13 @[dmi_jtag_to_core_sync.scala 29:11]
+    node _T_14 = or(c_wr_en, c_rd_en) @[dmi_jtag_to_core_sync.scala 31:28]
+    io.reg_en <= _T_14 @[dmi_jtag_to_core_sync.scala 31:17]
+    io.reg_wr_en <= c_wr_en @[dmi_jtag_to_core_sync.scala 32:17]
+    
+  module dmi_wrapper : 
+    input clock : Clock
+    input reset : AsyncReset
+    output io : {flip trst_n : AsyncReset, flip tck : Clock, flip tms : UInt<1>, flip tdi : UInt<1>, tdo : UInt<1>, tdoEnable : UInt<1>, flip jtag_id : UInt<32>, flip rd_data : UInt<32>, reg_wr_data : UInt<32>, reg_wr_addr : UInt<7>, reg_en : UInt<1>, reg_wr_en : UInt<1>, dmi_hard_reset : UInt<1>}
+    
+    wire rd_en : UInt<1>
+    rd_en <= UInt<1>("h00")
+    wire wr_en : UInt<1>
+    wr_en <= UInt<1>("h00")
+    wire dmireset : UInt<1>
+    dmireset <= UInt<1>("h00")
+    inst i_jtag_tap of rvjtag_tap @[dmi_wrapper.scala 35:27]
+    i_jtag_tap.clock <= clock
+    i_jtag_tap.reset <= reset
+    i_jtag_tap.io.trst <= io.trst_n @[dmi_wrapper.scala 36:27]
+    i_jtag_tap.io.tck <= io.tck @[dmi_wrapper.scala 37:27]
+    i_jtag_tap.io.tms <= io.tms @[dmi_wrapper.scala 38:27]
+    i_jtag_tap.io.tdi <= io.tdi @[dmi_wrapper.scala 39:27]
+    io.tdo <= i_jtag_tap.io.tdo @[dmi_wrapper.scala 40:27]
+    io.tdoEnable <= i_jtag_tap.io.tdoEnable @[dmi_wrapper.scala 41:27]
+    io.reg_wr_data <= i_jtag_tap.io.wr_data @[dmi_wrapper.scala 42:27]
+    io.reg_wr_addr <= i_jtag_tap.io.wr_addr @[dmi_wrapper.scala 43:27]
+    rd_en <= i_jtag_tap.io.rd_en @[dmi_wrapper.scala 44:27]
+    wr_en <= i_jtag_tap.io.wr_en @[dmi_wrapper.scala 45:27]
+    i_jtag_tap.io.rd_data <= io.rd_data @[dmi_wrapper.scala 46:27]
+    i_jtag_tap.io.rd_status <= UInt<2>("h00") @[dmi_wrapper.scala 47:27]
+    i_jtag_tap.io.idle <= UInt<3>("h00") @[dmi_wrapper.scala 48:27]
+    i_jtag_tap.io.dmi_stat <= UInt<2>("h00") @[dmi_wrapper.scala 49:27]
+    i_jtag_tap.io.version <= UInt<4>("h01") @[dmi_wrapper.scala 50:27]
+    i_jtag_tap.io.jtag_id <= io.jtag_id @[dmi_wrapper.scala 51:27]
+    io.dmi_hard_reset <= i_jtag_tap.io.dmi_hard_reset @[dmi_wrapper.scala 52:27]
+    dmireset <= i_jtag_tap.io.dmi_reset @[dmi_wrapper.scala 53:26]
+    inst i_dmi_jtag_to_core_sync of dmi_jtag_to_core_sync @[dmi_wrapper.scala 56:39]
+    i_dmi_jtag_to_core_sync.clock <= clock
+    i_dmi_jtag_to_core_sync.reset <= reset
+    i_dmi_jtag_to_core_sync.io.wr_en <= wr_en @[dmi_wrapper.scala 57:36]
+    i_dmi_jtag_to_core_sync.io.rd_en <= rd_en @[dmi_wrapper.scala 58:36]
+    io.reg_en <= i_dmi_jtag_to_core_sync.io.reg_en @[dmi_wrapper.scala 59:16]
+    io.reg_wr_en <= i_dmi_jtag_to_core_sync.io.reg_wr_en @[dmi_wrapper.scala 60:16]
+    
diff --git a/dmi_wrapper.v b/dmi_wrapper.v
new file mode 100644
index 00000000..eb864915
--- /dev/null
+++ b/dmi_wrapper.v
@@ -0,0 +1,525 @@
+module rvjtag_tap(
+  input         reset,
+  input         io_trst,
+  input         io_tck,
+  input         io_tms,
+  input         io_tdi,
+  output        io_dmi_hard_reset,
+  input  [30:0] io_jtag_id,
+  input  [31:0] io_rd_data,
+  output        io_tdo,
+  output        io_tdoEnable,
+  output        io_wr_en,
+  output        io_rd_en,
+  output [31:0] io_wr_data
+);
+`ifdef RANDOMIZE_REG_INIT
+  reg [63:0] _RAND_0;
+  reg [31:0] _RAND_1;
+  reg [31:0] _RAND_2;
+  reg [31:0] _RAND_3;
+  reg [31:0] _RAND_4;
+  reg [63:0] _RAND_5;
+`endif // RANDOMIZE_REG_INIT
+  reg [40:0] sr; // @[rvjtag_tap.scala 32:55]
+  reg [3:0] state; // @[rvjtag_tap.scala 39:57]
+  wire  jtag_reset = 4'h0 == state; // @[Conditional.scala 37:30]
+  wire  _T_2 = 4'h1 == state; // @[Conditional.scala 37:30]
+  wire  _T_4 = 4'h2 == state; // @[Conditional.scala 37:30]
+  wire  _T_6 = 4'h3 == state; // @[Conditional.scala 37:30]
+  wire  _T_8 = 4'h4 == state; // @[Conditional.scala 37:30]
+  wire  _T_10 = 4'h5 == state; // @[Conditional.scala 37:30]
+  wire  _T_12 = 4'h6 == state; // @[Conditional.scala 37:30]
+  wire  _T_14 = 4'h7 == state; // @[Conditional.scala 37:30]
+  wire  _T_16 = 4'h8 == state; // @[Conditional.scala 37:30]
+  wire  _T_18 = 4'h9 == state; // @[Conditional.scala 37:30]
+  wire  _T_20 = 4'ha == state; // @[Conditional.scala 37:30]
+  wire  _T_22 = 4'hb == state; // @[Conditional.scala 37:30]
+  wire  _T_24 = 4'hc == state; // @[Conditional.scala 37:30]
+  wire  _T_26 = 4'hd == state; // @[Conditional.scala 37:30]
+  wire  _T_28 = 4'he == state; // @[Conditional.scala 37:30]
+  wire  _T_30 = 4'hf == state; // @[Conditional.scala 37:30]
+  wire  _GEN_3 = _T_28 ? 1'h0 : _T_30; // @[Conditional.scala 39:67]
+  wire  _GEN_6 = _T_26 ? 1'h0 : _GEN_3; // @[Conditional.scala 39:67]
+  wire  _GEN_9 = _T_24 ? 1'h0 : _GEN_6; // @[Conditional.scala 39:67]
+  wire  _GEN_13 = _T_22 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67]
+  wire  _GEN_16 = _T_20 ? 1'h0 : _T_22; // @[Conditional.scala 39:67]
+  wire  _GEN_18 = _T_20 ? 1'h0 : _GEN_13; // @[Conditional.scala 39:67]
+  wire  _GEN_20 = _T_18 ? 1'h0 : _T_20; // @[Conditional.scala 39:67]
+  wire  _GEN_21 = _T_18 ? 1'h0 : _GEN_16; // @[Conditional.scala 39:67]
+  wire  _GEN_23 = _T_18 ? 1'h0 : _GEN_18; // @[Conditional.scala 39:67]
+  wire  _GEN_26 = _T_16 ? 1'h0 : _GEN_20; // @[Conditional.scala 39:67]
+  wire  _GEN_27 = _T_16 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67]
+  wire  _GEN_29 = _T_16 ? 1'h0 : _GEN_23; // @[Conditional.scala 39:67]
+  wire  _GEN_31 = _T_14 ? 1'h0 : _T_16; // @[Conditional.scala 39:67]
+  wire  _GEN_32 = _T_14 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67]
+  wire  _GEN_33 = _T_14 ? 1'h0 : _GEN_27; // @[Conditional.scala 39:67]
+  wire  _GEN_35 = _T_14 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67]
+  wire  _GEN_38 = _T_12 ? 1'h0 : _GEN_31; // @[Conditional.scala 39:67]
+  wire  _GEN_39 = _T_12 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67]
+  wire  _GEN_40 = _T_12 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67]
+  wire  _GEN_42 = _T_12 ? 1'h0 : _GEN_35; // @[Conditional.scala 39:67]
+  wire  _GEN_45 = _T_10 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67]
+  wire  _GEN_46 = _T_10 ? 1'h0 : _GEN_39; // @[Conditional.scala 39:67]
+  wire  _GEN_47 = _T_10 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67]
+  wire  _GEN_49 = _T_10 ? 1'h0 : _GEN_42; // @[Conditional.scala 39:67]
+  wire  _GEN_53 = _T_8 ? 1'h0 : _GEN_45; // @[Conditional.scala 39:67]
+  wire  _GEN_54 = _T_8 ? 1'h0 : _GEN_46; // @[Conditional.scala 39:67]
+  wire  _GEN_55 = _T_8 ? 1'h0 : _GEN_47; // @[Conditional.scala 39:67]
+  wire  _GEN_57 = _T_8 ? 1'h0 : _GEN_49; // @[Conditional.scala 39:67]
+  wire  _GEN_60 = _T_6 ? 1'h0 : _T_8; // @[Conditional.scala 39:67]
+  wire  _GEN_62 = _T_6 ? 1'h0 : _GEN_53; // @[Conditional.scala 39:67]
+  wire  _GEN_63 = _T_6 ? 1'h0 : _GEN_54; // @[Conditional.scala 39:67]
+  wire  _GEN_64 = _T_6 ? 1'h0 : _GEN_55; // @[Conditional.scala 39:67]
+  wire  _GEN_66 = _T_6 ? 1'h0 : _GEN_57; // @[Conditional.scala 39:67]
+  wire  _GEN_68 = _T_4 ? 1'h0 : _T_6; // @[Conditional.scala 39:67]
+  wire  _GEN_69 = _T_4 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67]
+  wire  _GEN_71 = _T_4 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67]
+  wire  _GEN_72 = _T_4 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67]
+  wire  _GEN_73 = _T_4 ? 1'h0 : _GEN_64; // @[Conditional.scala 39:67]
+  wire  _GEN_75 = _T_4 ? 1'h0 : _GEN_66; // @[Conditional.scala 39:67]
+  wire  _GEN_77 = _T_2 ? 1'h0 : _GEN_68; // @[Conditional.scala 39:67]
+  wire  _GEN_78 = _T_2 ? 1'h0 : _GEN_69; // @[Conditional.scala 39:67]
+  wire  _GEN_80 = _T_2 ? 1'h0 : _GEN_71; // @[Conditional.scala 39:67]
+  wire  _GEN_81 = _T_2 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67]
+  wire  _GEN_82 = _T_2 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67]
+  wire  _GEN_84 = _T_2 ? 1'h0 : _GEN_75; // @[Conditional.scala 39:67]
+  wire  capture_dr = jtag_reset ? 1'h0 : _GEN_77; // @[Conditional.scala 40:58]
+  wire  shift_dr = jtag_reset ? 1'h0 : _GEN_78; // @[Conditional.scala 40:58]
+  wire  update_dr = jtag_reset ? 1'h0 : _GEN_80; // @[Conditional.scala 40:58]
+  wire  capture_ir = jtag_reset ? 1'h0 : _GEN_81; // @[Conditional.scala 40:58]
+  wire  shift_ir = jtag_reset ? 1'h0 : _GEN_82; // @[Conditional.scala 40:58]
+  wire  update_ir = jtag_reset ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58]
+  wire  _T_34 = sr[4:0] == 5'h0; // @[rvjtag_tap.scala 85:98]
+  reg [4:0] ir; // @[rvjtag_tap.scala 85:52]
+  wire  devid_sel = ir == 5'h1; // @[rvjtag_tap.scala 86:18]
+  wire  _T_42 = ir == 5'h11; // @[rvjtag_tap.scala 87:22]
+  wire  _T_43 = ir == 5'h10; // @[rvjtag_tap.scala 87:32]
+  wire [1:0] dr_en = {_T_42,_T_43}; // @[Cat.scala 29:58]
+  wire [40:0] _T_49 = {io_tdi,sr[40:1]}; // @[Cat.scala 29:58]
+  wire  _T_53 = dr_en[0] | devid_sel; // @[rvjtag_tap.scala 94:32]
+  wire [40:0] _T_57 = {9'h0,io_tdi,sr[31:1]}; // @[Cat.scala 29:58]
+  wire [40:0] _T_59 = {40'h0,io_tdi}; // @[Cat.scala 29:58]
+  wire [40:0] _T_70 = {7'h0,io_rd_data,2'h0}; // @[Cat.scala 29:58]
+  wire [40:0] _T_73 = {9'h0,io_jtag_id,1'h1}; // @[Cat.scala 29:58]
+  wire [40:0] _T_78 = {36'h0,io_tdi,sr[4:1]}; // @[Cat.scala 29:58]
+  reg  _T_83; // @[rvjtag_tap.scala 106:37]
+  wire  _T_86 = update_dr & dr_en[0]; // @[rvjtag_tap.scala 108:82]
+  reg  _T_89; // @[rvjtag_tap.scala 108:67]
+  wire  _T_98 = update_dr & dr_en[1]; // @[rvjtag_tap.scala 111:67]
+  reg [40:0] dr; // @[rvjtag_tap.scala 111:52]
+  wire [40:0] _T_100 = {dr[40:2],2'h0}; // @[Cat.scala 29:58]
+  assign io_dmi_hard_reset = _T_89; // @[rvjtag_tap.scala 108:57]
+  assign io_tdo = _T_83; // @[rvjtag_tap.scala 106:28]
+  assign io_tdoEnable = shift_dr | shift_ir; // @[rvjtag_tap.scala 81:16]
+  assign io_wr_en = dr[1]; // @[rvjtag_tap.scala 114:14]
+  assign io_rd_en = dr[0]; // @[rvjtag_tap.scala 113:14]
+  assign io_wr_data = dr[33:2]; // @[rvjtag_tap.scala 115:14]
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+  integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+  `ifdef RANDOMIZE
+    `ifdef INIT_RANDOM
+      `INIT_RANDOM
+    `endif
+    `ifndef VERILATOR
+      `ifdef RANDOMIZE_DELAY
+        #`RANDOMIZE_DELAY begin end
+      `else
+        #0.002 begin end
+      `endif
+    `endif
+`ifdef RANDOMIZE_REG_INIT
+  _RAND_0 = {2{`RANDOM}};
+  sr = _RAND_0[40:0];
+  _RAND_1 = {1{`RANDOM}};
+  state = _RAND_1[3:0];
+  _RAND_2 = {1{`RANDOM}};
+  ir = _RAND_2[4:0];
+  _RAND_3 = {1{`RANDOM}};
+  _T_83 = _RAND_3[0:0];
+  _RAND_4 = {1{`RANDOM}};
+  _T_89 = _RAND_4[0:0];
+  _RAND_5 = {2{`RANDOM}};
+  dr = _RAND_5[40:0];
+`endif // RANDOMIZE_REG_INIT
+  if (io_trst) begin
+    sr = 41'h0;
+  end
+  if (io_trst) begin
+    state = 4'h0;
+  end
+  if (io_trst) begin
+    ir = 5'h1;
+  end
+  if (reset) begin
+    _T_83 = 1'h0;
+  end
+  if (io_trst) begin
+    _T_89 = 1'h0;
+  end
+  if (io_trst) begin
+    dr = 41'h0;
+  end
+  `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+  always @(posedge io_tck or posedge io_trst) begin
+    if (io_trst) begin
+      sr <= 41'h0;
+    end else if (shift_dr) begin
+      if (dr_en[1]) begin
+        sr <= _T_49;
+      end else if (_T_53) begin
+        sr <= _T_57;
+      end else begin
+        sr <= _T_59;
+      end
+    end else if (capture_dr) begin
+      if (dr_en[0]) begin
+        sr <= 41'h71;
+      end else if (dr_en[1]) begin
+        sr <= _T_70;
+      end else if (devid_sel) begin
+        sr <= _T_73;
+      end else begin
+        sr <= 41'h0;
+      end
+    end else if (shift_ir) begin
+      sr <= _T_78;
+    end else if (capture_ir) begin
+      sr <= 41'h1;
+    end else begin
+      sr <= 41'h0;
+    end
+  end
+  always @(posedge io_tck or posedge io_trst) begin
+    if (io_trst) begin
+      state <= 4'h0;
+    end else if (jtag_reset) begin
+      if (io_tms) begin
+        state <= 4'h0;
+      end else begin
+        state <= 4'h1;
+      end
+    end else if (_T_2) begin
+      if (io_tms) begin
+        state <= 4'h2;
+      end else begin
+        state <= 4'h1;
+      end
+    end else if (_T_4) begin
+      if (io_tms) begin
+        state <= 4'h9;
+      end else begin
+        state <= 4'h3;
+      end
+    end else if (_T_6) begin
+      if (io_tms) begin
+        state <= 4'h5;
+      end else begin
+        state <= 4'h4;
+      end
+    end else if (_T_8) begin
+      if (io_tms) begin
+        state <= 4'h5;
+      end else begin
+        state <= 4'h4;
+      end
+    end else if (_T_10) begin
+      if (io_tms) begin
+        state <= 4'h8;
+      end else begin
+        state <= 4'h6;
+      end
+    end else if (_T_12) begin
+      if (io_tms) begin
+        state <= 4'h7;
+      end else begin
+        state <= 4'h6;
+      end
+    end else if (_T_14) begin
+      if (io_tms) begin
+        state <= 4'h8;
+      end else begin
+        state <= 4'h4;
+      end
+    end else if (_T_16) begin
+      if (io_tms) begin
+        state <= 4'h2;
+      end else begin
+        state <= 4'h1;
+      end
+    end else if (_T_18) begin
+      if (io_tms) begin
+        state <= 4'h0;
+      end else begin
+        state <= 4'ha;
+      end
+    end else if (_T_20) begin
+      if (io_tms) begin
+        state <= 4'hc;
+      end else begin
+        state <= 4'hb;
+      end
+    end else if (_T_22) begin
+      if (io_tms) begin
+        state <= 4'hc;
+      end else begin
+        state <= 4'hb;
+      end
+    end else if (_T_24) begin
+      if (io_tms) begin
+        state <= 4'hf;
+      end else begin
+        state <= 4'hd;
+      end
+    end else if (_T_26) begin
+      if (io_tms) begin
+        state <= 4'he;
+      end else begin
+        state <= 4'hd;
+      end
+    end else if (_T_28) begin
+      if (io_tms) begin
+        state <= 4'hf;
+      end else begin
+        state <= 4'hb;
+      end
+    end else if (_T_30) begin
+      if (io_tms) begin
+        state <= 4'h2;
+      end else begin
+        state <= 4'h1;
+      end
+    end else begin
+      state <= 4'h0;
+    end
+  end
+  always @(posedge io_tck or posedge io_trst) begin
+    if (io_trst) begin
+      ir <= 5'h1;
+    end else if (jtag_reset) begin
+      ir <= 5'h1;
+    end else if (update_ir) begin
+      if (_T_34) begin
+        ir <= 5'h1f;
+      end else begin
+        ir <= sr[4:0];
+      end
+    end else begin
+      ir <= 5'h0;
+    end
+  end
+  always @(posedge io_tck or posedge reset) begin
+    if (reset) begin
+      _T_83 <= 1'h0;
+    end else begin
+      _T_83 <= sr[0];
+    end
+  end
+  always @(posedge io_tck or posedge io_trst) begin
+    if (io_trst) begin
+      _T_89 <= 1'h0;
+    end else begin
+      _T_89 <= _T_86 & sr[17];
+    end
+  end
+  always @(posedge io_tck or posedge io_trst) begin
+    if (io_trst) begin
+      dr <= 41'h0;
+    end else if (_T_98) begin
+      dr <= sr;
+    end else begin
+      dr <= _T_100;
+    end
+  end
+endmodule
+module dmi_jtag_to_core_sync(
+  input   clock,
+  input   reset,
+  input   io_rd_en,
+  input   io_wr_en,
+  output  io_reg_en,
+  output  io_reg_wr_en
+);
+`ifdef RANDOMIZE_REG_INIT
+  reg [31:0] _RAND_0;
+  reg [31:0] _RAND_1;
+`endif // RANDOMIZE_REG_INIT
+  reg [2:0] rden; // @[dmi_jtag_to_core_sync.scala 26:18]
+  reg [2:0] wren; // @[dmi_jtag_to_core_sync.scala 27:18]
+  wire  _T_8 = ~rden[2]; // @[dmi_jtag_to_core_sync.scala 28:24]
+  wire  c_rd_en = rden[1] & _T_8; // @[dmi_jtag_to_core_sync.scala 28:22]
+  wire  _T_12 = ~wren[2]; // @[dmi_jtag_to_core_sync.scala 29:24]
+  wire  c_wr_en = wren[1] & _T_12; // @[dmi_jtag_to_core_sync.scala 29:22]
+  assign io_reg_en = c_wr_en | c_rd_en; // @[dmi_jtag_to_core_sync.scala 31:17]
+  assign io_reg_wr_en = wren[1] & _T_12; // @[dmi_jtag_to_core_sync.scala 32:17]
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+  integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+  `ifdef RANDOMIZE
+    `ifdef INIT_RANDOM
+      `INIT_RANDOM
+    `endif
+    `ifndef VERILATOR
+      `ifdef RANDOMIZE_DELAY
+        #`RANDOMIZE_DELAY begin end
+      `else
+        #0.002 begin end
+      `endif
+    `endif
+`ifdef RANDOMIZE_REG_INIT
+  _RAND_0 = {1{`RANDOM}};
+  rden = _RAND_0[2:0];
+  _RAND_1 = {1{`RANDOM}};
+  wren = _RAND_1[2:0];
+`endif // RANDOMIZE_REG_INIT
+  if (reset) begin
+    rden = 3'h0;
+  end
+  if (reset) begin
+    wren = 3'h0;
+  end
+  `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      rden <= 3'h0;
+    end else begin
+      rden <= {rden[1:0],io_rd_en};
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      wren <= 3'h0;
+    end else begin
+      wren <= {wren[1:0],io_wr_en};
+    end
+  end
+endmodule
+module dmi_wrapper(
+  input         clock,
+  input         reset,
+  input         io_trst_n,
+  input         io_tck,
+  input         io_tms,
+  input         io_tdi,
+  output        io_tdo,
+  output        io_tdoEnable,
+  input  [31:0] io_jtag_id,
+  input  [31:0] io_rd_data,
+  output [31:0] io_reg_wr_data,
+  output [6:0]  io_reg_wr_addr,
+  output        io_reg_en,
+  output        io_reg_wr_en,
+  output        io_dmi_hard_reset
+);
+  wire  i_jtag_tap_reset; // @[dmi_wrapper.scala 35:27]
+  wire  i_jtag_tap_io_trst; // @[dmi_wrapper.scala 35:27]
+  wire  i_jtag_tap_io_tck; // @[dmi_wrapper.scala 35:27]
+  wire  i_jtag_tap_io_tms; // @[dmi_wrapper.scala 35:27]
+  wire  i_jtag_tap_io_tdi; // @[dmi_wrapper.scala 35:27]
+  wire  i_jtag_tap_io_dmi_hard_reset; // @[dmi_wrapper.scala 35:27]
+  wire [30:0] i_jtag_tap_io_jtag_id; // @[dmi_wrapper.scala 35:27]
+  wire [31:0] i_jtag_tap_io_rd_data; // @[dmi_wrapper.scala 35:27]
+  wire  i_jtag_tap_io_tdo; // @[dmi_wrapper.scala 35:27]
+  wire  i_jtag_tap_io_tdoEnable; // @[dmi_wrapper.scala 35:27]
+  wire  i_jtag_tap_io_wr_en; // @[dmi_wrapper.scala 35:27]
+  wire  i_jtag_tap_io_rd_en; // @[dmi_wrapper.scala 35:27]
+  wire [31:0] i_jtag_tap_io_wr_data; // @[dmi_wrapper.scala 35:27]
+  wire  i_dmi_jtag_to_core_sync_clock; // @[dmi_wrapper.scala 56:39]
+  wire  i_dmi_jtag_to_core_sync_reset; // @[dmi_wrapper.scala 56:39]
+  wire  i_dmi_jtag_to_core_sync_io_rd_en; // @[dmi_wrapper.scala 56:39]
+  wire  i_dmi_jtag_to_core_sync_io_wr_en; // @[dmi_wrapper.scala 56:39]
+  wire  i_dmi_jtag_to_core_sync_io_reg_en; // @[dmi_wrapper.scala 56:39]
+  wire  i_dmi_jtag_to_core_sync_io_reg_wr_en; // @[dmi_wrapper.scala 56:39]
+  rvjtag_tap i_jtag_tap ( // @[dmi_wrapper.scala 35:27]
+    .reset(i_jtag_tap_reset),
+    .io_trst(i_jtag_tap_io_trst),
+    .io_tck(i_jtag_tap_io_tck),
+    .io_tms(i_jtag_tap_io_tms),
+    .io_tdi(i_jtag_tap_io_tdi),
+    .io_dmi_hard_reset(i_jtag_tap_io_dmi_hard_reset),
+    .io_jtag_id(i_jtag_tap_io_jtag_id),
+    .io_rd_data(i_jtag_tap_io_rd_data),
+    .io_tdo(i_jtag_tap_io_tdo),
+    .io_tdoEnable(i_jtag_tap_io_tdoEnable),
+    .io_wr_en(i_jtag_tap_io_wr_en),
+    .io_rd_en(i_jtag_tap_io_rd_en),
+    .io_wr_data(i_jtag_tap_io_wr_data)
+  );
+  dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync ( // @[dmi_wrapper.scala 56:39]
+    .clock(i_dmi_jtag_to_core_sync_clock),
+    .reset(i_dmi_jtag_to_core_sync_reset),
+    .io_rd_en(i_dmi_jtag_to_core_sync_io_rd_en),
+    .io_wr_en(i_dmi_jtag_to_core_sync_io_wr_en),
+    .io_reg_en(i_dmi_jtag_to_core_sync_io_reg_en),
+    .io_reg_wr_en(i_dmi_jtag_to_core_sync_io_reg_wr_en)
+  );
+  assign io_tdo = i_jtag_tap_io_tdo; // @[dmi_wrapper.scala 40:27]
+  assign io_tdoEnable = i_jtag_tap_io_tdoEnable; // @[dmi_wrapper.scala 41:27]
+  assign io_reg_wr_data = i_jtag_tap_io_wr_data; // @[dmi_wrapper.scala 42:27]
+  assign io_reg_wr_addr = 7'h0; // @[dmi_wrapper.scala 43:27]
+  assign io_reg_en = i_dmi_jtag_to_core_sync_io_reg_en; // @[dmi_wrapper.scala 59:16]
+  assign io_reg_wr_en = i_dmi_jtag_to_core_sync_io_reg_wr_en; // @[dmi_wrapper.scala 60:16]
+  assign io_dmi_hard_reset = i_jtag_tap_io_dmi_hard_reset; // @[dmi_wrapper.scala 52:27]
+  assign i_jtag_tap_reset = reset;
+  assign i_jtag_tap_io_trst = io_trst_n; // @[dmi_wrapper.scala 36:27]
+  assign i_jtag_tap_io_tck = io_tck; // @[dmi_wrapper.scala 37:27]
+  assign i_jtag_tap_io_tms = io_tms; // @[dmi_wrapper.scala 38:27]
+  assign i_jtag_tap_io_tdi = io_tdi; // @[dmi_wrapper.scala 39:27]
+  assign i_jtag_tap_io_jtag_id = io_jtag_id[30:0]; // @[dmi_wrapper.scala 51:27]
+  assign i_jtag_tap_io_rd_data = io_rd_data; // @[dmi_wrapper.scala 46:27]
+  assign i_dmi_jtag_to_core_sync_clock = clock;
+  assign i_dmi_jtag_to_core_sync_reset = reset;
+  assign i_dmi_jtag_to_core_sync_io_rd_en = i_jtag_tap_io_rd_en; // @[dmi_wrapper.scala 58:36]
+  assign i_dmi_jtag_to_core_sync_io_wr_en = i_jtag_tap_io_wr_en; // @[dmi_wrapper.scala 57:36]
+endmodule
diff --git a/el2_dma_ctrl.anno.json b/el2_dma_ctrl.anno.json
new file mode 100644
index 00000000..fafac97a
--- /dev/null
+++ b/el2_dma_ctrl.anno.json
@@ -0,0 +1,115 @@
+[
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_stall_any",
+    "sources":[
+      "~el2_dma_ctrl|el2_dma_ctrl>io_dec_tlu_dma_qos_prty",
+      "~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_any_write",
+    "sources":[
+      "~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write",
+      "~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req",
+      "~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_req",
+      "~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready",
+      "~el2_dma_ctrl|el2_dma_ctrl>io_iccm_ready"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_dccm_write",
+    "sources":[
+      "~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req",
+      "~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write",
+      "~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_stall_any",
+    "sources":[
+      "~el2_dma_ctrl|el2_dma_ctrl>io_dec_tlu_dma_qos_prty",
+      "~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req",
+    "sources":[
+      "~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready",
+      "~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_addr",
+    "sources":[
+      "~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_any_read",
+    "sources":[
+      "~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req",
+      "~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_req",
+      "~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write",
+      "~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready",
+      "~el2_dma_ctrl|el2_dma_ctrl>io_iccm_ready"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_dccm_read",
+    "sources":[
+      "~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req",
+      "~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write",
+      "~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_sz",
+    "sources":[
+      "~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_req",
+    "sources":[
+      "~el2_dma_ctrl|el2_dma_ctrl>io_iccm_ready",
+      "~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write"
+    ]
+  },
+  {
+    "class":"logger.LogLevelAnnotation",
+    "globalLogLevel":{
+      
+    }
+  },
+  {
+    "class":"firrtl.EmitCircuitAnnotation",
+    "emitter":"firrtl.VerilogEmitter"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxResourceAnno",
+    "target":"el2_dma_ctrl.TEC_RV_ICG",
+    "resourceId":"/vsrc/TEC_RV_ICG.v"
+  },
+  {
+    "class":"firrtl.options.TargetDirAnnotation",
+    "directory":"."
+  },
+  {
+    "class":"firrtl.options.OutputAnnotationFileAnnotation",
+    "file":"el2_dma_ctrl"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
+    "targetDir":"."
+  }
+]
\ No newline at end of file
diff --git a/el2_dma_ctrl.fir b/el2_dma_ctrl.fir
new file mode 100644
index 00000000..4707af64
--- /dev/null
+++ b/el2_dma_ctrl.fir
@@ -0,0 +1,2267 @@
+;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
+circuit el2_dma_ctrl : 
+  extmodule TEC_RV_ICG : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG @[el2_lib.scala 474:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
+    
+  extmodule TEC_RV_ICG_1 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_1 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_1 @[el2_lib.scala 474:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
+    
+  extmodule TEC_RV_ICG_2 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_2 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_2 @[el2_lib.scala 474:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
+    
+  extmodule TEC_RV_ICG_3 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_3 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_3 @[el2_lib.scala 474:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
+    
+  extmodule TEC_RV_ICG_4 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_4 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_4 @[el2_lib.scala 474:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
+    
+  extmodule TEC_RV_ICG_5 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_5 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_5 @[el2_lib.scala 474:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
+    
+  extmodule TEC_RV_ICG_6 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_6 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_6 @[el2_lib.scala 474:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
+    
+  extmodule TEC_RV_ICG_7 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_7 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_7 @[el2_lib.scala 474:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
+    
+  extmodule TEC_RV_ICG_8 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_8 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_8 @[el2_lib.scala 474:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
+    
+  extmodule TEC_RV_ICG_9 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_9 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_9 @[el2_lib.scala 474:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
+    
+  extmodule TEC_RV_ICG_10 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_10 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_10 @[el2_lib.scala 474:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
+    
+  extmodule TEC_RV_ICG_11 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_11 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_11 @[el2_lib.scala 474:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
+    
+  extmodule TEC_RV_ICG_12 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_12 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_12 @[el2_lib.scala 474:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
+    
+  extmodule TEC_RV_ICG_13 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_13 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_13 @[el2_lib.scala 474:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
+    
+  extmodule TEC_RV_ICG_14 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_14 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_14 @[el2_lib.scala 474:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
+    
+  extmodule TEC_RV_ICG_15 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = TEC_RV_ICG
+    
+    
+  module rvclkhdr_15 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of TEC_RV_ICG_15 @[el2_lib.scala 474:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
+    clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
+    clkhdr.EN <= io.en @[el2_lib.scala 477:18]
+    clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
+    
+  module el2_dma_ctrl : 
+    input clock : Clock
+    input reset : AsyncReset
+    output io : {flip free_clk : Clock, flip rst_l : UInt<1>, flip dma_bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip scan_mode : UInt<1>, flip dbg_cmd_addr : UInt<32>, flip dbg_cmd_wrdata : UInt<32>, flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_size : UInt<2>, flip dbg_dma_bubble : UInt<1>, dma_dbg_ready : UInt<1>, dma_dbg_cmd_done : UInt<1>, dma_dbg_cmd_fail : UInt<1>, dma_dbg_rddata : UInt<32>, dma_dccm_req : UInt<1>, dma_iccm_req : UInt<1>, dma_mem_tag : UInt<3>, dma_mem_addr : UInt<32>, dma_mem_sz : UInt<3>, dma_mem_write : UInt<1>, dma_mem_wdata : UInt<64>, flip dccm_dma_rvalid : UInt<1>, flip dccm_dma_ecc_error : UInt<1>, flip dccm_dma_rtag : UInt<3>, flip dccm_dma_rdata : UInt<64>, flip iccm_dma_rvalid : UInt<1>, flip iccm_dma_ecc_error : UInt<1>, flip iccm_dma_rtag : UInt<3>, flip iccm_dma_rdata : UInt<64>, dma_dccm_stall_any : UInt<1>, dma_iccm_stall_any : UInt<1>, flip dccm_ready : UInt<1>, flip iccm_ready : UInt<1>, flip dec_tlu_dma_qos_prty : UInt<3>, dma_pmu_dccm_read : UInt<1>, dma_pmu_dccm_write : UInt<1>, dma_pmu_any_read : UInt<1>, dma_pmu_any_write : UInt<1>, flip dma_axi_awvalid : UInt<1>, dma_axi_awready : UInt<1>, flip dma_axi_awid : UInt<1>, flip dma_axi_awaddr : UInt<32>, flip dma_axi_awsize : UInt<3>, flip dma_axi_wvalid : UInt<1>, dma_axi_wready : UInt<1>, flip dma_axi_wdata : UInt<64>, flip dma_axi_wstrb : UInt<8>, dma_axi_bvalid : UInt<1>, flip dma_axi_bready : UInt<1>, dma_axi_bresp : UInt<2>, dma_axi_bid : UInt<1>, flip dma_axi_arvalid : UInt<1>, dma_axi_arready : UInt<1>, flip dma_axi_arid : UInt<1>, flip dma_axi_araddr : UInt<32>, flip dma_axi_arsize : UInt<3>, dma_axi_rvalid : UInt<1>, flip dma_axi_rready : UInt<1>, dma_axi_rid : UInt<1>, dma_axi_rdata : UInt<64>, dma_axi_rresp : UInt<2>, dma_axi_rlast : UInt<1>}
+    
+    wire fifo_error : UInt<2>[5] @[el2_dma_ctrl.scala 94:24]
+    wire fifo_error_bus : UInt<5>
+    fifo_error_bus <= UInt<1>("h00")
+    wire fifo_done : UInt<5>
+    fifo_done <= UInt<1>("h00")
+    wire fifo_addr : UInt<32>[5] @[el2_dma_ctrl.scala 100:23]
+    wire fifo_sz : UInt<3>[5] @[el2_dma_ctrl.scala 102:21]
+    wire fifo_byteen : UInt<8>[5] @[el2_dma_ctrl.scala 104:25]
+    wire fifo_data : UInt<64>[5] @[el2_dma_ctrl.scala 106:23]
+    wire fifo_tag : UInt<1>[5] @[el2_dma_ctrl.scala 108:22]
+    wire fifo_mid : UInt<1>[5] @[el2_dma_ctrl.scala 110:22]
+    wire fifo_prty : UInt<2>[5] @[el2_dma_ctrl.scala 112:23]
+    wire fifo_error_en : UInt<5>
+    fifo_error_en <= UInt<1>("h00")
+    wire fifo_error_in : UInt<2>[5] @[el2_dma_ctrl.scala 116:27]
+    wire fifo_data_in : UInt<64>[5] @[el2_dma_ctrl.scala 118:26]
+    wire RspPtr : UInt<3>
+    RspPtr <= UInt<1>("h00")
+    wire WrPtr : UInt<3>
+    WrPtr <= UInt<1>("h00")
+    wire RdPtr : UInt<3>
+    RdPtr <= UInt<1>("h00")
+    wire NxtRspPtr : UInt<3>
+    NxtRspPtr <= UInt<1>("h00")
+    wire NxtWrPtr : UInt<3>
+    NxtWrPtr <= UInt<1>("h00")
+    wire NxtRdPtr : UInt<3>
+    NxtRdPtr <= UInt<1>("h00")
+    wire dma_dbg_cmd_error : UInt<1>
+    dma_dbg_cmd_error <= UInt<1>("h00")
+    wire dma_dbg_cmd_done_q : UInt<1>
+    dma_dbg_cmd_done_q <= UInt<1>("h00")
+    wire fifo_empty : UInt<1>
+    fifo_empty <= UInt<1>("h00")
+    wire dma_address_error : UInt<1>
+    dma_address_error <= UInt<1>("h00")
+    wire dma_alignment_error : UInt<1>
+    dma_alignment_error <= UInt<1>("h00")
+    wire num_fifo_vld : UInt<4>
+    num_fifo_vld <= UInt<1>("h00")
+    wire dma_mem_req : UInt<1>
+    dma_mem_req <= UInt<1>("h00")
+    wire dma_mem_addr_int : UInt<32>
+    dma_mem_addr_int <= UInt<1>("h00")
+    wire dma_mem_sz_int : UInt<3>
+    dma_mem_sz_int <= UInt<1>("h00")
+    wire dma_mem_byteen : UInt<8>
+    dma_mem_byteen <= UInt<1>("h00")
+    wire dma_nack_count : UInt<3>
+    dma_nack_count <= UInt<1>("h00")
+    wire dma_nack_count_csr : UInt<3>
+    dma_nack_count_csr <= UInt<1>("h00")
+    wire bus_rsp_valid : UInt<1>
+    bus_rsp_valid <= UInt<1>("h00")
+    wire bus_rsp_sent : UInt<1>
+    bus_rsp_sent <= UInt<1>("h00")
+    wire bus_cmd_valid : UInt<1>
+    bus_cmd_valid <= UInt<1>("h00")
+    wire axi_mstr_prty_en : UInt<1>
+    axi_mstr_prty_en <= UInt<1>("h00")
+    wire bus_cmd_write : UInt<1>
+    bus_cmd_write <= UInt<1>("h00")
+    wire bus_cmd_posted_write : UInt<1>
+    bus_cmd_posted_write <= UInt<1>("h00")
+    wire bus_cmd_byteen : UInt<8>
+    bus_cmd_byteen <= UInt<1>("h00")
+    wire bus_cmd_sz : UInt<3>
+    bus_cmd_sz <= UInt<1>("h00")
+    wire bus_cmd_addr : UInt<32>
+    bus_cmd_addr <= UInt<1>("h00")
+    wire bus_cmd_wdata : UInt<64>
+    bus_cmd_wdata <= UInt<1>("h00")
+    wire bus_cmd_tag : UInt<1>
+    bus_cmd_tag <= UInt<1>("h00")
+    wire bus_cmd_mid : UInt<1>
+    bus_cmd_mid <= UInt<1>("h00")
+    wire bus_cmd_prty : UInt<2>
+    bus_cmd_prty <= UInt<1>("h00")
+    wire bus_posted_write_done : UInt<1>
+    bus_posted_write_done <= UInt<1>("h00")
+    wire fifo_full : UInt<1>
+    fifo_full <= UInt<1>("h00")
+    wire dbg_dma_bubble_bus : UInt<1>
+    dbg_dma_bubble_bus <= UInt<1>("h00")
+    wire axi_mstr_priority : UInt<1>
+    axi_mstr_priority <= UInt<1>("h00")
+    wire axi_mstr_sel : UInt<1>
+    axi_mstr_sel <= UInt<1>("h00")
+    wire axi_rsp_sent : UInt<1>
+    axi_rsp_sent <= UInt<1>("h00")
+    wire fifo_cmd_en : UInt<5>
+    fifo_cmd_en <= UInt<1>("h00")
+    wire fifo_data_en : UInt<5>
+    fifo_data_en <= UInt<1>("h00")
+    wire fifo_pend_en : UInt<5>
+    fifo_pend_en <= UInt<1>("h00")
+    wire fifo_error_bus_en : UInt<5>
+    fifo_error_bus_en <= UInt<1>("h00")
+    wire fifo_done_en : UInt<5>
+    fifo_done_en <= UInt<1>("h00")
+    wire fifo_done_bus_en : UInt<5>
+    fifo_done_bus_en <= UInt<1>("h00")
+    wire fifo_reset : UInt<5>
+    fifo_reset <= UInt<1>("h00")
+    wire fifo_valid : UInt<5>
+    fifo_valid <= UInt<1>("h00")
+    wire fifo_rpend : UInt<5>
+    fifo_rpend <= UInt<1>("h00")
+    wire fifo_done_bus : UInt<5>
+    fifo_done_bus <= UInt<1>("h00")
+    wire fifo_write : UInt<5>
+    fifo_write <= UInt<1>("h00")
+    wire fifo_posted_write : UInt<5>
+    fifo_posted_write <= UInt<1>("h00")
+    wire fifo_dbg : UInt<5>
+    fifo_dbg <= UInt<1>("h00")
+    wire wrbuf_vld : UInt<1>
+    wrbuf_vld <= UInt<1>("h00")
+    wire wrbuf_data_vld : UInt<1>
+    wrbuf_data_vld <= UInt<1>("h00")
+    wire rdbuf_vld : UInt<1>
+    rdbuf_vld <= UInt<1>("h00")
+    wire dma_free_clk : Clock @[el2_dma_ctrl.scala 226:26]
+    wire dma_bus_clk : Clock @[el2_dma_ctrl.scala 228:25]
+    wire dma_buffer_c1_clk : Clock @[el2_dma_ctrl.scala 230:31]
+    wire fifo_byteen_in : UInt<8>
+    fifo_byteen_in <= UInt<1>("h00")
+    node _T = bits(dma_mem_addr_int, 31, 0) @[el2_dma_ctrl.scala 239:95]
+    node _T_1 = bits(_T, 31, 28) @[el2_lib.scala 496:27]
+    node dma_mem_addr_in_dccm_region_nc = eq(_T_1, UInt<4>("h0f")) @[el2_lib.scala 496:49]
+    wire dma_mem_addr_in_dccm : UInt<1> @[el2_lib.scala 497:26]
+    node _T_2 = bits(_T, 31, 16) @[el2_lib.scala 501:24]
+    node _T_3 = eq(_T_2, UInt<16>("h0f004")) @[el2_lib.scala 501:39]
+    dma_mem_addr_in_dccm <= _T_3 @[el2_lib.scala 501:16]
+    node _T_4 = bits(dma_mem_addr_int, 31, 0) @[el2_dma_ctrl.scala 243:93]
+    node _T_5 = bits(_T_4, 31, 28) @[el2_lib.scala 496:27]
+    node dma_mem_addr_in_pic_region_nc = eq(_T_5, UInt<4>("h0f")) @[el2_lib.scala 496:49]
+    wire dma_mem_addr_in_pic : UInt<1> @[el2_lib.scala 497:26]
+    node _T_6 = bits(_T_4, 31, 15) @[el2_lib.scala 501:24]
+    node _T_7 = eq(_T_6, UInt<17>("h01e018")) @[el2_lib.scala 501:39]
+    dma_mem_addr_in_pic <= _T_7 @[el2_lib.scala 501:16]
+    node _T_8 = bits(dma_mem_addr_int, 31, 0) @[el2_dma_ctrl.scala 247:111]
+    node _T_9 = bits(_T_8, 31, 28) @[el2_lib.scala 496:27]
+    node dma_mem_addr_in_iccm_region_nc = eq(_T_9, UInt<4>("h0e")) @[el2_lib.scala 496:49]
+    wire dma_mem_addr_in_iccm : UInt<1> @[el2_lib.scala 497:26]
+    node _T_10 = bits(_T_8, 31, 16) @[el2_lib.scala 501:24]
+    node _T_11 = eq(_T_10, UInt<16>("h0ee00")) @[el2_lib.scala 501:39]
+    dma_mem_addr_in_iccm <= _T_11 @[el2_lib.scala 501:16]
+    node _T_12 = bits(io.dbg_cmd_valid, 0, 0) @[el2_dma_ctrl.scala 251:51]
+    node _T_13 = bits(io.dbg_cmd_addr, 31, 0) @[el2_dma_ctrl.scala 251:74]
+    node _T_14 = bits(bus_cmd_addr, 31, 0) @[el2_dma_ctrl.scala 251:94]
+    node fifo_addr_in = mux(_T_12, _T_13, _T_14) @[el2_dma_ctrl.scala 251:33]
+    node _T_15 = bits(io.dbg_cmd_valid, 0, 0) @[el2_dma_ctrl.scala 253:52]
+    node _T_16 = bits(io.dbg_cmd_addr, 2, 2) @[el2_dma_ctrl.scala 253:93]
+    node _T_17 = mul(UInt<3>("h04"), _T_16) @[el2_dma_ctrl.scala 253:76]
+    node _T_18 = dshl(UInt<4>("h0f"), _T_17) @[el2_dma_ctrl.scala 253:68]
+    node _T_19 = bits(bus_cmd_byteen, 7, 0) @[el2_dma_ctrl.scala 253:113]
+    node _T_20 = mux(_T_15, _T_18, _T_19) @[el2_dma_ctrl.scala 253:34]
+    fifo_byteen_in <= _T_20 @[el2_dma_ctrl.scala 253:28]
+    node _T_21 = bits(io.dbg_cmd_valid, 0, 0) @[el2_dma_ctrl.scala 255:51]
+    node _T_22 = bits(io.dbg_cmd_size, 1, 0) @[el2_dma_ctrl.scala 255:83]
+    node _T_23 = cat(UInt<1>("h00"), _T_22) @[Cat.scala 29:58]
+    node _T_24 = bits(bus_cmd_sz, 2, 0) @[el2_dma_ctrl.scala 255:101]
+    node fifo_sz_in = mux(_T_21, _T_23, _T_24) @[el2_dma_ctrl.scala 255:33]
+    node _T_25 = bits(io.dbg_cmd_valid, 0, 0) @[el2_dma_ctrl.scala 257:51]
+    node fifo_write_in = mux(_T_25, io.dbg_cmd_write, bus_cmd_write) @[el2_dma_ctrl.scala 257:33]
+    node _T_26 = eq(io.dbg_cmd_valid, UInt<1>("h00")) @[el2_dma_ctrl.scala 259:30]
+    node fifo_posted_write_in = and(_T_26, bus_cmd_posted_write) @[el2_dma_ctrl.scala 259:48]
+    node _T_27 = bits(axi_mstr_prty_en, 0, 0) @[el2_dma_ctrl.scala 264:73]
+    node _T_28 = and(_T_27, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 264:80]
+    node _T_29 = bits(io.dbg_cmd_type, 1, 1) @[el2_dma_ctrl.scala 264:138]
+    node _T_30 = bits(_T_29, 0, 0) @[el2_dma_ctrl.scala 264:142]
+    node _T_31 = and(io.dbg_cmd_valid, _T_30) @[el2_dma_ctrl.scala 264:121]
+    node _T_32 = or(_T_28, _T_31) @[el2_dma_ctrl.scala 264:101]
+    node _T_33 = eq(UInt<1>("h00"), WrPtr) @[el2_dma_ctrl.scala 264:158]
+    node _T_34 = and(_T_32, _T_33) @[el2_dma_ctrl.scala 264:151]
+    node _T_35 = bits(axi_mstr_prty_en, 0, 0) @[el2_dma_ctrl.scala 264:73]
+    node _T_36 = and(_T_35, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 264:80]
+    node _T_37 = bits(io.dbg_cmd_type, 1, 1) @[el2_dma_ctrl.scala 264:138]
+    node _T_38 = bits(_T_37, 0, 0) @[el2_dma_ctrl.scala 264:142]
+    node _T_39 = and(io.dbg_cmd_valid, _T_38) @[el2_dma_ctrl.scala 264:121]
+    node _T_40 = or(_T_36, _T_39) @[el2_dma_ctrl.scala 264:101]
+    node _T_41 = eq(UInt<1>("h01"), WrPtr) @[el2_dma_ctrl.scala 264:158]
+    node _T_42 = and(_T_40, _T_41) @[el2_dma_ctrl.scala 264:151]
+    node _T_43 = bits(axi_mstr_prty_en, 0, 0) @[el2_dma_ctrl.scala 264:73]
+    node _T_44 = and(_T_43, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 264:80]
+    node _T_45 = bits(io.dbg_cmd_type, 1, 1) @[el2_dma_ctrl.scala 264:138]
+    node _T_46 = bits(_T_45, 0, 0) @[el2_dma_ctrl.scala 264:142]
+    node _T_47 = and(io.dbg_cmd_valid, _T_46) @[el2_dma_ctrl.scala 264:121]
+    node _T_48 = or(_T_44, _T_47) @[el2_dma_ctrl.scala 264:101]
+    node _T_49 = eq(UInt<2>("h02"), WrPtr) @[el2_dma_ctrl.scala 264:158]
+    node _T_50 = and(_T_48, _T_49) @[el2_dma_ctrl.scala 264:151]
+    node _T_51 = bits(axi_mstr_prty_en, 0, 0) @[el2_dma_ctrl.scala 264:73]
+    node _T_52 = and(_T_51, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 264:80]
+    node _T_53 = bits(io.dbg_cmd_type, 1, 1) @[el2_dma_ctrl.scala 264:138]
+    node _T_54 = bits(_T_53, 0, 0) @[el2_dma_ctrl.scala 264:142]
+    node _T_55 = and(io.dbg_cmd_valid, _T_54) @[el2_dma_ctrl.scala 264:121]
+    node _T_56 = or(_T_52, _T_55) @[el2_dma_ctrl.scala 264:101]
+    node _T_57 = eq(UInt<2>("h03"), WrPtr) @[el2_dma_ctrl.scala 264:158]
+    node _T_58 = and(_T_56, _T_57) @[el2_dma_ctrl.scala 264:151]
+    node _T_59 = bits(axi_mstr_prty_en, 0, 0) @[el2_dma_ctrl.scala 264:73]
+    node _T_60 = and(_T_59, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 264:80]
+    node _T_61 = bits(io.dbg_cmd_type, 1, 1) @[el2_dma_ctrl.scala 264:138]
+    node _T_62 = bits(_T_61, 0, 0) @[el2_dma_ctrl.scala 264:142]
+    node _T_63 = and(io.dbg_cmd_valid, _T_62) @[el2_dma_ctrl.scala 264:121]
+    node _T_64 = or(_T_60, _T_63) @[el2_dma_ctrl.scala 264:101]
+    node _T_65 = eq(UInt<3>("h04"), WrPtr) @[el2_dma_ctrl.scala 264:158]
+    node _T_66 = and(_T_64, _T_65) @[el2_dma_ctrl.scala 264:151]
+    node _T_67 = cat(_T_66, _T_58) @[Cat.scala 29:58]
+    node _T_68 = cat(_T_67, _T_50) @[Cat.scala 29:58]
+    node _T_69 = cat(_T_68, _T_42) @[Cat.scala 29:58]
+    node _T_70 = cat(_T_69, _T_34) @[Cat.scala 29:58]
+    fifo_cmd_en <= _T_70 @[el2_dma_ctrl.scala 264:21]
+    node _T_71 = and(axi_mstr_prty_en, fifo_write_in) @[el2_dma_ctrl.scala 266:73]
+    node _T_72 = and(_T_71, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 266:89]
+    node _T_73 = bits(io.dbg_cmd_type, 1, 1) @[el2_dma_ctrl.scala 266:147]
+    node _T_74 = and(io.dbg_cmd_valid, _T_73) @[el2_dma_ctrl.scala 266:130]
+    node _T_75 = and(_T_74, io.dbg_cmd_write) @[el2_dma_ctrl.scala 266:151]
+    node _T_76 = or(_T_72, _T_75) @[el2_dma_ctrl.scala 266:110]
+    node _T_77 = eq(UInt<1>("h00"), WrPtr) @[el2_dma_ctrl.scala 266:179]
+    node _T_78 = and(_T_76, _T_77) @[el2_dma_ctrl.scala 266:172]
+    node _T_79 = or(dma_address_error, dma_alignment_error) @[el2_dma_ctrl.scala 266:213]
+    node _T_80 = eq(UInt<1>("h00"), RdPtr) @[el2_dma_ctrl.scala 266:243]
+    node _T_81 = and(_T_79, _T_80) @[el2_dma_ctrl.scala 266:236]
+    node _T_82 = or(_T_78, _T_81) @[el2_dma_ctrl.scala 266:191]
+    node _T_83 = eq(UInt<1>("h00"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 266:284]
+    node _T_84 = and(io.dccm_dma_rvalid, _T_83) @[el2_dma_ctrl.scala 266:277]
+    node _T_85 = or(_T_82, _T_84) @[el2_dma_ctrl.scala 266:255]
+    node _T_86 = eq(UInt<1>("h00"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 266:336]
+    node _T_87 = and(io.iccm_dma_rvalid, _T_86) @[el2_dma_ctrl.scala 266:329]
+    node _T_88 = or(_T_85, _T_87) @[el2_dma_ctrl.scala 266:307]
+    node _T_89 = and(axi_mstr_prty_en, fifo_write_in) @[el2_dma_ctrl.scala 266:73]
+    node _T_90 = and(_T_89, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 266:89]
+    node _T_91 = bits(io.dbg_cmd_type, 1, 1) @[el2_dma_ctrl.scala 266:147]
+    node _T_92 = and(io.dbg_cmd_valid, _T_91) @[el2_dma_ctrl.scala 266:130]
+    node _T_93 = and(_T_92, io.dbg_cmd_write) @[el2_dma_ctrl.scala 266:151]
+    node _T_94 = or(_T_90, _T_93) @[el2_dma_ctrl.scala 266:110]
+    node _T_95 = eq(UInt<1>("h01"), WrPtr) @[el2_dma_ctrl.scala 266:179]
+    node _T_96 = and(_T_94, _T_95) @[el2_dma_ctrl.scala 266:172]
+    node _T_97 = or(dma_address_error, dma_alignment_error) @[el2_dma_ctrl.scala 266:213]
+    node _T_98 = eq(UInt<1>("h01"), RdPtr) @[el2_dma_ctrl.scala 266:243]
+    node _T_99 = and(_T_97, _T_98) @[el2_dma_ctrl.scala 266:236]
+    node _T_100 = or(_T_96, _T_99) @[el2_dma_ctrl.scala 266:191]
+    node _T_101 = eq(UInt<1>("h01"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 266:284]
+    node _T_102 = and(io.dccm_dma_rvalid, _T_101) @[el2_dma_ctrl.scala 266:277]
+    node _T_103 = or(_T_100, _T_102) @[el2_dma_ctrl.scala 266:255]
+    node _T_104 = eq(UInt<1>("h01"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 266:336]
+    node _T_105 = and(io.iccm_dma_rvalid, _T_104) @[el2_dma_ctrl.scala 266:329]
+    node _T_106 = or(_T_103, _T_105) @[el2_dma_ctrl.scala 266:307]
+    node _T_107 = and(axi_mstr_prty_en, fifo_write_in) @[el2_dma_ctrl.scala 266:73]
+    node _T_108 = and(_T_107, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 266:89]
+    node _T_109 = bits(io.dbg_cmd_type, 1, 1) @[el2_dma_ctrl.scala 266:147]
+    node _T_110 = and(io.dbg_cmd_valid, _T_109) @[el2_dma_ctrl.scala 266:130]
+    node _T_111 = and(_T_110, io.dbg_cmd_write) @[el2_dma_ctrl.scala 266:151]
+    node _T_112 = or(_T_108, _T_111) @[el2_dma_ctrl.scala 266:110]
+    node _T_113 = eq(UInt<2>("h02"), WrPtr) @[el2_dma_ctrl.scala 266:179]
+    node _T_114 = and(_T_112, _T_113) @[el2_dma_ctrl.scala 266:172]
+    node _T_115 = or(dma_address_error, dma_alignment_error) @[el2_dma_ctrl.scala 266:213]
+    node _T_116 = eq(UInt<2>("h02"), RdPtr) @[el2_dma_ctrl.scala 266:243]
+    node _T_117 = and(_T_115, _T_116) @[el2_dma_ctrl.scala 266:236]
+    node _T_118 = or(_T_114, _T_117) @[el2_dma_ctrl.scala 266:191]
+    node _T_119 = eq(UInt<2>("h02"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 266:284]
+    node _T_120 = and(io.dccm_dma_rvalid, _T_119) @[el2_dma_ctrl.scala 266:277]
+    node _T_121 = or(_T_118, _T_120) @[el2_dma_ctrl.scala 266:255]
+    node _T_122 = eq(UInt<2>("h02"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 266:336]
+    node _T_123 = and(io.iccm_dma_rvalid, _T_122) @[el2_dma_ctrl.scala 266:329]
+    node _T_124 = or(_T_121, _T_123) @[el2_dma_ctrl.scala 266:307]
+    node _T_125 = and(axi_mstr_prty_en, fifo_write_in) @[el2_dma_ctrl.scala 266:73]
+    node _T_126 = and(_T_125, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 266:89]
+    node _T_127 = bits(io.dbg_cmd_type, 1, 1) @[el2_dma_ctrl.scala 266:147]
+    node _T_128 = and(io.dbg_cmd_valid, _T_127) @[el2_dma_ctrl.scala 266:130]
+    node _T_129 = and(_T_128, io.dbg_cmd_write) @[el2_dma_ctrl.scala 266:151]
+    node _T_130 = or(_T_126, _T_129) @[el2_dma_ctrl.scala 266:110]
+    node _T_131 = eq(UInt<2>("h03"), WrPtr) @[el2_dma_ctrl.scala 266:179]
+    node _T_132 = and(_T_130, _T_131) @[el2_dma_ctrl.scala 266:172]
+    node _T_133 = or(dma_address_error, dma_alignment_error) @[el2_dma_ctrl.scala 266:213]
+    node _T_134 = eq(UInt<2>("h03"), RdPtr) @[el2_dma_ctrl.scala 266:243]
+    node _T_135 = and(_T_133, _T_134) @[el2_dma_ctrl.scala 266:236]
+    node _T_136 = or(_T_132, _T_135) @[el2_dma_ctrl.scala 266:191]
+    node _T_137 = eq(UInt<2>("h03"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 266:284]
+    node _T_138 = and(io.dccm_dma_rvalid, _T_137) @[el2_dma_ctrl.scala 266:277]
+    node _T_139 = or(_T_136, _T_138) @[el2_dma_ctrl.scala 266:255]
+    node _T_140 = eq(UInt<2>("h03"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 266:336]
+    node _T_141 = and(io.iccm_dma_rvalid, _T_140) @[el2_dma_ctrl.scala 266:329]
+    node _T_142 = or(_T_139, _T_141) @[el2_dma_ctrl.scala 266:307]
+    node _T_143 = and(axi_mstr_prty_en, fifo_write_in) @[el2_dma_ctrl.scala 266:73]
+    node _T_144 = and(_T_143, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 266:89]
+    node _T_145 = bits(io.dbg_cmd_type, 1, 1) @[el2_dma_ctrl.scala 266:147]
+    node _T_146 = and(io.dbg_cmd_valid, _T_145) @[el2_dma_ctrl.scala 266:130]
+    node _T_147 = and(_T_146, io.dbg_cmd_write) @[el2_dma_ctrl.scala 266:151]
+    node _T_148 = or(_T_144, _T_147) @[el2_dma_ctrl.scala 266:110]
+    node _T_149 = eq(UInt<3>("h04"), WrPtr) @[el2_dma_ctrl.scala 266:179]
+    node _T_150 = and(_T_148, _T_149) @[el2_dma_ctrl.scala 266:172]
+    node _T_151 = or(dma_address_error, dma_alignment_error) @[el2_dma_ctrl.scala 266:213]
+    node _T_152 = eq(UInt<3>("h04"), RdPtr) @[el2_dma_ctrl.scala 266:243]
+    node _T_153 = and(_T_151, _T_152) @[el2_dma_ctrl.scala 266:236]
+    node _T_154 = or(_T_150, _T_153) @[el2_dma_ctrl.scala 266:191]
+    node _T_155 = eq(UInt<3>("h04"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 266:284]
+    node _T_156 = and(io.dccm_dma_rvalid, _T_155) @[el2_dma_ctrl.scala 266:277]
+    node _T_157 = or(_T_154, _T_156) @[el2_dma_ctrl.scala 266:255]
+    node _T_158 = eq(UInt<3>("h04"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 266:336]
+    node _T_159 = and(io.iccm_dma_rvalid, _T_158) @[el2_dma_ctrl.scala 266:329]
+    node _T_160 = or(_T_157, _T_159) @[el2_dma_ctrl.scala 266:307]
+    node _T_161 = cat(_T_160, _T_142) @[Cat.scala 29:58]
+    node _T_162 = cat(_T_161, _T_124) @[Cat.scala 29:58]
+    node _T_163 = cat(_T_162, _T_106) @[Cat.scala 29:58]
+    node _T_164 = cat(_T_163, _T_88) @[Cat.scala 29:58]
+    fifo_data_en <= _T_164 @[el2_dma_ctrl.scala 266:21]
+    node _T_165 = or(io.dma_dccm_req, io.dma_iccm_req) @[el2_dma_ctrl.scala 268:75]
+    node _T_166 = eq(io.dma_mem_write, UInt<1>("h00")) @[el2_dma_ctrl.scala 268:96]
+    node _T_167 = and(_T_165, _T_166) @[el2_dma_ctrl.scala 268:94]
+    node _T_168 = eq(UInt<1>("h00"), RdPtr) @[el2_dma_ctrl.scala 268:121]
+    node _T_169 = and(_T_167, _T_168) @[el2_dma_ctrl.scala 268:114]
+    node _T_170 = or(io.dma_dccm_req, io.dma_iccm_req) @[el2_dma_ctrl.scala 268:75]
+    node _T_171 = eq(io.dma_mem_write, UInt<1>("h00")) @[el2_dma_ctrl.scala 268:96]
+    node _T_172 = and(_T_170, _T_171) @[el2_dma_ctrl.scala 268:94]
+    node _T_173 = eq(UInt<1>("h01"), RdPtr) @[el2_dma_ctrl.scala 268:121]
+    node _T_174 = and(_T_172, _T_173) @[el2_dma_ctrl.scala 268:114]
+    node _T_175 = or(io.dma_dccm_req, io.dma_iccm_req) @[el2_dma_ctrl.scala 268:75]
+    node _T_176 = eq(io.dma_mem_write, UInt<1>("h00")) @[el2_dma_ctrl.scala 268:96]
+    node _T_177 = and(_T_175, _T_176) @[el2_dma_ctrl.scala 268:94]
+    node _T_178 = eq(UInt<2>("h02"), RdPtr) @[el2_dma_ctrl.scala 268:121]
+    node _T_179 = and(_T_177, _T_178) @[el2_dma_ctrl.scala 268:114]
+    node _T_180 = or(io.dma_dccm_req, io.dma_iccm_req) @[el2_dma_ctrl.scala 268:75]
+    node _T_181 = eq(io.dma_mem_write, UInt<1>("h00")) @[el2_dma_ctrl.scala 268:96]
+    node _T_182 = and(_T_180, _T_181) @[el2_dma_ctrl.scala 268:94]
+    node _T_183 = eq(UInt<2>("h03"), RdPtr) @[el2_dma_ctrl.scala 268:121]
+    node _T_184 = and(_T_182, _T_183) @[el2_dma_ctrl.scala 268:114]
+    node _T_185 = or(io.dma_dccm_req, io.dma_iccm_req) @[el2_dma_ctrl.scala 268:75]
+    node _T_186 = eq(io.dma_mem_write, UInt<1>("h00")) @[el2_dma_ctrl.scala 268:96]
+    node _T_187 = and(_T_185, _T_186) @[el2_dma_ctrl.scala 268:94]
+    node _T_188 = eq(UInt<3>("h04"), RdPtr) @[el2_dma_ctrl.scala 268:121]
+    node _T_189 = and(_T_187, _T_188) @[el2_dma_ctrl.scala 268:114]
+    node _T_190 = cat(_T_189, _T_184) @[Cat.scala 29:58]
+    node _T_191 = cat(_T_190, _T_179) @[Cat.scala 29:58]
+    node _T_192 = cat(_T_191, _T_174) @[Cat.scala 29:58]
+    node _T_193 = cat(_T_192, _T_169) @[Cat.scala 29:58]
+    fifo_pend_en <= _T_193 @[el2_dma_ctrl.scala 268:21]
+    node _T_194 = bits(dma_address_error, 0, 0) @[el2_dma_ctrl.scala 270:78]
+    node _T_195 = bits(dma_alignment_error, 0, 0) @[el2_dma_ctrl.scala 270:107]
+    node _T_196 = or(_T_194, _T_195) @[el2_dma_ctrl.scala 270:85]
+    node _T_197 = or(_T_196, dma_dbg_cmd_error) @[el2_dma_ctrl.scala 270:114]
+    node _T_198 = eq(UInt<1>("h00"), RdPtr) @[el2_dma_ctrl.scala 270:142]
+    node _T_199 = and(_T_197, _T_198) @[el2_dma_ctrl.scala 270:135]
+    node _T_200 = and(io.dccm_dma_rvalid, io.dccm_dma_ecc_error) @[el2_dma_ctrl.scala 270:177]
+    node _T_201 = eq(UInt<1>("h00"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 270:209]
+    node _T_202 = and(_T_200, _T_201) @[el2_dma_ctrl.scala 270:202]
+    node _T_203 = or(_T_199, _T_202) @[el2_dma_ctrl.scala 270:154]
+    node _T_204 = and(io.iccm_dma_rvalid, io.iccm_dma_ecc_error) @[el2_dma_ctrl.scala 270:255]
+    node _T_205 = eq(UInt<1>("h00"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 270:287]
+    node _T_206 = and(_T_204, _T_205) @[el2_dma_ctrl.scala 270:280]
+    node _T_207 = or(_T_203, _T_206) @[el2_dma_ctrl.scala 270:232]
+    node _T_208 = bits(dma_address_error, 0, 0) @[el2_dma_ctrl.scala 270:78]
+    node _T_209 = bits(dma_alignment_error, 0, 0) @[el2_dma_ctrl.scala 270:107]
+    node _T_210 = or(_T_208, _T_209) @[el2_dma_ctrl.scala 270:85]
+    node _T_211 = or(_T_210, dma_dbg_cmd_error) @[el2_dma_ctrl.scala 270:114]
+    node _T_212 = eq(UInt<1>("h01"), RdPtr) @[el2_dma_ctrl.scala 270:142]
+    node _T_213 = and(_T_211, _T_212) @[el2_dma_ctrl.scala 270:135]
+    node _T_214 = and(io.dccm_dma_rvalid, io.dccm_dma_ecc_error) @[el2_dma_ctrl.scala 270:177]
+    node _T_215 = eq(UInt<1>("h01"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 270:209]
+    node _T_216 = and(_T_214, _T_215) @[el2_dma_ctrl.scala 270:202]
+    node _T_217 = or(_T_213, _T_216) @[el2_dma_ctrl.scala 270:154]
+    node _T_218 = and(io.iccm_dma_rvalid, io.iccm_dma_ecc_error) @[el2_dma_ctrl.scala 270:255]
+    node _T_219 = eq(UInt<1>("h01"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 270:287]
+    node _T_220 = and(_T_218, _T_219) @[el2_dma_ctrl.scala 270:280]
+    node _T_221 = or(_T_217, _T_220) @[el2_dma_ctrl.scala 270:232]
+    node _T_222 = bits(dma_address_error, 0, 0) @[el2_dma_ctrl.scala 270:78]
+    node _T_223 = bits(dma_alignment_error, 0, 0) @[el2_dma_ctrl.scala 270:107]
+    node _T_224 = or(_T_222, _T_223) @[el2_dma_ctrl.scala 270:85]
+    node _T_225 = or(_T_224, dma_dbg_cmd_error) @[el2_dma_ctrl.scala 270:114]
+    node _T_226 = eq(UInt<2>("h02"), RdPtr) @[el2_dma_ctrl.scala 270:142]
+    node _T_227 = and(_T_225, _T_226) @[el2_dma_ctrl.scala 270:135]
+    node _T_228 = and(io.dccm_dma_rvalid, io.dccm_dma_ecc_error) @[el2_dma_ctrl.scala 270:177]
+    node _T_229 = eq(UInt<2>("h02"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 270:209]
+    node _T_230 = and(_T_228, _T_229) @[el2_dma_ctrl.scala 270:202]
+    node _T_231 = or(_T_227, _T_230) @[el2_dma_ctrl.scala 270:154]
+    node _T_232 = and(io.iccm_dma_rvalid, io.iccm_dma_ecc_error) @[el2_dma_ctrl.scala 270:255]
+    node _T_233 = eq(UInt<2>("h02"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 270:287]
+    node _T_234 = and(_T_232, _T_233) @[el2_dma_ctrl.scala 270:280]
+    node _T_235 = or(_T_231, _T_234) @[el2_dma_ctrl.scala 270:232]
+    node _T_236 = bits(dma_address_error, 0, 0) @[el2_dma_ctrl.scala 270:78]
+    node _T_237 = bits(dma_alignment_error, 0, 0) @[el2_dma_ctrl.scala 270:107]
+    node _T_238 = or(_T_236, _T_237) @[el2_dma_ctrl.scala 270:85]
+    node _T_239 = or(_T_238, dma_dbg_cmd_error) @[el2_dma_ctrl.scala 270:114]
+    node _T_240 = eq(UInt<2>("h03"), RdPtr) @[el2_dma_ctrl.scala 270:142]
+    node _T_241 = and(_T_239, _T_240) @[el2_dma_ctrl.scala 270:135]
+    node _T_242 = and(io.dccm_dma_rvalid, io.dccm_dma_ecc_error) @[el2_dma_ctrl.scala 270:177]
+    node _T_243 = eq(UInt<2>("h03"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 270:209]
+    node _T_244 = and(_T_242, _T_243) @[el2_dma_ctrl.scala 270:202]
+    node _T_245 = or(_T_241, _T_244) @[el2_dma_ctrl.scala 270:154]
+    node _T_246 = and(io.iccm_dma_rvalid, io.iccm_dma_ecc_error) @[el2_dma_ctrl.scala 270:255]
+    node _T_247 = eq(UInt<2>("h03"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 270:287]
+    node _T_248 = and(_T_246, _T_247) @[el2_dma_ctrl.scala 270:280]
+    node _T_249 = or(_T_245, _T_248) @[el2_dma_ctrl.scala 270:232]
+    node _T_250 = bits(dma_address_error, 0, 0) @[el2_dma_ctrl.scala 270:78]
+    node _T_251 = bits(dma_alignment_error, 0, 0) @[el2_dma_ctrl.scala 270:107]
+    node _T_252 = or(_T_250, _T_251) @[el2_dma_ctrl.scala 270:85]
+    node _T_253 = or(_T_252, dma_dbg_cmd_error) @[el2_dma_ctrl.scala 270:114]
+    node _T_254 = eq(UInt<3>("h04"), RdPtr) @[el2_dma_ctrl.scala 270:142]
+    node _T_255 = and(_T_253, _T_254) @[el2_dma_ctrl.scala 270:135]
+    node _T_256 = and(io.dccm_dma_rvalid, io.dccm_dma_ecc_error) @[el2_dma_ctrl.scala 270:177]
+    node _T_257 = eq(UInt<3>("h04"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 270:209]
+    node _T_258 = and(_T_256, _T_257) @[el2_dma_ctrl.scala 270:202]
+    node _T_259 = or(_T_255, _T_258) @[el2_dma_ctrl.scala 270:154]
+    node _T_260 = and(io.iccm_dma_rvalid, io.iccm_dma_ecc_error) @[el2_dma_ctrl.scala 270:255]
+    node _T_261 = eq(UInt<3>("h04"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 270:287]
+    node _T_262 = and(_T_260, _T_261) @[el2_dma_ctrl.scala 270:280]
+    node _T_263 = or(_T_259, _T_262) @[el2_dma_ctrl.scala 270:232]
+    node _T_264 = cat(_T_263, _T_249) @[Cat.scala 29:58]
+    node _T_265 = cat(_T_264, _T_235) @[Cat.scala 29:58]
+    node _T_266 = cat(_T_265, _T_221) @[Cat.scala 29:58]
+    node _T_267 = cat(_T_266, _T_207) @[Cat.scala 29:58]
+    fifo_error_en <= _T_267 @[el2_dma_ctrl.scala 270:21]
+    node _T_268 = bits(fifo_error_in[0], 1, 0) @[el2_dma_ctrl.scala 272:77]
+    node _T_269 = orr(_T_268) @[el2_dma_ctrl.scala 272:83]
+    node _T_270 = bits(fifo_error_en, 0, 0) @[el2_dma_ctrl.scala 272:103]
+    node _T_271 = and(_T_269, _T_270) @[el2_dma_ctrl.scala 272:88]
+    node _T_272 = orr(fifo_error[0]) @[el2_dma_ctrl.scala 272:125]
+    node _T_273 = or(_T_271, _T_272) @[el2_dma_ctrl.scala 272:108]
+    node _T_274 = and(_T_273, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 272:131]
+    node _T_275 = bits(fifo_error_in[1], 1, 0) @[el2_dma_ctrl.scala 272:77]
+    node _T_276 = orr(_T_275) @[el2_dma_ctrl.scala 272:83]
+    node _T_277 = bits(fifo_error_en, 1, 1) @[el2_dma_ctrl.scala 272:103]
+    node _T_278 = and(_T_276, _T_277) @[el2_dma_ctrl.scala 272:88]
+    node _T_279 = orr(fifo_error[1]) @[el2_dma_ctrl.scala 272:125]
+    node _T_280 = or(_T_278, _T_279) @[el2_dma_ctrl.scala 272:108]
+    node _T_281 = and(_T_280, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 272:131]
+    node _T_282 = bits(fifo_error_in[2], 1, 0) @[el2_dma_ctrl.scala 272:77]
+    node _T_283 = orr(_T_282) @[el2_dma_ctrl.scala 272:83]
+    node _T_284 = bits(fifo_error_en, 2, 2) @[el2_dma_ctrl.scala 272:103]
+    node _T_285 = and(_T_283, _T_284) @[el2_dma_ctrl.scala 272:88]
+    node _T_286 = orr(fifo_error[2]) @[el2_dma_ctrl.scala 272:125]
+    node _T_287 = or(_T_285, _T_286) @[el2_dma_ctrl.scala 272:108]
+    node _T_288 = and(_T_287, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 272:131]
+    node _T_289 = bits(fifo_error_in[3], 1, 0) @[el2_dma_ctrl.scala 272:77]
+    node _T_290 = orr(_T_289) @[el2_dma_ctrl.scala 272:83]
+    node _T_291 = bits(fifo_error_en, 3, 3) @[el2_dma_ctrl.scala 272:103]
+    node _T_292 = and(_T_290, _T_291) @[el2_dma_ctrl.scala 272:88]
+    node _T_293 = orr(fifo_error[3]) @[el2_dma_ctrl.scala 272:125]
+    node _T_294 = or(_T_292, _T_293) @[el2_dma_ctrl.scala 272:108]
+    node _T_295 = and(_T_294, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 272:131]
+    node _T_296 = bits(fifo_error_in[4], 1, 0) @[el2_dma_ctrl.scala 272:77]
+    node _T_297 = orr(_T_296) @[el2_dma_ctrl.scala 272:83]
+    node _T_298 = bits(fifo_error_en, 4, 4) @[el2_dma_ctrl.scala 272:103]
+    node _T_299 = and(_T_297, _T_298) @[el2_dma_ctrl.scala 272:88]
+    node _T_300 = orr(fifo_error[4]) @[el2_dma_ctrl.scala 272:125]
+    node _T_301 = or(_T_299, _T_300) @[el2_dma_ctrl.scala 272:108]
+    node _T_302 = and(_T_301, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 272:131]
+    node _T_303 = cat(_T_302, _T_295) @[Cat.scala 29:58]
+    node _T_304 = cat(_T_303, _T_288) @[Cat.scala 29:58]
+    node _T_305 = cat(_T_304, _T_281) @[Cat.scala 29:58]
+    node _T_306 = cat(_T_305, _T_274) @[Cat.scala 29:58]
+    fifo_error_bus_en <= _T_306 @[el2_dma_ctrl.scala 272:21]
+    node _T_307 = orr(fifo_error[0]) @[el2_dma_ctrl.scala 274:74]
+    node _T_308 = bits(fifo_error_en, 0, 0) @[el2_dma_ctrl.scala 274:93]
+    node _T_309 = or(_T_307, _T_308) @[el2_dma_ctrl.scala 274:78]
+    node _T_310 = or(io.dma_dccm_req, io.dma_iccm_req) @[el2_dma_ctrl.scala 274:117]
+    node _T_311 = and(_T_310, io.dma_mem_write) @[el2_dma_ctrl.scala 274:136]
+    node _T_312 = or(_T_309, _T_311) @[el2_dma_ctrl.scala 274:97]
+    node _T_313 = eq(UInt<1>("h00"), RdPtr) @[el2_dma_ctrl.scala 274:164]
+    node _T_314 = and(_T_312, _T_313) @[el2_dma_ctrl.scala 274:157]
+    node _T_315 = eq(UInt<1>("h00"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 274:205]
+    node _T_316 = and(io.dccm_dma_rvalid, _T_315) @[el2_dma_ctrl.scala 274:198]
+    node _T_317 = or(_T_314, _T_316) @[el2_dma_ctrl.scala 274:176]
+    node _T_318 = eq(UInt<1>("h00"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 274:257]
+    node _T_319 = and(io.iccm_dma_rvalid, _T_318) @[el2_dma_ctrl.scala 274:250]
+    node _T_320 = or(_T_317, _T_319) @[el2_dma_ctrl.scala 274:228]
+    node _T_321 = orr(fifo_error[1]) @[el2_dma_ctrl.scala 274:74]
+    node _T_322 = bits(fifo_error_en, 1, 1) @[el2_dma_ctrl.scala 274:93]
+    node _T_323 = or(_T_321, _T_322) @[el2_dma_ctrl.scala 274:78]
+    node _T_324 = or(io.dma_dccm_req, io.dma_iccm_req) @[el2_dma_ctrl.scala 274:117]
+    node _T_325 = and(_T_324, io.dma_mem_write) @[el2_dma_ctrl.scala 274:136]
+    node _T_326 = or(_T_323, _T_325) @[el2_dma_ctrl.scala 274:97]
+    node _T_327 = eq(UInt<1>("h01"), RdPtr) @[el2_dma_ctrl.scala 274:164]
+    node _T_328 = and(_T_326, _T_327) @[el2_dma_ctrl.scala 274:157]
+    node _T_329 = eq(UInt<1>("h01"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 274:205]
+    node _T_330 = and(io.dccm_dma_rvalid, _T_329) @[el2_dma_ctrl.scala 274:198]
+    node _T_331 = or(_T_328, _T_330) @[el2_dma_ctrl.scala 274:176]
+    node _T_332 = eq(UInt<1>("h01"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 274:257]
+    node _T_333 = and(io.iccm_dma_rvalid, _T_332) @[el2_dma_ctrl.scala 274:250]
+    node _T_334 = or(_T_331, _T_333) @[el2_dma_ctrl.scala 274:228]
+    node _T_335 = orr(fifo_error[2]) @[el2_dma_ctrl.scala 274:74]
+    node _T_336 = bits(fifo_error_en, 2, 2) @[el2_dma_ctrl.scala 274:93]
+    node _T_337 = or(_T_335, _T_336) @[el2_dma_ctrl.scala 274:78]
+    node _T_338 = or(io.dma_dccm_req, io.dma_iccm_req) @[el2_dma_ctrl.scala 274:117]
+    node _T_339 = and(_T_338, io.dma_mem_write) @[el2_dma_ctrl.scala 274:136]
+    node _T_340 = or(_T_337, _T_339) @[el2_dma_ctrl.scala 274:97]
+    node _T_341 = eq(UInt<2>("h02"), RdPtr) @[el2_dma_ctrl.scala 274:164]
+    node _T_342 = and(_T_340, _T_341) @[el2_dma_ctrl.scala 274:157]
+    node _T_343 = eq(UInt<2>("h02"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 274:205]
+    node _T_344 = and(io.dccm_dma_rvalid, _T_343) @[el2_dma_ctrl.scala 274:198]
+    node _T_345 = or(_T_342, _T_344) @[el2_dma_ctrl.scala 274:176]
+    node _T_346 = eq(UInt<2>("h02"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 274:257]
+    node _T_347 = and(io.iccm_dma_rvalid, _T_346) @[el2_dma_ctrl.scala 274:250]
+    node _T_348 = or(_T_345, _T_347) @[el2_dma_ctrl.scala 274:228]
+    node _T_349 = orr(fifo_error[3]) @[el2_dma_ctrl.scala 274:74]
+    node _T_350 = bits(fifo_error_en, 3, 3) @[el2_dma_ctrl.scala 274:93]
+    node _T_351 = or(_T_349, _T_350) @[el2_dma_ctrl.scala 274:78]
+    node _T_352 = or(io.dma_dccm_req, io.dma_iccm_req) @[el2_dma_ctrl.scala 274:117]
+    node _T_353 = and(_T_352, io.dma_mem_write) @[el2_dma_ctrl.scala 274:136]
+    node _T_354 = or(_T_351, _T_353) @[el2_dma_ctrl.scala 274:97]
+    node _T_355 = eq(UInt<2>("h03"), RdPtr) @[el2_dma_ctrl.scala 274:164]
+    node _T_356 = and(_T_354, _T_355) @[el2_dma_ctrl.scala 274:157]
+    node _T_357 = eq(UInt<2>("h03"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 274:205]
+    node _T_358 = and(io.dccm_dma_rvalid, _T_357) @[el2_dma_ctrl.scala 274:198]
+    node _T_359 = or(_T_356, _T_358) @[el2_dma_ctrl.scala 274:176]
+    node _T_360 = eq(UInt<2>("h03"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 274:257]
+    node _T_361 = and(io.iccm_dma_rvalid, _T_360) @[el2_dma_ctrl.scala 274:250]
+    node _T_362 = or(_T_359, _T_361) @[el2_dma_ctrl.scala 274:228]
+    node _T_363 = orr(fifo_error[4]) @[el2_dma_ctrl.scala 274:74]
+    node _T_364 = bits(fifo_error_en, 4, 4) @[el2_dma_ctrl.scala 274:93]
+    node _T_365 = or(_T_363, _T_364) @[el2_dma_ctrl.scala 274:78]
+    node _T_366 = or(io.dma_dccm_req, io.dma_iccm_req) @[el2_dma_ctrl.scala 274:117]
+    node _T_367 = and(_T_366, io.dma_mem_write) @[el2_dma_ctrl.scala 274:136]
+    node _T_368 = or(_T_365, _T_367) @[el2_dma_ctrl.scala 274:97]
+    node _T_369 = eq(UInt<3>("h04"), RdPtr) @[el2_dma_ctrl.scala 274:164]
+    node _T_370 = and(_T_368, _T_369) @[el2_dma_ctrl.scala 274:157]
+    node _T_371 = eq(UInt<3>("h04"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 274:205]
+    node _T_372 = and(io.dccm_dma_rvalid, _T_371) @[el2_dma_ctrl.scala 274:198]
+    node _T_373 = or(_T_370, _T_372) @[el2_dma_ctrl.scala 274:176]
+    node _T_374 = eq(UInt<3>("h04"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 274:257]
+    node _T_375 = and(io.iccm_dma_rvalid, _T_374) @[el2_dma_ctrl.scala 274:250]
+    node _T_376 = or(_T_373, _T_375) @[el2_dma_ctrl.scala 274:228]
+    node _T_377 = cat(_T_376, _T_362) @[Cat.scala 29:58]
+    node _T_378 = cat(_T_377, _T_348) @[Cat.scala 29:58]
+    node _T_379 = cat(_T_378, _T_334) @[Cat.scala 29:58]
+    node _T_380 = cat(_T_379, _T_320) @[Cat.scala 29:58]
+    fifo_done_en <= _T_380 @[el2_dma_ctrl.scala 274:21]
+    node _T_381 = bits(fifo_done_en, 0, 0) @[el2_dma_ctrl.scala 276:71]
+    node _T_382 = bits(fifo_done, 0, 0) @[el2_dma_ctrl.scala 276:86]
+    node _T_383 = or(_T_381, _T_382) @[el2_dma_ctrl.scala 276:75]
+    node _T_384 = and(_T_383, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 276:91]
+    node _T_385 = bits(fifo_done_en, 1, 1) @[el2_dma_ctrl.scala 276:71]
+    node _T_386 = bits(fifo_done, 1, 1) @[el2_dma_ctrl.scala 276:86]
+    node _T_387 = or(_T_385, _T_386) @[el2_dma_ctrl.scala 276:75]
+    node _T_388 = and(_T_387, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 276:91]
+    node _T_389 = bits(fifo_done_en, 2, 2) @[el2_dma_ctrl.scala 276:71]
+    node _T_390 = bits(fifo_done, 2, 2) @[el2_dma_ctrl.scala 276:86]
+    node _T_391 = or(_T_389, _T_390) @[el2_dma_ctrl.scala 276:75]
+    node _T_392 = and(_T_391, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 276:91]
+    node _T_393 = bits(fifo_done_en, 3, 3) @[el2_dma_ctrl.scala 276:71]
+    node _T_394 = bits(fifo_done, 3, 3) @[el2_dma_ctrl.scala 276:86]
+    node _T_395 = or(_T_393, _T_394) @[el2_dma_ctrl.scala 276:75]
+    node _T_396 = and(_T_395, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 276:91]
+    node _T_397 = bits(fifo_done_en, 4, 4) @[el2_dma_ctrl.scala 276:71]
+    node _T_398 = bits(fifo_done, 4, 4) @[el2_dma_ctrl.scala 276:86]
+    node _T_399 = or(_T_397, _T_398) @[el2_dma_ctrl.scala 276:75]
+    node _T_400 = and(_T_399, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 276:91]
+    node _T_401 = cat(_T_400, _T_396) @[Cat.scala 29:58]
+    node _T_402 = cat(_T_401, _T_392) @[Cat.scala 29:58]
+    node _T_403 = cat(_T_402, _T_388) @[Cat.scala 29:58]
+    node _T_404 = cat(_T_403, _T_384) @[Cat.scala 29:58]
+    fifo_done_bus_en <= _T_404 @[el2_dma_ctrl.scala 276:21]
+    node _T_405 = or(bus_rsp_sent, bus_posted_write_done) @[el2_dma_ctrl.scala 278:74]
+    node _T_406 = and(_T_405, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 278:99]
+    node _T_407 = or(_T_406, io.dma_dbg_cmd_done) @[el2_dma_ctrl.scala 278:120]
+    node _T_408 = eq(UInt<1>("h00"), RspPtr) @[el2_dma_ctrl.scala 278:150]
+    node _T_409 = and(_T_407, _T_408) @[el2_dma_ctrl.scala 278:143]
+    node _T_410 = or(bus_rsp_sent, bus_posted_write_done) @[el2_dma_ctrl.scala 278:74]
+    node _T_411 = and(_T_410, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 278:99]
+    node _T_412 = or(_T_411, io.dma_dbg_cmd_done) @[el2_dma_ctrl.scala 278:120]
+    node _T_413 = eq(UInt<1>("h01"), RspPtr) @[el2_dma_ctrl.scala 278:150]
+    node _T_414 = and(_T_412, _T_413) @[el2_dma_ctrl.scala 278:143]
+    node _T_415 = or(bus_rsp_sent, bus_posted_write_done) @[el2_dma_ctrl.scala 278:74]
+    node _T_416 = and(_T_415, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 278:99]
+    node _T_417 = or(_T_416, io.dma_dbg_cmd_done) @[el2_dma_ctrl.scala 278:120]
+    node _T_418 = eq(UInt<2>("h02"), RspPtr) @[el2_dma_ctrl.scala 278:150]
+    node _T_419 = and(_T_417, _T_418) @[el2_dma_ctrl.scala 278:143]
+    node _T_420 = or(bus_rsp_sent, bus_posted_write_done) @[el2_dma_ctrl.scala 278:74]
+    node _T_421 = and(_T_420, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 278:99]
+    node _T_422 = or(_T_421, io.dma_dbg_cmd_done) @[el2_dma_ctrl.scala 278:120]
+    node _T_423 = eq(UInt<2>("h03"), RspPtr) @[el2_dma_ctrl.scala 278:150]
+    node _T_424 = and(_T_422, _T_423) @[el2_dma_ctrl.scala 278:143]
+    node _T_425 = or(bus_rsp_sent, bus_posted_write_done) @[el2_dma_ctrl.scala 278:74]
+    node _T_426 = and(_T_425, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 278:99]
+    node _T_427 = or(_T_426, io.dma_dbg_cmd_done) @[el2_dma_ctrl.scala 278:120]
+    node _T_428 = eq(UInt<3>("h04"), RspPtr) @[el2_dma_ctrl.scala 278:150]
+    node _T_429 = and(_T_427, _T_428) @[el2_dma_ctrl.scala 278:143]
+    node _T_430 = cat(_T_429, _T_424) @[Cat.scala 29:58]
+    node _T_431 = cat(_T_430, _T_419) @[Cat.scala 29:58]
+    node _T_432 = cat(_T_431, _T_414) @[Cat.scala 29:58]
+    node _T_433 = cat(_T_432, _T_409) @[Cat.scala 29:58]
+    fifo_reset <= _T_433 @[el2_dma_ctrl.scala 278:21]
+    node _T_434 = eq(UInt<1>("h00"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 280:87]
+    node _T_435 = and(io.dccm_dma_rvalid, _T_434) @[el2_dma_ctrl.scala 280:80]
+    node _T_436 = cat(UInt<1>("h00"), io.dccm_dma_ecc_error) @[Cat.scala 29:58]
+    node _T_437 = eq(UInt<1>("h00"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 280:173]
+    node _T_438 = and(io.iccm_dma_rvalid, _T_437) @[el2_dma_ctrl.scala 280:166]
+    node _T_439 = cat(UInt<1>("h00"), io.iccm_dma_ecc_error) @[Cat.scala 29:58]
+    node _T_440 = or(dma_address_error, dma_alignment_error) @[el2_dma_ctrl.scala 280:255]
+    node _T_441 = or(_T_440, dma_dbg_cmd_error) @[el2_dma_ctrl.scala 280:277]
+    node _T_442 = cat(_T_441, dma_alignment_error) @[Cat.scala 29:58]
+    node _T_443 = mux(_T_438, _T_439, _T_442) @[el2_dma_ctrl.scala 280:146]
+    node _T_444 = mux(_T_435, _T_436, _T_443) @[el2_dma_ctrl.scala 280:60]
+    fifo_error_in[0] <= _T_444 @[el2_dma_ctrl.scala 280:53]
+    node _T_445 = eq(UInt<1>("h01"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 280:87]
+    node _T_446 = and(io.dccm_dma_rvalid, _T_445) @[el2_dma_ctrl.scala 280:80]
+    node _T_447 = cat(UInt<1>("h00"), io.dccm_dma_ecc_error) @[Cat.scala 29:58]
+    node _T_448 = eq(UInt<1>("h01"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 280:173]
+    node _T_449 = and(io.iccm_dma_rvalid, _T_448) @[el2_dma_ctrl.scala 280:166]
+    node _T_450 = cat(UInt<1>("h00"), io.iccm_dma_ecc_error) @[Cat.scala 29:58]
+    node _T_451 = or(dma_address_error, dma_alignment_error) @[el2_dma_ctrl.scala 280:255]
+    node _T_452 = or(_T_451, dma_dbg_cmd_error) @[el2_dma_ctrl.scala 280:277]
+    node _T_453 = cat(_T_452, dma_alignment_error) @[Cat.scala 29:58]
+    node _T_454 = mux(_T_449, _T_450, _T_453) @[el2_dma_ctrl.scala 280:146]
+    node _T_455 = mux(_T_446, _T_447, _T_454) @[el2_dma_ctrl.scala 280:60]
+    fifo_error_in[1] <= _T_455 @[el2_dma_ctrl.scala 280:53]
+    node _T_456 = eq(UInt<2>("h02"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 280:87]
+    node _T_457 = and(io.dccm_dma_rvalid, _T_456) @[el2_dma_ctrl.scala 280:80]
+    node _T_458 = cat(UInt<1>("h00"), io.dccm_dma_ecc_error) @[Cat.scala 29:58]
+    node _T_459 = eq(UInt<2>("h02"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 280:173]
+    node _T_460 = and(io.iccm_dma_rvalid, _T_459) @[el2_dma_ctrl.scala 280:166]
+    node _T_461 = cat(UInt<1>("h00"), io.iccm_dma_ecc_error) @[Cat.scala 29:58]
+    node _T_462 = or(dma_address_error, dma_alignment_error) @[el2_dma_ctrl.scala 280:255]
+    node _T_463 = or(_T_462, dma_dbg_cmd_error) @[el2_dma_ctrl.scala 280:277]
+    node _T_464 = cat(_T_463, dma_alignment_error) @[Cat.scala 29:58]
+    node _T_465 = mux(_T_460, _T_461, _T_464) @[el2_dma_ctrl.scala 280:146]
+    node _T_466 = mux(_T_457, _T_458, _T_465) @[el2_dma_ctrl.scala 280:60]
+    fifo_error_in[2] <= _T_466 @[el2_dma_ctrl.scala 280:53]
+    node _T_467 = eq(UInt<2>("h03"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 280:87]
+    node _T_468 = and(io.dccm_dma_rvalid, _T_467) @[el2_dma_ctrl.scala 280:80]
+    node _T_469 = cat(UInt<1>("h00"), io.dccm_dma_ecc_error) @[Cat.scala 29:58]
+    node _T_470 = eq(UInt<2>("h03"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 280:173]
+    node _T_471 = and(io.iccm_dma_rvalid, _T_470) @[el2_dma_ctrl.scala 280:166]
+    node _T_472 = cat(UInt<1>("h00"), io.iccm_dma_ecc_error) @[Cat.scala 29:58]
+    node _T_473 = or(dma_address_error, dma_alignment_error) @[el2_dma_ctrl.scala 280:255]
+    node _T_474 = or(_T_473, dma_dbg_cmd_error) @[el2_dma_ctrl.scala 280:277]
+    node _T_475 = cat(_T_474, dma_alignment_error) @[Cat.scala 29:58]
+    node _T_476 = mux(_T_471, _T_472, _T_475) @[el2_dma_ctrl.scala 280:146]
+    node _T_477 = mux(_T_468, _T_469, _T_476) @[el2_dma_ctrl.scala 280:60]
+    fifo_error_in[3] <= _T_477 @[el2_dma_ctrl.scala 280:53]
+    node _T_478 = eq(UInt<3>("h04"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 280:87]
+    node _T_479 = and(io.dccm_dma_rvalid, _T_478) @[el2_dma_ctrl.scala 280:80]
+    node _T_480 = cat(UInt<1>("h00"), io.dccm_dma_ecc_error) @[Cat.scala 29:58]
+    node _T_481 = eq(UInt<3>("h04"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 280:173]
+    node _T_482 = and(io.iccm_dma_rvalid, _T_481) @[el2_dma_ctrl.scala 280:166]
+    node _T_483 = cat(UInt<1>("h00"), io.iccm_dma_ecc_error) @[Cat.scala 29:58]
+    node _T_484 = or(dma_address_error, dma_alignment_error) @[el2_dma_ctrl.scala 280:255]
+    node _T_485 = or(_T_484, dma_dbg_cmd_error) @[el2_dma_ctrl.scala 280:277]
+    node _T_486 = cat(_T_485, dma_alignment_error) @[Cat.scala 29:58]
+    node _T_487 = mux(_T_482, _T_483, _T_486) @[el2_dma_ctrl.scala 280:146]
+    node _T_488 = mux(_T_479, _T_480, _T_487) @[el2_dma_ctrl.scala 280:60]
+    fifo_error_in[4] <= _T_488 @[el2_dma_ctrl.scala 280:53]
+    node _T_489 = bits(fifo_error_en, 0, 0) @[el2_dma_ctrl.scala 282:73]
+    node _T_490 = orr(fifo_error_in[0]) @[el2_dma_ctrl.scala 282:97]
+    node _T_491 = and(_T_489, _T_490) @[el2_dma_ctrl.scala 282:77]
+    node _T_492 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_493 = cat(_T_492, fifo_addr[0]) @[Cat.scala 29:58]
+    node _T_494 = eq(UInt<1>("h00"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 282:167]
+    node _T_495 = and(io.dccm_dma_rvalid, _T_494) @[el2_dma_ctrl.scala 282:160]
+    node _T_496 = eq(UInt<1>("h00"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 282:239]
+    node _T_497 = and(io.iccm_dma_rvalid, _T_496) @[el2_dma_ctrl.scala 282:232]
+    node _T_498 = cat(io.dbg_cmd_wrdata, io.dbg_cmd_wrdata) @[Cat.scala 29:58]
+    node _T_499 = bits(bus_cmd_wdata, 63, 0) @[el2_dma_ctrl.scala 282:344]
+    node _T_500 = mux(io.dbg_cmd_valid, _T_498, _T_499) @[el2_dma_ctrl.scala 282:284]
+    node _T_501 = mux(_T_497, io.iccm_dma_rdata, _T_500) @[el2_dma_ctrl.scala 282:212]
+    node _T_502 = mux(_T_495, io.dccm_dma_rdata, _T_501) @[el2_dma_ctrl.scala 282:140]
+    node _T_503 = mux(_T_491, _T_493, _T_502) @[el2_dma_ctrl.scala 282:59]
+    fifo_data_in[0] <= _T_503 @[el2_dma_ctrl.scala 282:52]
+    node _T_504 = bits(fifo_error_en, 1, 1) @[el2_dma_ctrl.scala 282:73]
+    node _T_505 = orr(fifo_error_in[1]) @[el2_dma_ctrl.scala 282:97]
+    node _T_506 = and(_T_504, _T_505) @[el2_dma_ctrl.scala 282:77]
+    node _T_507 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_508 = cat(_T_507, fifo_addr[1]) @[Cat.scala 29:58]
+    node _T_509 = eq(UInt<1>("h01"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 282:167]
+    node _T_510 = and(io.dccm_dma_rvalid, _T_509) @[el2_dma_ctrl.scala 282:160]
+    node _T_511 = eq(UInt<1>("h01"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 282:239]
+    node _T_512 = and(io.iccm_dma_rvalid, _T_511) @[el2_dma_ctrl.scala 282:232]
+    node _T_513 = cat(io.dbg_cmd_wrdata, io.dbg_cmd_wrdata) @[Cat.scala 29:58]
+    node _T_514 = bits(bus_cmd_wdata, 63, 0) @[el2_dma_ctrl.scala 282:344]
+    node _T_515 = mux(io.dbg_cmd_valid, _T_513, _T_514) @[el2_dma_ctrl.scala 282:284]
+    node _T_516 = mux(_T_512, io.iccm_dma_rdata, _T_515) @[el2_dma_ctrl.scala 282:212]
+    node _T_517 = mux(_T_510, io.dccm_dma_rdata, _T_516) @[el2_dma_ctrl.scala 282:140]
+    node _T_518 = mux(_T_506, _T_508, _T_517) @[el2_dma_ctrl.scala 282:59]
+    fifo_data_in[1] <= _T_518 @[el2_dma_ctrl.scala 282:52]
+    node _T_519 = bits(fifo_error_en, 2, 2) @[el2_dma_ctrl.scala 282:73]
+    node _T_520 = orr(fifo_error_in[2]) @[el2_dma_ctrl.scala 282:97]
+    node _T_521 = and(_T_519, _T_520) @[el2_dma_ctrl.scala 282:77]
+    node _T_522 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_523 = cat(_T_522, fifo_addr[2]) @[Cat.scala 29:58]
+    node _T_524 = eq(UInt<2>("h02"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 282:167]
+    node _T_525 = and(io.dccm_dma_rvalid, _T_524) @[el2_dma_ctrl.scala 282:160]
+    node _T_526 = eq(UInt<2>("h02"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 282:239]
+    node _T_527 = and(io.iccm_dma_rvalid, _T_526) @[el2_dma_ctrl.scala 282:232]
+    node _T_528 = cat(io.dbg_cmd_wrdata, io.dbg_cmd_wrdata) @[Cat.scala 29:58]
+    node _T_529 = bits(bus_cmd_wdata, 63, 0) @[el2_dma_ctrl.scala 282:344]
+    node _T_530 = mux(io.dbg_cmd_valid, _T_528, _T_529) @[el2_dma_ctrl.scala 282:284]
+    node _T_531 = mux(_T_527, io.iccm_dma_rdata, _T_530) @[el2_dma_ctrl.scala 282:212]
+    node _T_532 = mux(_T_525, io.dccm_dma_rdata, _T_531) @[el2_dma_ctrl.scala 282:140]
+    node _T_533 = mux(_T_521, _T_523, _T_532) @[el2_dma_ctrl.scala 282:59]
+    fifo_data_in[2] <= _T_533 @[el2_dma_ctrl.scala 282:52]
+    node _T_534 = bits(fifo_error_en, 3, 3) @[el2_dma_ctrl.scala 282:73]
+    node _T_535 = orr(fifo_error_in[3]) @[el2_dma_ctrl.scala 282:97]
+    node _T_536 = and(_T_534, _T_535) @[el2_dma_ctrl.scala 282:77]
+    node _T_537 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_538 = cat(_T_537, fifo_addr[3]) @[Cat.scala 29:58]
+    node _T_539 = eq(UInt<2>("h03"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 282:167]
+    node _T_540 = and(io.dccm_dma_rvalid, _T_539) @[el2_dma_ctrl.scala 282:160]
+    node _T_541 = eq(UInt<2>("h03"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 282:239]
+    node _T_542 = and(io.iccm_dma_rvalid, _T_541) @[el2_dma_ctrl.scala 282:232]
+    node _T_543 = cat(io.dbg_cmd_wrdata, io.dbg_cmd_wrdata) @[Cat.scala 29:58]
+    node _T_544 = bits(bus_cmd_wdata, 63, 0) @[el2_dma_ctrl.scala 282:344]
+    node _T_545 = mux(io.dbg_cmd_valid, _T_543, _T_544) @[el2_dma_ctrl.scala 282:284]
+    node _T_546 = mux(_T_542, io.iccm_dma_rdata, _T_545) @[el2_dma_ctrl.scala 282:212]
+    node _T_547 = mux(_T_540, io.dccm_dma_rdata, _T_546) @[el2_dma_ctrl.scala 282:140]
+    node _T_548 = mux(_T_536, _T_538, _T_547) @[el2_dma_ctrl.scala 282:59]
+    fifo_data_in[3] <= _T_548 @[el2_dma_ctrl.scala 282:52]
+    node _T_549 = bits(fifo_error_en, 4, 4) @[el2_dma_ctrl.scala 282:73]
+    node _T_550 = orr(fifo_error_in[4]) @[el2_dma_ctrl.scala 282:97]
+    node _T_551 = and(_T_549, _T_550) @[el2_dma_ctrl.scala 282:77]
+    node _T_552 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_553 = cat(_T_552, fifo_addr[4]) @[Cat.scala 29:58]
+    node _T_554 = eq(UInt<3>("h04"), io.dccm_dma_rtag) @[el2_dma_ctrl.scala 282:167]
+    node _T_555 = and(io.dccm_dma_rvalid, _T_554) @[el2_dma_ctrl.scala 282:160]
+    node _T_556 = eq(UInt<3>("h04"), io.iccm_dma_rtag) @[el2_dma_ctrl.scala 282:239]
+    node _T_557 = and(io.iccm_dma_rvalid, _T_556) @[el2_dma_ctrl.scala 282:232]
+    node _T_558 = cat(io.dbg_cmd_wrdata, io.dbg_cmd_wrdata) @[Cat.scala 29:58]
+    node _T_559 = bits(bus_cmd_wdata, 63, 0) @[el2_dma_ctrl.scala 282:344]
+    node _T_560 = mux(io.dbg_cmd_valid, _T_558, _T_559) @[el2_dma_ctrl.scala 282:284]
+    node _T_561 = mux(_T_557, io.iccm_dma_rdata, _T_560) @[el2_dma_ctrl.scala 282:212]
+    node _T_562 = mux(_T_555, io.dccm_dma_rdata, _T_561) @[el2_dma_ctrl.scala 282:140]
+    node _T_563 = mux(_T_551, _T_553, _T_562) @[el2_dma_ctrl.scala 282:59]
+    fifo_data_in[4] <= _T_563 @[el2_dma_ctrl.scala 282:52]
+    node _T_564 = bits(fifo_cmd_en, 0, 0) @[el2_dma_ctrl.scala 284:98]
+    node _T_565 = bits(fifo_valid, 0, 0) @[el2_dma_ctrl.scala 284:118]
+    node _T_566 = mux(_T_564, UInt<1>("h01"), _T_565) @[el2_dma_ctrl.scala 284:86]
+    node _T_567 = bits(fifo_reset, 0, 0) @[el2_dma_ctrl.scala 284:136]
+    node _T_568 = eq(_T_567, UInt<1>("h00")) @[el2_dma_ctrl.scala 284:125]
+    node _T_569 = and(_T_566, _T_568) @[el2_dma_ctrl.scala 284:123]
+    reg _T_570 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 284:82]
+    _T_570 <= _T_569 @[el2_dma_ctrl.scala 284:82]
+    node _T_571 = bits(fifo_cmd_en, 1, 1) @[el2_dma_ctrl.scala 284:98]
+    node _T_572 = bits(fifo_valid, 1, 1) @[el2_dma_ctrl.scala 284:118]
+    node _T_573 = mux(_T_571, UInt<1>("h01"), _T_572) @[el2_dma_ctrl.scala 284:86]
+    node _T_574 = bits(fifo_reset, 1, 1) @[el2_dma_ctrl.scala 284:136]
+    node _T_575 = eq(_T_574, UInt<1>("h00")) @[el2_dma_ctrl.scala 284:125]
+    node _T_576 = and(_T_573, _T_575) @[el2_dma_ctrl.scala 284:123]
+    reg _T_577 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 284:82]
+    _T_577 <= _T_576 @[el2_dma_ctrl.scala 284:82]
+    node _T_578 = bits(fifo_cmd_en, 2, 2) @[el2_dma_ctrl.scala 284:98]
+    node _T_579 = bits(fifo_valid, 2, 2) @[el2_dma_ctrl.scala 284:118]
+    node _T_580 = mux(_T_578, UInt<1>("h01"), _T_579) @[el2_dma_ctrl.scala 284:86]
+    node _T_581 = bits(fifo_reset, 2, 2) @[el2_dma_ctrl.scala 284:136]
+    node _T_582 = eq(_T_581, UInt<1>("h00")) @[el2_dma_ctrl.scala 284:125]
+    node _T_583 = and(_T_580, _T_582) @[el2_dma_ctrl.scala 284:123]
+    reg _T_584 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 284:82]
+    _T_584 <= _T_583 @[el2_dma_ctrl.scala 284:82]
+    node _T_585 = bits(fifo_cmd_en, 3, 3) @[el2_dma_ctrl.scala 284:98]
+    node _T_586 = bits(fifo_valid, 3, 3) @[el2_dma_ctrl.scala 284:118]
+    node _T_587 = mux(_T_585, UInt<1>("h01"), _T_586) @[el2_dma_ctrl.scala 284:86]
+    node _T_588 = bits(fifo_reset, 3, 3) @[el2_dma_ctrl.scala 284:136]
+    node _T_589 = eq(_T_588, UInt<1>("h00")) @[el2_dma_ctrl.scala 284:125]
+    node _T_590 = and(_T_587, _T_589) @[el2_dma_ctrl.scala 284:123]
+    reg _T_591 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 284:82]
+    _T_591 <= _T_590 @[el2_dma_ctrl.scala 284:82]
+    node _T_592 = bits(fifo_cmd_en, 4, 4) @[el2_dma_ctrl.scala 284:98]
+    node _T_593 = bits(fifo_valid, 4, 4) @[el2_dma_ctrl.scala 284:118]
+    node _T_594 = mux(_T_592, UInt<1>("h01"), _T_593) @[el2_dma_ctrl.scala 284:86]
+    node _T_595 = bits(fifo_reset, 4, 4) @[el2_dma_ctrl.scala 284:136]
+    node _T_596 = eq(_T_595, UInt<1>("h00")) @[el2_dma_ctrl.scala 284:125]
+    node _T_597 = and(_T_594, _T_596) @[el2_dma_ctrl.scala 284:123]
+    reg _T_598 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 284:82]
+    _T_598 <= _T_597 @[el2_dma_ctrl.scala 284:82]
+    node _T_599 = cat(_T_598, _T_591) @[Cat.scala 29:58]
+    node _T_600 = cat(_T_599, _T_584) @[Cat.scala 29:58]
+    node _T_601 = cat(_T_600, _T_577) @[Cat.scala 29:58]
+    node _T_602 = cat(_T_601, _T_570) @[Cat.scala 29:58]
+    fifo_valid <= _T_602 @[el2_dma_ctrl.scala 284:14]
+    node _T_603 = bits(fifo_error_en, 0, 0) @[el2_dma_ctrl.scala 286:103]
+    node _T_604 = bits(_T_603, 0, 0) @[el2_dma_ctrl.scala 286:113]
+    node _T_605 = mux(_T_604, fifo_error_in[0], fifo_error[0]) @[el2_dma_ctrl.scala 286:89]
+    node _T_606 = bits(fifo_reset, 0, 0) @[el2_dma_ctrl.scala 286:196]
+    node _T_607 = eq(_T_606, UInt<1>("h00")) @[el2_dma_ctrl.scala 286:185]
+    node _T_608 = bits(_T_607, 0, 0) @[Bitwise.scala 72:15]
+    node _T_609 = mux(_T_608, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+    node _T_610 = and(_T_605, _T_609) @[el2_dma_ctrl.scala 286:150]
+    reg _T_611 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 286:85]
+    _T_611 <= _T_610 @[el2_dma_ctrl.scala 286:85]
+    fifo_error[0] <= _T_611 @[el2_dma_ctrl.scala 286:50]
+    node _T_612 = bits(fifo_error_en, 1, 1) @[el2_dma_ctrl.scala 286:103]
+    node _T_613 = bits(_T_612, 0, 0) @[el2_dma_ctrl.scala 286:113]
+    node _T_614 = mux(_T_613, fifo_error_in[1], fifo_error[1]) @[el2_dma_ctrl.scala 286:89]
+    node _T_615 = bits(fifo_reset, 1, 1) @[el2_dma_ctrl.scala 286:196]
+    node _T_616 = eq(_T_615, UInt<1>("h00")) @[el2_dma_ctrl.scala 286:185]
+    node _T_617 = bits(_T_616, 0, 0) @[Bitwise.scala 72:15]
+    node _T_618 = mux(_T_617, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+    node _T_619 = and(_T_614, _T_618) @[el2_dma_ctrl.scala 286:150]
+    reg _T_620 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 286:85]
+    _T_620 <= _T_619 @[el2_dma_ctrl.scala 286:85]
+    fifo_error[1] <= _T_620 @[el2_dma_ctrl.scala 286:50]
+    node _T_621 = bits(fifo_error_en, 2, 2) @[el2_dma_ctrl.scala 286:103]
+    node _T_622 = bits(_T_621, 0, 0) @[el2_dma_ctrl.scala 286:113]
+    node _T_623 = mux(_T_622, fifo_error_in[2], fifo_error[2]) @[el2_dma_ctrl.scala 286:89]
+    node _T_624 = bits(fifo_reset, 2, 2) @[el2_dma_ctrl.scala 286:196]
+    node _T_625 = eq(_T_624, UInt<1>("h00")) @[el2_dma_ctrl.scala 286:185]
+    node _T_626 = bits(_T_625, 0, 0) @[Bitwise.scala 72:15]
+    node _T_627 = mux(_T_626, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+    node _T_628 = and(_T_623, _T_627) @[el2_dma_ctrl.scala 286:150]
+    reg _T_629 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 286:85]
+    _T_629 <= _T_628 @[el2_dma_ctrl.scala 286:85]
+    fifo_error[2] <= _T_629 @[el2_dma_ctrl.scala 286:50]
+    node _T_630 = bits(fifo_error_en, 3, 3) @[el2_dma_ctrl.scala 286:103]
+    node _T_631 = bits(_T_630, 0, 0) @[el2_dma_ctrl.scala 286:113]
+    node _T_632 = mux(_T_631, fifo_error_in[3], fifo_error[3]) @[el2_dma_ctrl.scala 286:89]
+    node _T_633 = bits(fifo_reset, 3, 3) @[el2_dma_ctrl.scala 286:196]
+    node _T_634 = eq(_T_633, UInt<1>("h00")) @[el2_dma_ctrl.scala 286:185]
+    node _T_635 = bits(_T_634, 0, 0) @[Bitwise.scala 72:15]
+    node _T_636 = mux(_T_635, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+    node _T_637 = and(_T_632, _T_636) @[el2_dma_ctrl.scala 286:150]
+    reg _T_638 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 286:85]
+    _T_638 <= _T_637 @[el2_dma_ctrl.scala 286:85]
+    fifo_error[3] <= _T_638 @[el2_dma_ctrl.scala 286:50]
+    node _T_639 = bits(fifo_error_en, 4, 4) @[el2_dma_ctrl.scala 286:103]
+    node _T_640 = bits(_T_639, 0, 0) @[el2_dma_ctrl.scala 286:113]
+    node _T_641 = mux(_T_640, fifo_error_in[4], fifo_error[4]) @[el2_dma_ctrl.scala 286:89]
+    node _T_642 = bits(fifo_reset, 4, 4) @[el2_dma_ctrl.scala 286:196]
+    node _T_643 = eq(_T_642, UInt<1>("h00")) @[el2_dma_ctrl.scala 286:185]
+    node _T_644 = bits(_T_643, 0, 0) @[Bitwise.scala 72:15]
+    node _T_645 = mux(_T_644, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+    node _T_646 = and(_T_641, _T_645) @[el2_dma_ctrl.scala 286:150]
+    reg _T_647 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 286:85]
+    _T_647 <= _T_646 @[el2_dma_ctrl.scala 286:85]
+    fifo_error[4] <= _T_647 @[el2_dma_ctrl.scala 286:50]
+    node _T_648 = bits(fifo_error_bus_en, 0, 0) @[el2_dma_ctrl.scala 288:111]
+    node _T_649 = bits(fifo_error_bus, 0, 0) @[el2_dma_ctrl.scala 288:135]
+    node _T_650 = mux(_T_648, UInt<1>("h01"), _T_649) @[el2_dma_ctrl.scala 288:93]
+    node _T_651 = bits(fifo_reset, 0, 0) @[el2_dma_ctrl.scala 288:153]
+    node _T_652 = eq(_T_651, UInt<1>("h00")) @[el2_dma_ctrl.scala 288:142]
+    node _T_653 = and(_T_650, _T_652) @[el2_dma_ctrl.scala 288:140]
+    reg _T_654 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 288:89]
+    _T_654 <= _T_653 @[el2_dma_ctrl.scala 288:89]
+    node _T_655 = bits(fifo_error_bus_en, 1, 1) @[el2_dma_ctrl.scala 288:111]
+    node _T_656 = bits(fifo_error_bus, 1, 1) @[el2_dma_ctrl.scala 288:135]
+    node _T_657 = mux(_T_655, UInt<1>("h01"), _T_656) @[el2_dma_ctrl.scala 288:93]
+    node _T_658 = bits(fifo_reset, 1, 1) @[el2_dma_ctrl.scala 288:153]
+    node _T_659 = eq(_T_658, UInt<1>("h00")) @[el2_dma_ctrl.scala 288:142]
+    node _T_660 = and(_T_657, _T_659) @[el2_dma_ctrl.scala 288:140]
+    reg _T_661 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 288:89]
+    _T_661 <= _T_660 @[el2_dma_ctrl.scala 288:89]
+    node _T_662 = bits(fifo_error_bus_en, 2, 2) @[el2_dma_ctrl.scala 288:111]
+    node _T_663 = bits(fifo_error_bus, 2, 2) @[el2_dma_ctrl.scala 288:135]
+    node _T_664 = mux(_T_662, UInt<1>("h01"), _T_663) @[el2_dma_ctrl.scala 288:93]
+    node _T_665 = bits(fifo_reset, 2, 2) @[el2_dma_ctrl.scala 288:153]
+    node _T_666 = eq(_T_665, UInt<1>("h00")) @[el2_dma_ctrl.scala 288:142]
+    node _T_667 = and(_T_664, _T_666) @[el2_dma_ctrl.scala 288:140]
+    reg _T_668 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 288:89]
+    _T_668 <= _T_667 @[el2_dma_ctrl.scala 288:89]
+    node _T_669 = bits(fifo_error_bus_en, 3, 3) @[el2_dma_ctrl.scala 288:111]
+    node _T_670 = bits(fifo_error_bus, 3, 3) @[el2_dma_ctrl.scala 288:135]
+    node _T_671 = mux(_T_669, UInt<1>("h01"), _T_670) @[el2_dma_ctrl.scala 288:93]
+    node _T_672 = bits(fifo_reset, 3, 3) @[el2_dma_ctrl.scala 288:153]
+    node _T_673 = eq(_T_672, UInt<1>("h00")) @[el2_dma_ctrl.scala 288:142]
+    node _T_674 = and(_T_671, _T_673) @[el2_dma_ctrl.scala 288:140]
+    reg _T_675 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 288:89]
+    _T_675 <= _T_674 @[el2_dma_ctrl.scala 288:89]
+    node _T_676 = bits(fifo_error_bus_en, 4, 4) @[el2_dma_ctrl.scala 288:111]
+    node _T_677 = bits(fifo_error_bus, 4, 4) @[el2_dma_ctrl.scala 288:135]
+    node _T_678 = mux(_T_676, UInt<1>("h01"), _T_677) @[el2_dma_ctrl.scala 288:93]
+    node _T_679 = bits(fifo_reset, 4, 4) @[el2_dma_ctrl.scala 288:153]
+    node _T_680 = eq(_T_679, UInt<1>("h00")) @[el2_dma_ctrl.scala 288:142]
+    node _T_681 = and(_T_678, _T_680) @[el2_dma_ctrl.scala 288:140]
+    reg _T_682 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 288:89]
+    _T_682 <= _T_681 @[el2_dma_ctrl.scala 288:89]
+    node _T_683 = cat(_T_682, _T_675) @[Cat.scala 29:58]
+    node _T_684 = cat(_T_683, _T_668) @[Cat.scala 29:58]
+    node _T_685 = cat(_T_684, _T_661) @[Cat.scala 29:58]
+    node _T_686 = cat(_T_685, _T_654) @[Cat.scala 29:58]
+    fifo_error_bus <= _T_686 @[el2_dma_ctrl.scala 288:21]
+    node _T_687 = bits(fifo_pend_en, 0, 0) @[el2_dma_ctrl.scala 290:106]
+    node _T_688 = bits(fifo_rpend, 0, 0) @[el2_dma_ctrl.scala 290:126]
+    node _T_689 = mux(_T_687, UInt<1>("h01"), _T_688) @[el2_dma_ctrl.scala 290:93]
+    node _T_690 = bits(fifo_reset, 0, 0) @[el2_dma_ctrl.scala 290:144]
+    node _T_691 = eq(_T_690, UInt<1>("h00")) @[el2_dma_ctrl.scala 290:133]
+    node _T_692 = and(_T_689, _T_691) @[el2_dma_ctrl.scala 290:131]
+    reg _T_693 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 290:89]
+    _T_693 <= _T_692 @[el2_dma_ctrl.scala 290:89]
+    node _T_694 = bits(fifo_pend_en, 1, 1) @[el2_dma_ctrl.scala 290:106]
+    node _T_695 = bits(fifo_rpend, 1, 1) @[el2_dma_ctrl.scala 290:126]
+    node _T_696 = mux(_T_694, UInt<1>("h01"), _T_695) @[el2_dma_ctrl.scala 290:93]
+    node _T_697 = bits(fifo_reset, 1, 1) @[el2_dma_ctrl.scala 290:144]
+    node _T_698 = eq(_T_697, UInt<1>("h00")) @[el2_dma_ctrl.scala 290:133]
+    node _T_699 = and(_T_696, _T_698) @[el2_dma_ctrl.scala 290:131]
+    reg _T_700 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 290:89]
+    _T_700 <= _T_699 @[el2_dma_ctrl.scala 290:89]
+    node _T_701 = bits(fifo_pend_en, 2, 2) @[el2_dma_ctrl.scala 290:106]
+    node _T_702 = bits(fifo_rpend, 2, 2) @[el2_dma_ctrl.scala 290:126]
+    node _T_703 = mux(_T_701, UInt<1>("h01"), _T_702) @[el2_dma_ctrl.scala 290:93]
+    node _T_704 = bits(fifo_reset, 2, 2) @[el2_dma_ctrl.scala 290:144]
+    node _T_705 = eq(_T_704, UInt<1>("h00")) @[el2_dma_ctrl.scala 290:133]
+    node _T_706 = and(_T_703, _T_705) @[el2_dma_ctrl.scala 290:131]
+    reg _T_707 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 290:89]
+    _T_707 <= _T_706 @[el2_dma_ctrl.scala 290:89]
+    node _T_708 = bits(fifo_pend_en, 3, 3) @[el2_dma_ctrl.scala 290:106]
+    node _T_709 = bits(fifo_rpend, 3, 3) @[el2_dma_ctrl.scala 290:126]
+    node _T_710 = mux(_T_708, UInt<1>("h01"), _T_709) @[el2_dma_ctrl.scala 290:93]
+    node _T_711 = bits(fifo_reset, 3, 3) @[el2_dma_ctrl.scala 290:144]
+    node _T_712 = eq(_T_711, UInt<1>("h00")) @[el2_dma_ctrl.scala 290:133]
+    node _T_713 = and(_T_710, _T_712) @[el2_dma_ctrl.scala 290:131]
+    reg _T_714 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 290:89]
+    _T_714 <= _T_713 @[el2_dma_ctrl.scala 290:89]
+    node _T_715 = bits(fifo_pend_en, 4, 4) @[el2_dma_ctrl.scala 290:106]
+    node _T_716 = bits(fifo_rpend, 4, 4) @[el2_dma_ctrl.scala 290:126]
+    node _T_717 = mux(_T_715, UInt<1>("h01"), _T_716) @[el2_dma_ctrl.scala 290:93]
+    node _T_718 = bits(fifo_reset, 4, 4) @[el2_dma_ctrl.scala 290:144]
+    node _T_719 = eq(_T_718, UInt<1>("h00")) @[el2_dma_ctrl.scala 290:133]
+    node _T_720 = and(_T_717, _T_719) @[el2_dma_ctrl.scala 290:131]
+    reg _T_721 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 290:89]
+    _T_721 <= _T_720 @[el2_dma_ctrl.scala 290:89]
+    node _T_722 = cat(_T_721, _T_714) @[Cat.scala 29:58]
+    node _T_723 = cat(_T_722, _T_707) @[Cat.scala 29:58]
+    node _T_724 = cat(_T_723, _T_700) @[Cat.scala 29:58]
+    node _T_725 = cat(_T_724, _T_693) @[Cat.scala 29:58]
+    fifo_rpend <= _T_725 @[el2_dma_ctrl.scala 290:21]
+    node _T_726 = bits(fifo_done_en, 0, 0) @[el2_dma_ctrl.scala 292:106]
+    node _T_727 = bits(fifo_done, 0, 0) @[el2_dma_ctrl.scala 292:125]
+    node _T_728 = mux(_T_726, UInt<1>("h01"), _T_727) @[el2_dma_ctrl.scala 292:93]
+    node _T_729 = bits(fifo_reset, 0, 0) @[el2_dma_ctrl.scala 292:143]
+    node _T_730 = eq(_T_729, UInt<1>("h00")) @[el2_dma_ctrl.scala 292:132]
+    node _T_731 = and(_T_728, _T_730) @[el2_dma_ctrl.scala 292:130]
+    reg _T_732 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 292:89]
+    _T_732 <= _T_731 @[el2_dma_ctrl.scala 292:89]
+    node _T_733 = bits(fifo_done_en, 1, 1) @[el2_dma_ctrl.scala 292:106]
+    node _T_734 = bits(fifo_done, 1, 1) @[el2_dma_ctrl.scala 292:125]
+    node _T_735 = mux(_T_733, UInt<1>("h01"), _T_734) @[el2_dma_ctrl.scala 292:93]
+    node _T_736 = bits(fifo_reset, 1, 1) @[el2_dma_ctrl.scala 292:143]
+    node _T_737 = eq(_T_736, UInt<1>("h00")) @[el2_dma_ctrl.scala 292:132]
+    node _T_738 = and(_T_735, _T_737) @[el2_dma_ctrl.scala 292:130]
+    reg _T_739 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 292:89]
+    _T_739 <= _T_738 @[el2_dma_ctrl.scala 292:89]
+    node _T_740 = bits(fifo_done_en, 2, 2) @[el2_dma_ctrl.scala 292:106]
+    node _T_741 = bits(fifo_done, 2, 2) @[el2_dma_ctrl.scala 292:125]
+    node _T_742 = mux(_T_740, UInt<1>("h01"), _T_741) @[el2_dma_ctrl.scala 292:93]
+    node _T_743 = bits(fifo_reset, 2, 2) @[el2_dma_ctrl.scala 292:143]
+    node _T_744 = eq(_T_743, UInt<1>("h00")) @[el2_dma_ctrl.scala 292:132]
+    node _T_745 = and(_T_742, _T_744) @[el2_dma_ctrl.scala 292:130]
+    reg _T_746 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 292:89]
+    _T_746 <= _T_745 @[el2_dma_ctrl.scala 292:89]
+    node _T_747 = bits(fifo_done_en, 3, 3) @[el2_dma_ctrl.scala 292:106]
+    node _T_748 = bits(fifo_done, 3, 3) @[el2_dma_ctrl.scala 292:125]
+    node _T_749 = mux(_T_747, UInt<1>("h01"), _T_748) @[el2_dma_ctrl.scala 292:93]
+    node _T_750 = bits(fifo_reset, 3, 3) @[el2_dma_ctrl.scala 292:143]
+    node _T_751 = eq(_T_750, UInt<1>("h00")) @[el2_dma_ctrl.scala 292:132]
+    node _T_752 = and(_T_749, _T_751) @[el2_dma_ctrl.scala 292:130]
+    reg _T_753 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 292:89]
+    _T_753 <= _T_752 @[el2_dma_ctrl.scala 292:89]
+    node _T_754 = bits(fifo_done_en, 4, 4) @[el2_dma_ctrl.scala 292:106]
+    node _T_755 = bits(fifo_done, 4, 4) @[el2_dma_ctrl.scala 292:125]
+    node _T_756 = mux(_T_754, UInt<1>("h01"), _T_755) @[el2_dma_ctrl.scala 292:93]
+    node _T_757 = bits(fifo_reset, 4, 4) @[el2_dma_ctrl.scala 292:143]
+    node _T_758 = eq(_T_757, UInt<1>("h00")) @[el2_dma_ctrl.scala 292:132]
+    node _T_759 = and(_T_756, _T_758) @[el2_dma_ctrl.scala 292:130]
+    reg _T_760 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 292:89]
+    _T_760 <= _T_759 @[el2_dma_ctrl.scala 292:89]
+    node _T_761 = cat(_T_760, _T_753) @[Cat.scala 29:58]
+    node _T_762 = cat(_T_761, _T_746) @[Cat.scala 29:58]
+    node _T_763 = cat(_T_762, _T_739) @[Cat.scala 29:58]
+    node _T_764 = cat(_T_763, _T_732) @[Cat.scala 29:58]
+    fifo_done <= _T_764 @[el2_dma_ctrl.scala 292:21]
+    node _T_765 = bits(fifo_done_bus_en, 0, 0) @[el2_dma_ctrl.scala 294:110]
+    node _T_766 = bits(fifo_done_bus, 0, 0) @[el2_dma_ctrl.scala 294:133]
+    node _T_767 = mux(_T_765, UInt<1>("h01"), _T_766) @[el2_dma_ctrl.scala 294:93]
+    node _T_768 = bits(fifo_reset, 0, 0) @[el2_dma_ctrl.scala 294:151]
+    node _T_769 = eq(_T_768, UInt<1>("h00")) @[el2_dma_ctrl.scala 294:140]
+    node _T_770 = and(_T_767, _T_769) @[el2_dma_ctrl.scala 294:138]
+    reg _T_771 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 294:89]
+    _T_771 <= _T_770 @[el2_dma_ctrl.scala 294:89]
+    node _T_772 = bits(fifo_done_bus_en, 1, 1) @[el2_dma_ctrl.scala 294:110]
+    node _T_773 = bits(fifo_done_bus, 1, 1) @[el2_dma_ctrl.scala 294:133]
+    node _T_774 = mux(_T_772, UInt<1>("h01"), _T_773) @[el2_dma_ctrl.scala 294:93]
+    node _T_775 = bits(fifo_reset, 1, 1) @[el2_dma_ctrl.scala 294:151]
+    node _T_776 = eq(_T_775, UInt<1>("h00")) @[el2_dma_ctrl.scala 294:140]
+    node _T_777 = and(_T_774, _T_776) @[el2_dma_ctrl.scala 294:138]
+    reg _T_778 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 294:89]
+    _T_778 <= _T_777 @[el2_dma_ctrl.scala 294:89]
+    node _T_779 = bits(fifo_done_bus_en, 2, 2) @[el2_dma_ctrl.scala 294:110]
+    node _T_780 = bits(fifo_done_bus, 2, 2) @[el2_dma_ctrl.scala 294:133]
+    node _T_781 = mux(_T_779, UInt<1>("h01"), _T_780) @[el2_dma_ctrl.scala 294:93]
+    node _T_782 = bits(fifo_reset, 2, 2) @[el2_dma_ctrl.scala 294:151]
+    node _T_783 = eq(_T_782, UInt<1>("h00")) @[el2_dma_ctrl.scala 294:140]
+    node _T_784 = and(_T_781, _T_783) @[el2_dma_ctrl.scala 294:138]
+    reg _T_785 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 294:89]
+    _T_785 <= _T_784 @[el2_dma_ctrl.scala 294:89]
+    node _T_786 = bits(fifo_done_bus_en, 3, 3) @[el2_dma_ctrl.scala 294:110]
+    node _T_787 = bits(fifo_done_bus, 3, 3) @[el2_dma_ctrl.scala 294:133]
+    node _T_788 = mux(_T_786, UInt<1>("h01"), _T_787) @[el2_dma_ctrl.scala 294:93]
+    node _T_789 = bits(fifo_reset, 3, 3) @[el2_dma_ctrl.scala 294:151]
+    node _T_790 = eq(_T_789, UInt<1>("h00")) @[el2_dma_ctrl.scala 294:140]
+    node _T_791 = and(_T_788, _T_790) @[el2_dma_ctrl.scala 294:138]
+    reg _T_792 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 294:89]
+    _T_792 <= _T_791 @[el2_dma_ctrl.scala 294:89]
+    node _T_793 = bits(fifo_done_bus_en, 4, 4) @[el2_dma_ctrl.scala 294:110]
+    node _T_794 = bits(fifo_done_bus, 4, 4) @[el2_dma_ctrl.scala 294:133]
+    node _T_795 = mux(_T_793, UInt<1>("h01"), _T_794) @[el2_dma_ctrl.scala 294:93]
+    node _T_796 = bits(fifo_reset, 4, 4) @[el2_dma_ctrl.scala 294:151]
+    node _T_797 = eq(_T_796, UInt<1>("h00")) @[el2_dma_ctrl.scala 294:140]
+    node _T_798 = and(_T_795, _T_797) @[el2_dma_ctrl.scala 294:138]
+    reg _T_799 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 294:89]
+    _T_799 <= _T_798 @[el2_dma_ctrl.scala 294:89]
+    node _T_800 = cat(_T_799, _T_792) @[Cat.scala 29:58]
+    node _T_801 = cat(_T_800, _T_785) @[Cat.scala 29:58]
+    node _T_802 = cat(_T_801, _T_778) @[Cat.scala 29:58]
+    node _T_803 = cat(_T_802, _T_771) @[Cat.scala 29:58]
+    fifo_done_bus <= _T_803 @[el2_dma_ctrl.scala 294:21]
+    node _T_804 = bits(fifo_cmd_en, 0, 0) @[el2_dma_ctrl.scala 296:84]
+    inst rvclkhdr of rvclkhdr @[el2_lib.scala 508:23]
+    rvclkhdr.clock <= clock
+    rvclkhdr.reset <= reset
+    rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18]
+    rvclkhdr.io.en <= _T_804 @[el2_lib.scala 511:17]
+    rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
+    reg _T_805 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
+    _T_805 <= fifo_addr_in @[el2_lib.scala 514:16]
+    fifo_addr[0] <= _T_805 @[el2_dma_ctrl.scala 296:49]
+    node _T_806 = bits(fifo_cmd_en, 1, 1) @[el2_dma_ctrl.scala 296:84]
+    inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 508:23]
+    rvclkhdr_1.clock <= clock
+    rvclkhdr_1.reset <= reset
+    rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18]
+    rvclkhdr_1.io.en <= _T_806 @[el2_lib.scala 511:17]
+    rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
+    reg _T_807 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
+    _T_807 <= fifo_addr_in @[el2_lib.scala 514:16]
+    fifo_addr[1] <= _T_807 @[el2_dma_ctrl.scala 296:49]
+    node _T_808 = bits(fifo_cmd_en, 2, 2) @[el2_dma_ctrl.scala 296:84]
+    inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 508:23]
+    rvclkhdr_2.clock <= clock
+    rvclkhdr_2.reset <= reset
+    rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18]
+    rvclkhdr_2.io.en <= _T_808 @[el2_lib.scala 511:17]
+    rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
+    reg _T_809 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
+    _T_809 <= fifo_addr_in @[el2_lib.scala 514:16]
+    fifo_addr[2] <= _T_809 @[el2_dma_ctrl.scala 296:49]
+    node _T_810 = bits(fifo_cmd_en, 3, 3) @[el2_dma_ctrl.scala 296:84]
+    inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23]
+    rvclkhdr_3.clock <= clock
+    rvclkhdr_3.reset <= reset
+    rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18]
+    rvclkhdr_3.io.en <= _T_810 @[el2_lib.scala 511:17]
+    rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
+    reg _T_811 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
+    _T_811 <= fifo_addr_in @[el2_lib.scala 514:16]
+    fifo_addr[3] <= _T_811 @[el2_dma_ctrl.scala 296:49]
+    node _T_812 = bits(fifo_cmd_en, 4, 4) @[el2_dma_ctrl.scala 296:84]
+    inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 508:23]
+    rvclkhdr_4.clock <= clock
+    rvclkhdr_4.reset <= reset
+    rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18]
+    rvclkhdr_4.io.en <= _T_812 @[el2_lib.scala 511:17]
+    rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
+    reg _T_813 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
+    _T_813 <= fifo_addr_in @[el2_lib.scala 514:16]
+    fifo_addr[4] <= _T_813 @[el2_dma_ctrl.scala 296:49]
+    node _T_814 = bits(fifo_sz_in, 2, 0) @[el2_dma_ctrl.scala 298:100]
+    node _T_815 = bits(fifo_cmd_en, 0, 0) @[el2_dma_ctrl.scala 298:123]
+    reg _T_816 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_815 : @[Reg.scala 28:19]
+      _T_816 <= _T_814 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    fifo_sz[0] <= _T_816 @[el2_dma_ctrl.scala 298:47]
+    node _T_817 = bits(fifo_sz_in, 2, 0) @[el2_dma_ctrl.scala 298:100]
+    node _T_818 = bits(fifo_cmd_en, 1, 1) @[el2_dma_ctrl.scala 298:123]
+    reg _T_819 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_818 : @[Reg.scala 28:19]
+      _T_819 <= _T_817 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    fifo_sz[1] <= _T_819 @[el2_dma_ctrl.scala 298:47]
+    node _T_820 = bits(fifo_sz_in, 2, 0) @[el2_dma_ctrl.scala 298:100]
+    node _T_821 = bits(fifo_cmd_en, 2, 2) @[el2_dma_ctrl.scala 298:123]
+    reg _T_822 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_821 : @[Reg.scala 28:19]
+      _T_822 <= _T_820 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    fifo_sz[2] <= _T_822 @[el2_dma_ctrl.scala 298:47]
+    node _T_823 = bits(fifo_sz_in, 2, 0) @[el2_dma_ctrl.scala 298:100]
+    node _T_824 = bits(fifo_cmd_en, 3, 3) @[el2_dma_ctrl.scala 298:123]
+    reg _T_825 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_824 : @[Reg.scala 28:19]
+      _T_825 <= _T_823 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    fifo_sz[3] <= _T_825 @[el2_dma_ctrl.scala 298:47]
+    node _T_826 = bits(fifo_sz_in, 2, 0) @[el2_dma_ctrl.scala 298:100]
+    node _T_827 = bits(fifo_cmd_en, 4, 4) @[el2_dma_ctrl.scala 298:123]
+    reg _T_828 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_827 : @[Reg.scala 28:19]
+      _T_828 <= _T_826 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    fifo_sz[4] <= _T_828 @[el2_dma_ctrl.scala 298:47]
+    node _T_829 = bits(fifo_byteen_in, 7, 0) @[el2_dma_ctrl.scala 300:108]
+    node _T_830 = bits(fifo_cmd_en, 0, 0) @[el2_dma_ctrl.scala 300:131]
+    node _T_831 = bits(_T_830, 0, 0) @[el2_dma_ctrl.scala 300:141]
+    reg _T_832 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_831 : @[Reg.scala 28:19]
+      _T_832 <= _T_829 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    fifo_byteen[0] <= _T_832 @[el2_dma_ctrl.scala 300:51]
+    node _T_833 = bits(fifo_byteen_in, 7, 0) @[el2_dma_ctrl.scala 300:108]
+    node _T_834 = bits(fifo_cmd_en, 1, 1) @[el2_dma_ctrl.scala 300:131]
+    node _T_835 = bits(_T_834, 0, 0) @[el2_dma_ctrl.scala 300:141]
+    reg _T_836 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_835 : @[Reg.scala 28:19]
+      _T_836 <= _T_833 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    fifo_byteen[1] <= _T_836 @[el2_dma_ctrl.scala 300:51]
+    node _T_837 = bits(fifo_byteen_in, 7, 0) @[el2_dma_ctrl.scala 300:108]
+    node _T_838 = bits(fifo_cmd_en, 2, 2) @[el2_dma_ctrl.scala 300:131]
+    node _T_839 = bits(_T_838, 0, 0) @[el2_dma_ctrl.scala 300:141]
+    reg _T_840 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_839 : @[Reg.scala 28:19]
+      _T_840 <= _T_837 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    fifo_byteen[2] <= _T_840 @[el2_dma_ctrl.scala 300:51]
+    node _T_841 = bits(fifo_byteen_in, 7, 0) @[el2_dma_ctrl.scala 300:108]
+    node _T_842 = bits(fifo_cmd_en, 3, 3) @[el2_dma_ctrl.scala 300:131]
+    node _T_843 = bits(_T_842, 0, 0) @[el2_dma_ctrl.scala 300:141]
+    reg _T_844 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_843 : @[Reg.scala 28:19]
+      _T_844 <= _T_841 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    fifo_byteen[3] <= _T_844 @[el2_dma_ctrl.scala 300:51]
+    node _T_845 = bits(fifo_byteen_in, 7, 0) @[el2_dma_ctrl.scala 300:108]
+    node _T_846 = bits(fifo_cmd_en, 4, 4) @[el2_dma_ctrl.scala 300:131]
+    node _T_847 = bits(_T_846, 0, 0) @[el2_dma_ctrl.scala 300:141]
+    reg _T_848 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_847 : @[Reg.scala 28:19]
+      _T_848 <= _T_845 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    fifo_byteen[4] <= _T_848 @[el2_dma_ctrl.scala 300:51]
+    node _T_849 = bits(fifo_cmd_en, 0, 0) @[el2_dma_ctrl.scala 302:129]
+    reg _T_850 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_849 : @[Reg.scala 28:19]
+      _T_850 <= fifo_write_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_851 = bits(fifo_cmd_en, 1, 1) @[el2_dma_ctrl.scala 302:129]
+    reg _T_852 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_851 : @[Reg.scala 28:19]
+      _T_852 <= fifo_write_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_853 = bits(fifo_cmd_en, 2, 2) @[el2_dma_ctrl.scala 302:129]
+    reg _T_854 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_853 : @[Reg.scala 28:19]
+      _T_854 <= fifo_write_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_855 = bits(fifo_cmd_en, 3, 3) @[el2_dma_ctrl.scala 302:129]
+    reg _T_856 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_855 : @[Reg.scala 28:19]
+      _T_856 <= fifo_write_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_857 = bits(fifo_cmd_en, 4, 4) @[el2_dma_ctrl.scala 302:129]
+    reg _T_858 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_857 : @[Reg.scala 28:19]
+      _T_858 <= fifo_write_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_859 = cat(_T_858, _T_856) @[Cat.scala 29:58]
+    node _T_860 = cat(_T_859, _T_854) @[Cat.scala 29:58]
+    node _T_861 = cat(_T_860, _T_852) @[Cat.scala 29:58]
+    node _T_862 = cat(_T_861, _T_850) @[Cat.scala 29:58]
+    fifo_write <= _T_862 @[el2_dma_ctrl.scala 302:21]
+    node _T_863 = bits(fifo_cmd_en, 0, 0) @[el2_dma_ctrl.scala 304:136]
+    reg _T_864 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_863 : @[Reg.scala 28:19]
+      _T_864 <= fifo_posted_write_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_865 = bits(fifo_cmd_en, 1, 1) @[el2_dma_ctrl.scala 304:136]
+    reg _T_866 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_865 : @[Reg.scala 28:19]
+      _T_866 <= fifo_posted_write_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_867 = bits(fifo_cmd_en, 2, 2) @[el2_dma_ctrl.scala 304:136]
+    reg _T_868 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_867 : @[Reg.scala 28:19]
+      _T_868 <= fifo_posted_write_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_869 = bits(fifo_cmd_en, 3, 3) @[el2_dma_ctrl.scala 304:136]
+    reg _T_870 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_869 : @[Reg.scala 28:19]
+      _T_870 <= fifo_posted_write_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_871 = bits(fifo_cmd_en, 4, 4) @[el2_dma_ctrl.scala 304:136]
+    reg _T_872 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_871 : @[Reg.scala 28:19]
+      _T_872 <= fifo_posted_write_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_873 = cat(_T_872, _T_870) @[Cat.scala 29:58]
+    node _T_874 = cat(_T_873, _T_868) @[Cat.scala 29:58]
+    node _T_875 = cat(_T_874, _T_866) @[Cat.scala 29:58]
+    node _T_876 = cat(_T_875, _T_864) @[Cat.scala 29:58]
+    fifo_posted_write <= _T_876 @[el2_dma_ctrl.scala 304:21]
+    node _T_877 = bits(fifo_cmd_en, 0, 0) @[el2_dma_ctrl.scala 306:126]
+    reg _T_878 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_877 : @[Reg.scala 28:19]
+      _T_878 <= io.dbg_cmd_valid @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_879 = bits(fifo_cmd_en, 1, 1) @[el2_dma_ctrl.scala 306:126]
+    reg _T_880 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_879 : @[Reg.scala 28:19]
+      _T_880 <= io.dbg_cmd_valid @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_881 = bits(fifo_cmd_en, 2, 2) @[el2_dma_ctrl.scala 306:126]
+    reg _T_882 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_881 : @[Reg.scala 28:19]
+      _T_882 <= io.dbg_cmd_valid @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_883 = bits(fifo_cmd_en, 3, 3) @[el2_dma_ctrl.scala 306:126]
+    reg _T_884 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_883 : @[Reg.scala 28:19]
+      _T_884 <= io.dbg_cmd_valid @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_885 = bits(fifo_cmd_en, 4, 4) @[el2_dma_ctrl.scala 306:126]
+    reg _T_886 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_885 : @[Reg.scala 28:19]
+      _T_886 <= io.dbg_cmd_valid @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_887 = cat(_T_886, _T_884) @[Cat.scala 29:58]
+    node _T_888 = cat(_T_887, _T_882) @[Cat.scala 29:58]
+    node _T_889 = cat(_T_888, _T_880) @[Cat.scala 29:58]
+    node _T_890 = cat(_T_889, _T_878) @[Cat.scala 29:58]
+    fifo_dbg <= _T_890 @[el2_dma_ctrl.scala 306:21]
+    node _T_891 = bits(fifo_data_en, 0, 0) @[el2_dma_ctrl.scala 308:88]
+    inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 508:23]
+    rvclkhdr_5.clock <= clock
+    rvclkhdr_5.reset <= reset
+    rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18]
+    rvclkhdr_5.io.en <= _T_891 @[el2_lib.scala 511:17]
+    rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
+    reg _T_892 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
+    _T_892 <= fifo_data_in[0] @[el2_lib.scala 514:16]
+    fifo_data[0] <= _T_892 @[el2_dma_ctrl.scala 308:49]
+    node _T_893 = bits(fifo_data_en, 1, 1) @[el2_dma_ctrl.scala 308:88]
+    inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 508:23]
+    rvclkhdr_6.clock <= clock
+    rvclkhdr_6.reset <= reset
+    rvclkhdr_6.io.clk <= clock @[el2_lib.scala 510:18]
+    rvclkhdr_6.io.en <= _T_893 @[el2_lib.scala 511:17]
+    rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
+    reg _T_894 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
+    _T_894 <= fifo_data_in[1] @[el2_lib.scala 514:16]
+    fifo_data[1] <= _T_894 @[el2_dma_ctrl.scala 308:49]
+    node _T_895 = bits(fifo_data_en, 2, 2) @[el2_dma_ctrl.scala 308:88]
+    inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 508:23]
+    rvclkhdr_7.clock <= clock
+    rvclkhdr_7.reset <= reset
+    rvclkhdr_7.io.clk <= clock @[el2_lib.scala 510:18]
+    rvclkhdr_7.io.en <= _T_895 @[el2_lib.scala 511:17]
+    rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
+    reg _T_896 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
+    _T_896 <= fifo_data_in[2] @[el2_lib.scala 514:16]
+    fifo_data[2] <= _T_896 @[el2_dma_ctrl.scala 308:49]
+    node _T_897 = bits(fifo_data_en, 3, 3) @[el2_dma_ctrl.scala 308:88]
+    inst rvclkhdr_8 of rvclkhdr_8 @[el2_lib.scala 508:23]
+    rvclkhdr_8.clock <= clock
+    rvclkhdr_8.reset <= reset
+    rvclkhdr_8.io.clk <= clock @[el2_lib.scala 510:18]
+    rvclkhdr_8.io.en <= _T_897 @[el2_lib.scala 511:17]
+    rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
+    reg _T_898 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
+    _T_898 <= fifo_data_in[3] @[el2_lib.scala 514:16]
+    fifo_data[3] <= _T_898 @[el2_dma_ctrl.scala 308:49]
+    node _T_899 = bits(fifo_data_en, 4, 4) @[el2_dma_ctrl.scala 308:88]
+    inst rvclkhdr_9 of rvclkhdr_9 @[el2_lib.scala 508:23]
+    rvclkhdr_9.clock <= clock
+    rvclkhdr_9.reset <= reset
+    rvclkhdr_9.io.clk <= clock @[el2_lib.scala 510:18]
+    rvclkhdr_9.io.en <= _T_899 @[el2_lib.scala 511:17]
+    rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
+    reg _T_900 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
+    _T_900 <= fifo_data_in[4] @[el2_lib.scala 514:16]
+    fifo_data[4] <= _T_900 @[el2_dma_ctrl.scala 308:49]
+    node _T_901 = bits(fifo_cmd_en, 0, 0) @[el2_dma_ctrl.scala 310:120]
+    reg _T_902 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_901 : @[Reg.scala 28:19]
+      _T_902 <= bus_cmd_tag @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    fifo_tag[0] <= _T_902 @[el2_dma_ctrl.scala 310:48]
+    node _T_903 = bits(fifo_cmd_en, 1, 1) @[el2_dma_ctrl.scala 310:120]
+    reg _T_904 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_903 : @[Reg.scala 28:19]
+      _T_904 <= bus_cmd_tag @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    fifo_tag[1] <= _T_904 @[el2_dma_ctrl.scala 310:48]
+    node _T_905 = bits(fifo_cmd_en, 2, 2) @[el2_dma_ctrl.scala 310:120]
+    reg _T_906 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_905 : @[Reg.scala 28:19]
+      _T_906 <= bus_cmd_tag @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    fifo_tag[2] <= _T_906 @[el2_dma_ctrl.scala 310:48]
+    node _T_907 = bits(fifo_cmd_en, 3, 3) @[el2_dma_ctrl.scala 310:120]
+    reg _T_908 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_907 : @[Reg.scala 28:19]
+      _T_908 <= bus_cmd_tag @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    fifo_tag[3] <= _T_908 @[el2_dma_ctrl.scala 310:48]
+    node _T_909 = bits(fifo_cmd_en, 4, 4) @[el2_dma_ctrl.scala 310:120]
+    reg _T_910 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_909 : @[Reg.scala 28:19]
+      _T_910 <= bus_cmd_tag @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    fifo_tag[4] <= _T_910 @[el2_dma_ctrl.scala 310:48]
+    node _T_911 = bits(fifo_cmd_en, 0, 0) @[el2_dma_ctrl.scala 312:120]
+    reg _T_912 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_911 : @[Reg.scala 28:19]
+      _T_912 <= bus_cmd_mid @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    fifo_mid[0] <= _T_912 @[el2_dma_ctrl.scala 312:48]
+    node _T_913 = bits(fifo_cmd_en, 1, 1) @[el2_dma_ctrl.scala 312:120]
+    reg _T_914 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_913 : @[Reg.scala 28:19]
+      _T_914 <= bus_cmd_mid @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    fifo_mid[1] <= _T_914 @[el2_dma_ctrl.scala 312:48]
+    node _T_915 = bits(fifo_cmd_en, 2, 2) @[el2_dma_ctrl.scala 312:120]
+    reg _T_916 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_915 : @[Reg.scala 28:19]
+      _T_916 <= bus_cmd_mid @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    fifo_mid[2] <= _T_916 @[el2_dma_ctrl.scala 312:48]
+    node _T_917 = bits(fifo_cmd_en, 3, 3) @[el2_dma_ctrl.scala 312:120]
+    reg _T_918 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_917 : @[Reg.scala 28:19]
+      _T_918 <= bus_cmd_mid @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    fifo_mid[3] <= _T_918 @[el2_dma_ctrl.scala 312:48]
+    node _T_919 = bits(fifo_cmd_en, 4, 4) @[el2_dma_ctrl.scala 312:120]
+    reg _T_920 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_919 : @[Reg.scala 28:19]
+      _T_920 <= bus_cmd_mid @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    fifo_mid[4] <= _T_920 @[el2_dma_ctrl.scala 312:48]
+    node _T_921 = bits(fifo_cmd_en, 0, 0) @[el2_dma_ctrl.scala 314:122]
+    reg _T_922 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_921 : @[Reg.scala 28:19]
+      _T_922 <= bus_cmd_prty @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    fifo_prty[0] <= _T_922 @[el2_dma_ctrl.scala 314:49]
+    node _T_923 = bits(fifo_cmd_en, 1, 1) @[el2_dma_ctrl.scala 314:122]
+    reg _T_924 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_923 : @[Reg.scala 28:19]
+      _T_924 <= bus_cmd_prty @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    fifo_prty[1] <= _T_924 @[el2_dma_ctrl.scala 314:49]
+    node _T_925 = bits(fifo_cmd_en, 2, 2) @[el2_dma_ctrl.scala 314:122]
+    reg _T_926 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_925 : @[Reg.scala 28:19]
+      _T_926 <= bus_cmd_prty @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    fifo_prty[2] <= _T_926 @[el2_dma_ctrl.scala 314:49]
+    node _T_927 = bits(fifo_cmd_en, 3, 3) @[el2_dma_ctrl.scala 314:122]
+    reg _T_928 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_927 : @[Reg.scala 28:19]
+      _T_928 <= bus_cmd_prty @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    fifo_prty[3] <= _T_928 @[el2_dma_ctrl.scala 314:49]
+    node _T_929 = bits(fifo_cmd_en, 4, 4) @[el2_dma_ctrl.scala 314:122]
+    reg _T_930 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_929 : @[Reg.scala 28:19]
+      _T_930 <= bus_cmd_prty @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    fifo_prty[4] <= _T_930 @[el2_dma_ctrl.scala 314:49]
+    node _T_931 = eq(WrPtr, UInt<3>("h04")) @[el2_dma_ctrl.scala 318:30]
+    node _T_932 = bits(_T_931, 0, 0) @[el2_dma_ctrl.scala 318:57]
+    node _T_933 = add(WrPtr, UInt<1>("h01")) @[el2_dma_ctrl.scala 318:76]
+    node _T_934 = tail(_T_933, 1) @[el2_dma_ctrl.scala 318:76]
+    node _T_935 = mux(_T_932, UInt<1>("h00"), _T_934) @[el2_dma_ctrl.scala 318:22]
+    NxtWrPtr <= _T_935 @[el2_dma_ctrl.scala 318:16]
+    node _T_936 = eq(RdPtr, UInt<3>("h04")) @[el2_dma_ctrl.scala 320:30]
+    node _T_937 = bits(_T_936, 0, 0) @[el2_dma_ctrl.scala 320:57]
+    node _T_938 = add(RdPtr, UInt<1>("h01")) @[el2_dma_ctrl.scala 320:76]
+    node _T_939 = tail(_T_938, 1) @[el2_dma_ctrl.scala 320:76]
+    node _T_940 = mux(_T_937, UInt<1>("h00"), _T_939) @[el2_dma_ctrl.scala 320:22]
+    NxtRdPtr <= _T_940 @[el2_dma_ctrl.scala 320:16]
+    node _T_941 = eq(RspPtr, UInt<3>("h04")) @[el2_dma_ctrl.scala 322:31]
+    node _T_942 = bits(_T_941, 0, 0) @[el2_dma_ctrl.scala 322:58]
+    node _T_943 = add(RspPtr, UInt<1>("h01")) @[el2_dma_ctrl.scala 322:78]
+    node _T_944 = tail(_T_943, 1) @[el2_dma_ctrl.scala 322:78]
+    node _T_945 = mux(_T_942, UInt<1>("h00"), _T_944) @[el2_dma_ctrl.scala 322:22]
+    NxtRspPtr <= _T_945 @[el2_dma_ctrl.scala 322:16]
+    node WrPtrEn = orr(fifo_cmd_en) @[el2_dma_ctrl.scala 324:30]
+    node _T_946 = or(io.dma_dccm_req, io.dma_iccm_req) @[el2_dma_ctrl.scala 326:35]
+    node _T_947 = bits(dma_address_error, 0, 0) @[el2_dma_ctrl.scala 326:74]
+    node _T_948 = bits(dma_alignment_error, 0, 0) @[el2_dma_ctrl.scala 326:103]
+    node _T_949 = or(_T_947, _T_948) @[el2_dma_ctrl.scala 326:81]
+    node _T_950 = or(_T_949, dma_dbg_cmd_error) @[el2_dma_ctrl.scala 326:110]
+    node RdPtrEn = or(_T_946, _T_950) @[el2_dma_ctrl.scala 326:53]
+    node _T_951 = or(bus_rsp_sent, bus_posted_write_done) @[el2_dma_ctrl.scala 328:55]
+    node _T_952 = and(_T_951, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 328:80]
+    node RspPtrEn = or(io.dma_dbg_cmd_done, _T_952) @[el2_dma_ctrl.scala 328:39]
+    reg _T_953 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when WrPtrEn : @[Reg.scala 28:19]
+      _T_953 <= NxtWrPtr @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    WrPtr <= _T_953 @[el2_dma_ctrl.scala 330:16]
+    node _T_954 = bits(RdPtrEn, 0, 0) @[el2_dma_ctrl.scala 335:38]
+    reg _T_955 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_954 : @[Reg.scala 28:19]
+      _T_955 <= NxtRdPtr @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    RdPtr <= _T_955 @[el2_dma_ctrl.scala 334:16]
+    node _T_956 = bits(RspPtrEn, 0, 0) @[el2_dma_ctrl.scala 339:40]
+    reg _T_957 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_956 : @[Reg.scala 28:19]
+      _T_957 <= NxtRspPtr @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    RspPtr <= _T_957 @[el2_dma_ctrl.scala 338:16]
+    wire num_fifo_vld_tmp : UInt<4>
+    num_fifo_vld_tmp <= UInt<1>("h00")
+    wire num_fifo_vld_tmp2 : UInt<4>
+    num_fifo_vld_tmp2 <= UInt<1>("h00")
+    node _T_958 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+    node _T_959 = cat(_T_958, axi_mstr_prty_en) @[Cat.scala 29:58]
+    node _T_960 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+    node _T_961 = cat(_T_960, bus_rsp_sent) @[Cat.scala 29:58]
+    node _T_962 = sub(_T_959, _T_961) @[el2_dma_ctrl.scala 349:62]
+    node _T_963 = tail(_T_962, 1) @[el2_dma_ctrl.scala 349:62]
+    num_fifo_vld_tmp <= _T_963 @[el2_dma_ctrl.scala 349:25]
+    node _T_964 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+    node _T_965 = bits(fifo_valid, 0, 0) @[el2_dma_ctrl.scala 351:88]
+    node _T_966 = cat(_T_964, _T_965) @[Cat.scala 29:58]
+    node _T_967 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+    node _T_968 = bits(fifo_valid, 1, 1) @[el2_dma_ctrl.scala 351:88]
+    node _T_969 = cat(_T_967, _T_968) @[Cat.scala 29:58]
+    node _T_970 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+    node _T_971 = bits(fifo_valid, 2, 2) @[el2_dma_ctrl.scala 351:88]
+    node _T_972 = cat(_T_970, _T_971) @[Cat.scala 29:58]
+    node _T_973 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+    node _T_974 = bits(fifo_valid, 3, 3) @[el2_dma_ctrl.scala 351:88]
+    node _T_975 = cat(_T_973, _T_974) @[Cat.scala 29:58]
+    node _T_976 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+    node _T_977 = bits(fifo_valid, 4, 4) @[el2_dma_ctrl.scala 351:88]
+    node _T_978 = cat(_T_976, _T_977) @[Cat.scala 29:58]
+    node _T_979 = add(_T_966, _T_969) @[el2_dma_ctrl.scala 351:102]
+    node _T_980 = tail(_T_979, 1) @[el2_dma_ctrl.scala 351:102]
+    node _T_981 = add(_T_980, _T_972) @[el2_dma_ctrl.scala 351:102]
+    node _T_982 = tail(_T_981, 1) @[el2_dma_ctrl.scala 351:102]
+    node _T_983 = add(_T_982, _T_975) @[el2_dma_ctrl.scala 351:102]
+    node _T_984 = tail(_T_983, 1) @[el2_dma_ctrl.scala 351:102]
+    node _T_985 = add(_T_984, _T_978) @[el2_dma_ctrl.scala 351:102]
+    node _T_986 = tail(_T_985, 1) @[el2_dma_ctrl.scala 351:102]
+    num_fifo_vld_tmp2 <= _T_986 @[el2_dma_ctrl.scala 351:25]
+    node _T_987 = add(num_fifo_vld_tmp, num_fifo_vld_tmp2) @[el2_dma_ctrl.scala 353:45]
+    node _T_988 = tail(_T_987, 1) @[el2_dma_ctrl.scala 353:45]
+    num_fifo_vld <= _T_988 @[el2_dma_ctrl.scala 353:25]
+    node fifo_full_spec = geq(num_fifo_vld_tmp2, UInt<3>("h05")) @[el2_dma_ctrl.scala 355:46]
+    node _T_989 = or(fifo_full, dbg_dma_bubble_bus) @[el2_dma_ctrl.scala 357:39]
+    node dma_fifo_ready = not(_T_989) @[el2_dma_ctrl.scala 357:27]
+    node _T_990 = dshr(fifo_valid, RdPtr) @[el2_dma_ctrl.scala 361:38]
+    node _T_991 = bits(_T_990, 0, 0) @[el2_dma_ctrl.scala 361:38]
+    node _T_992 = dshr(fifo_done, RdPtr) @[el2_dma_ctrl.scala 361:58]
+    node _T_993 = bits(_T_992, 0, 0) @[el2_dma_ctrl.scala 361:58]
+    node _T_994 = eq(_T_993, UInt<1>("h00")) @[el2_dma_ctrl.scala 361:48]
+    node _T_995 = and(_T_991, _T_994) @[el2_dma_ctrl.scala 361:46]
+    node _T_996 = dshr(fifo_dbg, RdPtr) @[el2_dma_ctrl.scala 361:77]
+    node _T_997 = bits(_T_996, 0, 0) @[el2_dma_ctrl.scala 361:77]
+    node _T_998 = eq(_T_997, UInt<1>("h00")) @[el2_dma_ctrl.scala 361:68]
+    node _T_999 = and(_T_995, _T_998) @[el2_dma_ctrl.scala 361:66]
+    node _T_1000 = or(dma_mem_addr_in_dccm, dma_mem_addr_in_iccm) @[el2_dma_ctrl.scala 361:111]
+    node _T_1001 = not(_T_1000) @[el2_dma_ctrl.scala 361:88]
+    node _T_1002 = and(_T_999, _T_1001) @[el2_dma_ctrl.scala 361:85]
+    dma_address_error <= _T_1002 @[el2_dma_ctrl.scala 361:25]
+    node _T_1003 = dshr(fifo_valid, RdPtr) @[el2_dma_ctrl.scala 362:38]
+    node _T_1004 = bits(_T_1003, 0, 0) @[el2_dma_ctrl.scala 362:38]
+    node _T_1005 = dshr(fifo_done, RdPtr) @[el2_dma_ctrl.scala 362:58]
+    node _T_1006 = bits(_T_1005, 0, 0) @[el2_dma_ctrl.scala 362:58]
+    node _T_1007 = eq(_T_1006, UInt<1>("h00")) @[el2_dma_ctrl.scala 362:48]
+    node _T_1008 = and(_T_1004, _T_1007) @[el2_dma_ctrl.scala 362:46]
+    node _T_1009 = eq(dma_address_error, UInt<1>("h00")) @[el2_dma_ctrl.scala 362:68]
+    node _T_1010 = and(_T_1008, _T_1009) @[el2_dma_ctrl.scala 362:66]
+    node _T_1011 = bits(dma_mem_sz_int, 2, 0) @[el2_dma_ctrl.scala 363:22]
+    node _T_1012 = eq(_T_1011, UInt<1>("h01")) @[el2_dma_ctrl.scala 363:28]
+    node _T_1013 = bits(dma_mem_addr_int, 0, 0) @[el2_dma_ctrl.scala 363:55]
+    node _T_1014 = and(_T_1012, _T_1013) @[el2_dma_ctrl.scala 363:37]
+    node _T_1015 = bits(dma_mem_sz_int, 2, 0) @[el2_dma_ctrl.scala 364:23]
+    node _T_1016 = eq(_T_1015, UInt<2>("h02")) @[el2_dma_ctrl.scala 364:29]
+    node _T_1017 = bits(dma_mem_addr_int, 1, 0) @[el2_dma_ctrl.scala 364:57]
+    node _T_1018 = orr(_T_1017) @[el2_dma_ctrl.scala 364:64]
+    node _T_1019 = and(_T_1016, _T_1018) @[el2_dma_ctrl.scala 364:38]
+    node _T_1020 = or(_T_1014, _T_1019) @[el2_dma_ctrl.scala 363:60]
+    node _T_1021 = bits(dma_mem_sz_int, 2, 0) @[el2_dma_ctrl.scala 365:23]
+    node _T_1022 = eq(_T_1021, UInt<2>("h03")) @[el2_dma_ctrl.scala 365:29]
+    node _T_1023 = bits(dma_mem_addr_int, 2, 0) @[el2_dma_ctrl.scala 365:57]
+    node _T_1024 = orr(_T_1023) @[el2_dma_ctrl.scala 365:64]
+    node _T_1025 = and(_T_1022, _T_1024) @[el2_dma_ctrl.scala 365:38]
+    node _T_1026 = or(_T_1020, _T_1025) @[el2_dma_ctrl.scala 364:70]
+    node _T_1027 = bits(dma_mem_sz_int, 1, 0) @[el2_dma_ctrl.scala 366:48]
+    node _T_1028 = eq(_T_1027, UInt<2>("h02")) @[el2_dma_ctrl.scala 366:55]
+    node _T_1029 = bits(dma_mem_sz_int, 1, 0) @[el2_dma_ctrl.scala 366:81]
+    node _T_1030 = eq(_T_1029, UInt<2>("h03")) @[el2_dma_ctrl.scala 366:88]
+    node _T_1031 = or(_T_1028, _T_1030) @[el2_dma_ctrl.scala 366:64]
+    node _T_1032 = not(_T_1031) @[el2_dma_ctrl.scala 366:31]
+    node _T_1033 = and(dma_mem_addr_in_iccm, _T_1032) @[el2_dma_ctrl.scala 366:29]
+    node _T_1034 = or(_T_1026, _T_1033) @[el2_dma_ctrl.scala 365:70]
+    node _T_1035 = and(dma_mem_addr_in_dccm, io.dma_mem_write) @[el2_dma_ctrl.scala 367:29]
+    node _T_1036 = bits(dma_mem_sz_int, 1, 0) @[el2_dma_ctrl.scala 367:67]
+    node _T_1037 = eq(_T_1036, UInt<2>("h02")) @[el2_dma_ctrl.scala 367:74]
+    node _T_1038 = bits(dma_mem_sz_int, 1, 0) @[el2_dma_ctrl.scala 367:100]
+    node _T_1039 = eq(_T_1038, UInt<2>("h03")) @[el2_dma_ctrl.scala 367:107]
+    node _T_1040 = or(_T_1037, _T_1039) @[el2_dma_ctrl.scala 367:83]
+    node _T_1041 = not(_T_1040) @[el2_dma_ctrl.scala 367:50]
+    node _T_1042 = and(_T_1035, _T_1041) @[el2_dma_ctrl.scala 367:48]
+    node _T_1043 = or(_T_1034, _T_1042) @[el2_dma_ctrl.scala 366:108]
+    node _T_1044 = bits(dma_mem_sz_int, 2, 0) @[el2_dma_ctrl.scala 368:42]
+    node _T_1045 = eq(_T_1044, UInt<2>("h02")) @[el2_dma_ctrl.scala 368:49]
+    node _T_1046 = and(io.dma_mem_write, _T_1045) @[el2_dma_ctrl.scala 368:25]
+    node _T_1047 = bits(dma_mem_addr_int, 2, 0) @[el2_dma_ctrl.scala 368:88]
+    node _T_1048 = eq(_T_1047, UInt<1>("h00")) @[el2_dma_ctrl.scala 368:94]
+    node _T_1049 = bits(dma_mem_byteen, 3, 0) @[el2_dma_ctrl.scala 368:121]
+    node _T_1050 = bits(dma_mem_addr_int, 2, 0) @[el2_dma_ctrl.scala 369:26]
+    node _T_1051 = eq(_T_1050, UInt<1>("h01")) @[el2_dma_ctrl.scala 369:32]
+    node _T_1052 = bits(dma_mem_byteen, 4, 1) @[el2_dma_ctrl.scala 369:59]
+    node _T_1053 = bits(dma_mem_addr_int, 2, 0) @[el2_dma_ctrl.scala 370:26]
+    node _T_1054 = eq(_T_1053, UInt<2>("h02")) @[el2_dma_ctrl.scala 370:32]
+    node _T_1055 = bits(dma_mem_byteen, 5, 2) @[el2_dma_ctrl.scala 370:59]
+    node _T_1056 = bits(dma_mem_addr_int, 2, 0) @[el2_dma_ctrl.scala 371:26]
+    node _T_1057 = eq(_T_1056, UInt<2>("h03")) @[el2_dma_ctrl.scala 371:32]
+    node _T_1058 = bits(dma_mem_byteen, 6, 3) @[el2_dma_ctrl.scala 371:59]
+    node _T_1059 = mux(_T_1048, _T_1049, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1060 = mux(_T_1051, _T_1052, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1061 = mux(_T_1054, _T_1055, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1062 = mux(_T_1057, _T_1058, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1063 = or(_T_1059, _T_1060) @[Mux.scala 27:72]
+    node _T_1064 = or(_T_1063, _T_1061) @[Mux.scala 27:72]
+    node _T_1065 = or(_T_1064, _T_1062) @[Mux.scala 27:72]
+    wire _T_1066 : UInt<4> @[Mux.scala 27:72]
+    _T_1066 <= _T_1065 @[Mux.scala 27:72]
+    node _T_1067 = neq(_T_1066, UInt<4>("h0f")) @[el2_dma_ctrl.scala 371:68]
+    node _T_1068 = and(_T_1046, _T_1067) @[el2_dma_ctrl.scala 368:58]
+    node _T_1069 = or(_T_1043, _T_1068) @[el2_dma_ctrl.scala 367:125]
+    node _T_1070 = bits(dma_mem_sz_int, 2, 0) @[el2_dma_ctrl.scala 372:42]
+    node _T_1071 = eq(_T_1070, UInt<2>("h03")) @[el2_dma_ctrl.scala 372:49]
+    node _T_1072 = and(io.dma_mem_write, _T_1071) @[el2_dma_ctrl.scala 372:25]
+    node _T_1073 = bits(dma_mem_byteen, 7, 0) @[el2_dma_ctrl.scala 372:77]
+    node _T_1074 = eq(_T_1073, UInt<4>("h0f")) @[el2_dma_ctrl.scala 372:83]
+    node _T_1075 = bits(dma_mem_byteen, 7, 0) @[el2_dma_ctrl.scala 372:113]
+    node _T_1076 = eq(_T_1075, UInt<8>("h0f0")) @[el2_dma_ctrl.scala 372:119]
+    node _T_1077 = or(_T_1074, _T_1076) @[el2_dma_ctrl.scala 372:96]
+    node _T_1078 = bits(dma_mem_byteen, 7, 0) @[el2_dma_ctrl.scala 372:149]
+    node _T_1079 = eq(_T_1078, UInt<8>("h0ff")) @[el2_dma_ctrl.scala 372:155]
+    node _T_1080 = or(_T_1077, _T_1079) @[el2_dma_ctrl.scala 372:132]
+    node _T_1081 = eq(_T_1080, UInt<1>("h00")) @[el2_dma_ctrl.scala 372:60]
+    node _T_1082 = and(_T_1072, _T_1081) @[el2_dma_ctrl.scala 372:58]
+    node _T_1083 = or(_T_1069, _T_1082) @[el2_dma_ctrl.scala 371:79]
+    node _T_1084 = and(_T_1010, _T_1083) @[el2_dma_ctrl.scala 362:87]
+    dma_alignment_error <= _T_1084 @[el2_dma_ctrl.scala 362:25]
+    node _T_1085 = and(fifo_empty, dbg_dma_bubble_bus) @[el2_dma_ctrl.scala 376:39]
+    io.dma_dbg_ready <= _T_1085 @[el2_dma_ctrl.scala 376:25]
+    node _T_1086 = dshr(fifo_valid, RspPtr) @[el2_dma_ctrl.scala 377:39]
+    node _T_1087 = bits(_T_1086, 0, 0) @[el2_dma_ctrl.scala 377:39]
+    node _T_1088 = dshr(fifo_dbg, RspPtr) @[el2_dma_ctrl.scala 377:58]
+    node _T_1089 = bits(_T_1088, 0, 0) @[el2_dma_ctrl.scala 377:58]
+    node _T_1090 = and(_T_1087, _T_1089) @[el2_dma_ctrl.scala 377:48]
+    node _T_1091 = dshr(fifo_done, RspPtr) @[el2_dma_ctrl.scala 377:78]
+    node _T_1092 = bits(_T_1091, 0, 0) @[el2_dma_ctrl.scala 377:78]
+    node _T_1093 = and(_T_1090, _T_1092) @[el2_dma_ctrl.scala 377:67]
+    io.dma_dbg_cmd_done <= _T_1093 @[el2_dma_ctrl.scala 377:25]
+    node _T_1094 = bits(fifo_addr[RspPtr], 2, 2) @[el2_dma_ctrl.scala 378:49]
+    node _T_1095 = bits(fifo_data[RspPtr], 63, 32) @[el2_dma_ctrl.scala 378:71]
+    node _T_1096 = bits(fifo_data[RspPtr], 31, 0) @[el2_dma_ctrl.scala 378:98]
+    node _T_1097 = mux(_T_1094, _T_1095, _T_1096) @[el2_dma_ctrl.scala 378:31]
+    io.dma_dbg_rddata <= _T_1097 @[el2_dma_ctrl.scala 378:25]
+    node _T_1098 = orr(fifo_error[RspPtr]) @[el2_dma_ctrl.scala 379:47]
+    io.dma_dbg_cmd_fail <= _T_1098 @[el2_dma_ctrl.scala 379:25]
+    node _T_1099 = dshr(fifo_valid, RdPtr) @[el2_dma_ctrl.scala 381:38]
+    node _T_1100 = bits(_T_1099, 0, 0) @[el2_dma_ctrl.scala 381:38]
+    node _T_1101 = dshr(fifo_done, RdPtr) @[el2_dma_ctrl.scala 381:58]
+    node _T_1102 = bits(_T_1101, 0, 0) @[el2_dma_ctrl.scala 381:58]
+    node _T_1103 = eq(_T_1102, UInt<1>("h00")) @[el2_dma_ctrl.scala 381:48]
+    node _T_1104 = and(_T_1100, _T_1103) @[el2_dma_ctrl.scala 381:46]
+    node _T_1105 = dshr(fifo_dbg, RdPtr) @[el2_dma_ctrl.scala 381:76]
+    node _T_1106 = bits(_T_1105, 0, 0) @[el2_dma_ctrl.scala 381:76]
+    node _T_1107 = and(_T_1104, _T_1106) @[el2_dma_ctrl.scala 381:66]
+    node _T_1108 = or(dma_mem_addr_in_dccm, dma_mem_addr_in_iccm) @[el2_dma_ctrl.scala 381:111]
+    node _T_1109 = or(_T_1108, dma_mem_addr_in_pic) @[el2_dma_ctrl.scala 381:134]
+    node _T_1110 = not(_T_1109) @[el2_dma_ctrl.scala 381:88]
+    node _T_1111 = bits(_T_1110, 0, 0) @[el2_dma_ctrl.scala 381:164]
+    node _T_1112 = bits(dma_mem_sz_int, 1, 0) @[el2_dma_ctrl.scala 381:184]
+    node _T_1113 = neq(_T_1112, UInt<2>("h02")) @[el2_dma_ctrl.scala 381:191]
+    node _T_1114 = or(_T_1111, _T_1113) @[el2_dma_ctrl.scala 381:167]
+    node _T_1115 = and(_T_1107, _T_1114) @[el2_dma_ctrl.scala 381:84]
+    dma_dbg_cmd_error <= _T_1115 @[el2_dma_ctrl.scala 381:25]
+    node _T_1116 = or(dma_mem_addr_in_dccm, dma_mem_addr_in_pic) @[el2_dma_ctrl.scala 385:64]
+    node _T_1117 = and(dma_mem_req, _T_1116) @[el2_dma_ctrl.scala 385:40]
+    node _T_1118 = geq(dma_nack_count, dma_nack_count_csr) @[el2_dma_ctrl.scala 385:105]
+    node _T_1119 = and(_T_1117, _T_1118) @[el2_dma_ctrl.scala 385:87]
+    io.dma_dccm_stall_any <= _T_1119 @[el2_dma_ctrl.scala 385:25]
+    node _T_1120 = and(dma_mem_req, dma_mem_addr_in_iccm) @[el2_dma_ctrl.scala 386:40]
+    node _T_1121 = geq(dma_nack_count, dma_nack_count_csr) @[el2_dma_ctrl.scala 386:81]
+    node _T_1122 = and(_T_1120, _T_1121) @[el2_dma_ctrl.scala 386:63]
+    io.dma_iccm_stall_any <= _T_1122 @[el2_dma_ctrl.scala 386:25]
+    node _T_1123 = orr(fifo_valid) @[el2_dma_ctrl.scala 390:30]
+    node _T_1124 = not(_T_1123) @[el2_dma_ctrl.scala 390:17]
+    fifo_empty <= _T_1124 @[el2_dma_ctrl.scala 390:14]
+    dma_nack_count_csr <= io.dec_tlu_dma_qos_prty @[el2_dma_ctrl.scala 394:22]
+    node _T_1125 = geq(dma_nack_count, dma_nack_count_csr) @[el2_dma_ctrl.scala 395:45]
+    node _T_1126 = or(io.dma_dccm_req, io.dma_iccm_req) @[el2_dma_ctrl.scala 395:95]
+    node _T_1127 = eq(_T_1126, UInt<1>("h00")) @[el2_dma_ctrl.scala 395:77]
+    node _T_1128 = bits(_T_1127, 0, 0) @[Bitwise.scala 72:15]
+    node _T_1129 = mux(_T_1128, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+    node _T_1130 = bits(dma_nack_count, 2, 0) @[el2_dma_ctrl.scala 395:131]
+    node _T_1131 = and(_T_1129, _T_1130) @[el2_dma_ctrl.scala 395:115]
+    node _T_1132 = bits(dma_mem_req, 0, 0) @[el2_dma_ctrl.scala 395:156]
+    node _T_1133 = or(io.dma_dccm_req, io.dma_iccm_req) @[el2_dma_ctrl.scala 395:183]
+    node _T_1134 = eq(_T_1133, UInt<1>("h00")) @[el2_dma_ctrl.scala 395:165]
+    node _T_1135 = and(_T_1132, _T_1134) @[el2_dma_ctrl.scala 395:163]
+    node _T_1136 = bits(dma_nack_count, 2, 0) @[el2_dma_ctrl.scala 395:218]
+    node _T_1137 = add(_T_1136, UInt<1>("h01")) @[el2_dma_ctrl.scala 395:224]
+    node _T_1138 = tail(_T_1137, 1) @[el2_dma_ctrl.scala 395:224]
+    node _T_1139 = mux(_T_1135, _T_1138, UInt<1>("h00")) @[el2_dma_ctrl.scala 395:142]
+    node dma_nack_count_d = mux(_T_1125, _T_1131, _T_1139) @[el2_dma_ctrl.scala 395:29]
+    node _T_1140 = bits(dma_nack_count_d, 2, 0) @[el2_dma_ctrl.scala 398:31]
+    node _T_1141 = bits(dma_mem_req, 0, 0) @[el2_dma_ctrl.scala 398:55]
+    reg _T_1142 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_1141 : @[Reg.scala 28:19]
+      _T_1142 <= _T_1140 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    dma_nack_count <= _T_1142 @[el2_dma_ctrl.scala 397:22]
+    node _T_1143 = dshr(fifo_valid, RdPtr) @[el2_dma_ctrl.scala 403:33]
+    node _T_1144 = bits(_T_1143, 0, 0) @[el2_dma_ctrl.scala 403:33]
+    node _T_1145 = dshr(fifo_rpend, RdPtr) @[el2_dma_ctrl.scala 403:54]
+    node _T_1146 = bits(_T_1145, 0, 0) @[el2_dma_ctrl.scala 403:54]
+    node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[el2_dma_ctrl.scala 403:43]
+    node _T_1148 = and(_T_1144, _T_1147) @[el2_dma_ctrl.scala 403:41]
+    node _T_1149 = dshr(fifo_done, RdPtr) @[el2_dma_ctrl.scala 403:74]
+    node _T_1150 = bits(_T_1149, 0, 0) @[el2_dma_ctrl.scala 403:74]
+    node _T_1151 = eq(_T_1150, UInt<1>("h00")) @[el2_dma_ctrl.scala 403:64]
+    node _T_1152 = and(_T_1148, _T_1151) @[el2_dma_ctrl.scala 403:62]
+    node _T_1153 = or(dma_address_error, dma_alignment_error) @[el2_dma_ctrl.scala 403:104]
+    node _T_1154 = or(_T_1153, dma_dbg_cmd_error) @[el2_dma_ctrl.scala 403:126]
+    node _T_1155 = eq(_T_1154, UInt<1>("h00")) @[el2_dma_ctrl.scala 403:84]
+    node _T_1156 = and(_T_1152, _T_1155) @[el2_dma_ctrl.scala 403:82]
+    dma_mem_req <= _T_1156 @[el2_dma_ctrl.scala 403:20]
+    node _T_1157 = or(dma_mem_addr_in_dccm, dma_mem_addr_in_pic) @[el2_dma_ctrl.scala 404:59]
+    node _T_1158 = and(dma_mem_req, _T_1157) @[el2_dma_ctrl.scala 404:35]
+    node _T_1159 = and(_T_1158, io.dccm_ready) @[el2_dma_ctrl.scala 404:82]
+    io.dma_dccm_req <= _T_1159 @[el2_dma_ctrl.scala 404:20]
+    node _T_1160 = and(dma_mem_req, dma_mem_addr_in_iccm) @[el2_dma_ctrl.scala 405:35]
+    node _T_1161 = and(_T_1160, io.iccm_ready) @[el2_dma_ctrl.scala 405:58]
+    io.dma_iccm_req <= _T_1161 @[el2_dma_ctrl.scala 405:20]
+    io.dma_mem_tag <= RdPtr @[el2_dma_ctrl.scala 406:20]
+    dma_mem_addr_int <= fifo_addr[RdPtr] @[el2_dma_ctrl.scala 407:20]
+    dma_mem_sz_int <= fifo_sz[RdPtr] @[el2_dma_ctrl.scala 408:20]
+    node _T_1162 = bits(dma_mem_byteen, 7, 0) @[el2_dma_ctrl.scala 409:61]
+    node _T_1163 = eq(_T_1162, UInt<8>("h0f0")) @[el2_dma_ctrl.scala 409:67]
+    node _T_1164 = and(io.dma_mem_write, _T_1163) @[el2_dma_ctrl.scala 409:44]
+    node _T_1165 = bits(dma_mem_addr_int, 31, 3) @[el2_dma_ctrl.scala 409:101]
+    node _T_1166 = bits(dma_mem_addr_int, 1, 0) @[el2_dma_ctrl.scala 409:131]
+    node _T_1167 = cat(_T_1165, UInt<1>("h01")) @[Cat.scala 29:58]
+    node _T_1168 = cat(_T_1167, _T_1166) @[Cat.scala 29:58]
+    node _T_1169 = bits(dma_mem_addr_int, 31, 0) @[el2_dma_ctrl.scala 409:156]
+    node _T_1170 = mux(_T_1164, _T_1168, _T_1169) @[el2_dma_ctrl.scala 409:26]
+    io.dma_mem_addr <= _T_1170 @[el2_dma_ctrl.scala 409:20]
+    node _T_1171 = bits(dma_mem_byteen, 7, 0) @[el2_dma_ctrl.scala 410:62]
+    node _T_1172 = eq(_T_1171, UInt<4>("h0f")) @[el2_dma_ctrl.scala 410:68]
+    node _T_1173 = bits(dma_mem_byteen, 7, 0) @[el2_dma_ctrl.scala 410:98]
+    node _T_1174 = eq(_T_1173, UInt<8>("h0f0")) @[el2_dma_ctrl.scala 410:104]
+    node _T_1175 = or(_T_1172, _T_1174) @[el2_dma_ctrl.scala 410:81]
+    node _T_1176 = and(io.dma_mem_write, _T_1175) @[el2_dma_ctrl.scala 410:44]
+    node _T_1177 = bits(dma_mem_sz_int, 2, 0) @[el2_dma_ctrl.scala 410:138]
+    node _T_1178 = mux(_T_1176, UInt<2>("h02"), _T_1177) @[el2_dma_ctrl.scala 410:26]
+    io.dma_mem_sz <= _T_1178 @[el2_dma_ctrl.scala 410:20]
+    dma_mem_byteen <= fifo_byteen[RdPtr] @[el2_dma_ctrl.scala 411:20]
+    node _T_1179 = dshr(fifo_write, RdPtr) @[el2_dma_ctrl.scala 412:33]
+    node _T_1180 = bits(_T_1179, 0, 0) @[el2_dma_ctrl.scala 412:33]
+    io.dma_mem_write <= _T_1180 @[el2_dma_ctrl.scala 412:20]
+    io.dma_mem_wdata <= fifo_data[RdPtr] @[el2_dma_ctrl.scala 413:20]
+    node _T_1181 = eq(io.dma_mem_write, UInt<1>("h00")) @[el2_dma_ctrl.scala 417:47]
+    node _T_1182 = and(io.dma_dccm_req, _T_1181) @[el2_dma_ctrl.scala 417:45]
+    io.dma_pmu_dccm_read <= _T_1182 @[el2_dma_ctrl.scala 417:26]
+    node _T_1183 = and(io.dma_dccm_req, io.dma_mem_write) @[el2_dma_ctrl.scala 418:45]
+    io.dma_pmu_dccm_write <= _T_1183 @[el2_dma_ctrl.scala 418:26]
+    node _T_1184 = or(io.dma_dccm_req, io.dma_iccm_req) @[el2_dma_ctrl.scala 419:46]
+    node _T_1185 = eq(io.dma_mem_write, UInt<1>("h00")) @[el2_dma_ctrl.scala 419:67]
+    node _T_1186 = and(_T_1184, _T_1185) @[el2_dma_ctrl.scala 419:65]
+    io.dma_pmu_any_read <= _T_1186 @[el2_dma_ctrl.scala 419:26]
+    node _T_1187 = or(io.dma_dccm_req, io.dma_iccm_req) @[el2_dma_ctrl.scala 420:46]
+    node _T_1188 = and(_T_1187, io.dma_mem_write) @[el2_dma_ctrl.scala 420:65]
+    io.dma_pmu_any_write <= _T_1188 @[el2_dma_ctrl.scala 420:26]
+    reg _T_1189 : UInt<1>, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 425:12]
+    _T_1189 <= fifo_full_spec @[el2_dma_ctrl.scala 425:12]
+    fifo_full <= _T_1189 @[el2_dma_ctrl.scala 424:22]
+    reg _T_1190 : UInt<1>, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 429:12]
+    _T_1190 <= io.dbg_dma_bubble @[el2_dma_ctrl.scala 429:12]
+    dbg_dma_bubble_bus <= _T_1190 @[el2_dma_ctrl.scala 428:22]
+    reg _T_1191 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 433:12]
+    _T_1191 <= io.dma_dbg_cmd_done @[el2_dma_ctrl.scala 433:12]
+    dma_dbg_cmd_done_q <= _T_1191 @[el2_dma_ctrl.scala 432:22]
+    node _T_1192 = and(bus_cmd_valid, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 438:44]
+    node _T_1193 = or(_T_1192, io.dbg_cmd_valid) @[el2_dma_ctrl.scala 438:65]
+    node dma_buffer_c1_clken = or(_T_1193, io.clk_override) @[el2_dma_ctrl.scala 438:84]
+    node _T_1194 = or(bus_cmd_valid, bus_rsp_valid) @[el2_dma_ctrl.scala 439:44]
+    node _T_1195 = or(_T_1194, io.dbg_cmd_valid) @[el2_dma_ctrl.scala 439:60]
+    node _T_1196 = or(_T_1195, io.dma_dbg_cmd_done) @[el2_dma_ctrl.scala 439:79]
+    node _T_1197 = or(_T_1196, dma_dbg_cmd_done_q) @[el2_dma_ctrl.scala 439:101]
+    node _T_1198 = orr(fifo_valid) @[el2_dma_ctrl.scala 439:136]
+    node _T_1199 = or(_T_1197, _T_1198) @[el2_dma_ctrl.scala 439:122]
+    node dma_free_clken = or(_T_1199, io.clk_override) @[el2_dma_ctrl.scala 439:141]
+    inst dma_buffer_c1cgc of rvclkhdr_10 @[el2_dma_ctrl.scala 441:32]
+    dma_buffer_c1cgc.clock <= clock
+    dma_buffer_c1cgc.reset <= reset
+    dma_buffer_c1cgc.io.en <= dma_buffer_c1_clken @[el2_dma_ctrl.scala 442:33]
+    dma_buffer_c1cgc.io.scan_mode <= io.scan_mode @[el2_dma_ctrl.scala 443:33]
+    dma_buffer_c1cgc.io.clk <= clock @[el2_dma_ctrl.scala 444:33]
+    dma_buffer_c1_clk <= dma_buffer_c1cgc.io.l1clk @[el2_dma_ctrl.scala 445:33]
+    inst dma_free_cgc of rvclkhdr_11 @[el2_dma_ctrl.scala 447:28]
+    dma_free_cgc.clock <= clock
+    dma_free_cgc.reset <= reset
+    dma_free_cgc.io.en <= dma_free_clken @[el2_dma_ctrl.scala 448:29]
+    dma_free_cgc.io.scan_mode <= io.scan_mode @[el2_dma_ctrl.scala 449:29]
+    dma_free_cgc.io.clk <= clock @[el2_dma_ctrl.scala 450:29]
+    dma_free_clk <= dma_free_cgc.io.l1clk @[el2_dma_ctrl.scala 451:29]
+    inst dma_bus_cgc of rvclkhdr_12 @[el2_dma_ctrl.scala 453:27]
+    dma_bus_cgc.clock <= clock
+    dma_bus_cgc.reset <= reset
+    dma_bus_cgc.io.en <= io.dma_bus_clk_en @[el2_dma_ctrl.scala 454:28]
+    dma_bus_cgc.io.scan_mode <= io.scan_mode @[el2_dma_ctrl.scala 455:28]
+    dma_bus_cgc.io.clk <= clock @[el2_dma_ctrl.scala 456:28]
+    dma_bus_clk <= dma_bus_cgc.io.l1clk @[el2_dma_ctrl.scala 457:28]
+    node wrbuf_en = and(io.dma_axi_awvalid, io.dma_axi_awready) @[el2_dma_ctrl.scala 461:46]
+    node wrbuf_data_en = and(io.dma_axi_wvalid, io.dma_axi_wready) @[el2_dma_ctrl.scala 462:45]
+    node wrbuf_cmd_sent = and(axi_mstr_prty_en, bus_cmd_write) @[el2_dma_ctrl.scala 463:40]
+    node _T_1200 = bits(wrbuf_cmd_sent, 0, 0) @[el2_dma_ctrl.scala 464:42]
+    node _T_1201 = eq(wrbuf_en, UInt<1>("h00")) @[el2_dma_ctrl.scala 464:51]
+    node wrbuf_rst = and(_T_1200, _T_1201) @[el2_dma_ctrl.scala 464:49]
+    node _T_1202 = bits(wrbuf_cmd_sent, 0, 0) @[el2_dma_ctrl.scala 465:42]
+    node _T_1203 = eq(wrbuf_data_en, UInt<1>("h00")) @[el2_dma_ctrl.scala 465:51]
+    node wrbuf_data_rst = and(_T_1202, _T_1203) @[el2_dma_ctrl.scala 465:49]
+    node _T_1204 = mux(wrbuf_en, UInt<1>("h01"), wrbuf_vld) @[el2_dma_ctrl.scala 467:63]
+    node _T_1205 = eq(wrbuf_rst, UInt<1>("h00")) @[el2_dma_ctrl.scala 467:92]
+    node _T_1206 = and(_T_1204, _T_1205) @[el2_dma_ctrl.scala 467:90]
+    reg _T_1207 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 467:59]
+    _T_1207 <= _T_1206 @[el2_dma_ctrl.scala 467:59]
+    wrbuf_vld <= _T_1207 @[el2_dma_ctrl.scala 467:25]
+    node _T_1208 = mux(wrbuf_data_en, UInt<1>("h01"), wrbuf_data_vld) @[el2_dma_ctrl.scala 469:63]
+    node _T_1209 = eq(wrbuf_data_rst, UInt<1>("h00")) @[el2_dma_ctrl.scala 469:102]
+    node _T_1210 = and(_T_1208, _T_1209) @[el2_dma_ctrl.scala 469:100]
+    reg _T_1211 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 469:59]
+    _T_1211 <= _T_1210 @[el2_dma_ctrl.scala 469:59]
+    wrbuf_data_vld <= _T_1211 @[el2_dma_ctrl.scala 469:25]
+    reg wrbuf_tag : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when wrbuf_en : @[Reg.scala 28:19]
+      wrbuf_tag <= io.dma_axi_awid @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    reg wrbuf_sz : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when wrbuf_en : @[Reg.scala 28:19]
+      wrbuf_sz <= io.dma_axi_awsize @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_1212 = and(wrbuf_en, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 479:62]
+    inst rvclkhdr_10 of rvclkhdr_13 @[el2_lib.scala 508:23]
+    rvclkhdr_10.clock <= clock
+    rvclkhdr_10.reset <= reset
+    rvclkhdr_10.io.clk <= clock @[el2_lib.scala 510:18]
+    rvclkhdr_10.io.en <= _T_1212 @[el2_lib.scala 511:17]
+    rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
+    reg wrbuf_addr : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
+    wrbuf_addr <= io.dma_axi_awaddr @[el2_lib.scala 514:16]
+    node _T_1213 = and(wrbuf_data_en, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 481:66]
+    inst rvclkhdr_11 of rvclkhdr_14 @[el2_lib.scala 508:23]
+    rvclkhdr_11.clock <= clock
+    rvclkhdr_11.reset <= reset
+    rvclkhdr_11.io.clk <= clock @[el2_lib.scala 510:18]
+    rvclkhdr_11.io.en <= _T_1213 @[el2_lib.scala 511:17]
+    rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
+    reg wrbuf_data : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
+    wrbuf_data <= io.dma_axi_wdata @[el2_lib.scala 514:16]
+    reg wrbuf_byteen : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when wrbuf_data_en : @[Reg.scala 28:19]
+      wrbuf_byteen <= io.dma_axi_wstrb @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node rdbuf_en = and(io.dma_axi_arvalid, io.dma_axi_arready) @[el2_dma_ctrl.scala 489:58]
+    node _T_1214 = eq(bus_cmd_write, UInt<1>("h00")) @[el2_dma_ctrl.scala 490:44]
+    node rdbuf_cmd_sent = and(axi_mstr_prty_en, _T_1214) @[el2_dma_ctrl.scala 490:42]
+    node _T_1215 = bits(rdbuf_cmd_sent, 0, 0) @[el2_dma_ctrl.scala 491:54]
+    node _T_1216 = eq(rdbuf_en, UInt<1>("h00")) @[el2_dma_ctrl.scala 491:63]
+    node rdbuf_rst = and(_T_1215, _T_1216) @[el2_dma_ctrl.scala 491:61]
+    node _T_1217 = mux(rdbuf_en, UInt<1>("h01"), rdbuf_vld) @[el2_dma_ctrl.scala 493:51]
+    node _T_1218 = eq(rdbuf_rst, UInt<1>("h00")) @[el2_dma_ctrl.scala 493:80]
+    node _T_1219 = and(_T_1217, _T_1218) @[el2_dma_ctrl.scala 493:78]
+    reg _T_1220 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dma_ctrl.scala 493:47]
+    _T_1220 <= _T_1219 @[el2_dma_ctrl.scala 493:47]
+    rdbuf_vld <= _T_1220 @[el2_dma_ctrl.scala 493:13]
+    reg rdbuf_tag : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when rdbuf_en : @[Reg.scala 28:19]
+      rdbuf_tag <= io.dma_axi_arid @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    reg rdbuf_sz : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when rdbuf_en : @[Reg.scala 28:19]
+      rdbuf_sz <= io.dma_axi_arsize @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_1221 = and(rdbuf_en, io.dma_bus_clk_en) @[el2_dma_ctrl.scala 503:55]
+    inst rvclkhdr_12 of rvclkhdr_15 @[el2_lib.scala 508:23]
+    rvclkhdr_12.clock <= clock
+    rvclkhdr_12.reset <= reset
+    rvclkhdr_12.io.clk <= clock @[el2_lib.scala 510:18]
+    rvclkhdr_12.io.en <= _T_1221 @[el2_lib.scala 511:17]
+    rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
+    reg rdbuf_addr : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
+    rdbuf_addr <= io.dma_axi_araddr @[el2_lib.scala 514:16]
+    node _T_1222 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[el2_dma_ctrl.scala 505:44]
+    node _T_1223 = and(wrbuf_vld, _T_1222) @[el2_dma_ctrl.scala 505:42]
+    node _T_1224 = not(_T_1223) @[el2_dma_ctrl.scala 505:30]
+    io.dma_axi_awready <= _T_1224 @[el2_dma_ctrl.scala 505:27]
+    node _T_1225 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[el2_dma_ctrl.scala 506:49]
+    node _T_1226 = and(wrbuf_data_vld, _T_1225) @[el2_dma_ctrl.scala 506:47]
+    node _T_1227 = not(_T_1226) @[el2_dma_ctrl.scala 506:30]
+    io.dma_axi_wready <= _T_1227 @[el2_dma_ctrl.scala 506:27]
+    node _T_1228 = eq(rdbuf_cmd_sent, UInt<1>("h00")) @[el2_dma_ctrl.scala 507:44]
+    node _T_1229 = and(rdbuf_vld, _T_1228) @[el2_dma_ctrl.scala 507:42]
+    node _T_1230 = not(_T_1229) @[el2_dma_ctrl.scala 507:30]
+    io.dma_axi_arready <= _T_1230 @[el2_dma_ctrl.scala 507:27]
+    node _T_1231 = and(wrbuf_vld, wrbuf_data_vld) @[el2_dma_ctrl.scala 511:51]
+    node _T_1232 = or(_T_1231, rdbuf_vld) @[el2_dma_ctrl.scala 511:69]
+    bus_cmd_valid <= _T_1232 @[el2_dma_ctrl.scala 511:37]
+    node _T_1233 = and(bus_cmd_valid, dma_fifo_ready) @[el2_dma_ctrl.scala 512:54]
+    axi_mstr_prty_en <= _T_1233 @[el2_dma_ctrl.scala 512:37]
+    bus_cmd_write <= axi_mstr_sel @[el2_dma_ctrl.scala 513:37]
+    bus_cmd_posted_write <= UInt<1>("h00") @[el2_dma_ctrl.scala 514:25]
+    node _T_1234 = bits(axi_mstr_sel, 0, 0) @[el2_dma_ctrl.scala 515:57]
+    node _T_1235 = mux(_T_1234, wrbuf_addr, rdbuf_addr) @[el2_dma_ctrl.scala 515:43]
+    bus_cmd_addr <= _T_1235 @[el2_dma_ctrl.scala 515:37]
+    node _T_1236 = bits(axi_mstr_sel, 0, 0) @[el2_dma_ctrl.scala 516:59]
+    node _T_1237 = mux(_T_1236, wrbuf_sz, rdbuf_sz) @[el2_dma_ctrl.scala 516:45]
+    bus_cmd_sz <= _T_1237 @[el2_dma_ctrl.scala 516:39]
+    bus_cmd_wdata <= wrbuf_data @[el2_dma_ctrl.scala 517:37]
+    bus_cmd_byteen <= wrbuf_byteen @[el2_dma_ctrl.scala 518:37]
+    node _T_1238 = bits(axi_mstr_sel, 0, 0) @[el2_dma_ctrl.scala 519:57]
+    node _T_1239 = mux(_T_1238, wrbuf_tag, rdbuf_tag) @[el2_dma_ctrl.scala 519:43]
+    bus_cmd_tag <= _T_1239 @[el2_dma_ctrl.scala 519:37]
+    bus_cmd_mid <= UInt<1>("h00") @[el2_dma_ctrl.scala 520:37]
+    bus_cmd_prty <= UInt<1>("h00") @[el2_dma_ctrl.scala 521:37]
+    node _T_1240 = and(wrbuf_vld, wrbuf_data_vld) @[el2_dma_ctrl.scala 525:43]
+    node _T_1241 = and(_T_1240, rdbuf_vld) @[el2_dma_ctrl.scala 525:60]
+    node _T_1242 = eq(_T_1241, UInt<1>("h01")) @[el2_dma_ctrl.scala 525:73]
+    node _T_1243 = and(wrbuf_vld, wrbuf_data_vld) @[el2_dma_ctrl.scala 525:111]
+    node _T_1244 = mux(_T_1242, axi_mstr_priority, _T_1243) @[el2_dma_ctrl.scala 525:31]
+    axi_mstr_sel <= _T_1244 @[el2_dma_ctrl.scala 525:25]
+    node axi_mstr_prty_in = not(axi_mstr_priority) @[el2_dma_ctrl.scala 526:27]
+    node _T_1245 = bits(axi_mstr_prty_en, 0, 0) @[el2_dma_ctrl.scala 530:55]
+    reg _T_1246 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_1245 : @[Reg.scala 28:19]
+      _T_1246 <= axi_mstr_prty_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    axi_mstr_priority <= _T_1246 @[el2_dma_ctrl.scala 529:27]
+    node _T_1247 = dshr(fifo_valid, RspPtr) @[el2_dma_ctrl.scala 533:39]
+    node _T_1248 = bits(_T_1247, 0, 0) @[el2_dma_ctrl.scala 533:39]
+    node _T_1249 = dshr(fifo_dbg, RspPtr) @[el2_dma_ctrl.scala 533:59]
+    node _T_1250 = bits(_T_1249, 0, 0) @[el2_dma_ctrl.scala 533:59]
+    node _T_1251 = eq(_T_1250, UInt<1>("h00")) @[el2_dma_ctrl.scala 533:50]
+    node _T_1252 = and(_T_1248, _T_1251) @[el2_dma_ctrl.scala 533:48]
+    node _T_1253 = dshr(fifo_done_bus, RspPtr) @[el2_dma_ctrl.scala 533:83]
+    node _T_1254 = bits(_T_1253, 0, 0) @[el2_dma_ctrl.scala 533:83]
+    node axi_rsp_valid = and(_T_1252, _T_1254) @[el2_dma_ctrl.scala 533:68]
+    node _T_1255 = dshr(fifo_write, RspPtr) @[el2_dma_ctrl.scala 535:39]
+    node axi_rsp_write = bits(_T_1255, 0, 0) @[el2_dma_ctrl.scala 535:39]
+    node _T_1256 = bits(fifo_error[RspPtr], 0, 0) @[el2_dma_ctrl.scala 536:51]
+    node _T_1257 = bits(fifo_error[RspPtr], 1, 1) @[el2_dma_ctrl.scala 536:83]
+    node _T_1258 = mux(_T_1257, UInt<2>("h03"), UInt<1>("h00")) @[el2_dma_ctrl.scala 536:64]
+    node axi_rsp_error = mux(_T_1256, UInt<2>("h02"), _T_1258) @[el2_dma_ctrl.scala 536:32]
+    node _T_1259 = and(axi_rsp_valid, axi_rsp_write) @[el2_dma_ctrl.scala 542:44]
+    io.dma_axi_bvalid <= _T_1259 @[el2_dma_ctrl.scala 542:27]
+    node _T_1260 = bits(axi_rsp_error, 1, 0) @[el2_dma_ctrl.scala 543:49]
+    io.dma_axi_bresp <= _T_1260 @[el2_dma_ctrl.scala 543:33]
+    io.dma_axi_bid <= fifo_tag[RspPtr] @[el2_dma_ctrl.scala 544:33]
+    node _T_1261 = eq(axi_rsp_write, UInt<1>("h00")) @[el2_dma_ctrl.scala 546:46]
+    node _T_1262 = and(axi_rsp_valid, _T_1261) @[el2_dma_ctrl.scala 546:44]
+    io.dma_axi_rvalid <= _T_1262 @[el2_dma_ctrl.scala 546:27]
+    io.dma_axi_rresp <= axi_rsp_error @[el2_dma_ctrl.scala 547:33]
+    node _T_1263 = bits(fifo_data[RspPtr], 63, 0) @[el2_dma_ctrl.scala 548:51]
+    io.dma_axi_rdata <= _T_1263 @[el2_dma_ctrl.scala 548:35]
+    io.dma_axi_rlast <= UInt<1>("h01") @[el2_dma_ctrl.scala 549:33]
+    io.dma_axi_rid <= fifo_tag[RspPtr] @[el2_dma_ctrl.scala 550:37]
+    bus_posted_write_done <= UInt<1>("h00") @[el2_dma_ctrl.scala 552:25]
+    node _T_1264 = or(io.dma_axi_bvalid, io.dma_axi_rvalid) @[el2_dma_ctrl.scala 553:59]
+    bus_rsp_valid <= _T_1264 @[el2_dma_ctrl.scala 553:37]
+    node _T_1265 = and(io.dma_axi_bvalid, io.dma_axi_bready) @[el2_dma_ctrl.scala 554:60]
+    node _T_1266 = and(io.dma_axi_rvalid, io.dma_axi_rready) @[el2_dma_ctrl.scala 554:102]
+    node _T_1267 = or(_T_1265, _T_1266) @[el2_dma_ctrl.scala 554:81]
+    bus_rsp_sent <= _T_1267 @[el2_dma_ctrl.scala 554:37]
+    
diff --git a/el2_dma_ctrl.v b/el2_dma_ctrl.v
new file mode 100644
index 00000000..8da16ae8
--- /dev/null
+++ b/el2_dma_ctrl.v
@@ -0,0 +1,2046 @@
+module rvclkhdr(
+  output  io_l1clk,
+  input   io_clk,
+  input   io_en,
+  input   io_scan_mode
+);
+  wire  clkhdr_Q; // @[el2_lib.scala 474:26]
+  wire  clkhdr_CK; // @[el2_lib.scala 474:26]
+  wire  clkhdr_EN; // @[el2_lib.scala 474:26]
+  wire  clkhdr_SE; // @[el2_lib.scala 474:26]
+  TEC_RV_ICG clkhdr ( // @[el2_lib.scala 474:26]
+    .Q(clkhdr_Q),
+    .CK(clkhdr_CK),
+    .EN(clkhdr_EN),
+    .SE(clkhdr_SE)
+  );
+  assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14]
+  assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18]
+  assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18]
+  assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18]
+endmodule
+module el2_dma_ctrl(
+  input         clock,
+  input         reset,
+  input         io_free_clk,
+  input         io_rst_l,
+  input         io_dma_bus_clk_en,
+  input         io_clk_override,
+  input         io_scan_mode,
+  input  [31:0] io_dbg_cmd_addr,
+  input  [31:0] io_dbg_cmd_wrdata,
+  input         io_dbg_cmd_valid,
+  input         io_dbg_cmd_write,
+  input  [1:0]  io_dbg_cmd_type,
+  input  [1:0]  io_dbg_cmd_size,
+  input         io_dbg_dma_bubble,
+  output        io_dma_dbg_ready,
+  output        io_dma_dbg_cmd_done,
+  output        io_dma_dbg_cmd_fail,
+  output [31:0] io_dma_dbg_rddata,
+  output        io_dma_dccm_req,
+  output        io_dma_iccm_req,
+  output [2:0]  io_dma_mem_tag,
+  output [31:0] io_dma_mem_addr,
+  output [2:0]  io_dma_mem_sz,
+  output        io_dma_mem_write,
+  output [63:0] io_dma_mem_wdata,
+  input         io_dccm_dma_rvalid,
+  input         io_dccm_dma_ecc_error,
+  input  [2:0]  io_dccm_dma_rtag,
+  input  [63:0] io_dccm_dma_rdata,
+  input         io_iccm_dma_rvalid,
+  input         io_iccm_dma_ecc_error,
+  input  [2:0]  io_iccm_dma_rtag,
+  input  [63:0] io_iccm_dma_rdata,
+  output        io_dma_dccm_stall_any,
+  output        io_dma_iccm_stall_any,
+  input         io_dccm_ready,
+  input         io_iccm_ready,
+  input  [2:0]  io_dec_tlu_dma_qos_prty,
+  output        io_dma_pmu_dccm_read,
+  output        io_dma_pmu_dccm_write,
+  output        io_dma_pmu_any_read,
+  output        io_dma_pmu_any_write,
+  input         io_dma_axi_awvalid,
+  output        io_dma_axi_awready,
+  input         io_dma_axi_awid,
+  input  [31:0] io_dma_axi_awaddr,
+  input  [2:0]  io_dma_axi_awsize,
+  input         io_dma_axi_wvalid,
+  output        io_dma_axi_wready,
+  input  [63:0] io_dma_axi_wdata,
+  input  [7:0]  io_dma_axi_wstrb,
+  output        io_dma_axi_bvalid,
+  input         io_dma_axi_bready,
+  output [1:0]  io_dma_axi_bresp,
+  output        io_dma_axi_bid,
+  input         io_dma_axi_arvalid,
+  output        io_dma_axi_arready,
+  input         io_dma_axi_arid,
+  input  [31:0] io_dma_axi_araddr,
+  input  [2:0]  io_dma_axi_arsize,
+  output        io_dma_axi_rvalid,
+  input         io_dma_axi_rready,
+  output        io_dma_axi_rid,
+  output [63:0] io_dma_axi_rdata,
+  output [1:0]  io_dma_axi_rresp,
+  output        io_dma_axi_rlast
+);
+`ifdef RANDOMIZE_REG_INIT
+  reg [31:0] _RAND_0;
+  reg [31:0] _RAND_1;
+  reg [31:0] _RAND_2;
+  reg [31:0] _RAND_3;
+  reg [31:0] _RAND_4;
+  reg [31:0] _RAND_5;
+  reg [31:0] _RAND_6;
+  reg [31:0] _RAND_7;
+  reg [31:0] _RAND_8;
+  reg [31:0] _RAND_9;
+  reg [31:0] _RAND_10;
+  reg [31:0] _RAND_11;
+  reg [31:0] _RAND_12;
+  reg [31:0] _RAND_13;
+  reg [31:0] _RAND_14;
+  reg [31:0] _RAND_15;
+  reg [31:0] _RAND_16;
+  reg [31:0] _RAND_17;
+  reg [31:0] _RAND_18;
+  reg [31:0] _RAND_19;
+  reg [31:0] _RAND_20;
+  reg [31:0] _RAND_21;
+  reg [31:0] _RAND_22;
+  reg [31:0] _RAND_23;
+  reg [31:0] _RAND_24;
+  reg [31:0] _RAND_25;
+  reg [31:0] _RAND_26;
+  reg [31:0] _RAND_27;
+  reg [31:0] _RAND_28;
+  reg [31:0] _RAND_29;
+  reg [31:0] _RAND_30;
+  reg [31:0] _RAND_31;
+  reg [31:0] _RAND_32;
+  reg [31:0] _RAND_33;
+  reg [31:0] _RAND_34;
+  reg [31:0] _RAND_35;
+  reg [31:0] _RAND_36;
+  reg [31:0] _RAND_37;
+  reg [31:0] _RAND_38;
+  reg [31:0] _RAND_39;
+  reg [31:0] _RAND_40;
+  reg [31:0] _RAND_41;
+  reg [31:0] _RAND_42;
+  reg [31:0] _RAND_43;
+  reg [31:0] _RAND_44;
+  reg [31:0] _RAND_45;
+  reg [31:0] _RAND_46;
+  reg [31:0] _RAND_47;
+  reg [31:0] _RAND_48;
+  reg [63:0] _RAND_49;
+  reg [31:0] _RAND_50;
+  reg [31:0] _RAND_51;
+  reg [31:0] _RAND_52;
+  reg [31:0] _RAND_53;
+  reg [31:0] _RAND_54;
+  reg [31:0] _RAND_55;
+  reg [31:0] _RAND_56;
+  reg [31:0] _RAND_57;
+  reg [31:0] _RAND_58;
+  reg [31:0] _RAND_59;
+  reg [31:0] _RAND_60;
+  reg [31:0] _RAND_61;
+  reg [31:0] _RAND_62;
+  reg [31:0] _RAND_63;
+  reg [31:0] _RAND_64;
+  reg [63:0] _RAND_65;
+  reg [63:0] _RAND_66;
+  reg [63:0] _RAND_67;
+  reg [63:0] _RAND_68;
+  reg [63:0] _RAND_69;
+  reg [31:0] _RAND_70;
+  reg [31:0] _RAND_71;
+  reg [31:0] _RAND_72;
+  reg [31:0] _RAND_73;
+  reg [31:0] _RAND_74;
+  reg [31:0] _RAND_75;
+  reg [31:0] _RAND_76;
+  reg [31:0] _RAND_77;
+  reg [31:0] _RAND_78;
+`endif // RANDOMIZE_REG_INIT
+  wire  rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_io_clk; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_io_en; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_1_io_en; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_2_io_en; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_3_io_en; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_4_io_en; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_5_io_l1clk; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_5_io_clk; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_5_io_en; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_6_io_l1clk; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_6_io_clk; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_6_io_en; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_7_io_l1clk; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_7_io_clk; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_7_io_en; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_8_io_l1clk; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_8_io_clk; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_8_io_en; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_9_io_l1clk; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_9_io_clk; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_9_io_en; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 508:23]
+  wire  dma_buffer_c1cgc_io_l1clk; // @[el2_dma_ctrl.scala 441:32]
+  wire  dma_buffer_c1cgc_io_clk; // @[el2_dma_ctrl.scala 441:32]
+  wire  dma_buffer_c1cgc_io_en; // @[el2_dma_ctrl.scala 441:32]
+  wire  dma_buffer_c1cgc_io_scan_mode; // @[el2_dma_ctrl.scala 441:32]
+  wire  dma_free_cgc_io_l1clk; // @[el2_dma_ctrl.scala 447:28]
+  wire  dma_free_cgc_io_clk; // @[el2_dma_ctrl.scala 447:28]
+  wire  dma_free_cgc_io_en; // @[el2_dma_ctrl.scala 447:28]
+  wire  dma_free_cgc_io_scan_mode; // @[el2_dma_ctrl.scala 447:28]
+  wire  dma_bus_cgc_io_l1clk; // @[el2_dma_ctrl.scala 453:27]
+  wire  dma_bus_cgc_io_clk; // @[el2_dma_ctrl.scala 453:27]
+  wire  dma_bus_cgc_io_en; // @[el2_dma_ctrl.scala 453:27]
+  wire  dma_bus_cgc_io_scan_mode; // @[el2_dma_ctrl.scala 453:27]
+  wire  rvclkhdr_10_io_l1clk; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_10_io_clk; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_10_io_en; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_11_io_l1clk; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_11_io_clk; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_11_io_en; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_12_io_l1clk; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_12_io_clk; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_12_io_en; // @[el2_lib.scala 508:23]
+  wire  rvclkhdr_12_io_scan_mode; // @[el2_lib.scala 508:23]
+  wire  dma_free_clk = dma_free_cgc_io_l1clk; // @[el2_dma_ctrl.scala 226:26 el2_dma_ctrl.scala 451:29]
+  reg [2:0] RdPtr; // @[Reg.scala 27:20]
+  reg [31:0] fifo_addr_4; // @[el2_lib.scala 514:16]
+  reg [31:0] fifo_addr_3; // @[el2_lib.scala 514:16]
+  reg [31:0] fifo_addr_2; // @[el2_lib.scala 514:16]
+  reg [31:0] fifo_addr_1; // @[el2_lib.scala 514:16]
+  reg [31:0] fifo_addr_0; // @[el2_lib.scala 514:16]
+  wire [31:0] _GEN_60 = 3'h1 == RdPtr ? fifo_addr_1 : fifo_addr_0; // @[el2_dma_ctrl.scala 407:20]
+  wire [31:0] _GEN_61 = 3'h2 == RdPtr ? fifo_addr_2 : _GEN_60; // @[el2_dma_ctrl.scala 407:20]
+  wire [31:0] _GEN_62 = 3'h3 == RdPtr ? fifo_addr_3 : _GEN_61; // @[el2_dma_ctrl.scala 407:20]
+  wire [31:0] dma_mem_addr_int = 3'h4 == RdPtr ? fifo_addr_4 : _GEN_62; // @[el2_dma_ctrl.scala 407:20]
+  wire  dma_mem_addr_in_dccm = dma_mem_addr_int[31:16] == 16'hf004; // @[el2_lib.scala 501:39]
+  wire  dma_mem_addr_in_pic = dma_mem_addr_int[31:15] == 17'h1e018; // @[el2_lib.scala 501:39]
+  wire  dma_mem_addr_in_iccm = dma_mem_addr_int[31:16] == 16'hee00; // @[el2_lib.scala 501:39]
+  wire  dma_bus_clk = dma_bus_cgc_io_l1clk; // @[el2_dma_ctrl.scala 228:25 el2_dma_ctrl.scala 457:28]
+  reg  wrbuf_vld; // @[el2_dma_ctrl.scala 467:59]
+  reg  wrbuf_data_vld; // @[el2_dma_ctrl.scala 469:59]
+  wire  _T_1240 = wrbuf_vld & wrbuf_data_vld; // @[el2_dma_ctrl.scala 525:43]
+  reg  rdbuf_vld; // @[el2_dma_ctrl.scala 493:47]
+  wire  _T_1241 = _T_1240 & rdbuf_vld; // @[el2_dma_ctrl.scala 525:60]
+  reg  axi_mstr_priority; // @[Reg.scala 27:20]
+  wire  axi_mstr_sel = _T_1241 ? axi_mstr_priority : _T_1240; // @[el2_dma_ctrl.scala 525:31]
+  reg [31:0] wrbuf_addr; // @[el2_lib.scala 514:16]
+  reg [31:0] rdbuf_addr; // @[el2_lib.scala 514:16]
+  wire [31:0] bus_cmd_addr = axi_mstr_sel ? wrbuf_addr : rdbuf_addr; // @[el2_dma_ctrl.scala 515:43]
+  wire [2:0] _GEN_90 = {{2'd0}, io_dbg_cmd_addr[2]}; // @[el2_dma_ctrl.scala 253:76]
+  wire [3:0] _T_17 = 3'h4 * _GEN_90; // @[el2_dma_ctrl.scala 253:76]
+  wire [18:0] _T_18 = 19'hf << _T_17; // @[el2_dma_ctrl.scala 253:68]
+  reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20]
+  wire [18:0] _T_20 = io_dbg_cmd_valid ? _T_18 : {{11'd0}, wrbuf_byteen}; // @[el2_dma_ctrl.scala 253:34]
+  wire [2:0] _T_23 = {1'h0,io_dbg_cmd_size}; // @[Cat.scala 29:58]
+  reg [2:0] wrbuf_sz; // @[Reg.scala 27:20]
+  reg [2:0] rdbuf_sz; // @[Reg.scala 27:20]
+  wire [2:0] bus_cmd_sz = axi_mstr_sel ? wrbuf_sz : rdbuf_sz; // @[el2_dma_ctrl.scala 516:45]
+  wire [2:0] fifo_sz_in = io_dbg_cmd_valid ? _T_23 : bus_cmd_sz; // @[el2_dma_ctrl.scala 255:33]
+  wire  fifo_write_in = io_dbg_cmd_valid ? io_dbg_cmd_write : axi_mstr_sel; // @[el2_dma_ctrl.scala 257:33]
+  wire  bus_cmd_valid = _T_1240 | rdbuf_vld; // @[el2_dma_ctrl.scala 511:69]
+  reg  fifo_full; // @[el2_dma_ctrl.scala 425:12]
+  reg  dbg_dma_bubble_bus; // @[el2_dma_ctrl.scala 429:12]
+  wire  _T_989 = fifo_full | dbg_dma_bubble_bus; // @[el2_dma_ctrl.scala 357:39]
+  wire  dma_fifo_ready = ~_T_989; // @[el2_dma_ctrl.scala 357:27]
+  wire  axi_mstr_prty_en = bus_cmd_valid & dma_fifo_ready; // @[el2_dma_ctrl.scala 512:54]
+  wire  _T_28 = axi_mstr_prty_en & io_dma_bus_clk_en; // @[el2_dma_ctrl.scala 264:80]
+  wire  _T_31 = io_dbg_cmd_valid & io_dbg_cmd_type[1]; // @[el2_dma_ctrl.scala 264:121]
+  wire  _T_32 = _T_28 | _T_31; // @[el2_dma_ctrl.scala 264:101]
+  reg [2:0] WrPtr; // @[Reg.scala 27:20]
+  wire  _T_33 = 3'h0 == WrPtr; // @[el2_dma_ctrl.scala 264:158]
+  wire  _T_34 = _T_32 & _T_33; // @[el2_dma_ctrl.scala 264:151]
+  wire  _T_41 = 3'h1 == WrPtr; // @[el2_dma_ctrl.scala 264:158]
+  wire  _T_42 = _T_32 & _T_41; // @[el2_dma_ctrl.scala 264:151]
+  wire  _T_49 = 3'h2 == WrPtr; // @[el2_dma_ctrl.scala 264:158]
+  wire  _T_50 = _T_32 & _T_49; // @[el2_dma_ctrl.scala 264:151]
+  wire  _T_57 = 3'h3 == WrPtr; // @[el2_dma_ctrl.scala 264:158]
+  wire  _T_58 = _T_32 & _T_57; // @[el2_dma_ctrl.scala 264:151]
+  wire  _T_65 = 3'h4 == WrPtr; // @[el2_dma_ctrl.scala 264:158]
+  wire  _T_66 = _T_32 & _T_65; // @[el2_dma_ctrl.scala 264:151]
+  wire [4:0] fifo_cmd_en = {_T_66,_T_58,_T_50,_T_42,_T_34}; // @[Cat.scala 29:58]
+  wire  _T_71 = axi_mstr_prty_en & fifo_write_in; // @[el2_dma_ctrl.scala 266:73]
+  wire  _T_72 = _T_71 & io_dma_bus_clk_en; // @[el2_dma_ctrl.scala 266:89]
+  wire  _T_75 = _T_31 & io_dbg_cmd_write; // @[el2_dma_ctrl.scala 266:151]
+  wire  _T_76 = _T_72 | _T_75; // @[el2_dma_ctrl.scala 266:110]
+  wire  _T_78 = _T_76 & _T_33; // @[el2_dma_ctrl.scala 266:172]
+  reg  _T_598; // @[el2_dma_ctrl.scala 284:82]
+  reg  _T_591; // @[el2_dma_ctrl.scala 284:82]
+  reg  _T_584; // @[el2_dma_ctrl.scala 284:82]
+  reg  _T_577; // @[el2_dma_ctrl.scala 284:82]
+  reg  _T_570; // @[el2_dma_ctrl.scala 284:82]
+  wire [4:0] fifo_valid = {_T_598,_T_591,_T_584,_T_577,_T_570}; // @[Cat.scala 29:58]
+  wire [4:0] _T_990 = fifo_valid >> RdPtr; // @[el2_dma_ctrl.scala 361:38]
+  reg  _T_760; // @[el2_dma_ctrl.scala 292:89]
+  reg  _T_753; // @[el2_dma_ctrl.scala 292:89]
+  reg  _T_746; // @[el2_dma_ctrl.scala 292:89]
+  reg  _T_739; // @[el2_dma_ctrl.scala 292:89]
+  reg  _T_732; // @[el2_dma_ctrl.scala 292:89]
+  wire [4:0] fifo_done = {_T_760,_T_753,_T_746,_T_739,_T_732}; // @[Cat.scala 29:58]
+  wire [4:0] _T_992 = fifo_done >> RdPtr; // @[el2_dma_ctrl.scala 361:58]
+  wire  _T_994 = ~_T_992[0]; // @[el2_dma_ctrl.scala 361:48]
+  wire  _T_995 = _T_990[0] & _T_994; // @[el2_dma_ctrl.scala 361:46]
+  wire  dma_buffer_c1_clk = dma_buffer_c1cgc_io_l1clk; // @[el2_dma_ctrl.scala 230:31 el2_dma_ctrl.scala 445:33]
+  reg  _T_886; // @[Reg.scala 27:20]
+  reg  _T_884; // @[Reg.scala 27:20]
+  reg  _T_882; // @[Reg.scala 27:20]
+  reg  _T_880; // @[Reg.scala 27:20]
+  reg  _T_878; // @[Reg.scala 27:20]
+  wire [4:0] fifo_dbg = {_T_886,_T_884,_T_882,_T_880,_T_878}; // @[Cat.scala 29:58]
+  wire [4:0] _T_996 = fifo_dbg >> RdPtr; // @[el2_dma_ctrl.scala 361:77]
+  wire  _T_998 = ~_T_996[0]; // @[el2_dma_ctrl.scala 361:68]
+  wire  _T_999 = _T_995 & _T_998; // @[el2_dma_ctrl.scala 361:66]
+  wire  _T_1000 = dma_mem_addr_in_dccm | dma_mem_addr_in_iccm; // @[el2_dma_ctrl.scala 361:111]
+  wire  _T_1001 = ~_T_1000; // @[el2_dma_ctrl.scala 361:88]
+  wire  dma_address_error = _T_999 & _T_1001; // @[el2_dma_ctrl.scala 361:85]
+  wire  _T_1009 = ~dma_address_error; // @[el2_dma_ctrl.scala 362:68]
+  wire  _T_1010 = _T_995 & _T_1009; // @[el2_dma_ctrl.scala 362:66]
+  reg [2:0] fifo_sz_4; // @[Reg.scala 27:20]
+  reg [2:0] fifo_sz_3; // @[Reg.scala 27:20]
+  reg [2:0] fifo_sz_2; // @[Reg.scala 27:20]
+  reg [2:0] fifo_sz_1; // @[Reg.scala 27:20]
+  reg [2:0] fifo_sz_0; // @[Reg.scala 27:20]
+  wire [2:0] _GEN_65 = 3'h1 == RdPtr ? fifo_sz_1 : fifo_sz_0; // @[el2_dma_ctrl.scala 408:20]
+  wire [2:0] _GEN_66 = 3'h2 == RdPtr ? fifo_sz_2 : _GEN_65; // @[el2_dma_ctrl.scala 408:20]
+  wire [2:0] _GEN_67 = 3'h3 == RdPtr ? fifo_sz_3 : _GEN_66; // @[el2_dma_ctrl.scala 408:20]
+  wire [2:0] dma_mem_sz_int = 3'h4 == RdPtr ? fifo_sz_4 : _GEN_67; // @[el2_dma_ctrl.scala 408:20]
+  wire  _T_1012 = dma_mem_sz_int == 3'h1; // @[el2_dma_ctrl.scala 363:28]
+  wire  _T_1014 = _T_1012 & dma_mem_addr_int[0]; // @[el2_dma_ctrl.scala 363:37]
+  wire  _T_1016 = dma_mem_sz_int == 3'h2; // @[el2_dma_ctrl.scala 364:29]
+  wire  _T_1018 = |dma_mem_addr_int[1:0]; // @[el2_dma_ctrl.scala 364:64]
+  wire  _T_1019 = _T_1016 & _T_1018; // @[el2_dma_ctrl.scala 364:38]
+  wire  _T_1020 = _T_1014 | _T_1019; // @[el2_dma_ctrl.scala 363:60]
+  wire  _T_1022 = dma_mem_sz_int == 3'h3; // @[el2_dma_ctrl.scala 365:29]
+  wire  _T_1024 = |dma_mem_addr_int[2:0]; // @[el2_dma_ctrl.scala 365:64]
+  wire  _T_1025 = _T_1022 & _T_1024; // @[el2_dma_ctrl.scala 365:38]
+  wire  _T_1026 = _T_1020 | _T_1025; // @[el2_dma_ctrl.scala 364:70]
+  wire  _T_1028 = dma_mem_sz_int[1:0] == 2'h2; // @[el2_dma_ctrl.scala 366:55]
+  wire  _T_1030 = dma_mem_sz_int[1:0] == 2'h3; // @[el2_dma_ctrl.scala 366:88]
+  wire  _T_1031 = _T_1028 | _T_1030; // @[el2_dma_ctrl.scala 366:64]
+  wire  _T_1032 = ~_T_1031; // @[el2_dma_ctrl.scala 366:31]
+  wire  _T_1033 = dma_mem_addr_in_iccm & _T_1032; // @[el2_dma_ctrl.scala 366:29]
+  wire  _T_1034 = _T_1026 | _T_1033; // @[el2_dma_ctrl.scala 365:70]
+  wire  _T_1035 = dma_mem_addr_in_dccm & io_dma_mem_write; // @[el2_dma_ctrl.scala 367:29]
+  wire  _T_1042 = _T_1035 & _T_1032; // @[el2_dma_ctrl.scala 367:48]
+  wire  _T_1043 = _T_1034 | _T_1042; // @[el2_dma_ctrl.scala 366:108]
+  wire  _T_1046 = io_dma_mem_write & _T_1016; // @[el2_dma_ctrl.scala 368:25]
+  wire  _T_1048 = dma_mem_addr_int[2:0] == 3'h0; // @[el2_dma_ctrl.scala 368:94]
+  reg [7:0] fifo_byteen_4; // @[Reg.scala 27:20]
+  reg [7:0] fifo_byteen_3; // @[Reg.scala 27:20]
+  reg [7:0] fifo_byteen_2; // @[Reg.scala 27:20]
+  reg [7:0] fifo_byteen_1; // @[Reg.scala 27:20]
+  reg [7:0] fifo_byteen_0; // @[Reg.scala 27:20]
+  wire [7:0] _GEN_70 = 3'h1 == RdPtr ? fifo_byteen_1 : fifo_byteen_0; // @[el2_dma_ctrl.scala 411:20]
+  wire [7:0] _GEN_71 = 3'h2 == RdPtr ? fifo_byteen_2 : _GEN_70; // @[el2_dma_ctrl.scala 411:20]
+  wire [7:0] _GEN_72 = 3'h3 == RdPtr ? fifo_byteen_3 : _GEN_71; // @[el2_dma_ctrl.scala 411:20]
+  wire [7:0] dma_mem_byteen = 3'h4 == RdPtr ? fifo_byteen_4 : _GEN_72; // @[el2_dma_ctrl.scala 411:20]
+  wire [3:0] _T_1059 = _T_1048 ? dma_mem_byteen[3:0] : 4'h0; // @[Mux.scala 27:72]
+  wire  _T_1051 = dma_mem_addr_int[2:0] == 3'h1; // @[el2_dma_ctrl.scala 369:32]
+  wire [3:0] _T_1060 = _T_1051 ? dma_mem_byteen[4:1] : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_1063 = _T_1059 | _T_1060; // @[Mux.scala 27:72]
+  wire  _T_1054 = dma_mem_addr_int[2:0] == 3'h2; // @[el2_dma_ctrl.scala 370:32]
+  wire [3:0] _T_1061 = _T_1054 ? dma_mem_byteen[5:2] : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_1064 = _T_1063 | _T_1061; // @[Mux.scala 27:72]
+  wire  _T_1057 = dma_mem_addr_int[2:0] == 3'h3; // @[el2_dma_ctrl.scala 371:32]
+  wire [3:0] _T_1062 = _T_1057 ? dma_mem_byteen[6:3] : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_1065 = _T_1064 | _T_1062; // @[Mux.scala 27:72]
+  wire  _T_1067 = _T_1065 != 4'hf; // @[el2_dma_ctrl.scala 371:68]
+  wire  _T_1068 = _T_1046 & _T_1067; // @[el2_dma_ctrl.scala 368:58]
+  wire  _T_1069 = _T_1043 | _T_1068; // @[el2_dma_ctrl.scala 367:125]
+  wire  _T_1072 = io_dma_mem_write & _T_1022; // @[el2_dma_ctrl.scala 372:25]
+  wire  _T_1074 = dma_mem_byteen == 8'hf; // @[el2_dma_ctrl.scala 372:83]
+  wire  _T_1076 = dma_mem_byteen == 8'hf0; // @[el2_dma_ctrl.scala 372:119]
+  wire  _T_1077 = _T_1074 | _T_1076; // @[el2_dma_ctrl.scala 372:96]
+  wire  _T_1079 = dma_mem_byteen == 8'hff; // @[el2_dma_ctrl.scala 372:155]
+  wire  _T_1080 = _T_1077 | _T_1079; // @[el2_dma_ctrl.scala 372:132]
+  wire  _T_1081 = ~_T_1080; // @[el2_dma_ctrl.scala 372:60]
+  wire  _T_1082 = _T_1072 & _T_1081; // @[el2_dma_ctrl.scala 372:58]
+  wire  _T_1083 = _T_1069 | _T_1082; // @[el2_dma_ctrl.scala 371:79]
+  wire  dma_alignment_error = _T_1010 & _T_1083; // @[el2_dma_ctrl.scala 362:87]
+  wire  _T_79 = dma_address_error | dma_alignment_error; // @[el2_dma_ctrl.scala 266:213]
+  wire  _T_80 = 3'h0 == RdPtr; // @[el2_dma_ctrl.scala 266:243]
+  wire  _T_81 = _T_79 & _T_80; // @[el2_dma_ctrl.scala 266:236]
+  wire  _T_82 = _T_78 | _T_81; // @[el2_dma_ctrl.scala 266:191]
+  wire  _T_83 = 3'h0 == io_dccm_dma_rtag; // @[el2_dma_ctrl.scala 266:284]
+  wire  _T_84 = io_dccm_dma_rvalid & _T_83; // @[el2_dma_ctrl.scala 266:277]
+  wire  _T_85 = _T_82 | _T_84; // @[el2_dma_ctrl.scala 266:255]
+  wire  _T_86 = 3'h0 == io_iccm_dma_rtag; // @[el2_dma_ctrl.scala 266:336]
+  wire  _T_87 = io_iccm_dma_rvalid & _T_86; // @[el2_dma_ctrl.scala 266:329]
+  wire  _T_88 = _T_85 | _T_87; // @[el2_dma_ctrl.scala 266:307]
+  wire  _T_96 = _T_76 & _T_41; // @[el2_dma_ctrl.scala 266:172]
+  wire  _T_98 = 3'h1 == RdPtr; // @[el2_dma_ctrl.scala 266:243]
+  wire  _T_99 = _T_79 & _T_98; // @[el2_dma_ctrl.scala 266:236]
+  wire  _T_100 = _T_96 | _T_99; // @[el2_dma_ctrl.scala 266:191]
+  wire  _T_101 = 3'h1 == io_dccm_dma_rtag; // @[el2_dma_ctrl.scala 266:284]
+  wire  _T_102 = io_dccm_dma_rvalid & _T_101; // @[el2_dma_ctrl.scala 266:277]
+  wire  _T_103 = _T_100 | _T_102; // @[el2_dma_ctrl.scala 266:255]
+  wire  _T_104 = 3'h1 == io_iccm_dma_rtag; // @[el2_dma_ctrl.scala 266:336]
+  wire  _T_105 = io_iccm_dma_rvalid & _T_104; // @[el2_dma_ctrl.scala 266:329]
+  wire  _T_106 = _T_103 | _T_105; // @[el2_dma_ctrl.scala 266:307]
+  wire  _T_114 = _T_76 & _T_49; // @[el2_dma_ctrl.scala 266:172]
+  wire  _T_116 = 3'h2 == RdPtr; // @[el2_dma_ctrl.scala 266:243]
+  wire  _T_117 = _T_79 & _T_116; // @[el2_dma_ctrl.scala 266:236]
+  wire  _T_118 = _T_114 | _T_117; // @[el2_dma_ctrl.scala 266:191]
+  wire  _T_119 = 3'h2 == io_dccm_dma_rtag; // @[el2_dma_ctrl.scala 266:284]
+  wire  _T_120 = io_dccm_dma_rvalid & _T_119; // @[el2_dma_ctrl.scala 266:277]
+  wire  _T_121 = _T_118 | _T_120; // @[el2_dma_ctrl.scala 266:255]
+  wire  _T_122 = 3'h2 == io_iccm_dma_rtag; // @[el2_dma_ctrl.scala 266:336]
+  wire  _T_123 = io_iccm_dma_rvalid & _T_122; // @[el2_dma_ctrl.scala 266:329]
+  wire  _T_124 = _T_121 | _T_123; // @[el2_dma_ctrl.scala 266:307]
+  wire  _T_132 = _T_76 & _T_57; // @[el2_dma_ctrl.scala 266:172]
+  wire  _T_134 = 3'h3 == RdPtr; // @[el2_dma_ctrl.scala 266:243]
+  wire  _T_135 = _T_79 & _T_134; // @[el2_dma_ctrl.scala 266:236]
+  wire  _T_136 = _T_132 | _T_135; // @[el2_dma_ctrl.scala 266:191]
+  wire  _T_137 = 3'h3 == io_dccm_dma_rtag; // @[el2_dma_ctrl.scala 266:284]
+  wire  _T_138 = io_dccm_dma_rvalid & _T_137; // @[el2_dma_ctrl.scala 266:277]
+  wire  _T_139 = _T_136 | _T_138; // @[el2_dma_ctrl.scala 266:255]
+  wire  _T_140 = 3'h3 == io_iccm_dma_rtag; // @[el2_dma_ctrl.scala 266:336]
+  wire  _T_141 = io_iccm_dma_rvalid & _T_140; // @[el2_dma_ctrl.scala 266:329]
+  wire  _T_142 = _T_139 | _T_141; // @[el2_dma_ctrl.scala 266:307]
+  wire  _T_150 = _T_76 & _T_65; // @[el2_dma_ctrl.scala 266:172]
+  wire  _T_152 = 3'h4 == RdPtr; // @[el2_dma_ctrl.scala 266:243]
+  wire  _T_153 = _T_79 & _T_152; // @[el2_dma_ctrl.scala 266:236]
+  wire  _T_154 = _T_150 | _T_153; // @[el2_dma_ctrl.scala 266:191]
+  wire  _T_155 = 3'h4 == io_dccm_dma_rtag; // @[el2_dma_ctrl.scala 266:284]
+  wire  _T_156 = io_dccm_dma_rvalid & _T_155; // @[el2_dma_ctrl.scala 266:277]
+  wire  _T_157 = _T_154 | _T_156; // @[el2_dma_ctrl.scala 266:255]
+  wire  _T_158 = 3'h4 == io_iccm_dma_rtag; // @[el2_dma_ctrl.scala 266:336]
+  wire  _T_159 = io_iccm_dma_rvalid & _T_158; // @[el2_dma_ctrl.scala 266:329]
+  wire  _T_160 = _T_157 | _T_159; // @[el2_dma_ctrl.scala 266:307]
+  wire [4:0] fifo_data_en = {_T_160,_T_142,_T_124,_T_106,_T_88}; // @[Cat.scala 29:58]
+  wire  _T_165 = io_dma_dccm_req | io_dma_iccm_req; // @[el2_dma_ctrl.scala 268:75]
+  wire  _T_166 = ~io_dma_mem_write; // @[el2_dma_ctrl.scala 268:96]
+  wire  _T_167 = _T_165 & _T_166; // @[el2_dma_ctrl.scala 268:94]
+  wire  _T_169 = _T_167 & _T_80; // @[el2_dma_ctrl.scala 268:114]
+  wire  _T_174 = _T_167 & _T_98; // @[el2_dma_ctrl.scala 268:114]
+  wire  _T_179 = _T_167 & _T_116; // @[el2_dma_ctrl.scala 268:114]
+  wire  _T_184 = _T_167 & _T_134; // @[el2_dma_ctrl.scala 268:114]
+  wire  _T_189 = _T_167 & _T_152; // @[el2_dma_ctrl.scala 268:114]
+  wire [4:0] fifo_pend_en = {_T_189,_T_184,_T_179,_T_174,_T_169}; // @[Cat.scala 29:58]
+  wire  _T_1107 = _T_995 & _T_996[0]; // @[el2_dma_ctrl.scala 381:66]
+  wire  _T_1109 = _T_1000 | dma_mem_addr_in_pic; // @[el2_dma_ctrl.scala 381:134]
+  wire  _T_1110 = ~_T_1109; // @[el2_dma_ctrl.scala 381:88]
+  wire  _T_1113 = dma_mem_sz_int[1:0] != 2'h2; // @[el2_dma_ctrl.scala 381:191]
+  wire  _T_1114 = _T_1110 | _T_1113; // @[el2_dma_ctrl.scala 381:167]
+  wire  dma_dbg_cmd_error = _T_1107 & _T_1114; // @[el2_dma_ctrl.scala 381:84]
+  wire  _T_197 = _T_79 | dma_dbg_cmd_error; // @[el2_dma_ctrl.scala 270:114]
+  wire  _T_199 = _T_197 & _T_80; // @[el2_dma_ctrl.scala 270:135]
+  wire  _T_200 = io_dccm_dma_rvalid & io_dccm_dma_ecc_error; // @[el2_dma_ctrl.scala 270:177]
+  wire  _T_202 = _T_200 & _T_83; // @[el2_dma_ctrl.scala 270:202]
+  wire  _T_203 = _T_199 | _T_202; // @[el2_dma_ctrl.scala 270:154]
+  wire  _T_204 = io_iccm_dma_rvalid & io_iccm_dma_ecc_error; // @[el2_dma_ctrl.scala 270:255]
+  wire  _T_206 = _T_204 & _T_86; // @[el2_dma_ctrl.scala 270:280]
+  wire  _T_207 = _T_203 | _T_206; // @[el2_dma_ctrl.scala 270:232]
+  wire  _T_213 = _T_197 & _T_98; // @[el2_dma_ctrl.scala 270:135]
+  wire  _T_216 = _T_200 & _T_101; // @[el2_dma_ctrl.scala 270:202]
+  wire  _T_217 = _T_213 | _T_216; // @[el2_dma_ctrl.scala 270:154]
+  wire  _T_220 = _T_204 & _T_104; // @[el2_dma_ctrl.scala 270:280]
+  wire  _T_221 = _T_217 | _T_220; // @[el2_dma_ctrl.scala 270:232]
+  wire  _T_227 = _T_197 & _T_116; // @[el2_dma_ctrl.scala 270:135]
+  wire  _T_230 = _T_200 & _T_119; // @[el2_dma_ctrl.scala 270:202]
+  wire  _T_231 = _T_227 | _T_230; // @[el2_dma_ctrl.scala 270:154]
+  wire  _T_234 = _T_204 & _T_122; // @[el2_dma_ctrl.scala 270:280]
+  wire  _T_235 = _T_231 | _T_234; // @[el2_dma_ctrl.scala 270:232]
+  wire  _T_241 = _T_197 & _T_134; // @[el2_dma_ctrl.scala 270:135]
+  wire  _T_244 = _T_200 & _T_137; // @[el2_dma_ctrl.scala 270:202]
+  wire  _T_245 = _T_241 | _T_244; // @[el2_dma_ctrl.scala 270:154]
+  wire  _T_248 = _T_204 & _T_140; // @[el2_dma_ctrl.scala 270:280]
+  wire  _T_249 = _T_245 | _T_248; // @[el2_dma_ctrl.scala 270:232]
+  wire  _T_255 = _T_197 & _T_152; // @[el2_dma_ctrl.scala 270:135]
+  wire  _T_258 = _T_200 & _T_155; // @[el2_dma_ctrl.scala 270:202]
+  wire  _T_259 = _T_255 | _T_258; // @[el2_dma_ctrl.scala 270:154]
+  wire  _T_262 = _T_204 & _T_158; // @[el2_dma_ctrl.scala 270:280]
+  wire  _T_263 = _T_259 | _T_262; // @[el2_dma_ctrl.scala 270:232]
+  wire [4:0] fifo_error_en = {_T_263,_T_249,_T_235,_T_221,_T_207}; // @[Cat.scala 29:58]
+  wire [1:0] _T_436 = {1'h0,io_dccm_dma_ecc_error}; // @[Cat.scala 29:58]
+  wire [1:0] _T_439 = {1'h0,io_iccm_dma_ecc_error}; // @[Cat.scala 29:58]
+  wire [1:0] _T_442 = {_T_197,dma_alignment_error}; // @[Cat.scala 29:58]
+  wire [1:0] _T_443 = _T_87 ? _T_439 : _T_442; // @[el2_dma_ctrl.scala 280:146]
+  wire [1:0] fifo_error_in_0 = _T_84 ? _T_436 : _T_443; // @[el2_dma_ctrl.scala 280:60]
+  wire  _T_269 = |fifo_error_in_0; // @[el2_dma_ctrl.scala 272:83]
+  reg [1:0] fifo_error_0; // @[el2_dma_ctrl.scala 286:85]
+  wire  _T_272 = |fifo_error_0; // @[el2_dma_ctrl.scala 272:125]
+  wire [1:0] _T_454 = _T_105 ? _T_439 : _T_442; // @[el2_dma_ctrl.scala 280:146]
+  wire [1:0] fifo_error_in_1 = _T_102 ? _T_436 : _T_454; // @[el2_dma_ctrl.scala 280:60]
+  wire  _T_276 = |fifo_error_in_1; // @[el2_dma_ctrl.scala 272:83]
+  reg [1:0] fifo_error_1; // @[el2_dma_ctrl.scala 286:85]
+  wire  _T_279 = |fifo_error_1; // @[el2_dma_ctrl.scala 272:125]
+  wire [1:0] _T_465 = _T_123 ? _T_439 : _T_442; // @[el2_dma_ctrl.scala 280:146]
+  wire [1:0] fifo_error_in_2 = _T_120 ? _T_436 : _T_465; // @[el2_dma_ctrl.scala 280:60]
+  wire  _T_283 = |fifo_error_in_2; // @[el2_dma_ctrl.scala 272:83]
+  reg [1:0] fifo_error_2; // @[el2_dma_ctrl.scala 286:85]
+  wire  _T_286 = |fifo_error_2; // @[el2_dma_ctrl.scala 272:125]
+  wire [1:0] _T_476 = _T_141 ? _T_439 : _T_442; // @[el2_dma_ctrl.scala 280:146]
+  wire [1:0] fifo_error_in_3 = _T_138 ? _T_436 : _T_476; // @[el2_dma_ctrl.scala 280:60]
+  wire  _T_290 = |fifo_error_in_3; // @[el2_dma_ctrl.scala 272:83]
+  reg [1:0] fifo_error_3; // @[el2_dma_ctrl.scala 286:85]
+  wire  _T_293 = |fifo_error_3; // @[el2_dma_ctrl.scala 272:125]
+  wire [1:0] _T_487 = _T_159 ? _T_439 : _T_442; // @[el2_dma_ctrl.scala 280:146]
+  wire [1:0] fifo_error_in_4 = _T_156 ? _T_436 : _T_487; // @[el2_dma_ctrl.scala 280:60]
+  wire  _T_297 = |fifo_error_in_4; // @[el2_dma_ctrl.scala 272:83]
+  reg [1:0] fifo_error_4; // @[el2_dma_ctrl.scala 286:85]
+  wire  _T_300 = |fifo_error_4; // @[el2_dma_ctrl.scala 272:125]
+  wire  _T_309 = _T_272 | fifo_error_en[0]; // @[el2_dma_ctrl.scala 274:78]
+  wire  _T_311 = _T_165 & io_dma_mem_write; // @[el2_dma_ctrl.scala 274:136]
+  wire  _T_312 = _T_309 | _T_311; // @[el2_dma_ctrl.scala 274:97]
+  wire  _T_314 = _T_312 & _T_80; // @[el2_dma_ctrl.scala 274:157]
+  wire  _T_317 = _T_314 | _T_84; // @[el2_dma_ctrl.scala 274:176]
+  wire  _T_320 = _T_317 | _T_87; // @[el2_dma_ctrl.scala 274:228]
+  wire  _T_323 = _T_279 | fifo_error_en[1]; // @[el2_dma_ctrl.scala 274:78]
+  wire  _T_326 = _T_323 | _T_311; // @[el2_dma_ctrl.scala 274:97]
+  wire  _T_328 = _T_326 & _T_98; // @[el2_dma_ctrl.scala 274:157]
+  wire  _T_331 = _T_328 | _T_102; // @[el2_dma_ctrl.scala 274:176]
+  wire  _T_334 = _T_331 | _T_105; // @[el2_dma_ctrl.scala 274:228]
+  wire  _T_337 = _T_286 | fifo_error_en[2]; // @[el2_dma_ctrl.scala 274:78]
+  wire  _T_340 = _T_337 | _T_311; // @[el2_dma_ctrl.scala 274:97]
+  wire  _T_342 = _T_340 & _T_116; // @[el2_dma_ctrl.scala 274:157]
+  wire  _T_345 = _T_342 | _T_120; // @[el2_dma_ctrl.scala 274:176]
+  wire  _T_348 = _T_345 | _T_123; // @[el2_dma_ctrl.scala 274:228]
+  wire  _T_351 = _T_293 | fifo_error_en[3]; // @[el2_dma_ctrl.scala 274:78]
+  wire  _T_354 = _T_351 | _T_311; // @[el2_dma_ctrl.scala 274:97]
+  wire  _T_356 = _T_354 & _T_134; // @[el2_dma_ctrl.scala 274:157]
+  wire  _T_359 = _T_356 | _T_138; // @[el2_dma_ctrl.scala 274:176]
+  wire  _T_362 = _T_359 | _T_141; // @[el2_dma_ctrl.scala 274:228]
+  wire  _T_365 = _T_300 | fifo_error_en[4]; // @[el2_dma_ctrl.scala 274:78]
+  wire  _T_368 = _T_365 | _T_311; // @[el2_dma_ctrl.scala 274:97]
+  wire  _T_370 = _T_368 & _T_152; // @[el2_dma_ctrl.scala 274:157]
+  wire  _T_373 = _T_370 | _T_156; // @[el2_dma_ctrl.scala 274:176]
+  wire  _T_376 = _T_373 | _T_159; // @[el2_dma_ctrl.scala 274:228]
+  wire [4:0] fifo_done_en = {_T_376,_T_362,_T_348,_T_334,_T_320}; // @[Cat.scala 29:58]
+  wire  _T_383 = fifo_done_en[0] | fifo_done[0]; // @[el2_dma_ctrl.scala 276:75]
+  wire  _T_384 = _T_383 & io_dma_bus_clk_en; // @[el2_dma_ctrl.scala 276:91]
+  wire  _T_387 = fifo_done_en[1] | fifo_done[1]; // @[el2_dma_ctrl.scala 276:75]
+  wire  _T_388 = _T_387 & io_dma_bus_clk_en; // @[el2_dma_ctrl.scala 276:91]
+  wire  _T_391 = fifo_done_en[2] | fifo_done[2]; // @[el2_dma_ctrl.scala 276:75]
+  wire  _T_392 = _T_391 & io_dma_bus_clk_en; // @[el2_dma_ctrl.scala 276:91]
+  wire  _T_395 = fifo_done_en[3] | fifo_done[3]; // @[el2_dma_ctrl.scala 276:75]
+  wire  _T_396 = _T_395 & io_dma_bus_clk_en; // @[el2_dma_ctrl.scala 276:91]
+  wire  _T_399 = fifo_done_en[4] | fifo_done[4]; // @[el2_dma_ctrl.scala 276:75]
+  wire  _T_400 = _T_399 & io_dma_bus_clk_en; // @[el2_dma_ctrl.scala 276:91]
+  wire [4:0] fifo_done_bus_en = {_T_400,_T_396,_T_392,_T_388,_T_384}; // @[Cat.scala 29:58]
+  wire  _T_1265 = io_dma_axi_bvalid & io_dma_axi_bready; // @[el2_dma_ctrl.scala 554:60]
+  wire  _T_1266 = io_dma_axi_rvalid & io_dma_axi_rready; // @[el2_dma_ctrl.scala 554:102]
+  wire  bus_rsp_sent = _T_1265 | _T_1266; // @[el2_dma_ctrl.scala 554:81]
+  wire  _T_406 = bus_rsp_sent & io_dma_bus_clk_en; // @[el2_dma_ctrl.scala 278:99]
+  wire  _T_407 = _T_406 | io_dma_dbg_cmd_done; // @[el2_dma_ctrl.scala 278:120]
+  reg [2:0] RspPtr; // @[Reg.scala 27:20]
+  wire  _T_408 = 3'h0 == RspPtr; // @[el2_dma_ctrl.scala 278:150]
+  wire  _T_409 = _T_407 & _T_408; // @[el2_dma_ctrl.scala 278:143]
+  wire  _T_413 = 3'h1 == RspPtr; // @[el2_dma_ctrl.scala 278:150]
+  wire  _T_414 = _T_407 & _T_413; // @[el2_dma_ctrl.scala 278:143]
+  wire  _T_418 = 3'h2 == RspPtr; // @[el2_dma_ctrl.scala 278:150]
+  wire  _T_419 = _T_407 & _T_418; // @[el2_dma_ctrl.scala 278:143]
+  wire  _T_423 = 3'h3 == RspPtr; // @[el2_dma_ctrl.scala 278:150]
+  wire  _T_424 = _T_407 & _T_423; // @[el2_dma_ctrl.scala 278:143]
+  wire  _T_428 = 3'h4 == RspPtr; // @[el2_dma_ctrl.scala 278:150]
+  wire  _T_429 = _T_407 & _T_428; // @[el2_dma_ctrl.scala 278:143]
+  wire [4:0] fifo_reset = {_T_429,_T_424,_T_419,_T_414,_T_409}; // @[Cat.scala 29:58]
+  wire  _T_491 = fifo_error_en[0] & _T_269; // @[el2_dma_ctrl.scala 282:77]
+  wire [63:0] _T_493 = {32'h0,fifo_addr_0}; // @[Cat.scala 29:58]
+  wire [63:0] _T_498 = {io_dbg_cmd_wrdata,io_dbg_cmd_wrdata}; // @[Cat.scala 29:58]
+  reg [63:0] wrbuf_data; // @[el2_lib.scala 514:16]
+  wire [63:0] _T_500 = io_dbg_cmd_valid ? _T_498 : wrbuf_data; // @[el2_dma_ctrl.scala 282:284]
+  wire  _T_506 = fifo_error_en[1] & _T_276; // @[el2_dma_ctrl.scala 282:77]
+  wire [63:0] _T_508 = {32'h0,fifo_addr_1}; // @[Cat.scala 29:58]
+  wire  _T_521 = fifo_error_en[2] & _T_283; // @[el2_dma_ctrl.scala 282:77]
+  wire [63:0] _T_523 = {32'h0,fifo_addr_2}; // @[Cat.scala 29:58]
+  wire  _T_536 = fifo_error_en[3] & _T_290; // @[el2_dma_ctrl.scala 282:77]
+  wire [63:0] _T_538 = {32'h0,fifo_addr_3}; // @[Cat.scala 29:58]
+  wire  _T_551 = fifo_error_en[4] & _T_297; // @[el2_dma_ctrl.scala 282:77]
+  wire [63:0] _T_553 = {32'h0,fifo_addr_4}; // @[Cat.scala 29:58]
+  wire  _T_566 = fifo_cmd_en[0] | fifo_valid[0]; // @[el2_dma_ctrl.scala 284:86]
+  wire  _T_568 = ~fifo_reset[0]; // @[el2_dma_ctrl.scala 284:125]
+  wire  _T_573 = fifo_cmd_en[1] | fifo_valid[1]; // @[el2_dma_ctrl.scala 284:86]
+  wire  _T_575 = ~fifo_reset[1]; // @[el2_dma_ctrl.scala 284:125]
+  wire  _T_580 = fifo_cmd_en[2] | fifo_valid[2]; // @[el2_dma_ctrl.scala 284:86]
+  wire  _T_582 = ~fifo_reset[2]; // @[el2_dma_ctrl.scala 284:125]
+  wire  _T_587 = fifo_cmd_en[3] | fifo_valid[3]; // @[el2_dma_ctrl.scala 284:86]
+  wire  _T_589 = ~fifo_reset[3]; // @[el2_dma_ctrl.scala 284:125]
+  wire  _T_594 = fifo_cmd_en[4] | fifo_valid[4]; // @[el2_dma_ctrl.scala 284:86]
+  wire  _T_596 = ~fifo_reset[4]; // @[el2_dma_ctrl.scala 284:125]
+  wire [1:0] _T_605 = fifo_error_en[0] ? fifo_error_in_0 : fifo_error_0; // @[el2_dma_ctrl.scala 286:89]
+  wire [1:0] _T_609 = _T_568 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  wire [1:0] _T_614 = fifo_error_en[1] ? fifo_error_in_1 : fifo_error_1; // @[el2_dma_ctrl.scala 286:89]
+  wire [1:0] _T_618 = _T_575 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  wire [1:0] _T_623 = fifo_error_en[2] ? fifo_error_in_2 : fifo_error_2; // @[el2_dma_ctrl.scala 286:89]
+  wire [1:0] _T_627 = _T_582 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  wire [1:0] _T_632 = fifo_error_en[3] ? fifo_error_in_3 : fifo_error_3; // @[el2_dma_ctrl.scala 286:89]
+  wire [1:0] _T_636 = _T_589 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  wire [1:0] _T_641 = fifo_error_en[4] ? fifo_error_in_4 : fifo_error_4; // @[el2_dma_ctrl.scala 286:89]
+  wire [1:0] _T_645 = _T_596 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  reg  _T_721; // @[el2_dma_ctrl.scala 290:89]
+  reg  _T_714; // @[el2_dma_ctrl.scala 290:89]
+  reg  _T_707; // @[el2_dma_ctrl.scala 290:89]
+  reg  _T_700; // @[el2_dma_ctrl.scala 290:89]
+  reg  _T_693; // @[el2_dma_ctrl.scala 290:89]
+  wire [4:0] fifo_rpend = {_T_721,_T_714,_T_707,_T_700,_T_693}; // @[Cat.scala 29:58]
+  wire  _T_689 = fifo_pend_en[0] | fifo_rpend[0]; // @[el2_dma_ctrl.scala 290:93]
+  wire  _T_696 = fifo_pend_en[1] | fifo_rpend[1]; // @[el2_dma_ctrl.scala 290:93]
+  wire  _T_703 = fifo_pend_en[2] | fifo_rpend[2]; // @[el2_dma_ctrl.scala 290:93]
+  wire  _T_710 = fifo_pend_en[3] | fifo_rpend[3]; // @[el2_dma_ctrl.scala 290:93]
+  wire  _T_717 = fifo_pend_en[4] | fifo_rpend[4]; // @[el2_dma_ctrl.scala 290:93]
+  reg  _T_799; // @[el2_dma_ctrl.scala 294:89]
+  reg  _T_792; // @[el2_dma_ctrl.scala 294:89]
+  reg  _T_785; // @[el2_dma_ctrl.scala 294:89]
+  reg  _T_778; // @[el2_dma_ctrl.scala 294:89]
+  reg  _T_771; // @[el2_dma_ctrl.scala 294:89]
+  wire [4:0] fifo_done_bus = {_T_799,_T_792,_T_785,_T_778,_T_771}; // @[Cat.scala 29:58]
+  wire  _T_767 = fifo_done_bus_en[0] | fifo_done_bus[0]; // @[el2_dma_ctrl.scala 294:93]
+  wire  _T_774 = fifo_done_bus_en[1] | fifo_done_bus[1]; // @[el2_dma_ctrl.scala 294:93]
+  wire  _T_781 = fifo_done_bus_en[2] | fifo_done_bus[2]; // @[el2_dma_ctrl.scala 294:93]
+  wire  _T_788 = fifo_done_bus_en[3] | fifo_done_bus[3]; // @[el2_dma_ctrl.scala 294:93]
+  wire  _T_795 = fifo_done_bus_en[4] | fifo_done_bus[4]; // @[el2_dma_ctrl.scala 294:93]
+  wire [7:0] fifo_byteen_in = _T_20[7:0]; // @[el2_dma_ctrl.scala 253:28]
+  reg  _T_850; // @[Reg.scala 27:20]
+  reg  _T_852; // @[Reg.scala 27:20]
+  reg  _T_854; // @[Reg.scala 27:20]
+  reg  _T_856; // @[Reg.scala 27:20]
+  reg  _T_858; // @[Reg.scala 27:20]
+  wire [4:0] fifo_write = {_T_858,_T_856,_T_854,_T_852,_T_850}; // @[Cat.scala 29:58]
+  reg [63:0] fifo_data_0; // @[el2_lib.scala 514:16]
+  reg [63:0] fifo_data_1; // @[el2_lib.scala 514:16]
+  reg [63:0] fifo_data_2; // @[el2_lib.scala 514:16]
+  reg [63:0] fifo_data_3; // @[el2_lib.scala 514:16]
+  reg [63:0] fifo_data_4; // @[el2_lib.scala 514:16]
+  reg  fifo_tag_0; // @[Reg.scala 27:20]
+  reg  wrbuf_tag; // @[Reg.scala 27:20]
+  reg  rdbuf_tag; // @[Reg.scala 27:20]
+  wire  bus_cmd_tag = axi_mstr_sel ? wrbuf_tag : rdbuf_tag; // @[el2_dma_ctrl.scala 519:43]
+  reg  fifo_tag_1; // @[Reg.scala 27:20]
+  reg  fifo_tag_2; // @[Reg.scala 27:20]
+  reg  fifo_tag_3; // @[Reg.scala 27:20]
+  reg  fifo_tag_4; // @[Reg.scala 27:20]
+  wire  _T_931 = WrPtr == 3'h4; // @[el2_dma_ctrl.scala 318:30]
+  wire [2:0] _T_934 = WrPtr + 3'h1; // @[el2_dma_ctrl.scala 318:76]
+  wire  _T_936 = RdPtr == 3'h4; // @[el2_dma_ctrl.scala 320:30]
+  wire [2:0] _T_939 = RdPtr + 3'h1; // @[el2_dma_ctrl.scala 320:76]
+  wire  _T_941 = RspPtr == 3'h4; // @[el2_dma_ctrl.scala 322:31]
+  wire [2:0] _T_944 = RspPtr + 3'h1; // @[el2_dma_ctrl.scala 322:78]
+  wire  WrPtrEn = |fifo_cmd_en; // @[el2_dma_ctrl.scala 324:30]
+  wire  RdPtrEn = _T_165 | _T_197; // @[el2_dma_ctrl.scala 326:53]
+  wire  RspPtrEn = io_dma_dbg_cmd_done | _T_406; // @[el2_dma_ctrl.scala 328:39]
+  wire [3:0] _T_966 = {3'h0,fifo_valid[0]}; // @[Cat.scala 29:58]
+  wire [3:0] _T_969 = {3'h0,fifo_valid[1]}; // @[Cat.scala 29:58]
+  wire [3:0] _T_972 = {3'h0,fifo_valid[2]}; // @[Cat.scala 29:58]
+  wire [3:0] _T_975 = {3'h0,fifo_valid[3]}; // @[Cat.scala 29:58]
+  wire [3:0] _T_978 = {3'h0,fifo_valid[4]}; // @[Cat.scala 29:58]
+  wire [3:0] _T_980 = _T_966 + _T_969; // @[el2_dma_ctrl.scala 351:102]
+  wire [3:0] _T_982 = _T_980 + _T_972; // @[el2_dma_ctrl.scala 351:102]
+  wire [3:0] _T_984 = _T_982 + _T_975; // @[el2_dma_ctrl.scala 351:102]
+  wire [3:0] num_fifo_vld_tmp2 = _T_984 + _T_978; // @[el2_dma_ctrl.scala 351:102]
+  wire  _T_1123 = |fifo_valid; // @[el2_dma_ctrl.scala 390:30]
+  wire  fifo_empty = ~_T_1123; // @[el2_dma_ctrl.scala 390:17]
+  wire [4:0] _T_1086 = fifo_valid >> RspPtr; // @[el2_dma_ctrl.scala 377:39]
+  wire [4:0] _T_1088 = fifo_dbg >> RspPtr; // @[el2_dma_ctrl.scala 377:58]
+  wire  _T_1090 = _T_1086[0] & _T_1088[0]; // @[el2_dma_ctrl.scala 377:48]
+  wire [4:0] _T_1091 = fifo_done >> RspPtr; // @[el2_dma_ctrl.scala 377:78]
+  wire [31:0] _GEN_44 = 3'h1 == RspPtr ? fifo_addr_1 : fifo_addr_0; // @[el2_dma_ctrl.scala 378:49]
+  wire [31:0] _GEN_45 = 3'h2 == RspPtr ? fifo_addr_2 : _GEN_44; // @[el2_dma_ctrl.scala 378:49]
+  wire [31:0] _GEN_46 = 3'h3 == RspPtr ? fifo_addr_3 : _GEN_45; // @[el2_dma_ctrl.scala 378:49]
+  wire [31:0] _GEN_47 = 3'h4 == RspPtr ? fifo_addr_4 : _GEN_46; // @[el2_dma_ctrl.scala 378:49]
+  wire [63:0] _GEN_49 = 3'h1 == RspPtr ? fifo_data_1 : fifo_data_0; // @[el2_dma_ctrl.scala 378:71]
+  wire [63:0] _GEN_50 = 3'h2 == RspPtr ? fifo_data_2 : _GEN_49; // @[el2_dma_ctrl.scala 378:71]
+  wire [63:0] _GEN_51 = 3'h3 == RspPtr ? fifo_data_3 : _GEN_50; // @[el2_dma_ctrl.scala 378:71]
+  wire [63:0] _GEN_52 = 3'h4 == RspPtr ? fifo_data_4 : _GEN_51; // @[el2_dma_ctrl.scala 378:71]
+  wire [1:0] _GEN_54 = 3'h1 == RspPtr ? fifo_error_1 : fifo_error_0; // @[el2_dma_ctrl.scala 379:47]
+  wire [1:0] _GEN_55 = 3'h2 == RspPtr ? fifo_error_2 : _GEN_54; // @[el2_dma_ctrl.scala 379:47]
+  wire [1:0] _GEN_56 = 3'h3 == RspPtr ? fifo_error_3 : _GEN_55; // @[el2_dma_ctrl.scala 379:47]
+  wire [1:0] _GEN_57 = 3'h4 == RspPtr ? fifo_error_4 : _GEN_56; // @[el2_dma_ctrl.scala 379:47]
+  wire  _T_1116 = dma_mem_addr_in_dccm | dma_mem_addr_in_pic; // @[el2_dma_ctrl.scala 385:64]
+  wire [4:0] _T_1145 = fifo_rpend >> RdPtr; // @[el2_dma_ctrl.scala 403:54]
+  wire  _T_1147 = ~_T_1145[0]; // @[el2_dma_ctrl.scala 403:43]
+  wire  _T_1148 = _T_990[0] & _T_1147; // @[el2_dma_ctrl.scala 403:41]
+  wire  _T_1152 = _T_1148 & _T_994; // @[el2_dma_ctrl.scala 403:62]
+  wire  _T_1155 = ~_T_197; // @[el2_dma_ctrl.scala 403:84]
+  wire  dma_mem_req = _T_1152 & _T_1155; // @[el2_dma_ctrl.scala 403:82]
+  wire  _T_1117 = dma_mem_req & _T_1116; // @[el2_dma_ctrl.scala 385:40]
+  reg [2:0] dma_nack_count; // @[Reg.scala 27:20]
+  wire  _T_1118 = dma_nack_count >= io_dec_tlu_dma_qos_prty; // @[el2_dma_ctrl.scala 385:105]
+  wire  _T_1120 = dma_mem_req & dma_mem_addr_in_iccm; // @[el2_dma_ctrl.scala 386:40]
+  wire  _T_1127 = ~_T_165; // @[el2_dma_ctrl.scala 395:77]
+  wire [2:0] _T_1129 = _T_1127 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
+  wire [2:0] _T_1131 = _T_1129 & dma_nack_count; // @[el2_dma_ctrl.scala 395:115]
+  wire  _T_1135 = dma_mem_req & _T_1127; // @[el2_dma_ctrl.scala 395:163]
+  wire [2:0] _T_1138 = dma_nack_count + 3'h1; // @[el2_dma_ctrl.scala 395:224]
+  wire  _T_1164 = io_dma_mem_write & _T_1076; // @[el2_dma_ctrl.scala 409:44]
+  wire [31:0] _T_1168 = {dma_mem_addr_int[31:3],1'h1,dma_mem_addr_int[1:0]}; // @[Cat.scala 29:58]
+  wire  _T_1176 = io_dma_mem_write & _T_1077; // @[el2_dma_ctrl.scala 410:44]
+  wire [4:0] _T_1179 = fifo_write >> RdPtr; // @[el2_dma_ctrl.scala 412:33]
+  wire [63:0] _GEN_75 = 3'h1 == RdPtr ? fifo_data_1 : fifo_data_0; // @[el2_dma_ctrl.scala 413:20]
+  wire [63:0] _GEN_76 = 3'h2 == RdPtr ? fifo_data_2 : _GEN_75; // @[el2_dma_ctrl.scala 413:20]
+  wire [63:0] _GEN_77 = 3'h3 == RdPtr ? fifo_data_3 : _GEN_76; // @[el2_dma_ctrl.scala 413:20]
+  reg  dma_dbg_cmd_done_q; // @[el2_dma_ctrl.scala 433:12]
+  wire  _T_1192 = bus_cmd_valid & io_dma_bus_clk_en; // @[el2_dma_ctrl.scala 438:44]
+  wire  _T_1193 = _T_1192 | io_dbg_cmd_valid; // @[el2_dma_ctrl.scala 438:65]
+  wire  bus_rsp_valid = io_dma_axi_bvalid | io_dma_axi_rvalid; // @[el2_dma_ctrl.scala 553:59]
+  wire  _T_1194 = bus_cmd_valid | bus_rsp_valid; // @[el2_dma_ctrl.scala 439:44]
+  wire  _T_1195 = _T_1194 | io_dbg_cmd_valid; // @[el2_dma_ctrl.scala 439:60]
+  wire  _T_1196 = _T_1195 | io_dma_dbg_cmd_done; // @[el2_dma_ctrl.scala 439:79]
+  wire  _T_1197 = _T_1196 | dma_dbg_cmd_done_q; // @[el2_dma_ctrl.scala 439:101]
+  wire  _T_1199 = _T_1197 | _T_1123; // @[el2_dma_ctrl.scala 439:122]
+  wire  wrbuf_en = io_dma_axi_awvalid & io_dma_axi_awready; // @[el2_dma_ctrl.scala 461:46]
+  wire  wrbuf_data_en = io_dma_axi_wvalid & io_dma_axi_wready; // @[el2_dma_ctrl.scala 462:45]
+  wire  wrbuf_cmd_sent = axi_mstr_prty_en & axi_mstr_sel; // @[el2_dma_ctrl.scala 463:40]
+  wire  _T_1201 = ~wrbuf_en; // @[el2_dma_ctrl.scala 464:51]
+  wire  wrbuf_rst = wrbuf_cmd_sent & _T_1201; // @[el2_dma_ctrl.scala 464:49]
+  wire  _T_1203 = ~wrbuf_data_en; // @[el2_dma_ctrl.scala 465:51]
+  wire  wrbuf_data_rst = wrbuf_cmd_sent & _T_1203; // @[el2_dma_ctrl.scala 465:49]
+  wire  _T_1204 = wrbuf_en | wrbuf_vld; // @[el2_dma_ctrl.scala 467:63]
+  wire  _T_1205 = ~wrbuf_rst; // @[el2_dma_ctrl.scala 467:92]
+  wire  _T_1208 = wrbuf_data_en | wrbuf_data_vld; // @[el2_dma_ctrl.scala 469:63]
+  wire  _T_1209 = ~wrbuf_data_rst; // @[el2_dma_ctrl.scala 469:102]
+  wire  rdbuf_en = io_dma_axi_arvalid & io_dma_axi_arready; // @[el2_dma_ctrl.scala 489:58]
+  wire  _T_1214 = ~axi_mstr_sel; // @[el2_dma_ctrl.scala 490:44]
+  wire  rdbuf_cmd_sent = axi_mstr_prty_en & _T_1214; // @[el2_dma_ctrl.scala 490:42]
+  wire  _T_1216 = ~rdbuf_en; // @[el2_dma_ctrl.scala 491:63]
+  wire  rdbuf_rst = rdbuf_cmd_sent & _T_1216; // @[el2_dma_ctrl.scala 491:61]
+  wire  _T_1217 = rdbuf_en | rdbuf_vld; // @[el2_dma_ctrl.scala 493:51]
+  wire  _T_1218 = ~rdbuf_rst; // @[el2_dma_ctrl.scala 493:80]
+  wire  _T_1222 = ~wrbuf_cmd_sent; // @[el2_dma_ctrl.scala 505:44]
+  wire  _T_1223 = wrbuf_vld & _T_1222; // @[el2_dma_ctrl.scala 505:42]
+  wire  _T_1226 = wrbuf_data_vld & _T_1222; // @[el2_dma_ctrl.scala 506:47]
+  wire  _T_1228 = ~rdbuf_cmd_sent; // @[el2_dma_ctrl.scala 507:44]
+  wire  _T_1229 = rdbuf_vld & _T_1228; // @[el2_dma_ctrl.scala 507:42]
+  wire  axi_mstr_prty_in = ~axi_mstr_priority; // @[el2_dma_ctrl.scala 526:27]
+  wire  _T_1251 = ~_T_1088[0]; // @[el2_dma_ctrl.scala 533:50]
+  wire  _T_1252 = _T_1086[0] & _T_1251; // @[el2_dma_ctrl.scala 533:48]
+  wire [4:0] _T_1253 = fifo_done_bus >> RspPtr; // @[el2_dma_ctrl.scala 533:83]
+  wire  axi_rsp_valid = _T_1252 & _T_1253[0]; // @[el2_dma_ctrl.scala 533:68]
+  wire [4:0] _T_1255 = fifo_write >> RspPtr; // @[el2_dma_ctrl.scala 535:39]
+  wire  axi_rsp_write = _T_1255[0]; // @[el2_dma_ctrl.scala 535:39]
+  wire [1:0] _T_1258 = _GEN_57[1] ? 2'h3 : 2'h0; // @[el2_dma_ctrl.scala 536:64]
+  wire  _GEN_86 = 3'h1 == RspPtr ? fifo_tag_1 : fifo_tag_0; // @[el2_dma_ctrl.scala 544:33]
+  wire  _GEN_87 = 3'h2 == RspPtr ? fifo_tag_2 : _GEN_86; // @[el2_dma_ctrl.scala 544:33]
+  wire  _GEN_88 = 3'h3 == RspPtr ? fifo_tag_3 : _GEN_87; // @[el2_dma_ctrl.scala 544:33]
+  wire  _T_1261 = ~axi_rsp_write; // @[el2_dma_ctrl.scala 546:46]
+  rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23]
+    .io_l1clk(rvclkhdr_io_l1clk),
+    .io_clk(rvclkhdr_io_clk),
+    .io_en(rvclkhdr_io_en),
+    .io_scan_mode(rvclkhdr_io_scan_mode)
+  );
+  rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23]
+    .io_l1clk(rvclkhdr_1_io_l1clk),
+    .io_clk(rvclkhdr_1_io_clk),
+    .io_en(rvclkhdr_1_io_en),
+    .io_scan_mode(rvclkhdr_1_io_scan_mode)
+  );
+  rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23]
+    .io_l1clk(rvclkhdr_2_io_l1clk),
+    .io_clk(rvclkhdr_2_io_clk),
+    .io_en(rvclkhdr_2_io_en),
+    .io_scan_mode(rvclkhdr_2_io_scan_mode)
+  );
+  rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23]
+    .io_l1clk(rvclkhdr_3_io_l1clk),
+    .io_clk(rvclkhdr_3_io_clk),
+    .io_en(rvclkhdr_3_io_en),
+    .io_scan_mode(rvclkhdr_3_io_scan_mode)
+  );
+  rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23]
+    .io_l1clk(rvclkhdr_4_io_l1clk),
+    .io_clk(rvclkhdr_4_io_clk),
+    .io_en(rvclkhdr_4_io_en),
+    .io_scan_mode(rvclkhdr_4_io_scan_mode)
+  );
+  rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 508:23]
+    .io_l1clk(rvclkhdr_5_io_l1clk),
+    .io_clk(rvclkhdr_5_io_clk),
+    .io_en(rvclkhdr_5_io_en),
+    .io_scan_mode(rvclkhdr_5_io_scan_mode)
+  );
+  rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 508:23]
+    .io_l1clk(rvclkhdr_6_io_l1clk),
+    .io_clk(rvclkhdr_6_io_clk),
+    .io_en(rvclkhdr_6_io_en),
+    .io_scan_mode(rvclkhdr_6_io_scan_mode)
+  );
+  rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 508:23]
+    .io_l1clk(rvclkhdr_7_io_l1clk),
+    .io_clk(rvclkhdr_7_io_clk),
+    .io_en(rvclkhdr_7_io_en),
+    .io_scan_mode(rvclkhdr_7_io_scan_mode)
+  );
+  rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 508:23]
+    .io_l1clk(rvclkhdr_8_io_l1clk),
+    .io_clk(rvclkhdr_8_io_clk),
+    .io_en(rvclkhdr_8_io_en),
+    .io_scan_mode(rvclkhdr_8_io_scan_mode)
+  );
+  rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 508:23]
+    .io_l1clk(rvclkhdr_9_io_l1clk),
+    .io_clk(rvclkhdr_9_io_clk),
+    .io_en(rvclkhdr_9_io_en),
+    .io_scan_mode(rvclkhdr_9_io_scan_mode)
+  );
+  rvclkhdr dma_buffer_c1cgc ( // @[el2_dma_ctrl.scala 441:32]
+    .io_l1clk(dma_buffer_c1cgc_io_l1clk),
+    .io_clk(dma_buffer_c1cgc_io_clk),
+    .io_en(dma_buffer_c1cgc_io_en),
+    .io_scan_mode(dma_buffer_c1cgc_io_scan_mode)
+  );
+  rvclkhdr dma_free_cgc ( // @[el2_dma_ctrl.scala 447:28]
+    .io_l1clk(dma_free_cgc_io_l1clk),
+    .io_clk(dma_free_cgc_io_clk),
+    .io_en(dma_free_cgc_io_en),
+    .io_scan_mode(dma_free_cgc_io_scan_mode)
+  );
+  rvclkhdr dma_bus_cgc ( // @[el2_dma_ctrl.scala 453:27]
+    .io_l1clk(dma_bus_cgc_io_l1clk),
+    .io_clk(dma_bus_cgc_io_clk),
+    .io_en(dma_bus_cgc_io_en),
+    .io_scan_mode(dma_bus_cgc_io_scan_mode)
+  );
+  rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 508:23]
+    .io_l1clk(rvclkhdr_10_io_l1clk),
+    .io_clk(rvclkhdr_10_io_clk),
+    .io_en(rvclkhdr_10_io_en),
+    .io_scan_mode(rvclkhdr_10_io_scan_mode)
+  );
+  rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 508:23]
+    .io_l1clk(rvclkhdr_11_io_l1clk),
+    .io_clk(rvclkhdr_11_io_clk),
+    .io_en(rvclkhdr_11_io_en),
+    .io_scan_mode(rvclkhdr_11_io_scan_mode)
+  );
+  rvclkhdr rvclkhdr_12 ( // @[el2_lib.scala 508:23]
+    .io_l1clk(rvclkhdr_12_io_l1clk),
+    .io_clk(rvclkhdr_12_io_clk),
+    .io_en(rvclkhdr_12_io_en),
+    .io_scan_mode(rvclkhdr_12_io_scan_mode)
+  );
+  assign io_dma_dbg_ready = fifo_empty & dbg_dma_bubble_bus; // @[el2_dma_ctrl.scala 376:25]
+  assign io_dma_dbg_cmd_done = _T_1090 & _T_1091[0]; // @[el2_dma_ctrl.scala 377:25]
+  assign io_dma_dbg_cmd_fail = |_GEN_57; // @[el2_dma_ctrl.scala 379:25]
+  assign io_dma_dbg_rddata = _GEN_47[2] ? _GEN_52[63:32] : _GEN_52[31:0]; // @[el2_dma_ctrl.scala 378:25]
+  assign io_dma_dccm_req = _T_1117 & io_dccm_ready; // @[el2_dma_ctrl.scala 404:20]
+  assign io_dma_iccm_req = _T_1120 & io_iccm_ready; // @[el2_dma_ctrl.scala 405:20]
+  assign io_dma_mem_tag = RdPtr; // @[el2_dma_ctrl.scala 406:20]
+  assign io_dma_mem_addr = _T_1164 ? _T_1168 : dma_mem_addr_int; // @[el2_dma_ctrl.scala 409:20]
+  assign io_dma_mem_sz = _T_1176 ? 3'h2 : dma_mem_sz_int; // @[el2_dma_ctrl.scala 410:20]
+  assign io_dma_mem_write = _T_1179[0]; // @[el2_dma_ctrl.scala 412:20]
+  assign io_dma_mem_wdata = 3'h4 == RdPtr ? fifo_data_4 : _GEN_77; // @[el2_dma_ctrl.scala 413:20]
+  assign io_dma_dccm_stall_any = _T_1117 & _T_1118; // @[el2_dma_ctrl.scala 385:25]
+  assign io_dma_iccm_stall_any = _T_1120 & _T_1118; // @[el2_dma_ctrl.scala 386:25]
+  assign io_dma_pmu_dccm_read = io_dma_dccm_req & _T_166; // @[el2_dma_ctrl.scala 417:26]
+  assign io_dma_pmu_dccm_write = io_dma_dccm_req & io_dma_mem_write; // @[el2_dma_ctrl.scala 418:26]
+  assign io_dma_pmu_any_read = _T_165 & _T_166; // @[el2_dma_ctrl.scala 419:26]
+  assign io_dma_pmu_any_write = _T_165 & io_dma_mem_write; // @[el2_dma_ctrl.scala 420:26]
+  assign io_dma_axi_awready = ~_T_1223; // @[el2_dma_ctrl.scala 505:27]
+  assign io_dma_axi_wready = ~_T_1226; // @[el2_dma_ctrl.scala 506:27]
+  assign io_dma_axi_bvalid = axi_rsp_valid & axi_rsp_write; // @[el2_dma_ctrl.scala 542:27]
+  assign io_dma_axi_bresp = _GEN_57[0] ? 2'h2 : _T_1258; // @[el2_dma_ctrl.scala 543:33]
+  assign io_dma_axi_bid = 3'h4 == RspPtr ? fifo_tag_4 : _GEN_88; // @[el2_dma_ctrl.scala 544:33]
+  assign io_dma_axi_arready = ~_T_1229; // @[el2_dma_ctrl.scala 507:27]
+  assign io_dma_axi_rvalid = axi_rsp_valid & _T_1261; // @[el2_dma_ctrl.scala 546:27]
+  assign io_dma_axi_rid = 3'h4 == RspPtr ? fifo_tag_4 : _GEN_88; // @[el2_dma_ctrl.scala 550:37]
+  assign io_dma_axi_rdata = 3'h4 == RspPtr ? fifo_data_4 : _GEN_51; // @[el2_dma_ctrl.scala 548:35]
+  assign io_dma_axi_rresp = _GEN_57[0] ? 2'h2 : _T_1258; // @[el2_dma_ctrl.scala 547:33]
+  assign io_dma_axi_rlast = 1'h1; // @[el2_dma_ctrl.scala 549:33]
+  assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18]
+  assign rvclkhdr_io_en = fifo_cmd_en[0]; // @[el2_lib.scala 511:17]
+  assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
+  assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18]
+  assign rvclkhdr_1_io_en = fifo_cmd_en[1]; // @[el2_lib.scala 511:17]
+  assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
+  assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18]
+  assign rvclkhdr_2_io_en = fifo_cmd_en[2]; // @[el2_lib.scala 511:17]
+  assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
+  assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18]
+  assign rvclkhdr_3_io_en = fifo_cmd_en[3]; // @[el2_lib.scala 511:17]
+  assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
+  assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18]
+  assign rvclkhdr_4_io_en = fifo_cmd_en[4]; // @[el2_lib.scala 511:17]
+  assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
+  assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 510:18]
+  assign rvclkhdr_5_io_en = fifo_data_en[0]; // @[el2_lib.scala 511:17]
+  assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
+  assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 510:18]
+  assign rvclkhdr_6_io_en = fifo_data_en[1]; // @[el2_lib.scala 511:17]
+  assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
+  assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 510:18]
+  assign rvclkhdr_7_io_en = fifo_data_en[2]; // @[el2_lib.scala 511:17]
+  assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
+  assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 510:18]
+  assign rvclkhdr_8_io_en = fifo_data_en[3]; // @[el2_lib.scala 511:17]
+  assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
+  assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 510:18]
+  assign rvclkhdr_9_io_en = fifo_data_en[4]; // @[el2_lib.scala 511:17]
+  assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
+  assign dma_buffer_c1cgc_io_clk = clock; // @[el2_dma_ctrl.scala 444:33]
+  assign dma_buffer_c1cgc_io_en = _T_1193 | io_clk_override; // @[el2_dma_ctrl.scala 442:33]
+  assign dma_buffer_c1cgc_io_scan_mode = io_scan_mode; // @[el2_dma_ctrl.scala 443:33]
+  assign dma_free_cgc_io_clk = clock; // @[el2_dma_ctrl.scala 450:29]
+  assign dma_free_cgc_io_en = _T_1199 | io_clk_override; // @[el2_dma_ctrl.scala 448:29]
+  assign dma_free_cgc_io_scan_mode = io_scan_mode; // @[el2_dma_ctrl.scala 449:29]
+  assign dma_bus_cgc_io_clk = clock; // @[el2_dma_ctrl.scala 456:28]
+  assign dma_bus_cgc_io_en = io_dma_bus_clk_en; // @[el2_dma_ctrl.scala 454:28]
+  assign dma_bus_cgc_io_scan_mode = io_scan_mode; // @[el2_dma_ctrl.scala 455:28]
+  assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 510:18]
+  assign rvclkhdr_10_io_en = wrbuf_en & io_dma_bus_clk_en; // @[el2_lib.scala 511:17]
+  assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
+  assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 510:18]
+  assign rvclkhdr_11_io_en = wrbuf_data_en & io_dma_bus_clk_en; // @[el2_lib.scala 511:17]
+  assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
+  assign rvclkhdr_12_io_clk = clock; // @[el2_lib.scala 510:18]
+  assign rvclkhdr_12_io_en = rdbuf_en & io_dma_bus_clk_en; // @[el2_lib.scala 511:17]
+  assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+  integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+  `ifdef RANDOMIZE
+    `ifdef INIT_RANDOM
+      `INIT_RANDOM
+    `endif
+    `ifndef VERILATOR
+      `ifdef RANDOMIZE_DELAY
+        #`RANDOMIZE_DELAY begin end
+      `else
+        #0.002 begin end
+      `endif
+    `endif
+`ifdef RANDOMIZE_REG_INIT
+  _RAND_0 = {1{`RANDOM}};
+  RdPtr = _RAND_0[2:0];
+  _RAND_1 = {1{`RANDOM}};
+  fifo_addr_4 = _RAND_1[31:0];
+  _RAND_2 = {1{`RANDOM}};
+  fifo_addr_3 = _RAND_2[31:0];
+  _RAND_3 = {1{`RANDOM}};
+  fifo_addr_2 = _RAND_3[31:0];
+  _RAND_4 = {1{`RANDOM}};
+  fifo_addr_1 = _RAND_4[31:0];
+  _RAND_5 = {1{`RANDOM}};
+  fifo_addr_0 = _RAND_5[31:0];
+  _RAND_6 = {1{`RANDOM}};
+  wrbuf_vld = _RAND_6[0:0];
+  _RAND_7 = {1{`RANDOM}};
+  wrbuf_data_vld = _RAND_7[0:0];
+  _RAND_8 = {1{`RANDOM}};
+  rdbuf_vld = _RAND_8[0:0];
+  _RAND_9 = {1{`RANDOM}};
+  axi_mstr_priority = _RAND_9[0:0];
+  _RAND_10 = {1{`RANDOM}};
+  wrbuf_addr = _RAND_10[31:0];
+  _RAND_11 = {1{`RANDOM}};
+  rdbuf_addr = _RAND_11[31:0];
+  _RAND_12 = {1{`RANDOM}};
+  wrbuf_byteen = _RAND_12[7:0];
+  _RAND_13 = {1{`RANDOM}};
+  wrbuf_sz = _RAND_13[2:0];
+  _RAND_14 = {1{`RANDOM}};
+  rdbuf_sz = _RAND_14[2:0];
+  _RAND_15 = {1{`RANDOM}};
+  fifo_full = _RAND_15[0:0];
+  _RAND_16 = {1{`RANDOM}};
+  dbg_dma_bubble_bus = _RAND_16[0:0];
+  _RAND_17 = {1{`RANDOM}};
+  WrPtr = _RAND_17[2:0];
+  _RAND_18 = {1{`RANDOM}};
+  _T_598 = _RAND_18[0:0];
+  _RAND_19 = {1{`RANDOM}};
+  _T_591 = _RAND_19[0:0];
+  _RAND_20 = {1{`RANDOM}};
+  _T_584 = _RAND_20[0:0];
+  _RAND_21 = {1{`RANDOM}};
+  _T_577 = _RAND_21[0:0];
+  _RAND_22 = {1{`RANDOM}};
+  _T_570 = _RAND_22[0:0];
+  _RAND_23 = {1{`RANDOM}};
+  _T_760 = _RAND_23[0:0];
+  _RAND_24 = {1{`RANDOM}};
+  _T_753 = _RAND_24[0:0];
+  _RAND_25 = {1{`RANDOM}};
+  _T_746 = _RAND_25[0:0];
+  _RAND_26 = {1{`RANDOM}};
+  _T_739 = _RAND_26[0:0];
+  _RAND_27 = {1{`RANDOM}};
+  _T_732 = _RAND_27[0:0];
+  _RAND_28 = {1{`RANDOM}};
+  _T_886 = _RAND_28[0:0];
+  _RAND_29 = {1{`RANDOM}};
+  _T_884 = _RAND_29[0:0];
+  _RAND_30 = {1{`RANDOM}};
+  _T_882 = _RAND_30[0:0];
+  _RAND_31 = {1{`RANDOM}};
+  _T_880 = _RAND_31[0:0];
+  _RAND_32 = {1{`RANDOM}};
+  _T_878 = _RAND_32[0:0];
+  _RAND_33 = {1{`RANDOM}};
+  fifo_sz_4 = _RAND_33[2:0];
+  _RAND_34 = {1{`RANDOM}};
+  fifo_sz_3 = _RAND_34[2:0];
+  _RAND_35 = {1{`RANDOM}};
+  fifo_sz_2 = _RAND_35[2:0];
+  _RAND_36 = {1{`RANDOM}};
+  fifo_sz_1 = _RAND_36[2:0];
+  _RAND_37 = {1{`RANDOM}};
+  fifo_sz_0 = _RAND_37[2:0];
+  _RAND_38 = {1{`RANDOM}};
+  fifo_byteen_4 = _RAND_38[7:0];
+  _RAND_39 = {1{`RANDOM}};
+  fifo_byteen_3 = _RAND_39[7:0];
+  _RAND_40 = {1{`RANDOM}};
+  fifo_byteen_2 = _RAND_40[7:0];
+  _RAND_41 = {1{`RANDOM}};
+  fifo_byteen_1 = _RAND_41[7:0];
+  _RAND_42 = {1{`RANDOM}};
+  fifo_byteen_0 = _RAND_42[7:0];
+  _RAND_43 = {1{`RANDOM}};
+  fifo_error_0 = _RAND_43[1:0];
+  _RAND_44 = {1{`RANDOM}};
+  fifo_error_1 = _RAND_44[1:0];
+  _RAND_45 = {1{`RANDOM}};
+  fifo_error_2 = _RAND_45[1:0];
+  _RAND_46 = {1{`RANDOM}};
+  fifo_error_3 = _RAND_46[1:0];
+  _RAND_47 = {1{`RANDOM}};
+  fifo_error_4 = _RAND_47[1:0];
+  _RAND_48 = {1{`RANDOM}};
+  RspPtr = _RAND_48[2:0];
+  _RAND_49 = {2{`RANDOM}};
+  wrbuf_data = _RAND_49[63:0];
+  _RAND_50 = {1{`RANDOM}};
+  _T_721 = _RAND_50[0:0];
+  _RAND_51 = {1{`RANDOM}};
+  _T_714 = _RAND_51[0:0];
+  _RAND_52 = {1{`RANDOM}};
+  _T_707 = _RAND_52[0:0];
+  _RAND_53 = {1{`RANDOM}};
+  _T_700 = _RAND_53[0:0];
+  _RAND_54 = {1{`RANDOM}};
+  _T_693 = _RAND_54[0:0];
+  _RAND_55 = {1{`RANDOM}};
+  _T_799 = _RAND_55[0:0];
+  _RAND_56 = {1{`RANDOM}};
+  _T_792 = _RAND_56[0:0];
+  _RAND_57 = {1{`RANDOM}};
+  _T_785 = _RAND_57[0:0];
+  _RAND_58 = {1{`RANDOM}};
+  _T_778 = _RAND_58[0:0];
+  _RAND_59 = {1{`RANDOM}};
+  _T_771 = _RAND_59[0:0];
+  _RAND_60 = {1{`RANDOM}};
+  _T_850 = _RAND_60[0:0];
+  _RAND_61 = {1{`RANDOM}};
+  _T_852 = _RAND_61[0:0];
+  _RAND_62 = {1{`RANDOM}};
+  _T_854 = _RAND_62[0:0];
+  _RAND_63 = {1{`RANDOM}};
+  _T_856 = _RAND_63[0:0];
+  _RAND_64 = {1{`RANDOM}};
+  _T_858 = _RAND_64[0:0];
+  _RAND_65 = {2{`RANDOM}};
+  fifo_data_0 = _RAND_65[63:0];
+  _RAND_66 = {2{`RANDOM}};
+  fifo_data_1 = _RAND_66[63:0];
+  _RAND_67 = {2{`RANDOM}};
+  fifo_data_2 = _RAND_67[63:0];
+  _RAND_68 = {2{`RANDOM}};
+  fifo_data_3 = _RAND_68[63:0];
+  _RAND_69 = {2{`RANDOM}};
+  fifo_data_4 = _RAND_69[63:0];
+  _RAND_70 = {1{`RANDOM}};
+  fifo_tag_0 = _RAND_70[0:0];
+  _RAND_71 = {1{`RANDOM}};
+  wrbuf_tag = _RAND_71[0:0];
+  _RAND_72 = {1{`RANDOM}};
+  rdbuf_tag = _RAND_72[0:0];
+  _RAND_73 = {1{`RANDOM}};
+  fifo_tag_1 = _RAND_73[0:0];
+  _RAND_74 = {1{`RANDOM}};
+  fifo_tag_2 = _RAND_74[0:0];
+  _RAND_75 = {1{`RANDOM}};
+  fifo_tag_3 = _RAND_75[0:0];
+  _RAND_76 = {1{`RANDOM}};
+  fifo_tag_4 = _RAND_76[0:0];
+  _RAND_77 = {1{`RANDOM}};
+  dma_nack_count = _RAND_77[2:0];
+  _RAND_78 = {1{`RANDOM}};
+  dma_dbg_cmd_done_q = _RAND_78[0:0];
+`endif // RANDOMIZE_REG_INIT
+  if (reset) begin
+    RdPtr = 3'h0;
+  end
+  if (reset) begin
+    fifo_addr_4 = 32'h0;
+  end
+  if (reset) begin
+    fifo_addr_3 = 32'h0;
+  end
+  if (reset) begin
+    fifo_addr_2 = 32'h0;
+  end
+  if (reset) begin
+    fifo_addr_1 = 32'h0;
+  end
+  if (reset) begin
+    fifo_addr_0 = 32'h0;
+  end
+  if (reset) begin
+    wrbuf_vld = 1'h0;
+  end
+  if (reset) begin
+    wrbuf_data_vld = 1'h0;
+  end
+  if (reset) begin
+    rdbuf_vld = 1'h0;
+  end
+  if (reset) begin
+    axi_mstr_priority = 1'h0;
+  end
+  if (reset) begin
+    wrbuf_addr = 32'h0;
+  end
+  if (reset) begin
+    rdbuf_addr = 32'h0;
+  end
+  if (reset) begin
+    wrbuf_byteen = 8'h0;
+  end
+  if (reset) begin
+    wrbuf_sz = 3'h0;
+  end
+  if (reset) begin
+    rdbuf_sz = 3'h0;
+  end
+  if (reset) begin
+    fifo_full = 1'h0;
+  end
+  if (reset) begin
+    dbg_dma_bubble_bus = 1'h0;
+  end
+  if (reset) begin
+    WrPtr = 3'h0;
+  end
+  if (reset) begin
+    _T_598 = 1'h0;
+  end
+  if (reset) begin
+    _T_591 = 1'h0;
+  end
+  if (reset) begin
+    _T_584 = 1'h0;
+  end
+  if (reset) begin
+    _T_577 = 1'h0;
+  end
+  if (reset) begin
+    _T_570 = 1'h0;
+  end
+  if (reset) begin
+    _T_760 = 1'h0;
+  end
+  if (reset) begin
+    _T_753 = 1'h0;
+  end
+  if (reset) begin
+    _T_746 = 1'h0;
+  end
+  if (reset) begin
+    _T_739 = 1'h0;
+  end
+  if (reset) begin
+    _T_732 = 1'h0;
+  end
+  if (reset) begin
+    _T_886 = 1'h0;
+  end
+  if (reset) begin
+    _T_884 = 1'h0;
+  end
+  if (reset) begin
+    _T_882 = 1'h0;
+  end
+  if (reset) begin
+    _T_880 = 1'h0;
+  end
+  if (reset) begin
+    _T_878 = 1'h0;
+  end
+  if (reset) begin
+    fifo_sz_4 = 3'h0;
+  end
+  if (reset) begin
+    fifo_sz_3 = 3'h0;
+  end
+  if (reset) begin
+    fifo_sz_2 = 3'h0;
+  end
+  if (reset) begin
+    fifo_sz_1 = 3'h0;
+  end
+  if (reset) begin
+    fifo_sz_0 = 3'h0;
+  end
+  if (reset) begin
+    fifo_byteen_4 = 8'h0;
+  end
+  if (reset) begin
+    fifo_byteen_3 = 8'h0;
+  end
+  if (reset) begin
+    fifo_byteen_2 = 8'h0;
+  end
+  if (reset) begin
+    fifo_byteen_1 = 8'h0;
+  end
+  if (reset) begin
+    fifo_byteen_0 = 8'h0;
+  end
+  if (reset) begin
+    fifo_error_0 = 2'h0;
+  end
+  if (reset) begin
+    fifo_error_1 = 2'h0;
+  end
+  if (reset) begin
+    fifo_error_2 = 2'h0;
+  end
+  if (reset) begin
+    fifo_error_3 = 2'h0;
+  end
+  if (reset) begin
+    fifo_error_4 = 2'h0;
+  end
+  if (reset) begin
+    RspPtr = 3'h0;
+  end
+  if (reset) begin
+    wrbuf_data = 64'h0;
+  end
+  if (reset) begin
+    _T_721 = 1'h0;
+  end
+  if (reset) begin
+    _T_714 = 1'h0;
+  end
+  if (reset) begin
+    _T_707 = 1'h0;
+  end
+  if (reset) begin
+    _T_700 = 1'h0;
+  end
+  if (reset) begin
+    _T_693 = 1'h0;
+  end
+  if (reset) begin
+    _T_799 = 1'h0;
+  end
+  if (reset) begin
+    _T_792 = 1'h0;
+  end
+  if (reset) begin
+    _T_785 = 1'h0;
+  end
+  if (reset) begin
+    _T_778 = 1'h0;
+  end
+  if (reset) begin
+    _T_771 = 1'h0;
+  end
+  if (reset) begin
+    _T_850 = 1'h0;
+  end
+  if (reset) begin
+    _T_852 = 1'h0;
+  end
+  if (reset) begin
+    _T_854 = 1'h0;
+  end
+  if (reset) begin
+    _T_856 = 1'h0;
+  end
+  if (reset) begin
+    _T_858 = 1'h0;
+  end
+  if (reset) begin
+    fifo_data_0 = 64'h0;
+  end
+  if (reset) begin
+    fifo_data_1 = 64'h0;
+  end
+  if (reset) begin
+    fifo_data_2 = 64'h0;
+  end
+  if (reset) begin
+    fifo_data_3 = 64'h0;
+  end
+  if (reset) begin
+    fifo_data_4 = 64'h0;
+  end
+  if (reset) begin
+    fifo_tag_0 = 1'h0;
+  end
+  if (reset) begin
+    wrbuf_tag = 1'h0;
+  end
+  if (reset) begin
+    rdbuf_tag = 1'h0;
+  end
+  if (reset) begin
+    fifo_tag_1 = 1'h0;
+  end
+  if (reset) begin
+    fifo_tag_2 = 1'h0;
+  end
+  if (reset) begin
+    fifo_tag_3 = 1'h0;
+  end
+  if (reset) begin
+    fifo_tag_4 = 1'h0;
+  end
+  if (reset) begin
+    dma_nack_count = 3'h0;
+  end
+  if (reset) begin
+    dma_dbg_cmd_done_q = 1'h0;
+  end
+  `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+  always @(posedge dma_free_clk or posedge reset) begin
+    if (reset) begin
+      RdPtr <= 3'h0;
+    end else if (RdPtrEn) begin
+      if (_T_936) begin
+        RdPtr <= 3'h0;
+      end else begin
+        RdPtr <= _T_939;
+      end
+    end
+  end
+  always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin
+    if (reset) begin
+      fifo_addr_4 <= 32'h0;
+    end else if (io_dbg_cmd_valid) begin
+      fifo_addr_4 <= io_dbg_cmd_addr;
+    end else if (axi_mstr_sel) begin
+      fifo_addr_4 <= wrbuf_addr;
+    end else begin
+      fifo_addr_4 <= rdbuf_addr;
+    end
+  end
+  always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
+    if (reset) begin
+      fifo_addr_3 <= 32'h0;
+    end else if (io_dbg_cmd_valid) begin
+      fifo_addr_3 <= io_dbg_cmd_addr;
+    end else if (axi_mstr_sel) begin
+      fifo_addr_3 <= wrbuf_addr;
+    end else begin
+      fifo_addr_3 <= rdbuf_addr;
+    end
+  end
+  always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
+    if (reset) begin
+      fifo_addr_2 <= 32'h0;
+    end else if (io_dbg_cmd_valid) begin
+      fifo_addr_2 <= io_dbg_cmd_addr;
+    end else if (axi_mstr_sel) begin
+      fifo_addr_2 <= wrbuf_addr;
+    end else begin
+      fifo_addr_2 <= rdbuf_addr;
+    end
+  end
+  always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
+    if (reset) begin
+      fifo_addr_1 <= 32'h0;
+    end else if (io_dbg_cmd_valid) begin
+      fifo_addr_1 <= io_dbg_cmd_addr;
+    end else if (axi_mstr_sel) begin
+      fifo_addr_1 <= wrbuf_addr;
+    end else begin
+      fifo_addr_1 <= rdbuf_addr;
+    end
+  end
+  always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
+    if (reset) begin
+      fifo_addr_0 <= 32'h0;
+    end else if (io_dbg_cmd_valid) begin
+      fifo_addr_0 <= io_dbg_cmd_addr;
+    end else begin
+      fifo_addr_0 <= bus_cmd_addr;
+    end
+  end
+  always @(posedge dma_bus_clk or posedge reset) begin
+    if (reset) begin
+      wrbuf_vld <= 1'h0;
+    end else begin
+      wrbuf_vld <= _T_1204 & _T_1205;
+    end
+  end
+  always @(posedge dma_bus_clk or posedge reset) begin
+    if (reset) begin
+      wrbuf_data_vld <= 1'h0;
+    end else begin
+      wrbuf_data_vld <= _T_1208 & _T_1209;
+    end
+  end
+  always @(posedge dma_bus_clk or posedge reset) begin
+    if (reset) begin
+      rdbuf_vld <= 1'h0;
+    end else begin
+      rdbuf_vld <= _T_1217 & _T_1218;
+    end
+  end
+  always @(posedge dma_bus_clk or posedge reset) begin
+    if (reset) begin
+      axi_mstr_priority <= 1'h0;
+    end else if (axi_mstr_prty_en) begin
+      axi_mstr_priority <= axi_mstr_prty_in;
+    end
+  end
+  always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin
+    if (reset) begin
+      wrbuf_addr <= 32'h0;
+    end else begin
+      wrbuf_addr <= io_dma_axi_awaddr;
+    end
+  end
+  always @(posedge rvclkhdr_12_io_l1clk or posedge reset) begin
+    if (reset) begin
+      rdbuf_addr <= 32'h0;
+    end else begin
+      rdbuf_addr <= io_dma_axi_araddr;
+    end
+  end
+  always @(posedge dma_bus_clk or posedge reset) begin
+    if (reset) begin
+      wrbuf_byteen <= 8'h0;
+    end else if (wrbuf_data_en) begin
+      wrbuf_byteen <= io_dma_axi_wstrb;
+    end
+  end
+  always @(posedge dma_bus_clk or posedge reset) begin
+    if (reset) begin
+      wrbuf_sz <= 3'h0;
+    end else if (wrbuf_en) begin
+      wrbuf_sz <= io_dma_axi_awsize;
+    end
+  end
+  always @(posedge dma_bus_clk or posedge reset) begin
+    if (reset) begin
+      rdbuf_sz <= 3'h0;
+    end else if (rdbuf_en) begin
+      rdbuf_sz <= io_dma_axi_arsize;
+    end
+  end
+  always @(posedge dma_bus_clk or posedge reset) begin
+    if (reset) begin
+      fifo_full <= 1'h0;
+    end else begin
+      fifo_full <= num_fifo_vld_tmp2 >= 4'h5;
+    end
+  end
+  always @(posedge dma_bus_clk or posedge reset) begin
+    if (reset) begin
+      dbg_dma_bubble_bus <= 1'h0;
+    end else begin
+      dbg_dma_bubble_bus <= io_dbg_dma_bubble;
+    end
+  end
+  always @(posedge dma_free_clk or posedge reset) begin
+    if (reset) begin
+      WrPtr <= 3'h0;
+    end else if (WrPtrEn) begin
+      if (_T_931) begin
+        WrPtr <= 3'h0;
+      end else begin
+        WrPtr <= _T_934;
+      end
+    end
+  end
+  always @(posedge dma_free_clk or posedge reset) begin
+    if (reset) begin
+      _T_598 <= 1'h0;
+    end else begin
+      _T_598 <= _T_594 & _T_596;
+    end
+  end
+  always @(posedge dma_free_clk or posedge reset) begin
+    if (reset) begin
+      _T_591 <= 1'h0;
+    end else begin
+      _T_591 <= _T_587 & _T_589;
+    end
+  end
+  always @(posedge dma_free_clk or posedge reset) begin
+    if (reset) begin
+      _T_584 <= 1'h0;
+    end else begin
+      _T_584 <= _T_580 & _T_582;
+    end
+  end
+  always @(posedge dma_free_clk or posedge reset) begin
+    if (reset) begin
+      _T_577 <= 1'h0;
+    end else begin
+      _T_577 <= _T_573 & _T_575;
+    end
+  end
+  always @(posedge dma_free_clk or posedge reset) begin
+    if (reset) begin
+      _T_570 <= 1'h0;
+    end else begin
+      _T_570 <= _T_566 & _T_568;
+    end
+  end
+  always @(posedge dma_free_clk or posedge reset) begin
+    if (reset) begin
+      _T_760 <= 1'h0;
+    end else begin
+      _T_760 <= _T_399 & _T_596;
+    end
+  end
+  always @(posedge dma_free_clk or posedge reset) begin
+    if (reset) begin
+      _T_753 <= 1'h0;
+    end else begin
+      _T_753 <= _T_395 & _T_589;
+    end
+  end
+  always @(posedge dma_free_clk or posedge reset) begin
+    if (reset) begin
+      _T_746 <= 1'h0;
+    end else begin
+      _T_746 <= _T_391 & _T_582;
+    end
+  end
+  always @(posedge dma_free_clk or posedge reset) begin
+    if (reset) begin
+      _T_739 <= 1'h0;
+    end else begin
+      _T_739 <= _T_387 & _T_575;
+    end
+  end
+  always @(posedge dma_free_clk or posedge reset) begin
+    if (reset) begin
+      _T_732 <= 1'h0;
+    end else begin
+      _T_732 <= _T_383 & _T_568;
+    end
+  end
+  always @(posedge dma_buffer_c1_clk or posedge reset) begin
+    if (reset) begin
+      _T_886 <= 1'h0;
+    end else if (fifo_cmd_en[4]) begin
+      _T_886 <= io_dbg_cmd_valid;
+    end
+  end
+  always @(posedge dma_buffer_c1_clk or posedge reset) begin
+    if (reset) begin
+      _T_884 <= 1'h0;
+    end else if (fifo_cmd_en[3]) begin
+      _T_884 <= io_dbg_cmd_valid;
+    end
+  end
+  always @(posedge dma_buffer_c1_clk or posedge reset) begin
+    if (reset) begin
+      _T_882 <= 1'h0;
+    end else if (fifo_cmd_en[2]) begin
+      _T_882 <= io_dbg_cmd_valid;
+    end
+  end
+  always @(posedge dma_buffer_c1_clk or posedge reset) begin
+    if (reset) begin
+      _T_880 <= 1'h0;
+    end else if (fifo_cmd_en[1]) begin
+      _T_880 <= io_dbg_cmd_valid;
+    end
+  end
+  always @(posedge dma_buffer_c1_clk or posedge reset) begin
+    if (reset) begin
+      _T_878 <= 1'h0;
+    end else if (fifo_cmd_en[0]) begin
+      _T_878 <= io_dbg_cmd_valid;
+    end
+  end
+  always @(posedge dma_buffer_c1_clk or posedge reset) begin
+    if (reset) begin
+      fifo_sz_4 <= 3'h0;
+    end else if (fifo_cmd_en[4]) begin
+      if (io_dbg_cmd_valid) begin
+        fifo_sz_4 <= _T_23;
+      end else if (axi_mstr_sel) begin
+        fifo_sz_4 <= wrbuf_sz;
+      end else begin
+        fifo_sz_4 <= rdbuf_sz;
+      end
+    end
+  end
+  always @(posedge dma_buffer_c1_clk or posedge reset) begin
+    if (reset) begin
+      fifo_sz_3 <= 3'h0;
+    end else if (fifo_cmd_en[3]) begin
+      if (io_dbg_cmd_valid) begin
+        fifo_sz_3 <= _T_23;
+      end else if (axi_mstr_sel) begin
+        fifo_sz_3 <= wrbuf_sz;
+      end else begin
+        fifo_sz_3 <= rdbuf_sz;
+      end
+    end
+  end
+  always @(posedge dma_buffer_c1_clk or posedge reset) begin
+    if (reset) begin
+      fifo_sz_2 <= 3'h0;
+    end else if (fifo_cmd_en[2]) begin
+      if (io_dbg_cmd_valid) begin
+        fifo_sz_2 <= _T_23;
+      end else if (axi_mstr_sel) begin
+        fifo_sz_2 <= wrbuf_sz;
+      end else begin
+        fifo_sz_2 <= rdbuf_sz;
+      end
+    end
+  end
+  always @(posedge dma_buffer_c1_clk or posedge reset) begin
+    if (reset) begin
+      fifo_sz_1 <= 3'h0;
+    end else if (fifo_cmd_en[1]) begin
+      if (io_dbg_cmd_valid) begin
+        fifo_sz_1 <= _T_23;
+      end else if (axi_mstr_sel) begin
+        fifo_sz_1 <= wrbuf_sz;
+      end else begin
+        fifo_sz_1 <= rdbuf_sz;
+      end
+    end
+  end
+  always @(posedge dma_buffer_c1_clk or posedge reset) begin
+    if (reset) begin
+      fifo_sz_0 <= 3'h0;
+    end else if (fifo_cmd_en[0]) begin
+      fifo_sz_0 <= fifo_sz_in;
+    end
+  end
+  always @(posedge dma_buffer_c1_clk or posedge reset) begin
+    if (reset) begin
+      fifo_byteen_4 <= 8'h0;
+    end else if (fifo_cmd_en[4]) begin
+      fifo_byteen_4 <= fifo_byteen_in;
+    end
+  end
+  always @(posedge dma_buffer_c1_clk or posedge reset) begin
+    if (reset) begin
+      fifo_byteen_3 <= 8'h0;
+    end else if (fifo_cmd_en[3]) begin
+      fifo_byteen_3 <= fifo_byteen_in;
+    end
+  end
+  always @(posedge dma_buffer_c1_clk or posedge reset) begin
+    if (reset) begin
+      fifo_byteen_2 <= 8'h0;
+    end else if (fifo_cmd_en[2]) begin
+      fifo_byteen_2 <= fifo_byteen_in;
+    end
+  end
+  always @(posedge dma_buffer_c1_clk or posedge reset) begin
+    if (reset) begin
+      fifo_byteen_1 <= 8'h0;
+    end else if (fifo_cmd_en[1]) begin
+      fifo_byteen_1 <= fifo_byteen_in;
+    end
+  end
+  always @(posedge dma_buffer_c1_clk or posedge reset) begin
+    if (reset) begin
+      fifo_byteen_0 <= 8'h0;
+    end else if (fifo_cmd_en[0]) begin
+      fifo_byteen_0 <= fifo_byteen_in;
+    end
+  end
+  always @(posedge dma_free_clk or posedge reset) begin
+    if (reset) begin
+      fifo_error_0 <= 2'h0;
+    end else begin
+      fifo_error_0 <= _T_605 & _T_609;
+    end
+  end
+  always @(posedge dma_free_clk or posedge reset) begin
+    if (reset) begin
+      fifo_error_1 <= 2'h0;
+    end else begin
+      fifo_error_1 <= _T_614 & _T_618;
+    end
+  end
+  always @(posedge dma_free_clk or posedge reset) begin
+    if (reset) begin
+      fifo_error_2 <= 2'h0;
+    end else begin
+      fifo_error_2 <= _T_623 & _T_627;
+    end
+  end
+  always @(posedge dma_free_clk or posedge reset) begin
+    if (reset) begin
+      fifo_error_3 <= 2'h0;
+    end else begin
+      fifo_error_3 <= _T_632 & _T_636;
+    end
+  end
+  always @(posedge dma_free_clk or posedge reset) begin
+    if (reset) begin
+      fifo_error_4 <= 2'h0;
+    end else begin
+      fifo_error_4 <= _T_641 & _T_645;
+    end
+  end
+  always @(posedge dma_free_clk or posedge reset) begin
+    if (reset) begin
+      RspPtr <= 3'h0;
+    end else if (RspPtrEn) begin
+      if (_T_941) begin
+        RspPtr <= 3'h0;
+      end else begin
+        RspPtr <= _T_944;
+      end
+    end
+  end
+  always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin
+    if (reset) begin
+      wrbuf_data <= 64'h0;
+    end else begin
+      wrbuf_data <= io_dma_axi_wdata;
+    end
+  end
+  always @(posedge dma_free_clk or posedge reset) begin
+    if (reset) begin
+      _T_721 <= 1'h0;
+    end else begin
+      _T_721 <= _T_717 & _T_596;
+    end
+  end
+  always @(posedge dma_free_clk or posedge reset) begin
+    if (reset) begin
+      _T_714 <= 1'h0;
+    end else begin
+      _T_714 <= _T_710 & _T_589;
+    end
+  end
+  always @(posedge dma_free_clk or posedge reset) begin
+    if (reset) begin
+      _T_707 <= 1'h0;
+    end else begin
+      _T_707 <= _T_703 & _T_582;
+    end
+  end
+  always @(posedge dma_free_clk or posedge reset) begin
+    if (reset) begin
+      _T_700 <= 1'h0;
+    end else begin
+      _T_700 <= _T_696 & _T_575;
+    end
+  end
+  always @(posedge dma_free_clk or posedge reset) begin
+    if (reset) begin
+      _T_693 <= 1'h0;
+    end else begin
+      _T_693 <= _T_689 & _T_568;
+    end
+  end
+  always @(posedge dma_free_clk or posedge reset) begin
+    if (reset) begin
+      _T_799 <= 1'h0;
+    end else begin
+      _T_799 <= _T_795 & _T_596;
+    end
+  end
+  always @(posedge dma_free_clk or posedge reset) begin
+    if (reset) begin
+      _T_792 <= 1'h0;
+    end else begin
+      _T_792 <= _T_788 & _T_589;
+    end
+  end
+  always @(posedge dma_free_clk or posedge reset) begin
+    if (reset) begin
+      _T_785 <= 1'h0;
+    end else begin
+      _T_785 <= _T_781 & _T_582;
+    end
+  end
+  always @(posedge dma_free_clk or posedge reset) begin
+    if (reset) begin
+      _T_778 <= 1'h0;
+    end else begin
+      _T_778 <= _T_774 & _T_575;
+    end
+  end
+  always @(posedge dma_free_clk or posedge reset) begin
+    if (reset) begin
+      _T_771 <= 1'h0;
+    end else begin
+      _T_771 <= _T_767 & _T_568;
+    end
+  end
+  always @(posedge dma_buffer_c1_clk or posedge reset) begin
+    if (reset) begin
+      _T_850 <= 1'h0;
+    end else if (fifo_cmd_en[0]) begin
+      if (io_dbg_cmd_valid) begin
+        _T_850 <= io_dbg_cmd_write;
+      end else if (_T_1241) begin
+        _T_850 <= axi_mstr_priority;
+      end else begin
+        _T_850 <= _T_1240;
+      end
+    end
+  end
+  always @(posedge dma_buffer_c1_clk or posedge reset) begin
+    if (reset) begin
+      _T_852 <= 1'h0;
+    end else if (fifo_cmd_en[1]) begin
+      if (io_dbg_cmd_valid) begin
+        _T_852 <= io_dbg_cmd_write;
+      end else if (_T_1241) begin
+        _T_852 <= axi_mstr_priority;
+      end else begin
+        _T_852 <= _T_1240;
+      end
+    end
+  end
+  always @(posedge dma_buffer_c1_clk or posedge reset) begin
+    if (reset) begin
+      _T_854 <= 1'h0;
+    end else if (fifo_cmd_en[2]) begin
+      if (io_dbg_cmd_valid) begin
+        _T_854 <= io_dbg_cmd_write;
+      end else if (_T_1241) begin
+        _T_854 <= axi_mstr_priority;
+      end else begin
+        _T_854 <= _T_1240;
+      end
+    end
+  end
+  always @(posedge dma_buffer_c1_clk or posedge reset) begin
+    if (reset) begin
+      _T_856 <= 1'h0;
+    end else if (fifo_cmd_en[3]) begin
+      if (io_dbg_cmd_valid) begin
+        _T_856 <= io_dbg_cmd_write;
+      end else if (_T_1241) begin
+        _T_856 <= axi_mstr_priority;
+      end else begin
+        _T_856 <= _T_1240;
+      end
+    end
+  end
+  always @(posedge dma_buffer_c1_clk or posedge reset) begin
+    if (reset) begin
+      _T_858 <= 1'h0;
+    end else if (fifo_cmd_en[4]) begin
+      _T_858 <= fifo_write_in;
+    end
+  end
+  always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin
+    if (reset) begin
+      fifo_data_0 <= 64'h0;
+    end else if (_T_491) begin
+      fifo_data_0 <= _T_493;
+    end else if (_T_84) begin
+      fifo_data_0 <= io_dccm_dma_rdata;
+    end else if (_T_87) begin
+      fifo_data_0 <= io_iccm_dma_rdata;
+    end else if (io_dbg_cmd_valid) begin
+      fifo_data_0 <= _T_498;
+    end else begin
+      fifo_data_0 <= wrbuf_data;
+    end
+  end
+  always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin
+    if (reset) begin
+      fifo_data_1 <= 64'h0;
+    end else if (_T_506) begin
+      fifo_data_1 <= _T_508;
+    end else if (_T_102) begin
+      fifo_data_1 <= io_dccm_dma_rdata;
+    end else if (_T_105) begin
+      fifo_data_1 <= io_iccm_dma_rdata;
+    end else if (io_dbg_cmd_valid) begin
+      fifo_data_1 <= _T_498;
+    end else begin
+      fifo_data_1 <= wrbuf_data;
+    end
+  end
+  always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
+    if (reset) begin
+      fifo_data_2 <= 64'h0;
+    end else if (_T_521) begin
+      fifo_data_2 <= _T_523;
+    end else if (_T_120) begin
+      fifo_data_2 <= io_dccm_dma_rdata;
+    end else if (_T_123) begin
+      fifo_data_2 <= io_iccm_dma_rdata;
+    end else if (io_dbg_cmd_valid) begin
+      fifo_data_2 <= _T_498;
+    end else begin
+      fifo_data_2 <= wrbuf_data;
+    end
+  end
+  always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
+    if (reset) begin
+      fifo_data_3 <= 64'h0;
+    end else if (_T_536) begin
+      fifo_data_3 <= _T_538;
+    end else if (_T_138) begin
+      fifo_data_3 <= io_dccm_dma_rdata;
+    end else if (_T_141) begin
+      fifo_data_3 <= io_iccm_dma_rdata;
+    end else if (io_dbg_cmd_valid) begin
+      fifo_data_3 <= _T_498;
+    end else begin
+      fifo_data_3 <= wrbuf_data;
+    end
+  end
+  always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin
+    if (reset) begin
+      fifo_data_4 <= 64'h0;
+    end else if (_T_551) begin
+      fifo_data_4 <= _T_553;
+    end else if (_T_156) begin
+      fifo_data_4 <= io_dccm_dma_rdata;
+    end else if (_T_159) begin
+      fifo_data_4 <= io_iccm_dma_rdata;
+    end else begin
+      fifo_data_4 <= _T_500;
+    end
+  end
+  always @(posedge dma_buffer_c1_clk or posedge reset) begin
+    if (reset) begin
+      fifo_tag_0 <= 1'h0;
+    end else if (fifo_cmd_en[0]) begin
+      if (axi_mstr_sel) begin
+        fifo_tag_0 <= wrbuf_tag;
+      end else begin
+        fifo_tag_0 <= rdbuf_tag;
+      end
+    end
+  end
+  always @(posedge dma_bus_clk or posedge reset) begin
+    if (reset) begin
+      wrbuf_tag <= 1'h0;
+    end else if (wrbuf_en) begin
+      wrbuf_tag <= io_dma_axi_awid;
+    end
+  end
+  always @(posedge dma_bus_clk or posedge reset) begin
+    if (reset) begin
+      rdbuf_tag <= 1'h0;
+    end else if (rdbuf_en) begin
+      rdbuf_tag <= io_dma_axi_arid;
+    end
+  end
+  always @(posedge dma_buffer_c1_clk or posedge reset) begin
+    if (reset) begin
+      fifo_tag_1 <= 1'h0;
+    end else if (fifo_cmd_en[1]) begin
+      if (axi_mstr_sel) begin
+        fifo_tag_1 <= wrbuf_tag;
+      end else begin
+        fifo_tag_1 <= rdbuf_tag;
+      end
+    end
+  end
+  always @(posedge dma_buffer_c1_clk or posedge reset) begin
+    if (reset) begin
+      fifo_tag_2 <= 1'h0;
+    end else if (fifo_cmd_en[2]) begin
+      if (axi_mstr_sel) begin
+        fifo_tag_2 <= wrbuf_tag;
+      end else begin
+        fifo_tag_2 <= rdbuf_tag;
+      end
+    end
+  end
+  always @(posedge dma_buffer_c1_clk or posedge reset) begin
+    if (reset) begin
+      fifo_tag_3 <= 1'h0;
+    end else if (fifo_cmd_en[3]) begin
+      if (axi_mstr_sel) begin
+        fifo_tag_3 <= wrbuf_tag;
+      end else begin
+        fifo_tag_3 <= rdbuf_tag;
+      end
+    end
+  end
+  always @(posedge dma_buffer_c1_clk or posedge reset) begin
+    if (reset) begin
+      fifo_tag_4 <= 1'h0;
+    end else if (fifo_cmd_en[4]) begin
+      fifo_tag_4 <= bus_cmd_tag;
+    end
+  end
+  always @(posedge dma_free_clk or posedge reset) begin
+    if (reset) begin
+      dma_nack_count <= 3'h0;
+    end else if (dma_mem_req) begin
+      if (_T_1118) begin
+        dma_nack_count <= _T_1131;
+      end else if (_T_1135) begin
+        dma_nack_count <= _T_1138;
+      end else begin
+        dma_nack_count <= 3'h0;
+      end
+    end
+  end
+  always @(posedge io_free_clk or posedge reset) begin
+    if (reset) begin
+      dma_dbg_cmd_done_q <= 1'h0;
+    end else begin
+      dma_dbg_cmd_done_q <= io_dma_dbg_cmd_done;
+    end
+  end
+endmodule
diff --git a/src/main/scala/dmi/dmi_jtag_to_core_sync.scala b/src/main/scala/dmi/dmi_jtag_to_core_sync.scala
index b866beb9..0631df2d 100644
--- a/src/main/scala/dmi/dmi_jtag_to_core_sync.scala
+++ b/src/main/scala/dmi/dmi_jtag_to_core_sync.scala
@@ -1,5 +1,37 @@
 package dmi
+import chisel3._
+import scala.collection._
+import chisel3.util._
+import include._
+import lib._
 
-class dmi_jtag_to_core_sync {
+class dmi_jtag_to_core_sync extends Module with el2_lib with RequireAsyncReset {
+  val io = IO(new Bundle{
+    // JTAG signals
+    val rd_en = Input(UInt(1.W))// 1 bit  Read Enable from JTAG
+    val wr_en = Input(UInt(1.W))// 1 bit  Write enable from JTAG
 
+    // Processor Signals
+    // val rst_n = Input(Bool())      // Core reset
+    // val clk  = Input(Bool())      // Core clock
+    val reg_en    = Output(UInt(1.W))  // 1 bit  Write interface bit to Processor
+    val reg_wr_en = Output(UInt(1.W))  // 1 bit  Write enable to Processor
+  })
+  val c_rd_en    =WireInit(0.U(1.W))
+  val c_wr_en    =WireInit(0.U(1.W))
+  val rden       =WireInit(0.U(3.W))
+  val wren       =WireInit(0.U(3.W))
+
+  // synchronizers
+  rden := RegNext(Cat(rden(1,0),io.rd_en),0.U)
+  wren := RegNext(Cat(wren(1,0),io.wr_en),0.U)
+  c_rd_en := rden(1) & !rden(2)
+  c_wr_en := wren(1) & !wren(2)
+  // Outputs
+  io.reg_en     := c_wr_en | c_rd_en
+  io.reg_wr_en  := c_wr_en
+}
+object dmijtag_main extends App{
+  println("Generate Verilog")
+  println((new chisel3.stage.ChiselStage).emitVerilog(new dmi_jtag_to_core_sync()))
 }
diff --git a/src/main/scala/dmi/dmi_wrapper.scala b/src/main/scala/dmi/dmi_wrapper.scala
index 2766360f..61ea9e78 100644
--- a/src/main/scala/dmi/dmi_wrapper.scala
+++ b/src/main/scala/dmi/dmi_wrapper.scala
@@ -1,5 +1,65 @@
 package dmi
+import chisel3._
+import scala.collection._
+import chisel3.util._
+import include._
+import lib._
 
-class dmi_wrapper {
+class dmi_wrapper extends Module with el2_lib with RequireAsyncReset {
+  val io = IO(new Bundle{
+    // JTAG signals
+    val trst_n      = Input(AsyncReset())
+    val tck       = Input(Clock())             // JTAG clock
+    val tms       =Input(UInt(1.W))             // Test mode select
+    val tdi       =Input(UInt(1.W))             // Test Data Input
+    val tdo       =Output(UInt(1.W))          // Test Data Output
+    val tdoEnable =Output(UInt(1.W))           // Test Data Output enable
 
+    // Processor Signals
+    // val              core_rst_n =Input(UInt(1.W))          // Core reset
+    //  val              core_clk   =Input(UInt(1.W))         // Core clock
+    val jtag_id        = Input(UInt(32.W))         // JTAG ID
+    val rd_data        = Input(UInt(32.W))         // 32 bit Read data from  Processor
+    val reg_wr_data    = Output(UInt(32.W))      // 32 bit Write data to Processor
+    val reg_wr_addr    = Output(UInt(7.W))       // 7 bit reg address to Processor
+    val reg_en         = Output(UInt(1.W))      // 1 bit  Read enable to Processor
+    val reg_wr_en      = Output(UInt(1.W))      // 1 bit  Write enable to Processor
+    val dmi_hard_reset = Output(UInt(1.W))
+  })
+  //Wire Declaration
+  val rd_en    = WireInit(0.U(1.W))
+  val wr_en    = WireInit(0.U(1.W))
+  val dmireset = WireInit(0.U(1.W))
+
+  //jtag_tap instantiation
+  val  i_jtag_tap = Module(new rvjtag_tap())
+  i_jtag_tap.io.trst      := io.trst_n                      // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset
+  i_jtag_tap.io.tck       := io.tck                          // dedicated JTAG TCK pad signal
+  i_jtag_tap.io.tms       := io.tms                          // dedicated JTAG TMS pad signal
+  i_jtag_tap.io.tdi       := io.tdi                          // dedicated JTAG TDI pad signal
+  io.tdo                  := i_jtag_tap.io.tdo                          // dedicated JTAG TDO pad signal
+  io.tdoEnable            := i_jtag_tap.io.tdoEnable              // enable for TDO pad
+  io.reg_wr_data          := i_jtag_tap.io.wr_data              // 32 bit Write data
+  io.reg_wr_addr          := i_jtag_tap.io.wr_addr              // 7 bit Write address
+  rd_en                   := i_jtag_tap.io.rd_en                      // 1 bit  read enable
+  wr_en                   := i_jtag_tap.io.wr_en                      // 1 bit  Write enable
+  i_jtag_tap.io.rd_data   := io.rd_data                  // 32 bit Read data
+  i_jtag_tap.io.rd_status := 0.U(2.W)
+  i_jtag_tap.io.idle      := 0.U(3.W)                         // no need to wait to sample data
+  i_jtag_tap.io.dmi_stat  := 0.U(2.W)                     // no need to wait or error possible
+  i_jtag_tap.io.version   := 1.U(4.W)                      // debug spec 0.13 compliant
+  i_jtag_tap.io.jtag_id   := io.jtag_id
+  io.dmi_hard_reset       := i_jtag_tap.io.dmi_hard_reset
+  dmireset               := i_jtag_tap.io.dmi_reset
+
+  // dmi_jtag_to_core_sync instantiation
+  val i_dmi_jtag_to_core_sync = Module(new dmi_jtag_to_core_sync())
+  i_dmi_jtag_to_core_sync.io.wr_en := wr_en  // 1 bit  Write enable
+  i_dmi_jtag_to_core_sync.io.rd_en := rd_en  // 1 bit  Read enable
+  io.reg_en    :=i_dmi_jtag_to_core_sync.io.reg_en        // 1 bit  Write interface bit
+  io.reg_wr_en := i_dmi_jtag_to_core_sync.io.reg_wr_en    // 1 bit  Write enable
+}
+object dmiwrapper_main extends App{
+  println("Generate Verilog")
+  println((new chisel3.stage.ChiselStage).emitVerilog(new dmi_wrapper()))
 }
diff --git a/src/main/scala/dmi/rvjtag_tap.scala b/src/main/scala/dmi/rvjtag_tap.scala
index 731d212b..12b9d7dc 100644
--- a/src/main/scala/dmi/rvjtag_tap.scala
+++ b/src/main/scala/dmi/rvjtag_tap.scala
@@ -1,5 +1,122 @@
 package dmi
+import chisel3._
+import chisel3.util._
+import include._
+import lib._
 
-class rvjtag_tap {
+class rvjtag_tap extends Module with el2_lib with RequireAsyncReset {
+  val io = IO(new Bundle{
+    val trst            = Input(AsyncReset())
+    val tck             = Input(Clock())
+    val tms             = Input(Bool())
+    val tdi             = Input(Bool())
+    val dmi_reset       = Output(Bool())
+    val dmi_hard_reset  = Output(Bool())
+    val rd_status       = Input(UInt(2.W))
+    val dmi_stat        = Input(UInt(2.W))
+    val idle            = Input(UInt(3.W))
+    val  version        = Input(UInt(4.W))
+    val jtag_id         = Input(UInt(31.W))
+    val rd_data         = Input(UInt(32.W))
+
+    val tdo             = Output(Bool())
+    val tdoEnable       = Output(Bool())
+    val wr_en           = Output(Bool())
+    val rd_en           = Output(Bool())
+    val wr_data         = Output(UInt(32.W))
+    val wr_addr         = Output(UInt(AWIDTH.W))
+  })
+  val AWIDTH = 7
+  val USER_DR_LENGTH = AWIDTH + 34
+  val nsr = WireInit(0.U(USER_DR_LENGTH.W))
+  val sr = withClockAndReset (io.tck,io.trst) {RegNext(nsr,0.U)}
+  val dr  = WireInit(0.U(USER_DR_LENGTH.W))
+  ///////////////////////////////////////////////////////
+  //                      Tap controller
+  ///////////////////////////////////////////////////////
+  val test_logic_reset_state :: run_test_idle_state :: select_dr_scan_state :: capture_dr_state :: shift_dr_state :: exit1_dr_state :: pause_dr_state :: exit2_dr_state :: update_dr_state :: select_ir_scan_state :: capture_ir_state :: shift_ir_state :: exit1_ir_state :: pause_ir_state :: exit2_ir_state :: update_ir_state :: Nil = Enum(16)
+  val nstate                = WireInit(test_logic_reset_state)
+  val state = withClockAndReset(io.tck,io.trst) {RegNext(nstate,test_logic_reset_state)}
+  val ir          = WireInit(0.U(5.W))
+  val jtag_reset  = WireInit(Bool(),false.B)
+  val shift_dr    = WireInit(UInt(1.W),init = 0.U)
+  val pause_dr    = WireInit(UInt(1.W),init = 0.U)
+  val update_dr   = WireInit(Bool(),false.B)
+  val capture_dr  = WireInit(UInt(1.W),init = 0.U)
+  val shift_ir    = WireInit(UInt(1.W),init = 0.U)
+  val pause_ir    = WireInit(UInt(1.W),init = 0.U)
+  val update_ir   = WireInit(Bool(),false.B)
+  val capture_ir  = WireInit(UInt(1.W),init = 0.U)
+  val dr_en       = WireInit(UInt(2.W),init = 0.U)
+  val devid_sel   = WireInit(Bool(),false.B)
+  val abits       = AWIDTH.U(6.W)
+
+  switch (state) {
+    is(test_logic_reset_state) {nstate := Mux(io.tms, test_logic_reset_state, run_test_idle_state)
+      jtag_reset := 1.U }
+    is(run_test_idle_state)     {nstate := Mux(io.tms,select_dr_scan_state,run_test_idle_state) }
+    is(select_dr_scan_state)    {nstate := Mux(io.tms,select_ir_scan_state,capture_dr_state) }
+    is(capture_dr_state)        {nstate := Mux(io.tms,exit1_dr_state,shift_dr_state)
+      capture_dr := 1.U }
+    is(shift_dr_state)          {nstate := Mux(io.tms,exit1_dr_state,shift_dr_state)
+      shift_dr := 1.U }
+    is(exit1_dr_state)          {nstate := Mux(io.tms,update_dr_state,pause_dr_state) }
+    is(pause_dr_state)          {nstate := Mux(io.tms,exit2_dr_state,pause_dr_state)
+      pause_dr := 1.U }
+    is(exit2_dr_state)          {nstate := Mux(io.tms,update_dr_state,shift_dr_state) }
+    is(update_dr_state)         {nstate := Mux(io.tms,select_dr_scan_state,run_test_idle_state)
+      update_dr := 1.U }
+    is(select_ir_scan_state)    {nstate := Mux(io.tms,test_logic_reset_state,capture_ir_state) }
+    is(capture_ir_state)        {nstate := Mux(io.tms,exit1_ir_state,shift_ir_state)
+      capture_ir := 1.U }
+    is(shift_ir_state)          {nstate := Mux(io.tms,exit1_ir_state,shift_ir_state)
+      shift_ir := 1.U }
+    is(exit1_ir_state)          {nstate := Mux(io.tms,update_ir_state,pause_ir_state) }
+    is(pause_ir_state)          {nstate := Mux(io.tms,exit2_ir_state,pause_ir_state)
+      pause_ir := 1.U }
+    is(exit2_ir_state)          {nstate := Mux(io.tms,update_ir_state,shift_ir_state) }
+    is(update_ir_state)         {nstate := Mux(io.tms,select_dr_scan_state,run_test_idle_state)
+      update_ir := 1.U }
+  }
+  io.tdoEnable := shift_dr | shift_ir
+  ///////////////////////////////////////////////////////
+  //                      IR register
+  //////////////////////////////////////////////////////
+  ir :=  withClockAndReset(io.tck,io.trst) {RegNext(Mux(jtag_reset,1.U,Mux(update_ir,Mux((sr(4,0)===0.U).asBool,"h1f".U,sr(4,0)),0.U)),1.U)}
+  devid_sel := ir==="b00001".U(5.W)
+  dr_en     := Cat(ir===17.U,ir===16.U)
+  ///////////////////////////////////////////////////////
+  //                      Shift register
+  ///////////////////////////////////////////////////////
+
+  when(shift_dr===1.U){
+    when(dr_en(1)===true.B){nsr :=Cat(io.tdi, sr(USER_DR_LENGTH-1,1))}
+      .elsewhen(dr_en(0)===1.U || devid_sel===true.B){nsr := Cat(Fill(USER_DR_LENGTH-32,0.U) , io.tdi, sr(31,1))}
+      .otherwise{nsr := Cat(Fill(USER_DR_LENGTH-1,0.U),io.tdi)} // bypass
+  }
+    .elsewhen(capture_dr ===1.U){
+      when(dr_en(0)){nsr := Cat(Fill(USER_DR_LENGTH-15,0.U) ,io.idle, io.dmi_stat,abits,io.version)}
+        .elsewhen(dr_en(1)){nsr := Cat(Fill(AWIDTH,0.U),io.rd_data,io.rd_status)}
+        .elsewhen(devid_sel){nsr := Cat(Fill(USER_DR_LENGTH-32,0.U),io.jtag_id,1.U)}
+    }
+    .elsewhen(shift_ir===1.U){nsr := Cat(Fill(USER_DR_LENGTH-5,0.U),io.tdi,sr(4,1))}
+    .elsewhen(capture_ir===1.U){nsr := Cat(Fill(USER_DR_LENGTH-1,0.U),1.U)}
+
+  // TDO retiming
+  withClock(io.tck) {io.tdo:=RegNext(sr(0),0.U)}
+  // DMI CS register
+  withClockAndReset (io.tck,io.trst) {io.dmi_hard_reset := RegNext(Mux(update_dr & dr_en(0).asBool(),sr(17),0.U),0.U)}
+  withClockAndReset (io.tck,io.trst) {io.dmi_reset := RegNext(Mux(update_dr & dr_en(0).asBool(),sr(16),0.U),0.U)}
+  // DR register
+  withClockAndReset (io.tck,io.trst) {dr := RegNext(Mux(update_dr & dr_en(1).asBool(),sr,Cat(dr(USER_DR_LENGTH-1,2),0.U(2.W))),0.U)}
+
+  io.rd_en   := dr(0)
+  io.wr_en   := dr(1)
+  io.wr_data := dr(33,2)
+  io.wr_addr := dr(40,34)
 
 }
+object tapmain extends App{
+  println("Generate Verilog")
+  println((new chisel3.stage.ChiselStage).emitVerilog(new rvjtag_tap()))
+}
diff --git a/src/main/scala/el2_dma_ctrl.scala b/src/main/scala/el2_dma_ctrl.scala
new file mode 100644
index 00000000..b6477c72
--- /dev/null
+++ b/src/main/scala/el2_dma_ctrl.scala
@@ -0,0 +1,558 @@
+package dma
+import chisel3._
+import chisel3.util._
+import scala.collection._
+import lib._
+
+class el2_dma_ctrl extends Module with el2_lib with RequireAsyncReset {
+  val io = IO(new Bundle {
+    val free_clk              = Input(Clock())
+    val rst_l                 = Input(Bool())
+    val dma_bus_clk_en        = Input(Bool())     // slave bus clock enable
+    val clk_override          = Input(Bool())
+    val scan_mode             = Input(Bool())
+
+    // Debug signals      
+    val dbg_cmd_addr          = Input(UInt(32.W))
+    val dbg_cmd_wrdata        = Input(UInt(32.W))
+    val dbg_cmd_valid         = Input(Bool())
+    val dbg_cmd_write         = Input(Bool())     // 1: write command, 0: read_command
+    val dbg_cmd_type          = Input(UInt(2.W))  // 0:gpr 1:csr 2: memory
+    val dbg_cmd_size          = Input(UInt(2.W))  // size of the abstract mem access debug command
+
+    val dbg_dma_bubble        = Input(Bool())     // Debug needs a bubble to send a valid
+    val dma_dbg_ready         = Output(Bool())    // DMA is ready to accept debug request
+    val dma_dbg_cmd_done      = Output(Bool())
+    val dma_dbg_cmd_fail      = Output(Bool())
+    val dma_dbg_rddata        = Output(UInt(32.W))
+
+    // Core side signals    
+    val dma_dccm_req          = Output(Bool())    // DMA dccm request (only one of dccm/iccm will be set)
+    val dma_iccm_req          = Output(Bool())    // DMA iccm request
+    val dma_mem_tag           = Output(UInt(3.W)) // DMA Buffer entry number
+    val dma_mem_addr          = Output(UInt(32.W))// DMA request address
+    val dma_mem_sz            = Output(UInt(3.W)) // DMA request size
+    val dma_mem_write         = Output(Bool())    // DMA write to dccm/iccm
+    val dma_mem_wdata         = Output(UInt(64.W))// DMA write data
+    val dccm_dma_rvalid       = Input(Bool())     // dccm data valid for DMA read
+    val dccm_dma_ecc_error    = Input(Bool())     // ECC error on DMA read
+    val dccm_dma_rtag         = Input(UInt(3.W))  // Tag of the DMA req
+    val dccm_dma_rdata        = Input(UInt(64.W)) // dccm data for DMA read
+    val iccm_dma_rvalid       = Input(Bool())     // iccm data valid for DMA read
+    val iccm_dma_ecc_error    = Input(Bool())     // ECC error on DMA read
+    val iccm_dma_rtag         = Input(UInt(3.W))  // Tag of the DMA req
+    val iccm_dma_rdata        = Input(UInt(64.W)) // iccm data for DMA read
+
+    val dma_dccm_stall_any    = Output(Bool())    // stall dccm pipe (bubble) so that DMA can proceed
+    val dma_iccm_stall_any    = Output(Bool())    // stall iccm pipe (bubble) so that DMA can proceed
+    val dccm_ready            = Input(Bool())     // dccm ready to accept DMA request
+    val iccm_ready            = Input(Bool())     // iccm ready to accept DMA request
+    val dec_tlu_dma_qos_prty  = Input(UInt(3.W))  // DMA QoS priority coming from MFDC [18:15]
+
+    // PMU signals
+    val dma_pmu_dccm_read     = Output(Bool())
+    val dma_pmu_dccm_write    = Output(Bool())
+    val dma_pmu_any_read      = Output(Bool())
+    val dma_pmu_any_write     = Output(Bool())
+
+    // AXI Write Channels
+    val dma_axi_awvalid       = Input(Bool())
+    val dma_axi_awready       = Output(Bool())
+    val dma_axi_awid          = Input(UInt(DMA_BUS_TAG.W))
+    val dma_axi_awaddr        = Input(UInt(32.W))
+    val dma_axi_awsize        = Input(UInt(3.W))
+
+    val dma_axi_wvalid        = Input(Bool())
+    val dma_axi_wready        = Output(Bool())
+    val dma_axi_wdata         = Input(UInt(64.W))
+    val dma_axi_wstrb         = Input(UInt(8.W))
+
+    val dma_axi_bvalid        = Output(Bool())
+    val dma_axi_bready        = Input(Bool())
+    val dma_axi_bresp         = Output(UInt(2.W))
+    val dma_axi_bid           = Output(UInt(DMA_BUS_TAG.W))
+
+    // AXI Read Channels
+    val dma_axi_arvalid       = Input(Bool())
+    val dma_axi_arready       = Output(Bool())
+    val dma_axi_arid          = Input(UInt(DMA_BUS_TAG.W))
+
+    val dma_axi_araddr        = Input(UInt(32.W))
+    val dma_axi_arsize        = Input(UInt(3.W))
+
+    val dma_axi_rvalid        = Output(Bool())
+    val dma_axi_rready        = Input(Bool())
+    val dma_axi_rid           = Output(UInt(DMA_BUS_TAG.W))
+    val dma_axi_rdata         = Output(UInt(64.W))
+    val dma_axi_rresp         = Output(UInt(2.W))
+    val dma_axi_rlast         = Output(Bool())
+  })
+
+
+  val DEPTH_PTR = log2Ceil(DMA_BUF_DEPTH)
+
+  val fifo_error = Wire(Vec(DMA_BUF_DEPTH, UInt(2.W)))
+
+  val fifo_error_bus = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
+
+  val fifo_done = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
+
+  val fifo_addr = Wire(Vec(DMA_BUF_DEPTH, UInt(32.W)))
+
+  val fifo_sz = Wire(Vec(DMA_BUF_DEPTH,UInt(3.W)))
+
+  val fifo_byteen = Wire(Vec(DMA_BUF_DEPTH,UInt(8.W)))
+
+  val fifo_data = Wire(Vec(DMA_BUF_DEPTH,UInt(64.W)))
+
+  val fifo_tag = Wire(Vec(DMA_BUF_DEPTH,UInt(DMA_BUS_TAG.W)))
+
+  val fifo_mid = Wire(Vec(DMA_BUF_DEPTH,UInt((DMA_BUS_ID:Int).W)))
+
+  val fifo_prty = Wire(Vec(DMA_BUF_DEPTH,UInt(DMA_BUS_PRTY.W)))
+
+  val fifo_error_en = WireInit(UInt(DMA_BUF_DEPTH.W),0.U)
+
+  val fifo_error_in = Wire(Vec(DMA_BUF_DEPTH, UInt(2.W)))
+
+  val fifo_data_in = Wire(Vec(DMA_BUF_DEPTH,UInt(64.W)))
+
+  val RspPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
+
+  val WrPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
+
+  val RdPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
+
+  val NxtRspPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
+
+  val NxtWrPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
+
+  val NxtRdPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
+
+  val dma_dbg_cmd_error = WireInit(UInt(1.W),0.U)
+
+  val dma_dbg_cmd_done_q = WireInit(UInt(1.W), 0.U)
+
+  val fifo_empty = WireInit(UInt(1.W), 0.U)
+
+  val dma_address_error = WireInit(UInt(1.W), 0.U)
+
+  val dma_alignment_error = WireInit(UInt(1.W), 0.U)
+
+  val num_fifo_vld = WireInit(UInt(4.W),0.U)
+
+  val dma_mem_req = WireInit(UInt(1.W), 0.U)
+
+  val dma_mem_addr_int = WireInit(UInt(32.W), 0.U)
+
+  val dma_mem_sz_int = WireInit(UInt(3.W), 0.U)
+
+  val dma_mem_byteen = WireInit(UInt(8.W), 0.U)
+
+  val dma_nack_count = WireInit(UInt(3.W), 0.U)
+
+  val dma_nack_count_csr = WireInit(UInt(3.W), 0.U)
+
+  val bus_rsp_valid = WireInit(UInt(1.W), 0.U)
+
+  val bus_rsp_sent = WireInit(UInt(1.W), 0.U)
+
+  val bus_cmd_valid = WireInit(UInt(1.W), 0.U)
+
+  val bus_cmd_sent = WireInit(UInt(1.W), 0.U)
+
+  val bus_cmd_write = WireInit(UInt(1.W), 0.U)
+
+  val bus_cmd_posted_write = WireInit(UInt(1.W), 0.U)
+
+  val bus_cmd_byteen = WireInit(UInt(8.W), 0.U)
+
+  val bus_cmd_sz = WireInit(UInt(3.W), 0.U)
+
+  val bus_cmd_addr = WireInit(UInt(32.W), 0.U)
+
+  val bus_cmd_wdata = WireInit(UInt(64.W), 0.U)
+
+  val bus_cmd_tag = WireInit(UInt(DMA_BUS_TAG.W), 0.U)
+
+  val bus_cmd_mid = WireInit(UInt((DMA_BUS_ID:Int).W), 0.U)
+
+  val bus_cmd_prty = WireInit(UInt(DMA_BUS_PRTY.W), 0.U)
+
+  val bus_posted_write_done = WireInit(UInt(1.W), 0.U)
+
+  val fifo_full_spec_bus = WireInit(UInt(1.W), 0.U)
+
+  val dbg_dma_bubble_bus = WireInit(UInt(1.W), 0.U)
+
+  val axi_mstr_priority = WireInit(UInt(1.W), 0.U)
+
+  val axi_mstr_sel = WireInit(UInt(1.W), 0.U)
+
+  val axi_rsp_sent = WireInit(UInt(1.W), 0.U)
+
+  val fifo_cmd_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
+
+  val fifo_data_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
+
+  val fifo_pend_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
+
+  val fifo_error_bus_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
+
+  val fifo_done_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
+
+  val fifo_done_bus_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
+
+  val fifo_reset = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
+
+  val fifo_valid = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
+
+  val fifo_rpend = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
+
+  val fifo_done_bus = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
+
+  val fifo_write = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
+
+  val fifo_posted_write = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
+
+  val fifo_dbg = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
+
+  val wrbuf_vld = WireInit(UInt(1.W), 0.U)
+
+  val wrbuf_data_vld = WireInit(UInt(1.W), 0.U)
+
+  val rdbuf_vld = WireInit(UInt(1.W), 0.U)
+
+  val dma_free_clk = Wire(Clock())
+
+  val dma_bus_clk = Wire(Clock())
+
+  val dma_buffer_c1_clk = Wire(Clock())
+
+  val fifo_byteen_in = WireInit(UInt(8.W), 0.U)
+
+  //------------------------LOGIC STARTS HERE---------------------------------
+
+
+  // DCCM Address check
+
+  val (dma_mem_addr_in_dccm,dma_mem_addr_in_dccm_region_nc) = rvrangecheck_ch(dma_mem_addr_int(31,0),DCCM_SADR.U,DCCM_SIZE)
+
+  // PIC memory address check
+
+  val (dma_mem_addr_in_pic,dma_mem_addr_in_pic_region_nc) = rvrangecheck_ch(dma_mem_addr_int(31,0),PIC_BASE_ADDR.U,PIC_SIZE)
+
+  //  ICCM Address check
+
+  val (dma_mem_addr_in_iccm,dma_mem_addr_in_iccm_region_nc) = if(ICCM_ENABLE) rvrangecheck_ch(dma_mem_addr_int(31,0),ICCM_SADR.U,ICCM_SIZE) else (0.U,0.U)
+
+  // FIFO inputs
+
+  val fifo_addr_in         = Mux(io.dbg_cmd_valid.asBool, io.dbg_cmd_addr(31,0), bus_cmd_addr(31,0))
+
+  fifo_byteen_in           := Mux(io.dbg_cmd_valid.asBool, "h0f".U << (4.U * io.dbg_cmd_addr(2)), bus_cmd_byteen(7,0))
+
+  val fifo_sz_in           = Mux(io.dbg_cmd_valid.asBool, Cat(0.U, io.dbg_cmd_size(1,0)), bus_cmd_sz(2,0))
+
+  val fifo_write_in        = Mux(io.dbg_cmd_valid.asBool, io.dbg_cmd_write, bus_cmd_write)
+
+  val fifo_posted_write_in = !io.dbg_cmd_valid & bus_cmd_posted_write
+
+  val fifo_dbg_in          = io.dbg_cmd_valid
+
+
+  fifo_cmd_en       := (0 until DMA_BUF_DEPTH).map(i => (((bus_cmd_sent.asBool & io.dma_bus_clk_en) | (io.dbg_cmd_valid & io.dbg_cmd_type(1).asBool)) & (i.U === WrPtr)).asUInt).reverse.reduce(Cat(_,_))
+
+  fifo_data_en      := (0 until DMA_BUF_DEPTH).map(i => (((bus_cmd_sent & fifo_write_in & io.dma_bus_clk_en) | (io.dbg_cmd_valid & io.dbg_cmd_type(1) & io.dbg_cmd_write)) & (i.U === WrPtr)) | ((dma_address_error | dma_alignment_error) & (i.U === RdPtr)) | (io.dccm_dma_rvalid & (i.U === io.dccm_dma_rtag)) | (io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag))).reverse.reduce(Cat(_,_))
+
+  fifo_pend_en      := (0 until DMA_BUF_DEPTH).map(i => ((io.dma_dccm_req | io.dma_iccm_req) & !io.dma_mem_write & (i.U === RdPtr)).asUInt).reverse.reduce(Cat(_,_))
+
+  fifo_error_en     := (0 until DMA_BUF_DEPTH).map(i => (((dma_address_error.asBool | dma_alignment_error.asBool | dma_dbg_cmd_error) & (i.U === RdPtr)) | ((io.dccm_dma_rvalid & io.dccm_dma_ecc_error) & (i.U === io.dccm_dma_rtag)) | ((io.iccm_dma_rvalid & io.iccm_dma_ecc_error) & (i.U === io.iccm_dma_rtag))).asUInt).reverse.reduce(Cat(_,_))
+
+  fifo_error_bus_en := (0 until DMA_BUF_DEPTH).map(i => ((((fifo_error_in(i)(1,0).orR) & fifo_error_en(i)) | (fifo_error(i).orR)) & io.dma_bus_clk_en).asUInt).reverse.reduce(Cat(_,_))
+
+  fifo_done_en      := (0 until DMA_BUF_DEPTH).map(i => (((fifo_error(i).orR | fifo_error_en(i) | ((io.dma_dccm_req | io.dma_iccm_req) & io.dma_mem_write)) & (i.U === RdPtr)) | (io.dccm_dma_rvalid & (i.U === io.dccm_dma_rtag)) | (io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag))).asUInt).reverse.reduce(Cat(_,_))
+
+  fifo_done_bus_en  := (0 until DMA_BUF_DEPTH).map(i => ((fifo_done_en(i) | fifo_done(i)) & io.dma_bus_clk_en).asUInt).reverse.reduce(Cat(_,_))
+
+  fifo_reset        := (0 until DMA_BUF_DEPTH).map(i => ((((bus_rsp_sent | bus_posted_write_done) & io.dma_bus_clk_en) | io.dma_dbg_cmd_done) & (i.U === RspPtr))).reverse.reduce(Cat(_,_))
+
+  (0 until DMA_BUF_DEPTH).map(i => fifo_error_in(i) := (Mux(io.dccm_dma_rvalid & (i.U === io.dccm_dma_rtag), Cat(0.U, io.dccm_dma_ecc_error), Mux(io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag), (Cat(0.U, io.iccm_dma_ecc_error)), (Cat((dma_address_error | dma_alignment_error | dma_dbg_cmd_error), dma_alignment_error))))))
+
+  (0 until DMA_BUF_DEPTH).map(i => fifo_data_in(i) := (Mux(fifo_error_en(i) & (fifo_error_in(i).orR), Cat(Fill(32, 0.U), fifo_addr(i)), Mux(io.dccm_dma_rvalid & (i.U === io.dccm_dma_rtag), io.dccm_dma_rdata, Mux(io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag), io.iccm_dma_rdata, Mux(io.dbg_cmd_valid, Fill(2, io.dbg_cmd_wrdata), bus_cmd_wdata(63,0)))))))
+
+  fifo_valid := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_cmd_en(i), 1.U, fifo_valid(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
+
+  (0 until DMA_BUF_DEPTH).map(i => fifo_error(i) := withClock(dma_free_clk) {RegNext(Mux(fifo_error_en(i).asBool(),fifo_error_in(i) , fifo_error(i)) & Fill(fifo_error_in(i).getWidth , !fifo_reset(i)), 0.U)})
+
+  fifo_error_bus    := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_error_bus_en(i), 1.U, fifo_error_bus(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
+
+  fifo_rpend        := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_pend_en(i), 1.U, fifo_rpend(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
+
+  fifo_done         := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_done_en(i), 1.U, fifo_done(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
+
+  fifo_done_bus     := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_done_bus_en(i), 1.U, fifo_done_bus(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
+
+  (0 until DMA_BUF_DEPTH).map(i => fifo_addr(i) := rvdffe(fifo_addr_in, fifo_cmd_en(i), clock, io.scan_mode))
+
+  (0 until DMA_BUF_DEPTH).map(i => fifo_sz(i) := withClock(dma_buffer_c1_clk) {RegEnable(fifo_sz_in(2,0), 0.U, fifo_cmd_en(i))})
+
+  (0 until DMA_BUF_DEPTH).map(i => fifo_byteen(i) := withClock(dma_buffer_c1_clk) {RegEnable(fifo_byteen_in(7,0), 0.U, fifo_cmd_en(i).asBool())})
+
+  fifo_write        := (0 until DMA_BUF_DEPTH).map(i => (withClock(dma_buffer_c1_clk) {RegEnable(fifo_write_in, 0.U, fifo_cmd_en(i))})).reverse.reduce(Cat(_,_))
+
+  fifo_posted_write := (0 until DMA_BUF_DEPTH).map(i => (withClock(dma_buffer_c1_clk) {RegEnable(fifo_posted_write_in, 0.U, fifo_cmd_en(i))})).reverse.reduce(Cat(_,_))
+
+  fifo_dbg          := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_buffer_c1_clk) {RegEnable(fifo_dbg_in, 0.U, fifo_cmd_en(i))}).reverse.reduce(Cat(_,_))
+
+  (0 until DMA_BUF_DEPTH).map(i => fifo_data(i) := rvdffe(fifo_data_in(i), fifo_data_en(i), clock, io.scan_mode))
+
+  (0 until DMA_BUF_DEPTH).map(i => fifo_tag(i) := withClock(dma_buffer_c1_clk) {RegEnable(bus_cmd_tag, 0.U, fifo_cmd_en(i))})
+
+  (0 until DMA_BUF_DEPTH).map(i => fifo_mid(i) := withClock(dma_buffer_c1_clk) {RegEnable(bus_cmd_mid, 0.U, fifo_cmd_en(i))})
+
+  (0 until DMA_BUF_DEPTH).map(i => fifo_prty(i) := withClock(dma_buffer_c1_clk) {RegEnable(bus_cmd_prty, 0.U, fifo_cmd_en(i))})
+
+  // Pointer logic
+
+  NxtWrPtr     := Mux((WrPtr === (DMA_BUF_DEPTH - 1).U).asBool, 0.U, WrPtr + 1.U)
+
+  NxtRdPtr     := Mux((RdPtr === (DMA_BUF_DEPTH - 1).U).asBool, 0.U, RdPtr + 1.U)
+
+  NxtRspPtr    := Mux((RspPtr === (DMA_BUF_DEPTH - 1).U).asBool, 0.U, RspPtr + 1.U)
+
+  val WrPtrEn  = fifo_cmd_en.orR
+
+  val RdPtrEn  = (io.dma_dccm_req | io.dma_iccm_req | (dma_address_error.asBool | dma_alignment_error.asBool | dma_dbg_cmd_error))
+
+  val RspPtrEn = (io.dma_dbg_cmd_done | (bus_rsp_sent | bus_posted_write_done) & io.dma_bus_clk_en)
+
+  WrPtr        := withClock(dma_free_clk) {
+    RegEnable(NxtWrPtr, 0.U, WrPtrEn)
+  }
+
+  RdPtr        := withClock(dma_free_clk) {
+    RegEnable(NxtRdPtr, 0.U, RdPtrEn.asBool)
+  }
+
+  RspPtr       := withClock(dma_free_clk) {
+    RegEnable(NxtRspPtr, 0.U, RspPtrEn.asBool)
+  }
+
+  // Miscellaneous signal
+
+  val fifo_full         = fifo_full_spec_bus;
+
+  val num_fifo_vld_tmp  = WireInit(UInt(4.W),0.U)
+  val num_fifo_vld_tmp2 = WireInit(UInt(4.W),0.U)
+
+  num_fifo_vld_tmp      := (Cat(Fill(3, 0.U), bus_cmd_sent)) - (Cat(Fill(3, 0.U), bus_rsp_sent))
+
+  num_fifo_vld_tmp2     := (0 until DMA_BUF_DEPTH).map(i => Cat(Fill(3,0.U), fifo_valid(i))).reduce(_+_)
+
+  num_fifo_vld          := num_fifo_vld_tmp + num_fifo_vld_tmp2
+
+  val fifo_full_spec    = (num_fifo_vld_tmp2 >= DMA_BUF_DEPTH.asUInt())
+
+  val dma_fifo_ready    = ~(fifo_full | dbg_dma_bubble_bus)
+
+  // Error logic
+
+  dma_address_error     := fifo_valid(RdPtr) & !fifo_done(RdPtr) & !fifo_dbg(RdPtr) & (~(dma_mem_addr_in_dccm | dma_mem_addr_in_iccm)).asUInt   // request not for ICCM or DCCM
+  dma_alignment_error   := fifo_valid(RdPtr) & !fifo_done(RdPtr) & !dma_address_error &
+    (((dma_mem_sz_int(2,0) === 1.U) & dma_mem_addr_int(0)) |                                                                                // HW size but unaligned
+      ((dma_mem_sz_int(2,0) === 2.U) & (dma_mem_addr_int(1, 0).orR)) |                                                                      // W size but unaligned
+      ((dma_mem_sz_int(2,0) === 3.U) & (dma_mem_addr_int(2, 0).orR)) |                                                                      // DW size but unaligned
+      (dma_mem_addr_in_iccm & ~((dma_mem_sz_int(1, 0) === 2.U) | (dma_mem_sz_int(1, 0) === 3.U)).asUInt  ) |                                // ICCM access not word size
+      (dma_mem_addr_in_dccm & io.dma_mem_write & ~((dma_mem_sz_int(1, 0) === 2.U) | (dma_mem_sz_int(1, 0) === 3.U)).asUInt) |               // DCCM write not word size
+      (io.dma_mem_write & (dma_mem_sz_int(2, 0) === 2.U) & (Mux1H(Seq((dma_mem_addr_int(2,0) === 0.U) -> (dma_mem_byteen(3,0)),
+        (dma_mem_addr_int(2,0) === 1.U) -> (dma_mem_byteen(4,1)),
+        (dma_mem_addr_int(2,0) === 2.U) -> (dma_mem_byteen(5,2)),
+        (dma_mem_addr_int(2,0) === 3.U) -> (dma_mem_byteen(6,3)))) =/= 15.U)) | // Write byte enables not aligned for word store
+      (io.dma_mem_write & (dma_mem_sz_int(2, 0) === 3.U) & !((dma_mem_byteen(7,0) === "h0f".U) | (dma_mem_byteen(7,0) === "hf0".U) | (dma_mem_byteen(7,0) === "hff".U)))) // Write byte enables not aligned for dword store
+
+  //Dbg outputs
+
+  io.dma_dbg_ready      := fifo_empty & dbg_dma_bubble_bus
+  io.dma_dbg_cmd_done   := (fifo_valid(RspPtr) & fifo_dbg(RspPtr) & fifo_done(RspPtr))
+  io.dma_dbg_rddata     := Mux(fifo_addr(RspPtr)(2), fifo_data(RspPtr)(63, 32), fifo_data(RspPtr)(31,0))
+  io.dma_dbg_cmd_fail   := fifo_error(RspPtr).orR
+
+  dma_dbg_cmd_error     := fifo_valid(RdPtr) & !fifo_done(RdPtr) & fifo_dbg(RdPtr) & ((~(dma_mem_addr_in_dccm | dma_mem_addr_in_iccm | dma_mem_addr_in_pic)).asBool() | (dma_mem_sz_int(1, 0) =/= 2.U))       // Only word accesses allowed
+
+  // Block the decode if fifo full
+
+  io.dma_dccm_stall_any := dma_mem_req & (dma_mem_addr_in_dccm | dma_mem_addr_in_pic) & (dma_nack_count >= dma_nack_count_csr)
+  io.dma_iccm_stall_any := dma_mem_req & dma_mem_addr_in_iccm & (dma_nack_count >= dma_nack_count_csr);
+
+  // Used to indicate ready to debug
+
+  fifo_empty := ~(fifo_valid.orR)
+
+  // Nack counter, stall the lsu pipe if 7 nacks
+
+  dma_nack_count_csr := io.dec_tlu_dma_qos_prty
+  val dma_nack_count_d = Mux(dma_nack_count >= dma_nack_count_csr, (Fill(3, !(io.dma_dccm_req | io.dma_iccm_req)) & dma_nack_count(2,0)), Mux((dma_mem_req.asBool & !(io.dma_dccm_req | io.dma_iccm_req)), dma_nack_count(2,0) + 1.U, 0.U))
+
+  dma_nack_count     := withClock(dma_free_clk) {
+    RegEnable(dma_nack_count_d(2,0), 0.U, dma_mem_req.asBool)
+  }
+
+  // Core outputs
+
+  dma_mem_req      := fifo_valid(RdPtr) & !fifo_rpend(RdPtr) & !fifo_done(RdPtr) & !(dma_address_error | dma_alignment_error | dma_dbg_cmd_error)
+  io.dma_dccm_req  := dma_mem_req & (dma_mem_addr_in_dccm | dma_mem_addr_in_pic) & io.dccm_ready;
+  io.dma_iccm_req  := dma_mem_req & dma_mem_addr_in_iccm & io.iccm_ready;
+  io.dma_mem_tag   := RdPtr
+  dma_mem_addr_int := fifo_addr(RdPtr)
+  dma_mem_sz_int   := fifo_sz(RdPtr)
+  io.dma_mem_addr  := Mux(io.dma_mem_write & (dma_mem_byteen(7,0) === "hf0".U), Cat(dma_mem_addr_int(31, 3), 1.U, dma_mem_addr_int(1, 0)), dma_mem_addr_int(31,0))
+  io.dma_mem_sz    := Mux(io.dma_mem_write & ((dma_mem_byteen(7,0) === "h0f".U) | (dma_mem_byteen(7,0) === "hf0".U)), 2.U, dma_mem_sz_int(2,0))
+  dma_mem_byteen   := fifo_byteen(RdPtr)
+  io.dma_mem_write := fifo_write(RdPtr)
+  io.dma_mem_wdata := fifo_data(RdPtr)
+
+  // PMU outputs
+
+  io.dma_pmu_dccm_read   := io.dma_dccm_req & !io.dma_mem_write;
+  io.dma_pmu_dccm_write  := io.dma_dccm_req & io.dma_mem_write;
+  io.dma_pmu_any_read    := (io.dma_dccm_req | io.dma_iccm_req) & !io.dma_mem_write;
+  io.dma_pmu_any_write   := (io.dma_dccm_req | io.dma_iccm_req) & io.dma_mem_write;
+
+  // Inputs
+
+  fifo_full_spec_bus := withClock(dma_bus_clk) {
+    RegNext(fifo_full_spec, 0.U)
+  }
+
+  dbg_dma_bubble_bus := withClock(dma_bus_clk) {
+    RegNext(io.dbg_dma_bubble, 0.U)
+  }
+
+  dma_dbg_cmd_done_q := withClock(io.free_clk) {
+    RegNext(io.dma_dbg_cmd_done, 0.U)
+  }
+
+  // Clock Gating logic
+
+  val dma_buffer_c1_clken = (bus_cmd_valid & io.dma_bus_clk_en) | io.dbg_cmd_valid | io.clk_override
+  val dma_free_clken      = (bus_cmd_valid | bus_rsp_valid | io.dbg_cmd_valid | io.dma_dbg_cmd_done | dma_dbg_cmd_done_q | (fifo_valid.orR) | io.clk_override)
+
+  val dma_buffer_c1cgc = Module(new rvclkhdr)
+  dma_buffer_c1cgc.io.en        := dma_buffer_c1_clken
+  dma_buffer_c1cgc.io.scan_mode := io.scan_mode
+  dma_buffer_c1cgc.io.clk       := clock
+  dma_buffer_c1_clk             := dma_buffer_c1cgc.io.l1clk
+
+  val dma_free_cgc = Module(new rvclkhdr)
+  dma_free_cgc.io.en        := dma_free_clken
+  dma_free_cgc.io.scan_mode := io.scan_mode
+  dma_free_cgc.io.clk       := clock
+  dma_free_clk              := dma_free_cgc.io.l1clk
+
+  val dma_bus_cgc = Module(new rvclkhdr)
+  dma_bus_cgc.io.en        := io.dma_bus_clk_en
+  dma_bus_cgc.io.scan_mode := io.scan_mode
+  dma_bus_cgc.io.clk       := clock
+  dma_bus_clk              := dma_bus_cgc.io.l1clk
+
+  // Write channel buffer
+
+  val wrbuf_en          = io.dma_axi_awvalid & io.dma_axi_awready
+  val wrbuf_data_en     = io.dma_axi_wvalid & io.dma_axi_wready
+  val wrbuf_cmd_sent    = bus_cmd_sent & bus_cmd_write
+  val wrbuf_rst         = wrbuf_cmd_sent.asBool & !wrbuf_en
+  val wrbuf_data_rst    = wrbuf_cmd_sent.asBool & !wrbuf_data_en
+
+  wrbuf_vld             := withClock(dma_bus_clk) {RegNext(Mux(wrbuf_en, 1.U, wrbuf_vld) & !wrbuf_rst, 0.U)}
+
+  wrbuf_data_vld        := withClock(dma_bus_clk) {RegNext(Mux(wrbuf_data_en, 1.U, wrbuf_data_vld) & !wrbuf_data_rst, 0.U)}
+
+  val wrbuf_tag         = withClock(dma_bus_clk) {
+    RegEnable(io.dma_axi_awid, 0.U, wrbuf_en)
+  }
+
+  val wrbuf_sz          = withClock(dma_bus_clk) {
+    RegEnable(io.dma_axi_awsize, 0.U, wrbuf_en)
+  }
+
+  val wrbuf_addr        = rvdffe(io.dma_axi_awaddr, wrbuf_en & io.dma_bus_clk_en, clock, io.scan_mode)
+
+  val wrbuf_data        = rvdffe(io.dma_axi_wdata, wrbuf_data_en & io.dma_bus_clk_en, clock, io.scan_mode)
+
+  val wrbuf_byteen 		  = withClock(dma_bus_clk) {
+    RegEnable(io.dma_axi_wstrb, 0.U, wrbuf_data_en)
+  }
+
+  // Read channel buffer
+
+  val rdbuf_en 			    = io.dma_axi_arvalid & io.dma_axi_arready
+  val rdbuf_cmd_sent 	  = bus_cmd_sent & !bus_cmd_write
+  val rdbuf_rst 		    = rdbuf_cmd_sent.asBool & !rdbuf_en
+
+  rdbuf_vld := withClock(dma_bus_clk) {RegNext(Mux(rdbuf_en, 1.U, rdbuf_vld) & !rdbuf_rst, 0.U)}
+
+  val rdbuf_tag 		    = withClock(dma_bus_clk) {
+    RegEnable(io.dma_axi_arid, 0.U, rdbuf_en)
+  }
+
+  val rdbuf_sz 			    = withClock(dma_bus_clk) {
+    RegEnable(io.dma_axi_arsize, 0.U, rdbuf_en)
+  }
+
+  val rdbuf_addr = rvdffe(io.dma_axi_araddr, rdbuf_en & io.dma_bus_clk_en, clock, io.scan_mode)
+
+  io.dma_axi_awready 	  := ~(wrbuf_vld & !wrbuf_cmd_sent)
+  io.dma_axi_wready 	  := ~(wrbuf_data_vld & !wrbuf_cmd_sent)
+  io.dma_axi_arready 	  := ~(rdbuf_vld & !rdbuf_cmd_sent)
+
+  //Generate a single request from read/write channel
+
+  bus_cmd_valid 		    := (wrbuf_vld & wrbuf_data_vld) | rdbuf_vld
+  bus_cmd_sent 			    := bus_cmd_valid & dma_fifo_ready.asUInt
+  bus_cmd_write 		    := axi_mstr_sel
+  bus_cmd_posted_write 	:= 0.U;
+  bus_cmd_addr 			    := Mux(axi_mstr_sel.asBool, wrbuf_addr, rdbuf_addr)
+  bus_cmd_sz 			      := Mux(axi_mstr_sel.asBool, wrbuf_sz, rdbuf_sz)
+  bus_cmd_wdata 		    := wrbuf_data
+  bus_cmd_byteen 		    := wrbuf_byteen
+  bus_cmd_tag 			    := Mux(axi_mstr_sel.asBool, wrbuf_tag, rdbuf_tag)
+  bus_cmd_mid 			    := 0.U
+  bus_cmd_prty 			    := 0.U
+
+  // Sel=1 -> write has higher priority
+
+  axi_mstr_sel          := Mux((wrbuf_vld & wrbuf_data_vld & rdbuf_vld) === 1.U, axi_mstr_priority, wrbuf_vld & wrbuf_data_vld)
+  val axi_mstr_prty_in 	= ~axi_mstr_priority
+  val axi_mstr_prty_en 	= bus_cmd_sent
+
+  axi_mstr_priority 	  := withClock(dma_bus_clk) {
+    RegEnable(axi_mstr_prty_in, 0.U, axi_mstr_prty_en.asBool)
+  }
+
+  val axi_rsp_valid 	  = fifo_valid(RspPtr) & !fifo_dbg(RspPtr) & fifo_done_bus(RspPtr)
+  val axi_rsp_rdata 	  = fifo_data(RspPtr)
+  val axi_rsp_write 	  = fifo_write(RspPtr)
+  val axi_rsp_error 	  = Mux(fifo_error(RspPtr)(0), 2.U, Mux(fifo_error(RspPtr)(1), 3.U, 0.U));
+
+  val axi_rsp_tag 		  = fifo_tag(RspPtr)
+
+  // AXI response channel signals
+
+  io.dma_axi_bvalid 	  := axi_rsp_valid & axi_rsp_write
+  io.dma_axi_bresp 	  	:= axi_rsp_error(1,0)
+  io.dma_axi_bid 	    	:= axi_rsp_tag
+
+  io.dma_axi_rvalid 	  := axi_rsp_valid & !axi_rsp_write
+  io.dma_axi_rresp 	  	:= axi_rsp_error
+  io.dma_axi_rdata 		  := axi_rsp_rdata(63,0)
+  io.dma_axi_rlast 	  	:= 1.U
+  io.dma_axi_rid 		    := axi_rsp_tag
+
+  bus_posted_write_done := 0.U
+  bus_rsp_valid 		    := (io.dma_axi_bvalid | io.dma_axi_rvalid)
+  bus_rsp_sent 			    := ((io.dma_axi_bvalid & io.dma_axi_bready) | (io.dma_axi_rvalid & io.dma_axi_rready))
+}
+object dma extends App{
+  chisel3.Driver.emitVerilog(new el2_dma_ctrl)
+}
\ No newline at end of file
diff --git a/src/main/scala/lib/GCD.scala b/src/main/scala/lib/GCD.scala
deleted file mode 100644
index 7cb03f12..00000000
--- a/src/main/scala/lib/GCD.scala
+++ /dev/null
@@ -1,123 +0,0 @@
-package lib
-
-import chisel3._
-import chisel3.util._
-/*
-///////////////////////////////////////////////////////////////
-class rvdff(val Width:Int = 1, val short:Int = 0) extends Module with RequireAsyncReset {
-  val io = IO(new Bundle {
-    val in = Input(UInt(Width.W))
-    val out = Output(UInt())
-  })
-  val inter = if(short==0) RegNext(io.in, init =0.U) else io.in
-  io.out := inter
-}
-
-/////////////////////////////////////////////////////////////
-class caller extends Module {
-  val io = IO(new Bundle {
-    val in = Input(UInt(32.W))
-    val out = Output(UInt())
-  })
-  val u0 = Module(new rvdff(32))
-  io <> u0.io
-}
-
-///////////////////////////////////////////////////////////////
-class reg1 extends Module with RequireAsyncReset{
-  val io = IO(new Bundle{
-    val in = Input(Bool())
-    val out = Output(Bool())
-  })
-
-  io.out := RegNext(io.in, init = 0.U)
-}
-
-class top extends Module with RequireAsyncReset{
-  val io = IO(new Bundle{
-    val in = Input(Bool())
-    val out = Output(Bool())
-  })
-  val negReset = (~reset.asBool).asAsyncReset
-  val r0 = Module(new reg1)
-  r0.io<>io
-  r0.reset := negReset
-}
-///////////////////////////////////////////////////////////////
-class rvbradder() extends Module {
-  val io = IO(new Bundle {
-    val pc = Input(UInt(31.W))
-    val offset = Input(UInt(12.W))
-    val dout = Output(UInt())
-  })
-  val inter = io.pc(11,0) +& io.offset
-  val cout = inter(inter.getWidth-1)
-  val pc_inc = io.pc(io.pc.getWidth-1, 12) + 1.U
-  val pc_dec = io.pc(io.pc.getWidth-1, 12) - 1.U
-  val sign = io.offset(io.offset.getWidth -1)
-
-  io.dout:= Cat(Fill(19,(sign ^(~cout))) & io.pc(io.pc.getWidth-1,12) |
-    (Fill(19,(~sign & cout)) & pc_inc) |
-    (Fill(19,(sign & ~cout)) & pc_dec) , inter(inter.getWidth-2,0))
-}
-
-///////////////////////////////////////////////////////////////
-class encoder_generator(val width:Int=4) extends Module {
-  val io = IO (new Bundle {
-    val in = Input (UInt(width.W))
-    val out = Output (UInt(log2Ceil(width).W))
-  })
-  var z:Array[UInt] = new Array[UInt](width)
-  for(i<- 0 until width){
-    z(i) = i.U
-  }
-  io.out := Mux1H(io.in , z)
-}
-
-///////////////////////////////////////////////////////////////
-class rvrangecheck(val CCM_SADR:Int = 0, val CCM_SIZE:Int = 128) extends Module {
-  val io = IO(new Bundle {
-    val addr = Input(UInt(32.W))
-    val in_range = Output(Bool())
-    val in_region = Output(Bool())
-    //val test = Output(UInt())
-  })
-  val start_addr = (CCM_SADR.U)(32.W)
-  val region = start_addr(31,28)
-  val MASK_BITS = 10+log2Ceil(CCM_SIZE)
-  io.in_region := io.addr(31,28) === region
-  val inter = if(CCM_SIZE == 48) io.addr(31, MASK_BITS) === start_addr(31, MASK_BITS) & ~(io.addr(MASK_BITS-1,MASK_BITS-2).andR)
-  else (io.addr(31,MASK_BITS)===start_addr(31,MASK_BITS))
-  io.in_range := inter
-}
-
-
-
-////////////////////////////////////////////////////////////////
-class tocopy extends Module{
-  val io = IO(new Bundle {
-    val in1 = Input(UInt(1.W))
-    val in2 = Input(UInt(1.W))
-    val out = Output(UInt())
-  })
-  io.out := io.in1 +& io.in2
-}
-class exp extends Module{
-  val io = IO(new Bundle{
-    val in1 = Input(UInt(1.W))
-    val in2 = Input(UInt(1.W))
-    val out = Output(UInt())
-  })
-
-  val mod_array= new Array[tocopy](2)
-  mod_array(0) = Module(new tocopy)
-  mod_array(0).io.in1:=io.in1
-  mod_array(0).io.in2:=io.in2
-  mod_array(1) = Module(new tocopy)
-  mod_array(1).io.in1:=io.in1
-  mod_array(1).io.in2:=io.in2
-  io.out:= mod_array(0).io.out +& mod_array(1).io.out
-}
-////////////////////////////////////////////////////////////////
-
-//println((new chisel3.stage.ChiselStage).emitVerilog(new exp))*/
\ No newline at end of file
diff --git a/src/main/scala/lib/ahb_to_axi4.scala b/src/main/scala/lib/ahb_to_axi4.scala
new file mode 100644
index 00000000..f2031e91
--- /dev/null
+++ b/src/main/scala/lib/ahb_to_axi4.scala
@@ -0,0 +1,240 @@
+//package lib
+//import chisel3._
+//import chisel3.util._
+////import chisel3.experimental.chiselName
+//
+////@chiselName
+//class ahb_to_axi4 extends Module with el2_lib with RequireAsyncReset {
+//    val io = IO(new Bundle {
+//        val scan_mode       = Input(Bool())
+//        val bus_clk_en      = Input(Bool())
+//        val clk_override    = Input(Bool())
+//        val axi_awready     = Input(Bool())
+//        val axi_wready      = Input(Bool())
+//        val axi_bvalid      = Input(Bool())
+//        val axi_bresp       = Input(UInt(2.W))
+//        val axi_bid         = Input(UInt(TAG.W))
+//        val axi_arready     = Input(Bool())
+//        val axi_rvalid      = Input(Bool())
+//        val axi_rid         = Input(UInt(TAG.W))
+//        val axi_rdata       = Input(UInt(64.W))
+//        val axi_rresp       = Input(UInt(2.W))
+//        val ahb_haddr       = Input(UInt(32.W)) // ahb bus address
+//        val ahb_hburst      = Input(UInt(3.W)) // tied to 0
+//        val ahb_hmastlock   = Input(Bool()) // tied to 0
+//        val ahb_hprot       = Input(UInt(4.W)) // tied to 4'b0011
+//        val ahb_hsize       = Input(UInt(3.W)) // size of bus transaction (possible values 0          =1          =2          =3)
+//        val ahb_htrans      = Input(UInt(2.W)) // Transaction type (possible values 0          =2 only right now)
+//        val ahb_hwrite      = Input(Bool()) // ahb bus write
+//        val ahb_hwdata      = Input(UInt(64.W)) // ahb bus write data
+//        val ahb_hsel        = Input(Bool()) // this slave was selected
+//        val ahb_hreadyin    = Input(Bool()) // previous hready was accepted or not
+//        // outputs
+//        val axi_awvalid     = Output(Bool())
+//        val axi_awid        = Output(UInt(TAG.W))
+//        val axi_awaddr      = Output(UInt(32.W))
+//        val axi_awsize      = Output(UInt(3.W))
+//        val axi_awprot      = Output(UInt(3.W))
+//        val axi_awlen       = Output(UInt(8.W))
+//        val axi_awburst     = Output(UInt(2.W))
+//        val axi_wvalid      = Output(Bool())
+//        val axi_wdata       = Output(UInt(64.W))
+//        val axi_wstrb       = Output(UInt(8.W))
+//        val axi_wlast       = Output(Bool())
+//        val axi_bready      = Output(Bool())
+//        val axi_arvalid     = Output(Bool())
+//        val axi_arid        = Output(UInt(TAG.W))
+//        val axi_araddr      = Output(UInt(32.W))
+//        val axi_arsize      = Output(UInt(3.W))
+//        val axi_arprot      = Output(UInt(3.W))
+//        val axi_arlen       = Output(UInt(8.W))
+//        val axi_arburst     = Output(UInt(2.W))
+//        val axi_rready      = Output(Bool())
+//        val ahb_hrdata      = Output(UInt(64.W)) // ahb bus read data
+//        val ahb_hreadyout   = Output(Bool()) // slave ready to accept transaction
+//        val ahb_hresp       = Output(Bool()) // slave response (high indicates erro)
+//    })
+//  val idle:: wr :: rd :: pend :: Nil = Enum(4)
+//    val TAG= 1
+//    val master_wstrb        = WireInit(0.U(8.W))
+//    val buf_state_en        = WireInit(false.B)
+//
+//  // Buffer signals (one entry buffer)
+//    val buf_read_error_in   = WireInit(false.B)
+//    val buf_read_error      = WireInit(false.B)
+//    val buf_rdata           = WireInit(0.U(64.W))
+//    val ahb_hready          = WireInit(Bool(), false.B)
+//    val ahb_hready_q        = WireInit(Bool(), false.B)
+//    val ahb_htrans_in       = WireInit(0.U(2.W))
+//    val ahb_htrans_q        = WireInit(0.U(2.W))
+//    val ahb_hsize_q         = WireInit(0.U(3.W))
+//    val ahb_hwrite_q        = WireInit(Bool(), false.B)
+//    val ahb_haddr_q         = WireInit(0.U(32.W))
+//    val ahb_hwdata_q        = WireInit(0.U(64.W))
+//    val ahb_hresp_q         = WireInit(Bool(), false.B)
+//
+//    //Miscellaneous signals
+//    val ahb_addr_in_iccm    = WireInit(Bool(), false.B)
+//    val ahb_addr_in_iccm_region_nc = WireInit(Bool(), false.B)
+//
+//    // signals needed for the read data coming back from the core and to block any further commands as AHB is a blocking bus
+//    val buf_rdata_en        = WireInit(Bool(), false.B)
+//    val ahb_bus_addr_clk_en = WireInit(Bool(), false.B)
+//    val buf_rdata_clk_en    = WireInit(Bool(), false.B)
+//    val ahb_clk             = Wire(Clock())
+//    val ahb_addr_clk        = Wire(Clock())
+//    val buf_rdata_clk       = Wire(Clock())
+//
+//    // Command buffer is the holding station where we convert to AXI and send to core
+//    val cmdbuf_wr_en        = WireInit(Bool(), false.B)
+//    val cmdbuf_rst          = WireInit(Bool(), false.B)
+//    val cmdbuf_full         = WireInit(Bool(), false.B)
+//    val cmdbuf_vld          = WireInit(Bool(), false.B)
+//    val cmdbuf_write        = WireInit(Bool(), false.B)
+//    val cmdbuf_size         = WireInit(0.U(2.W))
+//    val cmdbuf_wstrb        = WireInit(0.U(8.W))
+//    val cmdbuf_addr         = WireInit(0.U(32.W))
+//    val cmdbuf_wdata        = WireInit(0.U(64.W))
+//    val bus_clk             = Wire(Clock())
+//
+//  // Address check  dccm
+//    val (ahb_addr_in_dccm, ahb_addr_in_dccm_region_nc) = rvrangecheck_ch(ahb_haddr_q.asUInt,DCCM_SADR.asUInt(),DCCM_SIZE)
+//
+//  // Address check  iccm
+//    if (ICCM_ENABLE == 1) {
+//    ahb_addr_in_iccm            := rvrangecheck_ch(ahb_haddr_q.asUInt, ICCM_SADR.asUInt(), ICCM_SIZE)._1
+//    ahb_addr_in_iccm_region_nc  := rvrangecheck_ch(ahb_haddr_q.asUInt, ICCM_SADR.asUInt(), ICCM_SIZE)._2
+//  }
+//  else {
+//  ahb_addr_in_iccm              := 0.U
+//  ahb_addr_in_iccm_region_nc    := 0.U
+//
+//
+//  // PIC memory address check
+//  val (ahb_addr_in_pic, ahb_addr_in_pic_region_nc) = rvrangecheck_ch(ahb_haddr_q.asUInt,PIC_BASE_ADDR.asUInt(),PIC_SIZE)
+//
+//  // FSM to control the bus states and when to block the hready and load the command buffer
+//    val buf_state                = WireInit(idle)
+//    val buf_nxtstate             = WireInit(idle)
+//    buf_nxtstate                := idle
+//    buf_state_en                := false.B
+//    buf_rdata_en                := false.B      // signal to load the buffer when the core sends read data back
+//    buf_read_error_in           := false.B      // signal indicating that an error came back with the read from the core
+//    cmdbuf_wr_en                := false.B      // all clear from the gasket to load the buffer with the command for reads, command/dat for writes
+//    switch(buf_state){
+//
+//    is(idle) {
+//        buf_nxtstate            := Mux(io.ahb_hwrite, wr, rd)
+//        buf_state_en            := ahb_hready & io.ahb_htrans(1) & io.ahb_hsel // only transition on a valid hrtans
+//    }
+//    is(wr) { // Write command recieved last cycle
+//        buf_nxtstate            := Mux((io.ahb_hresp | (io.ahb_htrans(1, 0) === "b0".U) | !io.ahb_hsel).asBool, idle, Mux(io.ahb_hwrite, wr, rd))
+//        buf_state_en            := (!cmdbuf_full | io.ahb_hresp)
+//        cmdbuf_wr_en            := !cmdbuf_full & !(io.ahb_hresp | ((io.ahb_htrans(1, 0) === "b01".U) & io.ahb_hsel)) // Dont send command to the buffer in case of an error or when the master is not ready with the data now.
+//
+//    is(rd) { // Read command recieved last cycle.
+//        buf_nxtstate            := Mux(io.ahb_hresp, idle, pend) // If error go to idle, else wait for read data
+//        buf_state_en            := (!cmdbuf_full | io.ahb_hresp) // only when command can go, or if its an error
+//        cmdbuf_wr_en            := !io.ahb_hresp & !cmdbuf_full // send command only when no error
+//
+//    is(pend) { // Read Command has been sent. Waiting on Data.
+//        buf_nxtstate            := idle // go back for next command and present data next cycle
+//        buf_state_en            := io.axi_rvalid & !cmdbuf_write // read data is back
+//        buf_rdata_en            := buf_state_en // buffer the read data coming back from core
+//        buf_read_error_in       := buf_state_en & io.axi_rresp(1,0).orR // buffer error flag if return has Error ( ECC )
+//
+//
+//    buf_state                   := withClock(ahb_clk){RegEnable(buf_nxtstate,0.U,buf_state_en.asBool())}
+//
+//    master_wstrb                :=  (Fill(8,ahb_hsize_q(2,0) === 0.U)  & (1.U  << ahb_haddr_q(2,0)).asUInt()) |
+//                                    (Fill(8,ahb_hsize_q(2,0) === 1.U)  & (3.U  << ahb_haddr_q(2,0)).asUInt()) |
+//                                    (Fill(8,ahb_hsize_q(2,0) === 2.U)  & (15.U << ahb_haddr_q(2,0)).asUInt()) |
+//                                    (Fill(8,ahb_hsize_q(2,0) === 3.U)  &  255.U)
+//
+//    // AHB signals
+//    io.ahb_hreadyout            := Mux(io.ahb_hresp,(ahb_hresp_q & !ahb_hready_q), ((!cmdbuf_full | (buf_state === idle)) & !(buf_state === rd | buf_state === pend)  & !buf_read_error))
+//    ahb_hready                  := io.ahb_hreadyout & io.ahb_hreadyin
+//    ahb_htrans_in               := Fill(2,io.ahb_hsel) & io.ahb_htrans(1,0)
+//    io.ahb_hrdata               := buf_rdata(63,0)
+//    io.ahb_hresp                := ((ahb_htrans_q(1,0) =/= 0.U) & (buf_state =/= idle)  &
+//                                   ((!(ahb_addr_in_dccm | ahb_addr_in_iccm)) |                                                                                   // request not for ICCM or DCCM
+//                                   ((ahb_addr_in_iccm | (ahb_addr_in_dccm &  ahb_hwrite_q)) & !((ahb_hsize_q(1,0) === 2.U) | (ahb_hsize_q(1,0) === 3.U))) |    // ICCM Rd/Wr OR DCCM Wr not the right size
+//                                   ((ahb_hsize_q(2,0) === 1.U) & ahb_haddr_q(0))   |                                                                             // HW size but unaligned
+//                                   ((ahb_hsize_q(2,0) === 2.U) & (ahb_haddr_q(1,0)).orR) |                                                                          // W size but unaligned
+//                                   ((ahb_hsize_q(2,0) === 3.U) & (ahb_haddr_q(2,0)).orR))) |                                                                        // DW size but unaligned
+//                                   buf_read_error |                                                                                                              // Read ECC error
+//                                   (ahb_hresp_q & !ahb_hready_q)
+//
+//    // Buffer signals - needed for the read data and ECC error response
+//    buf_rdata                   := withClock(buf_rdata_clk){RegNext(io.axi_rdata,0.U)}
+//    buf_read_error              := withClock(ahb_clk){RegNext(buf_read_error_in,0.U)}
+//
+//    // All the Master signals are captured before presenting it to the command buffer. We check for Hresp before sending it to the cmd buffer.
+//    ahb_hresp_q                 := withClock(ahb_clk){RegNext(io.ahb_hresp,0.U)}
+//    ahb_hready_q                := withClock(ahb_clk){RegNext(ahb_hready,0.U)}
+//    ahb_htrans_q                := withClock(ahb_clk){RegNext(ahb_htrans_in,0.U)}
+//    ahb_hsize_q                 := withClock(ahb_addr_clk){RegNext(io.ahb_hsize,0.U)}
+//    ahb_hwrite_q                := withClock(ahb_addr_clk){RegNext(io.ahb_hwrite,0.U)}
+//    ahb_haddr_q                 := withClock(ahb_addr_clk){RegNext(io.ahb_haddr,0.U)}
+//
+//    // Clock header logic
+//    ahb_bus_addr_clk_en         := io.bus_clk_en & (ahb_hready & io.ahb_htrans(1))
+//    buf_rdata_clk_en            := io.bus_clk_en & buf_rdata_en;
+//
+//    ahb_clk                     := rvclkhdr(clock, io.bus_clk_en, io.scan_mode)
+//    ahb_addr_clk                := rvclkhdr(clock, ahb_bus_addr_clk_en, io.scan_mode)
+//    buf_rdata_clk               := rvclkhdr(clock, buf_rdata_clk_en, io.scan_mode)
+//
+//    cmdbuf_rst                  := (((io.axi_awvalid & io.axi_awready) | (io.axi_arvalid & io.axi_arready)) & !cmdbuf_wr_en) | (io.ahb_hresp & !cmdbuf_write)
+//    cmdbuf_full                 := (cmdbuf_vld & !((io.axi_awvalid & io.axi_awready) | (io.axi_arvalid & io.axi_arready)))
+//
+//    //rvdffsc
+//    cmdbuf_vld                  := withClock(bus_clk) {
+//        RegEnable("b1".U & Fill("b1".U.getWidth, cmdbuf_rst), 0.U, cmdbuf_wr_en.asBool())
+//
+//    //dffs
+//    cmdbuf_write                := withClock(bus_clk) {
+//        RegEnable(ahb_hwrite_q, 0.U, cmdbuf_wr_en.asBool())
+//
+//    cmdbuf_size                 := withClock(bus_clk) {
+//        RegEnable(ahb_hsize_q, 0.U, cmdbuf_wr_en.asBool())
+//
+//    cmdbuf_wstrb                := withClock(bus_clk) {
+//        RegEnable(master_wstrb, 0.U, cmdbuf_wr_en.asBool())
+//
+//    //rvdffe
+//    cmdbuf_addr := RegEnable(ahb_haddr_q, 0.U, cmdbuf_wr_en.asBool())
+//    cmdbuf_wdata := RegEnable(io.ahb_hwdata, 0.U, cmdbuf_wr_en.asBool())
+//
+//    // AXI Write Command Channel
+//    io.axi_awvalid          := cmdbuf_vld & cmdbuf_write
+//    io.axi_awid             := Fill(TAG, 0.U)
+//    io.axi_awaddr           := cmdbuf_addr
+//    io.axi_awsize           := Cat("b0".U, cmdbuf_size(1, 0))
+//    io.axi_awprot           := Fill(3, 0.U)
+//    io.axi_awlen            := Fill(8, 0.U)
+//    io.axi_awburst          := "b01".U
+//    // AXI Write Data Channel - This is tied to the command channel as we only write the command buffer once we have the data.
+//    io.axi_wvalid           := cmdbuf_vld & cmdbuf_write
+//    io.axi_wdata            := cmdbuf_wdata
+//    io.axi_wstrb            := cmdbuf_wstrb
+//    io.axi_wlast            := "b1".U
+//    // AXI Write Response - Always ready. AHB does not require a write response.
+//    io.axi_bready           := "b1".U
+//    // AXI Read Channels
+//    io.axi_arvalid          := cmdbuf_vld & !cmdbuf_write
+//    io.axi_arid             := Fill(TAG, 0.U)
+//    io.axi_araddr           := cmdbuf_addr
+//    io.axi_arsize           := Cat("b0".U, cmdbuf_size(1, 0))
+//    io.axi_arprot           := Fill(3, 0.U)
+//    io.axi_arlen            := Fill(8, 0.U)
+//    io.axi_arburst          := "b01".U
+//    // AXI Read Response Channel - Always ready as AHB reads are blocking and the the buffer is available for the read coming back always.
+//    io.axi_rready           := true.B
+//
+//
+//    bus_clk                 := rvclkhdr(clock, io.bus_clk_en, io.scan_mode)
+//}
+//object AHB_main extends App {
+//    println("Generate Verilog")
+//    println((new chisel3.stage.ChiselStage).emitVerilog(new ahb_to_axi4()))
diff --git a/src/main/scala/lib/axi4_to_ahb.scala b/src/main/scala/lib/axi4_to_ahb.scala
new file mode 100644
index 00000000..4484873e
--- /dev/null
+++ b/src/main/scala/lib/axi4_to_ahb.scala
@@ -0,0 +1,442 @@
+package lib
+
+import chisel3._
+import chisel3.util._
+
+trait Config {
+  val TAG = 1
+}
+
+class axi4_to_ahb_IO extends Bundle with Config {
+
+  val scan_mode = Input(Bool())
+  val bus_clk_en = Input(Bool())
+  val clk_override = Input(Bool())
+  val axi_awvalid = Input(Bool())
+  val axi_awid = Input(UInt(TAG.W)) // [TAG-1:0]
+  val axi_awaddr = Input(UInt(32.W)) // [31:0]
+  val axi_awsize = Input(UInt(3.W)) // [2:0]
+  val axi_awprot = Input(UInt(3.W)) // [2:0]
+  val axi_wvalid = Input(Bool())
+  val axi_wdata = Input(UInt(64.W)) // [63:0]
+  val axi_wstrb = Input(UInt(8.W)) // [7:0]
+  val axi_wlast = Input(Bool())
+  val axi_bready = Input(Bool())
+  val axi_arvalid = Input(Bool())
+  val axi_arid = Input(UInt(TAG.W)) // [TAG-1:0]
+  val axi_araddr = Input(UInt(32.W)) // [31:0]
+  val axi_arsize = Input(UInt(3.W)) // [2:0]
+  val axi_arprot = Input(UInt(3.W)) // [2:0]
+  val axi_rready = Input(Bool())
+  val ahb_hrdata = Input(UInt(64.W)) // [63:0]    // ahb bus read data
+  val ahb_hready = Input(Bool()) // slave ready to accept transaction
+  val ahb_hresp = Input(Bool()) // slave response (high indicates erro)
+  //----------------------------outputs---------------------------
+  val axi_awready = Output(Bool())
+  val axi_wready = Output(Bool())
+  val axi_bvalid = Output(Bool())
+  val axi_bresp = Output(UInt(2.W)) // [1:0]]
+  val axi_bid = Output(UInt(TAG.W)) // [TAG-1:0]
+  // AXI Read Channels
+  val axi_arready = Output(Bool())
+  val axi_rvalid = Output(Bool())
+  val axi_rid = Output(UInt(TAG.W)) // [TAG-1:0]
+  val axi_rdata = Output(UInt(32.W)) // [63:0]
+  val axi_rresp = Output(UInt(2.W)) // 1:0]
+  val axi_rlast = Output(Bool())
+  // AHB-Lite signals
+  val ahb_haddr = Output(UInt(32.W)) // [31:0]  // ahb bus address
+  val ahb_hburst = Output(UInt(3.W)) // [2:0]   // tied to 0
+  val ahb_hmastlock = Output(Bool()) // tied to 0
+  val ahb_hprot = Output(UInt(4.W)) // [3:0]   // tied to 4'b0011
+  val ahb_hsize = Output(UInt(3.W)) // [2:0]   // size of bus transaction (possible values 0,1,2,3)
+  val ahb_htrans = Output(UInt(2.W))
+  val ahb_hwrite = Output(Bool()) // ahb bus write
+  val ahb_hwdata = Output(UInt(64.W)) // [63:0]  // ahb bus write data
+}
+
+class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config {
+  val io = IO(new axi4_to_ahb_IO)
+  val idle :: cmd_rd :: cmd_wr :: data_rd :: data_wr :: done :: stream_rd :: stream_err_rd :: nil = Enum(8)
+  val state = RegInit(idle) // typedef enum
+  val buf_state = RegInit(idle)
+  val buf_nxtstate = RegInit(idle)
+  //logic signals
+  val slave_valid = WireInit(Bool(), init = false.B)
+  val slave_ready = WireInit(Bool(), init = false.B)
+  val slave_tag = WireInit(0.U(TAG.W)) // [TAG-1:0]
+  val slave_rdata = WireInit(0.U(64.W)) // [63:0]
+  val slave_opc = WireInit(0.U(4.W)) // [3:0]
+  val wrbuf_en = WireInit(Bool(), init = false.B)
+  val wrbuf_data_en = WireInit(Bool(), init = false.B)
+  val wrbuf_cmd_sent = WireInit(Bool(), init = false.B)
+  val wrbuf_rst = WireInit(Bool(), init = false.B)
+  val wrbuf_vld = WireInit(Bool(), init = false.B)
+  val wrbuf_data_vld = WireInit(Bool(), init = false.B)
+  val wrbuf_tag = WireInit(0.U(TAG.W)) // [TAG-1:0]
+  val wrbuf_size = WireInit(0.U(3.W)) // [2:0]
+  val wrbuf_addr = WireInit(0.U(32.W)) // [31:0]
+  val wrbuf_data = WireInit(0.U(64.W)) // [63:0]
+  val wrbuf_byteen = WireInit(0.U(8.W)) // [7:0]
+
+  val bus_write_clk_en = WireInit(Bool(), init = false.B)
+  val bus_clk = Wire(Clock())
+  val bus_write_clk = Wire(Clock())
+
+  val master_valid = WireInit(Bool(), init = false.B)
+  val master_ready = WireInit(0.U(1.W))
+  val master_tag = WireInit(0.U(TAG.W)) // [TAG-1:0]
+  val master_addr = WireInit(0.U(32.W)) // [31:0]
+  val master_wdata = WireInit(0.U(64.W)) // [63:0]
+  val master_size = WireInit(0.U(3.W)) // [2:0]
+  val master_opc = WireInit(0.U(3.W)) // [2:0]
+  val master_byteen = WireInit(0.U(8.W)) // [7:0]
+  // Buffer signals (one entry buffer)
+  val buf_addr = WireInit(0.U(32.W)) // [31:0]
+  val buf_size = WireInit(0.U(2.W)) // [1:0]
+  val buf_write = WireInit(Bool(), init = false.B)
+  val buf_byteen = WireInit(0.U(8.W)) // [7:0]
+  val buf_aligned = WireInit(Bool(), init = false.B)
+  val buf_data = WireInit(0.U(64.W)) // [63:0]
+  val buf_tag = WireInit(0.U(TAG.W)) // [TAG-1:0]
+  //Miscellaneous signals
+  val buf_rst = WireInit(Bool(), init = false.B)
+  val buf_tag_in = WireInit(0.U(TAG.W)) // [TAG-1:0]
+  val buf_addr_in = WireInit(0.U(32.W)) // [31:0]
+  val buf_byteen_in = WireInit(0.U(8.W)) // [7:0]
+  val buf_data_in = WireInit(0.U(64.W)) // [63:0]
+  val buf_write_in = WireInit(Bool(), init = false.B)
+  val buf_aligned_in = WireInit(Bool(), init = false.B)
+  val buf_size_in = WireInit(0.U(3.W)) // [2:0]
+
+  val buf_state_en = WireInit(Bool(), init = false.B)
+  val buf_wr_en = WireInit(Bool(), init = false.B)
+  val buf_data_wr_en = WireInit(Bool(), init = false.B)
+  val slvbuf_error_en = WireInit(Bool(), init = false.B)
+  val wr_cmd_vld = WireInit(Bool(), init = false.B)
+
+  val cmd_done_rst = WireInit(Bool(), init = false.B)
+  val cmd_done = WireInit(Bool(), init = false.B)
+  val cmd_doneQ = WireInit(Bool(), init = false.B)
+  val trxn_done = WireInit(Bool(), init = false.B)
+  val buf_cmd_byte_ptr = WireInit(0.U(3.W)) // [2:0]
+  val buf_cmd_byte_ptrQ = WireInit(0.U(3.W)) // [2:0]
+  val buf_cmd_nxtbyte_ptr = WireInit(0.U(3.W)) // [2:0]
+  val buf_cmd_byte_ptr_en = WireInit(Bool(), init = false.B)
+  val found = WireInit(Bool(), init = false.B)
+
+  val slave_valid_pre = WireInit(Bool(), init = false.B)
+  val ahb_hready_q = WireInit(Bool(), init = false.B)
+  val ahb_hresp_q = WireInit(Bool(), init = false.B)
+  val ahb_htrans_q = WireInit(0.U(2.W)) // [1:0]
+  val ahb_hwrite_q = WireInit(Bool(), init = false.B)
+  val ahb_hrdata_q = WireInit(0.U(64.W)) // [63:0]
+
+  val slvbuf_write = WireInit(Bool(), init = false.B)
+  val slvbuf_error = WireInit(Bool(), init = false.B)
+  val slvbuf_tag = WireInit(0.U(TAG.W)) // [TAG-1:0]
+
+  val slvbuf_error_in = WireInit(Bool(), init = false.B)
+  val slvbuf_wr_en = WireInit(Bool(), init = false.B)
+  val bypass_en = WireInit(Bool(), init = false.B)
+  val rd_bypass_idle = WireInit(Bool(), init = false.B)
+
+  val last_addr_en = WireInit(Bool(), init = false.B)
+  val last_bus_addr = WireInit(0.U(32.W)) // [31:0]
+  // Clocks
+  val buf_clken = WireInit(Bool(), init = false.B)
+  val slvbuf_clken = WireInit(Bool(), init = false.B)
+  val ahbm_addr_clken = WireInit(Bool(), init = false.B)
+  val ahbm_data_clken = WireInit(Bool(), init = false.B)
+  val buf_clk = Wire(Clock())
+  //val slvbuf_clk           = Wire(Clock())
+  val ahbm_clk = Wire(Clock())
+  val ahbm_addr_clk = Wire(Clock())
+  val ahbm_data_clk = Wire(Clock())
+
+  def get_write_size(byteen: UInt) = {
+
+    val byteen = WireInit(0.U(8.W))
+
+    val size = ("b11".U & (Fill(2, (byteen(7, 0) === "hff".U))) |
+      ("b10".U & (Fill(2, (byteen(7, 0) === "hf0".U) | (byteen(7, 0) === "h0f".U)))) |
+      ("b01".U & (Fill(2, (byteen(7, 0) === "hc0".U) | (byteen(7, 0) === "h30".U) | (byteen(7, 0) === "h0c".U) | (byteen(7, 0) === "h03".U)))))
+    size
+  }
+
+  def get_write_addr(byteen_e: UInt) = {
+    val byteen_e = WireInit(0.U(8.W))
+    val addr = ("h0".U & (Fill(3, (byteen_e(7, 0) === "hff".U) | (byteen_e(7, 0) === "h0f".U) | (byteen_e(7, 0) === "h03".U))) |
+      ("h2".U & (Fill(3, (byteen_e(7, 0) === "h0c".U)))) |
+      ("h4".U & (Fill(3, ((byteen_e(7, 0) === "hf0".U) | (byteen_e(7, 0) === "h03".U)))) |
+        ("h6".U & (Fill(3, (byteen_e(7, 0) === "hc0".U))))))
+    addr
+  }
+
+  def get_nxtbyte_ptr(current_byte_ptr: UInt, byteen: UInt, get_next: Bool): UInt = {
+    val start_ptr = Mux(get_next, current_byte_ptr + 1.U, current_byte_ptr)
+    val temp = (0 until 8).map(j => (byteen(j) & (j.asUInt() >= start_ptr)) -> j.U)
+    MuxCase(0.U, temp)
+  }
+
+  // Write buffer
+  wrbuf_en := io.axi_awvalid & io.axi_awready & master_ready
+  wrbuf_data_en := io.axi_wvalid & io.axi_wready & master_ready
+  wrbuf_cmd_sent := master_valid & master_ready & (master_opc(2, 1) === "b01".U)
+  wrbuf_rst := wrbuf_cmd_sent & !wrbuf_en
+
+  io.axi_awready := !(wrbuf_vld & !wrbuf_cmd_sent) & master_ready
+  io.axi_wready := !(wrbuf_data_vld & !wrbuf_cmd_sent) & master_ready
+  io.axi_arready := !(wrbuf_vld & wrbuf_data_vld) & master_ready
+  io.axi_rlast := true.B
+
+  wr_cmd_vld := wrbuf_vld & wrbuf_data_vld
+  master_valid := wr_cmd_vld | io.axi_arvalid
+  master_tag := Mux(wr_cmd_vld.asBool(), wrbuf_tag(TAG - 1, 0), io.axi_arid(TAG - 1, 0))
+  master_opc := Mux(wr_cmd_vld.asBool(), "b011".U, "b0".U)
+  master_addr := Mux(wr_cmd_vld.asBool(), wrbuf_addr(31, 0), io.axi_araddr(31, 0))
+  master_size := Mux(wr_cmd_vld.asBool(), wrbuf_size(2, 0), io.axi_arsize(2, 0))
+  master_byteen := wrbuf_byteen(7, 0)
+  master_wdata := wrbuf_data(63, 0)
+
+  // AXI response channel signals
+  io.axi_bvalid := slave_valid & slave_ready & slave_opc(3)
+  io.axi_bresp := Mux(slave_opc(0), "b10".U, Mux(slave_opc(1), "b11".U, "b0".U))
+  io.axi_bid := slave_tag(TAG - 1, 0)
+
+  io.axi_rvalid := slave_valid & slave_ready & (slave_opc(3, 2) === "b0".U)
+  io.axi_rresp := Mux(slave_opc(0), "b10".U, Mux(slave_opc(1), "b11".U, "b0".U))
+  io.axi_rid := slave_tag(TAG - 1, 0)
+  io.axi_rdata := slave_rdata(63, 0)
+  slave_ready := io.axi_bready & io.axi_rready
+
+  // Clock header logic
+  bus_write_clk_en := io.bus_clk_en & ((io.axi_awvalid & io.axi_awready) | (io.axi_wvalid & io.axi_wready))
+
+  bus_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode)
+  bus_write_clk := rvclkhdr(clock, bus_write_clk_en.asBool(), io.scan_mode)
+
+  //State machine
+  io.ahb_htrans := 0.U
+  master_ready := 0.U
+  buf_state_en := 0.U
+  switch(buf_state) {
+    is(idle) {
+      master_ready := 1.U
+      buf_write_in := (master_opc(2, 1) === "b01".U)
+      buf_nxtstate := Mux(buf_write_in.asBool(), cmd_wr, cmd_rd)
+      buf_state_en := master_valid & master_ready
+      buf_wr_en := buf_state_en
+      buf_data_wr_en := buf_state_en & (buf_nxtstate === cmd_wr)
+      buf_cmd_byte_ptr_en := buf_state_en
+      // ---------------------FROM FUNCTION CHECK LATER
+      buf_cmd_byte_ptr := Mux(buf_write_in.asBool(), (get_nxtbyte_ptr("b0".U, buf_byteen_in(7, 0), false.B)).asInstanceOf[UInt], master_addr(2, 0))
+      bypass_en := buf_state_en
+      rd_bypass_idle := bypass_en & (buf_nxtstate === cmd_rd)
+      io.ahb_htrans := (Fill(2, bypass_en)) & "b10".U
+    }
+
+    is(cmd_rd) {
+      buf_nxtstate := Mux((master_valid & (master_opc(2, 0) === "b000".U)).asBool(), stream_rd, data_rd)
+      buf_state_en := ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & !ahb_hwrite_q
+      cmd_done := buf_state_en & !master_valid
+      slvbuf_wr_en := buf_state_en
+      master_ready := (ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & !ahb_hwrite_q) & (buf_nxtstate === stream_rd) ////////////TBD////////
+      buf_wr_en := master_ready
+      bypass_en := master_ready & master_valid
+      buf_cmd_byte_ptr := Mux(bypass_en.asBool(), master_addr(2, 0), buf_addr(2, 0))
+      io.ahb_htrans := "b10".U & (Fill(2, (!buf_state_en | bypass_en)))
+    }
+
+    is(stream_rd) {
+      master_ready := (ahb_hready_q & !ahb_hresp_q) & !(master_valid & master_opc(2, 1) === "b01".U)
+      buf_wr_en := (master_valid & master_ready & (master_opc(2, 0) === "b000".U)) // update the fifo if we are streaming the read commands
+      buf_nxtstate := Mux(ahb_hresp_q.asBool(), stream_err_rd, Mux(buf_wr_en.asBool(), stream_rd, data_rd)) // assuming that the master accpets the slave response right away.
+      buf_state_en := (ahb_hready_q | ahb_hresp_q)
+      buf_data_wr_en := buf_state_en
+      slvbuf_error_in := ahb_hresp_q
+      slvbuf_error_en := buf_state_en
+      slave_valid_pre := buf_state_en & !ahb_hresp_q // send a response right away if we are not going through an error response.
+      cmd_done := buf_state_en & !master_valid // last one of the stream should not send a htrans
+      bypass_en := master_ready & master_valid & (buf_nxtstate === stream_rd) & buf_state_en
+      buf_cmd_byte_ptr := Mux(bypass_en.asBool(), master_addr(2, 0), buf_addr(2, 0))
+      io.ahb_htrans := "b10".U & Fill(2, (!((buf_nxtstate =/= stream_rd) & buf_state_en)))
+      slvbuf_wr_en := buf_wr_en // shifting the contents from the buf to slv_buf for streaming cases
+    }
+
+    is(stream_err_rd) {
+      buf_nxtstate := data_rd
+      buf_state_en := ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & !ahb_hwrite_q
+      slave_valid_pre := buf_state_en
+      slvbuf_wr_en := buf_state_en // Overwrite slvbuf with buffer
+      buf_cmd_byte_ptr := buf_addr(2, 0)
+      io.ahb_htrans := "b10".U(2.W) & Fill(2, !buf_state_en)
+    }
+
+    is(data_rd) {
+      buf_nxtstate := done
+      buf_state_en := (ahb_hready_q | ahb_hresp_q)
+      buf_data_wr_en := buf_state_en
+      slvbuf_error_in := ahb_hresp_q
+      slvbuf_error_en := buf_state_en
+      slvbuf_wr_en := buf_state_en
+    }
+
+    is(cmd_wr) {
+      buf_nxtstate := data_wr
+      trxn_done := ahb_hready_q & ahb_hwrite_q & (ahb_htrans_q(1, 0) =/= "b0".U)
+      buf_state_en := trxn_done
+      buf_cmd_byte_ptr_en := buf_state_en
+      slvbuf_wr_en := buf_state_en
+      buf_cmd_byte_ptr := Mux(trxn_done.asBool(), (get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B)).asInstanceOf[UInt], buf_cmd_byte_ptrQ)
+      cmd_done := trxn_done & (buf_aligned | (buf_cmd_byte_ptrQ === "b111".U) | (buf_byteen((get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B))) === "b0".U))
+      io.ahb_htrans := Fill(2, !(cmd_done | cmd_doneQ)) & "b10".U
+    }
+
+    is(data_wr) {
+      buf_state_en := (cmd_doneQ & ahb_hready_q) | ahb_hresp_q
+      master_ready := ((cmd_doneQ & ahb_hready_q) | ahb_hresp_q) & !ahb_hresp_q & slave_ready //////////TBD///////// // Ready to accept new command if current command done and no error
+      buf_nxtstate := Mux((ahb_hresp_q | !slave_ready).asBool(), done, Mux((master_valid & master_ready).asBool(), Mux((master_opc(2, 1) === "b01".U), cmd_wr, cmd_rd), idle))
+      slvbuf_error_in := ahb_hresp_q
+      slvbuf_error_en := buf_state_en
+      buf_write_in := (master_opc(2, 1) === "b01".U)
+      buf_wr_en := buf_state_en & ((buf_nxtstate === cmd_wr) | (buf_nxtstate === cmd_rd))
+      buf_data_wr_en := buf_wr_en
+      cmd_done := (ahb_hresp_q | (ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & ((buf_cmd_byte_ptrQ === "b111".U) | (buf_byteen((get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B))) === "b0".U))))
+      bypass_en := buf_state_en & buf_write_in & (buf_nxtstate === cmd_wr) // Only bypass for writes for the time being
+      io.ahb_htrans := Fill(2, (!(cmd_done | cmd_doneQ) | bypass_en)) & "b10".U
+      slave_valid_pre := buf_state_en & (buf_nxtstate =/= done)
+      trxn_done := ahb_hready_q & ahb_hwrite_q & (ahb_htrans_q(1, 0) =/= "b0".U)
+      buf_cmd_byte_ptr_en := trxn_done | bypass_en
+      //val  tmp_func         = get_nxtbyte_ptr(Fill(3,0.U),buf_byteen_in(7,0),false.B)
+      //val  tmp_func2        = get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2,0),buf_byteen(7,0),true.B)
+      buf_cmd_byte_ptr := Mux(bypass_en, get_nxtbyte_ptr(Fill(3, 0.U), buf_byteen_in(7, 0), false.B), Mux(trxn_done, get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B), buf_cmd_byte_ptrQ))
+    }
+    is(done) {
+      buf_nxtstate := idle
+      buf_state_en := slave_ready
+      slvbuf_error_en := true.B
+      slave_valid_pre := true.B
+    }
+  }
+
+  buf_rst := false.B
+  cmd_done_rst := slave_valid_pre
+  buf_addr_in := Cat(master_addr, Mux((buf_aligned_in & (master_opc(2, 1) === "b01".U)).asBool(), get_write_addr(master_byteen(7, 0)), master_addr(2, 0)))
+  buf_tag_in := master_tag(TAG - 1, 0)
+  buf_byteen_in := wrbuf_byteen(7,0)
+  buf_data_in := Mux((buf_state === data_rd), ahb_hrdata_q(63, 0), master_wdata(63, 0))
+  buf_size_in := Mux((buf_aligned_in & (master_size(1, 0) === "b11".U) & (master_opc(2, 1) === "b01".U)).asBool(), get_write_size(master_byteen(7, 0)), master_size(1, 0))
+  buf_aligned_in := (master_opc(2, 0) === "b0".U) | // reads are always aligned since they are either DW or sideeffects
+    (master_size(1, 0) === "b0".U) | (master_size(1, 0) === "b01".U) | (master_size(1, 0) === "b10".U) | // Always aligned for Byte/HW/Word since they can be only for non-idempotent. IFU/SB are always aligned
+    ((master_size(1, 0) === "b11".U) & ((master_byteen(7, 0) === "h3".U) | (master_byteen(7, 0) === "hc".U) | (master_byteen(7, 0) === "h30".U) | (master_byteen(7, 0) === "hc0".U) |
+      (master_byteen(7, 0) === "hf".U) | (master_byteen(7, 0) === "hf0".U) | (master_byteen(7, 0) === "hff".U)))
+  // Generate the ahb signals
+  io.ahb_haddr := Mux(bypass_en.asBool(), Cat(master_addr(31, 3), buf_cmd_byte_ptr(2, 0)), Cat(buf_addr(31, 3), buf_cmd_byte_ptr(2, 0)))
+  io.ahb_hsize := Mux(bypass_en.asBool(), Cat("b0".U, (Fill(2, buf_aligned_in) & buf_size_in(1, 0))), (Cat("b0".U, (Fill(2, buf_aligned) & buf_size(1, 0)))))
+
+  io.ahb_hburst := "b0".U
+  io.ahb_hmastlock := "b0".U
+  io.ahb_hprot := Cat("b001".U, ~io.axi_arprot(2))
+  io.ahb_hwrite := Mux(bypass_en.asBool(), (master_opc(2, 1) === "b01".U), buf_write)
+  io.ahb_hwdata := buf_data(63, 0)
+
+  slave_valid := slave_valid_pre
+  slave_opc := Cat(Mux(slvbuf_write.asBool(), "b11".U, "b00".U), Fill(2, slvbuf_error) & "b10".U)
+  slave_rdata := Mux(slvbuf_error.asBool(), Fill(2, last_bus_addr(31, 0)), Mux((buf_state === done), buf_data(63, 0), ahb_hrdata_q(63, 0)))
+  slave_tag := slvbuf_tag(TAG - 1, 0)
+
+  last_addr_en := (io.ahb_htrans(1, 0) =/= "b0".U) & io.ahb_hready & io.ahb_hwrite
+
+  //rvdffsc
+  wrbuf_vld      := withClock(bus_clk) {RegEnable("b1".U & Fill("b1".U.getWidth, wrbuf_rst), 0.U, wrbuf_en.asBool())}
+  wrbuf_data_vld := withClock(bus_clk) {RegEnable("b1".U & Fill("b1".U.getWidth, wrbuf_rst), 0.U, wrbuf_data_en.asBool())}
+  //rvdffs
+  wrbuf_tag := withClock(bus_clk) {RegEnable(io.axi_awid(TAG - 1, 0), 0.U, wrbuf_en.asBool())}
+  wrbuf_size := withClock(bus_clk) {RegEnable(io.axi_awsize(2, 0), 0.U, wrbuf_en.asBool())}
+  //rvdffe
+  wrbuf_addr := RegEnable(io.axi_awaddr, 0.U, wrbuf_en.asBool())
+  wrbuf_data := RegEnable(io.axi_wdata, 0.U, wrbuf_data_en.asBool())
+  //rvdffs
+  wrbuf_byteen := withClock(bus_clk) {
+    RegEnable(io.axi_wstrb(7, 0), 0.U, wrbuf_data_en.asBool())
+  }
+  last_bus_addr := withClock(ahbm_clk) {
+    RegEnable(io.ahb_haddr(31, 0), 0.U, last_addr_en.asBool())
+  }
+  //sc
+  buf_state := withClock(ahbm_clk) {
+    RegEnable(buf_nxtstate & Fill(buf_nxtstate.getWidth, buf_rst), 0.U, buf_state_en.asBool())
+  }
+  //s
+  buf_write := withClock(buf_clk) {
+    RegEnable(buf_write_in, 0.U, buf_wr_en.asBool())
+  }
+  buf_tag := withClock(buf_clk) {
+    RegEnable(buf_tag_in(TAG - 1, 0), 0.U, buf_wr_en.asBool())
+  }
+  //e
+  buf_addr := RegEnable(buf_addr_in(31, 0), 0.U, (buf_wr_en & io.bus_clk_en).asBool)
+  //s
+  buf_size := withClock(buf_clk) {
+    RegEnable(buf_size(1, 0), 0.U, buf_wr_en.asBool())
+  }
+  buf_aligned := withClock(buf_clk) {
+    RegEnable(buf_aligned_in, 0.U, buf_wr_en.asBool())
+  }
+  buf_byteen := withClock(buf_clk) {
+    RegEnable(buf_byteen(7, 0), 0.U, buf_wr_en.asBool())
+  }
+  //e
+  buf_data := RegEnable(buf_data_in(63, 0), 0.U, (buf_data_wr_en & io.bus_clk_en).asBool())
+  //s
+  slvbuf_write := withClock(buf_clk) {
+    RegEnable(buf_write, 0.U, slvbuf_wr_en.asBool())
+  }
+  slvbuf_tag := withClock(buf_clk) {
+    RegEnable(buf_tag(TAG - 1, 0), 0.U, slvbuf_wr_en.asBool())
+  }
+  slvbuf_error := withClock(ahbm_clk) {
+    RegEnable(slvbuf_error_in, 0.U, slvbuf_error_en.asBool())
+  }
+  //sc
+  cmd_doneQ := withClock(ahbm_clk) {
+    RegEnable("b1".U & Fill("b1".U.getWidth, cmd_done_rst), 0.U, cmd_done.asBool())
+  }
+  //rvdffs
+  buf_cmd_byte_ptrQ := withClock(ahbm_clk) {
+    RegEnable(buf_cmd_byte_ptr(2, 0), 0.U, buf_cmd_byte_ptr_en.asBool())
+  }
+
+  //rvdff
+  ahb_hready_q := withClock(ahbm_clk) {
+    RegNext(io.ahb_hready, 0.U)
+  }
+  ahb_htrans_q := withClock(ahbm_clk) {
+    RegNext(io.ahb_htrans(1, 0), 0.U)
+  }
+  ahb_hwrite_q := withClock(ahbm_addr_clk) {
+    RegNext(io.ahb_hwrite, 0.U)
+  }
+  ahb_hresp_q := withClock(ahbm_clk) {
+    RegNext(io.ahb_hresp, 0.U)
+  }
+  ahb_hrdata_q := withClock(ahbm_data_clk) {
+    RegNext(io.ahb_hrdata(63, 0), 0.U)
+  }
+
+  buf_clken := io.bus_clk_en & (buf_wr_en | slvbuf_wr_en | io.clk_override)
+  ahbm_addr_clken := io.bus_clk_en & ((io.ahb_hready & io.ahb_htrans(1)) | io.clk_override)
+  ahbm_data_clken := io.bus_clk_en & ((buf_state =/= idle) | io.clk_override)
+
+  //Clkhdr
+  buf_clk := rvclkhdr(clock, buf_clken, io.scan_mode)
+  ahbm_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode)
+  ahbm_addr_clk := rvclkhdr(clock, ahbm_addr_clken, io.scan_mode)
+  ahbm_data_clk := rvclkhdr(clock, ahbm_data_clken, io.scan_mode)
+}
+
+object AXImain extends App {
+  println("Generate Verilog")
+  println((new chisel3.stage.ChiselStage).emitVerilog(new axi4_to_ahb()))
+}
\ No newline at end of file
diff --git a/src/main/scala/lib/el2_lib.scala b/src/main/scala/lib/el2_lib.scala
index 8a026cf8..75e3e945 100644
--- a/src/main/scala/lib/el2_lib.scala
+++ b/src/main/scala/lib/el2_lib.scala
@@ -170,6 +170,8 @@ trait el2_lib extends param{
   val DATA_MEM_LINE = MEM_CAL
   val Tag_Word = MEM_CAL._4
 
+  implicit def bool2int(b:Boolean) = if (b) 1 else 0
+
   object rvsyncss {
     def apply(din:UInt,clk:Clock) =withClock(clk){RegNext(withClock(clk){RegNext(din,0.U)},0.U)}
   }
diff --git a/src/main/scala/lib/exp.sc b/src/main/scala/lib/exp.sc
deleted file mode 100644
index e69de29b..00000000
diff --git a/src/main/scala/lsu/el2_lsu.scala b/src/main/scala/lsu/el2_lsu.scala
index 917dc2eb..464f487c 100644
--- a/src/main/scala/lsu/el2_lsu.scala
+++ b/src/main/scala/lsu/el2_lsu.scala
@@ -421,9 +421,9 @@ class el2_lsu extends Module with RequireAsyncReset with param with el2_lib {
   bus_intf.io.end_addr_d                        := lsu_lsc_ctl.io.end_addr_d
   bus_intf.io.end_addr_m                        := lsu_lsc_ctl.io.end_addr_m
   bus_intf.io.end_addr_r                        := lsu_lsc_ctl.io.end_addr_r
-  bus_intf.io.store_data_r                         := dccm_ctl.io.store_data_r
-  bus_intf.io.lsu_pkt_m                          <> lsu_lsc_ctl.io.lsu_pkt_m
-  bus_intf.io.lsu_pkt_r                          <> lsu_lsc_ctl.io.lsu_pkt_r
+  bus_intf.io.store_data_r                      := dccm_ctl.io.store_data_r
+  bus_intf.io.lsu_pkt_m                         <> lsu_lsc_ctl.io.lsu_pkt_m
+  bus_intf.io.lsu_pkt_r                         <> lsu_lsc_ctl.io.lsu_pkt_r
   bus_intf.io.dec_tlu_force_halt                := io.dec_tlu_force_halt
   bus_intf.io.lsu_commit_r                      := lsu_lsc_ctl.io.lsu_commit_r
   bus_intf.io.is_sideeffects_m                  := lsu_lsc_ctl.io.is_sideeffects_m
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