diff --git a/.gitignore b/.gitignore index 241842cf..0b7e860a 100644 --- a/.gitignore +++ b/.gitignore @@ -1,20 +1,51 @@ -design/project/target/ -design/project/project/ +.metals/ +.vscode/ + + +# design/project/target/ +# design/project/project/ +design/project/ design/.idea/ -design/target/ +design/target/streams/ +design/target/.history + +design/target/scala-2.12/ +-design/target/scala-2.12/classes/wrapper* + +generated_rtl/*.sv +verif/sim/*.log +verif/sim/*.s +verif/sim/*.hex +verif/sim/*.dis +verif/sim/*.tbl +verif/sim/vcs* +verif/sim/simv* +verif/sim/quasar* +verif/sim/*.exe +verif/sim/obj* +verif/sim/*.o +verif/sim/ucli.key +verif/sim/vc_hdrs.h +verif/sim/csrc +verif/sim/*.csv +verif/sim/work +verif/sim/*.dump +verif/sim/*.fsdb +FM_WORK +tracer_logs/*.log +verif/LEC/formality_work/formality_log/*.log +verif/LEC/*.fss + design/snapshots/ - -design/dmi_wrapper.sv -design/firrtl_black_box_resource_files.f -design/gated_latch.sv -design/mem.sv -design/quasar_wrapper.anno.json -design/quasar_wrapper.fir - design/src/main/scala/lib/param.scala -generated_rtl/ +design/*.v +design/*.sv +design/*.f +design/*.json +design/*.fir + # soc/ # demo/ diff --git a/design/.idea/.gitignore b/design/.idea/.gitignore deleted file mode 100644 index 26d33521..00000000 --- a/design/.idea/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -# Default ignored files -/shelf/ -/workspace.xml diff --git a/design/.idea/.name b/design/.idea/.name deleted file mode 100644 index ed8791e6..00000000 --- a/design/.idea/.name +++ /dev/null @@ -1 +0,0 @@ -chisel-module-template \ No newline at end of file diff --git a/design/.idea/codeStyles/Project.xml b/design/.idea/codeStyles/Project.xml deleted file mode 100644 index 919ce1f1..00000000 --- a/design/.idea/codeStyles/Project.xml +++ /dev/null @@ -1,7 +0,0 @@ - - - - - - \ No newline at end of file diff --git a/design/.idea/codeStyles/codeStyleConfig.xml b/design/.idea/codeStyles/codeStyleConfig.xml deleted file mode 100644 index a55e7a17..00000000 --- a/design/.idea/codeStyles/codeStyleConfig.xml +++ /dev/null @@ -1,5 +0,0 @@ - - - - \ No newline at end of file diff --git a/design/.idea/compiler.xml b/design/.idea/compiler.xml deleted file mode 100644 index 2503dfae..00000000 --- a/design/.idea/compiler.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - \ No newline at end of file diff --git a/design/.idea/edaphic/defines.xml b/design/.idea/edaphic/defines.xml deleted file mode 100644 index f18bf180..00000000 --- a/design/.idea/edaphic/defines.xml +++ /dev/null @@ -1,358 +0,0 @@ - - - - - - - \ No newline at end of file diff --git a/design/.idea/inspectionProfiles/Project_Default.xml b/design/.idea/inspectionProfiles/Project_Default.xml deleted file mode 100644 index faae18f4..00000000 --- a/design/.idea/inspectionProfiles/Project_Default.xml +++ /dev/null @@ -1,6 +0,0 @@ - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__com_github_nscala_time_nscala_time_2_12_2_22_0_jar.xml b/design/.idea/libraries/sbt__com_github_nscala_time_nscala_time_2_12_2_22_0_jar.xml deleted file mode 100644 index 42693a29..00000000 --- a/design/.idea/libraries/sbt__com_github_nscala_time_nscala_time_2_12_2_22_0_jar.xml +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__com_github_scopt_scopt_2_12_3_7_1_jar.xml b/design/.idea/libraries/sbt__com_github_scopt_scopt_2_12_3_7_1_jar.xml deleted file mode 100644 index 8890a55e..00000000 --- a/design/.idea/libraries/sbt__com_github_scopt_scopt_2_12_3_7_1_jar.xml +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__com_google_protobuf_protobuf_java_3_9_0_jar.xml b/design/.idea/libraries/sbt__com_google_protobuf_protobuf_java_3_9_0_jar.xml deleted file mode 100644 index 39739678..00000000 --- a/design/.idea/libraries/sbt__com_google_protobuf_protobuf_java_3_9_0_jar.xml +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__com_lihaoyi_utest_2_12_0_6_6_jar.xml b/design/.idea/libraries/sbt__com_lihaoyi_utest_2_12_0_6_6_jar.xml deleted file mode 100644 index d7799fe9..00000000 --- a/design/.idea/libraries/sbt__com_lihaoyi_utest_2_12_0_6_6_jar.xml +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__com_thoughtworks_paranamer_paranamer_2_8_jar.xml b/design/.idea/libraries/sbt__com_thoughtworks_paranamer_paranamer_2_8_jar.xml deleted file mode 100644 index e38f590f..00000000 --- a/design/.idea/libraries/sbt__com_thoughtworks_paranamer_paranamer_2_8_jar.xml +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__edu_berkeley_cs_chisel3_2_12_3_3_1_jar.xml b/design/.idea/libraries/sbt__edu_berkeley_cs_chisel3_2_12_3_3_1_jar.xml deleted file mode 100644 index 801c82a9..00000000 --- a/design/.idea/libraries/sbt__edu_berkeley_cs_chisel3_2_12_3_3_1_jar.xml +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__edu_berkeley_cs_chisel3_core_2_12_3_3_1_jar.xml b/design/.idea/libraries/sbt__edu_berkeley_cs_chisel3_core_2_12_3_3_1_jar.xml deleted file mode 100644 index 8c6d70a0..00000000 --- a/design/.idea/libraries/sbt__edu_berkeley_cs_chisel3_core_2_12_3_3_1_jar.xml +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__edu_berkeley_cs_chisel3_macros_2_12_3_3_1_jar.xml b/design/.idea/libraries/sbt__edu_berkeley_cs_chisel3_macros_2_12_3_3_1_jar.xml deleted file mode 100644 index d0e51193..00000000 --- a/design/.idea/libraries/sbt__edu_berkeley_cs_chisel3_macros_2_12_3_3_1_jar.xml +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__edu_berkeley_cs_chisel_iotesters_2_12_1_4_1_jar.xml b/design/.idea/libraries/sbt__edu_berkeley_cs_chisel_iotesters_2_12_1_4_1_jar.xml deleted file mode 100644 index aac72b82..00000000 --- a/design/.idea/libraries/sbt__edu_berkeley_cs_chisel_iotesters_2_12_1_4_1_jar.xml +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__edu_berkeley_cs_chiseltest_2_12_0_2_1_jar.xml b/design/.idea/libraries/sbt__edu_berkeley_cs_chiseltest_2_12_0_2_1_jar.xml deleted file mode 100644 index 73562930..00000000 --- a/design/.idea/libraries/sbt__edu_berkeley_cs_chiseltest_2_12_0_2_1_jar.xml +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__edu_berkeley_cs_firrtl_2_12_1_3_1_jar.xml b/design/.idea/libraries/sbt__edu_berkeley_cs_firrtl_2_12_1_3_1_jar.xml deleted file mode 100644 index cf128575..00000000 --- a/design/.idea/libraries/sbt__edu_berkeley_cs_firrtl_2_12_1_3_1_jar.xml +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__edu_berkeley_cs_firrtl_interpreter_2_12_1_3_1_jar.xml b/design/.idea/libraries/sbt__edu_berkeley_cs_firrtl_interpreter_2_12_1_3_1_jar.xml deleted file mode 100644 index 4b66526d..00000000 --- a/design/.idea/libraries/sbt__edu_berkeley_cs_firrtl_interpreter_2_12_1_3_1_jar.xml +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__edu_berkeley_cs_treadle_2_12_1_2_1_jar.xml b/design/.idea/libraries/sbt__edu_berkeley_cs_treadle_2_12_1_2_1_jar.xml deleted file mode 100644 index c9bf4126..00000000 --- a/design/.idea/libraries/sbt__edu_berkeley_cs_treadle_2_12_1_2_1_jar.xml +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__joda_time_joda_time_2_10_1_jar.xml b/design/.idea/libraries/sbt__joda_time_joda_time_2_10_1_jar.xml deleted file mode 100644 index a30d2dd2..00000000 --- a/design/.idea/libraries/sbt__joda_time_joda_time_2_10_1_jar.xml +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__junit_junit_4_13_jar.xml b/design/.idea/libraries/sbt__junit_junit_4_13_jar.xml deleted file mode 100644 index c94c6bee..00000000 --- a/design/.idea/libraries/sbt__junit_junit_4_13_jar.xml +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__net_jcazevedo_moultingyaml_2_12_0_4_2_jar.xml b/design/.idea/libraries/sbt__net_jcazevedo_moultingyaml_2_12_0_4_2_jar.xml deleted file mode 100644 index 49b1572e..00000000 --- a/design/.idea/libraries/sbt__net_jcazevedo_moultingyaml_2_12_0_4_2_jar.xml +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__org_antlr_antlr4_runtime_4_7_1_jar.xml b/design/.idea/libraries/sbt__org_antlr_antlr4_runtime_4_7_1_jar.xml deleted file mode 100644 index 9b3561bc..00000000 --- a/design/.idea/libraries/sbt__org_antlr_antlr4_runtime_4_7_1_jar.xml +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__org_apache_commons_commons_lang3_3_9_jar.xml b/design/.idea/libraries/sbt__org_apache_commons_commons_lang3_3_9_jar.xml deleted file mode 100644 index 0ccb0703..00000000 --- a/design/.idea/libraries/sbt__org_apache_commons_commons_lang3_3_9_jar.xml +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__org_apache_commons_commons_text_1_8_jar.xml b/design/.idea/libraries/sbt__org_apache_commons_commons_text_1_8_jar.xml deleted file mode 100644 index 8bddb778..00000000 --- a/design/.idea/libraries/sbt__org_apache_commons_commons_text_1_8_jar.xml +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__org_fusesource_jansi_jansi_1_11_jar.xml b/design/.idea/libraries/sbt__org_fusesource_jansi_jansi_1_11_jar.xml deleted file mode 100644 index e31f80a8..00000000 --- a/design/.idea/libraries/sbt__org_fusesource_jansi_jansi_1_11_jar.xml +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__org_hamcrest_hamcrest_core_1_3_jar.xml b/design/.idea/libraries/sbt__org_hamcrest_hamcrest_core_1_3_jar.xml deleted file mode 100644 index a56afef2..00000000 --- a/design/.idea/libraries/sbt__org_hamcrest_hamcrest_core_1_3_jar.xml +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__org_joda_joda_convert_2_2_0_jar.xml b/design/.idea/libraries/sbt__org_joda_joda_convert_2_2_0_jar.xml deleted file mode 100644 index 00735961..00000000 --- a/design/.idea/libraries/sbt__org_joda_joda_convert_2_2_0_jar.xml +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__org_json4s_json4s_ast_2_12_3_6_8_jar.xml b/design/.idea/libraries/sbt__org_json4s_json4s_ast_2_12_3_6_8_jar.xml deleted file mode 100644 index e203171e..00000000 --- a/design/.idea/libraries/sbt__org_json4s_json4s_ast_2_12_3_6_8_jar.xml +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__org_json4s_json4s_core_2_12_3_6_8_jar.xml b/design/.idea/libraries/sbt__org_json4s_json4s_core_2_12_3_6_8_jar.xml deleted file mode 100644 index 085c408a..00000000 --- a/design/.idea/libraries/sbt__org_json4s_json4s_core_2_12_3_6_8_jar.xml +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__org_json4s_json4s_native_2_12_3_6_8_jar.xml b/design/.idea/libraries/sbt__org_json4s_json4s_native_2_12_3_6_8_jar.xml deleted file mode 100644 index 157eee7a..00000000 --- a/design/.idea/libraries/sbt__org_json4s_json4s_native_2_12_3_6_8_jar.xml +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__org_json4s_json4s_scalap_2_12_3_6_8_jar.xml b/design/.idea/libraries/sbt__org_json4s_json4s_scalap_2_12_3_6_8_jar.xml deleted file mode 100644 index f8306d58..00000000 --- a/design/.idea/libraries/sbt__org_json4s_json4s_scalap_2_12_3_6_8_jar.xml +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__org_portable_scala_portable_scala_reflect_2_12_0_1_0_jar.xml b/design/.idea/libraries/sbt__org_portable_scala_portable_scala_reflect_2_12_0_1_0_jar.xml deleted file mode 100644 index c5f2a7fa..00000000 --- a/design/.idea/libraries/sbt__org_portable_scala_portable_scala_reflect_2_12_0_1_0_jar.xml +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__org_scala_lang_modules_scala_jline_2_12_1_jar.xml b/design/.idea/libraries/sbt__org_scala_lang_modules_scala_jline_2_12_1_jar.xml deleted file mode 100644 index 3c04dea8..00000000 --- a/design/.idea/libraries/sbt__org_scala_lang_modules_scala_jline_2_12_1_jar.xml +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__org_scala_lang_modules_scala_xml_2_12_1_2_0_jar.xml b/design/.idea/libraries/sbt__org_scala_lang_modules_scala_xml_2_12_1_2_0_jar.xml deleted file mode 100644 index e150ef26..00000000 --- a/design/.idea/libraries/sbt__org_scala_lang_modules_scala_xml_2_12_1_2_0_jar.xml +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__org_scala_lang_scala_library_2_12_10_jar.xml b/design/.idea/libraries/sbt__org_scala_lang_scala_library_2_12_10_jar.xml deleted file mode 100644 index 7017716c..00000000 --- a/design/.idea/libraries/sbt__org_scala_lang_scala_library_2_12_10_jar.xml +++ /dev/null @@ -1,25 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__org_scala_lang_scala_reflect_2_12_10_jar.xml b/design/.idea/libraries/sbt__org_scala_lang_scala_reflect_2_12_10_jar.xml deleted file mode 100644 index 63706974..00000000 --- a/design/.idea/libraries/sbt__org_scala_lang_scala_reflect_2_12_10_jar.xml +++ /dev/null @@ -1,15 +0,0 @@ - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__org_scala_sbt_test_interface_1_0_jar.xml b/design/.idea/libraries/sbt__org_scala_sbt_test_interface_1_0_jar.xml deleted file mode 100644 index 75b8b51d..00000000 --- a/design/.idea/libraries/sbt__org_scala_sbt_test_interface_1_0_jar.xml +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__org_scalacheck_scalacheck_2_12_1_14_3_jar.xml b/design/.idea/libraries/sbt__org_scalacheck_scalacheck_2_12_1_14_3_jar.xml deleted file mode 100644 index f55bc1f8..00000000 --- a/design/.idea/libraries/sbt__org_scalacheck_scalacheck_2_12_1_14_3_jar.xml +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__org_scalactic_scalactic_2_12_3_0_8_jar.xml b/design/.idea/libraries/sbt__org_scalactic_scalactic_2_12_3_0_8_jar.xml deleted file mode 100644 index 7465d0fa..00000000 --- a/design/.idea/libraries/sbt__org_scalactic_scalactic_2_12_3_0_8_jar.xml +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__org_scalatest_scalatest_2_12_3_0_8_jar.xml b/design/.idea/libraries/sbt__org_scalatest_scalatest_2_12_3_0_8_jar.xml deleted file mode 100644 index ab74a504..00000000 --- a/design/.idea/libraries/sbt__org_scalatest_scalatest_2_12_3_0_8_jar.xml +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/libraries/sbt__org_yaml_snakeyaml_1_26_jar.xml b/design/.idea/libraries/sbt__org_yaml_snakeyaml_1_26_jar.xml deleted file mode 100644 index ad190242..00000000 --- a/design/.idea/libraries/sbt__org_yaml_snakeyaml_1_26_jar.xml +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/misc.xml b/design/.idea/misc.xml deleted file mode 100644 index 261ac96c..00000000 --- a/design/.idea/misc.xml +++ /dev/null @@ -1,894 +0,0 @@ - - - - - - - \ No newline at end of file diff --git a/design/.idea/modules.xml b/design/.idea/modules.xml deleted file mode 100644 index 4723e5e0..00000000 --- a/design/.idea/modules.xml +++ /dev/null @@ -1,9 +0,0 @@ - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/modules/chisel-module-template-build.iml b/design/.idea/modules/chisel-module-template-build.iml deleted file mode 100644 index 0943f635..00000000 --- a/design/.idea/modules/chisel-module-template-build.iml +++ /dev/null @@ -1,114 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/modules/chisel-module-template.iml b/design/.idea/modules/chisel-module-template.iml deleted file mode 100644 index 73f7cfc7..00000000 --- a/design/.idea/modules/chisel-module-template.iml +++ /dev/null @@ -1,52 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/sbt.xml b/design/.idea/sbt.xml deleted file mode 100644 index 742067a0..00000000 --- a/design/.idea/sbt.xml +++ /dev/null @@ -1,17 +0,0 @@ - - - - - - \ No newline at end of file diff --git a/design/.idea/scala_compiler.xml b/design/.idea/scala_compiler.xml deleted file mode 100644 index d400f5af..00000000 --- a/design/.idea/scala_compiler.xml +++ /dev/null @@ -1,14 +0,0 @@ - - - - - - - - - - - - - - \ No newline at end of file diff --git a/design/.idea/vcs.xml b/design/.idea/vcs.xml deleted file mode 100644 index 288b36b1..00000000 --- a/design/.idea/vcs.xml +++ /dev/null @@ -1,7 +0,0 @@ - - - - - - - \ No newline at end of file diff --git a/design/project/build.properties b/design/project/build.properties deleted file mode 100644 index b53dc26f..00000000 --- a/design/project/build.properties +++ /dev/null @@ -1 +0,0 @@ -sbt.version = 1.3.10 diff --git a/design/project/plugins.sbt b/design/project/plugins.sbt deleted file mode 100644 index 5708f81a..00000000 --- a/design/project/plugins.sbt +++ /dev/null @@ -1 +0,0 @@ -logLevel := Level.Warn diff --git a/design/project/project/target/config-classes/$11a24688b8328723cd4a$.class b/design/project/project/target/config-classes/$11a24688b8328723cd4a$.class deleted file mode 100644 index 21314f4d..00000000 Binary files a/design/project/project/target/config-classes/$11a24688b8328723cd4a$.class and /dev/null differ diff --git a/design/project/project/target/config-classes/$11a24688b8328723cd4a.cache b/design/project/project/target/config-classes/$11a24688b8328723cd4a.cache deleted file mode 100644 index 050f36c6..00000000 --- a/design/project/project/target/config-classes/$11a24688b8328723cd4a.cache +++ /dev/null @@ -1 +0,0 @@ -sbt.internal.DslEntry \ No newline at end of file diff --git a/design/project/project/target/config-classes/$11a24688b8328723cd4a.class b/design/project/project/target/config-classes/$11a24688b8328723cd4a.class deleted file mode 100644 index e7de5a66..00000000 Binary files a/design/project/project/target/config-classes/$11a24688b8328723cd4a.class and /dev/null differ diff --git a/design/project/target/.sbt-compilation-infos/swerv-chislified-compile/.sbt-idea-lock b/design/project/target/.sbt-compilation-infos/swerv-chislified-compile/.sbt-idea-lock deleted file mode 100644 index e69de29b..00000000 diff --git a/design/project/target/config-classes/$04b0ea8a85f2d3c5b201$.class b/design/project/target/config-classes/$04b0ea8a85f2d3c5b201$.class deleted file mode 100644 index d79a0ee0..00000000 Binary files a/design/project/target/config-classes/$04b0ea8a85f2d3c5b201$.class and /dev/null differ diff --git a/design/project/target/config-classes/$04b0ea8a85f2d3c5b201.cache b/design/project/target/config-classes/$04b0ea8a85f2d3c5b201.cache deleted file mode 100644 index 050f36c6..00000000 --- a/design/project/target/config-classes/$04b0ea8a85f2d3c5b201.cache +++ /dev/null @@ -1 +0,0 @@ -sbt.internal.DslEntry \ No newline at end of file diff --git a/design/project/target/config-classes/$04b0ea8a85f2d3c5b201.class b/design/project/target/config-classes/$04b0ea8a85f2d3c5b201.class deleted file mode 100644 index 882fa41e..00000000 Binary files a/design/project/target/config-classes/$04b0ea8a85f2d3c5b201.class and /dev/null differ diff --git a/design/project/target/config-classes/$0852019624a9baefe513$.class b/design/project/target/config-classes/$0852019624a9baefe513$.class deleted file mode 100644 index 4f4a083e..00000000 Binary files a/design/project/target/config-classes/$0852019624a9baefe513$.class and /dev/null differ diff --git a/design/project/target/config-classes/$0852019624a9baefe513.cache b/design/project/target/config-classes/$0852019624a9baefe513.cache deleted file mode 100644 index 050f36c6..00000000 --- a/design/project/target/config-classes/$0852019624a9baefe513.cache +++ /dev/null @@ -1 +0,0 @@ -sbt.internal.DslEntry \ No newline at end of file diff --git a/design/project/target/config-classes/$0852019624a9baefe513.class b/design/project/target/config-classes/$0852019624a9baefe513.class deleted file mode 100644 index 086c9e8a..00000000 Binary files a/design/project/target/config-classes/$0852019624a9baefe513.class and /dev/null differ diff --git a/design/project/target/config-classes/$0a951d39e75735de8e65$.class b/design/project/target/config-classes/$0a951d39e75735de8e65$.class deleted file mode 100644 index 37130e9f..00000000 Binary files a/design/project/target/config-classes/$0a951d39e75735de8e65$.class and /dev/null differ diff --git a/design/project/target/config-classes/$0a951d39e75735de8e65.cache b/design/project/target/config-classes/$0a951d39e75735de8e65.cache deleted file mode 100644 index 050f36c6..00000000 --- a/design/project/target/config-classes/$0a951d39e75735de8e65.cache +++ /dev/null @@ -1 +0,0 @@ -sbt.internal.DslEntry \ No newline at end of file diff --git a/design/project/target/config-classes/$0a951d39e75735de8e65.class b/design/project/target/config-classes/$0a951d39e75735de8e65.class deleted file mode 100644 index b3354fba..00000000 Binary files a/design/project/target/config-classes/$0a951d39e75735de8e65.class and /dev/null differ diff --git a/design/project/target/config-classes/$196903bbd62aff04c011$.class b/design/project/target/config-classes/$196903bbd62aff04c011$.class deleted file mode 100644 index 9d01afe7..00000000 Binary files a/design/project/target/config-classes/$196903bbd62aff04c011$.class and /dev/null differ diff --git a/design/project/target/config-classes/$196903bbd62aff04c011.cache b/design/project/target/config-classes/$196903bbd62aff04c011.cache deleted file mode 100644 index 050f36c6..00000000 --- a/design/project/target/config-classes/$196903bbd62aff04c011.cache +++ /dev/null @@ -1 +0,0 @@ -sbt.internal.DslEntry \ No newline at end of file diff --git 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a/design/project/target/config-classes/$db0ff82aa16445f1f5f0.class and /dev/null differ diff --git a/design/project/target/config-classes/$e1b3d700190c784e124b$.class b/design/project/target/config-classes/$e1b3d700190c784e124b$.class deleted file mode 100644 index 35828bda..00000000 Binary files a/design/project/target/config-classes/$e1b3d700190c784e124b$.class and /dev/null differ diff --git a/design/project/target/config-classes/$e1b3d700190c784e124b.cache b/design/project/target/config-classes/$e1b3d700190c784e124b.cache deleted file mode 100644 index 050f36c6..00000000 --- a/design/project/target/config-classes/$e1b3d700190c784e124b.cache +++ /dev/null @@ -1 +0,0 @@ -sbt.internal.DslEntry \ No newline at end of file diff --git a/design/project/target/config-classes/$e1b3d700190c784e124b.class b/design/project/target/config-classes/$e1b3d700190c784e124b.class deleted file mode 100644 index de0cb0ad..00000000 Binary files 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a/design/project/target/config-classes/$f8acbb999b9697e8aaa5.class and /dev/null differ diff --git a/design/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/inputs b/design/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/inputs deleted file mode 100644 index 72809935..00000000 --- a/design/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/inputs +++ /dev/null @@ -1 +0,0 @@ -2024296794 \ No newline at end of file diff --git a/design/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/output b/design/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/output deleted file mode 100644 index 848de634..00000000 --- a/design/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/output +++ /dev/null @@ -1 +0,0 @@ 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https://repo1.maven.org/maven2/org/jetbrains/scala/scala-compiler-indices-protocol_2.12/1.0.8/scala-compiler-indices-protocol_2.12-1.0.8.jar diff --git a/design/project/target/streams/_global/csrConfiguration/_global/streams/out b/design/project/target/streams/_global/csrConfiguration/_global/streams/out deleted file mode 100644 index e69de29b..00000000 diff --git a/design/project/target/streams/_global/csrProject/_global/streams/out b/design/project/target/streams/_global/csrProject/_global/streams/out deleted file mode 100644 index e69de29b..00000000 diff --git a/design/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/input_dsp b/design/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/input_dsp deleted file mode 100644 index 6cc9b2e0..00000000 --- a/design/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/input_dsp +++ /dev/null @@ -1 +0,0 @@ --1413115869 \ No newline at end of file diff --git a/design/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp b/design/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp deleted file mode 100644 index 2d4cf3d8..00000000 --- a/design/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp +++ /dev/null @@ -1 +0,0 @@ -{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.10\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","startLine"],"path":"(sbt.Classpaths.jvmBaseSettings) Defaults.scala","startLine":2531},"type":"LinePosition"}} \ No newline at end of file diff --git a/design/project/target/streams/_global/ivyConfiguration/_global/streams/out b/design/project/target/streams/_global/ivyConfiguration/_global/streams/out deleted file mode 100644 index e69de29b..00000000 diff --git a/design/project/target/streams/_global/ivySbt/_global/streams/out b/design/project/target/streams/_global/ivySbt/_global/streams/out deleted file mode 100644 index e69de29b..00000000 diff --git a/design/project/target/streams/_global/moduleSettings/_global/streams/out b/design/project/target/streams/_global/moduleSettings/_global/streams/out deleted file mode 100644 index e69de29b..00000000 diff --git a/design/project/target/streams/_global/projectDescriptors/_global/streams/out b/design/project/target/streams/_global/projectDescriptors/_global/streams/out deleted file mode 100644 index e69de29b..00000000 diff --git a/design/project/target/streams/_global/scalaCompilerBridgeScope/_global/streams/out b/design/project/target/streams/_global/scalaCompilerBridgeScope/_global/streams/out deleted file mode 100644 index e69de29b..00000000 diff --git a/design/project/target/streams/_global/update/_global/streams/out b/design/project/target/streams/_global/update/_global/streams/out deleted file mode 100644 index f43eac4e..00000000 --- a/design/project/target/streams/_global/update/_global/streams/out +++ /dev/null @@ -1,3 +0,0 @@ -[debug] "not up to date. inChanged = true, force = false -[debug] Updating ProjectRef(uri("file:/home/users/scratch/komal.javed.data/Quasar/quasar2/design/project/"), "design-build")... -[debug] Done updating ProjectRef(uri("file:/home/users/scratch/komal.javed.data/Quasar/quasar2/design/project/"), "design-build") diff --git a/design/project/target/streams/compile/_global/_global/compileBinaryFileInputs/previous b/design/project/target/streams/compile/_global/_global/compileBinaryFileInputs/previous deleted file mode 100644 index 4fe99a53..00000000 --- a/design/project/target/streams/compile/_global/_global/compileBinaryFileInputs/previous +++ /dev/null @@ -1 +0,0 @@ -["sbt.Task[scala.collection.immutable.Map[java.lang.String, scala.collection.Seq[scala.Tuple2[java.nio.file.Path, sbt.nio.FileStamp]]]]",{"2.12.10":{"hashes":[],"lastModifiedTimes":[["/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/sbt/1.3.10/sbt-1.3.10.jar",1586919578000],["/home/users/komal.javed/.sbt/boot/scala-2.12.10/lib/scala-library.jar",1568150453000],["/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/main_2.12/1.3.10/main_2.12-1.3.10.jar",1586919585000],["/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/io_2.12/1.3.4/io_2.12-1.3.4.jar",1585597895000],["/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/logic_2.12/1.3.10/logic_2.12-1.3.10.jar",1586919582000],["/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/actions_2.12/1.3.10/actions_2.12-1.3.10.jar",1586919588000],["/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/main-settings_2.12/1.3.10/main-settings_2.12-1.3.10.jar",1586919593000],["/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/run_2.12/1.3.10/run_2.12-1.3.10.jar",1586919595000],["/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/command_2.12/1.3.10/command_2.12-1.3.10.jar",1586919569000],["/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/collections_2.12/1.3.10/collections_2.12-1.3.10.jar",1586919594000],["/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/scripted-sbt-redux_2.12/1.3.10/scripted-sbt-redux_2.12-1.3.10.jar",1586919582000],["/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/scripted-plugin_2.12/1.3.10/scripted-plugin_2.12-1.3.10.jar",1586919592000],["/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-lm-integration_2.12/1.3.10/zinc-lm-integration_2.12-1.3.10.jar",1586919595000],["/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar",1554476959000],["/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/launcher-interface/1.1.3/launcher-interface-1.1.3.jar",1566946835000],["/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-api/2.11.2/log4j-api-2.11.2.jar",1549415503000],["/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-core/2.11.2/log4j-core-2.11.2.jar",1549415573000],["/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-slf4j-impl/2.11.2/log4j-slf4j-impl-2.11.2.jar",1549415635000],["/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/cb372/scalacache-caffeine_2.12/0.20.0/scalacache-caffeine_2.12-0.20.0.jar",1510153827000],["/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/lm-coursier-shaded_2.12/2.0.0-RC6-2/lm-coursier-shaded_2.12-2.0.0-RC6-2.jar",1584360077000],["/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-logging_2.12/1.3.3/util-logging_2.12-1.3.3.jar",1576119989000],["/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/librarymanagement-core_2.12/1.3.2/librarymanagement-core_2.12-1.3.2.jar",1586906938000],["/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/librarymanagement-ivy_2.12/1.3.2/librarymanagement-ivy_2.12-1.3.2.jar",1586906935000],["/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/compiler-interface/1.3.5/compiler-interface-1.3.5.jar",1585527738000],["/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-compile_2.12/1.3.5/zinc-compile_2.12-1.3.5.jar",1585527746000],["/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/swoval/file-tree-views/2.1.3/file-tree-views-2.1.3.jar",1562617173000],["/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/net/java/dev/jna/jna/5.5.0/jna-5.5.0.jar",1572453456000],["/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/net/java/dev/jna/jna-platform/5.5.0/jna-platform-5.5.0.jar",1572453499000],["/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-relation_2.12/1.3.3/util-relation_2.12-1.3.3.jar",1576119995000],["/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/completion_2.12/1.3.10/completion_2.12-1.3.10.jar",1586919580000],["/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/task-system_2.12/1.3.10/task-system_2.12-1.3.10.jar",1586919576000],["/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/tasks_2.12/1.3.10/tasks_2.12-1.3.10.jar",1586919595000],["/home/users/komal.jave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\ No newline at end of file diff --git a/design/project/target/streams/compile/_global/_global/compileOutputs/previous b/design/project/target/streams/compile/_global/_global/compileOutputs/previous deleted file mode 100644 index b347b117..00000000 --- a/design/project/target/streams/compile/_global/_global/compileOutputs/previous +++ /dev/null @@ -1 +0,0 @@ -["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/users/scratch/komal.javed.data/Quasar/quasar2/design/project/target/streams/compile/compileOutputs/_global/streams/inc_compile_2.12.zip"]] \ No newline at end of file diff --git a/design/project/target/streams/compile/_global/_global/compileSourceFileInputs/previous b/design/project/target/streams/compile/_global/_global/compileSourceFileInputs/previous deleted file mode 100644 index 15829e87..00000000 --- a/design/project/target/streams/compile/_global/_global/compileSourceFileInputs/previous +++ /dev/null @@ -1 +0,0 @@ -["sbt.Task[scala.collection.immutable.Map[java.lang.String, scala.collection.Seq[scala.Tuple2[java.nio.file.Path, sbt.nio.FileStamp]]]]",{"2.12.10":{"hashes":[],"lastModifiedTimes":[]}}] \ No newline at end of file diff --git a/design/project/target/streams/compile/_global/_global/dependencyClasspathFiles/previous b/design/project/target/streams/compile/_global/_global/dependencyClasspathFiles/previous deleted file mode 100644 index 289bfd84..00000000 --- a/design/project/target/streams/compile/_global/_global/dependencyClasspathFiles/previous +++ /dev/null @@ -1 +0,0 @@ -["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/sbt/1.3.10/sbt-1.3.10.jar","/home/users/komal.javed/.sbt/boot/scala-2.12.10/lib/scala-library.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/main_2.12/1.3.10/main_2.12-1.3.10.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/io_2.12/1.3.4/io_2.12-1.3.4.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/logic_2.12/1.3.10/logic_2.12-1.3.10.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/actions_2.12/1.3.10/actions_2.12-1.3.10.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/main-settings_2.12/1.3.10/main-settings_2.12-1.3.10.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/run_2.12/1.3.10/run_2.12-1.3.10.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/command_2.12/1.3.10/command_2.12-1.3.10.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/collections_2.12/1.3.10/collections_2.12-1.3.10.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/scripted-sbt-redux_2.12/1.3.10/scripted-sbt-redux_2.12-1.3.10.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/scripted-plugin_2.12/1.3.10/scripted-plugin_2.12-1.3.10.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-lm-integration_2.12/1.3.10/zinc-lm-integration_2.12-1.3.10.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/launcher-interface/1.1.3/launcher-interface-1.1.3.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-api/2.11.2/log4j-api-2.11.2.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-core/2.11.2/log4j-core-2.11.2.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-slf4j-impl/2.11.2/log4j-slf4j-impl-2.11.2.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/cb372/scalacache-caffeine_2.12/0.20.0/scalacache-caffeine_2.12-0.20.0.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/lm-coursier-shaded_2.12/2.0.0-RC6-2/lm-coursier-shaded_2.12-2.0.0-RC6-2.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-logging_2.12/1.3.3/util-logging_2.12-1.3.3.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/librarymanagement-core_2.12/1.3.2/librarymanagement-core_2.12-1.3.2.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/librarymanagement-ivy_2.12/1.3.2/librarymanagement-ivy_2.12-1.3.2.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/compiler-interface/1.3.5/compiler-interface-1.3.5.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-compile_2.12/1.3.5/zinc-compile_2.12-1.3.5.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/swoval/file-tree-views/2.1.3/file-tree-views-2.1.3.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/net/java/dev/jna/jna/5.5.0/jna-5.5.0.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/net/java/dev/jna/jna-platform/5.5.0/jna-platform-5.5.0.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-relation_2.12/1.3.3/util-relation_2.12-1.3.3.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/completion_2.12/1.3.10/completion_2.12-1.3.10.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/task-system_2.12/1.3.10/task-system_2.12-1.3.10.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/tasks_2.12/1.3.10/tasks_2.12-1.3.10.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/testing_2.12/1.3.10/testing_2.12-1.3.10.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/sjson-new-scalajson_2.12/0.8.3/sjson-new-scalajson_2.12-0.8.3.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-tracking_2.12/1.3.3/util-tracking_2.12-1.3.3.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-classpath_2.12/1.3.5/zinc-classpath_2.12-1.3.5.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-apiinfo_2.12/1.3.5/zinc-apiinfo_2.12-1.3.5.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc_2.12/1.3.5/zinc_2.12-1.3.5.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/core-macros_2.12/1.3.10/core-macros_2.12-1.3.10.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-cache_2.12/1.3.3/util-cache_2.12-1.3.3.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-control_2.12/1.3.3/util-control_2.12-1.3.3.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/protocol_2.12/1.3.10/protocol_2.12-1.3.10.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/sjson-new-core_2.12/0.8.3/sjson-new-core_2.12-0.8.3.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/template-resolver/0.1/template-resolver-0.1.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-position_2.12/1.3.3/util-position_2.12-1.3.3.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-scripted_2.12/1.3.3/util-scripted_2.12-1.3.3.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-compile-core_2.12/1.3.5/zinc-compile-core_2.12-1.3.5.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/slf4j/slf4j-api/1.7.26/slf4j-api-1.7.26.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/cb372/scalacache-core_2.12/0.20.0/scalacache-core_2.12-0.20.0.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/ben-manes/caffeine/caffeine/2.5.6/caffeine-2.5.6.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-interface/1.3.3/util-interface-1.3.3.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/jline/jline/2.14.6/jline-2.14.6.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lmax/disruptor/3.4.2/disruptor-3.4.2.jar","/home/users/komal.javed/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar","/home/users/komal.javed/.sbt/boot/scala-2.12.10/lib/scala-compiler.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/jcraft/jsch/0.1.54/jsch-0.1.54.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/gigahorse-okhttp_2.12/0.5.0/gigahorse-okhttp_2.12-0.5.0.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/squareup/okhttp3/okhttp-urlconnection/3.7.0/okhttp-urlconnection-3.7.0.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/ivy/ivy/2.3.0-sbt-fa726854dd30be842ff9e6d2093df6adfe3871f5/ivy-2.3.0-sbt-fa726854dd30be842ff9e6d2093df6adfe3871f5.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.7.0/protobuf-java-3.7.0.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-agent/1.3.10/test-agent-1.3.10.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/shaded-scalajson_2.12/1.0.0-M4/shaded-scalajson_2.12-1.0.0-M4.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/spire-math/jawn-parser_2.12/0.10.4/jawn-parser_2.12-0.10.4.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/compiler-bridge_2.12/1.3.5/compiler-bridge_2.12-1.3.5.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-classfile_2.12/1.3.5/zinc-classfile_2.12-1.3.5.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-core_2.12/1.3.5/zinc-core_2.12-1.3.5.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-persist_2.12/1.3.5/zinc-persist_2.12-1.3.5.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/sjson-new-murmurhash_2.12/0.8.3/sjson-new-murmurhash_2.12-0.8.3.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/ipcsocket/ipcsocket/1.0.1/ipcsocket-1.0.1.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-parser-combinators_2.12/1.1.2/scala-parser-combinators_2.12-1.1.2.jar","/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/gigahorse-core_2.12/0.5.0/gigahorse-core_2.12-0.5.0.jar","/home/users/komal.javed/.cache/coursier/v1/https/rep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\ No newline at end of file diff --git a/design/project/target/streams/compile/_global/_global/discoveredMainClasses/data b/design/project/target/streams/compile/_global/_global/discoveredMainClasses/data deleted file mode 100644 index 0637a088..00000000 --- a/design/project/target/streams/compile/_global/_global/discoveredMainClasses/data +++ /dev/null @@ -1 +0,0 @@ -[] \ No newline at end of file diff --git a/design/project/target/streams/compile/_global/_global/managedSourcePaths/previous b/design/project/target/streams/compile/_global/_global/managedSourcePaths/previous deleted file mode 100644 index a510b125..00000000 --- a/design/project/target/streams/compile/_global/_global/managedSourcePaths/previous +++ /dev/null @@ -1 +0,0 @@ -["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",[]] \ No newline at end of file diff --git a/design/project/target/streams/compile/bspReporter/_global/streams/out b/design/project/target/streams/compile/bspReporter/_global/streams/out deleted file mode 100644 index e69de29b..00000000 diff --git a/design/project/target/streams/compile/compile/_global/streams/out b/design/project/target/streams/compile/compile/_global/streams/out deleted file mode 100644 index e69de29b..00000000 diff --git a/design/project/target/streams/compile/compileIncremental/_global/streams/export b/design/project/target/streams/compile/compileIncremental/_global/streams/export deleted file mode 100644 index e69de29b..00000000 diff --git a/design/project/target/streams/compile/compileIncremental/_global/streams/out b/design/project/target/streams/compile/compileIncremental/_global/streams/out deleted file mode 100644 index 6db8e09d..00000000 --- a/design/project/target/streams/compile/compileIncremental/_global/streams/out +++ /dev/null @@ -1 +0,0 @@ -[debug] Full compilation, no sources in previous analysis. diff --git a/design/project/target/streams/compile/copyResources/_global/streams/copy-resources b/design/project/target/streams/compile/copyResources/_global/streams/copy-resources deleted file mode 100644 index 9d348e7b..00000000 --- a/design/project/target/streams/compile/copyResources/_global/streams/copy-resources +++ /dev/null @@ -1 +0,0 @@ -[[{},{}],{}] \ No newline at end of file diff --git a/design/project/target/streams/compile/copyResources/_global/streams/out b/design/project/target/streams/compile/copyResources/_global/streams/out deleted file mode 100644 index f25042f2..00000000 --- a/design/project/target/streams/compile/copyResources/_global/streams/out +++ /dev/null @@ -1,2 +0,0 @@ -[debug] Copy resource mappings:  -[debug]   diff --git a/design/project/target/streams/compile/dependencyClasspath/_global/streams/export b/design/project/target/streams/compile/dependencyClasspath/_global/streams/export deleted file mode 100644 index 1a81b4e2..00000000 --- a/design/project/target/streams/compile/dependencyClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ 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diff --git a/design/project/target/streams/compile/exportedProducts/_global/streams/export b/design/project/target/streams/compile/exportedProducts/_global/streams/export deleted file mode 100644 index bace10da..00000000 --- a/design/project/target/streams/compile/exportedProducts/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ -/home/users/scratch/komal.javed.data/Quasar/quasar2/design/project/target/scala-2.12/sbt-1.0/classes diff --git a/design/project/target/streams/compile/externalDependencyClasspath/_global/streams/export b/design/project/target/streams/compile/externalDependencyClasspath/_global/streams/export deleted file mode 100644 index 1a81b4e2..00000000 --- a/design/project/target/streams/compile/externalDependencyClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ -/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/sbt/1.3.10/sbt-1.3.10.jar:/home/users/komal.javed/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/main_2.12/1.3.10/main_2.12-1.3.10.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/io_2.12/1.3.4/io_2.12-1.3.4.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/logic_2.12/1.3.10/logic_2.12-1.3.10.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/actions_2.12/1.3.10/actions_2.12-1.3.10.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/main-settings_2.12/1.3.10/main-settings_2.12-1.3.10.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/run_2.12/1.3.10/run_2.12-1.3.10.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/command_2.12/1.3.10/command_2.12-1.3.10.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/collections_2.12/1.3.10/collections_2.12-1.3.10.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/scripted-sbt-redux_2.12/1.3.10/scripted-sbt-redux_2.12-1.3.10.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/scripted-plugin_2.12/1.3.10/scripted-plugin_2.12-1.3.10.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-lm-integration_2.12/1.3.10/zinc-lm-integration_2.12-1.3.10.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/launcher-interface/1.1.3/launcher-interface-1.1.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-api/2.11.2/log4j-api-2.11.2.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-core/2.11.2/log4j-core-2.11.2.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-slf4j-impl/2.11.2/log4j-slf4j-impl-2.11.2.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/cb372/scalacache-caffeine_2.12/0.20.0/scalacache-caffeine_2.12-0.20.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/lm-coursier-shaded_2.12/2.0.0-RC6-2/lm-coursier-shaded_2.12-2.0.0-RC6-2.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-logging_2.12/1.3.3/util-logging_2.12-1.3.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/librarymanagement-core_2.12/1.3.2/librarymanagement-core_2.12-1.3.2.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/librarymanagement-ivy_2.12/1.3.2/librarymanagement-ivy_2.12-1.3.2.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/compiler-interface/1.3.5/compiler-interface-1.3.5.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-compile_2.12/1.3.5/zinc-compile_2.12-1.3.5.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/swoval/file-tree-views/2.1.3/file-tree-views-2.1.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/net/java/dev/jna/jna/5.5.0/jna-5.5.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/net/java/dev/jna/jna-platform/5.5.0/jna-platform-5.5.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-relation_2.12/1.3.3/util-relation_2.12-1.3.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/completion_2.12/1.3.10/completion_2.12-1.3.10.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/task-system_2.12/1.3.10/task-system_2.12-1.3.10.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/tasks_2.12/1.3.10/tasks_2.12-1.3.10.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/testing_2.12/1.3.10/testing_2.12-1.3.10.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/sjson-new-scalajson_2.12/0.8.3/sjson-new-scalajson_2.12-0.8.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-tracking_2.12/1.3.3/util-tracking_2.12-1.3.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-classpath_2.12/1.3.5/zinc-classpath_2.12-1.3.5.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-apiinfo_2.12/1.3.5/zinc-apiinfo_2.12-1.3.5.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc_2.12/1.3.5/zinc_2.12-1.3.5.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/core-macros_2.12/1.3.10/core-macros_2.12-1.3.10.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-cache_2.12/1.3.3/util-cache_2.12-1.3.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-control_2.12/1.3.3/util-control_2.12-1.3.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/protocol_2.12/1.3.10/protocol_2.12-1.3.10.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/sjson-new-core_2.12/0.8.3/sjson-new-core_2.12-0.8.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/template-resolver/0.1/template-resolver-0.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-position_2.12/1.3.3/util-position_2.12-1.3.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-scripted_2.12/1.3.3/util-scripted_2.12-1.3.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-compile-core_2.12/1.3.5/zinc-compile-core_2.12-1.3.5.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/slf4j/slf4j-api/1.7.26/slf4j-api-1.7.26.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/cb372/scalacache-core_2.12/0.20.0/scalacache-core_2.12-0.20.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/ben-manes/caffeine/caffeine/2.5.6/caffeine-2.5.6.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-interface/1.3.3/util-interface-1.3.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/jline/jline/2.14.6/jline-2.14.6.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lmax/disruptor/3.4.2/disruptor-3.4.2.jar:/home/users/komal.javed/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/users/komal.javed/.sbt/boot/scala-2.12.10/lib/scala-compiler.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/jcraft/jsch/0.1.54/jsch-0.1.54.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/gigahorse-okhttp_2.12/0.5.0/gigahorse-okhttp_2.12-0.5.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/squareup/okhttp3/okhttp-urlconnection/3.7.0/okhttp-urlconnection-3.7.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/ivy/ivy/2.3.0-sbt-fa726854dd30be842ff9e6d2093df6adfe3871f5/ivy-2.3.0-sbt-fa726854dd30be842ff9e6d2093df6adfe3871f5.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.7.0/protobuf-java-3.7.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-agent/1.3.10/test-agent-1.3.10.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/shaded-scalajson_2.12/1.0.0-M4/shaded-scalajson_2.12-1.0.0-M4.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/spire-math/jawn-parser_2.12/0.10.4/jawn-parser_2.12-0.10.4.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/compiler-bridge_2.12/1.3.5/compiler-bridge_2.12-1.3.5.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-classfile_2.12/1.3.5/zinc-classfile_2.12-1.3.5.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-core_2.12/1.3.5/zinc-core_2.12-1.3.5.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-persist_2.12/1.3.5/zinc-persist_2.12-1.3.5.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/sjson-new-murmurhash_2.12/0.8.3/sjson-new-murmurhash_2.12-0.8.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/ipcsocket/ipcsocket/1.0.1/ipcsocket-1.0.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-parser-combinators_2.12/1.1.2/scala-parser-combinators_2.12-1.1.2.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/gigahorse-core_2.12/0.5.0/gigahorse-core_2.12-0.5.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/squareup/okhttp3/okhttp/3.14.2/okhttp-3.14.2.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/trueaccord/scalapb/scalapb-runtime_2.12/0.6.0/scala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diff --git a/design/project/target/streams/compile/incOptions/_global/streams/out b/design/project/target/streams/compile/incOptions/_global/streams/out deleted file mode 100644 index 98938a69..00000000 --- a/design/project/target/streams/compile/incOptions/_global/streams/out +++ /dev/null @@ -1,2 +0,0 @@ -[debug] Created transactional ClassFileManager with tempDir = /home/abdulhameed.akram/Downloads/ddsadasdasdasd/Quasar/project/target/scala-2.12/sbt-1.0/classes.bak -[debug] Removing the temporary directory used for backing up class files: /home/abdulhameed.akram/Downloads/ddsadasdasdasd/Quasar/project/target/scala-2.12/sbt-1.0/classes.bak diff --git a/design/project/target/streams/compile/internalDependencyClasspath/_global/streams/export b/design/project/target/streams/compile/internalDependencyClasspath/_global/streams/export deleted file mode 100644 index 8b137891..00000000 --- a/design/project/target/streams/compile/internalDependencyClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ - diff --git a/design/project/target/streams/compile/internalDependencyClasspath/_global/streams/out b/design/project/target/streams/compile/internalDependencyClasspath/_global/streams/out deleted file mode 100644 index e69de29b..00000000 diff --git a/design/project/target/streams/compile/managedClasspath/_global/streams/export b/design/project/target/streams/compile/managedClasspath/_global/streams/export deleted file mode 100644 index 1a81b4e2..00000000 --- a/design/project/target/streams/compile/managedClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ -/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/sbt/1.3.10/sbt-1.3.10.jar:/home/users/komal.javed/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/main_2.12/1.3.10/main_2.12-1.3.10.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/io_2.12/1.3.4/io_2.12-1.3.4.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/logic_2.12/1.3.10/logic_2.12-1.3.10.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/actions_2.12/1.3.10/actions_2.12-1.3.10.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/main-settings_2.12/1.3.10/main-settings_2.12-1.3.10.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/run_2.12/1.3.10/run_2.12-1.3.10.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/command_2.12/1.3.10/command_2.12-1.3.10.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/collections_2.12/1.3.10/collections_2.12-1.3.10.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/scripted-sbt-redux_2.12/1.3.10/scripted-sbt-redux_2.12-1.3.10.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/scripted-plugin_2.12/1.3.10/scripted-plugin_2.12-1.3.10.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-lm-integration_2.12/1.3.10/zinc-lm-integration_2.12-1.3.10.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/launcher-interface/1.1.3/launcher-interface-1.1.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-api/2.11.2/log4j-api-2.11.2.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-core/2.11.2/log4j-core-2.11.2.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-slf4j-impl/2.11.2/log4j-slf4j-impl-2.11.2.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/cb372/scalacache-caffeine_2.12/0.20.0/scalacache-caffeine_2.12-0.20.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/lm-coursier-shaded_2.12/2.0.0-RC6-2/lm-coursier-shaded_2.12-2.0.0-RC6-2.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-logging_2.12/1.3.3/util-logging_2.12-1.3.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/librarymanagement-core_2.12/1.3.2/librarymanagement-core_2.12-1.3.2.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/librarymanagement-ivy_2.12/1.3.2/librarymanagement-ivy_2.12-1.3.2.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/compiler-interface/1.3.5/compiler-interface-1.3.5.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-compile_2.12/1.3.5/zinc-compile_2.12-1.3.5.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/swoval/file-tree-views/2.1.3/file-tree-views-2.1.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/net/java/dev/jna/jna/5.5.0/jna-5.5.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/net/java/dev/jna/jna-platform/5.5.0/jna-platform-5.5.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-relation_2.12/1.3.3/util-relation_2.12-1.3.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/completion_2.12/1.3.10/completion_2.12-1.3.10.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/task-system_2.12/1.3.10/task-system_2.12-1.3.10.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/tasks_2.12/1.3.10/tasks_2.12-1.3.10.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/testing_2.12/1.3.10/testing_2.12-1.3.10.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/sjson-new-scalajson_2.12/0.8.3/sjson-new-scalajson_2.12-0.8.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-tracking_2.12/1.3.3/util-tracking_2.12-1.3.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-classpath_2.12/1.3.5/zinc-classpath_2.12-1.3.5.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-apiinfo_2.12/1.3.5/zinc-apiinfo_2.12-1.3.5.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc_2.12/1.3.5/zinc_2.12-1.3.5.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/core-macros_2.12/1.3.10/core-macros_2.12-1.3.10.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-cache_2.12/1.3.3/util-cache_2.12-1.3.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-control_2.12/1.3.3/util-control_2.12-1.3.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/protocol_2.12/1.3.10/protocol_2.12-1.3.10.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/sjson-new-core_2.12/0.8.3/sjson-new-core_2.12-0.8.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/template-resolver/0.1/template-resolver-0.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-position_2.12/1.3.3/util-position_2.12-1.3.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-scripted_2.12/1.3.3/util-scripted_2.12-1.3.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-compile-core_2.12/1.3.5/zinc-compile-core_2.12-1.3.5.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/slf4j/slf4j-api/1.7.26/slf4j-api-1.7.26.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/cb372/scalacache-core_2.12/0.20.0/scalacache-core_2.12-0.20.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/ben-manes/caffeine/caffeine/2.5.6/caffeine-2.5.6.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-interface/1.3.3/util-interface-1.3.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/jline/jline/2.14.6/jline-2.14.6.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lmax/disruptor/3.4.2/disruptor-3.4.2.jar:/home/users/komal.javed/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/users/komal.javed/.sbt/boot/scala-2.12.10/lib/scala-compiler.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/jcraft/jsch/0.1.54/jsch-0.1.54.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/gigahorse-okhttp_2.12/0.5.0/gigahorse-okhttp_2.12-0.5.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/squareup/okhttp3/okhttp-urlconnection/3.7.0/okhttp-urlconnection-3.7.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/ivy/ivy/2.3.0-sbt-fa726854dd30be842ff9e6d2093df6adfe3871f5/ivy-2.3.0-sbt-fa726854dd30be842ff9e6d2093df6adfe3871f5.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.7.0/protobuf-java-3.7.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-agent/1.3.10/test-agent-1.3.10.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/shaded-scalajson_2.12/1.0.0-M4/shaded-scalajson_2.12-1.0.0-M4.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/spire-math/jawn-parser_2.12/0.10.4/jawn-parser_2.12-0.10.4.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/compiler-bridge_2.12/1.3.5/compiler-bridge_2.12-1.3.5.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-classfile_2.12/1.3.5/zinc-classfile_2.12-1.3.5.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-core_2.12/1.3.5/zinc-core_2.12-1.3.5.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-persist_2.12/1.3.5/zinc-persist_2.12-1.3.5.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/sjson-new-murmurhash_2.12/0.8.3/sjson-new-murmurhash_2.12-0.8.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/ipcsocket/ipcsocket/1.0.1/ipcsocket-1.0.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-parser-combinators_2.12/1.1.2/scala-parser-combinators_2.12-1.1.2.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/eed3si9n/gigahorse-core_2.12/0.5.0/gigahorse-core_2.12-0.5.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/squareup/okhttp3/okhttp/3.14.2/okhttp-3.14.2.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/trueaccord/scalapb/scalapb-runtime_2.12/0.6.0/scalapb-runtime_2.12-0.6.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/sbinary_2.12/0.5.0/sbinary_2.12-0.5.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/typesafe/ssl-config-core_2.12/0.4.0/ssl-config-core_2.12-0.4.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/reactivestreams/reactive-streams/1.0.2/reactive-streams-1.0.2.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/squareup/okio/okio/1.17.2/okio-1.17.2.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/trueaccord/lenses/lenses_2.12/0.4.12/lenses_2.12-0.4.12.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/fastparse_2.12/0.4.2/fastparse_2.12-0.4.2.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/typesafe/config/1.3.3/config-1.3.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/fastparse-utils_2.12/0.4.2/fastparse-utils_2.12-0.4.2.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/sourcecode_2.12/0.1.3/sourcecode_2.12-0.1.3.jar diff --git a/design/project/target/streams/compile/scalacOptions/_global/streams/out b/design/project/target/streams/compile/scalacOptions/_global/streams/out deleted file mode 100644 index e69de29b..00000000 diff --git a/design/project/target/streams/compile/unmanagedClasspath/_global/streams/export b/design/project/target/streams/compile/unmanagedClasspath/_global/streams/export deleted file mode 100644 index 8b137891..00000000 --- a/design/project/target/streams/compile/unmanagedClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ - diff --git a/design/project/target/streams/compile/unmanagedClasspath/_global/streams/out b/design/project/target/streams/compile/unmanagedClasspath/_global/streams/out deleted file mode 100644 index e69de29b..00000000 diff --git a/design/project/target/streams/compile/unmanagedJars/_global/streams/export b/design/project/target/streams/compile/unmanagedJars/_global/streams/export deleted file mode 100644 index 8b137891..00000000 --- a/design/project/target/streams/compile/unmanagedJars/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ - diff --git a/design/project/target/streams/runtime/dependencyClasspath/_global/streams/export b/design/project/target/streams/runtime/dependencyClasspath/_global/streams/export deleted file mode 100644 index bace10da..00000000 --- a/design/project/target/streams/runtime/dependencyClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ -/home/users/scratch/komal.javed.data/Quasar/quasar2/design/project/target/scala-2.12/sbt-1.0/classes diff --git a/design/project/target/streams/runtime/exportedProducts/_global/streams/export b/design/project/target/streams/runtime/exportedProducts/_global/streams/export deleted file mode 100644 index bace10da..00000000 --- a/design/project/target/streams/runtime/exportedProducts/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ -/home/users/scratch/komal.javed.data/Quasar/quasar2/design/project/target/scala-2.12/sbt-1.0/classes diff --git a/design/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export b/design/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export deleted file mode 100644 index 8b137891..00000000 --- a/design/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ - diff --git a/design/project/target/streams/runtime/fullClasspath/_global/streams/export b/design/project/target/streams/runtime/fullClasspath/_global/streams/export deleted file mode 100644 index bace10da..00000000 --- a/design/project/target/streams/runtime/fullClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ -/home/users/scratch/komal.javed.data/Quasar/quasar2/design/project/target/scala-2.12/sbt-1.0/classes diff --git a/design/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export b/design/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export deleted file mode 100644 index bace10da..00000000 --- a/design/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ -/home/users/scratch/komal.javed.data/Quasar/quasar2/design/project/target/scala-2.12/sbt-1.0/classes diff --git a/design/project/target/streams/runtime/internalDependencyClasspath/_global/streams/out b/design/project/target/streams/runtime/internalDependencyClasspath/_global/streams/out deleted file mode 100644 index e69de29b..00000000 diff --git a/design/project/target/streams/runtime/managedClasspath/_global/streams/export b/design/project/target/streams/runtime/managedClasspath/_global/streams/export deleted file mode 100644 index 8b137891..00000000 --- a/design/project/target/streams/runtime/managedClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ - diff --git a/design/project/target/streams/runtime/unmanagedClasspath/_global/streams/export b/design/project/target/streams/runtime/unmanagedClasspath/_global/streams/export deleted file mode 100644 index 8b137891..00000000 --- a/design/project/target/streams/runtime/unmanagedClasspath/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ - diff --git a/design/project/target/streams/runtime/unmanagedClasspath/_global/streams/out b/design/project/target/streams/runtime/unmanagedClasspath/_global/streams/out deleted file mode 100644 index e69de29b..00000000 diff --git a/design/project/target/streams/runtime/unmanagedJars/_global/streams/export b/design/project/target/streams/runtime/unmanagedJars/_global/streams/export deleted file mode 100644 index 8b137891..00000000 --- a/design/project/target/streams/runtime/unmanagedJars/_global/streams/export +++ /dev/null @@ -1 +0,0 @@ - diff --git a/design/target/.history b/design/target/.history deleted file mode 100644 index f40b8c65..00000000 --- a/design/target/.history +++ /dev/null @@ -1,11 +0,0 @@ -;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure -;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("C:/Users/HP/AppData/Local/Temp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "C:/Users/HP/AppData/Roaming/JetBrains/IdeaIC2020.2/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure -;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/abdulhameedakram/.local/share/JetBrains/IdeaIC2020.2/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure -;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/abdulhameed.akram/.local/share/JetBrains/IdeaIC2020.2/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure -;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/abdulhameed.akram/.local/share/JetBrains/IdeaIC2020.3/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2020.3/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure -;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure -;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/abdulhameed.akram/.local/share/JetBrains/IdeaIC2020.3/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2020.3/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure -;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure -;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/laraibkhan/.local/share/JetBrains/IdeaIC2020.3/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2020.3/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure -;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/abdulhameed.akram/.local/share/JetBrains/IdeaIC2020.3/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2020.3/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure -;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure diff --git a/design/target/scala-2.12/chisel-module-template_2.12-3.3.0-tests.jar b/design/target/scala-2.12/chisel-module-template_2.12-3.3.0-tests.jar deleted file mode 100644 index c2778b3a..00000000 Binary files a/design/target/scala-2.12/chisel-module-template_2.12-3.3.0-tests.jar and /dev/null differ diff --git a/design/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar b/design/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar deleted file mode 100644 index 04c5955a..00000000 Binary files a/design/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar and /dev/null differ diff --git a/design/target/scala-2.12/classes/.vscode/settings.json b/design/target/scala-2.12/classes/.vscode/settings.json deleted file mode 100644 index 32cfc61d..00000000 --- a/design/target/scala-2.12/classes/.vscode/settings.json +++ /dev/null @@ -1,5 +0,0 @@ -{ - "files.watcherExclude": { - "**/target": true - } -} \ No newline at end of file diff --git a/design/target/scala-2.12/classes/DMA$.class b/design/target/scala-2.12/classes/DMA$.class deleted file mode 100644 index cac6a2af..00000000 Binary files a/design/target/scala-2.12/classes/DMA$.class and /dev/null differ diff --git a/design/target/scala-2.12/classes/DMA$delayedInit$body.class b/design/target/scala-2.12/classes/DMA$delayedInit$body.class deleted file mode 100644 index 1e564874..00000000 Binary files a/design/target/scala-2.12/classes/DMA$delayedInit$body.class and /dev/null differ diff --git a/design/target/scala-2.12/classes/DMA.class b/design/target/scala-2.12/classes/DMA.class deleted file mode 100644 index ccc485c7..00000000 Binary files a/design/target/scala-2.12/classes/DMA.class and /dev/null differ diff --git a/design/target/scala-2.12/classes/QUASAR$.class b/design/target/scala-2.12/classes/QUASAR$.class deleted file mode 100644 index c3e7f173..00000000 Binary files a/design/target/scala-2.12/classes/QUASAR$.class and /dev/null differ diff --git a/design/target/scala-2.12/classes/QUASAR$delayedInit$body.class b/design/target/scala-2.12/classes/QUASAR$delayedInit$body.class deleted file mode 100644 index 71b5f11a..00000000 Binary files a/design/target/scala-2.12/classes/QUASAR$delayedInit$body.class and /dev/null differ diff --git a/design/target/scala-2.12/classes/QUASAR.class b/design/target/scala-2.12/classes/QUASAR.class deleted file mode 100644 index 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a/design/target/scala-2.12/classes/dbg/debug$delayedInit$body.class b/design/target/scala-2.12/classes/dbg/debug$delayedInit$body.class deleted file mode 100644 index 4e4e78cc..00000000 Binary files a/design/target/scala-2.12/classes/dbg/debug$delayedInit$body.class and /dev/null differ diff --git a/design/target/scala-2.12/classes/dbg/debug.class b/design/target/scala-2.12/classes/dbg/debug.class deleted file mode 100644 index 9142298f..00000000 Binary files a/design/target/scala-2.12/classes/dbg/debug.class and /dev/null differ diff --git a/design/target/scala-2.12/classes/dbg/sb_state_t$.class b/design/target/scala-2.12/classes/dbg/sb_state_t$.class deleted file mode 100644 index fdc415e7..00000000 Binary files a/design/target/scala-2.12/classes/dbg/sb_state_t$.class and /dev/null differ diff --git a/design/target/scala-2.12/classes/dbg/sb_state_t.class b/design/target/scala-2.12/classes/dbg/sb_state_t.class deleted file mode 100644 index e180e267..00000000 Binary files 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except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -//******************************************************************************** -// $Id$ -// -// Function: AXI lite to Wishbone non pipelined bridge -// Comments: Assumes single accesses to a 32bit register on an 64bit aligned address -// -//******************************************************************************** - -`default_nettype none -module axi2wb - #(parameter AW = 12, - parameter IW = 0) - ( - input wire i_clk, - input wire i_rst, - - // Wishbone master - output reg [AW-1:2] o_wb_adr, - output reg [31:0] o_wb_dat, - output reg [3:0] o_wb_sel, - output reg o_wb_we, - output reg o_wb_cyc, - output reg o_wb_stb, - - input wire [31:0] i_wb_rdt, - input wire i_wb_ack, - input wire i_wb_err, - - // AXI slave - // AXI adress write channel - input wire [AW-1:0] i_awaddr, - input wire [IW-1:0] i_awid, - input wire i_awvalid, - output reg o_awready, - //AXI adress read channel - input wire [AW-1:0] i_araddr, - input wire [IW-1:0] i_arid, - input wire i_arvalid, - output reg o_arready, - //AXI write channel - input wire [63:0] i_wdata, - input wire [7:0] i_wstrb, - input wire i_wvalid, - output reg o_wready, - //AXI response channel - output reg [IW-1:0] o_bid, - output wire [1:0] o_bresp, - output reg o_bvalid, - input wire i_bready, - //AXI read channel - output reg [63:0] o_rdata, - output reg [IW-1:0] o_rid, - output wire [1:0] o_rresp, - output wire o_rlast, - output reg o_rvalid, - input wire i_rready - ); - - assign o_bresp = 2'b00; - assign o_rresp = 2'b00; - assign o_rlast = 1'b1; - - reg hi_32b_w; - reg arbiter; - reg [31:0] wb_rdt_low; - - - parameter STATESIZE = 4; - - parameter [STATESIZE-1:0] - IDLE = 4'd0, - AWACK = 4'd1, - WBWACK= 4'd2, - WBRACK1 = 4'd3, - WBR2 = 4'd4, - WBRACK2 = 4'd5, - BAXI = 4'd6, - RRAXI = 4'd7; - - reg [STATESIZE-1:0] cs; - - // formal helper registers - reg aw_req; - reg w_req; - reg ar_req; - - - initial o_rvalid = 1'b0; - initial o_bvalid = 1'b0; - initial o_wb_stb = 1'b0; - initial o_wb_cyc = 1'b0; - initial o_wb_we = 1'b0; - initial cs = 4'd0; - initial aw_req = 1'b0; - initial w_req = 1'b0; - initial ar_req = 1'b0; - - - always @(posedge i_clk) begin - if (i_rst) begin - o_awready <= 1'b0; - o_wready <= 1'b0; - o_arready <= 1'b0; - o_rvalid <= 1'b0; - o_bvalid <= 1'b0; - o_wb_adr <= {AW-2{1'b0}}; - o_wb_cyc <= 1'b0; - o_wb_stb <= 1'b0; - o_wb_sel <= 4'd0; - o_wb_we <= 1'b0; - arbiter <= 1'b1; - wb_rdt_low <= 32'hDEADBEEF; - cs <= IDLE; - - aw_req <= 1'b0; - w_req <= 1'b0; - ar_req <= 1'b0; - o_bid <= {IW{1'b0}}; - o_rid <= {IW{1'b0}}; - - end - else begin - if (i_awvalid & o_awready) - o_bid <= i_awid; - - if (i_arvalid & o_arready) - o_rid <= i_arid; - - o_awready <= 1'b0; - o_wready <= 1'b0; - o_arready <= 1'b0; - - if (i_awvalid && o_awready) - aw_req <= 1'b1; - else if (i_bready && o_bvalid) - aw_req <= 1'b0; - - if (i_wvalid && o_wready) - w_req <= 1'b1; - else if (i_bready && o_bvalid) - w_req <= 1'b0; - - if (i_arvalid && o_arready) - ar_req <= 1'b1; - else if (i_rready && o_rvalid) - ar_req <= 1'b0; - - case (cs) - IDLE : begin - arbiter <= 1'b1; - if (i_awvalid && arbiter) begin - o_wb_adr[AW-1:3] <= i_awaddr[AW-1:3]; - o_awready <= 1'b1; - arbiter <= 1'b0; - if (i_wvalid) begin - hi_32b_w = (i_wstrb[3:0] == 4'h0) ? 1'b1 : 1'b0; - o_wb_adr[2] <= hi_32b_w; - o_wb_cyc <= 1'b1; - o_wb_stb <= 1'b1; - o_wb_sel <= hi_32b_w ? i_wstrb[7:4] : i_wstrb[3:0]; - o_wb_dat <= hi_32b_w ? i_wdata[63:32] : i_wdata[31:0]; - o_wb_we <= 1'b1; - o_wready <= 1'b1; - cs <= WBWACK; - end - else begin - cs <= AWACK; - end - end - else if (i_arvalid) begin - o_wb_adr[AW-1:2] <= i_araddr[AW-1:2]; - o_wb_sel <= 4'hF; - o_wb_cyc <= 1'b1; - o_wb_stb <= 1'b1; - o_arready <= 1'b1; - cs <= WBRACK1; - end - end - - AWACK : begin - if (i_wvalid) begin - hi_32b_w = (i_wstrb[3:0] == 4'h0) ? 1'b1 : 1'b0; - o_wb_adr[2] <= hi_32b_w; - o_wb_cyc <= 1'b1; - o_wb_stb <= 1'b1; - o_wb_sel <= hi_32b_w ? i_wstrb[7:4] : i_wstrb[3:0]; - o_wb_dat <= hi_32b_w ? i_wdata[63:32] : i_wdata[31:0]; - o_wb_we <= 1'b1; - o_wready <= 1'b1; - cs <= WBWACK; - end - end - - WBWACK : begin - if ( i_wb_err || i_wb_ack ) begin - o_wb_cyc <= 1'b0; - o_wb_stb <= 1'b0; - o_wb_sel <= 4'h0; - o_wb_we <= 1'b0; - o_bvalid <= 1'b1; - cs <= BAXI; - end - end - - WBRACK1 : begin - if ( i_wb_err || i_wb_ack) begin - o_wb_cyc <= 1'b0; - o_wb_stb <= 1'b0; - o_wb_sel <= 4'h0; - wb_rdt_low <= i_wb_rdt; - cs <= WBR2; - end - end - - WBR2 : begin - o_wb_adr[2] <= 1'b1; - o_wb_sel <= 4'hF; - o_wb_cyc <= 1'b1; - o_wb_stb <= 1'b1; - cs <= WBRACK2; - end - - - WBRACK2 : begin - if ( i_wb_err || i_wb_ack) begin - o_wb_cyc <= 1'b0; - o_wb_stb <= 1'b0; - o_wb_sel <= 4'h0; - o_rvalid <= 1'b1; - o_rdata <= {i_wb_rdt, wb_rdt_low}; - cs <= RRAXI; - end - end - - BAXI : begin - o_bvalid <= 1'b1; - if (i_bready) begin - o_bvalid <= 1'b0; - cs <= IDLE; - end - end - - RRAXI : begin - o_rvalid <= 1'b1; - if (i_rready) begin - o_rvalid <= 1'b0; - cs <= IDLE; - end - end - - default : begin - o_awready <= 1'b0; - o_wready <= 1'b0; - o_arready <= 1'b0; - o_rvalid <= 1'b0; - o_bvalid <= 1'b0; - o_wb_adr <= {AW-2{1'b0}}; - o_wb_cyc <= 1'b0; - o_wb_stb <= 1'b0; - o_wb_sel <= 4'd0; - o_wb_we <= 1'b0; - arbiter <= 1'b1; - cs <= IDLE; - end - endcase - end - end - -`ifdef FORMAL - localparam F_LGDEPTH = 4; - - wire [(F_LGDEPTH-1):0] faxi_awr_outstanding, - faxi_wr_outstanding, - faxi_rd_outstanding; - - - faxil_slave - #( - .C_AXI_DATA_WIDTH(64), - .C_AXI_ADDR_WIDTH(AW), - .F_OPT_BRESP (1'b1), - .F_OPT_RRESP (1'b1), - .F_AXI_MAXWAIT (16), - .F_AXI_MAXDELAY (4), - .F_AXI_MAXRSTALL (1), - .F_LGDEPTH(F_LGDEPTH)) - faxil_slave - ( - .i_clk(i_clk), - .i_axi_reset_n(~i_rst), - // - .i_axi_awaddr(i_awaddr), - .i_axi_awcache(4'h0), - .i_axi_awprot(3'd0), - .i_axi_awvalid(i_awvalid), - .i_axi_awready(o_awready), - // - .i_axi_wdata(i_wdata), - .i_axi_wstrb(i_wstrb), - .i_axi_wvalid(i_wvalid), - .i_axi_wready(o_wready), - // - .i_axi_bresp(2'd0), - .i_axi_bvalid(o_bvalid), - .i_axi_bready(i_bready), - // - .i_axi_araddr(i_araddr), - .i_axi_arprot(3'd0), - .i_axi_arcache(4'h0), - .i_axi_arvalid(i_arvalid), - .i_axi_arready(o_arready), - // - .i_axi_rdata(o_rdata), - .i_axi_rresp(2'd0), - .i_axi_rvalid(o_rvalid), - .i_axi_rready(i_rready), - // - .f_axi_rd_outstanding(faxi_rd_outstanding), - .f_axi_wr_outstanding(faxi_wr_outstanding), - .f_axi_awr_outstanding(faxi_awr_outstanding)); - - - always @(*) begin - - assert(faxi_awr_outstanding <= 1); - assert(faxi_wr_outstanding <= 1); - assert(faxi_rd_outstanding <= 1); - - case (cs) - IDLE : begin - assert(!o_wb_we); - assert(!o_wb_stb); - assert(!o_wb_cyc); - assert(!aw_req); - assert(!ar_req); - assert(!w_req); - assert(faxi_awr_outstanding == 0); - assert(faxi_wr_outstanding == 0); - assert(faxi_rd_outstanding == 0); - end - AWACK : begin - assert(!o_wb_we); - assert(!o_wb_stb); - assert(!o_wb_cyc); - assert(faxi_awr_outstanding == (aw_req ? 1:0)); - assert(faxi_wr_outstanding == 0); - assert(faxi_rd_outstanding == 0); - end - WBWACK : begin - assert(faxi_awr_outstanding == (aw_req ? 1:0)); - assert(faxi_wr_outstanding == (w_req ? 1:0)); - assert(faxi_rd_outstanding == 0); - end - WBRACK : begin - assert(faxi_awr_outstanding == 0); - assert(faxi_wr_outstanding == 0); - assert(faxi_rd_outstanding == (ar_req ? 1:0)); - end - BAXI : begin - assert(faxi_rd_outstanding == 0); - end - RRAXI : begin - assert(faxi_awr_outstanding == 0); - assert(faxi_wr_outstanding == 0); - end - - default: - assert(0); - endcase // case (cs) - end - - fwbc_master - #(.AW (AW-2), - .DW (32), - .F_MAX_DELAY (4), - .OPT_BUS_ABORT (0)) - fwbc_master - (.i_clk (i_clk), - .i_reset (i_rst), - .i_wb_addr (o_wb_adr), - .i_wb_data (o_wb_dat), - .i_wb_sel (o_wb_sel), - .i_wb_we (o_wb_we), - .i_wb_cyc (o_wb_cyc), - .i_wb_stb (o_wb_stb), - .i_wb_cti (3'd0), - .i_wb_bte (2'd0), - .i_wb_idata (i_wb_rdt), - .i_wb_ack (i_wb_ack), - .i_wb_err (i_wb_err), - .i_wb_rty (1'b0)); - -`endif -endmodule -`default_nettype wire diff --git a/design/target/scala-2.12/classes/vsrc/beh_lib.sv b/design/target/scala-2.12/classes/vsrc/beh_lib.sv deleted file mode 100644 index 6518769d..00000000 --- a/design/target/scala-2.12/classes/vsrc/beh_lib.sv +++ /dev/null @@ -1,799 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 -// Copyright 2020 Western Digital Corporation or its affiliates. -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -// all flops call the rvdff flop -`define RV_FPGA_OPTIMIZE 1 -`define RV_PHYSICAL 1 - - -module rvdff #( parameter WIDTH=1, SHORT=0 ) - ( - input logic [WIDTH-1:0] din, - input logic clk, - input logic rst_l, - - output logic [WIDTH-1:0] dout - ); - -if (SHORT == 1) begin - assign dout = din; -end -else begin -`ifdef RV_CLOCKGATE - always @(posedge tb_top.clk) begin - #0 $strobe("CG: %0t %m din %x dout %x clk %b width %d",$time,din,dout,clk,WIDTH); - end -`endif - - always_ff @(posedge clk or negedge rst_l) begin - if (rst_l == 0) - dout[WIDTH-1:0] <= 0; - else - dout[WIDTH-1:0] <= din[WIDTH-1:0]; - end - -end -endmodule - -// rvdff with 2:1 input mux to flop din iff sel==1 -module rvdffs #( parameter WIDTH=1, SHORT=0 ) - ( - input logic [WIDTH-1:0] din, - input logic en, - input logic clk, - input logic rst_l, - output logic [WIDTH-1:0] dout - ); - -if (SHORT == 1) begin : genblock - assign dout = din; -end -else begin : genblock - rvdff #(WIDTH) dffs (.din((en) ? din[WIDTH-1:0] : dout[WIDTH-1:0]), .*); -end - -endmodule - -// rvdff with en and clear -module rvdffsc #( parameter WIDTH=1, SHORT=0 ) - ( - input logic [WIDTH-1:0] din, - input logic en, - input logic clear, - input logic clk, - input logic rst_l, - output logic [WIDTH-1:0] dout - ); - - logic [WIDTH-1:0] din_new; -if (SHORT == 1) begin - assign dout = din; -end -else begin - assign din_new = {WIDTH{~clear}} & (en ? din[WIDTH-1:0] : dout[WIDTH-1:0]); - rvdff #(WIDTH) dffsc (.din(din_new[WIDTH-1:0]), .*); -end -endmodule - -// _fpga versions -module rvdff_fpga #( parameter WIDTH=1, SHORT=0 ) - ( - input logic [WIDTH-1:0] din, - input logic clk, - input logic clken, - input logic rawclk, - input logic rst_l, - - output logic [WIDTH-1:0] dout - ); - -if (SHORT == 1) begin - assign dout = din; -end -else begin - `ifdef RV_FPGA_OPTIMIZE - rvdffs #(WIDTH) dffs (.clk(rawclk), .en(clken), .*); -`else - rvdff #(WIDTH) dff (.*); -`endif -end -endmodule - -// rvdff with 2:1 input mux to flop din iff sel==1 -module rvdffs_fpga #( parameter WIDTH=1, SHORT=0 ) - ( - input logic [WIDTH-1:0] din, - input logic en, - input logic clk, - input logic clken, - input logic rawclk, - input logic rst_l, - - output logic [WIDTH-1:0] dout - ); - -if (SHORT == 1) begin : genblock - assign dout = din; -end -else begin : genblock -`ifdef RV_FPGA_OPTIMIZE - rvdffs #(WIDTH) dffs (.clk(rawclk), .en(clken & en), .*); -`else - rvdffs #(WIDTH) dffs (.*); -`endif -end - -endmodule - -// rvdff with en and clear -module rvdffsc_fpga #( parameter WIDTH=1, SHORT=0 ) - ( - input logic [WIDTH-1:0] din, - input logic en, - input logic clear, - input logic clk, - input logic clken, - input logic rawclk, - input logic rst_l, - - output logic [WIDTH-1:0] dout - ); - - logic [WIDTH-1:0] din_new; -if (SHORT == 1) begin - assign dout = din; -end -else begin -`ifdef RV_FPGA_OPTIMIZE - rvdffs #(WIDTH) dffs (.clk(rawclk), .din(din[WIDTH-1:0] & {WIDTH{~clear}}),.en((en | clear) & clken), .*); -`else - rvdffsc #(WIDTH) dffsc (.*); -`endif -end -endmodule - - -module rvdffe #( parameter WIDTH=1, SHORT=0, OVERRIDE=0 ) - ( - input logic [WIDTH-1:0] din, - input logic en, - input logic clk, - input logic rst_l, - input logic scan_mode, - output logic [WIDTH-1:0] dout - ); - - logic l1clk; - -if (SHORT == 1) begin : genblock - if (1) begin : genblock - assign dout = din; - end -end -else begin : genblock - -`ifndef RV_PHYSICAL - if (WIDTH >= 8 || OVERRIDE==1) begin: genblock -`endif - -`ifdef RV_FPGA_OPTIMIZE - rvdffs #(WIDTH) dff ( .* ); -`else - rvclkhdr clkhdr ( .* ); - rvdff #(WIDTH) dff (.*, .clk(l1clk)); -`endif - -`ifndef RV_PHYSICAL - end - else - $error("%m: rvdffe must be WIDTH >= 8"); -`endif -end // else: !if(SHORT == 1) - -endmodule // rvdffe - - -module rvdffpcie #( parameter WIDTH=31 ) - ( - input logic [WIDTH-1:0] din, - input logic clk, - input logic rst_l, - input logic en, - input logic scan_mode, - output logic [WIDTH-1:0] dout - ); - - - -`ifndef RV_PHYSICAL - if (WIDTH == 31) begin: genblock -`endif - -`ifdef RV_FPGA_OPTIMIZE - rvdffs #(WIDTH) dff ( .* ); -`else - - rvdfflie #(.WIDTH(WIDTH), .LEFT(19)) dff (.*); - -`endif - -`ifndef RV_PHYSICAL - end - else - $error("%m: rvdffpcie width must be 31"); -`endif -endmodule - -// format: { LEFT, EXTRA } -// LEFT # of bits will be done with rvdffie, all else EXTRA with rvdffe -module rvdfflie #( parameter WIDTH=16, LEFT=8 ) - ( - input logic [WIDTH-1:0] din, - input logic clk, - input logic rst_l, - input logic en, - input logic scan_mode, - output logic [WIDTH-1:0] dout - ); - - localparam EXTRA = WIDTH-LEFT; - - - - - - - - localparam LMSB = WIDTH-1; - localparam LLSB = LMSB-LEFT+1; - localparam XMSB = LLSB-1; - localparam XLSB = LLSB-EXTRA; - - -`ifndef RV_PHYSICAL - if (WIDTH >= 16 && LEFT >= 8 && EXTRA >= 8) begin: genblock -`endif - -`ifdef RV_FPGA_OPTIMIZE - rvdffs #(WIDTH) dff ( .* ); -`else - - rvdffiee #(LEFT) dff_left (.*, .din(din[LMSB:LLSB]), .dout(dout[LMSB:LLSB])); - - - rvdffe #(EXTRA) dff_extra (.*, .din(din[XMSB:XLSB]), .dout(dout[XMSB:XLSB])); - - - - -`endif - -`ifndef RV_PHYSICAL - end - else - $error("%m: rvdfflie musb be WIDTH >= 16 && LEFT >= 8 && EXTRA >= 8"); -`endif -endmodule - - - - -// special power flop for predict packet -// format: { LEFT, RIGHT==31 } -// LEFT # of bits will be done with rvdffe; RIGHT is enabled by LEFT[LSB] & en -module rvdffppe #( parameter WIDTH=32 ) - ( - input logic [WIDTH-1:0] din, - input logic clk, - input logic rst_l, - input logic en, - input logic scan_mode, - output logic [WIDTH-1:0] dout - ); - - localparam RIGHT = 31; - localparam LEFT = WIDTH - RIGHT; - - localparam LMSB = WIDTH-1; - localparam LLSB = LMSB-LEFT+1; - localparam RMSB = LLSB-1; - localparam RLSB = LLSB-RIGHT; - - -`ifndef RV_PHYSICAL - if (WIDTH>=32 && LEFT>=8 && RIGHT>=8) begin: genblock -`endif - -`ifdef RV_FPGA_OPTIMIZE - rvdffs #(WIDTH) dff ( .* ); -`else - rvdffe #(LEFT) dff_left (.*, .din(din[LMSB:LLSB]), .dout(dout[LMSB:LLSB])); - - rvdffe #(RIGHT) dff_right (.*, .din(din[RMSB:RLSB]), .dout(dout[RMSB:RLSB]), .en(en & din[LLSB])); // qualify with pret - - -`endif - -`ifndef RV_PHYSICAL - end - else - $error("%m: must be WIDTH>=32 && LEFT>=8 && RIGHT>=8"); -`endif -endmodule - - - - -module rvdffie #( parameter WIDTH=1, OVERRIDE=0 ) - ( - input logic [WIDTH-1:0] din, - - input logic clk, - input logic rst_l, - input logic scan_mode, - output logic [WIDTH-1:0] dout - ); - - logic l1clk; - logic en; - - - - - - - - -`ifndef RV_PHYSICAL - if (WIDTH >= 8 || OVERRIDE==1) begin: genblock -`endif - - assign en = |(din ^ dout); - -`ifdef RV_FPGA_OPTIMIZE - rvdffs #(WIDTH) dff ( .* ); -`else - rvclkhdr clkhdr ( .* ); - rvdff #(WIDTH) dff (.*, .clk(l1clk)); -`endif - -`ifndef RV_PHYSICAL - end - else - $error("%m: rvdffie must be WIDTH >= 8"); -`endif - - -endmodule - -// ie flop but it has an .en input -module rvdffiee #( parameter WIDTH=1, OVERRIDE=0 ) - ( - input logic [WIDTH-1:0] din, - - input logic clk, - input logic rst_l, - input logic scan_mode, - input logic en, - output logic [WIDTH-1:0] dout - ); - - logic l1clk; - logic final_en; - -`ifndef RV_PHYSICAL - if (WIDTH >= 8 || OVERRIDE==1) begin: genblock -`endif - - assign final_en = (|(din ^ dout)) & en; - -`ifdef RV_FPGA_OPTIMIZE - rvdffs #(WIDTH) dff ( .*, .en(final_en) ); -`else - rvdffe #(WIDTH) dff (.*, .en(final_en)); -`endif - -`ifndef RV_PHYSICAL - end - else - $error("%m: rvdffie width must be >= 8"); -`endif - -endmodule - - - -module rvsyncss #(parameter WIDTH = 251) - ( - input logic clk, - input logic rst_l, - input logic [WIDTH-1:0] din, - output logic [WIDTH-1:0] dout - ); - - logic [WIDTH-1:0] din_ff1; - - rvdff #(WIDTH) sync_ff1 (.*, .din (din[WIDTH-1:0]), .dout(din_ff1[WIDTH-1:0])); - rvdff #(WIDTH) sync_ff2 (.*, .din (din_ff1[WIDTH-1:0]), .dout(dout[WIDTH-1:0])); - -endmodule // rvsyncss - -module rvsyncss_fpga #(parameter WIDTH = 251) - ( - input logic gw_clk, - input logic rawclk, - input logic clken, - input logic rst_l, - input logic [WIDTH-1:0] din, - output logic [WIDTH-1:0] dout - ); - - logic [WIDTH-1:0] din_ff1; - - rvdff_fpga #(WIDTH) sync_ff1 (.*, .clk(gw_clk), .rawclk(rawclk), .clken(clken), .din (din[WIDTH-1:0]), .dout(din_ff1[WIDTH-1:0])); - rvdff_fpga #(WIDTH) sync_ff2 (.*, .clk(gw_clk), .rawclk(rawclk), .clken(clken), .din (din_ff1[WIDTH-1:0]), .dout(dout[WIDTH-1:0])); - -endmodule // rvsyncss - -module rvlsadder - ( - input logic [31:0] rs1, - input logic [11:0] offset, - - output logic [31:0] dout - ); - - logic cout; - logic sign; - - logic [31:12] rs1_inc; - logic [31:12] rs1_dec; - - assign {cout,dout[11:0]} = {1'b0,rs1[11:0]} + {1'b0,offset[11:0]}; - - assign rs1_inc[31:12] = rs1[31:12] + 1; - - assign rs1_dec[31:12] = rs1[31:12] - 1; - - assign sign = offset[11]; - - assign dout[31:12] = ({20{ sign ^~ cout}} & rs1[31:12]) | - ({20{ ~sign & cout}} & rs1_inc[31:12]) | - ({20{ sign & ~cout}} & rs1_dec[31:12]); - -endmodule // rvlsadder - -// assume we only maintain pc[31:1] in the pipe - -module rvbradder - ( - input [31:1] pc, - input [12:1] offset, - - output [31:1] dout - ); - - logic cout; - logic sign; - - logic [31:13] pc_inc; - logic [31:13] pc_dec; - - assign {cout,dout[12:1]} = {1'b0,pc[12:1]} + {1'b0,offset[12:1]}; - - assign pc_inc[31:13] = pc[31:13] + 1; - - assign pc_dec[31:13] = pc[31:13] - 1; - - assign sign = offset[12]; - - - assign dout[31:13] = ({19{ sign ^~ cout}} & pc[31:13]) | - ({19{ ~sign & cout}} & pc_inc[31:13]) | - ({19{ sign & ~cout}} & pc_dec[31:13]); - - -endmodule // rvbradder - - -// 2s complement circuit -module rvtwoscomp #( parameter WIDTH=32 ) - ( - input logic [WIDTH-1:0] din, - - output logic [WIDTH-1:0] dout - ); - - logic [WIDTH-1:1] dout_temp; // holding for all other bits except for the lsb. LSB is always din - - genvar i; - - for ( i = 1; i < WIDTH; i++ ) begin : flip_after_first_one - assign dout_temp[i] = (|din[i-1:0]) ? ~din[i] : din[i]; - end : flip_after_first_one - - assign dout[WIDTH-1:0] = { dout_temp[WIDTH-1:1], din[0] }; - -endmodule // 2'scomp - -// find first -module rvfindfirst1 #( parameter WIDTH=32, SHIFT=$clog2(WIDTH) ) - ( - input logic [WIDTH-1:0] din, - - output logic [SHIFT-1:0] dout - ); - logic done; - - always_comb begin - dout[SHIFT-1:0] = {SHIFT{1'b0}}; - done = 1'b0; - - for ( int i = WIDTH-1; i > 0; i-- ) begin : find_first_one - done |= din[i]; - dout[SHIFT-1:0] += done ? 1'b0 : 1'b1; - end : find_first_one - end -endmodule // rvfindfirst1 - -module rvfindfirst1hot #( parameter WIDTH=32 ) - ( - input logic [WIDTH-1:0] din, - - output logic [WIDTH-1:0] dout - ); - logic done; - - always_comb begin - dout[WIDTH-1:0] = {WIDTH{1'b0}}; - done = 1'b0; - for ( int i = 0; i < WIDTH; i++ ) begin : find_first_one - dout[i] = ~done & din[i]; - done |= din[i]; - end : find_first_one - end -endmodule // rvfindfirst1hot - -// mask and match function matches bits after finding the first 0 position -// find first starting from LSB. Skip that location and match the rest of the bits -module rvmaskandmatch #( parameter WIDTH=32 ) - ( - input logic [WIDTH-1:0] mask, // this will have the mask in the lower bit positions - input logic [WIDTH-1:0] data, // this is what needs to be matched on the upper bits with the mask's upper bits - input logic masken, // when 1 : do mask. 0 : full match - output logic match - ); - - logic [WIDTH-1:0] matchvec; - logic masken_or_fullmask; - - assign masken_or_fullmask = masken & ~(&mask[WIDTH-1:0]); - - assign matchvec[0] = masken_or_fullmask | (mask[0] == data[0]); - genvar i; - - for ( i = 1; i < WIDTH; i++ ) begin : match_after_first_zero - assign matchvec[i] = (&mask[i-1:0] & masken_or_fullmask) ? 1'b1 : (mask[i] == data[i]); - end : match_after_first_zero - - assign match = &matchvec[WIDTH-1:0]; // all bits either matched or were masked off - -endmodule // rvmaskandmatch - - - - -// Check if the S_ADDR <= addr < E_ADDR -module rvrangecheck #(CCM_SADR = 32'h0, - CCM_SIZE = 128) ( - input logic [31:0] addr, // Address to be checked for range - output logic in_range, // S_ADDR <= start_addr < E_ADDR - output logic in_region -); - - localparam REGION_BITS = 4; - localparam MASK_BITS = 10 + $clog2(CCM_SIZE); - - logic [31:0] start_addr; - logic [3:0] region; - - assign start_addr[31:0] = CCM_SADR; - assign region[REGION_BITS-1:0] = start_addr[31:(32-REGION_BITS)]; - - assign in_region = (addr[31:(32-REGION_BITS)] == region[REGION_BITS-1:0]); - if (CCM_SIZE == 48) - assign in_range = (addr[31:MASK_BITS] == start_addr[31:MASK_BITS]) & ~(&addr[MASK_BITS-1 : MASK_BITS-2]); - else - assign in_range = (addr[31:MASK_BITS] == start_addr[31:MASK_BITS]); - -endmodule // rvrangechecker - -// 16 bit even parity generator -module rveven_paritygen #(WIDTH = 16) ( - input logic [WIDTH-1:0] data_in, // Data - output logic parity_out // generated even parity - ); - - assign parity_out = ^(data_in[WIDTH-1:0]) ; - -endmodule // rveven_paritygen - -module rveven_paritycheck #(WIDTH = 16) ( - input logic [WIDTH-1:0] data_in, // Data - input logic parity_in, - output logic parity_err // Parity error - ); - - assign parity_err = ^(data_in[WIDTH-1:0]) ^ parity_in ; - -endmodule // rveven_paritycheck - -module rvecc_encode ( - input [31:0] din, - output [6:0] ecc_out - ); -logic [5:0] ecc_out_temp; - - assign ecc_out_temp[0] = din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]; - assign ecc_out_temp[1] = din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31]; - assign ecc_out_temp[2] = din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31]; - assign ecc_out_temp[3] = din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]; - assign ecc_out_temp[4] = din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]; - assign ecc_out_temp[5] = din[26]^din[27]^din[28]^din[29]^din[30]^din[31]; - - assign ecc_out[6:0] = {(^din[31:0])^(^ecc_out_temp[5:0]),ecc_out_temp[5:0]}; - -endmodule // rvecc_encode - -module rvecc_decode ( - input en, - input [31:0] din, - input [6:0] ecc_in, - input sed_ded, // only do detection and no correction. Used for the I$ - output [31:0] dout, - output [6:0] ecc_out, - output single_ecc_error, - output double_ecc_error - - ); - - logic [6:0] ecc_check; - logic [38:0] error_mask; - logic [38:0] din_plus_parity, dout_plus_parity; - - // Generate the ecc bits - assign ecc_check[0] = ecc_in[0]^din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]; - assign ecc_check[1] = ecc_in[1]^din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31]; - assign ecc_check[2] = ecc_in[2]^din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31]; - assign ecc_check[3] = ecc_in[3]^din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]; - assign ecc_check[4] = ecc_in[4]^din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]; - assign ecc_check[5] = ecc_in[5]^din[26]^din[27]^din[28]^din[29]^din[30]^din[31]; - - // This is the parity bit - assign ecc_check[6] = ((^din[31:0])^(^ecc_in[6:0])) & ~sed_ded; - - assign single_ecc_error = en & (ecc_check[6:0] != 0) & ecc_check[6]; // this will never be on for sed_ded - assign double_ecc_error = en & (ecc_check[6:0] != 0) & ~ecc_check[6]; // all errors in the sed_ded case will be recorded as DE - - // Generate the mask for error correctiong - for (genvar i=1; i<40; i++) begin - assign error_mask[i-1] = (ecc_check[5:0] == i); - end - - // Generate the corrected data - assign din_plus_parity[38:0] = {ecc_in[6], din[31:26], ecc_in[5], din[25:11], ecc_in[4], din[10:4], ecc_in[3], din[3:1], ecc_in[2], din[0], ecc_in[1:0]}; - - assign dout_plus_parity[38:0] = single_ecc_error ? (error_mask[38:0] ^ din_plus_parity[38:0]) : din_plus_parity[38:0]; - assign dout[31:0] = {dout_plus_parity[37:32], dout_plus_parity[30:16], dout_plus_parity[14:8], dout_plus_parity[6:4], dout_plus_parity[2]}; - assign ecc_out[6:0] = {(dout_plus_parity[38] ^ (ecc_check[6:0] == 7'b1000000)), dout_plus_parity[31], dout_plus_parity[15], dout_plus_parity[7], dout_plus_parity[3], dout_plus_parity[1:0]}; - -endmodule // rvecc_decode - -module rvecc_encode_64 ( - input [63:0] din, - output [6:0] ecc_out - ); - assign ecc_out[0] = din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]^din[32]^din[34]^din[36]^din[38]^din[40]^din[42]^din[44]^din[46]^din[48]^din[50]^din[52]^din[54]^din[56]^din[57]^din[59]^din[61]^din[63]; - - assign ecc_out[1] = din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31]^din[32]^din[35]^din[36]^din[39]^din[40]^din[43]^din[44]^din[47]^din[48]^din[51]^din[52]^din[55]^din[56]^din[58]^din[59]^din[62]^din[63]; - - assign ecc_out[2] = din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31]^din[32]^din[37]^din[38]^din[39]^din[40]^din[45]^din[46]^din[47]^din[48]^din[53]^din[54]^din[55]^din[56]^din[60]^din[61]^din[62]^din[63]; - - assign ecc_out[3] = din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56]; - - assign ecc_out[4] = din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56]; - - assign ecc_out[5] = din[26]^din[27]^din[28]^din[29]^din[30]^din[31]^din[32]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56]; - - assign ecc_out[6] = din[57]^din[58]^din[59]^din[60]^din[61]^din[62]^din[63]; - -endmodule // rvecc_encode_64 - - -module rvecc_decode_64 ( - input en, - input [63:0] din, - input [6:0] ecc_in, - output ecc_error - ); - - logic [6:0] ecc_check; - - // Generate the ecc bits - assign ecc_check[0] = ecc_in[0]^din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]^din[32]^din[34]^din[36]^din[38]^din[40]^din[42]^din[44]^din[46]^din[48]^din[50]^din[52]^din[54]^din[56]^din[57]^din[59]^din[61]^din[63]; - - assign ecc_check[1] = ecc_in[1]^din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31]^din[32]^din[35]^din[36]^din[39]^din[40]^din[43]^din[44]^din[47]^din[48]^din[51]^din[52]^din[55]^din[56]^din[58]^din[59]^din[62]^din[63]; - - assign ecc_check[2] = ecc_in[2]^din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31]^din[32]^din[37]^din[38]^din[39]^din[40]^din[45]^din[46]^din[47]^din[48]^din[53]^din[54]^din[55]^din[56]^din[60]^din[61]^din[62]^din[63]; - - assign ecc_check[3] = ecc_in[3]^din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56]; - - assign ecc_check[4] = ecc_in[4]^din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56]; - - assign ecc_check[5] = ecc_in[5]^din[26]^din[27]^din[28]^din[29]^din[30]^din[31]^din[32]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56]; - - assign ecc_check[6] = ecc_in[6]^din[57]^din[58]^din[59]^din[60]^din[61]^din[62]^din[63]; - - assign ecc_error = en & (ecc_check[6:0] != 0); // all errors in the sed_ded case will be recorded as DE - - endmodule // rvecc_decode_64 - - -module TEC_RV_ICG - ( - input logic SE, EN, CK, - output Q - ); - - logic en_ff; - logic enable; - - assign enable = EN | SE; - -`ifdef VERILATOR - always @(negedge CK) begin - en_ff <= enable; - end -`else - always @(CK, enable) begin - if(!CK) - en_ff = enable; - end -`endif - assign Q = CK & en_ff; - -endmodule - -module rvoclkhdr - ( - input logic en, - input logic clk, - input logic scan_mode, - output logic l1clk - ); - - logic SE; - assign SE = 0; - -`ifdef RV_FPGA_OPTIMIZE - assign l1clk = clk; -`else - TEC_RV_ICG clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk)); -`endif - -endmodule - - - diff --git a/design/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv b/design/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv deleted file mode 100644 index 562f815e..00000000 --- a/design/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 -// Copyright 2018 Western Digital Corporation or it's affiliates. -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -//------------------------------------------------------------------------------------ -// -// Copyright Western Digital, 2019 -// Owner : Alex Grobman -// Description: -// This module Synchronizes the signals between JTAG (TCK) and -// processor (Core_clk) -// -//------------------------------------------------------------------------------------- - -module dmi_jtag_to_core_sync ( -// JTAG signals -input rd_en, // 1 bit Read Enable from JTAG -input wr_en, // 1 bit Write enable from JTAG - -// Processor Signals -input rst_n, // Core reset -input clk, // Core clock - -output reg_en, // 1 bit Write interface bit to Processor -output reg_wr_en // 1 bit Write enable to Processor -); - -wire c_rd_en; -wire c_wr_en; -reg [2:0] rden, wren; - - -// Outputs -assign reg_en = c_wr_en | c_rd_en; -assign reg_wr_en = c_wr_en; - - -// synchronizers -always @ ( posedge clk or negedge rst_n) begin - if(!rst_n) begin - rden <= '0; - wren <= '0; - end - else begin - rden <= {rden[1:0], rd_en}; - wren <= {wren[1:0], wr_en}; - end -end - -assign c_rd_en = rden[1] & ~rden[2]; -assign c_wr_en = wren[1] & ~wren[2]; - - -endmodule diff --git a/design/target/scala-2.12/classes/vsrc/dmi_wrapper.sv b/design/target/scala-2.12/classes/vsrc/dmi_wrapper.sv deleted file mode 100644 index d9fd7410..00000000 --- a/design/target/scala-2.12/classes/vsrc/dmi_wrapper.sv +++ /dev/null @@ -1,90 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 -// Copyright 2018 Western Digital Corporation or it's affiliates. -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -//------------------------------------------------------------------------------------ -// -// Copyright Western Digital, 2018 -// Owner : Anusha Narayanamoorthy -// Description: -// Wrapper module for JTAG_TAP and DMI synchronizer -// -//------------------------------------------------------------------------------------- - -module dmi_wrapper( - - // JTAG signals - input trst_n, // JTAG reset - input tck, // JTAG clock - input tms, // Test mode select - input tdi, // Test Data Input - output tdo, // Test Data Output - output tdoEnable, // Test Data Output enable - - // Processor Signals - input core_rst_n, // Core reset - input core_clk, // Core clock - input [31:1] jtag_id, // JTAG ID - input [31:0] rd_data, // 32 bit Read data from Processor - output [31:0] reg_wr_data, // 32 bit Write data to Processor - output [6:0] reg_wr_addr, // 7 bit reg address to Processor - output reg_en, // 1 bit Read enable to Processor - output reg_wr_en, // 1 bit Write enable to Processor - output dmi_hard_reset -); - - - - - - //Wire Declaration - wire rd_en; - wire wr_en; - wire dmireset; - - - //jtag_tap instantiation - rvjtag_tap i_jtag_tap( - .trst(trst_n), // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset - .tck(tck), // dedicated JTAG TCK pad signal - .tms(tms), // dedicated JTAG TMS pad signal - .tdi(tdi), // dedicated JTAG TDI pad signal - .tdo(tdo), // dedicated JTAG TDO pad signal - .tdoEnable(tdoEnable), // enable for TDO pad - .wr_data(reg_wr_data), // 32 bit Write data - .wr_addr(reg_wr_addr), // 7 bit Write address - .rd_en(rd_en), // 1 bit read enable - .wr_en(wr_en), // 1 bit Write enable - .rd_data(rd_data), // 32 bit Read data - .rd_status(2'b0), - .idle(3'h0), // no need to wait to sample data - .dmi_stat(2'b0), // no need to wait or error possible - .version(4'h1), // debug spec 0.13 compliant - .jtag_id(jtag_id), - .dmi_hard_reset(dmi_hard_reset), - .dmi_reset(dmireset) -); - - - // dmi_jtag_to_core_sync instantiation - dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync( - .wr_en(wr_en), // 1 bit Write enable - .rd_en(rd_en), // 1 bit Read enable - - .rst_n(core_rst_n), - .clk(core_clk), - .reg_en(reg_en), // 1 bit Write interface bit - .reg_wr_en(reg_wr_en) // 1 bit Write enable - ); - -endmodule diff --git a/design/target/scala-2.12/classes/vsrc/dpram64.v b/design/target/scala-2.12/classes/vsrc/dpram64.v deleted file mode 100644 index 56abe104..00000000 --- a/design/target/scala-2.12/classes/vsrc/dpram64.v +++ /dev/null @@ -1,66 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 -// Copyright 2019 Western Digital Corporation or its affiliates. -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -//******************************************************************************** -// $Id$ -// -// Function: Basic RAM model with separate read/write ports and byte-wise write enable -// Comments: -// -//******************************************************************************** - -module dpram64 - #(parameter SIZE=0, - parameter mem_clear = 0, - parameter memfile = "") - (input wire clk, - input wire [7:0] we, - input wire [63:0] din, - input wire [$clog2(SIZE)-1:0] waddr, - input wire [$clog2(SIZE)-1:0] raddr, - output reg [63:0] dout); - - localparam AW = $clog2(SIZE); - - reg [63:0] mem [0:SIZE/8-1] /* verilator public */; - - integer i; - wire [AW-4:0] wadd = waddr[AW-1:3]; - - always @(posedge clk) begin - if (we[0]) mem[wadd][ 7: 0] <= din[ 7: 0]; - if (we[1]) mem[wadd][15: 8] <= din[15: 8]; - if (we[2]) mem[wadd][23:16] <= din[23:16]; - if (we[3]) mem[wadd][31:24] <= din[31:24]; - if (we[4]) mem[wadd][39:32] <= din[39:32]; - if (we[5]) mem[wadd][47:40] <= din[47:40]; - if (we[6]) mem[wadd][55:48] <= din[55:48]; - if (we[7]) mem[wadd][63:56] <= din[63:56]; - dout <= mem[raddr[AW-1:3]]; - end - - generate - initial begin - if (mem_clear) - for (i=0;i> (16*iccm_rd_addr_lo_q[1]))}); - assign iccm_rd_data[63:0] = {iccm_data[63:0]}; - assign iccm_rd_data_ecc[77:0] = {iccm_bank_dout_fn[iccm_rd_addr_hi_q][38:0], iccm_bank_dout_fn[iccm_rd_addr_lo_q[ICCM_BANK_HI:2]][38:0]}; - -endmodule // ifu_iccm_mem diff --git a/design/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv b/design/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv deleted file mode 100644 index 8ddbf42c..00000000 --- a/design/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv +++ /dev/null @@ -1,302 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 -// Copyright 2020 Western Digital Corporation or its affiliates. -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -//******************************************************************************** -// $Id$ -// -// -// Owner: -// Function: DCCM for LSU pipe -// Comments: Single ported memory -// -// -// DC1 -> DC2 -> DC3 -> DC4 (Commit) -// -// //******************************************************************************** - - - -`define LOCAL_DCCM_RAM_TEST_PORTS .TEST1(dccm_ext_in_pkt[i].TEST1), \ - .RME(dccm_ext_in_pkt[i].RME), \ - .RM(dccm_ext_in_pkt[i].RM), \ - .LS(dccm_ext_in_pkt[i].LS), \ - .DS(dccm_ext_in_pkt[i].DS), \ - .SD(dccm_ext_in_pkt[i].SD), \ - .TEST_RNM(dccm_ext_in_pkt[i].TEST_RNM), \ - .BC1(dccm_ext_in_pkt[i].BC1), \ - .BC2(dccm_ext_in_pkt[i].BC2), \ - - - -module lsu_dccm_mem -//`include "parameter.sv" -#( - - parameter DCCM_BYTE_WIDTH, - parameter DCCM_BITS, - parameter DCCM_NUM_BANKS, - parameter DCCM_ENABLE= 'b1, - parameter DCCM_BANK_BITS, - parameter DCCM_SIZE, - parameter DCCM_FDATA_WIDTH, - parameter DCCM_WIDTH_BITS -) - ( - input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK. - input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in. - input logic rst_l, // reset, active low - input logic clk_override, // Override non-functional clock gating - - input logic dccm_wren, // write enable - input logic dccm_rden, // read enable - input logic [DCCM_BITS-1:0] dccm_wr_addr_lo, // write address - input logic [DCCM_BITS-1:0] dccm_wr_addr_hi, // write address - input logic [DCCM_BITS-1:0] dccm_rd_addr_lo, // read address - input logic [DCCM_BITS-1:0] dccm_rd_addr_hi, // read address for the upper bank in case of a misaligned access - input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo, // write data - input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi, // write data - input dccm_ext_in_pkt_t [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt, // the dccm packet from the soc - - output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo, // read data from the lo bank - output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi, // read data from the hi bank - - input logic scan_mode -); - - - //localparam DCCM_WIDTH_BITS = $clog2(DCCM_BYTE_WIDTH); - localparam DCCM_INDEX_BITS = (DCCM_BITS - DCCM_BANK_BITS - DCCM_WIDTH_BITS); - localparam DCCM_INDEX_DEPTH = ((DCCM_SIZE)*1024)/((DCCM_BYTE_WIDTH)*(DCCM_NUM_BANKS)); // Depth of memory bank - - logic [DCCM_NUM_BANKS-1:0] wren_bank; - logic [DCCM_NUM_BANKS-1:0] rden_bank; - logic [DCCM_NUM_BANKS-1:0] [DCCM_BITS-1:(DCCM_BANK_BITS+2)] addr_bank; - logic [DCCM_BITS-1:(DCCM_BANK_BITS+DCCM_WIDTH_BITS)] rd_addr_even, rd_addr_odd; - logic rd_unaligned, wr_unaligned; - logic [DCCM_NUM_BANKS-1:0] [DCCM_FDATA_WIDTH-1:0] dccm_bank_dout; - logic [DCCM_FDATA_WIDTH-1:0] wrdata; - - logic [DCCM_NUM_BANKS-1:0][DCCM_FDATA_WIDTH-1:0] wr_data_bank; - - logic [(DCCM_WIDTH_BITS+DCCM_BANK_BITS-1):DCCM_WIDTH_BITS] dccm_rd_addr_lo_q; - logic [(DCCM_WIDTH_BITS+DCCM_BANK_BITS-1):DCCM_WIDTH_BITS] dccm_rd_addr_hi_q; - - logic [DCCM_NUM_BANKS-1:0] dccm_clken; - - assign rd_unaligned = (dccm_rd_addr_lo[DCCM_WIDTH_BITS+:DCCM_BANK_BITS] != dccm_rd_addr_hi[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]); - assign wr_unaligned = (dccm_wr_addr_lo[DCCM_WIDTH_BITS+:DCCM_BANK_BITS] != dccm_wr_addr_hi[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]); - - // Align the read data - assign dccm_rd_data_lo[DCCM_FDATA_WIDTH-1:0] = dccm_bank_dout[dccm_rd_addr_lo_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]][DCCM_FDATA_WIDTH-1:0]; - assign dccm_rd_data_hi[DCCM_FDATA_WIDTH-1:0] = dccm_bank_dout[dccm_rd_addr_hi_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]][DCCM_FDATA_WIDTH-1:0]; - - - // 8 Banks, 16KB each (2048 x 72) - for (genvar i=0; i [4 bit version or revision] [16 bit part number] [11 bit manufacturer id] [value of 1'b1 in LSB] -*/ -input [31:1] jtag_id, -input [3:0] version -); - -localparam USER_DR_LENGTH = AWIDTH + 34; - - -reg [USER_DR_LENGTH-1:0] sr, nsr, dr; - -/////////////////////////////////////////////////////// -// Tap controller -/////////////////////////////////////////////////////// -logic[3:0] state, nstate; -logic [4:0] ir; -wire jtag_reset; -wire shift_dr; -wire pause_dr; -wire update_dr; -wire capture_dr; -wire shift_ir; -wire pause_ir ; -wire update_ir ; -wire capture_ir; -wire[1:0] dr_en; -wire devid_sel; -wire [5:0] abits; - -assign abits = AWIDTH[5:0]; - - -localparam TEST_LOGIC_RESET_STATE = 0; -localparam RUN_TEST_IDLE_STATE = 1; -localparam SELECT_DR_SCAN_STATE = 2; -localparam CAPTURE_DR_STATE = 3; -localparam SHIFT_DR_STATE = 4; -localparam EXIT1_DR_STATE = 5; -localparam PAUSE_DR_STATE = 6; -localparam EXIT2_DR_STATE = 7; -localparam UPDATE_DR_STATE = 8; -localparam SELECT_IR_SCAN_STATE = 9; -localparam CAPTURE_IR_STATE = 10; -localparam SHIFT_IR_STATE = 11; -localparam EXIT1_IR_STATE = 12; -localparam PAUSE_IR_STATE = 13; -localparam EXIT2_IR_STATE = 14; -localparam UPDATE_IR_STATE = 15; - -always_comb begin - nstate = state; - case(state) - TEST_LOGIC_RESET_STATE: nstate = tms ? TEST_LOGIC_RESET_STATE : RUN_TEST_IDLE_STATE; - RUN_TEST_IDLE_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE; - SELECT_DR_SCAN_STATE: nstate = tms ? SELECT_IR_SCAN_STATE : CAPTURE_DR_STATE; - CAPTURE_DR_STATE: nstate = tms ? EXIT1_DR_STATE : SHIFT_DR_STATE; - SHIFT_DR_STATE: nstate = tms ? EXIT1_DR_STATE : SHIFT_DR_STATE; - EXIT1_DR_STATE: nstate = tms ? UPDATE_DR_STATE : PAUSE_DR_STATE; - PAUSE_DR_STATE: nstate = tms ? EXIT2_DR_STATE : PAUSE_DR_STATE; - EXIT2_DR_STATE: nstate = tms ? UPDATE_DR_STATE : SHIFT_DR_STATE; - UPDATE_DR_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE; - SELECT_IR_SCAN_STATE: nstate = tms ? TEST_LOGIC_RESET_STATE : CAPTURE_IR_STATE; - CAPTURE_IR_STATE: nstate = tms ? EXIT1_IR_STATE : SHIFT_IR_STATE; - SHIFT_IR_STATE: nstate = tms ? EXIT1_IR_STATE : SHIFT_IR_STATE; - EXIT1_IR_STATE: nstate = tms ? UPDATE_IR_STATE : PAUSE_IR_STATE; - PAUSE_IR_STATE: nstate = tms ? EXIT2_IR_STATE : PAUSE_IR_STATE; - EXIT2_IR_STATE: nstate = tms ? UPDATE_IR_STATE : SHIFT_IR_STATE; - UPDATE_IR_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE; - default: nstate = TEST_LOGIC_RESET_STATE; - endcase -end - -always @ (posedge tck or negedge trst) begin - if(!trst) state <= TEST_LOGIC_RESET_STATE; - else state <= nstate; -end - -assign jtag_reset = state == TEST_LOGIC_RESET_STATE; -assign shift_dr = state == SHIFT_DR_STATE; -assign pause_dr = state == PAUSE_DR_STATE; -assign update_dr = state == UPDATE_DR_STATE; -assign capture_dr = state == CAPTURE_DR_STATE; -assign shift_ir = state == SHIFT_IR_STATE; -assign pause_ir = state == PAUSE_IR_STATE; -assign update_ir = state == UPDATE_IR_STATE; -assign capture_ir = state == CAPTURE_IR_STATE; - -assign tdoEnable = shift_dr | shift_ir; - -/////////////////////////////////////////////////////// -// IR register -/////////////////////////////////////////////////////// - -always @ (negedge tck or negedge trst) begin - if (!trst) ir <= 5'b1; - else begin - if (jtag_reset) ir <= 5'b1; - else if (update_ir) ir <= (sr[4:0] == '0) ? 5'h1f :sr[4:0]; - end -end - - -assign devid_sel = ir == 5'b00001; -assign dr_en[0] = ir == 5'b10000; -assign dr_en[1] = ir == 5'b10001; - -/////////////////////////////////////////////////////// -// Shift register -/////////////////////////////////////////////////////// -always @ (posedge tck or negedge trst) begin - if(!trst)begin - sr <= '0; - end - else begin - sr <= nsr; - end -end - -// SR next value -always_comb begin - nsr = sr; - case(1) - shift_dr: begin - case(1) - dr_en[1]: nsr = {tdi, sr[USER_DR_LENGTH-1:1]}; - - dr_en[0], - devid_sel: nsr = {{USER_DR_LENGTH-32{1'b0}},tdi, sr[31:1]}; - default: nsr = {{USER_DR_LENGTH-1{1'b0}},tdi}; // bypass - endcase - end - capture_dr: begin - case(1) - dr_en[0]: nsr = {{USER_DR_LENGTH-15{1'b0}}, idle, dmi_stat, abits, version}; - dr_en[1]: nsr = {{AWIDTH{1'b0}}, rd_data, rd_status}; - devid_sel: nsr = {{USER_DR_LENGTH-32{1'b0}}, jtag_id, 1'b1}; - endcase - end - shift_ir: nsr = {{USER_DR_LENGTH-5{1'b0}},tdi, sr[4:1]}; - capture_ir: nsr = {{USER_DR_LENGTH-1{1'b0}},1'b1}; - endcase -end - -// TDO retiming -always @ (negedge tck ) tdo <= sr[0]; - -// DMI CS register -always @ (posedge tck or negedge trst) begin - if(!trst) begin - dmi_hard_reset <= 1'b0; - dmi_reset <= 1'b0; - end - else if (update_dr & dr_en[0]) begin - dmi_hard_reset <= sr[17]; - dmi_reset <= sr[16]; - end - else begin - dmi_hard_reset <= 1'b0; - dmi_reset <= 1'b0; - end -end - -// DR register -always @ (posedge tck or negedge trst) begin - if(!trst) - dr <= '0; - else begin - if (update_dr & dr_en[1]) - dr <= sr; - else - dr <= {dr[USER_DR_LENGTH-1:2],2'b0}; - end -end - -assign {wr_addr, wr_data, wr_en, rd_en} = dr; - - - - -endmodule diff --git a/design/target/scala-2.12/classes/vsrc/simple_spi_top.v b/design/target/scala-2.12/classes/vsrc/simple_spi_top.v deleted file mode 100644 index 46e9d344..00000000 --- a/design/target/scala-2.12/classes/vsrc/simple_spi_top.v +++ /dev/null @@ -1,335 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// OpenCores MC68HC11E based SPI interface //// -//// //// -//// Author: Richard Herveille //// -//// richard@asics.ws //// -//// www.asics.ws //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2002 Richard Herveille //// -//// richard@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: simple_spi_top.v,v 1.5 2004-02-28 15:59:50 rherveille Exp $ -// -// $Date: 2004-02-28 15:59:50 $ -// $Revision: 1.5 $ -// $Author: rherveille $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// Revision 1.4 2003/08/01 11:41:54 rherveille -// Fixed some timing bugs. -// -// Revision 1.3 2003/01/09 16:47:59 rherveille -// Updated clkcnt size and decoding due to new SPR bit assignments. -// -// Revision 1.2 2003/01/07 13:29:52 rherveille -// Changed SPR bits coding. -// -// Revision 1.1.1.1 2002/12/22 16:07:15 rherveille -// Initial release -// -// - - - -// -// Motorola MC68HC11E based SPI interface -// -// Currently only MASTER mode is supported -// - -module simple_spi #( - parameter SS_WIDTH = 1 -)( - // 8bit WISHBONE bus slave interface - input wire clk_i, // clock - input wire rst_i, // reset (synchronous active high) - input wire cyc_i, // cycle - input wire stb_i, // strobe - input wire [2:0] adr_i, // address - input wire we_i, // write enable - input wire [7:0] dat_i, // data input - output reg [7:0] dat_o, // data output - output reg ack_o, // normal bus termination - output reg inta_o, // interrupt output - - // SPI port - output reg sck_o, // serial clock output - output [SS_WIDTH-1:0] ss_o, // slave select (active low) - output wire mosi_o, // MasterOut SlaveIN - input wire miso_i // MasterIn SlaveOut -); - - // - // Module body - // - reg [7:0] spcr; // Serial Peripheral Control Register ('HC11 naming) - wire [7:0] spsr; // Serial Peripheral Status Register ('HC11 naming) - reg [7:0] sper; // Serial Peripheral Extension Register - reg [7:0] treg; // Transmit Register - reg [SS_WIDTH-1:0] ss_r; // Slave Select Register - - // fifo signals - wire [7:0] rfdout; - reg wfre, rfwe; - wire rfre, rffull, rfempty; - wire [7:0] wfdout; - wire wfwe, wffull, wfempty; - - // misc signals - wire tirq; // transfer interrupt (selected number of transfers done) - wire wfov; // write fifo overrun (writing while fifo full) - reg [1:0] state; // statemachine state - reg [2:0] bcnt; - - // - // Wishbone interface - wire wb_acc = cyc_i & stb_i; // WISHBONE access - wire wb_wr = wb_acc & we_i; // WISHBONE write access - - // dat_i - always @(posedge clk_i) - if (rst_i) - begin - spcr <= 8'h10; // set master bit - sper <= 8'h00; - ss_r <= 0; - end - else if (wb_wr) - begin - if (adr_i == 3'b000) - spcr <= dat_i | 8'h10; // always set master bit - - if (adr_i == 3'b011) - sper <= dat_i; - - if (adr_i == 3'b100) - ss_r <= dat_i[SS_WIDTH-1:0]; - end - - // slave select (active low) - assign ss_o = ~ss_r; - - // write fifo - assign wfwe = wb_acc & (adr_i == 3'b010) & ack_o & we_i; - assign wfov = wfwe & wffull; - - // dat_o - always @(posedge clk_i) - case(adr_i) // synopsys full_case parallel_case - 3'b000: dat_o <= spcr; - 3'b001: dat_o <= spsr; - 3'b010: dat_o <= rfdout; - 3'b011: dat_o <= sper; - 3'b100: dat_o <= {{ (8-SS_WIDTH){1'b0} }, ss_r}; - default: dat_o <= 0; - endcase - - // read fifo - assign rfre = wb_acc & (adr_i == 3'b010) & ack_o & ~we_i; - - // ack_o - always @(posedge clk_i) - if (rst_i) - ack_o <= 1'b0; - else - ack_o <= wb_acc & !ack_o; - - // decode Serial Peripheral Control Register - wire spie = spcr[7]; // Interrupt enable bit - wire spe = spcr[6]; // System Enable bit - wire dwom = spcr[5]; // Port D Wired-OR Mode Bit - wire mstr = spcr[4]; // Master Mode Select Bit - wire cpol = spcr[3]; // Clock Polarity Bit - wire cpha = spcr[2]; // Clock Phase Bit - wire [1:0] spr = spcr[1:0]; // Clock Rate Select Bits - - // decode Serial Peripheral Extension Register - wire [1:0] icnt = sper[7:6]; // interrupt on transfer count - wire [1:0] spre = sper[1:0]; // extended clock rate select - - wire [3:0] espr = {spre, spr}; - - // generate status register - wire wr_spsr = wb_wr & (adr_i == 3'b001); - - reg spif; - always @(posedge clk_i) - if (~spe | rst_i) - spif <= 1'b0; - else - spif <= (tirq | spif) & ~(wr_spsr & dat_i[7]); - - reg wcol; - always @(posedge clk_i) - if (~spe | rst_i) - wcol <= 1'b0; - else - wcol <= (wfov | wcol) & ~(wr_spsr & dat_i[6]); - - assign spsr[7] = spif; - assign spsr[6] = wcol; - assign spsr[5:4] = 2'b00; - assign spsr[3] = wffull; - assign spsr[2] = wfempty; - assign spsr[1] = rffull; - assign spsr[0] = rfempty; - - - // generate IRQ output (inta_o) - always @(posedge clk_i) - inta_o <= spif & spie; - - // - // hookup read/write buffer fifo - fifo4 #(8) - rfifo( - .clk ( clk_i ), - .rst ( ~rst_i ), - .clr ( ~spe ), - .din ( treg ), - .we ( rfwe ), - .dout ( rfdout ), - .re ( rfre ), - .full ( rffull ), - .empty ( rfempty ) - ), - wfifo( - .clk ( clk_i ), - .rst ( ~rst_i ), - .clr ( ~spe ), - .din ( dat_i ), - .we ( wfwe ), - .dout ( wfdout ), - .re ( wfre ), - .full ( wffull ), - .empty ( wfempty ) - ); - - // - // generate clk divider - reg [11:0] clkcnt; - always @(posedge clk_i) - if(spe & (|clkcnt & |state)) - clkcnt <= clkcnt - 11'h1; - else - case (espr) // synopsys full_case parallel_case - 4'b0000: clkcnt <= 12'h0; // 2 -- original M68HC11 coding - 4'b0001: clkcnt <= 12'h1; // 4 -- original M68HC11 coding - 4'b0010: clkcnt <= 12'h3; // 16 -- original M68HC11 coding - 4'b0011: clkcnt <= 12'hf; // 32 -- original M68HC11 coding - 4'b0100: clkcnt <= 12'h1f; // 8 - 4'b0101: clkcnt <= 12'h7; // 64 - 4'b0110: clkcnt <= 12'h3f; // 128 - 4'b0111: clkcnt <= 12'h7f; // 256 - 4'b1000: clkcnt <= 12'hff; // 512 - 4'b1001: clkcnt <= 12'h1ff; // 1024 - 4'b1010: clkcnt <= 12'h3ff; // 2048 - 4'b1011: clkcnt <= 12'h7ff; // 4096 - default : clkcnt <= 12'hfff; - endcase - - // generate clock enable signal - wire ena = ~|clkcnt; - - // transfer statemachine - always @(posedge clk_i) - if (~spe | rst_i) - begin - state <= 2'b00; // idle - bcnt <= 3'h0; - treg <= 8'h00; - wfre <= 1'b0; - rfwe <= 1'b0; - sck_o <= 1'b0; - end - else - begin - wfre <= 1'b0; - rfwe <= 1'b0; - - case (state) //synopsys full_case parallel_case - 2'b00: // idle state - begin - bcnt <= 3'h7; // set transfer counter - treg <= wfdout; // load transfer register - sck_o <= cpol; // set sck - - if (~wfempty) begin - wfre <= 1'b1; - state <= 2'b01; - if (cpha) sck_o <= ~sck_o; - end - end - - 2'b01: // clock-phase2, next data - if (ena) begin - sck_o <= ~sck_o; - state <= 2'b11; - end - - 2'b11: // clock phase1 - if (ena) begin - treg <= {treg[6:0], miso_i}; - bcnt <= bcnt -3'h1; - - if (~|bcnt) begin - state <= 2'b00; - sck_o <= cpol; - rfwe <= 1'b1; - end else begin - state <= 2'b01; - sck_o <= ~sck_o; - end - end - - 2'b10: state <= 2'b00; - endcase - end - - assign mosi_o = treg[7]; - - - // count number of transfers (for interrupt generation) - reg [1:0] tcnt; // transfer count - always @(posedge clk_i) - if (~spe) - tcnt <= icnt; - else if (rfwe) // rfwe gets asserted when all bits have been transfered - if (|tcnt) - tcnt <= tcnt - 2'h1; - else - tcnt <= icnt; - - assign tirq = ~|tcnt & rfwe; - -endmodule - diff --git a/design/target/scala-2.12/classes/vsrc/swervolf_syscon.v b/design/target/scala-2.12/classes/vsrc/swervolf_syscon.v deleted file mode 100644 index 1c905413..00000000 --- a/design/target/scala-2.12/classes/vsrc/swervolf_syscon.v +++ /dev/null @@ -1,254 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 -// Copyright 2019-2020 Western Digital Corporation or its affiliates. -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -//******************************************************************************** -// $Id$ -// -// Function: SweRVolf SoC-level controller -// Comments: -// -//******************************************************************************** - -module swervolf_syscon - #(parameter [31:0] clk_freq_hz = 0) - (input wire i_clk, - input wire i_rst, - - input wire [63:0] i_gpio, - output reg [63:0] o_gpio, - output reg o_timer_irq, - output wire o_sw_irq3, - output wire o_sw_irq4, - input wire i_ram_init_done, - input wire i_ram_init_error, - output reg [31:0] o_nmi_vec, - output wire o_nmi_int, - - input wire [5:0] i_wb_adr, - input wire [31:0] i_wb_dat, - input wire [3:0] i_wb_sel, - input wire i_wb_we, - input wire i_wb_cyc, - input wire i_wb_stb, - output reg [31:0] o_wb_rdt, - output reg o_wb_ack); - - reg [63:0] mtime; - reg [63:0] mtimecmp; - - reg sw_irq3; - reg sw_irq3_edge; - reg sw_irq3_pol; - reg sw_irq3_timer; - reg sw_irq4; - reg sw_irq4_edge; - reg sw_irq4_pol; - reg sw_irq4_timer; - - reg irq_timer_en; - reg [31:0] irq_timer_cnt; - - reg nmi_int; - reg nmi_int_r; - -`ifdef SIMPRINT - reg [1023:0] signature_file; - integer f = 0; - initial begin - if ($value$plusargs("signature=%s", signature_file)) begin - $display("Writing signature to %0s", signature_file); - f = $fopen(signature_file, "w"); - end - end -`endif - -`ifndef VERSION_DIRTY - `define VERSION_DIRTY 1 -`endif -`ifndef VERSION_MAJOR - `define VERSION_MAJOR 255 -`endif -`ifndef VERSION_MINOR - `define VERSION_MINOR 255 -`endif -`ifndef VERSION_REV - `define VERSION_REV 255 -`endif -`ifndef VERSION_SHA - `define VERSION_SHA deadbeef -`endif - - wire [31:0] version; - - assign version[31] = `VERSION_DIRTY; - assign version[30:24] = `VERSION_REV; - assign version[23:16] = `VERSION_MAJOR; - assign version[15: 8] = `VERSION_MINOR; - assign version[ 7: 0] = `VERSION_PATCH; - - assign o_sw_irq4 = sw_irq4^sw_irq4_pol; - assign o_sw_irq3 = sw_irq3^sw_irq3_pol; - - assign o_nmi_int = nmi_int | nmi_int_r; - - wire reg_we = i_wb_cyc & i_wb_stb & i_wb_we & !o_wb_ack; - - //00 = ver - //04 = sha - //08 = simprint - //09 = simexit - //0A = RAM status - //0B = sw_irq - //10 = gpio - //20 = timer/timecmp - //40 = SPI - always @(posedge i_clk) begin - o_wb_ack <= i_wb_cyc & !o_wb_ack; - - if (sw_irq3_edge) - sw_irq3 <= 1'b0; - if (sw_irq4_edge) - sw_irq4 <= 1'b0; - - if (irq_timer_en) - irq_timer_cnt <= irq_timer_cnt - 1; - - nmi_int <= 1'b0; - nmi_int_r <= nmi_int; - - if (irq_timer_cnt == 32'd1) begin - irq_timer_en <= 1'b0; - if (sw_irq3_timer) - sw_irq3 <= 1'b1; - if (sw_irq4_timer) - sw_irq4 <= 1'b1; - if (!(sw_irq3_timer | sw_irq4_timer)) - nmi_int <= 1'b1; - end - - if (reg_we) - case (i_wb_adr[5:2]) - 2: begin //0x08-0x0B -`ifdef SIMPRINT - if (i_wb_sel[0]) begin - if (|f) $fwrite(f, "%c", i_wb_dat[7:0]); - $write("%c", i_wb_dat[7:0]); - end - if (i_wb_sel[1]) begin - $display("\nFinito"); - $finish; - end -`endif - if (i_wb_sel[3]) begin - sw_irq4 <= i_wb_dat[31]; - sw_irq4_edge <= i_wb_dat[30]; - sw_irq4_pol <= i_wb_dat[29]; - sw_irq4_timer <= i_wb_dat[28]; - sw_irq3 <= i_wb_dat[27]; - sw_irq3_edge <= i_wb_dat[26]; - sw_irq3_pol <= i_wb_dat[25]; - sw_irq3_timer <= i_wb_dat[24]; - end - end - 3: begin //0x0C-0x0F - if (i_wb_sel[0]) o_nmi_vec[7:0] <= i_wb_dat[7:0]; - if (i_wb_sel[1]) o_nmi_vec[15:8] <= i_wb_dat[15:8]; - if (i_wb_sel[2]) o_nmi_vec[23:16] <= i_wb_dat[23:16]; - if (i_wb_sel[3]) o_nmi_vec[31:24] <= i_wb_dat[31:24]; - end - 4 : begin //0x10-0x13 - if (i_wb_sel[0]) o_gpio[7:0] <= i_wb_dat[7:0] ; - if (i_wb_sel[1]) o_gpio[15:8] <= i_wb_dat[15:8] ; - if (i_wb_sel[2]) o_gpio[23:16] <= i_wb_dat[23:16]; - if (i_wb_sel[3]) o_gpio[31:24] <= i_wb_dat[31:24]; - end - 5: begin //0x14-0x17 - if (i_wb_sel[0]) o_gpio[39:32] <= i_wb_dat[7:0]; - if (i_wb_sel[1]) o_gpio[47:40] <= i_wb_dat[15:8]; - if (i_wb_sel[2]) o_gpio[55:48] <= i_wb_dat[23:16]; - if (i_wb_sel[3]) o_gpio[63:56] <= i_wb_dat[31:24]; - end - 10 : begin //0x28-0x2B - if (i_wb_sel[0]) mtimecmp[7:0] <= i_wb_dat[7:0]; - if (i_wb_sel[1]) mtimecmp[15:8] <= i_wb_dat[15:8]; - if (i_wb_sel[2]) mtimecmp[23:16] <= i_wb_dat[23:16]; - if (i_wb_sel[3]) mtimecmp[31:24] <= i_wb_dat[31:24]; - end - 11 : begin //0x2C-0x2F - if (i_wb_sel[0]) mtimecmp[39:32] <= i_wb_dat[7:0]; - if (i_wb_sel[1]) mtimecmp[47:40] <= i_wb_dat[15:8]; - if (i_wb_sel[2]) mtimecmp[55:48] <= i_wb_dat[23:16]; - if (i_wb_sel[3]) mtimecmp[63:56] <= i_wb_dat[31:24]; - end - 12 : begin //0x30-3f - if (i_wb_sel[0]) irq_timer_cnt[7:0] <= i_wb_dat[7:0] ; - if (i_wb_sel[1]) irq_timer_cnt[15:8] <= i_wb_dat[15:8] ; - if (i_wb_sel[2]) irq_timer_cnt[23:16] <= i_wb_dat[23:16]; - if (i_wb_sel[3]) irq_timer_cnt[31:24] <= i_wb_dat[31:24]; - end - 13 : begin - if (i_wb_sel[0]) - irq_timer_en <= i_wb_dat[0]; - end - endcase - - case (i_wb_adr[5:2]) - //0x00-0x03 - 0 : o_wb_rdt <= version; - //0x04-0x07 - 1 : o_wb_rdt <= 32'h`VERSION_SHA; - //0x08-0x0C - 2 : begin - //0xB - o_wb_rdt[31:28] <= {sw_irq4, sw_irq4_edge, sw_irq4_pol, sw_irq4_timer}; - o_wb_rdt[27:24] <= {sw_irq3, sw_irq3_edge, sw_irq3_pol, sw_irq3_timer}; - //0xA - o_wb_rdt[23:18] <= 6'd0; - o_wb_rdt[17:16] <= {i_ram_init_error, i_ram_init_done}; - //0x8-0x9 - o_wb_rdt[15:0] <= 16'd0; - end - //0xC-0xF - 3 : o_wb_rdt <= o_nmi_vec; - //0x10-0x13 - 4 : o_wb_rdt <= i_gpio[31:0]; - //0x14-0x17 - 5 : o_wb_rdt <= i_gpio[63:32]; - //0x20-0x23 - 8 : o_wb_rdt <= mtime[31:0]; - //0x24-0x27 - 9 : o_wb_rdt <= mtime[63:32]; - //0x28-0x2B - 10 : o_wb_rdt <= mtimecmp[31:0]; - //0x2C-0x2F - 11 : o_wb_rdt <= mtimecmp[63:32]; - //0x30-0x33 - 12 : o_wb_rdt <= irq_timer_cnt; - //0x34-0x37 - 13 : o_wb_rdt <= {31'd0, irq_timer_en}; - //0x3C - 15 : o_wb_rdt <= clk_freq_hz; - endcase - - mtime <= mtime + 64'd1; - o_timer_irq <= (mtime >= mtimecmp); - - if (i_rst) begin - mtime <= 64'd0; - mtimecmp <= 64'd0; - o_wb_ack <= 1'b0; - end - end -endmodule diff --git a/design/target/scala-2.12/classes/vsrc/uart_defines.v b/design/target/scala-2.12/classes/vsrc/uart_defines.v deleted file mode 100644 index fca7b6a5..00000000 --- a/design/target/scala-2.12/classes/vsrc/uart_defines.v +++ /dev/null @@ -1,233 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// uart_defines.v //// -//// //// -//// //// -//// This file is part of the "UART 16550 compatible" project //// -//// http://www.opencores.org/cores/uart16550/ //// -//// //// -//// Documentation related to this project: //// -//// - http://www.opencores.org/cores/uart16550/ //// -//// //// -//// Projects compatibility: //// -//// - WISHBONE //// -//// RS232 Protocol //// -//// 16550D uart (mostly supported) //// -//// //// -//// Overview (main Features): //// -//// Defines of the Core //// -//// //// -//// Known problems (limits): //// -//// None //// -//// //// -//// To Do: //// -//// Nothing. //// -//// //// -//// Author(s): //// -//// - gorban@opencores.org //// -//// - Jacob Gorban //// -//// - Igor Mohor (igorm@opencores.org) //// -//// //// -//// Created: 2001/05/12 //// -//// Last Updated: 2001/05/17 //// -//// (See log for the revision history) //// -//// //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000, 2001 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// Revision 1.13 2003/06/11 16:37:47 gorban -// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. -// -// Revision 1.12 2002/07/22 23:02:23 gorban -// Bug Fixes: -// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. -// Problem reported by Kenny.Tung. -// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. -// -// Improvements: -// * Made FIFO's as general inferrable memory where possible. -// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). -// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. -// -// * Added optional baudrate output (baud_o). -// This is identical to BAUDOUT* signal on 16550 chip. -// It outputs 16xbit_clock_rate - the divided clock. -// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. -// -// Revision 1.10 2001/12/11 08:55:40 mohor -// Scratch register define added. -// -// Revision 1.9 2001/12/03 21:44:29 gorban -// Updated specification documentation. -// Added full 32-bit data bus interface, now as default. -// Address is 5-bit wide in 32-bit data bus mode. -// Added wb_sel_i input to the core. It's used in the 32-bit mode. -// Added debug interface with two 32-bit read-only registers in 32-bit mode. -// Bits 5 and 6 of LSR are now only cleared on TX FIFO write. -// My small test bench is modified to work with 32-bit mode. -// -// Revision 1.8 2001/11/26 21:38:54 gorban -// Lots of fixes: -// Break condition wasn't handled correctly at all. -// LSR bits could lose their values. -// LSR value after reset was wrong. -// Timing of THRE interrupt signal corrected. -// LSR bit 0 timing corrected. -// -// Revision 1.7 2001/08/24 21:01:12 mohor -// Things connected to parity changed. -// Clock devider changed. -// -// Revision 1.6 2001/08/23 16:05:05 mohor -// Stop bit bug fixed. -// Parity bug fixed. -// WISHBONE read cycle bug fixed, -// OE indicator (Overrun Error) bug fixed. -// PE indicator (Parity Error) bug fixed. -// Register read bug fixed. -// -// Revision 1.5 2001/05/31 20:08:01 gorban -// FIFO changes and other corrections. -// -// Revision 1.4 2001/05/21 19:12:02 gorban -// Corrected some Linter messages. -// -// Revision 1.3 2001/05/17 18:34:18 gorban -// First 'stable' release. Should be sythesizable now. Also added new header. -// -// Revision 1.0 2001-05-17 21:27:11+02 jacob -// Initial revision -// -// - -// Uncomment this if you want your UART to have -// 16xBaudrate output port. -// If defined, the enable signal will be used to drive baudrate_o signal -// It's frequency is 16xbaudrate - -// `define UART_HAS_BAUDRATE_OUTPUT - -// Register addresses -`define UART_REG_RB 3'd0 // receiver buffer -`define UART_REG_TR 3'd0 // transmitter -`define UART_REG_IE 3'd1 // Interrupt enable -`define UART_REG_II 3'd2 // Interrupt identification -`define UART_REG_FC 3'd2 // FIFO control -`define UART_REG_LC 3'd3 // Line Control -`define UART_REG_MC 3'd4 // Modem control -`define UART_REG_LS 3'd5 // Line status -`define UART_REG_MS 3'd6 // Modem status -`define UART_REG_SR 3'd7 // Scratch register -`define UART_REG_DL1 3'd0 // Divisor latch bytes (1-2) -`define UART_REG_DL2 3'd1 - -// Interrupt Enable register bits -`define UART_IE_RDA 0 // Received Data available interrupt -`define UART_IE_THRE 1 // Transmitter Holding Register empty interrupt -`define UART_IE_RLS 2 // Receiver Line Status Interrupt -`define UART_IE_MS 3 // Modem Status Interrupt - -// Interrupt Identification register bits -`define UART_II_IP 0 // Interrupt pending when 0 -`define UART_II_II 3:1 // Interrupt identification - -// Interrupt identification values for bits 3:1 -`define UART_II_RLS 3'b011 // Receiver Line Status -`define UART_II_RDA 3'b010 // Receiver Data available -`define UART_II_TI 3'b110 // Timeout Indication -`define UART_II_THRE 3'b001 // Transmitter Holding Register empty -`define UART_II_MS 3'b000 // Modem Status - -// FIFO Control Register bits -`define UART_FC_TL 1:0 // Trigger level - -// FIFO trigger level values -`define UART_FC_1 2'b00 -`define UART_FC_4 2'b01 -`define UART_FC_8 2'b10 -`define UART_FC_14 2'b11 - -// Line Control register bits -`define UART_LC_BITS 1:0 // bits in character -`define UART_LC_SB 2 // stop bits -`define UART_LC_PE 3 // parity enable -`define UART_LC_EP 4 // even parity -`define UART_LC_SP 5 // stick parity -`define UART_LC_BC 6 // Break control -`define UART_LC_DL 7 // Divisor Latch access bit - -// Modem Control register bits -`define UART_MC_DTR 0 -`define UART_MC_RTS 1 -`define UART_MC_OUT1 2 -`define UART_MC_OUT2 3 -`define UART_MC_LB 4 // Loopback mode - -// Line Status Register bits -`define UART_LS_DR 0 // Data ready -`define UART_LS_OE 1 // Overrun Error -`define UART_LS_PE 2 // Parity Error -`define UART_LS_FE 3 // Framing Error -`define UART_LS_BI 4 // Break interrupt -`define UART_LS_TFE 5 // Transmit FIFO is empty -`define UART_LS_TE 6 // Transmitter Empty indicator -`define UART_LS_EI 7 // Error indicator - -// Modem Status Register bits -`define UART_MS_DCTS 0 // Delta signals -`define UART_MS_DDSR 1 -`define UART_MS_TERI 2 -`define UART_MS_DDCD 3 -`define UART_MS_CCTS 4 // Complement signals -`define UART_MS_CDSR 5 -`define UART_MS_CRI 6 -`define UART_MS_CDCD 7 - -// FIFO parameter defines - -`define UART_FIFO_WIDTH 8 -`define UART_FIFO_DEPTH 16 -`define UART_FIFO_POINTER_W 4 -`define UART_FIFO_COUNTER_W 5 -// receiver fifo has width 11 because it has break, parity and framing error bits -`define UART_FIFO_REC_WIDTH 11 - - -`define VERBOSE_WB 0 // All activity on the WISHBONE is recorded -`define VERBOSE_LINE_STATUS 0 // Details about the lsr (line status register) -`define FAST_TEST 1 // 64/1024 packets are sent - - - - - - - diff --git a/design/target/scala-2.12/classes/vsrc/uart_receiver.v b/design/target/scala-2.12/classes/vsrc/uart_receiver.v deleted file mode 100644 index 44c29367..00000000 --- a/design/target/scala-2.12/classes/vsrc/uart_receiver.v +++ /dev/null @@ -1,475 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// uart_receiver.v //// -//// //// -//// //// -//// This file is part of the "UART 16550 compatible" project //// -//// http://www.opencores.org/cores/uart16550/ //// -//// //// -//// Documentation related to this project: //// -//// - http://www.opencores.org/cores/uart16550/ //// -//// //// -//// Projects compatibility: //// -//// - WISHBONE //// -//// RS232 Protocol //// -//// 16550D uart (mostly supported) //// -//// //// -//// Overview (main Features): //// -//// UART core receiver logic //// -//// //// -//// Known problems (limits): //// -//// None known //// -//// //// -//// To Do: //// -//// Thourough testing. //// -//// //// -//// Author(s): //// -//// - gorban@opencores.org //// -//// - Jacob Gorban //// -//// - Igor Mohor (igorm@opencores.org) //// -//// //// -//// Created: 2001/05/12 //// -//// Last Updated: 2001/05/17 //// -//// (See log for the revision history) //// -//// //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000, 2001 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// Revision 1.29 2002/07/29 21:16:18 gorban -// The uart_defines.v file is included again in sources. -// -// Revision 1.28 2002/07/22 23:02:23 gorban -// Bug Fixes: -// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. -// Problem reported by Kenny.Tung. -// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. -// -// Improvements: -// * Made FIFO's as general inferrable memory where possible. -// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). -// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. -// -// * Added optional baudrate output (baud_o). -// This is identical to BAUDOUT* signal on 16550 chip. -// It outputs 16xbit_clock_rate - the divided clock. -// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. -// -// Revision 1.27 2001/12/30 20:39:13 mohor -// More than one character was stored in case of break. End of the break -// was not detected correctly. -// -// Revision 1.26 2001/12/20 13:28:27 mohor -// Missing declaration of rf_push_q fixed. -// -// Revision 1.25 2001/12/20 13:25:46 mohor -// rx push changed to be only one cycle wide. -// -// Revision 1.24 2001/12/19 08:03:34 mohor -// Warnings cleared. -// -// Revision 1.23 2001/12/19 07:33:54 mohor -// Synplicity was having troubles with the comment. -// -// Revision 1.22 2001/12/17 14:46:48 mohor -// overrun signal was moved to separate block because many sequential lsr -// reads were preventing data from being written to rx fifo. -// underrun signal was not used and was removed from the project. -// -// Revision 1.21 2001/12/13 10:31:16 mohor -// timeout irq must be set regardless of the rda irq (rda irq does not reset the -// timeout counter). -// -// Revision 1.20 2001/12/10 19:52:05 gorban -// Igor fixed break condition bugs -// -// Revision 1.19 2001/12/06 14:51:04 gorban -// Bug in LSR[0] is fixed. -// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers. -// -// Revision 1.18 2001/12/03 21:44:29 gorban -// Updated specification documentation. -// Added full 32-bit data bus interface, now as default. -// Address is 5-bit wide in 32-bit data bus mode. -// Added wb_sel_i input to the core. It's used in the 32-bit mode. -// Added debug interface with two 32-bit read-only registers in 32-bit mode. -// Bits 5 and 6 of LSR are now only cleared on TX FIFO write. -// My small test bench is modified to work with 32-bit mode. -// -// Revision 1.17 2001/11/28 19:36:39 gorban -// Fixed: timeout and break didn't pay attention to current data format when counting time -// -// Revision 1.16 2001/11/27 22:17:09 gorban -// Fixed bug that prevented synthesis in uart_receiver.v -// -// Revision 1.15 2001/11/26 21:38:54 gorban -// Lots of fixes: -// Break condition wasn't handled correctly at all. -// LSR bits could lose their values. -// LSR value after reset was wrong. -// Timing of THRE interrupt signal corrected. -// LSR bit 0 timing corrected. -// -// Revision 1.14 2001/11/10 12:43:21 gorban -// Logic Synthesis bugs fixed. Some other minor changes -// -// Revision 1.13 2001/11/08 14:54:23 mohor -// Comments in Slovene language deleted, few small fixes for better work of -// old tools. IRQs need to be fix. -// -// Revision 1.12 2001/11/07 17:51:52 gorban -// Heavily rewritten interrupt and LSR subsystems. -// Many bugs hopefully squashed. -// -// Revision 1.11 2001/10/31 15:19:22 gorban -// Fixes to break and timeout conditions -// -// Revision 1.10 2001/10/20 09:58:40 gorban -// Small synopsis fixes -// -// Revision 1.9 2001/08/24 21:01:12 mohor -// Things connected to parity changed. -// Clock devider changed. -// -// Revision 1.8 2001/08/23 16:05:05 mohor -// Stop bit bug fixed. -// Parity bug fixed. -// WISHBONE read cycle bug fixed, -// OE indicator (Overrun Error) bug fixed. -// PE indicator (Parity Error) bug fixed. -// Register read bug fixed. -// -// Revision 1.6 2001/06/23 11:21:48 gorban -// DL made 16-bit long. Fixed transmission/reception bugs. -// -// Revision 1.5 2001/06/02 14:28:14 gorban -// Fixed receiver and transmitter. Major bug fixed. -// -// Revision 1.4 2001/05/31 20:08:01 gorban -// FIFO changes and other corrections. -// -// Revision 1.3 2001/05/27 17:37:49 gorban -// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file. -// -// Revision 1.2 2001/05/21 19:12:02 gorban -// Corrected some Linter messages. -// -// Revision 1.1 2001/05/17 18:34:18 gorban -// First 'stable' release. Should be sythesizable now. Also added new header. -// -// Revision 1.0 2001-05-17 21:27:11+02 jacob -// Initial revision -// -// - -`include "uart_defines.v" - -module uart_receiver (clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable, - counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse); - -input clk; -input wb_rst_i; -input [7:0] lcr; -input rf_pop; -input srx_pad_i; -input enable; -input rx_reset; -input lsr_mask; - -output [9:0] counter_t; -output [`UART_FIFO_COUNTER_W-1:0] rf_count; -output [`UART_FIFO_REC_WIDTH-1:0] rf_data_out; -output rf_overrun; -output rf_error_bit; -output [3:0] rstate; -output rf_push_pulse; - -reg [3:0] rstate; -reg [3:0] rcounter16; -reg [2:0] rbit_counter; -reg [7:0] rshift; // receiver shift register -reg rparity; // received parity -reg rparity_error; -reg rframing_error; // framing error flag -reg rparity_xor; -reg [7:0] counter_b; // counts the 0 (low) signals -reg rf_push_q; - -// RX FIFO signals -reg [`UART_FIFO_REC_WIDTH-1:0] rf_data_in; -wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out; -wire rf_push_pulse; -reg rf_push; -wire rf_pop; -wire rf_overrun; -wire [`UART_FIFO_COUNTER_W-1:0] rf_count; -wire rf_error_bit; // an error (parity or framing) is inside the fifo -wire break_error = (counter_b == 0); - -// RX FIFO instance -uart_rfifo #(`UART_FIFO_REC_WIDTH) fifo_rx( - .clk( clk ), - .wb_rst_i( wb_rst_i ), - .data_in( rf_data_in ), - .data_out( rf_data_out ), - .push( rf_push_pulse ), - .pop( rf_pop ), - .overrun( rf_overrun ), - .count( rf_count ), - .error_bit( rf_error_bit ), - .fifo_reset( rx_reset ), - .reset_status(lsr_mask) -); - -wire rcounter16_eq_7 = (rcounter16 == 4'd7); -wire rcounter16_eq_0 = (rcounter16 == 4'd0); - -wire [3:0] rcounter16_minus_1 = rcounter16 - 3'd1; - -parameter sr_idle = 4'd0; -parameter sr_rec_start = 4'd1; -parameter sr_rec_bit = 4'd2; -parameter sr_rec_parity = 4'd3; -parameter sr_rec_stop = 4'd4; -parameter sr_check_parity = 4'd5; -parameter sr_rec_prepare = 4'd6; -parameter sr_end_bit = 4'd7; -parameter sr_ca_lc_parity = 4'd8; -parameter sr_wait1 = 4'd9; -parameter sr_push = 4'd10; - - -always @(posedge clk or posedge wb_rst_i) -begin - if (wb_rst_i) - begin - rstate <= sr_idle; - rcounter16 <= 0; - rbit_counter <= 0; - rparity_xor <= 1'b0; - rframing_error <= 1'b0; - rparity_error <= 1'b0; - rparity <= 1'b0; - rshift <= 0; - rf_push <= 1'b0; - rf_data_in <= 0; - end - else - if (enable) - begin - case (rstate) - sr_idle : begin - rf_push <= 1'b0; - rf_data_in <= 0; - rcounter16 <= 4'b1110; - if (srx_pad_i==1'b0 & ~break_error) // detected a pulse (start bit?) - begin - rstate <= sr_rec_start; - end - end - sr_rec_start : begin - rf_push <= 1'b0; - if (rcounter16_eq_7) // check the pulse - if (srx_pad_i==1'b1) // no start bit - rstate <= sr_idle; - else // start bit detected - rstate <= sr_rec_prepare; - rcounter16 <= rcounter16_minus_1; - end - sr_rec_prepare:begin - case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word - 2'b00 : rbit_counter <= 3'b100; - 2'b01 : rbit_counter <= 3'b101; - 2'b10 : rbit_counter <= 3'b110; - 2'b11 : rbit_counter <= 3'b111; - endcase - if (rcounter16_eq_0) - begin - rstate <= sr_rec_bit; - rcounter16 <= 4'b1110; - rshift <= 0; - end - else - rstate <= sr_rec_prepare; - rcounter16 <= rcounter16_minus_1; - end - sr_rec_bit : begin - if (rcounter16_eq_0) - rstate <= sr_end_bit; - if (rcounter16_eq_7) // read the bit - case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word - 2'b00 : rshift[4:0] <= {srx_pad_i, rshift[4:1]}; - 2'b01 : rshift[5:0] <= {srx_pad_i, rshift[5:1]}; - 2'b10 : rshift[6:0] <= {srx_pad_i, rshift[6:1]}; - 2'b11 : rshift[7:0] <= {srx_pad_i, rshift[7:1]}; - endcase - rcounter16 <= rcounter16_minus_1; - end - sr_end_bit : begin - if (rbit_counter==3'b0) // no more bits in word - if (lcr[`UART_LC_PE]) // choose state based on parity - rstate <= sr_rec_parity; - else - begin - rstate <= sr_rec_stop; - rparity_error <= 1'b0; // no parity - no error :) - end - else // else we have more bits to read - begin - rstate <= sr_rec_bit; - rbit_counter <= rbit_counter - 3'd1; - end - rcounter16 <= 4'b1110; - end - sr_rec_parity: begin - if (rcounter16_eq_7) // read the parity - begin - rparity <= srx_pad_i; - rstate <= sr_ca_lc_parity; - end - rcounter16 <= rcounter16_minus_1; - end - sr_ca_lc_parity : begin // rcounter equals 6 - rcounter16 <= rcounter16_minus_1; - rparity_xor <= ^{rshift,rparity}; // calculate parity on all incoming data - rstate <= sr_check_parity; - end - sr_check_parity: begin // rcounter equals 5 - case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]}) - 2'b00: rparity_error <= rparity_xor == 0; // no error if parity 1 - 2'b01: rparity_error <= ~rparity; // parity should sticked to 1 - 2'b10: rparity_error <= rparity_xor == 1; // error if parity is odd - 2'b11: rparity_error <= rparity; // parity should be sticked to 0 - endcase - rcounter16 <= rcounter16_minus_1; - rstate <= sr_wait1; - end - sr_wait1 : if (rcounter16_eq_0) - begin - rstate <= sr_rec_stop; - rcounter16 <= 4'b1110; - end - else - rcounter16 <= rcounter16_minus_1; - sr_rec_stop : begin - if (rcounter16_eq_7) // read the parity - begin - rframing_error <= !srx_pad_i; // no framing error if input is 1 (stop bit) - rstate <= sr_push; - end - rcounter16 <= rcounter16_minus_1; - end - sr_push : begin -/////////////////////////////////////// -// $display($time, ": received: %b", rf_data_in); - if(srx_pad_i | break_error) - begin - if(break_error) - rf_data_in <= {8'b0, 3'b100}; // break input (empty character) to receiver FIFO - else - rf_data_in <= {rshift, 1'b0, rparity_error, rframing_error}; - rf_push <= 1'b1; - rstate <= sr_idle; - end - else if(~rframing_error) // There's always a framing before break_error -> wait for break or srx_pad_i - begin - rf_data_in <= {rshift, 1'b0, rparity_error, rframing_error}; - rf_push <= 1'b1; - rcounter16 <= 4'b1110; - rstate <= sr_rec_start; - end - - end - default : rstate <= sr_idle; - endcase - end // if (enable) -end // always of receiver - -always @ (posedge clk or posedge wb_rst_i) -begin - if(wb_rst_i) - rf_push_q <= 0; - else - rf_push_q <= rf_push; -end - -assign rf_push_pulse = rf_push & ~rf_push_q; - - -// -// Break condition detection. -// Works in conjuction with the receiver state machine - -reg [9:0] toc_value; // value to be set to timeout counter - -always @(lcr) - case (lcr[3:0]) - 4'b0000 : toc_value = 447; // 7 bits - 4'b0100 : toc_value = 479; // 7.5 bits - 4'b0001, 4'b1000 : toc_value = 511; // 8 bits - 4'b1100 : toc_value = 543; // 8.5 bits - 4'b0010, 4'b0101, 4'b1001 : toc_value = 575; // 9 bits - 4'b0011, 4'b0110, 4'b1010, 4'b1101 : toc_value = 639; // 10 bits - 4'b0111, 4'b1011, 4'b1110 : toc_value = 703; // 11 bits - 4'b1111 : toc_value = 767; // 12 bits - endcase // case(lcr[3:0]) - -wire [7:0] brc_value; // value to be set to break counter -assign brc_value = toc_value[9:2]; // the same as timeout but 1 insead of 4 character times - -always @(posedge clk or posedge wb_rst_i) -begin - if (wb_rst_i) - counter_b <= 8'd159; - else - if (srx_pad_i) - counter_b <= brc_value; // character time length - 1 - else - if(enable & counter_b != 8'b0) // only work on enable times break not reached. - counter_b <= counter_b - 8'd1; // decrement break counter -end // always of break condition detection - -/// -/// Timeout condition detection -reg [9:0] counter_t; // counts the timeout condition clocks - -always @(posedge clk or posedge wb_rst_i) -begin - if (wb_rst_i) - counter_t <= 10'd639; // 10 bits for the default 8N1 - else - if(rf_push_pulse || rf_pop || rf_count == 0) // counter is reset when RX FIFO is empty, accessed or above trigger level - counter_t <= toc_value; - else - if (enable && counter_t != 10'b0) // we don't want to underflow - counter_t <= counter_t - 10'd1; -end - -endmodule diff --git a/design/target/scala-2.12/classes/vsrc/uart_regs.v b/design/target/scala-2.12/classes/vsrc/uart_regs.v deleted file mode 100644 index 931632c4..00000000 --- a/design/target/scala-2.12/classes/vsrc/uart_regs.v +++ /dev/null @@ -1,888 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// uart_regs.v //// -//// //// -//// //// -//// This file is part of the "UART 16550 compatible" project //// -//// http://www.opencores.org/cores/uart16550/ //// -//// //// -//// Documentation related to this project: //// -//// - http://www.opencores.org/cores/uart16550/ //// -//// //// -//// Projects compatibility: //// -//// - WISHBONE //// -//// RS232 Protocol //// -//// 16550D uart (mostly supported) //// -//// //// -//// Overview (main Features): //// -//// Registers of the uart 16550 core //// -//// //// -//// Known problems (limits): //// -//// Inserts 1 wait state in all WISHBONE transfers //// -//// //// -//// To Do: //// -//// Nothing or verification. //// -//// //// -//// Author(s): //// -//// - gorban@opencores.org //// -//// - Jacob Gorban //// -//// - Igor Mohor (igorm@opencores.org) //// -//// //// -//// Created: 2001/05/12 //// -//// Last Updated: (See log for the revision history //// -//// //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000, 2001 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// Revision 1.41 2004/05/21 11:44:41 tadejm -// Added synchronizer flops for RX input. -// -// Revision 1.40 2003/06/11 16:37:47 gorban -// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. -// -// Revision 1.39 2002/07/29 21:16:18 gorban -// The uart_defines.v file is included again in sources. -// -// Revision 1.38 2002/07/22 23:02:23 gorban -// Bug Fixes: -// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. -// Problem reported by Kenny.Tung. -// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. -// -// Improvements: -// * Made FIFO's as general inferrable memory where possible. -// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). -// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. -// -// * Added optional baudrate output (baud_o). -// This is identical to BAUDOUT* signal on 16550 chip. -// It outputs 16xbit_clock_rate - the divided clock. -// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. -// -// Revision 1.37 2001/12/27 13:24:09 mohor -// lsr[7] was not showing overrun errors. -// -// Revision 1.36 2001/12/20 13:25:46 mohor -// rx push changed to be only one cycle wide. -// -// Revision 1.35 2001/12/19 08:03:34 mohor -// Warnings cleared. -// -// Revision 1.34 2001/12/19 07:33:54 mohor -// Synplicity was having troubles with the comment. -// -// Revision 1.33 2001/12/17 10:14:43 mohor -// Things related to msr register changed. After THRE IRQ occurs, and one -// character is written to the transmit fifo, the detection of the THRE bit in the -// LSR is delayed for one character time. -// -// Revision 1.32 2001/12/14 13:19:24 mohor -// MSR register fixed. -// -// Revision 1.31 2001/12/14 10:06:58 mohor -// After reset modem status register MSR should be reset. -// -// Revision 1.30 2001/12/13 10:09:13 mohor -// thre irq should be cleared only when being source of interrupt. -// -// Revision 1.29 2001/12/12 09:05:46 mohor -// LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo). -// -// Revision 1.28 2001/12/10 19:52:41 gorban -// Scratch register added -// -// Revision 1.27 2001/12/06 14:51:04 gorban -// Bug in LSR[0] is fixed. -// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers. -// -// Revision 1.26 2001/12/03 21:44:29 gorban -// Updated specification documentation. -// Added full 32-bit data bus interface, now as default. -// Address is 5-bit wide in 32-bit data bus mode. -// Added wb_sel_i input to the core. It's used in the 32-bit mode. -// Added debug interface with two 32-bit read-only registers in 32-bit mode. -// Bits 5 and 6 of LSR are now only cleared on TX FIFO write. -// My small test bench is modified to work with 32-bit mode. -// -// Revision 1.25 2001/11/28 19:36:39 gorban -// Fixed: timeout and break didn't pay attention to current data format when counting time -// -// Revision 1.24 2001/11/26 21:38:54 gorban -// Lots of fixes: -// Break condition wasn't handled correctly at all. -// LSR bits could lose their values. -// LSR value after reset was wrong. -// Timing of THRE interrupt signal corrected. -// LSR bit 0 timing corrected. -// -// Revision 1.23 2001/11/12 21:57:29 gorban -// fixed more typo bugs -// -// Revision 1.22 2001/11/12 15:02:28 mohor -// lsr1r error fixed. -// -// Revision 1.21 2001/11/12 14:57:27 mohor -// ti_int_pnd error fixed. -// -// Revision 1.20 2001/11/12 14:50:27 mohor -// ti_int_d error fixed. -// -// Revision 1.19 2001/11/10 12:43:21 gorban -// Logic Synthesis bugs fixed. Some other minor changes -// -// Revision 1.18 2001/11/08 14:54:23 mohor -// Comments in Slovene language deleted, few small fixes for better work of -// old tools. IRQs need to be fix. -// -// Revision 1.17 2001/11/07 17:51:52 gorban -// Heavily rewritten interrupt and LSR subsystems. -// Many bugs hopefully squashed. -// -// Revision 1.16 2001/11/02 09:55:16 mohor -// no message -// -// Revision 1.15 2001/10/31 15:19:22 gorban -// Fixes to break and timeout conditions -// -// Revision 1.14 2001/10/29 17:00:46 gorban -// fixed parity sending and tx_fifo resets over- and underrun -// -// Revision 1.13 2001/10/20 09:58:40 gorban -// Small synopsis fixes -// -// Revision 1.12 2001/10/19 16:21:40 gorban -// Changes data_out to be synchronous again as it should have been. -// -// Revision 1.11 2001/10/18 20:35:45 gorban -// small fix -// -// Revision 1.10 2001/08/24 21:01:12 mohor -// Things connected to parity changed. -// Clock devider changed. -// -// Revision 1.9 2001/08/23 16:05:05 mohor -// Stop bit bug fixed. -// Parity bug fixed. -// WISHBONE read cycle bug fixed, -// OE indicator (Overrun Error) bug fixed. -// PE indicator (Parity Error) bug fixed. -// Register read bug fixed. -// -// Revision 1.10 2001/06/23 11:21:48 gorban -// DL made 16-bit long. Fixed transmission/reception bugs. -// -// Revision 1.9 2001/05/31 20:08:01 gorban -// FIFO changes and other corrections. -// -// Revision 1.8 2001/05/29 20:05:04 gorban -// Fixed some bugs and synthesis problems. -// -// Revision 1.7 2001/05/27 17:37:49 gorban -// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file. -// -// Revision 1.6 2001/05/21 19:12:02 gorban -// Corrected some Linter messages. -// -// Revision 1.5 2001/05/17 18:34:18 gorban -// First 'stable' release. Should be sythesizable now. Also added new header. -// -// Revision 1.0 2001-05-17 21:27:11+02 jacob -// Initial revision -// -// - -`include "uart_defines.v" - -`define UART_DL1 7:0 -`define UART_DL2 15:8 - -module uart_regs -#(parameter SIM = 0) - (clk, - wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_re_i, - -// additional signals - modem_inputs, - stx_pad_o, srx_pad_i, - - rts_pad_o, dtr_pad_o, int_o -`ifdef UART_HAS_BAUDRATE_OUTPUT - , baud_o -`endif - - ); - -input clk; -input wb_rst_i; -input [2:0] wb_addr_i; -input [7:0] wb_dat_i; -output [7:0] wb_dat_o; -input wb_we_i; -input wb_re_i; - -output stx_pad_o; -input srx_pad_i; - -input [3:0] modem_inputs; -output rts_pad_o; -output dtr_pad_o; -output int_o; -`ifdef UART_HAS_BAUDRATE_OUTPUT -output baud_o; -`endif - -wire [3:0] modem_inputs; -reg enable; -`ifdef UART_HAS_BAUDRATE_OUTPUT -assign baud_o = enable; // baud_o is actually the enable signal -`endif - - -wire stx_pad_o; // received from transmitter module -wire srx_pad_i; -wire srx_pad; - -reg [7:0] wb_dat_o; - -wire [2:0] wb_addr_i; -wire [7:0] wb_dat_i; - - -reg [3:0] ier; -reg [3:0] iir; -reg [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored -reg [4:0] mcr; -reg [7:0] lcr; -reg [7:0] msr; -reg [15:0] dl; // 32-bit divisor latch -reg [7:0] scratch; // UART scratch register -reg start_dlc; // activate dlc on writing to UART_DL1 -reg lsr_mask_d; // delay for lsr_mask condition -reg msi_reset; // reset MSR 4 lower bits indicator -//reg threi_clear; // THRE interrupt clear flag -reg [15:0] dlc; // 32-bit divisor latch counter -reg int_o; - -reg [3:0] trigger_level; // trigger level of the receiver FIFO -reg rx_reset; -reg tx_reset; - -wire dlab; // divisor latch access bit -wire cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i; // modem status bits -wire loopback; // loopback bit (MCR bit 4) -wire cts, dsr, ri, dcd; // effective signals -wire cts_c, dsr_c, ri_c, dcd_c; // Complement effective signals (considering loopback) -wire rts_pad_o, dtr_pad_o; // modem control outputs - -// LSR bits wires and regs -wire [7:0] lsr; -wire lsr0, lsr1, lsr2, lsr3, lsr4, lsr5, lsr6, lsr7; -reg lsr0r, lsr1r, lsr2r, lsr3r, lsr4r, lsr5r, lsr6r, lsr7r; -wire lsr_mask; // lsr_mask - -// -// ASSINGS -// - -assign lsr[7:0] = { lsr7r, lsr6r, lsr5r, lsr4r, lsr3r, lsr2r, lsr1r, lsr0r }; - -assign {cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i} = modem_inputs; -assign {cts, dsr, ri, dcd} = ~{cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i}; - -assign {cts_c, dsr_c, ri_c, dcd_c} = loopback ? {mcr[`UART_MC_RTS],mcr[`UART_MC_DTR],mcr[`UART_MC_OUT1],mcr[`UART_MC_OUT2]} - : {cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i}; - -assign dlab = lcr[`UART_LC_DL]; -assign loopback = mcr[4]; - -// assign modem outputs -assign rts_pad_o = mcr[`UART_MC_RTS]; -assign dtr_pad_o = mcr[`UART_MC_DTR]; - -// Interrupt signals -wire rls_int; // receiver line status interrupt -wire rda_int; // receiver data available interrupt -wire ti_int; // timeout indicator interrupt -wire thre_int; // transmitter holding register empty interrupt -wire ms_int; // modem status interrupt - -// FIFO signals -reg tf_push; -reg rf_pop; -wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out; -wire rf_error_bit; // an error (parity or framing) is inside the fifo -wire rf_overrun; -wire rf_push_pulse; -wire [`UART_FIFO_COUNTER_W-1:0] rf_count; -wire [`UART_FIFO_COUNTER_W-1:0] tf_count; -wire [2:0] tstate; -wire [3:0] rstate; -wire [9:0] counter_t; - -wire thre_set_en; // THRE status is delayed one character time when a character is written to fifo. -reg [7:0] block_cnt; // While counter counts, THRE status is blocked (delayed one character cycle) -reg [7:0] block_value; // One character length minus stop bit - -// Transmitter Instance -wire serial_out; - -uart_transmitter #(.SIM (SIM)) transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, serial_out, tstate, tf_count, tx_reset, lsr_mask); - - // Synchronizing and sampling serial RX input - uart_sync_flops i_uart_sync_flops - ( - .rst_i (wb_rst_i), - .clk_i (clk), - .stage1_rst_i (1'b0), - .stage1_clk_en_i (1'b1), - .async_dat_i (srx_pad_i), - .sync_dat_o (srx_pad) - ); - defparam i_uart_sync_flops.width = 1; - defparam i_uart_sync_flops.init_value = 1'b1; - -// handle loopback -wire serial_in = loopback ? serial_out : srx_pad; -assign stx_pad_o = loopback ? 1'b1 : serial_out; - -// Receiver Instance -uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, serial_in, enable, - counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse); - - -// Asynchronous reading here because the outputs are sampled in uart_wb.v file -always @(dl or dlab or ier or iir or scratch - or lcr or lsr or msr or rf_data_out or wb_addr_i or wb_re_i) // asynchrounous reading -begin - case (wb_addr_i) - `UART_REG_RB : wb_dat_o = dlab ? dl[`UART_DL1] : rf_data_out[10:3]; - `UART_REG_IE : wb_dat_o = dlab ? dl[`UART_DL2] : {4'd0,ier}; - `UART_REG_II : wb_dat_o = {4'b1100,iir}; - `UART_REG_LC : wb_dat_o = lcr; - `UART_REG_LS : wb_dat_o = lsr; - `UART_REG_MS : wb_dat_o = msr; - `UART_REG_SR : wb_dat_o = scratch; - default: wb_dat_o = 8'b0; // ?? - endcase // case(wb_addr_i) -end // always @ (dl or dlab or ier or iir or scratch... - - -// rf_pop signal handling -always @(posedge clk or posedge wb_rst_i) -begin - if (wb_rst_i) - rf_pop <= 0; - else - if (rf_pop) // restore the signal to 0 after one clock cycle - rf_pop <= 0; - else - if (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab) - rf_pop <= 1; // advance read pointer -end - -wire lsr_mask_condition; -wire iir_read; -wire msr_read; -wire fifo_read; -wire fifo_write; - -assign lsr_mask_condition = (wb_re_i && wb_addr_i == `UART_REG_LS && !dlab); -assign iir_read = (wb_re_i && wb_addr_i == `UART_REG_II && !dlab); -assign msr_read = (wb_re_i && wb_addr_i == `UART_REG_MS && !dlab); -assign fifo_read = (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab); -assign fifo_write = (wb_we_i && wb_addr_i == `UART_REG_TR && !dlab); - -// lsr_mask_d delayed signal handling -always @(posedge clk or posedge wb_rst_i) -begin - if (wb_rst_i) - lsr_mask_d <= 0; - else // reset bits in the Line Status Register - lsr_mask_d <= lsr_mask_condition; -end - -// lsr_mask is rise detected -assign lsr_mask = lsr_mask_condition && ~lsr_mask_d; - -// msi_reset signal handling -always @(posedge clk or posedge wb_rst_i) -begin - if (wb_rst_i) - msi_reset <= 1; - else - if (msi_reset) - msi_reset <= 0; - else - if (msr_read) - msi_reset <= 1; // reset bits in Modem Status Register -end - - -// -// WRITES AND RESETS // -// -// Line Control Register -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) - lcr <= 8'b00000011; // 8n1 setting - else - if (wb_we_i && wb_addr_i==`UART_REG_LC) - lcr <= wb_dat_i; - -// Interrupt Enable Register or UART_DL2 -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) - begin - ier <= 4'b0000; // no interrupts after reset -`ifdef PRESCALER_PRESET_HARD - dl[`UART_DL2] <= `PRESCALER_HIGH_PRESET; -`else - dl[`UART_DL2] <= 8'b0; -`endif - end - else - if (wb_we_i && wb_addr_i==`UART_REG_IE) - if (dlab) - begin - dl[`UART_DL2] <= -`ifdef PRESCALER_PRESET_HARD - dl[`UART_DL2]; -`else - wb_dat_i; -`endif - end - else - ier <= wb_dat_i[3:0]; // ier uses only 4 lsb - - -// FIFO Control Register and rx_reset, tx_reset signals -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) begin - fcr <= 2'b11; - rx_reset <= 0; - tx_reset <= 0; - end else - if (wb_we_i && wb_addr_i==`UART_REG_FC) begin - fcr <= wb_dat_i[7:6]; - rx_reset <= wb_dat_i[1]; - tx_reset <= wb_dat_i[2]; - end else begin - rx_reset <= 0; - tx_reset <= 0; - end - -// Modem Control Register -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) - mcr <= 5'b0; - else - if (wb_we_i && wb_addr_i==`UART_REG_MC) - mcr <= wb_dat_i[4:0]; - -// Scratch register -// Line Control Register -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) - scratch <= 0; // 8n1 setting - else - if (wb_we_i && wb_addr_i==`UART_REG_SR) - scratch <= wb_dat_i; - -// TX_FIFO or UART_DL1 -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) - begin -`ifdef PRESCALER_PRESET_HARD - dl[`UART_DL1] <= `PRESCALER_LOW_PRESET; -`else - dl[`UART_DL1] <= 8'b0; -`endif - tf_push <= 1'b0; - start_dlc <= 1'b0; - end - else - if (wb_we_i && wb_addr_i==`UART_REG_TR) - if (dlab) - begin -`ifdef PRESCALER_PRESET_HARD - dl[`UART_DL1] <= dl[`UART_DL1]; -`else - dl[`UART_DL1] <= wb_dat_i; -`endif - start_dlc <= 1'b1; // enable DL counter - tf_push <= 1'b0; - end - else - begin - tf_push <= 1'b1; - start_dlc <= 1'b0; - end // else: !if(dlab) - else - begin - start_dlc <= 1'b0; - tf_push <= 1'b0; - end // else: !if(dlab) - -// Receiver FIFO trigger level selection logic (asynchronous mux) -always @(fcr) - case (fcr[`UART_FC_TL]) - 2'b00 : trigger_level = 1; - 2'b01 : trigger_level = 4; - 2'b10 : trigger_level = 8; - 2'b11 : trigger_level = 14; - endcase // case(fcr[`UART_FC_TL]) - -// -// STATUS REGISTERS // -// - -// Modem Status Register -reg [3:0] delayed_modem_signals; -always @(posedge clk or posedge wb_rst_i) -begin - if (wb_rst_i) - begin - msr <= 0; - delayed_modem_signals[3:0] <= 0; - end - else begin - msr[`UART_MS_DDCD:`UART_MS_DCTS] <= msi_reset ? 4'b0 : - msr[`UART_MS_DDCD:`UART_MS_DCTS] | ({dcd, ri, dsr, cts} ^ delayed_modem_signals[3:0]); - msr[`UART_MS_CDCD:`UART_MS_CCTS] <= {dcd_c, ri_c, dsr_c, cts_c}; - delayed_modem_signals[3:0] <= {dcd, ri, dsr, cts}; - end -end - - -// Line Status Register - -// activation conditions -assign lsr0 = (rf_count==0 && rf_push_pulse); // data in receiver fifo available set condition -assign lsr1 = rf_overrun; // Receiver overrun error -assign lsr2 = rf_data_out[1]; // parity error bit -assign lsr3 = rf_data_out[0]; // framing error bit -assign lsr4 = rf_data_out[2]; // break error in the character -assign lsr5 = (tf_count==5'b0 && thre_set_en); // transmitter fifo is empty -assign lsr6 = (tf_count==5'b0 && thre_set_en && (tstate == /*`S_IDLE */ 0)); // transmitter empty -assign lsr7 = rf_error_bit | rf_overrun; - -// lsr bit0 (receiver data available) -reg lsr0_d; - -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) lsr0_d <= 0; - else lsr0_d <= lsr0; - -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) lsr0r <= 0; - else lsr0r <= (rf_count==1 && rf_pop && !rf_push_pulse || rx_reset) ? 1'b0 : // deassert condition - lsr0r || (lsr0 && ~lsr0_d); // set on rise of lsr0 and keep asserted until deasserted - -// lsr bit 1 (receiver overrun) -reg lsr1_d; // delayed - -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) lsr1_d <= 0; - else lsr1_d <= lsr1; - -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) lsr1r <= 0; - else lsr1r <= lsr_mask ? 1'b0 : lsr1r || (lsr1 && ~lsr1_d); // set on rise - -// lsr bit 2 (parity error) -reg lsr2_d; // delayed - -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) lsr2_d <= 0; - else lsr2_d <= lsr2; - -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) lsr2r <= 0; - else lsr2r <= lsr_mask ? 1'b0 : lsr2r || (lsr2 && ~lsr2_d); // set on rise - -// lsr bit 3 (framing error) -reg lsr3_d; // delayed - -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) lsr3_d <= 0; - else lsr3_d <= lsr3; - -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) lsr3r <= 0; - else lsr3r <= lsr_mask ? 1'b0 : lsr3r || (lsr3 && ~lsr3_d); // set on rise - -// lsr bit 4 (break indicator) -reg lsr4_d; // delayed - -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) lsr4_d <= 0; - else lsr4_d <= lsr4; - -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) lsr4r <= 0; - else lsr4r <= lsr_mask ? 1'b0 : lsr4r || (lsr4 && ~lsr4_d); - -// lsr bit 5 (transmitter fifo is empty) -reg lsr5_d; - -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) lsr5_d <= 1; - else lsr5_d <= lsr5; - -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) lsr5r <= 1; - else lsr5r <= (fifo_write) ? 1'b0 : lsr5r || (lsr5 && ~lsr5_d); - -// lsr bit 6 (transmitter empty indicator) -reg lsr6_d; - -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) lsr6_d <= 1; - else lsr6_d <= lsr6; - -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) lsr6r <= 1; - else lsr6r <= (fifo_write) ? 1'b0 : lsr6r || (lsr6 && ~lsr6_d); - -// lsr bit 7 (error in fifo) -reg lsr7_d; - -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) lsr7_d <= 0; - else lsr7_d <= lsr7; - -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) lsr7r <= 0; - else lsr7r <= lsr_mask ? 1'b0 : lsr7r || (lsr7 && ~lsr7_d); - -// Frequency divider -always @(posedge clk or posedge wb_rst_i) -begin - if (wb_rst_i) - dlc <= 0; - else - if (start_dlc | ~ (|dlc)) - dlc <= dl - 16'd1; // preset counter - else - dlc <= dlc - 16'd1; // decrement counter -end - -// Enable signal generation logic -always @(posedge clk or posedge wb_rst_i) -begin - if (wb_rst_i) - enable <= 1'b0; - else - if (|dl & ~(|dlc)) // dl>0 & dlc==0 - enable <= 1'b1; - else - enable <= 1'b0; -end - -// Delaying THRE status for one character cycle after a character is written to an empty fifo. -always @(lcr) - case (lcr[3:0]) - 4'b0000 : block_value = 95; // 6 bits - 4'b0100 : block_value = 103; // 6.5 bits - 4'b0001, 4'b1000 : block_value = 111; // 7 bits - 4'b1100 : block_value = 119; // 7.5 bits - 4'b0010, 4'b0101, 4'b1001 : block_value = 127; // 8 bits - 4'b0011, 4'b0110, 4'b1010, 4'b1101 : block_value = 143; // 9 bits - 4'b0111, 4'b1011, 4'b1110 : block_value = 159; // 10 bits - 4'b1111 : block_value = 175; // 11 bits - endcase // case(lcr[3:0]) - -// Counting time of one character minus stop bit -always @(posedge clk or posedge wb_rst_i) -begin - if (wb_rst_i) - block_cnt <= 8'd0; - else - if(lsr5r & fifo_write) // THRE bit set & write to fifo occured - block_cnt <= SIM ? 8'd1 : block_value; - else - if (enable & block_cnt != 8'b0) // only work on enable times - block_cnt <= block_cnt - 8'd1; // decrement break counter -end // always of break condition detection - -// Generating THRE status enable signal -assign thre_set_en = ~(|block_cnt); - - -// -// INTERRUPT LOGIC -// - -assign rls_int = ier[`UART_IE_RLS] && (lsr[`UART_LS_OE] || lsr[`UART_LS_PE] || lsr[`UART_LS_FE] || lsr[`UART_LS_BI]); -assign rda_int = ier[`UART_IE_RDA] && (rf_count >= {1'b0,trigger_level}); -assign thre_int = ier[`UART_IE_THRE] && lsr[`UART_LS_TFE]; -assign ms_int = ier[`UART_IE_MS] && (| msr[3:0]); -assign ti_int = ier[`UART_IE_RDA] && (counter_t == 10'b0) && (|rf_count); - -reg rls_int_d; -reg thre_int_d; -reg ms_int_d; -reg ti_int_d; -reg rda_int_d; - -// delay lines -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) rls_int_d <= 0; - else rls_int_d <= rls_int; - -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) rda_int_d <= 0; - else rda_int_d <= rda_int; - -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) thre_int_d <= 0; - else thre_int_d <= thre_int; - -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) ms_int_d <= 0; - else ms_int_d <= ms_int; - -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) ti_int_d <= 0; - else ti_int_d <= ti_int; - -// rise detection signals - -wire rls_int_rise; -wire thre_int_rise; -wire ms_int_rise; -wire ti_int_rise; -wire rda_int_rise; - -assign rda_int_rise = rda_int & ~rda_int_d; -assign rls_int_rise = rls_int & ~rls_int_d; -assign thre_int_rise = thre_int & ~thre_int_d; -assign ms_int_rise = ms_int & ~ms_int_d; -assign ti_int_rise = ti_int & ~ti_int_d; - -// interrupt pending flags -reg rls_int_pnd; -reg rda_int_pnd; -reg thre_int_pnd; -reg ms_int_pnd; -reg ti_int_pnd; - -// interrupt pending flags assignments -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) rls_int_pnd <= 0; - else - rls_int_pnd <= lsr_mask ? 1'b0 : // reset condition - rls_int_rise ? 1'b1 : // latch condition - rls_int_pnd && ier[`UART_IE_RLS]; // default operation: remove if masked - -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) rda_int_pnd <= 0; - else - rda_int_pnd <= ((rf_count == {1'b0,trigger_level}) && fifo_read) ? 1'b0 : // reset condition - rda_int_rise ? 1'b1 : // latch condition - rda_int_pnd && ier[`UART_IE_RDA]; // default operation: remove if masked - -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) thre_int_pnd <= 0; - else - thre_int_pnd <= fifo_write || (iir_read & ~iir[`UART_II_IP] & iir[`UART_II_II] == `UART_II_THRE)? 1'b0 : - thre_int_rise ? 1'b1 : - thre_int_pnd && ier[`UART_IE_THRE]; - -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) ms_int_pnd <= 0; - else - ms_int_pnd <= msr_read ? 1'b0 : - ms_int_rise ? 1'b1 : - ms_int_pnd && ier[`UART_IE_MS]; - -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) ti_int_pnd <= 0; - else - ti_int_pnd <= fifo_read ? 1'b0 : - ti_int_rise ? 1'b1 : - ti_int_pnd && ier[`UART_IE_RDA]; -// end of pending flags - -// INT_O logic -always @(posedge clk or posedge wb_rst_i) -begin - if (wb_rst_i) - int_o <= 1'b0; - else - int_o <= - rls_int_pnd ? ~lsr_mask : - rda_int_pnd ? 1'b1 : - ti_int_pnd ? ~fifo_read : - thre_int_pnd ? !(fifo_write & iir_read) : - ms_int_pnd ? ~msr_read : - 1'd0; // if no interrupt are pending -end - - -// Interrupt Identification register -always @(posedge clk or posedge wb_rst_i) -begin - if (wb_rst_i) - iir <= 1; - else - if (rls_int_pnd) // interrupt is pending - begin - iir[`UART_II_II] <= `UART_II_RLS; // set identification register to correct value - iir[`UART_II_IP] <= 1'b0; // and clear the IIR bit 0 (interrupt pending) - end else // the sequence of conditions determines priority of interrupt identification - if (rda_int) - begin - iir[`UART_II_II] <= `UART_II_RDA; - iir[`UART_II_IP] <= 1'b0; - end - else if (ti_int_pnd) - begin - iir[`UART_II_II] <= `UART_II_TI; - iir[`UART_II_IP] <= 1'b0; - end - else if (thre_int_pnd) - begin - iir[`UART_II_II] <= `UART_II_THRE; - iir[`UART_II_IP] <= 1'b0; - end - else if (ms_int_pnd) - begin - iir[`UART_II_II] <= `UART_II_MS; - iir[`UART_II_IP] <= 1'b0; - end else // no interrupt is pending - begin - iir[`UART_II_II] <= 0; - iir[`UART_II_IP] <= 1'b1; - end -end - -endmodule diff --git a/design/target/scala-2.12/classes/vsrc/uart_rfifo.v b/design/target/scala-2.12/classes/vsrc/uart_rfifo.v deleted file mode 100644 index 59a29b93..00000000 --- a/design/target/scala-2.12/classes/vsrc/uart_rfifo.v +++ /dev/null @@ -1,316 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// uart_rfifo.v (Modified from uart_fifo.v) //// -//// //// -//// //// -//// This file is part of the "UART 16550 compatible" project //// -//// http://www.opencores.org/cores/uart16550/ //// -//// //// -//// Documentation related to this project: //// -//// - http://www.opencores.org/cores/uart16550/ //// -//// //// -//// Projects compatibility: //// -//// - WISHBONE //// -//// RS232 Protocol //// -//// 16550D uart (mostly supported) //// -//// //// -//// Overview (main Features): //// -//// UART core receiver FIFO //// -//// //// -//// To Do: //// -//// Nothing. //// -//// //// -//// Author(s): //// -//// - gorban@opencores.org //// -//// - Jacob Gorban //// -//// - Igor Mohor (igorm@opencores.org) //// -//// //// -//// Created: 2001/05/12 //// -//// Last Updated: 2002/07/22 //// -//// (See log for the revision history) //// -//// //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000, 2001 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// Revision 1.3 2003/06/11 16:37:47 gorban -// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. -// -// Revision 1.2 2002/07/29 21:16:18 gorban -// The uart_defines.v file is included again in sources. -// -// Revision 1.1 2002/07/22 23:02:23 gorban -// Bug Fixes: -// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. -// Problem reported by Kenny.Tung. -// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. -// -// Improvements: -// * Made FIFO's as general inferrable memory where possible. -// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). -// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. -// -// * Added optional baudrate output (baud_o). -// This is identical to BAUDOUT* signal on 16550 chip. -// It outputs 16xbit_clock_rate - the divided clock. -// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. -// -// Revision 1.16 2001/12/20 13:25:46 mohor -// rx push changed to be only one cycle wide. -// -// Revision 1.15 2001/12/18 09:01:07 mohor -// Bug that was entered in the last update fixed (rx state machine). -// -// Revision 1.14 2001/12/17 14:46:48 mohor -// overrun signal was moved to separate block because many sequential lsr -// reads were preventing data from being written to rx fifo. -// underrun signal was not used and was removed from the project. -// -// Revision 1.13 2001/11/26 21:38:54 gorban -// Lots of fixes: -// Break condition wasn't handled correctly at all. -// LSR bits could lose their values. -// LSR value after reset was wrong. -// Timing of THRE interrupt signal corrected. -// LSR bit 0 timing corrected. -// -// Revision 1.12 2001/11/08 14:54:23 mohor -// Comments in Slovene language deleted, few small fixes for better work of -// old tools. IRQs need to be fix. -// -// Revision 1.11 2001/11/07 17:51:52 gorban -// Heavily rewritten interrupt and LSR subsystems. -// Many bugs hopefully squashed. -// -// Revision 1.10 2001/10/20 09:58:40 gorban -// Small synopsis fixes -// -// Revision 1.9 2001/08/24 21:01:12 mohor -// Things connected to parity changed. -// Clock devider changed. -// -// Revision 1.8 2001/08/24 08:48:10 mohor -// FIFO was not cleared after the data was read bug fixed. -// -// Revision 1.7 2001/08/23 16:05:05 mohor -// Stop bit bug fixed. -// Parity bug fixed. -// WISHBONE read cycle bug fixed, -// OE indicator (Overrun Error) bug fixed. -// PE indicator (Parity Error) bug fixed. -// Register read bug fixed. -// -// Revision 1.3 2001/05/31 20:08:01 gorban -// FIFO changes and other corrections. -// -// Revision 1.3 2001/05/27 17:37:48 gorban -// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file. -// -// Revision 1.2 2001/05/17 18:34:18 gorban -// First 'stable' release. Should be sythesizable now. Also added new header. -// -// Revision 1.0 2001-05-17 21:27:12+02 jacob -// Initial revision -// -// - -`include "uart_defines.v" - -module uart_rfifo (clk, - wb_rst_i, data_in, data_out, -// Control signals - push, // push strobe, active high - pop, // pop strobe, active high -// status signals - overrun, - count, - error_bit, - fifo_reset, - reset_status - ); - - -// FIFO parameters -parameter fifo_width = `UART_FIFO_WIDTH; -parameter fifo_depth = `UART_FIFO_DEPTH; -parameter fifo_pointer_w = `UART_FIFO_POINTER_W; -parameter fifo_counter_w = `UART_FIFO_COUNTER_W; - -input clk; -input wb_rst_i; -input push; -input pop; -input [fifo_width-1:0] data_in; -input fifo_reset; -input reset_status; - -output [fifo_width-1:0] data_out; -output overrun; -output [fifo_counter_w-1:0] count; -output error_bit; - -wire [fifo_width-1:0] data_out; -wire [7:0] data8_out; -// flags FIFO -reg [2:0] fifo[fifo_depth-1:0]; - -// FIFO pointers -reg [fifo_pointer_w-1:0] top; -reg [fifo_pointer_w-1:0] bottom; - -reg [fifo_counter_w-1:0] count; -reg overrun; - -wire [fifo_pointer_w-1:0] top_plus_1 = top + 4'h1; - -raminfr #(fifo_pointer_w,8,fifo_depth) rfifo - (.clk(clk), - .we(push), - .a(top), - .dpra(bottom), - .di(data_in[fifo_width-1:fifo_width-8]), - .dpo(data8_out) - ); - -always @(posedge clk or posedge wb_rst_i) // synchronous FIFO -begin - if (wb_rst_i) - begin - top <= 0; - bottom <= 0; - count <= 0; - fifo[0] <= 0; - fifo[1] <= 0; - fifo[2] <= 0; - fifo[3] <= 0; - fifo[4] <= 0; - fifo[5] <= 0; - fifo[6] <= 0; - fifo[7] <= 0; - fifo[8] <= 0; - fifo[9] <= 0; - fifo[10] <= 0; - fifo[11] <= 0; - fifo[12] <= 0; - fifo[13] <= 0; - fifo[14] <= 0; - fifo[15] <= 0; - end - else - if (fifo_reset) begin - top <= 0; - bottom <= 0; - count <= 0; - fifo[0] <= 0; - fifo[1] <= 0; - fifo[2] <= 0; - fifo[3] <= 0; - fifo[4] <= 0; - fifo[5] <= 0; - fifo[6] <= 0; - fifo[7] <= 0; - fifo[8] <= 0; - fifo[9] <= 0; - fifo[10] <= 0; - fifo[11] <= 0; - fifo[12] <= 0; - fifo[13] <= 0; - fifo[14] <= 0; - fifo[15] <= 0; - end - else - begin - case ({push, pop}) - 2'b10 : if (count0) - begin - fifo[bottom] <= 0; - bottom <= bottom + 4'd1; - count <= count - 5'd1; - end - 2'b11 : begin - bottom <= bottom + 4'd1; - top <= top_plus_1; - fifo[top] <= data_in[2:0]; - end - default: ; - endcase - end -end // always - -always @(posedge clk or posedge wb_rst_i) // synchronous FIFO -begin - if (wb_rst_i) - overrun <= 1'b0; - else - if(fifo_reset | reset_status) - overrun <= 1'b0; - else - if(push & ~pop & (count==fifo_depth)) - overrun <= 1'b1; -end // always - - -// please note though that data_out is only valid one clock after pop signal -assign data_out = {data8_out,fifo[bottom]}; - -// Additional logic for detection of error conditions (parity and framing) inside the FIFO -// for the Line Status Register bit 7 - -wire [2:0] word0 = fifo[0]; -wire [2:0] word1 = fifo[1]; -wire [2:0] word2 = fifo[2]; -wire [2:0] word3 = fifo[3]; -wire [2:0] word4 = fifo[4]; -wire [2:0] word5 = fifo[5]; -wire [2:0] word6 = fifo[6]; -wire [2:0] word7 = fifo[7]; - -wire [2:0] word8 = fifo[8]; -wire [2:0] word9 = fifo[9]; -wire [2:0] word10 = fifo[10]; -wire [2:0] word11 = fifo[11]; -wire [2:0] word12 = fifo[12]; -wire [2:0] word13 = fifo[13]; -wire [2:0] word14 = fifo[14]; -wire [2:0] word15 = fifo[15]; - -// a 1 is returned if any of the error bits in the fifo is 1 -assign error_bit = |(word0[2:0] | word1[2:0] | word2[2:0] | word3[2:0] | - word4[2:0] | word5[2:0] | word6[2:0] | word7[2:0] | - word8[2:0] | word9[2:0] | word10[2:0] | word11[2:0] | - word12[2:0] | word13[2:0] | word14[2:0] | word15[2:0] ); - -endmodule diff --git a/design/target/scala-2.12/classes/vsrc/uart_sync_flops.v b/design/target/scala-2.12/classes/vsrc/uart_sync_flops.v deleted file mode 100644 index 82a3a615..00000000 --- a/design/target/scala-2.12/classes/vsrc/uart_sync_flops.v +++ /dev/null @@ -1,117 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// uart_sync_flops.v //// -//// //// -//// //// -//// This file is part of the "UART 16550 compatible" project //// -//// http://www.opencores.org/cores/uart16550/ //// -//// //// -//// Documentation related to this project: //// -//// - http://www.opencores.org/cores/uart16550/ //// -//// //// -//// Projects compatibility: //// -//// - WISHBONE //// -//// RS232 Protocol //// -//// 16550D uart (mostly supported) //// -//// //// -//// Overview (main Features): //// -//// UART core receiver logic //// -//// //// -//// Known problems (limits): //// -//// None known //// -//// //// -//// To Do: //// -//// Thourough testing. //// -//// //// -//// Author(s): //// -//// - Andrej Erzen (andreje@flextronics.si) //// -//// - Tadej Markovic (tadejm@flextronics.si) //// -//// //// -//// Created: 2004/05/20 //// -//// Last Updated: 2004/05/20 //// -//// (See log for the revision history) //// -//// //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000, 2001 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// - -module uart_sync_flops -( - // internal signals - rst_i, - clk_i, - stage1_rst_i, - stage1_clk_en_i, - async_dat_i, - sync_dat_o -); - -parameter width = 1; -parameter init_value = 1'b0; - -input rst_i; // reset input -input clk_i; // clock input -input stage1_rst_i; // synchronous reset for stage 1 FF -input stage1_clk_en_i; // synchronous clock enable for stage 1 FF -input [width-1:0] async_dat_i; // asynchronous data input -output [width-1:0] sync_dat_o; // synchronous data output - - -// -// Interal signal declarations -// - -reg [width-1:0] sync_dat_o; -reg [width-1:0] flop_0; - - -// first stage -always @ (posedge clk_i or posedge rst_i) -begin - if (rst_i) - flop_0 <= {width{init_value}}; - else - flop_0 <= async_dat_i; -end - -// second stage -always @ (posedge clk_i or posedge rst_i) -begin - if (rst_i) - sync_dat_o <= {width{init_value}}; - else if (stage1_rst_i) - sync_dat_o <= {width{init_value}}; - else if (stage1_clk_en_i) - sync_dat_o <= flop_0; -end - -endmodule diff --git a/design/target/scala-2.12/classes/vsrc/uart_tfifo.v b/design/target/scala-2.12/classes/vsrc/uart_tfifo.v deleted file mode 100644 index 5b254cba..00000000 --- a/design/target/scala-2.12/classes/vsrc/uart_tfifo.v +++ /dev/null @@ -1,239 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// uart_tfifo.v //// -//// //// -//// //// -//// This file is part of the "UART 16550 compatible" project //// -//// http://www.opencores.org/cores/uart16550/ //// -//// //// -//// Documentation related to this project: //// -//// - http://www.opencores.org/cores/uart16550/ //// -//// //// -//// Projects compatibility: //// -//// - WISHBONE //// -//// RS232 Protocol //// -//// 16550D uart (mostly supported) //// -//// //// -//// Overview (main Features): //// -//// UART core transmitter FIFO //// -//// //// -//// To Do: //// -//// Nothing. //// -//// //// -//// Author(s): //// -//// - gorban@opencores.org //// -//// - Jacob Gorban //// -//// - Igor Mohor (igorm@opencores.org) //// -//// //// -//// Created: 2001/05/12 //// -//// Last Updated: 2002/07/22 //// -//// (See log for the revision history) //// -//// //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000, 2001 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// Revision 1.1 2002/07/22 23:02:23 gorban -// Bug Fixes: -// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. -// Problem reported by Kenny.Tung. -// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. -// -// Improvements: -// * Made FIFO's as general inferrable memory where possible. -// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). -// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. -// -// * Added optional baudrate output (baud_o). -// This is identical to BAUDOUT* signal on 16550 chip. -// It outputs 16xbit_clock_rate - the divided clock. -// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. -// -// Revision 1.16 2001/12/20 13:25:46 mohor -// rx push changed to be only one cycle wide. -// -// Revision 1.15 2001/12/18 09:01:07 mohor -// Bug that was entered in the last update fixed (rx state machine). -// -// Revision 1.14 2001/12/17 14:46:48 mohor -// overrun signal was moved to separate block because many sequential lsr -// reads were preventing data from being written to rx fifo. -// underrun signal was not used and was removed from the project. -// -// Revision 1.13 2001/11/26 21:38:54 gorban -// Lots of fixes: -// Break condition wasn't handled correctly at all. -// LSR bits could lose their values. -// LSR value after reset was wrong. -// Timing of THRE interrupt signal corrected. -// LSR bit 0 timing corrected. -// -// Revision 1.12 2001/11/08 14:54:23 mohor -// Comments in Slovene language deleted, few small fixes for better work of -// old tools. IRQs need to be fix. -// -// Revision 1.11 2001/11/07 17:51:52 gorban -// Heavily rewritten interrupt and LSR subsystems. -// Many bugs hopefully squashed. -// -// Revision 1.10 2001/10/20 09:58:40 gorban -// Small synopsis fixes -// -// Revision 1.9 2001/08/24 21:01:12 mohor -// Things connected to parity changed. -// Clock devider changed. -// -// Revision 1.8 2001/08/24 08:48:10 mohor -// FIFO was not cleared after the data was read bug fixed. -// -// Revision 1.7 2001/08/23 16:05:05 mohor -// Stop bit bug fixed. -// Parity bug fixed. -// WISHBONE read cycle bug fixed, -// OE indicator (Overrun Error) bug fixed. -// PE indicator (Parity Error) bug fixed. -// Register read bug fixed. -// -// Revision 1.3 2001/05/31 20:08:01 gorban -// FIFO changes and other corrections. -// -// Revision 1.3 2001/05/27 17:37:48 gorban -// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file. -// -// Revision 1.2 2001/05/17 18:34:18 gorban -// First 'stable' release. Should be sythesizable now. Also added new header. -// -// Revision 1.0 2001-05-17 21:27:12+02 jacob -// Initial revision -// -// - -`include "uart_defines.v" - -module uart_tfifo (clk, - wb_rst_i, data_in, data_out, -// Control signals - push, // push strobe, active high - pop, // pop strobe, active high -// status signals - overrun, - count, - fifo_reset, - reset_status - ); - - -// FIFO parameters -parameter fifo_width = `UART_FIFO_WIDTH; -parameter fifo_depth = `UART_FIFO_DEPTH; -parameter fifo_pointer_w = `UART_FIFO_POINTER_W; -parameter fifo_counter_w = `UART_FIFO_COUNTER_W; - -input clk; -input wb_rst_i; -input push; -input pop; -input [fifo_width-1:0] data_in; -input fifo_reset; -input reset_status; - -output [fifo_width-1:0] data_out; -output overrun; -output [fifo_counter_w-1:0] count; - -wire [fifo_width-1:0] data_out; - -// FIFO pointers -reg [fifo_pointer_w-1:0] top; -reg [fifo_pointer_w-1:0] bottom; - -reg [fifo_counter_w-1:0] count; -reg overrun; -wire [fifo_pointer_w-1:0] top_plus_1 = top + 4'd1; - -raminfr #(fifo_pointer_w,fifo_width,fifo_depth) tfifo - (.clk(clk), - .we(push), - .a(top), - .dpra(bottom), - .di(data_in), - .dpo(data_out) - ); - - -always @(posedge clk or posedge wb_rst_i) // synchronous FIFO -begin - if (wb_rst_i) - begin - top <= 0; - bottom <= 0; - count <= 0; - end - else - if (fifo_reset) begin - top <= 0; - bottom <= 0; - count <= 0; - end - else - begin - case ({push, pop}) - 2'b10 : if (count0) - begin - bottom <= bottom + 4'd1; - count <= count - 5'd1; - end - 2'b11 : begin - bottom <= bottom + 4'd1; - top <= top_plus_1; - end - default: ; - endcase - end -end // always - -always @(posedge clk or posedge wb_rst_i) // synchronous FIFO -begin - if (wb_rst_i) - overrun <= 1'b0; - else - if(fifo_reset | reset_status) - overrun <= 1'b0; - else - if(push & (count==fifo_depth)) - overrun <= 1'b1; -end // always - -endmodule diff --git a/design/target/scala-2.12/classes/vsrc/uart_top.v b/design/target/scala-2.12/classes/vsrc/uart_top.v deleted file mode 100644 index 528f2f72..00000000 --- a/design/target/scala-2.12/classes/vsrc/uart_top.v +++ /dev/null @@ -1,261 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// uart_top.v //// -//// //// -//// //// -//// This file is part of the "UART 16550 compatible" project //// -//// http://www.opencores.org/cores/uart16550/ //// -//// //// -//// Documentation related to this project: //// -//// - http://www.opencores.org/cores/uart16550/ //// -//// //// -//// Projects compatibility: //// -//// - WISHBONE //// -//// RS232 Protocol //// -//// 16550D uart (mostly supported) //// -//// //// -//// Overview (main Features): //// -//// UART core top level. //// -//// //// -//// Known problems (limits): //// -//// Note that transmitter and receiver instances are inside //// -//// the uart_regs.v file. //// -//// //// -//// To Do: //// -//// Nothing so far. //// -//// //// -//// Author(s): //// -//// - gorban@opencores.org //// -//// - Jacob Gorban //// -//// - Igor Mohor (igorm@opencores.org) //// -//// //// -//// Created: 2001/05/12 //// -//// Last Updated: 2001/05/17 //// -//// (See log for the revision history) //// -//// //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000, 2001 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// Revision 1.18 2002/07/22 23:02:23 gorban -// Bug Fixes: -// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. -// Problem reported by Kenny.Tung. -// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. -// -// Improvements: -// * Made FIFO's as general inferrable memory where possible. -// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). -// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. -// -// * Added optional baudrate output (baud_o). -// This is identical to BAUDOUT* signal on 16550 chip. -// It outputs 16xbit_clock_rate - the divided clock. -// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. -// -// Revision 1.17 2001/12/19 08:40:03 mohor -// Warnings fixed (unused signals removed). -// -// Revision 1.16 2001/12/06 14:51:04 gorban -// Bug in LSR[0] is fixed. -// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers. -// -// Revision 1.15 2001/12/03 21:44:29 gorban -// Updated specification documentation. -// Added full 32-bit data bus interface, now as default. -// Address is 5-bit wide in 32-bit data bus mode. -// Added wb_sel_i input to the core. It's used in the 32-bit mode. -// Added debug interface with two 32-bit read-only registers in 32-bit mode. -// Bits 5 and 6 of LSR are now only cleared on TX FIFO write. -// My small test bench is modified to work with 32-bit mode. -// -// Revision 1.14 2001/11/07 17:51:52 gorban -// Heavily rewritten interrupt and LSR subsystems. -// Many bugs hopefully squashed. -// -// Revision 1.13 2001/10/20 09:58:40 gorban -// Small synopsis fixes -// -// Revision 1.12 2001/08/25 15:46:19 gorban -// Modified port names again -// -// Revision 1.11 2001/08/24 21:01:12 mohor -// Things connected to parity changed. -// Clock devider changed. -// -// Revision 1.10 2001/08/23 16:05:05 mohor -// Stop bit bug fixed. -// Parity bug fixed. -// WISHBONE read cycle bug fixed, -// OE indicator (Overrun Error) bug fixed. -// PE indicator (Parity Error) bug fixed. -// Register read bug fixed. -// -// Revision 1.4 2001/05/31 20:08:01 gorban -// FIFO changes and other corrections. -// -// Revision 1.3 2001/05/21 19:12:02 gorban -// Corrected some Linter messages. -// -// Revision 1.2 2001/05/17 18:34:18 gorban -// First 'stable' release. Should be sythesizable now. Also added new header. -// -// Revision 1.0 2001-05-17 21:27:12+02 jacob -// Initial revision -// -// - -`include "uart_defines.v" - -module uart_top ( - wb_clk_i, - - // Wishbone signals - wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_sel_i, - int_o, // interrupt request - - // UART signals - // serial input/output - stx_pad_o, srx_pad_i, - - // modem signals - rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i -`ifdef UART_HAS_BAUDRATE_OUTPUT - , baud_o -`endif - ); -parameter SIM = 0; -parameter debug = 0; - -input wb_clk_i; - -// WISHBONE interface -input wb_rst_i; -input [2:0] wb_adr_i; -input [7:0] wb_dat_i; -output [7:0] wb_dat_o; -input wb_we_i; -input wb_stb_i; -input wb_cyc_i; -input [3:0] wb_sel_i; -output wb_ack_o; -output int_o; - -// UART signals -input srx_pad_i; -output stx_pad_o; -output rts_pad_o; -input cts_pad_i; -output dtr_pad_o; -input dsr_pad_i; -input ri_pad_i; -input dcd_pad_i; - -// optional baudrate output -`ifdef UART_HAS_BAUDRATE_OUTPUT -output baud_o; -`endif - - -wire stx_pad_o; -wire rts_pad_o; -wire dtr_pad_o; - -wire [2:0] wb_adr_i; -wire [7:0] wb_dat_i; -wire [7:0] wb_dat_o; - -wire [7:0] wb_dat8_i; // 8-bit internal data input -wire [7:0] wb_dat8_o; // 8-bit internal data output -wire [31:0] wb_dat32_o; // debug interface 32-bit output -wire [3:0] wb_sel_i; // WISHBONE select signal -wire [2:0] wb_adr_int; -wire we_o; // Write enable for registers -wire re_o; // Read enable for registers -// -// MODULE INSTANCES -// - -//// WISHBONE interface module -uart_wb wb_interface( - .clk( wb_clk_i ), - .wb_rst_i( wb_rst_i ), - .wb_dat_i(wb_dat_i), - .wb_dat_o(wb_dat_o), - .wb_dat8_i(wb_dat8_i), - .wb_dat8_o(wb_dat8_o), - .wb_dat32_o(32'b0), - .wb_sel_i(4'b0), - .wb_we_i( wb_we_i ), - .wb_stb_i( wb_stb_i ), - .wb_cyc_i( wb_cyc_i ), - .wb_ack_o( wb_ack_o ), - .wb_adr_i(wb_adr_i), - .wb_adr_int(wb_adr_int), - .we_o( we_o ), - .re_o(re_o) - ); - -// Registers -uart_regs #(.SIM (SIM)) regs( - .clk( wb_clk_i ), - .wb_rst_i( wb_rst_i ), - .wb_addr_i( wb_adr_int ), - .wb_dat_i( wb_dat8_i ), - .wb_dat_o( wb_dat8_o ), - .wb_we_i( we_o ), - .wb_re_i(re_o), - .modem_inputs( {cts_pad_i, dsr_pad_i, - ri_pad_i, dcd_pad_i} ), - .stx_pad_o( stx_pad_o ), - .srx_pad_i( srx_pad_i ), - .rts_pad_o( rts_pad_o ), - .dtr_pad_o( dtr_pad_o ), - .int_o( int_o ) -`ifdef UART_HAS_BAUDRATE_OUTPUT - , .baud_o(baud_o) -`endif - -); - -initial -begin - if(debug) begin - `ifdef UART_HAS_BAUDRATE_OUTPUT - $display("(%m) UART INFO: Has baudrate output\n"); - `else - $display("(%m) UART INFO: Doesn't have baudrate output\n"); - `endif - end -end - -endmodule - - diff --git a/design/target/scala-2.12/classes/vsrc/uart_transmitter.v b/design/target/scala-2.12/classes/vsrc/uart_transmitter.v deleted file mode 100644 index e2e8cf39..00000000 --- a/design/target/scala-2.12/classes/vsrc/uart_transmitter.v +++ /dev/null @@ -1,354 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// uart_transmitter.v //// -//// //// -//// //// -//// This file is part of the "UART 16550 compatible" project //// -//// http://www.opencores.org/cores/uart16550/ //// -//// //// -//// Documentation related to this project: //// -//// - http://www.opencores.org/cores/uart16550/ //// -//// //// -//// Projects compatibility: //// -//// - WISHBONE //// -//// RS232 Protocol //// -//// 16550D uart (mostly supported) //// -//// //// -//// Overview (main Features): //// -//// UART core transmitter logic //// -//// //// -//// Known problems (limits): //// -//// None known //// -//// //// -//// To Do: //// -//// Thourough testing. //// -//// //// -//// Author(s): //// -//// - gorban@opencores.org //// -//// - Jacob Gorban //// -//// - Igor Mohor (igorm@opencores.org) //// -//// //// -//// Created: 2001/05/12 //// -//// Last Updated: 2001/05/17 //// -//// (See log for the revision history) //// -//// //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000, 2001 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// Revision 1.18 2002/07/22 23:02:23 gorban -// Bug Fixes: -// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. -// Problem reported by Kenny.Tung. -// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. -// -// Improvements: -// * Made FIFO's as general inferrable memory where possible. -// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). -// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. -// -// * Added optional baudrate output (baud_o). -// This is identical to BAUDOUT* signal on 16550 chip. -// It outputs 16xbit_clock_rate - the divided clock. -// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. -// -// Revision 1.16 2002/01/08 11:29:40 mohor -// tf_pop was too wide. Now it is only 1 clk cycle width. -// -// Revision 1.15 2001/12/17 14:46:48 mohor -// overrun signal was moved to separate block because many sequential lsr -// reads were preventing data from being written to rx fifo. -// underrun signal was not used and was removed from the project. -// -// Revision 1.14 2001/12/03 21:44:29 gorban -// Updated specification documentation. -// Added full 32-bit data bus interface, now as default. -// Address is 5-bit wide in 32-bit data bus mode. -// Added wb_sel_i input to the core. It's used in the 32-bit mode. -// Added debug interface with two 32-bit read-only registers in 32-bit mode. -// Bits 5 and 6 of LSR are now only cleared on TX FIFO write. -// My small test bench is modified to work with 32-bit mode. -// -// Revision 1.13 2001/11/08 14:54:23 mohor -// Comments in Slovene language deleted, few small fixes for better work of -// old tools. IRQs need to be fix. -// -// Revision 1.12 2001/11/07 17:51:52 gorban -// Heavily rewritten interrupt and LSR subsystems. -// Many bugs hopefully squashed. -// -// Revision 1.11 2001/10/29 17:00:46 gorban -// fixed parity sending and tx_fifo resets over- and underrun -// -// Revision 1.10 2001/10/20 09:58:40 gorban -// Small synopsis fixes -// -// Revision 1.9 2001/08/24 21:01:12 mohor -// Things connected to parity changed. -// Clock devider changed. -// -// Revision 1.8 2001/08/23 16:05:05 mohor -// Stop bit bug fixed. -// Parity bug fixed. -// WISHBONE read cycle bug fixed, -// OE indicator (Overrun Error) bug fixed. -// PE indicator (Parity Error) bug fixed. -// Register read bug fixed. -// -// Revision 1.6 2001/06/23 11:21:48 gorban -// DL made 16-bit long. Fixed transmission/reception bugs. -// -// Revision 1.5 2001/06/02 14:28:14 gorban -// Fixed receiver and transmitter. Major bug fixed. -// -// Revision 1.4 2001/05/31 20:08:01 gorban -// FIFO changes and other corrections. -// -// Revision 1.3 2001/05/27 17:37:49 gorban -// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file. -// -// Revision 1.2 2001/05/21 19:12:02 gorban -// Corrected some Linter messages. -// -// Revision 1.1 2001/05/17 18:34:18 gorban -// First 'stable' release. Should be sythesizable now. Also added new header. -// -// Revision 1.0 2001-05-17 21:27:12+02 jacob -// Initial revision -// -// - -`include "uart_defines.v" - -module uart_transmitter -#(parameter SIM = 0) - (clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, tstate, tf_count, tx_reset, lsr_mask); - -input clk; -input wb_rst_i; -input [7:0] lcr; -input tf_push; -input [7:0] wb_dat_i; -input enable; -input tx_reset; -input lsr_mask; //reset of fifo -output stx_pad_o; -output [2:0] tstate; -output [`UART_FIFO_COUNTER_W-1:0] tf_count; - -reg [2:0] tstate; -reg [4:0] counter; -reg [2:0] bit_counter; // counts the bits to be sent -reg [6:0] shift_out; // output shift register -reg stx_o_tmp; -reg parity_xor; // parity of the word -reg tf_pop; -reg bit_out; - -// TX FIFO instance -// -// Transmitter FIFO signals -wire [`UART_FIFO_WIDTH-1:0] tf_data_in; -wire [`UART_FIFO_WIDTH-1:0] tf_data_out; -wire tf_push; -wire tf_overrun; -wire [`UART_FIFO_COUNTER_W-1:0] tf_count; - -assign tf_data_in = wb_dat_i; - -uart_tfifo fifo_tx( // error bit signal is not used in transmitter FIFO - .clk( clk ), - .wb_rst_i( wb_rst_i ), - .data_in( tf_data_in ), - .data_out( tf_data_out ), - .push( tf_push ), - .pop( tf_pop ), - .overrun( tf_overrun ), - .count( tf_count ), - .fifo_reset( tx_reset ), - .reset_status(lsr_mask) -); - -// TRANSMITTER FINAL STATE MACHINE - -localparam s_idle = 3'd0; -localparam s_send_start = 3'd1; -localparam s_send_byte = 3'd2; -localparam s_send_parity = 3'd3; -localparam s_send_stop = 3'd4; -localparam s_pop_byte = 3'd5; - -always @(posedge clk or posedge wb_rst_i) -begin - if (wb_rst_i) - begin - tstate <= s_idle; - stx_o_tmp <= 1'b1; - counter <= 5'b0; - shift_out <= 7'b0; - bit_out <= 1'b0; - parity_xor <= 1'b0; - tf_pop <= 1'b0; - bit_counter <= 3'b0; - end - else - if (enable | SIM) - begin - case (tstate) - s_idle : if (~|tf_count) // if tf_count==0 - begin - tstate <= s_idle; - stx_o_tmp <= 1'b1; - end - else - begin - tf_pop <= 1'b0; - stx_o_tmp <= 1'b1; - tstate <= s_pop_byte; - end - s_pop_byte : begin - tf_pop <= 1'b1; - case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word - 2'b00 : begin - bit_counter <= 3'b100; - parity_xor <= ^tf_data_out[4:0]; - end - 2'b01 : begin - bit_counter <= 3'b101; - parity_xor <= ^tf_data_out[5:0]; - end - 2'b10 : begin - bit_counter <= 3'b110; - parity_xor <= ^tf_data_out[6:0]; - end - 2'b11 : begin - bit_counter <= 3'b111; - parity_xor <= ^tf_data_out[7:0]; - end - endcase - {shift_out[6:0], bit_out} <= tf_data_out; - tstate <= s_send_start; - end - s_send_start : begin - tf_pop <= 1'b0; - if (~|counter) - counter <= 5'b01111; - else - if (counter == 5'b00001) - begin - counter <= 0; - tstate <= s_send_byte; - end - else - counter <= counter - 5'd1; - stx_o_tmp <= 1'b0; - if (SIM) begin - tstate <= s_idle; - $write("%c", tf_data_out); - $fflush(32'h80000001); - end - end - s_send_byte : begin - if (~|counter) - counter <= 5'b01111; - else - if (counter == 5'b00001) - begin - if (bit_counter > 3'b0) - begin - bit_counter <= bit_counter - 3'd1; - {shift_out[5:0],bit_out } <= {shift_out[6:1], shift_out[0]}; - tstate <= s_send_byte; - end - else // end of byte - if (~lcr[`UART_LC_PE]) - begin - tstate <= s_send_stop; - end - else - begin - case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]}) - 2'b00: bit_out <= ~parity_xor; - 2'b01: bit_out <= 1'b1; - 2'b10: bit_out <= parity_xor; - 2'b11: bit_out <= 1'b0; - endcase - tstate <= s_send_parity; - end - counter <= 0; - end - else - counter <= counter - 5'd1; - stx_o_tmp <= bit_out; // set output pin - end - s_send_parity : begin - if (~|counter) - counter <= 5'b01111; - else - if (counter == 5'b00001) - begin - counter <= 5'd0; - tstate <= s_send_stop; - end - else - counter <= counter - 5'd1; - stx_o_tmp <= bit_out; - end - s_send_stop : begin - if (~|counter) - begin - casez ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]}) - 3'b0??: counter <= 5'b01101; // 1 stop bit ok igor - 3'b100: counter <= 5'b10101; // 1.5 stop bit - default: counter <= 5'b11101; // 2 stop bits - endcase - end - else - if (counter == 5'b00001) - begin - counter <= 0; - tstate <= s_idle; - end - else - counter <= counter - 5'd1; - stx_o_tmp <= 1'b1; - end - - default : // should never get here - tstate <= s_idle; - endcase - end // end if enable - else - tf_pop <= 1'b0; // tf_pop must be 1 cycle width -end // transmitter logic - -assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp; // Break condition - -endmodule diff --git a/design/target/scala-2.12/classes/vsrc/uart_wb.v b/design/target/scala-2.12/classes/vsrc/uart_wb.v deleted file mode 100644 index d537b700..00000000 --- a/design/target/scala-2.12/classes/vsrc/uart_wb.v +++ /dev/null @@ -1,258 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// uart_wb.v //// -//// //// -//// //// -//// This file is part of the "UART 16550 compatible" project //// -//// http://www.opencores.org/cores/uart16550/ //// -//// //// -//// Documentation related to this project: //// -//// - http://www.opencores.org/cores/uart16550/ //// -//// //// -//// Projects compatibility: //// -//// - WISHBONE //// -//// RS232 Protocol //// -//// 16550D uart (mostly supported) //// -//// //// -//// Overview (main Features): //// -//// UART core WISHBONE interface. //// -//// //// -//// Known problems (limits): //// -//// Inserts one wait state on all transfers. //// -//// Note affected signals and the way they are affected. //// -//// //// -//// To Do: //// -//// Nothing. //// -//// //// -//// Author(s): //// -//// - gorban@opencores.org //// -//// - Jacob Gorban //// -//// - Igor Mohor (igorm@opencores.org) //// -//// //// -//// Created: 2001/05/12 //// -//// Last Updated: 2001/05/17 //// -//// (See log for the revision history) //// -//// //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000, 2001 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// Revision 1.16 2002/07/29 21:16:18 gorban -// The uart_defines.v file is included again in sources. -// -// Revision 1.15 2002/07/22 23:02:23 gorban -// Bug Fixes: -// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. -// Problem reported by Kenny.Tung. -// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. -// -// Improvements: -// * Made FIFO's as general inferrable memory where possible. -// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). -// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. -// -// * Added optional baudrate output (baud_o). -// This is identical to BAUDOUT* signal on 16550 chip. -// It outputs 16xbit_clock_rate - the divided clock. -// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. -// -// Revision 1.12 2001/12/19 08:03:34 mohor -// Warnings cleared. -// -// Revision 1.11 2001/12/06 14:51:04 gorban -// Bug in LSR[0] is fixed. -// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers. -// -// Revision 1.10 2001/12/03 21:44:29 gorban -// Updated specification documentation. -// Added full 32-bit data bus interface, now as default. -// Address is 5-bit wide in 32-bit data bus mode. -// Added wb_sel_i input to the core. It's used in the 32-bit mode. -// Added debug interface with two 32-bit read-only registers in 32-bit mode. -// Bits 5 and 6 of LSR are now only cleared on TX FIFO write. -// My small test bench is modified to work with 32-bit mode. -// -// Revision 1.9 2001/10/20 09:58:40 gorban -// Small synopsis fixes -// -// Revision 1.8 2001/08/24 21:01:12 mohor -// Things connected to parity changed. -// Clock devider changed. -// -// Revision 1.7 2001/08/23 16:05:05 mohor -// Stop bit bug fixed. -// Parity bug fixed. -// WISHBONE read cycle bug fixed, -// OE indicator (Overrun Error) bug fixed. -// PE indicator (Parity Error) bug fixed. -// Register read bug fixed. -// -// Revision 1.4 2001/05/31 20:08:01 gorban -// FIFO changes and other corrections. -// -// Revision 1.3 2001/05/21 19:12:01 gorban -// Corrected some Linter messages. -// -// Revision 1.2 2001/05/17 18:34:18 gorban -// First 'stable' release. Should be sythesizable now. Also added new header. -// -// Revision 1.0 2001-05-17 21:27:13+02 jacob -// Initial revision -// -// - -// UART core WISHBONE interface -// -// Author: Jacob Gorban (jacob.gorban@flextronicssemi.com) -// Company: Flextronics Semiconductor -// - -`include "uart_defines.v" - -module uart_wb (clk, wb_rst_i, - wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_adr_i, - wb_adr_int, wb_dat_i, wb_dat_o, wb_dat8_i, wb_dat8_o, wb_dat32_o, wb_sel_i, - we_o, re_o // Write and read enable output for the core -); - -input clk; - -// WISHBONE interface -input wb_rst_i; -input wb_we_i; -input wb_stb_i; -input wb_cyc_i; -input [3:0] wb_sel_i; -input [2:0] wb_adr_i; //WISHBONE address line - -input [7:0] wb_dat_i; //input WISHBONE bus -output [7:0] wb_dat_o; -reg [7:0] wb_dat_o; -wire [7:0] wb_dat_i; -reg [7:0] wb_dat_is; - -output [2:0] wb_adr_int; // internal signal for address bus -input [7:0] wb_dat8_o; // internal 8 bit output to be put into wb_dat_o -output [7:0] wb_dat8_i; -input [31:0] wb_dat32_o; // 32 bit data output (for debug interface) -output wb_ack_o; -output we_o; -output re_o; - -wire we_o; -reg wb_ack_o; -reg [7:0] wb_dat8_i; -wire [7:0] wb_dat8_o; -wire [2:0] wb_adr_int; // internal signal for address bus -reg [2:0] wb_adr_is; -reg wb_we_is; -reg wb_cyc_is; -reg wb_stb_is; -wire [3:0] wb_sel_i; -reg wre ;// timing control signal for write or read enable - -// wb_ack_o FSM -reg [1:0] wbstate; -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) begin - wb_ack_o <= 1'b0; - wbstate <= 0; - wre <= 1'b1; - end else - case (wbstate) - 0: begin - if (wb_stb_is & wb_cyc_is) begin - wre <= 0; - wbstate <= 1; - wb_ack_o <= 1; - end else begin - wre <= 1; - wb_ack_o <= 0; - end - end - 1: begin - wb_ack_o <= 0; - wbstate <= 2; - wre <= 0; - end - 2: begin - wb_ack_o <= 0; - wbstate <= 3; - wre <= 0; - end - 3: begin - wb_ack_o <= 0; - wbstate <= 0; - wre <= 1; - end - endcase - -assign we_o = wb_we_is & wb_stb_is & wb_cyc_is & wre ; //WE for registers -assign re_o = ~wb_we_is & wb_stb_is & wb_cyc_is & wre ; //RE for registers - -// Sample input signals -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) begin - wb_adr_is <= 0; - wb_we_is <= 0; - wb_cyc_is <= 0; - wb_stb_is <= 0; - wb_dat_is <= 0; - end else begin - wb_adr_is <= wb_adr_i; - wb_we_is <= wb_we_i; - wb_cyc_is <= wb_cyc_i; - wb_stb_is <= wb_stb_i; - wb_dat_is <= wb_dat_i; - end - -always @(posedge clk or posedge wb_rst_i) - if (wb_rst_i) - wb_dat_o <= 0; - else - wb_dat_o <= wb_dat8_o; - -always @(wb_dat_is) - wb_dat8_i = wb_dat_is; - -assign wb_adr_int = wb_adr_is; - - -endmodule - - - - - - - - - - diff --git a/design/target/scala-2.12/classes/vsrc/wb_mem_wrapper.v b/design/target/scala-2.12/classes/vsrc/wb_mem_wrapper.v deleted file mode 100644 index 283e268a..00000000 --- a/design/target/scala-2.12/classes/vsrc/wb_mem_wrapper.v +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 -// Copyright 2019 Western Digital Corporation or its affiliates. -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -//******************************************************************************** -// $Id$ -// -// Function: Wrapper for on-chip memory instantiations -// Comments: -// -//******************************************************************************** - -`default_nettype none -module wb_mem_wrapper - #(parameter MEM_SIZE = 0, - parameter mem_clear = 0, - parameter INIT_FILE = "") - ( - input wire i_clk, - input wire i_rst, - input wire [$clog2(MEM_SIZE)-1:2] i_wb_adr, - input wire [31:0] i_wb_dat, - input wire [3:0] i_wb_sel, - input wire i_wb_we , - input wire i_wb_cyc, - input wire i_wb_stb, - output reg o_wb_ack, - output wire [31:0] o_wb_rdt); - - wire [31:0] mem_addr; - wire [63:0] mem_wdata; - wire [63:0] mem_rdata; - - wire [7:0] mem_we; - - assign mem_we[3:0] = (i_wb_cyc & i_wb_stb & i_wb_we & !i_wb_adr[2]) ? i_wb_sel : 4'd0; - assign mem_we[7:4] = (i_wb_cyc & i_wb_stb & i_wb_we & i_wb_adr[2]) ? i_wb_sel : 4'd0; - - assign mem_wdata = {i_wb_dat, i_wb_dat}; - - assign o_wb_rdt = i_wb_adr[2] ? mem_rdata[63:32] : mem_rdata[31:0]; - - always @(posedge i_clk) begin - o_wb_ack <= i_wb_cyc & i_wb_stb & !o_wb_ack; - if (i_rst) - o_wb_ack <= 1'b0; - end - - dpram64 - #(.SIZE (MEM_SIZE), - .mem_clear (mem_clear), - .memfile (INIT_FILE)) - ram - (.clk (i_clk), - .we (mem_we), - .din (mem_wdata), - .waddr ({i_wb_adr[$clog2(MEM_SIZE)-1:3],3'b000}), - .raddr ({i_wb_adr[$clog2(MEM_SIZE)-1:3],3'b000}), - .dout (mem_rdata)); - -endmodule diff --git a/design/target/scala-2.12/quasar_2.12-3.3.0.jar b/design/target/scala-2.12/quasar_2.12-3.3.0.jar deleted file mode 100644 index 4723cf8a..00000000 Binary files a/design/target/scala-2.12/quasar_2.12-3.3.0.jar and /dev/null differ diff --git a/design/target/scala-2.12/update/update_cache_2.12/inputs b/design/target/scala-2.12/update/update_cache_2.12/inputs deleted file mode 100644 index bd0d9c65..00000000 --- a/design/target/scala-2.12/update/update_cache_2.12/inputs +++ /dev/null @@ -1 +0,0 @@ -699957781 \ No newline at end of file diff --git a/design/target/scala-2.12/update/update_cache_2.12/output b/design/target/scala-2.12/update/update_cache_2.12/output deleted file mode 100644 index ea6017ca..00000000 --- a/design/target/scala-2.12/update/update_cache_2.12/output +++ /dev/null @@ -1 +0,0 @@ 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