Bus-buffer testing start

el2_lsu_bus_buffer.fir

@@ -2516,13 +2516,13 @@ circuit el2_lsu_bus_buffer :
     obuf_merge_en <= _T_1764 @[el2_lsu_bus_buffer.scala 367:17]
     reg obuf_wr_enQ : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 374:55]
     obuf_wr_enQ <= obuf_wr_en @[el2_lsu_bus_buffer.scala 374:55]
-    node _T_1765 = eq(obuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 375:76]
-    node _T_1766 = mux(obuf_wr_en, UInt<1>("h01"), _T_1765) @[el2_lsu_bus_buffer.scala 375:55]
-    node _T_1767 = and(_T_1766, obuf_rst) @[el2_lsu_bus_buffer.scala 375:89]
-    reg _T_1768 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 375:51]
-    _T_1768 <= _T_1767 @[el2_lsu_bus_buffer.scala 375:51]
+    node _T_1765 = eq(obuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 375:79]
+    node _T_1766 = mux(obuf_wr_en, UInt<1>("h01"), _T_1765) @[el2_lsu_bus_buffer.scala 375:58]
+    node _T_1767 = and(_T_1766, obuf_rst) @[el2_lsu_bus_buffer.scala 375:92]
+    reg _T_1768 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 375:54]
+    _T_1768 <= _T_1767 @[el2_lsu_bus_buffer.scala 375:54]
     obuf_valid <= _T_1768 @[el2_lsu_bus_buffer.scala 375:14]
-    reg _T_1769 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    reg _T_1769 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when obuf_wr_en : @[Reg.scala 28:19]
       _T_1769 <= obuf_nosend_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]

el2_lsu_bus_buffer.v

@@ -379,7 +379,7 @@ module el2_lsu_bus_buffer(
   wire  _T_3994 = _GEN_350 == 3'h3; // @[el2_lsu_bus_buffer.scala 471:104]
   wire  _T_3995 = obuf_merge & _T_3994; // @[el2_lsu_bus_buffer.scala 471:91]
   wire  _T_3996 = _T_3993 | _T_3995; // @[el2_lsu_bus_buffer.scala 471:77]
-  reg  obuf_valid; // @[el2_lsu_bus_buffer.scala 375:51]
+  reg  obuf_valid; // @[el2_lsu_bus_buffer.scala 375:54]
   wire  _T_3997 = _T_3996 & obuf_valid; // @[el2_lsu_bus_buffer.scala 471:135]
   reg  obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 374:55]
   wire  _T_3998 = _T_3997 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 471:148]
@@ -1243,7 +1243,7 @@ module el2_lsu_bus_buffer(
   wire [7:0] _T_1535 = _T_1489 ? obuf_data1_in[55:48] : obuf_data1_in[55:48]; // @[el2_lsu_bus_buffer.scala 364:44]
   wire [7:0] _T_1540 = _T_1493 ? obuf_data1_in[63:56] : obuf_data1_in[63:56]; // @[el2_lsu_bus_buffer.scala 364:44]
   wire [55:0] _T_1546 = {_T_1540,_T_1535,_T_1530,_T_1525,_T_1520,_T_1515,_T_1510}; // @[Cat.scala 29:58]
-  wire  _T_1766 = obuf_wr_en | _T_1157; // @[el2_lsu_bus_buffer.scala 375:55]
+  wire  _T_1766 = obuf_wr_en | _T_1157; // @[el2_lsu_bus_buffer.scala 375:58]
   reg [1:0] obuf_sz; // @[Reg.scala 27:20]
   reg [7:0] obuf_byteen; // @[Reg.scala 27:20]
   reg [63:0] obuf_data; // @[el2_lib.scala 491:16]
@@ -3506,7 +3506,7 @@ end // initial
       end
     end
   end
-  always @(posedge io_lsu_busm_clk or posedge reset) begin
+  always @(posedge io_lsu_free_c2_clk or posedge reset) begin
     if (reset) begin
       obuf_valid <= 1'h0;
     end else begin
@@ -3838,7 +3838,7 @@ end // initial
       obuf_data_done <= _T_1231 & _T_4721;
     end
   end
-  always @(posedge io_lsu_busm_clk or posedge reset) begin
+  always @(posedge io_lsu_free_c2_clk or posedge reset) begin
     if (reset) begin
       obuf_nosend <= 1'h0;
     end else if (obuf_wr_en) begin

src/main/scala/lsu/el2_lsu_bus_buffer.scala

@@ -372,8 +372,8 @@ class  el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
     (ibuf_buf_byp & ldst_samedw_r & io.ldst_dual_r)
 
   val obuf_wr_enQ = withClock(io.lsu_busm_clk){RegNext(obuf_wr_en, false.B)}
-  obuf_valid := withClock(io.lsu_busm_clk){RegNext(Mux(obuf_wr_en, true.B, !obuf_valid) & obuf_rst, false.B)}
-  obuf_nosend := withClock(io.lsu_busm_clk){RegEnable(obuf_nosend_in, false.B, obuf_wr_en)}
+  obuf_valid := withClock(io.lsu_free_c2_clk){RegNext(Mux(obuf_wr_en, true.B, !obuf_valid) & obuf_rst, false.B)}
+  obuf_nosend := withClock(io.lsu_free_c2_clk){RegEnable(obuf_nosend_in, false.B, obuf_wr_en)}
   obuf_cmd_done := withClock(io.lsu_busm_clk){RegNext(obuf_cmd_done_in, false.B)}
   obuf_data_done := withClock(io.lsu_busm_clk){RegNext(obuf_data_done_in, false.B)}
   obuf_rdrsp_pend := withClock(io.lsu_busm_clk){RegNext(obuf_rdrsp_pend_in, false.B)}