From 4328532fdbdb85e372999169fba16bd50a0e1609 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E2=80=8BLaraib=20Khan?= <​laraib.khan@lampromellon.com> Date: Thu, 17 Dec 2020 10:16:07 +0500 Subject: [PATCH] vsrc replaced --- dmi_wrapper.sv | 90 + firrtl_black_box_resource_files.f | 2 +- .../vsrc/gated_latch.v => gated_latch.sv | 6 +- gated_latch.v | 6 +- mem.sv | 16 +- quasar_wrapper.anno.json | 2 +- quasar_wrapper.fir | 4626 +++++++++-------- quasar_wrapper.v | 2158 ++++---- src/main/resources/vsrc/beh_lib.sv | 506 ++ .../resources/vsrc/dmi_jtag_to_core_sync.sv | 64 + src/main/resources/vsrc/dmi_wrapper.sv | 90 + .../main/resources/vsrc/gated_latch.sv | 6 +- src/main/resources/vsrc/ifu_ic_mem.sv | 12 +- src/main/resources/vsrc/lsu_dccm_mem.sv | 2 +- src/main/resources/vsrc/mem.sv | 16 +- src/main/resources/vsrc/mem_lib.sv | 202 + src/main/resources/vsrc/mem_mod.sv | 64 + src/main/resources/vsrc/rvjtag_tap.sv | 223 + src/main/scala/dec/dec_tlu_ctl.scala | 6 +- src/main/scala/lib/lib.scala | 2 +- target/scala-2.12/classes/dec/csr_tlu.class | Bin 216091 -> 215903 bytes .../classes/lib/lib$gated_latch.class | Bin 2045 -> 2046 bytes target/scala-2.12/classes/vsrc/beh_lib.sv | 506 ++ .../classes/vsrc/dmi_jtag_to_core_sync.sv | 64 + target/scala-2.12/classes/vsrc/dmi_wrapper.sv | 90 + target/scala-2.12/classes/vsrc/gated_latch.sv | 14 + target/scala-2.12/classes/vsrc/ifu_ic_mem.sv | 12 +- .../scala-2.12/classes/vsrc/lsu_dccm_mem.sv | 2 +- target/scala-2.12/classes/vsrc/mem.sv | 16 +- target/scala-2.12/classes/vsrc/mem_lib.sv | 202 + target/scala-2.12/classes/vsrc/mem_mod.sv | 64 + target/scala-2.12/classes/vsrc/rvjtag_tap.sv | 223 + 32 files changed, 5859 insertions(+), 3433 deletions(-) rename src/main/resources/vsrc/gated_latch.v => gated_latch.sv (74%) create mode 100644 src/main/resources/vsrc/beh_lib.sv rename target/scala-2.12/classes/vsrc/gated_latch.v => src/main/resources/vsrc/gated_latch.sv (74%) create mode 100644 src/main/resources/vsrc/mem_lib.sv create mode 100644 src/main/resources/vsrc/mem_mod.sv create mode 100644 src/main/resources/vsrc/rvjtag_tap.sv create mode 100644 target/scala-2.12/classes/vsrc/beh_lib.sv create mode 100644 target/scala-2.12/classes/vsrc/gated_latch.sv create mode 100644 target/scala-2.12/classes/vsrc/mem_lib.sv create mode 100644 target/scala-2.12/classes/vsrc/mem_mod.sv create mode 100644 target/scala-2.12/classes/vsrc/rvjtag_tap.sv diff --git a/dmi_wrapper.sv b/dmi_wrapper.sv index e69de29b..d9fd7410 100644 --- a/dmi_wrapper.sv +++ b/dmi_wrapper.sv @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2018 Western Digital Corporation or it's affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//------------------------------------------------------------------------------------ +// +// Copyright Western Digital, 2018 +// Owner : Anusha Narayanamoorthy +// Description: +// Wrapper module for JTAG_TAP and DMI synchronizer +// +//------------------------------------------------------------------------------------- + +module dmi_wrapper( + + // JTAG signals + input trst_n, // JTAG reset + input tck, // JTAG clock + input tms, // Test mode select + input tdi, // Test Data Input + output tdo, // Test Data Output + output tdoEnable, // Test Data Output enable + + // Processor Signals + input core_rst_n, // Core reset + input core_clk, // Core clock + input [31:1] jtag_id, // JTAG ID + input [31:0] rd_data, // 32 bit Read data from Processor + output [31:0] reg_wr_data, // 32 bit Write data to Processor + output [6:0] reg_wr_addr, // 7 bit reg address to Processor + output reg_en, // 1 bit Read enable to Processor + output reg_wr_en, // 1 bit Write enable to Processor + output dmi_hard_reset +); + + + + + + //Wire Declaration + wire rd_en; + wire wr_en; + wire dmireset; + + + //jtag_tap instantiation + rvjtag_tap i_jtag_tap( + .trst(trst_n), // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset + .tck(tck), // dedicated JTAG TCK pad signal + .tms(tms), // dedicated JTAG TMS pad signal + .tdi(tdi), // dedicated JTAG TDI pad signal + .tdo(tdo), // dedicated JTAG TDO pad signal + .tdoEnable(tdoEnable), // enable for TDO pad + .wr_data(reg_wr_data), // 32 bit Write data + .wr_addr(reg_wr_addr), // 7 bit Write address + .rd_en(rd_en), // 1 bit read enable + .wr_en(wr_en), // 1 bit Write enable + .rd_data(rd_data), // 32 bit Read data + .rd_status(2'b0), + .idle(3'h0), // no need to wait to sample data + .dmi_stat(2'b0), // no need to wait or error possible + .version(4'h1), // debug spec 0.13 compliant + .jtag_id(jtag_id), + .dmi_hard_reset(dmi_hard_reset), + .dmi_reset(dmireset) +); + + + // dmi_jtag_to_core_sync instantiation + dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync( + .wr_en(wr_en), // 1 bit Write enable + .rd_en(rd_en), // 1 bit Read enable + + .rst_n(core_rst_n), + .clk(core_clk), + .reg_en(reg_en), // 1 bit Write interface bit + .reg_wr_en(reg_wr_en) // 1 bit Write enable + ); + +endmodule diff --git a/firrtl_black_box_resource_files.f b/firrtl_black_box_resource_files.f index 5646ae13..89983276 100644 --- a/firrtl_black_box_resource_files.f +++ b/firrtl_black_box_resource_files.f @@ -1,3 +1,3 @@ -/home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.v +/home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.sv /home/laraibkhan/Desktop/SweRV-Chislified/dmi_wrapper.sv /home/laraibkhan/Desktop/SweRV-Chislified/mem.sv \ No newline at end of file diff --git a/src/main/resources/vsrc/gated_latch.v b/gated_latch.sv similarity index 74% rename from src/main/resources/vsrc/gated_latch.v rename to gated_latch.sv index 36570337..51b96c9d 100644 --- a/src/main/resources/vsrc/gated_latch.v +++ b/gated_latch.sv @@ -1,10 +1,10 @@ module gated_latch ( - input wire SE, EN, CK, + input logic SE, EN, CK, output Q ); - reg en_ff; - wire enable; + logic en_ff; + logic enable; assign enable = EN | SE; always @(CK, enable) begin if(!CK) diff --git a/gated_latch.v b/gated_latch.v index 36570337..51b96c9d 100644 --- a/gated_latch.v +++ b/gated_latch.v @@ -1,10 +1,10 @@ module gated_latch ( - input wire SE, EN, CK, + input logic SE, EN, CK, output Q ); - reg en_ff; - wire enable; + logic en_ff; + logic enable; assign enable = EN | SE; always @(CK, enable) begin if(!CK) diff --git a/mem.sv b/mem.sv index 56e9fe57..0aee1897 100644 --- a/mem.sv +++ b/mem.sv @@ -15,14 +15,14 @@ module mem #( parameter DCCM_NUM_BANKS, parameter ICACHE_BANK_HI, parameter ICACHE_BANK_LO, - parameter DCCM_ENABLE, + parameter DCCM_ENABLE= 'b1, parameter ICACHE_TAG_LO, parameter ICACHE_DATA_INDEX_LO, parameter ICCM_NUM_BANKS, parameter ICACHE_ECC, - parameter ICACHE_ENABLE, + parameter ICACHE_ENABLE= 'b1, parameter DCCM_BANK_BITS, - parameter ICCM_ENABLE, + parameter ICCM_ENABLE= 'b1, parameter ICCM_BANK_BITS, parameter ICACHE_TAG_DEPTH, parameter ICACHE_WAYPACK, @@ -77,8 +77,9 @@ module mem #( input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache. input logic ic_sel_premux_data, // Premux data sel - input logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC - input logic [70:0] ic_debug_wr_data, // Debug wr cache. + input logic [70:0] ic_wr_data_0, // Data to fill to the Icache. With ECC + input logic [70:0] ic_wr_data_1, + input logic [70:0] ic_debug_wr_data, // Debug wr cache. output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC input logic [ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache. input logic ic_debug_rd_en, // Icache debug rd @@ -100,6 +101,9 @@ module mem #( ); + logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data; +assign ic_wr_data [0] = ic_wr_data_0; +assign ic_wr_data [1] = ic_wr_data_1; // DCCM Instantiation if (DCCM_ENABLE == 1) begin: Gen_dccm_enable lsu_dccm_mem #( @@ -142,7 +146,7 @@ else begin assign ic_rd_hit[ICACHE_NUM_WAYS-1:0] = '0; assign ic_tag_perr = '0 ; assign ic_rd_data = '0 ; - assign ic_stag_debug_rd_data = '0 ; + assign ic_tag_debug_rd_data = '0 ; end // else: !if( ICACHE_ENABLE ) diff --git a/quasar_wrapper.anno.json b/quasar_wrapper.anno.json index 50a67c3d..afde105e 100644 --- a/quasar_wrapper.anno.json +++ b/quasar_wrapper.anno.json @@ -6,7 +6,7 @@ { "class":"firrtl.transforms.BlackBoxResourceAnno", "target":"quasar_wrapper.gated_latch", - "resourceId":"/vsrc/gated_latch.v" + "resourceId":"/vsrc/gated_latch.sv" }, { "class":"firrtl.transforms.DontTouchAnnotation", diff --git a/quasar_wrapper.fir b/quasar_wrapper.fir index 532e2e0c..c652dec9 100644 --- a/quasar_wrapper.fir +++ b/quasar_wrapper.fir @@ -73418,974 +73418,982 @@ circuit quasar_wrapper : reg _T_339 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_339 <= mfdc_ns @[lib.scala 374:16] mfdc_int <= _T_339 @[dec_tlu_ctl.scala 1747:11] - node _T_340 = bits(io.dec_csr_wrdata_r, 18, 16) @[dec_tlu_ctl.scala 1756:39] - node _T_341 = not(_T_340) @[dec_tlu_ctl.scala 1756:19] - node _T_342 = bits(io.dec_csr_wrdata_r, 11, 0) @[dec_tlu_ctl.scala 1756:66] - node _T_343 = cat(_T_341, _T_342) @[Cat.scala 29:58] - mfdc_ns <= _T_343 @[dec_tlu_ctl.scala 1756:12] - node _T_344 = bits(mfdc_int, 14, 12) @[dec_tlu_ctl.scala 1757:28] - node _T_345 = not(_T_344) @[dec_tlu_ctl.scala 1757:19] - node _T_346 = bits(mfdc_int, 11, 0) @[dec_tlu_ctl.scala 1757:54] - node _T_347 = cat(_T_345, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_340 = bits(io.dec_csr_wrdata_r, 18, 16) @[dec_tlu_ctl.scala 1752:40] + node _T_341 = not(_T_340) @[dec_tlu_ctl.scala 1752:20] + node _T_342 = bits(io.dec_csr_wrdata_r, 11, 7) @[dec_tlu_ctl.scala 1752:67] + node _T_343 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1752:95] + node _T_344 = not(_T_343) @[dec_tlu_ctl.scala 1752:75] + node _T_345 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1752:119] + node _T_346 = cat(_T_344, _T_345) @[Cat.scala 29:58] + node _T_347 = cat(_T_341, _T_342) @[Cat.scala 29:58] node _T_348 = cat(_T_347, _T_346) @[Cat.scala 29:58] - mfdc <= _T_348 @[dec_tlu_ctl.scala 1757:12] - node _T_349 = bits(mfdc, 18, 16) @[dec_tlu_ctl.scala 1761:46] - io.dec_tlu_dma_qos_prty <= _T_349 @[dec_tlu_ctl.scala 1761:39] - node _T_350 = bits(mfdc, 11, 11) @[dec_tlu_ctl.scala 1762:46] - io.dec_tlu_external_ldfwd_disable <= _T_350 @[dec_tlu_ctl.scala 1762:39] - node _T_351 = bits(mfdc, 8, 8) @[dec_tlu_ctl.scala 1763:46] - io.dec_tlu_core_ecc_disable <= _T_351 @[dec_tlu_ctl.scala 1763:39] - node _T_352 = bits(mfdc, 6, 6) @[dec_tlu_ctl.scala 1764:46] - io.dec_tlu_sideeffect_posted_disable <= _T_352 @[dec_tlu_ctl.scala 1764:39] - node _T_353 = bits(mfdc, 3, 3) @[dec_tlu_ctl.scala 1765:46] - io.dec_tlu_bpred_disable <= _T_353 @[dec_tlu_ctl.scala 1765:39] - node _T_354 = bits(mfdc, 2, 2) @[dec_tlu_ctl.scala 1766:46] - io.dec_tlu_wb_coalescing_disable <= _T_354 @[dec_tlu_ctl.scala 1766:39] - node _T_355 = bits(mfdc, 0, 0) @[dec_tlu_ctl.scala 1767:46] - io.dec_tlu_pipelining_disable <= _T_355 @[dec_tlu_ctl.scala 1767:39] - node _T_356 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1776:70] - node _T_357 = eq(_T_356, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 1776:77] - node _T_358 = and(io.dec_csr_wen_r_mod, _T_357) @[dec_tlu_ctl.scala 1776:48] - node _T_359 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1776:89] - node _T_360 = and(_T_358, _T_359) @[dec_tlu_ctl.scala 1776:87] - node _T_361 = not(io.take_ext_int_start) @[dec_tlu_ctl.scala 1776:113] - node _T_362 = and(_T_360, _T_361) @[dec_tlu_ctl.scala 1776:111] - io.dec_tlu_wr_pause_r <= _T_362 @[dec_tlu_ctl.scala 1776:24] - node _T_363 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1783:61] - node _T_364 = eq(_T_363, UInt<12>("h07c0")) @[dec_tlu_ctl.scala 1783:68] - node wr_mrac_r = and(io.dec_csr_wen_r_mod, _T_364) @[dec_tlu_ctl.scala 1783:39] - node _T_365 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1786:39] - node _T_366 = bits(io.dec_csr_wrdata_r, 30, 30) @[dec_tlu_ctl.scala 1786:64] - node _T_367 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1786:91] - node _T_368 = not(_T_367) @[dec_tlu_ctl.scala 1786:71] - node _T_369 = and(_T_366, _T_368) @[dec_tlu_ctl.scala 1786:69] - node _T_370 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1787:41] - node _T_371 = bits(io.dec_csr_wrdata_r, 28, 28) @[dec_tlu_ctl.scala 1787:66] - node _T_372 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1787:93] - node _T_373 = not(_T_372) @[dec_tlu_ctl.scala 1787:73] - node _T_374 = and(_T_371, _T_373) @[dec_tlu_ctl.scala 1787:71] - node _T_375 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1788:41] - node _T_376 = bits(io.dec_csr_wrdata_r, 26, 26) @[dec_tlu_ctl.scala 1788:66] - node _T_377 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1788:93] - node _T_378 = not(_T_377) @[dec_tlu_ctl.scala 1788:73] - node _T_379 = and(_T_376, _T_378) @[dec_tlu_ctl.scala 1788:71] - node _T_380 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1789:41] - node _T_381 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 1789:66] - node _T_382 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1789:93] - node _T_383 = not(_T_382) @[dec_tlu_ctl.scala 1789:73] - node _T_384 = and(_T_381, _T_383) @[dec_tlu_ctl.scala 1789:71] - node _T_385 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1790:41] - node _T_386 = bits(io.dec_csr_wrdata_r, 22, 22) @[dec_tlu_ctl.scala 1790:66] - node _T_387 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1790:93] - node _T_388 = not(_T_387) @[dec_tlu_ctl.scala 1790:73] - node _T_389 = and(_T_386, _T_388) @[dec_tlu_ctl.scala 1790:71] - node _T_390 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1791:41] - node _T_391 = bits(io.dec_csr_wrdata_r, 20, 20) @[dec_tlu_ctl.scala 1791:66] - node _T_392 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1791:93] - node _T_393 = not(_T_392) @[dec_tlu_ctl.scala 1791:73] - node _T_394 = and(_T_391, _T_393) @[dec_tlu_ctl.scala 1791:71] - node _T_395 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1792:41] - node _T_396 = bits(io.dec_csr_wrdata_r, 18, 18) @[dec_tlu_ctl.scala 1792:66] - node _T_397 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1792:93] - node _T_398 = not(_T_397) @[dec_tlu_ctl.scala 1792:73] - node _T_399 = and(_T_396, _T_398) @[dec_tlu_ctl.scala 1792:71] - node _T_400 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1793:41] - node _T_401 = bits(io.dec_csr_wrdata_r, 16, 16) @[dec_tlu_ctl.scala 1793:66] - node _T_402 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1793:93] - node _T_403 = not(_T_402) @[dec_tlu_ctl.scala 1793:73] - node _T_404 = and(_T_401, _T_403) @[dec_tlu_ctl.scala 1793:71] - node _T_405 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1794:41] - node _T_406 = bits(io.dec_csr_wrdata_r, 14, 14) @[dec_tlu_ctl.scala 1794:66] - node _T_407 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1794:93] - node _T_408 = not(_T_407) @[dec_tlu_ctl.scala 1794:73] - node _T_409 = and(_T_406, _T_408) @[dec_tlu_ctl.scala 1794:71] - node _T_410 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1795:41] - node _T_411 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 1795:66] - node _T_412 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1795:93] - node _T_413 = not(_T_412) @[dec_tlu_ctl.scala 1795:73] - node _T_414 = and(_T_411, _T_413) @[dec_tlu_ctl.scala 1795:71] - node _T_415 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1796:41] - node _T_416 = bits(io.dec_csr_wrdata_r, 10, 10) @[dec_tlu_ctl.scala 1796:66] - node _T_417 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1796:93] - node _T_418 = not(_T_417) @[dec_tlu_ctl.scala 1796:73] - node _T_419 = and(_T_416, _T_418) @[dec_tlu_ctl.scala 1796:71] - node _T_420 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1797:41] - node _T_421 = bits(io.dec_csr_wrdata_r, 8, 8) @[dec_tlu_ctl.scala 1797:66] - node _T_422 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1797:93] - node _T_423 = not(_T_422) @[dec_tlu_ctl.scala 1797:73] - node _T_424 = and(_T_421, _T_423) @[dec_tlu_ctl.scala 1797:70] - node _T_425 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1798:41] - node _T_426 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1798:66] - node _T_427 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1798:93] - node _T_428 = not(_T_427) @[dec_tlu_ctl.scala 1798:73] - node _T_429 = and(_T_426, _T_428) @[dec_tlu_ctl.scala 1798:70] - node _T_430 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1799:41] - node _T_431 = bits(io.dec_csr_wrdata_r, 4, 4) @[dec_tlu_ctl.scala 1799:66] - node _T_432 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1799:93] - node _T_433 = not(_T_432) @[dec_tlu_ctl.scala 1799:73] - node _T_434 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 1799:70] - node _T_435 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1800:41] - node _T_436 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 1800:66] - node _T_437 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1800:93] - node _T_438 = not(_T_437) @[dec_tlu_ctl.scala 1800:73] - node _T_439 = and(_T_436, _T_438) @[dec_tlu_ctl.scala 1800:70] - node _T_440 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1801:41] - node _T_441 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1801:66] - node _T_442 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1801:93] - node _T_443 = not(_T_442) @[dec_tlu_ctl.scala 1801:73] - node _T_444 = and(_T_441, _T_443) @[dec_tlu_ctl.scala 1801:70] - node _T_445 = cat(_T_440, _T_444) @[Cat.scala 29:58] - node _T_446 = cat(_T_435, _T_439) @[Cat.scala 29:58] - node _T_447 = cat(_T_446, _T_445) @[Cat.scala 29:58] - node _T_448 = cat(_T_430, _T_434) @[Cat.scala 29:58] - node _T_449 = cat(_T_425, _T_429) @[Cat.scala 29:58] - node _T_450 = cat(_T_449, _T_448) @[Cat.scala 29:58] - node _T_451 = cat(_T_450, _T_447) @[Cat.scala 29:58] - node _T_452 = cat(_T_420, _T_424) @[Cat.scala 29:58] - node _T_453 = cat(_T_415, _T_419) @[Cat.scala 29:58] - node _T_454 = cat(_T_453, _T_452) @[Cat.scala 29:58] - node _T_455 = cat(_T_410, _T_414) @[Cat.scala 29:58] - node _T_456 = cat(_T_405, _T_409) @[Cat.scala 29:58] + mfdc_ns <= _T_348 @[dec_tlu_ctl.scala 1752:13] + node _T_349 = bits(mfdc_int, 14, 12) @[dec_tlu_ctl.scala 1753:29] + node _T_350 = not(_T_349) @[dec_tlu_ctl.scala 1753:20] + node _T_351 = bits(mfdc_int, 11, 7) @[dec_tlu_ctl.scala 1753:55] + node _T_352 = bits(mfdc_int, 6, 6) @[dec_tlu_ctl.scala 1753:72] + node _T_353 = not(_T_352) @[dec_tlu_ctl.scala 1753:63] + node _T_354 = bits(mfdc_int, 5, 0) @[dec_tlu_ctl.scala 1753:85] + node _T_355 = cat(_T_353, _T_354) @[Cat.scala 29:58] + node _T_356 = cat(_T_350, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_357 = cat(_T_356, _T_351) @[Cat.scala 29:58] + node _T_358 = cat(_T_357, _T_355) @[Cat.scala 29:58] + mfdc <= _T_358 @[dec_tlu_ctl.scala 1753:13] + node _T_359 = bits(mfdc, 18, 16) @[dec_tlu_ctl.scala 1761:46] + io.dec_tlu_dma_qos_prty <= _T_359 @[dec_tlu_ctl.scala 1761:39] + node _T_360 = bits(mfdc, 11, 11) @[dec_tlu_ctl.scala 1762:46] + io.dec_tlu_external_ldfwd_disable <= _T_360 @[dec_tlu_ctl.scala 1762:39] + node _T_361 = bits(mfdc, 8, 8) @[dec_tlu_ctl.scala 1763:46] + io.dec_tlu_core_ecc_disable <= _T_361 @[dec_tlu_ctl.scala 1763:39] + node _T_362 = bits(mfdc, 6, 6) @[dec_tlu_ctl.scala 1764:46] + io.dec_tlu_sideeffect_posted_disable <= _T_362 @[dec_tlu_ctl.scala 1764:39] + node _T_363 = bits(mfdc, 3, 3) @[dec_tlu_ctl.scala 1765:46] + io.dec_tlu_bpred_disable <= _T_363 @[dec_tlu_ctl.scala 1765:39] + node _T_364 = bits(mfdc, 2, 2) @[dec_tlu_ctl.scala 1766:46] + io.dec_tlu_wb_coalescing_disable <= _T_364 @[dec_tlu_ctl.scala 1766:39] + node _T_365 = bits(mfdc, 0, 0) @[dec_tlu_ctl.scala 1767:46] + io.dec_tlu_pipelining_disable <= _T_365 @[dec_tlu_ctl.scala 1767:39] + node _T_366 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1776:70] + node _T_367 = eq(_T_366, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 1776:77] + node _T_368 = and(io.dec_csr_wen_r_mod, _T_367) @[dec_tlu_ctl.scala 1776:48] + node _T_369 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1776:89] + node _T_370 = and(_T_368, _T_369) @[dec_tlu_ctl.scala 1776:87] + node _T_371 = not(io.take_ext_int_start) @[dec_tlu_ctl.scala 1776:113] + node _T_372 = and(_T_370, _T_371) @[dec_tlu_ctl.scala 1776:111] + io.dec_tlu_wr_pause_r <= _T_372 @[dec_tlu_ctl.scala 1776:24] + node _T_373 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1783:61] + node _T_374 = eq(_T_373, UInt<12>("h07c0")) @[dec_tlu_ctl.scala 1783:68] + node wr_mrac_r = and(io.dec_csr_wen_r_mod, _T_374) @[dec_tlu_ctl.scala 1783:39] + node _T_375 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1786:39] + node _T_376 = bits(io.dec_csr_wrdata_r, 30, 30) @[dec_tlu_ctl.scala 1786:64] + node _T_377 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1786:91] + node _T_378 = not(_T_377) @[dec_tlu_ctl.scala 1786:71] + node _T_379 = and(_T_376, _T_378) @[dec_tlu_ctl.scala 1786:69] + node _T_380 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1787:41] + node _T_381 = bits(io.dec_csr_wrdata_r, 28, 28) @[dec_tlu_ctl.scala 1787:66] + node _T_382 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1787:93] + node _T_383 = not(_T_382) @[dec_tlu_ctl.scala 1787:73] + node _T_384 = and(_T_381, _T_383) @[dec_tlu_ctl.scala 1787:71] + node _T_385 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1788:41] + node _T_386 = bits(io.dec_csr_wrdata_r, 26, 26) @[dec_tlu_ctl.scala 1788:66] + node _T_387 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1788:93] + node _T_388 = not(_T_387) @[dec_tlu_ctl.scala 1788:73] + node _T_389 = and(_T_386, _T_388) @[dec_tlu_ctl.scala 1788:71] + node _T_390 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1789:41] + node _T_391 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 1789:66] + node _T_392 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1789:93] + node _T_393 = not(_T_392) @[dec_tlu_ctl.scala 1789:73] + node _T_394 = and(_T_391, _T_393) @[dec_tlu_ctl.scala 1789:71] + node _T_395 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1790:41] + node _T_396 = bits(io.dec_csr_wrdata_r, 22, 22) @[dec_tlu_ctl.scala 1790:66] + node _T_397 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1790:93] + node _T_398 = not(_T_397) @[dec_tlu_ctl.scala 1790:73] + node _T_399 = and(_T_396, _T_398) @[dec_tlu_ctl.scala 1790:71] + node _T_400 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1791:41] + node _T_401 = bits(io.dec_csr_wrdata_r, 20, 20) @[dec_tlu_ctl.scala 1791:66] + node _T_402 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1791:93] + node _T_403 = not(_T_402) @[dec_tlu_ctl.scala 1791:73] + node _T_404 = and(_T_401, _T_403) @[dec_tlu_ctl.scala 1791:71] + node _T_405 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1792:41] + node _T_406 = bits(io.dec_csr_wrdata_r, 18, 18) @[dec_tlu_ctl.scala 1792:66] + node _T_407 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1792:93] + node _T_408 = not(_T_407) @[dec_tlu_ctl.scala 1792:73] + node _T_409 = and(_T_406, _T_408) @[dec_tlu_ctl.scala 1792:71] + node _T_410 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1793:41] + node _T_411 = bits(io.dec_csr_wrdata_r, 16, 16) @[dec_tlu_ctl.scala 1793:66] + node _T_412 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1793:93] + node _T_413 = not(_T_412) @[dec_tlu_ctl.scala 1793:73] + node _T_414 = and(_T_411, _T_413) @[dec_tlu_ctl.scala 1793:71] + node _T_415 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1794:41] + node _T_416 = bits(io.dec_csr_wrdata_r, 14, 14) @[dec_tlu_ctl.scala 1794:66] + node _T_417 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1794:93] + node _T_418 = not(_T_417) @[dec_tlu_ctl.scala 1794:73] + node _T_419 = and(_T_416, _T_418) @[dec_tlu_ctl.scala 1794:71] + node _T_420 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1795:41] + node _T_421 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 1795:66] + node _T_422 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1795:93] + node _T_423 = not(_T_422) @[dec_tlu_ctl.scala 1795:73] + node _T_424 = and(_T_421, _T_423) @[dec_tlu_ctl.scala 1795:71] + node _T_425 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1796:41] + node _T_426 = bits(io.dec_csr_wrdata_r, 10, 10) @[dec_tlu_ctl.scala 1796:66] + node _T_427 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1796:93] + node _T_428 = not(_T_427) @[dec_tlu_ctl.scala 1796:73] + node _T_429 = and(_T_426, _T_428) @[dec_tlu_ctl.scala 1796:71] + node _T_430 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1797:41] + node _T_431 = bits(io.dec_csr_wrdata_r, 8, 8) @[dec_tlu_ctl.scala 1797:66] + node _T_432 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1797:93] + node _T_433 = not(_T_432) @[dec_tlu_ctl.scala 1797:73] + node _T_434 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 1797:70] + node _T_435 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1798:41] + node _T_436 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1798:66] + node _T_437 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1798:93] + node _T_438 = not(_T_437) @[dec_tlu_ctl.scala 1798:73] + node _T_439 = and(_T_436, _T_438) @[dec_tlu_ctl.scala 1798:70] + node _T_440 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1799:41] + node _T_441 = bits(io.dec_csr_wrdata_r, 4, 4) @[dec_tlu_ctl.scala 1799:66] + node _T_442 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1799:93] + node _T_443 = not(_T_442) @[dec_tlu_ctl.scala 1799:73] + node _T_444 = and(_T_441, _T_443) @[dec_tlu_ctl.scala 1799:70] + node _T_445 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1800:41] + node _T_446 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 1800:66] + node _T_447 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1800:93] + node _T_448 = not(_T_447) @[dec_tlu_ctl.scala 1800:73] + node _T_449 = and(_T_446, _T_448) @[dec_tlu_ctl.scala 1800:70] + node _T_450 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1801:41] + node _T_451 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1801:66] + node _T_452 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1801:93] + node _T_453 = not(_T_452) @[dec_tlu_ctl.scala 1801:73] + node _T_454 = and(_T_451, _T_453) @[dec_tlu_ctl.scala 1801:70] + node _T_455 = cat(_T_450, _T_454) @[Cat.scala 29:58] + node _T_456 = cat(_T_445, _T_449) @[Cat.scala 29:58] node _T_457 = cat(_T_456, _T_455) @[Cat.scala 29:58] - node _T_458 = cat(_T_457, _T_454) @[Cat.scala 29:58] - node _T_459 = cat(_T_458, _T_451) @[Cat.scala 29:58] - node _T_460 = cat(_T_400, _T_404) @[Cat.scala 29:58] - node _T_461 = cat(_T_395, _T_399) @[Cat.scala 29:58] - node _T_462 = cat(_T_461, _T_460) @[Cat.scala 29:58] - node _T_463 = cat(_T_390, _T_394) @[Cat.scala 29:58] - node _T_464 = cat(_T_385, _T_389) @[Cat.scala 29:58] - node _T_465 = cat(_T_464, _T_463) @[Cat.scala 29:58] - node _T_466 = cat(_T_465, _T_462) @[Cat.scala 29:58] - node _T_467 = cat(_T_380, _T_384) @[Cat.scala 29:58] - node _T_468 = cat(_T_375, _T_379) @[Cat.scala 29:58] - node _T_469 = cat(_T_468, _T_467) @[Cat.scala 29:58] - node _T_470 = cat(_T_370, _T_374) @[Cat.scala 29:58] - node _T_471 = cat(_T_365, _T_369) @[Cat.scala 29:58] + node _T_458 = cat(_T_440, _T_444) @[Cat.scala 29:58] + node _T_459 = cat(_T_435, _T_439) @[Cat.scala 29:58] + node _T_460 = cat(_T_459, _T_458) @[Cat.scala 29:58] + node _T_461 = cat(_T_460, _T_457) @[Cat.scala 29:58] + node _T_462 = cat(_T_430, _T_434) @[Cat.scala 29:58] + node _T_463 = cat(_T_425, _T_429) @[Cat.scala 29:58] + node _T_464 = cat(_T_463, _T_462) @[Cat.scala 29:58] + node _T_465 = cat(_T_420, _T_424) @[Cat.scala 29:58] + node _T_466 = cat(_T_415, _T_419) @[Cat.scala 29:58] + node _T_467 = cat(_T_466, _T_465) @[Cat.scala 29:58] + node _T_468 = cat(_T_467, _T_464) @[Cat.scala 29:58] + node _T_469 = cat(_T_468, _T_461) @[Cat.scala 29:58] + node _T_470 = cat(_T_410, _T_414) @[Cat.scala 29:58] + node _T_471 = cat(_T_405, _T_409) @[Cat.scala 29:58] node _T_472 = cat(_T_471, _T_470) @[Cat.scala 29:58] - node _T_473 = cat(_T_472, _T_469) @[Cat.scala 29:58] - node _T_474 = cat(_T_473, _T_466) @[Cat.scala 29:58] - node mrac_in = cat(_T_474, _T_459) @[Cat.scala 29:58] - node _T_475 = bits(wr_mrac_r, 0, 0) @[dec_tlu_ctl.scala 1804:38] + node _T_473 = cat(_T_400, _T_404) @[Cat.scala 29:58] + node _T_474 = cat(_T_395, _T_399) @[Cat.scala 29:58] + node _T_475 = cat(_T_474, _T_473) @[Cat.scala 29:58] + node _T_476 = cat(_T_475, _T_472) @[Cat.scala 29:58] + node _T_477 = cat(_T_390, _T_394) @[Cat.scala 29:58] + node _T_478 = cat(_T_385, _T_389) @[Cat.scala 29:58] + node _T_479 = cat(_T_478, _T_477) @[Cat.scala 29:58] + node _T_480 = cat(_T_380, _T_384) @[Cat.scala 29:58] + node _T_481 = cat(_T_375, _T_379) @[Cat.scala 29:58] + node _T_482 = cat(_T_481, _T_480) @[Cat.scala 29:58] + node _T_483 = cat(_T_482, _T_479) @[Cat.scala 29:58] + node _T_484 = cat(_T_483, _T_476) @[Cat.scala 29:58] + node mrac_in = cat(_T_484, _T_469) @[Cat.scala 29:58] + node _T_485 = bits(wr_mrac_r, 0, 0) @[dec_tlu_ctl.scala 1804:38] inst rvclkhdr_10 of rvclkhdr_730 @[lib.scala 368:23] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset rvclkhdr_10.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_10.io.en <= _T_475 @[lib.scala 371:17] + rvclkhdr_10.io.en <= _T_485 @[lib.scala 371:17] rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg mrac : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] mrac <= mrac_in @[lib.scala 374:16] io.dec_tlu_mrac_ff <= mrac @[dec_tlu_ctl.scala 1806:21] - node _T_476 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1814:62] - node _T_477 = eq(_T_476, UInt<12>("h0bc0")) @[dec_tlu_ctl.scala 1814:69] - node wr_mdeau_r = and(io.dec_csr_wen_r_mod, _T_477) @[dec_tlu_ctl.scala 1814:40] - node _T_478 = not(wr_mdeau_r) @[dec_tlu_ctl.scala 1824:59] - node _T_479 = and(io.mdseac_locked_f, _T_478) @[dec_tlu_ctl.scala 1824:57] - node _T_480 = or(mdseac_en, _T_479) @[dec_tlu_ctl.scala 1824:35] - io.mdseac_locked_ns <= _T_480 @[dec_tlu_ctl.scala 1824:22] - node _T_481 = or(io.lsu_imprecise_error_store_any, io.lsu_imprecise_error_load_any) @[dec_tlu_ctl.scala 1826:49] - node _T_482 = not(io.nmi_int_detected_f) @[dec_tlu_ctl.scala 1826:86] - node _T_483 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 1826:84] - node _T_484 = not(io.mdseac_locked_f) @[dec_tlu_ctl.scala 1826:111] - node _T_485 = and(_T_483, _T_484) @[dec_tlu_ctl.scala 1826:109] - mdseac_en <= _T_485 @[dec_tlu_ctl.scala 1826:12] - node _T_486 = bits(mdseac_en, 0, 0) @[dec_tlu_ctl.scala 1828:64] + node _T_486 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1814:62] + node _T_487 = eq(_T_486, UInt<12>("h0bc0")) @[dec_tlu_ctl.scala 1814:69] + node wr_mdeau_r = and(io.dec_csr_wen_r_mod, _T_487) @[dec_tlu_ctl.scala 1814:40] + node _T_488 = not(wr_mdeau_r) @[dec_tlu_ctl.scala 1824:59] + node _T_489 = and(io.mdseac_locked_f, _T_488) @[dec_tlu_ctl.scala 1824:57] + node _T_490 = or(mdseac_en, _T_489) @[dec_tlu_ctl.scala 1824:35] + io.mdseac_locked_ns <= _T_490 @[dec_tlu_ctl.scala 1824:22] + node _T_491 = or(io.lsu_imprecise_error_store_any, io.lsu_imprecise_error_load_any) @[dec_tlu_ctl.scala 1826:49] + node _T_492 = not(io.nmi_int_detected_f) @[dec_tlu_ctl.scala 1826:86] + node _T_493 = and(_T_491, _T_492) @[dec_tlu_ctl.scala 1826:84] + node _T_494 = not(io.mdseac_locked_f) @[dec_tlu_ctl.scala 1826:111] + node _T_495 = and(_T_493, _T_494) @[dec_tlu_ctl.scala 1826:109] + mdseac_en <= _T_495 @[dec_tlu_ctl.scala 1826:12] + node _T_496 = bits(mdseac_en, 0, 0) @[dec_tlu_ctl.scala 1828:64] inst rvclkhdr_11 of rvclkhdr_731 @[lib.scala 368:23] rvclkhdr_11.clock <= clock rvclkhdr_11.reset <= reset rvclkhdr_11.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_11.io.en <= _T_486 @[lib.scala 371:17] + rvclkhdr_11.io.en <= _T_496 @[lib.scala 371:17] rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg mdseac : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] mdseac <= io.lsu_imprecise_error_addr_any @[lib.scala 374:16] - node _T_487 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1837:61] - node _T_488 = eq(_T_487, UInt<12>("h07c6")) @[dec_tlu_ctl.scala 1837:68] - node wr_mpmc_r = and(io.dec_csr_wen_r_mod, _T_488) @[dec_tlu_ctl.scala 1837:39] - node _T_489 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1841:51] - node _T_490 = and(wr_mpmc_r, _T_489) @[dec_tlu_ctl.scala 1841:30] - node _T_491 = not(io.internal_dbg_halt_mode_f2) @[dec_tlu_ctl.scala 1841:57] - node _T_492 = and(_T_490, _T_491) @[dec_tlu_ctl.scala 1841:55] - node _T_493 = not(io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 1841:89] - node _T_494 = and(_T_492, _T_493) @[dec_tlu_ctl.scala 1841:87] - io.fw_halt_req <= _T_494 @[dec_tlu_ctl.scala 1841:17] + node _T_497 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1837:61] + node _T_498 = eq(_T_497, UInt<12>("h07c6")) @[dec_tlu_ctl.scala 1837:68] + node wr_mpmc_r = and(io.dec_csr_wen_r_mod, _T_498) @[dec_tlu_ctl.scala 1837:39] + node _T_499 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1841:51] + node _T_500 = and(wr_mpmc_r, _T_499) @[dec_tlu_ctl.scala 1841:30] + node _T_501 = not(io.internal_dbg_halt_mode_f2) @[dec_tlu_ctl.scala 1841:57] + node _T_502 = and(_T_500, _T_501) @[dec_tlu_ctl.scala 1841:55] + node _T_503 = not(io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 1841:89] + node _T_504 = and(_T_502, _T_503) @[dec_tlu_ctl.scala 1841:87] + io.fw_halt_req <= _T_504 @[dec_tlu_ctl.scala 1841:17] wire fw_halted_ns : UInt<1> fw_halted_ns <= UInt<1>("h00") reg fw_halted : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1843:48] fw_halted <= fw_halted_ns @[dec_tlu_ctl.scala 1843:48] - node _T_495 = or(io.fw_halt_req, fw_halted) @[dec_tlu_ctl.scala 1844:34] - node _T_496 = not(set_mie_pmu_fw_halt) @[dec_tlu_ctl.scala 1844:49] - node _T_497 = and(_T_495, _T_496) @[dec_tlu_ctl.scala 1844:47] - fw_halted_ns <= _T_497 @[dec_tlu_ctl.scala 1844:15] - node _T_498 = bits(wr_mpmc_r, 0, 0) @[dec_tlu_ctl.scala 1845:29] - node _T_499 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1845:57] - node _T_500 = not(_T_499) @[dec_tlu_ctl.scala 1845:37] - node _T_501 = not(mpmc) @[dec_tlu_ctl.scala 1845:62] - node _T_502 = mux(_T_498, _T_500, _T_501) @[dec_tlu_ctl.scala 1845:18] - mpmc_b_ns <= _T_502 @[dec_tlu_ctl.scala 1845:12] - reg _T_503 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1847:44] - _T_503 <= mpmc_b_ns @[dec_tlu_ctl.scala 1847:44] - mpmc_b <= _T_503 @[dec_tlu_ctl.scala 1847:9] - node _T_504 = not(mpmc_b) @[dec_tlu_ctl.scala 1850:10] - mpmc <= _T_504 @[dec_tlu_ctl.scala 1850:7] - node _T_505 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1859:40] - node _T_506 = gt(_T_505, UInt<5>("h01a")) @[dec_tlu_ctl.scala 1859:48] - node _T_507 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1859:92] - node csr_sat = mux(_T_506, UInt<5>("h01a"), _T_507) @[dec_tlu_ctl.scala 1859:19] - node _T_508 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1861:63] - node _T_509 = eq(_T_508, UInt<12>("h07f0")) @[dec_tlu_ctl.scala 1861:70] - node wr_micect_r = and(io.dec_csr_wen_r_mod, _T_509) @[dec_tlu_ctl.scala 1861:41] - node _T_510 = cat(UInt<26>("h00"), io.ic_perr_r_d1) @[Cat.scala 29:58] - node _T_511 = add(micect, _T_510) @[dec_tlu_ctl.scala 1862:23] - node _T_512 = tail(_T_511, 1) @[dec_tlu_ctl.scala 1862:23] - micect_inc <= _T_512 @[dec_tlu_ctl.scala 1862:13] - node _T_513 = bits(wr_micect_r, 0, 0) @[dec_tlu_ctl.scala 1863:35] - node _T_514 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1863:75] - node _T_515 = cat(csr_sat, _T_514) @[Cat.scala 29:58] - node _T_516 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1863:95] - node _T_517 = cat(_T_516, micect_inc) @[Cat.scala 29:58] - node micect_ns = mux(_T_513, _T_515, _T_517) @[dec_tlu_ctl.scala 1863:22] - node _T_518 = or(wr_micect_r, io.ic_perr_r_d1) @[dec_tlu_ctl.scala 1865:42] - node _T_519 = bits(_T_518, 0, 0) @[dec_tlu_ctl.scala 1865:61] + node _T_505 = or(io.fw_halt_req, fw_halted) @[dec_tlu_ctl.scala 1844:34] + node _T_506 = not(set_mie_pmu_fw_halt) @[dec_tlu_ctl.scala 1844:49] + node _T_507 = and(_T_505, _T_506) @[dec_tlu_ctl.scala 1844:47] + fw_halted_ns <= _T_507 @[dec_tlu_ctl.scala 1844:15] + node _T_508 = bits(wr_mpmc_r, 0, 0) @[dec_tlu_ctl.scala 1845:29] + node _T_509 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1845:57] + node _T_510 = not(_T_509) @[dec_tlu_ctl.scala 1845:37] + node _T_511 = not(mpmc) @[dec_tlu_ctl.scala 1845:62] + node _T_512 = mux(_T_508, _T_510, _T_511) @[dec_tlu_ctl.scala 1845:18] + mpmc_b_ns <= _T_512 @[dec_tlu_ctl.scala 1845:12] + reg _T_513 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1847:44] + _T_513 <= mpmc_b_ns @[dec_tlu_ctl.scala 1847:44] + mpmc_b <= _T_513 @[dec_tlu_ctl.scala 1847:9] + node _T_514 = not(mpmc_b) @[dec_tlu_ctl.scala 1850:10] + mpmc <= _T_514 @[dec_tlu_ctl.scala 1850:7] + node _T_515 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1859:40] + node _T_516 = gt(_T_515, UInt<5>("h01a")) @[dec_tlu_ctl.scala 1859:48] + node _T_517 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1859:92] + node csr_sat = mux(_T_516, UInt<5>("h01a"), _T_517) @[dec_tlu_ctl.scala 1859:19] + node _T_518 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1861:63] + node _T_519 = eq(_T_518, UInt<12>("h07f0")) @[dec_tlu_ctl.scala 1861:70] + node wr_micect_r = and(io.dec_csr_wen_r_mod, _T_519) @[dec_tlu_ctl.scala 1861:41] + node _T_520 = cat(UInt<26>("h00"), io.ic_perr_r_d1) @[Cat.scala 29:58] + node _T_521 = add(micect, _T_520) @[dec_tlu_ctl.scala 1862:23] + node _T_522 = tail(_T_521, 1) @[dec_tlu_ctl.scala 1862:23] + micect_inc <= _T_522 @[dec_tlu_ctl.scala 1862:13] + node _T_523 = bits(wr_micect_r, 0, 0) @[dec_tlu_ctl.scala 1863:35] + node _T_524 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1863:75] + node _T_525 = cat(csr_sat, _T_524) @[Cat.scala 29:58] + node _T_526 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1863:95] + node _T_527 = cat(_T_526, micect_inc) @[Cat.scala 29:58] + node micect_ns = mux(_T_523, _T_525, _T_527) @[dec_tlu_ctl.scala 1863:22] + node _T_528 = or(wr_micect_r, io.ic_perr_r_d1) @[dec_tlu_ctl.scala 1865:42] + node _T_529 = bits(_T_528, 0, 0) @[dec_tlu_ctl.scala 1865:61] inst rvclkhdr_12 of rvclkhdr_732 @[lib.scala 368:23] rvclkhdr_12.clock <= clock rvclkhdr_12.reset <= reset rvclkhdr_12.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_12.io.en <= _T_519 @[lib.scala 371:17] + rvclkhdr_12.io.en <= _T_529 @[lib.scala 371:17] rvclkhdr_12.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_520 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_520 <= micect_ns @[lib.scala 374:16] - micect <= _T_520 @[dec_tlu_ctl.scala 1865:9] - node _T_521 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1867:48] - node _T_522 = dshl(UInt<32>("h0ffffffff"), _T_521) @[dec_tlu_ctl.scala 1867:39] - node _T_523 = bits(micect, 26, 0) @[dec_tlu_ctl.scala 1867:79] - node _T_524 = cat(UInt<5>("h00"), _T_523) @[Cat.scala 29:58] - node _T_525 = and(_T_522, _T_524) @[dec_tlu_ctl.scala 1867:57] - node _T_526 = orr(_T_525) @[dec_tlu_ctl.scala 1867:88] - mice_ce_req <= _T_526 @[dec_tlu_ctl.scala 1867:14] - node _T_527 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1876:69] - node _T_528 = eq(_T_527, UInt<12>("h07f1")) @[dec_tlu_ctl.scala 1876:76] - node wr_miccmect_r = and(io.dec_csr_wen_r_mod, _T_528) @[dec_tlu_ctl.scala 1876:47] - node _T_529 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1877:26] - node _T_530 = or(io.iccm_sbecc_r_d1, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1877:70] - node _T_531 = cat(UInt<26>("h00"), _T_530) @[Cat.scala 29:58] - node _T_532 = add(_T_529, _T_531) @[dec_tlu_ctl.scala 1877:33] - node _T_533 = tail(_T_532, 1) @[dec_tlu_ctl.scala 1877:33] - miccmect_inc <= _T_533 @[dec_tlu_ctl.scala 1877:15] - node _T_534 = bits(wr_miccmect_r, 0, 0) @[dec_tlu_ctl.scala 1878:45] - node _T_535 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1878:85] - node _T_536 = cat(csr_sat, _T_535) @[Cat.scala 29:58] - node _T_537 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1878:107] - node _T_538 = cat(_T_537, miccmect_inc) @[Cat.scala 29:58] - node miccmect_ns = mux(_T_534, _T_536, _T_538) @[dec_tlu_ctl.scala 1878:30] - node _T_539 = or(wr_miccmect_r, io.iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 1880:48] - node _T_540 = or(_T_539, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1880:69] - node _T_541 = bits(_T_540, 0, 0) @[dec_tlu_ctl.scala 1880:93] + reg _T_530 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_530 <= micect_ns @[lib.scala 374:16] + micect <= _T_530 @[dec_tlu_ctl.scala 1865:9] + node _T_531 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1867:48] + node _T_532 = dshl(UInt<32>("h0ffffffff"), _T_531) @[dec_tlu_ctl.scala 1867:39] + node _T_533 = bits(micect, 26, 0) @[dec_tlu_ctl.scala 1867:79] + node _T_534 = cat(UInt<5>("h00"), _T_533) @[Cat.scala 29:58] + node _T_535 = and(_T_532, _T_534) @[dec_tlu_ctl.scala 1867:57] + node _T_536 = orr(_T_535) @[dec_tlu_ctl.scala 1867:88] + mice_ce_req <= _T_536 @[dec_tlu_ctl.scala 1867:14] + node _T_537 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1876:69] + node _T_538 = eq(_T_537, UInt<12>("h07f1")) @[dec_tlu_ctl.scala 1876:76] + node wr_miccmect_r = and(io.dec_csr_wen_r_mod, _T_538) @[dec_tlu_ctl.scala 1876:47] + node _T_539 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1877:26] + node _T_540 = or(io.iccm_sbecc_r_d1, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1877:70] + node _T_541 = cat(UInt<26>("h00"), _T_540) @[Cat.scala 29:58] + node _T_542 = add(_T_539, _T_541) @[dec_tlu_ctl.scala 1877:33] + node _T_543 = tail(_T_542, 1) @[dec_tlu_ctl.scala 1877:33] + miccmect_inc <= _T_543 @[dec_tlu_ctl.scala 1877:15] + node _T_544 = bits(wr_miccmect_r, 0, 0) @[dec_tlu_ctl.scala 1878:45] + node _T_545 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1878:85] + node _T_546 = cat(csr_sat, _T_545) @[Cat.scala 29:58] + node _T_547 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1878:107] + node _T_548 = cat(_T_547, miccmect_inc) @[Cat.scala 29:58] + node miccmect_ns = mux(_T_544, _T_546, _T_548) @[dec_tlu_ctl.scala 1878:30] + node _T_549 = or(wr_miccmect_r, io.iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 1880:48] + node _T_550 = or(_T_549, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1880:69] + node _T_551 = bits(_T_550, 0, 0) @[dec_tlu_ctl.scala 1880:93] inst rvclkhdr_13 of rvclkhdr_733 @[lib.scala 368:23] rvclkhdr_13.clock <= clock rvclkhdr_13.reset <= reset rvclkhdr_13.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_13.io.en <= _T_541 @[lib.scala 371:17] + rvclkhdr_13.io.en <= _T_551 @[lib.scala 371:17] rvclkhdr_13.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_542 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_542 <= miccmect_ns @[lib.scala 374:16] - miccmect <= _T_542 @[dec_tlu_ctl.scala 1880:11] - node _T_543 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1882:51] - node _T_544 = dshl(UInt<32>("h0ffffffff"), _T_543) @[dec_tlu_ctl.scala 1882:40] - node _T_545 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1882:84] - node _T_546 = cat(UInt<5>("h00"), _T_545) @[Cat.scala 29:58] - node _T_547 = and(_T_544, _T_546) @[dec_tlu_ctl.scala 1882:60] - node _T_548 = orr(_T_547) @[dec_tlu_ctl.scala 1882:93] - miccme_ce_req <= _T_548 @[dec_tlu_ctl.scala 1882:15] - node _T_549 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1891:69] - node _T_550 = eq(_T_549, UInt<12>("h07f2")) @[dec_tlu_ctl.scala 1891:76] - node wr_mdccmect_r = and(io.dec_csr_wen_r_mod, _T_550) @[dec_tlu_ctl.scala 1891:47] - node _T_551 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1892:26] - node _T_552 = cat(UInt<26>("h00"), io.lsu_single_ecc_error_r_d1) @[Cat.scala 29:58] - node _T_553 = add(_T_551, _T_552) @[dec_tlu_ctl.scala 1892:33] - node _T_554 = tail(_T_553, 1) @[dec_tlu_ctl.scala 1892:33] - mdccmect_inc <= _T_554 @[dec_tlu_ctl.scala 1892:15] - node _T_555 = bits(wr_mdccmect_r, 0, 0) @[dec_tlu_ctl.scala 1893:45] - node _T_556 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1893:85] - node _T_557 = cat(csr_sat, _T_556) @[Cat.scala 29:58] - node _T_558 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1893:107] - node _T_559 = cat(_T_558, mdccmect_inc) @[Cat.scala 29:58] - node mdccmect_ns = mux(_T_555, _T_557, _T_559) @[dec_tlu_ctl.scala 1893:30] - node _T_560 = or(wr_mdccmect_r, io.lsu_single_ecc_error_r_d1) @[dec_tlu_ctl.scala 1895:49] - node _T_561 = bits(_T_560, 0, 0) @[dec_tlu_ctl.scala 1895:81] + reg _T_552 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_552 <= miccmect_ns @[lib.scala 374:16] + miccmect <= _T_552 @[dec_tlu_ctl.scala 1880:11] + node _T_553 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1882:51] + node _T_554 = dshl(UInt<32>("h0ffffffff"), _T_553) @[dec_tlu_ctl.scala 1882:40] + node _T_555 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1882:84] + node _T_556 = cat(UInt<5>("h00"), _T_555) @[Cat.scala 29:58] + node _T_557 = and(_T_554, _T_556) @[dec_tlu_ctl.scala 1882:60] + node _T_558 = orr(_T_557) @[dec_tlu_ctl.scala 1882:93] + miccme_ce_req <= _T_558 @[dec_tlu_ctl.scala 1882:15] + node _T_559 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1891:69] + node _T_560 = eq(_T_559, UInt<12>("h07f2")) @[dec_tlu_ctl.scala 1891:76] + node wr_mdccmect_r = and(io.dec_csr_wen_r_mod, _T_560) @[dec_tlu_ctl.scala 1891:47] + node _T_561 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1892:26] + node _T_562 = cat(UInt<26>("h00"), io.lsu_single_ecc_error_r_d1) @[Cat.scala 29:58] + node _T_563 = add(_T_561, _T_562) @[dec_tlu_ctl.scala 1892:33] + node _T_564 = tail(_T_563, 1) @[dec_tlu_ctl.scala 1892:33] + mdccmect_inc <= _T_564 @[dec_tlu_ctl.scala 1892:15] + node _T_565 = bits(wr_mdccmect_r, 0, 0) @[dec_tlu_ctl.scala 1893:45] + node _T_566 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1893:85] + node _T_567 = cat(csr_sat, _T_566) @[Cat.scala 29:58] + node _T_568 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1893:107] + node _T_569 = cat(_T_568, mdccmect_inc) @[Cat.scala 29:58] + node mdccmect_ns = mux(_T_565, _T_567, _T_569) @[dec_tlu_ctl.scala 1893:30] + node _T_570 = or(wr_mdccmect_r, io.lsu_single_ecc_error_r_d1) @[dec_tlu_ctl.scala 1895:49] + node _T_571 = bits(_T_570, 0, 0) @[dec_tlu_ctl.scala 1895:81] inst rvclkhdr_14 of rvclkhdr_734 @[lib.scala 368:23] rvclkhdr_14.clock <= clock rvclkhdr_14.reset <= reset rvclkhdr_14.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_14.io.en <= _T_561 @[lib.scala 371:17] + rvclkhdr_14.io.en <= _T_571 @[lib.scala 371:17] rvclkhdr_14.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_562 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_562 <= mdccmect_ns @[lib.scala 374:16] - mdccmect <= _T_562 @[dec_tlu_ctl.scala 1895:11] - node _T_563 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1897:52] - node _T_564 = dshl(UInt<32>("h0ffffffff"), _T_563) @[dec_tlu_ctl.scala 1897:41] - node _T_565 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1897:85] - node _T_566 = cat(UInt<5>("h00"), _T_565) @[Cat.scala 29:58] - node _T_567 = and(_T_564, _T_566) @[dec_tlu_ctl.scala 1897:61] - node _T_568 = orr(_T_567) @[dec_tlu_ctl.scala 1897:94] - mdccme_ce_req <= _T_568 @[dec_tlu_ctl.scala 1897:16] - node _T_569 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1907:62] - node _T_570 = eq(_T_569, UInt<12>("h07ce")) @[dec_tlu_ctl.scala 1907:69] - node wr_mfdht_r = and(io.dec_csr_wen_r_mod, _T_570) @[dec_tlu_ctl.scala 1907:40] - node _T_571 = bits(wr_mfdht_r, 0, 0) @[dec_tlu_ctl.scala 1909:32] - node _T_572 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1909:59] - node mfdht_ns = mux(_T_571, _T_572, mfdht) @[dec_tlu_ctl.scala 1909:20] - reg _T_573 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1911:43] - _T_573 <= mfdht_ns @[dec_tlu_ctl.scala 1911:43] - mfdht <= _T_573 @[dec_tlu_ctl.scala 1911:8] - node _T_574 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1920:62] - node _T_575 = eq(_T_574, UInt<12>("h07cf")) @[dec_tlu_ctl.scala 1920:69] - node wr_mfdhs_r = and(io.dec_csr_wen_r_mod, _T_575) @[dec_tlu_ctl.scala 1920:40] - node _T_576 = bits(wr_mfdhs_r, 0, 0) @[dec_tlu_ctl.scala 1922:32] - node _T_577 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 1922:60] - node _T_578 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1923:43] - node _T_579 = and(io.dbg_tlu_halted, _T_578) @[dec_tlu_ctl.scala 1923:41] - node _T_580 = bits(_T_579, 0, 0) @[dec_tlu_ctl.scala 1923:65] - node _T_581 = not(io.lsu_idle_any_f) @[dec_tlu_ctl.scala 1923:78] - node _T_582 = not(io.ifu_miss_state_idle_f) @[dec_tlu_ctl.scala 1923:98] - node _T_583 = cat(_T_581, _T_582) @[Cat.scala 29:58] - node _T_584 = mux(_T_580, _T_583, mfdhs) @[dec_tlu_ctl.scala 1923:21] - node mfdhs_ns = mux(_T_576, _T_577, _T_584) @[dec_tlu_ctl.scala 1922:20] - node _T_585 = or(wr_mfdhs_r, io.dbg_tlu_halted) @[dec_tlu_ctl.scala 1925:71] - node _T_586 = bits(_T_585, 0, 0) @[dec_tlu_ctl.scala 1925:92] - reg _T_587 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_586 : @[Reg.scala 28:19] - _T_587 <= mfdhs_ns @[Reg.scala 28:23] + reg _T_572 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_572 <= mdccmect_ns @[lib.scala 374:16] + mdccmect <= _T_572 @[dec_tlu_ctl.scala 1895:11] + node _T_573 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1897:52] + node _T_574 = dshl(UInt<32>("h0ffffffff"), _T_573) @[dec_tlu_ctl.scala 1897:41] + node _T_575 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1897:85] + node _T_576 = cat(UInt<5>("h00"), _T_575) @[Cat.scala 29:58] + node _T_577 = and(_T_574, _T_576) @[dec_tlu_ctl.scala 1897:61] + node _T_578 = orr(_T_577) @[dec_tlu_ctl.scala 1897:94] + mdccme_ce_req <= _T_578 @[dec_tlu_ctl.scala 1897:16] + node _T_579 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1907:62] + node _T_580 = eq(_T_579, UInt<12>("h07ce")) @[dec_tlu_ctl.scala 1907:69] + node wr_mfdht_r = and(io.dec_csr_wen_r_mod, _T_580) @[dec_tlu_ctl.scala 1907:40] + node _T_581 = bits(wr_mfdht_r, 0, 0) @[dec_tlu_ctl.scala 1909:32] + node _T_582 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1909:59] + node mfdht_ns = mux(_T_581, _T_582, mfdht) @[dec_tlu_ctl.scala 1909:20] + reg _T_583 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1911:43] + _T_583 <= mfdht_ns @[dec_tlu_ctl.scala 1911:43] + mfdht <= _T_583 @[dec_tlu_ctl.scala 1911:8] + node _T_584 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1920:62] + node _T_585 = eq(_T_584, UInt<12>("h07cf")) @[dec_tlu_ctl.scala 1920:69] + node wr_mfdhs_r = and(io.dec_csr_wen_r_mod, _T_585) @[dec_tlu_ctl.scala 1920:40] + node _T_586 = bits(wr_mfdhs_r, 0, 0) @[dec_tlu_ctl.scala 1922:32] + node _T_587 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 1922:60] + node _T_588 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1923:43] + node _T_589 = and(io.dbg_tlu_halted, _T_588) @[dec_tlu_ctl.scala 1923:41] + node _T_590 = bits(_T_589, 0, 0) @[dec_tlu_ctl.scala 1923:65] + node _T_591 = not(io.lsu_idle_any_f) @[dec_tlu_ctl.scala 1923:78] + node _T_592 = not(io.ifu_miss_state_idle_f) @[dec_tlu_ctl.scala 1923:98] + node _T_593 = cat(_T_591, _T_592) @[Cat.scala 29:58] + node _T_594 = mux(_T_590, _T_593, mfdhs) @[dec_tlu_ctl.scala 1923:21] + node mfdhs_ns = mux(_T_586, _T_587, _T_594) @[dec_tlu_ctl.scala 1922:20] + node _T_595 = or(wr_mfdhs_r, io.dbg_tlu_halted) @[dec_tlu_ctl.scala 1925:71] + node _T_596 = bits(_T_595, 0, 0) @[dec_tlu_ctl.scala 1925:92] + reg _T_597 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_596 : @[Reg.scala 28:19] + _T_597 <= mfdhs_ns @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mfdhs <= _T_587 @[dec_tlu_ctl.scala 1925:8] - node _T_588 = bits(io.debug_halt_req_f, 0, 0) @[dec_tlu_ctl.scala 1927:47] - node _T_589 = add(force_halt_ctr_f, UInt<32>("h01")) @[dec_tlu_ctl.scala 1927:74] - node _T_590 = tail(_T_589, 1) @[dec_tlu_ctl.scala 1927:74] - node _T_591 = bits(io.dbg_tlu_halted_f, 0, 0) @[dec_tlu_ctl.scala 1928:48] - node _T_592 = mux(_T_591, UInt<32>("h00"), force_halt_ctr_f) @[dec_tlu_ctl.scala 1928:27] - node force_halt_ctr = mux(_T_588, _T_590, _T_592) @[dec_tlu_ctl.scala 1927:26] - node _T_593 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1930:81] - reg _T_594 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_593 : @[Reg.scala 28:19] - _T_594 <= force_halt_ctr @[Reg.scala 28:23] + mfdhs <= _T_597 @[dec_tlu_ctl.scala 1925:8] + node _T_598 = bits(io.debug_halt_req_f, 0, 0) @[dec_tlu_ctl.scala 1927:47] + node _T_599 = add(force_halt_ctr_f, UInt<32>("h01")) @[dec_tlu_ctl.scala 1927:74] + node _T_600 = tail(_T_599, 1) @[dec_tlu_ctl.scala 1927:74] + node _T_601 = bits(io.dbg_tlu_halted_f, 0, 0) @[dec_tlu_ctl.scala 1928:48] + node _T_602 = mux(_T_601, UInt<32>("h00"), force_halt_ctr_f) @[dec_tlu_ctl.scala 1928:27] + node force_halt_ctr = mux(_T_598, _T_600, _T_602) @[dec_tlu_ctl.scala 1927:26] + node _T_603 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1930:81] + reg _T_604 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_603 : @[Reg.scala 28:19] + _T_604 <= force_halt_ctr @[Reg.scala 28:23] skip @[Reg.scala 28:19] - force_halt_ctr_f <= _T_594 @[dec_tlu_ctl.scala 1930:19] - node _T_595 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1932:24] - node _T_596 = bits(mfdht, 5, 1) @[dec_tlu_ctl.scala 1932:79] - node _T_597 = dshl(UInt<32>("h0ffffffff"), _T_596) @[dec_tlu_ctl.scala 1932:71] - node _T_598 = and(force_halt_ctr_f, _T_597) @[dec_tlu_ctl.scala 1932:48] - node _T_599 = orr(_T_598) @[dec_tlu_ctl.scala 1932:87] - node _T_600 = and(_T_595, _T_599) @[dec_tlu_ctl.scala 1932:28] - io.force_halt <= _T_600 @[dec_tlu_ctl.scala 1932:16] - node _T_601 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1940:62] - node _T_602 = eq(_T_601, UInt<12>("h0bc8")) @[dec_tlu_ctl.scala 1940:69] - node wr_meivt_r = and(io.dec_csr_wen_r_mod, _T_602) @[dec_tlu_ctl.scala 1940:40] - node _T_603 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 1942:40] - node _T_604 = bits(wr_meivt_r, 0, 0) @[dec_tlu_ctl.scala 1942:59] + force_halt_ctr_f <= _T_604 @[dec_tlu_ctl.scala 1930:19] + node _T_605 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1932:24] + node _T_606 = bits(mfdht, 5, 1) @[dec_tlu_ctl.scala 1932:79] + node _T_607 = dshl(UInt<32>("h0ffffffff"), _T_606) @[dec_tlu_ctl.scala 1932:71] + node _T_608 = and(force_halt_ctr_f, _T_607) @[dec_tlu_ctl.scala 1932:48] + node _T_609 = orr(_T_608) @[dec_tlu_ctl.scala 1932:87] + node _T_610 = and(_T_605, _T_609) @[dec_tlu_ctl.scala 1932:28] + io.force_halt <= _T_610 @[dec_tlu_ctl.scala 1932:16] + node _T_611 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1940:62] + node _T_612 = eq(_T_611, UInt<12>("h0bc8")) @[dec_tlu_ctl.scala 1940:69] + node wr_meivt_r = and(io.dec_csr_wen_r_mod, _T_612) @[dec_tlu_ctl.scala 1940:40] + node _T_613 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 1942:40] + node _T_614 = bits(wr_meivt_r, 0, 0) @[dec_tlu_ctl.scala 1942:59] inst rvclkhdr_15 of rvclkhdr_735 @[lib.scala 368:23] rvclkhdr_15.clock <= clock rvclkhdr_15.reset <= reset rvclkhdr_15.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_15.io.en <= _T_604 @[lib.scala 371:17] + rvclkhdr_15.io.en <= _T_614 @[lib.scala 371:17] rvclkhdr_15.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg meivt : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - meivt <= _T_603 @[lib.scala 374:16] - node _T_605 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1954:49] + meivt <= _T_613 @[lib.scala 374:16] + node _T_615 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1954:49] inst rvclkhdr_16 of rvclkhdr_736 @[lib.scala 368:23] rvclkhdr_16.clock <= clock rvclkhdr_16.reset <= reset rvclkhdr_16.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_16.io.en <= _T_605 @[lib.scala 371:17] + rvclkhdr_16.io.en <= _T_615 @[lib.scala 371:17] rvclkhdr_16.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg meihap : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] meihap <= io.pic_claimid @[lib.scala 374:16] - node _T_606 = cat(meivt, meihap) @[Cat.scala 29:58] - io.dec_tlu_meihap <= _T_606 @[dec_tlu_ctl.scala 1955:20] - node _T_607 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1964:65] - node _T_608 = eq(_T_607, UInt<12>("h0bcc")) @[dec_tlu_ctl.scala 1964:72] - node wr_meicurpl_r = and(io.dec_csr_wen_r_mod, _T_608) @[dec_tlu_ctl.scala 1964:43] - node _T_609 = bits(wr_meicurpl_r, 0, 0) @[dec_tlu_ctl.scala 1965:38] - node _T_610 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1965:65] - node meicurpl_ns = mux(_T_609, _T_610, meicurpl) @[dec_tlu_ctl.scala 1965:23] - reg _T_611 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1967:46] - _T_611 <= meicurpl_ns @[dec_tlu_ctl.scala 1967:46] - meicurpl <= _T_611 @[dec_tlu_ctl.scala 1967:11] + node _T_616 = cat(meivt, meihap) @[Cat.scala 29:58] + io.dec_tlu_meihap <= _T_616 @[dec_tlu_ctl.scala 1955:20] + node _T_617 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1964:65] + node _T_618 = eq(_T_617, UInt<12>("h0bcc")) @[dec_tlu_ctl.scala 1964:72] + node wr_meicurpl_r = and(io.dec_csr_wen_r_mod, _T_618) @[dec_tlu_ctl.scala 1964:43] + node _T_619 = bits(wr_meicurpl_r, 0, 0) @[dec_tlu_ctl.scala 1965:38] + node _T_620 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1965:65] + node meicurpl_ns = mux(_T_619, _T_620, meicurpl) @[dec_tlu_ctl.scala 1965:23] + reg _T_621 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1967:46] + _T_621 <= meicurpl_ns @[dec_tlu_ctl.scala 1967:46] + meicurpl <= _T_621 @[dec_tlu_ctl.scala 1967:11] io.dec_tlu_meicurpl <= meicurpl @[dec_tlu_ctl.scala 1969:22] - node _T_612 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1979:66] - node _T_613 = eq(_T_612, UInt<12>("h0bcb")) @[dec_tlu_ctl.scala 1979:73] - node _T_614 = and(io.dec_csr_wen_r_mod, _T_613) @[dec_tlu_ctl.scala 1979:44] - node wr_meicidpl_r = or(_T_614, io.take_ext_int_start) @[dec_tlu_ctl.scala 1979:88] - node _T_615 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1981:37] - node _T_616 = bits(wr_meicidpl_r, 0, 0) @[dec_tlu_ctl.scala 1982:38] - node _T_617 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1982:65] - node _T_618 = mux(_T_616, _T_617, meicidpl) @[dec_tlu_ctl.scala 1982:23] - node meicidpl_ns = mux(_T_615, io.pic_pl, _T_618) @[dec_tlu_ctl.scala 1981:23] - reg _T_619 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1984:44] - _T_619 <= meicidpl_ns @[dec_tlu_ctl.scala 1984:44] - meicidpl <= _T_619 @[dec_tlu_ctl.scala 1984:11] - node _T_620 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1991:62] - node _T_621 = eq(_T_620, UInt<12>("h0bca")) @[dec_tlu_ctl.scala 1991:69] - node _T_622 = and(io.dec_csr_wen_r_mod, _T_621) @[dec_tlu_ctl.scala 1991:40] - node _T_623 = or(_T_622, io.take_ext_int_start) @[dec_tlu_ctl.scala 1991:83] - wr_meicpct_r <= _T_623 @[dec_tlu_ctl.scala 1991:15] - node _T_624 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2000:62] - node _T_625 = eq(_T_624, UInt<12>("h0bc9")) @[dec_tlu_ctl.scala 2000:69] - node wr_meipt_r = and(io.dec_csr_wen_r_mod, _T_625) @[dec_tlu_ctl.scala 2000:40] - node _T_626 = bits(wr_meipt_r, 0, 0) @[dec_tlu_ctl.scala 2001:32] - node _T_627 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2001:59] - node meipt_ns = mux(_T_626, _T_627, meipt) @[dec_tlu_ctl.scala 2001:20] - reg _T_628 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2003:43] - _T_628 <= meipt_ns @[dec_tlu_ctl.scala 2003:43] - meipt <= _T_628 @[dec_tlu_ctl.scala 2003:8] + node _T_622 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1979:66] + node _T_623 = eq(_T_622, UInt<12>("h0bcb")) @[dec_tlu_ctl.scala 1979:73] + node _T_624 = and(io.dec_csr_wen_r_mod, _T_623) @[dec_tlu_ctl.scala 1979:44] + node wr_meicidpl_r = or(_T_624, io.take_ext_int_start) @[dec_tlu_ctl.scala 1979:88] + node _T_625 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1981:37] + node _T_626 = bits(wr_meicidpl_r, 0, 0) @[dec_tlu_ctl.scala 1982:38] + node _T_627 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1982:65] + node _T_628 = mux(_T_626, _T_627, meicidpl) @[dec_tlu_ctl.scala 1982:23] + node meicidpl_ns = mux(_T_625, io.pic_pl, _T_628) @[dec_tlu_ctl.scala 1981:23] + reg _T_629 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1984:44] + _T_629 <= meicidpl_ns @[dec_tlu_ctl.scala 1984:44] + meicidpl <= _T_629 @[dec_tlu_ctl.scala 1984:11] + node _T_630 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1991:62] + node _T_631 = eq(_T_630, UInt<12>("h0bca")) @[dec_tlu_ctl.scala 1991:69] + node _T_632 = and(io.dec_csr_wen_r_mod, _T_631) @[dec_tlu_ctl.scala 1991:40] + node _T_633 = or(_T_632, io.take_ext_int_start) @[dec_tlu_ctl.scala 1991:83] + wr_meicpct_r <= _T_633 @[dec_tlu_ctl.scala 1991:15] + node _T_634 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2000:62] + node _T_635 = eq(_T_634, UInt<12>("h0bc9")) @[dec_tlu_ctl.scala 2000:69] + node wr_meipt_r = and(io.dec_csr_wen_r_mod, _T_635) @[dec_tlu_ctl.scala 2000:40] + node _T_636 = bits(wr_meipt_r, 0, 0) @[dec_tlu_ctl.scala 2001:32] + node _T_637 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2001:59] + node meipt_ns = mux(_T_636, _T_637, meipt) @[dec_tlu_ctl.scala 2001:20] + reg _T_638 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2003:43] + _T_638 <= meipt_ns @[dec_tlu_ctl.scala 2003:43] + meipt <= _T_638 @[dec_tlu_ctl.scala 2003:8] io.dec_tlu_meipt <= meipt @[dec_tlu_ctl.scala 2005:19] - node _T_629 = and(io.trigger_hit_r_d1, io.dcsr_single_step_done_f) @[dec_tlu_ctl.scala 2031:89] - node trigger_hit_for_dscr_cause_r_d1 = or(io.trigger_hit_dmode_r_d1, _T_629) @[dec_tlu_ctl.scala 2031:66] - node _T_630 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2034:31] - node _T_631 = and(io.dcsr_single_step_done_f, _T_630) @[dec_tlu_ctl.scala 2034:29] - node _T_632 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2034:63] - node _T_633 = and(_T_631, _T_632) @[dec_tlu_ctl.scala 2034:61] - node _T_634 = not(io.debug_halt_req) @[dec_tlu_ctl.scala 2034:98] - node _T_635 = and(_T_633, _T_634) @[dec_tlu_ctl.scala 2034:96] - node _T_636 = bits(_T_635, 0, 0) @[dec_tlu_ctl.scala 2034:118] - node _T_637 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2035:48] - node _T_638 = and(io.debug_halt_req, _T_637) @[dec_tlu_ctl.scala 2035:46] - node _T_639 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2035:80] - node _T_640 = and(_T_638, _T_639) @[dec_tlu_ctl.scala 2035:78] - node _T_641 = bits(_T_640, 0, 0) @[dec_tlu_ctl.scala 2035:114] - node _T_642 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2036:77] - node _T_643 = and(io.ebreak_to_debug_mode_r_d1, _T_642) @[dec_tlu_ctl.scala 2036:75] - node _T_644 = bits(_T_643, 0, 0) @[dec_tlu_ctl.scala 2036:111] - node _T_645 = bits(trigger_hit_for_dscr_cause_r_d1, 0, 0) @[dec_tlu_ctl.scala 2037:108] - node _T_646 = mux(_T_636, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_647 = mux(_T_641, UInt<3>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_648 = mux(_T_644, UInt<3>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_649 = mux(_T_645, UInt<3>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_650 = or(_T_646, _T_647) @[Mux.scala 27:72] - node _T_651 = or(_T_650, _T_648) @[Mux.scala 27:72] - node _T_652 = or(_T_651, _T_649) @[Mux.scala 27:72] + node _T_639 = and(io.trigger_hit_r_d1, io.dcsr_single_step_done_f) @[dec_tlu_ctl.scala 2031:89] + node trigger_hit_for_dscr_cause_r_d1 = or(io.trigger_hit_dmode_r_d1, _T_639) @[dec_tlu_ctl.scala 2031:66] + node _T_640 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2034:31] + node _T_641 = and(io.dcsr_single_step_done_f, _T_640) @[dec_tlu_ctl.scala 2034:29] + node _T_642 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2034:63] + node _T_643 = and(_T_641, _T_642) @[dec_tlu_ctl.scala 2034:61] + node _T_644 = not(io.debug_halt_req) @[dec_tlu_ctl.scala 2034:98] + node _T_645 = and(_T_643, _T_644) @[dec_tlu_ctl.scala 2034:96] + node _T_646 = bits(_T_645, 0, 0) @[dec_tlu_ctl.scala 2034:118] + node _T_647 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2035:48] + node _T_648 = and(io.debug_halt_req, _T_647) @[dec_tlu_ctl.scala 2035:46] + node _T_649 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2035:80] + node _T_650 = and(_T_648, _T_649) @[dec_tlu_ctl.scala 2035:78] + node _T_651 = bits(_T_650, 0, 0) @[dec_tlu_ctl.scala 2035:114] + node _T_652 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2036:77] + node _T_653 = and(io.ebreak_to_debug_mode_r_d1, _T_652) @[dec_tlu_ctl.scala 2036:75] + node _T_654 = bits(_T_653, 0, 0) @[dec_tlu_ctl.scala 2036:111] + node _T_655 = bits(trigger_hit_for_dscr_cause_r_d1, 0, 0) @[dec_tlu_ctl.scala 2037:108] + node _T_656 = mux(_T_646, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_657 = mux(_T_651, UInt<3>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_658 = mux(_T_654, UInt<3>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_659 = mux(_T_655, UInt<3>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_660 = or(_T_656, _T_657) @[Mux.scala 27:72] + node _T_661 = or(_T_660, _T_658) @[Mux.scala 27:72] + node _T_662 = or(_T_661, _T_659) @[Mux.scala 27:72] wire dcsr_cause : UInt<3> @[Mux.scala 27:72] - dcsr_cause <= _T_652 @[Mux.scala 27:72] - node _T_653 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2039:46] - node _T_654 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2039:91] - node _T_655 = eq(_T_654, UInt<12>("h07b0")) @[dec_tlu_ctl.scala 2039:98] - node wr_dcsr_r = and(_T_653, _T_655) @[dec_tlu_ctl.scala 2039:69] - node _T_656 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2045:69] - node _T_657 = eq(_T_656, UInt<3>("h03")) @[dec_tlu_ctl.scala 2045:75] - node dcsr_cause_upgradeable = and(io.internal_dbg_halt_mode_f, _T_657) @[dec_tlu_ctl.scala 2045:59] - node _T_658 = not(io.dbg_tlu_halted) @[dec_tlu_ctl.scala 2046:59] - node _T_659 = or(_T_658, dcsr_cause_upgradeable) @[dec_tlu_ctl.scala 2046:78] - node enter_debug_halt_req_le = and(io.enter_debug_halt_req, _T_659) @[dec_tlu_ctl.scala 2046:56] + dcsr_cause <= _T_662 @[Mux.scala 27:72] + node _T_663 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2039:46] + node _T_664 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2039:91] + node _T_665 = eq(_T_664, UInt<12>("h07b0")) @[dec_tlu_ctl.scala 2039:98] + node wr_dcsr_r = and(_T_663, _T_665) @[dec_tlu_ctl.scala 2039:69] + node _T_666 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2045:69] + node _T_667 = eq(_T_666, UInt<3>("h03")) @[dec_tlu_ctl.scala 2045:75] + node dcsr_cause_upgradeable = and(io.internal_dbg_halt_mode_f, _T_667) @[dec_tlu_ctl.scala 2045:59] + node _T_668 = not(io.dbg_tlu_halted) @[dec_tlu_ctl.scala 2046:59] + node _T_669 = or(_T_668, dcsr_cause_upgradeable) @[dec_tlu_ctl.scala 2046:78] + node enter_debug_halt_req_le = and(io.enter_debug_halt_req, _T_669) @[dec_tlu_ctl.scala 2046:56] node nmi_in_debug_mode = and(io.nmi_int_detected_f, io.internal_dbg_halt_mode_f) @[dec_tlu_ctl.scala 2048:48] - node _T_660 = bits(enter_debug_halt_req_le, 0, 0) @[dec_tlu_ctl.scala 2049:44] - node _T_661 = bits(io.dcsr, 15, 9) @[dec_tlu_ctl.scala 2049:64] - node _T_662 = bits(io.dcsr, 5, 2) @[dec_tlu_ctl.scala 2049:91] - node _T_663 = cat(_T_662, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_664 = cat(_T_661, dcsr_cause) @[Cat.scala 29:58] - node _T_665 = cat(_T_664, _T_663) @[Cat.scala 29:58] - node _T_666 = bits(wr_dcsr_r, 0, 0) @[dec_tlu_ctl.scala 2050:18] - node _T_667 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 2050:49] - node _T_668 = bits(io.dec_csr_wrdata_r, 11, 10) @[dec_tlu_ctl.scala 2050:84] - node _T_669 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2050:110] - node _T_670 = bits(io.dcsr, 3, 3) @[dec_tlu_ctl.scala 2050:154] - node _T_671 = or(nmi_in_debug_mode, _T_670) @[dec_tlu_ctl.scala 2050:145] - node _T_672 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2050:178] + node _T_670 = bits(enter_debug_halt_req_le, 0, 0) @[dec_tlu_ctl.scala 2049:44] + node _T_671 = bits(io.dcsr, 15, 9) @[dec_tlu_ctl.scala 2049:64] + node _T_672 = bits(io.dcsr, 5, 2) @[dec_tlu_ctl.scala 2049:91] node _T_673 = cat(_T_672, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_674 = cat(UInt<2>("h00"), _T_671) @[Cat.scala 29:58] + node _T_674 = cat(_T_671, dcsr_cause) @[Cat.scala 29:58] node _T_675 = cat(_T_674, _T_673) @[Cat.scala 29:58] - node _T_676 = cat(UInt<1>("h00"), _T_669) @[Cat.scala 29:58] - node _T_677 = cat(_T_667, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_678 = cat(_T_677, _T_668) @[Cat.scala 29:58] - node _T_679 = cat(_T_678, _T_676) @[Cat.scala 29:58] - node _T_680 = cat(_T_679, _T_675) @[Cat.scala 29:58] - node _T_681 = bits(io.dcsr, 15, 4) @[dec_tlu_ctl.scala 2050:211] - node _T_682 = bits(io.dcsr, 2, 2) @[dec_tlu_ctl.scala 2050:245] + node _T_676 = bits(wr_dcsr_r, 0, 0) @[dec_tlu_ctl.scala 2050:18] + node _T_677 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 2050:49] + node _T_678 = bits(io.dec_csr_wrdata_r, 11, 10) @[dec_tlu_ctl.scala 2050:84] + node _T_679 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2050:110] + node _T_680 = bits(io.dcsr, 3, 3) @[dec_tlu_ctl.scala 2050:154] + node _T_681 = or(nmi_in_debug_mode, _T_680) @[dec_tlu_ctl.scala 2050:145] + node _T_682 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2050:178] node _T_683 = cat(_T_682, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_684 = cat(_T_681, nmi_in_debug_mode) @[Cat.scala 29:58] + node _T_684 = cat(UInt<2>("h00"), _T_681) @[Cat.scala 29:58] node _T_685 = cat(_T_684, _T_683) @[Cat.scala 29:58] - node _T_686 = mux(_T_666, _T_680, _T_685) @[dec_tlu_ctl.scala 2050:7] - node dcsr_ns = mux(_T_660, _T_665, _T_686) @[dec_tlu_ctl.scala 2049:19] - node _T_687 = or(enter_debug_halt_req_le, wr_dcsr_r) @[dec_tlu_ctl.scala 2052:54] - node _T_688 = or(_T_687, io.internal_dbg_halt_mode) @[dec_tlu_ctl.scala 2052:66] - node _T_689 = or(_T_688, io.take_nmi) @[dec_tlu_ctl.scala 2052:94] - node _T_690 = bits(_T_689, 0, 0) @[dec_tlu_ctl.scala 2052:109] + node _T_686 = cat(UInt<1>("h00"), _T_679) @[Cat.scala 29:58] + node _T_687 = cat(_T_677, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_688 = cat(_T_687, _T_678) @[Cat.scala 29:58] + node _T_689 = cat(_T_688, _T_686) @[Cat.scala 29:58] + node _T_690 = cat(_T_689, _T_685) @[Cat.scala 29:58] + node _T_691 = bits(io.dcsr, 15, 4) @[dec_tlu_ctl.scala 2050:211] + node _T_692 = bits(io.dcsr, 2, 2) @[dec_tlu_ctl.scala 2050:245] + node _T_693 = cat(_T_692, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_694 = cat(_T_691, nmi_in_debug_mode) @[Cat.scala 29:58] + node _T_695 = cat(_T_694, _T_693) @[Cat.scala 29:58] + node _T_696 = mux(_T_676, _T_690, _T_695) @[dec_tlu_ctl.scala 2050:7] + node dcsr_ns = mux(_T_670, _T_675, _T_696) @[dec_tlu_ctl.scala 2049:19] + node _T_697 = or(enter_debug_halt_req_le, wr_dcsr_r) @[dec_tlu_ctl.scala 2052:54] + node _T_698 = or(_T_697, io.internal_dbg_halt_mode) @[dec_tlu_ctl.scala 2052:66] + node _T_699 = or(_T_698, io.take_nmi) @[dec_tlu_ctl.scala 2052:94] + node _T_700 = bits(_T_699, 0, 0) @[dec_tlu_ctl.scala 2052:109] inst rvclkhdr_17 of rvclkhdr_737 @[lib.scala 368:23] rvclkhdr_17.clock <= clock rvclkhdr_17.reset <= reset rvclkhdr_17.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_17.io.en <= _T_690 @[lib.scala 371:17] + rvclkhdr_17.io.en <= _T_700 @[lib.scala 371:17] rvclkhdr_17.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_691 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_691 <= dcsr_ns @[lib.scala 374:16] - io.dcsr <= _T_691 @[dec_tlu_ctl.scala 2052:10] - node _T_692 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2060:45] - node _T_693 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2060:90] - node _T_694 = eq(_T_693, UInt<12>("h07b1")) @[dec_tlu_ctl.scala 2060:97] - node wr_dpc_r = and(_T_692, _T_694) @[dec_tlu_ctl.scala 2060:68] - node _T_695 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2061:44] - node _T_696 = and(io.dbg_tlu_halted, _T_695) @[dec_tlu_ctl.scala 2061:42] - node _T_697 = not(io.request_debug_mode_done) @[dec_tlu_ctl.scala 2061:67] - node dpc_capture_npc = and(_T_696, _T_697) @[dec_tlu_ctl.scala 2061:65] - node _T_698 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2065:21] - node _T_699 = not(dpc_capture_npc) @[dec_tlu_ctl.scala 2065:39] - node _T_700 = and(_T_698, _T_699) @[dec_tlu_ctl.scala 2065:37] - node _T_701 = and(_T_700, wr_dpc_r) @[dec_tlu_ctl.scala 2065:56] - node _T_702 = bits(_T_701, 0, 0) @[dec_tlu_ctl.scala 2065:68] - node _T_703 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 2065:97] - node _T_704 = bits(io.request_debug_mode_r, 0, 0) @[dec_tlu_ctl.scala 2066:68] - node _T_705 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2067:33] - node _T_706 = and(_T_705, dpc_capture_npc) @[dec_tlu_ctl.scala 2067:49] - node _T_707 = bits(_T_706, 0, 0) @[dec_tlu_ctl.scala 2067:68] - node _T_708 = mux(_T_702, _T_703, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_709 = mux(_T_704, pc_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_710 = mux(_T_707, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_711 = or(_T_708, _T_709) @[Mux.scala 27:72] - node _T_712 = or(_T_711, _T_710) @[Mux.scala 27:72] + reg _T_701 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_701 <= dcsr_ns @[lib.scala 374:16] + io.dcsr <= _T_701 @[dec_tlu_ctl.scala 2052:10] + node _T_702 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2060:45] + node _T_703 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2060:90] + node _T_704 = eq(_T_703, UInt<12>("h07b1")) @[dec_tlu_ctl.scala 2060:97] + node wr_dpc_r = and(_T_702, _T_704) @[dec_tlu_ctl.scala 2060:68] + node _T_705 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2061:44] + node _T_706 = and(io.dbg_tlu_halted, _T_705) @[dec_tlu_ctl.scala 2061:42] + node _T_707 = not(io.request_debug_mode_done) @[dec_tlu_ctl.scala 2061:67] + node dpc_capture_npc = and(_T_706, _T_707) @[dec_tlu_ctl.scala 2061:65] + node _T_708 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2065:21] + node _T_709 = not(dpc_capture_npc) @[dec_tlu_ctl.scala 2065:39] + node _T_710 = and(_T_708, _T_709) @[dec_tlu_ctl.scala 2065:37] + node _T_711 = and(_T_710, wr_dpc_r) @[dec_tlu_ctl.scala 2065:56] + node _T_712 = bits(_T_711, 0, 0) @[dec_tlu_ctl.scala 2065:68] + node _T_713 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 2065:97] + node _T_714 = bits(io.request_debug_mode_r, 0, 0) @[dec_tlu_ctl.scala 2066:68] + node _T_715 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2067:33] + node _T_716 = and(_T_715, dpc_capture_npc) @[dec_tlu_ctl.scala 2067:49] + node _T_717 = bits(_T_716, 0, 0) @[dec_tlu_ctl.scala 2067:68] + node _T_718 = mux(_T_712, _T_713, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_719 = mux(_T_714, pc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_720 = mux(_T_717, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_721 = or(_T_718, _T_719) @[Mux.scala 27:72] + node _T_722 = or(_T_721, _T_720) @[Mux.scala 27:72] wire dpc_ns : UInt<31> @[Mux.scala 27:72] - dpc_ns <= _T_712 @[Mux.scala 27:72] - node _T_713 = or(wr_dpc_r, io.request_debug_mode_r) @[dec_tlu_ctl.scala 2069:36] - node _T_714 = or(_T_713, dpc_capture_npc) @[dec_tlu_ctl.scala 2069:53] - node _T_715 = bits(_T_714, 0, 0) @[dec_tlu_ctl.scala 2069:72] + dpc_ns <= _T_722 @[Mux.scala 27:72] + node _T_723 = or(wr_dpc_r, io.request_debug_mode_r) @[dec_tlu_ctl.scala 2069:36] + node _T_724 = or(_T_723, dpc_capture_npc) @[dec_tlu_ctl.scala 2069:53] + node _T_725 = bits(_T_724, 0, 0) @[dec_tlu_ctl.scala 2069:72] inst rvclkhdr_18 of rvclkhdr_738 @[lib.scala 368:23] rvclkhdr_18.clock <= clock rvclkhdr_18.reset <= reset rvclkhdr_18.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_18.io.en <= _T_715 @[lib.scala 371:17] + rvclkhdr_18.io.en <= _T_725 @[lib.scala 371:17] rvclkhdr_18.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_716 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_716 <= dpc_ns @[lib.scala 374:16] - io.dpc <= _T_716 @[dec_tlu_ctl.scala 2069:9] - node _T_717 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 2083:43] - node _T_718 = bits(io.dec_csr_wrdata_r, 21, 20) @[dec_tlu_ctl.scala 2083:68] - node _T_719 = bits(io.dec_csr_wrdata_r, 16, 3) @[dec_tlu_ctl.scala 2083:96] - node _T_720 = cat(_T_717, _T_718) @[Cat.scala 29:58] - node dicawics_ns = cat(_T_720, _T_719) @[Cat.scala 29:58] - node _T_721 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2084:50] - node _T_722 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2084:95] - node _T_723 = eq(_T_722, UInt<12>("h07c8")) @[dec_tlu_ctl.scala 2084:102] - node wr_dicawics_r = and(_T_721, _T_723) @[dec_tlu_ctl.scala 2084:73] - node _T_724 = bits(wr_dicawics_r, 0, 0) @[dec_tlu_ctl.scala 2086:50] + reg _T_726 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_726 <= dpc_ns @[lib.scala 374:16] + io.dpc <= _T_726 @[dec_tlu_ctl.scala 2069:9] + node _T_727 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 2083:43] + node _T_728 = bits(io.dec_csr_wrdata_r, 21, 20) @[dec_tlu_ctl.scala 2083:68] + node _T_729 = bits(io.dec_csr_wrdata_r, 16, 3) @[dec_tlu_ctl.scala 2083:96] + node _T_730 = cat(_T_727, _T_728) @[Cat.scala 29:58] + node dicawics_ns = cat(_T_730, _T_729) @[Cat.scala 29:58] + node _T_731 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2084:50] + node _T_732 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2084:95] + node _T_733 = eq(_T_732, UInt<12>("h07c8")) @[dec_tlu_ctl.scala 2084:102] + node wr_dicawics_r = and(_T_731, _T_733) @[dec_tlu_ctl.scala 2084:73] + node _T_734 = bits(wr_dicawics_r, 0, 0) @[dec_tlu_ctl.scala 2086:50] inst rvclkhdr_19 of rvclkhdr_739 @[lib.scala 368:23] rvclkhdr_19.clock <= clock rvclkhdr_19.reset <= reset rvclkhdr_19.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_19.io.en <= _T_724 @[lib.scala 371:17] + rvclkhdr_19.io.en <= _T_734 @[lib.scala 371:17] rvclkhdr_19.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg dicawics : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] dicawics <= dicawics_ns @[lib.scala 374:16] - node _T_725 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2102:48] - node _T_726 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2102:93] - node _T_727 = eq(_T_726, UInt<12>("h07c9")) @[dec_tlu_ctl.scala 2102:100] - node wr_dicad0_r = and(_T_725, _T_727) @[dec_tlu_ctl.scala 2102:71] - node _T_728 = bits(wr_dicad0_r, 0, 0) @[dec_tlu_ctl.scala 2103:34] - node dicad0_ns = mux(_T_728, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data) @[dec_tlu_ctl.scala 2103:21] - node _T_729 = or(wr_dicad0_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2105:46] - node _T_730 = bits(_T_729, 0, 0) @[dec_tlu_ctl.scala 2105:79] + node _T_735 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2102:48] + node _T_736 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2102:93] + node _T_737 = eq(_T_736, UInt<12>("h07c9")) @[dec_tlu_ctl.scala 2102:100] + node wr_dicad0_r = and(_T_735, _T_737) @[dec_tlu_ctl.scala 2102:71] + node _T_738 = bits(wr_dicad0_r, 0, 0) @[dec_tlu_ctl.scala 2103:34] + node dicad0_ns = mux(_T_738, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data) @[dec_tlu_ctl.scala 2103:21] + node _T_739 = or(wr_dicad0_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2105:46] + node _T_740 = bits(_T_739, 0, 0) @[dec_tlu_ctl.scala 2105:79] inst rvclkhdr_20 of rvclkhdr_740 @[lib.scala 368:23] rvclkhdr_20.clock <= clock rvclkhdr_20.reset <= reset rvclkhdr_20.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_20.io.en <= _T_730 @[lib.scala 371:17] + rvclkhdr_20.io.en <= _T_740 @[lib.scala 371:17] rvclkhdr_20.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg dicad0 : UInt, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] dicad0 <= dicad0_ns @[lib.scala 374:16] - node _T_731 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2115:49] - node _T_732 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2115:94] - node _T_733 = eq(_T_732, UInt<12>("h07cc")) @[dec_tlu_ctl.scala 2115:101] - node wr_dicad0h_r = and(_T_731, _T_733) @[dec_tlu_ctl.scala 2115:72] - node _T_734 = bits(wr_dicad0h_r, 0, 0) @[dec_tlu_ctl.scala 2117:36] - node _T_735 = bits(io.ifu_ic_debug_rd_data, 63, 32) @[dec_tlu_ctl.scala 2117:88] - node dicad0h_ns = mux(_T_734, io.dec_csr_wrdata_r, _T_735) @[dec_tlu_ctl.scala 2117:22] - node _T_736 = or(wr_dicad0h_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2119:48] - node _T_737 = bits(_T_736, 0, 0) @[dec_tlu_ctl.scala 2119:81] + node _T_741 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2115:49] + node _T_742 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2115:94] + node _T_743 = eq(_T_742, UInt<12>("h07cc")) @[dec_tlu_ctl.scala 2115:101] + node wr_dicad0h_r = and(_T_741, _T_743) @[dec_tlu_ctl.scala 2115:72] + node _T_744 = bits(wr_dicad0h_r, 0, 0) @[dec_tlu_ctl.scala 2117:36] + node _T_745 = bits(io.ifu_ic_debug_rd_data, 63, 32) @[dec_tlu_ctl.scala 2117:88] + node dicad0h_ns = mux(_T_744, io.dec_csr_wrdata_r, _T_745) @[dec_tlu_ctl.scala 2117:22] + node _T_746 = or(wr_dicad0h_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2119:48] + node _T_747 = bits(_T_746, 0, 0) @[dec_tlu_ctl.scala 2119:81] inst rvclkhdr_21 of rvclkhdr_741 @[lib.scala 368:23] rvclkhdr_21.clock <= clock rvclkhdr_21.reset <= reset rvclkhdr_21.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_21.io.en <= _T_737 @[lib.scala 371:17] + rvclkhdr_21.io.en <= _T_747 @[lib.scala 371:17] rvclkhdr_21.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg dicad0h : UInt, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] dicad0h <= dicad0h_ns @[lib.scala 374:16] - wire _T_738 : UInt<4> - _T_738 <= UInt<1>("h00") - node _T_739 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2142:48] - node _T_740 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2142:93] - node _T_741 = eq(_T_740, UInt<12>("h07ca")) @[dec_tlu_ctl.scala 2142:100] - node _T_742 = and(_T_739, _T_741) @[dec_tlu_ctl.scala 2142:71] - node _T_743 = bits(_T_742, 0, 0) @[dec_tlu_ctl.scala 2144:34] - node _T_744 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2144:61] - node _T_745 = bits(io.ifu_ic_debug_rd_data, 67, 64) @[dec_tlu_ctl.scala 2144:91] - node _T_746 = mux(_T_743, _T_744, _T_745) @[dec_tlu_ctl.scala 2144:21] - node _T_747 = or(_T_742, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2146:77] - node _T_748 = bits(_T_747, 0, 0) @[dec_tlu_ctl.scala 2146:110] - reg _T_749 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_748 : @[Reg.scala 28:19] - _T_749 <= _T_746 @[Reg.scala 28:23] + wire _T_748 : UInt<7> + _T_748 <= UInt<1>("h00") + node _T_749 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2127:48] + node _T_750 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2127:93] + node _T_751 = eq(_T_750, UInt<12>("h07ca")) @[dec_tlu_ctl.scala 2127:100] + node _T_752 = and(_T_749, _T_751) @[dec_tlu_ctl.scala 2127:71] + node _T_753 = bits(_T_752, 0, 0) @[dec_tlu_ctl.scala 2129:34] + node _T_754 = bits(io.ifu_ic_debug_rd_data, 70, 64) @[dec_tlu_ctl.scala 2129:86] + node _T_755 = mux(_T_753, io.dec_csr_wrdata_r, _T_754) @[dec_tlu_ctl.scala 2129:21] + node _T_756 = or(_T_752, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2131:78] + node _T_757 = bits(_T_756, 0, 0) @[dec_tlu_ctl.scala 2131:111] + reg _T_758 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_757 : @[Reg.scala 28:19] + _T_758 <= _T_755 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - _T_738 <= _T_749 @[dec_tlu_ctl.scala 2146:13] - node _T_750 = cat(UInt<28>("h00"), _T_738) @[Cat.scala 29:58] - dicad1 <= _T_750 @[dec_tlu_ctl.scala 2147:9] - node _T_751 = bits(dicad1, 3, 0) @[dec_tlu_ctl.scala 2155:69] - node _T_752 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2155:83] - node _T_753 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2155:97] - node _T_754 = cat(_T_752, _T_753) @[Cat.scala 29:58] - node _T_755 = cat(UInt<2>("h00"), _T_751) @[Cat.scala 29:58] - node _T_756 = cat(_T_755, _T_754) @[Cat.scala 29:58] - io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_756 @[dec_tlu_ctl.scala 2155:47] + _T_748 <= _T_758 @[dec_tlu_ctl.scala 2131:13] + node _T_759 = cat(UInt<25>("h00"), _T_748) @[Cat.scala 29:58] + dicad1 <= _T_759 @[dec_tlu_ctl.scala 2132:9] + node _T_760 = bits(dicad1, 6, 0) @[dec_tlu_ctl.scala 2154:74] + node _T_761 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2154:88] + node _T_762 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2154:102] + node _T_763 = cat(_T_760, _T_761) @[Cat.scala 29:58] + node _T_764 = cat(_T_763, _T_762) @[Cat.scala 29:58] + io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_764 @[dec_tlu_ctl.scala 2154:61] io.dec_tlu_ic_diag_pkt.icache_dicawics <= dicawics @[dec_tlu_ctl.scala 2157:41] - node _T_757 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 2159:52] - node _T_758 = and(_T_757, io.dec_i0_decode_d) @[dec_tlu_ctl.scala 2159:75] - node _T_759 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 2159:98] - node _T_760 = and(_T_758, _T_759) @[dec_tlu_ctl.scala 2159:96] - node _T_761 = bits(io.dec_csr_rdaddr_d, 11, 0) @[dec_tlu_ctl.scala 2159:142] - node _T_762 = eq(_T_761, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2159:149] - node icache_rd_valid = and(_T_760, _T_762) @[dec_tlu_ctl.scala 2159:120] - node _T_763 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2160:52] - node _T_764 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2160:97] - node _T_765 = eq(_T_764, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2160:104] - node icache_wr_valid = and(_T_763, _T_765) @[dec_tlu_ctl.scala 2160:75] + node _T_765 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 2159:52] + node _T_766 = and(_T_765, io.dec_i0_decode_d) @[dec_tlu_ctl.scala 2159:75] + node _T_767 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 2159:98] + node _T_768 = and(_T_766, _T_767) @[dec_tlu_ctl.scala 2159:96] + node _T_769 = bits(io.dec_csr_rdaddr_d, 11, 0) @[dec_tlu_ctl.scala 2159:142] + node _T_770 = eq(_T_769, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2159:149] + node icache_rd_valid = and(_T_768, _T_770) @[dec_tlu_ctl.scala 2159:120] + node _T_771 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2160:52] + node _T_772 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2160:97] + node _T_773 = eq(_T_772, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2160:104] + node icache_wr_valid = and(_T_771, _T_773) @[dec_tlu_ctl.scala 2160:75] reg icache_rd_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2162:58] icache_rd_valid_f <= icache_rd_valid @[dec_tlu_ctl.scala 2162:58] reg icache_wr_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2163:58] icache_wr_valid_f <= icache_wr_valid @[dec_tlu_ctl.scala 2163:58] io.dec_tlu_ic_diag_pkt.icache_rd_valid <= icache_rd_valid_f @[dec_tlu_ctl.scala 2165:41] io.dec_tlu_ic_diag_pkt.icache_wr_valid <= icache_wr_valid_f @[dec_tlu_ctl.scala 2166:41] - node _T_766 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2174:62] - node _T_767 = eq(_T_766, UInt<12>("h07a0")) @[dec_tlu_ctl.scala 2174:69] - node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_767) @[dec_tlu_ctl.scala 2174:40] - node _T_768 = bits(wr_mtsel_r, 0, 0) @[dec_tlu_ctl.scala 2175:32] - node _T_769 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 2175:59] - node mtsel_ns = mux(_T_768, _T_769, mtsel) @[dec_tlu_ctl.scala 2175:20] - reg _T_770 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2177:43] - _T_770 <= mtsel_ns @[dec_tlu_ctl.scala 2177:43] - mtsel <= _T_770 @[dec_tlu_ctl.scala 2177:8] - node _T_771 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2212:38] - node _T_772 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2212:64] - node _T_773 = not(_T_772) @[dec_tlu_ctl.scala 2212:44] - node tdata_load = and(_T_771, _T_773) @[dec_tlu_ctl.scala 2212:42] - node _T_774 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2214:40] - node _T_775 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2214:66] - node _T_776 = not(_T_775) @[dec_tlu_ctl.scala 2214:46] - node tdata_opcode = and(_T_774, _T_776) @[dec_tlu_ctl.scala 2214:44] - node _T_777 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2216:41] - node _T_778 = and(_T_777, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2216:46] - node _T_779 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 2216:90] - node tdata_action = and(_T_778, _T_779) @[dec_tlu_ctl.scala 2216:69] - node _T_780 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2218:47] - node _T_781 = and(_T_780, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2218:52] - node _T_782 = bits(io.dec_csr_wrdata_r, 20, 19) @[dec_tlu_ctl.scala 2218:94] - node _T_783 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2218:136] - node _T_784 = bits(io.dec_csr_wrdata_r, 7, 6) @[dec_tlu_ctl.scala 2219:43] - node _T_785 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 2219:83] - node _T_786 = cat(_T_785, tdata_load) @[Cat.scala 29:58] - node _T_787 = cat(_T_784, tdata_opcode) @[Cat.scala 29:58] - node _T_788 = cat(_T_787, _T_786) @[Cat.scala 29:58] - node _T_789 = cat(tdata_action, _T_783) @[Cat.scala 29:58] - node _T_790 = cat(_T_781, _T_782) @[Cat.scala 29:58] - node _T_791 = cat(_T_790, _T_789) @[Cat.scala 29:58] - node tdata_wrdata_r = cat(_T_791, _T_788) @[Cat.scala 29:58] - node _T_792 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] - node _T_793 = eq(_T_792, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] - node _T_794 = and(io.dec_csr_wen_r_mod, _T_793) @[dec_tlu_ctl.scala 2222:70] - node _T_795 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2222:121] - node _T_796 = and(_T_794, _T_795) @[dec_tlu_ctl.scala 2222:112] - node _T_797 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2222:154] - node _T_798 = not(_T_797) @[dec_tlu_ctl.scala 2222:138] - node _T_799 = or(_T_798, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] - node _T_800 = and(_T_796, _T_799) @[dec_tlu_ctl.scala 2222:135] - node _T_801 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] - node _T_802 = eq(_T_801, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] - node _T_803 = and(io.dec_csr_wen_r_mod, _T_802) @[dec_tlu_ctl.scala 2222:70] - node _T_804 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2222:121] - node _T_805 = and(_T_803, _T_804) @[dec_tlu_ctl.scala 2222:112] - node _T_806 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2222:154] - node _T_807 = not(_T_806) @[dec_tlu_ctl.scala 2222:138] - node _T_808 = or(_T_807, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] - node _T_809 = and(_T_805, _T_808) @[dec_tlu_ctl.scala 2222:135] - node _T_810 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] - node _T_811 = eq(_T_810, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] - node _T_812 = and(io.dec_csr_wen_r_mod, _T_811) @[dec_tlu_ctl.scala 2222:70] - node _T_813 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2222:121] - node _T_814 = and(_T_812, _T_813) @[dec_tlu_ctl.scala 2222:112] - node _T_815 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2222:154] - node _T_816 = not(_T_815) @[dec_tlu_ctl.scala 2222:138] - node _T_817 = or(_T_816, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] - node _T_818 = and(_T_814, _T_817) @[dec_tlu_ctl.scala 2222:135] - node _T_819 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] - node _T_820 = eq(_T_819, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] - node _T_821 = and(io.dec_csr_wen_r_mod, _T_820) @[dec_tlu_ctl.scala 2222:70] - node _T_822 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2222:121] - node _T_823 = and(_T_821, _T_822) @[dec_tlu_ctl.scala 2222:112] - node _T_824 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2222:154] - node _T_825 = not(_T_824) @[dec_tlu_ctl.scala 2222:138] - node _T_826 = or(_T_825, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] - node _T_827 = and(_T_823, _T_826) @[dec_tlu_ctl.scala 2222:135] + node _T_774 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2174:62] + node _T_775 = eq(_T_774, UInt<12>("h07a0")) @[dec_tlu_ctl.scala 2174:69] + node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_775) @[dec_tlu_ctl.scala 2174:40] + node _T_776 = bits(wr_mtsel_r, 0, 0) @[dec_tlu_ctl.scala 2175:32] + node _T_777 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 2175:59] + node mtsel_ns = mux(_T_776, _T_777, mtsel) @[dec_tlu_ctl.scala 2175:20] + reg _T_778 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2177:43] + _T_778 <= mtsel_ns @[dec_tlu_ctl.scala 2177:43] + mtsel <= _T_778 @[dec_tlu_ctl.scala 2177:8] + node _T_779 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2212:38] + node _T_780 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2212:64] + node _T_781 = not(_T_780) @[dec_tlu_ctl.scala 2212:44] + node tdata_load = and(_T_779, _T_781) @[dec_tlu_ctl.scala 2212:42] + node _T_782 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2214:40] + node _T_783 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2214:66] + node _T_784 = not(_T_783) @[dec_tlu_ctl.scala 2214:46] + node tdata_opcode = and(_T_782, _T_784) @[dec_tlu_ctl.scala 2214:44] + node _T_785 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2216:41] + node _T_786 = and(_T_785, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2216:46] + node _T_787 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 2216:90] + node tdata_action = and(_T_786, _T_787) @[dec_tlu_ctl.scala 2216:69] + node _T_788 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2218:47] + node _T_789 = and(_T_788, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2218:52] + node _T_790 = bits(io.dec_csr_wrdata_r, 20, 19) @[dec_tlu_ctl.scala 2218:94] + node _T_791 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2218:136] + node _T_792 = bits(io.dec_csr_wrdata_r, 7, 6) @[dec_tlu_ctl.scala 2219:43] + node _T_793 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 2219:83] + node _T_794 = cat(_T_793, tdata_load) @[Cat.scala 29:58] + node _T_795 = cat(_T_792, tdata_opcode) @[Cat.scala 29:58] + node _T_796 = cat(_T_795, _T_794) @[Cat.scala 29:58] + node _T_797 = cat(tdata_action, _T_791) @[Cat.scala 29:58] + node _T_798 = cat(_T_789, _T_790) @[Cat.scala 29:58] + node _T_799 = cat(_T_798, _T_797) @[Cat.scala 29:58] + node tdata_wrdata_r = cat(_T_799, _T_796) @[Cat.scala 29:58] + node _T_800 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] + node _T_801 = eq(_T_800, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] + node _T_802 = and(io.dec_csr_wen_r_mod, _T_801) @[dec_tlu_ctl.scala 2222:70] + node _T_803 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2222:121] + node _T_804 = and(_T_802, _T_803) @[dec_tlu_ctl.scala 2222:112] + node _T_805 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2222:154] + node _T_806 = not(_T_805) @[dec_tlu_ctl.scala 2222:138] + node _T_807 = or(_T_806, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] + node _T_808 = and(_T_804, _T_807) @[dec_tlu_ctl.scala 2222:135] + node _T_809 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] + node _T_810 = eq(_T_809, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] + node _T_811 = and(io.dec_csr_wen_r_mod, _T_810) @[dec_tlu_ctl.scala 2222:70] + node _T_812 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2222:121] + node _T_813 = and(_T_811, _T_812) @[dec_tlu_ctl.scala 2222:112] + node _T_814 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2222:154] + node _T_815 = not(_T_814) @[dec_tlu_ctl.scala 2222:138] + node _T_816 = or(_T_815, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] + node _T_817 = and(_T_813, _T_816) @[dec_tlu_ctl.scala 2222:135] + node _T_818 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] + node _T_819 = eq(_T_818, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] + node _T_820 = and(io.dec_csr_wen_r_mod, _T_819) @[dec_tlu_ctl.scala 2222:70] + node _T_821 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2222:121] + node _T_822 = and(_T_820, _T_821) @[dec_tlu_ctl.scala 2222:112] + node _T_823 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2222:154] + node _T_824 = not(_T_823) @[dec_tlu_ctl.scala 2222:138] + node _T_825 = or(_T_824, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] + node _T_826 = and(_T_822, _T_825) @[dec_tlu_ctl.scala 2222:135] + node _T_827 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] + node _T_828 = eq(_T_827, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] + node _T_829 = and(io.dec_csr_wen_r_mod, _T_828) @[dec_tlu_ctl.scala 2222:70] + node _T_830 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2222:121] + node _T_831 = and(_T_829, _T_830) @[dec_tlu_ctl.scala 2222:112] + node _T_832 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2222:154] + node _T_833 = not(_T_832) @[dec_tlu_ctl.scala 2222:138] + node _T_834 = or(_T_833, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] + node _T_835 = and(_T_831, _T_834) @[dec_tlu_ctl.scala 2222:135] wire wr_mtdata1_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2222:42] - wr_mtdata1_t_r[0] <= _T_800 @[dec_tlu_ctl.scala 2222:42] - wr_mtdata1_t_r[1] <= _T_809 @[dec_tlu_ctl.scala 2222:42] - wr_mtdata1_t_r[2] <= _T_818 @[dec_tlu_ctl.scala 2222:42] - wr_mtdata1_t_r[3] <= _T_827 @[dec_tlu_ctl.scala 2222:42] - node _T_828 = bits(wr_mtdata1_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2223:68] - node _T_829 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2223:111] - node _T_830 = bits(io.update_hit_bit_r, 0, 0) @[dec_tlu_ctl.scala 2223:135] - node _T_831 = bits(io.mtdata1_t[0], 8, 8) @[dec_tlu_ctl.scala 2223:156] - node _T_832 = or(_T_830, _T_831) @[dec_tlu_ctl.scala 2223:139] - node _T_833 = bits(io.mtdata1_t[0], 7, 0) @[dec_tlu_ctl.scala 2223:176] - node _T_834 = cat(_T_829, _T_832) @[Cat.scala 29:58] - node _T_835 = cat(_T_834, _T_833) @[Cat.scala 29:58] - node _T_836 = mux(_T_828, tdata_wrdata_r, _T_835) @[dec_tlu_ctl.scala 2223:49] - node _T_837 = bits(wr_mtdata1_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2223:68] - node _T_838 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2223:111] - node _T_839 = bits(io.update_hit_bit_r, 1, 1) @[dec_tlu_ctl.scala 2223:135] - node _T_840 = bits(io.mtdata1_t[1], 8, 8) @[dec_tlu_ctl.scala 2223:156] - node _T_841 = or(_T_839, _T_840) @[dec_tlu_ctl.scala 2223:139] - node _T_842 = bits(io.mtdata1_t[1], 7, 0) @[dec_tlu_ctl.scala 2223:176] - node _T_843 = cat(_T_838, _T_841) @[Cat.scala 29:58] - node _T_844 = cat(_T_843, _T_842) @[Cat.scala 29:58] - node _T_845 = mux(_T_837, tdata_wrdata_r, _T_844) @[dec_tlu_ctl.scala 2223:49] - node _T_846 = bits(wr_mtdata1_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2223:68] - node _T_847 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2223:111] - node _T_848 = bits(io.update_hit_bit_r, 2, 2) @[dec_tlu_ctl.scala 2223:135] - node _T_849 = bits(io.mtdata1_t[2], 8, 8) @[dec_tlu_ctl.scala 2223:156] - node _T_850 = or(_T_848, _T_849) @[dec_tlu_ctl.scala 2223:139] - node _T_851 = bits(io.mtdata1_t[2], 7, 0) @[dec_tlu_ctl.scala 2223:176] - node _T_852 = cat(_T_847, _T_850) @[Cat.scala 29:58] - node _T_853 = cat(_T_852, _T_851) @[Cat.scala 29:58] - node _T_854 = mux(_T_846, tdata_wrdata_r, _T_853) @[dec_tlu_ctl.scala 2223:49] - node _T_855 = bits(wr_mtdata1_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2223:68] - node _T_856 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2223:111] - node _T_857 = bits(io.update_hit_bit_r, 3, 3) @[dec_tlu_ctl.scala 2223:135] - node _T_858 = bits(io.mtdata1_t[3], 8, 8) @[dec_tlu_ctl.scala 2223:156] - node _T_859 = or(_T_857, _T_858) @[dec_tlu_ctl.scala 2223:139] - node _T_860 = bits(io.mtdata1_t[3], 7, 0) @[dec_tlu_ctl.scala 2223:176] - node _T_861 = cat(_T_856, _T_859) @[Cat.scala 29:58] - node _T_862 = cat(_T_861, _T_860) @[Cat.scala 29:58] - node _T_863 = mux(_T_855, tdata_wrdata_r, _T_862) @[dec_tlu_ctl.scala 2223:49] + wr_mtdata1_t_r[0] <= _T_808 @[dec_tlu_ctl.scala 2222:42] + wr_mtdata1_t_r[1] <= _T_817 @[dec_tlu_ctl.scala 2222:42] + wr_mtdata1_t_r[2] <= _T_826 @[dec_tlu_ctl.scala 2222:42] + wr_mtdata1_t_r[3] <= _T_835 @[dec_tlu_ctl.scala 2222:42] + node _T_836 = bits(wr_mtdata1_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2223:68] + node _T_837 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2223:111] + node _T_838 = bits(io.update_hit_bit_r, 0, 0) @[dec_tlu_ctl.scala 2223:135] + node _T_839 = bits(io.mtdata1_t[0], 8, 8) @[dec_tlu_ctl.scala 2223:156] + node _T_840 = or(_T_838, _T_839) @[dec_tlu_ctl.scala 2223:139] + node _T_841 = bits(io.mtdata1_t[0], 7, 0) @[dec_tlu_ctl.scala 2223:176] + node _T_842 = cat(_T_837, _T_840) @[Cat.scala 29:58] + node _T_843 = cat(_T_842, _T_841) @[Cat.scala 29:58] + node _T_844 = mux(_T_836, tdata_wrdata_r, _T_843) @[dec_tlu_ctl.scala 2223:49] + node _T_845 = bits(wr_mtdata1_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2223:68] + node _T_846 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2223:111] + node _T_847 = bits(io.update_hit_bit_r, 1, 1) @[dec_tlu_ctl.scala 2223:135] + node _T_848 = bits(io.mtdata1_t[1], 8, 8) @[dec_tlu_ctl.scala 2223:156] + node _T_849 = or(_T_847, _T_848) @[dec_tlu_ctl.scala 2223:139] + node _T_850 = bits(io.mtdata1_t[1], 7, 0) @[dec_tlu_ctl.scala 2223:176] + node _T_851 = cat(_T_846, _T_849) @[Cat.scala 29:58] + node _T_852 = cat(_T_851, _T_850) @[Cat.scala 29:58] + node _T_853 = mux(_T_845, tdata_wrdata_r, _T_852) @[dec_tlu_ctl.scala 2223:49] + node _T_854 = bits(wr_mtdata1_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2223:68] + node _T_855 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2223:111] + node _T_856 = bits(io.update_hit_bit_r, 2, 2) @[dec_tlu_ctl.scala 2223:135] + node _T_857 = bits(io.mtdata1_t[2], 8, 8) @[dec_tlu_ctl.scala 2223:156] + node _T_858 = or(_T_856, _T_857) @[dec_tlu_ctl.scala 2223:139] + node _T_859 = bits(io.mtdata1_t[2], 7, 0) @[dec_tlu_ctl.scala 2223:176] + node _T_860 = cat(_T_855, _T_858) @[Cat.scala 29:58] + node _T_861 = cat(_T_860, _T_859) @[Cat.scala 29:58] + node _T_862 = mux(_T_854, tdata_wrdata_r, _T_861) @[dec_tlu_ctl.scala 2223:49] + node _T_863 = bits(wr_mtdata1_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2223:68] + node _T_864 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2223:111] + node _T_865 = bits(io.update_hit_bit_r, 3, 3) @[dec_tlu_ctl.scala 2223:135] + node _T_866 = bits(io.mtdata1_t[3], 8, 8) @[dec_tlu_ctl.scala 2223:156] + node _T_867 = or(_T_865, _T_866) @[dec_tlu_ctl.scala 2223:139] + node _T_868 = bits(io.mtdata1_t[3], 7, 0) @[dec_tlu_ctl.scala 2223:176] + node _T_869 = cat(_T_864, _T_867) @[Cat.scala 29:58] + node _T_870 = cat(_T_869, _T_868) @[Cat.scala 29:58] + node _T_871 = mux(_T_863, tdata_wrdata_r, _T_870) @[dec_tlu_ctl.scala 2223:49] wire mtdata1_t_ns : UInt<10>[4] @[dec_tlu_ctl.scala 2223:40] - mtdata1_t_ns[0] <= _T_836 @[dec_tlu_ctl.scala 2223:40] - mtdata1_t_ns[1] <= _T_845 @[dec_tlu_ctl.scala 2223:40] - mtdata1_t_ns[2] <= _T_854 @[dec_tlu_ctl.scala 2223:40] - mtdata1_t_ns[3] <= _T_863 @[dec_tlu_ctl.scala 2223:40] - reg _T_864 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2225:74] - _T_864 <= mtdata1_t_ns[0] @[dec_tlu_ctl.scala 2225:74] - io.mtdata1_t[0] <= _T_864 @[dec_tlu_ctl.scala 2225:39] - reg _T_865 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2225:74] - _T_865 <= mtdata1_t_ns[1] @[dec_tlu_ctl.scala 2225:74] - io.mtdata1_t[1] <= _T_865 @[dec_tlu_ctl.scala 2225:39] - reg _T_866 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2225:74] - _T_866 <= mtdata1_t_ns[2] @[dec_tlu_ctl.scala 2225:74] - io.mtdata1_t[2] <= _T_866 @[dec_tlu_ctl.scala 2225:39] - reg _T_867 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2225:74] - _T_867 <= mtdata1_t_ns[3] @[dec_tlu_ctl.scala 2225:74] - io.mtdata1_t[3] <= _T_867 @[dec_tlu_ctl.scala 2225:39] - node _T_868 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2228:58] - node _T_869 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2228:104] - node _T_870 = bits(io.mtdata1_t[0], 8, 7) @[dec_tlu_ctl.scala 2228:142] - node _T_871 = bits(io.mtdata1_t[0], 6, 5) @[dec_tlu_ctl.scala 2228:174] - node _T_872 = bits(io.mtdata1_t[0], 4, 3) @[dec_tlu_ctl.scala 2228:206] - node _T_873 = bits(io.mtdata1_t[0], 2, 0) @[dec_tlu_ctl.scala 2228:238] - node _T_874 = cat(UInt<3>("h00"), _T_873) @[Cat.scala 29:58] - node _T_875 = cat(_T_871, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_876 = cat(_T_875, _T_872) @[Cat.scala 29:58] - node _T_877 = cat(_T_876, _T_874) @[Cat.scala 29:58] - node _T_878 = cat(_T_870, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_879 = cat(UInt<4>("h02"), _T_869) @[Cat.scala 29:58] - node _T_880 = cat(_T_879, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_881 = cat(_T_880, _T_878) @[Cat.scala 29:58] - node _T_882 = cat(_T_881, _T_877) @[Cat.scala 29:58] - node _T_883 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2228:58] - node _T_884 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2228:104] - node _T_885 = bits(io.mtdata1_t[1], 8, 7) @[dec_tlu_ctl.scala 2228:142] - node _T_886 = bits(io.mtdata1_t[1], 6, 5) @[dec_tlu_ctl.scala 2228:174] - node _T_887 = bits(io.mtdata1_t[1], 4, 3) @[dec_tlu_ctl.scala 2228:206] - node _T_888 = bits(io.mtdata1_t[1], 2, 0) @[dec_tlu_ctl.scala 2228:238] - node _T_889 = cat(UInt<3>("h00"), _T_888) @[Cat.scala 29:58] - node _T_890 = cat(_T_886, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_891 = cat(_T_890, _T_887) @[Cat.scala 29:58] - node _T_892 = cat(_T_891, _T_889) @[Cat.scala 29:58] - node _T_893 = cat(_T_885, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_894 = cat(UInt<4>("h02"), _T_884) @[Cat.scala 29:58] - node _T_895 = cat(_T_894, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_896 = cat(_T_895, _T_893) @[Cat.scala 29:58] - node _T_897 = cat(_T_896, _T_892) @[Cat.scala 29:58] - node _T_898 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2228:58] - node _T_899 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2228:104] - node _T_900 = bits(io.mtdata1_t[2], 8, 7) @[dec_tlu_ctl.scala 2228:142] - node _T_901 = bits(io.mtdata1_t[2], 6, 5) @[dec_tlu_ctl.scala 2228:174] - node _T_902 = bits(io.mtdata1_t[2], 4, 3) @[dec_tlu_ctl.scala 2228:206] - node _T_903 = bits(io.mtdata1_t[2], 2, 0) @[dec_tlu_ctl.scala 2228:238] - node _T_904 = cat(UInt<3>("h00"), _T_903) @[Cat.scala 29:58] - node _T_905 = cat(_T_901, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_906 = cat(_T_905, _T_902) @[Cat.scala 29:58] - node _T_907 = cat(_T_906, _T_904) @[Cat.scala 29:58] - node _T_908 = cat(_T_900, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_909 = cat(UInt<4>("h02"), _T_899) @[Cat.scala 29:58] - node _T_910 = cat(_T_909, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_911 = cat(_T_910, _T_908) @[Cat.scala 29:58] - node _T_912 = cat(_T_911, _T_907) @[Cat.scala 29:58] - node _T_913 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2228:58] - node _T_914 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2228:104] - node _T_915 = bits(io.mtdata1_t[3], 8, 7) @[dec_tlu_ctl.scala 2228:142] - node _T_916 = bits(io.mtdata1_t[3], 6, 5) @[dec_tlu_ctl.scala 2228:174] - node _T_917 = bits(io.mtdata1_t[3], 4, 3) @[dec_tlu_ctl.scala 2228:206] - node _T_918 = bits(io.mtdata1_t[3], 2, 0) @[dec_tlu_ctl.scala 2228:238] - node _T_919 = cat(UInt<3>("h00"), _T_918) @[Cat.scala 29:58] - node _T_920 = cat(_T_916, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_921 = cat(_T_920, _T_917) @[Cat.scala 29:58] - node _T_922 = cat(_T_921, _T_919) @[Cat.scala 29:58] - node _T_923 = cat(_T_915, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_924 = cat(UInt<4>("h02"), _T_914) @[Cat.scala 29:58] - node _T_925 = cat(_T_924, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_926 = cat(_T_925, _T_923) @[Cat.scala 29:58] - node _T_927 = cat(_T_926, _T_922) @[Cat.scala 29:58] - node _T_928 = mux(_T_868, _T_882, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_929 = mux(_T_883, _T_897, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_930 = mux(_T_898, _T_912, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_931 = mux(_T_913, _T_927, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_932 = or(_T_928, _T_929) @[Mux.scala 27:72] - node _T_933 = or(_T_932, _T_930) @[Mux.scala 27:72] - node _T_934 = or(_T_933, _T_931) @[Mux.scala 27:72] + mtdata1_t_ns[0] <= _T_844 @[dec_tlu_ctl.scala 2223:40] + mtdata1_t_ns[1] <= _T_853 @[dec_tlu_ctl.scala 2223:40] + mtdata1_t_ns[2] <= _T_862 @[dec_tlu_ctl.scala 2223:40] + mtdata1_t_ns[3] <= _T_871 @[dec_tlu_ctl.scala 2223:40] + reg _T_872 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2225:74] + _T_872 <= mtdata1_t_ns[0] @[dec_tlu_ctl.scala 2225:74] + io.mtdata1_t[0] <= _T_872 @[dec_tlu_ctl.scala 2225:39] + reg _T_873 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2225:74] + _T_873 <= mtdata1_t_ns[1] @[dec_tlu_ctl.scala 2225:74] + io.mtdata1_t[1] <= _T_873 @[dec_tlu_ctl.scala 2225:39] + reg _T_874 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2225:74] + _T_874 <= mtdata1_t_ns[2] @[dec_tlu_ctl.scala 2225:74] + io.mtdata1_t[2] <= _T_874 @[dec_tlu_ctl.scala 2225:39] + reg _T_875 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2225:74] + _T_875 <= mtdata1_t_ns[3] @[dec_tlu_ctl.scala 2225:74] + io.mtdata1_t[3] <= _T_875 @[dec_tlu_ctl.scala 2225:39] + node _T_876 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2228:58] + node _T_877 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2228:104] + node _T_878 = bits(io.mtdata1_t[0], 8, 7) @[dec_tlu_ctl.scala 2228:142] + node _T_879 = bits(io.mtdata1_t[0], 6, 5) @[dec_tlu_ctl.scala 2228:174] + node _T_880 = bits(io.mtdata1_t[0], 4, 3) @[dec_tlu_ctl.scala 2228:206] + node _T_881 = bits(io.mtdata1_t[0], 2, 0) @[dec_tlu_ctl.scala 2228:238] + node _T_882 = cat(UInt<3>("h00"), _T_881) @[Cat.scala 29:58] + node _T_883 = cat(_T_879, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_884 = cat(_T_883, _T_880) @[Cat.scala 29:58] + node _T_885 = cat(_T_884, _T_882) @[Cat.scala 29:58] + node _T_886 = cat(_T_878, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_887 = cat(UInt<4>("h02"), _T_877) @[Cat.scala 29:58] + node _T_888 = cat(_T_887, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_889 = cat(_T_888, _T_886) @[Cat.scala 29:58] + node _T_890 = cat(_T_889, _T_885) @[Cat.scala 29:58] + node _T_891 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2228:58] + node _T_892 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2228:104] + node _T_893 = bits(io.mtdata1_t[1], 8, 7) @[dec_tlu_ctl.scala 2228:142] + node _T_894 = bits(io.mtdata1_t[1], 6, 5) @[dec_tlu_ctl.scala 2228:174] + node _T_895 = bits(io.mtdata1_t[1], 4, 3) @[dec_tlu_ctl.scala 2228:206] + node _T_896 = bits(io.mtdata1_t[1], 2, 0) @[dec_tlu_ctl.scala 2228:238] + node _T_897 = cat(UInt<3>("h00"), _T_896) @[Cat.scala 29:58] + node _T_898 = cat(_T_894, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_899 = cat(_T_898, _T_895) @[Cat.scala 29:58] + node _T_900 = cat(_T_899, _T_897) @[Cat.scala 29:58] + node _T_901 = cat(_T_893, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_902 = cat(UInt<4>("h02"), _T_892) @[Cat.scala 29:58] + node _T_903 = cat(_T_902, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_904 = cat(_T_903, _T_901) @[Cat.scala 29:58] + node _T_905 = cat(_T_904, _T_900) @[Cat.scala 29:58] + node _T_906 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2228:58] + node _T_907 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2228:104] + node _T_908 = bits(io.mtdata1_t[2], 8, 7) @[dec_tlu_ctl.scala 2228:142] + node _T_909 = bits(io.mtdata1_t[2], 6, 5) @[dec_tlu_ctl.scala 2228:174] + node _T_910 = bits(io.mtdata1_t[2], 4, 3) @[dec_tlu_ctl.scala 2228:206] + node _T_911 = bits(io.mtdata1_t[2], 2, 0) @[dec_tlu_ctl.scala 2228:238] + node _T_912 = cat(UInt<3>("h00"), _T_911) @[Cat.scala 29:58] + node _T_913 = cat(_T_909, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_914 = cat(_T_913, _T_910) @[Cat.scala 29:58] + node _T_915 = cat(_T_914, _T_912) @[Cat.scala 29:58] + node _T_916 = cat(_T_908, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_917 = cat(UInt<4>("h02"), _T_907) @[Cat.scala 29:58] + node _T_918 = cat(_T_917, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_919 = cat(_T_918, _T_916) @[Cat.scala 29:58] + node _T_920 = cat(_T_919, _T_915) @[Cat.scala 29:58] + node _T_921 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2228:58] + node _T_922 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2228:104] + node _T_923 = bits(io.mtdata1_t[3], 8, 7) @[dec_tlu_ctl.scala 2228:142] + node _T_924 = bits(io.mtdata1_t[3], 6, 5) @[dec_tlu_ctl.scala 2228:174] + node _T_925 = bits(io.mtdata1_t[3], 4, 3) @[dec_tlu_ctl.scala 2228:206] + node _T_926 = bits(io.mtdata1_t[3], 2, 0) @[dec_tlu_ctl.scala 2228:238] + node _T_927 = cat(UInt<3>("h00"), _T_926) @[Cat.scala 29:58] + node _T_928 = cat(_T_924, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_929 = cat(_T_928, _T_925) @[Cat.scala 29:58] + node _T_930 = cat(_T_929, _T_927) @[Cat.scala 29:58] + node _T_931 = cat(_T_923, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_932 = cat(UInt<4>("h02"), _T_922) @[Cat.scala 29:58] + node _T_933 = cat(_T_932, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_934 = cat(_T_933, _T_931) @[Cat.scala 29:58] + node _T_935 = cat(_T_934, _T_930) @[Cat.scala 29:58] + node _T_936 = mux(_T_876, _T_890, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_937 = mux(_T_891, _T_905, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_938 = mux(_T_906, _T_920, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_939 = mux(_T_921, _T_935, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_940 = or(_T_936, _T_937) @[Mux.scala 27:72] + node _T_941 = or(_T_940, _T_938) @[Mux.scala 27:72] + node _T_942 = or(_T_941, _T_939) @[Mux.scala 27:72] wire mtdata1_tsel_out : UInt<32> @[Mux.scala 27:72] - mtdata1_tsel_out <= _T_934 @[Mux.scala 27:72] - node _T_935 = bits(io.mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 2230:58] - io.trigger_pkt_any[0].select <= _T_935 @[dec_tlu_ctl.scala 2230:40] - node _T_936 = bits(io.mtdata1_t[0], 4, 4) @[dec_tlu_ctl.scala 2231:61] - io.trigger_pkt_any[0].match_pkt <= _T_936 @[dec_tlu_ctl.scala 2231:43] - node _T_937 = bits(io.mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 2232:58] - io.trigger_pkt_any[0].store <= _T_937 @[dec_tlu_ctl.scala 2232:40] - node _T_938 = bits(io.mtdata1_t[0], 0, 0) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[0].load <= _T_938 @[dec_tlu_ctl.scala 2233:40] - node _T_939 = bits(io.mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[0].execute <= _T_939 @[dec_tlu_ctl.scala 2234:40] - node _T_940 = bits(io.mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 2235:58] - io.trigger_pkt_any[0].m <= _T_940 @[dec_tlu_ctl.scala 2235:40] - node _T_941 = bits(io.mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 2230:58] - io.trigger_pkt_any[1].select <= _T_941 @[dec_tlu_ctl.scala 2230:40] - node _T_942 = bits(io.mtdata1_t[1], 4, 4) @[dec_tlu_ctl.scala 2231:61] - io.trigger_pkt_any[1].match_pkt <= _T_942 @[dec_tlu_ctl.scala 2231:43] - node _T_943 = bits(io.mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 2232:58] - io.trigger_pkt_any[1].store <= _T_943 @[dec_tlu_ctl.scala 2232:40] - node _T_944 = bits(io.mtdata1_t[1], 0, 0) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[1].load <= _T_944 @[dec_tlu_ctl.scala 2233:40] - node _T_945 = bits(io.mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[1].execute <= _T_945 @[dec_tlu_ctl.scala 2234:40] - node _T_946 = bits(io.mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 2235:58] - io.trigger_pkt_any[1].m <= _T_946 @[dec_tlu_ctl.scala 2235:40] - node _T_947 = bits(io.mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 2230:58] - io.trigger_pkt_any[2].select <= _T_947 @[dec_tlu_ctl.scala 2230:40] - node _T_948 = bits(io.mtdata1_t[2], 4, 4) @[dec_tlu_ctl.scala 2231:61] - io.trigger_pkt_any[2].match_pkt <= _T_948 @[dec_tlu_ctl.scala 2231:43] - node _T_949 = bits(io.mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 2232:58] - io.trigger_pkt_any[2].store <= _T_949 @[dec_tlu_ctl.scala 2232:40] - node _T_950 = bits(io.mtdata1_t[2], 0, 0) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[2].load <= _T_950 @[dec_tlu_ctl.scala 2233:40] - node _T_951 = bits(io.mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[2].execute <= _T_951 @[dec_tlu_ctl.scala 2234:40] - node _T_952 = bits(io.mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 2235:58] - io.trigger_pkt_any[2].m <= _T_952 @[dec_tlu_ctl.scala 2235:40] - node _T_953 = bits(io.mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 2230:58] - io.trigger_pkt_any[3].select <= _T_953 @[dec_tlu_ctl.scala 2230:40] - node _T_954 = bits(io.mtdata1_t[3], 4, 4) @[dec_tlu_ctl.scala 2231:61] - io.trigger_pkt_any[3].match_pkt <= _T_954 @[dec_tlu_ctl.scala 2231:43] - node _T_955 = bits(io.mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 2232:58] - io.trigger_pkt_any[3].store <= _T_955 @[dec_tlu_ctl.scala 2232:40] - node _T_956 = bits(io.mtdata1_t[3], 0, 0) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[3].load <= _T_956 @[dec_tlu_ctl.scala 2233:40] - node _T_957 = bits(io.mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[3].execute <= _T_957 @[dec_tlu_ctl.scala 2234:40] - node _T_958 = bits(io.mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 2235:58] - io.trigger_pkt_any[3].m <= _T_958 @[dec_tlu_ctl.scala 2235:40] - node _T_959 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] - node _T_960 = eq(_T_959, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] - node _T_961 = and(io.dec_csr_wen_r_mod, _T_960) @[dec_tlu_ctl.scala 2242:69] - node _T_962 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2242:120] - node _T_963 = and(_T_961, _T_962) @[dec_tlu_ctl.scala 2242:111] - node _T_964 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2242:153] - node _T_965 = not(_T_964) @[dec_tlu_ctl.scala 2242:137] - node _T_966 = or(_T_965, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] - node _T_967 = and(_T_963, _T_966) @[dec_tlu_ctl.scala 2242:134] - node _T_968 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] - node _T_969 = eq(_T_968, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] - node _T_970 = and(io.dec_csr_wen_r_mod, _T_969) @[dec_tlu_ctl.scala 2242:69] - node _T_971 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2242:120] - node _T_972 = and(_T_970, _T_971) @[dec_tlu_ctl.scala 2242:111] - node _T_973 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2242:153] - node _T_974 = not(_T_973) @[dec_tlu_ctl.scala 2242:137] - node _T_975 = or(_T_974, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] - node _T_976 = and(_T_972, _T_975) @[dec_tlu_ctl.scala 2242:134] - node _T_977 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] - node _T_978 = eq(_T_977, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] - node _T_979 = and(io.dec_csr_wen_r_mod, _T_978) @[dec_tlu_ctl.scala 2242:69] - node _T_980 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2242:120] - node _T_981 = and(_T_979, _T_980) @[dec_tlu_ctl.scala 2242:111] - node _T_982 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2242:153] - node _T_983 = not(_T_982) @[dec_tlu_ctl.scala 2242:137] - node _T_984 = or(_T_983, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] - node _T_985 = and(_T_981, _T_984) @[dec_tlu_ctl.scala 2242:134] - node _T_986 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] - node _T_987 = eq(_T_986, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] - node _T_988 = and(io.dec_csr_wen_r_mod, _T_987) @[dec_tlu_ctl.scala 2242:69] - node _T_989 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2242:120] - node _T_990 = and(_T_988, _T_989) @[dec_tlu_ctl.scala 2242:111] - node _T_991 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2242:153] - node _T_992 = not(_T_991) @[dec_tlu_ctl.scala 2242:137] - node _T_993 = or(_T_992, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] - node _T_994 = and(_T_990, _T_993) @[dec_tlu_ctl.scala 2242:134] + mtdata1_tsel_out <= _T_942 @[Mux.scala 27:72] + node _T_943 = bits(io.mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 2230:58] + io.trigger_pkt_any[0].select <= _T_943 @[dec_tlu_ctl.scala 2230:40] + node _T_944 = bits(io.mtdata1_t[0], 4, 4) @[dec_tlu_ctl.scala 2231:61] + io.trigger_pkt_any[0].match_pkt <= _T_944 @[dec_tlu_ctl.scala 2231:43] + node _T_945 = bits(io.mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 2232:58] + io.trigger_pkt_any[0].store <= _T_945 @[dec_tlu_ctl.scala 2232:40] + node _T_946 = bits(io.mtdata1_t[0], 0, 0) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[0].load <= _T_946 @[dec_tlu_ctl.scala 2233:40] + node _T_947 = bits(io.mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[0].execute <= _T_947 @[dec_tlu_ctl.scala 2234:40] + node _T_948 = bits(io.mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 2235:58] + io.trigger_pkt_any[0].m <= _T_948 @[dec_tlu_ctl.scala 2235:40] + node _T_949 = bits(io.mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 2230:58] + io.trigger_pkt_any[1].select <= _T_949 @[dec_tlu_ctl.scala 2230:40] + node _T_950 = bits(io.mtdata1_t[1], 4, 4) @[dec_tlu_ctl.scala 2231:61] + io.trigger_pkt_any[1].match_pkt <= _T_950 @[dec_tlu_ctl.scala 2231:43] + node _T_951 = bits(io.mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 2232:58] + io.trigger_pkt_any[1].store <= _T_951 @[dec_tlu_ctl.scala 2232:40] + node _T_952 = bits(io.mtdata1_t[1], 0, 0) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[1].load <= _T_952 @[dec_tlu_ctl.scala 2233:40] + node _T_953 = bits(io.mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[1].execute <= _T_953 @[dec_tlu_ctl.scala 2234:40] + node _T_954 = bits(io.mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 2235:58] + io.trigger_pkt_any[1].m <= _T_954 @[dec_tlu_ctl.scala 2235:40] + node _T_955 = bits(io.mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 2230:58] + io.trigger_pkt_any[2].select <= _T_955 @[dec_tlu_ctl.scala 2230:40] + node _T_956 = bits(io.mtdata1_t[2], 4, 4) @[dec_tlu_ctl.scala 2231:61] + io.trigger_pkt_any[2].match_pkt <= _T_956 @[dec_tlu_ctl.scala 2231:43] + node _T_957 = bits(io.mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 2232:58] + io.trigger_pkt_any[2].store <= _T_957 @[dec_tlu_ctl.scala 2232:40] + node _T_958 = bits(io.mtdata1_t[2], 0, 0) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[2].load <= _T_958 @[dec_tlu_ctl.scala 2233:40] + node _T_959 = bits(io.mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[2].execute <= _T_959 @[dec_tlu_ctl.scala 2234:40] + node _T_960 = bits(io.mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 2235:58] + io.trigger_pkt_any[2].m <= _T_960 @[dec_tlu_ctl.scala 2235:40] + node _T_961 = bits(io.mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 2230:58] + io.trigger_pkt_any[3].select <= _T_961 @[dec_tlu_ctl.scala 2230:40] + node _T_962 = bits(io.mtdata1_t[3], 4, 4) @[dec_tlu_ctl.scala 2231:61] + io.trigger_pkt_any[3].match_pkt <= _T_962 @[dec_tlu_ctl.scala 2231:43] + node _T_963 = bits(io.mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 2232:58] + io.trigger_pkt_any[3].store <= _T_963 @[dec_tlu_ctl.scala 2232:40] + node _T_964 = bits(io.mtdata1_t[3], 0, 0) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[3].load <= _T_964 @[dec_tlu_ctl.scala 2233:40] + node _T_965 = bits(io.mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[3].execute <= _T_965 @[dec_tlu_ctl.scala 2234:40] + node _T_966 = bits(io.mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 2235:58] + io.trigger_pkt_any[3].m <= _T_966 @[dec_tlu_ctl.scala 2235:40] + node _T_967 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] + node _T_968 = eq(_T_967, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] + node _T_969 = and(io.dec_csr_wen_r_mod, _T_968) @[dec_tlu_ctl.scala 2242:69] + node _T_970 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2242:120] + node _T_971 = and(_T_969, _T_970) @[dec_tlu_ctl.scala 2242:111] + node _T_972 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2242:153] + node _T_973 = not(_T_972) @[dec_tlu_ctl.scala 2242:137] + node _T_974 = or(_T_973, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] + node _T_975 = and(_T_971, _T_974) @[dec_tlu_ctl.scala 2242:134] + node _T_976 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] + node _T_977 = eq(_T_976, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] + node _T_978 = and(io.dec_csr_wen_r_mod, _T_977) @[dec_tlu_ctl.scala 2242:69] + node _T_979 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2242:120] + node _T_980 = and(_T_978, _T_979) @[dec_tlu_ctl.scala 2242:111] + node _T_981 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2242:153] + node _T_982 = not(_T_981) @[dec_tlu_ctl.scala 2242:137] + node _T_983 = or(_T_982, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] + node _T_984 = and(_T_980, _T_983) @[dec_tlu_ctl.scala 2242:134] + node _T_985 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] + node _T_986 = eq(_T_985, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] + node _T_987 = and(io.dec_csr_wen_r_mod, _T_986) @[dec_tlu_ctl.scala 2242:69] + node _T_988 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2242:120] + node _T_989 = and(_T_987, _T_988) @[dec_tlu_ctl.scala 2242:111] + node _T_990 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2242:153] + node _T_991 = not(_T_990) @[dec_tlu_ctl.scala 2242:137] + node _T_992 = or(_T_991, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] + node _T_993 = and(_T_989, _T_992) @[dec_tlu_ctl.scala 2242:134] + node _T_994 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] + node _T_995 = eq(_T_994, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] + node _T_996 = and(io.dec_csr_wen_r_mod, _T_995) @[dec_tlu_ctl.scala 2242:69] + node _T_997 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2242:120] + node _T_998 = and(_T_996, _T_997) @[dec_tlu_ctl.scala 2242:111] + node _T_999 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2242:153] + node _T_1000 = not(_T_999) @[dec_tlu_ctl.scala 2242:137] + node _T_1001 = or(_T_1000, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] + node _T_1002 = and(_T_998, _T_1001) @[dec_tlu_ctl.scala 2242:134] wire wr_mtdata2_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2242:42] - wr_mtdata2_t_r[0] <= _T_967 @[dec_tlu_ctl.scala 2242:42] - wr_mtdata2_t_r[1] <= _T_976 @[dec_tlu_ctl.scala 2242:42] - wr_mtdata2_t_r[2] <= _T_985 @[dec_tlu_ctl.scala 2242:42] - wr_mtdata2_t_r[3] <= _T_994 @[dec_tlu_ctl.scala 2242:42] - node _T_995 = bits(wr_mtdata2_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2243:84] + wr_mtdata2_t_r[0] <= _T_975 @[dec_tlu_ctl.scala 2242:42] + wr_mtdata2_t_r[1] <= _T_984 @[dec_tlu_ctl.scala 2242:42] + wr_mtdata2_t_r[2] <= _T_993 @[dec_tlu_ctl.scala 2242:42] + wr_mtdata2_t_r[3] <= _T_1002 @[dec_tlu_ctl.scala 2242:42] + node _T_1003 = bits(wr_mtdata2_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2243:84] inst rvclkhdr_22 of rvclkhdr_742 @[lib.scala 368:23] rvclkhdr_22.clock <= clock rvclkhdr_22.reset <= reset rvclkhdr_22.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_22.io.en <= _T_995 @[lib.scala 371:17] + rvclkhdr_22.io.en <= _T_1003 @[lib.scala 371:17] rvclkhdr_22.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_996 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_996 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[0] <= _T_996 @[dec_tlu_ctl.scala 2243:36] - node _T_997 = bits(wr_mtdata2_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2243:84] + reg _T_1004 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1004 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[0] <= _T_1004 @[dec_tlu_ctl.scala 2243:36] + node _T_1005 = bits(wr_mtdata2_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2243:84] inst rvclkhdr_23 of rvclkhdr_743 @[lib.scala 368:23] rvclkhdr_23.clock <= clock rvclkhdr_23.reset <= reset rvclkhdr_23.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_23.io.en <= _T_997 @[lib.scala 371:17] + rvclkhdr_23.io.en <= _T_1005 @[lib.scala 371:17] rvclkhdr_23.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_998 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_998 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[1] <= _T_998 @[dec_tlu_ctl.scala 2243:36] - node _T_999 = bits(wr_mtdata2_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2243:84] + reg _T_1006 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1006 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[1] <= _T_1006 @[dec_tlu_ctl.scala 2243:36] + node _T_1007 = bits(wr_mtdata2_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2243:84] inst rvclkhdr_24 of rvclkhdr_744 @[lib.scala 368:23] rvclkhdr_24.clock <= clock rvclkhdr_24.reset <= reset rvclkhdr_24.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_24.io.en <= _T_999 @[lib.scala 371:17] + rvclkhdr_24.io.en <= _T_1007 @[lib.scala 371:17] rvclkhdr_24.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_1000 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_1000 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[2] <= _T_1000 @[dec_tlu_ctl.scala 2243:36] - node _T_1001 = bits(wr_mtdata2_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2243:84] + reg _T_1008 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1008 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[2] <= _T_1008 @[dec_tlu_ctl.scala 2243:36] + node _T_1009 = bits(wr_mtdata2_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2243:84] inst rvclkhdr_25 of rvclkhdr_745 @[lib.scala 368:23] rvclkhdr_25.clock <= clock rvclkhdr_25.reset <= reset rvclkhdr_25.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_25.io.en <= _T_1001 @[lib.scala 371:17] + rvclkhdr_25.io.en <= _T_1009 @[lib.scala 371:17] rvclkhdr_25.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_1002 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_1002 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[3] <= _T_1002 @[dec_tlu_ctl.scala 2243:36] - node _T_1003 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2247:57] - node _T_1004 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2247:57] - node _T_1005 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2247:57] - node _T_1006 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2247:57] - node _T_1007 = mux(_T_1003, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1008 = mux(_T_1004, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1009 = mux(_T_1005, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1010 = mux(_T_1006, mtdata2_t[3], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1011 = or(_T_1007, _T_1008) @[Mux.scala 27:72] - node _T_1012 = or(_T_1011, _T_1009) @[Mux.scala 27:72] - node _T_1013 = or(_T_1012, _T_1010) @[Mux.scala 27:72] + reg _T_1010 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1010 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[3] <= _T_1010 @[dec_tlu_ctl.scala 2243:36] + node _T_1011 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2247:57] + node _T_1012 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2247:57] + node _T_1013 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2247:57] + node _T_1014 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2247:57] + node _T_1015 = mux(_T_1011, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1016 = mux(_T_1012, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1017 = mux(_T_1013, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1018 = mux(_T_1014, mtdata2_t[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1019 = or(_T_1015, _T_1016) @[Mux.scala 27:72] + node _T_1020 = or(_T_1019, _T_1017) @[Mux.scala 27:72] + node _T_1021 = or(_T_1020, _T_1018) @[Mux.scala 27:72] wire mtdata2_tsel_out : UInt<32> @[Mux.scala 27:72] - mtdata2_tsel_out <= _T_1013 @[Mux.scala 27:72] + mtdata2_tsel_out <= _T_1021 @[Mux.scala 27:72] io.trigger_pkt_any[0].tdata2 <= mtdata2_t[0] @[dec_tlu_ctl.scala 2248:51] io.trigger_pkt_any[1].tdata2 <= mtdata2_t[1] @[dec_tlu_ctl.scala 2248:51] io.trigger_pkt_any[2].tdata2 <= mtdata2_t[2] @[dec_tlu_ctl.scala 2248:51] @@ -74394,246 +74402,238 @@ circuit quasar_wrapper : mhpme_vec[1] <= mhpme4 @[dec_tlu_ctl.scala 2259:15] mhpme_vec[2] <= mhpme5 @[dec_tlu_ctl.scala 2260:15] mhpme_vec[3] <= mhpme6 @[dec_tlu_ctl.scala 2261:15] - node _T_1014 = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15] - node _T_1015 = mux(_T_1014, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1015) @[dec_tlu_ctl.scala 2267:59] + node _T_1022 = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15] + node _T_1023 = mux(_T_1022, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1023) @[dec_tlu_ctl.scala 2267:59] wire mhpmc_inc_r : UInt<1>[4] @[dec_tlu_ctl.scala 2268:24] wire mhpmc_inc_r_d1 : UInt<1>[4] @[dec_tlu_ctl.scala 2269:27] - node _T_1016 = bits(mcountinhibit, 3, 3) @[dec_tlu_ctl.scala 2273:38] - node _T_1017 = not(_T_1016) @[dec_tlu_ctl.scala 2273:24] - node _T_1018 = eq(mhpme_vec[0], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] - node _T_1019 = bits(_T_1018, 0, 0) @[dec_tlu_ctl.scala 2274:62] - node _T_1020 = eq(mhpme_vec[0], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] - node _T_1021 = bits(_T_1020, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1022 = eq(mhpme_vec[0], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] - node _T_1023 = bits(_T_1022, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1024 = eq(mhpme_vec[0], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] - node _T_1025 = bits(_T_1024, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1026 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] - node _T_1027 = and(io.tlu_i0_commit_cmt, _T_1026) @[dec_tlu_ctl.scala 2277:94] - node _T_1028 = eq(mhpme_vec[0], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] - node _T_1029 = bits(_T_1028, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1030 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] - node _T_1031 = and(io.tlu_i0_commit_cmt, _T_1030) @[dec_tlu_ctl.scala 2278:94] - node _T_1032 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] - node _T_1033 = and(_T_1031, _T_1032) @[dec_tlu_ctl.scala 2278:115] - node _T_1034 = eq(mhpme_vec[0], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] - node _T_1035 = bits(_T_1034, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1036 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] - node _T_1037 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] - node _T_1038 = and(_T_1036, _T_1037) @[dec_tlu_ctl.scala 2279:115] - node _T_1039 = eq(mhpme_vec[0], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] - node _T_1040 = bits(_T_1039, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1041 = eq(mhpme_vec[0], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] - node _T_1042 = bits(_T_1041, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1043 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] - node _T_1044 = bits(_T_1043, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1045 = eq(mhpme_vec[0], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] - node _T_1046 = bits(_T_1045, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1047 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] - node _T_1048 = eq(mhpme_vec[0], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] - node _T_1049 = bits(_T_1048, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1050 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] - node _T_1051 = eq(mhpme_vec[0], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] - node _T_1052 = bits(_T_1051, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1053 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] - node _T_1054 = eq(mhpme_vec[0], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] - node _T_1055 = bits(_T_1054, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1056 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] - node _T_1057 = eq(mhpme_vec[0], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] - node _T_1058 = bits(_T_1057, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1059 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] - node _T_1060 = and(_T_1059, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] - node _T_1061 = eq(mhpme_vec[0], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] - node _T_1062 = bits(_T_1061, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1063 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] - node _T_1064 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] - node _T_1065 = and(_T_1063, _T_1064) @[dec_tlu_ctl.scala 2288:101] - node _T_1066 = eq(mhpme_vec[0], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] - node _T_1067 = bits(_T_1066, 0, 0) @[dec_tlu_ctl.scala 2289:59] - node _T_1068 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] - node _T_1069 = eq(mhpme_vec[0], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] - node _T_1070 = bits(_T_1069, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1071 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] - node _T_1072 = eq(mhpme_vec[0], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] - node _T_1073 = bits(_T_1072, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1074 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] - node _T_1075 = eq(mhpme_vec[0], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] - node _T_1076 = bits(_T_1075, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1077 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] - node _T_1078 = eq(mhpme_vec[0], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] - node _T_1079 = bits(_T_1078, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1080 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] - node _T_1081 = eq(mhpme_vec[0], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] - node _T_1082 = bits(_T_1081, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1083 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] - node _T_1084 = eq(mhpme_vec[0], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] - node _T_1085 = bits(_T_1084, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1086 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] - node _T_1087 = eq(mhpme_vec[0], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] - node _T_1088 = bits(_T_1087, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1089 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] - node _T_1090 = eq(mhpme_vec[0], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] - node _T_1091 = bits(_T_1090, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1092 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] - node _T_1093 = eq(mhpme_vec[0], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] - node _T_1094 = bits(_T_1093, 0, 0) @[dec_tlu_ctl.scala 2298:59] - node _T_1095 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] - node _T_1096 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] - node _T_1097 = or(_T_1095, _T_1096) @[dec_tlu_ctl.scala 2298:101] - node _T_1098 = eq(mhpme_vec[0], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] - node _T_1099 = bits(_T_1098, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1100 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] - node _T_1101 = eq(mhpme_vec[0], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] - node _T_1102 = bits(_T_1101, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1103 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] - node _T_1104 = eq(mhpme_vec[0], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] - node _T_1105 = bits(_T_1104, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1106 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] - node _T_1107 = eq(mhpme_vec[0], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] - node _T_1108 = bits(_T_1107, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1109 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] - node _T_1110 = bits(_T_1109, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1111 = eq(mhpme_vec[0], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] - node _T_1112 = bits(_T_1111, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1113 = eq(mhpme_vec[0], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] - node _T_1114 = bits(_T_1113, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1115 = eq(mhpme_vec[0], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] - node _T_1116 = bits(_T_1115, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1117 = eq(mhpme_vec[0], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] - node _T_1118 = bits(_T_1117, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1119 = eq(mhpme_vec[0], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] - node _T_1120 = bits(_T_1119, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1121 = eq(mhpme_vec[0], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] - node _T_1122 = bits(_T_1121, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1123 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] - node _T_1124 = or(_T_1123, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] - node _T_1125 = eq(mhpme_vec[0], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] - node _T_1126 = bits(_T_1125, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1127 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] - node _T_1128 = or(_T_1127, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] - node _T_1129 = eq(mhpme_vec[0], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] - node _T_1130 = bits(_T_1129, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1131 = eq(mhpme_vec[0], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] - node _T_1132 = bits(_T_1131, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1133 = eq(mhpme_vec[0], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] - node _T_1134 = bits(_T_1133, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1135 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] - node _T_1136 = and(_T_1135, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] - node _T_1137 = eq(mhpme_vec[0], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] - node _T_1138 = bits(_T_1137, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1139 = eq(mhpme_vec[0], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] - node _T_1140 = bits(_T_1139, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_1141 = eq(mhpme_vec[0], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] - node _T_1142 = bits(_T_1141, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_1143 = eq(mhpme_vec[0], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] - node _T_1144 = bits(_T_1143, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_1145 = eq(mhpme_vec[0], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] - node _T_1146 = bits(_T_1145, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_1147 = eq(mhpme_vec[0], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] - node _T_1148 = bits(_T_1147, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_1149 = eq(mhpme_vec[0], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] - node _T_1150 = bits(_T_1149, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_1151 = eq(mhpme_vec[0], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] - node _T_1152 = bits(_T_1151, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_1153 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] - node _T_1154 = bits(_T_1153, 0, 0) @[dec_tlu_ctl.scala 2321:84] - node _T_1155 = not(_T_1154) @[dec_tlu_ctl.scala 2321:73] - node _T_1156 = eq(mhpme_vec[0], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] - node _T_1157 = bits(_T_1156, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_1158 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] - node _T_1159 = bits(_T_1158, 0, 0) @[dec_tlu_ctl.scala 2322:84] - node _T_1160 = not(_T_1159) @[dec_tlu_ctl.scala 2322:73] - node _T_1161 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] - node _T_1162 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] - node _T_1163 = and(_T_1161, _T_1162) @[dec_tlu_ctl.scala 2322:113] - node _T_1164 = orr(_T_1163) @[dec_tlu_ctl.scala 2322:125] - node _T_1165 = and(_T_1160, _T_1164) @[dec_tlu_ctl.scala 2322:98] - node _T_1166 = eq(mhpme_vec[0], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] - node _T_1167 = bits(_T_1166, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_1168 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] - node _T_1169 = eq(mhpme_vec[0], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] - node _T_1170 = bits(_T_1169, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_1171 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] - node _T_1172 = eq(mhpme_vec[0], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] - node _T_1173 = bits(_T_1172, 0, 0) @[dec_tlu_ctl.scala 2325:62] - node _T_1174 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] - node _T_1175 = eq(mhpme_vec[0], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] - node _T_1176 = bits(_T_1175, 0, 0) @[dec_tlu_ctl.scala 2327:62] - node _T_1177 = eq(mhpme_vec[0], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] - node _T_1178 = bits(_T_1177, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_1179 = eq(mhpme_vec[0], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] - node _T_1180 = bits(_T_1179, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_1181 = eq(mhpme_vec[0], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] - node _T_1182 = bits(_T_1181, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_1183 = eq(mhpme_vec[0], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] - node _T_1184 = bits(_T_1183, 0, 0) @[dec_tlu_ctl.scala 2331:62] - node _T_1185 = mux(_T_1019, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1186 = mux(_T_1021, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1187 = mux(_T_1023, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1188 = mux(_T_1025, _T_1027, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1189 = mux(_T_1029, _T_1033, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1190 = mux(_T_1035, _T_1038, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1191 = mux(_T_1040, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1192 = mux(_T_1042, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1193 = mux(_T_1044, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1194 = mux(_T_1046, _T_1047, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1195 = mux(_T_1049, _T_1050, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1196 = mux(_T_1052, _T_1053, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1197 = mux(_T_1055, _T_1056, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1198 = mux(_T_1058, _T_1060, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1199 = mux(_T_1062, _T_1065, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1200 = mux(_T_1067, _T_1068, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1201 = mux(_T_1070, _T_1071, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1202 = mux(_T_1073, _T_1074, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1203 = mux(_T_1076, _T_1077, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1204 = mux(_T_1079, _T_1080, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1205 = mux(_T_1082, _T_1083, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1206 = mux(_T_1085, _T_1086, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1207 = mux(_T_1088, _T_1089, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1208 = mux(_T_1091, _T_1092, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1209 = mux(_T_1094, _T_1097, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1210 = mux(_T_1099, _T_1100, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1211 = mux(_T_1102, _T_1103, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1212 = mux(_T_1105, _T_1106, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1213 = mux(_T_1108, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1214 = mux(_T_1110, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1215 = mux(_T_1112, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1216 = mux(_T_1114, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1217 = mux(_T_1116, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1218 = mux(_T_1118, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1219 = mux(_T_1120, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1220 = mux(_T_1122, _T_1124, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1221 = mux(_T_1126, _T_1128, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1222 = mux(_T_1130, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1223 = mux(_T_1132, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1224 = mux(_T_1134, _T_1136, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1225 = mux(_T_1138, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1226 = mux(_T_1140, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1227 = mux(_T_1142, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1228 = mux(_T_1144, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1229 = mux(_T_1146, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1230 = mux(_T_1148, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1231 = mux(_T_1150, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1232 = mux(_T_1152, _T_1155, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1233 = mux(_T_1157, _T_1165, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1234 = mux(_T_1167, _T_1168, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1235 = mux(_T_1170, _T_1171, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1236 = mux(_T_1173, _T_1174, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1237 = mux(_T_1176, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1238 = mux(_T_1178, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1239 = mux(_T_1180, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1240 = mux(_T_1182, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1241 = mux(_T_1184, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1242 = or(_T_1185, _T_1186) @[Mux.scala 27:72] - node _T_1243 = or(_T_1242, _T_1187) @[Mux.scala 27:72] - node _T_1244 = or(_T_1243, _T_1188) @[Mux.scala 27:72] - node _T_1245 = or(_T_1244, _T_1189) @[Mux.scala 27:72] - node _T_1246 = or(_T_1245, _T_1190) @[Mux.scala 27:72] - node _T_1247 = or(_T_1246, _T_1191) @[Mux.scala 27:72] - node _T_1248 = or(_T_1247, _T_1192) @[Mux.scala 27:72] - node _T_1249 = or(_T_1248, _T_1193) @[Mux.scala 27:72] - node _T_1250 = or(_T_1249, _T_1194) @[Mux.scala 27:72] + node _T_1024 = bits(mcountinhibit, 3, 3) @[dec_tlu_ctl.scala 2273:38] + node _T_1025 = not(_T_1024) @[dec_tlu_ctl.scala 2273:24] + node _T_1026 = eq(mhpme_vec[0], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] + node _T_1027 = bits(_T_1026, 0, 0) @[dec_tlu_ctl.scala 2274:62] + node _T_1028 = eq(mhpme_vec[0], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] + node _T_1029 = bits(_T_1028, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1030 = eq(mhpme_vec[0], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] + node _T_1031 = bits(_T_1030, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1032 = eq(mhpme_vec[0], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] + node _T_1033 = bits(_T_1032, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1034 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] + node _T_1035 = and(io.tlu_i0_commit_cmt, _T_1034) @[dec_tlu_ctl.scala 2277:94] + node _T_1036 = eq(mhpme_vec[0], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] + node _T_1037 = bits(_T_1036, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1038 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] + node _T_1039 = and(io.tlu_i0_commit_cmt, _T_1038) @[dec_tlu_ctl.scala 2278:94] + node _T_1040 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] + node _T_1041 = and(_T_1039, _T_1040) @[dec_tlu_ctl.scala 2278:115] + node _T_1042 = eq(mhpme_vec[0], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] + node _T_1043 = bits(_T_1042, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1044 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] + node _T_1045 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] + node _T_1046 = and(_T_1044, _T_1045) @[dec_tlu_ctl.scala 2279:115] + node _T_1047 = eq(mhpme_vec[0], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] + node _T_1048 = bits(_T_1047, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1049 = eq(mhpme_vec[0], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] + node _T_1050 = bits(_T_1049, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1051 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] + node _T_1052 = bits(_T_1051, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1053 = eq(mhpme_vec[0], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] + node _T_1054 = bits(_T_1053, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1055 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] + node _T_1056 = eq(mhpme_vec[0], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] + node _T_1057 = bits(_T_1056, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1058 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] + node _T_1059 = eq(mhpme_vec[0], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] + node _T_1060 = bits(_T_1059, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1061 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] + node _T_1062 = eq(mhpme_vec[0], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] + node _T_1063 = bits(_T_1062, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1064 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] + node _T_1065 = eq(mhpme_vec[0], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] + node _T_1066 = bits(_T_1065, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1067 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] + node _T_1068 = and(_T_1067, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] + node _T_1069 = eq(mhpme_vec[0], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] + node _T_1070 = bits(_T_1069, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1071 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] + node _T_1072 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] + node _T_1073 = and(_T_1071, _T_1072) @[dec_tlu_ctl.scala 2288:101] + node _T_1074 = eq(mhpme_vec[0], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] + node _T_1075 = bits(_T_1074, 0, 0) @[dec_tlu_ctl.scala 2289:59] + node _T_1076 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] + node _T_1077 = eq(mhpme_vec[0], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] + node _T_1078 = bits(_T_1077, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1079 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] + node _T_1080 = eq(mhpme_vec[0], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] + node _T_1081 = bits(_T_1080, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1082 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] + node _T_1083 = eq(mhpme_vec[0], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] + node _T_1084 = bits(_T_1083, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1085 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] + node _T_1086 = eq(mhpme_vec[0], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] + node _T_1087 = bits(_T_1086, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1088 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] + node _T_1089 = eq(mhpme_vec[0], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] + node _T_1090 = bits(_T_1089, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1091 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] + node _T_1092 = eq(mhpme_vec[0], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] + node _T_1093 = bits(_T_1092, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1094 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] + node _T_1095 = eq(mhpme_vec[0], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] + node _T_1096 = bits(_T_1095, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1097 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] + node _T_1098 = eq(mhpme_vec[0], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] + node _T_1099 = bits(_T_1098, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1100 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] + node _T_1101 = eq(mhpme_vec[0], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] + node _T_1102 = bits(_T_1101, 0, 0) @[dec_tlu_ctl.scala 2298:59] + node _T_1103 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] + node _T_1104 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] + node _T_1105 = or(_T_1103, _T_1104) @[dec_tlu_ctl.scala 2298:101] + node _T_1106 = eq(mhpme_vec[0], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] + node _T_1107 = bits(_T_1106, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1108 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] + node _T_1109 = eq(mhpme_vec[0], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] + node _T_1110 = bits(_T_1109, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1111 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] + node _T_1112 = eq(mhpme_vec[0], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] + node _T_1113 = bits(_T_1112, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1114 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] + node _T_1115 = eq(mhpme_vec[0], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] + node _T_1116 = bits(_T_1115, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1117 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] + node _T_1118 = bits(_T_1117, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1119 = eq(mhpme_vec[0], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] + node _T_1120 = bits(_T_1119, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1121 = eq(mhpme_vec[0], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] + node _T_1122 = bits(_T_1121, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1123 = eq(mhpme_vec[0], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] + node _T_1124 = bits(_T_1123, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1125 = eq(mhpme_vec[0], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] + node _T_1126 = bits(_T_1125, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1127 = eq(mhpme_vec[0], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] + node _T_1128 = bits(_T_1127, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1129 = eq(mhpme_vec[0], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] + node _T_1130 = bits(_T_1129, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1131 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] + node _T_1132 = or(_T_1131, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] + node _T_1133 = eq(mhpme_vec[0], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] + node _T_1134 = bits(_T_1133, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1135 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] + node _T_1136 = or(_T_1135, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] + node _T_1137 = eq(mhpme_vec[0], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] + node _T_1138 = bits(_T_1137, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1139 = eq(mhpme_vec[0], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] + node _T_1140 = bits(_T_1139, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1141 = eq(mhpme_vec[0], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] + node _T_1142 = bits(_T_1141, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1143 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] + node _T_1144 = and(_T_1143, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] + node _T_1145 = eq(mhpme_vec[0], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] + node _T_1146 = bits(_T_1145, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_1147 = eq(mhpme_vec[0], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] + node _T_1148 = bits(_T_1147, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_1149 = eq(mhpme_vec[0], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] + node _T_1150 = bits(_T_1149, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_1151 = eq(mhpme_vec[0], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] + node _T_1152 = bits(_T_1151, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_1153 = eq(mhpme_vec[0], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] + node _T_1154 = bits(_T_1153, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_1155 = eq(mhpme_vec[0], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] + node _T_1156 = bits(_T_1155, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_1157 = eq(mhpme_vec[0], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] + node _T_1158 = bits(_T_1157, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_1159 = eq(mhpme_vec[0], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] + node _T_1160 = bits(_T_1159, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_1161 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] + node _T_1162 = bits(_T_1161, 0, 0) @[dec_tlu_ctl.scala 2321:84] + node _T_1163 = not(_T_1162) @[dec_tlu_ctl.scala 2321:73] + node _T_1164 = eq(mhpme_vec[0], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] + node _T_1165 = bits(_T_1164, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_1166 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] + node _T_1167 = bits(_T_1166, 0, 0) @[dec_tlu_ctl.scala 2322:84] + node _T_1168 = not(_T_1167) @[dec_tlu_ctl.scala 2322:73] + node _T_1169 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] + node _T_1170 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] + node _T_1171 = and(_T_1169, _T_1170) @[dec_tlu_ctl.scala 2322:113] + node _T_1172 = orr(_T_1171) @[dec_tlu_ctl.scala 2322:125] + node _T_1173 = and(_T_1168, _T_1172) @[dec_tlu_ctl.scala 2322:98] + node _T_1174 = eq(mhpme_vec[0], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] + node _T_1175 = bits(_T_1174, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_1176 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] + node _T_1177 = eq(mhpme_vec[0], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] + node _T_1178 = bits(_T_1177, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_1179 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] + node _T_1180 = eq(mhpme_vec[0], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] + node _T_1181 = bits(_T_1180, 0, 0) @[dec_tlu_ctl.scala 2325:62] + node _T_1182 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] + node _T_1183 = eq(mhpme_vec[0], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] + node _T_1184 = bits(_T_1183, 0, 0) @[dec_tlu_ctl.scala 2327:62] + node _T_1185 = eq(mhpme_vec[0], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] + node _T_1186 = bits(_T_1185, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_1187 = eq(mhpme_vec[0], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] + node _T_1188 = bits(_T_1187, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_1189 = eq(mhpme_vec[0], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] + node _T_1190 = bits(_T_1189, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_1191 = eq(mhpme_vec[0], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] + node _T_1192 = bits(_T_1191, 0, 0) @[dec_tlu_ctl.scala 2331:62] + node _T_1193 = mux(_T_1027, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1194 = mux(_T_1029, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1195 = mux(_T_1031, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1196 = mux(_T_1033, _T_1035, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1197 = mux(_T_1037, _T_1041, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1198 = mux(_T_1043, _T_1046, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1199 = mux(_T_1048, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1200 = mux(_T_1050, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1201 = mux(_T_1052, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1202 = mux(_T_1054, _T_1055, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1203 = mux(_T_1057, _T_1058, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1204 = mux(_T_1060, _T_1061, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1205 = mux(_T_1063, _T_1064, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1206 = mux(_T_1066, _T_1068, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1207 = mux(_T_1070, _T_1073, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1208 = mux(_T_1075, _T_1076, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1209 = mux(_T_1078, _T_1079, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1210 = mux(_T_1081, _T_1082, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1211 = mux(_T_1084, _T_1085, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1212 = mux(_T_1087, _T_1088, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1213 = mux(_T_1090, _T_1091, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1214 = mux(_T_1093, _T_1094, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1215 = mux(_T_1096, _T_1097, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1216 = mux(_T_1099, _T_1100, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1217 = mux(_T_1102, _T_1105, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1218 = mux(_T_1107, _T_1108, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1219 = mux(_T_1110, _T_1111, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1220 = mux(_T_1113, _T_1114, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1221 = mux(_T_1116, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1222 = mux(_T_1118, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1223 = mux(_T_1120, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1224 = mux(_T_1122, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1225 = mux(_T_1124, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1226 = mux(_T_1126, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1227 = mux(_T_1128, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1228 = mux(_T_1130, _T_1132, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1229 = mux(_T_1134, _T_1136, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1230 = mux(_T_1138, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1231 = mux(_T_1140, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1232 = mux(_T_1142, _T_1144, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1233 = mux(_T_1146, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1234 = mux(_T_1148, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1235 = mux(_T_1150, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1236 = mux(_T_1152, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1237 = mux(_T_1154, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1238 = mux(_T_1156, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1239 = mux(_T_1158, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1240 = mux(_T_1160, _T_1163, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1241 = mux(_T_1165, _T_1173, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1242 = mux(_T_1175, _T_1176, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1243 = mux(_T_1178, _T_1179, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1244 = mux(_T_1181, _T_1182, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1245 = mux(_T_1184, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1246 = mux(_T_1186, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1247 = mux(_T_1188, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1248 = mux(_T_1190, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1249 = mux(_T_1192, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1250 = or(_T_1193, _T_1194) @[Mux.scala 27:72] node _T_1251 = or(_T_1250, _T_1195) @[Mux.scala 27:72] node _T_1252 = or(_T_1251, _T_1196) @[Mux.scala 27:72] node _T_1253 = or(_T_1252, _T_1197) @[Mux.scala 27:72] @@ -74681,245 +74681,245 @@ circuit quasar_wrapper : node _T_1295 = or(_T_1294, _T_1239) @[Mux.scala 27:72] node _T_1296 = or(_T_1295, _T_1240) @[Mux.scala 27:72] node _T_1297 = or(_T_1296, _T_1241) @[Mux.scala 27:72] - wire _T_1298 : UInt<1> @[Mux.scala 27:72] - _T_1298 <= _T_1297 @[Mux.scala 27:72] - node _T_1299 = and(_T_1017, _T_1298) @[dec_tlu_ctl.scala 2273:44] - mhpmc_inc_r[0] <= _T_1299 @[dec_tlu_ctl.scala 2273:19] - node _T_1300 = bits(mcountinhibit, 4, 4) @[dec_tlu_ctl.scala 2273:38] - node _T_1301 = not(_T_1300) @[dec_tlu_ctl.scala 2273:24] - node _T_1302 = eq(mhpme_vec[1], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] - node _T_1303 = bits(_T_1302, 0, 0) @[dec_tlu_ctl.scala 2274:62] - node _T_1304 = eq(mhpme_vec[1], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] - node _T_1305 = bits(_T_1304, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1306 = eq(mhpme_vec[1], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] - node _T_1307 = bits(_T_1306, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1308 = eq(mhpme_vec[1], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] - node _T_1309 = bits(_T_1308, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1310 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] - node _T_1311 = and(io.tlu_i0_commit_cmt, _T_1310) @[dec_tlu_ctl.scala 2277:94] - node _T_1312 = eq(mhpme_vec[1], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] - node _T_1313 = bits(_T_1312, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1314 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] - node _T_1315 = and(io.tlu_i0_commit_cmt, _T_1314) @[dec_tlu_ctl.scala 2278:94] - node _T_1316 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] - node _T_1317 = and(_T_1315, _T_1316) @[dec_tlu_ctl.scala 2278:115] - node _T_1318 = eq(mhpme_vec[1], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] - node _T_1319 = bits(_T_1318, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1320 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] - node _T_1321 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] - node _T_1322 = and(_T_1320, _T_1321) @[dec_tlu_ctl.scala 2279:115] - node _T_1323 = eq(mhpme_vec[1], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] - node _T_1324 = bits(_T_1323, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1325 = eq(mhpme_vec[1], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] - node _T_1326 = bits(_T_1325, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1327 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] - node _T_1328 = bits(_T_1327, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1329 = eq(mhpme_vec[1], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] - node _T_1330 = bits(_T_1329, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1331 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] - node _T_1332 = eq(mhpme_vec[1], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] - node _T_1333 = bits(_T_1332, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1334 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] - node _T_1335 = eq(mhpme_vec[1], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] - node _T_1336 = bits(_T_1335, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1337 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] - node _T_1338 = eq(mhpme_vec[1], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] - node _T_1339 = bits(_T_1338, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1340 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] - node _T_1341 = eq(mhpme_vec[1], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] - node _T_1342 = bits(_T_1341, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1343 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] - node _T_1344 = and(_T_1343, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] - node _T_1345 = eq(mhpme_vec[1], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] - node _T_1346 = bits(_T_1345, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1347 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] - node _T_1348 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] - node _T_1349 = and(_T_1347, _T_1348) @[dec_tlu_ctl.scala 2288:101] - node _T_1350 = eq(mhpme_vec[1], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] - node _T_1351 = bits(_T_1350, 0, 0) @[dec_tlu_ctl.scala 2289:59] - node _T_1352 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] - node _T_1353 = eq(mhpme_vec[1], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] - node _T_1354 = bits(_T_1353, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1355 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] - node _T_1356 = eq(mhpme_vec[1], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] - node _T_1357 = bits(_T_1356, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1358 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] - node _T_1359 = eq(mhpme_vec[1], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] - node _T_1360 = bits(_T_1359, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1361 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] - node _T_1362 = eq(mhpme_vec[1], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] - node _T_1363 = bits(_T_1362, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1364 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] - node _T_1365 = eq(mhpme_vec[1], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] - node _T_1366 = bits(_T_1365, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1367 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] - node _T_1368 = eq(mhpme_vec[1], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] - node _T_1369 = bits(_T_1368, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1370 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] - node _T_1371 = eq(mhpme_vec[1], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] - node _T_1372 = bits(_T_1371, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1373 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] - node _T_1374 = eq(mhpme_vec[1], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] - node _T_1375 = bits(_T_1374, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1376 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] - node _T_1377 = eq(mhpme_vec[1], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] - node _T_1378 = bits(_T_1377, 0, 0) @[dec_tlu_ctl.scala 2298:59] - node _T_1379 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] - node _T_1380 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] - node _T_1381 = or(_T_1379, _T_1380) @[dec_tlu_ctl.scala 2298:101] - node _T_1382 = eq(mhpme_vec[1], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] - node _T_1383 = bits(_T_1382, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1384 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] - node _T_1385 = eq(mhpme_vec[1], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] - node _T_1386 = bits(_T_1385, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1387 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] - node _T_1388 = eq(mhpme_vec[1], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] - node _T_1389 = bits(_T_1388, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1390 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] - node _T_1391 = eq(mhpme_vec[1], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] - node _T_1392 = bits(_T_1391, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1393 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] - node _T_1394 = bits(_T_1393, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1395 = eq(mhpme_vec[1], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] - node _T_1396 = bits(_T_1395, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1397 = eq(mhpme_vec[1], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] - node _T_1398 = bits(_T_1397, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1399 = eq(mhpme_vec[1], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] - node _T_1400 = bits(_T_1399, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1401 = eq(mhpme_vec[1], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] - node _T_1402 = bits(_T_1401, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1403 = eq(mhpme_vec[1], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] - node _T_1404 = bits(_T_1403, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1405 = eq(mhpme_vec[1], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] - node _T_1406 = bits(_T_1405, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1407 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] - node _T_1408 = or(_T_1407, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] - node _T_1409 = eq(mhpme_vec[1], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] - node _T_1410 = bits(_T_1409, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1411 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] - node _T_1412 = or(_T_1411, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] - node _T_1413 = eq(mhpme_vec[1], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] - node _T_1414 = bits(_T_1413, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1415 = eq(mhpme_vec[1], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] - node _T_1416 = bits(_T_1415, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1417 = eq(mhpme_vec[1], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] - node _T_1418 = bits(_T_1417, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1419 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] - node _T_1420 = and(_T_1419, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] - node _T_1421 = eq(mhpme_vec[1], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] - node _T_1422 = bits(_T_1421, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1423 = eq(mhpme_vec[1], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] - node _T_1424 = bits(_T_1423, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_1425 = eq(mhpme_vec[1], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] - node _T_1426 = bits(_T_1425, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_1427 = eq(mhpme_vec[1], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] - node _T_1428 = bits(_T_1427, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_1429 = eq(mhpme_vec[1], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] - node _T_1430 = bits(_T_1429, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_1431 = eq(mhpme_vec[1], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] - node _T_1432 = bits(_T_1431, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_1433 = eq(mhpme_vec[1], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] - node _T_1434 = bits(_T_1433, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_1435 = eq(mhpme_vec[1], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] - node _T_1436 = bits(_T_1435, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_1437 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] - node _T_1438 = bits(_T_1437, 0, 0) @[dec_tlu_ctl.scala 2321:84] - node _T_1439 = not(_T_1438) @[dec_tlu_ctl.scala 2321:73] - node _T_1440 = eq(mhpme_vec[1], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] - node _T_1441 = bits(_T_1440, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_1442 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] - node _T_1443 = bits(_T_1442, 0, 0) @[dec_tlu_ctl.scala 2322:84] - node _T_1444 = not(_T_1443) @[dec_tlu_ctl.scala 2322:73] - node _T_1445 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] - node _T_1446 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] - node _T_1447 = and(_T_1445, _T_1446) @[dec_tlu_ctl.scala 2322:113] - node _T_1448 = orr(_T_1447) @[dec_tlu_ctl.scala 2322:125] - node _T_1449 = and(_T_1444, _T_1448) @[dec_tlu_ctl.scala 2322:98] - node _T_1450 = eq(mhpme_vec[1], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] - node _T_1451 = bits(_T_1450, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_1452 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] - node _T_1453 = eq(mhpme_vec[1], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] - node _T_1454 = bits(_T_1453, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_1455 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] - node _T_1456 = eq(mhpme_vec[1], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] - node _T_1457 = bits(_T_1456, 0, 0) @[dec_tlu_ctl.scala 2325:62] - node _T_1458 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] - node _T_1459 = eq(mhpme_vec[1], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] - node _T_1460 = bits(_T_1459, 0, 0) @[dec_tlu_ctl.scala 2327:62] - node _T_1461 = eq(mhpme_vec[1], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] - node _T_1462 = bits(_T_1461, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_1463 = eq(mhpme_vec[1], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] - node _T_1464 = bits(_T_1463, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_1465 = eq(mhpme_vec[1], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] - node _T_1466 = bits(_T_1465, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_1467 = eq(mhpme_vec[1], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] - node _T_1468 = bits(_T_1467, 0, 0) @[dec_tlu_ctl.scala 2331:62] - node _T_1469 = mux(_T_1303, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1470 = mux(_T_1305, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1471 = mux(_T_1307, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1472 = mux(_T_1309, _T_1311, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1473 = mux(_T_1313, _T_1317, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1474 = mux(_T_1319, _T_1322, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1475 = mux(_T_1324, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1476 = mux(_T_1326, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1477 = mux(_T_1328, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1478 = mux(_T_1330, _T_1331, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1479 = mux(_T_1333, _T_1334, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1480 = mux(_T_1336, _T_1337, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1481 = mux(_T_1339, _T_1340, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1482 = mux(_T_1342, _T_1344, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1483 = mux(_T_1346, _T_1349, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1484 = mux(_T_1351, _T_1352, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1485 = mux(_T_1354, _T_1355, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1486 = mux(_T_1357, _T_1358, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1487 = mux(_T_1360, _T_1361, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1488 = mux(_T_1363, _T_1364, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1489 = mux(_T_1366, _T_1367, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1490 = mux(_T_1369, _T_1370, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1491 = mux(_T_1372, _T_1373, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1492 = mux(_T_1375, _T_1376, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1493 = mux(_T_1378, _T_1381, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1494 = mux(_T_1383, _T_1384, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1495 = mux(_T_1386, _T_1387, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1496 = mux(_T_1389, _T_1390, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1497 = mux(_T_1392, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1498 = mux(_T_1394, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1499 = mux(_T_1396, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1500 = mux(_T_1398, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1501 = mux(_T_1400, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1502 = mux(_T_1402, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1503 = mux(_T_1404, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1504 = mux(_T_1406, _T_1408, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1505 = mux(_T_1410, _T_1412, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1506 = mux(_T_1414, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1507 = mux(_T_1416, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1508 = mux(_T_1418, _T_1420, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1509 = mux(_T_1422, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1510 = mux(_T_1424, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1511 = mux(_T_1426, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1512 = mux(_T_1428, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1513 = mux(_T_1430, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1514 = mux(_T_1432, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1515 = mux(_T_1434, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1516 = mux(_T_1436, _T_1439, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1517 = mux(_T_1441, _T_1449, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1518 = mux(_T_1451, _T_1452, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1519 = mux(_T_1454, _T_1455, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1520 = mux(_T_1457, _T_1458, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1521 = mux(_T_1460, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1522 = mux(_T_1462, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1523 = mux(_T_1464, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1524 = mux(_T_1466, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1525 = mux(_T_1468, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1526 = or(_T_1469, _T_1470) @[Mux.scala 27:72] - node _T_1527 = or(_T_1526, _T_1471) @[Mux.scala 27:72] - node _T_1528 = or(_T_1527, _T_1472) @[Mux.scala 27:72] - node _T_1529 = or(_T_1528, _T_1473) @[Mux.scala 27:72] - node _T_1530 = or(_T_1529, _T_1474) @[Mux.scala 27:72] - node _T_1531 = or(_T_1530, _T_1475) @[Mux.scala 27:72] - node _T_1532 = or(_T_1531, _T_1476) @[Mux.scala 27:72] - node _T_1533 = or(_T_1532, _T_1477) @[Mux.scala 27:72] - node _T_1534 = or(_T_1533, _T_1478) @[Mux.scala 27:72] + node _T_1298 = or(_T_1297, _T_1242) @[Mux.scala 27:72] + node _T_1299 = or(_T_1298, _T_1243) @[Mux.scala 27:72] + node _T_1300 = or(_T_1299, _T_1244) @[Mux.scala 27:72] + node _T_1301 = or(_T_1300, _T_1245) @[Mux.scala 27:72] + node _T_1302 = or(_T_1301, _T_1246) @[Mux.scala 27:72] + node _T_1303 = or(_T_1302, _T_1247) @[Mux.scala 27:72] + node _T_1304 = or(_T_1303, _T_1248) @[Mux.scala 27:72] + node _T_1305 = or(_T_1304, _T_1249) @[Mux.scala 27:72] + wire _T_1306 : UInt<1> @[Mux.scala 27:72] + _T_1306 <= _T_1305 @[Mux.scala 27:72] + node _T_1307 = and(_T_1025, _T_1306) @[dec_tlu_ctl.scala 2273:44] + mhpmc_inc_r[0] <= _T_1307 @[dec_tlu_ctl.scala 2273:19] + node _T_1308 = bits(mcountinhibit, 4, 4) @[dec_tlu_ctl.scala 2273:38] + node _T_1309 = not(_T_1308) @[dec_tlu_ctl.scala 2273:24] + node _T_1310 = eq(mhpme_vec[1], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] + node _T_1311 = bits(_T_1310, 0, 0) @[dec_tlu_ctl.scala 2274:62] + node _T_1312 = eq(mhpme_vec[1], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] + node _T_1313 = bits(_T_1312, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1314 = eq(mhpme_vec[1], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] + node _T_1315 = bits(_T_1314, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1316 = eq(mhpme_vec[1], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] + node _T_1317 = bits(_T_1316, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1318 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] + node _T_1319 = and(io.tlu_i0_commit_cmt, _T_1318) @[dec_tlu_ctl.scala 2277:94] + node _T_1320 = eq(mhpme_vec[1], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] + node _T_1321 = bits(_T_1320, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1322 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] + node _T_1323 = and(io.tlu_i0_commit_cmt, _T_1322) @[dec_tlu_ctl.scala 2278:94] + node _T_1324 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] + node _T_1325 = and(_T_1323, _T_1324) @[dec_tlu_ctl.scala 2278:115] + node _T_1326 = eq(mhpme_vec[1], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] + node _T_1327 = bits(_T_1326, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1328 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] + node _T_1329 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] + node _T_1330 = and(_T_1328, _T_1329) @[dec_tlu_ctl.scala 2279:115] + node _T_1331 = eq(mhpme_vec[1], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] + node _T_1332 = bits(_T_1331, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1333 = eq(mhpme_vec[1], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] + node _T_1334 = bits(_T_1333, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1335 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] + node _T_1336 = bits(_T_1335, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1337 = eq(mhpme_vec[1], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] + node _T_1338 = bits(_T_1337, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1339 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] + node _T_1340 = eq(mhpme_vec[1], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] + node _T_1341 = bits(_T_1340, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1342 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] + node _T_1343 = eq(mhpme_vec[1], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] + node _T_1344 = bits(_T_1343, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1345 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] + node _T_1346 = eq(mhpme_vec[1], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] + node _T_1347 = bits(_T_1346, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1348 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] + node _T_1349 = eq(mhpme_vec[1], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] + node _T_1350 = bits(_T_1349, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1351 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] + node _T_1352 = and(_T_1351, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] + node _T_1353 = eq(mhpme_vec[1], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] + node _T_1354 = bits(_T_1353, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1355 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] + node _T_1356 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] + node _T_1357 = and(_T_1355, _T_1356) @[dec_tlu_ctl.scala 2288:101] + node _T_1358 = eq(mhpme_vec[1], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] + node _T_1359 = bits(_T_1358, 0, 0) @[dec_tlu_ctl.scala 2289:59] + node _T_1360 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] + node _T_1361 = eq(mhpme_vec[1], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] + node _T_1362 = bits(_T_1361, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1363 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] + node _T_1364 = eq(mhpme_vec[1], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] + node _T_1365 = bits(_T_1364, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1366 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] + node _T_1367 = eq(mhpme_vec[1], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] + node _T_1368 = bits(_T_1367, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1369 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] + node _T_1370 = eq(mhpme_vec[1], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] + node _T_1371 = bits(_T_1370, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1372 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] + node _T_1373 = eq(mhpme_vec[1], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] + node _T_1374 = bits(_T_1373, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1375 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] + node _T_1376 = eq(mhpme_vec[1], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] + node _T_1377 = bits(_T_1376, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1378 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] + node _T_1379 = eq(mhpme_vec[1], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] + node _T_1380 = bits(_T_1379, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1381 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] + node _T_1382 = eq(mhpme_vec[1], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] + node _T_1383 = bits(_T_1382, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1384 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] + node _T_1385 = eq(mhpme_vec[1], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] + node _T_1386 = bits(_T_1385, 0, 0) @[dec_tlu_ctl.scala 2298:59] + node _T_1387 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] + node _T_1388 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] + node _T_1389 = or(_T_1387, _T_1388) @[dec_tlu_ctl.scala 2298:101] + node _T_1390 = eq(mhpme_vec[1], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] + node _T_1391 = bits(_T_1390, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1392 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] + node _T_1393 = eq(mhpme_vec[1], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] + node _T_1394 = bits(_T_1393, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1395 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] + node _T_1396 = eq(mhpme_vec[1], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] + node _T_1397 = bits(_T_1396, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1398 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] + node _T_1399 = eq(mhpme_vec[1], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] + node _T_1400 = bits(_T_1399, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1401 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] + node _T_1402 = bits(_T_1401, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1403 = eq(mhpme_vec[1], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] + node _T_1404 = bits(_T_1403, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1405 = eq(mhpme_vec[1], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] + node _T_1406 = bits(_T_1405, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1407 = eq(mhpme_vec[1], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] + node _T_1408 = bits(_T_1407, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1409 = eq(mhpme_vec[1], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] + node _T_1410 = bits(_T_1409, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1411 = eq(mhpme_vec[1], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] + node _T_1412 = bits(_T_1411, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1413 = eq(mhpme_vec[1], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] + node _T_1414 = bits(_T_1413, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1415 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] + node _T_1416 = or(_T_1415, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] + node _T_1417 = eq(mhpme_vec[1], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] + node _T_1418 = bits(_T_1417, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1419 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] + node _T_1420 = or(_T_1419, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] + node _T_1421 = eq(mhpme_vec[1], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] + node _T_1422 = bits(_T_1421, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1423 = eq(mhpme_vec[1], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] + node _T_1424 = bits(_T_1423, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1425 = eq(mhpme_vec[1], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] + node _T_1426 = bits(_T_1425, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1427 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] + node _T_1428 = and(_T_1427, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] + node _T_1429 = eq(mhpme_vec[1], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] + node _T_1430 = bits(_T_1429, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_1431 = eq(mhpme_vec[1], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] + node _T_1432 = bits(_T_1431, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_1433 = eq(mhpme_vec[1], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] + node _T_1434 = bits(_T_1433, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_1435 = eq(mhpme_vec[1], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] + node _T_1436 = bits(_T_1435, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_1437 = eq(mhpme_vec[1], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] + node _T_1438 = bits(_T_1437, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_1439 = eq(mhpme_vec[1], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] + node _T_1440 = bits(_T_1439, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_1441 = eq(mhpme_vec[1], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] + node _T_1442 = bits(_T_1441, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_1443 = eq(mhpme_vec[1], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] + node _T_1444 = bits(_T_1443, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_1445 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] + node _T_1446 = bits(_T_1445, 0, 0) @[dec_tlu_ctl.scala 2321:84] + node _T_1447 = not(_T_1446) @[dec_tlu_ctl.scala 2321:73] + node _T_1448 = eq(mhpme_vec[1], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] + node _T_1449 = bits(_T_1448, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_1450 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] + node _T_1451 = bits(_T_1450, 0, 0) @[dec_tlu_ctl.scala 2322:84] + node _T_1452 = not(_T_1451) @[dec_tlu_ctl.scala 2322:73] + node _T_1453 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] + node _T_1454 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] + node _T_1455 = and(_T_1453, _T_1454) @[dec_tlu_ctl.scala 2322:113] + node _T_1456 = orr(_T_1455) @[dec_tlu_ctl.scala 2322:125] + node _T_1457 = and(_T_1452, _T_1456) @[dec_tlu_ctl.scala 2322:98] + node _T_1458 = eq(mhpme_vec[1], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] + node _T_1459 = bits(_T_1458, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_1460 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] + node _T_1461 = eq(mhpme_vec[1], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] + node _T_1462 = bits(_T_1461, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_1463 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] + node _T_1464 = eq(mhpme_vec[1], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] + node _T_1465 = bits(_T_1464, 0, 0) @[dec_tlu_ctl.scala 2325:62] + node _T_1466 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] + node _T_1467 = eq(mhpme_vec[1], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] + node _T_1468 = bits(_T_1467, 0, 0) @[dec_tlu_ctl.scala 2327:62] + node _T_1469 = eq(mhpme_vec[1], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] + node _T_1470 = bits(_T_1469, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_1471 = eq(mhpme_vec[1], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] + node _T_1472 = bits(_T_1471, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_1473 = eq(mhpme_vec[1], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] + node _T_1474 = bits(_T_1473, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_1475 = eq(mhpme_vec[1], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] + node _T_1476 = bits(_T_1475, 0, 0) @[dec_tlu_ctl.scala 2331:62] + node _T_1477 = mux(_T_1311, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1478 = mux(_T_1313, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1479 = mux(_T_1315, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1480 = mux(_T_1317, _T_1319, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1481 = mux(_T_1321, _T_1325, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1482 = mux(_T_1327, _T_1330, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1483 = mux(_T_1332, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1484 = mux(_T_1334, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1485 = mux(_T_1336, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1486 = mux(_T_1338, _T_1339, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1487 = mux(_T_1341, _T_1342, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1488 = mux(_T_1344, _T_1345, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1489 = mux(_T_1347, _T_1348, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1490 = mux(_T_1350, _T_1352, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1491 = mux(_T_1354, _T_1357, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1492 = mux(_T_1359, _T_1360, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1493 = mux(_T_1362, _T_1363, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1494 = mux(_T_1365, _T_1366, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1495 = mux(_T_1368, _T_1369, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1496 = mux(_T_1371, _T_1372, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1497 = mux(_T_1374, _T_1375, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1498 = mux(_T_1377, _T_1378, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1499 = mux(_T_1380, _T_1381, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1500 = mux(_T_1383, _T_1384, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1501 = mux(_T_1386, _T_1389, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1502 = mux(_T_1391, _T_1392, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1503 = mux(_T_1394, _T_1395, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1504 = mux(_T_1397, _T_1398, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1505 = mux(_T_1400, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1506 = mux(_T_1402, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1507 = mux(_T_1404, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1508 = mux(_T_1406, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1509 = mux(_T_1408, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1510 = mux(_T_1410, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1511 = mux(_T_1412, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1512 = mux(_T_1414, _T_1416, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1513 = mux(_T_1418, _T_1420, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1514 = mux(_T_1422, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1515 = mux(_T_1424, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1516 = mux(_T_1426, _T_1428, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1517 = mux(_T_1430, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1518 = mux(_T_1432, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1519 = mux(_T_1434, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1520 = mux(_T_1436, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1521 = mux(_T_1438, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1522 = mux(_T_1440, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1523 = mux(_T_1442, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1524 = mux(_T_1444, _T_1447, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1525 = mux(_T_1449, _T_1457, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1526 = mux(_T_1459, _T_1460, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1527 = mux(_T_1462, _T_1463, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1528 = mux(_T_1465, _T_1466, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1529 = mux(_T_1468, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1530 = mux(_T_1470, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1531 = mux(_T_1472, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1532 = mux(_T_1474, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1533 = mux(_T_1476, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1534 = or(_T_1477, _T_1478) @[Mux.scala 27:72] node _T_1535 = or(_T_1534, _T_1479) @[Mux.scala 27:72] node _T_1536 = or(_T_1535, _T_1480) @[Mux.scala 27:72] node _T_1537 = or(_T_1536, _T_1481) @[Mux.scala 27:72] @@ -74967,245 +74967,245 @@ circuit quasar_wrapper : node _T_1579 = or(_T_1578, _T_1523) @[Mux.scala 27:72] node _T_1580 = or(_T_1579, _T_1524) @[Mux.scala 27:72] node _T_1581 = or(_T_1580, _T_1525) @[Mux.scala 27:72] - wire _T_1582 : UInt<1> @[Mux.scala 27:72] - _T_1582 <= _T_1581 @[Mux.scala 27:72] - node _T_1583 = and(_T_1301, _T_1582) @[dec_tlu_ctl.scala 2273:44] - mhpmc_inc_r[1] <= _T_1583 @[dec_tlu_ctl.scala 2273:19] - node _T_1584 = bits(mcountinhibit, 5, 5) @[dec_tlu_ctl.scala 2273:38] - node _T_1585 = not(_T_1584) @[dec_tlu_ctl.scala 2273:24] - node _T_1586 = eq(mhpme_vec[2], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] - node _T_1587 = bits(_T_1586, 0, 0) @[dec_tlu_ctl.scala 2274:62] - node _T_1588 = eq(mhpme_vec[2], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] - node _T_1589 = bits(_T_1588, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1590 = eq(mhpme_vec[2], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] - node _T_1591 = bits(_T_1590, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1592 = eq(mhpme_vec[2], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] - node _T_1593 = bits(_T_1592, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1594 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] - node _T_1595 = and(io.tlu_i0_commit_cmt, _T_1594) @[dec_tlu_ctl.scala 2277:94] - node _T_1596 = eq(mhpme_vec[2], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] - node _T_1597 = bits(_T_1596, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1598 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] - node _T_1599 = and(io.tlu_i0_commit_cmt, _T_1598) @[dec_tlu_ctl.scala 2278:94] - node _T_1600 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] - node _T_1601 = and(_T_1599, _T_1600) @[dec_tlu_ctl.scala 2278:115] - node _T_1602 = eq(mhpme_vec[2], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] - node _T_1603 = bits(_T_1602, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1604 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] - node _T_1605 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] - node _T_1606 = and(_T_1604, _T_1605) @[dec_tlu_ctl.scala 2279:115] - node _T_1607 = eq(mhpme_vec[2], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] - node _T_1608 = bits(_T_1607, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1609 = eq(mhpme_vec[2], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] - node _T_1610 = bits(_T_1609, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1611 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] - node _T_1612 = bits(_T_1611, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1613 = eq(mhpme_vec[2], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] - node _T_1614 = bits(_T_1613, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1615 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] - node _T_1616 = eq(mhpme_vec[2], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] - node _T_1617 = bits(_T_1616, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1618 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] - node _T_1619 = eq(mhpme_vec[2], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] - node _T_1620 = bits(_T_1619, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1621 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] - node _T_1622 = eq(mhpme_vec[2], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] - node _T_1623 = bits(_T_1622, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1624 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] - node _T_1625 = eq(mhpme_vec[2], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] - node _T_1626 = bits(_T_1625, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1627 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] - node _T_1628 = and(_T_1627, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] - node _T_1629 = eq(mhpme_vec[2], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] - node _T_1630 = bits(_T_1629, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1631 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] - node _T_1632 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] - node _T_1633 = and(_T_1631, _T_1632) @[dec_tlu_ctl.scala 2288:101] - node _T_1634 = eq(mhpme_vec[2], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] - node _T_1635 = bits(_T_1634, 0, 0) @[dec_tlu_ctl.scala 2289:59] - node _T_1636 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] - node _T_1637 = eq(mhpme_vec[2], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] - node _T_1638 = bits(_T_1637, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1639 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] - node _T_1640 = eq(mhpme_vec[2], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] - node _T_1641 = bits(_T_1640, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1642 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] - node _T_1643 = eq(mhpme_vec[2], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] - node _T_1644 = bits(_T_1643, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1645 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] - node _T_1646 = eq(mhpme_vec[2], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] - node _T_1647 = bits(_T_1646, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1648 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] - node _T_1649 = eq(mhpme_vec[2], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] - node _T_1650 = bits(_T_1649, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1651 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] - node _T_1652 = eq(mhpme_vec[2], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] - node _T_1653 = bits(_T_1652, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1654 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] - node _T_1655 = eq(mhpme_vec[2], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] - node _T_1656 = bits(_T_1655, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1657 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] - node _T_1658 = eq(mhpme_vec[2], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] - node _T_1659 = bits(_T_1658, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1660 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] - node _T_1661 = eq(mhpme_vec[2], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] - node _T_1662 = bits(_T_1661, 0, 0) @[dec_tlu_ctl.scala 2298:59] - node _T_1663 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] - node _T_1664 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] - node _T_1665 = or(_T_1663, _T_1664) @[dec_tlu_ctl.scala 2298:101] - node _T_1666 = eq(mhpme_vec[2], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] - node _T_1667 = bits(_T_1666, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1668 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] - node _T_1669 = eq(mhpme_vec[2], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] - node _T_1670 = bits(_T_1669, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1671 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] - node _T_1672 = eq(mhpme_vec[2], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] - node _T_1673 = bits(_T_1672, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1674 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] - node _T_1675 = eq(mhpme_vec[2], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] - node _T_1676 = bits(_T_1675, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1677 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] - node _T_1678 = bits(_T_1677, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1679 = eq(mhpme_vec[2], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] - node _T_1680 = bits(_T_1679, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1681 = eq(mhpme_vec[2], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] - node _T_1682 = bits(_T_1681, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1683 = eq(mhpme_vec[2], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] - node _T_1684 = bits(_T_1683, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1685 = eq(mhpme_vec[2], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] - node _T_1686 = bits(_T_1685, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1687 = eq(mhpme_vec[2], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] - node _T_1688 = bits(_T_1687, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1689 = eq(mhpme_vec[2], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] - node _T_1690 = bits(_T_1689, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1691 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] - node _T_1692 = or(_T_1691, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] - node _T_1693 = eq(mhpme_vec[2], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] - node _T_1694 = bits(_T_1693, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1695 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] - node _T_1696 = or(_T_1695, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] - node _T_1697 = eq(mhpme_vec[2], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] - node _T_1698 = bits(_T_1697, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1699 = eq(mhpme_vec[2], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] - node _T_1700 = bits(_T_1699, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1701 = eq(mhpme_vec[2], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] - node _T_1702 = bits(_T_1701, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1703 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] - node _T_1704 = and(_T_1703, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] - node _T_1705 = eq(mhpme_vec[2], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] - node _T_1706 = bits(_T_1705, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1707 = eq(mhpme_vec[2], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] - node _T_1708 = bits(_T_1707, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_1709 = eq(mhpme_vec[2], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] - node _T_1710 = bits(_T_1709, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_1711 = eq(mhpme_vec[2], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] - node _T_1712 = bits(_T_1711, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_1713 = eq(mhpme_vec[2], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] - node _T_1714 = bits(_T_1713, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_1715 = eq(mhpme_vec[2], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] - node _T_1716 = bits(_T_1715, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_1717 = eq(mhpme_vec[2], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] - node _T_1718 = bits(_T_1717, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_1719 = eq(mhpme_vec[2], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] - node _T_1720 = bits(_T_1719, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_1721 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] - node _T_1722 = bits(_T_1721, 0, 0) @[dec_tlu_ctl.scala 2321:84] - node _T_1723 = not(_T_1722) @[dec_tlu_ctl.scala 2321:73] - node _T_1724 = eq(mhpme_vec[2], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] - node _T_1725 = bits(_T_1724, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_1726 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] - node _T_1727 = bits(_T_1726, 0, 0) @[dec_tlu_ctl.scala 2322:84] - node _T_1728 = not(_T_1727) @[dec_tlu_ctl.scala 2322:73] - node _T_1729 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] - node _T_1730 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] - node _T_1731 = and(_T_1729, _T_1730) @[dec_tlu_ctl.scala 2322:113] - node _T_1732 = orr(_T_1731) @[dec_tlu_ctl.scala 2322:125] - node _T_1733 = and(_T_1728, _T_1732) @[dec_tlu_ctl.scala 2322:98] - node _T_1734 = eq(mhpme_vec[2], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] - node _T_1735 = bits(_T_1734, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_1736 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] - node _T_1737 = eq(mhpme_vec[2], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] - node _T_1738 = bits(_T_1737, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_1739 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] - node _T_1740 = eq(mhpme_vec[2], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] - node _T_1741 = bits(_T_1740, 0, 0) @[dec_tlu_ctl.scala 2325:62] - node _T_1742 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] - node _T_1743 = eq(mhpme_vec[2], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] - node _T_1744 = bits(_T_1743, 0, 0) @[dec_tlu_ctl.scala 2327:62] - node _T_1745 = eq(mhpme_vec[2], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] - node _T_1746 = bits(_T_1745, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_1747 = eq(mhpme_vec[2], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] - node _T_1748 = bits(_T_1747, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_1749 = eq(mhpme_vec[2], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] - node _T_1750 = bits(_T_1749, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_1751 = eq(mhpme_vec[2], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] - node _T_1752 = bits(_T_1751, 0, 0) @[dec_tlu_ctl.scala 2331:62] - node _T_1753 = mux(_T_1587, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1754 = mux(_T_1589, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1755 = mux(_T_1591, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1756 = mux(_T_1593, _T_1595, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1757 = mux(_T_1597, _T_1601, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1758 = mux(_T_1603, _T_1606, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1759 = mux(_T_1608, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1760 = mux(_T_1610, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1761 = mux(_T_1612, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1762 = mux(_T_1614, _T_1615, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1763 = mux(_T_1617, _T_1618, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1764 = mux(_T_1620, _T_1621, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1765 = mux(_T_1623, _T_1624, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1766 = mux(_T_1626, _T_1628, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1767 = mux(_T_1630, _T_1633, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1768 = mux(_T_1635, _T_1636, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1769 = mux(_T_1638, _T_1639, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1770 = mux(_T_1641, _T_1642, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1771 = mux(_T_1644, _T_1645, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1772 = mux(_T_1647, _T_1648, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1773 = mux(_T_1650, _T_1651, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1774 = mux(_T_1653, _T_1654, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1775 = mux(_T_1656, _T_1657, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1776 = mux(_T_1659, _T_1660, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1777 = mux(_T_1662, _T_1665, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1778 = mux(_T_1667, _T_1668, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1779 = mux(_T_1670, _T_1671, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1780 = mux(_T_1673, _T_1674, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1781 = mux(_T_1676, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1782 = mux(_T_1678, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1783 = mux(_T_1680, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1784 = mux(_T_1682, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1785 = mux(_T_1684, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1786 = mux(_T_1686, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1787 = mux(_T_1688, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1788 = mux(_T_1690, _T_1692, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1789 = mux(_T_1694, _T_1696, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1790 = mux(_T_1698, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1791 = mux(_T_1700, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1792 = mux(_T_1702, _T_1704, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1793 = mux(_T_1706, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1794 = mux(_T_1708, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1795 = mux(_T_1710, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1796 = mux(_T_1712, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1797 = mux(_T_1714, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1798 = mux(_T_1716, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1799 = mux(_T_1718, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1800 = mux(_T_1720, _T_1723, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1801 = mux(_T_1725, _T_1733, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1802 = mux(_T_1735, _T_1736, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1803 = mux(_T_1738, _T_1739, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1804 = mux(_T_1741, _T_1742, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1805 = mux(_T_1744, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1806 = mux(_T_1746, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1807 = mux(_T_1748, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1808 = mux(_T_1750, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1809 = mux(_T_1752, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1810 = or(_T_1753, _T_1754) @[Mux.scala 27:72] - node _T_1811 = or(_T_1810, _T_1755) @[Mux.scala 27:72] - node _T_1812 = or(_T_1811, _T_1756) @[Mux.scala 27:72] - node _T_1813 = or(_T_1812, _T_1757) @[Mux.scala 27:72] - node _T_1814 = or(_T_1813, _T_1758) @[Mux.scala 27:72] - node _T_1815 = or(_T_1814, _T_1759) @[Mux.scala 27:72] - node _T_1816 = or(_T_1815, _T_1760) @[Mux.scala 27:72] - node _T_1817 = or(_T_1816, _T_1761) @[Mux.scala 27:72] - node _T_1818 = or(_T_1817, _T_1762) @[Mux.scala 27:72] + node _T_1582 = or(_T_1581, _T_1526) @[Mux.scala 27:72] + node _T_1583 = or(_T_1582, _T_1527) @[Mux.scala 27:72] + node _T_1584 = or(_T_1583, _T_1528) @[Mux.scala 27:72] + node _T_1585 = or(_T_1584, _T_1529) @[Mux.scala 27:72] + node _T_1586 = or(_T_1585, _T_1530) @[Mux.scala 27:72] + node _T_1587 = or(_T_1586, _T_1531) @[Mux.scala 27:72] + node _T_1588 = or(_T_1587, _T_1532) @[Mux.scala 27:72] + node _T_1589 = or(_T_1588, _T_1533) @[Mux.scala 27:72] + wire _T_1590 : UInt<1> @[Mux.scala 27:72] + _T_1590 <= _T_1589 @[Mux.scala 27:72] + node _T_1591 = and(_T_1309, _T_1590) @[dec_tlu_ctl.scala 2273:44] + mhpmc_inc_r[1] <= _T_1591 @[dec_tlu_ctl.scala 2273:19] + node _T_1592 = bits(mcountinhibit, 5, 5) @[dec_tlu_ctl.scala 2273:38] + node _T_1593 = not(_T_1592) @[dec_tlu_ctl.scala 2273:24] + node _T_1594 = eq(mhpme_vec[2], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] + node _T_1595 = bits(_T_1594, 0, 0) @[dec_tlu_ctl.scala 2274:62] + node _T_1596 = eq(mhpme_vec[2], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] + node _T_1597 = bits(_T_1596, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1598 = eq(mhpme_vec[2], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] + node _T_1599 = bits(_T_1598, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1600 = eq(mhpme_vec[2], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] + node _T_1601 = bits(_T_1600, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1602 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] + node _T_1603 = and(io.tlu_i0_commit_cmt, _T_1602) @[dec_tlu_ctl.scala 2277:94] + node _T_1604 = eq(mhpme_vec[2], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] + node _T_1605 = bits(_T_1604, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1606 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] + node _T_1607 = and(io.tlu_i0_commit_cmt, _T_1606) @[dec_tlu_ctl.scala 2278:94] + node _T_1608 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] + node _T_1609 = and(_T_1607, _T_1608) @[dec_tlu_ctl.scala 2278:115] + node _T_1610 = eq(mhpme_vec[2], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] + node _T_1611 = bits(_T_1610, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1612 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] + node _T_1613 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] + node _T_1614 = and(_T_1612, _T_1613) @[dec_tlu_ctl.scala 2279:115] + node _T_1615 = eq(mhpme_vec[2], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] + node _T_1616 = bits(_T_1615, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1617 = eq(mhpme_vec[2], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] + node _T_1618 = bits(_T_1617, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1619 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] + node _T_1620 = bits(_T_1619, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1621 = eq(mhpme_vec[2], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] + node _T_1622 = bits(_T_1621, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1623 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] + node _T_1624 = eq(mhpme_vec[2], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] + node _T_1625 = bits(_T_1624, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1626 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] + node _T_1627 = eq(mhpme_vec[2], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] + node _T_1628 = bits(_T_1627, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1629 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] + node _T_1630 = eq(mhpme_vec[2], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] + node _T_1631 = bits(_T_1630, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1632 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] + node _T_1633 = eq(mhpme_vec[2], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] + node _T_1634 = bits(_T_1633, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1635 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] + node _T_1636 = and(_T_1635, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] + node _T_1637 = eq(mhpme_vec[2], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] + node _T_1638 = bits(_T_1637, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1639 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] + node _T_1640 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] + node _T_1641 = and(_T_1639, _T_1640) @[dec_tlu_ctl.scala 2288:101] + node _T_1642 = eq(mhpme_vec[2], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] + node _T_1643 = bits(_T_1642, 0, 0) @[dec_tlu_ctl.scala 2289:59] + node _T_1644 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] + node _T_1645 = eq(mhpme_vec[2], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] + node _T_1646 = bits(_T_1645, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1647 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] + node _T_1648 = eq(mhpme_vec[2], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] + node _T_1649 = bits(_T_1648, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1650 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] + node _T_1651 = eq(mhpme_vec[2], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] + node _T_1652 = bits(_T_1651, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1653 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] + node _T_1654 = eq(mhpme_vec[2], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] + node _T_1655 = bits(_T_1654, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1656 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] + node _T_1657 = eq(mhpme_vec[2], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] + node _T_1658 = bits(_T_1657, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1659 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] + node _T_1660 = eq(mhpme_vec[2], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] + node _T_1661 = bits(_T_1660, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1662 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] + node _T_1663 = eq(mhpme_vec[2], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] + node _T_1664 = bits(_T_1663, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1665 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] + node _T_1666 = eq(mhpme_vec[2], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] + node _T_1667 = bits(_T_1666, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1668 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] + node _T_1669 = eq(mhpme_vec[2], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] + node _T_1670 = bits(_T_1669, 0, 0) @[dec_tlu_ctl.scala 2298:59] + node _T_1671 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] + node _T_1672 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] + node _T_1673 = or(_T_1671, _T_1672) @[dec_tlu_ctl.scala 2298:101] + node _T_1674 = eq(mhpme_vec[2], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] + node _T_1675 = bits(_T_1674, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1676 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] + node _T_1677 = eq(mhpme_vec[2], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] + node _T_1678 = bits(_T_1677, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1679 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] + node _T_1680 = eq(mhpme_vec[2], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] + node _T_1681 = bits(_T_1680, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1682 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] + node _T_1683 = eq(mhpme_vec[2], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] + node _T_1684 = bits(_T_1683, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1685 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] + node _T_1686 = bits(_T_1685, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1687 = eq(mhpme_vec[2], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] + node _T_1688 = bits(_T_1687, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1689 = eq(mhpme_vec[2], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] + node _T_1690 = bits(_T_1689, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1691 = eq(mhpme_vec[2], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] + node _T_1692 = bits(_T_1691, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1693 = eq(mhpme_vec[2], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] + node _T_1694 = bits(_T_1693, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1695 = eq(mhpme_vec[2], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] + node _T_1696 = bits(_T_1695, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1697 = eq(mhpme_vec[2], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] + node _T_1698 = bits(_T_1697, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1699 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] + node _T_1700 = or(_T_1699, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] + node _T_1701 = eq(mhpme_vec[2], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] + node _T_1702 = bits(_T_1701, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1703 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] + node _T_1704 = or(_T_1703, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] + node _T_1705 = eq(mhpme_vec[2], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] + node _T_1706 = bits(_T_1705, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1707 = eq(mhpme_vec[2], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] + node _T_1708 = bits(_T_1707, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1709 = eq(mhpme_vec[2], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] + node _T_1710 = bits(_T_1709, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1711 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] + node _T_1712 = and(_T_1711, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] + node _T_1713 = eq(mhpme_vec[2], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] + node _T_1714 = bits(_T_1713, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_1715 = eq(mhpme_vec[2], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] + node _T_1716 = bits(_T_1715, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_1717 = eq(mhpme_vec[2], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] + node _T_1718 = bits(_T_1717, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_1719 = eq(mhpme_vec[2], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] + node _T_1720 = bits(_T_1719, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_1721 = eq(mhpme_vec[2], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] + node _T_1722 = bits(_T_1721, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_1723 = eq(mhpme_vec[2], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] + node _T_1724 = bits(_T_1723, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_1725 = eq(mhpme_vec[2], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] + node _T_1726 = bits(_T_1725, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_1727 = eq(mhpme_vec[2], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] + node _T_1728 = bits(_T_1727, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_1729 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] + node _T_1730 = bits(_T_1729, 0, 0) @[dec_tlu_ctl.scala 2321:84] + node _T_1731 = not(_T_1730) @[dec_tlu_ctl.scala 2321:73] + node _T_1732 = eq(mhpme_vec[2], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] + node _T_1733 = bits(_T_1732, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_1734 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] + node _T_1735 = bits(_T_1734, 0, 0) @[dec_tlu_ctl.scala 2322:84] + node _T_1736 = not(_T_1735) @[dec_tlu_ctl.scala 2322:73] + node _T_1737 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] + node _T_1738 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] + node _T_1739 = and(_T_1737, _T_1738) @[dec_tlu_ctl.scala 2322:113] + node _T_1740 = orr(_T_1739) @[dec_tlu_ctl.scala 2322:125] + node _T_1741 = and(_T_1736, _T_1740) @[dec_tlu_ctl.scala 2322:98] + node _T_1742 = eq(mhpme_vec[2], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] + node _T_1743 = bits(_T_1742, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_1744 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] + node _T_1745 = eq(mhpme_vec[2], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] + node _T_1746 = bits(_T_1745, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_1747 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] + node _T_1748 = eq(mhpme_vec[2], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] + node _T_1749 = bits(_T_1748, 0, 0) @[dec_tlu_ctl.scala 2325:62] + node _T_1750 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] + node _T_1751 = eq(mhpme_vec[2], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] + node _T_1752 = bits(_T_1751, 0, 0) @[dec_tlu_ctl.scala 2327:62] + node _T_1753 = eq(mhpme_vec[2], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] + node _T_1754 = bits(_T_1753, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_1755 = eq(mhpme_vec[2], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] + node _T_1756 = bits(_T_1755, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_1757 = eq(mhpme_vec[2], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] + node _T_1758 = bits(_T_1757, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_1759 = eq(mhpme_vec[2], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] + node _T_1760 = bits(_T_1759, 0, 0) @[dec_tlu_ctl.scala 2331:62] + node _T_1761 = mux(_T_1595, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1762 = mux(_T_1597, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1763 = mux(_T_1599, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1764 = mux(_T_1601, _T_1603, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1765 = mux(_T_1605, _T_1609, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1766 = mux(_T_1611, _T_1614, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1767 = mux(_T_1616, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1768 = mux(_T_1618, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1769 = mux(_T_1620, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1770 = mux(_T_1622, _T_1623, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1771 = mux(_T_1625, _T_1626, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1772 = mux(_T_1628, _T_1629, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1773 = mux(_T_1631, _T_1632, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1774 = mux(_T_1634, _T_1636, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1775 = mux(_T_1638, _T_1641, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1776 = mux(_T_1643, _T_1644, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1777 = mux(_T_1646, _T_1647, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1778 = mux(_T_1649, _T_1650, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1779 = mux(_T_1652, _T_1653, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1780 = mux(_T_1655, _T_1656, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1781 = mux(_T_1658, _T_1659, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1782 = mux(_T_1661, _T_1662, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1783 = mux(_T_1664, _T_1665, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1784 = mux(_T_1667, _T_1668, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1785 = mux(_T_1670, _T_1673, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1786 = mux(_T_1675, _T_1676, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1787 = mux(_T_1678, _T_1679, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1788 = mux(_T_1681, _T_1682, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1789 = mux(_T_1684, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1790 = mux(_T_1686, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1791 = mux(_T_1688, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1792 = mux(_T_1690, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1793 = mux(_T_1692, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1794 = mux(_T_1694, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1795 = mux(_T_1696, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1796 = mux(_T_1698, _T_1700, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1797 = mux(_T_1702, _T_1704, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1798 = mux(_T_1706, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1799 = mux(_T_1708, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1800 = mux(_T_1710, _T_1712, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1801 = mux(_T_1714, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1802 = mux(_T_1716, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1803 = mux(_T_1718, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1804 = mux(_T_1720, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1805 = mux(_T_1722, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1806 = mux(_T_1724, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1807 = mux(_T_1726, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1808 = mux(_T_1728, _T_1731, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1809 = mux(_T_1733, _T_1741, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1810 = mux(_T_1743, _T_1744, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1811 = mux(_T_1746, _T_1747, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1812 = mux(_T_1749, _T_1750, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1813 = mux(_T_1752, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1814 = mux(_T_1754, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1815 = mux(_T_1756, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1816 = mux(_T_1758, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1817 = mux(_T_1760, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1818 = or(_T_1761, _T_1762) @[Mux.scala 27:72] node _T_1819 = or(_T_1818, _T_1763) @[Mux.scala 27:72] node _T_1820 = or(_T_1819, _T_1764) @[Mux.scala 27:72] node _T_1821 = or(_T_1820, _T_1765) @[Mux.scala 27:72] @@ -75253,245 +75253,245 @@ circuit quasar_wrapper : node _T_1863 = or(_T_1862, _T_1807) @[Mux.scala 27:72] node _T_1864 = or(_T_1863, _T_1808) @[Mux.scala 27:72] node _T_1865 = or(_T_1864, _T_1809) @[Mux.scala 27:72] - wire _T_1866 : UInt<1> @[Mux.scala 27:72] - _T_1866 <= _T_1865 @[Mux.scala 27:72] - node _T_1867 = and(_T_1585, _T_1866) @[dec_tlu_ctl.scala 2273:44] - mhpmc_inc_r[2] <= _T_1867 @[dec_tlu_ctl.scala 2273:19] - node _T_1868 = bits(mcountinhibit, 6, 6) @[dec_tlu_ctl.scala 2273:38] - node _T_1869 = not(_T_1868) @[dec_tlu_ctl.scala 2273:24] - node _T_1870 = eq(mhpme_vec[3], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] - node _T_1871 = bits(_T_1870, 0, 0) @[dec_tlu_ctl.scala 2274:62] - node _T_1872 = eq(mhpme_vec[3], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] - node _T_1873 = bits(_T_1872, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1874 = eq(mhpme_vec[3], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] - node _T_1875 = bits(_T_1874, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1876 = eq(mhpme_vec[3], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] - node _T_1877 = bits(_T_1876, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1878 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] - node _T_1879 = and(io.tlu_i0_commit_cmt, _T_1878) @[dec_tlu_ctl.scala 2277:94] - node _T_1880 = eq(mhpme_vec[3], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] - node _T_1881 = bits(_T_1880, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1882 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] - node _T_1883 = and(io.tlu_i0_commit_cmt, _T_1882) @[dec_tlu_ctl.scala 2278:94] - node _T_1884 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] - node _T_1885 = and(_T_1883, _T_1884) @[dec_tlu_ctl.scala 2278:115] - node _T_1886 = eq(mhpme_vec[3], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] - node _T_1887 = bits(_T_1886, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1888 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] - node _T_1889 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] - node _T_1890 = and(_T_1888, _T_1889) @[dec_tlu_ctl.scala 2279:115] - node _T_1891 = eq(mhpme_vec[3], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] - node _T_1892 = bits(_T_1891, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1893 = eq(mhpme_vec[3], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] - node _T_1894 = bits(_T_1893, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1895 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] - node _T_1896 = bits(_T_1895, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1897 = eq(mhpme_vec[3], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] - node _T_1898 = bits(_T_1897, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1899 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] - node _T_1900 = eq(mhpme_vec[3], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] - node _T_1901 = bits(_T_1900, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1902 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] - node _T_1903 = eq(mhpme_vec[3], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] - node _T_1904 = bits(_T_1903, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1905 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] - node _T_1906 = eq(mhpme_vec[3], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] - node _T_1907 = bits(_T_1906, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1908 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] - node _T_1909 = eq(mhpme_vec[3], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] - node _T_1910 = bits(_T_1909, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1911 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] - node _T_1912 = and(_T_1911, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] - node _T_1913 = eq(mhpme_vec[3], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] - node _T_1914 = bits(_T_1913, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1915 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] - node _T_1916 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] - node _T_1917 = and(_T_1915, _T_1916) @[dec_tlu_ctl.scala 2288:101] - node _T_1918 = eq(mhpme_vec[3], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] - node _T_1919 = bits(_T_1918, 0, 0) @[dec_tlu_ctl.scala 2289:59] - node _T_1920 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] - node _T_1921 = eq(mhpme_vec[3], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] - node _T_1922 = bits(_T_1921, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1923 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] - node _T_1924 = eq(mhpme_vec[3], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] - node _T_1925 = bits(_T_1924, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1926 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] - node _T_1927 = eq(mhpme_vec[3], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] - node _T_1928 = bits(_T_1927, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1929 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] - node _T_1930 = eq(mhpme_vec[3], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] - node _T_1931 = bits(_T_1930, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1932 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] - node _T_1933 = eq(mhpme_vec[3], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] - node _T_1934 = bits(_T_1933, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1935 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] - node _T_1936 = eq(mhpme_vec[3], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] - node _T_1937 = bits(_T_1936, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1938 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] - node _T_1939 = eq(mhpme_vec[3], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] - node _T_1940 = bits(_T_1939, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1941 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] - node _T_1942 = eq(mhpme_vec[3], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] - node _T_1943 = bits(_T_1942, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1944 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] - node _T_1945 = eq(mhpme_vec[3], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] - node _T_1946 = bits(_T_1945, 0, 0) @[dec_tlu_ctl.scala 2298:59] - node _T_1947 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] - node _T_1948 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] - node _T_1949 = or(_T_1947, _T_1948) @[dec_tlu_ctl.scala 2298:101] - node _T_1950 = eq(mhpme_vec[3], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] - node _T_1951 = bits(_T_1950, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1952 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] - node _T_1953 = eq(mhpme_vec[3], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] - node _T_1954 = bits(_T_1953, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1955 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] - node _T_1956 = eq(mhpme_vec[3], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] - node _T_1957 = bits(_T_1956, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1958 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] - node _T_1959 = eq(mhpme_vec[3], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] - node _T_1960 = bits(_T_1959, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1961 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] - node _T_1962 = bits(_T_1961, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1963 = eq(mhpme_vec[3], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] - node _T_1964 = bits(_T_1963, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1965 = eq(mhpme_vec[3], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] - node _T_1966 = bits(_T_1965, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1967 = eq(mhpme_vec[3], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] - node _T_1968 = bits(_T_1967, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1969 = eq(mhpme_vec[3], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] - node _T_1970 = bits(_T_1969, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1971 = eq(mhpme_vec[3], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] - node _T_1972 = bits(_T_1971, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1973 = eq(mhpme_vec[3], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] - node _T_1974 = bits(_T_1973, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1975 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] - node _T_1976 = or(_T_1975, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] - node _T_1977 = eq(mhpme_vec[3], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] - node _T_1978 = bits(_T_1977, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1979 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] - node _T_1980 = or(_T_1979, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] - node _T_1981 = eq(mhpme_vec[3], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] - node _T_1982 = bits(_T_1981, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1983 = eq(mhpme_vec[3], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] - node _T_1984 = bits(_T_1983, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1985 = eq(mhpme_vec[3], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] - node _T_1986 = bits(_T_1985, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1987 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] - node _T_1988 = and(_T_1987, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] - node _T_1989 = eq(mhpme_vec[3], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] - node _T_1990 = bits(_T_1989, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1991 = eq(mhpme_vec[3], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] - node _T_1992 = bits(_T_1991, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_1993 = eq(mhpme_vec[3], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] - node _T_1994 = bits(_T_1993, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_1995 = eq(mhpme_vec[3], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] - node _T_1996 = bits(_T_1995, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_1997 = eq(mhpme_vec[3], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] - node _T_1998 = bits(_T_1997, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_1999 = eq(mhpme_vec[3], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] - node _T_2000 = bits(_T_1999, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_2001 = eq(mhpme_vec[3], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] - node _T_2002 = bits(_T_2001, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_2003 = eq(mhpme_vec[3], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] - node _T_2004 = bits(_T_2003, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_2005 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] - node _T_2006 = bits(_T_2005, 0, 0) @[dec_tlu_ctl.scala 2321:84] - node _T_2007 = not(_T_2006) @[dec_tlu_ctl.scala 2321:73] - node _T_2008 = eq(mhpme_vec[3], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] - node _T_2009 = bits(_T_2008, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_2010 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] - node _T_2011 = bits(_T_2010, 0, 0) @[dec_tlu_ctl.scala 2322:84] - node _T_2012 = not(_T_2011) @[dec_tlu_ctl.scala 2322:73] - node _T_2013 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] - node _T_2014 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] - node _T_2015 = and(_T_2013, _T_2014) @[dec_tlu_ctl.scala 2322:113] - node _T_2016 = orr(_T_2015) @[dec_tlu_ctl.scala 2322:125] - node _T_2017 = and(_T_2012, _T_2016) @[dec_tlu_ctl.scala 2322:98] - node _T_2018 = eq(mhpme_vec[3], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] - node _T_2019 = bits(_T_2018, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_2020 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] - node _T_2021 = eq(mhpme_vec[3], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] - node _T_2022 = bits(_T_2021, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_2023 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] - node _T_2024 = eq(mhpme_vec[3], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] - node _T_2025 = bits(_T_2024, 0, 0) @[dec_tlu_ctl.scala 2325:62] - node _T_2026 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] - node _T_2027 = eq(mhpme_vec[3], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] - node _T_2028 = bits(_T_2027, 0, 0) @[dec_tlu_ctl.scala 2327:62] - node _T_2029 = eq(mhpme_vec[3], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] - node _T_2030 = bits(_T_2029, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_2031 = eq(mhpme_vec[3], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] - node _T_2032 = bits(_T_2031, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_2033 = eq(mhpme_vec[3], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] - node _T_2034 = bits(_T_2033, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_2035 = eq(mhpme_vec[3], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] - node _T_2036 = bits(_T_2035, 0, 0) @[dec_tlu_ctl.scala 2331:62] - node _T_2037 = mux(_T_1871, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2038 = mux(_T_1873, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2039 = mux(_T_1875, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2040 = mux(_T_1877, _T_1879, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2041 = mux(_T_1881, _T_1885, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2042 = mux(_T_1887, _T_1890, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2043 = mux(_T_1892, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2044 = mux(_T_1894, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2045 = mux(_T_1896, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2046 = mux(_T_1898, _T_1899, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2047 = mux(_T_1901, _T_1902, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2048 = mux(_T_1904, _T_1905, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2049 = mux(_T_1907, _T_1908, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2050 = mux(_T_1910, _T_1912, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2051 = mux(_T_1914, _T_1917, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2052 = mux(_T_1919, _T_1920, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2053 = mux(_T_1922, _T_1923, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2054 = mux(_T_1925, _T_1926, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2055 = mux(_T_1928, _T_1929, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2056 = mux(_T_1931, _T_1932, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2057 = mux(_T_1934, _T_1935, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2058 = mux(_T_1937, _T_1938, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2059 = mux(_T_1940, _T_1941, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2060 = mux(_T_1943, _T_1944, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2061 = mux(_T_1946, _T_1949, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2062 = mux(_T_1951, _T_1952, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2063 = mux(_T_1954, _T_1955, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2064 = mux(_T_1957, _T_1958, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2065 = mux(_T_1960, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2066 = mux(_T_1962, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2067 = mux(_T_1964, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2068 = mux(_T_1966, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2069 = mux(_T_1968, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2070 = mux(_T_1970, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2071 = mux(_T_1972, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2072 = mux(_T_1974, _T_1976, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2073 = mux(_T_1978, _T_1980, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2074 = mux(_T_1982, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2075 = mux(_T_1984, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2076 = mux(_T_1986, _T_1988, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2077 = mux(_T_1990, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2078 = mux(_T_1992, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2079 = mux(_T_1994, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2080 = mux(_T_1996, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2081 = mux(_T_1998, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2082 = mux(_T_2000, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2083 = mux(_T_2002, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2084 = mux(_T_2004, _T_2007, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2085 = mux(_T_2009, _T_2017, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2086 = mux(_T_2019, _T_2020, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2087 = mux(_T_2022, _T_2023, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2088 = mux(_T_2025, _T_2026, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2089 = mux(_T_2028, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2090 = mux(_T_2030, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2091 = mux(_T_2032, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2092 = mux(_T_2034, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2093 = mux(_T_2036, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2094 = or(_T_2037, _T_2038) @[Mux.scala 27:72] - node _T_2095 = or(_T_2094, _T_2039) @[Mux.scala 27:72] - node _T_2096 = or(_T_2095, _T_2040) @[Mux.scala 27:72] - node _T_2097 = or(_T_2096, _T_2041) @[Mux.scala 27:72] - node _T_2098 = or(_T_2097, _T_2042) @[Mux.scala 27:72] - node _T_2099 = or(_T_2098, _T_2043) @[Mux.scala 27:72] - node _T_2100 = or(_T_2099, _T_2044) @[Mux.scala 27:72] - node _T_2101 = or(_T_2100, _T_2045) @[Mux.scala 27:72] - node _T_2102 = or(_T_2101, _T_2046) @[Mux.scala 27:72] + node _T_1866 = or(_T_1865, _T_1810) @[Mux.scala 27:72] + node _T_1867 = or(_T_1866, _T_1811) @[Mux.scala 27:72] + node _T_1868 = or(_T_1867, _T_1812) @[Mux.scala 27:72] + node _T_1869 = or(_T_1868, _T_1813) @[Mux.scala 27:72] + node _T_1870 = or(_T_1869, _T_1814) @[Mux.scala 27:72] + node _T_1871 = or(_T_1870, _T_1815) @[Mux.scala 27:72] + node _T_1872 = or(_T_1871, _T_1816) @[Mux.scala 27:72] + node _T_1873 = or(_T_1872, _T_1817) @[Mux.scala 27:72] + wire _T_1874 : UInt<1> @[Mux.scala 27:72] + _T_1874 <= _T_1873 @[Mux.scala 27:72] + node _T_1875 = and(_T_1593, _T_1874) @[dec_tlu_ctl.scala 2273:44] + mhpmc_inc_r[2] <= _T_1875 @[dec_tlu_ctl.scala 2273:19] + node _T_1876 = bits(mcountinhibit, 6, 6) @[dec_tlu_ctl.scala 2273:38] + node _T_1877 = not(_T_1876) @[dec_tlu_ctl.scala 2273:24] + node _T_1878 = eq(mhpme_vec[3], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] + node _T_1879 = bits(_T_1878, 0, 0) @[dec_tlu_ctl.scala 2274:62] + node _T_1880 = eq(mhpme_vec[3], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] + node _T_1881 = bits(_T_1880, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1882 = eq(mhpme_vec[3], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] + node _T_1883 = bits(_T_1882, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1884 = eq(mhpme_vec[3], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] + node _T_1885 = bits(_T_1884, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1886 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] + node _T_1887 = and(io.tlu_i0_commit_cmt, _T_1886) @[dec_tlu_ctl.scala 2277:94] + node _T_1888 = eq(mhpme_vec[3], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] + node _T_1889 = bits(_T_1888, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1890 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] + node _T_1891 = and(io.tlu_i0_commit_cmt, _T_1890) @[dec_tlu_ctl.scala 2278:94] + node _T_1892 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] + node _T_1893 = and(_T_1891, _T_1892) @[dec_tlu_ctl.scala 2278:115] + node _T_1894 = eq(mhpme_vec[3], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] + node _T_1895 = bits(_T_1894, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1896 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] + node _T_1897 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] + node _T_1898 = and(_T_1896, _T_1897) @[dec_tlu_ctl.scala 2279:115] + node _T_1899 = eq(mhpme_vec[3], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] + node _T_1900 = bits(_T_1899, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1901 = eq(mhpme_vec[3], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] + node _T_1902 = bits(_T_1901, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1903 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] + node _T_1904 = bits(_T_1903, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1905 = eq(mhpme_vec[3], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] + node _T_1906 = bits(_T_1905, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1907 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] + node _T_1908 = eq(mhpme_vec[3], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] + node _T_1909 = bits(_T_1908, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1910 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] + node _T_1911 = eq(mhpme_vec[3], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] + node _T_1912 = bits(_T_1911, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1913 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] + node _T_1914 = eq(mhpme_vec[3], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] + node _T_1915 = bits(_T_1914, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1916 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] + node _T_1917 = eq(mhpme_vec[3], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] + node _T_1918 = bits(_T_1917, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1919 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] + node _T_1920 = and(_T_1919, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] + node _T_1921 = eq(mhpme_vec[3], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] + node _T_1922 = bits(_T_1921, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1923 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] + node _T_1924 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] + node _T_1925 = and(_T_1923, _T_1924) @[dec_tlu_ctl.scala 2288:101] + node _T_1926 = eq(mhpme_vec[3], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] + node _T_1927 = bits(_T_1926, 0, 0) @[dec_tlu_ctl.scala 2289:59] + node _T_1928 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] + node _T_1929 = eq(mhpme_vec[3], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] + node _T_1930 = bits(_T_1929, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1931 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] + node _T_1932 = eq(mhpme_vec[3], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] + node _T_1933 = bits(_T_1932, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1934 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] + node _T_1935 = eq(mhpme_vec[3], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] + node _T_1936 = bits(_T_1935, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1937 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] + node _T_1938 = eq(mhpme_vec[3], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] + node _T_1939 = bits(_T_1938, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1940 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] + node _T_1941 = eq(mhpme_vec[3], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] + node _T_1942 = bits(_T_1941, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1943 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] + node _T_1944 = eq(mhpme_vec[3], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] + node _T_1945 = bits(_T_1944, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1946 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] + node _T_1947 = eq(mhpme_vec[3], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] + node _T_1948 = bits(_T_1947, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1949 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] + node _T_1950 = eq(mhpme_vec[3], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] + node _T_1951 = bits(_T_1950, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1952 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] + node _T_1953 = eq(mhpme_vec[3], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] + node _T_1954 = bits(_T_1953, 0, 0) @[dec_tlu_ctl.scala 2298:59] + node _T_1955 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] + node _T_1956 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] + node _T_1957 = or(_T_1955, _T_1956) @[dec_tlu_ctl.scala 2298:101] + node _T_1958 = eq(mhpme_vec[3], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] + node _T_1959 = bits(_T_1958, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1960 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] + node _T_1961 = eq(mhpme_vec[3], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] + node _T_1962 = bits(_T_1961, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1963 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] + node _T_1964 = eq(mhpme_vec[3], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] + node _T_1965 = bits(_T_1964, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1966 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] + node _T_1967 = eq(mhpme_vec[3], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] + node _T_1968 = bits(_T_1967, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1969 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] + node _T_1970 = bits(_T_1969, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1971 = eq(mhpme_vec[3], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] + node _T_1972 = bits(_T_1971, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1973 = eq(mhpme_vec[3], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] + node _T_1974 = bits(_T_1973, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1975 = eq(mhpme_vec[3], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] + node _T_1976 = bits(_T_1975, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1977 = eq(mhpme_vec[3], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] + node _T_1978 = bits(_T_1977, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1979 = eq(mhpme_vec[3], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] + node _T_1980 = bits(_T_1979, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1981 = eq(mhpme_vec[3], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] + node _T_1982 = bits(_T_1981, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1983 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] + node _T_1984 = or(_T_1983, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] + node _T_1985 = eq(mhpme_vec[3], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] + node _T_1986 = bits(_T_1985, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1987 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] + node _T_1988 = or(_T_1987, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] + node _T_1989 = eq(mhpme_vec[3], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] + node _T_1990 = bits(_T_1989, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1991 = eq(mhpme_vec[3], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] + node _T_1992 = bits(_T_1991, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1993 = eq(mhpme_vec[3], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] + node _T_1994 = bits(_T_1993, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1995 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] + node _T_1996 = and(_T_1995, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] + node _T_1997 = eq(mhpme_vec[3], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] + node _T_1998 = bits(_T_1997, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_1999 = eq(mhpme_vec[3], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] + node _T_2000 = bits(_T_1999, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_2001 = eq(mhpme_vec[3], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] + node _T_2002 = bits(_T_2001, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_2003 = eq(mhpme_vec[3], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] + node _T_2004 = bits(_T_2003, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_2005 = eq(mhpme_vec[3], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] + node _T_2006 = bits(_T_2005, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_2007 = eq(mhpme_vec[3], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] + node _T_2008 = bits(_T_2007, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_2009 = eq(mhpme_vec[3], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] + node _T_2010 = bits(_T_2009, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_2011 = eq(mhpme_vec[3], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] + node _T_2012 = bits(_T_2011, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_2013 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] + node _T_2014 = bits(_T_2013, 0, 0) @[dec_tlu_ctl.scala 2321:84] + node _T_2015 = not(_T_2014) @[dec_tlu_ctl.scala 2321:73] + node _T_2016 = eq(mhpme_vec[3], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] + node _T_2017 = bits(_T_2016, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_2018 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] + node _T_2019 = bits(_T_2018, 0, 0) @[dec_tlu_ctl.scala 2322:84] + node _T_2020 = not(_T_2019) @[dec_tlu_ctl.scala 2322:73] + node _T_2021 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] + node _T_2022 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] + node _T_2023 = and(_T_2021, _T_2022) @[dec_tlu_ctl.scala 2322:113] + node _T_2024 = orr(_T_2023) @[dec_tlu_ctl.scala 2322:125] + node _T_2025 = and(_T_2020, _T_2024) @[dec_tlu_ctl.scala 2322:98] + node _T_2026 = eq(mhpme_vec[3], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] + node _T_2027 = bits(_T_2026, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_2028 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] + node _T_2029 = eq(mhpme_vec[3], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] + node _T_2030 = bits(_T_2029, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_2031 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] + node _T_2032 = eq(mhpme_vec[3], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] + node _T_2033 = bits(_T_2032, 0, 0) @[dec_tlu_ctl.scala 2325:62] + node _T_2034 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] + node _T_2035 = eq(mhpme_vec[3], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] + node _T_2036 = bits(_T_2035, 0, 0) @[dec_tlu_ctl.scala 2327:62] + node _T_2037 = eq(mhpme_vec[3], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] + node _T_2038 = bits(_T_2037, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_2039 = eq(mhpme_vec[3], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] + node _T_2040 = bits(_T_2039, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_2041 = eq(mhpme_vec[3], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] + node _T_2042 = bits(_T_2041, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_2043 = eq(mhpme_vec[3], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] + node _T_2044 = bits(_T_2043, 0, 0) @[dec_tlu_ctl.scala 2331:62] + node _T_2045 = mux(_T_1879, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2046 = mux(_T_1881, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2047 = mux(_T_1883, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2048 = mux(_T_1885, _T_1887, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2049 = mux(_T_1889, _T_1893, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2050 = mux(_T_1895, _T_1898, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2051 = mux(_T_1900, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2052 = mux(_T_1902, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2053 = mux(_T_1904, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2054 = mux(_T_1906, _T_1907, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2055 = mux(_T_1909, _T_1910, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2056 = mux(_T_1912, _T_1913, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2057 = mux(_T_1915, _T_1916, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2058 = mux(_T_1918, _T_1920, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2059 = mux(_T_1922, _T_1925, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2060 = mux(_T_1927, _T_1928, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2061 = mux(_T_1930, _T_1931, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2062 = mux(_T_1933, _T_1934, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2063 = mux(_T_1936, _T_1937, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2064 = mux(_T_1939, _T_1940, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2065 = mux(_T_1942, _T_1943, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2066 = mux(_T_1945, _T_1946, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2067 = mux(_T_1948, _T_1949, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2068 = mux(_T_1951, _T_1952, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2069 = mux(_T_1954, _T_1957, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2070 = mux(_T_1959, _T_1960, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2071 = mux(_T_1962, _T_1963, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2072 = mux(_T_1965, _T_1966, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2073 = mux(_T_1968, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2074 = mux(_T_1970, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2075 = mux(_T_1972, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2076 = mux(_T_1974, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2077 = mux(_T_1976, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2078 = mux(_T_1978, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2079 = mux(_T_1980, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2080 = mux(_T_1982, _T_1984, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2081 = mux(_T_1986, _T_1988, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2082 = mux(_T_1990, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2083 = mux(_T_1992, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2084 = mux(_T_1994, _T_1996, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2085 = mux(_T_1998, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2086 = mux(_T_2000, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2087 = mux(_T_2002, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2088 = mux(_T_2004, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2089 = mux(_T_2006, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2090 = mux(_T_2008, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2091 = mux(_T_2010, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2092 = mux(_T_2012, _T_2015, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2093 = mux(_T_2017, _T_2025, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2094 = mux(_T_2027, _T_2028, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2095 = mux(_T_2030, _T_2031, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2096 = mux(_T_2033, _T_2034, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2097 = mux(_T_2036, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2098 = mux(_T_2038, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2099 = mux(_T_2040, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2100 = mux(_T_2042, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2101 = mux(_T_2044, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2102 = or(_T_2045, _T_2046) @[Mux.scala 27:72] node _T_2103 = or(_T_2102, _T_2047) @[Mux.scala 27:72] node _T_2104 = or(_T_2103, _T_2048) @[Mux.scala 27:72] node _T_2105 = or(_T_2104, _T_2049) @[Mux.scala 27:72] @@ -75539,583 +75539,583 @@ circuit quasar_wrapper : node _T_2147 = or(_T_2146, _T_2091) @[Mux.scala 27:72] node _T_2148 = or(_T_2147, _T_2092) @[Mux.scala 27:72] node _T_2149 = or(_T_2148, _T_2093) @[Mux.scala 27:72] - wire _T_2150 : UInt<1> @[Mux.scala 27:72] - _T_2150 <= _T_2149 @[Mux.scala 27:72] - node _T_2151 = and(_T_1869, _T_2150) @[dec_tlu_ctl.scala 2273:44] - mhpmc_inc_r[3] <= _T_2151 @[dec_tlu_ctl.scala 2273:19] - reg _T_2152 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2334:53] - _T_2152 <= mhpmc_inc_r[0] @[dec_tlu_ctl.scala 2334:53] - mhpmc_inc_r_d1[0] <= _T_2152 @[dec_tlu_ctl.scala 2334:20] - reg _T_2153 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2335:53] - _T_2153 <= mhpmc_inc_r[1] @[dec_tlu_ctl.scala 2335:53] - mhpmc_inc_r_d1[1] <= _T_2153 @[dec_tlu_ctl.scala 2335:20] - reg _T_2154 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2336:53] - _T_2154 <= mhpmc_inc_r[2] @[dec_tlu_ctl.scala 2336:53] - mhpmc_inc_r_d1[2] <= _T_2154 @[dec_tlu_ctl.scala 2336:20] - reg _T_2155 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2337:53] - _T_2155 <= mhpmc_inc_r[3] @[dec_tlu_ctl.scala 2337:53] - mhpmc_inc_r_d1[3] <= _T_2155 @[dec_tlu_ctl.scala 2337:20] + node _T_2150 = or(_T_2149, _T_2094) @[Mux.scala 27:72] + node _T_2151 = or(_T_2150, _T_2095) @[Mux.scala 27:72] + node _T_2152 = or(_T_2151, _T_2096) @[Mux.scala 27:72] + node _T_2153 = or(_T_2152, _T_2097) @[Mux.scala 27:72] + node _T_2154 = or(_T_2153, _T_2098) @[Mux.scala 27:72] + node _T_2155 = or(_T_2154, _T_2099) @[Mux.scala 27:72] + node _T_2156 = or(_T_2155, _T_2100) @[Mux.scala 27:72] + node _T_2157 = or(_T_2156, _T_2101) @[Mux.scala 27:72] + wire _T_2158 : UInt<1> @[Mux.scala 27:72] + _T_2158 <= _T_2157 @[Mux.scala 27:72] + node _T_2159 = and(_T_1877, _T_2158) @[dec_tlu_ctl.scala 2273:44] + mhpmc_inc_r[3] <= _T_2159 @[dec_tlu_ctl.scala 2273:19] + reg _T_2160 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2334:53] + _T_2160 <= mhpmc_inc_r[0] @[dec_tlu_ctl.scala 2334:53] + mhpmc_inc_r_d1[0] <= _T_2160 @[dec_tlu_ctl.scala 2334:20] + reg _T_2161 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2335:53] + _T_2161 <= mhpmc_inc_r[1] @[dec_tlu_ctl.scala 2335:53] + mhpmc_inc_r_d1[1] <= _T_2161 @[dec_tlu_ctl.scala 2335:20] + reg _T_2162 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2336:53] + _T_2162 <= mhpmc_inc_r[2] @[dec_tlu_ctl.scala 2336:53] + mhpmc_inc_r_d1[2] <= _T_2162 @[dec_tlu_ctl.scala 2336:20] + reg _T_2163 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2337:53] + _T_2163 <= mhpmc_inc_r[3] @[dec_tlu_ctl.scala 2337:53] + mhpmc_inc_r_d1[3] <= _T_2163 @[dec_tlu_ctl.scala 2337:20] reg perfcnt_halted_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2338:56] perfcnt_halted_d1 <= perfcnt_halted @[dec_tlu_ctl.scala 2338:56] - node _T_2156 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2341:53] - node _T_2157 = and(io.dec_tlu_dbg_halted, _T_2156) @[dec_tlu_ctl.scala 2341:44] - node _T_2158 = or(_T_2157, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2341:67] - perfcnt_halted <= _T_2158 @[dec_tlu_ctl.scala 2341:17] - node _T_2159 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2342:70] - node _T_2160 = and(io.dec_tlu_dbg_halted, _T_2159) @[dec_tlu_ctl.scala 2342:61] - node _T_2161 = not(_T_2160) @[dec_tlu_ctl.scala 2342:37] - node _T_2162 = bits(_T_2161, 0, 0) @[Bitwise.scala 72:15] - node _T_2163 = mux(_T_2162, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_2164 = bits(mhpme_vec[3], 9, 9) @[dec_tlu_ctl.scala 2342:104] - node _T_2165 = bits(mhpme_vec[2], 9, 9) @[dec_tlu_ctl.scala 2342:120] - node _T_2166 = bits(mhpme_vec[1], 9, 9) @[dec_tlu_ctl.scala 2342:136] - node _T_2167 = bits(mhpme_vec[0], 9, 9) @[dec_tlu_ctl.scala 2342:152] - node _T_2168 = cat(_T_2166, _T_2167) @[Cat.scala 29:58] - node _T_2169 = cat(_T_2164, _T_2165) @[Cat.scala 29:58] - node _T_2170 = cat(_T_2169, _T_2168) @[Cat.scala 29:58] - node perfcnt_during_sleep = and(_T_2163, _T_2170) @[dec_tlu_ctl.scala 2342:86] - node _T_2171 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2344:88] - node _T_2172 = not(_T_2171) @[dec_tlu_ctl.scala 2344:67] - node _T_2173 = and(perfcnt_halted_d1, _T_2172) @[dec_tlu_ctl.scala 2344:65] - node _T_2174 = not(_T_2173) @[dec_tlu_ctl.scala 2344:45] - node _T_2175 = and(mhpmc_inc_r_d1[0], _T_2174) @[dec_tlu_ctl.scala 2344:43] - io.dec_tlu_perfcnt0 <= _T_2175 @[dec_tlu_ctl.scala 2344:22] - node _T_2176 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2345:88] - node _T_2177 = not(_T_2176) @[dec_tlu_ctl.scala 2345:67] - node _T_2178 = and(perfcnt_halted_d1, _T_2177) @[dec_tlu_ctl.scala 2345:65] - node _T_2179 = not(_T_2178) @[dec_tlu_ctl.scala 2345:45] - node _T_2180 = and(mhpmc_inc_r_d1[1], _T_2179) @[dec_tlu_ctl.scala 2345:43] - io.dec_tlu_perfcnt1 <= _T_2180 @[dec_tlu_ctl.scala 2345:22] - node _T_2181 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2346:88] - node _T_2182 = not(_T_2181) @[dec_tlu_ctl.scala 2346:67] - node _T_2183 = and(perfcnt_halted_d1, _T_2182) @[dec_tlu_ctl.scala 2346:65] - node _T_2184 = not(_T_2183) @[dec_tlu_ctl.scala 2346:45] - node _T_2185 = and(mhpmc_inc_r_d1[2], _T_2184) @[dec_tlu_ctl.scala 2346:43] - io.dec_tlu_perfcnt2 <= _T_2185 @[dec_tlu_ctl.scala 2346:22] - node _T_2186 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2347:88] - node _T_2187 = not(_T_2186) @[dec_tlu_ctl.scala 2347:67] - node _T_2188 = and(perfcnt_halted_d1, _T_2187) @[dec_tlu_ctl.scala 2347:65] - node _T_2189 = not(_T_2188) @[dec_tlu_ctl.scala 2347:45] - node _T_2190 = and(mhpmc_inc_r_d1[3], _T_2189) @[dec_tlu_ctl.scala 2347:43] - io.dec_tlu_perfcnt3 <= _T_2190 @[dec_tlu_ctl.scala 2347:22] - node _T_2191 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2353:65] - node _T_2192 = eq(_T_2191, UInt<12>("h0b03")) @[dec_tlu_ctl.scala 2353:72] - node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2192) @[dec_tlu_ctl.scala 2353:43] - node _T_2193 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2354:23] - node _T_2194 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2354:61] - node _T_2195 = or(_T_2193, _T_2194) @[dec_tlu_ctl.scala 2354:39] - node _T_2196 = orr(mhpmc_inc_r[0]) @[dec_tlu_ctl.scala 2354:86] - node mhpmc3_wr_en1 = and(_T_2195, _T_2196) @[dec_tlu_ctl.scala 2354:66] + node _T_2164 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2341:53] + node _T_2165 = and(io.dec_tlu_dbg_halted, _T_2164) @[dec_tlu_ctl.scala 2341:44] + node _T_2166 = or(_T_2165, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2341:67] + perfcnt_halted <= _T_2166 @[dec_tlu_ctl.scala 2341:17] + node _T_2167 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2342:70] + node _T_2168 = and(io.dec_tlu_dbg_halted, _T_2167) @[dec_tlu_ctl.scala 2342:61] + node _T_2169 = not(_T_2168) @[dec_tlu_ctl.scala 2342:37] + node _T_2170 = bits(_T_2169, 0, 0) @[Bitwise.scala 72:15] + node _T_2171 = mux(_T_2170, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2172 = bits(mhpme_vec[3], 9, 9) @[dec_tlu_ctl.scala 2342:104] + node _T_2173 = bits(mhpme_vec[2], 9, 9) @[dec_tlu_ctl.scala 2342:120] + node _T_2174 = bits(mhpme_vec[1], 9, 9) @[dec_tlu_ctl.scala 2342:136] + node _T_2175 = bits(mhpme_vec[0], 9, 9) @[dec_tlu_ctl.scala 2342:152] + node _T_2176 = cat(_T_2174, _T_2175) @[Cat.scala 29:58] + node _T_2177 = cat(_T_2172, _T_2173) @[Cat.scala 29:58] + node _T_2178 = cat(_T_2177, _T_2176) @[Cat.scala 29:58] + node perfcnt_during_sleep = and(_T_2171, _T_2178) @[dec_tlu_ctl.scala 2342:86] + node _T_2179 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2344:88] + node _T_2180 = not(_T_2179) @[dec_tlu_ctl.scala 2344:67] + node _T_2181 = and(perfcnt_halted_d1, _T_2180) @[dec_tlu_ctl.scala 2344:65] + node _T_2182 = not(_T_2181) @[dec_tlu_ctl.scala 2344:45] + node _T_2183 = and(mhpmc_inc_r_d1[0], _T_2182) @[dec_tlu_ctl.scala 2344:43] + io.dec_tlu_perfcnt0 <= _T_2183 @[dec_tlu_ctl.scala 2344:22] + node _T_2184 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2345:88] + node _T_2185 = not(_T_2184) @[dec_tlu_ctl.scala 2345:67] + node _T_2186 = and(perfcnt_halted_d1, _T_2185) @[dec_tlu_ctl.scala 2345:65] + node _T_2187 = not(_T_2186) @[dec_tlu_ctl.scala 2345:45] + node _T_2188 = and(mhpmc_inc_r_d1[1], _T_2187) @[dec_tlu_ctl.scala 2345:43] + io.dec_tlu_perfcnt1 <= _T_2188 @[dec_tlu_ctl.scala 2345:22] + node _T_2189 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2346:88] + node _T_2190 = not(_T_2189) @[dec_tlu_ctl.scala 2346:67] + node _T_2191 = and(perfcnt_halted_d1, _T_2190) @[dec_tlu_ctl.scala 2346:65] + node _T_2192 = not(_T_2191) @[dec_tlu_ctl.scala 2346:45] + node _T_2193 = and(mhpmc_inc_r_d1[2], _T_2192) @[dec_tlu_ctl.scala 2346:43] + io.dec_tlu_perfcnt2 <= _T_2193 @[dec_tlu_ctl.scala 2346:22] + node _T_2194 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2347:88] + node _T_2195 = not(_T_2194) @[dec_tlu_ctl.scala 2347:67] + node _T_2196 = and(perfcnt_halted_d1, _T_2195) @[dec_tlu_ctl.scala 2347:65] + node _T_2197 = not(_T_2196) @[dec_tlu_ctl.scala 2347:45] + node _T_2198 = and(mhpmc_inc_r_d1[3], _T_2197) @[dec_tlu_ctl.scala 2347:43] + io.dec_tlu_perfcnt3 <= _T_2198 @[dec_tlu_ctl.scala 2347:22] + node _T_2199 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2353:65] + node _T_2200 = eq(_T_2199, UInt<12>("h0b03")) @[dec_tlu_ctl.scala 2353:72] + node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2200) @[dec_tlu_ctl.scala 2353:43] + node _T_2201 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2354:23] + node _T_2202 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2354:61] + node _T_2203 = or(_T_2201, _T_2202) @[dec_tlu_ctl.scala 2354:39] + node _T_2204 = orr(mhpmc_inc_r[0]) @[dec_tlu_ctl.scala 2354:86] + node mhpmc3_wr_en1 = and(_T_2203, _T_2204) @[dec_tlu_ctl.scala 2354:66] node mhpmc3_wr_en = or(mhpmc3_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2355:36] - node _T_2197 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2358:28] - node _T_2198 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2358:41] - node _T_2199 = cat(_T_2197, _T_2198) @[Cat.scala 29:58] - node _T_2200 = cat(UInt<63>("h00"), mhpmc_inc_r[0]) @[Cat.scala 29:58] - node _T_2201 = add(_T_2199, _T_2200) @[dec_tlu_ctl.scala 2358:49] - node _T_2202 = tail(_T_2201, 1) @[dec_tlu_ctl.scala 2358:49] - mhpmc3_incr <= _T_2202 @[dec_tlu_ctl.scala 2358:14] - node _T_2203 = bits(mhpmc3_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2359:36] - node _T_2204 = bits(mhpmc3_incr, 31, 0) @[dec_tlu_ctl.scala 2359:76] - node mhpmc3_ns = mux(_T_2203, io.dec_csr_wrdata_r, _T_2204) @[dec_tlu_ctl.scala 2359:21] - node _T_2205 = bits(mhpmc3_wr_en, 0, 0) @[dec_tlu_ctl.scala 2361:42] + node _T_2205 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2358:28] + node _T_2206 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2358:41] + node _T_2207 = cat(_T_2205, _T_2206) @[Cat.scala 29:58] + node _T_2208 = cat(UInt<63>("h00"), mhpmc_inc_r[0]) @[Cat.scala 29:58] + node _T_2209 = add(_T_2207, _T_2208) @[dec_tlu_ctl.scala 2358:49] + node _T_2210 = tail(_T_2209, 1) @[dec_tlu_ctl.scala 2358:49] + mhpmc3_incr <= _T_2210 @[dec_tlu_ctl.scala 2358:14] + node _T_2211 = bits(mhpmc3_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2359:36] + node _T_2212 = bits(mhpmc3_incr, 31, 0) @[dec_tlu_ctl.scala 2359:76] + node mhpmc3_ns = mux(_T_2211, io.dec_csr_wrdata_r, _T_2212) @[dec_tlu_ctl.scala 2359:21] + node _T_2213 = bits(mhpmc3_wr_en, 0, 0) @[dec_tlu_ctl.scala 2361:42] inst rvclkhdr_26 of rvclkhdr_746 @[lib.scala 368:23] rvclkhdr_26.clock <= clock rvclkhdr_26.reset <= reset rvclkhdr_26.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_26.io.en <= _T_2205 @[lib.scala 371:17] + rvclkhdr_26.io.en <= _T_2213 @[lib.scala 371:17] rvclkhdr_26.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2206 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2206 <= mhpmc3_ns @[lib.scala 374:16] - mhpmc3 <= _T_2206 @[dec_tlu_ctl.scala 2361:9] - node _T_2207 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2363:66] - node _T_2208 = eq(_T_2207, UInt<12>("h0b83")) @[dec_tlu_ctl.scala 2363:73] - node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2208) @[dec_tlu_ctl.scala 2363:44] + reg _T_2214 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2214 <= mhpmc3_ns @[lib.scala 374:16] + mhpmc3 <= _T_2214 @[dec_tlu_ctl.scala 2361:9] + node _T_2215 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2363:66] + node _T_2216 = eq(_T_2215, UInt<12>("h0b83")) @[dec_tlu_ctl.scala 2363:73] + node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2216) @[dec_tlu_ctl.scala 2363:44] node mhpmc3h_wr_en = or(mhpmc3h_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2364:38] - node _T_2209 = bits(mhpmc3h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2365:38] - node _T_2210 = bits(mhpmc3_incr, 63, 32) @[dec_tlu_ctl.scala 2365:78] - node mhpmc3h_ns = mux(_T_2209, io.dec_csr_wrdata_r, _T_2210) @[dec_tlu_ctl.scala 2365:22] - node _T_2211 = bits(mhpmc3h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2367:46] + node _T_2217 = bits(mhpmc3h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2365:38] + node _T_2218 = bits(mhpmc3_incr, 63, 32) @[dec_tlu_ctl.scala 2365:78] + node mhpmc3h_ns = mux(_T_2217, io.dec_csr_wrdata_r, _T_2218) @[dec_tlu_ctl.scala 2365:22] + node _T_2219 = bits(mhpmc3h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2367:46] inst rvclkhdr_27 of rvclkhdr_747 @[lib.scala 368:23] rvclkhdr_27.clock <= clock rvclkhdr_27.reset <= reset rvclkhdr_27.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_27.io.en <= _T_2211 @[lib.scala 371:17] + rvclkhdr_27.io.en <= _T_2219 @[lib.scala 371:17] rvclkhdr_27.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2212 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2212 <= mhpmc3h_ns @[lib.scala 374:16] - mhpmc3h <= _T_2212 @[dec_tlu_ctl.scala 2367:10] - node _T_2213 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2372:65] - node _T_2214 = eq(_T_2213, UInt<12>("h0b04")) @[dec_tlu_ctl.scala 2372:72] - node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2214) @[dec_tlu_ctl.scala 2372:43] - node _T_2215 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2373:23] - node _T_2216 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2373:61] - node _T_2217 = or(_T_2215, _T_2216) @[dec_tlu_ctl.scala 2373:39] - node _T_2218 = orr(mhpmc_inc_r[1]) @[dec_tlu_ctl.scala 2373:86] - node mhpmc4_wr_en1 = and(_T_2217, _T_2218) @[dec_tlu_ctl.scala 2373:66] + reg _T_2220 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2220 <= mhpmc3h_ns @[lib.scala 374:16] + mhpmc3h <= _T_2220 @[dec_tlu_ctl.scala 2367:10] + node _T_2221 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2372:65] + node _T_2222 = eq(_T_2221, UInt<12>("h0b04")) @[dec_tlu_ctl.scala 2372:72] + node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2222) @[dec_tlu_ctl.scala 2372:43] + node _T_2223 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2373:23] + node _T_2224 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2373:61] + node _T_2225 = or(_T_2223, _T_2224) @[dec_tlu_ctl.scala 2373:39] + node _T_2226 = orr(mhpmc_inc_r[1]) @[dec_tlu_ctl.scala 2373:86] + node mhpmc4_wr_en1 = and(_T_2225, _T_2226) @[dec_tlu_ctl.scala 2373:66] node mhpmc4_wr_en = or(mhpmc4_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2374:36] - node _T_2219 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2378:28] - node _T_2220 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2378:41] - node _T_2221 = cat(_T_2219, _T_2220) @[Cat.scala 29:58] - node _T_2222 = cat(UInt<63>("h00"), mhpmc_inc_r[1]) @[Cat.scala 29:58] - node _T_2223 = add(_T_2221, _T_2222) @[dec_tlu_ctl.scala 2378:49] - node _T_2224 = tail(_T_2223, 1) @[dec_tlu_ctl.scala 2378:49] - mhpmc4_incr <= _T_2224 @[dec_tlu_ctl.scala 2378:14] - node _T_2225 = bits(mhpmc4_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2379:36] - node _T_2226 = bits(io.dec_csr_wrdata_r, 31, 0) @[dec_tlu_ctl.scala 2379:63] - node _T_2227 = bits(mhpmc4_incr, 31, 0) @[dec_tlu_ctl.scala 2379:82] - node mhpmc4_ns = mux(_T_2225, _T_2226, _T_2227) @[dec_tlu_ctl.scala 2379:21] - node _T_2228 = bits(mhpmc4_wr_en, 0, 0) @[dec_tlu_ctl.scala 2380:43] + node _T_2227 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2378:28] + node _T_2228 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2378:41] + node _T_2229 = cat(_T_2227, _T_2228) @[Cat.scala 29:58] + node _T_2230 = cat(UInt<63>("h00"), mhpmc_inc_r[1]) @[Cat.scala 29:58] + node _T_2231 = add(_T_2229, _T_2230) @[dec_tlu_ctl.scala 2378:49] + node _T_2232 = tail(_T_2231, 1) @[dec_tlu_ctl.scala 2378:49] + mhpmc4_incr <= _T_2232 @[dec_tlu_ctl.scala 2378:14] + node _T_2233 = bits(mhpmc4_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2379:36] + node _T_2234 = bits(io.dec_csr_wrdata_r, 31, 0) @[dec_tlu_ctl.scala 2379:63] + node _T_2235 = bits(mhpmc4_incr, 31, 0) @[dec_tlu_ctl.scala 2379:82] + node mhpmc4_ns = mux(_T_2233, _T_2234, _T_2235) @[dec_tlu_ctl.scala 2379:21] + node _T_2236 = bits(mhpmc4_wr_en, 0, 0) @[dec_tlu_ctl.scala 2380:43] inst rvclkhdr_28 of rvclkhdr_748 @[lib.scala 368:23] rvclkhdr_28.clock <= clock rvclkhdr_28.reset <= reset rvclkhdr_28.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_28.io.en <= _T_2228 @[lib.scala 371:17] + rvclkhdr_28.io.en <= _T_2236 @[lib.scala 371:17] rvclkhdr_28.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2229 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2229 <= mhpmc4_ns @[lib.scala 374:16] - mhpmc4 <= _T_2229 @[dec_tlu_ctl.scala 2380:9] - node _T_2230 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2382:66] - node _T_2231 = eq(_T_2230, UInt<12>("h0b84")) @[dec_tlu_ctl.scala 2382:73] - node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2231) @[dec_tlu_ctl.scala 2382:44] + reg _T_2237 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2237 <= mhpmc4_ns @[lib.scala 374:16] + mhpmc4 <= _T_2237 @[dec_tlu_ctl.scala 2380:9] + node _T_2238 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2382:66] + node _T_2239 = eq(_T_2238, UInt<12>("h0b84")) @[dec_tlu_ctl.scala 2382:73] + node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2239) @[dec_tlu_ctl.scala 2382:44] node mhpmc4h_wr_en = or(mhpmc4h_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2383:38] - node _T_2232 = bits(mhpmc4h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2384:38] - node _T_2233 = bits(mhpmc4_incr, 63, 32) @[dec_tlu_ctl.scala 2384:78] - node mhpmc4h_ns = mux(_T_2232, io.dec_csr_wrdata_r, _T_2233) @[dec_tlu_ctl.scala 2384:22] - node _T_2234 = bits(mhpmc4h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2385:46] + node _T_2240 = bits(mhpmc4h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2384:38] + node _T_2241 = bits(mhpmc4_incr, 63, 32) @[dec_tlu_ctl.scala 2384:78] + node mhpmc4h_ns = mux(_T_2240, io.dec_csr_wrdata_r, _T_2241) @[dec_tlu_ctl.scala 2384:22] + node _T_2242 = bits(mhpmc4h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2385:46] inst rvclkhdr_29 of rvclkhdr_749 @[lib.scala 368:23] rvclkhdr_29.clock <= clock rvclkhdr_29.reset <= reset rvclkhdr_29.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_29.io.en <= _T_2234 @[lib.scala 371:17] + rvclkhdr_29.io.en <= _T_2242 @[lib.scala 371:17] rvclkhdr_29.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2235 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2235 <= mhpmc4h_ns @[lib.scala 374:16] - mhpmc4h <= _T_2235 @[dec_tlu_ctl.scala 2385:10] - node _T_2236 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2391:65] - node _T_2237 = eq(_T_2236, UInt<12>("h0b05")) @[dec_tlu_ctl.scala 2391:72] - node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2237) @[dec_tlu_ctl.scala 2391:43] - node _T_2238 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2392:23] - node _T_2239 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2392:61] - node _T_2240 = or(_T_2238, _T_2239) @[dec_tlu_ctl.scala 2392:39] - node _T_2241 = orr(mhpmc_inc_r[2]) @[dec_tlu_ctl.scala 2392:86] - node mhpmc5_wr_en1 = and(_T_2240, _T_2241) @[dec_tlu_ctl.scala 2392:66] + reg _T_2243 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2243 <= mhpmc4h_ns @[lib.scala 374:16] + mhpmc4h <= _T_2243 @[dec_tlu_ctl.scala 2385:10] + node _T_2244 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2391:65] + node _T_2245 = eq(_T_2244, UInt<12>("h0b05")) @[dec_tlu_ctl.scala 2391:72] + node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2245) @[dec_tlu_ctl.scala 2391:43] + node _T_2246 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2392:23] + node _T_2247 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2392:61] + node _T_2248 = or(_T_2246, _T_2247) @[dec_tlu_ctl.scala 2392:39] + node _T_2249 = orr(mhpmc_inc_r[2]) @[dec_tlu_ctl.scala 2392:86] + node mhpmc5_wr_en1 = and(_T_2248, _T_2249) @[dec_tlu_ctl.scala 2392:66] node mhpmc5_wr_en = or(mhpmc5_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2393:36] - node _T_2242 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2395:28] - node _T_2243 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2395:41] - node _T_2244 = cat(_T_2242, _T_2243) @[Cat.scala 29:58] - node _T_2245 = cat(UInt<63>("h00"), mhpmc_inc_r[2]) @[Cat.scala 29:58] - node _T_2246 = add(_T_2244, _T_2245) @[dec_tlu_ctl.scala 2395:49] - node _T_2247 = tail(_T_2246, 1) @[dec_tlu_ctl.scala 2395:49] - mhpmc5_incr <= _T_2247 @[dec_tlu_ctl.scala 2395:14] - node _T_2248 = bits(mhpmc5_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2396:36] - node _T_2249 = bits(mhpmc5_incr, 31, 0) @[dec_tlu_ctl.scala 2396:76] - node mhpmc5_ns = mux(_T_2248, io.dec_csr_wrdata_r, _T_2249) @[dec_tlu_ctl.scala 2396:21] - node _T_2250 = bits(mhpmc5_wr_en, 0, 0) @[dec_tlu_ctl.scala 2398:43] + node _T_2250 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2395:28] + node _T_2251 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2395:41] + node _T_2252 = cat(_T_2250, _T_2251) @[Cat.scala 29:58] + node _T_2253 = cat(UInt<63>("h00"), mhpmc_inc_r[2]) @[Cat.scala 29:58] + node _T_2254 = add(_T_2252, _T_2253) @[dec_tlu_ctl.scala 2395:49] + node _T_2255 = tail(_T_2254, 1) @[dec_tlu_ctl.scala 2395:49] + mhpmc5_incr <= _T_2255 @[dec_tlu_ctl.scala 2395:14] + node _T_2256 = bits(mhpmc5_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2396:36] + node _T_2257 = bits(mhpmc5_incr, 31, 0) @[dec_tlu_ctl.scala 2396:76] + node mhpmc5_ns = mux(_T_2256, io.dec_csr_wrdata_r, _T_2257) @[dec_tlu_ctl.scala 2396:21] + node _T_2258 = bits(mhpmc5_wr_en, 0, 0) @[dec_tlu_ctl.scala 2398:43] inst rvclkhdr_30 of rvclkhdr_750 @[lib.scala 368:23] rvclkhdr_30.clock <= clock rvclkhdr_30.reset <= reset rvclkhdr_30.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_30.io.en <= _T_2250 @[lib.scala 371:17] + rvclkhdr_30.io.en <= _T_2258 @[lib.scala 371:17] rvclkhdr_30.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2251 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2251 <= mhpmc5_ns @[lib.scala 374:16] - mhpmc5 <= _T_2251 @[dec_tlu_ctl.scala 2398:9] - node _T_2252 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2400:66] - node _T_2253 = eq(_T_2252, UInt<12>("h0b85")) @[dec_tlu_ctl.scala 2400:73] - node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2253) @[dec_tlu_ctl.scala 2400:44] + reg _T_2259 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2259 <= mhpmc5_ns @[lib.scala 374:16] + mhpmc5 <= _T_2259 @[dec_tlu_ctl.scala 2398:9] + node _T_2260 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2400:66] + node _T_2261 = eq(_T_2260, UInt<12>("h0b85")) @[dec_tlu_ctl.scala 2400:73] + node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2261) @[dec_tlu_ctl.scala 2400:44] node mhpmc5h_wr_en = or(mhpmc5h_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2401:38] - node _T_2254 = bits(mhpmc5h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2402:38] - node _T_2255 = bits(mhpmc5_incr, 63, 32) @[dec_tlu_ctl.scala 2402:78] - node mhpmc5h_ns = mux(_T_2254, io.dec_csr_wrdata_r, _T_2255) @[dec_tlu_ctl.scala 2402:22] - node _T_2256 = bits(mhpmc5h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2404:46] + node _T_2262 = bits(mhpmc5h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2402:38] + node _T_2263 = bits(mhpmc5_incr, 63, 32) @[dec_tlu_ctl.scala 2402:78] + node mhpmc5h_ns = mux(_T_2262, io.dec_csr_wrdata_r, _T_2263) @[dec_tlu_ctl.scala 2402:22] + node _T_2264 = bits(mhpmc5h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2404:46] inst rvclkhdr_31 of rvclkhdr_751 @[lib.scala 368:23] rvclkhdr_31.clock <= clock rvclkhdr_31.reset <= reset rvclkhdr_31.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_31.io.en <= _T_2256 @[lib.scala 371:17] + rvclkhdr_31.io.en <= _T_2264 @[lib.scala 371:17] rvclkhdr_31.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2257 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2257 <= mhpmc5h_ns @[lib.scala 374:16] - mhpmc5h <= _T_2257 @[dec_tlu_ctl.scala 2404:10] - node _T_2258 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2409:65] - node _T_2259 = eq(_T_2258, UInt<12>("h0b06")) @[dec_tlu_ctl.scala 2409:72] - node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2259) @[dec_tlu_ctl.scala 2409:43] - node _T_2260 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2410:23] - node _T_2261 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2410:61] - node _T_2262 = or(_T_2260, _T_2261) @[dec_tlu_ctl.scala 2410:39] - node _T_2263 = orr(mhpmc_inc_r[3]) @[dec_tlu_ctl.scala 2410:86] - node mhpmc6_wr_en1 = and(_T_2262, _T_2263) @[dec_tlu_ctl.scala 2410:66] + reg _T_2265 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2265 <= mhpmc5h_ns @[lib.scala 374:16] + mhpmc5h <= _T_2265 @[dec_tlu_ctl.scala 2404:10] + node _T_2266 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2409:65] + node _T_2267 = eq(_T_2266, UInt<12>("h0b06")) @[dec_tlu_ctl.scala 2409:72] + node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2267) @[dec_tlu_ctl.scala 2409:43] + node _T_2268 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2410:23] + node _T_2269 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2410:61] + node _T_2270 = or(_T_2268, _T_2269) @[dec_tlu_ctl.scala 2410:39] + node _T_2271 = orr(mhpmc_inc_r[3]) @[dec_tlu_ctl.scala 2410:86] + node mhpmc6_wr_en1 = and(_T_2270, _T_2271) @[dec_tlu_ctl.scala 2410:66] node mhpmc6_wr_en = or(mhpmc6_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2411:36] - node _T_2264 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2413:28] - node _T_2265 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2413:41] - node _T_2266 = cat(_T_2264, _T_2265) @[Cat.scala 29:58] - node _T_2267 = cat(UInt<63>("h00"), mhpmc_inc_r[3]) @[Cat.scala 29:58] - node _T_2268 = add(_T_2266, _T_2267) @[dec_tlu_ctl.scala 2413:49] - node _T_2269 = tail(_T_2268, 1) @[dec_tlu_ctl.scala 2413:49] - mhpmc6_incr <= _T_2269 @[dec_tlu_ctl.scala 2413:14] - node _T_2270 = bits(mhpmc6_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2414:36] - node _T_2271 = bits(mhpmc6_incr, 31, 0) @[dec_tlu_ctl.scala 2414:76] - node mhpmc6_ns = mux(_T_2270, io.dec_csr_wrdata_r, _T_2271) @[dec_tlu_ctl.scala 2414:21] - node _T_2272 = bits(mhpmc6_wr_en, 0, 0) @[dec_tlu_ctl.scala 2416:43] + node _T_2272 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2413:28] + node _T_2273 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2413:41] + node _T_2274 = cat(_T_2272, _T_2273) @[Cat.scala 29:58] + node _T_2275 = cat(UInt<63>("h00"), mhpmc_inc_r[3]) @[Cat.scala 29:58] + node _T_2276 = add(_T_2274, _T_2275) @[dec_tlu_ctl.scala 2413:49] + node _T_2277 = tail(_T_2276, 1) @[dec_tlu_ctl.scala 2413:49] + mhpmc6_incr <= _T_2277 @[dec_tlu_ctl.scala 2413:14] + node _T_2278 = bits(mhpmc6_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2414:36] + node _T_2279 = bits(mhpmc6_incr, 31, 0) @[dec_tlu_ctl.scala 2414:76] + node mhpmc6_ns = mux(_T_2278, io.dec_csr_wrdata_r, _T_2279) @[dec_tlu_ctl.scala 2414:21] + node _T_2280 = bits(mhpmc6_wr_en, 0, 0) @[dec_tlu_ctl.scala 2416:43] inst rvclkhdr_32 of rvclkhdr_752 @[lib.scala 368:23] rvclkhdr_32.clock <= clock rvclkhdr_32.reset <= reset rvclkhdr_32.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_32.io.en <= _T_2272 @[lib.scala 371:17] + rvclkhdr_32.io.en <= _T_2280 @[lib.scala 371:17] rvclkhdr_32.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2273 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2273 <= mhpmc6_ns @[lib.scala 374:16] - mhpmc6 <= _T_2273 @[dec_tlu_ctl.scala 2416:9] - node _T_2274 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2418:66] - node _T_2275 = eq(_T_2274, UInt<12>("h0b86")) @[dec_tlu_ctl.scala 2418:73] - node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2275) @[dec_tlu_ctl.scala 2418:44] + reg _T_2281 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2281 <= mhpmc6_ns @[lib.scala 374:16] + mhpmc6 <= _T_2281 @[dec_tlu_ctl.scala 2416:9] + node _T_2282 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2418:66] + node _T_2283 = eq(_T_2282, UInt<12>("h0b86")) @[dec_tlu_ctl.scala 2418:73] + node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2283) @[dec_tlu_ctl.scala 2418:44] node mhpmc6h_wr_en = or(mhpmc6h_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2419:38] - node _T_2276 = bits(mhpmc6h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2420:38] - node _T_2277 = bits(mhpmc6_incr, 63, 32) @[dec_tlu_ctl.scala 2420:78] - node mhpmc6h_ns = mux(_T_2276, io.dec_csr_wrdata_r, _T_2277) @[dec_tlu_ctl.scala 2420:22] - node _T_2278 = bits(mhpmc6h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2422:46] + node _T_2284 = bits(mhpmc6h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2420:38] + node _T_2285 = bits(mhpmc6_incr, 63, 32) @[dec_tlu_ctl.scala 2420:78] + node mhpmc6h_ns = mux(_T_2284, io.dec_csr_wrdata_r, _T_2285) @[dec_tlu_ctl.scala 2420:22] + node _T_2286 = bits(mhpmc6h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2422:46] inst rvclkhdr_33 of rvclkhdr_753 @[lib.scala 368:23] rvclkhdr_33.clock <= clock rvclkhdr_33.reset <= reset rvclkhdr_33.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_33.io.en <= _T_2278 @[lib.scala 371:17] + rvclkhdr_33.io.en <= _T_2286 @[lib.scala 371:17] rvclkhdr_33.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2279 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2279 <= mhpmc6h_ns @[lib.scala 374:16] - mhpmc6h <= _T_2279 @[dec_tlu_ctl.scala 2422:10] - node _T_2280 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2429:50] - node _T_2281 = gt(_T_2280, UInt<10>("h0204")) @[dec_tlu_ctl.scala 2429:56] - node _T_2282 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 2429:93] - node _T_2283 = orr(_T_2282) @[dec_tlu_ctl.scala 2429:102] - node _T_2284 = or(_T_2281, _T_2283) @[dec_tlu_ctl.scala 2429:71] - node _T_2285 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2429:141] - node event_saturate_r = mux(_T_2284, UInt<10>("h0204"), _T_2285) @[dec_tlu_ctl.scala 2429:28] - node _T_2286 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2431:63] - node _T_2287 = eq(_T_2286, UInt<12>("h0323")) @[dec_tlu_ctl.scala 2431:70] - node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_2287) @[dec_tlu_ctl.scala 2431:41] - node _T_2288 = bits(wr_mhpme3_r, 0, 0) @[dec_tlu_ctl.scala 2433:80] - reg _T_2289 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2288 : @[Reg.scala 28:19] - _T_2289 <= event_saturate_r @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - mhpme3 <= _T_2289 @[dec_tlu_ctl.scala 2433:9] - node _T_2290 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2438:63] - node _T_2291 = eq(_T_2290, UInt<12>("h0324")) @[dec_tlu_ctl.scala 2438:70] - node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_2291) @[dec_tlu_ctl.scala 2438:41] - node _T_2292 = bits(wr_mhpme4_r, 0, 0) @[dec_tlu_ctl.scala 2439:80] - reg _T_2293 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2292 : @[Reg.scala 28:19] - _T_2293 <= event_saturate_r @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - mhpme4 <= _T_2293 @[dec_tlu_ctl.scala 2439:9] - node _T_2294 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2445:63] - node _T_2295 = eq(_T_2294, UInt<12>("h0325")) @[dec_tlu_ctl.scala 2445:70] - node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_2295) @[dec_tlu_ctl.scala 2445:41] - node _T_2296 = bits(wr_mhpme5_r, 0, 0) @[dec_tlu_ctl.scala 2446:80] + reg _T_2287 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2287 <= mhpmc6h_ns @[lib.scala 374:16] + mhpmc6h <= _T_2287 @[dec_tlu_ctl.scala 2422:10] + node _T_2288 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2429:50] + node _T_2289 = gt(_T_2288, UInt<10>("h0204")) @[dec_tlu_ctl.scala 2429:56] + node _T_2290 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 2429:93] + node _T_2291 = orr(_T_2290) @[dec_tlu_ctl.scala 2429:102] + node _T_2292 = or(_T_2289, _T_2291) @[dec_tlu_ctl.scala 2429:71] + node _T_2293 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2429:141] + node event_saturate_r = mux(_T_2292, UInt<10>("h0204"), _T_2293) @[dec_tlu_ctl.scala 2429:28] + node _T_2294 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2431:63] + node _T_2295 = eq(_T_2294, UInt<12>("h0323")) @[dec_tlu_ctl.scala 2431:70] + node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_2295) @[dec_tlu_ctl.scala 2431:41] + node _T_2296 = bits(wr_mhpme3_r, 0, 0) @[dec_tlu_ctl.scala 2433:80] reg _T_2297 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_2296 : @[Reg.scala 28:19] _T_2297 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme5 <= _T_2297 @[dec_tlu_ctl.scala 2446:9] - node _T_2298 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2452:63] - node _T_2299 = eq(_T_2298, UInt<12>("h0326")) @[dec_tlu_ctl.scala 2452:70] - node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_2299) @[dec_tlu_ctl.scala 2452:41] - node _T_2300 = bits(wr_mhpme6_r, 0, 0) @[dec_tlu_ctl.scala 2453:80] + mhpme3 <= _T_2297 @[dec_tlu_ctl.scala 2433:9] + node _T_2298 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2438:63] + node _T_2299 = eq(_T_2298, UInt<12>("h0324")) @[dec_tlu_ctl.scala 2438:70] + node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_2299) @[dec_tlu_ctl.scala 2438:41] + node _T_2300 = bits(wr_mhpme4_r, 0, 0) @[dec_tlu_ctl.scala 2439:80] reg _T_2301 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_2300 : @[Reg.scala 28:19] _T_2301 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme6 <= _T_2301 @[dec_tlu_ctl.scala 2453:9] - node _T_2302 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2469:70] - node _T_2303 = eq(_T_2302, UInt<12>("h0320")) @[dec_tlu_ctl.scala 2469:77] - node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_2303) @[dec_tlu_ctl.scala 2469:48] - node _T_2304 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2471:54] - wire temp_ncount0 : UInt<1> - temp_ncount0 <= _T_2304 - node _T_2305 = bits(mcountinhibit, 1, 1) @[dec_tlu_ctl.scala 2472:54] - wire temp_ncount1 : UInt<1> - temp_ncount1 <= _T_2305 - node _T_2306 = bits(mcountinhibit, 6, 2) @[dec_tlu_ctl.scala 2473:55] - wire temp_ncount6_2 : UInt<5> - temp_ncount6_2 <= _T_2306 - node _T_2307 = bits(io.dec_csr_wrdata_r, 6, 2) @[dec_tlu_ctl.scala 2474:74] - node _T_2308 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2474:103] + mhpme4 <= _T_2301 @[dec_tlu_ctl.scala 2439:9] + node _T_2302 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2445:63] + node _T_2303 = eq(_T_2302, UInt<12>("h0325")) @[dec_tlu_ctl.scala 2445:70] + node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_2303) @[dec_tlu_ctl.scala 2445:41] + node _T_2304 = bits(wr_mhpme5_r, 0, 0) @[dec_tlu_ctl.scala 2446:80] + reg _T_2305 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2304 : @[Reg.scala 28:19] + _T_2305 <= event_saturate_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mhpme5 <= _T_2305 @[dec_tlu_ctl.scala 2446:9] + node _T_2306 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2452:63] + node _T_2307 = eq(_T_2306, UInt<12>("h0326")) @[dec_tlu_ctl.scala 2452:70] + node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_2307) @[dec_tlu_ctl.scala 2452:41] + node _T_2308 = bits(wr_mhpme6_r, 0, 0) @[dec_tlu_ctl.scala 2453:80] reg _T_2309 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_2308 : @[Reg.scala 28:19] - _T_2309 <= _T_2307 @[Reg.scala 28:23] + _T_2309 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - temp_ncount6_2 <= _T_2309 @[dec_tlu_ctl.scala 2474:17] - node _T_2310 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2476:72] - node _T_2311 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2476:99] - reg _T_2312 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2311 : @[Reg.scala 28:19] - _T_2312 <= _T_2310 @[Reg.scala 28:23] + mhpme6 <= _T_2309 @[dec_tlu_ctl.scala 2453:9] + node _T_2310 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2469:70] + node _T_2311 = eq(_T_2310, UInt<12>("h0320")) @[dec_tlu_ctl.scala 2469:77] + node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_2311) @[dec_tlu_ctl.scala 2469:48] + node _T_2312 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2471:54] + wire temp_ncount0 : UInt<1> + temp_ncount0 <= _T_2312 + node _T_2313 = bits(mcountinhibit, 1, 1) @[dec_tlu_ctl.scala 2472:54] + wire temp_ncount1 : UInt<1> + temp_ncount1 <= _T_2313 + node _T_2314 = bits(mcountinhibit, 6, 2) @[dec_tlu_ctl.scala 2473:55] + wire temp_ncount6_2 : UInt<5> + temp_ncount6_2 <= _T_2314 + node _T_2315 = bits(io.dec_csr_wrdata_r, 6, 2) @[dec_tlu_ctl.scala 2474:74] + node _T_2316 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2474:103] + reg _T_2317 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2316 : @[Reg.scala 28:19] + _T_2317 <= _T_2315 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - temp_ncount0 <= _T_2312 @[dec_tlu_ctl.scala 2476:15] - node _T_2313 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2314 = cat(_T_2313, temp_ncount0) @[Cat.scala 29:58] - mcountinhibit <= _T_2314 @[dec_tlu_ctl.scala 2477:16] - node _T_2315 = or(io.i0_valid_wb, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 2484:51] - node _T_2316 = or(_T_2315, io.interrupt_valid_r_d1) @[dec_tlu_ctl.scala 2484:78] - node _T_2317 = or(_T_2316, io.dec_tlu_i0_valid_wb1) @[dec_tlu_ctl.scala 2484:104] - node _T_2318 = or(_T_2317, io.dec_tlu_i0_exc_valid_wb1) @[dec_tlu_ctl.scala 2484:130] - node _T_2319 = or(_T_2318, io.dec_tlu_int_valid_wb1) @[dec_tlu_ctl.scala 2485:32] - node _T_2320 = or(_T_2319, io.clk_override) @[dec_tlu_ctl.scala 2485:59] - node _T_2321 = bits(_T_2320, 0, 0) @[dec_tlu_ctl.scala 2485:78] + temp_ncount6_2 <= _T_2317 @[dec_tlu_ctl.scala 2474:17] + node _T_2318 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2476:72] + node _T_2319 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2476:99] + reg _T_2320 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2319 : @[Reg.scala 28:19] + _T_2320 <= _T_2318 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + temp_ncount0 <= _T_2320 @[dec_tlu_ctl.scala 2476:15] + node _T_2321 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2322 = cat(_T_2321, temp_ncount0) @[Cat.scala 29:58] + mcountinhibit <= _T_2322 @[dec_tlu_ctl.scala 2477:16] + node _T_2323 = or(io.i0_valid_wb, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 2484:51] + node _T_2324 = or(_T_2323, io.interrupt_valid_r_d1) @[dec_tlu_ctl.scala 2484:78] + node _T_2325 = or(_T_2324, io.dec_tlu_i0_valid_wb1) @[dec_tlu_ctl.scala 2484:104] + node _T_2326 = or(_T_2325, io.dec_tlu_i0_exc_valid_wb1) @[dec_tlu_ctl.scala 2484:130] + node _T_2327 = or(_T_2326, io.dec_tlu_int_valid_wb1) @[dec_tlu_ctl.scala 2485:32] + node _T_2328 = or(_T_2327, io.clk_override) @[dec_tlu_ctl.scala 2485:59] + node _T_2329 = bits(_T_2328, 0, 0) @[dec_tlu_ctl.scala 2485:78] inst rvclkhdr_34 of rvclkhdr_754 @[lib.scala 343:22] rvclkhdr_34.clock <= clock rvclkhdr_34.reset <= reset rvclkhdr_34.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_34.io.en <= _T_2321 @[lib.scala 345:16] + rvclkhdr_34.io.en <= _T_2329 @[lib.scala 345:16] rvclkhdr_34.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - reg _T_2322 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2487:62] - _T_2322 <= io.i0_valid_wb @[dec_tlu_ctl.scala 2487:62] - io.dec_tlu_i0_valid_wb1 <= _T_2322 @[dec_tlu_ctl.scala 2487:30] - node _T_2323 = or(io.i0_exception_valid_r_d1, io.lsu_i0_exc_r_d1) @[dec_tlu_ctl.scala 2488:91] - node _T_2324 = not(io.trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 2488:137] - node _T_2325 = and(io.trigger_hit_r_d1, _T_2324) @[dec_tlu_ctl.scala 2488:135] - node _T_2326 = or(_T_2323, _T_2325) @[dec_tlu_ctl.scala 2488:112] - reg _T_2327 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2488:62] - _T_2327 <= _T_2326 @[dec_tlu_ctl.scala 2488:62] - io.dec_tlu_i0_exc_valid_wb1 <= _T_2327 @[dec_tlu_ctl.scala 2488:30] - reg _T_2328 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2489:62] - _T_2328 <= io.exc_cause_wb @[dec_tlu_ctl.scala 2489:62] - io.dec_tlu_exc_cause_wb1 <= _T_2328 @[dec_tlu_ctl.scala 2489:30] - reg _T_2329 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2490:62] - _T_2329 <= io.interrupt_valid_r_d1 @[dec_tlu_ctl.scala 2490:62] - io.dec_tlu_int_valid_wb1 <= _T_2329 @[dec_tlu_ctl.scala 2490:30] + reg _T_2330 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2487:62] + _T_2330 <= io.i0_valid_wb @[dec_tlu_ctl.scala 2487:62] + io.dec_tlu_i0_valid_wb1 <= _T_2330 @[dec_tlu_ctl.scala 2487:30] + node _T_2331 = or(io.i0_exception_valid_r_d1, io.lsu_i0_exc_r_d1) @[dec_tlu_ctl.scala 2488:91] + node _T_2332 = not(io.trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 2488:137] + node _T_2333 = and(io.trigger_hit_r_d1, _T_2332) @[dec_tlu_ctl.scala 2488:135] + node _T_2334 = or(_T_2331, _T_2333) @[dec_tlu_ctl.scala 2488:112] + reg _T_2335 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2488:62] + _T_2335 <= _T_2334 @[dec_tlu_ctl.scala 2488:62] + io.dec_tlu_i0_exc_valid_wb1 <= _T_2335 @[dec_tlu_ctl.scala 2488:30] + reg _T_2336 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2489:62] + _T_2336 <= io.exc_cause_wb @[dec_tlu_ctl.scala 2489:62] + io.dec_tlu_exc_cause_wb1 <= _T_2336 @[dec_tlu_ctl.scala 2489:30] + reg _T_2337 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2490:62] + _T_2337 <= io.interrupt_valid_r_d1 @[dec_tlu_ctl.scala 2490:62] + io.dec_tlu_int_valid_wb1 <= _T_2337 @[dec_tlu_ctl.scala 2490:30] io.dec_tlu_mtval_wb1 <= mtval @[dec_tlu_ctl.scala 2492:24] - node _T_2330 = bits(io.csr_pkt.csr_misa, 0, 0) @[dec_tlu_ctl.scala 2498:61] - node _T_2331 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[dec_tlu_ctl.scala 2499:42] - node _T_2332 = bits(io.csr_pkt.csr_marchid, 0, 0) @[dec_tlu_ctl.scala 2500:40] - node _T_2333 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[dec_tlu_ctl.scala 2501:39] - node _T_2334 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[dec_tlu_ctl.scala 2502:40] - node _T_2335 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58] - node _T_2336 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[dec_tlu_ctl.scala 2503:40] - node _T_2337 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 2503:103] - node _T_2338 = bits(io.mstatus, 0, 0) @[dec_tlu_ctl.scala 2503:128] - node _T_2339 = cat(UInt<3>("h00"), _T_2338) @[Cat.scala 29:58] - node _T_2340 = cat(_T_2339, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2341 = cat(UInt<3>("h00"), _T_2337) @[Cat.scala 29:58] - node _T_2342 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58] - node _T_2343 = cat(_T_2342, _T_2341) @[Cat.scala 29:58] - node _T_2344 = cat(_T_2343, _T_2340) @[Cat.scala 29:58] - node _T_2345 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[dec_tlu_ctl.scala 2504:38] - node _T_2346 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 2504:70] - node _T_2347 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 2504:96] - node _T_2348 = cat(_T_2346, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2349 = cat(_T_2348, _T_2347) @[Cat.scala 29:58] - node _T_2350 = bits(io.csr_pkt.csr_mip, 0, 0) @[dec_tlu_ctl.scala 2505:36] - node _T_2351 = bits(io.mip, 5, 3) @[dec_tlu_ctl.scala 2505:78] - node _T_2352 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 2505:102] - node _T_2353 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 2505:123] - node _T_2354 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 2505:144] - node _T_2355 = cat(_T_2354, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2356 = cat(_T_2353, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2338 = bits(io.csr_pkt.csr_misa, 0, 0) @[dec_tlu_ctl.scala 2498:61] + node _T_2339 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[dec_tlu_ctl.scala 2499:42] + node _T_2340 = bits(io.csr_pkt.csr_marchid, 0, 0) @[dec_tlu_ctl.scala 2500:40] + node _T_2341 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[dec_tlu_ctl.scala 2501:39] + node _T_2342 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[dec_tlu_ctl.scala 2502:40] + node _T_2343 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_2344 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[dec_tlu_ctl.scala 2503:40] + node _T_2345 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 2503:103] + node _T_2346 = bits(io.mstatus, 0, 0) @[dec_tlu_ctl.scala 2503:128] + node _T_2347 = cat(UInt<3>("h00"), _T_2346) @[Cat.scala 29:58] + node _T_2348 = cat(_T_2347, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2349 = cat(UInt<3>("h00"), _T_2345) @[Cat.scala 29:58] + node _T_2350 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58] + node _T_2351 = cat(_T_2350, _T_2349) @[Cat.scala 29:58] + node _T_2352 = cat(_T_2351, _T_2348) @[Cat.scala 29:58] + node _T_2353 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[dec_tlu_ctl.scala 2504:38] + node _T_2354 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 2504:70] + node _T_2355 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 2504:96] + node _T_2356 = cat(_T_2354, UInt<1>("h00")) @[Cat.scala 29:58] node _T_2357 = cat(_T_2356, _T_2355) @[Cat.scala 29:58] - node _T_2358 = cat(_T_2352, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2359 = cat(UInt<1>("h00"), _T_2351) @[Cat.scala 29:58] - node _T_2360 = cat(_T_2359, UInt<16>("h00")) @[Cat.scala 29:58] - node _T_2361 = cat(_T_2360, _T_2358) @[Cat.scala 29:58] - node _T_2362 = cat(_T_2361, _T_2357) @[Cat.scala 29:58] - node _T_2363 = bits(io.csr_pkt.csr_mie, 0, 0) @[dec_tlu_ctl.scala 2506:36] - node _T_2364 = bits(mie, 5, 3) @[dec_tlu_ctl.scala 2506:75] - node _T_2365 = bits(mie, 2, 2) @[dec_tlu_ctl.scala 2506:96] - node _T_2366 = bits(mie, 1, 1) @[dec_tlu_ctl.scala 2506:114] - node _T_2367 = bits(mie, 0, 0) @[dec_tlu_ctl.scala 2506:132] - node _T_2368 = cat(_T_2367, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2369 = cat(_T_2366, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2370 = cat(_T_2369, _T_2368) @[Cat.scala 29:58] - node _T_2371 = cat(_T_2365, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2372 = cat(UInt<1>("h00"), _T_2364) @[Cat.scala 29:58] - node _T_2373 = cat(_T_2372, UInt<16>("h00")) @[Cat.scala 29:58] - node _T_2374 = cat(_T_2373, _T_2371) @[Cat.scala 29:58] - node _T_2375 = cat(_T_2374, _T_2370) @[Cat.scala 29:58] - node _T_2376 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[dec_tlu_ctl.scala 2507:40] - node _T_2377 = bits(mcyclel, 31, 0) @[dec_tlu_ctl.scala 2507:65] - node _T_2378 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[dec_tlu_ctl.scala 2508:40] - node _T_2379 = bits(mcycleh_inc, 31, 0) @[dec_tlu_ctl.scala 2508:69] - node _T_2380 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[dec_tlu_ctl.scala 2509:42] - node _T_2381 = bits(minstretl, 31, 0) @[dec_tlu_ctl.scala 2509:72] - node _T_2382 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[dec_tlu_ctl.scala 2510:42] - node _T_2383 = bits(minstreth_inc, 31, 0) @[dec_tlu_ctl.scala 2510:72] - node _T_2384 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[dec_tlu_ctl.scala 2511:41] - node _T_2385 = bits(mscratch, 31, 0) @[dec_tlu_ctl.scala 2511:66] - node _T_2386 = bits(io.csr_pkt.csr_mepc, 0, 0) @[dec_tlu_ctl.scala 2512:37] - node _T_2387 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2388 = bits(io.csr_pkt.csr_mcause, 0, 0) @[dec_tlu_ctl.scala 2513:39] - node _T_2389 = bits(mcause, 31, 0) @[dec_tlu_ctl.scala 2513:64] - node _T_2390 = bits(io.csr_pkt.csr_mscause, 0, 0) @[dec_tlu_ctl.scala 2514:40] - node _T_2391 = bits(mscause, 3, 0) @[dec_tlu_ctl.scala 2514:80] - node _T_2392 = cat(UInt<28>("h00"), _T_2391) @[Cat.scala 29:58] - node _T_2393 = bits(io.csr_pkt.csr_mtval, 0, 0) @[dec_tlu_ctl.scala 2515:38] - node _T_2394 = bits(mtval, 31, 0) @[dec_tlu_ctl.scala 2515:63] - node _T_2395 = bits(io.csr_pkt.csr_mrac, 0, 0) @[dec_tlu_ctl.scala 2516:37] - node _T_2396 = bits(mrac, 31, 0) @[dec_tlu_ctl.scala 2516:62] - node _T_2397 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[dec_tlu_ctl.scala 2517:39] - node _T_2398 = bits(mdseac, 31, 0) @[dec_tlu_ctl.scala 2517:64] - node _T_2399 = bits(io.csr_pkt.csr_meivt, 0, 0) @[dec_tlu_ctl.scala 2518:38] - node _T_2400 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58] - node _T_2401 = bits(io.csr_pkt.csr_meihap, 0, 0) @[dec_tlu_ctl.scala 2519:39] - node _T_2402 = cat(meivt, meihap) @[Cat.scala 29:58] - node _T_2403 = cat(_T_2402, UInt<2>("h00")) @[Cat.scala 29:58] - node _T_2404 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[dec_tlu_ctl.scala 2520:41] - node _T_2405 = bits(meicurpl, 3, 0) @[dec_tlu_ctl.scala 2520:81] - node _T_2406 = cat(UInt<28>("h00"), _T_2405) @[Cat.scala 29:58] - node _T_2407 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[dec_tlu_ctl.scala 2521:41] - node _T_2408 = bits(meicidpl, 3, 0) @[dec_tlu_ctl.scala 2521:81] - node _T_2409 = cat(UInt<28>("h00"), _T_2408) @[Cat.scala 29:58] - node _T_2410 = bits(io.csr_pkt.csr_meipt, 0, 0) @[dec_tlu_ctl.scala 2522:38] - node _T_2411 = bits(meipt, 3, 0) @[dec_tlu_ctl.scala 2522:78] - node _T_2412 = cat(UInt<28>("h00"), _T_2411) @[Cat.scala 29:58] - node _T_2413 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[dec_tlu_ctl.scala 2523:37] - node _T_2414 = bits(mcgc, 8, 0) @[dec_tlu_ctl.scala 2523:77] - node _T_2415 = cat(UInt<23>("h00"), _T_2414) @[Cat.scala 29:58] - node _T_2416 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[dec_tlu_ctl.scala 2524:37] - node _T_2417 = bits(mfdc, 18, 0) @[dec_tlu_ctl.scala 2524:77] - node _T_2418 = cat(UInt<13>("h00"), _T_2417) @[Cat.scala 29:58] - node _T_2419 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[dec_tlu_ctl.scala 2525:37] - node _T_2420 = bits(io.dcsr, 15, 2) @[dec_tlu_ctl.scala 2525:85] - node _T_2421 = cat(UInt<16>("h04000"), _T_2420) @[Cat.scala 29:58] - node _T_2422 = cat(_T_2421, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_2423 = bits(io.csr_pkt.csr_dpc, 0, 0) @[dec_tlu_ctl.scala 2526:36] - node _T_2424 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2425 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[dec_tlu_ctl.scala 2527:39] - node _T_2426 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2527:64] - node _T_2427 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[dec_tlu_ctl.scala 2528:40] - node _T_2428 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2528:65] - node _T_2429 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[dec_tlu_ctl.scala 2529:39] - node _T_2430 = bits(dicad1, 31, 0) @[dec_tlu_ctl.scala 2529:64] - node _T_2431 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[dec_tlu_ctl.scala 2530:41] - node _T_2432 = bits(dicawics, 16, 16) @[dec_tlu_ctl.scala 2530:80] - node _T_2433 = bits(dicawics, 15, 14) @[dec_tlu_ctl.scala 2530:104] - node _T_2434 = bits(dicawics, 13, 0) @[dec_tlu_ctl.scala 2530:131] - node _T_2435 = cat(UInt<3>("h00"), _T_2434) @[Cat.scala 29:58] - node _T_2436 = cat(_T_2435, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2437 = cat(UInt<2>("h00"), _T_2433) @[Cat.scala 29:58] - node _T_2438 = cat(UInt<7>("h00"), _T_2432) @[Cat.scala 29:58] - node _T_2439 = cat(_T_2438, _T_2437) @[Cat.scala 29:58] - node _T_2440 = cat(_T_2439, _T_2436) @[Cat.scala 29:58] - node _T_2441 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[dec_tlu_ctl.scala 2531:38] - node _T_2442 = bits(mtsel, 1, 0) @[dec_tlu_ctl.scala 2531:78] - node _T_2443 = cat(UInt<30>("h00"), _T_2442) @[Cat.scala 29:58] - node _T_2444 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[dec_tlu_ctl.scala 2532:40] - node _T_2445 = bits(mtdata1_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2532:74] - node _T_2446 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[dec_tlu_ctl.scala 2533:40] - node _T_2447 = bits(mtdata2_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2533:74] - node _T_2448 = bits(io.csr_pkt.csr_micect, 0, 0) @[dec_tlu_ctl.scala 2534:39] - node _T_2449 = bits(micect, 31, 0) @[dec_tlu_ctl.scala 2534:64] - node _T_2450 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[dec_tlu_ctl.scala 2535:41] - node _T_2451 = bits(miccmect, 31, 0) @[dec_tlu_ctl.scala 2535:66] - node _T_2452 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[dec_tlu_ctl.scala 2536:41] - node _T_2453 = bits(mdccmect, 31, 0) @[dec_tlu_ctl.scala 2536:66] - node _T_2454 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[dec_tlu_ctl.scala 2537:39] - node _T_2455 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2537:64] - node _T_2456 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[dec_tlu_ctl.scala 2538:39] - node _T_2457 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2538:64] - node _T_2458 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[dec_tlu_ctl.scala 2539:39] - node _T_2459 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2539:64] - node _T_2460 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[dec_tlu_ctl.scala 2540:39] - node _T_2461 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2540:64] - node _T_2462 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[dec_tlu_ctl.scala 2541:40] - node _T_2463 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2541:65] - node _T_2464 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[dec_tlu_ctl.scala 2542:40] - node _T_2465 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2542:65] - node _T_2466 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[dec_tlu_ctl.scala 2543:40] - node _T_2467 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2543:65] - node _T_2468 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[dec_tlu_ctl.scala 2544:40] - node _T_2469 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2544:65] - node _T_2470 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[dec_tlu_ctl.scala 2545:38] - node _T_2471 = bits(mfdht, 5, 0) @[dec_tlu_ctl.scala 2545:78] - node _T_2472 = cat(UInt<26>("h00"), _T_2471) @[Cat.scala 29:58] - node _T_2473 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[dec_tlu_ctl.scala 2546:38] - node _T_2474 = bits(mfdhs, 1, 0) @[dec_tlu_ctl.scala 2546:78] - node _T_2475 = cat(UInt<30>("h00"), _T_2474) @[Cat.scala 29:58] - node _T_2476 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[dec_tlu_ctl.scala 2547:39] - node _T_2477 = bits(mhpme3, 9, 0) @[dec_tlu_ctl.scala 2547:79] - node _T_2478 = cat(UInt<22>("h00"), _T_2477) @[Cat.scala 29:58] - node _T_2479 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[dec_tlu_ctl.scala 2548:39] - node _T_2480 = bits(mhpme4, 9, 0) @[dec_tlu_ctl.scala 2548:79] - node _T_2481 = cat(UInt<22>("h00"), _T_2480) @[Cat.scala 29:58] - node _T_2482 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[dec_tlu_ctl.scala 2549:39] - node _T_2483 = bits(mhpme5, 9, 0) @[dec_tlu_ctl.scala 2549:78] - node _T_2484 = cat(UInt<22>("h00"), _T_2483) @[Cat.scala 29:58] - node _T_2485 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[dec_tlu_ctl.scala 2550:39] - node _T_2486 = bits(mhpme6, 9, 0) @[dec_tlu_ctl.scala 2550:78] - node _T_2487 = cat(UInt<22>("h00"), _T_2486) @[Cat.scala 29:58] - node _T_2488 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2551:46] - node _T_2489 = bits(mcountinhibit, 6, 0) @[dec_tlu_ctl.scala 2551:86] - node _T_2490 = cat(UInt<25>("h00"), _T_2489) @[Cat.scala 29:58] - node _T_2491 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[dec_tlu_ctl.scala 2552:37] - node _T_2492 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58] - node _T_2493 = cat(_T_2492, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2494 = bits(io.dec_timer_read_d, 0, 0) @[dec_tlu_ctl.scala 2553:37] - node _T_2495 = bits(io.dec_timer_rddata_d, 31, 0) @[dec_tlu_ctl.scala 2553:76] - node _T_2496 = mux(_T_2330, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2497 = mux(_T_2331, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2498 = mux(_T_2332, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2499 = mux(_T_2333, UInt<32>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2500 = mux(_T_2334, _T_2335, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2501 = mux(_T_2336, _T_2344, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2502 = mux(_T_2345, _T_2349, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2503 = mux(_T_2350, _T_2362, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2504 = mux(_T_2363, _T_2375, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2505 = mux(_T_2376, _T_2377, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2506 = mux(_T_2378, _T_2379, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2507 = mux(_T_2380, _T_2381, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2508 = mux(_T_2382, _T_2383, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2509 = mux(_T_2384, _T_2385, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2510 = mux(_T_2386, _T_2387, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2511 = mux(_T_2388, _T_2389, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2512 = mux(_T_2390, _T_2392, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2513 = mux(_T_2393, _T_2394, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2514 = mux(_T_2395, _T_2396, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2515 = mux(_T_2397, _T_2398, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2516 = mux(_T_2399, _T_2400, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2517 = mux(_T_2401, _T_2403, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2518 = mux(_T_2404, _T_2406, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2519 = mux(_T_2407, _T_2409, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2520 = mux(_T_2410, _T_2412, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2521 = mux(_T_2413, _T_2415, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2522 = mux(_T_2416, _T_2418, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2523 = mux(_T_2419, _T_2422, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2524 = mux(_T_2423, _T_2424, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2525 = mux(_T_2425, _T_2426, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2526 = mux(_T_2427, _T_2428, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2527 = mux(_T_2429, _T_2430, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2528 = mux(_T_2431, _T_2440, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2529 = mux(_T_2441, _T_2443, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2530 = mux(_T_2444, _T_2445, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2531 = mux(_T_2446, _T_2447, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2532 = mux(_T_2448, _T_2449, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2533 = mux(_T_2450, _T_2451, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2534 = mux(_T_2452, _T_2453, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2535 = mux(_T_2454, _T_2455, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2536 = mux(_T_2456, _T_2457, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2537 = mux(_T_2458, _T_2459, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2538 = mux(_T_2460, _T_2461, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2539 = mux(_T_2462, _T_2463, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2540 = mux(_T_2464, _T_2465, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2541 = mux(_T_2466, _T_2467, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2542 = mux(_T_2468, _T_2469, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2543 = mux(_T_2470, _T_2472, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2544 = mux(_T_2473, _T_2475, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2545 = mux(_T_2476, _T_2478, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2546 = mux(_T_2479, _T_2481, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2547 = mux(_T_2482, _T_2484, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2548 = mux(_T_2485, _T_2487, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2549 = mux(_T_2488, _T_2490, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2550 = mux(_T_2491, _T_2493, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2551 = mux(_T_2494, _T_2495, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2552 = or(_T_2496, _T_2497) @[Mux.scala 27:72] - node _T_2553 = or(_T_2552, _T_2498) @[Mux.scala 27:72] - node _T_2554 = or(_T_2553, _T_2499) @[Mux.scala 27:72] - node _T_2555 = or(_T_2554, _T_2500) @[Mux.scala 27:72] - node _T_2556 = or(_T_2555, _T_2501) @[Mux.scala 27:72] - node _T_2557 = or(_T_2556, _T_2502) @[Mux.scala 27:72] - node _T_2558 = or(_T_2557, _T_2503) @[Mux.scala 27:72] - node _T_2559 = or(_T_2558, _T_2504) @[Mux.scala 27:72] - node _T_2560 = or(_T_2559, _T_2505) @[Mux.scala 27:72] + node _T_2358 = bits(io.csr_pkt.csr_mip, 0, 0) @[dec_tlu_ctl.scala 2505:36] + node _T_2359 = bits(io.mip, 5, 3) @[dec_tlu_ctl.scala 2505:78] + node _T_2360 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 2505:102] + node _T_2361 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 2505:123] + node _T_2362 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 2505:144] + node _T_2363 = cat(_T_2362, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2364 = cat(_T_2361, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2365 = cat(_T_2364, _T_2363) @[Cat.scala 29:58] + node _T_2366 = cat(_T_2360, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2367 = cat(UInt<1>("h00"), _T_2359) @[Cat.scala 29:58] + node _T_2368 = cat(_T_2367, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_2369 = cat(_T_2368, _T_2366) @[Cat.scala 29:58] + node _T_2370 = cat(_T_2369, _T_2365) @[Cat.scala 29:58] + node _T_2371 = bits(io.csr_pkt.csr_mie, 0, 0) @[dec_tlu_ctl.scala 2506:36] + node _T_2372 = bits(mie, 5, 3) @[dec_tlu_ctl.scala 2506:75] + node _T_2373 = bits(mie, 2, 2) @[dec_tlu_ctl.scala 2506:96] + node _T_2374 = bits(mie, 1, 1) @[dec_tlu_ctl.scala 2506:114] + node _T_2375 = bits(mie, 0, 0) @[dec_tlu_ctl.scala 2506:132] + node _T_2376 = cat(_T_2375, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2377 = cat(_T_2374, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2378 = cat(_T_2377, _T_2376) @[Cat.scala 29:58] + node _T_2379 = cat(_T_2373, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2380 = cat(UInt<1>("h00"), _T_2372) @[Cat.scala 29:58] + node _T_2381 = cat(_T_2380, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_2382 = cat(_T_2381, _T_2379) @[Cat.scala 29:58] + node _T_2383 = cat(_T_2382, _T_2378) @[Cat.scala 29:58] + node _T_2384 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[dec_tlu_ctl.scala 2507:40] + node _T_2385 = bits(mcyclel, 31, 0) @[dec_tlu_ctl.scala 2507:65] + node _T_2386 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[dec_tlu_ctl.scala 2508:40] + node _T_2387 = bits(mcycleh_inc, 31, 0) @[dec_tlu_ctl.scala 2508:69] + node _T_2388 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[dec_tlu_ctl.scala 2509:42] + node _T_2389 = bits(minstretl, 31, 0) @[dec_tlu_ctl.scala 2509:72] + node _T_2390 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[dec_tlu_ctl.scala 2510:42] + node _T_2391 = bits(minstreth_inc, 31, 0) @[dec_tlu_ctl.scala 2510:72] + node _T_2392 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[dec_tlu_ctl.scala 2511:41] + node _T_2393 = bits(mscratch, 31, 0) @[dec_tlu_ctl.scala 2511:66] + node _T_2394 = bits(io.csr_pkt.csr_mepc, 0, 0) @[dec_tlu_ctl.scala 2512:37] + node _T_2395 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2396 = bits(io.csr_pkt.csr_mcause, 0, 0) @[dec_tlu_ctl.scala 2513:39] + node _T_2397 = bits(mcause, 31, 0) @[dec_tlu_ctl.scala 2513:64] + node _T_2398 = bits(io.csr_pkt.csr_mscause, 0, 0) @[dec_tlu_ctl.scala 2514:40] + node _T_2399 = bits(mscause, 3, 0) @[dec_tlu_ctl.scala 2514:80] + node _T_2400 = cat(UInt<28>("h00"), _T_2399) @[Cat.scala 29:58] + node _T_2401 = bits(io.csr_pkt.csr_mtval, 0, 0) @[dec_tlu_ctl.scala 2515:38] + node _T_2402 = bits(mtval, 31, 0) @[dec_tlu_ctl.scala 2515:63] + node _T_2403 = bits(io.csr_pkt.csr_mrac, 0, 0) @[dec_tlu_ctl.scala 2516:37] + node _T_2404 = bits(mrac, 31, 0) @[dec_tlu_ctl.scala 2516:62] + node _T_2405 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[dec_tlu_ctl.scala 2517:39] + node _T_2406 = bits(mdseac, 31, 0) @[dec_tlu_ctl.scala 2517:64] + node _T_2407 = bits(io.csr_pkt.csr_meivt, 0, 0) @[dec_tlu_ctl.scala 2518:38] + node _T_2408 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58] + node _T_2409 = bits(io.csr_pkt.csr_meihap, 0, 0) @[dec_tlu_ctl.scala 2519:39] + node _T_2410 = cat(meivt, meihap) @[Cat.scala 29:58] + node _T_2411 = cat(_T_2410, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_2412 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[dec_tlu_ctl.scala 2520:41] + node _T_2413 = bits(meicurpl, 3, 0) @[dec_tlu_ctl.scala 2520:81] + node _T_2414 = cat(UInt<28>("h00"), _T_2413) @[Cat.scala 29:58] + node _T_2415 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[dec_tlu_ctl.scala 2521:41] + node _T_2416 = bits(meicidpl, 3, 0) @[dec_tlu_ctl.scala 2521:81] + node _T_2417 = cat(UInt<28>("h00"), _T_2416) @[Cat.scala 29:58] + node _T_2418 = bits(io.csr_pkt.csr_meipt, 0, 0) @[dec_tlu_ctl.scala 2522:38] + node _T_2419 = bits(meipt, 3, 0) @[dec_tlu_ctl.scala 2522:78] + node _T_2420 = cat(UInt<28>("h00"), _T_2419) @[Cat.scala 29:58] + node _T_2421 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[dec_tlu_ctl.scala 2523:37] + node _T_2422 = bits(mcgc, 8, 0) @[dec_tlu_ctl.scala 2523:77] + node _T_2423 = cat(UInt<23>("h00"), _T_2422) @[Cat.scala 29:58] + node _T_2424 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[dec_tlu_ctl.scala 2524:37] + node _T_2425 = bits(mfdc, 18, 0) @[dec_tlu_ctl.scala 2524:77] + node _T_2426 = cat(UInt<13>("h00"), _T_2425) @[Cat.scala 29:58] + node _T_2427 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[dec_tlu_ctl.scala 2525:37] + node _T_2428 = bits(io.dcsr, 15, 2) @[dec_tlu_ctl.scala 2525:85] + node _T_2429 = cat(UInt<16>("h04000"), _T_2428) @[Cat.scala 29:58] + node _T_2430 = cat(_T_2429, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_2431 = bits(io.csr_pkt.csr_dpc, 0, 0) @[dec_tlu_ctl.scala 2526:36] + node _T_2432 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2433 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[dec_tlu_ctl.scala 2527:39] + node _T_2434 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2527:64] + node _T_2435 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[dec_tlu_ctl.scala 2528:40] + node _T_2436 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2528:65] + node _T_2437 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[dec_tlu_ctl.scala 2529:39] + node _T_2438 = bits(dicad1, 31, 0) @[dec_tlu_ctl.scala 2529:64] + node _T_2439 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[dec_tlu_ctl.scala 2530:41] + node _T_2440 = bits(dicawics, 16, 16) @[dec_tlu_ctl.scala 2530:80] + node _T_2441 = bits(dicawics, 15, 14) @[dec_tlu_ctl.scala 2530:104] + node _T_2442 = bits(dicawics, 13, 0) @[dec_tlu_ctl.scala 2530:131] + node _T_2443 = cat(UInt<3>("h00"), _T_2442) @[Cat.scala 29:58] + node _T_2444 = cat(_T_2443, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2445 = cat(UInt<2>("h00"), _T_2441) @[Cat.scala 29:58] + node _T_2446 = cat(UInt<7>("h00"), _T_2440) @[Cat.scala 29:58] + node _T_2447 = cat(_T_2446, _T_2445) @[Cat.scala 29:58] + node _T_2448 = cat(_T_2447, _T_2444) @[Cat.scala 29:58] + node _T_2449 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[dec_tlu_ctl.scala 2531:38] + node _T_2450 = bits(mtsel, 1, 0) @[dec_tlu_ctl.scala 2531:78] + node _T_2451 = cat(UInt<30>("h00"), _T_2450) @[Cat.scala 29:58] + node _T_2452 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[dec_tlu_ctl.scala 2532:40] + node _T_2453 = bits(mtdata1_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2532:74] + node _T_2454 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[dec_tlu_ctl.scala 2533:40] + node _T_2455 = bits(mtdata2_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2533:74] + node _T_2456 = bits(io.csr_pkt.csr_micect, 0, 0) @[dec_tlu_ctl.scala 2534:39] + node _T_2457 = bits(micect, 31, 0) @[dec_tlu_ctl.scala 2534:64] + node _T_2458 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[dec_tlu_ctl.scala 2535:41] + node _T_2459 = bits(miccmect, 31, 0) @[dec_tlu_ctl.scala 2535:66] + node _T_2460 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[dec_tlu_ctl.scala 2536:41] + node _T_2461 = bits(mdccmect, 31, 0) @[dec_tlu_ctl.scala 2536:66] + node _T_2462 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[dec_tlu_ctl.scala 2537:39] + node _T_2463 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2537:64] + node _T_2464 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[dec_tlu_ctl.scala 2538:39] + node _T_2465 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2538:64] + node _T_2466 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[dec_tlu_ctl.scala 2539:39] + node _T_2467 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2539:64] + node _T_2468 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[dec_tlu_ctl.scala 2540:39] + node _T_2469 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2540:64] + node _T_2470 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[dec_tlu_ctl.scala 2541:40] + node _T_2471 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2541:65] + node _T_2472 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[dec_tlu_ctl.scala 2542:40] + node _T_2473 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2542:65] + node _T_2474 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[dec_tlu_ctl.scala 2543:40] + node _T_2475 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2543:65] + node _T_2476 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[dec_tlu_ctl.scala 2544:40] + node _T_2477 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2544:65] + node _T_2478 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[dec_tlu_ctl.scala 2545:38] + node _T_2479 = bits(mfdht, 5, 0) @[dec_tlu_ctl.scala 2545:78] + node _T_2480 = cat(UInt<26>("h00"), _T_2479) @[Cat.scala 29:58] + node _T_2481 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[dec_tlu_ctl.scala 2546:38] + node _T_2482 = bits(mfdhs, 1, 0) @[dec_tlu_ctl.scala 2546:78] + node _T_2483 = cat(UInt<30>("h00"), _T_2482) @[Cat.scala 29:58] + node _T_2484 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[dec_tlu_ctl.scala 2547:39] + node _T_2485 = bits(mhpme3, 9, 0) @[dec_tlu_ctl.scala 2547:79] + node _T_2486 = cat(UInt<22>("h00"), _T_2485) @[Cat.scala 29:58] + node _T_2487 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[dec_tlu_ctl.scala 2548:39] + node _T_2488 = bits(mhpme4, 9, 0) @[dec_tlu_ctl.scala 2548:79] + node _T_2489 = cat(UInt<22>("h00"), _T_2488) @[Cat.scala 29:58] + node _T_2490 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[dec_tlu_ctl.scala 2549:39] + node _T_2491 = bits(mhpme5, 9, 0) @[dec_tlu_ctl.scala 2549:78] + node _T_2492 = cat(UInt<22>("h00"), _T_2491) @[Cat.scala 29:58] + node _T_2493 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[dec_tlu_ctl.scala 2550:39] + node _T_2494 = bits(mhpme6, 9, 0) @[dec_tlu_ctl.scala 2550:78] + node _T_2495 = cat(UInt<22>("h00"), _T_2494) @[Cat.scala 29:58] + node _T_2496 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2551:46] + node _T_2497 = bits(mcountinhibit, 6, 0) @[dec_tlu_ctl.scala 2551:86] + node _T_2498 = cat(UInt<25>("h00"), _T_2497) @[Cat.scala 29:58] + node _T_2499 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[dec_tlu_ctl.scala 2552:37] + node _T_2500 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58] + node _T_2501 = cat(_T_2500, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2502 = bits(io.dec_timer_read_d, 0, 0) @[dec_tlu_ctl.scala 2553:37] + node _T_2503 = bits(io.dec_timer_rddata_d, 31, 0) @[dec_tlu_ctl.scala 2553:76] + node _T_2504 = mux(_T_2338, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2505 = mux(_T_2339, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2506 = mux(_T_2340, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2507 = mux(_T_2341, UInt<32>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2508 = mux(_T_2342, _T_2343, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2509 = mux(_T_2344, _T_2352, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2510 = mux(_T_2353, _T_2357, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2511 = mux(_T_2358, _T_2370, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2512 = mux(_T_2371, _T_2383, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2513 = mux(_T_2384, _T_2385, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2514 = mux(_T_2386, _T_2387, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2515 = mux(_T_2388, _T_2389, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2516 = mux(_T_2390, _T_2391, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2517 = mux(_T_2392, _T_2393, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2518 = mux(_T_2394, _T_2395, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2519 = mux(_T_2396, _T_2397, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2520 = mux(_T_2398, _T_2400, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2521 = mux(_T_2401, _T_2402, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2522 = mux(_T_2403, _T_2404, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2523 = mux(_T_2405, _T_2406, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2524 = mux(_T_2407, _T_2408, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2525 = mux(_T_2409, _T_2411, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2526 = mux(_T_2412, _T_2414, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2527 = mux(_T_2415, _T_2417, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2528 = mux(_T_2418, _T_2420, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2529 = mux(_T_2421, _T_2423, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2530 = mux(_T_2424, _T_2426, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2531 = mux(_T_2427, _T_2430, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2532 = mux(_T_2431, _T_2432, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2533 = mux(_T_2433, _T_2434, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2534 = mux(_T_2435, _T_2436, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2535 = mux(_T_2437, _T_2438, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2536 = mux(_T_2439, _T_2448, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2537 = mux(_T_2449, _T_2451, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2538 = mux(_T_2452, _T_2453, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2539 = mux(_T_2454, _T_2455, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2540 = mux(_T_2456, _T_2457, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2541 = mux(_T_2458, _T_2459, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2542 = mux(_T_2460, _T_2461, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2543 = mux(_T_2462, _T_2463, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2544 = mux(_T_2464, _T_2465, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2545 = mux(_T_2466, _T_2467, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2546 = mux(_T_2468, _T_2469, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2547 = mux(_T_2470, _T_2471, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2548 = mux(_T_2472, _T_2473, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2549 = mux(_T_2474, _T_2475, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2550 = mux(_T_2476, _T_2477, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2551 = mux(_T_2478, _T_2480, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2552 = mux(_T_2481, _T_2483, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2553 = mux(_T_2484, _T_2486, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2554 = mux(_T_2487, _T_2489, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2555 = mux(_T_2490, _T_2492, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2556 = mux(_T_2493, _T_2495, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2557 = mux(_T_2496, _T_2498, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2558 = mux(_T_2499, _T_2501, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2559 = mux(_T_2502, _T_2503, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2560 = or(_T_2504, _T_2505) @[Mux.scala 27:72] node _T_2561 = or(_T_2560, _T_2506) @[Mux.scala 27:72] node _T_2562 = or(_T_2561, _T_2507) @[Mux.scala 27:72] node _T_2563 = or(_T_2562, _T_2508) @[Mux.scala 27:72] @@ -76162,9 +76162,17 @@ circuit quasar_wrapper : node _T_2604 = or(_T_2603, _T_2549) @[Mux.scala 27:72] node _T_2605 = or(_T_2604, _T_2550) @[Mux.scala 27:72] node _T_2606 = or(_T_2605, _T_2551) @[Mux.scala 27:72] - wire _T_2607 : UInt @[Mux.scala 27:72] - _T_2607 <= _T_2606 @[Mux.scala 27:72] - io.dec_csr_rddata_d <= _T_2607 @[dec_tlu_ctl.scala 2497:21] + node _T_2607 = or(_T_2606, _T_2552) @[Mux.scala 27:72] + node _T_2608 = or(_T_2607, _T_2553) @[Mux.scala 27:72] + node _T_2609 = or(_T_2608, _T_2554) @[Mux.scala 27:72] + node _T_2610 = or(_T_2609, _T_2555) @[Mux.scala 27:72] + node _T_2611 = or(_T_2610, _T_2556) @[Mux.scala 27:72] + node _T_2612 = or(_T_2611, _T_2557) @[Mux.scala 27:72] + node _T_2613 = or(_T_2612, _T_2558) @[Mux.scala 27:72] + node _T_2614 = or(_T_2613, _T_2559) @[Mux.scala 27:72] + wire _T_2615 : UInt @[Mux.scala 27:72] + _T_2615 <= _T_2614 @[Mux.scala 27:72] + io.dec_csr_rddata_d <= _T_2615 @[dec_tlu_ctl.scala 2497:21] module dec_decode_csr_read : input clock : Clock diff --git a/quasar_wrapper.v b/quasar_wrapper.v index 0d9841d2..22ccee53 100644 --- a/quasar_wrapper.v +++ b/quasar_wrapper.v @@ -50891,13 +50891,13 @@ module csr_tlu( wire _T_2 = ~io_rfpc_i0_r; // @[dec_tlu_ctl.scala 1450:68] wire _T_5 = io_dec_csr_wraddr_r == 12'h300; // @[dec_tlu_ctl.scala 1451:71] wire wr_mstatus_r = io_dec_csr_wen_r_mod & _T_5; // @[dec_tlu_ctl.scala 1451:42] - wire _T_488 = io_dec_csr_wraddr_r == 12'h7c6; // @[dec_tlu_ctl.scala 1837:68] - wire wr_mpmc_r = io_dec_csr_wen_r_mod & _T_488; // @[dec_tlu_ctl.scala 1837:39] - wire _T_500 = ~io_dec_csr_wrdata_r[1]; // @[dec_tlu_ctl.scala 1845:37] + wire _T_498 = io_dec_csr_wraddr_r == 12'h7c6; // @[dec_tlu_ctl.scala 1837:68] + wire wr_mpmc_r = io_dec_csr_wen_r_mod & _T_498; // @[dec_tlu_ctl.scala 1837:39] + wire _T_510 = ~io_dec_csr_wrdata_r[1]; // @[dec_tlu_ctl.scala 1845:37] reg mpmc_b; // @[dec_tlu_ctl.scala 1847:44] wire mpmc = ~mpmc_b; // @[dec_tlu_ctl.scala 1850:10] - wire _T_501 = ~mpmc; // @[dec_tlu_ctl.scala 1845:62] - wire mpmc_b_ns = wr_mpmc_r ? _T_500 : _T_501; // @[dec_tlu_ctl.scala 1845:18] + wire _T_511 = ~mpmc; // @[dec_tlu_ctl.scala 1845:62] + wire mpmc_b_ns = wr_mpmc_r ? _T_510 : _T_511; // @[dec_tlu_ctl.scala 1845:18] wire _T_6 = ~mpmc_b_ns; // @[dec_tlu_ctl.scala 1454:28] wire set_mie_pmu_fw_halt = _T_6 & io_fw_halt_req; // @[dec_tlu_ctl.scala 1454:39] wire _T_7 = ~wr_mstatus_r; // @[dec_tlu_ctl.scala 1457:5] @@ -50932,24 +50932,24 @@ module csr_tlu( wire _T_58 = io_dec_csr_wraddr_r == 12'h305; // @[dec_tlu_ctl.scala 1476:69] reg [30:0] _T_62; // @[lib.scala 374:16] reg [31:0] mdccmect; // @[lib.scala 374:16] - wire [62:0] _T_564 = 63'hffffffff << mdccmect[31:27]; // @[dec_tlu_ctl.scala 1897:41] - wire [31:0] _T_566 = {5'h0,mdccmect[26:0]}; // @[Cat.scala 29:58] - wire [62:0] _GEN_9 = {{31'd0}, _T_566}; // @[dec_tlu_ctl.scala 1897:61] - wire [62:0] _T_567 = _T_564 & _GEN_9; // @[dec_tlu_ctl.scala 1897:61] - wire mdccme_ce_req = |_T_567; // @[dec_tlu_ctl.scala 1897:94] + wire [62:0] _T_574 = 63'hffffffff << mdccmect[31:27]; // @[dec_tlu_ctl.scala 1897:41] + wire [31:0] _T_576 = {5'h0,mdccmect[26:0]}; // @[Cat.scala 29:58] + wire [62:0] _GEN_9 = {{31'd0}, _T_576}; // @[dec_tlu_ctl.scala 1897:61] + wire [62:0] _T_577 = _T_574 & _GEN_9; // @[dec_tlu_ctl.scala 1897:61] + wire mdccme_ce_req = |_T_577; // @[dec_tlu_ctl.scala 1897:94] reg [31:0] miccmect; // @[lib.scala 374:16] - wire [62:0] _T_544 = 63'hffffffff << miccmect[31:27]; // @[dec_tlu_ctl.scala 1882:40] - wire [31:0] _T_546 = {5'h0,miccmect[26:0]}; // @[Cat.scala 29:58] - wire [62:0] _GEN_10 = {{31'd0}, _T_546}; // @[dec_tlu_ctl.scala 1882:60] - wire [62:0] _T_547 = _T_544 & _GEN_10; // @[dec_tlu_ctl.scala 1882:60] - wire miccme_ce_req = |_T_547; // @[dec_tlu_ctl.scala 1882:93] + wire [62:0] _T_554 = 63'hffffffff << miccmect[31:27]; // @[dec_tlu_ctl.scala 1882:40] + wire [31:0] _T_556 = {5'h0,miccmect[26:0]}; // @[Cat.scala 29:58] + wire [62:0] _GEN_10 = {{31'd0}, _T_556}; // @[dec_tlu_ctl.scala 1882:60] + wire [62:0] _T_557 = _T_554 & _GEN_10; // @[dec_tlu_ctl.scala 1882:60] + wire miccme_ce_req = |_T_557; // @[dec_tlu_ctl.scala 1882:93] wire _T_63 = mdccme_ce_req | miccme_ce_req; // @[dec_tlu_ctl.scala 1490:30] reg [31:0] micect; // @[lib.scala 374:16] - wire [62:0] _T_522 = 63'hffffffff << micect[31:27]; // @[dec_tlu_ctl.scala 1867:39] - wire [31:0] _T_524 = {5'h0,micect[26:0]}; // @[Cat.scala 29:58] - wire [62:0] _GEN_11 = {{31'd0}, _T_524}; // @[dec_tlu_ctl.scala 1867:57] - wire [62:0] _T_525 = _T_522 & _GEN_11; // @[dec_tlu_ctl.scala 1867:57] - wire mice_ce_req = |_T_525; // @[dec_tlu_ctl.scala 1867:88] + wire [62:0] _T_532 = 63'hffffffff << micect[31:27]; // @[dec_tlu_ctl.scala 1867:39] + wire [31:0] _T_534 = {5'h0,micect[26:0]}; // @[Cat.scala 29:58] + wire [62:0] _GEN_11 = {{31'd0}, _T_534}; // @[dec_tlu_ctl.scala 1867:57] + wire [62:0] _T_535 = _T_532 & _GEN_11; // @[dec_tlu_ctl.scala 1867:57] + wire mice_ce_req = |_T_535; // @[dec_tlu_ctl.scala 1867:88] wire ce_int = _T_63 | mice_ce_req; // @[dec_tlu_ctl.scala 1490:46] wire [2:0] _T_65 = {io_mexintpend,io_timer_int_sync,io_soft_int_sync}; // @[Cat.scala 29:58] wire [2:0] _T_67 = {ce_int,io_dec_timer_t0_pulse,io_dec_timer_t1_pulse}; // @[Cat.scala 29:58] @@ -51141,427 +51141,423 @@ module csr_tlu( reg [8:0] mcgc; // @[lib.scala 374:16] wire _T_337 = io_dec_csr_wraddr_r == 12'h7f9; // @[dec_tlu_ctl.scala 1743:68] reg [14:0] mfdc_int; // @[lib.scala 374:16] - wire [2:0] _T_341 = ~io_dec_csr_wrdata_r[18:16]; // @[dec_tlu_ctl.scala 1756:19] - wire [2:0] _T_345 = ~mfdc_int[14:12]; // @[dec_tlu_ctl.scala 1757:19] - wire [18:0] mfdc = {_T_345,4'h0,mfdc_int[11:0]}; // @[Cat.scala 29:58] - wire _T_357 = io_dec_csr_wraddr_r == 12'h7c2; // @[dec_tlu_ctl.scala 1776:77] - wire _T_358 = io_dec_csr_wen_r_mod & _T_357; // @[dec_tlu_ctl.scala 1776:48] - wire _T_360 = _T_358 & _T_297; // @[dec_tlu_ctl.scala 1776:87] - wire _T_361 = ~io_take_ext_int_start; // @[dec_tlu_ctl.scala 1776:113] - wire _T_364 = io_dec_csr_wraddr_r == 12'h7c0; // @[dec_tlu_ctl.scala 1783:68] - wire _T_368 = ~io_dec_csr_wrdata_r[31]; // @[dec_tlu_ctl.scala 1786:71] - wire _T_369 = io_dec_csr_wrdata_r[30] & _T_368; // @[dec_tlu_ctl.scala 1786:69] - wire _T_373 = ~io_dec_csr_wrdata_r[29]; // @[dec_tlu_ctl.scala 1787:73] - wire _T_374 = io_dec_csr_wrdata_r[28] & _T_373; // @[dec_tlu_ctl.scala 1787:71] - wire _T_378 = ~io_dec_csr_wrdata_r[27]; // @[dec_tlu_ctl.scala 1788:73] - wire _T_379 = io_dec_csr_wrdata_r[26] & _T_378; // @[dec_tlu_ctl.scala 1788:71] - wire _T_383 = ~io_dec_csr_wrdata_r[25]; // @[dec_tlu_ctl.scala 1789:73] - wire _T_384 = io_dec_csr_wrdata_r[24] & _T_383; // @[dec_tlu_ctl.scala 1789:71] - wire _T_388 = ~io_dec_csr_wrdata_r[23]; // @[dec_tlu_ctl.scala 1790:73] - wire _T_389 = io_dec_csr_wrdata_r[22] & _T_388; // @[dec_tlu_ctl.scala 1790:71] - wire _T_393 = ~io_dec_csr_wrdata_r[21]; // @[dec_tlu_ctl.scala 1791:73] - wire _T_394 = io_dec_csr_wrdata_r[20] & _T_393; // @[dec_tlu_ctl.scala 1791:71] - wire _T_398 = ~io_dec_csr_wrdata_r[19]; // @[dec_tlu_ctl.scala 1792:73] - wire _T_399 = io_dec_csr_wrdata_r[18] & _T_398; // @[dec_tlu_ctl.scala 1792:71] - wire _T_403 = ~io_dec_csr_wrdata_r[17]; // @[dec_tlu_ctl.scala 1793:73] - wire _T_404 = io_dec_csr_wrdata_r[16] & _T_403; // @[dec_tlu_ctl.scala 1793:71] - wire _T_408 = ~io_dec_csr_wrdata_r[15]; // @[dec_tlu_ctl.scala 1794:73] - wire _T_409 = io_dec_csr_wrdata_r[14] & _T_408; // @[dec_tlu_ctl.scala 1794:71] - wire _T_413 = ~io_dec_csr_wrdata_r[13]; // @[dec_tlu_ctl.scala 1795:73] - wire _T_414 = io_dec_csr_wrdata_r[12] & _T_413; // @[dec_tlu_ctl.scala 1795:71] - wire _T_418 = ~io_dec_csr_wrdata_r[11]; // @[dec_tlu_ctl.scala 1796:73] - wire _T_419 = io_dec_csr_wrdata_r[10] & _T_418; // @[dec_tlu_ctl.scala 1796:71] - wire _T_423 = ~io_dec_csr_wrdata_r[9]; // @[dec_tlu_ctl.scala 1797:73] - wire _T_424 = io_dec_csr_wrdata_r[8] & _T_423; // @[dec_tlu_ctl.scala 1797:70] - wire _T_428 = ~io_dec_csr_wrdata_r[7]; // @[dec_tlu_ctl.scala 1798:73] - wire _T_429 = io_dec_csr_wrdata_r[6] & _T_428; // @[dec_tlu_ctl.scala 1798:70] - wire _T_433 = ~io_dec_csr_wrdata_r[5]; // @[dec_tlu_ctl.scala 1799:73] - wire _T_434 = io_dec_csr_wrdata_r[4] & _T_433; // @[dec_tlu_ctl.scala 1799:70] - wire _T_438 = ~io_dec_csr_wrdata_r[3]; // @[dec_tlu_ctl.scala 1800:73] - wire _T_439 = io_dec_csr_wrdata_r[2] & _T_438; // @[dec_tlu_ctl.scala 1800:70] - wire _T_444 = io_dec_csr_wrdata_r[0] & _T_500; // @[dec_tlu_ctl.scala 1801:70] - wire [7:0] _T_451 = {io_dec_csr_wrdata_r[7],_T_429,io_dec_csr_wrdata_r[5],_T_434,io_dec_csr_wrdata_r[3],_T_439,io_dec_csr_wrdata_r[1],_T_444}; // @[Cat.scala 29:58] - wire [15:0] _T_459 = {io_dec_csr_wrdata_r[15],_T_409,io_dec_csr_wrdata_r[13],_T_414,io_dec_csr_wrdata_r[11],_T_419,io_dec_csr_wrdata_r[9],_T_424,_T_451}; // @[Cat.scala 29:58] - wire [7:0] _T_466 = {io_dec_csr_wrdata_r[23],_T_389,io_dec_csr_wrdata_r[21],_T_394,io_dec_csr_wrdata_r[19],_T_399,io_dec_csr_wrdata_r[17],_T_404}; // @[Cat.scala 29:58] - wire [15:0] _T_474 = {io_dec_csr_wrdata_r[31],_T_369,io_dec_csr_wrdata_r[29],_T_374,io_dec_csr_wrdata_r[27],_T_379,io_dec_csr_wrdata_r[25],_T_384,_T_466}; // @[Cat.scala 29:58] + wire [2:0] _T_341 = ~io_dec_csr_wrdata_r[18:16]; // @[dec_tlu_ctl.scala 1752:20] + wire _T_344 = ~io_dec_csr_wrdata_r[6]; // @[dec_tlu_ctl.scala 1752:75] + wire [6:0] _T_346 = {_T_344,io_dec_csr_wrdata_r[5:0]}; // @[Cat.scala 29:58] + wire [7:0] _T_347 = {_T_341,io_dec_csr_wrdata_r[11:7]}; // @[Cat.scala 29:58] + wire [2:0] _T_350 = ~mfdc_int[14:12]; // @[dec_tlu_ctl.scala 1753:20] + wire _T_353 = ~mfdc_int[6]; // @[dec_tlu_ctl.scala 1753:63] + wire [18:0] mfdc = {_T_350,4'h0,mfdc_int[11:7],_T_353,mfdc_int[5:0]}; // @[Cat.scala 29:58] + wire _T_367 = io_dec_csr_wraddr_r == 12'h7c2; // @[dec_tlu_ctl.scala 1776:77] + wire _T_368 = io_dec_csr_wen_r_mod & _T_367; // @[dec_tlu_ctl.scala 1776:48] + wire _T_370 = _T_368 & _T_297; // @[dec_tlu_ctl.scala 1776:87] + wire _T_371 = ~io_take_ext_int_start; // @[dec_tlu_ctl.scala 1776:113] + wire _T_374 = io_dec_csr_wraddr_r == 12'h7c0; // @[dec_tlu_ctl.scala 1783:68] + wire _T_378 = ~io_dec_csr_wrdata_r[31]; // @[dec_tlu_ctl.scala 1786:71] + wire _T_379 = io_dec_csr_wrdata_r[30] & _T_378; // @[dec_tlu_ctl.scala 1786:69] + wire _T_383 = ~io_dec_csr_wrdata_r[29]; // @[dec_tlu_ctl.scala 1787:73] + wire _T_384 = io_dec_csr_wrdata_r[28] & _T_383; // @[dec_tlu_ctl.scala 1787:71] + wire _T_388 = ~io_dec_csr_wrdata_r[27]; // @[dec_tlu_ctl.scala 1788:73] + wire _T_389 = io_dec_csr_wrdata_r[26] & _T_388; // @[dec_tlu_ctl.scala 1788:71] + wire _T_393 = ~io_dec_csr_wrdata_r[25]; // @[dec_tlu_ctl.scala 1789:73] + wire _T_394 = io_dec_csr_wrdata_r[24] & _T_393; // @[dec_tlu_ctl.scala 1789:71] + wire _T_398 = ~io_dec_csr_wrdata_r[23]; // @[dec_tlu_ctl.scala 1790:73] + wire _T_399 = io_dec_csr_wrdata_r[22] & _T_398; // @[dec_tlu_ctl.scala 1790:71] + wire _T_403 = ~io_dec_csr_wrdata_r[21]; // @[dec_tlu_ctl.scala 1791:73] + wire _T_404 = io_dec_csr_wrdata_r[20] & _T_403; // @[dec_tlu_ctl.scala 1791:71] + wire _T_408 = ~io_dec_csr_wrdata_r[19]; // @[dec_tlu_ctl.scala 1792:73] + wire _T_409 = io_dec_csr_wrdata_r[18] & _T_408; // @[dec_tlu_ctl.scala 1792:71] + wire _T_413 = ~io_dec_csr_wrdata_r[17]; // @[dec_tlu_ctl.scala 1793:73] + wire _T_414 = io_dec_csr_wrdata_r[16] & _T_413; // @[dec_tlu_ctl.scala 1793:71] + wire _T_418 = ~io_dec_csr_wrdata_r[15]; // @[dec_tlu_ctl.scala 1794:73] + wire _T_419 = io_dec_csr_wrdata_r[14] & _T_418; // @[dec_tlu_ctl.scala 1794:71] + wire _T_423 = ~io_dec_csr_wrdata_r[13]; // @[dec_tlu_ctl.scala 1795:73] + wire _T_424 = io_dec_csr_wrdata_r[12] & _T_423; // @[dec_tlu_ctl.scala 1795:71] + wire _T_428 = ~io_dec_csr_wrdata_r[11]; // @[dec_tlu_ctl.scala 1796:73] + wire _T_429 = io_dec_csr_wrdata_r[10] & _T_428; // @[dec_tlu_ctl.scala 1796:71] + wire _T_433 = ~io_dec_csr_wrdata_r[9]; // @[dec_tlu_ctl.scala 1797:73] + wire _T_434 = io_dec_csr_wrdata_r[8] & _T_433; // @[dec_tlu_ctl.scala 1797:70] + wire _T_438 = ~io_dec_csr_wrdata_r[7]; // @[dec_tlu_ctl.scala 1798:73] + wire _T_439 = io_dec_csr_wrdata_r[6] & _T_438; // @[dec_tlu_ctl.scala 1798:70] + wire _T_443 = ~io_dec_csr_wrdata_r[5]; // @[dec_tlu_ctl.scala 1799:73] + wire _T_444 = io_dec_csr_wrdata_r[4] & _T_443; // @[dec_tlu_ctl.scala 1799:70] + wire _T_448 = ~io_dec_csr_wrdata_r[3]; // @[dec_tlu_ctl.scala 1800:73] + wire _T_449 = io_dec_csr_wrdata_r[2] & _T_448; // @[dec_tlu_ctl.scala 1800:70] + wire _T_454 = io_dec_csr_wrdata_r[0] & _T_510; // @[dec_tlu_ctl.scala 1801:70] + wire [7:0] _T_461 = {io_dec_csr_wrdata_r[7],_T_439,io_dec_csr_wrdata_r[5],_T_444,io_dec_csr_wrdata_r[3],_T_449,io_dec_csr_wrdata_r[1],_T_454}; // @[Cat.scala 29:58] + wire [15:0] _T_469 = {io_dec_csr_wrdata_r[15],_T_419,io_dec_csr_wrdata_r[13],_T_424,io_dec_csr_wrdata_r[11],_T_429,io_dec_csr_wrdata_r[9],_T_434,_T_461}; // @[Cat.scala 29:58] + wire [7:0] _T_476 = {io_dec_csr_wrdata_r[23],_T_399,io_dec_csr_wrdata_r[21],_T_404,io_dec_csr_wrdata_r[19],_T_409,io_dec_csr_wrdata_r[17],_T_414}; // @[Cat.scala 29:58] + wire [15:0] _T_484 = {io_dec_csr_wrdata_r[31],_T_379,io_dec_csr_wrdata_r[29],_T_384,io_dec_csr_wrdata_r[27],_T_389,io_dec_csr_wrdata_r[25],_T_394,_T_476}; // @[Cat.scala 29:58] reg [31:0] mrac; // @[lib.scala 374:16] - wire _T_477 = io_dec_csr_wraddr_r == 12'hbc0; // @[dec_tlu_ctl.scala 1814:69] - wire wr_mdeau_r = io_dec_csr_wen_r_mod & _T_477; // @[dec_tlu_ctl.scala 1814:40] - wire _T_478 = ~wr_mdeau_r; // @[dec_tlu_ctl.scala 1824:59] - wire _T_479 = io_mdseac_locked_f & _T_478; // @[dec_tlu_ctl.scala 1824:57] - wire _T_481 = io_lsu_imprecise_error_store_any | io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 1826:49] - wire _T_482 = ~io_nmi_int_detected_f; // @[dec_tlu_ctl.scala 1826:86] - wire _T_483 = _T_481 & _T_482; // @[dec_tlu_ctl.scala 1826:84] - wire _T_484 = ~io_mdseac_locked_f; // @[dec_tlu_ctl.scala 1826:111] - wire mdseac_en = _T_483 & _T_484; // @[dec_tlu_ctl.scala 1826:109] + wire _T_487 = io_dec_csr_wraddr_r == 12'hbc0; // @[dec_tlu_ctl.scala 1814:69] + wire wr_mdeau_r = io_dec_csr_wen_r_mod & _T_487; // @[dec_tlu_ctl.scala 1814:40] + wire _T_488 = ~wr_mdeau_r; // @[dec_tlu_ctl.scala 1824:59] + wire _T_489 = io_mdseac_locked_f & _T_488; // @[dec_tlu_ctl.scala 1824:57] + wire _T_491 = io_lsu_imprecise_error_store_any | io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 1826:49] + wire _T_492 = ~io_nmi_int_detected_f; // @[dec_tlu_ctl.scala 1826:86] + wire _T_493 = _T_491 & _T_492; // @[dec_tlu_ctl.scala 1826:84] + wire _T_494 = ~io_mdseac_locked_f; // @[dec_tlu_ctl.scala 1826:111] + wire mdseac_en = _T_493 & _T_494; // @[dec_tlu_ctl.scala 1826:109] reg [31:0] mdseac; // @[lib.scala 374:16] - wire _T_490 = wr_mpmc_r & io_dec_csr_wrdata_r[0]; // @[dec_tlu_ctl.scala 1841:30] - wire _T_491 = ~io_internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 1841:57] - wire _T_492 = _T_490 & _T_491; // @[dec_tlu_ctl.scala 1841:55] - wire _T_493 = ~io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 1841:89] - wire _T_506 = io_dec_csr_wrdata_r[31:27] > 5'h1a; // @[dec_tlu_ctl.scala 1859:48] - wire [4:0] csr_sat = _T_506 ? 5'h1a : io_dec_csr_wrdata_r[31:27]; // @[dec_tlu_ctl.scala 1859:19] - wire _T_509 = io_dec_csr_wraddr_r == 12'h7f0; // @[dec_tlu_ctl.scala 1861:70] - wire wr_micect_r = io_dec_csr_wen_r_mod & _T_509; // @[dec_tlu_ctl.scala 1861:41] - wire [26:0] _T_510 = {26'h0,io_ic_perr_r_d1}; // @[Cat.scala 29:58] - wire [31:0] _GEN_14 = {{5'd0}, _T_510}; // @[dec_tlu_ctl.scala 1862:23] - wire [31:0] _T_512 = micect + _GEN_14; // @[dec_tlu_ctl.scala 1862:23] - wire [31:0] _T_515 = {csr_sat,io_dec_csr_wrdata_r[26:0]}; // @[Cat.scala 29:58] - wire [26:0] micect_inc = _T_512[26:0]; // @[dec_tlu_ctl.scala 1862:13] - wire [31:0] _T_517 = {micect[31:27],micect_inc}; // @[Cat.scala 29:58] - wire _T_528 = io_dec_csr_wraddr_r == 12'h7f1; // @[dec_tlu_ctl.scala 1876:76] - wire wr_miccmect_r = io_dec_csr_wen_r_mod & _T_528; // @[dec_tlu_ctl.scala 1876:47] - wire _T_530 = io_iccm_sbecc_r_d1 | io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 1877:70] - wire [26:0] _T_531 = {26'h0,_T_530}; // @[Cat.scala 29:58] - wire [26:0] miccmect_inc = miccmect[26:0] + _T_531; // @[dec_tlu_ctl.scala 1877:33] - wire [31:0] _T_538 = {miccmect[31:27],miccmect_inc}; // @[Cat.scala 29:58] - wire _T_539 = wr_miccmect_r | io_iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 1880:48] - wire _T_550 = io_dec_csr_wraddr_r == 12'h7f2; // @[dec_tlu_ctl.scala 1891:76] - wire wr_mdccmect_r = io_dec_csr_wen_r_mod & _T_550; // @[dec_tlu_ctl.scala 1891:47] - wire [26:0] _T_552 = {26'h0,io_lsu_single_ecc_error_r_d1}; // @[Cat.scala 29:58] - wire [26:0] mdccmect_inc = mdccmect[26:0] + _T_552; // @[dec_tlu_ctl.scala 1892:33] - wire [31:0] _T_559 = {mdccmect[31:27],mdccmect_inc}; // @[Cat.scala 29:58] - wire _T_570 = io_dec_csr_wraddr_r == 12'h7ce; // @[dec_tlu_ctl.scala 1907:69] - wire wr_mfdht_r = io_dec_csr_wen_r_mod & _T_570; // @[dec_tlu_ctl.scala 1907:40] + wire _T_500 = wr_mpmc_r & io_dec_csr_wrdata_r[0]; // @[dec_tlu_ctl.scala 1841:30] + wire _T_501 = ~io_internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 1841:57] + wire _T_502 = _T_500 & _T_501; // @[dec_tlu_ctl.scala 1841:55] + wire _T_503 = ~io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 1841:89] + wire _T_516 = io_dec_csr_wrdata_r[31:27] > 5'h1a; // @[dec_tlu_ctl.scala 1859:48] + wire [4:0] csr_sat = _T_516 ? 5'h1a : io_dec_csr_wrdata_r[31:27]; // @[dec_tlu_ctl.scala 1859:19] + wire _T_519 = io_dec_csr_wraddr_r == 12'h7f0; // @[dec_tlu_ctl.scala 1861:70] + wire wr_micect_r = io_dec_csr_wen_r_mod & _T_519; // @[dec_tlu_ctl.scala 1861:41] + wire [26:0] _T_520 = {26'h0,io_ic_perr_r_d1}; // @[Cat.scala 29:58] + wire [31:0] _GEN_14 = {{5'd0}, _T_520}; // @[dec_tlu_ctl.scala 1862:23] + wire [31:0] _T_522 = micect + _GEN_14; // @[dec_tlu_ctl.scala 1862:23] + wire [31:0] _T_525 = {csr_sat,io_dec_csr_wrdata_r[26:0]}; // @[Cat.scala 29:58] + wire [26:0] micect_inc = _T_522[26:0]; // @[dec_tlu_ctl.scala 1862:13] + wire [31:0] _T_527 = {micect[31:27],micect_inc}; // @[Cat.scala 29:58] + wire _T_538 = io_dec_csr_wraddr_r == 12'h7f1; // @[dec_tlu_ctl.scala 1876:76] + wire wr_miccmect_r = io_dec_csr_wen_r_mod & _T_538; // @[dec_tlu_ctl.scala 1876:47] + wire _T_540 = io_iccm_sbecc_r_d1 | io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 1877:70] + wire [26:0] _T_541 = {26'h0,_T_540}; // @[Cat.scala 29:58] + wire [26:0] miccmect_inc = miccmect[26:0] + _T_541; // @[dec_tlu_ctl.scala 1877:33] + wire [31:0] _T_548 = {miccmect[31:27],miccmect_inc}; // @[Cat.scala 29:58] + wire _T_549 = wr_miccmect_r | io_iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 1880:48] + wire _T_560 = io_dec_csr_wraddr_r == 12'h7f2; // @[dec_tlu_ctl.scala 1891:76] + wire wr_mdccmect_r = io_dec_csr_wen_r_mod & _T_560; // @[dec_tlu_ctl.scala 1891:47] + wire [26:0] _T_562 = {26'h0,io_lsu_single_ecc_error_r_d1}; // @[Cat.scala 29:58] + wire [26:0] mdccmect_inc = mdccmect[26:0] + _T_562; // @[dec_tlu_ctl.scala 1892:33] + wire [31:0] _T_569 = {mdccmect[31:27],mdccmect_inc}; // @[Cat.scala 29:58] + wire _T_580 = io_dec_csr_wraddr_r == 12'h7ce; // @[dec_tlu_ctl.scala 1907:69] + wire wr_mfdht_r = io_dec_csr_wen_r_mod & _T_580; // @[dec_tlu_ctl.scala 1907:40] reg [5:0] mfdht; // @[dec_tlu_ctl.scala 1911:43] - wire _T_575 = io_dec_csr_wraddr_r == 12'h7cf; // @[dec_tlu_ctl.scala 1920:69] - wire wr_mfdhs_r = io_dec_csr_wen_r_mod & _T_575; // @[dec_tlu_ctl.scala 1920:40] - wire _T_578 = ~io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1923:43] - wire _T_579 = io_dbg_tlu_halted & _T_578; // @[dec_tlu_ctl.scala 1923:41] - wire _T_581 = ~io_lsu_idle_any_f; // @[dec_tlu_ctl.scala 1923:78] - wire _T_582 = ~io_ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 1923:98] - wire [1:0] _T_583 = {_T_581,_T_582}; // @[Cat.scala 29:58] + wire _T_585 = io_dec_csr_wraddr_r == 12'h7cf; // @[dec_tlu_ctl.scala 1920:69] + wire wr_mfdhs_r = io_dec_csr_wen_r_mod & _T_585; // @[dec_tlu_ctl.scala 1920:40] + wire _T_588 = ~io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1923:43] + wire _T_589 = io_dbg_tlu_halted & _T_588; // @[dec_tlu_ctl.scala 1923:41] + wire _T_591 = ~io_lsu_idle_any_f; // @[dec_tlu_ctl.scala 1923:78] + wire _T_592 = ~io_ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 1923:98] + wire [1:0] _T_593 = {_T_591,_T_592}; // @[Cat.scala 29:58] reg [1:0] mfdhs; // @[Reg.scala 27:20] - wire _T_585 = wr_mfdhs_r | io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 1925:71] + wire _T_595 = wr_mfdhs_r | io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 1925:71] reg [31:0] force_halt_ctr_f; // @[Reg.scala 27:20] - wire [31:0] _T_590 = force_halt_ctr_f + 32'h1; // @[dec_tlu_ctl.scala 1927:74] - wire [62:0] _T_597 = 63'hffffffff << mfdht[5:1]; // @[dec_tlu_ctl.scala 1932:71] + wire [31:0] _T_600 = force_halt_ctr_f + 32'h1; // @[dec_tlu_ctl.scala 1927:74] + wire [62:0] _T_607 = 63'hffffffff << mfdht[5:1]; // @[dec_tlu_ctl.scala 1932:71] wire [62:0] _GEN_15 = {{31'd0}, force_halt_ctr_f}; // @[dec_tlu_ctl.scala 1932:48] - wire [62:0] _T_598 = _GEN_15 & _T_597; // @[dec_tlu_ctl.scala 1932:48] - wire _T_599 = |_T_598; // @[dec_tlu_ctl.scala 1932:87] - wire _T_602 = io_dec_csr_wraddr_r == 12'hbc8; // @[dec_tlu_ctl.scala 1940:69] + wire [62:0] _T_608 = _GEN_15 & _T_607; // @[dec_tlu_ctl.scala 1932:48] + wire _T_609 = |_T_608; // @[dec_tlu_ctl.scala 1932:87] + wire _T_612 = io_dec_csr_wraddr_r == 12'hbc8; // @[dec_tlu_ctl.scala 1940:69] reg [21:0] meivt; // @[lib.scala 374:16] - wire _T_621 = io_dec_csr_wraddr_r == 12'hbca; // @[dec_tlu_ctl.scala 1991:69] - wire _T_622 = io_dec_csr_wen_r_mod & _T_621; // @[dec_tlu_ctl.scala 1991:40] - wire wr_meicpct_r = _T_622 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1991:83] + wire _T_631 = io_dec_csr_wraddr_r == 12'hbca; // @[dec_tlu_ctl.scala 1991:69] + wire _T_632 = io_dec_csr_wen_r_mod & _T_631; // @[dec_tlu_ctl.scala 1991:40] + wire wr_meicpct_r = _T_632 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1991:83] reg [7:0] meihap; // @[lib.scala 374:16] - wire _T_608 = io_dec_csr_wraddr_r == 12'hbcc; // @[dec_tlu_ctl.scala 1964:72] - wire wr_meicurpl_r = io_dec_csr_wen_r_mod & _T_608; // @[dec_tlu_ctl.scala 1964:43] + wire _T_618 = io_dec_csr_wraddr_r == 12'hbcc; // @[dec_tlu_ctl.scala 1964:72] + wire wr_meicurpl_r = io_dec_csr_wen_r_mod & _T_618; // @[dec_tlu_ctl.scala 1964:43] reg [3:0] meicurpl; // @[dec_tlu_ctl.scala 1967:46] - wire _T_613 = io_dec_csr_wraddr_r == 12'hbcb; // @[dec_tlu_ctl.scala 1979:73] - wire _T_614 = io_dec_csr_wen_r_mod & _T_613; // @[dec_tlu_ctl.scala 1979:44] - wire wr_meicidpl_r = _T_614 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1979:88] + wire _T_623 = io_dec_csr_wraddr_r == 12'hbcb; // @[dec_tlu_ctl.scala 1979:73] + wire _T_624 = io_dec_csr_wen_r_mod & _T_623; // @[dec_tlu_ctl.scala 1979:44] + wire wr_meicidpl_r = _T_624 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1979:88] reg [3:0] meicidpl; // @[dec_tlu_ctl.scala 1984:44] - wire _T_625 = io_dec_csr_wraddr_r == 12'hbc9; // @[dec_tlu_ctl.scala 2000:69] - wire wr_meipt_r = io_dec_csr_wen_r_mod & _T_625; // @[dec_tlu_ctl.scala 2000:40] + wire _T_635 = io_dec_csr_wraddr_r == 12'hbc9; // @[dec_tlu_ctl.scala 2000:69] + wire wr_meipt_r = io_dec_csr_wen_r_mod & _T_635; // @[dec_tlu_ctl.scala 2000:40] reg [3:0] meipt; // @[dec_tlu_ctl.scala 2003:43] - wire _T_629 = io_trigger_hit_r_d1 & io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 2031:89] - wire trigger_hit_for_dscr_cause_r_d1 = io_trigger_hit_dmode_r_d1 | _T_629; // @[dec_tlu_ctl.scala 2031:66] - wire _T_630 = ~io_ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 2034:31] - wire _T_631 = io_dcsr_single_step_done_f & _T_630; // @[dec_tlu_ctl.scala 2034:29] - wire _T_632 = ~trigger_hit_for_dscr_cause_r_d1; // @[dec_tlu_ctl.scala 2034:63] - wire _T_633 = _T_631 & _T_632; // @[dec_tlu_ctl.scala 2034:61] - wire _T_634 = ~io_debug_halt_req; // @[dec_tlu_ctl.scala 2034:98] - wire _T_635 = _T_633 & _T_634; // @[dec_tlu_ctl.scala 2034:96] - wire _T_638 = io_debug_halt_req & _T_630; // @[dec_tlu_ctl.scala 2035:46] - wire _T_640 = _T_638 & _T_632; // @[dec_tlu_ctl.scala 2035:78] - wire _T_643 = io_ebreak_to_debug_mode_r_d1 & _T_632; // @[dec_tlu_ctl.scala 2036:75] - wire [2:0] _T_646 = _T_635 ? 3'h4 : 3'h0; // @[Mux.scala 27:72] - wire [2:0] _T_647 = _T_640 ? 3'h3 : 3'h0; // @[Mux.scala 27:72] - wire [2:0] _T_648 = _T_643 ? 3'h1 : 3'h0; // @[Mux.scala 27:72] - wire [2:0] _T_649 = trigger_hit_for_dscr_cause_r_d1 ? 3'h2 : 3'h0; // @[Mux.scala 27:72] - wire [2:0] _T_650 = _T_646 | _T_647; // @[Mux.scala 27:72] - wire [2:0] _T_651 = _T_650 | _T_648; // @[Mux.scala 27:72] - wire [2:0] dcsr_cause = _T_651 | _T_649; // @[Mux.scala 27:72] - wire _T_653 = io_allow_dbg_halt_csr_write & io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 2039:46] - wire _T_655 = io_dec_csr_wraddr_r == 12'h7b0; // @[dec_tlu_ctl.scala 2039:98] - wire wr_dcsr_r = _T_653 & _T_655; // @[dec_tlu_ctl.scala 2039:69] - wire _T_657 = io_dcsr[8:6] == 3'h3; // @[dec_tlu_ctl.scala 2045:75] - wire dcsr_cause_upgradeable = io_internal_dbg_halt_mode_f & _T_657; // @[dec_tlu_ctl.scala 2045:59] - wire _T_658 = ~io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 2046:59] - wire _T_659 = _T_658 | dcsr_cause_upgradeable; // @[dec_tlu_ctl.scala 2046:78] - wire enter_debug_halt_req_le = io_enter_debug_halt_req & _T_659; // @[dec_tlu_ctl.scala 2046:56] + wire _T_639 = io_trigger_hit_r_d1 & io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 2031:89] + wire trigger_hit_for_dscr_cause_r_d1 = io_trigger_hit_dmode_r_d1 | _T_639; // @[dec_tlu_ctl.scala 2031:66] + wire _T_640 = ~io_ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 2034:31] + wire _T_641 = io_dcsr_single_step_done_f & _T_640; // @[dec_tlu_ctl.scala 2034:29] + wire _T_642 = ~trigger_hit_for_dscr_cause_r_d1; // @[dec_tlu_ctl.scala 2034:63] + wire _T_643 = _T_641 & _T_642; // @[dec_tlu_ctl.scala 2034:61] + wire _T_644 = ~io_debug_halt_req; // @[dec_tlu_ctl.scala 2034:98] + wire _T_645 = _T_643 & _T_644; // @[dec_tlu_ctl.scala 2034:96] + wire _T_648 = io_debug_halt_req & _T_640; // @[dec_tlu_ctl.scala 2035:46] + wire _T_650 = _T_648 & _T_642; // @[dec_tlu_ctl.scala 2035:78] + wire _T_653 = io_ebreak_to_debug_mode_r_d1 & _T_642; // @[dec_tlu_ctl.scala 2036:75] + wire [2:0] _T_656 = _T_645 ? 3'h4 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_657 = _T_650 ? 3'h3 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_658 = _T_653 ? 3'h1 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_659 = trigger_hit_for_dscr_cause_r_d1 ? 3'h2 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_660 = _T_656 | _T_657; // @[Mux.scala 27:72] + wire [2:0] _T_661 = _T_660 | _T_658; // @[Mux.scala 27:72] + wire [2:0] dcsr_cause = _T_661 | _T_659; // @[Mux.scala 27:72] + wire _T_663 = io_allow_dbg_halt_csr_write & io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 2039:46] + wire _T_665 = io_dec_csr_wraddr_r == 12'h7b0; // @[dec_tlu_ctl.scala 2039:98] + wire wr_dcsr_r = _T_663 & _T_665; // @[dec_tlu_ctl.scala 2039:69] + wire _T_667 = io_dcsr[8:6] == 3'h3; // @[dec_tlu_ctl.scala 2045:75] + wire dcsr_cause_upgradeable = io_internal_dbg_halt_mode_f & _T_667; // @[dec_tlu_ctl.scala 2045:59] + wire _T_668 = ~io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 2046:59] + wire _T_669 = _T_668 | dcsr_cause_upgradeable; // @[dec_tlu_ctl.scala 2046:78] + wire enter_debug_halt_req_le = io_enter_debug_halt_req & _T_669; // @[dec_tlu_ctl.scala 2046:56] wire nmi_in_debug_mode = io_nmi_int_detected_f & io_internal_dbg_halt_mode_f; // @[dec_tlu_ctl.scala 2048:48] - wire [15:0] _T_665 = {io_dcsr[15:9],dcsr_cause,io_dcsr[5:2],2'h3}; // @[Cat.scala 29:58] - wire _T_671 = nmi_in_debug_mode | io_dcsr[3]; // @[dec_tlu_ctl.scala 2050:145] - wire [15:0] _T_680 = {io_dec_csr_wrdata_r[15],3'h0,io_dec_csr_wrdata_r[11:10],1'h0,io_dcsr[8:6],2'h0,_T_671,io_dec_csr_wrdata_r[2],2'h3}; // @[Cat.scala 29:58] - wire [15:0] _T_685 = {io_dcsr[15:4],nmi_in_debug_mode,io_dcsr[2],2'h3}; // @[Cat.scala 29:58] - wire _T_687 = enter_debug_halt_req_le | wr_dcsr_r; // @[dec_tlu_ctl.scala 2052:54] - wire _T_688 = _T_687 | io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 2052:66] - reg [15:0] _T_691; // @[lib.scala 374:16] - wire _T_694 = io_dec_csr_wraddr_r == 12'h7b1; // @[dec_tlu_ctl.scala 2060:97] - wire wr_dpc_r = _T_653 & _T_694; // @[dec_tlu_ctl.scala 2060:68] - wire _T_697 = ~io_request_debug_mode_done; // @[dec_tlu_ctl.scala 2061:67] - wire dpc_capture_npc = _T_579 & _T_697; // @[dec_tlu_ctl.scala 2061:65] - wire _T_698 = ~io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2065:21] - wire _T_699 = ~dpc_capture_npc; // @[dec_tlu_ctl.scala 2065:39] - wire _T_700 = _T_698 & _T_699; // @[dec_tlu_ctl.scala 2065:37] - wire _T_701 = _T_700 & wr_dpc_r; // @[dec_tlu_ctl.scala 2065:56] - wire _T_706 = _T_698 & dpc_capture_npc; // @[dec_tlu_ctl.scala 2067:49] - wire [30:0] _T_708 = _T_701 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72] - wire [30:0] _T_709 = io_request_debug_mode_r ? pc_r : 31'h0; // @[Mux.scala 27:72] - wire [30:0] _T_710 = _T_706 ? io_npc_r : 31'h0; // @[Mux.scala 27:72] - wire [30:0] _T_711 = _T_708 | _T_709; // @[Mux.scala 27:72] - wire _T_713 = wr_dpc_r | io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2069:36] - reg [30:0] _T_716; // @[lib.scala 374:16] - wire [2:0] _T_720 = {io_dec_csr_wrdata_r[24],io_dec_csr_wrdata_r[21:20]}; // @[Cat.scala 29:58] - wire _T_723 = io_dec_csr_wraddr_r == 12'h7c8; // @[dec_tlu_ctl.scala 2084:102] + wire [15:0] _T_675 = {io_dcsr[15:9],dcsr_cause,io_dcsr[5:2],2'h3}; // @[Cat.scala 29:58] + wire _T_681 = nmi_in_debug_mode | io_dcsr[3]; // @[dec_tlu_ctl.scala 2050:145] + wire [15:0] _T_690 = {io_dec_csr_wrdata_r[15],3'h0,io_dec_csr_wrdata_r[11:10],1'h0,io_dcsr[8:6],2'h0,_T_681,io_dec_csr_wrdata_r[2],2'h3}; // @[Cat.scala 29:58] + wire [15:0] _T_695 = {io_dcsr[15:4],nmi_in_debug_mode,io_dcsr[2],2'h3}; // @[Cat.scala 29:58] + wire _T_697 = enter_debug_halt_req_le | wr_dcsr_r; // @[dec_tlu_ctl.scala 2052:54] + wire _T_698 = _T_697 | io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 2052:66] + reg [15:0] _T_701; // @[lib.scala 374:16] + wire _T_704 = io_dec_csr_wraddr_r == 12'h7b1; // @[dec_tlu_ctl.scala 2060:97] + wire wr_dpc_r = _T_663 & _T_704; // @[dec_tlu_ctl.scala 2060:68] + wire _T_707 = ~io_request_debug_mode_done; // @[dec_tlu_ctl.scala 2061:67] + wire dpc_capture_npc = _T_589 & _T_707; // @[dec_tlu_ctl.scala 2061:65] + wire _T_708 = ~io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2065:21] + wire _T_709 = ~dpc_capture_npc; // @[dec_tlu_ctl.scala 2065:39] + wire _T_710 = _T_708 & _T_709; // @[dec_tlu_ctl.scala 2065:37] + wire _T_711 = _T_710 & wr_dpc_r; // @[dec_tlu_ctl.scala 2065:56] + wire _T_716 = _T_708 & dpc_capture_npc; // @[dec_tlu_ctl.scala 2067:49] + wire [30:0] _T_718 = _T_711 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_719 = io_request_debug_mode_r ? pc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_720 = _T_716 ? io_npc_r : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_721 = _T_718 | _T_719; // @[Mux.scala 27:72] + wire _T_723 = wr_dpc_r | io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2069:36] + reg [30:0] _T_726; // @[lib.scala 374:16] + wire [2:0] _T_730 = {io_dec_csr_wrdata_r[24],io_dec_csr_wrdata_r[21:20]}; // @[Cat.scala 29:58] + wire _T_733 = io_dec_csr_wraddr_r == 12'h7c8; // @[dec_tlu_ctl.scala 2084:102] reg [16:0] dicawics; // @[lib.scala 374:16] - wire _T_727 = io_dec_csr_wraddr_r == 12'h7c9; // @[dec_tlu_ctl.scala 2102:100] - wire wr_dicad0_r = _T_653 & _T_727; // @[dec_tlu_ctl.scala 2102:71] + wire _T_737 = io_dec_csr_wraddr_r == 12'h7c9; // @[dec_tlu_ctl.scala 2102:100] + wire wr_dicad0_r = _T_663 & _T_737; // @[dec_tlu_ctl.scala 2102:71] reg [70:0] dicad0; // @[lib.scala 374:16] - wire _T_733 = io_dec_csr_wraddr_r == 12'h7cc; // @[dec_tlu_ctl.scala 2115:101] - wire wr_dicad0h_r = _T_653 & _T_733; // @[dec_tlu_ctl.scala 2115:72] + wire _T_743 = io_dec_csr_wraddr_r == 12'h7cc; // @[dec_tlu_ctl.scala 2115:101] + wire wr_dicad0h_r = _T_663 & _T_743; // @[dec_tlu_ctl.scala 2115:72] reg [31:0] dicad0h; // @[lib.scala 374:16] - wire _T_741 = io_dec_csr_wraddr_r == 12'h7ca; // @[dec_tlu_ctl.scala 2142:100] - wire _T_742 = _T_653 & _T_741; // @[dec_tlu_ctl.scala 2142:71] - wire _T_747 = _T_742 | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2146:77] - reg [3:0] _T_749; // @[Reg.scala 27:20] - wire [31:0] dicad1 = {28'h0,_T_749}; // @[Cat.scala 29:58] - wire [69:0] _T_756 = {2'h0,dicad1[3:0],dicad0h,dicad0[31:0]}; // @[Cat.scala 29:58] - wire _T_757 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 2159:52] - wire _T_758 = _T_757 & io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 2159:75] - wire _T_759 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 2159:98] - wire _T_760 = _T_758 & _T_759; // @[dec_tlu_ctl.scala 2159:96] - wire _T_762 = io_dec_csr_rdaddr_d == 12'h7cb; // @[dec_tlu_ctl.scala 2159:149] - wire _T_765 = io_dec_csr_wraddr_r == 12'h7cb; // @[dec_tlu_ctl.scala 2160:104] + wire _T_751 = io_dec_csr_wraddr_r == 12'h7ca; // @[dec_tlu_ctl.scala 2127:100] + wire _T_752 = _T_663 & _T_751; // @[dec_tlu_ctl.scala 2127:71] + wire _T_756 = _T_752 | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2131:78] + reg [31:0] _T_758; // @[Reg.scala 27:20] + wire [31:0] dicad1 = {25'h0,_T_758[6:0]}; // @[Cat.scala 29:58] + wire [38:0] _T_763 = {dicad1[6:0],dicad0h}; // @[Cat.scala 29:58] + wire _T_765 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 2159:52] + wire _T_766 = _T_765 & io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 2159:75] + wire _T_767 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 2159:98] + wire _T_768 = _T_766 & _T_767; // @[dec_tlu_ctl.scala 2159:96] + wire _T_770 = io_dec_csr_rdaddr_d == 12'h7cb; // @[dec_tlu_ctl.scala 2159:149] + wire _T_773 = io_dec_csr_wraddr_r == 12'h7cb; // @[dec_tlu_ctl.scala 2160:104] reg icache_rd_valid_f; // @[dec_tlu_ctl.scala 2162:58] reg icache_wr_valid_f; // @[dec_tlu_ctl.scala 2163:58] - wire _T_767 = io_dec_csr_wraddr_r == 12'h7a0; // @[dec_tlu_ctl.scala 2174:69] - wire wr_mtsel_r = io_dec_csr_wen_r_mod & _T_767; // @[dec_tlu_ctl.scala 2174:40] + wire _T_775 = io_dec_csr_wraddr_r == 12'h7a0; // @[dec_tlu_ctl.scala 2174:69] + wire wr_mtsel_r = io_dec_csr_wen_r_mod & _T_775; // @[dec_tlu_ctl.scala 2174:40] reg [1:0] mtsel; // @[dec_tlu_ctl.scala 2177:43] - wire tdata_load = io_dec_csr_wrdata_r[0] & _T_398; // @[dec_tlu_ctl.scala 2212:42] - wire tdata_opcode = io_dec_csr_wrdata_r[2] & _T_398; // @[dec_tlu_ctl.scala 2214:44] - wire _T_778 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2216:46] - wire tdata_action = _T_778 & io_dec_csr_wrdata_r[12]; // @[dec_tlu_ctl.scala 2216:69] - wire [9:0] tdata_wrdata_r = {_T_778,io_dec_csr_wrdata_r[20:19],tdata_action,io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7:6],tdata_opcode,io_dec_csr_wrdata_r[1],tdata_load}; // @[Cat.scala 29:58] - wire _T_793 = io_dec_csr_wraddr_r == 12'h7a1; // @[dec_tlu_ctl.scala 2222:99] - wire _T_794 = io_dec_csr_wen_r_mod & _T_793; // @[dec_tlu_ctl.scala 2222:70] - wire _T_795 = mtsel == 2'h0; // @[dec_tlu_ctl.scala 2222:121] - wire _T_796 = _T_794 & _T_795; // @[dec_tlu_ctl.scala 2222:112] - wire _T_798 = ~io_mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 2222:138] - wire _T_799 = _T_798 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] - wire wr_mtdata1_t_r_0 = _T_796 & _T_799; // @[dec_tlu_ctl.scala 2222:135] - wire _T_804 = mtsel == 2'h1; // @[dec_tlu_ctl.scala 2222:121] - wire _T_805 = _T_794 & _T_804; // @[dec_tlu_ctl.scala 2222:112] - wire _T_807 = ~io_mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 2222:138] - wire _T_808 = _T_807 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] - wire wr_mtdata1_t_r_1 = _T_805 & _T_808; // @[dec_tlu_ctl.scala 2222:135] - wire _T_813 = mtsel == 2'h2; // @[dec_tlu_ctl.scala 2222:121] - wire _T_814 = _T_794 & _T_813; // @[dec_tlu_ctl.scala 2222:112] - wire _T_816 = ~io_mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 2222:138] - wire _T_817 = _T_816 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] - wire wr_mtdata1_t_r_2 = _T_814 & _T_817; // @[dec_tlu_ctl.scala 2222:135] - wire _T_822 = mtsel == 2'h3; // @[dec_tlu_ctl.scala 2222:121] - wire _T_823 = _T_794 & _T_822; // @[dec_tlu_ctl.scala 2222:112] - wire _T_825 = ~io_mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 2222:138] - wire _T_826 = _T_825 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] - wire wr_mtdata1_t_r_3 = _T_823 & _T_826; // @[dec_tlu_ctl.scala 2222:135] - wire _T_832 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[dec_tlu_ctl.scala 2223:139] - wire [9:0] _T_835 = {io_mtdata1_t_0[9],_T_832,io_mtdata1_t_0[7:0]}; // @[Cat.scala 29:58] - wire _T_841 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[dec_tlu_ctl.scala 2223:139] - wire [9:0] _T_844 = {io_mtdata1_t_1[9],_T_841,io_mtdata1_t_1[7:0]}; // @[Cat.scala 29:58] - wire _T_850 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[dec_tlu_ctl.scala 2223:139] - wire [9:0] _T_853 = {io_mtdata1_t_2[9],_T_850,io_mtdata1_t_2[7:0]}; // @[Cat.scala 29:58] - wire _T_859 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[dec_tlu_ctl.scala 2223:139] - wire [9:0] _T_862 = {io_mtdata1_t_3[9],_T_859,io_mtdata1_t_3[7:0]}; // @[Cat.scala 29:58] - reg [9:0] _T_864; // @[dec_tlu_ctl.scala 2225:74] - reg [9:0] _T_865; // @[dec_tlu_ctl.scala 2225:74] - reg [9:0] _T_866; // @[dec_tlu_ctl.scala 2225:74] - reg [9:0] _T_867; // @[dec_tlu_ctl.scala 2225:74] - wire [31:0] _T_882 = {4'h2,io_mtdata1_t_0[9],6'h1f,io_mtdata1_t_0[8:7],6'h0,io_mtdata1_t_0[6:5],3'h0,io_mtdata1_t_0[4:3],3'h0,io_mtdata1_t_0[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_897 = {4'h2,io_mtdata1_t_1[9],6'h1f,io_mtdata1_t_1[8:7],6'h0,io_mtdata1_t_1[6:5],3'h0,io_mtdata1_t_1[4:3],3'h0,io_mtdata1_t_1[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_912 = {4'h2,io_mtdata1_t_2[9],6'h1f,io_mtdata1_t_2[8:7],6'h0,io_mtdata1_t_2[6:5],3'h0,io_mtdata1_t_2[4:3],3'h0,io_mtdata1_t_2[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_927 = {4'h2,io_mtdata1_t_3[9],6'h1f,io_mtdata1_t_3[8:7],6'h0,io_mtdata1_t_3[6:5],3'h0,io_mtdata1_t_3[4:3],3'h0,io_mtdata1_t_3[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_928 = _T_795 ? _T_882 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_929 = _T_804 ? _T_897 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_930 = _T_813 ? _T_912 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_931 = _T_822 ? _T_927 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_932 = _T_928 | _T_929; // @[Mux.scala 27:72] - wire [31:0] _T_933 = _T_932 | _T_930; // @[Mux.scala 27:72] - wire [31:0] mtdata1_tsel_out = _T_933 | _T_931; // @[Mux.scala 27:72] - wire _T_960 = io_dec_csr_wraddr_r == 12'h7a2; // @[dec_tlu_ctl.scala 2242:98] - wire _T_961 = io_dec_csr_wen_r_mod & _T_960; // @[dec_tlu_ctl.scala 2242:69] - wire _T_963 = _T_961 & _T_795; // @[dec_tlu_ctl.scala 2242:111] - wire _T_972 = _T_961 & _T_804; // @[dec_tlu_ctl.scala 2242:111] - wire _T_981 = _T_961 & _T_813; // @[dec_tlu_ctl.scala 2242:111] - wire _T_990 = _T_961 & _T_822; // @[dec_tlu_ctl.scala 2242:111] + wire tdata_load = io_dec_csr_wrdata_r[0] & _T_408; // @[dec_tlu_ctl.scala 2212:42] + wire tdata_opcode = io_dec_csr_wrdata_r[2] & _T_408; // @[dec_tlu_ctl.scala 2214:44] + wire _T_786 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2216:46] + wire tdata_action = _T_786 & io_dec_csr_wrdata_r[12]; // @[dec_tlu_ctl.scala 2216:69] + wire [9:0] tdata_wrdata_r = {_T_786,io_dec_csr_wrdata_r[20:19],tdata_action,io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7:6],tdata_opcode,io_dec_csr_wrdata_r[1],tdata_load}; // @[Cat.scala 29:58] + wire _T_801 = io_dec_csr_wraddr_r == 12'h7a1; // @[dec_tlu_ctl.scala 2222:99] + wire _T_802 = io_dec_csr_wen_r_mod & _T_801; // @[dec_tlu_ctl.scala 2222:70] + wire _T_803 = mtsel == 2'h0; // @[dec_tlu_ctl.scala 2222:121] + wire _T_804 = _T_802 & _T_803; // @[dec_tlu_ctl.scala 2222:112] + wire _T_806 = ~io_mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 2222:138] + wire _T_807 = _T_806 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] + wire wr_mtdata1_t_r_0 = _T_804 & _T_807; // @[dec_tlu_ctl.scala 2222:135] + wire _T_812 = mtsel == 2'h1; // @[dec_tlu_ctl.scala 2222:121] + wire _T_813 = _T_802 & _T_812; // @[dec_tlu_ctl.scala 2222:112] + wire _T_815 = ~io_mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 2222:138] + wire _T_816 = _T_815 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] + wire wr_mtdata1_t_r_1 = _T_813 & _T_816; // @[dec_tlu_ctl.scala 2222:135] + wire _T_821 = mtsel == 2'h2; // @[dec_tlu_ctl.scala 2222:121] + wire _T_822 = _T_802 & _T_821; // @[dec_tlu_ctl.scala 2222:112] + wire _T_824 = ~io_mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 2222:138] + wire _T_825 = _T_824 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] + wire wr_mtdata1_t_r_2 = _T_822 & _T_825; // @[dec_tlu_ctl.scala 2222:135] + wire _T_830 = mtsel == 2'h3; // @[dec_tlu_ctl.scala 2222:121] + wire _T_831 = _T_802 & _T_830; // @[dec_tlu_ctl.scala 2222:112] + wire _T_833 = ~io_mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 2222:138] + wire _T_834 = _T_833 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] + wire wr_mtdata1_t_r_3 = _T_831 & _T_834; // @[dec_tlu_ctl.scala 2222:135] + wire _T_840 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[dec_tlu_ctl.scala 2223:139] + wire [9:0] _T_843 = {io_mtdata1_t_0[9],_T_840,io_mtdata1_t_0[7:0]}; // @[Cat.scala 29:58] + wire _T_849 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[dec_tlu_ctl.scala 2223:139] + wire [9:0] _T_852 = {io_mtdata1_t_1[9],_T_849,io_mtdata1_t_1[7:0]}; // @[Cat.scala 29:58] + wire _T_858 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[dec_tlu_ctl.scala 2223:139] + wire [9:0] _T_861 = {io_mtdata1_t_2[9],_T_858,io_mtdata1_t_2[7:0]}; // @[Cat.scala 29:58] + wire _T_867 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[dec_tlu_ctl.scala 2223:139] + wire [9:0] _T_870 = {io_mtdata1_t_3[9],_T_867,io_mtdata1_t_3[7:0]}; // @[Cat.scala 29:58] + reg [9:0] _T_872; // @[dec_tlu_ctl.scala 2225:74] + reg [9:0] _T_873; // @[dec_tlu_ctl.scala 2225:74] + reg [9:0] _T_874; // @[dec_tlu_ctl.scala 2225:74] + reg [9:0] _T_875; // @[dec_tlu_ctl.scala 2225:74] + wire [31:0] _T_890 = {4'h2,io_mtdata1_t_0[9],6'h1f,io_mtdata1_t_0[8:7],6'h0,io_mtdata1_t_0[6:5],3'h0,io_mtdata1_t_0[4:3],3'h0,io_mtdata1_t_0[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_905 = {4'h2,io_mtdata1_t_1[9],6'h1f,io_mtdata1_t_1[8:7],6'h0,io_mtdata1_t_1[6:5],3'h0,io_mtdata1_t_1[4:3],3'h0,io_mtdata1_t_1[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_920 = {4'h2,io_mtdata1_t_2[9],6'h1f,io_mtdata1_t_2[8:7],6'h0,io_mtdata1_t_2[6:5],3'h0,io_mtdata1_t_2[4:3],3'h0,io_mtdata1_t_2[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_935 = {4'h2,io_mtdata1_t_3[9],6'h1f,io_mtdata1_t_3[8:7],6'h0,io_mtdata1_t_3[6:5],3'h0,io_mtdata1_t_3[4:3],3'h0,io_mtdata1_t_3[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_936 = _T_803 ? _T_890 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_937 = _T_812 ? _T_905 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_938 = _T_821 ? _T_920 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_939 = _T_830 ? _T_935 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_940 = _T_936 | _T_937; // @[Mux.scala 27:72] + wire [31:0] _T_941 = _T_940 | _T_938; // @[Mux.scala 27:72] + wire [31:0] mtdata1_tsel_out = _T_941 | _T_939; // @[Mux.scala 27:72] + wire _T_968 = io_dec_csr_wraddr_r == 12'h7a2; // @[dec_tlu_ctl.scala 2242:98] + wire _T_969 = io_dec_csr_wen_r_mod & _T_968; // @[dec_tlu_ctl.scala 2242:69] + wire _T_971 = _T_969 & _T_803; // @[dec_tlu_ctl.scala 2242:111] + wire _T_980 = _T_969 & _T_812; // @[dec_tlu_ctl.scala 2242:111] + wire _T_989 = _T_969 & _T_821; // @[dec_tlu_ctl.scala 2242:111] + wire _T_998 = _T_969 & _T_830; // @[dec_tlu_ctl.scala 2242:111] reg [31:0] mtdata2_t_0; // @[lib.scala 374:16] reg [31:0] mtdata2_t_1; // @[lib.scala 374:16] reg [31:0] mtdata2_t_2; // @[lib.scala 374:16] reg [31:0] mtdata2_t_3; // @[lib.scala 374:16] - wire [31:0] _T_1007 = _T_795 ? mtdata2_t_0 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1008 = _T_804 ? mtdata2_t_1 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1009 = _T_813 ? mtdata2_t_2 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1010 = _T_822 ? mtdata2_t_3 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1011 = _T_1007 | _T_1008; // @[Mux.scala 27:72] - wire [31:0] _T_1012 = _T_1011 | _T_1009; // @[Mux.scala 27:72] - wire [31:0] mtdata2_tsel_out = _T_1012 | _T_1010; // @[Mux.scala 27:72] - wire [3:0] _T_1015 = io_tlu_i0_commit_cmt ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1015; // @[dec_tlu_ctl.scala 2267:59] - wire _T_1017 = ~mcountinhibit[3]; // @[dec_tlu_ctl.scala 2273:24] + wire [31:0] _T_1015 = _T_803 ? mtdata2_t_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1016 = _T_812 ? mtdata2_t_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1017 = _T_821 ? mtdata2_t_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1018 = _T_830 ? mtdata2_t_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1019 = _T_1015 | _T_1016; // @[Mux.scala 27:72] + wire [31:0] _T_1020 = _T_1019 | _T_1017; // @[Mux.scala 27:72] + wire [31:0] mtdata2_tsel_out = _T_1020 | _T_1018; // @[Mux.scala 27:72] + wire [3:0] _T_1023 = io_tlu_i0_commit_cmt ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1023; // @[dec_tlu_ctl.scala 2267:59] + wire _T_1025 = ~mcountinhibit[3]; // @[dec_tlu_ctl.scala 2273:24] reg [9:0] mhpme3; // @[Reg.scala 27:20] - wire _T_1018 = mhpme3 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1020 = mhpme3 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1022 = mhpme3 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1024 = mhpme3 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1026 = ~io_illegal_r; // @[dec_tlu_ctl.scala 2277:96] - wire _T_1027 = io_tlu_i0_commit_cmt & _T_1026; // @[dec_tlu_ctl.scala 2277:94] - wire _T_1028 = mhpme3 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1030 = ~io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2278:96] - wire _T_1031 = io_tlu_i0_commit_cmt & _T_1030; // @[dec_tlu_ctl.scala 2278:94] - wire _T_1033 = _T_1031 & _T_1026; // @[dec_tlu_ctl.scala 2278:115] - wire _T_1034 = mhpme3 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1036 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2279:94] - wire _T_1038 = _T_1036 & _T_1026; // @[dec_tlu_ctl.scala 2279:115] - wire _T_1039 = mhpme3 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1041 = mhpme3 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1043 = mhpme3 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1045 = mhpme3 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1047 = pmu_i0_itype_qual == 4'h1; // @[dec_tlu_ctl.scala 2283:91] - wire _T_1048 = mhpme3 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1050 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2284:105] - wire _T_1051 = mhpme3 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1053 = pmu_i0_itype_qual == 4'h2; // @[dec_tlu_ctl.scala 2285:91] - wire _T_1054 = mhpme3 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1056 = pmu_i0_itype_qual == 4'h3; // @[dec_tlu_ctl.scala 2286:91] - wire _T_1057 = mhpme3 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1060 = _T_1053 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2287:100] - wire _T_1061 = mhpme3 == 10'he; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1065 = _T_1056 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2288:101] - wire _T_1066 = mhpme3 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1068 = pmu_i0_itype_qual == 4'h4; // @[dec_tlu_ctl.scala 2289:89] - wire _T_1069 = mhpme3 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1071 = pmu_i0_itype_qual == 4'h5; // @[dec_tlu_ctl.scala 2290:89] - wire _T_1072 = mhpme3 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1074 = pmu_i0_itype_qual == 4'h6; // @[dec_tlu_ctl.scala 2291:89] - wire _T_1075 = mhpme3 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1077 = pmu_i0_itype_qual == 4'h7; // @[dec_tlu_ctl.scala 2292:89] - wire _T_1078 = mhpme3 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1080 = pmu_i0_itype_qual == 4'h8; // @[dec_tlu_ctl.scala 2293:89] - wire _T_1081 = mhpme3 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1083 = pmu_i0_itype_qual == 4'h9; // @[dec_tlu_ctl.scala 2294:89] - wire _T_1084 = mhpme3 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1086 = pmu_i0_itype_qual == 4'ha; // @[dec_tlu_ctl.scala 2295:89] - wire _T_1087 = mhpme3 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1089 = pmu_i0_itype_qual == 4'hb; // @[dec_tlu_ctl.scala 2296:89] - wire _T_1090 = mhpme3 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1092 = pmu_i0_itype_qual == 4'hc; // @[dec_tlu_ctl.scala 2297:89] - wire _T_1093 = mhpme3 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1095 = pmu_i0_itype_qual == 4'hd; // @[dec_tlu_ctl.scala 2298:89] - wire _T_1096 = pmu_i0_itype_qual == 4'he; // @[dec_tlu_ctl.scala 2298:122] - wire _T_1097 = _T_1095 | _T_1096; // @[dec_tlu_ctl.scala 2298:101] - wire _T_1098 = mhpme3 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1100 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2299:95] - wire _T_1101 = mhpme3 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1103 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2300:97] - wire _T_1104 = mhpme3 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1106 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2301:110] - wire _T_1107 = mhpme3 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1111 = mhpme3 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] - wire _T_1113 = mhpme3 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1115 = mhpme3 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1117 = mhpme3 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1119 = mhpme3 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1121 = mhpme3 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1123 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 2309:98] - wire _T_1124 = _T_1123 | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 2309:120] - wire _T_1125 = mhpme3 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1127 = io_take_timer_int | io_take_int_timer0_int; // @[dec_tlu_ctl.scala 2310:92] - wire _T_1128 = _T_1127 | io_take_int_timer1_int; // @[dec_tlu_ctl.scala 2310:117] - wire _T_1129 = mhpme3 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1131 = mhpme3 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1133 = mhpme3 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1135 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2313:97] - wire _T_1136 = _T_1135 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2313:129] - wire _T_1137 = mhpme3 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1139 = mhpme3 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] - wire _T_1141 = mhpme3 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] - wire _T_1143 = mhpme3 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] - wire _T_1145 = mhpme3 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] - wire _T_1147 = mhpme3 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] - wire _T_1149 = mhpme3 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] - wire _T_1151 = mhpme3 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] - wire _T_1155 = ~io_mstatus[0]; // @[dec_tlu_ctl.scala 2321:73] - wire _T_1156 = mhpme3 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] - wire [5:0] _T_1163 = io_mip & mie; // @[dec_tlu_ctl.scala 2322:113] - wire _T_1164 = |_T_1163; // @[dec_tlu_ctl.scala 2322:125] - wire _T_1165 = _T_1155 & _T_1164; // @[dec_tlu_ctl.scala 2322:98] - wire _T_1166 = mhpme3 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] - wire _T_1168 = pmu_i0_itype_qual == 4'hf; // @[dec_tlu_ctl.scala 2323:91] - wire _T_1169 = mhpme3 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] - wire _T_1171 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 2324:94] - wire _T_1172 = mhpme3 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] - wire _T_1174 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 2325:94] - wire _T_1175 = mhpme3 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] - wire _T_1177 = mhpme3 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] - wire _T_1179 = mhpme3 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] - wire _T_1181 = mhpme3 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] - wire _T_1183 = mhpme3 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] - wire _T_1186 = _T_1020 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_1187 = _T_1022 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_1188 = _T_1024 & _T_1027; // @[Mux.scala 27:72] - wire _T_1189 = _T_1028 & _T_1033; // @[Mux.scala 27:72] - wire _T_1190 = _T_1034 & _T_1038; // @[Mux.scala 27:72] - wire _T_1191 = _T_1039 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_1192 = _T_1041 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_1193 = _T_1043 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_1194 = _T_1045 & _T_1047; // @[Mux.scala 27:72] - wire _T_1195 = _T_1048 & _T_1050; // @[Mux.scala 27:72] - wire _T_1196 = _T_1051 & _T_1053; // @[Mux.scala 27:72] - wire _T_1197 = _T_1054 & _T_1056; // @[Mux.scala 27:72] - wire _T_1198 = _T_1057 & _T_1060; // @[Mux.scala 27:72] - wire _T_1199 = _T_1061 & _T_1065; // @[Mux.scala 27:72] - wire _T_1200 = _T_1066 & _T_1068; // @[Mux.scala 27:72] - wire _T_1201 = _T_1069 & _T_1071; // @[Mux.scala 27:72] - wire _T_1202 = _T_1072 & _T_1074; // @[Mux.scala 27:72] - wire _T_1203 = _T_1075 & _T_1077; // @[Mux.scala 27:72] - wire _T_1204 = _T_1078 & _T_1080; // @[Mux.scala 27:72] - wire _T_1205 = _T_1081 & _T_1083; // @[Mux.scala 27:72] - wire _T_1206 = _T_1084 & _T_1086; // @[Mux.scala 27:72] - wire _T_1207 = _T_1087 & _T_1089; // @[Mux.scala 27:72] - wire _T_1208 = _T_1090 & _T_1092; // @[Mux.scala 27:72] - wire _T_1209 = _T_1093 & _T_1097; // @[Mux.scala 27:72] - wire _T_1210 = _T_1098 & _T_1100; // @[Mux.scala 27:72] - wire _T_1211 = _T_1101 & _T_1103; // @[Mux.scala 27:72] - wire _T_1212 = _T_1104 & _T_1106; // @[Mux.scala 27:72] - wire _T_1213 = _T_1107 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_1215 = _T_1111 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_1216 = _T_1113 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_1217 = _T_1115 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_1218 = _T_1117 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_1219 = _T_1119 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_1220 = _T_1121 & _T_1124; // @[Mux.scala 27:72] - wire _T_1221 = _T_1125 & _T_1128; // @[Mux.scala 27:72] - wire _T_1222 = _T_1129 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_1223 = _T_1131 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_1224 = _T_1133 & _T_1136; // @[Mux.scala 27:72] - wire _T_1225 = _T_1137 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1226 = _T_1139 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1227 = _T_1141 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_1228 = _T_1143 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1229 = _T_1145 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1230 = _T_1147 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1231 = _T_1149 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1232 = _T_1151 & _T_1155; // @[Mux.scala 27:72] - wire _T_1233 = _T_1156 & _T_1165; // @[Mux.scala 27:72] - wire _T_1234 = _T_1166 & _T_1168; // @[Mux.scala 27:72] - wire _T_1235 = _T_1169 & _T_1171; // @[Mux.scala 27:72] - wire _T_1236 = _T_1172 & _T_1174; // @[Mux.scala 27:72] - wire _T_1237 = _T_1175 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_1238 = _T_1177 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_1239 = _T_1179 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_1240 = _T_1181 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_1241 = _T_1183 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_1242 = _T_1018 | _T_1186; // @[Mux.scala 27:72] - wire _T_1243 = _T_1242 | _T_1187; // @[Mux.scala 27:72] - wire _T_1244 = _T_1243 | _T_1188; // @[Mux.scala 27:72] - wire _T_1245 = _T_1244 | _T_1189; // @[Mux.scala 27:72] - wire _T_1246 = _T_1245 | _T_1190; // @[Mux.scala 27:72] - wire _T_1247 = _T_1246 | _T_1191; // @[Mux.scala 27:72] - wire _T_1248 = _T_1247 | _T_1192; // @[Mux.scala 27:72] - wire _T_1249 = _T_1248 | _T_1193; // @[Mux.scala 27:72] - wire _T_1250 = _T_1249 | _T_1194; // @[Mux.scala 27:72] + wire _T_1026 = mhpme3 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1028 = mhpme3 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1030 = mhpme3 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1032 = mhpme3 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1034 = ~io_illegal_r; // @[dec_tlu_ctl.scala 2277:96] + wire _T_1035 = io_tlu_i0_commit_cmt & _T_1034; // @[dec_tlu_ctl.scala 2277:94] + wire _T_1036 = mhpme3 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1038 = ~io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2278:96] + wire _T_1039 = io_tlu_i0_commit_cmt & _T_1038; // @[dec_tlu_ctl.scala 2278:94] + wire _T_1041 = _T_1039 & _T_1034; // @[dec_tlu_ctl.scala 2278:115] + wire _T_1042 = mhpme3 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1044 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2279:94] + wire _T_1046 = _T_1044 & _T_1034; // @[dec_tlu_ctl.scala 2279:115] + wire _T_1047 = mhpme3 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1049 = mhpme3 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1051 = mhpme3 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1053 = mhpme3 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1055 = pmu_i0_itype_qual == 4'h1; // @[dec_tlu_ctl.scala 2283:91] + wire _T_1056 = mhpme3 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1058 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2284:105] + wire _T_1059 = mhpme3 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1061 = pmu_i0_itype_qual == 4'h2; // @[dec_tlu_ctl.scala 2285:91] + wire _T_1062 = mhpme3 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1064 = pmu_i0_itype_qual == 4'h3; // @[dec_tlu_ctl.scala 2286:91] + wire _T_1065 = mhpme3 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1068 = _T_1061 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2287:100] + wire _T_1069 = mhpme3 == 10'he; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1073 = _T_1064 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2288:101] + wire _T_1074 = mhpme3 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1076 = pmu_i0_itype_qual == 4'h4; // @[dec_tlu_ctl.scala 2289:89] + wire _T_1077 = mhpme3 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1079 = pmu_i0_itype_qual == 4'h5; // @[dec_tlu_ctl.scala 2290:89] + wire _T_1080 = mhpme3 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1082 = pmu_i0_itype_qual == 4'h6; // @[dec_tlu_ctl.scala 2291:89] + wire _T_1083 = mhpme3 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1085 = pmu_i0_itype_qual == 4'h7; // @[dec_tlu_ctl.scala 2292:89] + wire _T_1086 = mhpme3 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1088 = pmu_i0_itype_qual == 4'h8; // @[dec_tlu_ctl.scala 2293:89] + wire _T_1089 = mhpme3 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1091 = pmu_i0_itype_qual == 4'h9; // @[dec_tlu_ctl.scala 2294:89] + wire _T_1092 = mhpme3 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1094 = pmu_i0_itype_qual == 4'ha; // @[dec_tlu_ctl.scala 2295:89] + wire _T_1095 = mhpme3 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1097 = pmu_i0_itype_qual == 4'hb; // @[dec_tlu_ctl.scala 2296:89] + wire _T_1098 = mhpme3 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1100 = pmu_i0_itype_qual == 4'hc; // @[dec_tlu_ctl.scala 2297:89] + wire _T_1101 = mhpme3 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1103 = pmu_i0_itype_qual == 4'hd; // @[dec_tlu_ctl.scala 2298:89] + wire _T_1104 = pmu_i0_itype_qual == 4'he; // @[dec_tlu_ctl.scala 2298:122] + wire _T_1105 = _T_1103 | _T_1104; // @[dec_tlu_ctl.scala 2298:101] + wire _T_1106 = mhpme3 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1108 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2299:95] + wire _T_1109 = mhpme3 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1111 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2300:97] + wire _T_1112 = mhpme3 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1114 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2301:110] + wire _T_1115 = mhpme3 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1119 = mhpme3 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] + wire _T_1121 = mhpme3 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1123 = mhpme3 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1125 = mhpme3 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1127 = mhpme3 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1129 = mhpme3 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1131 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 2309:98] + wire _T_1132 = _T_1131 | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 2309:120] + wire _T_1133 = mhpme3 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1135 = io_take_timer_int | io_take_int_timer0_int; // @[dec_tlu_ctl.scala 2310:92] + wire _T_1136 = _T_1135 | io_take_int_timer1_int; // @[dec_tlu_ctl.scala 2310:117] + wire _T_1137 = mhpme3 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1139 = mhpme3 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1141 = mhpme3 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1143 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2313:97] + wire _T_1144 = _T_1143 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2313:129] + wire _T_1145 = mhpme3 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] + wire _T_1147 = mhpme3 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] + wire _T_1149 = mhpme3 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] + wire _T_1151 = mhpme3 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] + wire _T_1153 = mhpme3 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] + wire _T_1155 = mhpme3 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] + wire _T_1157 = mhpme3 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] + wire _T_1159 = mhpme3 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] + wire _T_1163 = ~io_mstatus[0]; // @[dec_tlu_ctl.scala 2321:73] + wire _T_1164 = mhpme3 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] + wire [5:0] _T_1171 = io_mip & mie; // @[dec_tlu_ctl.scala 2322:113] + wire _T_1172 = |_T_1171; // @[dec_tlu_ctl.scala 2322:125] + wire _T_1173 = _T_1163 & _T_1172; // @[dec_tlu_ctl.scala 2322:98] + wire _T_1174 = mhpme3 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] + wire _T_1176 = pmu_i0_itype_qual == 4'hf; // @[dec_tlu_ctl.scala 2323:91] + wire _T_1177 = mhpme3 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] + wire _T_1179 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 2324:94] + wire _T_1180 = mhpme3 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] + wire _T_1182 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 2325:94] + wire _T_1183 = mhpme3 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] + wire _T_1185 = mhpme3 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] + wire _T_1187 = mhpme3 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] + wire _T_1189 = mhpme3 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] + wire _T_1191 = mhpme3 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] + wire _T_1194 = _T_1028 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1195 = _T_1030 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1196 = _T_1032 & _T_1035; // @[Mux.scala 27:72] + wire _T_1197 = _T_1036 & _T_1041; // @[Mux.scala 27:72] + wire _T_1198 = _T_1042 & _T_1046; // @[Mux.scala 27:72] + wire _T_1199 = _T_1047 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1200 = _T_1049 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1201 = _T_1051 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1202 = _T_1053 & _T_1055; // @[Mux.scala 27:72] + wire _T_1203 = _T_1056 & _T_1058; // @[Mux.scala 27:72] + wire _T_1204 = _T_1059 & _T_1061; // @[Mux.scala 27:72] + wire _T_1205 = _T_1062 & _T_1064; // @[Mux.scala 27:72] + wire _T_1206 = _T_1065 & _T_1068; // @[Mux.scala 27:72] + wire _T_1207 = _T_1069 & _T_1073; // @[Mux.scala 27:72] + wire _T_1208 = _T_1074 & _T_1076; // @[Mux.scala 27:72] + wire _T_1209 = _T_1077 & _T_1079; // @[Mux.scala 27:72] + wire _T_1210 = _T_1080 & _T_1082; // @[Mux.scala 27:72] + wire _T_1211 = _T_1083 & _T_1085; // @[Mux.scala 27:72] + wire _T_1212 = _T_1086 & _T_1088; // @[Mux.scala 27:72] + wire _T_1213 = _T_1089 & _T_1091; // @[Mux.scala 27:72] + wire _T_1214 = _T_1092 & _T_1094; // @[Mux.scala 27:72] + wire _T_1215 = _T_1095 & _T_1097; // @[Mux.scala 27:72] + wire _T_1216 = _T_1098 & _T_1100; // @[Mux.scala 27:72] + wire _T_1217 = _T_1101 & _T_1105; // @[Mux.scala 27:72] + wire _T_1218 = _T_1106 & _T_1108; // @[Mux.scala 27:72] + wire _T_1219 = _T_1109 & _T_1111; // @[Mux.scala 27:72] + wire _T_1220 = _T_1112 & _T_1114; // @[Mux.scala 27:72] + wire _T_1221 = _T_1115 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1223 = _T_1119 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1224 = _T_1121 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1225 = _T_1123 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1226 = _T_1125 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1227 = _T_1127 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1228 = _T_1129 & _T_1132; // @[Mux.scala 27:72] + wire _T_1229 = _T_1133 & _T_1136; // @[Mux.scala 27:72] + wire _T_1230 = _T_1137 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1231 = _T_1139 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1232 = _T_1141 & _T_1144; // @[Mux.scala 27:72] + wire _T_1233 = _T_1145 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1234 = _T_1147 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1235 = _T_1149 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1236 = _T_1151 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1237 = _T_1153 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1238 = _T_1155 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1239 = _T_1157 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1240 = _T_1159 & _T_1163; // @[Mux.scala 27:72] + wire _T_1241 = _T_1164 & _T_1173; // @[Mux.scala 27:72] + wire _T_1242 = _T_1174 & _T_1176; // @[Mux.scala 27:72] + wire _T_1243 = _T_1177 & _T_1179; // @[Mux.scala 27:72] + wire _T_1244 = _T_1180 & _T_1182; // @[Mux.scala 27:72] + wire _T_1245 = _T_1183 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1246 = _T_1185 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1247 = _T_1187 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1248 = _T_1189 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1249 = _T_1191 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1250 = _T_1026 | _T_1194; // @[Mux.scala 27:72] wire _T_1251 = _T_1250 | _T_1195; // @[Mux.scala 27:72] wire _T_1252 = _T_1251 | _T_1196; // @[Mux.scala 27:72] wire _T_1253 = _T_1252 | _T_1197; // @[Mux.scala 27:72] @@ -51581,7 +51577,7 @@ module csr_tlu( wire _T_1267 = _T_1266 | _T_1211; // @[Mux.scala 27:72] wire _T_1268 = _T_1267 | _T_1212; // @[Mux.scala 27:72] wire _T_1269 = _T_1268 | _T_1213; // @[Mux.scala 27:72] - wire _T_1270 = _T_1269 | _T_1193; // @[Mux.scala 27:72] + wire _T_1270 = _T_1269 | _T_1214; // @[Mux.scala 27:72] wire _T_1271 = _T_1270 | _T_1215; // @[Mux.scala 27:72] wire _T_1272 = _T_1271 | _T_1216; // @[Mux.scala 27:72] wire _T_1273 = _T_1272 | _T_1217; // @[Mux.scala 27:72] @@ -51589,7 +51585,7 @@ module csr_tlu( wire _T_1275 = _T_1274 | _T_1219; // @[Mux.scala 27:72] wire _T_1276 = _T_1275 | _T_1220; // @[Mux.scala 27:72] wire _T_1277 = _T_1276 | _T_1221; // @[Mux.scala 27:72] - wire _T_1278 = _T_1277 | _T_1222; // @[Mux.scala 27:72] + wire _T_1278 = _T_1277 | _T_1201; // @[Mux.scala 27:72] wire _T_1279 = _T_1278 | _T_1223; // @[Mux.scala 27:72] wire _T_1280 = _T_1279 | _T_1224; // @[Mux.scala 27:72] wire _T_1281 = _T_1280 | _T_1225; // @[Mux.scala 27:72] @@ -51609,129 +51605,129 @@ module csr_tlu( wire _T_1295 = _T_1294 | _T_1239; // @[Mux.scala 27:72] wire _T_1296 = _T_1295 | _T_1240; // @[Mux.scala 27:72] wire _T_1297 = _T_1296 | _T_1241; // @[Mux.scala 27:72] - wire mhpmc_inc_r_0 = _T_1017 & _T_1297; // @[dec_tlu_ctl.scala 2273:44] - wire _T_1301 = ~mcountinhibit[4]; // @[dec_tlu_ctl.scala 2273:24] + wire _T_1298 = _T_1297 | _T_1242; // @[Mux.scala 27:72] + wire _T_1299 = _T_1298 | _T_1243; // @[Mux.scala 27:72] + wire _T_1300 = _T_1299 | _T_1244; // @[Mux.scala 27:72] + wire _T_1301 = _T_1300 | _T_1245; // @[Mux.scala 27:72] + wire _T_1302 = _T_1301 | _T_1246; // @[Mux.scala 27:72] + wire _T_1303 = _T_1302 | _T_1247; // @[Mux.scala 27:72] + wire _T_1304 = _T_1303 | _T_1248; // @[Mux.scala 27:72] + wire _T_1305 = _T_1304 | _T_1249; // @[Mux.scala 27:72] + wire mhpmc_inc_r_0 = _T_1025 & _T_1305; // @[dec_tlu_ctl.scala 2273:44] + wire _T_1309 = ~mcountinhibit[4]; // @[dec_tlu_ctl.scala 2273:24] reg [9:0] mhpme4; // @[Reg.scala 27:20] - wire _T_1302 = mhpme4 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1304 = mhpme4 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1306 = mhpme4 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1308 = mhpme4 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1312 = mhpme4 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1318 = mhpme4 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1323 = mhpme4 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1325 = mhpme4 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1327 = mhpme4 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1329 = mhpme4 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1332 = mhpme4 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1335 = mhpme4 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1338 = mhpme4 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1341 = mhpme4 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1345 = mhpme4 == 10'he; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1350 = mhpme4 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1353 = mhpme4 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1356 = mhpme4 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1359 = mhpme4 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1362 = mhpme4 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1365 = mhpme4 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1368 = mhpme4 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1371 = mhpme4 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1374 = mhpme4 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1377 = mhpme4 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1382 = mhpme4 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1385 = mhpme4 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1388 = mhpme4 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1391 = mhpme4 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1395 = mhpme4 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] - wire _T_1397 = mhpme4 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1399 = mhpme4 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1401 = mhpme4 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1403 = mhpme4 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1405 = mhpme4 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1409 = mhpme4 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1413 = mhpme4 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1415 = mhpme4 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1417 = mhpme4 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1421 = mhpme4 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1423 = mhpme4 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] - wire _T_1425 = mhpme4 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] - wire _T_1427 = mhpme4 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] - wire _T_1429 = mhpme4 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] - wire _T_1431 = mhpme4 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] - wire _T_1433 = mhpme4 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] - wire _T_1435 = mhpme4 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] - wire _T_1440 = mhpme4 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] - wire _T_1450 = mhpme4 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] - wire _T_1453 = mhpme4 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] - wire _T_1456 = mhpme4 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] - wire _T_1459 = mhpme4 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] - wire _T_1461 = mhpme4 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] - wire _T_1463 = mhpme4 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] - wire _T_1465 = mhpme4 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] - wire _T_1467 = mhpme4 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] - wire _T_1470 = _T_1304 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_1471 = _T_1306 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_1472 = _T_1308 & _T_1027; // @[Mux.scala 27:72] - wire _T_1473 = _T_1312 & _T_1033; // @[Mux.scala 27:72] - wire _T_1474 = _T_1318 & _T_1038; // @[Mux.scala 27:72] - wire _T_1475 = _T_1323 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_1476 = _T_1325 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_1477 = _T_1327 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_1478 = _T_1329 & _T_1047; // @[Mux.scala 27:72] - wire _T_1479 = _T_1332 & _T_1050; // @[Mux.scala 27:72] - wire _T_1480 = _T_1335 & _T_1053; // @[Mux.scala 27:72] - wire _T_1481 = _T_1338 & _T_1056; // @[Mux.scala 27:72] - wire _T_1482 = _T_1341 & _T_1060; // @[Mux.scala 27:72] - wire _T_1483 = _T_1345 & _T_1065; // @[Mux.scala 27:72] - wire _T_1484 = _T_1350 & _T_1068; // @[Mux.scala 27:72] - wire _T_1485 = _T_1353 & _T_1071; // @[Mux.scala 27:72] - wire _T_1486 = _T_1356 & _T_1074; // @[Mux.scala 27:72] - wire _T_1487 = _T_1359 & _T_1077; // @[Mux.scala 27:72] - wire _T_1488 = _T_1362 & _T_1080; // @[Mux.scala 27:72] - wire _T_1489 = _T_1365 & _T_1083; // @[Mux.scala 27:72] - wire _T_1490 = _T_1368 & _T_1086; // @[Mux.scala 27:72] - wire _T_1491 = _T_1371 & _T_1089; // @[Mux.scala 27:72] - wire _T_1492 = _T_1374 & _T_1092; // @[Mux.scala 27:72] - wire _T_1493 = _T_1377 & _T_1097; // @[Mux.scala 27:72] - wire _T_1494 = _T_1382 & _T_1100; // @[Mux.scala 27:72] - wire _T_1495 = _T_1385 & _T_1103; // @[Mux.scala 27:72] - wire _T_1496 = _T_1388 & _T_1106; // @[Mux.scala 27:72] - wire _T_1497 = _T_1391 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_1499 = _T_1395 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_1500 = _T_1397 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_1501 = _T_1399 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_1502 = _T_1401 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_1503 = _T_1403 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_1504 = _T_1405 & _T_1124; // @[Mux.scala 27:72] - wire _T_1505 = _T_1409 & _T_1128; // @[Mux.scala 27:72] - wire _T_1506 = _T_1413 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_1507 = _T_1415 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_1508 = _T_1417 & _T_1136; // @[Mux.scala 27:72] - wire _T_1509 = _T_1421 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1510 = _T_1423 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1511 = _T_1425 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_1512 = _T_1427 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1513 = _T_1429 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1514 = _T_1431 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1515 = _T_1433 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1516 = _T_1435 & _T_1155; // @[Mux.scala 27:72] - wire _T_1517 = _T_1440 & _T_1165; // @[Mux.scala 27:72] - wire _T_1518 = _T_1450 & _T_1168; // @[Mux.scala 27:72] - wire _T_1519 = _T_1453 & _T_1171; // @[Mux.scala 27:72] - wire _T_1520 = _T_1456 & _T_1174; // @[Mux.scala 27:72] - wire _T_1521 = _T_1459 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_1522 = _T_1461 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_1523 = _T_1463 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_1524 = _T_1465 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_1525 = _T_1467 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_1526 = _T_1302 | _T_1470; // @[Mux.scala 27:72] - wire _T_1527 = _T_1526 | _T_1471; // @[Mux.scala 27:72] - wire _T_1528 = _T_1527 | _T_1472; // @[Mux.scala 27:72] - wire _T_1529 = _T_1528 | _T_1473; // @[Mux.scala 27:72] - wire _T_1530 = _T_1529 | _T_1474; // @[Mux.scala 27:72] - wire _T_1531 = _T_1530 | _T_1475; // @[Mux.scala 27:72] - wire _T_1532 = _T_1531 | _T_1476; // @[Mux.scala 27:72] - wire _T_1533 = _T_1532 | _T_1477; // @[Mux.scala 27:72] - wire _T_1534 = _T_1533 | _T_1478; // @[Mux.scala 27:72] + wire _T_1310 = mhpme4 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1312 = mhpme4 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1314 = mhpme4 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1316 = mhpme4 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1320 = mhpme4 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1326 = mhpme4 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1331 = mhpme4 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1333 = mhpme4 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1335 = mhpme4 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1337 = mhpme4 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1340 = mhpme4 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1343 = mhpme4 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1346 = mhpme4 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1349 = mhpme4 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1353 = mhpme4 == 10'he; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1358 = mhpme4 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1361 = mhpme4 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1364 = mhpme4 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1367 = mhpme4 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1370 = mhpme4 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1373 = mhpme4 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1376 = mhpme4 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1379 = mhpme4 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1382 = mhpme4 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1385 = mhpme4 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1390 = mhpme4 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1393 = mhpme4 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1396 = mhpme4 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1399 = mhpme4 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1403 = mhpme4 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] + wire _T_1405 = mhpme4 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1407 = mhpme4 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1409 = mhpme4 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1411 = mhpme4 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1413 = mhpme4 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1417 = mhpme4 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1421 = mhpme4 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1423 = mhpme4 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1425 = mhpme4 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1429 = mhpme4 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] + wire _T_1431 = mhpme4 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] + wire _T_1433 = mhpme4 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] + wire _T_1435 = mhpme4 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] + wire _T_1437 = mhpme4 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] + wire _T_1439 = mhpme4 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] + wire _T_1441 = mhpme4 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] + wire _T_1443 = mhpme4 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] + wire _T_1448 = mhpme4 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] + wire _T_1458 = mhpme4 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] + wire _T_1461 = mhpme4 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] + wire _T_1464 = mhpme4 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] + wire _T_1467 = mhpme4 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] + wire _T_1469 = mhpme4 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] + wire _T_1471 = mhpme4 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] + wire _T_1473 = mhpme4 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] + wire _T_1475 = mhpme4 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] + wire _T_1478 = _T_1312 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1479 = _T_1314 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1480 = _T_1316 & _T_1035; // @[Mux.scala 27:72] + wire _T_1481 = _T_1320 & _T_1041; // @[Mux.scala 27:72] + wire _T_1482 = _T_1326 & _T_1046; // @[Mux.scala 27:72] + wire _T_1483 = _T_1331 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1484 = _T_1333 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1485 = _T_1335 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1486 = _T_1337 & _T_1055; // @[Mux.scala 27:72] + wire _T_1487 = _T_1340 & _T_1058; // @[Mux.scala 27:72] + wire _T_1488 = _T_1343 & _T_1061; // @[Mux.scala 27:72] + wire _T_1489 = _T_1346 & _T_1064; // @[Mux.scala 27:72] + wire _T_1490 = _T_1349 & _T_1068; // @[Mux.scala 27:72] + wire _T_1491 = _T_1353 & _T_1073; // @[Mux.scala 27:72] + wire _T_1492 = _T_1358 & _T_1076; // @[Mux.scala 27:72] + wire _T_1493 = _T_1361 & _T_1079; // @[Mux.scala 27:72] + wire _T_1494 = _T_1364 & _T_1082; // @[Mux.scala 27:72] + wire _T_1495 = _T_1367 & _T_1085; // @[Mux.scala 27:72] + wire _T_1496 = _T_1370 & _T_1088; // @[Mux.scala 27:72] + wire _T_1497 = _T_1373 & _T_1091; // @[Mux.scala 27:72] + wire _T_1498 = _T_1376 & _T_1094; // @[Mux.scala 27:72] + wire _T_1499 = _T_1379 & _T_1097; // @[Mux.scala 27:72] + wire _T_1500 = _T_1382 & _T_1100; // @[Mux.scala 27:72] + wire _T_1501 = _T_1385 & _T_1105; // @[Mux.scala 27:72] + wire _T_1502 = _T_1390 & _T_1108; // @[Mux.scala 27:72] + wire _T_1503 = _T_1393 & _T_1111; // @[Mux.scala 27:72] + wire _T_1504 = _T_1396 & _T_1114; // @[Mux.scala 27:72] + wire _T_1505 = _T_1399 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1507 = _T_1403 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1508 = _T_1405 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1509 = _T_1407 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1510 = _T_1409 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1511 = _T_1411 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1512 = _T_1413 & _T_1132; // @[Mux.scala 27:72] + wire _T_1513 = _T_1417 & _T_1136; // @[Mux.scala 27:72] + wire _T_1514 = _T_1421 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1515 = _T_1423 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1516 = _T_1425 & _T_1144; // @[Mux.scala 27:72] + wire _T_1517 = _T_1429 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1518 = _T_1431 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1519 = _T_1433 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1520 = _T_1435 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1521 = _T_1437 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1522 = _T_1439 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1523 = _T_1441 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1524 = _T_1443 & _T_1163; // @[Mux.scala 27:72] + wire _T_1525 = _T_1448 & _T_1173; // @[Mux.scala 27:72] + wire _T_1526 = _T_1458 & _T_1176; // @[Mux.scala 27:72] + wire _T_1527 = _T_1461 & _T_1179; // @[Mux.scala 27:72] + wire _T_1528 = _T_1464 & _T_1182; // @[Mux.scala 27:72] + wire _T_1529 = _T_1467 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1530 = _T_1469 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1531 = _T_1471 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1532 = _T_1473 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1533 = _T_1475 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1534 = _T_1310 | _T_1478; // @[Mux.scala 27:72] wire _T_1535 = _T_1534 | _T_1479; // @[Mux.scala 27:72] wire _T_1536 = _T_1535 | _T_1480; // @[Mux.scala 27:72] wire _T_1537 = _T_1536 | _T_1481; // @[Mux.scala 27:72] @@ -51751,7 +51747,7 @@ module csr_tlu( wire _T_1551 = _T_1550 | _T_1495; // @[Mux.scala 27:72] wire _T_1552 = _T_1551 | _T_1496; // @[Mux.scala 27:72] wire _T_1553 = _T_1552 | _T_1497; // @[Mux.scala 27:72] - wire _T_1554 = _T_1553 | _T_1477; // @[Mux.scala 27:72] + wire _T_1554 = _T_1553 | _T_1498; // @[Mux.scala 27:72] wire _T_1555 = _T_1554 | _T_1499; // @[Mux.scala 27:72] wire _T_1556 = _T_1555 | _T_1500; // @[Mux.scala 27:72] wire _T_1557 = _T_1556 | _T_1501; // @[Mux.scala 27:72] @@ -51759,7 +51755,7 @@ module csr_tlu( wire _T_1559 = _T_1558 | _T_1503; // @[Mux.scala 27:72] wire _T_1560 = _T_1559 | _T_1504; // @[Mux.scala 27:72] wire _T_1561 = _T_1560 | _T_1505; // @[Mux.scala 27:72] - wire _T_1562 = _T_1561 | _T_1506; // @[Mux.scala 27:72] + wire _T_1562 = _T_1561 | _T_1485; // @[Mux.scala 27:72] wire _T_1563 = _T_1562 | _T_1507; // @[Mux.scala 27:72] wire _T_1564 = _T_1563 | _T_1508; // @[Mux.scala 27:72] wire _T_1565 = _T_1564 | _T_1509; // @[Mux.scala 27:72] @@ -51779,129 +51775,129 @@ module csr_tlu( wire _T_1579 = _T_1578 | _T_1523; // @[Mux.scala 27:72] wire _T_1580 = _T_1579 | _T_1524; // @[Mux.scala 27:72] wire _T_1581 = _T_1580 | _T_1525; // @[Mux.scala 27:72] - wire mhpmc_inc_r_1 = _T_1301 & _T_1581; // @[dec_tlu_ctl.scala 2273:44] - wire _T_1585 = ~mcountinhibit[5]; // @[dec_tlu_ctl.scala 2273:24] + wire _T_1582 = _T_1581 | _T_1526; // @[Mux.scala 27:72] + wire _T_1583 = _T_1582 | _T_1527; // @[Mux.scala 27:72] + wire _T_1584 = _T_1583 | _T_1528; // @[Mux.scala 27:72] + wire _T_1585 = _T_1584 | _T_1529; // @[Mux.scala 27:72] + wire _T_1586 = _T_1585 | _T_1530; // @[Mux.scala 27:72] + wire _T_1587 = _T_1586 | _T_1531; // @[Mux.scala 27:72] + wire _T_1588 = _T_1587 | _T_1532; // @[Mux.scala 27:72] + wire _T_1589 = _T_1588 | _T_1533; // @[Mux.scala 27:72] + wire mhpmc_inc_r_1 = _T_1309 & _T_1589; // @[dec_tlu_ctl.scala 2273:44] + wire _T_1593 = ~mcountinhibit[5]; // @[dec_tlu_ctl.scala 2273:24] reg [9:0] mhpme5; // @[Reg.scala 27:20] - wire _T_1586 = mhpme5 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1588 = mhpme5 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1590 = mhpme5 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1592 = mhpme5 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1596 = mhpme5 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1602 = mhpme5 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1607 = mhpme5 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1609 = mhpme5 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1611 = mhpme5 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1613 = mhpme5 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1616 = mhpme5 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1619 = mhpme5 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1622 = mhpme5 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1625 = mhpme5 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1629 = mhpme5 == 10'he; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1634 = mhpme5 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1637 = mhpme5 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1640 = mhpme5 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1643 = mhpme5 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1646 = mhpme5 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1649 = mhpme5 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1652 = mhpme5 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1655 = mhpme5 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1658 = mhpme5 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1661 = mhpme5 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1666 = mhpme5 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1669 = mhpme5 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1672 = mhpme5 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1675 = mhpme5 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1679 = mhpme5 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] - wire _T_1681 = mhpme5 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1683 = mhpme5 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1685 = mhpme5 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1687 = mhpme5 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1689 = mhpme5 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1693 = mhpme5 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1697 = mhpme5 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1699 = mhpme5 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1701 = mhpme5 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1705 = mhpme5 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1707 = mhpme5 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] - wire _T_1709 = mhpme5 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] - wire _T_1711 = mhpme5 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] - wire _T_1713 = mhpme5 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] - wire _T_1715 = mhpme5 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] - wire _T_1717 = mhpme5 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] - wire _T_1719 = mhpme5 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] - wire _T_1724 = mhpme5 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] - wire _T_1734 = mhpme5 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] - wire _T_1737 = mhpme5 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] - wire _T_1740 = mhpme5 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] - wire _T_1743 = mhpme5 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] - wire _T_1745 = mhpme5 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] - wire _T_1747 = mhpme5 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] - wire _T_1749 = mhpme5 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] - wire _T_1751 = mhpme5 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] - wire _T_1754 = _T_1588 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_1755 = _T_1590 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_1756 = _T_1592 & _T_1027; // @[Mux.scala 27:72] - wire _T_1757 = _T_1596 & _T_1033; // @[Mux.scala 27:72] - wire _T_1758 = _T_1602 & _T_1038; // @[Mux.scala 27:72] - wire _T_1759 = _T_1607 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_1760 = _T_1609 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_1761 = _T_1611 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_1762 = _T_1613 & _T_1047; // @[Mux.scala 27:72] - wire _T_1763 = _T_1616 & _T_1050; // @[Mux.scala 27:72] - wire _T_1764 = _T_1619 & _T_1053; // @[Mux.scala 27:72] - wire _T_1765 = _T_1622 & _T_1056; // @[Mux.scala 27:72] - wire _T_1766 = _T_1625 & _T_1060; // @[Mux.scala 27:72] - wire _T_1767 = _T_1629 & _T_1065; // @[Mux.scala 27:72] - wire _T_1768 = _T_1634 & _T_1068; // @[Mux.scala 27:72] - wire _T_1769 = _T_1637 & _T_1071; // @[Mux.scala 27:72] - wire _T_1770 = _T_1640 & _T_1074; // @[Mux.scala 27:72] - wire _T_1771 = _T_1643 & _T_1077; // @[Mux.scala 27:72] - wire _T_1772 = _T_1646 & _T_1080; // @[Mux.scala 27:72] - wire _T_1773 = _T_1649 & _T_1083; // @[Mux.scala 27:72] - wire _T_1774 = _T_1652 & _T_1086; // @[Mux.scala 27:72] - wire _T_1775 = _T_1655 & _T_1089; // @[Mux.scala 27:72] - wire _T_1776 = _T_1658 & _T_1092; // @[Mux.scala 27:72] - wire _T_1777 = _T_1661 & _T_1097; // @[Mux.scala 27:72] - wire _T_1778 = _T_1666 & _T_1100; // @[Mux.scala 27:72] - wire _T_1779 = _T_1669 & _T_1103; // @[Mux.scala 27:72] - wire _T_1780 = _T_1672 & _T_1106; // @[Mux.scala 27:72] - wire _T_1781 = _T_1675 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_1783 = _T_1679 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_1784 = _T_1681 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_1785 = _T_1683 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_1786 = _T_1685 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_1787 = _T_1687 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_1788 = _T_1689 & _T_1124; // @[Mux.scala 27:72] - wire _T_1789 = _T_1693 & _T_1128; // @[Mux.scala 27:72] - wire _T_1790 = _T_1697 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_1791 = _T_1699 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_1792 = _T_1701 & _T_1136; // @[Mux.scala 27:72] - wire _T_1793 = _T_1705 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1794 = _T_1707 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1795 = _T_1709 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_1796 = _T_1711 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1797 = _T_1713 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1798 = _T_1715 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1799 = _T_1717 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1800 = _T_1719 & _T_1155; // @[Mux.scala 27:72] - wire _T_1801 = _T_1724 & _T_1165; // @[Mux.scala 27:72] - wire _T_1802 = _T_1734 & _T_1168; // @[Mux.scala 27:72] - wire _T_1803 = _T_1737 & _T_1171; // @[Mux.scala 27:72] - wire _T_1804 = _T_1740 & _T_1174; // @[Mux.scala 27:72] - wire _T_1805 = _T_1743 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_1806 = _T_1745 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_1807 = _T_1747 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_1808 = _T_1749 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_1809 = _T_1751 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_1810 = _T_1586 | _T_1754; // @[Mux.scala 27:72] - wire _T_1811 = _T_1810 | _T_1755; // @[Mux.scala 27:72] - wire _T_1812 = _T_1811 | _T_1756; // @[Mux.scala 27:72] - wire _T_1813 = _T_1812 | _T_1757; // @[Mux.scala 27:72] - wire _T_1814 = _T_1813 | _T_1758; // @[Mux.scala 27:72] - wire _T_1815 = _T_1814 | _T_1759; // @[Mux.scala 27:72] - wire _T_1816 = _T_1815 | _T_1760; // @[Mux.scala 27:72] - wire _T_1817 = _T_1816 | _T_1761; // @[Mux.scala 27:72] - wire _T_1818 = _T_1817 | _T_1762; // @[Mux.scala 27:72] + wire _T_1594 = mhpme5 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1596 = mhpme5 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1598 = mhpme5 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1600 = mhpme5 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1604 = mhpme5 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1610 = mhpme5 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1615 = mhpme5 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1617 = mhpme5 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1619 = mhpme5 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1621 = mhpme5 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1624 = mhpme5 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1627 = mhpme5 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1630 = mhpme5 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1633 = mhpme5 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1637 = mhpme5 == 10'he; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1642 = mhpme5 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1645 = mhpme5 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1648 = mhpme5 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1651 = mhpme5 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1654 = mhpme5 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1657 = mhpme5 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1660 = mhpme5 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1663 = mhpme5 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1666 = mhpme5 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1669 = mhpme5 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1674 = mhpme5 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1677 = mhpme5 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1680 = mhpme5 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1683 = mhpme5 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1687 = mhpme5 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] + wire _T_1689 = mhpme5 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1691 = mhpme5 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1693 = mhpme5 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1695 = mhpme5 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1697 = mhpme5 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1701 = mhpme5 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1705 = mhpme5 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1707 = mhpme5 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1709 = mhpme5 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1713 = mhpme5 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] + wire _T_1715 = mhpme5 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] + wire _T_1717 = mhpme5 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] + wire _T_1719 = mhpme5 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] + wire _T_1721 = mhpme5 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] + wire _T_1723 = mhpme5 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] + wire _T_1725 = mhpme5 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] + wire _T_1727 = mhpme5 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] + wire _T_1732 = mhpme5 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] + wire _T_1742 = mhpme5 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] + wire _T_1745 = mhpme5 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] + wire _T_1748 = mhpme5 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] + wire _T_1751 = mhpme5 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] + wire _T_1753 = mhpme5 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] + wire _T_1755 = mhpme5 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] + wire _T_1757 = mhpme5 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] + wire _T_1759 = mhpme5 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] + wire _T_1762 = _T_1596 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1763 = _T_1598 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1764 = _T_1600 & _T_1035; // @[Mux.scala 27:72] + wire _T_1765 = _T_1604 & _T_1041; // @[Mux.scala 27:72] + wire _T_1766 = _T_1610 & _T_1046; // @[Mux.scala 27:72] + wire _T_1767 = _T_1615 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1768 = _T_1617 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1769 = _T_1619 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1770 = _T_1621 & _T_1055; // @[Mux.scala 27:72] + wire _T_1771 = _T_1624 & _T_1058; // @[Mux.scala 27:72] + wire _T_1772 = _T_1627 & _T_1061; // @[Mux.scala 27:72] + wire _T_1773 = _T_1630 & _T_1064; // @[Mux.scala 27:72] + wire _T_1774 = _T_1633 & _T_1068; // @[Mux.scala 27:72] + wire _T_1775 = _T_1637 & _T_1073; // @[Mux.scala 27:72] + wire _T_1776 = _T_1642 & _T_1076; // @[Mux.scala 27:72] + wire _T_1777 = _T_1645 & _T_1079; // @[Mux.scala 27:72] + wire _T_1778 = _T_1648 & _T_1082; // @[Mux.scala 27:72] + wire _T_1779 = _T_1651 & _T_1085; // @[Mux.scala 27:72] + wire _T_1780 = _T_1654 & _T_1088; // @[Mux.scala 27:72] + wire _T_1781 = _T_1657 & _T_1091; // @[Mux.scala 27:72] + wire _T_1782 = _T_1660 & _T_1094; // @[Mux.scala 27:72] + wire _T_1783 = _T_1663 & _T_1097; // @[Mux.scala 27:72] + wire _T_1784 = _T_1666 & _T_1100; // @[Mux.scala 27:72] + wire _T_1785 = _T_1669 & _T_1105; // @[Mux.scala 27:72] + wire _T_1786 = _T_1674 & _T_1108; // @[Mux.scala 27:72] + wire _T_1787 = _T_1677 & _T_1111; // @[Mux.scala 27:72] + wire _T_1788 = _T_1680 & _T_1114; // @[Mux.scala 27:72] + wire _T_1789 = _T_1683 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1791 = _T_1687 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1792 = _T_1689 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1793 = _T_1691 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1794 = _T_1693 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1795 = _T_1695 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1796 = _T_1697 & _T_1132; // @[Mux.scala 27:72] + wire _T_1797 = _T_1701 & _T_1136; // @[Mux.scala 27:72] + wire _T_1798 = _T_1705 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1799 = _T_1707 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1800 = _T_1709 & _T_1144; // @[Mux.scala 27:72] + wire _T_1801 = _T_1713 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1802 = _T_1715 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1803 = _T_1717 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1804 = _T_1719 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1805 = _T_1721 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1806 = _T_1723 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1807 = _T_1725 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1808 = _T_1727 & _T_1163; // @[Mux.scala 27:72] + wire _T_1809 = _T_1732 & _T_1173; // @[Mux.scala 27:72] + wire _T_1810 = _T_1742 & _T_1176; // @[Mux.scala 27:72] + wire _T_1811 = _T_1745 & _T_1179; // @[Mux.scala 27:72] + wire _T_1812 = _T_1748 & _T_1182; // @[Mux.scala 27:72] + wire _T_1813 = _T_1751 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1814 = _T_1753 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1815 = _T_1755 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1816 = _T_1757 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1817 = _T_1759 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1818 = _T_1594 | _T_1762; // @[Mux.scala 27:72] wire _T_1819 = _T_1818 | _T_1763; // @[Mux.scala 27:72] wire _T_1820 = _T_1819 | _T_1764; // @[Mux.scala 27:72] wire _T_1821 = _T_1820 | _T_1765; // @[Mux.scala 27:72] @@ -51921,7 +51917,7 @@ module csr_tlu( wire _T_1835 = _T_1834 | _T_1779; // @[Mux.scala 27:72] wire _T_1836 = _T_1835 | _T_1780; // @[Mux.scala 27:72] wire _T_1837 = _T_1836 | _T_1781; // @[Mux.scala 27:72] - wire _T_1838 = _T_1837 | _T_1761; // @[Mux.scala 27:72] + wire _T_1838 = _T_1837 | _T_1782; // @[Mux.scala 27:72] wire _T_1839 = _T_1838 | _T_1783; // @[Mux.scala 27:72] wire _T_1840 = _T_1839 | _T_1784; // @[Mux.scala 27:72] wire _T_1841 = _T_1840 | _T_1785; // @[Mux.scala 27:72] @@ -51929,7 +51925,7 @@ module csr_tlu( wire _T_1843 = _T_1842 | _T_1787; // @[Mux.scala 27:72] wire _T_1844 = _T_1843 | _T_1788; // @[Mux.scala 27:72] wire _T_1845 = _T_1844 | _T_1789; // @[Mux.scala 27:72] - wire _T_1846 = _T_1845 | _T_1790; // @[Mux.scala 27:72] + wire _T_1846 = _T_1845 | _T_1769; // @[Mux.scala 27:72] wire _T_1847 = _T_1846 | _T_1791; // @[Mux.scala 27:72] wire _T_1848 = _T_1847 | _T_1792; // @[Mux.scala 27:72] wire _T_1849 = _T_1848 | _T_1793; // @[Mux.scala 27:72] @@ -51949,129 +51945,129 @@ module csr_tlu( wire _T_1863 = _T_1862 | _T_1807; // @[Mux.scala 27:72] wire _T_1864 = _T_1863 | _T_1808; // @[Mux.scala 27:72] wire _T_1865 = _T_1864 | _T_1809; // @[Mux.scala 27:72] - wire mhpmc_inc_r_2 = _T_1585 & _T_1865; // @[dec_tlu_ctl.scala 2273:44] - wire _T_1869 = ~mcountinhibit[6]; // @[dec_tlu_ctl.scala 2273:24] + wire _T_1866 = _T_1865 | _T_1810; // @[Mux.scala 27:72] + wire _T_1867 = _T_1866 | _T_1811; // @[Mux.scala 27:72] + wire _T_1868 = _T_1867 | _T_1812; // @[Mux.scala 27:72] + wire _T_1869 = _T_1868 | _T_1813; // @[Mux.scala 27:72] + wire _T_1870 = _T_1869 | _T_1814; // @[Mux.scala 27:72] + wire _T_1871 = _T_1870 | _T_1815; // @[Mux.scala 27:72] + wire _T_1872 = _T_1871 | _T_1816; // @[Mux.scala 27:72] + wire _T_1873 = _T_1872 | _T_1817; // @[Mux.scala 27:72] + wire mhpmc_inc_r_2 = _T_1593 & _T_1873; // @[dec_tlu_ctl.scala 2273:44] + wire _T_1877 = ~mcountinhibit[6]; // @[dec_tlu_ctl.scala 2273:24] reg [9:0] mhpme6; // @[Reg.scala 27:20] - wire _T_1870 = mhpme6 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1872 = mhpme6 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1874 = mhpme6 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1876 = mhpme6 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1880 = mhpme6 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1886 = mhpme6 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1891 = mhpme6 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1893 = mhpme6 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1895 = mhpme6 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1897 = mhpme6 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1900 = mhpme6 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1903 = mhpme6 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1906 = mhpme6 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1909 = mhpme6 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1913 = mhpme6 == 10'he; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1918 = mhpme6 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1921 = mhpme6 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1924 = mhpme6 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1927 = mhpme6 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1930 = mhpme6 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1933 = mhpme6 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1936 = mhpme6 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1939 = mhpme6 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1942 = mhpme6 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1945 = mhpme6 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1950 = mhpme6 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1953 = mhpme6 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1956 = mhpme6 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1959 = mhpme6 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1963 = mhpme6 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] - wire _T_1965 = mhpme6 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1967 = mhpme6 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1969 = mhpme6 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1971 = mhpme6 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1973 = mhpme6 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1977 = mhpme6 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1981 = mhpme6 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1983 = mhpme6 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1985 = mhpme6 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1989 = mhpme6 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1991 = mhpme6 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] - wire _T_1993 = mhpme6 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] - wire _T_1995 = mhpme6 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] - wire _T_1997 = mhpme6 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] - wire _T_1999 = mhpme6 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] - wire _T_2001 = mhpme6 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] - wire _T_2003 = mhpme6 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] - wire _T_2008 = mhpme6 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] - wire _T_2018 = mhpme6 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] - wire _T_2021 = mhpme6 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] - wire _T_2024 = mhpme6 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] - wire _T_2027 = mhpme6 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] - wire _T_2029 = mhpme6 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] - wire _T_2031 = mhpme6 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] - wire _T_2033 = mhpme6 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] - wire _T_2035 = mhpme6 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] - wire _T_2038 = _T_1872 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_2039 = _T_1874 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_2040 = _T_1876 & _T_1027; // @[Mux.scala 27:72] - wire _T_2041 = _T_1880 & _T_1033; // @[Mux.scala 27:72] - wire _T_2042 = _T_1886 & _T_1038; // @[Mux.scala 27:72] - wire _T_2043 = _T_1891 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_2044 = _T_1893 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_2045 = _T_1895 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_2046 = _T_1897 & _T_1047; // @[Mux.scala 27:72] - wire _T_2047 = _T_1900 & _T_1050; // @[Mux.scala 27:72] - wire _T_2048 = _T_1903 & _T_1053; // @[Mux.scala 27:72] - wire _T_2049 = _T_1906 & _T_1056; // @[Mux.scala 27:72] - wire _T_2050 = _T_1909 & _T_1060; // @[Mux.scala 27:72] - wire _T_2051 = _T_1913 & _T_1065; // @[Mux.scala 27:72] - wire _T_2052 = _T_1918 & _T_1068; // @[Mux.scala 27:72] - wire _T_2053 = _T_1921 & _T_1071; // @[Mux.scala 27:72] - wire _T_2054 = _T_1924 & _T_1074; // @[Mux.scala 27:72] - wire _T_2055 = _T_1927 & _T_1077; // @[Mux.scala 27:72] - wire _T_2056 = _T_1930 & _T_1080; // @[Mux.scala 27:72] - wire _T_2057 = _T_1933 & _T_1083; // @[Mux.scala 27:72] - wire _T_2058 = _T_1936 & _T_1086; // @[Mux.scala 27:72] - wire _T_2059 = _T_1939 & _T_1089; // @[Mux.scala 27:72] - wire _T_2060 = _T_1942 & _T_1092; // @[Mux.scala 27:72] - wire _T_2061 = _T_1945 & _T_1097; // @[Mux.scala 27:72] - wire _T_2062 = _T_1950 & _T_1100; // @[Mux.scala 27:72] - wire _T_2063 = _T_1953 & _T_1103; // @[Mux.scala 27:72] - wire _T_2064 = _T_1956 & _T_1106; // @[Mux.scala 27:72] - wire _T_2065 = _T_1959 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_2067 = _T_1963 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_2068 = _T_1965 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_2069 = _T_1967 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_2070 = _T_1969 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_2071 = _T_1971 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_2072 = _T_1973 & _T_1124; // @[Mux.scala 27:72] - wire _T_2073 = _T_1977 & _T_1128; // @[Mux.scala 27:72] - wire _T_2074 = _T_1981 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_2075 = _T_1983 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_2076 = _T_1985 & _T_1136; // @[Mux.scala 27:72] - wire _T_2077 = _T_1989 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_2078 = _T_1991 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_2079 = _T_1993 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_2080 = _T_1995 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_2081 = _T_1997 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_2082 = _T_1999 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_2083 = _T_2001 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_2084 = _T_2003 & _T_1155; // @[Mux.scala 27:72] - wire _T_2085 = _T_2008 & _T_1165; // @[Mux.scala 27:72] - wire _T_2086 = _T_2018 & _T_1168; // @[Mux.scala 27:72] - wire _T_2087 = _T_2021 & _T_1171; // @[Mux.scala 27:72] - wire _T_2088 = _T_2024 & _T_1174; // @[Mux.scala 27:72] - wire _T_2089 = _T_2027 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_2090 = _T_2029 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_2091 = _T_2031 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_2092 = _T_2033 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_2093 = _T_2035 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_2094 = _T_1870 | _T_2038; // @[Mux.scala 27:72] - wire _T_2095 = _T_2094 | _T_2039; // @[Mux.scala 27:72] - wire _T_2096 = _T_2095 | _T_2040; // @[Mux.scala 27:72] - wire _T_2097 = _T_2096 | _T_2041; // @[Mux.scala 27:72] - wire _T_2098 = _T_2097 | _T_2042; // @[Mux.scala 27:72] - wire _T_2099 = _T_2098 | _T_2043; // @[Mux.scala 27:72] - wire _T_2100 = _T_2099 | _T_2044; // @[Mux.scala 27:72] - wire _T_2101 = _T_2100 | _T_2045; // @[Mux.scala 27:72] - wire _T_2102 = _T_2101 | _T_2046; // @[Mux.scala 27:72] + wire _T_1878 = mhpme6 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1880 = mhpme6 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1882 = mhpme6 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1884 = mhpme6 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1888 = mhpme6 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1894 = mhpme6 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1899 = mhpme6 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1901 = mhpme6 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1903 = mhpme6 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1905 = mhpme6 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1908 = mhpme6 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1911 = mhpme6 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1914 = mhpme6 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1917 = mhpme6 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1921 = mhpme6 == 10'he; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1926 = mhpme6 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1929 = mhpme6 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1932 = mhpme6 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1935 = mhpme6 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1938 = mhpme6 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1941 = mhpme6 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1944 = mhpme6 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1947 = mhpme6 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1950 = mhpme6 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1953 = mhpme6 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1958 = mhpme6 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1961 = mhpme6 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1964 = mhpme6 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1967 = mhpme6 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1971 = mhpme6 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] + wire _T_1973 = mhpme6 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1975 = mhpme6 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1977 = mhpme6 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1979 = mhpme6 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1981 = mhpme6 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1985 = mhpme6 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1989 = mhpme6 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1991 = mhpme6 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1993 = mhpme6 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1997 = mhpme6 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] + wire _T_1999 = mhpme6 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] + wire _T_2001 = mhpme6 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] + wire _T_2003 = mhpme6 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] + wire _T_2005 = mhpme6 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] + wire _T_2007 = mhpme6 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] + wire _T_2009 = mhpme6 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] + wire _T_2011 = mhpme6 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] + wire _T_2016 = mhpme6 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] + wire _T_2026 = mhpme6 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] + wire _T_2029 = mhpme6 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] + wire _T_2032 = mhpme6 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] + wire _T_2035 = mhpme6 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] + wire _T_2037 = mhpme6 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] + wire _T_2039 = mhpme6 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] + wire _T_2041 = mhpme6 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] + wire _T_2043 = mhpme6 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] + wire _T_2046 = _T_1880 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_2047 = _T_1882 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_2048 = _T_1884 & _T_1035; // @[Mux.scala 27:72] + wire _T_2049 = _T_1888 & _T_1041; // @[Mux.scala 27:72] + wire _T_2050 = _T_1894 & _T_1046; // @[Mux.scala 27:72] + wire _T_2051 = _T_1899 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_2052 = _T_1901 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_2053 = _T_1903 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_2054 = _T_1905 & _T_1055; // @[Mux.scala 27:72] + wire _T_2055 = _T_1908 & _T_1058; // @[Mux.scala 27:72] + wire _T_2056 = _T_1911 & _T_1061; // @[Mux.scala 27:72] + wire _T_2057 = _T_1914 & _T_1064; // @[Mux.scala 27:72] + wire _T_2058 = _T_1917 & _T_1068; // @[Mux.scala 27:72] + wire _T_2059 = _T_1921 & _T_1073; // @[Mux.scala 27:72] + wire _T_2060 = _T_1926 & _T_1076; // @[Mux.scala 27:72] + wire _T_2061 = _T_1929 & _T_1079; // @[Mux.scala 27:72] + wire _T_2062 = _T_1932 & _T_1082; // @[Mux.scala 27:72] + wire _T_2063 = _T_1935 & _T_1085; // @[Mux.scala 27:72] + wire _T_2064 = _T_1938 & _T_1088; // @[Mux.scala 27:72] + wire _T_2065 = _T_1941 & _T_1091; // @[Mux.scala 27:72] + wire _T_2066 = _T_1944 & _T_1094; // @[Mux.scala 27:72] + wire _T_2067 = _T_1947 & _T_1097; // @[Mux.scala 27:72] + wire _T_2068 = _T_1950 & _T_1100; // @[Mux.scala 27:72] + wire _T_2069 = _T_1953 & _T_1105; // @[Mux.scala 27:72] + wire _T_2070 = _T_1958 & _T_1108; // @[Mux.scala 27:72] + wire _T_2071 = _T_1961 & _T_1111; // @[Mux.scala 27:72] + wire _T_2072 = _T_1964 & _T_1114; // @[Mux.scala 27:72] + wire _T_2073 = _T_1967 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_2075 = _T_1971 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_2076 = _T_1973 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_2077 = _T_1975 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_2078 = _T_1977 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_2079 = _T_1979 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_2080 = _T_1981 & _T_1132; // @[Mux.scala 27:72] + wire _T_2081 = _T_1985 & _T_1136; // @[Mux.scala 27:72] + wire _T_2082 = _T_1989 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_2083 = _T_1991 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_2084 = _T_1993 & _T_1144; // @[Mux.scala 27:72] + wire _T_2085 = _T_1997 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_2086 = _T_1999 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_2087 = _T_2001 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_2088 = _T_2003 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_2089 = _T_2005 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_2090 = _T_2007 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_2091 = _T_2009 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_2092 = _T_2011 & _T_1163; // @[Mux.scala 27:72] + wire _T_2093 = _T_2016 & _T_1173; // @[Mux.scala 27:72] + wire _T_2094 = _T_2026 & _T_1176; // @[Mux.scala 27:72] + wire _T_2095 = _T_2029 & _T_1179; // @[Mux.scala 27:72] + wire _T_2096 = _T_2032 & _T_1182; // @[Mux.scala 27:72] + wire _T_2097 = _T_2035 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_2098 = _T_2037 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_2099 = _T_2039 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_2100 = _T_2041 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_2101 = _T_2043 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_2102 = _T_1878 | _T_2046; // @[Mux.scala 27:72] wire _T_2103 = _T_2102 | _T_2047; // @[Mux.scala 27:72] wire _T_2104 = _T_2103 | _T_2048; // @[Mux.scala 27:72] wire _T_2105 = _T_2104 | _T_2049; // @[Mux.scala 27:72] @@ -52091,7 +52087,7 @@ module csr_tlu( wire _T_2119 = _T_2118 | _T_2063; // @[Mux.scala 27:72] wire _T_2120 = _T_2119 | _T_2064; // @[Mux.scala 27:72] wire _T_2121 = _T_2120 | _T_2065; // @[Mux.scala 27:72] - wire _T_2122 = _T_2121 | _T_2045; // @[Mux.scala 27:72] + wire _T_2122 = _T_2121 | _T_2066; // @[Mux.scala 27:72] wire _T_2123 = _T_2122 | _T_2067; // @[Mux.scala 27:72] wire _T_2124 = _T_2123 | _T_2068; // @[Mux.scala 27:72] wire _T_2125 = _T_2124 | _T_2069; // @[Mux.scala 27:72] @@ -52099,7 +52095,7 @@ module csr_tlu( wire _T_2127 = _T_2126 | _T_2071; // @[Mux.scala 27:72] wire _T_2128 = _T_2127 | _T_2072; // @[Mux.scala 27:72] wire _T_2129 = _T_2128 | _T_2073; // @[Mux.scala 27:72] - wire _T_2130 = _T_2129 | _T_2074; // @[Mux.scala 27:72] + wire _T_2130 = _T_2129 | _T_2053; // @[Mux.scala 27:72] wire _T_2131 = _T_2130 | _T_2075; // @[Mux.scala 27:72] wire _T_2132 = _T_2131 | _T_2076; // @[Mux.scala 27:72] wire _T_2133 = _T_2132 | _T_2077; // @[Mux.scala 27:72] @@ -52119,194 +52115,194 @@ module csr_tlu( wire _T_2147 = _T_2146 | _T_2091; // @[Mux.scala 27:72] wire _T_2148 = _T_2147 | _T_2092; // @[Mux.scala 27:72] wire _T_2149 = _T_2148 | _T_2093; // @[Mux.scala 27:72] - wire mhpmc_inc_r_3 = _T_1869 & _T_2149; // @[dec_tlu_ctl.scala 2273:44] + wire _T_2150 = _T_2149 | _T_2094; // @[Mux.scala 27:72] + wire _T_2151 = _T_2150 | _T_2095; // @[Mux.scala 27:72] + wire _T_2152 = _T_2151 | _T_2096; // @[Mux.scala 27:72] + wire _T_2153 = _T_2152 | _T_2097; // @[Mux.scala 27:72] + wire _T_2154 = _T_2153 | _T_2098; // @[Mux.scala 27:72] + wire _T_2155 = _T_2154 | _T_2099; // @[Mux.scala 27:72] + wire _T_2156 = _T_2155 | _T_2100; // @[Mux.scala 27:72] + wire _T_2157 = _T_2156 | _T_2101; // @[Mux.scala 27:72] + wire mhpmc_inc_r_3 = _T_1877 & _T_2157; // @[dec_tlu_ctl.scala 2273:44] reg mhpmc_inc_r_d1_0; // @[dec_tlu_ctl.scala 2334:53] reg mhpmc_inc_r_d1_1; // @[dec_tlu_ctl.scala 2335:53] reg mhpmc_inc_r_d1_2; // @[dec_tlu_ctl.scala 2336:53] reg mhpmc_inc_r_d1_3; // @[dec_tlu_ctl.scala 2337:53] reg perfcnt_halted_d1; // @[dec_tlu_ctl.scala 2338:56] wire perfcnt_halted = _T_85 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2341:67] - wire _T_2161 = ~_T_85; // @[dec_tlu_ctl.scala 2342:37] - wire [3:0] _T_2163 = _T_2161 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_2170 = {mhpme6[9],mhpme5[9],mhpme4[9],mhpme3[9]}; // @[Cat.scala 29:58] - wire [3:0] perfcnt_during_sleep = _T_2163 & _T_2170; // @[dec_tlu_ctl.scala 2342:86] - wire _T_2172 = ~perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2344:67] - wire _T_2173 = perfcnt_halted_d1 & _T_2172; // @[dec_tlu_ctl.scala 2344:65] - wire _T_2174 = ~_T_2173; // @[dec_tlu_ctl.scala 2344:45] - wire _T_2177 = ~perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2345:67] - wire _T_2178 = perfcnt_halted_d1 & _T_2177; // @[dec_tlu_ctl.scala 2345:65] - wire _T_2179 = ~_T_2178; // @[dec_tlu_ctl.scala 2345:45] - wire _T_2182 = ~perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2346:67] - wire _T_2183 = perfcnt_halted_d1 & _T_2182; // @[dec_tlu_ctl.scala 2346:65] - wire _T_2184 = ~_T_2183; // @[dec_tlu_ctl.scala 2346:45] - wire _T_2187 = ~perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2347:67] - wire _T_2188 = perfcnt_halted_d1 & _T_2187; // @[dec_tlu_ctl.scala 2347:65] - wire _T_2189 = ~_T_2188; // @[dec_tlu_ctl.scala 2347:45] - wire _T_2192 = io_dec_csr_wraddr_r == 12'hb03; // @[dec_tlu_ctl.scala 2353:72] - wire mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_2192; // @[dec_tlu_ctl.scala 2353:43] - wire _T_2193 = ~perfcnt_halted; // @[dec_tlu_ctl.scala 2354:23] - wire _T_2195 = _T_2193 | perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2354:39] - wire _T_2196 = |mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 2354:86] - wire mhpmc3_wr_en1 = _T_2195 & _T_2196; // @[dec_tlu_ctl.scala 2354:66] + wire _T_2169 = ~_T_85; // @[dec_tlu_ctl.scala 2342:37] + wire [3:0] _T_2171 = _T_2169 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_2178 = {mhpme6[9],mhpme5[9],mhpme4[9],mhpme3[9]}; // @[Cat.scala 29:58] + wire [3:0] perfcnt_during_sleep = _T_2171 & _T_2178; // @[dec_tlu_ctl.scala 2342:86] + wire _T_2180 = ~perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2344:67] + wire _T_2181 = perfcnt_halted_d1 & _T_2180; // @[dec_tlu_ctl.scala 2344:65] + wire _T_2182 = ~_T_2181; // @[dec_tlu_ctl.scala 2344:45] + wire _T_2185 = ~perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2345:67] + wire _T_2186 = perfcnt_halted_d1 & _T_2185; // @[dec_tlu_ctl.scala 2345:65] + wire _T_2187 = ~_T_2186; // @[dec_tlu_ctl.scala 2345:45] + wire _T_2190 = ~perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2346:67] + wire _T_2191 = perfcnt_halted_d1 & _T_2190; // @[dec_tlu_ctl.scala 2346:65] + wire _T_2192 = ~_T_2191; // @[dec_tlu_ctl.scala 2346:45] + wire _T_2195 = ~perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2347:67] + wire _T_2196 = perfcnt_halted_d1 & _T_2195; // @[dec_tlu_ctl.scala 2347:65] + wire _T_2197 = ~_T_2196; // @[dec_tlu_ctl.scala 2347:45] + wire _T_2200 = io_dec_csr_wraddr_r == 12'hb03; // @[dec_tlu_ctl.scala 2353:72] + wire mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_2200; // @[dec_tlu_ctl.scala 2353:43] + wire _T_2201 = ~perfcnt_halted; // @[dec_tlu_ctl.scala 2354:23] + wire _T_2203 = _T_2201 | perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2354:39] + wire _T_2204 = |mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 2354:86] + wire mhpmc3_wr_en1 = _T_2203 & _T_2204; // @[dec_tlu_ctl.scala 2354:66] reg [31:0] mhpmc3h; // @[lib.scala 374:16] reg [31:0] mhpmc3; // @[lib.scala 374:16] - wire [63:0] _T_2199 = {mhpmc3h,mhpmc3}; // @[Cat.scala 29:58] - wire [63:0] _T_2200 = {63'h0,mhpmc_inc_r_0}; // @[Cat.scala 29:58] - wire [63:0] mhpmc3_incr = _T_2199 + _T_2200; // @[dec_tlu_ctl.scala 2358:49] - wire _T_2208 = io_dec_csr_wraddr_r == 12'hb83; // @[dec_tlu_ctl.scala 2363:73] - wire mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_2208; // @[dec_tlu_ctl.scala 2363:44] - wire _T_2214 = io_dec_csr_wraddr_r == 12'hb04; // @[dec_tlu_ctl.scala 2372:72] - wire mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_2214; // @[dec_tlu_ctl.scala 2372:43] - wire _T_2217 = _T_2193 | perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2373:39] - wire _T_2218 = |mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 2373:86] - wire mhpmc4_wr_en1 = _T_2217 & _T_2218; // @[dec_tlu_ctl.scala 2373:66] + wire [63:0] _T_2207 = {mhpmc3h,mhpmc3}; // @[Cat.scala 29:58] + wire [63:0] _T_2208 = {63'h0,mhpmc_inc_r_0}; // @[Cat.scala 29:58] + wire [63:0] mhpmc3_incr = _T_2207 + _T_2208; // @[dec_tlu_ctl.scala 2358:49] + wire _T_2216 = io_dec_csr_wraddr_r == 12'hb83; // @[dec_tlu_ctl.scala 2363:73] + wire mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_2216; // @[dec_tlu_ctl.scala 2363:44] + wire _T_2222 = io_dec_csr_wraddr_r == 12'hb04; // @[dec_tlu_ctl.scala 2372:72] + wire mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_2222; // @[dec_tlu_ctl.scala 2372:43] + wire _T_2225 = _T_2201 | perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2373:39] + wire _T_2226 = |mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 2373:86] + wire mhpmc4_wr_en1 = _T_2225 & _T_2226; // @[dec_tlu_ctl.scala 2373:66] reg [31:0] mhpmc4h; // @[lib.scala 374:16] reg [31:0] mhpmc4; // @[lib.scala 374:16] - wire [63:0] _T_2221 = {mhpmc4h,mhpmc4}; // @[Cat.scala 29:58] - wire [63:0] _T_2222 = {63'h0,mhpmc_inc_r_1}; // @[Cat.scala 29:58] - wire [63:0] mhpmc4_incr = _T_2221 + _T_2222; // @[dec_tlu_ctl.scala 2378:49] - wire _T_2231 = io_dec_csr_wraddr_r == 12'hb84; // @[dec_tlu_ctl.scala 2382:73] - wire mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_2231; // @[dec_tlu_ctl.scala 2382:44] - wire _T_2237 = io_dec_csr_wraddr_r == 12'hb05; // @[dec_tlu_ctl.scala 2391:72] - wire mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_2237; // @[dec_tlu_ctl.scala 2391:43] - wire _T_2240 = _T_2193 | perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2392:39] - wire _T_2241 = |mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 2392:86] - wire mhpmc5_wr_en1 = _T_2240 & _T_2241; // @[dec_tlu_ctl.scala 2392:66] + wire [63:0] _T_2229 = {mhpmc4h,mhpmc4}; // @[Cat.scala 29:58] + wire [63:0] _T_2230 = {63'h0,mhpmc_inc_r_1}; // @[Cat.scala 29:58] + wire [63:0] mhpmc4_incr = _T_2229 + _T_2230; // @[dec_tlu_ctl.scala 2378:49] + wire _T_2239 = io_dec_csr_wraddr_r == 12'hb84; // @[dec_tlu_ctl.scala 2382:73] + wire mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_2239; // @[dec_tlu_ctl.scala 2382:44] + wire _T_2245 = io_dec_csr_wraddr_r == 12'hb05; // @[dec_tlu_ctl.scala 2391:72] + wire mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_2245; // @[dec_tlu_ctl.scala 2391:43] + wire _T_2248 = _T_2201 | perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2392:39] + wire _T_2249 = |mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 2392:86] + wire mhpmc5_wr_en1 = _T_2248 & _T_2249; // @[dec_tlu_ctl.scala 2392:66] reg [31:0] mhpmc5h; // @[lib.scala 374:16] reg [31:0] mhpmc5; // @[lib.scala 374:16] - wire [63:0] _T_2244 = {mhpmc5h,mhpmc5}; // @[Cat.scala 29:58] - wire [63:0] _T_2245 = {63'h0,mhpmc_inc_r_2}; // @[Cat.scala 29:58] - wire [63:0] mhpmc5_incr = _T_2244 + _T_2245; // @[dec_tlu_ctl.scala 2395:49] - wire _T_2253 = io_dec_csr_wraddr_r == 12'hb85; // @[dec_tlu_ctl.scala 2400:73] - wire mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_2253; // @[dec_tlu_ctl.scala 2400:44] - wire _T_2259 = io_dec_csr_wraddr_r == 12'hb06; // @[dec_tlu_ctl.scala 2409:72] - wire mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_2259; // @[dec_tlu_ctl.scala 2409:43] - wire _T_2262 = _T_2193 | perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2410:39] - wire _T_2263 = |mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 2410:86] - wire mhpmc6_wr_en1 = _T_2262 & _T_2263; // @[dec_tlu_ctl.scala 2410:66] + wire [63:0] _T_2252 = {mhpmc5h,mhpmc5}; // @[Cat.scala 29:58] + wire [63:0] _T_2253 = {63'h0,mhpmc_inc_r_2}; // @[Cat.scala 29:58] + wire [63:0] mhpmc5_incr = _T_2252 + _T_2253; // @[dec_tlu_ctl.scala 2395:49] + wire _T_2261 = io_dec_csr_wraddr_r == 12'hb85; // @[dec_tlu_ctl.scala 2400:73] + wire mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_2261; // @[dec_tlu_ctl.scala 2400:44] + wire _T_2267 = io_dec_csr_wraddr_r == 12'hb06; // @[dec_tlu_ctl.scala 2409:72] + wire mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_2267; // @[dec_tlu_ctl.scala 2409:43] + wire _T_2270 = _T_2201 | perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2410:39] + wire _T_2271 = |mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 2410:86] + wire mhpmc6_wr_en1 = _T_2270 & _T_2271; // @[dec_tlu_ctl.scala 2410:66] reg [31:0] mhpmc6h; // @[lib.scala 374:16] reg [31:0] mhpmc6; // @[lib.scala 374:16] - wire [63:0] _T_2266 = {mhpmc6h,mhpmc6}; // @[Cat.scala 29:58] - wire [63:0] _T_2267 = {63'h0,mhpmc_inc_r_3}; // @[Cat.scala 29:58] - wire [63:0] mhpmc6_incr = _T_2266 + _T_2267; // @[dec_tlu_ctl.scala 2413:49] - wire _T_2275 = io_dec_csr_wraddr_r == 12'hb86; // @[dec_tlu_ctl.scala 2418:73] - wire mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_2275; // @[dec_tlu_ctl.scala 2418:44] - wire _T_2281 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[dec_tlu_ctl.scala 2429:56] - wire _T_2283 = |io_dec_csr_wrdata_r[31:10]; // @[dec_tlu_ctl.scala 2429:102] - wire _T_2284 = _T_2281 | _T_2283; // @[dec_tlu_ctl.scala 2429:71] - wire _T_2287 = io_dec_csr_wraddr_r == 12'h323; // @[dec_tlu_ctl.scala 2431:70] - wire wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_2287; // @[dec_tlu_ctl.scala 2431:41] - wire _T_2291 = io_dec_csr_wraddr_r == 12'h324; // @[dec_tlu_ctl.scala 2438:70] - wire wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_2291; // @[dec_tlu_ctl.scala 2438:41] - wire _T_2295 = io_dec_csr_wraddr_r == 12'h325; // @[dec_tlu_ctl.scala 2445:70] - wire wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_2295; // @[dec_tlu_ctl.scala 2445:41] - wire _T_2299 = io_dec_csr_wraddr_r == 12'h326; // @[dec_tlu_ctl.scala 2452:70] - wire wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_2299; // @[dec_tlu_ctl.scala 2452:41] - wire _T_2303 = io_dec_csr_wraddr_r == 12'h320; // @[dec_tlu_ctl.scala 2469:77] - wire wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_2303; // @[dec_tlu_ctl.scala 2469:48] - wire _T_2315 = io_i0_valid_wb | io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 2484:51] - wire _T_2316 = _T_2315 | io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 2484:78] - wire _T_2317 = _T_2316 | io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 2484:104] - wire _T_2318 = _T_2317 | io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 2484:130] - wire _T_2319 = _T_2318 | io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 2485:32] - reg _T_2322; // @[dec_tlu_ctl.scala 2487:62] - wire _T_2323 = io_i0_exception_valid_r_d1 | io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 2488:91] - wire _T_2324 = ~io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 2488:137] - wire _T_2325 = io_trigger_hit_r_d1 & _T_2324; // @[dec_tlu_ctl.scala 2488:135] - reg _T_2327; // @[dec_tlu_ctl.scala 2488:62] - reg [4:0] _T_2328; // @[dec_tlu_ctl.scala 2489:62] - reg _T_2329; // @[dec_tlu_ctl.scala 2490:62] - wire [31:0] _T_2335 = {io_core_id,4'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2344 = {21'h3,3'h0,io_mstatus[1],3'h0,io_mstatus[0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2349 = {io_mtvec[30:1],1'h0,io_mtvec[0]}; // @[Cat.scala 29:58] - wire [31:0] _T_2362 = {1'h0,io_mip[5:3],16'h0,io_mip[2],3'h0,io_mip[1],3'h0,io_mip[0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2375 = {1'h0,mie[5:3],16'h0,mie[2],3'h0,mie[1],3'h0,mie[0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2387 = {io_mepc,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2392 = {28'h0,mscause}; // @[Cat.scala 29:58] - wire [31:0] _T_2400 = {meivt,10'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2403 = {meivt,meihap,2'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2406 = {28'h0,meicurpl}; // @[Cat.scala 29:58] - wire [31:0] _T_2409 = {28'h0,meicidpl}; // @[Cat.scala 29:58] - wire [31:0] _T_2412 = {28'h0,meipt}; // @[Cat.scala 29:58] - wire [31:0] _T_2415 = {23'h0,mcgc}; // @[Cat.scala 29:58] - wire [31:0] _T_2418 = {13'h0,_T_345,4'h0,mfdc_int[11:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_2422 = {16'h4000,io_dcsr[15:2],2'h3}; // @[Cat.scala 29:58] - wire [31:0] _T_2424 = {io_dpc,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2440 = {7'h0,dicawics[16],2'h0,dicawics[15:14],3'h0,dicawics[13:0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2443 = {30'h0,mtsel}; // @[Cat.scala 29:58] - wire [31:0] _T_2472 = {26'h0,mfdht}; // @[Cat.scala 29:58] - wire [31:0] _T_2475 = {30'h0,mfdhs}; // @[Cat.scala 29:58] - wire [31:0] _T_2478 = {22'h0,mhpme3}; // @[Cat.scala 29:58] - wire [31:0] _T_2481 = {22'h0,mhpme4}; // @[Cat.scala 29:58] - wire [31:0] _T_2484 = {22'h0,mhpme5}; // @[Cat.scala 29:58] - wire [31:0] _T_2487 = {22'h0,mhpme6}; // @[Cat.scala 29:58] - wire [31:0] _T_2490 = {25'h0,temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] - wire [31:0] _T_2493 = {30'h0,mpmc,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2496 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2497 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2498 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2499 = io_csr_pkt_csr_mimpid ? 32'h2 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2500 = io_csr_pkt_csr_mhartid ? _T_2335 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2501 = io_csr_pkt_csr_mstatus ? _T_2344 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2502 = io_csr_pkt_csr_mtvec ? _T_2349 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2503 = io_csr_pkt_csr_mip ? _T_2362 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2504 = io_csr_pkt_csr_mie ? _T_2375 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2505 = io_csr_pkt_csr_mcyclel ? mcyclel : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2506 = io_csr_pkt_csr_mcycleh ? mcycleh_inc : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2507 = io_csr_pkt_csr_minstretl ? minstretl : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2508 = io_csr_pkt_csr_minstreth ? minstreth_inc : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2509 = io_csr_pkt_csr_mscratch ? mscratch : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2510 = io_csr_pkt_csr_mepc ? _T_2387 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2511 = io_csr_pkt_csr_mcause ? mcause : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2512 = io_csr_pkt_csr_mscause ? _T_2392 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2513 = io_csr_pkt_csr_mtval ? mtval : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2514 = io_csr_pkt_csr_mrac ? mrac : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2515 = io_csr_pkt_csr_mdseac ? mdseac : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2516 = io_csr_pkt_csr_meivt ? _T_2400 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2517 = io_csr_pkt_csr_meihap ? _T_2403 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2518 = io_csr_pkt_csr_meicurpl ? _T_2406 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2519 = io_csr_pkt_csr_meicidpl ? _T_2409 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2520 = io_csr_pkt_csr_meipt ? _T_2412 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2521 = io_csr_pkt_csr_mcgc ? _T_2415 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2522 = io_csr_pkt_csr_mfdc ? _T_2418 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2523 = io_csr_pkt_csr_dcsr ? _T_2422 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2524 = io_csr_pkt_csr_dpc ? _T_2424 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2525 = io_csr_pkt_csr_dicad0 ? dicad0[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2526 = io_csr_pkt_csr_dicad0h ? dicad0h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2527 = io_csr_pkt_csr_dicad1 ? dicad1 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2528 = io_csr_pkt_csr_dicawics ? _T_2440 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2529 = io_csr_pkt_csr_mtsel ? _T_2443 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2530 = io_csr_pkt_csr_mtdata1 ? mtdata1_tsel_out : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2531 = io_csr_pkt_csr_mtdata2 ? mtdata2_tsel_out : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2532 = io_csr_pkt_csr_micect ? micect : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2533 = io_csr_pkt_csr_miccmect ? miccmect : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2534 = io_csr_pkt_csr_mdccmect ? mdccmect : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2535 = io_csr_pkt_csr_mhpmc3 ? mhpmc3 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2536 = io_csr_pkt_csr_mhpmc4 ? mhpmc4 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2537 = io_csr_pkt_csr_mhpmc5 ? mhpmc5 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2538 = io_csr_pkt_csr_mhpmc6 ? mhpmc6 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2539 = io_csr_pkt_csr_mhpmc3h ? mhpmc3h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2540 = io_csr_pkt_csr_mhpmc4h ? mhpmc4h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2541 = io_csr_pkt_csr_mhpmc5h ? mhpmc5h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2542 = io_csr_pkt_csr_mhpmc6h ? mhpmc6h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2543 = io_csr_pkt_csr_mfdht ? _T_2472 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2544 = io_csr_pkt_csr_mfdhs ? _T_2475 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2545 = io_csr_pkt_csr_mhpme3 ? _T_2478 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2546 = io_csr_pkt_csr_mhpme4 ? _T_2481 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2547 = io_csr_pkt_csr_mhpme5 ? _T_2484 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2548 = io_csr_pkt_csr_mhpme6 ? _T_2487 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2549 = io_csr_pkt_csr_mcountinhibit ? _T_2490 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2550 = io_csr_pkt_csr_mpmc ? _T_2493 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2551 = io_dec_timer_read_d ? io_dec_timer_rddata_d : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2552 = _T_2496 | _T_2497; // @[Mux.scala 27:72] - wire [31:0] _T_2553 = _T_2552 | _T_2498; // @[Mux.scala 27:72] - wire [31:0] _T_2554 = _T_2553 | _T_2499; // @[Mux.scala 27:72] - wire [31:0] _T_2555 = _T_2554 | _T_2500; // @[Mux.scala 27:72] - wire [31:0] _T_2556 = _T_2555 | _T_2501; // @[Mux.scala 27:72] - wire [31:0] _T_2557 = _T_2556 | _T_2502; // @[Mux.scala 27:72] - wire [31:0] _T_2558 = _T_2557 | _T_2503; // @[Mux.scala 27:72] - wire [31:0] _T_2559 = _T_2558 | _T_2504; // @[Mux.scala 27:72] - wire [31:0] _T_2560 = _T_2559 | _T_2505; // @[Mux.scala 27:72] + wire [63:0] _T_2274 = {mhpmc6h,mhpmc6}; // @[Cat.scala 29:58] + wire [63:0] _T_2275 = {63'h0,mhpmc_inc_r_3}; // @[Cat.scala 29:58] + wire [63:0] mhpmc6_incr = _T_2274 + _T_2275; // @[dec_tlu_ctl.scala 2413:49] + wire _T_2283 = io_dec_csr_wraddr_r == 12'hb86; // @[dec_tlu_ctl.scala 2418:73] + wire mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_2283; // @[dec_tlu_ctl.scala 2418:44] + wire _T_2289 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[dec_tlu_ctl.scala 2429:56] + wire _T_2291 = |io_dec_csr_wrdata_r[31:10]; // @[dec_tlu_ctl.scala 2429:102] + wire _T_2292 = _T_2289 | _T_2291; // @[dec_tlu_ctl.scala 2429:71] + wire _T_2295 = io_dec_csr_wraddr_r == 12'h323; // @[dec_tlu_ctl.scala 2431:70] + wire wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_2295; // @[dec_tlu_ctl.scala 2431:41] + wire _T_2299 = io_dec_csr_wraddr_r == 12'h324; // @[dec_tlu_ctl.scala 2438:70] + wire wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_2299; // @[dec_tlu_ctl.scala 2438:41] + wire _T_2303 = io_dec_csr_wraddr_r == 12'h325; // @[dec_tlu_ctl.scala 2445:70] + wire wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_2303; // @[dec_tlu_ctl.scala 2445:41] + wire _T_2307 = io_dec_csr_wraddr_r == 12'h326; // @[dec_tlu_ctl.scala 2452:70] + wire wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_2307; // @[dec_tlu_ctl.scala 2452:41] + wire _T_2311 = io_dec_csr_wraddr_r == 12'h320; // @[dec_tlu_ctl.scala 2469:77] + wire wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_2311; // @[dec_tlu_ctl.scala 2469:48] + wire _T_2323 = io_i0_valid_wb | io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 2484:51] + wire _T_2324 = _T_2323 | io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 2484:78] + wire _T_2325 = _T_2324 | io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 2484:104] + wire _T_2326 = _T_2325 | io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 2484:130] + wire _T_2327 = _T_2326 | io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 2485:32] + reg _T_2330; // @[dec_tlu_ctl.scala 2487:62] + wire _T_2331 = io_i0_exception_valid_r_d1 | io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 2488:91] + wire _T_2332 = ~io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 2488:137] + wire _T_2333 = io_trigger_hit_r_d1 & _T_2332; // @[dec_tlu_ctl.scala 2488:135] + reg _T_2335; // @[dec_tlu_ctl.scala 2488:62] + reg [4:0] _T_2336; // @[dec_tlu_ctl.scala 2489:62] + reg _T_2337; // @[dec_tlu_ctl.scala 2490:62] + wire [31:0] _T_2343 = {io_core_id,4'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2352 = {21'h3,3'h0,io_mstatus[1],3'h0,io_mstatus[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2357 = {io_mtvec[30:1],1'h0,io_mtvec[0]}; // @[Cat.scala 29:58] + wire [31:0] _T_2370 = {1'h0,io_mip[5:3],16'h0,io_mip[2],3'h0,io_mip[1],3'h0,io_mip[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2383 = {1'h0,mie[5:3],16'h0,mie[2],3'h0,mie[1],3'h0,mie[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2395 = {io_mepc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2400 = {28'h0,mscause}; // @[Cat.scala 29:58] + wire [31:0] _T_2408 = {meivt,10'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2411 = {meivt,meihap,2'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2414 = {28'h0,meicurpl}; // @[Cat.scala 29:58] + wire [31:0] _T_2417 = {28'h0,meicidpl}; // @[Cat.scala 29:58] + wire [31:0] _T_2420 = {28'h0,meipt}; // @[Cat.scala 29:58] + wire [31:0] _T_2423 = {23'h0,mcgc}; // @[Cat.scala 29:58] + wire [31:0] _T_2426 = {13'h0,_T_350,4'h0,mfdc_int[11:7],_T_353,mfdc_int[5:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_2430 = {16'h4000,io_dcsr[15:2],2'h3}; // @[Cat.scala 29:58] + wire [31:0] _T_2432 = {io_dpc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2448 = {7'h0,dicawics[16],2'h0,dicawics[15:14],3'h0,dicawics[13:0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2451 = {30'h0,mtsel}; // @[Cat.scala 29:58] + wire [31:0] _T_2480 = {26'h0,mfdht}; // @[Cat.scala 29:58] + wire [31:0] _T_2483 = {30'h0,mfdhs}; // @[Cat.scala 29:58] + wire [31:0] _T_2486 = {22'h0,mhpme3}; // @[Cat.scala 29:58] + wire [31:0] _T_2489 = {22'h0,mhpme4}; // @[Cat.scala 29:58] + wire [31:0] _T_2492 = {22'h0,mhpme5}; // @[Cat.scala 29:58] + wire [31:0] _T_2495 = {22'h0,mhpme6}; // @[Cat.scala 29:58] + wire [31:0] _T_2498 = {25'h0,temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] + wire [31:0] _T_2501 = {30'h0,mpmc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2504 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2505 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2506 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2507 = io_csr_pkt_csr_mimpid ? 32'h2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2508 = io_csr_pkt_csr_mhartid ? _T_2343 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2509 = io_csr_pkt_csr_mstatus ? _T_2352 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2510 = io_csr_pkt_csr_mtvec ? _T_2357 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2511 = io_csr_pkt_csr_mip ? _T_2370 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2512 = io_csr_pkt_csr_mie ? _T_2383 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2513 = io_csr_pkt_csr_mcyclel ? mcyclel : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2514 = io_csr_pkt_csr_mcycleh ? mcycleh_inc : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2515 = io_csr_pkt_csr_minstretl ? minstretl : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2516 = io_csr_pkt_csr_minstreth ? minstreth_inc : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2517 = io_csr_pkt_csr_mscratch ? mscratch : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2518 = io_csr_pkt_csr_mepc ? _T_2395 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2519 = io_csr_pkt_csr_mcause ? mcause : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2520 = io_csr_pkt_csr_mscause ? _T_2400 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2521 = io_csr_pkt_csr_mtval ? mtval : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2522 = io_csr_pkt_csr_mrac ? mrac : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2523 = io_csr_pkt_csr_mdseac ? mdseac : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2524 = io_csr_pkt_csr_meivt ? _T_2408 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2525 = io_csr_pkt_csr_meihap ? _T_2411 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2526 = io_csr_pkt_csr_meicurpl ? _T_2414 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2527 = io_csr_pkt_csr_meicidpl ? _T_2417 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2528 = io_csr_pkt_csr_meipt ? _T_2420 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2529 = io_csr_pkt_csr_mcgc ? _T_2423 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2530 = io_csr_pkt_csr_mfdc ? _T_2426 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2531 = io_csr_pkt_csr_dcsr ? _T_2430 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2532 = io_csr_pkt_csr_dpc ? _T_2432 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2533 = io_csr_pkt_csr_dicad0 ? dicad0[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2534 = io_csr_pkt_csr_dicad0h ? dicad0h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2535 = io_csr_pkt_csr_dicad1 ? dicad1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2536 = io_csr_pkt_csr_dicawics ? _T_2448 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2537 = io_csr_pkt_csr_mtsel ? _T_2451 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2538 = io_csr_pkt_csr_mtdata1 ? mtdata1_tsel_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2539 = io_csr_pkt_csr_mtdata2 ? mtdata2_tsel_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2540 = io_csr_pkt_csr_micect ? micect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2541 = io_csr_pkt_csr_miccmect ? miccmect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2542 = io_csr_pkt_csr_mdccmect ? mdccmect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2543 = io_csr_pkt_csr_mhpmc3 ? mhpmc3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2544 = io_csr_pkt_csr_mhpmc4 ? mhpmc4 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2545 = io_csr_pkt_csr_mhpmc5 ? mhpmc5 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2546 = io_csr_pkt_csr_mhpmc6 ? mhpmc6 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2547 = io_csr_pkt_csr_mhpmc3h ? mhpmc3h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2548 = io_csr_pkt_csr_mhpmc4h ? mhpmc4h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2549 = io_csr_pkt_csr_mhpmc5h ? mhpmc5h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2550 = io_csr_pkt_csr_mhpmc6h ? mhpmc6h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2551 = io_csr_pkt_csr_mfdht ? _T_2480 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2552 = io_csr_pkt_csr_mfdhs ? _T_2483 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2553 = io_csr_pkt_csr_mhpme3 ? _T_2486 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2554 = io_csr_pkt_csr_mhpme4 ? _T_2489 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2555 = io_csr_pkt_csr_mhpme5 ? _T_2492 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2556 = io_csr_pkt_csr_mhpme6 ? _T_2495 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2557 = io_csr_pkt_csr_mcountinhibit ? _T_2498 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2558 = io_csr_pkt_csr_mpmc ? _T_2501 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2559 = io_dec_timer_read_d ? io_dec_timer_rddata_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2560 = _T_2504 | _T_2505; // @[Mux.scala 27:72] wire [31:0] _T_2561 = _T_2560 | _T_2506; // @[Mux.scala 27:72] wire [31:0] _T_2562 = _T_2561 | _T_2507; // @[Mux.scala 27:72] wire [31:0] _T_2563 = _T_2562 | _T_2508; // @[Mux.scala 27:72] @@ -52352,6 +52348,14 @@ module csr_tlu( wire [31:0] _T_2603 = _T_2602 | _T_2548; // @[Mux.scala 27:72] wire [31:0] _T_2604 = _T_2603 | _T_2549; // @[Mux.scala 27:72] wire [31:0] _T_2605 = _T_2604 | _T_2550; // @[Mux.scala 27:72] + wire [31:0] _T_2606 = _T_2605 | _T_2551; // @[Mux.scala 27:72] + wire [31:0] _T_2607 = _T_2606 | _T_2552; // @[Mux.scala 27:72] + wire [31:0] _T_2608 = _T_2607 | _T_2553; // @[Mux.scala 27:72] + wire [31:0] _T_2609 = _T_2608 | _T_2554; // @[Mux.scala 27:72] + wire [31:0] _T_2610 = _T_2609 | _T_2555; // @[Mux.scala 27:72] + wire [31:0] _T_2611 = _T_2610 | _T_2556; // @[Mux.scala 27:72] + wire [31:0] _T_2612 = _T_2611 | _T_2557; // @[Mux.scala 27:72] + wire [31:0] _T_2613 = _T_2612 | _T_2558; // @[Mux.scala 27:72] rvclkhdr rvclkhdr ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -52562,7 +52566,7 @@ module csr_tlu( .io_en(rvclkhdr_34_io_en), .io_scan_mode(rvclkhdr_34_io_scan_mode) ); - assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {{1'd0}, _T_756}; // @[dec_tlu_ctl.scala 2155:47] + assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {_T_763,dicad0[31:0]}; // @[dec_tlu_ctl.scala 2154:61] assign io_dec_tlu_ic_diag_pkt_icache_dicawics = dicawics; // @[dec_tlu_ctl.scala 2157:41] assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = icache_rd_valid_f; // @[dec_tlu_ctl.scala 2165:41] assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = icache_wr_valid_f; // @[dec_tlu_ctl.scala 2166:41] @@ -52594,24 +52598,24 @@ module csr_tlu( assign io_trigger_pkt_any_3_execute = io_mtdata1_t_3[2]; // @[dec_tlu_ctl.scala 2234:40] assign io_trigger_pkt_any_3_m = io_mtdata1_t_3[3]; // @[dec_tlu_ctl.scala 2235:40] assign io_trigger_pkt_any_3_tdata2 = mtdata2_t_3; // @[dec_tlu_ctl.scala 2248:51] - assign io_dec_tlu_int_valid_wb1 = _T_2329; // @[dec_tlu_ctl.scala 2490:30] - assign io_dec_tlu_i0_exc_valid_wb1 = _T_2327; // @[dec_tlu_ctl.scala 2488:30] - assign io_dec_tlu_i0_valid_wb1 = _T_2322; // @[dec_tlu_ctl.scala 2487:30] + assign io_dec_tlu_int_valid_wb1 = _T_2337; // @[dec_tlu_ctl.scala 2490:30] + assign io_dec_tlu_i0_exc_valid_wb1 = _T_2335; // @[dec_tlu_ctl.scala 2488:30] + assign io_dec_tlu_i0_valid_wb1 = _T_2330; // @[dec_tlu_ctl.scala 2487:30] assign io_dec_tlu_mtval_wb1 = mtval; // @[dec_tlu_ctl.scala 2492:24] - assign io_dec_tlu_exc_cause_wb1 = _T_2328; // @[dec_tlu_ctl.scala 2489:30] - assign io_dec_tlu_perfcnt0 = mhpmc_inc_r_d1_0 & _T_2174; // @[dec_tlu_ctl.scala 2344:22] - assign io_dec_tlu_perfcnt1 = mhpmc_inc_r_d1_1 & _T_2179; // @[dec_tlu_ctl.scala 2345:22] - assign io_dec_tlu_perfcnt2 = mhpmc_inc_r_d1_2 & _T_2184; // @[dec_tlu_ctl.scala 2346:22] - assign io_dec_tlu_perfcnt3 = mhpmc_inc_r_d1_3 & _T_2189; // @[dec_tlu_ctl.scala 2347:22] + assign io_dec_tlu_exc_cause_wb1 = _T_2336; // @[dec_tlu_ctl.scala 2489:30] + assign io_dec_tlu_perfcnt0 = mhpmc_inc_r_d1_0 & _T_2182; // @[dec_tlu_ctl.scala 2344:22] + assign io_dec_tlu_perfcnt1 = mhpmc_inc_r_d1_1 & _T_2187; // @[dec_tlu_ctl.scala 2345:22] + assign io_dec_tlu_perfcnt2 = mhpmc_inc_r_d1_2 & _T_2192; // @[dec_tlu_ctl.scala 2346:22] + assign io_dec_tlu_perfcnt3 = mhpmc_inc_r_d1_3 & _T_2197; // @[dec_tlu_ctl.scala 2347:22] assign io_dec_tlu_misc_clk_override = mcgc[8]; // @[dec_tlu_ctl.scala 1717:31] assign io_dec_tlu_dec_clk_override = mcgc[7]; // @[dec_tlu_ctl.scala 1718:31] assign io_dec_tlu_lsu_clk_override = mcgc[4]; // @[dec_tlu_ctl.scala 1720:31] assign io_dec_tlu_pic_clk_override = mcgc[2]; // @[dec_tlu_ctl.scala 1722:31] assign io_dec_tlu_dccm_clk_override = mcgc[1]; // @[dec_tlu_ctl.scala 1723:31] assign io_dec_tlu_icm_clk_override = mcgc[0]; // @[dec_tlu_ctl.scala 1724:31] - assign io_dec_csr_rddata_d = _T_2605 | _T_2551; // @[dec_tlu_ctl.scala 2497:21] + assign io_dec_csr_rddata_d = _T_2613 | _T_2559; // @[dec_tlu_ctl.scala 2497:21] assign io_dec_tlu_pipelining_disable = mfdc[0]; // @[dec_tlu_ctl.scala 1767:39] - assign io_dec_tlu_wr_pause_r = _T_360 & _T_361; // @[dec_tlu_ctl.scala 1776:24] + assign io_dec_tlu_wr_pause_r = _T_370 & _T_371; // @[dec_tlu_ctl.scala 1776:24] assign io_dec_tlu_meipt = meipt; // @[dec_tlu_ctl.scala 2005:19] assign io_dec_tlu_meicurpl = meicurpl; // @[dec_tlu_ctl.scala 1969:22] assign io_dec_tlu_meihap = {meivt,meihap}; // @[dec_tlu_ctl.scala 1955:20] @@ -52623,23 +52627,23 @@ module csr_tlu( assign io_dec_tlu_external_ldfwd_disable = mfdc[11]; // @[dec_tlu_ctl.scala 1762:39] assign io_dec_tlu_dma_qos_prty = mfdc[18:16]; // @[dec_tlu_ctl.scala 1761:39] assign io_dec_csr_wen_r_mod = _T_1 & _T_2; // @[dec_tlu_ctl.scala 1450:23] - assign io_fw_halt_req = _T_492 & _T_493; // @[dec_tlu_ctl.scala 1841:17] + assign io_fw_halt_req = _T_502 & _T_503; // @[dec_tlu_ctl.scala 1841:17] assign io_mstatus = _T_56; // @[dec_tlu_ctl.scala 1466:13] assign io_mstatus_mie_ns = io_mstatus[0] & _T_54; // @[dec_tlu_ctl.scala 1465:20] - assign io_dcsr = _T_691; // @[dec_tlu_ctl.scala 2052:10] + assign io_dcsr = _T_701; // @[dec_tlu_ctl.scala 2052:10] assign io_mtvec = _T_62; // @[dec_tlu_ctl.scala 1478:11] assign io_mip = _T_68; // @[dec_tlu_ctl.scala 1493:9] assign io_mie_ns = wr_mie_r ? _T_78 : mie; // @[dec_tlu_ctl.scala 1507:12] assign io_npc_r = _T_161 | _T_159; // @[dec_tlu_ctl.scala 1601:11] assign io_npc_r_d1 = _T_167; // @[dec_tlu_ctl.scala 1607:14] assign io_mepc = _T_196; // @[dec_tlu_ctl.scala 1626:10] - assign io_mdseac_locked_ns = mdseac_en | _T_479; // @[dec_tlu_ctl.scala 1824:22] - assign io_force_halt = mfdht[0] & _T_599; // @[dec_tlu_ctl.scala 1932:16] - assign io_dpc = _T_716; // @[dec_tlu_ctl.scala 2069:9] - assign io_mtdata1_t_0 = _T_864; // @[dec_tlu_ctl.scala 2225:39] - assign io_mtdata1_t_1 = _T_865; // @[dec_tlu_ctl.scala 2225:39] - assign io_mtdata1_t_2 = _T_866; // @[dec_tlu_ctl.scala 2225:39] - assign io_mtdata1_t_3 = _T_867; // @[dec_tlu_ctl.scala 2225:39] + assign io_mdseac_locked_ns = mdseac_en | _T_489; // @[dec_tlu_ctl.scala 1824:22] + assign io_force_halt = mfdht[0] & _T_609; // @[dec_tlu_ctl.scala 1932:16] + assign io_dpc = _T_726; // @[dec_tlu_ctl.scala 2069:9] + assign io_mtdata1_t_0 = _T_872; // @[dec_tlu_ctl.scala 2225:39] + assign io_mtdata1_t_1 = _T_873; // @[dec_tlu_ctl.scala 2225:39] + assign io_mtdata1_t_2 = _T_874; // @[dec_tlu_ctl.scala 2225:39] + assign io_mtdata1_t_3 = _T_875; // @[dec_tlu_ctl.scala 2225:39] assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_io_en = io_dec_csr_wen_r_mod & _T_58; // @[lib.scala 371:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] @@ -52671,34 +52675,34 @@ module csr_tlu( assign rvclkhdr_9_io_en = io_dec_csr_wen_r_mod & _T_337; // @[lib.scala 371:17] assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_10_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_10_io_en = io_dec_csr_wen_r_mod & _T_364; // @[lib.scala 371:17] + assign rvclkhdr_10_io_en = io_dec_csr_wen_r_mod & _T_374; // @[lib.scala 371:17] assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_11_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_11_io_en = _T_483 & _T_484; // @[lib.scala 371:17] + assign rvclkhdr_11_io_en = _T_493 & _T_494; // @[lib.scala 371:17] assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_12_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_12_io_en = wr_micect_r | io_ic_perr_r_d1; // @[lib.scala 371:17] assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_13_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_13_io_en = _T_539 | io_iccm_dma_sb_error; // @[lib.scala 371:17] + assign rvclkhdr_13_io_en = _T_549 | io_iccm_dma_sb_error; // @[lib.scala 371:17] assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_14_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_14_io_en = wr_mdccmect_r | io_lsu_single_ecc_error_r_d1; // @[lib.scala 371:17] assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_15_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_15_io_en = io_dec_csr_wen_r_mod & _T_602; // @[lib.scala 371:17] + assign rvclkhdr_15_io_en = io_dec_csr_wen_r_mod & _T_612; // @[lib.scala 371:17] assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_16_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_16_io_en = _T_622 | io_take_ext_int_start; // @[lib.scala 371:17] + assign rvclkhdr_16_io_en = _T_632 | io_take_ext_int_start; // @[lib.scala 371:17] assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_17_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_17_io_en = _T_688 | io_take_nmi; // @[lib.scala 371:17] + assign rvclkhdr_17_io_en = _T_698 | io_take_nmi; // @[lib.scala 371:17] assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_18_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_18_io_en = _T_713 | dpc_capture_npc; // @[lib.scala 371:17] + assign rvclkhdr_18_io_en = _T_723 | dpc_capture_npc; // @[lib.scala 371:17] assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_19_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_19_io_en = _T_653 & _T_723; // @[lib.scala 371:17] + assign rvclkhdr_19_io_en = _T_663 & _T_733; // @[lib.scala 371:17] assign rvclkhdr_19_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_20_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_20_io_en = wr_dicad0_r | io_ifu_ic_debug_rd_data_valid; // @[lib.scala 371:17] @@ -52707,16 +52711,16 @@ module csr_tlu( assign rvclkhdr_21_io_en = wr_dicad0h_r | io_ifu_ic_debug_rd_data_valid; // @[lib.scala 371:17] assign rvclkhdr_21_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_22_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_22_io_en = _T_963 & _T_799; // @[lib.scala 371:17] + assign rvclkhdr_22_io_en = _T_971 & _T_807; // @[lib.scala 371:17] assign rvclkhdr_22_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_23_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_23_io_en = _T_972 & _T_808; // @[lib.scala 371:17] + assign rvclkhdr_23_io_en = _T_980 & _T_816; // @[lib.scala 371:17] assign rvclkhdr_23_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_24_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_24_io_en = _T_981 & _T_817; // @[lib.scala 371:17] + assign rvclkhdr_24_io_en = _T_989 & _T_825; // @[lib.scala 371:17] assign rvclkhdr_24_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_25_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_25_io_en = _T_990 & _T_826; // @[lib.scala 371:17] + assign rvclkhdr_25_io_en = _T_998 & _T_834; // @[lib.scala 371:17] assign rvclkhdr_25_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_26_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_26_io_en = mhpmc3_wr_en0 | mhpmc3_wr_en1; // @[lib.scala 371:17] @@ -52743,7 +52747,7 @@ module csr_tlu( assign rvclkhdr_33_io_en = mhpmc6h_wr_en0 | mhpmc6_wr_en1; // @[lib.scala 371:17] assign rvclkhdr_33_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_34_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_34_io_en = _T_2319 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_34_io_en = _T_2327 | io_clk_override; // @[lib.scala 345:16] assign rvclkhdr_34_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE @@ -52853,9 +52857,9 @@ initial begin _RAND_35 = {1{`RANDOM}}; meipt = _RAND_35[3:0]; _RAND_36 = {1{`RANDOM}}; - _T_691 = _RAND_36[15:0]; + _T_701 = _RAND_36[15:0]; _RAND_37 = {1{`RANDOM}}; - _T_716 = _RAND_37[30:0]; + _T_726 = _RAND_37[30:0]; _RAND_38 = {1{`RANDOM}}; dicawics = _RAND_38[16:0]; _RAND_39 = {3{`RANDOM}}; @@ -52863,7 +52867,7 @@ initial begin _RAND_40 = {1{`RANDOM}}; dicad0h = _RAND_40[31:0]; _RAND_41 = {1{`RANDOM}}; - _T_749 = _RAND_41[3:0]; + _T_758 = _RAND_41[31:0]; _RAND_42 = {1{`RANDOM}}; icache_rd_valid_f = _RAND_42[0:0]; _RAND_43 = {1{`RANDOM}}; @@ -52871,13 +52875,13 @@ initial begin _RAND_44 = {1{`RANDOM}}; mtsel = _RAND_44[1:0]; _RAND_45 = {1{`RANDOM}}; - _T_864 = _RAND_45[9:0]; + _T_872 = _RAND_45[9:0]; _RAND_46 = {1{`RANDOM}}; - _T_865 = _RAND_46[9:0]; + _T_873 = _RAND_46[9:0]; _RAND_47 = {1{`RANDOM}}; - _T_866 = _RAND_47[9:0]; + _T_874 = _RAND_47[9:0]; _RAND_48 = {1{`RANDOM}}; - _T_867 = _RAND_48[9:0]; + _T_875 = _RAND_48[9:0]; _RAND_49 = {1{`RANDOM}}; mtdata2_t_0 = _RAND_49[31:0]; _RAND_50 = {1{`RANDOM}}; @@ -52921,13 +52925,13 @@ initial begin _RAND_69 = {1{`RANDOM}}; mhpmc6 = _RAND_69[31:0]; _RAND_70 = {1{`RANDOM}}; - _T_2322 = _RAND_70[0:0]; + _T_2330 = _RAND_70[0:0]; _RAND_71 = {1{`RANDOM}}; - _T_2327 = _RAND_71[0:0]; + _T_2335 = _RAND_71[0:0]; _RAND_72 = {1{`RANDOM}}; - _T_2328 = _RAND_72[4:0]; + _T_2336 = _RAND_72[4:0]; _RAND_73 = {1{`RANDOM}}; - _T_2329 = _RAND_73[0:0]; + _T_2337 = _RAND_73[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin mpmc_b = 1'h0; @@ -53038,10 +53042,10 @@ initial begin meipt = 4'h0; end if (reset) begin - _T_691 = 16'h0; + _T_701 = 16'h0; end if (reset) begin - _T_716 = 31'h0; + _T_726 = 31'h0; end if (reset) begin dicawics = 17'h0; @@ -53053,7 +53057,7 @@ initial begin dicad0h = 32'h0; end if (reset) begin - _T_749 = 4'h0; + _T_758 = 32'h0; end if (reset) begin icache_rd_valid_f = 1'h0; @@ -53065,16 +53069,16 @@ initial begin mtsel = 2'h0; end if (reset) begin - _T_864 = 10'h0; + _T_872 = 10'h0; end if (reset) begin - _T_865 = 10'h0; + _T_873 = 10'h0; end if (reset) begin - _T_866 = 10'h0; + _T_874 = 10'h0; end if (reset) begin - _T_867 = 10'h0; + _T_875 = 10'h0; end if (reset) begin mtdata2_t_0 = 32'h0; @@ -53140,16 +53144,16 @@ initial begin mhpmc6 = 32'h0; end if (reset) begin - _T_2322 = 1'h0; + _T_2330 = 1'h0; end if (reset) begin - _T_2327 = 1'h0; + _T_2335 = 1'h0; end if (reset) begin - _T_2328 = 5'h0; + _T_2336 = 5'h0; end if (reset) begin - _T_2329 = 1'h0; + _T_2337 = 1'h0; end `endif // RANDOMIZE end // initial @@ -53161,9 +53165,9 @@ end // initial if (reset) begin mpmc_b <= 1'h0; end else if (wr_mpmc_r) begin - mpmc_b <= _T_500; + mpmc_b <= _T_510; end else begin - mpmc_b <= _T_501; + mpmc_b <= _T_511; end end always @(posedge io_free_clk or posedge reset) begin @@ -53184,27 +53188,27 @@ end // initial if (reset) begin mdccmect <= 32'h0; end else if (wr_mdccmect_r) begin - mdccmect <= _T_515; + mdccmect <= _T_525; end else begin - mdccmect <= _T_559; + mdccmect <= _T_569; end end always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin if (reset) begin miccmect <= 32'h0; end else if (wr_miccmect_r) begin - miccmect <= _T_515; + miccmect <= _T_525; end else begin - miccmect <= _T_538; + miccmect <= _T_548; end end always @(posedge rvclkhdr_12_io_l1clk or posedge reset) begin if (reset) begin micect <= 32'h0; end else if (wr_micect_r) begin - micect <= _T_515; + micect <= _T_525; end else begin - micect <= _T_517; + micect <= _T_527; end end always @(posedge io_free_clk or posedge reset) begin @@ -53352,14 +53356,14 @@ end // initial if (reset) begin mfdc_int <= 15'h0; end else begin - mfdc_int <= {_T_341,io_dec_csr_wrdata_r[11:0]}; + mfdc_int <= {_T_347,_T_346}; end end always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin if (reset) begin mrac <= 32'h0; end else begin - mrac <= {_T_474,_T_459}; + mrac <= {_T_484,_T_469}; end end always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin @@ -53379,11 +53383,11 @@ end // initial always @(posedge io_active_clk or posedge reset) begin if (reset) begin mfdhs <= 2'h0; - end else if (_T_585) begin + end else if (_T_595) begin if (wr_mfdhs_r) begin mfdhs <= io_dec_csr_wrdata_r[1:0]; - end else if (_T_579) begin - mfdhs <= _T_583; + end else if (_T_589) begin + mfdhs <= _T_593; end end end @@ -53392,7 +53396,7 @@ end // initial force_halt_ctr_f <= 32'h0; end else if (mfdht[0]) begin if (io_debug_halt_req_f) begin - force_halt_ctr_f <= _T_590; + force_halt_ctr_f <= _T_600; end else if (io_dbg_tlu_halted_f) begin force_halt_ctr_f <= 32'h0; end @@ -53437,27 +53441,27 @@ end // initial end always @(posedge rvclkhdr_17_io_l1clk or posedge reset) begin if (reset) begin - _T_691 <= 16'h0; + _T_701 <= 16'h0; end else if (enter_debug_halt_req_le) begin - _T_691 <= _T_665; + _T_701 <= _T_675; end else if (wr_dcsr_r) begin - _T_691 <= _T_680; + _T_701 <= _T_690; end else begin - _T_691 <= _T_685; + _T_701 <= _T_695; end end always @(posedge rvclkhdr_18_io_l1clk or posedge reset) begin if (reset) begin - _T_716 <= 31'h0; + _T_726 <= 31'h0; end else begin - _T_716 <= _T_711 | _T_710; + _T_726 <= _T_721 | _T_720; end end always @(posedge rvclkhdr_19_io_l1clk or posedge reset) begin if (reset) begin dicawics <= 17'h0; end else begin - dicawics <= {_T_720,io_dec_csr_wrdata_r[16:3]}; + dicawics <= {_T_730,io_dec_csr_wrdata_r[16:3]}; end end always @(posedge rvclkhdr_20_io_l1clk or posedge reset) begin @@ -53480,12 +53484,12 @@ end // initial end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_749 <= 4'h0; - end else if (_T_747) begin - if (_T_742) begin - _T_749 <= io_dec_csr_wrdata_r[3:0]; + _T_758 <= 32'h0; + end else if (_T_756) begin + if (_T_752) begin + _T_758 <= io_dec_csr_wrdata_r; end else begin - _T_749 <= io_ifu_ic_debug_rd_data[67:64]; + _T_758 <= {{25'd0}, io_ifu_ic_debug_rd_data[70:64]}; end end end @@ -53493,14 +53497,14 @@ end // initial if (reset) begin icache_rd_valid_f <= 1'h0; end else begin - icache_rd_valid_f <= _T_760 & _T_762; + icache_rd_valid_f <= _T_768 & _T_770; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin icache_wr_valid_f <= 1'h0; end else begin - icache_wr_valid_f <= _T_653 & _T_765; + icache_wr_valid_f <= _T_663 & _T_773; end end always @(posedge io_csr_wr_clk or posedge reset) begin @@ -53512,38 +53516,38 @@ end // initial end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_864 <= 10'h0; + _T_872 <= 10'h0; end else if (wr_mtdata1_t_r_0) begin - _T_864 <= tdata_wrdata_r; + _T_872 <= tdata_wrdata_r; end else begin - _T_864 <= _T_835; + _T_872 <= _T_843; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_865 <= 10'h0; + _T_873 <= 10'h0; end else if (wr_mtdata1_t_r_1) begin - _T_865 <= tdata_wrdata_r; + _T_873 <= tdata_wrdata_r; end else begin - _T_865 <= _T_844; + _T_873 <= _T_852; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_866 <= 10'h0; + _T_874 <= 10'h0; end else if (wr_mtdata1_t_r_2) begin - _T_866 <= tdata_wrdata_r; + _T_874 <= tdata_wrdata_r; end else begin - _T_866 <= _T_853; + _T_874 <= _T_861; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_867 <= 10'h0; + _T_875 <= 10'h0; end else if (wr_mtdata1_t_r_3) begin - _T_867 <= tdata_wrdata_r; + _T_875 <= tdata_wrdata_r; end else begin - _T_867 <= _T_862; + _T_875 <= _T_870; end end always @(posedge rvclkhdr_22_io_l1clk or posedge reset) begin @@ -53578,7 +53582,7 @@ end // initial if (reset) begin mhpme3 <= 10'h0; end else if (wr_mhpme3_r) begin - if (_T_2284) begin + if (_T_2292) begin mhpme3 <= 10'h204; end else begin mhpme3 <= io_dec_csr_wrdata_r[9:0]; @@ -53589,7 +53593,7 @@ end // initial if (reset) begin mhpme4 <= 10'h0; end else if (wr_mhpme4_r) begin - if (_T_2284) begin + if (_T_2292) begin mhpme4 <= 10'h204; end else begin mhpme4 <= io_dec_csr_wrdata_r[9:0]; @@ -53600,7 +53604,7 @@ end // initial if (reset) begin mhpme5 <= 10'h0; end else if (wr_mhpme5_r) begin - if (_T_2284) begin + if (_T_2292) begin mhpme5 <= 10'h204; end else begin mhpme5 <= io_dec_csr_wrdata_r[9:0]; @@ -53611,7 +53615,7 @@ end // initial if (reset) begin mhpme6 <= 10'h0; end else if (wr_mhpme6_r) begin - if (_T_2284) begin + if (_T_2292) begin mhpme6 <= 10'h204; end else begin mhpme6 <= io_dec_csr_wrdata_r[9:0]; @@ -53622,28 +53626,28 @@ end // initial if (reset) begin mhpmc_inc_r_d1_0 <= 1'h0; end else begin - mhpmc_inc_r_d1_0 <= _T_1017 & _T_1297; + mhpmc_inc_r_d1_0 <= _T_1025 & _T_1305; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin mhpmc_inc_r_d1_1 <= 1'h0; end else begin - mhpmc_inc_r_d1_1 <= _T_1301 & _T_1581; + mhpmc_inc_r_d1_1 <= _T_1309 & _T_1589; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin mhpmc_inc_r_d1_2 <= 1'h0; end else begin - mhpmc_inc_r_d1_2 <= _T_1585 & _T_1865; + mhpmc_inc_r_d1_2 <= _T_1593 & _T_1873; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin mhpmc_inc_r_d1_3 <= 1'h0; end else begin - mhpmc_inc_r_d1_3 <= _T_1869 & _T_2149; + mhpmc_inc_r_d1_3 <= _T_1877 & _T_2157; end end always @(posedge io_free_clk or posedge reset) begin @@ -53727,30 +53731,30 @@ end // initial end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2322 <= 1'h0; + _T_2330 <= 1'h0; end else begin - _T_2322 <= io_i0_valid_wb; + _T_2330 <= io_i0_valid_wb; end end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2327 <= 1'h0; + _T_2335 <= 1'h0; end else begin - _T_2327 <= _T_2323 | _T_2325; + _T_2335 <= _T_2331 | _T_2333; end end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2328 <= 5'h0; + _T_2336 <= 5'h0; end else begin - _T_2328 <= io_exc_cause_wb; + _T_2336 <= io_exc_cause_wb; end end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2329 <= 1'h0; + _T_2337 <= 1'h0; end else begin - _T_2329 <= io_interrupt_valid_r_d1; + _T_2337 <= io_interrupt_valid_r_d1; end end endmodule diff --git a/src/main/resources/vsrc/beh_lib.sv b/src/main/resources/vsrc/beh_lib.sv new file mode 100644 index 00000000..ea8f8dea --- /dev/null +++ b/src/main/resources/vsrc/beh_lib.sv @@ -0,0 +1,506 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2020 Western Digital Corporation or it's affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// all flops call the rvdff flop + + +module rvdff #( parameter WIDTH=1, SHORT=0 ) + ( + input logic [WIDTH-1:0] din, + input logic clk, + input logic rst_l, + + output logic [WIDTH-1:0] dout + ); + +if (SHORT == 1) begin + assign dout = din; +end +else begin +`ifdef CLOCKGATE + always @(posedge tb_top.clk) begin + #0 $strobe("CG: %0t %m din %x dout %x clk %b width %d",$time,din,dout,clk,WIDTH); + end +`endif + + always_ff @(posedge clk or negedge rst_l) begin + if (rst_l == 0) + dout[WIDTH-1:0] <= 0; + else + dout[WIDTH-1:0] <= din[WIDTH-1:0]; + end + +end +endmodule + +// rvdff with 2:1 input mux to flop din iff sel==1 +module rvdffs #( parameter WIDTH=1, SHORT=0 ) + ( + input logic [WIDTH-1:0] din, + input logic en, + input logic clk, + input logic rst_l, + output logic [WIDTH-1:0] dout + ); + +if (SHORT == 1) begin : genblock + assign dout = din; +end +else begin : genblock + rvdff #(WIDTH) dffs (.din((en) ? din[WIDTH-1:0] : dout[WIDTH-1:0]), .*); +end + +endmodule + +// rvdff with en and clear +module rvdffsc #( parameter WIDTH=1, SHORT=0 ) + ( + input logic [WIDTH-1:0] din, + input logic en, + input logic clear, + input logic clk, + input logic rst_l, + output logic [WIDTH-1:0] dout + ); + + logic [WIDTH-1:0] din_new; +if (SHORT == 1) begin + assign dout = din; +end +else begin + assign din_new = {WIDTH{~clear}} & (en ? din[WIDTH-1:0] : dout[WIDTH-1:0]); + rvdff #(WIDTH) dffsc (.din(din_new[WIDTH-1:0]), .*); +end +endmodule + +module rvdffe #( parameter WIDTH=1, SHORT=0 ) + ( + input logic [WIDTH-1:0] din, + input logic en, + input logic clk, + input logic rst_l, + input logic scan_mode, + output logic [WIDTH-1:0] dout + ); + + logic l1clk; + +if (SHORT == 1) begin : genblock + if (1) begin : genblock + assign dout = din; + end +end +else begin : genblock + +`ifndef PHYSICAL + if (WIDTH >= 8) begin: genblock +`endif + +`ifdef RV_FPGA_OPTIMIZE + rvdffs #(WIDTH) dff ( .* ); +`else + rvclkhdr clkhdr ( .* ); + rvdff #(WIDTH) dff (.*, .clk(l1clk)); +`endif + +`ifndef PHYSICAL + end + else + $error(" rvdffe width must be >= 8"); +`endif +end // else: !if(SHORT == 1) + +endmodule // rvdffe + +module rvsyncss #(parameter WIDTH = 251) + ( + input logic clk, + input logic rst_l, + input logic [WIDTH-1:0] din, + output logic [WIDTH-1:0] dout + ); + + logic [WIDTH-1:0] din_ff1; + + rvdff #(WIDTH) sync_ff1 (.*, .din (din[WIDTH-1:0]), .dout(din_ff1[WIDTH-1:0])); + rvdff #(WIDTH) sync_ff2 (.*, .din (din_ff1[WIDTH-1:0]), .dout(dout[WIDTH-1:0])); + +endmodule // rvsyncss + +module rvlsadder + ( + input logic [31:0] rs1, + input logic [11:0] offset, + + output logic [31:0] dout + ); + + logic cout; + logic sign; + + logic [31:12] rs1_inc; + logic [31:12] rs1_dec; + + assign {cout,dout[11:0]} = {1'b0,rs1[11:0]} + {1'b0,offset[11:0]}; + + assign rs1_inc[31:12] = rs1[31:12] + 1; + + assign rs1_dec[31:12] = rs1[31:12] - 1; + + assign sign = offset[11]; + + assign dout[31:12] = ({20{ sign ^~ cout}} & rs1[31:12]) | + ({20{ ~sign & cout}} & rs1_inc[31:12]) | + ({20{ sign & ~cout}} & rs1_dec[31:12]); + +endmodule // rvlsadder + +// assume we only maintain pc[31:1] in the pipe + +module rvbradder + ( + input [31:1] pc, + input [12:1] offset, + + output [31:1] dout + ); + + logic cout; + logic sign; + + logic [31:13] pc_inc; + logic [31:13] pc_dec; + + assign {cout,dout[12:1]} = {1'b0,pc[12:1]} + {1'b0,offset[12:1]}; + + assign pc_inc[31:13] = pc[31:13] + 1; + + assign pc_dec[31:13] = pc[31:13] - 1; + + assign sign = offset[12]; + + + assign dout[31:13] = ({19{ sign ^~ cout}} & pc[31:13]) | + ({19{ ~sign & cout}} & pc_inc[31:13]) | + ({19{ sign & ~cout}} & pc_dec[31:13]); + + +endmodule // rvbradder + + +// 2s complement circuit +module rvtwoscomp #( parameter WIDTH=32 ) + ( + input logic [WIDTH-1:0] din, + + output logic [WIDTH-1:0] dout + ); + + logic [WIDTH-1:1] dout_temp; // holding for all other bits except for the lsb. LSB is always din + + genvar i; + + for ( i = 1; i < WIDTH; i++ ) begin : flip_after_first_one + assign dout_temp[i] = (|din[i-1:0]) ? ~din[i] : din[i]; + end : flip_after_first_one + + assign dout[WIDTH-1:0] = { dout_temp[WIDTH-1:1], din[0] }; + +endmodule // 2'scomp + +// find first +module rvfindfirst1 #( parameter WIDTH=32, SHIFT=$clog2(WIDTH) ) + ( + input logic [WIDTH-1:0] din, + + output logic [SHIFT-1:0] dout + ); + logic done; + + always_comb begin + dout[SHIFT-1:0] = {SHIFT{1'b0}}; + done = 1'b0; + + for ( int i = WIDTH-1; i > 0; i-- ) begin : find_first_one + done |= din[i]; + dout[SHIFT-1:0] += done ? 1'b0 : 1'b1; + end : find_first_one + end +endmodule // rvfindfirst1 + +module rvfindfirst1hot #( parameter WIDTH=32 ) + ( + input logic [WIDTH-1:0] din, + + output logic [WIDTH-1:0] dout + ); + logic done; + + always_comb begin + dout[WIDTH-1:0] = {WIDTH{1'b0}}; + done = 1'b0; + for ( int i = 0; i < WIDTH; i++ ) begin : find_first_one + dout[i] = ~done & din[i]; + done |= din[i]; + end : find_first_one + end +endmodule // rvfindfirst1hot + +// mask and match function matches bits after finding the first 0 position +// find first starting from LSB. Skip that location and match the rest of the bits +module rvmaskandmatch #( parameter WIDTH=32 ) + ( + input logic [WIDTH-1:0] mask, // this will have the mask in the lower bit positions + input logic [WIDTH-1:0] data, // this is what needs to be matched on the upper bits with the mask's upper bits + input logic masken, // when 1 : do mask. 0 : full match + output logic match + ); + + logic [WIDTH-1:0] matchvec; + logic masken_or_fullmask; + + assign masken_or_fullmask = masken & ~(&mask[WIDTH-1:0]); + + assign matchvec[0] = masken_or_fullmask | (mask[0] == data[0]); + genvar i; + + for ( i = 1; i < WIDTH; i++ ) begin : match_after_first_zero + assign matchvec[i] = (&mask[i-1:0] & masken_or_fullmask) ? 1'b1 : (mask[i] == data[i]); + end : match_after_first_zero + + assign match = &matchvec[WIDTH-1:0]; // all bits either matched or were masked off + +endmodule // rvmaskandmatch + + + + +// Check if the S_ADDR <= addr < E_ADDR +module rvrangecheck #(CCM_SADR = 32'h0, + CCM_SIZE = 128) ( + input logic [31:0] addr, // Address to be checked for range + output logic in_range, // S_ADDR <= start_addr < E_ADDR + output logic in_region +); + + localparam REGION_BITS = 4; + localparam MASK_BITS = 10 + $clog2(CCM_SIZE); + + logic [31:0] start_addr; + logic [3:0] region; + + assign start_addr[31:0] = CCM_SADR; + assign region[REGION_BITS-1:0] = start_addr[31:(32-REGION_BITS)]; + + assign in_region = (addr[31:(32-REGION_BITS)] == region[REGION_BITS-1:0]); + if (CCM_SIZE == 48) + assign in_range = (addr[31:MASK_BITS] == start_addr[31:MASK_BITS]) & ~(&addr[MASK_BITS-1 : MASK_BITS-2]); + else + assign in_range = (addr[31:MASK_BITS] == start_addr[31:MASK_BITS]); + +endmodule // rvrangechecker + +// 16 bit even parity generator +module rveven_paritygen #(WIDTH = 16) ( + input logic [WIDTH-1:0] data_in, // Data + output logic parity_out // generated even parity + ); + + assign parity_out = ^(data_in[WIDTH-1:0]) ; + +endmodule // rveven_paritygen + +module rveven_paritycheck #(WIDTH = 16) ( + input logic [WIDTH-1:0] data_in, // Data + input logic parity_in, + output logic parity_err // Parity error + ); + + assign parity_err = ^(data_in[WIDTH-1:0]) ^ parity_in ; + +endmodule // rveven_paritycheck + +module rvecc_encode ( + input [31:0] din, + output [6:0] ecc_out + ); +logic [5:0] ecc_out_temp; + + assign ecc_out_temp[0] = din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]; + assign ecc_out_temp[1] = din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31]; + assign ecc_out_temp[2] = din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31]; + assign ecc_out_temp[3] = din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]; + assign ecc_out_temp[4] = din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]; + assign ecc_out_temp[5] = din[26]^din[27]^din[28]^din[29]^din[30]^din[31]; + + assign ecc_out[6:0] = {(^din[31:0])^(^ecc_out_temp[5:0]),ecc_out_temp[5:0]}; + +endmodule // rvecc_encode + +module rvecc_decode ( + input en, + input [31:0] din, + input [6:0] ecc_in, + input sed_ded, // only do detection and no correction. Used for the I$ + output [31:0] dout, + output [6:0] ecc_out, + output single_ecc_error, + output double_ecc_error + + ); + + logic [6:0] ecc_check; + logic [38:0] error_mask; + logic [38:0] din_plus_parity, dout_plus_parity; + + // Generate the ecc bits + assign ecc_check[0] = ecc_in[0]^din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]; + assign ecc_check[1] = ecc_in[1]^din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31]; + assign ecc_check[2] = ecc_in[2]^din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31]; + assign ecc_check[3] = ecc_in[3]^din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]; + assign ecc_check[4] = ecc_in[4]^din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]; + assign ecc_check[5] = ecc_in[5]^din[26]^din[27]^din[28]^din[29]^din[30]^din[31]; + + // This is the parity bit + assign ecc_check[6] = ((^din[31:0])^(^ecc_in[6:0])) & ~sed_ded; + + assign single_ecc_error = en & (ecc_check[6:0] != 0) & ecc_check[6]; // this will never be on for sed_ded + assign double_ecc_error = en & (ecc_check[6:0] != 0) & ~ecc_check[6]; // all errors in the sed_ded case will be recorded as DE + + // Generate the mask for error correctiong + for (genvar i=1; i<40; i++) begin + assign error_mask[i-1] = (ecc_check[5:0] == i); + end + + // Generate the corrected data + assign din_plus_parity[38:0] = {ecc_in[6], din[31:26], ecc_in[5], din[25:11], ecc_in[4], din[10:4], ecc_in[3], din[3:1], ecc_in[2], din[0], ecc_in[1:0]}; + + assign dout_plus_parity[38:0] = single_ecc_error ? (error_mask[38:0] ^ din_plus_parity[38:0]) : din_plus_parity[38:0]; + assign dout[31:0] = {dout_plus_parity[37:32], dout_plus_parity[30:16], dout_plus_parity[14:8], dout_plus_parity[6:4], dout_plus_parity[2]}; + assign ecc_out[6:0] = {(dout_plus_parity[38] ^ (ecc_check[6:0] == 7'b1000000)), dout_plus_parity[31], dout_plus_parity[15], dout_plus_parity[7], dout_plus_parity[3], dout_plus_parity[1:0]}; + +endmodule // rvecc_decode + +module rvecc_encode_64 ( + input [63:0] din, + output [6:0] ecc_out + ); + assign ecc_out[0] = din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]^din[32]^din[34]^din[36]^din[38]^din[40]^din[42]^din[44]^din[46]^din[48]^din[50]^din[52]^din[54]^din[56]^din[57]^din[59]^din[61]^din[63]; + + assign ecc_out[1] = din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31]^din[32]^din[35]^din[36]^din[39]^din[40]^din[43]^din[44]^din[47]^din[48]^din[51]^din[52]^din[55]^din[56]^din[58]^din[59]^din[62]^din[63]; + + assign ecc_out[2] = din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31]^din[32]^din[37]^din[38]^din[39]^din[40]^din[45]^din[46]^din[47]^din[48]^din[53]^din[54]^din[55]^din[56]^din[60]^din[61]^din[62]^din[63]; + + assign ecc_out[3] = din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56]; + + assign ecc_out[4] = din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56]; + + assign ecc_out[5] = din[26]^din[27]^din[28]^din[29]^din[30]^din[31]^din[32]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56]; + + assign ecc_out[6] = din[57]^din[58]^din[59]^din[60]^din[61]^din[62]^din[63]; + +endmodule // rvecc_encode_64 + + +module rvecc_decode_64 ( + input en, + input [63:0] din, + input [6:0] ecc_in, + output ecc_error + ); + + logic [6:0] ecc_check; + + // Generate the ecc bits + assign ecc_check[0] = ecc_in[0]^din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]^din[32]^din[34]^din[36]^din[38]^din[40]^din[42]^din[44]^din[46]^din[48]^din[50]^din[52]^din[54]^din[56]^din[57]^din[59]^din[61]^din[63]; + + assign ecc_check[1] = ecc_in[1]^din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31]^din[32]^din[35]^din[36]^din[39]^din[40]^din[43]^din[44]^din[47]^din[48]^din[51]^din[52]^din[55]^din[56]^din[58]^din[59]^din[62]^din[63]; + + assign ecc_check[2] = ecc_in[2]^din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31]^din[32]^din[37]^din[38]^din[39]^din[40]^din[45]^din[46]^din[47]^din[48]^din[53]^din[54]^din[55]^din[56]^din[60]^din[61]^din[62]^din[63]; + + assign ecc_check[3] = ecc_in[3]^din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56]; + + assign ecc_check[4] = ecc_in[4]^din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56]; + + assign ecc_check[5] = ecc_in[5]^din[26]^din[27]^din[28]^din[29]^din[30]^din[31]^din[32]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56]; + + assign ecc_check[6] = ecc_in[6]^din[57]^din[58]^din[59]^din[60]^din[61]^din[62]^din[63]; + + assign ecc_error = en & (ecc_check[6:0] != 0); // all errors in the sed_ded case will be recorded as DE + + endmodule // rvecc_decode_64 + + +module gated_flop + ( + input logic SE, EN, CK, + output Q + ); + + logic en_ff; + logic enable; + + assign enable = EN | SE; + +`ifdef VERILATOR + always @(negedge CK) begin + en_ff <= enable; + end +`else + always @(CK, enable) begin + if(!CK) + en_ff = enable; + end +`endif + assign Q = CK & en_ff; + +endmodule + +module rvclkhdr + ( + input logic en, + input logic clk, + input logic scan_mode, + output logic l1clk + ); + + logic SE; + assign SE = scan_mode; + + gated_flop clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk)); + +endmodule // rvclkhdr + +module rvoclkhdr + ( + input logic en, + input logic clk, + input logic scan_mode, + output logic l1clk + ); + + logic SE; + assign SE = scan_mode; + +`ifdef RV_FPGA_OPTIMIZE + assign l1clk = clk; +`else + gated_flop clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk)); +`endif + +endmodule + + + diff --git a/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv b/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv index e69de29b..562f815e 100644 --- a/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv +++ b/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2018 Western Digital Corporation or it's affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//------------------------------------------------------------------------------------ +// +// Copyright Western Digital, 2019 +// Owner : Alex Grobman +// Description: +// This module Synchronizes the signals between JTAG (TCK) and +// processor (Core_clk) +// +//------------------------------------------------------------------------------------- + +module dmi_jtag_to_core_sync ( +// JTAG signals +input rd_en, // 1 bit Read Enable from JTAG +input wr_en, // 1 bit Write enable from JTAG + +// Processor Signals +input rst_n, // Core reset +input clk, // Core clock + +output reg_en, // 1 bit Write interface bit to Processor +output reg_wr_en // 1 bit Write enable to Processor +); + +wire c_rd_en; +wire c_wr_en; +reg [2:0] rden, wren; + + +// Outputs +assign reg_en = c_wr_en | c_rd_en; +assign reg_wr_en = c_wr_en; + + +// synchronizers +always @ ( posedge clk or negedge rst_n) begin + if(!rst_n) begin + rden <= '0; + wren <= '0; + end + else begin + rden <= {rden[1:0], rd_en}; + wren <= {wren[1:0], wr_en}; + end +end + +assign c_rd_en = rden[1] & ~rden[2]; +assign c_wr_en = wren[1] & ~wren[2]; + + +endmodule diff --git a/src/main/resources/vsrc/dmi_wrapper.sv b/src/main/resources/vsrc/dmi_wrapper.sv index e69de29b..d9fd7410 100644 --- a/src/main/resources/vsrc/dmi_wrapper.sv +++ b/src/main/resources/vsrc/dmi_wrapper.sv @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2018 Western Digital Corporation or it's affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//------------------------------------------------------------------------------------ +// +// Copyright Western Digital, 2018 +// Owner : Anusha Narayanamoorthy +// Description: +// Wrapper module for JTAG_TAP and DMI synchronizer +// +//------------------------------------------------------------------------------------- + +module dmi_wrapper( + + // JTAG signals + input trst_n, // JTAG reset + input tck, // JTAG clock + input tms, // Test mode select + input tdi, // Test Data Input + output tdo, // Test Data Output + output tdoEnable, // Test Data Output enable + + // Processor Signals + input core_rst_n, // Core reset + input core_clk, // Core clock + input [31:1] jtag_id, // JTAG ID + input [31:0] rd_data, // 32 bit Read data from Processor + output [31:0] reg_wr_data, // 32 bit Write data to Processor + output [6:0] reg_wr_addr, // 7 bit reg address to Processor + output reg_en, // 1 bit Read enable to Processor + output reg_wr_en, // 1 bit Write enable to Processor + output dmi_hard_reset +); + + + + + + //Wire Declaration + wire rd_en; + wire wr_en; + wire dmireset; + + + //jtag_tap instantiation + rvjtag_tap i_jtag_tap( + .trst(trst_n), // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset + .tck(tck), // dedicated JTAG TCK pad signal + .tms(tms), // dedicated JTAG TMS pad signal + .tdi(tdi), // dedicated JTAG TDI pad signal + .tdo(tdo), // dedicated JTAG TDO pad signal + .tdoEnable(tdoEnable), // enable for TDO pad + .wr_data(reg_wr_data), // 32 bit Write data + .wr_addr(reg_wr_addr), // 7 bit Write address + .rd_en(rd_en), // 1 bit read enable + .wr_en(wr_en), // 1 bit Write enable + .rd_data(rd_data), // 32 bit Read data + .rd_status(2'b0), + .idle(3'h0), // no need to wait to sample data + .dmi_stat(2'b0), // no need to wait or error possible + .version(4'h1), // debug spec 0.13 compliant + .jtag_id(jtag_id), + .dmi_hard_reset(dmi_hard_reset), + .dmi_reset(dmireset) +); + + + // dmi_jtag_to_core_sync instantiation + dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync( + .wr_en(wr_en), // 1 bit Write enable + .rd_en(rd_en), // 1 bit Read enable + + .rst_n(core_rst_n), + .clk(core_clk), + .reg_en(reg_en), // 1 bit Write interface bit + .reg_wr_en(reg_wr_en) // 1 bit Write enable + ); + +endmodule diff --git a/target/scala-2.12/classes/vsrc/gated_latch.v b/src/main/resources/vsrc/gated_latch.sv similarity index 74% rename from target/scala-2.12/classes/vsrc/gated_latch.v rename to src/main/resources/vsrc/gated_latch.sv index 36570337..51b96c9d 100644 --- a/target/scala-2.12/classes/vsrc/gated_latch.v +++ b/src/main/resources/vsrc/gated_latch.sv @@ -1,10 +1,10 @@ module gated_latch ( - input wire SE, EN, CK, + input logic SE, EN, CK, output Q ); - reg en_ff; - wire enable; + logic en_ff; + logic enable; assign enable = EN | SE; always @(CK, enable) begin if(!CK) diff --git a/src/main/resources/vsrc/ifu_ic_mem.sv b/src/main/resources/vsrc/ifu_ic_mem.sv index 0875c8ef..269925a6 100644 --- a/src/main/resources/vsrc/ifu_ic_mem.sv +++ b/src/main/resources/vsrc/ifu_ic_mem.sv @@ -23,7 +23,7 @@ module ifu_ic_mem parameter ICACHE_NUM_WAYS, parameter ICACHE_BANK_BITS, parameter ICACHE_BEAT_ADDR_HI, - parameter ICACHE_BANKS_WAY, + parameter ICACHE_BANKS_WAY=2, parameter ICACHE_INDEX_HI, parameter ICACHE_BANK_HI, parameter ICACHE_BANK_LO, @@ -67,7 +67,7 @@ module ifu_ic_mem ) ; - IC_TAG #( + EL2_IC_TAG #( .ICACHE_BEAT_BITS(ICACHE_BEAT_BITS), .ICACHE_NUM_WAYS(ICACHE_NUM_WAYS), .ICACHE_BANK_BITS(ICACHE_BANK_BITS), @@ -90,7 +90,7 @@ module ifu_ic_mem .ic_rw_addr (ic_rw_addr[31:3]) ) ; - IC_DATA #( + EL2_IC_DATA #( .ICACHE_BEAT_BITS(ICACHE_BEAT_BITS), .ICACHE_NUM_WAYS(ICACHE_NUM_WAYS), .ICACHE_BANK_BITS(ICACHE_BANK_BITS), @@ -119,7 +119,7 @@ module ifu_ic_mem ///////////////////////////////////////////////// ////// ICACHE DATA MODULE //////////////////// ///////////////////////////////////////////////// -module IC_DATA +module EL2_IC_DATA #( parameter ICACHE_BEAT_BITS, parameter ICACHE_NUM_WAYS, @@ -990,7 +990,7 @@ endmodule // EL2_IC_DATA ///////////////////////////////////////////////// ////// ICACHE TAG MODULE //////////////////// ///////////////////////////////////////////////// -module IC_TAG +module EL2_IC_TAG #( parameter ICACHE_BEAT_BITS, parameter ICACHE_NUM_WAYS, @@ -1025,7 +1025,7 @@ module IC_TAG input logic ic_debug_tag_array, // Debug tag array input logic [ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr. - output logic [25:0] ictag_debug_rd_data, + output logic [25:0] ic_tag_debug_rd_data, input logic [70:0] ic_debug_wr_data, // Debug wr cache. output logic [ICACHE_NUM_WAYS-1:0] ic_rd_hit, diff --git a/src/main/resources/vsrc/lsu_dccm_mem.sv b/src/main/resources/vsrc/lsu_dccm_mem.sv index 1608a603..85c81c49 100644 --- a/src/main/resources/vsrc/lsu_dccm_mem.sv +++ b/src/main/resources/vsrc/lsu_dccm_mem.sv @@ -27,7 +27,7 @@ // //******************************************************************************** -module el2_lsu_dccm_mem +module lsu_dccm_mem #( parameter DCCM_BYTE_WIDTH, parameter DCCM_BITS, diff --git a/src/main/resources/vsrc/mem.sv b/src/main/resources/vsrc/mem.sv index 56e9fe57..0aee1897 100644 --- a/src/main/resources/vsrc/mem.sv +++ b/src/main/resources/vsrc/mem.sv @@ -15,14 +15,14 @@ module mem #( parameter DCCM_NUM_BANKS, parameter ICACHE_BANK_HI, parameter ICACHE_BANK_LO, - parameter DCCM_ENABLE, + parameter DCCM_ENABLE= 'b1, parameter ICACHE_TAG_LO, parameter ICACHE_DATA_INDEX_LO, parameter ICCM_NUM_BANKS, parameter ICACHE_ECC, - parameter ICACHE_ENABLE, + parameter ICACHE_ENABLE= 'b1, parameter DCCM_BANK_BITS, - parameter ICCM_ENABLE, + parameter ICCM_ENABLE= 'b1, parameter ICCM_BANK_BITS, parameter ICACHE_TAG_DEPTH, parameter ICACHE_WAYPACK, @@ -77,8 +77,9 @@ module mem #( input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache. input logic ic_sel_premux_data, // Premux data sel - input logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC - input logic [70:0] ic_debug_wr_data, // Debug wr cache. + input logic [70:0] ic_wr_data_0, // Data to fill to the Icache. With ECC + input logic [70:0] ic_wr_data_1, + input logic [70:0] ic_debug_wr_data, // Debug wr cache. output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC input logic [ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache. input logic ic_debug_rd_en, // Icache debug rd @@ -100,6 +101,9 @@ module mem #( ); + logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data; +assign ic_wr_data [0] = ic_wr_data_0; +assign ic_wr_data [1] = ic_wr_data_1; // DCCM Instantiation if (DCCM_ENABLE == 1) begin: Gen_dccm_enable lsu_dccm_mem #( @@ -142,7 +146,7 @@ else begin assign ic_rd_hit[ICACHE_NUM_WAYS-1:0] = '0; assign ic_tag_perr = '0 ; assign ic_rd_data = '0 ; - assign ic_stag_debug_rd_data = '0 ; + assign ic_tag_debug_rd_data = '0 ; end // else: !if( ICACHE_ENABLE ) diff --git a/src/main/resources/vsrc/mem_lib.sv b/src/main/resources/vsrc/mem_lib.sv new file mode 100644 index 00000000..e741c618 --- /dev/null +++ b/src/main/resources/vsrc/mem_lib.sv @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2020 Western Digital Corporation or it's affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`define EL2_LOCAL_RAM_TEST_IO \ +input logic WE, \ +input logic ME, \ +input logic CLK + +`define EL2_RAM(depth, width) \ +module ram_``depth``x``width( \ + input logic [$clog2(depth)-1:0] ADR, \ + input logic [(width-1):0] D, \ + output logic [(width-1):0] Q, \ + `EL2_LOCAL_RAM_TEST_IO \ +); \ +reg [(width-1):0] ram_core [(depth-1):0]; \ + \ +always @(posedge CLK) begin \ + if (ME && WE) ram_core[ADR] = D; \ + if (ME && ~WE) Q <= ram_core[ADR]; \ +end \ + \ +endmodule + +`define EL2_RAM_BE(depth, width) \ +module ram_be_``depth``x``width( \ + input logic [$clog2(depth)-1:0] ADR, \ + input logic [(width-1):0] D, WEM, \ + output logic [(width-1):0] Q, \ + `EL2_LOCAL_RAM_TEST_IO \ +); \ +reg [(width-1):0] ram_core [(depth-1):0]; \ + \ +always @(posedge CLK) begin \ + if (ME && WE) ram_core[ADR] = D & WEM | ~WEM & ram_core[ADR];\ + if (ME && ~WE) Q <= ram_core[ADR]; \ +end \ + \ + \ +endmodule + +// parameterizable RAM for verilator sims +module el2_ram #(depth=4096, width=39) ( +input logic [$clog2(depth)-1:0] ADR, +input logic [(width-1):0] D, +output logic [(width-1):0] Q, + `EL2_LOCAL_RAM_TEST_IO +); +reg [(width-1):0] ram_core [(depth-1):0]; + +always @(posedge CLK) begin + if (ME && WE) ram_core[ADR] = D; + if (ME && ~WE) Q <= ram_core[ADR]; +end +endmodule + +//========================================================================================================================= +//=================================== START OF CCM ======================================================================= +//============= Possible sram sizes for a 39 bit wide memory ( 4 bytes + 7 bits ECC ) ===================================== +//------------------------------------------------------------------------------------------------------------------------- +`EL2_RAM(32768, 39) +`EL2_RAM(16384, 39) +`EL2_RAM(8192, 39) +`EL2_RAM(4096, 39) +`EL2_RAM(3072, 39) +`EL2_RAM(2048, 39) +`EL2_RAM(1536, 39) // need this for the 48KB DCCM option) +`EL2_RAM(1024, 39) +`EL2_RAM(768, 39) +`EL2_RAM(512, 39) +`EL2_RAM(256, 39) +`EL2_RAM(128, 39) +`EL2_RAM(1024, 20) +`EL2_RAM(512, 20) +`EL2_RAM(256, 20) +`EL2_RAM(128, 20) +`EL2_RAM(64, 20) +`EL2_RAM(4096, 34) +`EL2_RAM(2048, 34) +`EL2_RAM(1024, 34) +`EL2_RAM(512, 34) +`EL2_RAM(256, 34) +`EL2_RAM(128, 34) +`EL2_RAM(64, 34) +`EL2_RAM(8192, 68) +`EL2_RAM(4096, 68) +`EL2_RAM(2048, 68) +`EL2_RAM(1024, 68) +`EL2_RAM(512, 68) +`EL2_RAM(256, 68) +`EL2_RAM(128, 68) +`EL2_RAM(64, 68) +`EL2_RAM(8192, 71) +`EL2_RAM(4096, 71) +`EL2_RAM(2048, 71) +`EL2_RAM(1024, 71) +`EL2_RAM(512, 71) +`EL2_RAM(256, 71) +`EL2_RAM(128, 71) +`EL2_RAM(64, 71) +`EL2_RAM(4096, 42) +`EL2_RAM(2048, 42) +`EL2_RAM(1024, 42) +`EL2_RAM(512, 42) +`EL2_RAM(256, 42) +`EL2_RAM(128, 42) +`EL2_RAM(64, 42) +`EL2_RAM(4096, 22) +`EL2_RAM(2048, 22) +`EL2_RAM(1024, 22) +`EL2_RAM(512, 22) +`EL2_RAM(256, 22) +`EL2_RAM(128, 22) +`EL2_RAM(64, 22) +`EL2_RAM(1024, 26) +`EL2_RAM(4096, 26) +`EL2_RAM(2048, 26) +`EL2_RAM(512, 26) +`EL2_RAM(256, 26) +`EL2_RAM(128, 26) +`EL2_RAM(64, 26) +`EL2_RAM(32, 26) +`EL2_RAM(32, 22) +`EL2_RAM_BE(8192, 142) +`EL2_RAM_BE(4096, 142) +`EL2_RAM_BE(2048, 142) +`EL2_RAM_BE(1024, 142) +`EL2_RAM_BE(512, 142) +`EL2_RAM_BE(256, 142) +`EL2_RAM_BE(128, 142) +`EL2_RAM_BE(64, 142) +`EL2_RAM_BE(8192, 284) +`EL2_RAM_BE(4096, 284) +`EL2_RAM_BE(2048, 284) +`EL2_RAM_BE(1024, 284) +`EL2_RAM_BE(512, 284) +`EL2_RAM_BE(256, 284) +`EL2_RAM_BE(128, 284) +`EL2_RAM_BE(64, 284) +`EL2_RAM_BE(8192, 136) +`EL2_RAM_BE(4096, 136) +`EL2_RAM_BE(2048, 136) +`EL2_RAM_BE(1024, 136) +`EL2_RAM_BE(512, 136) +`EL2_RAM_BE(256, 136) +`EL2_RAM_BE(128, 136) +`EL2_RAM_BE(64, 136) +`EL2_RAM_BE(8192, 272) +`EL2_RAM_BE(4096, 272) +`EL2_RAM_BE(2048, 272) +`EL2_RAM_BE(1024, 272) +`EL2_RAM_BE(512, 272) +`EL2_RAM_BE(256, 272) +`EL2_RAM_BE(128, 272) +`EL2_RAM_BE(64, 272) +`EL2_RAM_BE(4096, 52) +`EL2_RAM_BE(2048, 52) +`EL2_RAM_BE(1024, 52) +`EL2_RAM_BE(512, 52) +`EL2_RAM_BE(256, 52) +`EL2_RAM_BE(128, 52) +`EL2_RAM_BE(64, 52) +`EL2_RAM_BE(4096, 104) +`EL2_RAM_BE(2048, 104) +`EL2_RAM_BE(1024, 104) +`EL2_RAM_BE(512, 104) +`EL2_RAM_BE(256, 104) +`EL2_RAM_BE(128, 104) +`EL2_RAM_BE(64, 104) +`EL2_RAM_BE(4096, 44) +`EL2_RAM_BE(2048, 44) +`EL2_RAM_BE(1024, 44) +`EL2_RAM_BE(512, 44) +`EL2_RAM_BE(256, 44) +`EL2_RAM_BE(128, 44) +`EL2_RAM_BE(64, 44) +`EL2_RAM_BE(4096, 88) +`EL2_RAM_BE(2048, 88) +`EL2_RAM_BE(1024, 88) +`EL2_RAM_BE(512, 88) +`EL2_RAM_BE(256, 88) +`EL2_RAM_BE(128, 88) +`EL2_RAM_BE(64, 88) + + +`undef EL2_RAM +`undef EL2_RAM_BE +`undef EL2_LOCAL_RAM_TEST_IO + + diff --git a/src/main/resources/vsrc/mem_mod.sv b/src/main/resources/vsrc/mem_mod.sv new file mode 100644 index 00000000..e78f5cec --- /dev/null +++ b/src/main/resources/vsrc/mem_mod.sv @@ -0,0 +1,64 @@ +module el2_btb_tag_hash #( +`include "param.vh" + ) ( + input logic [pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1] pc, + output logic [pt.BTB_BTAG_SIZE-1:0] hash + ); + + assign hash = {(pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+1] ^ + pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+1] ^ + pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1])}; +endmodule + +module el2_btb_tag_hash_fold #( +`include "param.vh" + )( + input logic [pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1] pc, + output logic [pt.BTB_BTAG_SIZE-1:0] hash + ); + + assign hash = {( + pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+1] ^ + pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1])}; + +endmodule + +module el2_btb_addr_hash #( +`include "param.vh" + )( + input logic [pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO] pc, + output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hash + ); + + +if(pt.BTB_FOLD2_INDEX_HASH) begin : fold2 + assign hash[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = pc[pt.BTB_INDEX1_HI:pt.BTB_INDEX1_LO] ^ + pc[pt.BTB_INDEX3_HI:pt.BTB_INDEX3_LO]; +end + else begin + assign hash[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = pc[pt.BTB_INDEX1_HI:pt.BTB_INDEX1_LO] ^ + pc[pt.BTB_INDEX2_HI:pt.BTB_INDEX2_LO] ^ + pc[pt.BTB_INDEX3_HI:pt.BTB_INDEX3_LO]; +end + +endmodule + +module el2_btb_ghr_hash #( +`include "param.vh" + )( + input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hashin, + input logic [pt.BHT_GHR_SIZE-1:0] ghr, + output logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] hash + ); + + // The hash function is too complex to write in verilog for all cases. + // The config script generates the logic string based on the bp config. + if(pt.BHT_GHR_HASH_1) begin : ghrhash_cfg1 + assign hash[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] = { ghr[pt.BHT_GHR_SIZE-1:pt.BTB_INDEX1_HI-1], hashin[pt.BTB_INDEX1_HI:2]^ghr[pt.BTB_INDEX1_HI-2:0]}; + end + else begin : ghrhash_cfg2 + assign hash[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] = { hashin[pt.BHT_GHR_SIZE+1:2]^ghr[pt.BHT_GHR_SIZE-1:0]}; + end + + +endmodule diff --git a/src/main/resources/vsrc/rvjtag_tap.sv b/src/main/resources/vsrc/rvjtag_tap.sv new file mode 100644 index 00000000..24634344 --- /dev/null +++ b/src/main/resources/vsrc/rvjtag_tap.sv @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2019 Western Digital Corporation or it's affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License + +module rvjtag_tap #( +parameter AWIDTH = 7 +) +( +input trst, +input tck, +input tms, +input tdi, +output reg tdo, +output tdoEnable, + +output [31:0] wr_data, +output [AWIDTH-1:0] wr_addr, +output wr_en, +output rd_en, + +input [31:0] rd_data, +input [1:0] rd_status, + +output reg dmi_reset, +output reg dmi_hard_reset, + +input [2:0] idle, +input [1:0] dmi_stat, +/* +-- revisionCode : 4'h0; +-- manufacturersIdCode : 11'h45; +-- deviceIdCode : 16'h0001; +-- order MSB .. LSB -> [4 bit version or revision] [16 bit part number] [11 bit manufacturer id] [value of 1'b1 in LSB] +*/ +input [31:1] jtag_id, +input [3:0] version +); + +localparam USER_DR_LENGTH = AWIDTH + 34; + + +reg [USER_DR_LENGTH-1:0] sr, nsr, dr; + +/////////////////////////////////////////////////////// +// Tap controller +/////////////////////////////////////////////////////// +logic[3:0] state, nstate; +logic [4:0] ir; +wire jtag_reset; +wire shift_dr; +wire pause_dr; +wire update_dr; +wire capture_dr; +wire shift_ir; +wire pause_ir ; +wire update_ir ; +wire capture_ir; +wire[1:0] dr_en; +wire devid_sel; +wire [5:0] abits; + +assign abits = AWIDTH[5:0]; + + +localparam TEST_LOGIC_RESET_STATE = 0; +localparam RUN_TEST_IDLE_STATE = 1; +localparam SELECT_DR_SCAN_STATE = 2; +localparam CAPTURE_DR_STATE = 3; +localparam SHIFT_DR_STATE = 4; +localparam EXIT1_DR_STATE = 5; +localparam PAUSE_DR_STATE = 6; +localparam EXIT2_DR_STATE = 7; +localparam UPDATE_DR_STATE = 8; +localparam SELECT_IR_SCAN_STATE = 9; +localparam CAPTURE_IR_STATE = 10; +localparam SHIFT_IR_STATE = 11; +localparam EXIT1_IR_STATE = 12; +localparam PAUSE_IR_STATE = 13; +localparam EXIT2_IR_STATE = 14; +localparam UPDATE_IR_STATE = 15; + +always_comb begin + nstate = state; + case(state) + TEST_LOGIC_RESET_STATE: nstate = tms ? TEST_LOGIC_RESET_STATE : RUN_TEST_IDLE_STATE; + RUN_TEST_IDLE_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE; + SELECT_DR_SCAN_STATE: nstate = tms ? SELECT_IR_SCAN_STATE : CAPTURE_DR_STATE; + CAPTURE_DR_STATE: nstate = tms ? EXIT1_DR_STATE : SHIFT_DR_STATE; + SHIFT_DR_STATE: nstate = tms ? EXIT1_DR_STATE : SHIFT_DR_STATE; + EXIT1_DR_STATE: nstate = tms ? UPDATE_DR_STATE : PAUSE_DR_STATE; + PAUSE_DR_STATE: nstate = tms ? EXIT2_DR_STATE : PAUSE_DR_STATE; + EXIT2_DR_STATE: nstate = tms ? UPDATE_DR_STATE : SHIFT_DR_STATE; + UPDATE_DR_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE; + SELECT_IR_SCAN_STATE: nstate = tms ? TEST_LOGIC_RESET_STATE : CAPTURE_IR_STATE; + CAPTURE_IR_STATE: nstate = tms ? EXIT1_IR_STATE : SHIFT_IR_STATE; + SHIFT_IR_STATE: nstate = tms ? EXIT1_IR_STATE : SHIFT_IR_STATE; + EXIT1_IR_STATE: nstate = tms ? UPDATE_IR_STATE : PAUSE_IR_STATE; + PAUSE_IR_STATE: nstate = tms ? EXIT2_IR_STATE : PAUSE_IR_STATE; + EXIT2_IR_STATE: nstate = tms ? UPDATE_IR_STATE : SHIFT_IR_STATE; + UPDATE_IR_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE; + default: nstate = TEST_LOGIC_RESET_STATE; + endcase +end + +always @ (posedge tck or negedge trst) begin + if(!trst) state <= TEST_LOGIC_RESET_STATE; + else state <= nstate; +end + +assign jtag_reset = state == TEST_LOGIC_RESET_STATE; +assign shift_dr = state == SHIFT_DR_STATE; +assign pause_dr = state == PAUSE_DR_STATE; +assign update_dr = state == UPDATE_DR_STATE; +assign capture_dr = state == CAPTURE_DR_STATE; +assign shift_ir = state == SHIFT_IR_STATE; +assign pause_ir = state == PAUSE_IR_STATE; +assign update_ir = state == UPDATE_IR_STATE; +assign capture_ir = state == CAPTURE_IR_STATE; + +assign tdoEnable = shift_dr | shift_ir; + +/////////////////////////////////////////////////////// +// IR register +/////////////////////////////////////////////////////// + +always @ (negedge tck or negedge trst) begin + if (!trst) ir <= 5'b1; + else begin + if (jtag_reset) ir <= 5'b1; + else if (update_ir) ir <= (sr[4:0] == '0) ? 5'h1f :sr[4:0]; + end +end + + +assign devid_sel = ir == 5'b00001; +assign dr_en[0] = ir == 5'b10000; +assign dr_en[1] = ir == 5'b10001; + +/////////////////////////////////////////////////////// +// Shift register +/////////////////////////////////////////////////////// +always @ (posedge tck or negedge trst) begin + if(!trst)begin + sr <= '0; + end + else begin + sr <= nsr; + end +end + +// SR next value +always_comb begin + nsr = sr; + case(1) + shift_dr: begin + case(1) + dr_en[1]: nsr = {tdi, sr[USER_DR_LENGTH-1:1]}; + + dr_en[0], + devid_sel: nsr = {{USER_DR_LENGTH-32{1'b0}},tdi, sr[31:1]}; + default: nsr = {{USER_DR_LENGTH-1{1'b0}},tdi}; // bypass + endcase + end + capture_dr: begin + case(1) + dr_en[0]: nsr = {{USER_DR_LENGTH-15{1'b0}}, idle, dmi_stat, abits, version}; + dr_en[1]: nsr = {{AWIDTH{1'b0}}, rd_data, rd_status}; + devid_sel: nsr = {{USER_DR_LENGTH-32{1'b0}}, jtag_id, 1'b1}; + endcase + end + shift_ir: nsr = {{USER_DR_LENGTH-5{1'b0}},tdi, sr[4:1]}; + capture_ir: nsr = {{USER_DR_LENGTH-1{1'b0}},1'b1}; + endcase +end + +// TDO retiming +always @ (negedge tck ) tdo <= sr[0]; + +// DMI CS register +always @ (posedge tck or negedge trst) begin + if(!trst) begin + dmi_hard_reset <= 1'b0; + dmi_reset <= 1'b0; + end + else if (update_dr & dr_en[0]) begin + dmi_hard_reset <= sr[17]; + dmi_reset <= sr[16]; + end + else begin + dmi_hard_reset <= 1'b0; + dmi_reset <= 1'b0; + end +end + +// DR register +always @ (posedge tck or negedge trst) begin + if(!trst) + dr <= '0; + else begin + if (update_dr & dr_en[1]) + dr <= sr; + else + dr <= {dr[USER_DR_LENGTH-1:2],2'b0}; + end +end + +assign {wr_addr, wr_data, wr_en, rd_en} = dr; + + + + +endmodule diff --git a/src/main/scala/dec/dec_tlu_ctl.scala b/src/main/scala/dec/dec_tlu_ctl.scala index ee2b23ed..05ab4fef 100644 --- a/src/main/scala/dec/dec_tlu_ctl.scala +++ b/src/main/scala/dec/dec_tlu_ctl.scala @@ -1747,7 +1747,7 @@ val wr_mcycleh_r = WireInit(UInt(1.W), 0.U) mfdc_int := rvdffe(mfdc_ns,wr_mfdc_r.asBool,clock,io.scan_mode) // rvdffe #(15) mfdc_ff (.*, .en(wr_mfdc_r), .din({mfdc_ns[14:0]}), .dout(mfdc_int[14:0])); - if(BUILD_AXI4 == true){ + if(BUILD_AXI4 == 1){ // flip poweron value of bit 6 for AXI build mfdc_ns := Cat(~io.dec_csr_wrdata_r(18,16),io.dec_csr_wrdata_r(11,7), ~io.dec_csr_wrdata_r(6), io.dec_csr_wrdata_r(5,0)) mfdc := Cat(~mfdc_int(14,12),0.U(4.W), mfdc_int(11,7), ~mfdc_int(6), mfdc_int(5,0)) @@ -2118,7 +2118,7 @@ miccme_ce_req := (("hffffffff".U(32.W) << miccmect(31,27)) & Cat(0.U(5.W), miccm val dicad0h = rvdffe(dicad0h_ns,(wr_dicad0h_r | io.ifu_ic_debug_rd_data_valid).asBool,clock,io.scan_mode) - if (ICACHE_ECC == true) { + if (ICACHE_ECC == 1) { // ---------------------------------------------------------------------- // DICAD1 (R/W) (Only accessible in debug mode) // [6:0] : ECC @@ -2151,7 +2151,7 @@ miccme_ce_req := (("hffffffff".U(32.W) << miccmect(31,27)) & Cat(0.U(5.W), miccm // DICAGO (R/W) (Only accessible in debug mode) // [0] : Go - if (ICACHE_ECC == true) io.dec_tlu_ic_diag_pkt.icache_wrdata := Cat(dicad1(6,0), dicad0h(31,0), dicad0(31,0)) + if (ICACHE_ECC == 1) io.dec_tlu_ic_diag_pkt.icache_wrdata := Cat(dicad1(6,0), dicad0h(31,0), dicad0(31,0)) else io.dec_tlu_ic_diag_pkt.icache_wrdata := Cat(0.U(2.W),dicad1(3,0), dicad0h(31,0), dicad0(31,0)) io.dec_tlu_ic_diag_pkt.icache_dicawics := dicawics diff --git a/src/main/scala/lib/lib.scala b/src/main/scala/lib/lib.scala index cc4f7ca1..8b23c215 100644 --- a/src/main/scala/lib/lib.scala +++ b/src/main/scala/lib/lib.scala @@ -321,7 +321,7 @@ trait lib extends param{ val EN = Input(Bool()) val SE = Input(Bool()) }) - addResource("/vsrc/gated_latch.v") + addResource("/vsrc/gated_latch.sv") } class rvclkhdr extends Module { diff --git a/target/scala-2.12/classes/dec/csr_tlu.class b/target/scala-2.12/classes/dec/csr_tlu.class index d49138de3b67abde840f0f62660d1ea8d021e525..f3452e79402ee3a0b683b3c2b362d00596aa4aa2 100644 GIT binary patch literal 215903 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zWouwlOE$k`^UFwJw@a=7$!?ci2C^e`g3juA;tg&h6sgD&;<6tX5g7DBH;vl3&-FHw1wZ{5Kv2rcED3y@Jtr{ z;Q&x{h<)%KP`QaW@ETsiE9eaG;T^n%uJF0)6GWfj1AK%o8k-l`!A7n-d@dGEauOV1 z(9w-34Jfe4^@PvGgp-^vc!LieJ&4kR8(id`OZ~rly?|aE_J%&t7aGtJLevqO!Y-%? z9iSQP1nMR+ndPB&6g8m+Ob4no5e}0WLLDo@U=%XoAeGiRm`33>n`jl$TKhWv zlXUwMVZUa-F6?)7mF8ILSY~sqV1fsFoS4O@&4xLg&|snm@E3>o;h{dX`GG$KKo+Z( z5D7Z6e`}8v;0yAL{JYof(z@Hp0hoKtx3!#5u!4TsA0E%1s8vp= 8) begin: genblock +`endif + +`ifdef RV_FPGA_OPTIMIZE + rvdffs #(WIDTH) dff ( .* ); +`else + rvclkhdr clkhdr ( .* ); + rvdff #(WIDTH) dff (.*, .clk(l1clk)); +`endif + +`ifndef PHYSICAL + end + else + $error(" rvdffe width must be >= 8"); +`endif +end // else: !if(SHORT == 1) + +endmodule // rvdffe + +module rvsyncss #(parameter WIDTH = 251) + ( + input logic clk, + input logic rst_l, + input logic [WIDTH-1:0] din, + output logic [WIDTH-1:0] dout + ); + + logic [WIDTH-1:0] din_ff1; + + rvdff #(WIDTH) sync_ff1 (.*, .din (din[WIDTH-1:0]), .dout(din_ff1[WIDTH-1:0])); + rvdff #(WIDTH) sync_ff2 (.*, .din (din_ff1[WIDTH-1:0]), .dout(dout[WIDTH-1:0])); + +endmodule // rvsyncss + +module rvlsadder + ( + input logic [31:0] rs1, + input logic [11:0] offset, + + output logic [31:0] dout + ); + + logic cout; + logic sign; + + logic [31:12] rs1_inc; + logic [31:12] rs1_dec; + + assign {cout,dout[11:0]} = {1'b0,rs1[11:0]} + {1'b0,offset[11:0]}; + + assign rs1_inc[31:12] = rs1[31:12] + 1; + + assign rs1_dec[31:12] = rs1[31:12] - 1; + + assign sign = offset[11]; + + assign dout[31:12] = ({20{ sign ^~ cout}} & rs1[31:12]) | + ({20{ ~sign & cout}} & rs1_inc[31:12]) | + ({20{ sign & ~cout}} & rs1_dec[31:12]); + +endmodule // rvlsadder + +// assume we only maintain pc[31:1] in the pipe + +module rvbradder + ( + input [31:1] pc, + input [12:1] offset, + + output [31:1] dout + ); + + logic cout; + logic sign; + + logic [31:13] pc_inc; + logic [31:13] pc_dec; + + assign {cout,dout[12:1]} = {1'b0,pc[12:1]} + {1'b0,offset[12:1]}; + + assign pc_inc[31:13] = pc[31:13] + 1; + + assign pc_dec[31:13] = pc[31:13] - 1; + + assign sign = offset[12]; + + + assign dout[31:13] = ({19{ sign ^~ cout}} & pc[31:13]) | + ({19{ ~sign & cout}} & pc_inc[31:13]) | + ({19{ sign & ~cout}} & pc_dec[31:13]); + + +endmodule // rvbradder + + +// 2s complement circuit +module rvtwoscomp #( parameter WIDTH=32 ) + ( + input logic [WIDTH-1:0] din, + + output logic [WIDTH-1:0] dout + ); + + logic [WIDTH-1:1] dout_temp; // holding for all other bits except for the lsb. LSB is always din + + genvar i; + + for ( i = 1; i < WIDTH; i++ ) begin : flip_after_first_one + assign dout_temp[i] = (|din[i-1:0]) ? ~din[i] : din[i]; + end : flip_after_first_one + + assign dout[WIDTH-1:0] = { dout_temp[WIDTH-1:1], din[0] }; + +endmodule // 2'scomp + +// find first +module rvfindfirst1 #( parameter WIDTH=32, SHIFT=$clog2(WIDTH) ) + ( + input logic [WIDTH-1:0] din, + + output logic [SHIFT-1:0] dout + ); + logic done; + + always_comb begin + dout[SHIFT-1:0] = {SHIFT{1'b0}}; + done = 1'b0; + + for ( int i = WIDTH-1; i > 0; i-- ) begin : find_first_one + done |= din[i]; + dout[SHIFT-1:0] += done ? 1'b0 : 1'b1; + end : find_first_one + end +endmodule // rvfindfirst1 + +module rvfindfirst1hot #( parameter WIDTH=32 ) + ( + input logic [WIDTH-1:0] din, + + output logic [WIDTH-1:0] dout + ); + logic done; + + always_comb begin + dout[WIDTH-1:0] = {WIDTH{1'b0}}; + done = 1'b0; + for ( int i = 0; i < WIDTH; i++ ) begin : find_first_one + dout[i] = ~done & din[i]; + done |= din[i]; + end : find_first_one + end +endmodule // rvfindfirst1hot + +// mask and match function matches bits after finding the first 0 position +// find first starting from LSB. Skip that location and match the rest of the bits +module rvmaskandmatch #( parameter WIDTH=32 ) + ( + input logic [WIDTH-1:0] mask, // this will have the mask in the lower bit positions + input logic [WIDTH-1:0] data, // this is what needs to be matched on the upper bits with the mask's upper bits + input logic masken, // when 1 : do mask. 0 : full match + output logic match + ); + + logic [WIDTH-1:0] matchvec; + logic masken_or_fullmask; + + assign masken_or_fullmask = masken & ~(&mask[WIDTH-1:0]); + + assign matchvec[0] = masken_or_fullmask | (mask[0] == data[0]); + genvar i; + + for ( i = 1; i < WIDTH; i++ ) begin : match_after_first_zero + assign matchvec[i] = (&mask[i-1:0] & masken_or_fullmask) ? 1'b1 : (mask[i] == data[i]); + end : match_after_first_zero + + assign match = &matchvec[WIDTH-1:0]; // all bits either matched or were masked off + +endmodule // rvmaskandmatch + + + + +// Check if the S_ADDR <= addr < E_ADDR +module rvrangecheck #(CCM_SADR = 32'h0, + CCM_SIZE = 128) ( + input logic [31:0] addr, // Address to be checked for range + output logic in_range, // S_ADDR <= start_addr < E_ADDR + output logic in_region +); + + localparam REGION_BITS = 4; + localparam MASK_BITS = 10 + $clog2(CCM_SIZE); + + logic [31:0] start_addr; + logic [3:0] region; + + assign start_addr[31:0] = CCM_SADR; + assign region[REGION_BITS-1:0] = start_addr[31:(32-REGION_BITS)]; + + assign in_region = (addr[31:(32-REGION_BITS)] == region[REGION_BITS-1:0]); + if (CCM_SIZE == 48) + assign in_range = (addr[31:MASK_BITS] == start_addr[31:MASK_BITS]) & ~(&addr[MASK_BITS-1 : MASK_BITS-2]); + else + assign in_range = (addr[31:MASK_BITS] == start_addr[31:MASK_BITS]); + +endmodule // rvrangechecker + +// 16 bit even parity generator +module rveven_paritygen #(WIDTH = 16) ( + input logic [WIDTH-1:0] data_in, // Data + output logic parity_out // generated even parity + ); + + assign parity_out = ^(data_in[WIDTH-1:0]) ; + +endmodule // rveven_paritygen + +module rveven_paritycheck #(WIDTH = 16) ( + input logic [WIDTH-1:0] data_in, // Data + input logic parity_in, + output logic parity_err // Parity error + ); + + assign parity_err = ^(data_in[WIDTH-1:0]) ^ parity_in ; + +endmodule // rveven_paritycheck + +module rvecc_encode ( + input [31:0] din, + output [6:0] ecc_out + ); +logic [5:0] ecc_out_temp; + + assign ecc_out_temp[0] = din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]; + assign ecc_out_temp[1] = din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31]; + assign ecc_out_temp[2] = din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31]; + assign ecc_out_temp[3] = din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]; + assign ecc_out_temp[4] = din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]; + assign ecc_out_temp[5] = din[26]^din[27]^din[28]^din[29]^din[30]^din[31]; + + assign ecc_out[6:0] = {(^din[31:0])^(^ecc_out_temp[5:0]),ecc_out_temp[5:0]}; + +endmodule // rvecc_encode + +module rvecc_decode ( + input en, + input [31:0] din, + input [6:0] ecc_in, + input sed_ded, // only do detection and no correction. Used for the I$ + output [31:0] dout, + output [6:0] ecc_out, + output single_ecc_error, + output double_ecc_error + + ); + + logic [6:0] ecc_check; + logic [38:0] error_mask; + logic [38:0] din_plus_parity, dout_plus_parity; + + // Generate the ecc bits + assign ecc_check[0] = ecc_in[0]^din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]; + assign ecc_check[1] = ecc_in[1]^din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31]; + assign ecc_check[2] = ecc_in[2]^din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31]; + assign ecc_check[3] = ecc_in[3]^din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]; + assign ecc_check[4] = ecc_in[4]^din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]; + assign ecc_check[5] = ecc_in[5]^din[26]^din[27]^din[28]^din[29]^din[30]^din[31]; + + // This is the parity bit + assign ecc_check[6] = ((^din[31:0])^(^ecc_in[6:0])) & ~sed_ded; + + assign single_ecc_error = en & (ecc_check[6:0] != 0) & ecc_check[6]; // this will never be on for sed_ded + assign double_ecc_error = en & (ecc_check[6:0] != 0) & ~ecc_check[6]; // all errors in the sed_ded case will be recorded as DE + + // Generate the mask for error correctiong + for (genvar i=1; i<40; i++) begin + assign error_mask[i-1] = (ecc_check[5:0] == i); + end + + // Generate the corrected data + assign din_plus_parity[38:0] = {ecc_in[6], din[31:26], ecc_in[5], din[25:11], ecc_in[4], din[10:4], ecc_in[3], din[3:1], ecc_in[2], din[0], ecc_in[1:0]}; + + assign dout_plus_parity[38:0] = single_ecc_error ? (error_mask[38:0] ^ din_plus_parity[38:0]) : din_plus_parity[38:0]; + assign dout[31:0] = {dout_plus_parity[37:32], dout_plus_parity[30:16], dout_plus_parity[14:8], dout_plus_parity[6:4], dout_plus_parity[2]}; + assign ecc_out[6:0] = {(dout_plus_parity[38] ^ (ecc_check[6:0] == 7'b1000000)), dout_plus_parity[31], dout_plus_parity[15], dout_plus_parity[7], dout_plus_parity[3], dout_plus_parity[1:0]}; + +endmodule // rvecc_decode + +module rvecc_encode_64 ( + input [63:0] din, + output [6:0] ecc_out + ); + assign ecc_out[0] = din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]^din[32]^din[34]^din[36]^din[38]^din[40]^din[42]^din[44]^din[46]^din[48]^din[50]^din[52]^din[54]^din[56]^din[57]^din[59]^din[61]^din[63]; + + assign ecc_out[1] = din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31]^din[32]^din[35]^din[36]^din[39]^din[40]^din[43]^din[44]^din[47]^din[48]^din[51]^din[52]^din[55]^din[56]^din[58]^din[59]^din[62]^din[63]; + + assign ecc_out[2] = din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31]^din[32]^din[37]^din[38]^din[39]^din[40]^din[45]^din[46]^din[47]^din[48]^din[53]^din[54]^din[55]^din[56]^din[60]^din[61]^din[62]^din[63]; + + assign ecc_out[3] = din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56]; + + assign ecc_out[4] = din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56]; + + assign ecc_out[5] = din[26]^din[27]^din[28]^din[29]^din[30]^din[31]^din[32]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56]; + + assign ecc_out[6] = din[57]^din[58]^din[59]^din[60]^din[61]^din[62]^din[63]; + +endmodule // rvecc_encode_64 + + +module rvecc_decode_64 ( + input en, + input [63:0] din, + input [6:0] ecc_in, + output ecc_error + ); + + logic [6:0] ecc_check; + + // Generate the ecc bits + assign ecc_check[0] = ecc_in[0]^din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]^din[32]^din[34]^din[36]^din[38]^din[40]^din[42]^din[44]^din[46]^din[48]^din[50]^din[52]^din[54]^din[56]^din[57]^din[59]^din[61]^din[63]; + + assign ecc_check[1] = ecc_in[1]^din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31]^din[32]^din[35]^din[36]^din[39]^din[40]^din[43]^din[44]^din[47]^din[48]^din[51]^din[52]^din[55]^din[56]^din[58]^din[59]^din[62]^din[63]; + + assign ecc_check[2] = ecc_in[2]^din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31]^din[32]^din[37]^din[38]^din[39]^din[40]^din[45]^din[46]^din[47]^din[48]^din[53]^din[54]^din[55]^din[56]^din[60]^din[61]^din[62]^din[63]; + + assign ecc_check[3] = ecc_in[3]^din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56]; + + assign ecc_check[4] = ecc_in[4]^din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56]; + + assign ecc_check[5] = ecc_in[5]^din[26]^din[27]^din[28]^din[29]^din[30]^din[31]^din[32]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56]; + + assign ecc_check[6] = ecc_in[6]^din[57]^din[58]^din[59]^din[60]^din[61]^din[62]^din[63]; + + assign ecc_error = en & (ecc_check[6:0] != 0); // all errors in the sed_ded case will be recorded as DE + + endmodule // rvecc_decode_64 + + +module gated_flop + ( + input logic SE, EN, CK, + output Q + ); + + logic en_ff; + logic enable; + + assign enable = EN | SE; + +`ifdef VERILATOR + always @(negedge CK) begin + en_ff <= enable; + end +`else + always @(CK, enable) begin + if(!CK) + en_ff = enable; + end +`endif + assign Q = CK & en_ff; + +endmodule + +module rvclkhdr + ( + input logic en, + input logic clk, + input logic scan_mode, + output logic l1clk + ); + + logic SE; + assign SE = scan_mode; + + gated_flop clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk)); + +endmodule // rvclkhdr + +module rvoclkhdr + ( + input logic en, + input logic clk, + input logic scan_mode, + output logic l1clk + ); + + logic SE; + assign SE = scan_mode; + +`ifdef RV_FPGA_OPTIMIZE + assign l1clk = clk; +`else + gated_flop clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk)); +`endif + +endmodule + + + diff --git a/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv b/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv index e69de29b..562f815e 100644 --- a/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv +++ b/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2018 Western Digital Corporation or it's affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//------------------------------------------------------------------------------------ +// +// Copyright Western Digital, 2019 +// Owner : Alex Grobman +// Description: +// This module Synchronizes the signals between JTAG (TCK) and +// processor (Core_clk) +// +//------------------------------------------------------------------------------------- + +module dmi_jtag_to_core_sync ( +// JTAG signals +input rd_en, // 1 bit Read Enable from JTAG +input wr_en, // 1 bit Write enable from JTAG + +// Processor Signals +input rst_n, // Core reset +input clk, // Core clock + +output reg_en, // 1 bit Write interface bit to Processor +output reg_wr_en // 1 bit Write enable to Processor +); + +wire c_rd_en; +wire c_wr_en; +reg [2:0] rden, wren; + + +// Outputs +assign reg_en = c_wr_en | c_rd_en; +assign reg_wr_en = c_wr_en; + + +// synchronizers +always @ ( posedge clk or negedge rst_n) begin + if(!rst_n) begin + rden <= '0; + wren <= '0; + end + else begin + rden <= {rden[1:0], rd_en}; + wren <= {wren[1:0], wr_en}; + end +end + +assign c_rd_en = rden[1] & ~rden[2]; +assign c_wr_en = wren[1] & ~wren[2]; + + +endmodule diff --git a/target/scala-2.12/classes/vsrc/dmi_wrapper.sv b/target/scala-2.12/classes/vsrc/dmi_wrapper.sv index e69de29b..d9fd7410 100644 --- a/target/scala-2.12/classes/vsrc/dmi_wrapper.sv +++ b/target/scala-2.12/classes/vsrc/dmi_wrapper.sv @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2018 Western Digital Corporation or it's affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//------------------------------------------------------------------------------------ +// +// Copyright Western Digital, 2018 +// Owner : Anusha Narayanamoorthy +// Description: +// Wrapper module for JTAG_TAP and DMI synchronizer +// +//------------------------------------------------------------------------------------- + +module dmi_wrapper( + + // JTAG signals + input trst_n, // JTAG reset + input tck, // JTAG clock + input tms, // Test mode select + input tdi, // Test Data Input + output tdo, // Test Data Output + output tdoEnable, // Test Data Output enable + + // Processor Signals + input core_rst_n, // Core reset + input core_clk, // Core clock + input [31:1] jtag_id, // JTAG ID + input [31:0] rd_data, // 32 bit Read data from Processor + output [31:0] reg_wr_data, // 32 bit Write data to Processor + output [6:0] reg_wr_addr, // 7 bit reg address to Processor + output reg_en, // 1 bit Read enable to Processor + output reg_wr_en, // 1 bit Write enable to Processor + output dmi_hard_reset +); + + + + + + //Wire Declaration + wire rd_en; + wire wr_en; + wire dmireset; + + + //jtag_tap instantiation + rvjtag_tap i_jtag_tap( + .trst(trst_n), // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset + .tck(tck), // dedicated JTAG TCK pad signal + .tms(tms), // dedicated JTAG TMS pad signal + .tdi(tdi), // dedicated JTAG TDI pad signal + .tdo(tdo), // dedicated JTAG TDO pad signal + .tdoEnable(tdoEnable), // enable for TDO pad + .wr_data(reg_wr_data), // 32 bit Write data + .wr_addr(reg_wr_addr), // 7 bit Write address + .rd_en(rd_en), // 1 bit read enable + .wr_en(wr_en), // 1 bit Write enable + .rd_data(rd_data), // 32 bit Read data + .rd_status(2'b0), + .idle(3'h0), // no need to wait to sample data + .dmi_stat(2'b0), // no need to wait or error possible + .version(4'h1), // debug spec 0.13 compliant + .jtag_id(jtag_id), + .dmi_hard_reset(dmi_hard_reset), + .dmi_reset(dmireset) +); + + + // dmi_jtag_to_core_sync instantiation + dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync( + .wr_en(wr_en), // 1 bit Write enable + .rd_en(rd_en), // 1 bit Read enable + + .rst_n(core_rst_n), + .clk(core_clk), + .reg_en(reg_en), // 1 bit Write interface bit + .reg_wr_en(reg_wr_en) // 1 bit Write enable + ); + +endmodule diff --git a/target/scala-2.12/classes/vsrc/gated_latch.sv b/target/scala-2.12/classes/vsrc/gated_latch.sv new file mode 100644 index 00000000..51b96c9d --- /dev/null +++ b/target/scala-2.12/classes/vsrc/gated_latch.sv @@ -0,0 +1,14 @@ +module gated_latch + ( + input logic SE, EN, CK, + output Q + ); + logic en_ff; + logic enable; + assign enable = EN | SE; + always @(CK, enable) begin + if(!CK) + en_ff = enable; + end + assign Q = CK & en_ff; +endmodule diff --git a/target/scala-2.12/classes/vsrc/ifu_ic_mem.sv b/target/scala-2.12/classes/vsrc/ifu_ic_mem.sv index 0875c8ef..269925a6 100644 --- a/target/scala-2.12/classes/vsrc/ifu_ic_mem.sv +++ b/target/scala-2.12/classes/vsrc/ifu_ic_mem.sv @@ -23,7 +23,7 @@ module ifu_ic_mem parameter ICACHE_NUM_WAYS, parameter ICACHE_BANK_BITS, parameter ICACHE_BEAT_ADDR_HI, - parameter ICACHE_BANKS_WAY, + parameter ICACHE_BANKS_WAY=2, parameter ICACHE_INDEX_HI, parameter ICACHE_BANK_HI, parameter ICACHE_BANK_LO, @@ -67,7 +67,7 @@ module ifu_ic_mem ) ; - IC_TAG #( + EL2_IC_TAG #( .ICACHE_BEAT_BITS(ICACHE_BEAT_BITS), .ICACHE_NUM_WAYS(ICACHE_NUM_WAYS), .ICACHE_BANK_BITS(ICACHE_BANK_BITS), @@ -90,7 +90,7 @@ module ifu_ic_mem .ic_rw_addr (ic_rw_addr[31:3]) ) ; - IC_DATA #( + EL2_IC_DATA #( .ICACHE_BEAT_BITS(ICACHE_BEAT_BITS), .ICACHE_NUM_WAYS(ICACHE_NUM_WAYS), .ICACHE_BANK_BITS(ICACHE_BANK_BITS), @@ -119,7 +119,7 @@ module ifu_ic_mem ///////////////////////////////////////////////// ////// ICACHE DATA MODULE //////////////////// ///////////////////////////////////////////////// -module IC_DATA +module EL2_IC_DATA #( parameter ICACHE_BEAT_BITS, parameter ICACHE_NUM_WAYS, @@ -990,7 +990,7 @@ endmodule // EL2_IC_DATA ///////////////////////////////////////////////// ////// ICACHE TAG MODULE //////////////////// ///////////////////////////////////////////////// -module IC_TAG +module EL2_IC_TAG #( parameter ICACHE_BEAT_BITS, parameter ICACHE_NUM_WAYS, @@ -1025,7 +1025,7 @@ module IC_TAG input logic ic_debug_tag_array, // Debug tag array input logic [ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr. - output logic [25:0] ictag_debug_rd_data, + output logic [25:0] ic_tag_debug_rd_data, input logic [70:0] ic_debug_wr_data, // Debug wr cache. output logic [ICACHE_NUM_WAYS-1:0] ic_rd_hit, diff --git a/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv b/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv index 1608a603..85c81c49 100644 --- a/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv +++ b/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv @@ -27,7 +27,7 @@ // //******************************************************************************** -module el2_lsu_dccm_mem +module lsu_dccm_mem #( parameter DCCM_BYTE_WIDTH, parameter DCCM_BITS, diff --git a/target/scala-2.12/classes/vsrc/mem.sv b/target/scala-2.12/classes/vsrc/mem.sv index 56e9fe57..0aee1897 100644 --- a/target/scala-2.12/classes/vsrc/mem.sv +++ b/target/scala-2.12/classes/vsrc/mem.sv @@ -15,14 +15,14 @@ module mem #( parameter DCCM_NUM_BANKS, parameter ICACHE_BANK_HI, parameter ICACHE_BANK_LO, - parameter DCCM_ENABLE, + parameter DCCM_ENABLE= 'b1, parameter ICACHE_TAG_LO, parameter ICACHE_DATA_INDEX_LO, parameter ICCM_NUM_BANKS, parameter ICACHE_ECC, - parameter ICACHE_ENABLE, + parameter ICACHE_ENABLE= 'b1, parameter DCCM_BANK_BITS, - parameter ICCM_ENABLE, + parameter ICCM_ENABLE= 'b1, parameter ICCM_BANK_BITS, parameter ICACHE_TAG_DEPTH, parameter ICACHE_WAYPACK, @@ -77,8 +77,9 @@ module mem #( input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache. input logic ic_sel_premux_data, // Premux data sel - input logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC - input logic [70:0] ic_debug_wr_data, // Debug wr cache. + input logic [70:0] ic_wr_data_0, // Data to fill to the Icache. With ECC + input logic [70:0] ic_wr_data_1, + input logic [70:0] ic_debug_wr_data, // Debug wr cache. output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC input logic [ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache. input logic ic_debug_rd_en, // Icache debug rd @@ -100,6 +101,9 @@ module mem #( ); + logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data; +assign ic_wr_data [0] = ic_wr_data_0; +assign ic_wr_data [1] = ic_wr_data_1; // DCCM Instantiation if (DCCM_ENABLE == 1) begin: Gen_dccm_enable lsu_dccm_mem #( @@ -142,7 +146,7 @@ else begin assign ic_rd_hit[ICACHE_NUM_WAYS-1:0] = '0; assign ic_tag_perr = '0 ; assign ic_rd_data = '0 ; - assign ic_stag_debug_rd_data = '0 ; + assign ic_tag_debug_rd_data = '0 ; end // else: !if( ICACHE_ENABLE ) diff --git a/target/scala-2.12/classes/vsrc/mem_lib.sv b/target/scala-2.12/classes/vsrc/mem_lib.sv new file mode 100644 index 00000000..e741c618 --- /dev/null +++ b/target/scala-2.12/classes/vsrc/mem_lib.sv @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2020 Western Digital Corporation or it's affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`define EL2_LOCAL_RAM_TEST_IO \ +input logic WE, \ +input logic ME, \ +input logic CLK + +`define EL2_RAM(depth, width) \ +module ram_``depth``x``width( \ + input logic [$clog2(depth)-1:0] ADR, \ + input logic [(width-1):0] D, \ + output logic [(width-1):0] Q, \ + `EL2_LOCAL_RAM_TEST_IO \ +); \ +reg [(width-1):0] ram_core [(depth-1):0]; \ + \ +always @(posedge CLK) begin \ + if (ME && WE) ram_core[ADR] = D; \ + if (ME && ~WE) Q <= ram_core[ADR]; \ +end \ + \ +endmodule + +`define EL2_RAM_BE(depth, width) \ +module ram_be_``depth``x``width( \ + input logic [$clog2(depth)-1:0] ADR, \ + input logic [(width-1):0] D, WEM, \ + output logic [(width-1):0] Q, \ + `EL2_LOCAL_RAM_TEST_IO \ +); \ +reg [(width-1):0] ram_core [(depth-1):0]; \ + \ +always @(posedge CLK) begin \ + if (ME && WE) ram_core[ADR] = D & WEM | ~WEM & ram_core[ADR];\ + if (ME && ~WE) Q <= ram_core[ADR]; \ +end \ + \ + \ +endmodule + +// parameterizable RAM for verilator sims +module el2_ram #(depth=4096, width=39) ( +input logic [$clog2(depth)-1:0] ADR, +input logic [(width-1):0] D, +output logic [(width-1):0] Q, + `EL2_LOCAL_RAM_TEST_IO +); +reg [(width-1):0] ram_core [(depth-1):0]; + +always @(posedge CLK) begin + if (ME && WE) ram_core[ADR] = D; + if (ME && ~WE) Q <= ram_core[ADR]; +end +endmodule + +//========================================================================================================================= +//=================================== START OF CCM ======================================================================= +//============= Possible sram sizes for a 39 bit wide memory ( 4 bytes + 7 bits ECC ) ===================================== +//------------------------------------------------------------------------------------------------------------------------- +`EL2_RAM(32768, 39) +`EL2_RAM(16384, 39) +`EL2_RAM(8192, 39) +`EL2_RAM(4096, 39) +`EL2_RAM(3072, 39) +`EL2_RAM(2048, 39) +`EL2_RAM(1536, 39) // need this for the 48KB DCCM option) +`EL2_RAM(1024, 39) +`EL2_RAM(768, 39) +`EL2_RAM(512, 39) +`EL2_RAM(256, 39) +`EL2_RAM(128, 39) +`EL2_RAM(1024, 20) +`EL2_RAM(512, 20) +`EL2_RAM(256, 20) +`EL2_RAM(128, 20) +`EL2_RAM(64, 20) +`EL2_RAM(4096, 34) +`EL2_RAM(2048, 34) +`EL2_RAM(1024, 34) +`EL2_RAM(512, 34) +`EL2_RAM(256, 34) +`EL2_RAM(128, 34) +`EL2_RAM(64, 34) +`EL2_RAM(8192, 68) +`EL2_RAM(4096, 68) +`EL2_RAM(2048, 68) +`EL2_RAM(1024, 68) +`EL2_RAM(512, 68) +`EL2_RAM(256, 68) +`EL2_RAM(128, 68) +`EL2_RAM(64, 68) +`EL2_RAM(8192, 71) +`EL2_RAM(4096, 71) +`EL2_RAM(2048, 71) +`EL2_RAM(1024, 71) +`EL2_RAM(512, 71) +`EL2_RAM(256, 71) +`EL2_RAM(128, 71) +`EL2_RAM(64, 71) +`EL2_RAM(4096, 42) +`EL2_RAM(2048, 42) +`EL2_RAM(1024, 42) +`EL2_RAM(512, 42) +`EL2_RAM(256, 42) +`EL2_RAM(128, 42) +`EL2_RAM(64, 42) +`EL2_RAM(4096, 22) +`EL2_RAM(2048, 22) +`EL2_RAM(1024, 22) +`EL2_RAM(512, 22) +`EL2_RAM(256, 22) +`EL2_RAM(128, 22) +`EL2_RAM(64, 22) +`EL2_RAM(1024, 26) +`EL2_RAM(4096, 26) +`EL2_RAM(2048, 26) +`EL2_RAM(512, 26) +`EL2_RAM(256, 26) +`EL2_RAM(128, 26) +`EL2_RAM(64, 26) +`EL2_RAM(32, 26) +`EL2_RAM(32, 22) +`EL2_RAM_BE(8192, 142) +`EL2_RAM_BE(4096, 142) +`EL2_RAM_BE(2048, 142) +`EL2_RAM_BE(1024, 142) +`EL2_RAM_BE(512, 142) +`EL2_RAM_BE(256, 142) +`EL2_RAM_BE(128, 142) +`EL2_RAM_BE(64, 142) +`EL2_RAM_BE(8192, 284) +`EL2_RAM_BE(4096, 284) +`EL2_RAM_BE(2048, 284) +`EL2_RAM_BE(1024, 284) +`EL2_RAM_BE(512, 284) +`EL2_RAM_BE(256, 284) +`EL2_RAM_BE(128, 284) +`EL2_RAM_BE(64, 284) +`EL2_RAM_BE(8192, 136) +`EL2_RAM_BE(4096, 136) +`EL2_RAM_BE(2048, 136) +`EL2_RAM_BE(1024, 136) +`EL2_RAM_BE(512, 136) +`EL2_RAM_BE(256, 136) +`EL2_RAM_BE(128, 136) +`EL2_RAM_BE(64, 136) +`EL2_RAM_BE(8192, 272) +`EL2_RAM_BE(4096, 272) +`EL2_RAM_BE(2048, 272) +`EL2_RAM_BE(1024, 272) +`EL2_RAM_BE(512, 272) +`EL2_RAM_BE(256, 272) +`EL2_RAM_BE(128, 272) +`EL2_RAM_BE(64, 272) +`EL2_RAM_BE(4096, 52) +`EL2_RAM_BE(2048, 52) +`EL2_RAM_BE(1024, 52) +`EL2_RAM_BE(512, 52) +`EL2_RAM_BE(256, 52) +`EL2_RAM_BE(128, 52) +`EL2_RAM_BE(64, 52) +`EL2_RAM_BE(4096, 104) +`EL2_RAM_BE(2048, 104) +`EL2_RAM_BE(1024, 104) +`EL2_RAM_BE(512, 104) +`EL2_RAM_BE(256, 104) +`EL2_RAM_BE(128, 104) +`EL2_RAM_BE(64, 104) +`EL2_RAM_BE(4096, 44) +`EL2_RAM_BE(2048, 44) +`EL2_RAM_BE(1024, 44) +`EL2_RAM_BE(512, 44) +`EL2_RAM_BE(256, 44) +`EL2_RAM_BE(128, 44) +`EL2_RAM_BE(64, 44) +`EL2_RAM_BE(4096, 88) +`EL2_RAM_BE(2048, 88) +`EL2_RAM_BE(1024, 88) +`EL2_RAM_BE(512, 88) +`EL2_RAM_BE(256, 88) +`EL2_RAM_BE(128, 88) +`EL2_RAM_BE(64, 88) + + +`undef EL2_RAM +`undef EL2_RAM_BE +`undef EL2_LOCAL_RAM_TEST_IO + + diff --git a/target/scala-2.12/classes/vsrc/mem_mod.sv b/target/scala-2.12/classes/vsrc/mem_mod.sv new file mode 100644 index 00000000..e78f5cec --- /dev/null +++ b/target/scala-2.12/classes/vsrc/mem_mod.sv @@ -0,0 +1,64 @@ +module el2_btb_tag_hash #( +`include "param.vh" + ) ( + input logic [pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1] pc, + output logic [pt.BTB_BTAG_SIZE-1:0] hash + ); + + assign hash = {(pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE+1] ^ + pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+1] ^ + pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1])}; +endmodule + +module el2_btb_tag_hash_fold #( +`include "param.vh" + )( + input logic [pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1] pc, + output logic [pt.BTB_BTAG_SIZE-1:0] hash + ); + + assign hash = {( + pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE+1] ^ + pc[pt.BTB_ADDR_HI+pt.BTB_BTAG_SIZE:pt.BTB_ADDR_HI+1])}; + +endmodule + +module el2_btb_addr_hash #( +`include "param.vh" + )( + input logic [pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO] pc, + output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hash + ); + + +if(pt.BTB_FOLD2_INDEX_HASH) begin : fold2 + assign hash[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = pc[pt.BTB_INDEX1_HI:pt.BTB_INDEX1_LO] ^ + pc[pt.BTB_INDEX3_HI:pt.BTB_INDEX3_LO]; +end + else begin + assign hash[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = pc[pt.BTB_INDEX1_HI:pt.BTB_INDEX1_LO] ^ + pc[pt.BTB_INDEX2_HI:pt.BTB_INDEX2_LO] ^ + pc[pt.BTB_INDEX3_HI:pt.BTB_INDEX3_LO]; +end + +endmodule + +module el2_btb_ghr_hash #( +`include "param.vh" + )( + input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] hashin, + input logic [pt.BHT_GHR_SIZE-1:0] ghr, + output logic [pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] hash + ); + + // The hash function is too complex to write in verilog for all cases. + // The config script generates the logic string based on the bp config. + if(pt.BHT_GHR_HASH_1) begin : ghrhash_cfg1 + assign hash[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] = { ghr[pt.BHT_GHR_SIZE-1:pt.BTB_INDEX1_HI-1], hashin[pt.BTB_INDEX1_HI:2]^ghr[pt.BTB_INDEX1_HI-2:0]}; + end + else begin : ghrhash_cfg2 + assign hash[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO] = { hashin[pt.BHT_GHR_SIZE+1:2]^ghr[pt.BHT_GHR_SIZE-1:0]}; + end + + +endmodule diff --git a/target/scala-2.12/classes/vsrc/rvjtag_tap.sv b/target/scala-2.12/classes/vsrc/rvjtag_tap.sv new file mode 100644 index 00000000..24634344 --- /dev/null +++ b/target/scala-2.12/classes/vsrc/rvjtag_tap.sv @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2019 Western Digital Corporation or it's affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License + +module rvjtag_tap #( +parameter AWIDTH = 7 +) +( +input trst, +input tck, +input tms, +input tdi, +output reg tdo, +output tdoEnable, + +output [31:0] wr_data, +output [AWIDTH-1:0] wr_addr, +output wr_en, +output rd_en, + +input [31:0] rd_data, +input [1:0] rd_status, + +output reg dmi_reset, +output reg dmi_hard_reset, + +input [2:0] idle, +input [1:0] dmi_stat, +/* +-- revisionCode : 4'h0; +-- manufacturersIdCode : 11'h45; +-- deviceIdCode : 16'h0001; +-- order MSB .. LSB -> [4 bit version or revision] [16 bit part number] [11 bit manufacturer id] [value of 1'b1 in LSB] +*/ +input [31:1] jtag_id, +input [3:0] version +); + +localparam USER_DR_LENGTH = AWIDTH + 34; + + +reg [USER_DR_LENGTH-1:0] sr, nsr, dr; + +/////////////////////////////////////////////////////// +// Tap controller +/////////////////////////////////////////////////////// +logic[3:0] state, nstate; +logic [4:0] ir; +wire jtag_reset; +wire shift_dr; +wire pause_dr; +wire update_dr; +wire capture_dr; +wire shift_ir; +wire pause_ir ; +wire update_ir ; +wire capture_ir; +wire[1:0] dr_en; +wire devid_sel; +wire [5:0] abits; + +assign abits = AWIDTH[5:0]; + + +localparam TEST_LOGIC_RESET_STATE = 0; +localparam RUN_TEST_IDLE_STATE = 1; +localparam SELECT_DR_SCAN_STATE = 2; +localparam CAPTURE_DR_STATE = 3; +localparam SHIFT_DR_STATE = 4; +localparam EXIT1_DR_STATE = 5; +localparam PAUSE_DR_STATE = 6; +localparam EXIT2_DR_STATE = 7; +localparam UPDATE_DR_STATE = 8; +localparam SELECT_IR_SCAN_STATE = 9; +localparam CAPTURE_IR_STATE = 10; +localparam SHIFT_IR_STATE = 11; +localparam EXIT1_IR_STATE = 12; +localparam PAUSE_IR_STATE = 13; +localparam EXIT2_IR_STATE = 14; +localparam UPDATE_IR_STATE = 15; + +always_comb begin + nstate = state; + case(state) + TEST_LOGIC_RESET_STATE: nstate = tms ? TEST_LOGIC_RESET_STATE : RUN_TEST_IDLE_STATE; + RUN_TEST_IDLE_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE; + SELECT_DR_SCAN_STATE: nstate = tms ? SELECT_IR_SCAN_STATE : CAPTURE_DR_STATE; + CAPTURE_DR_STATE: nstate = tms ? EXIT1_DR_STATE : SHIFT_DR_STATE; + SHIFT_DR_STATE: nstate = tms ? EXIT1_DR_STATE : SHIFT_DR_STATE; + EXIT1_DR_STATE: nstate = tms ? UPDATE_DR_STATE : PAUSE_DR_STATE; + PAUSE_DR_STATE: nstate = tms ? EXIT2_DR_STATE : PAUSE_DR_STATE; + EXIT2_DR_STATE: nstate = tms ? UPDATE_DR_STATE : SHIFT_DR_STATE; + UPDATE_DR_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE; + SELECT_IR_SCAN_STATE: nstate = tms ? TEST_LOGIC_RESET_STATE : CAPTURE_IR_STATE; + CAPTURE_IR_STATE: nstate = tms ? EXIT1_IR_STATE : SHIFT_IR_STATE; + SHIFT_IR_STATE: nstate = tms ? EXIT1_IR_STATE : SHIFT_IR_STATE; + EXIT1_IR_STATE: nstate = tms ? UPDATE_IR_STATE : PAUSE_IR_STATE; + PAUSE_IR_STATE: nstate = tms ? EXIT2_IR_STATE : PAUSE_IR_STATE; + EXIT2_IR_STATE: nstate = tms ? UPDATE_IR_STATE : SHIFT_IR_STATE; + UPDATE_IR_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE; + default: nstate = TEST_LOGIC_RESET_STATE; + endcase +end + +always @ (posedge tck or negedge trst) begin + if(!trst) state <= TEST_LOGIC_RESET_STATE; + else state <= nstate; +end + +assign jtag_reset = state == TEST_LOGIC_RESET_STATE; +assign shift_dr = state == SHIFT_DR_STATE; +assign pause_dr = state == PAUSE_DR_STATE; +assign update_dr = state == UPDATE_DR_STATE; +assign capture_dr = state == CAPTURE_DR_STATE; +assign shift_ir = state == SHIFT_IR_STATE; +assign pause_ir = state == PAUSE_IR_STATE; +assign update_ir = state == UPDATE_IR_STATE; +assign capture_ir = state == CAPTURE_IR_STATE; + +assign tdoEnable = shift_dr | shift_ir; + +/////////////////////////////////////////////////////// +// IR register +/////////////////////////////////////////////////////// + +always @ (negedge tck or negedge trst) begin + if (!trst) ir <= 5'b1; + else begin + if (jtag_reset) ir <= 5'b1; + else if (update_ir) ir <= (sr[4:0] == '0) ? 5'h1f :sr[4:0]; + end +end + + +assign devid_sel = ir == 5'b00001; +assign dr_en[0] = ir == 5'b10000; +assign dr_en[1] = ir == 5'b10001; + +/////////////////////////////////////////////////////// +// Shift register +/////////////////////////////////////////////////////// +always @ (posedge tck or negedge trst) begin + if(!trst)begin + sr <= '0; + end + else begin + sr <= nsr; + end +end + +// SR next value +always_comb begin + nsr = sr; + case(1) + shift_dr: begin + case(1) + dr_en[1]: nsr = {tdi, sr[USER_DR_LENGTH-1:1]}; + + dr_en[0], + devid_sel: nsr = {{USER_DR_LENGTH-32{1'b0}},tdi, sr[31:1]}; + default: nsr = {{USER_DR_LENGTH-1{1'b0}},tdi}; // bypass + endcase + end + capture_dr: begin + case(1) + dr_en[0]: nsr = {{USER_DR_LENGTH-15{1'b0}}, idle, dmi_stat, abits, version}; + dr_en[1]: nsr = {{AWIDTH{1'b0}}, rd_data, rd_status}; + devid_sel: nsr = {{USER_DR_LENGTH-32{1'b0}}, jtag_id, 1'b1}; + endcase + end + shift_ir: nsr = {{USER_DR_LENGTH-5{1'b0}},tdi, sr[4:1]}; + capture_ir: nsr = {{USER_DR_LENGTH-1{1'b0}},1'b1}; + endcase +end + +// TDO retiming +always @ (negedge tck ) tdo <= sr[0]; + +// DMI CS register +always @ (posedge tck or negedge trst) begin + if(!trst) begin + dmi_hard_reset <= 1'b0; + dmi_reset <= 1'b0; + end + else if (update_dr & dr_en[0]) begin + dmi_hard_reset <= sr[17]; + dmi_reset <= sr[16]; + end + else begin + dmi_hard_reset <= 1'b0; + dmi_reset <= 1'b0; + end +end + +// DR register +always @ (posedge tck or negedge trst) begin + if(!trst) + dr <= '0; + else begin + if (update_dr & dr_en[1]) + dr <= sr; + else + dr <= {dr[USER_DR_LENGTH-1:2],2'b0}; + end +end + +assign {wr_addr, wr_data, wr_en, rd_en} = dr; + + + + +endmodule