From 432a2fdc44657b944a4c08e0c5dea4b45079a0c1 Mon Sep 17 00:00:00 2001 From: waleed-lm Date: Wed, 14 Oct 2020 19:32:17 +0500 Subject: [PATCH] Alingner Done --- el2_ifu_aln_ctl.fir | 30 +++++++++--------- el2_ifu_aln_ctl.v | 10 +++--- src/main/scala/ifu/el2_ifu_aln_ctl.scala | 6 ++-- .../classes/ifu/el2_ifu_aln_ctl.class | Bin 192530 -> 192530 bytes 4 files changed, 22 insertions(+), 24 deletions(-) diff --git a/el2_ifu_aln_ctl.fir b/el2_ifu_aln_ctl.fir index b591b814..3d03c9c9 100644 --- a/el2_ifu_aln_ctl.fir +++ b/el2_ifu_aln_ctl.fir @@ -2360,17 +2360,17 @@ circuit el2_ifu_aln_ctl : node _T_166 = and(_T_164, _T_165) @[el2_ifu_aln_ctl.scala 184:35] node _T_167 = bits(_T_166, 0, 0) @[el2_ifu_aln_ctl.scala 184:52] node _T_168 = or(q0off, f0_shift_2B) @[el2_ifu_aln_ctl.scala 184:76] - node _T_169 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 185:11] - node _T_170 = eq(_T_169, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 185:6] - node _T_171 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 185:23] - node _T_172 = and(_T_170, _T_171) @[el2_ifu_aln_ctl.scala 185:15] - node _T_173 = bits(_T_172, 0, 0) @[el2_ifu_aln_ctl.scala 185:32] - node _T_174 = or(q0off, f1_shift_2B) @[el2_ifu_aln_ctl.scala 185:56] - node _T_175 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 186:11] - node _T_176 = eq(_T_175, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 186:6] - node _T_177 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 186:23] - node _T_178 = and(_T_176, _T_177) @[el2_ifu_aln_ctl.scala 186:15] - node _T_179 = bits(_T_178, 0, 0) @[el2_ifu_aln_ctl.scala 186:32] + node _T_169 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 185:31] + node _T_170 = eq(_T_169, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 185:26] + node _T_171 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 185:43] + node _T_172 = and(_T_170, _T_171) @[el2_ifu_aln_ctl.scala 185:35] + node _T_173 = bits(_T_172, 0, 0) @[el2_ifu_aln_ctl.scala 185:52] + node _T_174 = or(q0off, f1_shift_2B) @[el2_ifu_aln_ctl.scala 185:76] + node _T_175 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 186:31] + node _T_176 = eq(_T_175, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 186:26] + node _T_177 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 186:43] + node _T_178 = and(_T_176, _T_177) @[el2_ifu_aln_ctl.scala 186:35] + node _T_179 = bits(_T_178, 0, 0) @[el2_ifu_aln_ctl.scala 186:52] node _T_180 = mux(_T_167, _T_168, UInt<1>("h00")) @[Mux.scala 27:72] node _T_181 = mux(_T_173, _T_174, UInt<1>("h00")) @[Mux.scala 27:72] node _T_182 = mux(_T_179, q0off, UInt<1>("h00")) @[Mux.scala 27:72] @@ -3138,10 +3138,10 @@ circuit el2_ifu_aln_ctl : node _T_788 = bits(shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 415:37] node _T_789 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 415:52] node _T_790 = bits(shift_4B, 0, 0) @[el2_ifu_aln_ctl.scala 415:66] - node _T_791 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 415:83] - node _T_792 = eq(_T_791, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 415:77] - node _T_793 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 415:94] - node _T_794 = and(_T_792, _T_793) @[el2_ifu_aln_ctl.scala 415:87] + node _T_791 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 415:82] + node _T_792 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 415:94] + node _T_793 = eq(_T_792, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 415:88] + node _T_794 = and(_T_791, _T_793) @[el2_ifu_aln_ctl.scala 415:86] node _T_795 = mux(_T_788, _T_789, UInt<1>("h00")) @[Mux.scala 27:72] node _T_796 = mux(_T_790, _T_794, UInt<1>("h00")) @[Mux.scala 27:72] node _T_797 = or(_T_795, _T_796) @[Mux.scala 27:72] diff --git a/el2_ifu_aln_ctl.v b/el2_ifu_aln_ctl.v index 4363eccb..64c93acc 100644 --- a/el2_ifu_aln_ctl.v +++ b/el2_ifu_aln_ctl.v @@ -764,9 +764,7 @@ module el2_ifu_aln_ctl( wire _T_118 = ~qwen[2]; // @[el2_ifu_aln_ctl.scala 176:26] wire _T_120 = _T_118 & _T_188; // @[el2_ifu_aln_ctl.scala 176:35] wire _T_795 = shift_2B & f0val[0]; // @[Mux.scala 27:72] - wire _T_792 = ~f0val[0]; // @[el2_ifu_aln_ctl.scala 415:77] - wire _T_794 = _T_792 & f0val[0]; // @[el2_ifu_aln_ctl.scala 415:87] - wire _T_796 = shift_4B & _T_794; // @[Mux.scala 27:72] + wire _T_796 = shift_4B & _T_802; // @[Mux.scala 27:72] wire f0_shift_2B = _T_795 | _T_796; // @[Mux.scala 27:72] wire _T_122 = q2off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 176:74] wire _T_126 = _T_118 & _T_187; // @[el2_ifu_aln_ctl.scala 177:15] @@ -789,9 +787,9 @@ module el2_ifu_aln_ctl( wire _T_164 = ~qwen[0]; // @[el2_ifu_aln_ctl.scala 184:26] wire _T_166 = _T_164 & _T_186; // @[el2_ifu_aln_ctl.scala 184:35] wire _T_168 = q0off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 184:76] - wire _T_172 = _T_164 & _T_188; // @[el2_ifu_aln_ctl.scala 185:15] - wire _T_174 = q0off | f1_shift_2B; // @[el2_ifu_aln_ctl.scala 185:56] - wire _T_178 = _T_164 & _T_187; // @[el2_ifu_aln_ctl.scala 186:15] + wire _T_172 = _T_164 & _T_188; // @[el2_ifu_aln_ctl.scala 185:35] + wire _T_174 = q0off | f1_shift_2B; // @[el2_ifu_aln_ctl.scala 185:76] + wire _T_178 = _T_164 & _T_187; // @[el2_ifu_aln_ctl.scala 186:35] wire _T_180 = _T_166 & _T_168; // @[Mux.scala 27:72] wire _T_181 = _T_172 & _T_174; // @[Mux.scala 27:72] wire _T_182 = _T_178 & q0off; // @[Mux.scala 27:72] diff --git a/src/main/scala/ifu/el2_ifu_aln_ctl.scala b/src/main/scala/ifu/el2_ifu_aln_ctl.scala index 4d464dad..5abcf7d8 100644 --- a/src/main/scala/ifu/el2_ifu_aln_ctl.scala +++ b/src/main/scala/ifu/el2_ifu_aln_ctl.scala @@ -182,8 +182,8 @@ class el2_ifu_aln_ctl extends Module with el2_lib with RequireAsyncReset { (!qwen(1) & (rdptr===2.U)).asBool->q1off)) q0off_in := Mux1H(Seq((!qwen(0) & (rdptr===0.U)).asBool -> (q0off.asUInt | f0_shift_2B), - (!qwen(0) & (rdptr===2.U)).asBool -> (q0off.asUInt | f1_shift_2B), - (!qwen(0) & (rdptr===1.U)).asBool -> q0off)) + (!qwen(0) & (rdptr===2.U)).asBool -> (q0off.asUInt | f1_shift_2B), + (!qwen(0) & (rdptr===1.U)).asBool -> q0off)) val q0ptr = Mux1H(Seq((rdptr===0.U)->q0off, (rdptr===1.U)->q1off, @@ -412,7 +412,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib with RequireAsyncReset { shift_2B := i0_shift & first2B shift_4B := i0_shift & first4B - f0_shift_2B := Mux1H(Seq(shift_2B.asBool -> f0val(0), shift_4B.asBool -> (!f0val(0) & f0val(0)))) + f0_shift_2B := Mux1H(Seq(shift_2B.asBool -> f0val(0), shift_4B.asBool -> (f0val(0) & !f0val(1)))) f1_shift_2B := f0val(0) & !f0val(1) & shift_4B } diff --git a/target/scala-2.12/classes/ifu/el2_ifu_aln_ctl.class b/target/scala-2.12/classes/ifu/el2_ifu_aln_ctl.class index 05bdbcb2be522bafc390b2a7386c121cfa291bfd..05a1e4160851caeec869f49b8de29efc6a306d8f 100644 GIT binary patch delta 197 zcmbRAfP2yd?uIRl){CYKeP)!JzF-9-ALGvHj#C(ArZ+5Nlx5VOuGq~eJ$>gQM!xBV zPk}1pFEH{lG3=aPcmSwG;SD3pbb-Z;LenoTWR#oku$WPR(Pw(#Vn!<@<90!eyRaBx z9On{L<8~p8+n%t5(JGfQXnNo@M%n2zg_!uKe-vcWVT_nw_!j7p4Zj$9nCAZnRt0I x!bHv`2oraKP28TmgwZ^gF&N|yb>{g3z947lOg}Ejq{A2vvRZn(r4ZB2y8xC!I#B=s