From 43402819b0e14c8013c1d4b654c53845cccb55a2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E2=80=8BLaraib=20Khan?= <​laraib.khan@lampromellon.com> Date: Thu, 14 Jan 2021 10:12:56 +0500 Subject: [PATCH] slv_error corrected --- axi4_to_ahb.fir | 878 +++++++++--------- axi4_to_ahb.v | 300 +++--- src/main/scala/lib/ahb_to_axi4.scala | 1 - src/main/scala/lib/axi4_to_ahb.scala | 40 +- .../scala-2.12/classes/lib/ahb_to_axi4$.class | Bin 3896 -> 3896 bytes .../lib/ahb_to_axi4$delayedInit$body.class | Bin 756 -> 756 bytes .../scala-2.12/classes/lib/ahb_to_axi4.class | Bin 145871 -> 145867 bytes .../scala-2.12/classes/lib/axi4_to_ahb$.class | Bin 3996 -> 3996 bytes .../lib/axi4_to_ahb$delayedInit$body.class | Bin 756 -> 756 bytes .../scala-2.12/classes/lib/axi4_to_ahb.class | Bin 105964 -> 105967 bytes 10 files changed, 608 insertions(+), 611 deletions(-) diff --git a/axi4_to_ahb.fir b/axi4_to_ahb.fir index 1e88bd14..20a8c118 100644 --- a/axi4_to_ahb.fir +++ b/axi4_to_ahb.fir @@ -340,8 +340,8 @@ circuit axi4_to_ahb : node _T_54 = and(buf_state_en, _T_53) @[axi4_to_ahb.scala 167:38] buf_data_wr_en <= _T_54 @[axi4_to_ahb.scala 167:22] buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 168:27] - node _T_55 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 170:50] - node _T_56 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 170:94] + node _T_55 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 169:50] + node _T_56 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 169:94] node _T_57 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 136:52] node _T_58 = tail(_T_57, 1) @[axi4_to_ahb.scala 136:52] node _T_59 = mux(UInt<1>("h00"), _T_58, UInt<3>("h00")) @[axi4_to_ahb.scala 136:24] @@ -377,166 +377,166 @@ circuit axi4_to_ahb : node _T_89 = mux(_T_68, UInt<2>("h02"), _T_88) @[Mux.scala 98:16] node _T_90 = mux(_T_65, UInt<1>("h01"), _T_89) @[Mux.scala 98:16] node _T_91 = mux(_T_62, UInt<1>("h00"), _T_90) @[Mux.scala 98:16] - node _T_92 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 170:124] - node _T_93 = mux(_T_55, _T_91, _T_92) @[axi4_to_ahb.scala 170:30] - buf_cmd_byte_ptr <= _T_93 @[axi4_to_ahb.scala 170:24] - bypass_en <= buf_state_en @[axi4_to_ahb.scala 171:17] - node _T_94 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 172:51] - node _T_95 = and(bypass_en, _T_94) @[axi4_to_ahb.scala 172:35] - rd_bypass_idle <= _T_95 @[axi4_to_ahb.scala 172:22] + node _T_92 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 169:124] + node _T_93 = mux(_T_55, _T_91, _T_92) @[axi4_to_ahb.scala 169:30] + buf_cmd_byte_ptr <= _T_93 @[axi4_to_ahb.scala 169:24] + bypass_en <= buf_state_en @[axi4_to_ahb.scala 170:17] + node _T_94 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 171:51] + node _T_95 = and(bypass_en, _T_94) @[axi4_to_ahb.scala 171:35] + rd_bypass_idle <= _T_95 @[axi4_to_ahb.scala 171:22] node _T_96 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] node _T_97 = mux(_T_96, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_98 = and(_T_97, UInt<2>("h02")) @[axi4_to_ahb.scala 173:49] - io.ahb.out.htrans <= _T_98 @[axi4_to_ahb.scala 173:25] + node _T_98 = and(_T_97, UInt<2>("h02")) @[axi4_to_ahb.scala 172:49] + io.ahb.out.htrans <= _T_98 @[axi4_to_ahb.scala 172:25] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] node _T_99 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] when _T_99 : @[Conditional.scala 39:67] - node _T_100 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 177:54] - node _T_101 = eq(_T_100, UInt<1>("h00")) @[axi4_to_ahb.scala 177:61] - node _T_102 = and(master_valid, _T_101) @[axi4_to_ahb.scala 177:41] - node _T_103 = bits(_T_102, 0, 0) @[axi4_to_ahb.scala 177:82] - node _T_104 = mux(_T_103, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 177:26] - buf_nxtstate <= _T_104 @[axi4_to_ahb.scala 177:20] - node _T_105 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 178:51] - node _T_106 = neq(_T_105, UInt<1>("h00")) @[axi4_to_ahb.scala 178:58] - node _T_107 = and(ahb_hready_q, _T_106) @[axi4_to_ahb.scala 178:36] - node _T_108 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 178:72] - node _T_109 = and(_T_107, _T_108) @[axi4_to_ahb.scala 178:70] - buf_state_en <= _T_109 @[axi4_to_ahb.scala 178:20] - node _T_110 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 179:34] - node _T_111 = and(buf_state_en, _T_110) @[axi4_to_ahb.scala 179:32] - cmd_done <= _T_111 @[axi4_to_ahb.scala 179:16] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 180:20] - node _T_112 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 181:52] - node _T_113 = neq(_T_112, UInt<1>("h00")) @[axi4_to_ahb.scala 181:59] - node _T_114 = and(ahb_hready_q, _T_113) @[axi4_to_ahb.scala 181:37] - node _T_115 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 181:73] - node _T_116 = and(_T_114, _T_115) @[axi4_to_ahb.scala 181:71] - node _T_117 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 181:122] - node _T_118 = eq(_T_117, UInt<1>("h00")) @[axi4_to_ahb.scala 181:129] - node _T_119 = and(master_valid, _T_118) @[axi4_to_ahb.scala 181:109] - node _T_120 = bits(_T_119, 0, 0) @[axi4_to_ahb.scala 181:150] - node _T_121 = mux(_T_120, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 181:94] - node _T_122 = eq(_T_121, UInt<3>("h06")) @[axi4_to_ahb.scala 181:174] - node _T_123 = and(_T_116, _T_122) @[axi4_to_ahb.scala 181:88] - master_ready <= _T_123 @[axi4_to_ahb.scala 181:20] - buf_wr_en <= master_ready @[axi4_to_ahb.scala 182:17] - node _T_124 = and(master_ready, master_valid) @[axi4_to_ahb.scala 183:33] - bypass_en <= _T_124 @[axi4_to_ahb.scala 183:17] - node _T_125 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 184:47] - node _T_126 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 184:62] - node _T_127 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 184:78] - node _T_128 = mux(_T_125, _T_126, _T_127) @[axi4_to_ahb.scala 184:30] - buf_cmd_byte_ptr <= _T_128 @[axi4_to_ahb.scala 184:24] - node _T_129 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 185:48] - node _T_130 = or(_T_129, bypass_en) @[axi4_to_ahb.scala 185:62] + node _T_100 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 176:54] + node _T_101 = eq(_T_100, UInt<1>("h00")) @[axi4_to_ahb.scala 176:61] + node _T_102 = and(master_valid, _T_101) @[axi4_to_ahb.scala 176:41] + node _T_103 = bits(_T_102, 0, 0) @[axi4_to_ahb.scala 176:82] + node _T_104 = mux(_T_103, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 176:26] + buf_nxtstate <= _T_104 @[axi4_to_ahb.scala 176:20] + node _T_105 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 177:51] + node _T_106 = neq(_T_105, UInt<1>("h00")) @[axi4_to_ahb.scala 177:58] + node _T_107 = and(ahb_hready_q, _T_106) @[axi4_to_ahb.scala 177:36] + node _T_108 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 177:72] + node _T_109 = and(_T_107, _T_108) @[axi4_to_ahb.scala 177:70] + buf_state_en <= _T_109 @[axi4_to_ahb.scala 177:20] + node _T_110 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 178:34] + node _T_111 = and(buf_state_en, _T_110) @[axi4_to_ahb.scala 178:32] + cmd_done <= _T_111 @[axi4_to_ahb.scala 178:16] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 179:20] + node _T_112 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 180:52] + node _T_113 = neq(_T_112, UInt<1>("h00")) @[axi4_to_ahb.scala 180:59] + node _T_114 = and(ahb_hready_q, _T_113) @[axi4_to_ahb.scala 180:37] + node _T_115 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 180:73] + node _T_116 = and(_T_114, _T_115) @[axi4_to_ahb.scala 180:71] + node _T_117 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 180:122] + node _T_118 = eq(_T_117, UInt<1>("h00")) @[axi4_to_ahb.scala 180:129] + node _T_119 = and(master_valid, _T_118) @[axi4_to_ahb.scala 180:109] + node _T_120 = bits(_T_119, 0, 0) @[axi4_to_ahb.scala 180:150] + node _T_121 = mux(_T_120, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 180:94] + node _T_122 = eq(_T_121, UInt<3>("h06")) @[axi4_to_ahb.scala 180:174] + node _T_123 = and(_T_116, _T_122) @[axi4_to_ahb.scala 180:88] + master_ready <= _T_123 @[axi4_to_ahb.scala 180:20] + buf_wr_en <= master_ready @[axi4_to_ahb.scala 181:17] + node _T_124 = and(master_ready, master_valid) @[axi4_to_ahb.scala 182:33] + bypass_en <= _T_124 @[axi4_to_ahb.scala 182:17] + node _T_125 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 183:47] + node _T_126 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 183:62] + node _T_127 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 183:78] + node _T_128 = mux(_T_125, _T_126, _T_127) @[axi4_to_ahb.scala 183:30] + buf_cmd_byte_ptr <= _T_128 @[axi4_to_ahb.scala 183:24] + node _T_129 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 184:48] + node _T_130 = or(_T_129, bypass_en) @[axi4_to_ahb.scala 184:62] node _T_131 = bits(_T_130, 0, 0) @[Bitwise.scala 72:15] node _T_132 = mux(_T_131, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_133 = and(UInt<2>("h02"), _T_132) @[axi4_to_ahb.scala 185:36] - io.ahb.out.htrans <= _T_133 @[axi4_to_ahb.scala 185:25] + node _T_133 = and(UInt<2>("h02"), _T_132) @[axi4_to_ahb.scala 184:36] + io.ahb.out.htrans <= _T_133 @[axi4_to_ahb.scala 184:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_134 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] when _T_134 : @[Conditional.scala 39:67] - node _T_135 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 189:39] - node _T_136 = and(ahb_hready_q, _T_135) @[axi4_to_ahb.scala 189:37] - node _T_137 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 189:82] - node _T_138 = eq(_T_137, UInt<1>("h01")) @[axi4_to_ahb.scala 189:89] - node _T_139 = and(master_valid, _T_138) @[axi4_to_ahb.scala 189:70] - node _T_140 = not(_T_139) @[axi4_to_ahb.scala 189:55] - node _T_141 = and(_T_136, _T_140) @[axi4_to_ahb.scala 189:53] - master_ready <= _T_141 @[axi4_to_ahb.scala 189:20] - node _T_142 = and(master_valid, master_ready) @[axi4_to_ahb.scala 190:34] - node _T_143 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 190:62] - node _T_144 = eq(_T_143, UInt<1>("h00")) @[axi4_to_ahb.scala 190:69] - node _T_145 = and(_T_142, _T_144) @[axi4_to_ahb.scala 190:49] - buf_wr_en <= _T_145 @[axi4_to_ahb.scala 190:17] - node _T_146 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 191:45] - node _T_147 = and(master_valid, master_ready) @[axi4_to_ahb.scala 191:82] - node _T_148 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 191:110] - node _T_149 = eq(_T_148, UInt<1>("h00")) @[axi4_to_ahb.scala 191:117] - node _T_150 = and(_T_147, _T_149) @[axi4_to_ahb.scala 191:97] - node _T_151 = bits(_T_150, 0, 0) @[axi4_to_ahb.scala 191:138] - node _T_152 = mux(_T_151, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 191:67] - node _T_153 = mux(_T_146, UInt<3>("h07"), _T_152) @[axi4_to_ahb.scala 191:26] - buf_nxtstate <= _T_153 @[axi4_to_ahb.scala 191:20] - node _T_154 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 192:37] - buf_state_en <= _T_154 @[axi4_to_ahb.scala 192:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 193:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 194:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 195:23] - node _T_155 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 196:41] - node _T_156 = and(buf_state_en, _T_155) @[axi4_to_ahb.scala 196:39] - slave_valid_pre <= _T_156 @[axi4_to_ahb.scala 196:23] - node _T_157 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 197:34] - node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 197:32] - cmd_done <= _T_158 @[axi4_to_ahb.scala 197:16] - node _T_159 = and(master_ready, master_valid) @[axi4_to_ahb.scala 198:33] - node _T_160 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 198:64] - node _T_161 = and(_T_159, _T_160) @[axi4_to_ahb.scala 198:48] - node _T_162 = and(_T_161, buf_state_en) @[axi4_to_ahb.scala 198:79] - bypass_en <= _T_162 @[axi4_to_ahb.scala 198:17] - node _T_163 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 199:47] - node _T_164 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 199:62] - node _T_165 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 199:78] - node _T_166 = mux(_T_163, _T_164, _T_165) @[axi4_to_ahb.scala 199:30] - buf_cmd_byte_ptr <= _T_166 @[axi4_to_ahb.scala 199:24] - node _T_167 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 200:63] - node _T_168 = and(_T_167, buf_state_en) @[axi4_to_ahb.scala 200:78] - node _T_169 = eq(_T_168, UInt<1>("h00")) @[axi4_to_ahb.scala 200:47] + node _T_135 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 188:39] + node _T_136 = and(ahb_hready_q, _T_135) @[axi4_to_ahb.scala 188:37] + node _T_137 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 188:82] + node _T_138 = eq(_T_137, UInt<1>("h01")) @[axi4_to_ahb.scala 188:89] + node _T_139 = and(master_valid, _T_138) @[axi4_to_ahb.scala 188:70] + node _T_140 = not(_T_139) @[axi4_to_ahb.scala 188:55] + node _T_141 = and(_T_136, _T_140) @[axi4_to_ahb.scala 188:53] + master_ready <= _T_141 @[axi4_to_ahb.scala 188:20] + node _T_142 = and(master_valid, master_ready) @[axi4_to_ahb.scala 189:34] + node _T_143 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 189:62] + node _T_144 = eq(_T_143, UInt<1>("h00")) @[axi4_to_ahb.scala 189:69] + node _T_145 = and(_T_142, _T_144) @[axi4_to_ahb.scala 189:49] + buf_wr_en <= _T_145 @[axi4_to_ahb.scala 189:17] + node _T_146 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 190:45] + node _T_147 = and(master_valid, master_ready) @[axi4_to_ahb.scala 190:82] + node _T_148 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 190:110] + node _T_149 = eq(_T_148, UInt<1>("h00")) @[axi4_to_ahb.scala 190:117] + node _T_150 = and(_T_147, _T_149) @[axi4_to_ahb.scala 190:97] + node _T_151 = bits(_T_150, 0, 0) @[axi4_to_ahb.scala 190:138] + node _T_152 = mux(_T_151, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 190:67] + node _T_153 = mux(_T_146, UInt<3>("h07"), _T_152) @[axi4_to_ahb.scala 190:26] + buf_nxtstate <= _T_153 @[axi4_to_ahb.scala 190:20] + node _T_154 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 191:37] + buf_state_en <= _T_154 @[axi4_to_ahb.scala 191:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 192:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 193:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 194:23] + node _T_155 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 195:41] + node _T_156 = and(buf_state_en, _T_155) @[axi4_to_ahb.scala 195:39] + slave_valid_pre <= _T_156 @[axi4_to_ahb.scala 195:23] + node _T_157 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 196:34] + node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 196:32] + cmd_done <= _T_158 @[axi4_to_ahb.scala 196:16] + node _T_159 = and(master_ready, master_valid) @[axi4_to_ahb.scala 197:33] + node _T_160 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 197:64] + node _T_161 = and(_T_159, _T_160) @[axi4_to_ahb.scala 197:48] + node _T_162 = and(_T_161, buf_state_en) @[axi4_to_ahb.scala 197:79] + bypass_en <= _T_162 @[axi4_to_ahb.scala 197:17] + node _T_163 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 198:47] + node _T_164 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 198:62] + node _T_165 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 198:78] + node _T_166 = mux(_T_163, _T_164, _T_165) @[axi4_to_ahb.scala 198:30] + buf_cmd_byte_ptr <= _T_166 @[axi4_to_ahb.scala 198:24] + node _T_167 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 199:63] + node _T_168 = and(_T_167, buf_state_en) @[axi4_to_ahb.scala 199:78] + node _T_169 = eq(_T_168, UInt<1>("h00")) @[axi4_to_ahb.scala 199:47] node _T_170 = bits(_T_169, 0, 0) @[Bitwise.scala 72:15] node _T_171 = mux(_T_170, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_172 = and(UInt<2>("h02"), _T_171) @[axi4_to_ahb.scala 200:36] - io.ahb.out.htrans <= _T_172 @[axi4_to_ahb.scala 200:25] - slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 201:20] + node _T_172 = and(UInt<2>("h02"), _T_171) @[axi4_to_ahb.scala 199:36] + io.ahb.out.htrans <= _T_172 @[axi4_to_ahb.scala 199:25] + slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 200:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_173 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] when _T_173 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 205:20] - node _T_174 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 206:51] - node _T_175 = neq(_T_174, UInt<1>("h00")) @[axi4_to_ahb.scala 206:58] - node _T_176 = and(ahb_hready_q, _T_175) @[axi4_to_ahb.scala 206:36] - node _T_177 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 206:72] - node _T_178 = and(_T_176, _T_177) @[axi4_to_ahb.scala 206:70] - buf_state_en <= _T_178 @[axi4_to_ahb.scala 206:20] - slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 207:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 208:20] - node _T_179 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 209:35] - buf_cmd_byte_ptr <= _T_179 @[axi4_to_ahb.scala 209:24] - node _T_180 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 210:51] + buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 204:20] + node _T_174 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 205:51] + node _T_175 = neq(_T_174, UInt<1>("h00")) @[axi4_to_ahb.scala 205:58] + node _T_176 = and(ahb_hready_q, _T_175) @[axi4_to_ahb.scala 205:36] + node _T_177 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 205:72] + node _T_178 = and(_T_176, _T_177) @[axi4_to_ahb.scala 205:70] + buf_state_en <= _T_178 @[axi4_to_ahb.scala 205:20] + slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 206:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 207:20] + node _T_179 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 208:35] + buf_cmd_byte_ptr <= _T_179 @[axi4_to_ahb.scala 208:24] + node _T_180 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 209:51] node _T_181 = bits(_T_180, 0, 0) @[Bitwise.scala 72:15] node _T_182 = mux(_T_181, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_183 = and(UInt<2>("h02"), _T_182) @[axi4_to_ahb.scala 210:41] - io.ahb.out.htrans <= _T_183 @[axi4_to_ahb.scala 210:25] + node _T_183 = and(UInt<2>("h02"), _T_182) @[axi4_to_ahb.scala 209:41] + io.ahb.out.htrans <= _T_183 @[axi4_to_ahb.scala 209:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_184 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] when _T_184 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 214:20] - node _T_185 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 215:37] - buf_state_en <= _T_185 @[axi4_to_ahb.scala 215:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 216:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 217:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 218:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 219:20] + buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 213:20] + node _T_185 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 214:37] + buf_state_en <= _T_185 @[axi4_to_ahb.scala 214:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 215:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 216:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 217:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 218:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_186 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] when _T_186 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 223:20] - node _T_187 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 224:33] - node _T_188 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 224:63] - node _T_189 = neq(_T_188, UInt<1>("h00")) @[axi4_to_ahb.scala 224:70] - node _T_190 = and(_T_187, _T_189) @[axi4_to_ahb.scala 224:48] - trxn_done <= _T_190 @[axi4_to_ahb.scala 224:17] - buf_state_en <= trxn_done @[axi4_to_ahb.scala 225:20] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 226:27] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 227:20] - node _T_191 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 228:47] - node _T_192 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 228:85] - node _T_193 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 228:103] + buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 222:20] + node _T_187 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 223:33] + node _T_188 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 223:63] + node _T_189 = neq(_T_188, UInt<1>("h00")) @[axi4_to_ahb.scala 223:70] + node _T_190 = and(_T_187, _T_189) @[axi4_to_ahb.scala 223:48] + trxn_done <= _T_190 @[axi4_to_ahb.scala 223:17] + buf_state_en <= trxn_done @[axi4_to_ahb.scala 224:20] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 225:27] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 226:20] + node _T_191 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 227:47] + node _T_192 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 227:85] + node _T_193 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 227:103] node _T_194 = add(_T_192, UInt<1>("h01")) @[axi4_to_ahb.scala 136:52] node _T_195 = tail(_T_194, 1) @[axi4_to_ahb.scala 136:52] node _T_196 = mux(UInt<1>("h01"), _T_195, _T_192) @[axi4_to_ahb.scala 136:24] @@ -572,12 +572,12 @@ circuit axi4_to_ahb : node _T_226 = mux(_T_205, UInt<2>("h02"), _T_225) @[Mux.scala 98:16] node _T_227 = mux(_T_202, UInt<1>("h01"), _T_226) @[Mux.scala 98:16] node _T_228 = mux(_T_199, UInt<1>("h00"), _T_227) @[Mux.scala 98:16] - node _T_229 = mux(_T_191, _T_228, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 228:30] - buf_cmd_byte_ptr <= _T_229 @[axi4_to_ahb.scala 228:24] - node _T_230 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 229:65] - node _T_231 = or(buf_aligned, _T_230) @[axi4_to_ahb.scala 229:44] - node _T_232 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 229:127] - node _T_233 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 229:145] + node _T_229 = mux(_T_191, _T_228, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 227:30] + buf_cmd_byte_ptr <= _T_229 @[axi4_to_ahb.scala 227:24] + node _T_230 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 228:65] + node _T_231 = or(buf_aligned, _T_230) @[axi4_to_ahb.scala 228:44] + node _T_232 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 228:127] + node _T_233 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 228:145] node _T_234 = add(_T_232, UInt<1>("h01")) @[axi4_to_ahb.scala 136:52] node _T_235 = tail(_T_234, 1) @[axi4_to_ahb.scala 136:52] node _T_236 = mux(UInt<1>("h01"), _T_235, _T_232) @[axi4_to_ahb.scala 136:24] @@ -613,56 +613,56 @@ circuit axi4_to_ahb : node _T_266 = mux(_T_245, UInt<2>("h02"), _T_265) @[Mux.scala 98:16] node _T_267 = mux(_T_242, UInt<1>("h01"), _T_266) @[Mux.scala 98:16] node _T_268 = mux(_T_239, UInt<1>("h00"), _T_267) @[Mux.scala 98:16] - node _T_269 = dshr(buf_byteen, _T_268) @[axi4_to_ahb.scala 229:92] - node _T_270 = bits(_T_269, 0, 0) @[axi4_to_ahb.scala 229:92] - node _T_271 = eq(_T_270, UInt<1>("h00")) @[axi4_to_ahb.scala 229:163] - node _T_272 = or(_T_231, _T_271) @[axi4_to_ahb.scala 229:79] - node _T_273 = and(trxn_done, _T_272) @[axi4_to_ahb.scala 229:29] - cmd_done <= _T_273 @[axi4_to_ahb.scala 229:16] - node _T_274 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 230:47] - node _T_275 = eq(_T_274, UInt<1>("h00")) @[axi4_to_ahb.scala 230:36] + node _T_269 = dshr(buf_byteen, _T_268) @[axi4_to_ahb.scala 228:92] + node _T_270 = bits(_T_269, 0, 0) @[axi4_to_ahb.scala 228:92] + node _T_271 = eq(_T_270, UInt<1>("h00")) @[axi4_to_ahb.scala 228:163] + node _T_272 = or(_T_231, _T_271) @[axi4_to_ahb.scala 228:79] + node _T_273 = and(trxn_done, _T_272) @[axi4_to_ahb.scala 228:29] + cmd_done <= _T_273 @[axi4_to_ahb.scala 228:16] + node _T_274 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 229:47] + node _T_275 = eq(_T_274, UInt<1>("h00")) @[axi4_to_ahb.scala 229:36] node _T_276 = bits(_T_275, 0, 0) @[Bitwise.scala 72:15] node _T_277 = mux(_T_276, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_278 = and(_T_277, UInt<2>("h02")) @[axi4_to_ahb.scala 230:61] - io.ahb.out.htrans <= _T_278 @[axi4_to_ahb.scala 230:25] + node _T_278 = and(_T_277, UInt<2>("h02")) @[axi4_to_ahb.scala 229:61] + io.ahb.out.htrans <= _T_278 @[axi4_to_ahb.scala 229:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_279 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] when _T_279 : @[Conditional.scala 39:67] - node _T_280 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 234:34] - node _T_281 = or(_T_280, ahb_hresp_q) @[axi4_to_ahb.scala 234:50] - buf_state_en <= _T_281 @[axi4_to_ahb.scala 234:20] - node _T_282 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 235:38] - node _T_283 = and(buf_state_en, _T_282) @[axi4_to_ahb.scala 235:36] - node _T_284 = and(_T_283, slave_ready) @[axi4_to_ahb.scala 235:51] - master_ready <= _T_284 @[axi4_to_ahb.scala 235:20] - node _T_285 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 236:42] - node _T_286 = or(ahb_hresp_q, _T_285) @[axi4_to_ahb.scala 236:40] - node _T_287 = and(master_valid, master_valid) @[axi4_to_ahb.scala 236:81] - node _T_288 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 236:113] - node _T_289 = eq(_T_288, UInt<1>("h01")) @[axi4_to_ahb.scala 236:120] - node _T_290 = bits(_T_289, 0, 0) @[axi4_to_ahb.scala 236:135] - node _T_291 = mux(_T_290, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 236:101] - node _T_292 = mux(_T_287, _T_291, UInt<3>("h00")) @[axi4_to_ahb.scala 236:66] - node _T_293 = mux(_T_286, UInt<3>("h05"), _T_292) @[axi4_to_ahb.scala 236:26] - buf_nxtstate <= _T_293 @[axi4_to_ahb.scala 236:20] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 237:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 238:23] - node _T_294 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 239:33] - node _T_295 = eq(_T_294, UInt<1>("h01")) @[axi4_to_ahb.scala 239:40] - buf_write_in <= _T_295 @[axi4_to_ahb.scala 239:20] - node _T_296 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 240:50] - node _T_297 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 240:78] - node _T_298 = or(_T_296, _T_297) @[axi4_to_ahb.scala 240:62] - node _T_299 = and(buf_state_en, _T_298) @[axi4_to_ahb.scala 240:33] - buf_wr_en <= _T_299 @[axi4_to_ahb.scala 240:17] - buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 241:22] - node _T_300 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 242:63] - node _T_301 = neq(_T_300, UInt<1>("h00")) @[axi4_to_ahb.scala 242:70] - node _T_302 = and(ahb_hready_q, _T_301) @[axi4_to_ahb.scala 242:48] - node _T_303 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 243:29] - node _T_304 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 243:85] - node _T_305 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 243:103] + node _T_280 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 233:34] + node _T_281 = or(_T_280, ahb_hresp_q) @[axi4_to_ahb.scala 233:50] + buf_state_en <= _T_281 @[axi4_to_ahb.scala 233:20] + node _T_282 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 234:38] + node _T_283 = and(buf_state_en, _T_282) @[axi4_to_ahb.scala 234:36] + node _T_284 = and(_T_283, slave_ready) @[axi4_to_ahb.scala 234:51] + master_ready <= _T_284 @[axi4_to_ahb.scala 234:20] + node _T_285 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 235:42] + node _T_286 = or(ahb_hresp_q, _T_285) @[axi4_to_ahb.scala 235:40] + node _T_287 = and(master_valid, master_valid) @[axi4_to_ahb.scala 235:81] + node _T_288 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 235:113] + node _T_289 = eq(_T_288, UInt<1>("h01")) @[axi4_to_ahb.scala 235:120] + node _T_290 = bits(_T_289, 0, 0) @[axi4_to_ahb.scala 235:135] + node _T_291 = mux(_T_290, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 235:101] + node _T_292 = mux(_T_287, _T_291, UInt<3>("h00")) @[axi4_to_ahb.scala 235:66] + node _T_293 = mux(_T_286, UInt<3>("h05"), _T_292) @[axi4_to_ahb.scala 235:26] + buf_nxtstate <= _T_293 @[axi4_to_ahb.scala 235:20] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 236:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 237:23] + node _T_294 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 238:33] + node _T_295 = eq(_T_294, UInt<1>("h01")) @[axi4_to_ahb.scala 238:40] + buf_write_in <= _T_295 @[axi4_to_ahb.scala 238:20] + node _T_296 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 239:50] + node _T_297 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 239:78] + node _T_298 = or(_T_296, _T_297) @[axi4_to_ahb.scala 239:62] + node _T_299 = and(buf_state_en, _T_298) @[axi4_to_ahb.scala 239:33] + buf_wr_en <= _T_299 @[axi4_to_ahb.scala 239:17] + buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 240:22] + node _T_300 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 241:63] + node _T_301 = neq(_T_300, UInt<1>("h00")) @[axi4_to_ahb.scala 241:70] + node _T_302 = and(ahb_hready_q, _T_301) @[axi4_to_ahb.scala 241:48] + node _T_303 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 242:29] + node _T_304 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 242:85] + node _T_305 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 242:103] node _T_306 = add(_T_304, UInt<1>("h01")) @[axi4_to_ahb.scala 136:52] node _T_307 = tail(_T_306, 1) @[axi4_to_ahb.scala 136:52] node _T_308 = mux(UInt<1>("h01"), _T_307, _T_304) @[axi4_to_ahb.scala 136:24] @@ -698,35 +698,35 @@ circuit axi4_to_ahb : node _T_338 = mux(_T_317, UInt<2>("h02"), _T_337) @[Mux.scala 98:16] node _T_339 = mux(_T_314, UInt<1>("h01"), _T_338) @[Mux.scala 98:16] node _T_340 = mux(_T_311, UInt<1>("h00"), _T_339) @[Mux.scala 98:16] - node _T_341 = dshr(buf_byteen, _T_340) @[axi4_to_ahb.scala 243:51] - node _T_342 = bits(_T_341, 0, 0) @[axi4_to_ahb.scala 243:51] - node _T_343 = eq(_T_342, UInt<1>("h00")) @[axi4_to_ahb.scala 243:120] - node _T_344 = or(_T_303, _T_343) @[axi4_to_ahb.scala 243:38] - node _T_345 = and(_T_302, _T_344) @[axi4_to_ahb.scala 242:79] - node _T_346 = or(ahb_hresp_q, _T_345) @[axi4_to_ahb.scala 242:32] - cmd_done <= _T_346 @[axi4_to_ahb.scala 242:16] - node _T_347 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 244:33] - node _T_348 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 244:64] - node _T_349 = and(_T_347, _T_348) @[axi4_to_ahb.scala 244:48] - bypass_en <= _T_349 @[axi4_to_ahb.scala 244:17] - node _T_350 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 245:48] - node _T_351 = eq(_T_350, UInt<1>("h00")) @[axi4_to_ahb.scala 245:37] - node _T_352 = or(_T_351, bypass_en) @[axi4_to_ahb.scala 245:61] + node _T_341 = dshr(buf_byteen, _T_340) @[axi4_to_ahb.scala 242:51] + node _T_342 = bits(_T_341, 0, 0) @[axi4_to_ahb.scala 242:51] + node _T_343 = eq(_T_342, UInt<1>("h00")) @[axi4_to_ahb.scala 242:120] + node _T_344 = or(_T_303, _T_343) @[axi4_to_ahb.scala 242:38] + node _T_345 = and(_T_302, _T_344) @[axi4_to_ahb.scala 241:79] + node _T_346 = or(ahb_hresp_q, _T_345) @[axi4_to_ahb.scala 241:32] + cmd_done <= _T_346 @[axi4_to_ahb.scala 241:16] + node _T_347 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 243:33] + node _T_348 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 243:64] + node _T_349 = and(_T_347, _T_348) @[axi4_to_ahb.scala 243:48] + bypass_en <= _T_349 @[axi4_to_ahb.scala 243:17] + node _T_350 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 244:48] + node _T_351 = eq(_T_350, UInt<1>("h00")) @[axi4_to_ahb.scala 244:37] + node _T_352 = or(_T_351, bypass_en) @[axi4_to_ahb.scala 244:61] node _T_353 = bits(_T_352, 0, 0) @[Bitwise.scala 72:15] node _T_354 = mux(_T_353, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_355 = and(_T_354, UInt<2>("h02")) @[axi4_to_ahb.scala 245:75] - io.ahb.out.htrans <= _T_355 @[axi4_to_ahb.scala 245:25] - node _T_356 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 246:55] - node _T_357 = and(buf_state_en, _T_356) @[axi4_to_ahb.scala 246:39] - slave_valid_pre <= _T_357 @[axi4_to_ahb.scala 246:23] - node _T_358 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 247:33] - node _T_359 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 247:63] - node _T_360 = neq(_T_359, UInt<1>("h00")) @[axi4_to_ahb.scala 247:70] - node _T_361 = and(_T_358, _T_360) @[axi4_to_ahb.scala 247:48] - trxn_done <= _T_361 @[axi4_to_ahb.scala 247:17] - node _T_362 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 248:40] - buf_cmd_byte_ptr_en <= _T_362 @[axi4_to_ahb.scala 248:27] - node _T_363 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 249:81] + node _T_355 = and(_T_354, UInt<2>("h02")) @[axi4_to_ahb.scala 244:75] + io.ahb.out.htrans <= _T_355 @[axi4_to_ahb.scala 244:25] + node _T_356 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 245:55] + node _T_357 = and(buf_state_en, _T_356) @[axi4_to_ahb.scala 245:39] + slave_valid_pre <= _T_357 @[axi4_to_ahb.scala 245:23] + node _T_358 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 246:33] + node _T_359 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 246:63] + node _T_360 = neq(_T_359, UInt<1>("h00")) @[axi4_to_ahb.scala 246:70] + node _T_361 = and(_T_358, _T_360) @[axi4_to_ahb.scala 246:48] + trxn_done <= _T_361 @[axi4_to_ahb.scala 246:17] + node _T_362 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 247:40] + buf_cmd_byte_ptr_en <= _T_362 @[axi4_to_ahb.scala 247:27] + node _T_363 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 248:81] node _T_364 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 136:52] node _T_365 = tail(_T_364, 1) @[axi4_to_ahb.scala 136:52] node _T_366 = mux(UInt<1>("h00"), _T_365, UInt<3>("h00")) @[axi4_to_ahb.scala 136:24] @@ -762,8 +762,8 @@ circuit axi4_to_ahb : node _T_396 = mux(_T_375, UInt<2>("h02"), _T_395) @[Mux.scala 98:16] node _T_397 = mux(_T_372, UInt<1>("h01"), _T_396) @[Mux.scala 98:16] node _T_398 = mux(_T_369, UInt<1>("h00"), _T_397) @[Mux.scala 98:16] - node _T_399 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 249:147] - node _T_400 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 249:165] + node _T_399 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 248:147] + node _T_400 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 248:165] node _T_401 = add(_T_399, UInt<1>("h01")) @[axi4_to_ahb.scala 136:52] node _T_402 = tail(_T_401, 1) @[axi4_to_ahb.scala 136:52] node _T_403 = mux(UInt<1>("h01"), _T_402, _T_399) @[axi4_to_ahb.scala 136:24] @@ -799,25 +799,25 @@ circuit axi4_to_ahb : node _T_433 = mux(_T_412, UInt<2>("h02"), _T_432) @[Mux.scala 98:16] node _T_434 = mux(_T_409, UInt<1>("h01"), _T_433) @[Mux.scala 98:16] node _T_435 = mux(_T_406, UInt<1>("h00"), _T_434) @[Mux.scala 98:16] - node _T_436 = mux(trxn_done, _T_435, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 249:102] - node _T_437 = mux(bypass_en, _T_398, _T_436) @[axi4_to_ahb.scala 249:30] - buf_cmd_byte_ptr <= _T_437 @[axi4_to_ahb.scala 249:24] + node _T_436 = mux(trxn_done, _T_435, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 248:102] + node _T_437 = mux(bypass_en, _T_398, _T_436) @[axi4_to_ahb.scala 248:30] + buf_cmd_byte_ptr <= _T_437 @[axi4_to_ahb.scala 248:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_438 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] when _T_438 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 252:20] - buf_state_en <= slave_ready @[axi4_to_ahb.scala 253:20] - slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 254:23] - slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 255:23] + buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 251:20] + buf_state_en <= slave_ready @[axi4_to_ahb.scala 252:20] + slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 253:23] + slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 254:23] skip @[Conditional.scala 39:67] - cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 259:16] - node _T_439 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 260:33] - node _T_440 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 260:75] - node _T_441 = eq(_T_440, UInt<1>("h01")) @[axi4_to_ahb.scala 260:82] - node _T_442 = and(buf_aligned_in, _T_441) @[axi4_to_ahb.scala 260:62] - node _T_443 = bits(_T_442, 0, 0) @[axi4_to_ahb.scala 260:102] - node _T_444 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 260:134] + cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 258:16] + node _T_439 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 259:33] + node _T_440 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 259:75] + node _T_441 = eq(_T_440, UInt<1>("h01")) @[axi4_to_ahb.scala 259:82] + node _T_442 = and(buf_aligned_in, _T_441) @[axi4_to_ahb.scala 259:62] + node _T_443 = bits(_T_442, 0, 0) @[axi4_to_ahb.scala 259:102] + node _T_444 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 259:134] node _T_445 = bits(_T_444, 7, 0) @[axi4_to_ahb.scala 127:50] node _T_446 = eq(_T_445, UInt<8>("h0ff")) @[axi4_to_ahb.scala 127:57] node _T_447 = bits(_T_444, 7, 0) @[axi4_to_ahb.scala 127:81] @@ -855,27 +855,27 @@ circuit axi4_to_ahb : node _T_479 = bits(_T_478, 0, 0) @[Bitwise.scala 72:15] node _T_480 = mux(_T_479, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] node _T_481 = and(UInt<3>("h06"), _T_480) @[axi4_to_ahb.scala 131:13] - node _T_482 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 260:154] - node _T_483 = mux(_T_443, _T_476, _T_482) @[axi4_to_ahb.scala 260:45] + node _T_482 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 259:154] + node _T_483 = mux(_T_443, _T_476, _T_482) @[axi4_to_ahb.scala 259:45] node _T_484 = cat(_T_439, _T_483) @[Cat.scala 29:58] - buf_addr_in <= _T_484 @[axi4_to_ahb.scala 260:15] - node _T_485 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 261:27] - buf_tag_in <= _T_485 @[axi4_to_ahb.scala 261:14] - node _T_486 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 262:32] - buf_byteen_in <= _T_486 @[axi4_to_ahb.scala 262:17] - node _T_487 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 263:33] - node _T_488 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 263:59] - node _T_489 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 263:80] - node _T_490 = mux(_T_487, _T_488, _T_489) @[axi4_to_ahb.scala 263:21] - buf_data_in <= _T_490 @[axi4_to_ahb.scala 263:15] - node _T_491 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 264:52] - node _T_492 = eq(_T_491, UInt<2>("h03")) @[axi4_to_ahb.scala 264:59] - node _T_493 = and(buf_aligned_in, _T_492) @[axi4_to_ahb.scala 264:38] - node _T_494 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 264:85] - node _T_495 = eq(_T_494, UInt<1>("h01")) @[axi4_to_ahb.scala 264:92] - node _T_496 = and(_T_493, _T_495) @[axi4_to_ahb.scala 264:72] - node _T_497 = bits(_T_496, 0, 0) @[axi4_to_ahb.scala 264:112] - node _T_498 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 264:144] + buf_addr_in <= _T_484 @[axi4_to_ahb.scala 259:15] + node _T_485 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 260:27] + buf_tag_in <= _T_485 @[axi4_to_ahb.scala 260:14] + node _T_486 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 261:32] + buf_byteen_in <= _T_486 @[axi4_to_ahb.scala 261:17] + node _T_487 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 262:33] + node _T_488 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 262:59] + node _T_489 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 262:80] + node _T_490 = mux(_T_487, _T_488, _T_489) @[axi4_to_ahb.scala 262:21] + buf_data_in <= _T_490 @[axi4_to_ahb.scala 262:15] + node _T_491 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 263:52] + node _T_492 = eq(_T_491, UInt<2>("h03")) @[axi4_to_ahb.scala 263:59] + node _T_493 = and(buf_aligned_in, _T_492) @[axi4_to_ahb.scala 263:38] + node _T_494 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 263:85] + node _T_495 = eq(_T_494, UInt<1>("h01")) @[axi4_to_ahb.scala 263:92] + node _T_496 = and(_T_493, _T_495) @[axi4_to_ahb.scala 263:72] + node _T_497 = bits(_T_496, 0, 0) @[axi4_to_ahb.scala 263:112] + node _T_498 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 263:144] node _T_499 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 120:42] node _T_500 = eq(_T_499, UInt<8>("h0ff")) @[axi4_to_ahb.scala 120:49] node _T_501 = bits(_T_500, 0, 0) @[Bitwise.scala 72:15] @@ -905,136 +905,136 @@ circuit axi4_to_ahb : node _T_525 = mux(_T_524, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] node _T_526 = and(UInt<2>("h01"), _T_525) @[axi4_to_ahb.scala 122:21] node _T_527 = or(_T_512, _T_526) @[axi4_to_ahb.scala 121:93] - node _T_528 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 264:164] - node _T_529 = mux(_T_497, _T_527, _T_528) @[axi4_to_ahb.scala 264:21] - buf_size_in <= _T_529 @[axi4_to_ahb.scala 264:15] - node _T_530 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 265:32] - node _T_531 = eq(_T_530, UInt<1>("h00")) @[axi4_to_ahb.scala 265:39] - node _T_532 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 266:17] - node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 266:24] - node _T_534 = or(_T_531, _T_533) @[axi4_to_ahb.scala 265:48] - node _T_535 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 266:47] - node _T_536 = eq(_T_535, UInt<2>("h01")) @[axi4_to_ahb.scala 266:54] - node _T_537 = or(_T_534, _T_536) @[axi4_to_ahb.scala 266:33] - node _T_538 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 266:86] - node _T_539 = eq(_T_538, UInt<2>("h02")) @[axi4_to_ahb.scala 266:93] - node _T_540 = or(_T_537, _T_539) @[axi4_to_ahb.scala 266:72] - node _T_541 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 267:18] - node _T_542 = eq(_T_541, UInt<2>("h03")) @[axi4_to_ahb.scala 267:25] - node _T_543 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 267:55] - node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 267:62] - node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 267:90] - node _T_546 = eq(_T_545, UInt<4>("h0c")) @[axi4_to_ahb.scala 267:97] - node _T_547 = or(_T_544, _T_546) @[axi4_to_ahb.scala 267:74] - node _T_548 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 267:125] - node _T_549 = eq(_T_548, UInt<6>("h030")) @[axi4_to_ahb.scala 267:132] - node _T_550 = or(_T_547, _T_549) @[axi4_to_ahb.scala 267:109] - node _T_551 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 267:161] - node _T_552 = eq(_T_551, UInt<8>("h0c0")) @[axi4_to_ahb.scala 267:168] - node _T_553 = or(_T_550, _T_552) @[axi4_to_ahb.scala 267:145] - node _T_554 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 268:21] - node _T_555 = eq(_T_554, UInt<4>("h0f")) @[axi4_to_ahb.scala 268:28] - node _T_556 = or(_T_553, _T_555) @[axi4_to_ahb.scala 267:181] - node _T_557 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 268:56] - node _T_558 = eq(_T_557, UInt<8>("h0f0")) @[axi4_to_ahb.scala 268:63] - node _T_559 = or(_T_556, _T_558) @[axi4_to_ahb.scala 268:40] - node _T_560 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 268:92] - node _T_561 = eq(_T_560, UInt<8>("h0ff")) @[axi4_to_ahb.scala 268:99] - node _T_562 = or(_T_559, _T_561) @[axi4_to_ahb.scala 268:76] - node _T_563 = and(_T_542, _T_562) @[axi4_to_ahb.scala 267:38] - node _T_564 = or(_T_540, _T_563) @[axi4_to_ahb.scala 266:106] - buf_aligned_in <= _T_564 @[axi4_to_ahb.scala 265:18] - node _T_565 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 270:47] - node _T_566 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 270:62] - node _T_567 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 270:79] - node _T_568 = mux(_T_565, _T_566, _T_567) @[axi4_to_ahb.scala 270:30] - node _T_569 = eq(io.ahb.out.htrans, UInt<2>("h02")) @[axi4_to_ahb.scala 270:115] + node _T_528 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 263:164] + node _T_529 = mux(_T_497, _T_527, _T_528) @[axi4_to_ahb.scala 263:21] + buf_size_in <= _T_529 @[axi4_to_ahb.scala 263:15] + node _T_530 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 264:32] + node _T_531 = eq(_T_530, UInt<1>("h00")) @[axi4_to_ahb.scala 264:39] + node _T_532 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 265:17] + node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 265:24] + node _T_534 = or(_T_531, _T_533) @[axi4_to_ahb.scala 264:48] + node _T_535 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 265:47] + node _T_536 = eq(_T_535, UInt<2>("h01")) @[axi4_to_ahb.scala 265:54] + node _T_537 = or(_T_534, _T_536) @[axi4_to_ahb.scala 265:33] + node _T_538 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 265:86] + node _T_539 = eq(_T_538, UInt<2>("h02")) @[axi4_to_ahb.scala 265:93] + node _T_540 = or(_T_537, _T_539) @[axi4_to_ahb.scala 265:72] + node _T_541 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 266:18] + node _T_542 = eq(_T_541, UInt<2>("h03")) @[axi4_to_ahb.scala 266:25] + node _T_543 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 266:55] + node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 266:62] + node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 266:90] + node _T_546 = eq(_T_545, UInt<4>("h0c")) @[axi4_to_ahb.scala 266:97] + node _T_547 = or(_T_544, _T_546) @[axi4_to_ahb.scala 266:74] + node _T_548 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 266:125] + node _T_549 = eq(_T_548, UInt<6>("h030")) @[axi4_to_ahb.scala 266:132] + node _T_550 = or(_T_547, _T_549) @[axi4_to_ahb.scala 266:109] + node _T_551 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 266:161] + node _T_552 = eq(_T_551, UInt<8>("h0c0")) @[axi4_to_ahb.scala 266:168] + node _T_553 = or(_T_550, _T_552) @[axi4_to_ahb.scala 266:145] + node _T_554 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 267:21] + node _T_555 = eq(_T_554, UInt<4>("h0f")) @[axi4_to_ahb.scala 267:28] + node _T_556 = or(_T_553, _T_555) @[axi4_to_ahb.scala 266:181] + node _T_557 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 267:56] + node _T_558 = eq(_T_557, UInt<8>("h0f0")) @[axi4_to_ahb.scala 267:63] + node _T_559 = or(_T_556, _T_558) @[axi4_to_ahb.scala 267:40] + node _T_560 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 267:92] + node _T_561 = eq(_T_560, UInt<8>("h0ff")) @[axi4_to_ahb.scala 267:99] + node _T_562 = or(_T_559, _T_561) @[axi4_to_ahb.scala 267:76] + node _T_563 = and(_T_542, _T_562) @[axi4_to_ahb.scala 266:38] + node _T_564 = or(_T_540, _T_563) @[axi4_to_ahb.scala 265:106] + buf_aligned_in <= _T_564 @[axi4_to_ahb.scala 264:18] + node _T_565 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 269:47] + node _T_566 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 269:62] + node _T_567 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 269:79] + node _T_568 = mux(_T_565, _T_566, _T_567) @[axi4_to_ahb.scala 269:30] + node _T_569 = eq(io.ahb.out.htrans, UInt<2>("h02")) @[axi4_to_ahb.scala 269:115] node _T_570 = bits(_T_569, 0, 0) @[Bitwise.scala 72:15] node _T_571 = mux(_T_570, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_572 = and(_T_571, buf_cmd_byte_ptr) @[axi4_to_ahb.scala 270:124] + node _T_572 = and(_T_571, buf_cmd_byte_ptr) @[axi4_to_ahb.scala 269:124] node _T_573 = cat(_T_568, _T_572) @[Cat.scala 29:58] - io.ahb.out.haddr <= _T_573 @[axi4_to_ahb.scala 270:20] - node _T_574 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 271:43] + io.ahb.out.haddr <= _T_573 @[axi4_to_ahb.scala 269:20] + node _T_574 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 270:43] node _T_575 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] node _T_576 = mux(_T_575, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_577 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 271:94] - node _T_578 = and(_T_576, _T_577) @[axi4_to_ahb.scala 271:81] + node _T_577 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 270:94] + node _T_578 = and(_T_576, _T_577) @[axi4_to_ahb.scala 270:81] node _T_579 = cat(UInt<1>("h00"), _T_578) @[Cat.scala 29:58] node _T_580 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] node _T_581 = mux(_T_580, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_582 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 271:148] - node _T_583 = and(_T_581, _T_582) @[axi4_to_ahb.scala 271:138] + node _T_582 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 270:148] + node _T_583 = and(_T_581, _T_582) @[axi4_to_ahb.scala 270:138] node _T_584 = cat(UInt<1>("h00"), _T_583) @[Cat.scala 29:58] - node _T_585 = mux(_T_574, _T_579, _T_584) @[axi4_to_ahb.scala 271:26] - io.ahb.out.hsize <= _T_585 @[axi4_to_ahb.scala 271:20] - io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 273:21] - io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 274:24] - node _T_586 = bits(io.axi.ar.bits.prot, 2, 2) @[axi4_to_ahb.scala 275:57] - node _T_587 = eq(_T_586, UInt<1>("h00")) @[axi4_to_ahb.scala 275:37] + node _T_585 = mux(_T_574, _T_579, _T_584) @[axi4_to_ahb.scala 270:26] + io.ahb.out.hsize <= _T_585 @[axi4_to_ahb.scala 270:20] + io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 272:21] + io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 273:24] + node _T_586 = bits(io.axi.ar.bits.prot, 2, 2) @[axi4_to_ahb.scala 274:57] + node _T_587 = eq(_T_586, UInt<1>("h00")) @[axi4_to_ahb.scala 274:37] node _T_588 = cat(UInt<1>("h01"), _T_587) @[Cat.scala 29:58] - io.ahb.out.hprot <= _T_588 @[axi4_to_ahb.scala 275:20] - node _T_589 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 276:44] - node _T_590 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 276:59] - node _T_591 = eq(_T_590, UInt<1>("h01")) @[axi4_to_ahb.scala 276:66] - node _T_592 = mux(_T_589, _T_591, buf_write) @[axi4_to_ahb.scala 276:27] - io.ahb.out.hwrite <= _T_592 @[axi4_to_ahb.scala 276:21] - node _T_593 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 277:32] - io.ahb.out.hwdata <= _T_593 @[axi4_to_ahb.scala 277:21] - slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 279:15] - node _T_594 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 280:43] - node _T_595 = mux(_T_594, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 280:23] + io.ahb.out.hprot <= _T_588 @[axi4_to_ahb.scala 274:20] + node _T_589 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 275:44] + node _T_590 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 275:59] + node _T_591 = eq(_T_590, UInt<1>("h01")) @[axi4_to_ahb.scala 275:66] + node _T_592 = mux(_T_589, _T_591, buf_write) @[axi4_to_ahb.scala 275:27] + io.ahb.out.hwrite <= _T_592 @[axi4_to_ahb.scala 275:21] + node _T_593 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 276:32] + io.ahb.out.hwdata <= _T_593 @[axi4_to_ahb.scala 276:21] + slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 278:15] + node _T_594 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 279:43] + node _T_595 = mux(_T_594, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 279:23] node _T_596 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] node _T_597 = mux(_T_596, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_598 = and(_T_597, UInt<2>("h02")) @[axi4_to_ahb.scala 280:88] + node _T_598 = and(_T_597, UInt<2>("h02")) @[axi4_to_ahb.scala 279:88] node _T_599 = cat(_T_595, _T_598) @[Cat.scala 29:58] - slave_opc <= _T_599 @[axi4_to_ahb.scala 280:13] - node _T_600 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 281:41] - node _T_601 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 281:66] + slave_opc <= _T_599 @[axi4_to_ahb.scala 279:13] + node _T_600 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 280:41] + node _T_601 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 280:66] node _T_602 = cat(_T_601, _T_601) @[Cat.scala 29:58] - node _T_603 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 281:91] - node _T_604 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 281:110] - node _T_605 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 281:131] - node _T_606 = mux(_T_603, _T_604, _T_605) @[axi4_to_ahb.scala 281:79] - node _T_607 = mux(_T_600, _T_602, _T_606) @[axi4_to_ahb.scala 281:21] - slave_rdata <= _T_607 @[axi4_to_ahb.scala 281:15] - node _T_608 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 282:26] - slave_tag <= _T_608 @[axi4_to_ahb.scala 282:13] - node _T_609 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 284:37] - node _T_610 = neq(_T_609, UInt<1>("h00")) @[axi4_to_ahb.scala 284:44] - node _T_611 = and(_T_610, io.ahb.in.hready) @[axi4_to_ahb.scala 284:56] - node _T_612 = and(_T_611, io.ahb.out.hwrite) @[axi4_to_ahb.scala 284:75] - last_addr_en <= _T_612 @[axi4_to_ahb.scala 284:16] - node _T_613 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 286:31] - node _T_614 = and(_T_613, master_ready) @[axi4_to_ahb.scala 286:49] - wrbuf_en <= _T_614 @[axi4_to_ahb.scala 286:12] - node _T_615 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 287:35] - node _T_616 = and(_T_615, master_ready) @[axi4_to_ahb.scala 287:52] - wrbuf_data_en <= _T_616 @[axi4_to_ahb.scala 287:17] - node _T_617 = and(master_valid, master_ready) @[axi4_to_ahb.scala 288:34] - node _T_618 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 288:62] - node _T_619 = eq(_T_618, UInt<1>("h01")) @[axi4_to_ahb.scala 288:69] - node _T_620 = and(_T_617, _T_619) @[axi4_to_ahb.scala 288:49] - wrbuf_cmd_sent <= _T_620 @[axi4_to_ahb.scala 288:18] - node _T_621 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 289:34] - node _T_622 = and(wrbuf_cmd_sent, _T_621) @[axi4_to_ahb.scala 289:32] - node _T_623 = or(_T_622, dec_tlu_force_halt_bus) @[axi4_to_ahb.scala 289:45] - wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 289:13] - node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 291:36] - node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 291:34] - node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 291:22] - node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 291:53] - io.axi.aw.ready <= _T_627 @[axi4_to_ahb.scala 291:19] - node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 292:40] - node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 292:38] - node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 292:21] - node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 292:57] - io.axi.w.ready <= _T_631 @[axi4_to_ahb.scala 292:18] - node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 293:34] - node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 293:22] - node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 293:52] - io.axi.ar.ready <= _T_634 @[axi4_to_ahb.scala 293:19] - io.axi.r.bits.last <= UInt<1>("h01") @[axi4_to_ahb.scala 294:22] - node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 296:49] + node _T_603 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 280:91] + node _T_604 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 280:110] + node _T_605 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 280:131] + node _T_606 = mux(_T_603, _T_604, _T_605) @[axi4_to_ahb.scala 280:79] + node _T_607 = mux(_T_600, _T_602, _T_606) @[axi4_to_ahb.scala 280:21] + slave_rdata <= _T_607 @[axi4_to_ahb.scala 280:15] + node _T_608 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 281:26] + slave_tag <= _T_608 @[axi4_to_ahb.scala 281:13] + node _T_609 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 283:37] + node _T_610 = neq(_T_609, UInt<1>("h00")) @[axi4_to_ahb.scala 283:44] + node _T_611 = and(_T_610, io.ahb.in.hready) @[axi4_to_ahb.scala 283:56] + node _T_612 = and(_T_611, io.ahb.out.hwrite) @[axi4_to_ahb.scala 283:75] + last_addr_en <= _T_612 @[axi4_to_ahb.scala 283:16] + node _T_613 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 285:31] + node _T_614 = and(_T_613, master_ready) @[axi4_to_ahb.scala 285:49] + wrbuf_en <= _T_614 @[axi4_to_ahb.scala 285:12] + node _T_615 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 286:35] + node _T_616 = and(_T_615, master_ready) @[axi4_to_ahb.scala 286:52] + wrbuf_data_en <= _T_616 @[axi4_to_ahb.scala 286:17] + node _T_617 = and(master_valid, master_ready) @[axi4_to_ahb.scala 287:34] + node _T_618 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 287:62] + node _T_619 = eq(_T_618, UInt<1>("h01")) @[axi4_to_ahb.scala 287:69] + node _T_620 = and(_T_617, _T_619) @[axi4_to_ahb.scala 287:49] + wrbuf_cmd_sent <= _T_620 @[axi4_to_ahb.scala 287:18] + node _T_621 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 288:34] + node _T_622 = and(wrbuf_cmd_sent, _T_621) @[axi4_to_ahb.scala 288:32] + node _T_623 = or(_T_622, dec_tlu_force_halt_bus) @[axi4_to_ahb.scala 288:45] + wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 288:13] + node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 290:36] + node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 290:34] + node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 290:22] + node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 290:53] + io.axi.aw.ready <= _T_627 @[axi4_to_ahb.scala 290:19] + node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 291:40] + node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 291:38] + node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 291:21] + node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 291:57] + io.axi.w.ready <= _T_631 @[axi4_to_ahb.scala 291:18] + node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 292:34] + node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 292:22] + node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 292:52] + io.axi.ar.ready <= _T_634 @[axi4_to_ahb.scala 292:19] + io.axi.r.bits.last <= UInt<1>("h01") @[axi4_to_ahb.scala 293:22] + node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 295:49] wire _T_636 : UInt @[lib.scala 389:21] node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[lib.scala 391:75] node _T_638 = and(UInt<1>("h01"), _T_637) @[lib.scala 391:53] @@ -1046,8 +1046,8 @@ circuit axi4_to_ahb : _T_642 <= _T_638 @[Reg.scala 28:23] skip @[Reg.scala 28:19] _T_636 <= _T_642 @[lib.scala 391:14] - wrbuf_vld <= _T_636 @[axi4_to_ahb.scala 296:13] - node _T_643 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 297:59] + wrbuf_vld <= _T_636 @[axi4_to_ahb.scala 295:13] + node _T_643 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 296:59] wire _T_644 : UInt @[lib.scala 389:21] node _T_645 = eq(wrbuf_rst, UInt<1>("h00")) @[lib.scala 391:75] node _T_646 = and(UInt<1>("h01"), _T_645) @[lib.scala 391:53] @@ -1059,25 +1059,25 @@ circuit axi4_to_ahb : _T_650 <= _T_646 @[Reg.scala 28:23] skip @[Reg.scala 28:19] _T_644 <= _T_650 @[lib.scala 391:14] - wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 297:18] - node _T_651 = bits(io.axi.aw.bits.id, 0, 0) @[axi4_to_ahb.scala 298:45] - node _T_652 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 298:74] + wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 296:18] + node _T_651 = bits(io.axi.aw.bits.id, 0, 0) @[axi4_to_ahb.scala 297:45] + node _T_652 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 297:74] node _T_653 = and(io.bus_clk_en, _T_652) @[lib.scala 383:57] reg _T_654 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_653 : @[Reg.scala 28:19] _T_654 <= _T_651 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_tag <= _T_654 @[axi4_to_ahb.scala 298:13] - node _T_655 = bits(io.axi.aw.bits.size, 2, 0) @[axi4_to_ahb.scala 299:48] - node _T_656 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 299:71] + wrbuf_tag <= _T_654 @[axi4_to_ahb.scala 297:13] + node _T_655 = bits(io.axi.aw.bits.size, 2, 0) @[axi4_to_ahb.scala 298:48] + node _T_656 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 298:71] node _T_657 = and(io.bus_clk_en, _T_656) @[lib.scala 383:57] reg _T_658 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_657 : @[Reg.scala 28:19] _T_658 <= _T_655 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_size <= _T_658 @[axi4_to_ahb.scala 299:14] - node _T_659 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 300:54] - node _T_660 = and(_T_659, io.bus_clk_en) @[axi4_to_ahb.scala 300:61] + wrbuf_size <= _T_658 @[axi4_to_ahb.scala 298:14] + node _T_659 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 299:54] + node _T_660 = and(_T_659, io.bus_clk_en) @[axi4_to_ahb.scala 299:61] inst rvclkhdr of rvclkhdr @[lib.scala 399:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset @@ -1088,9 +1088,9 @@ circuit axi4_to_ahb : when _T_660 : @[Reg.scala 28:19] _T_661 <= io.axi.aw.bits.addr @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_addr <= _T_661 @[axi4_to_ahb.scala 300:14] - node _T_662 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 301:58] - node _T_663 = and(_T_662, io.bus_clk_en) @[axi4_to_ahb.scala 301:65] + wrbuf_addr <= _T_661 @[axi4_to_ahb.scala 299:14] + node _T_662 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 300:58] + node _T_663 = and(_T_662, io.bus_clk_en) @[axi4_to_ahb.scala 300:65] inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 399:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset @@ -1101,41 +1101,41 @@ circuit axi4_to_ahb : when _T_663 : @[Reg.scala 28:19] _T_664 <= io.axi.w.bits.data @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_data <= _T_664 @[axi4_to_ahb.scala 301:14] - node _T_665 = bits(io.axi.w.bits.strb, 7, 0) @[axi4_to_ahb.scala 302:49] - node _T_666 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 302:77] + wrbuf_data <= _T_664 @[axi4_to_ahb.scala 300:14] + node _T_665 = bits(io.axi.w.bits.strb, 7, 0) @[axi4_to_ahb.scala 301:49] + node _T_666 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 301:77] node _T_667 = and(io.bus_clk_en, _T_666) @[lib.scala 383:57] reg _T_668 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_667 : @[Reg.scala 28:19] _T_668 <= _T_665 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_byteen <= _T_668 @[axi4_to_ahb.scala 302:16] - node _T_669 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 303:48] - node _T_670 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 303:76] + wrbuf_byteen <= _T_668 @[axi4_to_ahb.scala 301:16] + node _T_669 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 302:48] + node _T_670 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 302:76] node _T_671 = and(io.bus_clk_en, _T_670) @[lib.scala 383:57] reg _T_672 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_671 : @[Reg.scala 28:19] _T_672 <= _T_669 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - last_bus_addr <= _T_672 @[axi4_to_ahb.scala 303:17] - node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 304:58] + last_bus_addr <= _T_672 @[axi4_to_ahb.scala 302:17] + node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 303:66] node _T_674 = and(buf_clken, _T_673) @[lib.scala 383:57] reg _T_675 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_674 : @[Reg.scala 28:19] _T_675 <= buf_write_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_write <= _T_675 @[axi4_to_ahb.scala 304:13] - node _T_676 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 305:36] - node _T_677 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 305:66] + buf_write <= _T_675 @[axi4_to_ahb.scala 303:21] + node _T_676 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 304:46] + node _T_677 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 304:76] node _T_678 = and(buf_clken, _T_677) @[lib.scala 383:57] reg _T_679 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_678 : @[Reg.scala 28:19] _T_679 <= _T_676 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_tag <= _T_679 @[axi4_to_ahb.scala 305:11] - node _T_680 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 306:33] - node _T_681 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 306:53] - node _T_682 = bits(_T_681, 0, 0) @[axi4_to_ahb.scala 306:70] + buf_tag <= _T_679 @[axi4_to_ahb.scala 304:21] + node _T_680 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 305:42] + node _T_681 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 305:62] + node _T_682 = bits(_T_681, 0, 0) @[axi4_to_ahb.scala 305:79] inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 399:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -1146,33 +1146,33 @@ circuit axi4_to_ahb : when _T_682 : @[Reg.scala 28:19] _T_683 <= _T_680 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_addr <= _T_683 @[axi4_to_ahb.scala 306:12] - node _T_684 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 307:38] - node _T_685 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 307:62] + buf_addr <= _T_683 @[axi4_to_ahb.scala 305:21] + node _T_684 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 306:47] + node _T_685 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 306:70] node _T_686 = and(buf_clken, _T_685) @[lib.scala 383:57] reg _T_687 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_686 : @[Reg.scala 28:19] _T_687 <= _T_684 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_size <= _T_687 @[axi4_to_ahb.scala 307:12] - node _T_688 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 308:62] + buf_size <= _T_687 @[axi4_to_ahb.scala 306:21] + node _T_688 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 307:68] node _T_689 = and(buf_clken, _T_688) @[lib.scala 383:57] reg _T_690 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_689 : @[Reg.scala 28:19] _T_690 <= buf_aligned_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_aligned <= _T_690 @[axi4_to_ahb.scala 308:15] - node _T_691 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 309:42] - node _T_692 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 309:66] + buf_aligned <= _T_690 @[axi4_to_ahb.scala 307:21] + node _T_691 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 308:49] + node _T_692 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 308:73] node _T_693 = and(buf_clken, _T_692) @[lib.scala 383:57] reg _T_694 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_693 : @[Reg.scala 28:19] _T_694 <= _T_691 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_byteen <= _T_694 @[axi4_to_ahb.scala 309:14] - node _T_695 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 310:33] - node _T_696 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 310:58] - node _T_697 = bits(_T_696, 0, 0) @[axi4_to_ahb.scala 310:81] + buf_byteen <= _T_694 @[axi4_to_ahb.scala 308:21] + node _T_695 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 309:42] + node _T_696 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 309:67] + node _T_697 = bits(_T_696, 0, 0) @[axi4_to_ahb.scala 309:90] inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 399:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -1183,30 +1183,30 @@ circuit axi4_to_ahb : when _T_697 : @[Reg.scala 28:19] _T_698 <= _T_695 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_data <= _T_698 @[axi4_to_ahb.scala 310:12] - node _T_699 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 311:61] + buf_data <= _T_698 @[axi4_to_ahb.scala 309:21] + node _T_699 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 310:66] node _T_700 = and(buf_clken, _T_699) @[lib.scala 383:57] reg _T_701 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_700 : @[Reg.scala 28:19] _T_701 <= buf_write @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_write <= _T_701 @[axi4_to_ahb.scala 311:16] - node _T_702 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 312:36] - node _T_703 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 312:69] + slvbuf_write <= _T_701 @[axi4_to_ahb.scala 310:21] + node _T_702 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 311:43] + node _T_703 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 311:76] node _T_704 = and(buf_clken, _T_703) @[lib.scala 383:57] reg _T_705 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_704 : @[Reg.scala 28:19] _T_705 <= _T_702 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_tag <= _T_705 @[axi4_to_ahb.scala 312:14] - node _T_706 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 313:70] - node _T_707 = and(buf_clken, _T_706) @[lib.scala 383:57] + slvbuf_tag <= _T_705 @[axi4_to_ahb.scala 311:21] + node _T_706 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 312:75] + node _T_707 = and(io.bus_clk_en, _T_706) @[lib.scala 383:57] reg _T_708 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_707 : @[Reg.scala 28:19] _T_708 <= slvbuf_error_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_error <= _T_708 @[axi4_to_ahb.scala 313:16] - node _T_709 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 314:49] + slvbuf_error <= _T_708 @[axi4_to_ahb.scala 312:21] + node _T_709 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 313:57] wire _T_710 : UInt @[lib.scala 389:21] node _T_711 = eq(cmd_done_rst, UInt<1>("h00")) @[lib.scala 391:75] node _T_712 = and(UInt<1>("h01"), _T_711) @[lib.scala 391:53] @@ -1218,54 +1218,54 @@ circuit axi4_to_ahb : _T_716 <= _T_712 @[Reg.scala 28:23] skip @[Reg.scala 28:19] _T_710 <= _T_716 @[lib.scala 391:14] - cmd_doneQ <= _T_710 @[axi4_to_ahb.scala 314:13] - node _T_717 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 315:52] - node _T_718 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 315:86] + cmd_doneQ <= _T_710 @[axi4_to_ahb.scala 313:21] + node _T_717 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 314:52] + node _T_718 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 314:86] node _T_719 = and(io.bus_clk_en, _T_718) @[lib.scala 383:57] reg _T_720 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_719 : @[Reg.scala 28:19] _T_720 <= _T_717 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_cmd_byte_ptrQ <= _T_720 @[axi4_to_ahb.scala 315:21] + buf_cmd_byte_ptrQ <= _T_720 @[axi4_to_ahb.scala 314:21] reg _T_721 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when io.bus_clk_en : @[Reg.scala 28:19] _T_721 <= io.ahb.in.hready @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ahb_hready_q <= _T_721 @[axi4_to_ahb.scala 316:16] - node _T_722 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 317:47] + ahb_hready_q <= _T_721 @[axi4_to_ahb.scala 315:21] + node _T_722 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 316:52] reg _T_723 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when io.bus_clk_en : @[Reg.scala 28:19] _T_723 <= _T_722 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ahb_htrans_q <= _T_723 @[axi4_to_ahb.scala 317:16] + ahb_htrans_q <= _T_723 @[axi4_to_ahb.scala 316:21] reg _T_724 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when io.bus_clk_en : @[Reg.scala 28:19] _T_724 <= io.ahb.out.hwrite @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ahb_hwrite_q <= _T_724 @[axi4_to_ahb.scala 318:16] + ahb_hwrite_q <= _T_724 @[axi4_to_ahb.scala 317:21] reg _T_725 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when io.bus_clk_en : @[Reg.scala 28:19] _T_725 <= io.ahb.in.hresp @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ahb_hresp_q <= _T_725 @[axi4_to_ahb.scala 319:15] - node _T_726 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 320:46] + ahb_hresp_q <= _T_725 @[axi4_to_ahb.scala 318:21] + node _T_726 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 319:51] reg _T_727 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when ahbm_data_clken : @[Reg.scala 28:19] _T_727 <= _T_726 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ahb_hrdata_q <= _T_727 @[axi4_to_ahb.scala 320:16] - node _T_728 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 321:43] - node _T_729 = or(_T_728, io.clk_override) @[axi4_to_ahb.scala 321:58] - node _T_730 = and(io.bus_clk_en, _T_729) @[axi4_to_ahb.scala 321:30] - buf_clken <= _T_730 @[axi4_to_ahb.scala 321:13] - node _T_731 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 322:50] - node _T_732 = or(_T_731, io.clk_override) @[axi4_to_ahb.scala 322:60] - node _T_733 = and(io.bus_clk_en, _T_732) @[axi4_to_ahb.scala 322:36] - ahbm_data_clken <= _T_733 @[axi4_to_ahb.scala 322:19] - node _T_734 = asClock(UInt<1>("h00")) @[axi4_to_ahb.scala 325:27] - bus_clk <= _T_734 @[axi4_to_ahb.scala 325:13] - node _T_735 = asClock(UInt<1>("h00")) @[axi4_to_ahb.scala 326:27] - buf_clk <= _T_735 @[axi4_to_ahb.scala 326:13] - node _T_736 = asClock(UInt<1>("h00")) @[axi4_to_ahb.scala 327:33] - ahbm_data_clk <= _T_736 @[axi4_to_ahb.scala 327:19] + ahb_hrdata_q <= _T_727 @[axi4_to_ahb.scala 319:21] + node _T_728 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 320:51] + node _T_729 = or(_T_728, io.clk_override) @[axi4_to_ahb.scala 320:66] + node _T_730 = and(io.bus_clk_en, _T_729) @[axi4_to_ahb.scala 320:38] + buf_clken <= _T_730 @[axi4_to_ahb.scala 320:21] + node _T_731 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 321:52] + node _T_732 = or(_T_731, io.clk_override) @[axi4_to_ahb.scala 321:62] + node _T_733 = and(io.bus_clk_en, _T_732) @[axi4_to_ahb.scala 321:38] + ahbm_data_clken <= _T_733 @[axi4_to_ahb.scala 321:21] + node _T_734 = asClock(UInt<1>("h00")) @[axi4_to_ahb.scala 323:27] + bus_clk <= _T_734 @[axi4_to_ahb.scala 323:13] + node _T_735 = asClock(UInt<1>("h00")) @[axi4_to_ahb.scala 324:27] + buf_clk <= _T_735 @[axi4_to_ahb.scala 324:13] + node _T_736 = asClock(UInt<1>("h00")) @[axi4_to_ahb.scala 325:33] + ahbm_data_clk <= _T_736 @[axi4_to_ahb.scala 325:19] diff --git a/axi4_to_ahb.v b/axi4_to_ahb.v index 429ec2e2..1acfe3c6 100644 --- a/axi4_to_ahb.v +++ b/axi4_to_ahb.v @@ -124,19 +124,19 @@ module axi4_to_ahb( wire _T_99 = 3'h1 == buf_state; // @[Conditional.scala 37:30] reg ahb_hready_q; // @[Reg.scala 27:20] reg [1:0] ahb_htrans_q; // @[Reg.scala 27:20] - wire _T_106 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 178:58] - wire _T_107 = ahb_hready_q & _T_106; // @[axi4_to_ahb.scala 178:36] + wire _T_106 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 177:58] + wire _T_107 = ahb_hready_q & _T_106; // @[axi4_to_ahb.scala 177:36] reg ahb_hwrite_q; // @[Reg.scala 27:20] - wire _T_108 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 178:72] - wire _T_109 = _T_107 & _T_108; // @[axi4_to_ahb.scala 178:70] + wire _T_108 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 177:72] + wire _T_109 = _T_107 & _T_108; // @[axi4_to_ahb.scala 177:70] wire _T_134 = 3'h6 == buf_state; // @[Conditional.scala 37:30] reg ahb_hresp_q; // @[Reg.scala 27:20] - wire _T_154 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 192:37] + wire _T_154 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 191:37] wire _T_173 = 3'h7 == buf_state; // @[Conditional.scala 37:30] wire _T_184 = 3'h3 == buf_state; // @[Conditional.scala 37:30] wire _T_186 = 3'h2 == buf_state; // @[Conditional.scala 37:30] - wire _T_187 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 224:33] - wire _T_190 = _T_187 & _T_106; // @[axi4_to_ahb.scala 224:48] + wire _T_187 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 223:33] + wire _T_190 = _T_187 & _T_106; // @[axi4_to_ahb.scala 223:48] wire _T_279 = 3'h4 == buf_state; // @[Conditional.scala 37:30] wire _GEN_16 = _T_279 & _T_190; // @[Conditional.scala 39:67] wire _GEN_20 = _T_186 ? _T_190 : _GEN_16; // @[Conditional.scala 39:67] @@ -146,8 +146,8 @@ module axi4_to_ahb( wire _GEN_96 = _T_99 ? 1'h0 : _GEN_80; // @[Conditional.scala 39:67] wire trxn_done = _T_47 ? 1'h0 : _GEN_96; // @[Conditional.scala 40:58] reg cmd_doneQ; // @[Reg.scala 27:20] - wire _T_280 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 234:34] - wire _T_281 = _T_280 | ahb_hresp_q; // @[axi4_to_ahb.scala 234:50] + wire _T_280 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 233:34] + wire _T_281 = _T_280 | ahb_hresp_q; // @[axi4_to_ahb.scala 233:50] wire _T_438 = 3'h5 == buf_state; // @[Conditional.scala 37:30] wire slave_ready = io_axi_b_ready & io_axi_r_ready; // @[axi4_to_ahb.scala 158:33] wire _GEN_2 = _T_438 & slave_ready; // @[Conditional.scala 39:67] @@ -170,18 +170,18 @@ module axi4_to_ahb( wire _GEN_98 = _T_99 ? 1'h0 : _GEN_82; // @[Conditional.scala 39:67] wire buf_write_in = _T_47 ? _T_49 : _GEN_98; // @[Conditional.scala 40:58] wire [2:0] _T_51 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 164:26] - wire _T_101 = master_opc == 3'h0; // @[axi4_to_ahb.scala 177:61] - wire _T_102 = master_valid & _T_101; // @[axi4_to_ahb.scala 177:41] - wire [2:0] _T_104 = _T_102 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 177:26] - wire _T_122 = _T_104 == 3'h6; // @[axi4_to_ahb.scala 181:174] - wire _T_123 = _T_109 & _T_122; // @[axi4_to_ahb.scala 181:88] - wire _T_135 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 189:39] - wire _T_136 = ahb_hready_q & _T_135; // @[axi4_to_ahb.scala 189:37] - wire _T_139 = master_valid & _T_49; // @[axi4_to_ahb.scala 189:70] - wire _T_140 = ~_T_139; // @[axi4_to_ahb.scala 189:55] - wire _T_141 = _T_136 & _T_140; // @[axi4_to_ahb.scala 189:53] - wire _T_283 = buf_state_en & _T_135; // @[axi4_to_ahb.scala 235:36] - wire _T_284 = _T_283 & slave_ready; // @[axi4_to_ahb.scala 235:51] + wire _T_101 = master_opc == 3'h0; // @[axi4_to_ahb.scala 176:61] + wire _T_102 = master_valid & _T_101; // @[axi4_to_ahb.scala 176:41] + wire [2:0] _T_104 = _T_102 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 176:26] + wire _T_122 = _T_104 == 3'h6; // @[axi4_to_ahb.scala 180:174] + wire _T_123 = _T_109 & _T_122; // @[axi4_to_ahb.scala 180:88] + wire _T_135 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 188:39] + wire _T_136 = ahb_hready_q & _T_135; // @[axi4_to_ahb.scala 188:37] + wire _T_139 = master_valid & _T_49; // @[axi4_to_ahb.scala 188:70] + wire _T_140 = ~_T_139; // @[axi4_to_ahb.scala 188:55] + wire _T_141 = _T_136 & _T_140; // @[axi4_to_ahb.scala 188:53] + wire _T_283 = buf_state_en & _T_135; // @[axi4_to_ahb.scala 234:36] + wire _T_284 = _T_283 & slave_ready; // @[axi4_to_ahb.scala 234:51] wire _GEN_5 = _T_279 & _T_284; // @[Conditional.scala 39:67] wire _GEN_27 = _T_186 ? 1'h0 : _GEN_5; // @[Conditional.scala 39:67] wire _GEN_46 = _T_184 ? 1'h0 : _GEN_27; // @[Conditional.scala 39:67] @@ -189,15 +189,15 @@ module axi4_to_ahb( wire _GEN_67 = _T_134 ? _T_141 : _GEN_63; // @[Conditional.scala 39:67] wire _GEN_87 = _T_99 ? _T_123 : _GEN_67; // @[Conditional.scala 39:67] wire master_ready = _T_47 | _GEN_87; // @[Conditional.scala 40:58] - wire _T_147 = master_valid & master_ready; // @[axi4_to_ahb.scala 191:82] - wire _T_150 = _T_147 & _T_101; // @[axi4_to_ahb.scala 191:97] - wire [2:0] _T_152 = _T_150 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 191:67] - wire [2:0] _T_153 = ahb_hresp_q ? 3'h7 : _T_152; // @[axi4_to_ahb.scala 191:26] - wire _T_285 = ~slave_ready; // @[axi4_to_ahb.scala 236:42] - wire _T_286 = ahb_hresp_q | _T_285; // @[axi4_to_ahb.scala 236:40] - wire [2:0] _T_291 = _T_49 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 236:101] - wire [2:0] _T_292 = master_valid ? _T_291 : 3'h0; // @[axi4_to_ahb.scala 236:66] - wire [2:0] _T_293 = _T_286 ? 3'h5 : _T_292; // @[axi4_to_ahb.scala 236:26] + wire _T_147 = master_valid & master_ready; // @[axi4_to_ahb.scala 190:82] + wire _T_150 = _T_147 & _T_101; // @[axi4_to_ahb.scala 190:97] + wire [2:0] _T_152 = _T_150 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 190:67] + wire [2:0] _T_153 = ahb_hresp_q ? 3'h7 : _T_152; // @[axi4_to_ahb.scala 190:26] + wire _T_285 = ~slave_ready; // @[axi4_to_ahb.scala 235:42] + wire _T_286 = ahb_hresp_q | _T_285; // @[axi4_to_ahb.scala 235:40] + wire [2:0] _T_291 = _T_49 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 235:101] + wire [2:0] _T_292 = master_valid ? _T_291 : 3'h0; // @[axi4_to_ahb.scala 235:66] + wire [2:0] _T_293 = _T_286 ? 3'h5 : _T_292; // @[axi4_to_ahb.scala 235:26] wire [2:0] _GEN_6 = _T_279 ? _T_293 : 3'h0; // @[Conditional.scala 39:67] wire [2:0] _GEN_19 = _T_186 ? 3'h4 : _GEN_6; // @[Conditional.scala 39:67] wire [2:0] _GEN_35 = _T_184 ? 3'h5 : _GEN_19; // @[Conditional.scala 39:67] @@ -216,8 +216,8 @@ module axi4_to_ahb( wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_ar_bits_size; // @[axi4_to_ahb.scala 145:21] reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20] reg [63:0] wrbuf_data; // @[Reg.scala 27:20] - wire _T_356 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 246:55] - wire _T_357 = buf_state_en & _T_356; // @[axi4_to_ahb.scala 246:39] + wire _T_356 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 245:55] + wire _T_357 = buf_state_en & _T_356; // @[axi4_to_ahb.scala 245:39] wire _GEN_15 = _T_279 ? _T_357 : _T_438; // @[Conditional.scala 39:67] wire _GEN_34 = _T_186 ? 1'h0 : _GEN_15; // @[Conditional.scala 39:67] wire _GEN_50 = _T_184 ? 1'h0 : _GEN_34; // @[Conditional.scala 39:67] @@ -227,20 +227,20 @@ module axi4_to_ahb( wire slave_valid_pre = _T_47 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58] wire _T_28 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 150:33] reg slvbuf_write; // @[Reg.scala 27:20] - wire [1:0] _T_595 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 280:23] + wire [1:0] _T_595 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 279:23] reg slvbuf_error; // @[Reg.scala 27:20] wire [1:0] _T_597 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_598 = _T_597 & 2'h2; // @[axi4_to_ahb.scala 280:88] + wire [1:0] _T_598 = _T_597 & 2'h2; // @[axi4_to_ahb.scala 279:88] wire [3:0] slave_opc = {_T_595,_T_598}; // @[Cat.scala 29:58] wire [1:0] _T_33 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 151:55] reg slvbuf_tag; // @[Reg.scala 27:20] wire _T_38 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 154:66] reg [31:0] last_bus_addr; // @[Reg.scala 27:20] wire [63:0] _T_602 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58] - wire _T_603 = buf_state == 3'h5; // @[axi4_to_ahb.scala 281:91] + wire _T_603 = buf_state == 3'h5; // @[axi4_to_ahb.scala 280:91] reg [63:0] buf_data; // @[Reg.scala 27:20] reg [63:0] ahb_hrdata_q; // @[Reg.scala 27:20] - wire [63:0] _T_606 = _T_603 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 281:79] + wire [63:0] _T_606 = _T_603 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 280:79] wire _T_53 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 167:54] wire _T_54 = buf_state_en & _T_53; // @[axi4_to_ahb.scala 167:38] wire [2:0] _T_85 = wrbuf_byteen[6] ? 3'h6 : 3'h7; // @[Mux.scala 98:16] @@ -250,14 +250,14 @@ module axi4_to_ahb( wire [2:0] _T_89 = wrbuf_byteen[2] ? 3'h2 : _T_88; // @[Mux.scala 98:16] wire [2:0] _T_90 = wrbuf_byteen[1] ? 3'h1 : _T_89; // @[Mux.scala 98:16] wire [2:0] _T_91 = wrbuf_byteen[0] ? 3'h0 : _T_90; // @[Mux.scala 98:16] - wire [2:0] _T_93 = buf_write_in ? _T_91 : master_addr[2:0]; // @[axi4_to_ahb.scala 170:30] - wire _T_94 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 172:51] - wire _T_124 = master_ready & master_valid; // @[axi4_to_ahb.scala 183:33] - wire _T_160 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 198:64] - wire _T_161 = _T_124 & _T_160; // @[axi4_to_ahb.scala 198:48] - wire _T_162 = _T_161 & buf_state_en; // @[axi4_to_ahb.scala 198:79] - wire _T_347 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 244:33] - wire _T_349 = _T_347 & _T_53; // @[axi4_to_ahb.scala 244:48] + wire [2:0] _T_93 = buf_write_in ? _T_91 : master_addr[2:0]; // @[axi4_to_ahb.scala 169:30] + wire _T_94 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 171:51] + wire _T_124 = master_ready & master_valid; // @[axi4_to_ahb.scala 182:33] + wire _T_160 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 197:64] + wire _T_161 = _T_124 & _T_160; // @[axi4_to_ahb.scala 197:48] + wire _T_162 = _T_161 & buf_state_en; // @[axi4_to_ahb.scala 197:79] + wire _T_347 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 243:33] + wire _T_349 = _T_347 & _T_53; // @[axi4_to_ahb.scala 243:48] wire _GEN_13 = _T_279 & _T_349; // @[Conditional.scala 39:67] wire _GEN_33 = _T_186 ? 1'h0 : _GEN_13; // @[Conditional.scala 39:67] wire _GEN_49 = _T_184 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67] @@ -266,22 +266,22 @@ module axi4_to_ahb( wire _GEN_89 = _T_99 ? _T_124 : _GEN_76; // @[Conditional.scala 39:67] wire bypass_en = _T_47 ? buf_state_en : _GEN_89; // @[Conditional.scala 40:58] wire [1:0] _T_97 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_98 = _T_97 & 2'h2; // @[axi4_to_ahb.scala 173:49] - wire _T_110 = ~master_valid; // @[axi4_to_ahb.scala 179:34] - wire _T_111 = buf_state_en & _T_110; // @[axi4_to_ahb.scala 179:32] + wire [1:0] _T_98 = _T_97 & 2'h2; // @[axi4_to_ahb.scala 172:49] + wire _T_110 = ~master_valid; // @[axi4_to_ahb.scala 178:34] + wire _T_111 = buf_state_en & _T_110; // @[axi4_to_ahb.scala 178:32] reg [31:0] buf_addr; // @[Reg.scala 27:20] - wire [2:0] _T_128 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 184:30] - wire _T_129 = ~buf_state_en; // @[axi4_to_ahb.scala 185:48] - wire _T_130 = _T_129 | bypass_en; // @[axi4_to_ahb.scala 185:62] + wire [2:0] _T_128 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 183:30] + wire _T_129 = ~buf_state_en; // @[axi4_to_ahb.scala 184:48] + wire _T_130 = _T_129 | bypass_en; // @[axi4_to_ahb.scala 184:62] wire [1:0] _T_132 = _T_130 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_133 = 2'h2 & _T_132; // @[axi4_to_ahb.scala 185:36] - wire _T_167 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 200:63] - wire _T_168 = _T_167 & buf_state_en; // @[axi4_to_ahb.scala 200:78] - wire _T_169 = ~_T_168; // @[axi4_to_ahb.scala 200:47] + wire [1:0] _T_133 = 2'h2 & _T_132; // @[axi4_to_ahb.scala 184:36] + wire _T_167 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 199:63] + wire _T_168 = _T_167 & buf_state_en; // @[axi4_to_ahb.scala 199:78] + wire _T_169 = ~_T_168; // @[axi4_to_ahb.scala 199:47] wire [1:0] _T_171 = _T_169 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_172 = 2'h2 & _T_171; // @[axi4_to_ahb.scala 200:36] + wire [1:0] _T_172 = 2'h2 & _T_171; // @[axi4_to_ahb.scala 199:36] wire [1:0] _T_182 = _T_129 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_183 = 2'h2 & _T_182; // @[axi4_to_ahb.scala 210:41] + wire [1:0] _T_183 = 2'h2 & _T_182; // @[axi4_to_ahb.scala 209:41] reg [2:0] buf_cmd_byte_ptrQ; // @[Reg.scala 27:20] reg [7:0] buf_byteen; // @[Reg.scala 27:20] wire [2:0] _T_195 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 136:52] @@ -306,17 +306,17 @@ module axi4_to_ahb( wire [2:0] _T_226 = _T_205 ? 3'h2 : _T_225; // @[Mux.scala 98:16] wire [2:0] _T_227 = _T_202 ? 3'h1 : _T_226; // @[Mux.scala 98:16] wire [2:0] _T_228 = _T_199 ? 3'h0 : _T_227; // @[Mux.scala 98:16] - wire [2:0] _T_229 = trxn_done ? _T_228 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 228:30] - wire _T_230 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 229:65] + wire [2:0] _T_229 = trxn_done ? _T_228 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 227:30] + wire _T_230 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 228:65] reg buf_aligned; // @[Reg.scala 27:20] - wire _T_231 = buf_aligned | _T_230; // @[axi4_to_ahb.scala 229:44] - wire [7:0] _T_269 = buf_byteen >> _T_228; // @[axi4_to_ahb.scala 229:92] - wire _T_271 = ~_T_269[0]; // @[axi4_to_ahb.scala 229:163] - wire _T_272 = _T_231 | _T_271; // @[axi4_to_ahb.scala 229:79] - wire _T_273 = trxn_done & _T_272; // @[axi4_to_ahb.scala 229:29] - wire _T_344 = _T_230 | _T_271; // @[axi4_to_ahb.scala 243:38] - wire _T_345 = _T_107 & _T_344; // @[axi4_to_ahb.scala 242:79] - wire _T_346 = ahb_hresp_q | _T_345; // @[axi4_to_ahb.scala 242:32] + wire _T_231 = buf_aligned | _T_230; // @[axi4_to_ahb.scala 228:44] + wire [7:0] _T_269 = buf_byteen >> _T_228; // @[axi4_to_ahb.scala 228:92] + wire _T_271 = ~_T_269[0]; // @[axi4_to_ahb.scala 228:163] + wire _T_272 = _T_231 | _T_271; // @[axi4_to_ahb.scala 228:79] + wire _T_273 = trxn_done & _T_272; // @[axi4_to_ahb.scala 228:29] + wire _T_344 = _T_230 | _T_271; // @[axi4_to_ahb.scala 242:38] + wire _T_345 = _T_107 & _T_344; // @[axi4_to_ahb.scala 241:79] + wire _T_346 = ahb_hresp_q | _T_345; // @[axi4_to_ahb.scala 241:32] wire _GEN_12 = _T_279 & _T_346; // @[Conditional.scala 39:67] wire _GEN_25 = _T_186 ? _T_273 : _GEN_12; // @[Conditional.scala 39:67] wire _GEN_44 = _T_184 ? 1'h0 : _GEN_25; // @[Conditional.scala 39:67] @@ -324,17 +324,17 @@ module axi4_to_ahb( wire _GEN_75 = _T_134 ? _T_111 : _GEN_62; // @[Conditional.scala 39:67] wire _GEN_85 = _T_99 ? _T_111 : _GEN_75; // @[Conditional.scala 39:67] wire cmd_done = _T_47 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] - wire _T_274 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 230:47] - wire _T_275 = ~_T_274; // @[axi4_to_ahb.scala 230:36] + wire _T_274 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 229:47] + wire _T_275 = ~_T_274; // @[axi4_to_ahb.scala 229:36] wire [1:0] _T_277 = _T_275 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_278 = _T_277 & 2'h2; // @[axi4_to_ahb.scala 230:61] - wire _T_298 = _T_53 | _T_94; // @[axi4_to_ahb.scala 240:62] - wire _T_299 = buf_state_en & _T_298; // @[axi4_to_ahb.scala 240:33] - wire _T_352 = _T_275 | bypass_en; // @[axi4_to_ahb.scala 245:61] + wire [1:0] _T_278 = _T_277 & 2'h2; // @[axi4_to_ahb.scala 229:61] + wire _T_298 = _T_53 | _T_94; // @[axi4_to_ahb.scala 239:62] + wire _T_299 = buf_state_en & _T_298; // @[axi4_to_ahb.scala 239:33] + wire _T_352 = _T_275 | bypass_en; // @[axi4_to_ahb.scala 244:61] wire [1:0] _T_354 = _T_352 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_355 = _T_354 & 2'h2; // @[axi4_to_ahb.scala 245:75] - wire _T_362 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 248:40] - wire [2:0] _T_437 = bypass_en ? _T_91 : _T_229; // @[axi4_to_ahb.scala 249:30] + wire [1:0] _T_355 = _T_354 & 2'h2; // @[axi4_to_ahb.scala 244:75] + wire _T_362 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 247:40] + wire [2:0] _T_437 = bypass_en ? _T_91 : _T_229; // @[axi4_to_ahb.scala 248:30] wire _GEN_7 = _T_279 & ahb_hresp_q; // @[Conditional.scala 39:67] wire _GEN_8 = _T_279 ? buf_state_en : _T_438; // @[Conditional.scala 39:67] wire _GEN_10 = _T_279 & _T_299; // @[Conditional.scala 39:67] @@ -383,29 +383,29 @@ module axi4_to_ahb( wire [2:0] buf_cmd_byte_ptr = _T_47 ? _T_93 : _GEN_90; // @[Conditional.scala 40:58] wire slvbuf_wr_en = _T_47 ? 1'h0 : _GEN_86; // @[Conditional.scala 40:58] wire slvbuf_error_en = _T_47 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58] - wire _T_533 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 266:24] - wire _T_534 = _T_101 | _T_533; // @[axi4_to_ahb.scala 265:48] - wire _T_536 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 266:54] - wire _T_537 = _T_534 | _T_536; // @[axi4_to_ahb.scala 266:33] - wire _T_539 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 266:93] - wire _T_540 = _T_537 | _T_539; // @[axi4_to_ahb.scala 266:72] - wire _T_542 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 267:25] - wire _T_544 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 267:62] - wire _T_546 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 267:97] - wire _T_547 = _T_544 | _T_546; // @[axi4_to_ahb.scala 267:74] - wire _T_549 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 267:132] - wire _T_550 = _T_547 | _T_549; // @[axi4_to_ahb.scala 267:109] - wire _T_552 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 267:168] - wire _T_553 = _T_550 | _T_552; // @[axi4_to_ahb.scala 267:145] - wire _T_555 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 268:28] - wire _T_556 = _T_553 | _T_555; // @[axi4_to_ahb.scala 267:181] - wire _T_558 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 268:63] - wire _T_559 = _T_556 | _T_558; // @[axi4_to_ahb.scala 268:40] - wire _T_561 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 268:99] - wire _T_562 = _T_559 | _T_561; // @[axi4_to_ahb.scala 268:76] - wire _T_563 = _T_542 & _T_562; // @[axi4_to_ahb.scala 267:38] - wire buf_aligned_in = _T_540 | _T_563; // @[axi4_to_ahb.scala 266:106] - wire _T_442 = buf_aligned_in & _T_49; // @[axi4_to_ahb.scala 260:62] + wire _T_533 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 265:24] + wire _T_534 = _T_101 | _T_533; // @[axi4_to_ahb.scala 264:48] + wire _T_536 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 265:54] + wire _T_537 = _T_534 | _T_536; // @[axi4_to_ahb.scala 265:33] + wire _T_539 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 265:93] + wire _T_540 = _T_537 | _T_539; // @[axi4_to_ahb.scala 265:72] + wire _T_542 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 266:25] + wire _T_544 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 266:62] + wire _T_546 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 266:97] + wire _T_547 = _T_544 | _T_546; // @[axi4_to_ahb.scala 266:74] + wire _T_549 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 266:132] + wire _T_550 = _T_547 | _T_549; // @[axi4_to_ahb.scala 266:109] + wire _T_552 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 266:168] + wire _T_553 = _T_550 | _T_552; // @[axi4_to_ahb.scala 266:145] + wire _T_555 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 267:28] + wire _T_556 = _T_553 | _T_555; // @[axi4_to_ahb.scala 266:181] + wire _T_558 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 267:63] + wire _T_559 = _T_556 | _T_558; // @[axi4_to_ahb.scala 267:40] + wire _T_561 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 267:99] + wire _T_562 = _T_559 | _T_561; // @[axi4_to_ahb.scala 267:76] + wire _T_563 = _T_542 & _T_562; // @[axi4_to_ahb.scala 266:38] + wire buf_aligned_in = _T_540 | _T_563; // @[axi4_to_ahb.scala 265:106] + wire _T_442 = buf_aligned_in & _T_49; // @[axi4_to_ahb.scala 259:62] wire [2:0] _T_459 = _T_546 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] wire [2:0] _T_460 = 3'h2 & _T_459; // @[axi4_to_ahb.scala 128:15] wire _T_466 = _T_558 | _T_544; // @[axi4_to_ahb.scala 129:56] @@ -415,11 +415,11 @@ module axi4_to_ahb( wire [2:0] _T_474 = _T_552 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] wire [2:0] _T_475 = 3'h6 & _T_474; // @[axi4_to_ahb.scala 130:15] wire [2:0] _T_476 = _T_470 | _T_475; // @[axi4_to_ahb.scala 129:96] - wire [2:0] _T_483 = _T_442 ? _T_476 : master_addr[2:0]; // @[axi4_to_ahb.scala 260:45] + wire [2:0] _T_483 = _T_442 ? _T_476 : master_addr[2:0]; // @[axi4_to_ahb.scala 259:45] wire [31:0] buf_addr_in = {master_addr[31:3],_T_483}; // @[Cat.scala 29:58] - wire _T_487 = buf_state == 3'h3; // @[axi4_to_ahb.scala 263:33] - wire _T_493 = buf_aligned_in & _T_542; // @[axi4_to_ahb.scala 264:38] - wire _T_496 = _T_493 & _T_49; // @[axi4_to_ahb.scala 264:72] + wire _T_487 = buf_state == 3'h3; // @[axi4_to_ahb.scala 262:33] + wire _T_493 = buf_aligned_in & _T_542; // @[axi4_to_ahb.scala 263:38] + wire _T_496 = _T_493 & _T_49; // @[axi4_to_ahb.scala 263:72] wire [1:0] _T_502 = _T_561 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire _T_508 = _T_558 | _T_555; // @[axi4_to_ahb.scala 121:55] wire [1:0] _T_510 = _T_508 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] @@ -431,65 +431,65 @@ module axi4_to_ahb( wire [1:0] _T_525 = _T_523 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_526 = 2'h1 & _T_525; // @[axi4_to_ahb.scala 122:21] wire [1:0] _T_527 = _T_512 | _T_526; // @[axi4_to_ahb.scala 121:93] - wire [1:0] _T_529 = _T_496 ? _T_527 : master_size[1:0]; // @[axi4_to_ahb.scala 264:21] - wire [28:0] _T_568 = bypass_en ? master_addr[31:3] : buf_addr[31:3]; // @[axi4_to_ahb.scala 270:30] - wire _T_569 = io_ahb_out_htrans == 2'h2; // @[axi4_to_ahb.scala 270:115] + wire [1:0] _T_529 = _T_496 ? _T_527 : master_size[1:0]; // @[axi4_to_ahb.scala 263:21] + wire [28:0] _T_568 = bypass_en ? master_addr[31:3] : buf_addr[31:3]; // @[axi4_to_ahb.scala 269:30] + wire _T_569 = io_ahb_out_htrans == 2'h2; // @[axi4_to_ahb.scala 269:115] wire [2:0] _T_571 = _T_569 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_572 = _T_571 & buf_cmd_byte_ptr; // @[axi4_to_ahb.scala 270:124] + wire [2:0] _T_572 = _T_571 & buf_cmd_byte_ptr; // @[axi4_to_ahb.scala 269:124] wire [1:0] _T_576 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [2:0] buf_size_in = {{1'd0}, _T_529}; // @[axi4_to_ahb.scala 264:15] - wire [1:0] _T_578 = _T_576 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 271:81] + wire [2:0] buf_size_in = {{1'd0}, _T_529}; // @[axi4_to_ahb.scala 263:15] + wire [1:0] _T_578 = _T_576 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 270:81] wire [2:0] _T_579 = {1'h0,_T_578}; // @[Cat.scala 29:58] wire [1:0] _T_581 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] reg [1:0] buf_size; // @[Reg.scala 27:20] - wire [1:0] _T_583 = _T_581 & buf_size; // @[axi4_to_ahb.scala 271:138] + wire [1:0] _T_583 = _T_581 & buf_size; // @[axi4_to_ahb.scala 270:138] wire [2:0] _T_584 = {1'h0,_T_583}; // @[Cat.scala 29:58] - wire _T_587 = ~io_axi_ar_bits_prot[2]; // @[axi4_to_ahb.scala 275:37] + wire _T_587 = ~io_axi_ar_bits_prot[2]; // @[axi4_to_ahb.scala 274:37] wire [1:0] _T_588 = {1'h1,_T_587}; // @[Cat.scala 29:58] reg buf_write; // @[Reg.scala 27:20] - wire _T_610 = io_ahb_out_htrans != 2'h0; // @[axi4_to_ahb.scala 284:44] - wire _T_611 = _T_610 & io_ahb_in_hready; // @[axi4_to_ahb.scala 284:56] - wire last_addr_en = _T_611 & io_ahb_out_hwrite; // @[axi4_to_ahb.scala 284:75] - wire _T_613 = io_axi_aw_valid & io_axi_aw_ready; // @[axi4_to_ahb.scala 286:31] - wire wrbuf_en = _T_613 & master_ready; // @[axi4_to_ahb.scala 286:49] - wire _T_615 = io_axi_w_valid & io_axi_w_ready; // @[axi4_to_ahb.scala 287:35] - wire wrbuf_data_en = _T_615 & master_ready; // @[axi4_to_ahb.scala 287:52] - wire wrbuf_cmd_sent = _T_147 & _T_49; // @[axi4_to_ahb.scala 288:49] - wire _T_621 = ~wrbuf_en; // @[axi4_to_ahb.scala 289:34] - wire _T_622 = wrbuf_cmd_sent & _T_621; // @[axi4_to_ahb.scala 289:32] - wire wrbuf_rst = _T_622 | dec_tlu_force_halt_bus; // @[axi4_to_ahb.scala 289:45] - wire _T_624 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 291:36] - wire _T_625 = wrbuf_vld & _T_624; // @[axi4_to_ahb.scala 291:34] - wire _T_626 = ~_T_625; // @[axi4_to_ahb.scala 291:22] - wire _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 292:38] - wire _T_630 = ~_T_629; // @[axi4_to_ahb.scala 292:21] - wire _T_633 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 293:22] + wire _T_610 = io_ahb_out_htrans != 2'h0; // @[axi4_to_ahb.scala 283:44] + wire _T_611 = _T_610 & io_ahb_in_hready; // @[axi4_to_ahb.scala 283:56] + wire last_addr_en = _T_611 & io_ahb_out_hwrite; // @[axi4_to_ahb.scala 283:75] + wire _T_613 = io_axi_aw_valid & io_axi_aw_ready; // @[axi4_to_ahb.scala 285:31] + wire wrbuf_en = _T_613 & master_ready; // @[axi4_to_ahb.scala 285:49] + wire _T_615 = io_axi_w_valid & io_axi_w_ready; // @[axi4_to_ahb.scala 286:35] + wire wrbuf_data_en = _T_615 & master_ready; // @[axi4_to_ahb.scala 286:52] + wire wrbuf_cmd_sent = _T_147 & _T_49; // @[axi4_to_ahb.scala 287:49] + wire _T_621 = ~wrbuf_en; // @[axi4_to_ahb.scala 288:34] + wire _T_622 = wrbuf_cmd_sent & _T_621; // @[axi4_to_ahb.scala 288:32] + wire wrbuf_rst = _T_622 | dec_tlu_force_halt_bus; // @[axi4_to_ahb.scala 288:45] + wire _T_624 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 290:36] + wire _T_625 = wrbuf_vld & _T_624; // @[axi4_to_ahb.scala 290:34] + wire _T_626 = ~_T_625; // @[axi4_to_ahb.scala 290:22] + wire _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 291:38] + wire _T_630 = ~_T_629; // @[axi4_to_ahb.scala 291:21] + wire _T_633 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 292:22] wire _T_637 = ~wrbuf_rst; // @[lib.scala 391:75] wire _T_639 = wrbuf_en | wrbuf_rst; // @[lib.scala 391:95] wire _T_640 = _T_639 & io_bus_clk_en; // @[lib.scala 391:102] wire _T_647 = wrbuf_data_en | wrbuf_rst; // @[lib.scala 391:95] wire _T_648 = _T_647 & io_bus_clk_en; // @[lib.scala 391:102] wire _T_653 = io_bus_clk_en & wrbuf_en; // @[lib.scala 383:57] - wire _T_660 = wrbuf_en & io_bus_clk_en; // @[axi4_to_ahb.scala 300:61] - wire _T_663 = wrbuf_data_en & io_bus_clk_en; // @[axi4_to_ahb.scala 301:65] + wire _T_660 = wrbuf_en & io_bus_clk_en; // @[axi4_to_ahb.scala 299:61] + wire _T_663 = wrbuf_data_en & io_bus_clk_en; // @[axi4_to_ahb.scala 300:65] wire _T_667 = io_bus_clk_en & wrbuf_data_en; // @[lib.scala 383:57] wire _T_671 = io_bus_clk_en & last_addr_en; // @[lib.scala 383:57] - wire _T_728 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 321:43] - wire _T_729 = _T_728 | io_clk_override; // @[axi4_to_ahb.scala 321:58] - wire buf_clken = io_bus_clk_en & _T_729; // @[axi4_to_ahb.scala 321:30] + wire _T_728 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 320:51] + wire _T_729 = _T_728 | io_clk_override; // @[axi4_to_ahb.scala 320:66] + wire buf_clken = io_bus_clk_en & _T_729; // @[axi4_to_ahb.scala 320:38] wire _T_674 = buf_clken & buf_wr_en; // @[lib.scala 383:57] reg buf_tag; // @[Reg.scala 27:20] - wire _T_681 = buf_wr_en & io_bus_clk_en; // @[axi4_to_ahb.scala 306:53] - wire _T_696 = buf_data_wr_en & io_bus_clk_en; // @[axi4_to_ahb.scala 310:58] + wire _T_681 = buf_wr_en & io_bus_clk_en; // @[axi4_to_ahb.scala 305:62] + wire _T_696 = buf_data_wr_en & io_bus_clk_en; // @[axi4_to_ahb.scala 309:67] wire _T_700 = buf_clken & slvbuf_wr_en; // @[lib.scala 383:57] - wire _T_707 = buf_clken & slvbuf_error_en; // @[lib.scala 383:57] + wire _T_707 = io_bus_clk_en & slvbuf_error_en; // @[lib.scala 383:57] wire _T_711 = ~slave_valid_pre; // @[lib.scala 391:75] wire _T_713 = cmd_done | slave_valid_pre; // @[lib.scala 391:95] wire _T_714 = _T_713 & io_bus_clk_en; // @[lib.scala 391:102] wire _T_719 = io_bus_clk_en & buf_cmd_byte_ptr_en; // @[lib.scala 383:57] - wire _T_731 = buf_state != 3'h0; // @[axi4_to_ahb.scala 322:50] - wire _T_732 = _T_731 | io_clk_override; // @[axi4_to_ahb.scala 322:60] - wire ahbm_data_clken = io_bus_clk_en & _T_732; // @[axi4_to_ahb.scala 322:36] + wire _T_731 = buf_state != 3'h0; // @[axi4_to_ahb.scala 321:52] + wire _T_732 = _T_731 | io_clk_override; // @[axi4_to_ahb.scala 321:62] + wire ahbm_data_clken = io_bus_clk_en & _T_732; // @[axi4_to_ahb.scala 321:38] rvclkhdr rvclkhdr ( // @[lib.scala 399:23] .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en) @@ -506,25 +506,25 @@ module axi4_to_ahb( .io_clk(rvclkhdr_3_io_clk), .io_en(rvclkhdr_3_io_en) ); - assign io_axi_aw_ready = _T_626 & master_ready; // @[axi4_to_ahb.scala 291:19] - assign io_axi_w_ready = _T_630 & master_ready; // @[axi4_to_ahb.scala 292:18] + assign io_axi_aw_ready = _T_626 & master_ready; // @[axi4_to_ahb.scala 290:19] + assign io_axi_w_ready = _T_630 & master_ready; // @[axi4_to_ahb.scala 291:18] assign io_axi_b_valid = _T_28 & slave_opc[3]; // @[axi4_to_ahb.scala 150:18] assign io_axi_b_bits_resp = slave_opc[0] ? 2'h2 : _T_33; // @[axi4_to_ahb.scala 151:22] assign io_axi_b_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 152:20] - assign io_axi_ar_ready = _T_633 & master_ready; // @[axi4_to_ahb.scala 293:19] + assign io_axi_ar_ready = _T_633 & master_ready; // @[axi4_to_ahb.scala 292:19] assign io_axi_r_valid = _T_28 & _T_38; // @[axi4_to_ahb.scala 154:18] assign io_axi_r_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 156:20] assign io_axi_r_bits_data = slvbuf_error ? _T_602 : _T_606; // @[axi4_to_ahb.scala 157:22] assign io_axi_r_bits_resp = slave_opc[0] ? 2'h2 : _T_33; // @[axi4_to_ahb.scala 155:22] - assign io_axi_r_bits_last = 1'h1; // @[axi4_to_ahb.scala 294:22] - assign io_ahb_out_haddr = {_T_568,_T_572}; // @[axi4_to_ahb.scala 270:20] - assign io_ahb_out_hburst = 3'h0; // @[axi4_to_ahb.scala 273:21] - assign io_ahb_out_hmastlock = 1'h0; // @[axi4_to_ahb.scala 274:24] - assign io_ahb_out_hprot = {{2'd0}, _T_588}; // @[axi4_to_ahb.scala 275:20] - assign io_ahb_out_hsize = bypass_en ? _T_579 : _T_584; // @[axi4_to_ahb.scala 271:20] - assign io_ahb_out_htrans = _T_47 ? _T_98 : _GEN_91; // @[axi4_to_ahb.scala 29:21 axi4_to_ahb.scala 173:25 axi4_to_ahb.scala 185:25 axi4_to_ahb.scala 200:25 axi4_to_ahb.scala 210:25 axi4_to_ahb.scala 230:25 axi4_to_ahb.scala 245:25] - assign io_ahb_out_hwrite = bypass_en ? _T_49 : buf_write; // @[axi4_to_ahb.scala 276:21] - assign io_ahb_out_hwdata = buf_data; // @[axi4_to_ahb.scala 277:21] + assign io_axi_r_bits_last = 1'h1; // @[axi4_to_ahb.scala 293:22] + assign io_ahb_out_haddr = {_T_568,_T_572}; // @[axi4_to_ahb.scala 269:20] + assign io_ahb_out_hburst = 3'h0; // @[axi4_to_ahb.scala 272:21] + assign io_ahb_out_hmastlock = 1'h0; // @[axi4_to_ahb.scala 273:24] + assign io_ahb_out_hprot = {{2'd0}, _T_588}; // @[axi4_to_ahb.scala 274:20] + assign io_ahb_out_hsize = bypass_en ? _T_579 : _T_584; // @[axi4_to_ahb.scala 270:20] + assign io_ahb_out_htrans = _T_47 ? _T_98 : _GEN_91; // @[axi4_to_ahb.scala 29:21 axi4_to_ahb.scala 172:25 axi4_to_ahb.scala 184:25 axi4_to_ahb.scala 199:25 axi4_to_ahb.scala 209:25 axi4_to_ahb.scala 229:25 axi4_to_ahb.scala 244:25] + assign io_ahb_out_hwrite = bypass_en ? _T_49 : buf_write; // @[axi4_to_ahb.scala 275:21] + assign io_ahb_out_hwdata = buf_data; // @[axi4_to_ahb.scala 276:21] assign rvclkhdr_io_clk = clock; // @[lib.scala 401:18] assign rvclkhdr_io_en = wrbuf_en & io_bus_clk_en; // @[lib.scala 402:17] assign rvclkhdr_1_io_clk = clock; // @[lib.scala 401:18] diff --git a/src/main/scala/lib/ahb_to_axi4.scala b/src/main/scala/lib/ahb_to_axi4.scala index 7b02c0ca..9c1aacaf 100644 --- a/src/main/scala/lib/ahb_to_axi4.scala +++ b/src/main/scala/lib/ahb_to_axi4.scala @@ -111,7 +111,6 @@ class ahb_to_axi4(TAG : Int) extends Module with lib with RequireAsyncReset { ((ahb_hsize_q(2,0) === 3.U) & (ahb_haddr_q(2,0)).orR))) | // DW size but unaligned buf_read_error | // Read ECC error (ahb_hresp_q & !ahb_hready_q) - // Buffer signals - needed for the read data and ECC error response buf_rdata := rvdff_fpga(io.axi.r.bits.data,buf_rdata_clk,buf_rdata_clk_en,clock) buf_read_error := rvdff_fpga(buf_read_error_in,bus_clk,io.bus_clk_en,clock) diff --git a/src/main/scala/lib/axi4_to_ahb.scala b/src/main/scala/lib/axi4_to_ahb.scala index 3c4ae99a..4aad9843 100644 --- a/src/main/scala/lib/axi4_to_ahb.scala +++ b/src/main/scala/lib/axi4_to_ahb.scala @@ -166,7 +166,6 @@ class axi4_to_ahb(val TAG : Int = 3) extends Module with lib with RequireAsyncRe buf_wr_en := buf_state_en buf_data_wr_en := buf_state_en & (buf_nxtstate === cmd_wr) buf_cmd_byte_ptr_en := buf_state_en - // ---------------------FROM FUNCTION CHECK LATER buf_cmd_byte_ptr := Mux(buf_write_in.asBool(), (get_nxtbyte_ptr(0.U(3.W), buf_byteen_in(7, 0), false.B)), master_addr(2, 0)) bypass_en := buf_state_en rd_bypass_idle := bypass_en & (buf_nxtstate === cmd_rd) @@ -301,27 +300,26 @@ class axi4_to_ahb(val TAG : Int = 3) extends Module with lib with RequireAsyncRe wrbuf_data := rvdffe(io.axi.w.bits.data, wrbuf_data_en.asBool & io.bus_clk_en, clock, io.scan_mode) wrbuf_byteen := rvdffs_fpga(io.axi.w.bits.strb(7, 0), wrbuf_data_en.asBool(), bus_clk, io.bus_clk_en, clock) last_bus_addr := rvdffs_fpga(io.ahb.out.haddr(31, 0), last_addr_en.asBool(), bus_clk, io.bus_clk_en, clock) - buf_write := rvdffs_fpga(buf_write_in, buf_wr_en.asBool(), buf_clk, buf_clken, clock) - buf_tag := rvdffs_fpga(buf_tag_in(TAG - 1, 0), buf_wr_en.asBool(), buf_clk, buf_clken, clock) - buf_addr := rvdffe(buf_addr_in(31, 0), (buf_wr_en & io.bus_clk_en).asBool, clock, io.scan_mode) - buf_size := rvdffs_fpga(buf_size_in(1, 0), buf_wr_en.asBool(), buf_clk, buf_clken, clock) - buf_aligned := rvdffs_fpga(buf_aligned_in, buf_wr_en.asBool(), buf_clk, buf_clken, clock) - buf_byteen := rvdffs_fpga(buf_byteen_in(7, 0), buf_wr_en.asBool(), buf_clk, buf_clken, clock) - buf_data := rvdffe(buf_data_in(63, 0), (buf_data_wr_en & io.bus_clk_en).asBool(), clock, io.scan_mode) - slvbuf_write := rvdffs_fpga(buf_write, slvbuf_wr_en.asBool(), buf_clk, buf_clken, clock) - slvbuf_tag := rvdffs_fpga(buf_tag(TAG - 1, 0), slvbuf_wr_en.asBool(), buf_clk, buf_clken, clock) - slvbuf_error := rvdffs_fpga(slvbuf_error_in, slvbuf_error_en.asBool(), buf_clk, buf_clken, clock) - cmd_doneQ := rvdffsc_fpga(1.U, cmd_done.asBool(), cmd_done_rst, bus_clk, io.bus_clk_en, clock) + buf_write := rvdffs_fpga(buf_write_in, buf_wr_en.asBool(), buf_clk, buf_clken, clock) + buf_tag := rvdffs_fpga(buf_tag_in(TAG - 1, 0), buf_wr_en.asBool(), buf_clk, buf_clken, clock) + buf_addr := rvdffe(buf_addr_in(31, 0), (buf_wr_en & io.bus_clk_en).asBool, clock, io.scan_mode) + buf_size := rvdffs_fpga(buf_size_in(1,0), buf_wr_en.asBool(), buf_clk, buf_clken, clock) + buf_aligned := rvdffs_fpga(buf_aligned_in, buf_wr_en.asBool(), buf_clk, buf_clken, clock) + buf_byteen := rvdffs_fpga(buf_byteen_in(7, 0), buf_wr_en.asBool(), buf_clk, buf_clken, clock) + buf_data := rvdffe(buf_data_in(63, 0), (buf_data_wr_en & io.bus_clk_en).asBool(), clock, io.scan_mode) + slvbuf_write := rvdffs_fpga(buf_write, slvbuf_wr_en.asBool(), buf_clk, buf_clken, clock) + slvbuf_tag := rvdffs_fpga(buf_tag(TAG - 1, 0), slvbuf_wr_en.asBool(), buf_clk, buf_clken, clock) + slvbuf_error := rvdffs_fpga(slvbuf_error_in, slvbuf_error_en.asBool(), bus_clk, io.bus_clk_en, clock) + cmd_doneQ := rvdffsc_fpga(1.U, cmd_done.asBool(), cmd_done_rst, bus_clk, io.bus_clk_en, clock) buf_cmd_byte_ptrQ := rvdffs_fpga(buf_cmd_byte_ptr(2, 0), buf_cmd_byte_ptr_en.asBool(), bus_clk, io.bus_clk_en, clock) - ahb_hready_q := rvdff_fpga(io.ahb.in.hready, bus_clk, io.bus_clk_en, clock) - ahb_htrans_q := rvdff_fpga(io.ahb.out.htrans(1, 0), bus_clk,io.bus_clk_en, clock) - ahb_hwrite_q := rvdff_fpga(io.ahb.out.hwrite,bus_clk, io.bus_clk_en, clock) - ahb_hresp_q := rvdff_fpga(io.ahb.in.hresp,bus_clk, io.bus_clk_en, clock) - ahb_hrdata_q := rvdff_fpga(io.ahb.in.hrdata(63, 0), ahbm_data_clk, ahbm_data_clken, clock) - buf_clken := io.bus_clk_en & (buf_wr_en | slvbuf_wr_en | io.clk_override) - ahbm_data_clken := io.bus_clk_en & ((buf_state =/= idle) | io.clk_override) - - if (RV_FPGA_OPTIMIZE) { + ahb_hready_q := rvdff_fpga(io.ahb.in.hready, bus_clk, io.bus_clk_en, clock) + ahb_htrans_q := rvdff_fpga(io.ahb.out.htrans(1, 0), bus_clk,io.bus_clk_en, clock) + ahb_hwrite_q := rvdff_fpga(io.ahb.out.hwrite,bus_clk, io.bus_clk_en, clock) + ahb_hresp_q := rvdff_fpga(io.ahb.in.hresp,bus_clk, io.bus_clk_en, clock) + ahb_hrdata_q := rvdff_fpga(io.ahb.in.hrdata(63, 0), ahbm_data_clk, ahbm_data_clken, clock) + buf_clken := io.bus_clk_en & (buf_wr_en | slvbuf_wr_en | io.clk_override) + ahbm_data_clken := io.bus_clk_en & ((buf_state =/= idle) | io.clk_override) + if (RV_FPGA_OPTIMIZE) { bus_clk := 0.B.asClock() buf_clk := 0.B.asClock() ahbm_data_clk := 0.B.asClock() diff --git a/target/scala-2.12/classes/lib/ahb_to_axi4$.class b/target/scala-2.12/classes/lib/ahb_to_axi4$.class index a8291990afb4860c22ce620fe2f90bf85f73a6e1..860308bc9543ad350e7f6b2534e5a96ee80d2ba0 100644 GIT binary patch delta 99 zcmdlXw?l5jA1=ntlmBwr0!c<*@yS8lo>10iZYv<`9k&gT)aHT6OHOX$u>kUS^SFXl i1%XM)$+^5Pj9Vse;`L?S!l2Huc`^%M1yH7zZ#Mv)@*vUx delta 99 zcmdlXw?l5jA1=l%lmBwr0!c<*@yS8lo>10iZYv<`9k&gT)aHT6OHOX$u>kUS^SFXl i1%XM)$+^5Pj9Vvf;`L?S%An4$Wikt21yH7zZ#Mv-K_K4% diff --git a/target/scala-2.12/classes/lib/ahb_to_axi4$delayedInit$body.class b/target/scala-2.12/classes/lib/ahb_to_axi4$delayedInit$body.class index 84f18778bf8f1b220d7b73e004abee6e1447752b..034a9bf0dc5396dbb6e779ae1558d042c472355b 100644 GIT binary patch delta 19 Zcmeyu`h|5vI1}UM$q`HeKyoFMHvmm12Pyyn delta 19 Zcmeyu`h|5vI1}TR$q`HeKyoFMHvmmH2P^;p diff --git a/target/scala-2.12/classes/lib/ahb_to_axi4.class b/target/scala-2.12/classes/lib/ahb_to_axi4.class index 4797a7e28ee14c717844d2872d4bafff8f81dd45..dc8dd6b6008aa66b9c79d104d3cde97a5151e133 100644 GIT binary patch delta 2759 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