colin
/
quasar
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

axi to ahb update

This commit is contained in:
​Laraib Khan 2020-12-03 14:08:12 +05:00
parent 7a1457b2e2
commit 439c0adebc
4 changed files with 173 additions and 78 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

96
axi4_to_ahb.fir
View File

@ -545,14 +545,14 @@ circuit axi4_to_ahb :
node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 175:44] node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 175:44]
node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 175:62] node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 175:62]
node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 175:48] node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 175:48]
node _T_86 = mux(_T_64, UInt<1>("h00"), UInt<4>("h08")) @[Mux.scala 98:16] node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16]
node _T_87 = mux(_T_67, UInt<1>("h01"), _T_86) @[Mux.scala 98:16] node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16]
node _T_88 = mux(_T_70, UInt<2>("h02"), _T_87) @[Mux.scala 98:16] node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16]
node _T_89 = mux(_T_73, UInt<2>("h03"), _T_88) @[Mux.scala 98:16] node _T_89 = mux(_T_76, UInt<3>("h04"), _T_88) @[Mux.scala 98:16]
node _T_90 = mux(_T_76, UInt<3>("h04"), _T_89) @[Mux.scala 98:16] node _T_90 = mux(_T_73, UInt<2>("h03"), _T_89) @[Mux.scala 98:16]
node _T_91 = mux(_T_79, UInt<3>("h05"), _T_90) @[Mux.scala 98:16] node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16]
node _T_92 = mux(_T_82, UInt<3>("h06"), _T_91) @[Mux.scala 98:16] node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16]
node _T_93 = mux(_T_85, UInt<3>("h07"), _T_92) @[Mux.scala 98:16] node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16]
node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 233:124] node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 233:124]
node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 233:30] node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 233:30]
buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 233:24] buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 233:24]
@ -740,14 +740,14 @@ circuit axi4_to_ahb :
node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 175:44] node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 175:44]
node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 175:62] node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 175:62]
node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 175:48] node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 175:48]
node _T_223 = mux(_T_201, UInt<1>("h00"), UInt<4>("h08")) @[Mux.scala 98:16] node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16]
node _T_224 = mux(_T_204, UInt<1>("h01"), _T_223) @[Mux.scala 98:16] node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16]
node _T_225 = mux(_T_207, UInt<2>("h02"), _T_224) @[Mux.scala 98:16] node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16]
node _T_226 = mux(_T_210, UInt<2>("h03"), _T_225) @[Mux.scala 98:16] node _T_226 = mux(_T_213, UInt<3>("h04"), _T_225) @[Mux.scala 98:16]
node _T_227 = mux(_T_213, UInt<3>("h04"), _T_226) @[Mux.scala 98:16] node _T_227 = mux(_T_210, UInt<2>("h03"), _T_226) @[Mux.scala 98:16]
node _T_228 = mux(_T_216, UInt<3>("h05"), _T_227) @[Mux.scala 98:16] node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16]
node _T_229 = mux(_T_219, UInt<3>("h06"), _T_228) @[Mux.scala 98:16] node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16]
node _T_230 = mux(_T_222, UInt<3>("h07"), _T_229) @[Mux.scala 98:16] node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16]
node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 291:30] node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 291:30]
buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 291:24] buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 291:24]
node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 292:65] node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 292:65]
@ -781,14 +781,14 @@ circuit axi4_to_ahb :
node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 175:44] node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 175:44]
node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 175:62] node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 175:62]
node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 175:48] node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 175:48]
node _T_263 = mux(_T_241, UInt<1>("h00"), UInt<4>("h08")) @[Mux.scala 98:16] node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16]
node _T_264 = mux(_T_244, UInt<1>("h01"), _T_263) @[Mux.scala 98:16] node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16]
node _T_265 = mux(_T_247, UInt<2>("h02"), _T_264) @[Mux.scala 98:16] node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16]
node _T_266 = mux(_T_250, UInt<2>("h03"), _T_265) @[Mux.scala 98:16] node _T_266 = mux(_T_253, UInt<3>("h04"), _T_265) @[Mux.scala 98:16]
node _T_267 = mux(_T_253, UInt<3>("h04"), _T_266) @[Mux.scala 98:16] node _T_267 = mux(_T_250, UInt<2>("h03"), _T_266) @[Mux.scala 98:16]
node _T_268 = mux(_T_256, UInt<3>("h05"), _T_267) @[Mux.scala 98:16] node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16]
node _T_269 = mux(_T_259, UInt<3>("h06"), _T_268) @[Mux.scala 98:16] node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16]
node _T_270 = mux(_T_262, UInt<3>("h07"), _T_269) @[Mux.scala 98:16] node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16]
node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 292:92] node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 292:92]
node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 292:92] node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 292:92]
node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 292:163] node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 292:163]
@ -866,14 +866,14 @@ circuit axi4_to_ahb :
node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 175:44] node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 175:44]
node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 175:62] node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 175:62]
node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 175:48] node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 175:48]
node _T_335 = mux(_T_313, UInt<1>("h00"), UInt<4>("h08")) @[Mux.scala 98:16] node _T_335 = mux(_T_334, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16]
node _T_336 = mux(_T_316, UInt<1>("h01"), _T_335) @[Mux.scala 98:16] node _T_336 = mux(_T_331, UInt<3>("h06"), _T_335) @[Mux.scala 98:16]
node _T_337 = mux(_T_319, UInt<2>("h02"), _T_336) @[Mux.scala 98:16] node _T_337 = mux(_T_328, UInt<3>("h05"), _T_336) @[Mux.scala 98:16]
node _T_338 = mux(_T_322, UInt<2>("h03"), _T_337) @[Mux.scala 98:16] node _T_338 = mux(_T_325, UInt<3>("h04"), _T_337) @[Mux.scala 98:16]
node _T_339 = mux(_T_325, UInt<3>("h04"), _T_338) @[Mux.scala 98:16] node _T_339 = mux(_T_322, UInt<2>("h03"), _T_338) @[Mux.scala 98:16]
node _T_340 = mux(_T_328, UInt<3>("h05"), _T_339) @[Mux.scala 98:16] node _T_340 = mux(_T_319, UInt<2>("h02"), _T_339) @[Mux.scala 98:16]
node _T_341 = mux(_T_331, UInt<3>("h06"), _T_340) @[Mux.scala 98:16] node _T_341 = mux(_T_316, UInt<1>("h01"), _T_340) @[Mux.scala 98:16]
node _T_342 = mux(_T_334, UInt<3>("h07"), _T_341) @[Mux.scala 98:16] node _T_342 = mux(_T_313, UInt<1>("h00"), _T_341) @[Mux.scala 98:16]
node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 306:51] node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 306:51]
node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 306:51] node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 306:51]
node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 306:116] node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 306:116]
@ -930,14 +930,14 @@ circuit axi4_to_ahb :
node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 175:44] node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 175:44]
node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 175:62] node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 175:62]
node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 175:48] node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 175:48]
node _T_393 = mux(_T_371, UInt<1>("h00"), UInt<4>("h08")) @[Mux.scala 98:16] node _T_393 = mux(_T_392, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16]
node _T_394 = mux(_T_374, UInt<1>("h01"), _T_393) @[Mux.scala 98:16] node _T_394 = mux(_T_389, UInt<3>("h06"), _T_393) @[Mux.scala 98:16]
node _T_395 = mux(_T_377, UInt<2>("h02"), _T_394) @[Mux.scala 98:16] node _T_395 = mux(_T_386, UInt<3>("h05"), _T_394) @[Mux.scala 98:16]
node _T_396 = mux(_T_380, UInt<2>("h03"), _T_395) @[Mux.scala 98:16] node _T_396 = mux(_T_383, UInt<3>("h04"), _T_395) @[Mux.scala 98:16]
node _T_397 = mux(_T_383, UInt<3>("h04"), _T_396) @[Mux.scala 98:16] node _T_397 = mux(_T_380, UInt<2>("h03"), _T_396) @[Mux.scala 98:16]
node _T_398 = mux(_T_386, UInt<3>("h05"), _T_397) @[Mux.scala 98:16] node _T_398 = mux(_T_377, UInt<2>("h02"), _T_397) @[Mux.scala 98:16]
node _T_399 = mux(_T_389, UInt<3>("h06"), _T_398) @[Mux.scala 98:16] node _T_399 = mux(_T_374, UInt<1>("h01"), _T_398) @[Mux.scala 98:16]
node _T_400 = mux(_T_392, UInt<3>("h07"), _T_399) @[Mux.scala 98:16] node _T_400 = mux(_T_371, UInt<1>("h00"), _T_399) @[Mux.scala 98:16]
node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 312:141] node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 312:141]
node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 312:157] node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 312:157]
node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52]
@ -967,14 +967,14 @@ circuit axi4_to_ahb :
node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 175:44] node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 175:44]
node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 175:62] node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 175:62]
node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 175:48] node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 175:48]
node _T_430 = mux(_T_408, UInt<1>("h00"), UInt<4>("h08")) @[Mux.scala 98:16] node _T_430 = mux(_T_429, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16]
node _T_431 = mux(_T_411, UInt<1>("h01"), _T_430) @[Mux.scala 98:16] node _T_431 = mux(_T_426, UInt<3>("h06"), _T_430) @[Mux.scala 98:16]
node _T_432 = mux(_T_414, UInt<2>("h02"), _T_431) @[Mux.scala 98:16] node _T_432 = mux(_T_423, UInt<3>("h05"), _T_431) @[Mux.scala 98:16]
node _T_433 = mux(_T_417, UInt<2>("h03"), _T_432) @[Mux.scala 98:16] node _T_433 = mux(_T_420, UInt<3>("h04"), _T_432) @[Mux.scala 98:16]
node _T_434 = mux(_T_420, UInt<3>("h04"), _T_433) @[Mux.scala 98:16] node _T_434 = mux(_T_417, UInt<2>("h03"), _T_433) @[Mux.scala 98:16]
node _T_435 = mux(_T_423, UInt<3>("h05"), _T_434) @[Mux.scala 98:16] node _T_435 = mux(_T_414, UInt<2>("h02"), _T_434) @[Mux.scala 98:16]
node _T_436 = mux(_T_426, UInt<3>("h06"), _T_435) @[Mux.scala 98:16] node _T_436 = mux(_T_411, UInt<1>("h01"), _T_435) @[Mux.scala 98:16]
node _T_437 = mux(_T_429, UInt<3>("h07"), _T_436) @[Mux.scala 98:16] node _T_437 = mux(_T_408, UInt<1>("h00"), _T_436) @[Mux.scala 98:16]
node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 312:97] node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 312:97]
node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 312:30] node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 312:30]
buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 312:24] buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 312:24]

151
axi4_to_ahb.v
View File

@ -263,15 +263,14 @@ module axi4_to_ahb(
wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 199:74] wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 199:74]
wire _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 230:54] wire _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 230:54]
wire _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 230:38] wire _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 230:38]
wire [3:0] _T_86 = wrbuf_byteen[0] ? 4'h0 : 4'h8; // @[Mux.scala 98:16] wire [2:0] _T_87 = wrbuf_byteen[6] ? 3'h6 : 3'h7; // @[Mux.scala 98:16]
wire [3:0] _T_87 = wrbuf_byteen[1] ? 4'h1 : _T_86; // @[Mux.scala 98:16] wire [2:0] _T_88 = wrbuf_byteen[5] ? 3'h5 : _T_87; // @[Mux.scala 98:16]
wire [3:0] _T_88 = wrbuf_byteen[2] ? 4'h2 : _T_87; // @[Mux.scala 98:16] wire [2:0] _T_89 = wrbuf_byteen[4] ? 3'h4 : _T_88; // @[Mux.scala 98:16]
wire [3:0] _T_89 = wrbuf_byteen[3] ? 4'h3 : _T_88; // @[Mux.scala 98:16] wire [2:0] _T_90 = wrbuf_byteen[3] ? 3'h3 : _T_89; // @[Mux.scala 98:16]
wire [3:0] _T_90 = wrbuf_byteen[4] ? 4'h4 : _T_89; // @[Mux.scala 98:16] wire [2:0] _T_91 = wrbuf_byteen[2] ? 3'h2 : _T_90; // @[Mux.scala 98:16]
wire [3:0] _T_91 = wrbuf_byteen[5] ? 4'h5 : _T_90; // @[Mux.scala 98:16] wire [2:0] _T_92 = wrbuf_byteen[1] ? 3'h1 : _T_91; // @[Mux.scala 98:16]
wire [3:0] _T_92 = wrbuf_byteen[6] ? 4'h6 : _T_91; // @[Mux.scala 98:16] wire [2:0] _T_93 = wrbuf_byteen[0] ? 3'h0 : _T_92; // @[Mux.scala 98:16]
wire [3:0] _T_93 = wrbuf_byteen[7] ? 4'h7 : _T_92; // @[Mux.scala 98:16] wire [2:0] _T_95 = buf_write_in ? _T_93 : master_addr[2:0]; // @[axi4_to_ahb.scala 233:30]
wire [3:0] _T_95 = buf_write_in ? _T_93 : {{1'd0}, master_addr[2:0]}; // @[axi4_to_ahb.scala 233:30]
wire _T_96 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 235:51] wire _T_96 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 235:51]
wire _T_126 = master_ready & master_valid; // @[axi4_to_ahb.scala 246:33] wire _T_126 = master_ready & master_valid; // @[axi4_to_ahb.scala 246:33]
wire _T_162 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 261:64] wire _T_162 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 261:64]
@ -320,15 +319,14 @@ module axi4_to_ahb(
wire _T_216 = buf_byteen[5] & _T_215; // @[axi4_to_ahb.scala 175:48] wire _T_216 = buf_byteen[5] & _T_215; // @[axi4_to_ahb.scala 175:48]
wire _T_218 = 3'h6 >= _T_197; // @[axi4_to_ahb.scala 175:62] wire _T_218 = 3'h6 >= _T_197; // @[axi4_to_ahb.scala 175:62]
wire _T_219 = buf_byteen[6] & _T_218; // @[axi4_to_ahb.scala 175:48] wire _T_219 = buf_byteen[6] & _T_218; // @[axi4_to_ahb.scala 175:48]
wire [3:0] _T_223 = _T_201 ? 4'h0 : 4'h8; // @[Mux.scala 98:16] wire [2:0] _T_224 = _T_219 ? 3'h6 : 3'h7; // @[Mux.scala 98:16]
wire [3:0] _T_224 = _T_204 ? 4'h1 : _T_223; // @[Mux.scala 98:16] wire [2:0] _T_225 = _T_216 ? 3'h5 : _T_224; // @[Mux.scala 98:16]
wire [3:0] _T_225 = _T_207 ? 4'h2 : _T_224; // @[Mux.scala 98:16] wire [2:0] _T_226 = _T_213 ? 3'h4 : _T_225; // @[Mux.scala 98:16]
wire [3:0] _T_226 = _T_210 ? 4'h3 : _T_225; // @[Mux.scala 98:16] wire [2:0] _T_227 = _T_210 ? 3'h3 : _T_226; // @[Mux.scala 98:16]
wire [3:0] _T_227 = _T_213 ? 4'h4 : _T_226; // @[Mux.scala 98:16] wire [2:0] _T_228 = _T_207 ? 3'h2 : _T_227; // @[Mux.scala 98:16]
wire [3:0] _T_228 = _T_216 ? 4'h5 : _T_227; // @[Mux.scala 98:16] wire [2:0] _T_229 = _T_204 ? 3'h1 : _T_228; // @[Mux.scala 98:16]
wire [3:0] _T_229 = _T_219 ? 4'h6 : _T_228; // @[Mux.scala 98:16] wire [2:0] _T_230 = _T_201 ? 3'h0 : _T_229; // @[Mux.scala 98:16]
wire [3:0] _T_230 = buf_byteen[7] ? 4'h7 : _T_229; // @[Mux.scala 98:16] wire [2:0] _T_231 = trxn_done ? _T_230 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 291:30]
wire [3:0] _T_231 = trxn_done ? _T_230 : {{1'd0}, buf_cmd_byte_ptrQ}; // @[axi4_to_ahb.scala 291:30]
wire _T_232 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 292:65] wire _T_232 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 292:65]
reg buf_aligned; // @[Reg.scala 27:20] reg buf_aligned; // @[Reg.scala 27:20]
wire _T_233 = buf_aligned | _T_232; // @[axi4_to_ahb.scala 292:44] wire _T_233 = buf_aligned | _T_232; // @[axi4_to_ahb.scala 292:44]
@ -356,7 +354,7 @@ module axi4_to_ahb(
wire [1:0] _T_356 = _T_354 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_356 = _T_354 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_357 = _T_356 & 2'h2; // @[axi4_to_ahb.scala 308:71] wire [1:0] _T_357 = _T_356 & 2'h2; // @[axi4_to_ahb.scala 308:71]
wire _T_364 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 311:40] wire _T_364 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 311:40]
wire [3:0] _T_439 = bypass_en ? _T_93 : _T_231; // @[axi4_to_ahb.scala 312:30] wire [2:0] _T_439 = bypass_en ? _T_93 : _T_231; // @[axi4_to_ahb.scala 312:30]
wire _GEN_6 = _T_281 & ahb_hresp_q; // @[Conditional.scala 39:67] wire _GEN_6 = _T_281 & ahb_hresp_q; // @[Conditional.scala 39:67]
wire _GEN_7 = _T_281 ? buf_state_en : _T_440; // @[Conditional.scala 39:67] wire _GEN_7 = _T_281 ? buf_state_en : _T_440; // @[Conditional.scala 39:67]
wire _GEN_9 = _T_281 & _T_301; // @[Conditional.scala 39:67] wire _GEN_9 = _T_281 & _T_301; // @[Conditional.scala 39:67]
@ -369,10 +367,10 @@ module axi4_to_ahb(
wire _GEN_10 = _T_281 & buf_wr_en; // @[Conditional.scala 39:67] wire _GEN_10 = _T_281 & buf_wr_en; // @[Conditional.scala 39:67]
wire [1:0] _GEN_13 = _T_281 ? _T_357 : 2'h0; // @[Conditional.scala 39:67] wire [1:0] _GEN_13 = _T_281 ? _T_357 : 2'h0; // @[Conditional.scala 39:67]
wire _GEN_16 = _T_281 & _T_364; // @[Conditional.scala 39:67] wire _GEN_16 = _T_281 & _T_364; // @[Conditional.scala 39:67]
wire [3:0] _GEN_17 = _T_281 ? _T_439 : 4'h0; // @[Conditional.scala 39:67] wire [2:0] _GEN_17 = _T_281 ? _T_439 : 3'h0; // @[Conditional.scala 39:67]
wire _GEN_21 = _T_188 ? buf_state_en : _GEN_16; // @[Conditional.scala 39:67] wire _GEN_21 = _T_188 ? buf_state_en : _GEN_16; // @[Conditional.scala 39:67]
wire _GEN_22 = _T_188 & buf_state_en; // @[Conditional.scala 39:67] wire _GEN_22 = _T_188 & buf_state_en; // @[Conditional.scala 39:67]
wire [3:0] _GEN_23 = _T_188 ? _T_231 : _GEN_17; // @[Conditional.scala 39:67] wire [2:0] _GEN_23 = _T_188 ? _T_231 : _GEN_17; // @[Conditional.scala 39:67]
wire [1:0] _GEN_25 = _T_188 ? _T_280 : _GEN_13; // @[Conditional.scala 39:67] wire [1:0] _GEN_25 = _T_188 ? _T_280 : _GEN_13; // @[Conditional.scala 39:67]
wire _GEN_28 = _T_188 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67] wire _GEN_28 = _T_188 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67]
wire _GEN_31 = _T_188 ? 1'h0 : _GEN_10; // @[Conditional.scala 39:67] wire _GEN_31 = _T_188 ? 1'h0 : _GEN_10; // @[Conditional.scala 39:67]
@ -380,29 +378,29 @@ module axi4_to_ahb(
wire _GEN_38 = _T_186 ? buf_state_en : _GEN_28; // @[Conditional.scala 39:67] wire _GEN_38 = _T_186 ? buf_state_en : _GEN_28; // @[Conditional.scala 39:67]
wire _GEN_39 = _T_186 ? buf_state_en : _GEN_22; // @[Conditional.scala 39:67] wire _GEN_39 = _T_186 ? buf_state_en : _GEN_22; // @[Conditional.scala 39:67]
wire _GEN_41 = _T_186 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67] wire _GEN_41 = _T_186 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67]
wire [3:0] _GEN_42 = _T_186 ? 4'h0 : _GEN_23; // @[Conditional.scala 39:67] wire [2:0] _GEN_42 = _T_186 ? 3'h0 : _GEN_23; // @[Conditional.scala 39:67]
wire [1:0] _GEN_44 = _T_186 ? 2'h0 : _GEN_25; // @[Conditional.scala 39:67] wire [1:0] _GEN_44 = _T_186 ? 2'h0 : _GEN_25; // @[Conditional.scala 39:67]
wire _GEN_53 = _T_175 ? buf_state_en : _GEN_39; // @[Conditional.scala 39:67] wire _GEN_53 = _T_175 ? buf_state_en : _GEN_39; // @[Conditional.scala 39:67]
wire [3:0] _GEN_54 = _T_175 ? {{1'd0}, buf_addr[2:0]} : _GEN_42; // @[Conditional.scala 39:67] wire [2:0] _GEN_54 = _T_175 ? buf_addr[2:0] : _GEN_42; // @[Conditional.scala 39:67]
wire [1:0] _GEN_55 = _T_175 ? _T_185 : _GEN_44; // @[Conditional.scala 39:67] wire [1:0] _GEN_55 = _T_175 ? _T_185 : _GEN_44; // @[Conditional.scala 39:67]
wire _GEN_56 = _T_175 ? 1'h0 : _GEN_36; // @[Conditional.scala 39:67] wire _GEN_56 = _T_175 ? 1'h0 : _GEN_36; // @[Conditional.scala 39:67]
wire _GEN_58 = _T_175 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67] wire _GEN_58 = _T_175 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67]
wire _GEN_60 = _T_175 ? 1'h0 : _GEN_41; // @[Conditional.scala 39:67] wire _GEN_60 = _T_175 ? 1'h0 : _GEN_41; // @[Conditional.scala 39:67]
wire _GEN_70 = _T_136 ? buf_state_en : _GEN_56; // @[Conditional.scala 39:67] wire _GEN_70 = _T_136 ? buf_state_en : _GEN_56; // @[Conditional.scala 39:67]
wire _GEN_72 = _T_136 ? buf_state_en : _GEN_58; // @[Conditional.scala 39:67] wire _GEN_72 = _T_136 ? buf_state_en : _GEN_58; // @[Conditional.scala 39:67]
wire [3:0] _GEN_76 = _T_136 ? {{1'd0}, _T_130} : _GEN_54; // @[Conditional.scala 39:67] wire [2:0] _GEN_76 = _T_136 ? _T_130 : _GEN_54; // @[Conditional.scala 39:67]
wire [1:0] _GEN_77 = _T_136 ? _T_174 : _GEN_55; // @[Conditional.scala 39:67] wire [1:0] _GEN_77 = _T_136 ? _T_174 : _GEN_55; // @[Conditional.scala 39:67]
wire _GEN_78 = _T_136 ? buf_wr_en : _GEN_53; // @[Conditional.scala 39:67] wire _GEN_78 = _T_136 ? buf_wr_en : _GEN_53; // @[Conditional.scala 39:67]
wire _GEN_80 = _T_136 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67] wire _GEN_80 = _T_136 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67]
wire _GEN_85 = _T_101 ? buf_state_en : _GEN_78; // @[Conditional.scala 39:67] wire _GEN_85 = _T_101 ? buf_state_en : _GEN_78; // @[Conditional.scala 39:67]
wire [3:0] _GEN_89 = _T_101 ? {{1'd0}, _T_130} : _GEN_76; // @[Conditional.scala 39:67] wire [2:0] _GEN_89 = _T_101 ? _T_130 : _GEN_76; // @[Conditional.scala 39:67]
wire [1:0] _GEN_90 = _T_101 ? _T_135 : _GEN_77; // @[Conditional.scala 39:67] wire [1:0] _GEN_90 = _T_101 ? _T_135 : _GEN_77; // @[Conditional.scala 39:67]
wire _GEN_91 = _T_101 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67] wire _GEN_91 = _T_101 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67]
wire _GEN_93 = _T_101 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67] wire _GEN_93 = _T_101 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67]
wire _GEN_96 = _T_101 ? 1'h0 : _GEN_80; // @[Conditional.scala 39:67] wire _GEN_96 = _T_101 ? 1'h0 : _GEN_80; // @[Conditional.scala 39:67]
wire buf_data_wr_en = _T_49 ? _T_56 : _GEN_91; // @[Conditional.scala 40:58] wire buf_data_wr_en = _T_49 ? _T_56 : _GEN_91; // @[Conditional.scala 40:58]
wire buf_cmd_byte_ptr_en = _T_49 ? buf_state_en : _GEN_96; // @[Conditional.scala 40:58] wire buf_cmd_byte_ptr_en = _T_49 ? buf_state_en : _GEN_96; // @[Conditional.scala 40:58]
wire [3:0] _GEN_105 = _T_49 ? _T_95 : _GEN_89; // @[Conditional.scala 40:58] wire [2:0] buf_cmd_byte_ptr = _T_49 ? _T_95 : _GEN_89; // @[Conditional.scala 40:58]
wire slvbuf_wr_en = _T_49 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] wire slvbuf_wr_en = _T_49 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58]
wire slvbuf_error_en = _T_49 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58] wire slvbuf_error_en = _T_49 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58]
wire _T_535 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 348:24] wire _T_535 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 348:24]
@ -453,7 +451,6 @@ module axi4_to_ahb(
wire [1:0] _T_528 = 2'h1 & _T_527; // @[axi4_to_ahb.scala 162:21] wire [1:0] _T_528 = 2'h1 & _T_527; // @[axi4_to_ahb.scala 162:21]
wire [1:0] _T_529 = _T_514 | _T_528; // @[axi4_to_ahb.scala 161:93] wire [1:0] _T_529 = _T_514 | _T_528; // @[axi4_to_ahb.scala 161:93]
wire [1:0] _T_531 = _T_498 ? _T_529 : master_size[1:0]; // @[axi4_to_ahb.scala 346:21] wire [1:0] _T_531 = _T_498 ? _T_529 : master_size[1:0]; // @[axi4_to_ahb.scala 346:21]
wire [2:0] buf_cmd_byte_ptr = _GEN_105[2:0]; // @[axi4_to_ahb.scala 217:20 axi4_to_ahb.scala 233:24 axi4_to_ahb.scala 247:24 axi4_to_ahb.scala 262:24 axi4_to_ahb.scala 272:24 axi4_to_ahb.scala 291:24 axi4_to_ahb.scala 312:24]
wire [31:0] _T_570 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] wire [31:0] _T_570 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58]
wire [31:0] _T_573 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] wire [31:0] _T_573 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58]
wire [1:0] _T_577 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_577 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
@ -973,7 +970,105 @@ end // initial
if (reset) begin if (reset) begin
buf_cmd_byte_ptrQ <= 3'h0; buf_cmd_byte_ptrQ <= 3'h0;
end else if (buf_cmd_byte_ptr_en) begin end else if (buf_cmd_byte_ptr_en) begin
buf_cmd_byte_ptrQ <= buf_cmd_byte_ptr; if (_T_49) begin
if (buf_write_in) begin
if (wrbuf_byteen[0]) begin
buf_cmd_byte_ptrQ <= 3'h0;
end else if (wrbuf_byteen[1]) begin
buf_cmd_byte_ptrQ <= 3'h1;
end else if (wrbuf_byteen[2]) begin
buf_cmd_byte_ptrQ <= 3'h2;
end else if (wrbuf_byteen[3]) begin
buf_cmd_byte_ptrQ <= 3'h3;
end else if (wrbuf_byteen[4]) begin
buf_cmd_byte_ptrQ <= 3'h4;
end else if (wrbuf_byteen[5]) begin
buf_cmd_byte_ptrQ <= 3'h5;
end else if (wrbuf_byteen[6]) begin
buf_cmd_byte_ptrQ <= 3'h6;
end else begin
buf_cmd_byte_ptrQ <= 3'h7;
end
end else begin
buf_cmd_byte_ptrQ <= master_addr[2:0];
end
end else if (_T_101) begin
if (bypass_en) begin
buf_cmd_byte_ptrQ <= master_addr[2:0];
end else begin
buf_cmd_byte_ptrQ <= buf_addr[2:0];
end
end else if (_T_136) begin
if (bypass_en) begin
buf_cmd_byte_ptrQ <= master_addr[2:0];
end else begin
buf_cmd_byte_ptrQ <= buf_addr[2:0];
end
end else if (_T_175) begin
buf_cmd_byte_ptrQ <= buf_addr[2:0];
end else if (_T_186) begin
buf_cmd_byte_ptrQ <= 3'h0;
end else if (_T_188) begin
if (trxn_done) begin
if (_T_201) begin
buf_cmd_byte_ptrQ <= 3'h0;
end else if (_T_204) begin
buf_cmd_byte_ptrQ <= 3'h1;
end else if (_T_207) begin
buf_cmd_byte_ptrQ <= 3'h2;
end else if (_T_210) begin
buf_cmd_byte_ptrQ <= 3'h3;
end else if (_T_213) begin
buf_cmd_byte_ptrQ <= 3'h4;
end else if (_T_216) begin
buf_cmd_byte_ptrQ <= 3'h5;
end else if (_T_219) begin
buf_cmd_byte_ptrQ <= 3'h6;
end else begin
buf_cmd_byte_ptrQ <= 3'h7;
end
end
end else if (_T_281) begin
if (bypass_en) begin
if (wrbuf_byteen[0]) begin
buf_cmd_byte_ptrQ <= 3'h0;
end else if (wrbuf_byteen[1]) begin
buf_cmd_byte_ptrQ <= 3'h1;
end else if (wrbuf_byteen[2]) begin
buf_cmd_byte_ptrQ <= 3'h2;
end else if (wrbuf_byteen[3]) begin
buf_cmd_byte_ptrQ <= 3'h3;
end else if (wrbuf_byteen[4]) begin
buf_cmd_byte_ptrQ <= 3'h4;
end else if (wrbuf_byteen[5]) begin
buf_cmd_byte_ptrQ <= 3'h5;
end else if (wrbuf_byteen[6]) begin
buf_cmd_byte_ptrQ <= 3'h6;
end else begin
buf_cmd_byte_ptrQ <= 3'h7;
end
end else if (trxn_done) begin
if (_T_201) begin
buf_cmd_byte_ptrQ <= 3'h0;
end else if (_T_204) begin
buf_cmd_byte_ptrQ <= 3'h1;
end else if (_T_207) begin
buf_cmd_byte_ptrQ <= 3'h2;
end else if (_T_210) begin
buf_cmd_byte_ptrQ <= 3'h3;
end else if (_T_213) begin
buf_cmd_byte_ptrQ <= 3'h4;
end else if (_T_216) begin
buf_cmd_byte_ptrQ <= 3'h5;
end else if (_T_219) begin
buf_cmd_byte_ptrQ <= 3'h6;
end else begin
buf_cmd_byte_ptrQ <= 3'h7;
end
end
end else begin
buf_cmd_byte_ptrQ <= 3'h0;
end
end end
end end
always @(posedge buf_clk or posedge reset) begin always @(posedge buf_clk or posedge reset) begin

4
src/main/scala/lib/axi4_to_ahb.scala
View File

@ -172,8 +172,8 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
} }
def get_nxtbyte_ptr(current_byte_ptr: UInt, byteen: UInt, get_next: Bool): UInt = { def get_nxtbyte_ptr(current_byte_ptr: UInt, byteen: UInt, get_next: Bool): UInt = {
val start_ptr = Mux(get_next, current_byte_ptr + 1.U, current_byte_ptr) val start_ptr = Mux(get_next, current_byte_ptr + 1.U, current_byte_ptr)
val temp = (0 until 8).map(j => (byteen(j) & (j.asUInt() >= start_ptr)) -> j.U).reverse val temp = (0 until 8).map(j => (byteen(j) & (j.asUInt() >= start_ptr)) -> j.U)
MuxCase(8.U, temp) MuxCase(7.U, temp)
} }
wr_cmd_vld := wrbuf_vld & wrbuf_data_vld wr_cmd_vld := wrbuf_vld & wrbuf_data_vld
master_valid := wr_cmd_vld | io.axi_arvalid master_valid := wr_cmd_vld | io.axi_arvalid

BIN
target/scala-2.12/classes/lib/axi4_to_ahb.class
View File

Binary file not shown.