diff --git a/axi4_to_ahb.fir b/axi4_to_ahb.fir index 20a8c118..8add4ba2 100644 --- a/axi4_to_ahb.fir +++ b/axi4_to_ahb.fir @@ -123,16 +123,18 @@ circuit axi4_to_ahb : buf_nxtstate <= UInt<3>("h00") node _T_2 = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 36:62] wire _T_3 : UInt @[lib.scala 389:21] - node _T_4 = eq(buf_rst, UInt<1>("h00")) @[lib.scala 391:75] - node _T_5 = and(buf_nxtstate, _T_4) @[lib.scala 391:53] - node _T_6 = or(_T_2, buf_rst) @[lib.scala 391:95] - node _T_7 = and(_T_6, io.bus_clk_en) @[lib.scala 391:102] - node _T_8 = bits(_T_7, 0, 0) @[lib.scala 8:44] - reg _T_9 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_8 : @[Reg.scala 28:19] - _T_9 <= _T_5 @[Reg.scala 28:23] + node _T_4 = eq(buf_rst, UInt<1>("h00")) @[lib.scala 391:73] + node _T_5 = bits(_T_4, 0, 0) @[Bitwise.scala 72:15] + node _T_6 = mux(_T_5, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_7 = and(buf_nxtstate, _T_6) @[lib.scala 391:53] + node _T_8 = or(_T_2, buf_rst) @[lib.scala 391:92] + node _T_9 = and(_T_8, io.bus_clk_en) @[lib.scala 391:99] + node _T_10 = bits(_T_9, 0, 0) @[lib.scala 8:44] + reg _T_11 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_10 : @[Reg.scala 28:19] + _T_11 <= _T_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - _T_3 <= _T_9 @[lib.scala 391:14] + _T_3 <= _T_11 @[lib.scala 391:14] buf_state <= _T_3 @[axi4_to_ahb.scala 36:13] wire slave_valid : UInt<1> slave_valid <= UInt<1>("h00") @@ -271,1001 +273,1001 @@ circuit axi4_to_ahb : wire ahbm_data_clken : UInt<1> ahbm_data_clken <= UInt<1>("h00") wire buf_clk : Clock @[axi4_to_ahb.scala 118:21] - node _T_10 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 140:27] - wr_cmd_vld <= _T_10 @[axi4_to_ahb.scala 140:14] - node _T_11 = or(wr_cmd_vld, io.axi.ar.valid) @[axi4_to_ahb.scala 141:30] - master_valid <= _T_11 @[axi4_to_ahb.scala 141:16] - node _T_12 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 142:38] - node _T_13 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 142:51] - node _T_14 = bits(io.axi.ar.bits.id, 0, 0) @[axi4_to_ahb.scala 142:82] - node _T_15 = mux(_T_12, _T_13, _T_14) @[axi4_to_ahb.scala 142:20] - master_tag <= _T_15 @[axi4_to_ahb.scala 142:14] - node _T_16 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 143:38] - node _T_17 = mux(_T_16, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 143:20] - master_opc <= _T_17 @[axi4_to_ahb.scala 143:14] - node _T_18 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 144:39] - node _T_19 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 144:53] - node _T_20 = bits(io.axi.ar.bits.addr, 31, 0) @[axi4_to_ahb.scala 144:81] - node _T_21 = mux(_T_18, _T_19, _T_20) @[axi4_to_ahb.scala 144:21] - master_addr <= _T_21 @[axi4_to_ahb.scala 144:15] - node _T_22 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 145:39] - node _T_23 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 145:53] - node _T_24 = bits(io.axi.ar.bits.size, 2, 0) @[axi4_to_ahb.scala 145:80] - node _T_25 = mux(_T_22, _T_23, _T_24) @[axi4_to_ahb.scala 145:21] - master_size <= _T_25 @[axi4_to_ahb.scala 145:15] - node _T_26 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 146:32] - master_byteen <= _T_26 @[axi4_to_ahb.scala 146:17] - node _T_27 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 147:29] - master_wdata <= _T_27 @[axi4_to_ahb.scala 147:16] - node _T_28 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 150:33] - node _T_29 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 150:58] - node _T_30 = and(_T_28, _T_29) @[axi4_to_ahb.scala 150:47] - io.axi.b.valid <= _T_30 @[axi4_to_ahb.scala 150:18] - node _T_31 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 151:38] - node _T_32 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 151:65] - node _T_33 = mux(_T_32, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 151:55] - node _T_34 = mux(_T_31, UInt<2>("h02"), _T_33) @[axi4_to_ahb.scala 151:28] - io.axi.b.bits.resp <= _T_34 @[axi4_to_ahb.scala 151:22] - node _T_35 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 152:32] - io.axi.b.bits.id <= _T_35 @[axi4_to_ahb.scala 152:20] - node _T_36 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 154:33] - node _T_37 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 154:59] - node _T_38 = eq(_T_37, UInt<1>("h00")) @[axi4_to_ahb.scala 154:66] - node _T_39 = and(_T_36, _T_38) @[axi4_to_ahb.scala 154:47] - io.axi.r.valid <= _T_39 @[axi4_to_ahb.scala 154:18] - node _T_40 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 155:38] - node _T_41 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 155:65] - node _T_42 = mux(_T_41, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 155:55] - node _T_43 = mux(_T_40, UInt<2>("h02"), _T_42) @[axi4_to_ahb.scala 155:28] - io.axi.r.bits.resp <= _T_43 @[axi4_to_ahb.scala 155:22] - node _T_44 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 156:32] - io.axi.r.bits.id <= _T_44 @[axi4_to_ahb.scala 156:20] - node _T_45 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 157:36] - io.axi.r.bits.data <= _T_45 @[axi4_to_ahb.scala 157:22] - node _T_46 = and(io.axi.b.ready, io.axi.r.ready) @[axi4_to_ahb.scala 158:33] - slave_ready <= _T_46 @[axi4_to_ahb.scala 158:15] - node _T_47 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] - when _T_47 : @[Conditional.scala 40:58] + node _T_12 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 140:27] + wr_cmd_vld <= _T_12 @[axi4_to_ahb.scala 140:14] + node _T_13 = or(wr_cmd_vld, io.axi.ar.valid) @[axi4_to_ahb.scala 141:30] + master_valid <= _T_13 @[axi4_to_ahb.scala 141:16] + node _T_14 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 142:38] + node _T_15 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 142:51] + node _T_16 = bits(io.axi.ar.bits.id, 0, 0) @[axi4_to_ahb.scala 142:82] + node _T_17 = mux(_T_14, _T_15, _T_16) @[axi4_to_ahb.scala 142:20] + master_tag <= _T_17 @[axi4_to_ahb.scala 142:14] + node _T_18 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 143:38] + node _T_19 = mux(_T_18, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 143:20] + master_opc <= _T_19 @[axi4_to_ahb.scala 143:14] + node _T_20 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 144:39] + node _T_21 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 144:53] + node _T_22 = bits(io.axi.ar.bits.addr, 31, 0) @[axi4_to_ahb.scala 144:81] + node _T_23 = mux(_T_20, _T_21, _T_22) @[axi4_to_ahb.scala 144:21] + master_addr <= _T_23 @[axi4_to_ahb.scala 144:15] + node _T_24 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 145:39] + node _T_25 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 145:53] + node _T_26 = bits(io.axi.ar.bits.size, 2, 0) @[axi4_to_ahb.scala 145:80] + node _T_27 = mux(_T_24, _T_25, _T_26) @[axi4_to_ahb.scala 145:21] + master_size <= _T_27 @[axi4_to_ahb.scala 145:15] + node _T_28 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 146:32] + master_byteen <= _T_28 @[axi4_to_ahb.scala 146:17] + node _T_29 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 147:29] + master_wdata <= _T_29 @[axi4_to_ahb.scala 147:16] + node _T_30 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 150:33] + node _T_31 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 150:58] + node _T_32 = and(_T_30, _T_31) @[axi4_to_ahb.scala 150:47] + io.axi.b.valid <= _T_32 @[axi4_to_ahb.scala 150:18] + node _T_33 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 151:38] + node _T_34 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 151:65] + node _T_35 = mux(_T_34, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 151:55] + node _T_36 = mux(_T_33, UInt<2>("h02"), _T_35) @[axi4_to_ahb.scala 151:28] + io.axi.b.bits.resp <= _T_36 @[axi4_to_ahb.scala 151:22] + node _T_37 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 152:32] + io.axi.b.bits.id <= _T_37 @[axi4_to_ahb.scala 152:20] + node _T_38 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 154:33] + node _T_39 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 154:59] + node _T_40 = eq(_T_39, UInt<1>("h00")) @[axi4_to_ahb.scala 154:66] + node _T_41 = and(_T_38, _T_40) @[axi4_to_ahb.scala 154:47] + io.axi.r.valid <= _T_41 @[axi4_to_ahb.scala 154:18] + node _T_42 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 155:38] + node _T_43 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 155:65] + node _T_44 = mux(_T_43, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 155:55] + node _T_45 = mux(_T_42, UInt<2>("h02"), _T_44) @[axi4_to_ahb.scala 155:28] + io.axi.r.bits.resp <= _T_45 @[axi4_to_ahb.scala 155:22] + node _T_46 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 156:32] + io.axi.r.bits.id <= _T_46 @[axi4_to_ahb.scala 156:20] + node _T_47 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 157:36] + io.axi.r.bits.data <= _T_47 @[axi4_to_ahb.scala 157:22] + node _T_48 = and(io.axi.b.ready, io.axi.r.ready) @[axi4_to_ahb.scala 158:33] + slave_ready <= _T_48 @[axi4_to_ahb.scala 158:15] + node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] + when _T_49 : @[Conditional.scala 40:58] master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 162:20] - node _T_48 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 163:34] - node _T_49 = eq(_T_48, UInt<1>("h01")) @[axi4_to_ahb.scala 163:41] - buf_write_in <= _T_49 @[axi4_to_ahb.scala 163:20] - node _T_50 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 164:46] - node _T_51 = mux(_T_50, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 164:26] - buf_nxtstate <= _T_51 @[axi4_to_ahb.scala 164:20] - node _T_52 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 165:36] - buf_state_en <= _T_52 @[axi4_to_ahb.scala 165:20] + node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 163:34] + node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 163:41] + buf_write_in <= _T_51 @[axi4_to_ahb.scala 163:20] + node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 164:46] + node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 164:26] + buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 164:20] + node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 165:36] + buf_state_en <= _T_54 @[axi4_to_ahb.scala 165:20] buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 166:17] - node _T_53 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 167:54] - node _T_54 = and(buf_state_en, _T_53) @[axi4_to_ahb.scala 167:38] - buf_data_wr_en <= _T_54 @[axi4_to_ahb.scala 167:22] + node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 167:54] + node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 167:38] + buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 167:22] buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 168:27] - node _T_55 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 169:50] - node _T_56 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 169:94] - node _T_57 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 136:52] - node _T_58 = tail(_T_57, 1) @[axi4_to_ahb.scala 136:52] - node _T_59 = mux(UInt<1>("h00"), _T_58, UInt<3>("h00")) @[axi4_to_ahb.scala 136:24] - node _T_60 = bits(_T_56, 0, 0) @[axi4_to_ahb.scala 137:44] - node _T_61 = geq(UInt<1>("h00"), _T_59) @[axi4_to_ahb.scala 137:62] - node _T_62 = and(_T_60, _T_61) @[axi4_to_ahb.scala 137:48] - node _T_63 = bits(_T_56, 1, 1) @[axi4_to_ahb.scala 137:44] - node _T_64 = geq(UInt<1>("h01"), _T_59) @[axi4_to_ahb.scala 137:62] - node _T_65 = and(_T_63, _T_64) @[axi4_to_ahb.scala 137:48] - node _T_66 = bits(_T_56, 2, 2) @[axi4_to_ahb.scala 137:44] - node _T_67 = geq(UInt<2>("h02"), _T_59) @[axi4_to_ahb.scala 137:62] - node _T_68 = and(_T_66, _T_67) @[axi4_to_ahb.scala 137:48] - node _T_69 = bits(_T_56, 3, 3) @[axi4_to_ahb.scala 137:44] - node _T_70 = geq(UInt<2>("h03"), _T_59) @[axi4_to_ahb.scala 137:62] - node _T_71 = and(_T_69, _T_70) @[axi4_to_ahb.scala 137:48] - node _T_72 = bits(_T_56, 4, 4) @[axi4_to_ahb.scala 137:44] - node _T_73 = geq(UInt<3>("h04"), _T_59) @[axi4_to_ahb.scala 137:62] - node _T_74 = and(_T_72, _T_73) @[axi4_to_ahb.scala 137:48] - node _T_75 = bits(_T_56, 5, 5) @[axi4_to_ahb.scala 137:44] - node _T_76 = geq(UInt<3>("h05"), _T_59) @[axi4_to_ahb.scala 137:62] - node _T_77 = and(_T_75, _T_76) @[axi4_to_ahb.scala 137:48] - node _T_78 = bits(_T_56, 6, 6) @[axi4_to_ahb.scala 137:44] - node _T_79 = geq(UInt<3>("h06"), _T_59) @[axi4_to_ahb.scala 137:62] - node _T_80 = and(_T_78, _T_79) @[axi4_to_ahb.scala 137:48] - node _T_81 = bits(_T_56, 7, 7) @[axi4_to_ahb.scala 137:44] - node _T_82 = geq(UInt<3>("h07"), _T_59) @[axi4_to_ahb.scala 137:62] - node _T_83 = and(_T_81, _T_82) @[axi4_to_ahb.scala 137:48] - node _T_84 = mux(_T_83, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_85 = mux(_T_80, UInt<3>("h06"), _T_84) @[Mux.scala 98:16] - node _T_86 = mux(_T_77, UInt<3>("h05"), _T_85) @[Mux.scala 98:16] - node _T_87 = mux(_T_74, UInt<3>("h04"), _T_86) @[Mux.scala 98:16] - node _T_88 = mux(_T_71, UInt<2>("h03"), _T_87) @[Mux.scala 98:16] - node _T_89 = mux(_T_68, UInt<2>("h02"), _T_88) @[Mux.scala 98:16] - node _T_90 = mux(_T_65, UInt<1>("h01"), _T_89) @[Mux.scala 98:16] - node _T_91 = mux(_T_62, UInt<1>("h00"), _T_90) @[Mux.scala 98:16] - node _T_92 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 169:124] - node _T_93 = mux(_T_55, _T_91, _T_92) @[axi4_to_ahb.scala 169:30] - buf_cmd_byte_ptr <= _T_93 @[axi4_to_ahb.scala 169:24] + node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 169:50] + node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 169:94] + node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 136:52] + node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 136:52] + node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 136:24] + node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 137:44] + node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 137:62] + node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 137:48] + node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 137:44] + node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 137:62] + node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 137:48] + node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 137:44] + node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 137:62] + node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 137:48] + node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 137:44] + node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 137:62] + node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 137:48] + node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 137:44] + node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 137:62] + node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 137:48] + node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 137:44] + node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 137:62] + node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 137:48] + node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 137:44] + node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 137:62] + node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 137:48] + node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 137:44] + node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 137:62] + node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 137:48] + node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] + node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] + node _T_89 = mux(_T_76, UInt<3>("h04"), _T_88) @[Mux.scala 98:16] + node _T_90 = mux(_T_73, UInt<2>("h03"), _T_89) @[Mux.scala 98:16] + node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] + node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] + node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] + node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 169:124] + node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 169:30] + buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 169:24] bypass_en <= buf_state_en @[axi4_to_ahb.scala 170:17] - node _T_94 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 171:51] - node _T_95 = and(bypass_en, _T_94) @[axi4_to_ahb.scala 171:35] - rd_bypass_idle <= _T_95 @[axi4_to_ahb.scala 171:22] - node _T_96 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] - node _T_97 = mux(_T_96, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_98 = and(_T_97, UInt<2>("h02")) @[axi4_to_ahb.scala 172:49] - io.ahb.out.htrans <= _T_98 @[axi4_to_ahb.scala 172:25] + node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 171:51] + node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 171:35] + rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 171:22] + node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] + node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 172:49] + io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 172:25] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] - node _T_99 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] - when _T_99 : @[Conditional.scala 39:67] - node _T_100 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 176:54] - node _T_101 = eq(_T_100, UInt<1>("h00")) @[axi4_to_ahb.scala 176:61] - node _T_102 = and(master_valid, _T_101) @[axi4_to_ahb.scala 176:41] - node _T_103 = bits(_T_102, 0, 0) @[axi4_to_ahb.scala 176:82] - node _T_104 = mux(_T_103, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 176:26] - buf_nxtstate <= _T_104 @[axi4_to_ahb.scala 176:20] - node _T_105 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 177:51] - node _T_106 = neq(_T_105, UInt<1>("h00")) @[axi4_to_ahb.scala 177:58] - node _T_107 = and(ahb_hready_q, _T_106) @[axi4_to_ahb.scala 177:36] - node _T_108 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 177:72] - node _T_109 = and(_T_107, _T_108) @[axi4_to_ahb.scala 177:70] - buf_state_en <= _T_109 @[axi4_to_ahb.scala 177:20] - node _T_110 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 178:34] - node _T_111 = and(buf_state_en, _T_110) @[axi4_to_ahb.scala 178:32] - cmd_done <= _T_111 @[axi4_to_ahb.scala 178:16] + node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] + when _T_101 : @[Conditional.scala 39:67] + node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 176:54] + node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 176:61] + node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 176:41] + node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 176:82] + node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 176:26] + buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 176:20] + node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 177:51] + node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 177:58] + node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 177:36] + node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 177:72] + node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 177:70] + buf_state_en <= _T_111 @[axi4_to_ahb.scala 177:20] + node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 178:34] + node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 178:32] + cmd_done <= _T_113 @[axi4_to_ahb.scala 178:16] slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 179:20] - node _T_112 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 180:52] - node _T_113 = neq(_T_112, UInt<1>("h00")) @[axi4_to_ahb.scala 180:59] - node _T_114 = and(ahb_hready_q, _T_113) @[axi4_to_ahb.scala 180:37] - node _T_115 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 180:73] - node _T_116 = and(_T_114, _T_115) @[axi4_to_ahb.scala 180:71] - node _T_117 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 180:122] - node _T_118 = eq(_T_117, UInt<1>("h00")) @[axi4_to_ahb.scala 180:129] - node _T_119 = and(master_valid, _T_118) @[axi4_to_ahb.scala 180:109] - node _T_120 = bits(_T_119, 0, 0) @[axi4_to_ahb.scala 180:150] - node _T_121 = mux(_T_120, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 180:94] - node _T_122 = eq(_T_121, UInt<3>("h06")) @[axi4_to_ahb.scala 180:174] - node _T_123 = and(_T_116, _T_122) @[axi4_to_ahb.scala 180:88] - master_ready <= _T_123 @[axi4_to_ahb.scala 180:20] + node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 180:52] + node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 180:59] + node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 180:37] + node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 180:73] + node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 180:71] + node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 180:122] + node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 180:129] + node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 180:109] + node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 180:150] + node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 180:94] + node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 180:174] + node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 180:88] + master_ready <= _T_125 @[axi4_to_ahb.scala 180:20] buf_wr_en <= master_ready @[axi4_to_ahb.scala 181:17] - node _T_124 = and(master_ready, master_valid) @[axi4_to_ahb.scala 182:33] - bypass_en <= _T_124 @[axi4_to_ahb.scala 182:17] - node _T_125 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 183:47] - node _T_126 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 183:62] - node _T_127 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 183:78] - node _T_128 = mux(_T_125, _T_126, _T_127) @[axi4_to_ahb.scala 183:30] - buf_cmd_byte_ptr <= _T_128 @[axi4_to_ahb.scala 183:24] - node _T_129 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 184:48] - node _T_130 = or(_T_129, bypass_en) @[axi4_to_ahb.scala 184:62] - node _T_131 = bits(_T_130, 0, 0) @[Bitwise.scala 72:15] - node _T_132 = mux(_T_131, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_133 = and(UInt<2>("h02"), _T_132) @[axi4_to_ahb.scala 184:36] - io.ahb.out.htrans <= _T_133 @[axi4_to_ahb.scala 184:25] + node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 182:33] + bypass_en <= _T_126 @[axi4_to_ahb.scala 182:17] + node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 183:47] + node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 183:62] + node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 183:78] + node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 183:30] + buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 183:24] + node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 184:48] + node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 184:62] + node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] + node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 184:36] + io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 184:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_134 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] - when _T_134 : @[Conditional.scala 39:67] - node _T_135 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 188:39] - node _T_136 = and(ahb_hready_q, _T_135) @[axi4_to_ahb.scala 188:37] - node _T_137 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 188:82] - node _T_138 = eq(_T_137, UInt<1>("h01")) @[axi4_to_ahb.scala 188:89] - node _T_139 = and(master_valid, _T_138) @[axi4_to_ahb.scala 188:70] - node _T_140 = not(_T_139) @[axi4_to_ahb.scala 188:55] - node _T_141 = and(_T_136, _T_140) @[axi4_to_ahb.scala 188:53] - master_ready <= _T_141 @[axi4_to_ahb.scala 188:20] - node _T_142 = and(master_valid, master_ready) @[axi4_to_ahb.scala 189:34] - node _T_143 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 189:62] - node _T_144 = eq(_T_143, UInt<1>("h00")) @[axi4_to_ahb.scala 189:69] - node _T_145 = and(_T_142, _T_144) @[axi4_to_ahb.scala 189:49] - buf_wr_en <= _T_145 @[axi4_to_ahb.scala 189:17] - node _T_146 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 190:45] - node _T_147 = and(master_valid, master_ready) @[axi4_to_ahb.scala 190:82] - node _T_148 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 190:110] - node _T_149 = eq(_T_148, UInt<1>("h00")) @[axi4_to_ahb.scala 190:117] - node _T_150 = and(_T_147, _T_149) @[axi4_to_ahb.scala 190:97] - node _T_151 = bits(_T_150, 0, 0) @[axi4_to_ahb.scala 190:138] - node _T_152 = mux(_T_151, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 190:67] - node _T_153 = mux(_T_146, UInt<3>("h07"), _T_152) @[axi4_to_ahb.scala 190:26] - buf_nxtstate <= _T_153 @[axi4_to_ahb.scala 190:20] - node _T_154 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 191:37] - buf_state_en <= _T_154 @[axi4_to_ahb.scala 191:20] + node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] + when _T_136 : @[Conditional.scala 39:67] + node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 188:39] + node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 188:37] + node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 188:82] + node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 188:89] + node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 188:70] + node _T_142 = not(_T_141) @[axi4_to_ahb.scala 188:55] + node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 188:53] + master_ready <= _T_143 @[axi4_to_ahb.scala 188:20] + node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 189:34] + node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 189:62] + node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 189:69] + node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 189:49] + buf_wr_en <= _T_147 @[axi4_to_ahb.scala 189:17] + node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 190:45] + node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 190:82] + node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 190:110] + node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 190:117] + node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 190:97] + node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 190:138] + node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 190:67] + node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 190:26] + buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 190:20] + node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 191:37] + buf_state_en <= _T_156 @[axi4_to_ahb.scala 191:20] buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 192:22] slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 193:23] slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 194:23] - node _T_155 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 195:41] - node _T_156 = and(buf_state_en, _T_155) @[axi4_to_ahb.scala 195:39] - slave_valid_pre <= _T_156 @[axi4_to_ahb.scala 195:23] - node _T_157 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 196:34] - node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 196:32] - cmd_done <= _T_158 @[axi4_to_ahb.scala 196:16] - node _T_159 = and(master_ready, master_valid) @[axi4_to_ahb.scala 197:33] - node _T_160 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 197:64] - node _T_161 = and(_T_159, _T_160) @[axi4_to_ahb.scala 197:48] - node _T_162 = and(_T_161, buf_state_en) @[axi4_to_ahb.scala 197:79] - bypass_en <= _T_162 @[axi4_to_ahb.scala 197:17] - node _T_163 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 198:47] - node _T_164 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 198:62] - node _T_165 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 198:78] - node _T_166 = mux(_T_163, _T_164, _T_165) @[axi4_to_ahb.scala 198:30] - buf_cmd_byte_ptr <= _T_166 @[axi4_to_ahb.scala 198:24] - node _T_167 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 199:63] - node _T_168 = and(_T_167, buf_state_en) @[axi4_to_ahb.scala 199:78] - node _T_169 = eq(_T_168, UInt<1>("h00")) @[axi4_to_ahb.scala 199:47] - node _T_170 = bits(_T_169, 0, 0) @[Bitwise.scala 72:15] - node _T_171 = mux(_T_170, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_172 = and(UInt<2>("h02"), _T_171) @[axi4_to_ahb.scala 199:36] - io.ahb.out.htrans <= _T_172 @[axi4_to_ahb.scala 199:25] + node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 195:41] + node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 195:39] + slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 195:23] + node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 196:34] + node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 196:32] + cmd_done <= _T_160 @[axi4_to_ahb.scala 196:16] + node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 197:33] + node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 197:64] + node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 197:48] + node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 197:79] + bypass_en <= _T_164 @[axi4_to_ahb.scala 197:17] + node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 198:47] + node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 198:62] + node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 198:78] + node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 198:30] + buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 198:24] + node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 199:63] + node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 199:78] + node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 199:47] + node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] + node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 199:36] + io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 199:25] slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 200:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_173 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] - when _T_173 : @[Conditional.scala 39:67] + node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] + when _T_175 : @[Conditional.scala 39:67] buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 204:20] - node _T_174 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 205:51] - node _T_175 = neq(_T_174, UInt<1>("h00")) @[axi4_to_ahb.scala 205:58] - node _T_176 = and(ahb_hready_q, _T_175) @[axi4_to_ahb.scala 205:36] - node _T_177 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 205:72] - node _T_178 = and(_T_176, _T_177) @[axi4_to_ahb.scala 205:70] - buf_state_en <= _T_178 @[axi4_to_ahb.scala 205:20] + node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 205:51] + node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 205:58] + node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 205:36] + node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 205:72] + node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 205:70] + buf_state_en <= _T_180 @[axi4_to_ahb.scala 205:20] slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 206:23] slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 207:20] - node _T_179 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 208:35] - buf_cmd_byte_ptr <= _T_179 @[axi4_to_ahb.scala 208:24] - node _T_180 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 209:51] - node _T_181 = bits(_T_180, 0, 0) @[Bitwise.scala 72:15] - node _T_182 = mux(_T_181, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_183 = and(UInt<2>("h02"), _T_182) @[axi4_to_ahb.scala 209:41] - io.ahb.out.htrans <= _T_183 @[axi4_to_ahb.scala 209:25] + node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 208:35] + buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 208:24] + node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 209:51] + node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] + node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 209:41] + io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 209:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_184 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] - when _T_184 : @[Conditional.scala 39:67] + node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] + when _T_186 : @[Conditional.scala 39:67] buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 213:20] - node _T_185 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 214:37] - buf_state_en <= _T_185 @[axi4_to_ahb.scala 214:20] + node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 214:37] + buf_state_en <= _T_187 @[axi4_to_ahb.scala 214:20] buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 215:22] slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 216:23] slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 217:23] slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 218:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_186 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] - when _T_186 : @[Conditional.scala 39:67] + node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] + when _T_188 : @[Conditional.scala 39:67] buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 222:20] - node _T_187 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 223:33] - node _T_188 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 223:63] - node _T_189 = neq(_T_188, UInt<1>("h00")) @[axi4_to_ahb.scala 223:70] - node _T_190 = and(_T_187, _T_189) @[axi4_to_ahb.scala 223:48] - trxn_done <= _T_190 @[axi4_to_ahb.scala 223:17] + node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 223:33] + node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 223:63] + node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 223:70] + node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 223:48] + trxn_done <= _T_192 @[axi4_to_ahb.scala 223:17] buf_state_en <= trxn_done @[axi4_to_ahb.scala 224:20] buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 225:27] slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 226:20] - node _T_191 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 227:47] - node _T_192 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 227:85] - node _T_193 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 227:103] - node _T_194 = add(_T_192, UInt<1>("h01")) @[axi4_to_ahb.scala 136:52] - node _T_195 = tail(_T_194, 1) @[axi4_to_ahb.scala 136:52] - node _T_196 = mux(UInt<1>("h01"), _T_195, _T_192) @[axi4_to_ahb.scala 136:24] - node _T_197 = bits(_T_193, 0, 0) @[axi4_to_ahb.scala 137:44] - node _T_198 = geq(UInt<1>("h00"), _T_196) @[axi4_to_ahb.scala 137:62] - node _T_199 = and(_T_197, _T_198) @[axi4_to_ahb.scala 137:48] - node _T_200 = bits(_T_193, 1, 1) @[axi4_to_ahb.scala 137:44] - node _T_201 = geq(UInt<1>("h01"), _T_196) @[axi4_to_ahb.scala 137:62] - node _T_202 = and(_T_200, _T_201) @[axi4_to_ahb.scala 137:48] - node _T_203 = bits(_T_193, 2, 2) @[axi4_to_ahb.scala 137:44] - node _T_204 = geq(UInt<2>("h02"), _T_196) @[axi4_to_ahb.scala 137:62] - node _T_205 = and(_T_203, _T_204) @[axi4_to_ahb.scala 137:48] - node _T_206 = bits(_T_193, 3, 3) @[axi4_to_ahb.scala 137:44] - node _T_207 = geq(UInt<2>("h03"), _T_196) @[axi4_to_ahb.scala 137:62] - node _T_208 = and(_T_206, _T_207) @[axi4_to_ahb.scala 137:48] - node _T_209 = bits(_T_193, 4, 4) @[axi4_to_ahb.scala 137:44] - node _T_210 = geq(UInt<3>("h04"), _T_196) @[axi4_to_ahb.scala 137:62] - node _T_211 = and(_T_209, _T_210) @[axi4_to_ahb.scala 137:48] - node _T_212 = bits(_T_193, 5, 5) @[axi4_to_ahb.scala 137:44] - node _T_213 = geq(UInt<3>("h05"), _T_196) @[axi4_to_ahb.scala 137:62] - node _T_214 = and(_T_212, _T_213) @[axi4_to_ahb.scala 137:48] - node _T_215 = bits(_T_193, 6, 6) @[axi4_to_ahb.scala 137:44] - node _T_216 = geq(UInt<3>("h06"), _T_196) @[axi4_to_ahb.scala 137:62] - node _T_217 = and(_T_215, _T_216) @[axi4_to_ahb.scala 137:48] - node _T_218 = bits(_T_193, 7, 7) @[axi4_to_ahb.scala 137:44] - node _T_219 = geq(UInt<3>("h07"), _T_196) @[axi4_to_ahb.scala 137:62] - node _T_220 = and(_T_218, _T_219) @[axi4_to_ahb.scala 137:48] - node _T_221 = mux(_T_220, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_222 = mux(_T_217, UInt<3>("h06"), _T_221) @[Mux.scala 98:16] - node _T_223 = mux(_T_214, UInt<3>("h05"), _T_222) @[Mux.scala 98:16] - node _T_224 = mux(_T_211, UInt<3>("h04"), _T_223) @[Mux.scala 98:16] - node _T_225 = mux(_T_208, UInt<2>("h03"), _T_224) @[Mux.scala 98:16] - node _T_226 = mux(_T_205, UInt<2>("h02"), _T_225) @[Mux.scala 98:16] - node _T_227 = mux(_T_202, UInt<1>("h01"), _T_226) @[Mux.scala 98:16] - node _T_228 = mux(_T_199, UInt<1>("h00"), _T_227) @[Mux.scala 98:16] - node _T_229 = mux(_T_191, _T_228, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 227:30] - buf_cmd_byte_ptr <= _T_229 @[axi4_to_ahb.scala 227:24] - node _T_230 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 228:65] - node _T_231 = or(buf_aligned, _T_230) @[axi4_to_ahb.scala 228:44] - node _T_232 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 228:127] - node _T_233 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 228:145] - node _T_234 = add(_T_232, UInt<1>("h01")) @[axi4_to_ahb.scala 136:52] - node _T_235 = tail(_T_234, 1) @[axi4_to_ahb.scala 136:52] - node _T_236 = mux(UInt<1>("h01"), _T_235, _T_232) @[axi4_to_ahb.scala 136:24] - node _T_237 = bits(_T_233, 0, 0) @[axi4_to_ahb.scala 137:44] - node _T_238 = geq(UInt<1>("h00"), _T_236) @[axi4_to_ahb.scala 137:62] - node _T_239 = and(_T_237, _T_238) @[axi4_to_ahb.scala 137:48] - node _T_240 = bits(_T_233, 1, 1) @[axi4_to_ahb.scala 137:44] - node _T_241 = geq(UInt<1>("h01"), _T_236) @[axi4_to_ahb.scala 137:62] - node _T_242 = and(_T_240, _T_241) @[axi4_to_ahb.scala 137:48] - node _T_243 = bits(_T_233, 2, 2) @[axi4_to_ahb.scala 137:44] - node _T_244 = geq(UInt<2>("h02"), _T_236) @[axi4_to_ahb.scala 137:62] - node _T_245 = and(_T_243, _T_244) @[axi4_to_ahb.scala 137:48] - node _T_246 = bits(_T_233, 3, 3) @[axi4_to_ahb.scala 137:44] - node _T_247 = geq(UInt<2>("h03"), _T_236) @[axi4_to_ahb.scala 137:62] - node _T_248 = and(_T_246, _T_247) @[axi4_to_ahb.scala 137:48] - node _T_249 = bits(_T_233, 4, 4) @[axi4_to_ahb.scala 137:44] - node _T_250 = geq(UInt<3>("h04"), _T_236) @[axi4_to_ahb.scala 137:62] - node _T_251 = and(_T_249, _T_250) @[axi4_to_ahb.scala 137:48] - node _T_252 = bits(_T_233, 5, 5) @[axi4_to_ahb.scala 137:44] - node _T_253 = geq(UInt<3>("h05"), _T_236) @[axi4_to_ahb.scala 137:62] - node _T_254 = and(_T_252, _T_253) @[axi4_to_ahb.scala 137:48] - node _T_255 = bits(_T_233, 6, 6) @[axi4_to_ahb.scala 137:44] - node _T_256 = geq(UInt<3>("h06"), _T_236) @[axi4_to_ahb.scala 137:62] - node _T_257 = and(_T_255, _T_256) @[axi4_to_ahb.scala 137:48] - node _T_258 = bits(_T_233, 7, 7) @[axi4_to_ahb.scala 137:44] - node _T_259 = geq(UInt<3>("h07"), _T_236) @[axi4_to_ahb.scala 137:62] - node _T_260 = and(_T_258, _T_259) @[axi4_to_ahb.scala 137:48] - node _T_261 = mux(_T_260, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_262 = mux(_T_257, UInt<3>("h06"), _T_261) @[Mux.scala 98:16] - node _T_263 = mux(_T_254, UInt<3>("h05"), _T_262) @[Mux.scala 98:16] - node _T_264 = mux(_T_251, UInt<3>("h04"), _T_263) @[Mux.scala 98:16] - node _T_265 = mux(_T_248, UInt<2>("h03"), _T_264) @[Mux.scala 98:16] - node _T_266 = mux(_T_245, UInt<2>("h02"), _T_265) @[Mux.scala 98:16] - node _T_267 = mux(_T_242, UInt<1>("h01"), _T_266) @[Mux.scala 98:16] - node _T_268 = mux(_T_239, UInt<1>("h00"), _T_267) @[Mux.scala 98:16] - node _T_269 = dshr(buf_byteen, _T_268) @[axi4_to_ahb.scala 228:92] - node _T_270 = bits(_T_269, 0, 0) @[axi4_to_ahb.scala 228:92] - node _T_271 = eq(_T_270, UInt<1>("h00")) @[axi4_to_ahb.scala 228:163] - node _T_272 = or(_T_231, _T_271) @[axi4_to_ahb.scala 228:79] - node _T_273 = and(trxn_done, _T_272) @[axi4_to_ahb.scala 228:29] - cmd_done <= _T_273 @[axi4_to_ahb.scala 228:16] - node _T_274 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 229:47] - node _T_275 = eq(_T_274, UInt<1>("h00")) @[axi4_to_ahb.scala 229:36] - node _T_276 = bits(_T_275, 0, 0) @[Bitwise.scala 72:15] - node _T_277 = mux(_T_276, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_278 = and(_T_277, UInt<2>("h02")) @[axi4_to_ahb.scala 229:61] - io.ahb.out.htrans <= _T_278 @[axi4_to_ahb.scala 229:25] + node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 227:47] + node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 227:85] + node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 227:103] + node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 136:52] + node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 136:52] + node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 136:24] + node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 137:44] + node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 137:62] + node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 137:48] + node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 137:44] + node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 137:62] + node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 137:48] + node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 137:44] + node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 137:62] + node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 137:48] + node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 137:44] + node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 137:62] + node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 137:48] + node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 137:44] + node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 137:62] + node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 137:48] + node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 137:44] + node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 137:62] + node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 137:48] + node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 137:44] + node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 137:62] + node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 137:48] + node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 137:44] + node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 137:62] + node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 137:48] + node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] + node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] + node _T_226 = mux(_T_213, UInt<3>("h04"), _T_225) @[Mux.scala 98:16] + node _T_227 = mux(_T_210, UInt<2>("h03"), _T_226) @[Mux.scala 98:16] + node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] + node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] + node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] + node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 227:30] + buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 227:24] + node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 228:65] + node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 228:44] + node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 228:127] + node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 228:145] + node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 136:52] + node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 136:52] + node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 136:24] + node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 137:44] + node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 137:62] + node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 137:48] + node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 137:44] + node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 137:62] + node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 137:48] + node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 137:44] + node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 137:62] + node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 137:48] + node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 137:44] + node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 137:62] + node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 137:48] + node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 137:44] + node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 137:62] + node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 137:48] + node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 137:44] + node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 137:62] + node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 137:48] + node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 137:44] + node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 137:62] + node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 137:48] + node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 137:44] + node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 137:62] + node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 137:48] + node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] + node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] + node _T_266 = mux(_T_253, UInt<3>("h04"), _T_265) @[Mux.scala 98:16] + node _T_267 = mux(_T_250, UInt<2>("h03"), _T_266) @[Mux.scala 98:16] + node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] + node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] + node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] + node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 228:92] + node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 228:92] + node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 228:163] + node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 228:79] + node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 228:29] + cmd_done <= _T_275 @[axi4_to_ahb.scala 228:16] + node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 229:47] + node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 229:36] + node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] + node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 229:61] + io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 229:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_279 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] - when _T_279 : @[Conditional.scala 39:67] - node _T_280 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 233:34] - node _T_281 = or(_T_280, ahb_hresp_q) @[axi4_to_ahb.scala 233:50] - buf_state_en <= _T_281 @[axi4_to_ahb.scala 233:20] - node _T_282 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 234:38] - node _T_283 = and(buf_state_en, _T_282) @[axi4_to_ahb.scala 234:36] - node _T_284 = and(_T_283, slave_ready) @[axi4_to_ahb.scala 234:51] - master_ready <= _T_284 @[axi4_to_ahb.scala 234:20] - node _T_285 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 235:42] - node _T_286 = or(ahb_hresp_q, _T_285) @[axi4_to_ahb.scala 235:40] - node _T_287 = and(master_valid, master_valid) @[axi4_to_ahb.scala 235:81] - node _T_288 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 235:113] - node _T_289 = eq(_T_288, UInt<1>("h01")) @[axi4_to_ahb.scala 235:120] - node _T_290 = bits(_T_289, 0, 0) @[axi4_to_ahb.scala 235:135] - node _T_291 = mux(_T_290, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 235:101] - node _T_292 = mux(_T_287, _T_291, UInt<3>("h00")) @[axi4_to_ahb.scala 235:66] - node _T_293 = mux(_T_286, UInt<3>("h05"), _T_292) @[axi4_to_ahb.scala 235:26] - buf_nxtstate <= _T_293 @[axi4_to_ahb.scala 235:20] + node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] + when _T_281 : @[Conditional.scala 39:67] + node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 233:34] + node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 233:50] + buf_state_en <= _T_283 @[axi4_to_ahb.scala 233:20] + node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 234:38] + node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 234:36] + node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 234:51] + master_ready <= _T_286 @[axi4_to_ahb.scala 234:20] + node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 235:42] + node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 235:40] + node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 235:81] + node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 235:113] + node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 235:120] + node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 235:135] + node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 235:101] + node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 235:66] + node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 235:26] + buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 235:20] slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 236:23] slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 237:23] - node _T_294 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 238:33] - node _T_295 = eq(_T_294, UInt<1>("h01")) @[axi4_to_ahb.scala 238:40] - buf_write_in <= _T_295 @[axi4_to_ahb.scala 238:20] - node _T_296 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 239:50] - node _T_297 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 239:78] - node _T_298 = or(_T_296, _T_297) @[axi4_to_ahb.scala 239:62] - node _T_299 = and(buf_state_en, _T_298) @[axi4_to_ahb.scala 239:33] - buf_wr_en <= _T_299 @[axi4_to_ahb.scala 239:17] + node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 238:33] + node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 238:40] + buf_write_in <= _T_297 @[axi4_to_ahb.scala 238:20] + node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 239:50] + node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 239:78] + node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 239:62] + node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 239:33] + buf_wr_en <= _T_301 @[axi4_to_ahb.scala 239:17] buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 240:22] - node _T_300 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 241:63] - node _T_301 = neq(_T_300, UInt<1>("h00")) @[axi4_to_ahb.scala 241:70] - node _T_302 = and(ahb_hready_q, _T_301) @[axi4_to_ahb.scala 241:48] - node _T_303 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 242:29] - node _T_304 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 242:85] - node _T_305 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 242:103] - node _T_306 = add(_T_304, UInt<1>("h01")) @[axi4_to_ahb.scala 136:52] - node _T_307 = tail(_T_306, 1) @[axi4_to_ahb.scala 136:52] - node _T_308 = mux(UInt<1>("h01"), _T_307, _T_304) @[axi4_to_ahb.scala 136:24] - node _T_309 = bits(_T_305, 0, 0) @[axi4_to_ahb.scala 137:44] - node _T_310 = geq(UInt<1>("h00"), _T_308) @[axi4_to_ahb.scala 137:62] - node _T_311 = and(_T_309, _T_310) @[axi4_to_ahb.scala 137:48] - node _T_312 = bits(_T_305, 1, 1) @[axi4_to_ahb.scala 137:44] - node _T_313 = geq(UInt<1>("h01"), _T_308) @[axi4_to_ahb.scala 137:62] - node _T_314 = and(_T_312, _T_313) @[axi4_to_ahb.scala 137:48] - node _T_315 = bits(_T_305, 2, 2) @[axi4_to_ahb.scala 137:44] - node _T_316 = geq(UInt<2>("h02"), _T_308) @[axi4_to_ahb.scala 137:62] - node _T_317 = and(_T_315, _T_316) @[axi4_to_ahb.scala 137:48] - node _T_318 = bits(_T_305, 3, 3) @[axi4_to_ahb.scala 137:44] - node _T_319 = geq(UInt<2>("h03"), _T_308) @[axi4_to_ahb.scala 137:62] - node _T_320 = and(_T_318, _T_319) @[axi4_to_ahb.scala 137:48] - node _T_321 = bits(_T_305, 4, 4) @[axi4_to_ahb.scala 137:44] - node _T_322 = geq(UInt<3>("h04"), _T_308) @[axi4_to_ahb.scala 137:62] - node _T_323 = and(_T_321, _T_322) @[axi4_to_ahb.scala 137:48] - node _T_324 = bits(_T_305, 5, 5) @[axi4_to_ahb.scala 137:44] - node _T_325 = geq(UInt<3>("h05"), _T_308) @[axi4_to_ahb.scala 137:62] - node _T_326 = and(_T_324, _T_325) @[axi4_to_ahb.scala 137:48] - node _T_327 = bits(_T_305, 6, 6) @[axi4_to_ahb.scala 137:44] - node _T_328 = geq(UInt<3>("h06"), _T_308) @[axi4_to_ahb.scala 137:62] - node _T_329 = and(_T_327, _T_328) @[axi4_to_ahb.scala 137:48] - node _T_330 = bits(_T_305, 7, 7) @[axi4_to_ahb.scala 137:44] - node _T_331 = geq(UInt<3>("h07"), _T_308) @[axi4_to_ahb.scala 137:62] - node _T_332 = and(_T_330, _T_331) @[axi4_to_ahb.scala 137:48] - node _T_333 = mux(_T_332, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_334 = mux(_T_329, UInt<3>("h06"), _T_333) @[Mux.scala 98:16] - node _T_335 = mux(_T_326, UInt<3>("h05"), _T_334) @[Mux.scala 98:16] - node _T_336 = mux(_T_323, UInt<3>("h04"), _T_335) @[Mux.scala 98:16] - node _T_337 = mux(_T_320, UInt<2>("h03"), _T_336) @[Mux.scala 98:16] - node _T_338 = mux(_T_317, UInt<2>("h02"), _T_337) @[Mux.scala 98:16] - node _T_339 = mux(_T_314, UInt<1>("h01"), _T_338) @[Mux.scala 98:16] - node _T_340 = mux(_T_311, UInt<1>("h00"), _T_339) @[Mux.scala 98:16] - node _T_341 = dshr(buf_byteen, _T_340) @[axi4_to_ahb.scala 242:51] - node _T_342 = bits(_T_341, 0, 0) @[axi4_to_ahb.scala 242:51] - node _T_343 = eq(_T_342, UInt<1>("h00")) @[axi4_to_ahb.scala 242:120] - node _T_344 = or(_T_303, _T_343) @[axi4_to_ahb.scala 242:38] - node _T_345 = and(_T_302, _T_344) @[axi4_to_ahb.scala 241:79] - node _T_346 = or(ahb_hresp_q, _T_345) @[axi4_to_ahb.scala 241:32] - cmd_done <= _T_346 @[axi4_to_ahb.scala 241:16] - node _T_347 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 243:33] - node _T_348 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 243:64] - node _T_349 = and(_T_347, _T_348) @[axi4_to_ahb.scala 243:48] - bypass_en <= _T_349 @[axi4_to_ahb.scala 243:17] - node _T_350 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 244:48] - node _T_351 = eq(_T_350, UInt<1>("h00")) @[axi4_to_ahb.scala 244:37] - node _T_352 = or(_T_351, bypass_en) @[axi4_to_ahb.scala 244:61] - node _T_353 = bits(_T_352, 0, 0) @[Bitwise.scala 72:15] - node _T_354 = mux(_T_353, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_355 = and(_T_354, UInt<2>("h02")) @[axi4_to_ahb.scala 244:75] - io.ahb.out.htrans <= _T_355 @[axi4_to_ahb.scala 244:25] - node _T_356 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 245:55] - node _T_357 = and(buf_state_en, _T_356) @[axi4_to_ahb.scala 245:39] - slave_valid_pre <= _T_357 @[axi4_to_ahb.scala 245:23] - node _T_358 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 246:33] - node _T_359 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 246:63] - node _T_360 = neq(_T_359, UInt<1>("h00")) @[axi4_to_ahb.scala 246:70] - node _T_361 = and(_T_358, _T_360) @[axi4_to_ahb.scala 246:48] - trxn_done <= _T_361 @[axi4_to_ahb.scala 246:17] - node _T_362 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 247:40] - buf_cmd_byte_ptr_en <= _T_362 @[axi4_to_ahb.scala 247:27] - node _T_363 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 248:81] - node _T_364 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 136:52] - node _T_365 = tail(_T_364, 1) @[axi4_to_ahb.scala 136:52] - node _T_366 = mux(UInt<1>("h00"), _T_365, UInt<3>("h00")) @[axi4_to_ahb.scala 136:24] - node _T_367 = bits(_T_363, 0, 0) @[axi4_to_ahb.scala 137:44] - node _T_368 = geq(UInt<1>("h00"), _T_366) @[axi4_to_ahb.scala 137:62] - node _T_369 = and(_T_367, _T_368) @[axi4_to_ahb.scala 137:48] - node _T_370 = bits(_T_363, 1, 1) @[axi4_to_ahb.scala 137:44] - node _T_371 = geq(UInt<1>("h01"), _T_366) @[axi4_to_ahb.scala 137:62] - node _T_372 = and(_T_370, _T_371) @[axi4_to_ahb.scala 137:48] - node _T_373 = bits(_T_363, 2, 2) @[axi4_to_ahb.scala 137:44] - node _T_374 = geq(UInt<2>("h02"), _T_366) @[axi4_to_ahb.scala 137:62] - node _T_375 = and(_T_373, _T_374) @[axi4_to_ahb.scala 137:48] - node _T_376 = bits(_T_363, 3, 3) @[axi4_to_ahb.scala 137:44] - node _T_377 = geq(UInt<2>("h03"), _T_366) @[axi4_to_ahb.scala 137:62] - node _T_378 = and(_T_376, _T_377) @[axi4_to_ahb.scala 137:48] - node _T_379 = bits(_T_363, 4, 4) @[axi4_to_ahb.scala 137:44] - node _T_380 = geq(UInt<3>("h04"), _T_366) @[axi4_to_ahb.scala 137:62] - node _T_381 = and(_T_379, _T_380) @[axi4_to_ahb.scala 137:48] - node _T_382 = bits(_T_363, 5, 5) @[axi4_to_ahb.scala 137:44] - node _T_383 = geq(UInt<3>("h05"), _T_366) @[axi4_to_ahb.scala 137:62] - node _T_384 = and(_T_382, _T_383) @[axi4_to_ahb.scala 137:48] - node _T_385 = bits(_T_363, 6, 6) @[axi4_to_ahb.scala 137:44] - node _T_386 = geq(UInt<3>("h06"), _T_366) @[axi4_to_ahb.scala 137:62] - node _T_387 = and(_T_385, _T_386) @[axi4_to_ahb.scala 137:48] - node _T_388 = bits(_T_363, 7, 7) @[axi4_to_ahb.scala 137:44] - node _T_389 = geq(UInt<3>("h07"), _T_366) @[axi4_to_ahb.scala 137:62] - node _T_390 = and(_T_388, _T_389) @[axi4_to_ahb.scala 137:48] - node _T_391 = mux(_T_390, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_392 = mux(_T_387, UInt<3>("h06"), _T_391) @[Mux.scala 98:16] - node _T_393 = mux(_T_384, UInt<3>("h05"), _T_392) @[Mux.scala 98:16] - node _T_394 = mux(_T_381, UInt<3>("h04"), _T_393) @[Mux.scala 98:16] - node _T_395 = mux(_T_378, UInt<2>("h03"), _T_394) @[Mux.scala 98:16] - node _T_396 = mux(_T_375, UInt<2>("h02"), _T_395) @[Mux.scala 98:16] - node _T_397 = mux(_T_372, UInt<1>("h01"), _T_396) @[Mux.scala 98:16] - node _T_398 = mux(_T_369, UInt<1>("h00"), _T_397) @[Mux.scala 98:16] - node _T_399 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 248:147] - node _T_400 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 248:165] - node _T_401 = add(_T_399, UInt<1>("h01")) @[axi4_to_ahb.scala 136:52] - node _T_402 = tail(_T_401, 1) @[axi4_to_ahb.scala 136:52] - node _T_403 = mux(UInt<1>("h01"), _T_402, _T_399) @[axi4_to_ahb.scala 136:24] - node _T_404 = bits(_T_400, 0, 0) @[axi4_to_ahb.scala 137:44] - node _T_405 = geq(UInt<1>("h00"), _T_403) @[axi4_to_ahb.scala 137:62] - node _T_406 = and(_T_404, _T_405) @[axi4_to_ahb.scala 137:48] - node _T_407 = bits(_T_400, 1, 1) @[axi4_to_ahb.scala 137:44] - node _T_408 = geq(UInt<1>("h01"), _T_403) @[axi4_to_ahb.scala 137:62] - node _T_409 = and(_T_407, _T_408) @[axi4_to_ahb.scala 137:48] - node _T_410 = bits(_T_400, 2, 2) @[axi4_to_ahb.scala 137:44] - node _T_411 = geq(UInt<2>("h02"), _T_403) @[axi4_to_ahb.scala 137:62] - node _T_412 = and(_T_410, _T_411) @[axi4_to_ahb.scala 137:48] - node _T_413 = bits(_T_400, 3, 3) @[axi4_to_ahb.scala 137:44] - node _T_414 = geq(UInt<2>("h03"), _T_403) @[axi4_to_ahb.scala 137:62] - node _T_415 = and(_T_413, _T_414) @[axi4_to_ahb.scala 137:48] - node _T_416 = bits(_T_400, 4, 4) @[axi4_to_ahb.scala 137:44] - node _T_417 = geq(UInt<3>("h04"), _T_403) @[axi4_to_ahb.scala 137:62] - node _T_418 = and(_T_416, _T_417) @[axi4_to_ahb.scala 137:48] - node _T_419 = bits(_T_400, 5, 5) @[axi4_to_ahb.scala 137:44] - node _T_420 = geq(UInt<3>("h05"), _T_403) @[axi4_to_ahb.scala 137:62] - node _T_421 = and(_T_419, _T_420) @[axi4_to_ahb.scala 137:48] - node _T_422 = bits(_T_400, 6, 6) @[axi4_to_ahb.scala 137:44] - node _T_423 = geq(UInt<3>("h06"), _T_403) @[axi4_to_ahb.scala 137:62] - node _T_424 = and(_T_422, _T_423) @[axi4_to_ahb.scala 137:48] - node _T_425 = bits(_T_400, 7, 7) @[axi4_to_ahb.scala 137:44] - node _T_426 = geq(UInt<3>("h07"), _T_403) @[axi4_to_ahb.scala 137:62] - node _T_427 = and(_T_425, _T_426) @[axi4_to_ahb.scala 137:48] - node _T_428 = mux(_T_427, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_429 = mux(_T_424, UInt<3>("h06"), _T_428) @[Mux.scala 98:16] - node _T_430 = mux(_T_421, UInt<3>("h05"), _T_429) @[Mux.scala 98:16] - node _T_431 = mux(_T_418, UInt<3>("h04"), _T_430) @[Mux.scala 98:16] - node _T_432 = mux(_T_415, UInt<2>("h03"), _T_431) @[Mux.scala 98:16] - node _T_433 = mux(_T_412, UInt<2>("h02"), _T_432) @[Mux.scala 98:16] - node _T_434 = mux(_T_409, UInt<1>("h01"), _T_433) @[Mux.scala 98:16] - node _T_435 = mux(_T_406, UInt<1>("h00"), _T_434) @[Mux.scala 98:16] - node _T_436 = mux(trxn_done, _T_435, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 248:102] - node _T_437 = mux(bypass_en, _T_398, _T_436) @[axi4_to_ahb.scala 248:30] - buf_cmd_byte_ptr <= _T_437 @[axi4_to_ahb.scala 248:24] + node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 241:63] + node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 241:70] + node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 241:48] + node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 242:29] + node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 242:85] + node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 242:103] + node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 136:52] + node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 136:52] + node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 136:24] + node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 137:44] + node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 137:62] + node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 137:48] + node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 137:44] + node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 137:62] + node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 137:48] + node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 137:44] + node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 137:62] + node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 137:48] + node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 137:44] + node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 137:62] + node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 137:48] + node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 137:44] + node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 137:62] + node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 137:48] + node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 137:44] + node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 137:62] + node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 137:48] + node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 137:44] + node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 137:62] + node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 137:48] + node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 137:44] + node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 137:62] + node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 137:48] + node _T_335 = mux(_T_334, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_336 = mux(_T_331, UInt<3>("h06"), _T_335) @[Mux.scala 98:16] + node _T_337 = mux(_T_328, UInt<3>("h05"), _T_336) @[Mux.scala 98:16] + node _T_338 = mux(_T_325, UInt<3>("h04"), _T_337) @[Mux.scala 98:16] + node _T_339 = mux(_T_322, UInt<2>("h03"), _T_338) @[Mux.scala 98:16] + node _T_340 = mux(_T_319, UInt<2>("h02"), _T_339) @[Mux.scala 98:16] + node _T_341 = mux(_T_316, UInt<1>("h01"), _T_340) @[Mux.scala 98:16] + node _T_342 = mux(_T_313, UInt<1>("h00"), _T_341) @[Mux.scala 98:16] + node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 242:51] + node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 242:51] + node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 242:120] + node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 242:38] + node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 241:79] + node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 241:32] + cmd_done <= _T_348 @[axi4_to_ahb.scala 241:16] + node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 243:33] + node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 243:64] + node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 243:48] + bypass_en <= _T_351 @[axi4_to_ahb.scala 243:17] + node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 244:48] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 244:37] + node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 244:61] + node _T_355 = bits(_T_354, 0, 0) @[Bitwise.scala 72:15] + node _T_356 = mux(_T_355, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 244:75] + io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 244:25] + node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 245:55] + node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 245:39] + slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 245:23] + node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 246:33] + node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 246:63] + node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 246:70] + node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 246:48] + trxn_done <= _T_363 @[axi4_to_ahb.scala 246:17] + node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 247:40] + buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 247:27] + node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 248:81] + node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 136:52] + node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 136:52] + node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 136:24] + node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 137:44] + node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 137:62] + node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 137:48] + node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 137:44] + node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 137:62] + node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 137:48] + node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 137:44] + node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 137:62] + node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 137:48] + node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 137:44] + node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 137:62] + node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 137:48] + node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 137:44] + node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 137:62] + node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 137:48] + node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 137:44] + node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 137:62] + node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 137:48] + node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 137:44] + node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 137:62] + node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 137:48] + node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 137:44] + node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 137:62] + node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 137:48] + node _T_393 = mux(_T_392, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_394 = mux(_T_389, UInt<3>("h06"), _T_393) @[Mux.scala 98:16] + node _T_395 = mux(_T_386, UInt<3>("h05"), _T_394) @[Mux.scala 98:16] + node _T_396 = mux(_T_383, UInt<3>("h04"), _T_395) @[Mux.scala 98:16] + node _T_397 = mux(_T_380, UInt<2>("h03"), _T_396) @[Mux.scala 98:16] + node _T_398 = mux(_T_377, UInt<2>("h02"), _T_397) @[Mux.scala 98:16] + node _T_399 = mux(_T_374, UInt<1>("h01"), _T_398) @[Mux.scala 98:16] + node _T_400 = mux(_T_371, UInt<1>("h00"), _T_399) @[Mux.scala 98:16] + node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 248:147] + node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 248:165] + node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 136:52] + node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 136:52] + node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 136:24] + node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 137:44] + node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 137:62] + node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 137:48] + node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 137:44] + node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 137:62] + node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 137:48] + node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 137:44] + node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 137:62] + node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 137:48] + node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 137:44] + node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 137:62] + node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 137:48] + node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 137:44] + node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 137:62] + node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 137:48] + node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 137:44] + node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 137:62] + node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 137:48] + node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 137:44] + node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 137:62] + node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 137:48] + node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 137:44] + node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 137:62] + node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 137:48] + node _T_430 = mux(_T_429, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_431 = mux(_T_426, UInt<3>("h06"), _T_430) @[Mux.scala 98:16] + node _T_432 = mux(_T_423, UInt<3>("h05"), _T_431) @[Mux.scala 98:16] + node _T_433 = mux(_T_420, UInt<3>("h04"), _T_432) @[Mux.scala 98:16] + node _T_434 = mux(_T_417, UInt<2>("h03"), _T_433) @[Mux.scala 98:16] + node _T_435 = mux(_T_414, UInt<2>("h02"), _T_434) @[Mux.scala 98:16] + node _T_436 = mux(_T_411, UInt<1>("h01"), _T_435) @[Mux.scala 98:16] + node _T_437 = mux(_T_408, UInt<1>("h00"), _T_436) @[Mux.scala 98:16] + node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 248:102] + node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 248:30] + buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 248:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_438 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] - when _T_438 : @[Conditional.scala 39:67] + node _T_440 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] + when _T_440 : @[Conditional.scala 39:67] buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 251:20] buf_state_en <= slave_ready @[axi4_to_ahb.scala 252:20] slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 253:23] slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 254:23] skip @[Conditional.scala 39:67] cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 258:16] - node _T_439 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 259:33] - node _T_440 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 259:75] - node _T_441 = eq(_T_440, UInt<1>("h01")) @[axi4_to_ahb.scala 259:82] - node _T_442 = and(buf_aligned_in, _T_441) @[axi4_to_ahb.scala 259:62] - node _T_443 = bits(_T_442, 0, 0) @[axi4_to_ahb.scala 259:102] - node _T_444 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 259:134] - node _T_445 = bits(_T_444, 7, 0) @[axi4_to_ahb.scala 127:50] - node _T_446 = eq(_T_445, UInt<8>("h0ff")) @[axi4_to_ahb.scala 127:57] - node _T_447 = bits(_T_444, 7, 0) @[axi4_to_ahb.scala 127:81] - node _T_448 = eq(_T_447, UInt<8>("h0f")) @[axi4_to_ahb.scala 127:88] - node _T_449 = or(_T_446, _T_448) @[axi4_to_ahb.scala 127:70] - node _T_450 = bits(_T_444, 7, 0) @[axi4_to_ahb.scala 127:117] - node _T_451 = eq(_T_450, UInt<8>("h03")) @[axi4_to_ahb.scala 127:124] - node _T_452 = or(_T_449, _T_451) @[axi4_to_ahb.scala 127:106] - node _T_453 = bits(_T_452, 0, 0) @[Bitwise.scala 72:15] - node _T_454 = mux(_T_453, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_455 = and(UInt<3>("h00"), _T_454) @[axi4_to_ahb.scala 127:29] - node _T_456 = bits(_T_444, 7, 0) @[axi4_to_ahb.scala 128:35] - node _T_457 = eq(_T_456, UInt<8>("h0c")) @[axi4_to_ahb.scala 128:42] - node _T_458 = bits(_T_457, 0, 0) @[Bitwise.scala 72:15] - node _T_459 = mux(_T_458, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_460 = and(UInt<2>("h02"), _T_459) @[axi4_to_ahb.scala 128:15] - node _T_461 = or(_T_455, _T_460) @[axi4_to_ahb.scala 127:146] - node _T_462 = bits(_T_444, 7, 0) @[axi4_to_ahb.scala 129:36] - node _T_463 = eq(_T_462, UInt<8>("h0f0")) @[axi4_to_ahb.scala 129:43] - node _T_464 = bits(_T_444, 7, 0) @[axi4_to_ahb.scala 129:67] - node _T_465 = eq(_T_464, UInt<8>("h03")) @[axi4_to_ahb.scala 129:74] - node _T_466 = or(_T_463, _T_465) @[axi4_to_ahb.scala 129:56] - node _T_467 = bits(_T_466, 0, 0) @[Bitwise.scala 72:15] - node _T_468 = mux(_T_467, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_469 = and(UInt<3>("h04"), _T_468) @[axi4_to_ahb.scala 129:15] - node _T_470 = or(_T_461, _T_469) @[axi4_to_ahb.scala 128:63] - node _T_471 = bits(_T_444, 7, 0) @[axi4_to_ahb.scala 130:35] - node _T_472 = eq(_T_471, UInt<8>("h0c0")) @[axi4_to_ahb.scala 130:42] - node _T_473 = bits(_T_472, 0, 0) @[Bitwise.scala 72:15] - node _T_474 = mux(_T_473, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_475 = and(UInt<3>("h06"), _T_474) @[axi4_to_ahb.scala 130:15] - node _T_476 = or(_T_470, _T_475) @[axi4_to_ahb.scala 129:96] - node _T_477 = bits(_T_444, 7, 0) @[axi4_to_ahb.scala 131:33] - node _T_478 = eq(_T_477, UInt<8>("h0c0")) @[axi4_to_ahb.scala 131:40] - node _T_479 = bits(_T_478, 0, 0) @[Bitwise.scala 72:15] - node _T_480 = mux(_T_479, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_481 = and(UInt<3>("h06"), _T_480) @[axi4_to_ahb.scala 131:13] - node _T_482 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 259:154] - node _T_483 = mux(_T_443, _T_476, _T_482) @[axi4_to_ahb.scala 259:45] - node _T_484 = cat(_T_439, _T_483) @[Cat.scala 29:58] - buf_addr_in <= _T_484 @[axi4_to_ahb.scala 259:15] - node _T_485 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 260:27] - buf_tag_in <= _T_485 @[axi4_to_ahb.scala 260:14] - node _T_486 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 261:32] - buf_byteen_in <= _T_486 @[axi4_to_ahb.scala 261:17] - node _T_487 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 262:33] - node _T_488 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 262:59] - node _T_489 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 262:80] - node _T_490 = mux(_T_487, _T_488, _T_489) @[axi4_to_ahb.scala 262:21] - buf_data_in <= _T_490 @[axi4_to_ahb.scala 262:15] - node _T_491 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 263:52] - node _T_492 = eq(_T_491, UInt<2>("h03")) @[axi4_to_ahb.scala 263:59] - node _T_493 = and(buf_aligned_in, _T_492) @[axi4_to_ahb.scala 263:38] - node _T_494 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 263:85] - node _T_495 = eq(_T_494, UInt<1>("h01")) @[axi4_to_ahb.scala 263:92] - node _T_496 = and(_T_493, _T_495) @[axi4_to_ahb.scala 263:72] - node _T_497 = bits(_T_496, 0, 0) @[axi4_to_ahb.scala 263:112] - node _T_498 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 263:144] - node _T_499 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 120:42] - node _T_500 = eq(_T_499, UInt<8>("h0ff")) @[axi4_to_ahb.scala 120:49] - node _T_501 = bits(_T_500, 0, 0) @[Bitwise.scala 72:15] - node _T_502 = mux(_T_501, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_503 = and(UInt<2>("h03"), _T_502) @[axi4_to_ahb.scala 120:25] - node _T_504 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 121:35] - node _T_505 = eq(_T_504, UInt<8>("h0f0")) @[axi4_to_ahb.scala 121:42] - node _T_506 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 121:64] - node _T_507 = eq(_T_506, UInt<8>("h0f")) @[axi4_to_ahb.scala 121:71] - node _T_508 = or(_T_505, _T_507) @[axi4_to_ahb.scala 121:55] - node _T_509 = bits(_T_508, 0, 0) @[Bitwise.scala 72:15] - node _T_510 = mux(_T_509, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_511 = and(UInt<2>("h02"), _T_510) @[axi4_to_ahb.scala 121:16] - node _T_512 = or(_T_503, _T_511) @[axi4_to_ahb.scala 120:64] - node _T_513 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 122:40] - node _T_514 = eq(_T_513, UInt<8>("h0c0")) @[axi4_to_ahb.scala 122:47] - node _T_515 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 122:69] - node _T_516 = eq(_T_515, UInt<6>("h030")) @[axi4_to_ahb.scala 122:76] - node _T_517 = or(_T_514, _T_516) @[axi4_to_ahb.scala 122:60] - node _T_518 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 122:98] - node _T_519 = eq(_T_518, UInt<8>("h0c")) @[axi4_to_ahb.scala 122:105] - node _T_520 = or(_T_517, _T_519) @[axi4_to_ahb.scala 122:89] - node _T_521 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 122:132] - node _T_522 = eq(_T_521, UInt<8>("h03")) @[axi4_to_ahb.scala 122:139] - node _T_523 = or(_T_520, _T_522) @[axi4_to_ahb.scala 122:123] - node _T_524 = bits(_T_523, 0, 0) @[Bitwise.scala 72:15] - node _T_525 = mux(_T_524, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_526 = and(UInt<2>("h01"), _T_525) @[axi4_to_ahb.scala 122:21] - node _T_527 = or(_T_512, _T_526) @[axi4_to_ahb.scala 121:93] - node _T_528 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 263:164] - node _T_529 = mux(_T_497, _T_527, _T_528) @[axi4_to_ahb.scala 263:21] - buf_size_in <= _T_529 @[axi4_to_ahb.scala 263:15] - node _T_530 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 264:32] - node _T_531 = eq(_T_530, UInt<1>("h00")) @[axi4_to_ahb.scala 264:39] - node _T_532 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 265:17] - node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 265:24] - node _T_534 = or(_T_531, _T_533) @[axi4_to_ahb.scala 264:48] - node _T_535 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 265:47] - node _T_536 = eq(_T_535, UInt<2>("h01")) @[axi4_to_ahb.scala 265:54] - node _T_537 = or(_T_534, _T_536) @[axi4_to_ahb.scala 265:33] - node _T_538 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 265:86] - node _T_539 = eq(_T_538, UInt<2>("h02")) @[axi4_to_ahb.scala 265:93] - node _T_540 = or(_T_537, _T_539) @[axi4_to_ahb.scala 265:72] - node _T_541 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 266:18] - node _T_542 = eq(_T_541, UInt<2>("h03")) @[axi4_to_ahb.scala 266:25] - node _T_543 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 266:55] - node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 266:62] - node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 266:90] - node _T_546 = eq(_T_545, UInt<4>("h0c")) @[axi4_to_ahb.scala 266:97] - node _T_547 = or(_T_544, _T_546) @[axi4_to_ahb.scala 266:74] - node _T_548 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 266:125] - node _T_549 = eq(_T_548, UInt<6>("h030")) @[axi4_to_ahb.scala 266:132] - node _T_550 = or(_T_547, _T_549) @[axi4_to_ahb.scala 266:109] - node _T_551 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 266:161] - node _T_552 = eq(_T_551, UInt<8>("h0c0")) @[axi4_to_ahb.scala 266:168] - node _T_553 = or(_T_550, _T_552) @[axi4_to_ahb.scala 266:145] - node _T_554 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 267:21] - node _T_555 = eq(_T_554, UInt<4>("h0f")) @[axi4_to_ahb.scala 267:28] - node _T_556 = or(_T_553, _T_555) @[axi4_to_ahb.scala 266:181] - node _T_557 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 267:56] - node _T_558 = eq(_T_557, UInt<8>("h0f0")) @[axi4_to_ahb.scala 267:63] - node _T_559 = or(_T_556, _T_558) @[axi4_to_ahb.scala 267:40] - node _T_560 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 267:92] - node _T_561 = eq(_T_560, UInt<8>("h0ff")) @[axi4_to_ahb.scala 267:99] - node _T_562 = or(_T_559, _T_561) @[axi4_to_ahb.scala 267:76] - node _T_563 = and(_T_542, _T_562) @[axi4_to_ahb.scala 266:38] - node _T_564 = or(_T_540, _T_563) @[axi4_to_ahb.scala 265:106] - buf_aligned_in <= _T_564 @[axi4_to_ahb.scala 264:18] - node _T_565 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 269:47] - node _T_566 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 269:62] - node _T_567 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 269:79] - node _T_568 = mux(_T_565, _T_566, _T_567) @[axi4_to_ahb.scala 269:30] - node _T_569 = eq(io.ahb.out.htrans, UInt<2>("h02")) @[axi4_to_ahb.scala 269:115] - node _T_570 = bits(_T_569, 0, 0) @[Bitwise.scala 72:15] - node _T_571 = mux(_T_570, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_572 = and(_T_571, buf_cmd_byte_ptr) @[axi4_to_ahb.scala 269:124] - node _T_573 = cat(_T_568, _T_572) @[Cat.scala 29:58] - io.ahb.out.haddr <= _T_573 @[axi4_to_ahb.scala 269:20] - node _T_574 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 270:43] - node _T_575 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] - node _T_576 = mux(_T_575, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_577 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 270:94] - node _T_578 = and(_T_576, _T_577) @[axi4_to_ahb.scala 270:81] - node _T_579 = cat(UInt<1>("h00"), _T_578) @[Cat.scala 29:58] - node _T_580 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] - node _T_581 = mux(_T_580, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_582 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 270:148] - node _T_583 = and(_T_581, _T_582) @[axi4_to_ahb.scala 270:138] - node _T_584 = cat(UInt<1>("h00"), _T_583) @[Cat.scala 29:58] - node _T_585 = mux(_T_574, _T_579, _T_584) @[axi4_to_ahb.scala 270:26] - io.ahb.out.hsize <= _T_585 @[axi4_to_ahb.scala 270:20] + node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 259:33] + node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 259:75] + node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 259:82] + node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 259:62] + node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 259:102] + node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 259:134] + node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:50] + node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 127:57] + node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:81] + node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 127:88] + node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 127:70] + node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 127:117] + node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 127:124] + node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 127:106] + node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] + node _T_456 = mux(_T_455, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 127:29] + node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 128:35] + node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 128:42] + node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] + node _T_461 = mux(_T_460, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 128:15] + node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 127:146] + node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:36] + node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 129:43] + node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 129:67] + node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 129:74] + node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 129:56] + node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] + node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 129:15] + node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 128:63] + node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 130:35] + node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 130:42] + node _T_475 = bits(_T_474, 0, 0) @[Bitwise.scala 72:15] + node _T_476 = mux(_T_475, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 130:15] + node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 129:96] + node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 131:33] + node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 131:40] + node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] + node _T_482 = mux(_T_481, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 131:13] + node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 259:154] + node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 259:45] + node _T_486 = cat(_T_441, _T_485) @[Cat.scala 29:58] + buf_addr_in <= _T_486 @[axi4_to_ahb.scala 259:15] + node _T_487 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 260:27] + buf_tag_in <= _T_487 @[axi4_to_ahb.scala 260:14] + node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 261:32] + buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 261:17] + node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 262:33] + node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 262:59] + node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 262:80] + node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 262:21] + buf_data_in <= _T_492 @[axi4_to_ahb.scala 262:15] + node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 263:52] + node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 263:59] + node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 263:38] + node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 263:85] + node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 263:92] + node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 263:72] + node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 263:112] + node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 263:144] + node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 120:42] + node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 120:49] + node _T_503 = bits(_T_502, 0, 0) @[Bitwise.scala 72:15] + node _T_504 = mux(_T_503, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 120:25] + node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 121:35] + node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 121:42] + node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 121:64] + node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 121:71] + node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 121:55] + node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] + node _T_512 = mux(_T_511, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 121:16] + node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 120:64] + node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:40] + node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 122:47] + node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:69] + node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 122:76] + node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 122:60] + node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:98] + node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 122:105] + node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 122:89] + node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 122:132] + node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 122:139] + node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 122:123] + node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] + node _T_527 = mux(_T_526, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 122:21] + node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 121:93] + node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 263:164] + node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 263:21] + buf_size_in <= _T_531 @[axi4_to_ahb.scala 263:15] + node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 264:32] + node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 264:39] + node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 265:17] + node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 265:24] + node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 264:48] + node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 265:47] + node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 265:54] + node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 265:33] + node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 265:86] + node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 265:93] + node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 265:72] + node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 266:18] + node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 266:25] + node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 266:55] + node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 266:62] + node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 266:90] + node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 266:97] + node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 266:74] + node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 266:125] + node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 266:132] + node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 266:109] + node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 266:161] + node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 266:168] + node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 266:145] + node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 267:21] + node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 267:28] + node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 266:181] + node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 267:56] + node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 267:63] + node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 267:40] + node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 267:92] + node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 267:99] + node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 267:76] + node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 266:38] + node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 265:106] + buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 264:18] + node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 269:47] + node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 269:62] + node _T_569 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 269:79] + node _T_570 = mux(_T_567, _T_568, _T_569) @[axi4_to_ahb.scala 269:30] + node _T_571 = eq(io.ahb.out.htrans, UInt<2>("h02")) @[axi4_to_ahb.scala 269:115] + node _T_572 = bits(_T_571, 0, 0) @[Bitwise.scala 72:15] + node _T_573 = mux(_T_572, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_574 = and(_T_573, buf_cmd_byte_ptr) @[axi4_to_ahb.scala 269:124] + node _T_575 = cat(_T_570, _T_574) @[Cat.scala 29:58] + io.ahb.out.haddr <= _T_575 @[axi4_to_ahb.scala 269:20] + node _T_576 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 270:43] + node _T_577 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] + node _T_578 = mux(_T_577, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_579 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 270:94] + node _T_580 = and(_T_578, _T_579) @[axi4_to_ahb.scala 270:81] + node _T_581 = cat(UInt<1>("h00"), _T_580) @[Cat.scala 29:58] + node _T_582 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] + node _T_583 = mux(_T_582, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_584 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 270:148] + node _T_585 = and(_T_583, _T_584) @[axi4_to_ahb.scala 270:138] + node _T_586 = cat(UInt<1>("h00"), _T_585) @[Cat.scala 29:58] + node _T_587 = mux(_T_576, _T_581, _T_586) @[axi4_to_ahb.scala 270:26] + io.ahb.out.hsize <= _T_587 @[axi4_to_ahb.scala 270:20] io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 272:21] io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 273:24] - node _T_586 = bits(io.axi.ar.bits.prot, 2, 2) @[axi4_to_ahb.scala 274:57] - node _T_587 = eq(_T_586, UInt<1>("h00")) @[axi4_to_ahb.scala 274:37] - node _T_588 = cat(UInt<1>("h01"), _T_587) @[Cat.scala 29:58] - io.ahb.out.hprot <= _T_588 @[axi4_to_ahb.scala 274:20] - node _T_589 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 275:44] - node _T_590 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 275:59] - node _T_591 = eq(_T_590, UInt<1>("h01")) @[axi4_to_ahb.scala 275:66] - node _T_592 = mux(_T_589, _T_591, buf_write) @[axi4_to_ahb.scala 275:27] - io.ahb.out.hwrite <= _T_592 @[axi4_to_ahb.scala 275:21] - node _T_593 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 276:32] - io.ahb.out.hwdata <= _T_593 @[axi4_to_ahb.scala 276:21] + node _T_588 = bits(io.axi.ar.bits.prot, 2, 2) @[axi4_to_ahb.scala 274:57] + node _T_589 = eq(_T_588, UInt<1>("h00")) @[axi4_to_ahb.scala 274:37] + node _T_590 = cat(UInt<1>("h01"), _T_589) @[Cat.scala 29:58] + io.ahb.out.hprot <= _T_590 @[axi4_to_ahb.scala 274:20] + node _T_591 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 275:44] + node _T_592 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 275:59] + node _T_593 = eq(_T_592, UInt<1>("h01")) @[axi4_to_ahb.scala 275:66] + node _T_594 = mux(_T_591, _T_593, buf_write) @[axi4_to_ahb.scala 275:27] + io.ahb.out.hwrite <= _T_594 @[axi4_to_ahb.scala 275:21] + node _T_595 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 276:32] + io.ahb.out.hwdata <= _T_595 @[axi4_to_ahb.scala 276:21] slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 278:15] - node _T_594 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 279:43] - node _T_595 = mux(_T_594, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 279:23] - node _T_596 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] - node _T_597 = mux(_T_596, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_598 = and(_T_597, UInt<2>("h02")) @[axi4_to_ahb.scala 279:88] - node _T_599 = cat(_T_595, _T_598) @[Cat.scala 29:58] - slave_opc <= _T_599 @[axi4_to_ahb.scala 279:13] - node _T_600 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 280:41] - node _T_601 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 280:66] - node _T_602 = cat(_T_601, _T_601) @[Cat.scala 29:58] - node _T_603 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 280:91] - node _T_604 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 280:110] - node _T_605 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 280:131] - node _T_606 = mux(_T_603, _T_604, _T_605) @[axi4_to_ahb.scala 280:79] - node _T_607 = mux(_T_600, _T_602, _T_606) @[axi4_to_ahb.scala 280:21] - slave_rdata <= _T_607 @[axi4_to_ahb.scala 280:15] - node _T_608 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 281:26] - slave_tag <= _T_608 @[axi4_to_ahb.scala 281:13] - node _T_609 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 283:37] - node _T_610 = neq(_T_609, UInt<1>("h00")) @[axi4_to_ahb.scala 283:44] - node _T_611 = and(_T_610, io.ahb.in.hready) @[axi4_to_ahb.scala 283:56] - node _T_612 = and(_T_611, io.ahb.out.hwrite) @[axi4_to_ahb.scala 283:75] - last_addr_en <= _T_612 @[axi4_to_ahb.scala 283:16] - node _T_613 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 285:31] - node _T_614 = and(_T_613, master_ready) @[axi4_to_ahb.scala 285:49] - wrbuf_en <= _T_614 @[axi4_to_ahb.scala 285:12] - node _T_615 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 286:35] - node _T_616 = and(_T_615, master_ready) @[axi4_to_ahb.scala 286:52] - wrbuf_data_en <= _T_616 @[axi4_to_ahb.scala 286:17] - node _T_617 = and(master_valid, master_ready) @[axi4_to_ahb.scala 287:34] - node _T_618 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 287:62] - node _T_619 = eq(_T_618, UInt<1>("h01")) @[axi4_to_ahb.scala 287:69] - node _T_620 = and(_T_617, _T_619) @[axi4_to_ahb.scala 287:49] - wrbuf_cmd_sent <= _T_620 @[axi4_to_ahb.scala 287:18] - node _T_621 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 288:34] - node _T_622 = and(wrbuf_cmd_sent, _T_621) @[axi4_to_ahb.scala 288:32] - node _T_623 = or(_T_622, dec_tlu_force_halt_bus) @[axi4_to_ahb.scala 288:45] - wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 288:13] - node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 290:36] - node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 290:34] - node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 290:22] - node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 290:53] - io.axi.aw.ready <= _T_627 @[axi4_to_ahb.scala 290:19] - node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 291:40] - node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 291:38] - node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 291:21] - node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 291:57] - io.axi.w.ready <= _T_631 @[axi4_to_ahb.scala 291:18] - node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 292:34] - node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 292:22] - node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 292:52] - io.axi.ar.ready <= _T_634 @[axi4_to_ahb.scala 292:19] + node _T_596 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 279:43] + node _T_597 = mux(_T_596, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 279:23] + node _T_598 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] + node _T_599 = mux(_T_598, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_600 = and(_T_599, UInt<2>("h02")) @[axi4_to_ahb.scala 279:88] + node _T_601 = cat(_T_597, _T_600) @[Cat.scala 29:58] + slave_opc <= _T_601 @[axi4_to_ahb.scala 279:13] + node _T_602 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 280:41] + node _T_603 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 280:66] + node _T_604 = cat(_T_603, _T_603) @[Cat.scala 29:58] + node _T_605 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 280:91] + node _T_606 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 280:110] + node _T_607 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 280:131] + node _T_608 = mux(_T_605, _T_606, _T_607) @[axi4_to_ahb.scala 280:79] + node _T_609 = mux(_T_602, _T_604, _T_608) @[axi4_to_ahb.scala 280:21] + slave_rdata <= _T_609 @[axi4_to_ahb.scala 280:15] + node _T_610 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 281:26] + slave_tag <= _T_610 @[axi4_to_ahb.scala 281:13] + node _T_611 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 283:37] + node _T_612 = neq(_T_611, UInt<1>("h00")) @[axi4_to_ahb.scala 283:44] + node _T_613 = and(_T_612, io.ahb.in.hready) @[axi4_to_ahb.scala 283:56] + node _T_614 = and(_T_613, io.ahb.out.hwrite) @[axi4_to_ahb.scala 283:75] + last_addr_en <= _T_614 @[axi4_to_ahb.scala 283:16] + node _T_615 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 285:31] + node _T_616 = and(_T_615, master_ready) @[axi4_to_ahb.scala 285:49] + wrbuf_en <= _T_616 @[axi4_to_ahb.scala 285:12] + node _T_617 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 286:35] + node _T_618 = and(_T_617, master_ready) @[axi4_to_ahb.scala 286:52] + wrbuf_data_en <= _T_618 @[axi4_to_ahb.scala 286:17] + node _T_619 = and(master_valid, master_ready) @[axi4_to_ahb.scala 287:34] + node _T_620 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 287:62] + node _T_621 = eq(_T_620, UInt<1>("h01")) @[axi4_to_ahb.scala 287:69] + node _T_622 = and(_T_619, _T_621) @[axi4_to_ahb.scala 287:49] + wrbuf_cmd_sent <= _T_622 @[axi4_to_ahb.scala 287:18] + node _T_623 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 288:34] + node _T_624 = and(wrbuf_cmd_sent, _T_623) @[axi4_to_ahb.scala 288:32] + node _T_625 = or(_T_624, dec_tlu_force_halt_bus) @[axi4_to_ahb.scala 288:45] + wrbuf_rst <= _T_625 @[axi4_to_ahb.scala 288:13] + node _T_626 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 290:36] + node _T_627 = and(wrbuf_vld, _T_626) @[axi4_to_ahb.scala 290:34] + node _T_628 = eq(_T_627, UInt<1>("h00")) @[axi4_to_ahb.scala 290:22] + node _T_629 = and(_T_628, master_ready) @[axi4_to_ahb.scala 290:53] + io.axi.aw.ready <= _T_629 @[axi4_to_ahb.scala 290:19] + node _T_630 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 291:40] + node _T_631 = and(wrbuf_data_vld, _T_630) @[axi4_to_ahb.scala 291:38] + node _T_632 = eq(_T_631, UInt<1>("h00")) @[axi4_to_ahb.scala 291:21] + node _T_633 = and(_T_632, master_ready) @[axi4_to_ahb.scala 291:57] + io.axi.w.ready <= _T_633 @[axi4_to_ahb.scala 291:18] + node _T_634 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 292:34] + node _T_635 = eq(_T_634, UInt<1>("h00")) @[axi4_to_ahb.scala 292:22] + node _T_636 = and(_T_635, master_ready) @[axi4_to_ahb.scala 292:52] + io.axi.ar.ready <= _T_636 @[axi4_to_ahb.scala 292:19] io.axi.r.bits.last <= UInt<1>("h01") @[axi4_to_ahb.scala 293:22] - node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 295:49] - wire _T_636 : UInt @[lib.scala 389:21] - node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[lib.scala 391:75] - node _T_638 = and(UInt<1>("h01"), _T_637) @[lib.scala 391:53] - node _T_639 = or(_T_635, wrbuf_rst) @[lib.scala 391:95] - node _T_640 = and(_T_639, io.bus_clk_en) @[lib.scala 391:102] - node _T_641 = bits(_T_640, 0, 0) @[lib.scala 8:44] - reg _T_642 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_641 : @[Reg.scala 28:19] - _T_642 <= _T_638 @[Reg.scala 28:23] + node _T_637 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 295:49] + wire _T_638 : UInt @[lib.scala 389:21] + node _T_639 = eq(wrbuf_rst, UInt<1>("h00")) @[lib.scala 391:73] + node _T_640 = and(UInt<1>("h01"), _T_639) @[lib.scala 391:53] + node _T_641 = or(_T_637, wrbuf_rst) @[lib.scala 391:92] + node _T_642 = and(_T_641, io.bus_clk_en) @[lib.scala 391:99] + node _T_643 = bits(_T_642, 0, 0) @[lib.scala 8:44] + reg _T_644 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_643 : @[Reg.scala 28:19] + _T_644 <= _T_640 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - _T_636 <= _T_642 @[lib.scala 391:14] - wrbuf_vld <= _T_636 @[axi4_to_ahb.scala 295:13] - node _T_643 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 296:59] - wire _T_644 : UInt @[lib.scala 389:21] - node _T_645 = eq(wrbuf_rst, UInt<1>("h00")) @[lib.scala 391:75] - node _T_646 = and(UInt<1>("h01"), _T_645) @[lib.scala 391:53] - node _T_647 = or(_T_643, wrbuf_rst) @[lib.scala 391:95] - node _T_648 = and(_T_647, io.bus_clk_en) @[lib.scala 391:102] - node _T_649 = bits(_T_648, 0, 0) @[lib.scala 8:44] - reg _T_650 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_649 : @[Reg.scala 28:19] - _T_650 <= _T_646 @[Reg.scala 28:23] + _T_638 <= _T_644 @[lib.scala 391:14] + wrbuf_vld <= _T_638 @[axi4_to_ahb.scala 295:13] + node _T_645 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 296:59] + wire _T_646 : UInt @[lib.scala 389:21] + node _T_647 = eq(wrbuf_rst, UInt<1>("h00")) @[lib.scala 391:73] + node _T_648 = and(UInt<1>("h01"), _T_647) @[lib.scala 391:53] + node _T_649 = or(_T_645, wrbuf_rst) @[lib.scala 391:92] + node _T_650 = and(_T_649, io.bus_clk_en) @[lib.scala 391:99] + node _T_651 = bits(_T_650, 0, 0) @[lib.scala 8:44] + reg _T_652 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_651 : @[Reg.scala 28:19] + _T_652 <= _T_648 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - _T_644 <= _T_650 @[lib.scala 391:14] - wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 296:18] - node _T_651 = bits(io.axi.aw.bits.id, 0, 0) @[axi4_to_ahb.scala 297:45] - node _T_652 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 297:74] - node _T_653 = and(io.bus_clk_en, _T_652) @[lib.scala 383:57] - reg _T_654 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_653 : @[Reg.scala 28:19] - _T_654 <= _T_651 @[Reg.scala 28:23] + _T_646 <= _T_652 @[lib.scala 391:14] + wrbuf_data_vld <= _T_646 @[axi4_to_ahb.scala 296:18] + node _T_653 = bits(io.axi.aw.bits.id, 0, 0) @[axi4_to_ahb.scala 297:45] + node _T_654 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 297:74] + node _T_655 = and(io.bus_clk_en, _T_654) @[lib.scala 383:57] + reg _T_656 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_655 : @[Reg.scala 28:19] + _T_656 <= _T_653 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_tag <= _T_654 @[axi4_to_ahb.scala 297:13] - node _T_655 = bits(io.axi.aw.bits.size, 2, 0) @[axi4_to_ahb.scala 298:48] - node _T_656 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 298:71] - node _T_657 = and(io.bus_clk_en, _T_656) @[lib.scala 383:57] - reg _T_658 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_657 : @[Reg.scala 28:19] - _T_658 <= _T_655 @[Reg.scala 28:23] + wrbuf_tag <= _T_656 @[axi4_to_ahb.scala 297:13] + node _T_657 = bits(io.axi.aw.bits.size, 2, 0) @[axi4_to_ahb.scala 298:48] + node _T_658 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 298:71] + node _T_659 = and(io.bus_clk_en, _T_658) @[lib.scala 383:57] + reg _T_660 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_659 : @[Reg.scala 28:19] + _T_660 <= _T_657 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_size <= _T_658 @[axi4_to_ahb.scala 298:14] - node _T_659 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 299:54] - node _T_660 = and(_T_659, io.bus_clk_en) @[axi4_to_ahb.scala 299:61] + wrbuf_size <= _T_660 @[axi4_to_ahb.scala 298:14] + node _T_661 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 299:54] + node _T_662 = and(_T_661, io.bus_clk_en) @[axi4_to_ahb.scala 299:61] inst rvclkhdr of rvclkhdr @[lib.scala 399:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 401:18] - rvclkhdr.io.en <= _T_660 @[lib.scala 402:17] + rvclkhdr.io.en <= _T_662 @[lib.scala 402:17] rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] - reg _T_661 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_660 : @[Reg.scala 28:19] - _T_661 <= io.axi.aw.bits.addr @[Reg.scala 28:23] + reg _T_663 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_662 : @[Reg.scala 28:19] + _T_663 <= io.axi.aw.bits.addr @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_addr <= _T_661 @[axi4_to_ahb.scala 299:14] - node _T_662 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 300:58] - node _T_663 = and(_T_662, io.bus_clk_en) @[axi4_to_ahb.scala 300:65] + wrbuf_addr <= _T_663 @[axi4_to_ahb.scala 299:14] + node _T_664 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 300:58] + node _T_665 = and(_T_664, io.bus_clk_en) @[axi4_to_ahb.scala 300:65] inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 399:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_1.io.en <= _T_663 @[lib.scala 402:17] + rvclkhdr_1.io.en <= _T_665 @[lib.scala 402:17] rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] - reg _T_664 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_663 : @[Reg.scala 28:19] - _T_664 <= io.axi.w.bits.data @[Reg.scala 28:23] + reg _T_666 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_665 : @[Reg.scala 28:19] + _T_666 <= io.axi.w.bits.data @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_data <= _T_664 @[axi4_to_ahb.scala 300:14] - node _T_665 = bits(io.axi.w.bits.strb, 7, 0) @[axi4_to_ahb.scala 301:49] - node _T_666 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 301:77] - node _T_667 = and(io.bus_clk_en, _T_666) @[lib.scala 383:57] - reg _T_668 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_667 : @[Reg.scala 28:19] - _T_668 <= _T_665 @[Reg.scala 28:23] + wrbuf_data <= _T_666 @[axi4_to_ahb.scala 300:14] + node _T_667 = bits(io.axi.w.bits.strb, 7, 0) @[axi4_to_ahb.scala 301:49] + node _T_668 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 301:77] + node _T_669 = and(io.bus_clk_en, _T_668) @[lib.scala 383:57] + reg _T_670 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_669 : @[Reg.scala 28:19] + _T_670 <= _T_667 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_byteen <= _T_668 @[axi4_to_ahb.scala 301:16] - node _T_669 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 302:48] - node _T_670 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 302:76] - node _T_671 = and(io.bus_clk_en, _T_670) @[lib.scala 383:57] - reg _T_672 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_671 : @[Reg.scala 28:19] - _T_672 <= _T_669 @[Reg.scala 28:23] + wrbuf_byteen <= _T_670 @[axi4_to_ahb.scala 301:16] + node _T_671 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 302:48] + node _T_672 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 302:76] + node _T_673 = and(io.bus_clk_en, _T_672) @[lib.scala 383:57] + reg _T_674 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_673 : @[Reg.scala 28:19] + _T_674 <= _T_671 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - last_bus_addr <= _T_672 @[axi4_to_ahb.scala 302:17] - node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 303:66] - node _T_674 = and(buf_clken, _T_673) @[lib.scala 383:57] - reg _T_675 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_674 : @[Reg.scala 28:19] - _T_675 <= buf_write_in @[Reg.scala 28:23] + last_bus_addr <= _T_674 @[axi4_to_ahb.scala 302:17] + node _T_675 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 303:66] + node _T_676 = and(buf_clken, _T_675) @[lib.scala 383:57] + reg _T_677 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_676 : @[Reg.scala 28:19] + _T_677 <= buf_write_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_write <= _T_675 @[axi4_to_ahb.scala 303:21] - node _T_676 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 304:46] - node _T_677 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 304:76] - node _T_678 = and(buf_clken, _T_677) @[lib.scala 383:57] - reg _T_679 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_678 : @[Reg.scala 28:19] - _T_679 <= _T_676 @[Reg.scala 28:23] + buf_write <= _T_677 @[axi4_to_ahb.scala 303:21] + node _T_678 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 304:46] + node _T_679 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 304:76] + node _T_680 = and(buf_clken, _T_679) @[lib.scala 383:57] + reg _T_681 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_680 : @[Reg.scala 28:19] + _T_681 <= _T_678 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_tag <= _T_679 @[axi4_to_ahb.scala 304:21] - node _T_680 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 305:42] - node _T_681 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 305:62] - node _T_682 = bits(_T_681, 0, 0) @[axi4_to_ahb.scala 305:79] + buf_tag <= _T_681 @[axi4_to_ahb.scala 304:21] + node _T_682 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 305:42] + node _T_683 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 305:62] + node _T_684 = bits(_T_683, 0, 0) @[axi4_to_ahb.scala 305:79] inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 399:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset rvclkhdr_2.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_2.io.en <= _T_682 @[lib.scala 402:17] + rvclkhdr_2.io.en <= _T_684 @[lib.scala 402:17] rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] - reg _T_683 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_682 : @[Reg.scala 28:19] - _T_683 <= _T_680 @[Reg.scala 28:23] + reg _T_685 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_684 : @[Reg.scala 28:19] + _T_685 <= _T_682 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_addr <= _T_683 @[axi4_to_ahb.scala 305:21] - node _T_684 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 306:47] - node _T_685 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 306:70] - node _T_686 = and(buf_clken, _T_685) @[lib.scala 383:57] - reg _T_687 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_686 : @[Reg.scala 28:19] - _T_687 <= _T_684 @[Reg.scala 28:23] + buf_addr <= _T_685 @[axi4_to_ahb.scala 305:21] + node _T_686 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 306:47] + node _T_687 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 306:70] + node _T_688 = and(buf_clken, _T_687) @[lib.scala 383:57] + reg _T_689 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_688 : @[Reg.scala 28:19] + _T_689 <= _T_686 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_size <= _T_687 @[axi4_to_ahb.scala 306:21] - node _T_688 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 307:68] - node _T_689 = and(buf_clken, _T_688) @[lib.scala 383:57] - reg _T_690 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_689 : @[Reg.scala 28:19] - _T_690 <= buf_aligned_in @[Reg.scala 28:23] + buf_size <= _T_689 @[axi4_to_ahb.scala 306:21] + node _T_690 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 307:68] + node _T_691 = and(buf_clken, _T_690) @[lib.scala 383:57] + reg _T_692 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_691 : @[Reg.scala 28:19] + _T_692 <= buf_aligned_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_aligned <= _T_690 @[axi4_to_ahb.scala 307:21] - node _T_691 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 308:49] - node _T_692 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 308:73] - node _T_693 = and(buf_clken, _T_692) @[lib.scala 383:57] - reg _T_694 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_693 : @[Reg.scala 28:19] - _T_694 <= _T_691 @[Reg.scala 28:23] + buf_aligned <= _T_692 @[axi4_to_ahb.scala 307:21] + node _T_693 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 308:49] + node _T_694 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 308:73] + node _T_695 = and(buf_clken, _T_694) @[lib.scala 383:57] + reg _T_696 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_695 : @[Reg.scala 28:19] + _T_696 <= _T_693 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_byteen <= _T_694 @[axi4_to_ahb.scala 308:21] - node _T_695 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 309:42] - node _T_696 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 309:67] - node _T_697 = bits(_T_696, 0, 0) @[axi4_to_ahb.scala 309:90] + buf_byteen <= _T_696 @[axi4_to_ahb.scala 308:21] + node _T_697 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 309:42] + node _T_698 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 309:67] + node _T_699 = bits(_T_698, 0, 0) @[axi4_to_ahb.scala 309:90] inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 399:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset rvclkhdr_3.io.clk <= clock @[lib.scala 401:18] - rvclkhdr_3.io.en <= _T_697 @[lib.scala 402:17] + rvclkhdr_3.io.en <= _T_699 @[lib.scala 402:17] rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] - reg _T_698 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_697 : @[Reg.scala 28:19] - _T_698 <= _T_695 @[Reg.scala 28:23] + reg _T_700 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_699 : @[Reg.scala 28:19] + _T_700 <= _T_697 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_data <= _T_698 @[axi4_to_ahb.scala 309:21] - node _T_699 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 310:66] - node _T_700 = and(buf_clken, _T_699) @[lib.scala 383:57] - reg _T_701 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_700 : @[Reg.scala 28:19] - _T_701 <= buf_write @[Reg.scala 28:23] + buf_data <= _T_700 @[axi4_to_ahb.scala 309:21] + node _T_701 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 310:66] + node _T_702 = and(buf_clken, _T_701) @[lib.scala 383:57] + reg _T_703 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_702 : @[Reg.scala 28:19] + _T_703 <= buf_write @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_write <= _T_701 @[axi4_to_ahb.scala 310:21] - node _T_702 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 311:43] - node _T_703 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 311:76] - node _T_704 = and(buf_clken, _T_703) @[lib.scala 383:57] - reg _T_705 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_704 : @[Reg.scala 28:19] - _T_705 <= _T_702 @[Reg.scala 28:23] + slvbuf_write <= _T_703 @[axi4_to_ahb.scala 310:21] + node _T_704 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 311:43] + node _T_705 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 311:76] + node _T_706 = and(buf_clken, _T_705) @[lib.scala 383:57] + reg _T_707 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_706 : @[Reg.scala 28:19] + _T_707 <= _T_704 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_tag <= _T_705 @[axi4_to_ahb.scala 311:21] - node _T_706 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 312:75] - node _T_707 = and(io.bus_clk_en, _T_706) @[lib.scala 383:57] - reg _T_708 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_707 : @[Reg.scala 28:19] - _T_708 <= slvbuf_error_in @[Reg.scala 28:23] + slvbuf_tag <= _T_707 @[axi4_to_ahb.scala 311:21] + node _T_708 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 312:75] + node _T_709 = and(io.bus_clk_en, _T_708) @[lib.scala 383:57] + reg _T_710 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_709 : @[Reg.scala 28:19] + _T_710 <= slvbuf_error_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_error <= _T_708 @[axi4_to_ahb.scala 312:21] - node _T_709 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 313:57] - wire _T_710 : UInt @[lib.scala 389:21] - node _T_711 = eq(cmd_done_rst, UInt<1>("h00")) @[lib.scala 391:75] - node _T_712 = and(UInt<1>("h01"), _T_711) @[lib.scala 391:53] - node _T_713 = or(_T_709, cmd_done_rst) @[lib.scala 391:95] - node _T_714 = and(_T_713, io.bus_clk_en) @[lib.scala 391:102] - node _T_715 = bits(_T_714, 0, 0) @[lib.scala 8:44] - reg _T_716 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_715 : @[Reg.scala 28:19] - _T_716 <= _T_712 @[Reg.scala 28:23] + slvbuf_error <= _T_710 @[axi4_to_ahb.scala 312:21] + node _T_711 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 313:57] + wire _T_712 : UInt @[lib.scala 389:21] + node _T_713 = eq(cmd_done_rst, UInt<1>("h00")) @[lib.scala 391:73] + node _T_714 = and(UInt<1>("h01"), _T_713) @[lib.scala 391:53] + node _T_715 = or(_T_711, cmd_done_rst) @[lib.scala 391:92] + node _T_716 = and(_T_715, io.bus_clk_en) @[lib.scala 391:99] + node _T_717 = bits(_T_716, 0, 0) @[lib.scala 8:44] + reg _T_718 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_717 : @[Reg.scala 28:19] + _T_718 <= _T_714 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - _T_710 <= _T_716 @[lib.scala 391:14] - cmd_doneQ <= _T_710 @[axi4_to_ahb.scala 313:21] - node _T_717 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 314:52] - node _T_718 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 314:86] - node _T_719 = and(io.bus_clk_en, _T_718) @[lib.scala 383:57] - reg _T_720 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_719 : @[Reg.scala 28:19] - _T_720 <= _T_717 @[Reg.scala 28:23] + _T_712 <= _T_718 @[lib.scala 391:14] + cmd_doneQ <= _T_712 @[axi4_to_ahb.scala 313:21] + node _T_719 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 314:52] + node _T_720 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 314:86] + node _T_721 = and(io.bus_clk_en, _T_720) @[lib.scala 383:57] + reg _T_722 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_721 : @[Reg.scala 28:19] + _T_722 <= _T_719 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_cmd_byte_ptrQ <= _T_720 @[axi4_to_ahb.scala 314:21] - reg _T_721 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when io.bus_clk_en : @[Reg.scala 28:19] - _T_721 <= io.ahb.in.hready @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - ahb_hready_q <= _T_721 @[axi4_to_ahb.scala 315:21] - node _T_722 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 316:52] + buf_cmd_byte_ptrQ <= _T_722 @[axi4_to_ahb.scala 314:21] reg _T_723 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when io.bus_clk_en : @[Reg.scala 28:19] - _T_723 <= _T_722 @[Reg.scala 28:23] + _T_723 <= io.ahb.in.hready @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ahb_htrans_q <= _T_723 @[axi4_to_ahb.scala 316:21] - reg _T_724 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when io.bus_clk_en : @[Reg.scala 28:19] - _T_724 <= io.ahb.out.hwrite @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - ahb_hwrite_q <= _T_724 @[axi4_to_ahb.scala 317:21] + ahb_hready_q <= _T_723 @[axi4_to_ahb.scala 315:21] + node _T_724 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 316:52] reg _T_725 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when io.bus_clk_en : @[Reg.scala 28:19] - _T_725 <= io.ahb.in.hresp @[Reg.scala 28:23] + _T_725 <= _T_724 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ahb_hresp_q <= _T_725 @[axi4_to_ahb.scala 318:21] - node _T_726 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 319:51] + ahb_htrans_q <= _T_725 @[axi4_to_ahb.scala 316:21] + reg _T_726 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when io.bus_clk_en : @[Reg.scala 28:19] + _T_726 <= io.ahb.out.hwrite @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ahb_hwrite_q <= _T_726 @[axi4_to_ahb.scala 317:21] reg _T_727 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when ahbm_data_clken : @[Reg.scala 28:19] - _T_727 <= _T_726 @[Reg.scala 28:23] + when io.bus_clk_en : @[Reg.scala 28:19] + _T_727 <= io.ahb.in.hresp @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ahb_hrdata_q <= _T_727 @[axi4_to_ahb.scala 319:21] - node _T_728 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 320:51] - node _T_729 = or(_T_728, io.clk_override) @[axi4_to_ahb.scala 320:66] - node _T_730 = and(io.bus_clk_en, _T_729) @[axi4_to_ahb.scala 320:38] - buf_clken <= _T_730 @[axi4_to_ahb.scala 320:21] - node _T_731 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 321:52] - node _T_732 = or(_T_731, io.clk_override) @[axi4_to_ahb.scala 321:62] - node _T_733 = and(io.bus_clk_en, _T_732) @[axi4_to_ahb.scala 321:38] - ahbm_data_clken <= _T_733 @[axi4_to_ahb.scala 321:21] - node _T_734 = asClock(UInt<1>("h00")) @[axi4_to_ahb.scala 323:27] - bus_clk <= _T_734 @[axi4_to_ahb.scala 323:13] - node _T_735 = asClock(UInt<1>("h00")) @[axi4_to_ahb.scala 324:27] - buf_clk <= _T_735 @[axi4_to_ahb.scala 324:13] - node _T_736 = asClock(UInt<1>("h00")) @[axi4_to_ahb.scala 325:33] - ahbm_data_clk <= _T_736 @[axi4_to_ahb.scala 325:19] + ahb_hresp_q <= _T_727 @[axi4_to_ahb.scala 318:21] + node _T_728 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 319:51] + reg _T_729 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ahbm_data_clken : @[Reg.scala 28:19] + _T_729 <= _T_728 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ahb_hrdata_q <= _T_729 @[axi4_to_ahb.scala 319:21] + node _T_730 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 320:51] + node _T_731 = or(_T_730, io.clk_override) @[axi4_to_ahb.scala 320:66] + node _T_732 = and(io.bus_clk_en, _T_731) @[axi4_to_ahb.scala 320:38] + buf_clken <= _T_732 @[axi4_to_ahb.scala 320:21] + node _T_733 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 321:52] + node _T_734 = or(_T_733, io.clk_override) @[axi4_to_ahb.scala 321:62] + node _T_735 = and(io.bus_clk_en, _T_734) @[axi4_to_ahb.scala 321:38] + ahbm_data_clken <= _T_735 @[axi4_to_ahb.scala 321:21] + node _T_736 = asClock(UInt<1>("h00")) @[axi4_to_ahb.scala 323:27] + bus_clk <= _T_736 @[axi4_to_ahb.scala 323:13] + node _T_737 = asClock(UInt<1>("h00")) @[axi4_to_ahb.scala 324:27] + buf_clk <= _T_737 @[axi4_to_ahb.scala 324:13] + node _T_738 = asClock(UInt<1>("h00")) @[axi4_to_ahb.scala 325:33] + ahbm_data_clk <= _T_738 @[axi4_to_ahb.scala 325:19] diff --git a/axi4_to_ahb.v b/axi4_to_ahb.v index 1acfe3c6..2a2ffdf4 100644 --- a/axi4_to_ahb.v +++ b/axi4_to_ahb.v @@ -116,99 +116,99 @@ module axi4_to_ahb( wire dec_tlu_force_halt_bus = io_dec_tlu_force_halt | dec_tlu_force_halt_bus_q; // @[axi4_to_ahb.scala 24:54] wire _T = ~io_bus_clk_en; // @[axi4_to_ahb.scala 25:35] reg [2:0] buf_state; // @[Reg.scala 27:20] - wire _T_47 = 3'h0 == buf_state; // @[Conditional.scala 37:30] + wire _T_49 = 3'h0 == buf_state; // @[Conditional.scala 37:30] reg wrbuf_vld; // @[Reg.scala 27:20] reg wrbuf_data_vld; // @[Reg.scala 27:20] wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 140:27] wire master_valid = wr_cmd_vld | io_axi_ar_valid; // @[axi4_to_ahb.scala 141:30] - wire _T_99 = 3'h1 == buf_state; // @[Conditional.scala 37:30] + wire _T_101 = 3'h1 == buf_state; // @[Conditional.scala 37:30] reg ahb_hready_q; // @[Reg.scala 27:20] reg [1:0] ahb_htrans_q; // @[Reg.scala 27:20] - wire _T_106 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 177:58] - wire _T_107 = ahb_hready_q & _T_106; // @[axi4_to_ahb.scala 177:36] + wire _T_108 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 177:58] + wire _T_109 = ahb_hready_q & _T_108; // @[axi4_to_ahb.scala 177:36] reg ahb_hwrite_q; // @[Reg.scala 27:20] - wire _T_108 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 177:72] - wire _T_109 = _T_107 & _T_108; // @[axi4_to_ahb.scala 177:70] - wire _T_134 = 3'h6 == buf_state; // @[Conditional.scala 37:30] + wire _T_110 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 177:72] + wire _T_111 = _T_109 & _T_110; // @[axi4_to_ahb.scala 177:70] + wire _T_136 = 3'h6 == buf_state; // @[Conditional.scala 37:30] reg ahb_hresp_q; // @[Reg.scala 27:20] - wire _T_154 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 191:37] - wire _T_173 = 3'h7 == buf_state; // @[Conditional.scala 37:30] - wire _T_184 = 3'h3 == buf_state; // @[Conditional.scala 37:30] - wire _T_186 = 3'h2 == buf_state; // @[Conditional.scala 37:30] - wire _T_187 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 223:33] - wire _T_190 = _T_187 & _T_106; // @[axi4_to_ahb.scala 223:48] - wire _T_279 = 3'h4 == buf_state; // @[Conditional.scala 37:30] - wire _GEN_16 = _T_279 & _T_190; // @[Conditional.scala 39:67] - wire _GEN_20 = _T_186 ? _T_190 : _GEN_16; // @[Conditional.scala 39:67] - wire _GEN_41 = _T_184 ? 1'h0 : _GEN_20; // @[Conditional.scala 39:67] - wire _GEN_60 = _T_173 ? 1'h0 : _GEN_41; // @[Conditional.scala 39:67] - wire _GEN_80 = _T_134 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67] - wire _GEN_96 = _T_99 ? 1'h0 : _GEN_80; // @[Conditional.scala 39:67] - wire trxn_done = _T_47 ? 1'h0 : _GEN_96; // @[Conditional.scala 40:58] + wire _T_156 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 191:37] + wire _T_175 = 3'h7 == buf_state; // @[Conditional.scala 37:30] + wire _T_186 = 3'h3 == buf_state; // @[Conditional.scala 37:30] + wire _T_188 = 3'h2 == buf_state; // @[Conditional.scala 37:30] + wire _T_189 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 223:33] + wire _T_192 = _T_189 & _T_108; // @[axi4_to_ahb.scala 223:48] + wire _T_281 = 3'h4 == buf_state; // @[Conditional.scala 37:30] + wire _GEN_16 = _T_281 & _T_192; // @[Conditional.scala 39:67] + wire _GEN_20 = _T_188 ? _T_192 : _GEN_16; // @[Conditional.scala 39:67] + wire _GEN_41 = _T_186 ? 1'h0 : _GEN_20; // @[Conditional.scala 39:67] + wire _GEN_60 = _T_175 ? 1'h0 : _GEN_41; // @[Conditional.scala 39:67] + wire _GEN_80 = _T_136 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67] + wire _GEN_96 = _T_101 ? 1'h0 : _GEN_80; // @[Conditional.scala 39:67] + wire trxn_done = _T_49 ? 1'h0 : _GEN_96; // @[Conditional.scala 40:58] reg cmd_doneQ; // @[Reg.scala 27:20] - wire _T_280 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 233:34] - wire _T_281 = _T_280 | ahb_hresp_q; // @[axi4_to_ahb.scala 233:50] - wire _T_438 = 3'h5 == buf_state; // @[Conditional.scala 37:30] + wire _T_282 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 233:34] + wire _T_283 = _T_282 | ahb_hresp_q; // @[axi4_to_ahb.scala 233:50] + wire _T_440 = 3'h5 == buf_state; // @[Conditional.scala 37:30] wire slave_ready = io_axi_b_ready & io_axi_r_ready; // @[axi4_to_ahb.scala 158:33] - wire _GEN_2 = _T_438 & slave_ready; // @[Conditional.scala 39:67] - wire _GEN_4 = _T_279 ? _T_281 : _GEN_2; // @[Conditional.scala 39:67] - wire _GEN_21 = _T_186 ? trxn_done : _GEN_4; // @[Conditional.scala 39:67] - wire _GEN_36 = _T_184 ? _T_154 : _GEN_21; // @[Conditional.scala 39:67] - wire _GEN_52 = _T_173 ? _T_109 : _GEN_36; // @[Conditional.scala 39:67] - wire _GEN_70 = _T_134 ? _T_154 : _GEN_52; // @[Conditional.scala 39:67] - wire _GEN_84 = _T_99 ? _T_109 : _GEN_70; // @[Conditional.scala 39:67] - wire buf_state_en = _T_47 ? master_valid : _GEN_84; // @[Conditional.scala 40:58] - wire _T_4 = ~dec_tlu_force_halt_bus; // @[lib.scala 391:75] - wire [1:0] _T_17 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 143:20] - wire [2:0] master_opc = {{1'd0}, _T_17}; // @[axi4_to_ahb.scala 143:14] - wire _T_49 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 163:41] - wire _GEN_9 = _T_279 & _T_49; // @[Conditional.scala 39:67] - wire _GEN_30 = _T_186 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67] - wire _GEN_47 = _T_184 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67] - wire _GEN_64 = _T_173 ? 1'h0 : _GEN_47; // @[Conditional.scala 39:67] - wire _GEN_82 = _T_134 ? 1'h0 : _GEN_64; // @[Conditional.scala 39:67] - wire _GEN_98 = _T_99 ? 1'h0 : _GEN_82; // @[Conditional.scala 39:67] - wire buf_write_in = _T_47 ? _T_49 : _GEN_98; // @[Conditional.scala 40:58] - wire [2:0] _T_51 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 164:26] - wire _T_101 = master_opc == 3'h0; // @[axi4_to_ahb.scala 176:61] - wire _T_102 = master_valid & _T_101; // @[axi4_to_ahb.scala 176:41] - wire [2:0] _T_104 = _T_102 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 176:26] - wire _T_122 = _T_104 == 3'h6; // @[axi4_to_ahb.scala 180:174] - wire _T_123 = _T_109 & _T_122; // @[axi4_to_ahb.scala 180:88] - wire _T_135 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 188:39] - wire _T_136 = ahb_hready_q & _T_135; // @[axi4_to_ahb.scala 188:37] - wire _T_139 = master_valid & _T_49; // @[axi4_to_ahb.scala 188:70] - wire _T_140 = ~_T_139; // @[axi4_to_ahb.scala 188:55] - wire _T_141 = _T_136 & _T_140; // @[axi4_to_ahb.scala 188:53] - wire _T_283 = buf_state_en & _T_135; // @[axi4_to_ahb.scala 234:36] - wire _T_284 = _T_283 & slave_ready; // @[axi4_to_ahb.scala 234:51] - wire _GEN_5 = _T_279 & _T_284; // @[Conditional.scala 39:67] - wire _GEN_27 = _T_186 ? 1'h0 : _GEN_5; // @[Conditional.scala 39:67] - wire _GEN_46 = _T_184 ? 1'h0 : _GEN_27; // @[Conditional.scala 39:67] - wire _GEN_63 = _T_173 ? 1'h0 : _GEN_46; // @[Conditional.scala 39:67] - wire _GEN_67 = _T_134 ? _T_141 : _GEN_63; // @[Conditional.scala 39:67] - wire _GEN_87 = _T_99 ? _T_123 : _GEN_67; // @[Conditional.scala 39:67] - wire master_ready = _T_47 | _GEN_87; // @[Conditional.scala 40:58] - wire _T_147 = master_valid & master_ready; // @[axi4_to_ahb.scala 190:82] - wire _T_150 = _T_147 & _T_101; // @[axi4_to_ahb.scala 190:97] - wire [2:0] _T_152 = _T_150 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 190:67] - wire [2:0] _T_153 = ahb_hresp_q ? 3'h7 : _T_152; // @[axi4_to_ahb.scala 190:26] - wire _T_285 = ~slave_ready; // @[axi4_to_ahb.scala 235:42] - wire _T_286 = ahb_hresp_q | _T_285; // @[axi4_to_ahb.scala 235:40] - wire [2:0] _T_291 = _T_49 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 235:101] - wire [2:0] _T_292 = master_valid ? _T_291 : 3'h0; // @[axi4_to_ahb.scala 235:66] - wire [2:0] _T_293 = _T_286 ? 3'h5 : _T_292; // @[axi4_to_ahb.scala 235:26] - wire [2:0] _GEN_6 = _T_279 ? _T_293 : 3'h0; // @[Conditional.scala 39:67] - wire [2:0] _GEN_19 = _T_186 ? 3'h4 : _GEN_6; // @[Conditional.scala 39:67] - wire [2:0] _GEN_35 = _T_184 ? 3'h5 : _GEN_19; // @[Conditional.scala 39:67] - wire [2:0] _GEN_51 = _T_173 ? 3'h3 : _GEN_35; // @[Conditional.scala 39:67] - wire [2:0] _GEN_69 = _T_134 ? _T_153 : _GEN_51; // @[Conditional.scala 39:67] - wire [2:0] _GEN_83 = _T_99 ? _T_104 : _GEN_69; // @[Conditional.scala 39:67] - wire [2:0] buf_nxtstate = _T_47 ? _T_51 : _GEN_83; // @[Conditional.scala 40:58] - wire [2:0] _GEN_141 = {{2'd0}, _T_4}; // @[lib.scala 391:53] - wire [2:0] _T_5 = buf_nxtstate & _GEN_141; // @[lib.scala 391:53] - wire _T_6 = buf_state_en | dec_tlu_force_halt_bus; // @[lib.scala 391:95] - wire _T_7 = _T_6 & io_bus_clk_en; // @[lib.scala 391:102] + wire _GEN_2 = _T_440 & slave_ready; // @[Conditional.scala 39:67] + wire _GEN_4 = _T_281 ? _T_283 : _GEN_2; // @[Conditional.scala 39:67] + wire _GEN_21 = _T_188 ? trxn_done : _GEN_4; // @[Conditional.scala 39:67] + wire _GEN_36 = _T_186 ? _T_156 : _GEN_21; // @[Conditional.scala 39:67] + wire _GEN_52 = _T_175 ? _T_111 : _GEN_36; // @[Conditional.scala 39:67] + wire _GEN_70 = _T_136 ? _T_156 : _GEN_52; // @[Conditional.scala 39:67] + wire _GEN_84 = _T_101 ? _T_111 : _GEN_70; // @[Conditional.scala 39:67] + wire buf_state_en = _T_49 ? master_valid : _GEN_84; // @[Conditional.scala 40:58] + wire _T_4 = ~dec_tlu_force_halt_bus; // @[lib.scala 391:73] + wire [2:0] _T_6 = _T_4 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_19 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 143:20] + wire [2:0] master_opc = {{1'd0}, _T_19}; // @[axi4_to_ahb.scala 143:14] + wire _T_51 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 163:41] + wire _GEN_9 = _T_281 & _T_51; // @[Conditional.scala 39:67] + wire _GEN_30 = _T_188 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67] + wire _GEN_47 = _T_186 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67] + wire _GEN_64 = _T_175 ? 1'h0 : _GEN_47; // @[Conditional.scala 39:67] + wire _GEN_82 = _T_136 ? 1'h0 : _GEN_64; // @[Conditional.scala 39:67] + wire _GEN_98 = _T_101 ? 1'h0 : _GEN_82; // @[Conditional.scala 39:67] + wire buf_write_in = _T_49 ? _T_51 : _GEN_98; // @[Conditional.scala 40:58] + wire [2:0] _T_53 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 164:26] + wire _T_103 = master_opc == 3'h0; // @[axi4_to_ahb.scala 176:61] + wire _T_104 = master_valid & _T_103; // @[axi4_to_ahb.scala 176:41] + wire [2:0] _T_106 = _T_104 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 176:26] + wire _T_124 = _T_106 == 3'h6; // @[axi4_to_ahb.scala 180:174] + wire _T_125 = _T_111 & _T_124; // @[axi4_to_ahb.scala 180:88] + wire _T_137 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 188:39] + wire _T_138 = ahb_hready_q & _T_137; // @[axi4_to_ahb.scala 188:37] + wire _T_141 = master_valid & _T_51; // @[axi4_to_ahb.scala 188:70] + wire _T_142 = ~_T_141; // @[axi4_to_ahb.scala 188:55] + wire _T_143 = _T_138 & _T_142; // @[axi4_to_ahb.scala 188:53] + wire _T_285 = buf_state_en & _T_137; // @[axi4_to_ahb.scala 234:36] + wire _T_286 = _T_285 & slave_ready; // @[axi4_to_ahb.scala 234:51] + wire _GEN_5 = _T_281 & _T_286; // @[Conditional.scala 39:67] + wire _GEN_27 = _T_188 ? 1'h0 : _GEN_5; // @[Conditional.scala 39:67] + wire _GEN_46 = _T_186 ? 1'h0 : _GEN_27; // @[Conditional.scala 39:67] + wire _GEN_63 = _T_175 ? 1'h0 : _GEN_46; // @[Conditional.scala 39:67] + wire _GEN_67 = _T_136 ? _T_143 : _GEN_63; // @[Conditional.scala 39:67] + wire _GEN_87 = _T_101 ? _T_125 : _GEN_67; // @[Conditional.scala 39:67] + wire master_ready = _T_49 | _GEN_87; // @[Conditional.scala 40:58] + wire _T_149 = master_valid & master_ready; // @[axi4_to_ahb.scala 190:82] + wire _T_152 = _T_149 & _T_103; // @[axi4_to_ahb.scala 190:97] + wire [2:0] _T_154 = _T_152 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 190:67] + wire [2:0] _T_155 = ahb_hresp_q ? 3'h7 : _T_154; // @[axi4_to_ahb.scala 190:26] + wire _T_287 = ~slave_ready; // @[axi4_to_ahb.scala 235:42] + wire _T_288 = ahb_hresp_q | _T_287; // @[axi4_to_ahb.scala 235:40] + wire [2:0] _T_293 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 235:101] + wire [2:0] _T_294 = master_valid ? _T_293 : 3'h0; // @[axi4_to_ahb.scala 235:66] + wire [2:0] _T_295 = _T_288 ? 3'h5 : _T_294; // @[axi4_to_ahb.scala 235:26] + wire [2:0] _GEN_6 = _T_281 ? _T_295 : 3'h0; // @[Conditional.scala 39:67] + wire [2:0] _GEN_19 = _T_188 ? 3'h4 : _GEN_6; // @[Conditional.scala 39:67] + wire [2:0] _GEN_35 = _T_186 ? 3'h5 : _GEN_19; // @[Conditional.scala 39:67] + wire [2:0] _GEN_51 = _T_175 ? 3'h3 : _GEN_35; // @[Conditional.scala 39:67] + wire [2:0] _GEN_69 = _T_136 ? _T_155 : _GEN_51; // @[Conditional.scala 39:67] + wire [2:0] _GEN_83 = _T_101 ? _T_106 : _GEN_69; // @[Conditional.scala 39:67] + wire [2:0] buf_nxtstate = _T_49 ? _T_53 : _GEN_83; // @[Conditional.scala 40:58] + wire [2:0] _T_7 = buf_nxtstate & _T_6; // @[lib.scala 391:53] + wire _T_8 = buf_state_en | dec_tlu_force_halt_bus; // @[lib.scala 391:92] + wire _T_9 = _T_8 & io_bus_clk_en; // @[lib.scala 391:99] reg wrbuf_tag; // @[Reg.scala 27:20] reg [31:0] wrbuf_addr; // @[Reg.scala 27:20] wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_ar_bits_addr; // @[axi4_to_ahb.scala 144:21] @@ -216,280 +216,280 @@ module axi4_to_ahb( wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_ar_bits_size; // @[axi4_to_ahb.scala 145:21] reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20] reg [63:0] wrbuf_data; // @[Reg.scala 27:20] - wire _T_356 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 245:55] - wire _T_357 = buf_state_en & _T_356; // @[axi4_to_ahb.scala 245:39] - wire _GEN_15 = _T_279 ? _T_357 : _T_438; // @[Conditional.scala 39:67] - wire _GEN_34 = _T_186 ? 1'h0 : _GEN_15; // @[Conditional.scala 39:67] - wire _GEN_50 = _T_184 ? 1'h0 : _GEN_34; // @[Conditional.scala 39:67] - wire _GEN_53 = _T_173 ? buf_state_en : _GEN_50; // @[Conditional.scala 39:67] - wire _GEN_74 = _T_134 ? _T_283 : _GEN_53; // @[Conditional.scala 39:67] - wire _GEN_95 = _T_99 ? 1'h0 : _GEN_74; // @[Conditional.scala 39:67] - wire slave_valid_pre = _T_47 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58] - wire _T_28 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 150:33] + wire _T_358 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 245:55] + wire _T_359 = buf_state_en & _T_358; // @[axi4_to_ahb.scala 245:39] + wire _GEN_15 = _T_281 ? _T_359 : _T_440; // @[Conditional.scala 39:67] + wire _GEN_34 = _T_188 ? 1'h0 : _GEN_15; // @[Conditional.scala 39:67] + wire _GEN_50 = _T_186 ? 1'h0 : _GEN_34; // @[Conditional.scala 39:67] + wire _GEN_53 = _T_175 ? buf_state_en : _GEN_50; // @[Conditional.scala 39:67] + wire _GEN_74 = _T_136 ? _T_285 : _GEN_53; // @[Conditional.scala 39:67] + wire _GEN_95 = _T_101 ? 1'h0 : _GEN_74; // @[Conditional.scala 39:67] + wire slave_valid_pre = _T_49 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58] + wire _T_30 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 150:33] reg slvbuf_write; // @[Reg.scala 27:20] - wire [1:0] _T_595 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 279:23] + wire [1:0] _T_597 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 279:23] reg slvbuf_error; // @[Reg.scala 27:20] - wire [1:0] _T_597 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_598 = _T_597 & 2'h2; // @[axi4_to_ahb.scala 279:88] - wire [3:0] slave_opc = {_T_595,_T_598}; // @[Cat.scala 29:58] - wire [1:0] _T_33 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 151:55] + wire [1:0] _T_599 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_600 = _T_599 & 2'h2; // @[axi4_to_ahb.scala 279:88] + wire [3:0] slave_opc = {_T_597,_T_600}; // @[Cat.scala 29:58] + wire [1:0] _T_35 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 151:55] reg slvbuf_tag; // @[Reg.scala 27:20] - wire _T_38 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 154:66] + wire _T_40 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 154:66] reg [31:0] last_bus_addr; // @[Reg.scala 27:20] - wire [63:0] _T_602 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58] - wire _T_603 = buf_state == 3'h5; // @[axi4_to_ahb.scala 280:91] + wire [63:0] _T_604 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58] + wire _T_605 = buf_state == 3'h5; // @[axi4_to_ahb.scala 280:91] reg [63:0] buf_data; // @[Reg.scala 27:20] reg [63:0] ahb_hrdata_q; // @[Reg.scala 27:20] - wire [63:0] _T_606 = _T_603 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 280:79] - wire _T_53 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 167:54] - wire _T_54 = buf_state_en & _T_53; // @[axi4_to_ahb.scala 167:38] - wire [2:0] _T_85 = wrbuf_byteen[6] ? 3'h6 : 3'h7; // @[Mux.scala 98:16] - wire [2:0] _T_86 = wrbuf_byteen[5] ? 3'h5 : _T_85; // @[Mux.scala 98:16] - wire [2:0] _T_87 = wrbuf_byteen[4] ? 3'h4 : _T_86; // @[Mux.scala 98:16] - wire [2:0] _T_88 = wrbuf_byteen[3] ? 3'h3 : _T_87; // @[Mux.scala 98:16] - wire [2:0] _T_89 = wrbuf_byteen[2] ? 3'h2 : _T_88; // @[Mux.scala 98:16] - wire [2:0] _T_90 = wrbuf_byteen[1] ? 3'h1 : _T_89; // @[Mux.scala 98:16] - wire [2:0] _T_91 = wrbuf_byteen[0] ? 3'h0 : _T_90; // @[Mux.scala 98:16] - wire [2:0] _T_93 = buf_write_in ? _T_91 : master_addr[2:0]; // @[axi4_to_ahb.scala 169:30] - wire _T_94 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 171:51] - wire _T_124 = master_ready & master_valid; // @[axi4_to_ahb.scala 182:33] - wire _T_160 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 197:64] - wire _T_161 = _T_124 & _T_160; // @[axi4_to_ahb.scala 197:48] - wire _T_162 = _T_161 & buf_state_en; // @[axi4_to_ahb.scala 197:79] - wire _T_347 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 243:33] - wire _T_349 = _T_347 & _T_53; // @[axi4_to_ahb.scala 243:48] - wire _GEN_13 = _T_279 & _T_349; // @[Conditional.scala 39:67] - wire _GEN_33 = _T_186 ? 1'h0 : _GEN_13; // @[Conditional.scala 39:67] - wire _GEN_49 = _T_184 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67] - wire _GEN_66 = _T_173 ? 1'h0 : _GEN_49; // @[Conditional.scala 39:67] - wire _GEN_76 = _T_134 ? _T_162 : _GEN_66; // @[Conditional.scala 39:67] - wire _GEN_89 = _T_99 ? _T_124 : _GEN_76; // @[Conditional.scala 39:67] - wire bypass_en = _T_47 ? buf_state_en : _GEN_89; // @[Conditional.scala 40:58] - wire [1:0] _T_97 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_98 = _T_97 & 2'h2; // @[axi4_to_ahb.scala 172:49] - wire _T_110 = ~master_valid; // @[axi4_to_ahb.scala 178:34] - wire _T_111 = buf_state_en & _T_110; // @[axi4_to_ahb.scala 178:32] + wire [63:0] _T_608 = _T_605 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 280:79] + wire _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 167:54] + wire _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 167:38] + wire [2:0] _T_87 = wrbuf_byteen[6] ? 3'h6 : 3'h7; // @[Mux.scala 98:16] + wire [2:0] _T_88 = wrbuf_byteen[5] ? 3'h5 : _T_87; // @[Mux.scala 98:16] + wire [2:0] _T_89 = wrbuf_byteen[4] ? 3'h4 : _T_88; // @[Mux.scala 98:16] + wire [2:0] _T_90 = wrbuf_byteen[3] ? 3'h3 : _T_89; // @[Mux.scala 98:16] + wire [2:0] _T_91 = wrbuf_byteen[2] ? 3'h2 : _T_90; // @[Mux.scala 98:16] + wire [2:0] _T_92 = wrbuf_byteen[1] ? 3'h1 : _T_91; // @[Mux.scala 98:16] + wire [2:0] _T_93 = wrbuf_byteen[0] ? 3'h0 : _T_92; // @[Mux.scala 98:16] + wire [2:0] _T_95 = buf_write_in ? _T_93 : master_addr[2:0]; // @[axi4_to_ahb.scala 169:30] + wire _T_96 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 171:51] + wire _T_126 = master_ready & master_valid; // @[axi4_to_ahb.scala 182:33] + wire _T_162 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 197:64] + wire _T_163 = _T_126 & _T_162; // @[axi4_to_ahb.scala 197:48] + wire _T_164 = _T_163 & buf_state_en; // @[axi4_to_ahb.scala 197:79] + wire _T_349 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 243:33] + wire _T_351 = _T_349 & _T_55; // @[axi4_to_ahb.scala 243:48] + wire _GEN_13 = _T_281 & _T_351; // @[Conditional.scala 39:67] + wire _GEN_33 = _T_188 ? 1'h0 : _GEN_13; // @[Conditional.scala 39:67] + wire _GEN_49 = _T_186 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67] + wire _GEN_66 = _T_175 ? 1'h0 : _GEN_49; // @[Conditional.scala 39:67] + wire _GEN_76 = _T_136 ? _T_164 : _GEN_66; // @[Conditional.scala 39:67] + wire _GEN_89 = _T_101 ? _T_126 : _GEN_76; // @[Conditional.scala 39:67] + wire bypass_en = _T_49 ? buf_state_en : _GEN_89; // @[Conditional.scala 40:58] + wire [1:0] _T_99 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_100 = _T_99 & 2'h2; // @[axi4_to_ahb.scala 172:49] + wire _T_112 = ~master_valid; // @[axi4_to_ahb.scala 178:34] + wire _T_113 = buf_state_en & _T_112; // @[axi4_to_ahb.scala 178:32] reg [31:0] buf_addr; // @[Reg.scala 27:20] - wire [2:0] _T_128 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 183:30] - wire _T_129 = ~buf_state_en; // @[axi4_to_ahb.scala 184:48] - wire _T_130 = _T_129 | bypass_en; // @[axi4_to_ahb.scala 184:62] - wire [1:0] _T_132 = _T_130 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_133 = 2'h2 & _T_132; // @[axi4_to_ahb.scala 184:36] - wire _T_167 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 199:63] - wire _T_168 = _T_167 & buf_state_en; // @[axi4_to_ahb.scala 199:78] - wire _T_169 = ~_T_168; // @[axi4_to_ahb.scala 199:47] - wire [1:0] _T_171 = _T_169 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_172 = 2'h2 & _T_171; // @[axi4_to_ahb.scala 199:36] - wire [1:0] _T_182 = _T_129 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_183 = 2'h2 & _T_182; // @[axi4_to_ahb.scala 209:41] + wire [2:0] _T_130 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 183:30] + wire _T_131 = ~buf_state_en; // @[axi4_to_ahb.scala 184:48] + wire _T_132 = _T_131 | bypass_en; // @[axi4_to_ahb.scala 184:62] + wire [1:0] _T_134 = _T_132 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_135 = 2'h2 & _T_134; // @[axi4_to_ahb.scala 184:36] + wire _T_169 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 199:63] + wire _T_170 = _T_169 & buf_state_en; // @[axi4_to_ahb.scala 199:78] + wire _T_171 = ~_T_170; // @[axi4_to_ahb.scala 199:47] + wire [1:0] _T_173 = _T_171 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_174 = 2'h2 & _T_173; // @[axi4_to_ahb.scala 199:36] + wire [1:0] _T_184 = _T_131 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_185 = 2'h2 & _T_184; // @[axi4_to_ahb.scala 209:41] reg [2:0] buf_cmd_byte_ptrQ; // @[Reg.scala 27:20] reg [7:0] buf_byteen; // @[Reg.scala 27:20] - wire [2:0] _T_195 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 136:52] - wire _T_198 = 3'h0 >= _T_195; // @[axi4_to_ahb.scala 137:62] - wire _T_199 = buf_byteen[0] & _T_198; // @[axi4_to_ahb.scala 137:48] - wire _T_201 = 3'h1 >= _T_195; // @[axi4_to_ahb.scala 137:62] - wire _T_202 = buf_byteen[1] & _T_201; // @[axi4_to_ahb.scala 137:48] - wire _T_204 = 3'h2 >= _T_195; // @[axi4_to_ahb.scala 137:62] - wire _T_205 = buf_byteen[2] & _T_204; // @[axi4_to_ahb.scala 137:48] - wire _T_207 = 3'h3 >= _T_195; // @[axi4_to_ahb.scala 137:62] - wire _T_208 = buf_byteen[3] & _T_207; // @[axi4_to_ahb.scala 137:48] - wire _T_210 = 3'h4 >= _T_195; // @[axi4_to_ahb.scala 137:62] - wire _T_211 = buf_byteen[4] & _T_210; // @[axi4_to_ahb.scala 137:48] - wire _T_213 = 3'h5 >= _T_195; // @[axi4_to_ahb.scala 137:62] - wire _T_214 = buf_byteen[5] & _T_213; // @[axi4_to_ahb.scala 137:48] - wire _T_216 = 3'h6 >= _T_195; // @[axi4_to_ahb.scala 137:62] - wire _T_217 = buf_byteen[6] & _T_216; // @[axi4_to_ahb.scala 137:48] - wire [2:0] _T_222 = _T_217 ? 3'h6 : 3'h7; // @[Mux.scala 98:16] - wire [2:0] _T_223 = _T_214 ? 3'h5 : _T_222; // @[Mux.scala 98:16] - wire [2:0] _T_224 = _T_211 ? 3'h4 : _T_223; // @[Mux.scala 98:16] - wire [2:0] _T_225 = _T_208 ? 3'h3 : _T_224; // @[Mux.scala 98:16] - wire [2:0] _T_226 = _T_205 ? 3'h2 : _T_225; // @[Mux.scala 98:16] - wire [2:0] _T_227 = _T_202 ? 3'h1 : _T_226; // @[Mux.scala 98:16] - wire [2:0] _T_228 = _T_199 ? 3'h0 : _T_227; // @[Mux.scala 98:16] - wire [2:0] _T_229 = trxn_done ? _T_228 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 227:30] - wire _T_230 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 228:65] + wire [2:0] _T_197 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 136:52] + wire _T_200 = 3'h0 >= _T_197; // @[axi4_to_ahb.scala 137:62] + wire _T_201 = buf_byteen[0] & _T_200; // @[axi4_to_ahb.scala 137:48] + wire _T_203 = 3'h1 >= _T_197; // @[axi4_to_ahb.scala 137:62] + wire _T_204 = buf_byteen[1] & _T_203; // @[axi4_to_ahb.scala 137:48] + wire _T_206 = 3'h2 >= _T_197; // @[axi4_to_ahb.scala 137:62] + wire _T_207 = buf_byteen[2] & _T_206; // @[axi4_to_ahb.scala 137:48] + wire _T_209 = 3'h3 >= _T_197; // @[axi4_to_ahb.scala 137:62] + wire _T_210 = buf_byteen[3] & _T_209; // @[axi4_to_ahb.scala 137:48] + wire _T_212 = 3'h4 >= _T_197; // @[axi4_to_ahb.scala 137:62] + wire _T_213 = buf_byteen[4] & _T_212; // @[axi4_to_ahb.scala 137:48] + wire _T_215 = 3'h5 >= _T_197; // @[axi4_to_ahb.scala 137:62] + wire _T_216 = buf_byteen[5] & _T_215; // @[axi4_to_ahb.scala 137:48] + wire _T_218 = 3'h6 >= _T_197; // @[axi4_to_ahb.scala 137:62] + wire _T_219 = buf_byteen[6] & _T_218; // @[axi4_to_ahb.scala 137:48] + wire [2:0] _T_224 = _T_219 ? 3'h6 : 3'h7; // @[Mux.scala 98:16] + wire [2:0] _T_225 = _T_216 ? 3'h5 : _T_224; // @[Mux.scala 98:16] + wire [2:0] _T_226 = _T_213 ? 3'h4 : _T_225; // @[Mux.scala 98:16] + wire [2:0] _T_227 = _T_210 ? 3'h3 : _T_226; // @[Mux.scala 98:16] + wire [2:0] _T_228 = _T_207 ? 3'h2 : _T_227; // @[Mux.scala 98:16] + wire [2:0] _T_229 = _T_204 ? 3'h1 : _T_228; // @[Mux.scala 98:16] + wire [2:0] _T_230 = _T_201 ? 3'h0 : _T_229; // @[Mux.scala 98:16] + wire [2:0] _T_231 = trxn_done ? _T_230 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 227:30] + wire _T_232 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 228:65] reg buf_aligned; // @[Reg.scala 27:20] - wire _T_231 = buf_aligned | _T_230; // @[axi4_to_ahb.scala 228:44] - wire [7:0] _T_269 = buf_byteen >> _T_228; // @[axi4_to_ahb.scala 228:92] - wire _T_271 = ~_T_269[0]; // @[axi4_to_ahb.scala 228:163] - wire _T_272 = _T_231 | _T_271; // @[axi4_to_ahb.scala 228:79] - wire _T_273 = trxn_done & _T_272; // @[axi4_to_ahb.scala 228:29] - wire _T_344 = _T_230 | _T_271; // @[axi4_to_ahb.scala 242:38] - wire _T_345 = _T_107 & _T_344; // @[axi4_to_ahb.scala 241:79] - wire _T_346 = ahb_hresp_q | _T_345; // @[axi4_to_ahb.scala 241:32] - wire _GEN_12 = _T_279 & _T_346; // @[Conditional.scala 39:67] - wire _GEN_25 = _T_186 ? _T_273 : _GEN_12; // @[Conditional.scala 39:67] - wire _GEN_44 = _T_184 ? 1'h0 : _GEN_25; // @[Conditional.scala 39:67] - wire _GEN_62 = _T_173 ? 1'h0 : _GEN_44; // @[Conditional.scala 39:67] - wire _GEN_75 = _T_134 ? _T_111 : _GEN_62; // @[Conditional.scala 39:67] - wire _GEN_85 = _T_99 ? _T_111 : _GEN_75; // @[Conditional.scala 39:67] - wire cmd_done = _T_47 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] - wire _T_274 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 229:47] - wire _T_275 = ~_T_274; // @[axi4_to_ahb.scala 229:36] - wire [1:0] _T_277 = _T_275 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_278 = _T_277 & 2'h2; // @[axi4_to_ahb.scala 229:61] - wire _T_298 = _T_53 | _T_94; // @[axi4_to_ahb.scala 239:62] - wire _T_299 = buf_state_en & _T_298; // @[axi4_to_ahb.scala 239:33] - wire _T_352 = _T_275 | bypass_en; // @[axi4_to_ahb.scala 244:61] - wire [1:0] _T_354 = _T_352 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_355 = _T_354 & 2'h2; // @[axi4_to_ahb.scala 244:75] - wire _T_362 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 247:40] - wire [2:0] _T_437 = bypass_en ? _T_91 : _T_229; // @[axi4_to_ahb.scala 248:30] - wire _GEN_7 = _T_279 & ahb_hresp_q; // @[Conditional.scala 39:67] - wire _GEN_8 = _T_279 ? buf_state_en : _T_438; // @[Conditional.scala 39:67] - wire _GEN_10 = _T_279 & _T_299; // @[Conditional.scala 39:67] - wire _GEN_31 = _T_186 ? 1'h0 : _GEN_10; // @[Conditional.scala 39:67] - wire _GEN_48 = _T_184 ? 1'h0 : _GEN_31; // @[Conditional.scala 39:67] - wire _GEN_65 = _T_173 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67] - wire _GEN_68 = _T_134 ? _T_150 : _GEN_65; // @[Conditional.scala 39:67] - wire _GEN_88 = _T_99 ? master_ready : _GEN_68; // @[Conditional.scala 39:67] - wire buf_wr_en = _T_47 ? buf_state_en : _GEN_88; // @[Conditional.scala 40:58] - wire _GEN_11 = _T_279 & buf_wr_en; // @[Conditional.scala 39:67] - wire [1:0] _GEN_14 = _T_279 ? _T_355 : 2'h0; // @[Conditional.scala 39:67] - wire _GEN_17 = _T_279 & _T_362; // @[Conditional.scala 39:67] - wire [2:0] _GEN_18 = _T_279 ? _T_437 : 3'h0; // @[Conditional.scala 39:67] - wire _GEN_22 = _T_186 ? buf_state_en : _GEN_17; // @[Conditional.scala 39:67] - wire _GEN_23 = _T_186 & buf_state_en; // @[Conditional.scala 39:67] - wire [2:0] _GEN_24 = _T_186 ? _T_229 : _GEN_18; // @[Conditional.scala 39:67] - wire [1:0] _GEN_26 = _T_186 ? _T_278 : _GEN_14; // @[Conditional.scala 39:67] - wire _GEN_29 = _T_186 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67] - wire _GEN_32 = _T_186 ? 1'h0 : _GEN_11; // @[Conditional.scala 39:67] - wire _GEN_37 = _T_184 ? buf_state_en : _GEN_32; // @[Conditional.scala 39:67] - wire _GEN_39 = _T_184 ? buf_state_en : _GEN_29; // @[Conditional.scala 39:67] - wire _GEN_40 = _T_184 ? buf_state_en : _GEN_23; // @[Conditional.scala 39:67] - wire _GEN_42 = _T_184 ? 1'h0 : _GEN_22; // @[Conditional.scala 39:67] - wire [2:0] _GEN_43 = _T_184 ? 3'h0 : _GEN_24; // @[Conditional.scala 39:67] - wire [1:0] _GEN_45 = _T_184 ? 2'h0 : _GEN_26; // @[Conditional.scala 39:67] - wire _GEN_54 = _T_173 ? buf_state_en : _GEN_40; // @[Conditional.scala 39:67] - wire [2:0] _GEN_55 = _T_173 ? buf_addr[2:0] : _GEN_43; // @[Conditional.scala 39:67] - wire [1:0] _GEN_56 = _T_173 ? _T_183 : _GEN_45; // @[Conditional.scala 39:67] - wire _GEN_57 = _T_173 ? 1'h0 : _GEN_37; // @[Conditional.scala 39:67] - wire _GEN_59 = _T_173 ? 1'h0 : _GEN_39; // @[Conditional.scala 39:67] - wire _GEN_61 = _T_173 ? 1'h0 : _GEN_42; // @[Conditional.scala 39:67] - wire _GEN_71 = _T_134 ? buf_state_en : _GEN_57; // @[Conditional.scala 39:67] - wire _GEN_73 = _T_134 ? buf_state_en : _GEN_59; // @[Conditional.scala 39:67] - wire [2:0] _GEN_77 = _T_134 ? _T_128 : _GEN_55; // @[Conditional.scala 39:67] - wire [1:0] _GEN_78 = _T_134 ? _T_172 : _GEN_56; // @[Conditional.scala 39:67] - wire _GEN_79 = _T_134 ? buf_wr_en : _GEN_54; // @[Conditional.scala 39:67] - wire _GEN_81 = _T_134 ? 1'h0 : _GEN_61; // @[Conditional.scala 39:67] - wire _GEN_86 = _T_99 ? buf_state_en : _GEN_79; // @[Conditional.scala 39:67] - wire [2:0] _GEN_90 = _T_99 ? _T_128 : _GEN_77; // @[Conditional.scala 39:67] - wire [1:0] _GEN_91 = _T_99 ? _T_133 : _GEN_78; // @[Conditional.scala 39:67] - wire _GEN_92 = _T_99 ? 1'h0 : _GEN_71; // @[Conditional.scala 39:67] - wire _GEN_94 = _T_99 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67] - wire _GEN_97 = _T_99 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] - wire buf_data_wr_en = _T_47 ? _T_54 : _GEN_92; // @[Conditional.scala 40:58] - wire buf_cmd_byte_ptr_en = _T_47 ? buf_state_en : _GEN_97; // @[Conditional.scala 40:58] - wire [2:0] buf_cmd_byte_ptr = _T_47 ? _T_93 : _GEN_90; // @[Conditional.scala 40:58] - wire slvbuf_wr_en = _T_47 ? 1'h0 : _GEN_86; // @[Conditional.scala 40:58] - wire slvbuf_error_en = _T_47 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58] - wire _T_533 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 265:24] - wire _T_534 = _T_101 | _T_533; // @[axi4_to_ahb.scala 264:48] - wire _T_536 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 265:54] - wire _T_537 = _T_534 | _T_536; // @[axi4_to_ahb.scala 265:33] - wire _T_539 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 265:93] - wire _T_540 = _T_537 | _T_539; // @[axi4_to_ahb.scala 265:72] - wire _T_542 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 266:25] - wire _T_544 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 266:62] - wire _T_546 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 266:97] - wire _T_547 = _T_544 | _T_546; // @[axi4_to_ahb.scala 266:74] - wire _T_549 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 266:132] - wire _T_550 = _T_547 | _T_549; // @[axi4_to_ahb.scala 266:109] - wire _T_552 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 266:168] - wire _T_553 = _T_550 | _T_552; // @[axi4_to_ahb.scala 266:145] - wire _T_555 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 267:28] - wire _T_556 = _T_553 | _T_555; // @[axi4_to_ahb.scala 266:181] - wire _T_558 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 267:63] - wire _T_559 = _T_556 | _T_558; // @[axi4_to_ahb.scala 267:40] - wire _T_561 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 267:99] - wire _T_562 = _T_559 | _T_561; // @[axi4_to_ahb.scala 267:76] - wire _T_563 = _T_542 & _T_562; // @[axi4_to_ahb.scala 266:38] - wire buf_aligned_in = _T_540 | _T_563; // @[axi4_to_ahb.scala 265:106] - wire _T_442 = buf_aligned_in & _T_49; // @[axi4_to_ahb.scala 259:62] - wire [2:0] _T_459 = _T_546 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_460 = 3'h2 & _T_459; // @[axi4_to_ahb.scala 128:15] - wire _T_466 = _T_558 | _T_544; // @[axi4_to_ahb.scala 129:56] - wire [2:0] _T_468 = _T_466 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_469 = 3'h4 & _T_468; // @[axi4_to_ahb.scala 129:15] - wire [2:0] _T_470 = _T_460 | _T_469; // @[axi4_to_ahb.scala 128:63] - wire [2:0] _T_474 = _T_552 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_475 = 3'h6 & _T_474; // @[axi4_to_ahb.scala 130:15] - wire [2:0] _T_476 = _T_470 | _T_475; // @[axi4_to_ahb.scala 129:96] - wire [2:0] _T_483 = _T_442 ? _T_476 : master_addr[2:0]; // @[axi4_to_ahb.scala 259:45] - wire [31:0] buf_addr_in = {master_addr[31:3],_T_483}; // @[Cat.scala 29:58] - wire _T_487 = buf_state == 3'h3; // @[axi4_to_ahb.scala 262:33] - wire _T_493 = buf_aligned_in & _T_542; // @[axi4_to_ahb.scala 263:38] - wire _T_496 = _T_493 & _T_49; // @[axi4_to_ahb.scala 263:72] - wire [1:0] _T_502 = _T_561 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire _T_508 = _T_558 | _T_555; // @[axi4_to_ahb.scala 121:55] - wire [1:0] _T_510 = _T_508 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_511 = 2'h2 & _T_510; // @[axi4_to_ahb.scala 121:16] - wire [1:0] _T_512 = _T_502 | _T_511; // @[axi4_to_ahb.scala 120:64] - wire _T_517 = _T_552 | _T_549; // @[axi4_to_ahb.scala 122:60] - wire _T_520 = _T_517 | _T_546; // @[axi4_to_ahb.scala 122:89] - wire _T_523 = _T_520 | _T_544; // @[axi4_to_ahb.scala 122:123] - wire [1:0] _T_525 = _T_523 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_526 = 2'h1 & _T_525; // @[axi4_to_ahb.scala 122:21] - wire [1:0] _T_527 = _T_512 | _T_526; // @[axi4_to_ahb.scala 121:93] - wire [1:0] _T_529 = _T_496 ? _T_527 : master_size[1:0]; // @[axi4_to_ahb.scala 263:21] - wire [28:0] _T_568 = bypass_en ? master_addr[31:3] : buf_addr[31:3]; // @[axi4_to_ahb.scala 269:30] - wire _T_569 = io_ahb_out_htrans == 2'h2; // @[axi4_to_ahb.scala 269:115] - wire [2:0] _T_571 = _T_569 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_572 = _T_571 & buf_cmd_byte_ptr; // @[axi4_to_ahb.scala 269:124] - wire [1:0] _T_576 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [2:0] buf_size_in = {{1'd0}, _T_529}; // @[axi4_to_ahb.scala 263:15] - wire [1:0] _T_578 = _T_576 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 270:81] - wire [2:0] _T_579 = {1'h0,_T_578}; // @[Cat.scala 29:58] - wire [1:0] _T_581 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire _T_233 = buf_aligned | _T_232; // @[axi4_to_ahb.scala 228:44] + wire [7:0] _T_271 = buf_byteen >> _T_230; // @[axi4_to_ahb.scala 228:92] + wire _T_273 = ~_T_271[0]; // @[axi4_to_ahb.scala 228:163] + wire _T_274 = _T_233 | _T_273; // @[axi4_to_ahb.scala 228:79] + wire _T_275 = trxn_done & _T_274; // @[axi4_to_ahb.scala 228:29] + wire _T_346 = _T_232 | _T_273; // @[axi4_to_ahb.scala 242:38] + wire _T_347 = _T_109 & _T_346; // @[axi4_to_ahb.scala 241:79] + wire _T_348 = ahb_hresp_q | _T_347; // @[axi4_to_ahb.scala 241:32] + wire _GEN_12 = _T_281 & _T_348; // @[Conditional.scala 39:67] + wire _GEN_25 = _T_188 ? _T_275 : _GEN_12; // @[Conditional.scala 39:67] + wire _GEN_44 = _T_186 ? 1'h0 : _GEN_25; // @[Conditional.scala 39:67] + wire _GEN_62 = _T_175 ? 1'h0 : _GEN_44; // @[Conditional.scala 39:67] + wire _GEN_75 = _T_136 ? _T_113 : _GEN_62; // @[Conditional.scala 39:67] + wire _GEN_85 = _T_101 ? _T_113 : _GEN_75; // @[Conditional.scala 39:67] + wire cmd_done = _T_49 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] + wire _T_276 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 229:47] + wire _T_277 = ~_T_276; // @[axi4_to_ahb.scala 229:36] + wire [1:0] _T_279 = _T_277 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_280 = _T_279 & 2'h2; // @[axi4_to_ahb.scala 229:61] + wire _T_300 = _T_55 | _T_96; // @[axi4_to_ahb.scala 239:62] + wire _T_301 = buf_state_en & _T_300; // @[axi4_to_ahb.scala 239:33] + wire _T_354 = _T_277 | bypass_en; // @[axi4_to_ahb.scala 244:61] + wire [1:0] _T_356 = _T_354 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_357 = _T_356 & 2'h2; // @[axi4_to_ahb.scala 244:75] + wire _T_364 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 247:40] + wire [2:0] _T_439 = bypass_en ? _T_93 : _T_231; // @[axi4_to_ahb.scala 248:30] + wire _GEN_7 = _T_281 & ahb_hresp_q; // @[Conditional.scala 39:67] + wire _GEN_8 = _T_281 ? buf_state_en : _T_440; // @[Conditional.scala 39:67] + wire _GEN_10 = _T_281 & _T_301; // @[Conditional.scala 39:67] + wire _GEN_31 = _T_188 ? 1'h0 : _GEN_10; // @[Conditional.scala 39:67] + wire _GEN_48 = _T_186 ? 1'h0 : _GEN_31; // @[Conditional.scala 39:67] + wire _GEN_65 = _T_175 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67] + wire _GEN_68 = _T_136 ? _T_152 : _GEN_65; // @[Conditional.scala 39:67] + wire _GEN_88 = _T_101 ? master_ready : _GEN_68; // @[Conditional.scala 39:67] + wire buf_wr_en = _T_49 ? buf_state_en : _GEN_88; // @[Conditional.scala 40:58] + wire _GEN_11 = _T_281 & buf_wr_en; // @[Conditional.scala 39:67] + wire [1:0] _GEN_14 = _T_281 ? _T_357 : 2'h0; // @[Conditional.scala 39:67] + wire _GEN_17 = _T_281 & _T_364; // @[Conditional.scala 39:67] + wire [2:0] _GEN_18 = _T_281 ? _T_439 : 3'h0; // @[Conditional.scala 39:67] + wire _GEN_22 = _T_188 ? buf_state_en : _GEN_17; // @[Conditional.scala 39:67] + wire _GEN_23 = _T_188 & buf_state_en; // @[Conditional.scala 39:67] + wire [2:0] _GEN_24 = _T_188 ? _T_231 : _GEN_18; // @[Conditional.scala 39:67] + wire [1:0] _GEN_26 = _T_188 ? _T_280 : _GEN_14; // @[Conditional.scala 39:67] + wire _GEN_29 = _T_188 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67] + wire _GEN_32 = _T_188 ? 1'h0 : _GEN_11; // @[Conditional.scala 39:67] + wire _GEN_37 = _T_186 ? buf_state_en : _GEN_32; // @[Conditional.scala 39:67] + wire _GEN_39 = _T_186 ? buf_state_en : _GEN_29; // @[Conditional.scala 39:67] + wire _GEN_40 = _T_186 ? buf_state_en : _GEN_23; // @[Conditional.scala 39:67] + wire _GEN_42 = _T_186 ? 1'h0 : _GEN_22; // @[Conditional.scala 39:67] + wire [2:0] _GEN_43 = _T_186 ? 3'h0 : _GEN_24; // @[Conditional.scala 39:67] + wire [1:0] _GEN_45 = _T_186 ? 2'h0 : _GEN_26; // @[Conditional.scala 39:67] + wire _GEN_54 = _T_175 ? buf_state_en : _GEN_40; // @[Conditional.scala 39:67] + wire [2:0] _GEN_55 = _T_175 ? buf_addr[2:0] : _GEN_43; // @[Conditional.scala 39:67] + wire [1:0] _GEN_56 = _T_175 ? _T_185 : _GEN_45; // @[Conditional.scala 39:67] + wire _GEN_57 = _T_175 ? 1'h0 : _GEN_37; // @[Conditional.scala 39:67] + wire _GEN_59 = _T_175 ? 1'h0 : _GEN_39; // @[Conditional.scala 39:67] + wire _GEN_61 = _T_175 ? 1'h0 : _GEN_42; // @[Conditional.scala 39:67] + wire _GEN_71 = _T_136 ? buf_state_en : _GEN_57; // @[Conditional.scala 39:67] + wire _GEN_73 = _T_136 ? buf_state_en : _GEN_59; // @[Conditional.scala 39:67] + wire [2:0] _GEN_77 = _T_136 ? _T_130 : _GEN_55; // @[Conditional.scala 39:67] + wire [1:0] _GEN_78 = _T_136 ? _T_174 : _GEN_56; // @[Conditional.scala 39:67] + wire _GEN_79 = _T_136 ? buf_wr_en : _GEN_54; // @[Conditional.scala 39:67] + wire _GEN_81 = _T_136 ? 1'h0 : _GEN_61; // @[Conditional.scala 39:67] + wire _GEN_86 = _T_101 ? buf_state_en : _GEN_79; // @[Conditional.scala 39:67] + wire [2:0] _GEN_90 = _T_101 ? _T_130 : _GEN_77; // @[Conditional.scala 39:67] + wire [1:0] _GEN_91 = _T_101 ? _T_135 : _GEN_78; // @[Conditional.scala 39:67] + wire _GEN_92 = _T_101 ? 1'h0 : _GEN_71; // @[Conditional.scala 39:67] + wire _GEN_94 = _T_101 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67] + wire _GEN_97 = _T_101 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] + wire buf_data_wr_en = _T_49 ? _T_56 : _GEN_92; // @[Conditional.scala 40:58] + wire buf_cmd_byte_ptr_en = _T_49 ? buf_state_en : _GEN_97; // @[Conditional.scala 40:58] + wire [2:0] buf_cmd_byte_ptr = _T_49 ? _T_95 : _GEN_90; // @[Conditional.scala 40:58] + wire slvbuf_wr_en = _T_49 ? 1'h0 : _GEN_86; // @[Conditional.scala 40:58] + wire slvbuf_error_en = _T_49 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58] + wire _T_535 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 265:24] + wire _T_536 = _T_103 | _T_535; // @[axi4_to_ahb.scala 264:48] + wire _T_538 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 265:54] + wire _T_539 = _T_536 | _T_538; // @[axi4_to_ahb.scala 265:33] + wire _T_541 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 265:93] + wire _T_542 = _T_539 | _T_541; // @[axi4_to_ahb.scala 265:72] + wire _T_544 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 266:25] + wire _T_546 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 266:62] + wire _T_548 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 266:97] + wire _T_549 = _T_546 | _T_548; // @[axi4_to_ahb.scala 266:74] + wire _T_551 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 266:132] + wire _T_552 = _T_549 | _T_551; // @[axi4_to_ahb.scala 266:109] + wire _T_554 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 266:168] + wire _T_555 = _T_552 | _T_554; // @[axi4_to_ahb.scala 266:145] + wire _T_557 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 267:28] + wire _T_558 = _T_555 | _T_557; // @[axi4_to_ahb.scala 266:181] + wire _T_560 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 267:63] + wire _T_561 = _T_558 | _T_560; // @[axi4_to_ahb.scala 267:40] + wire _T_563 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 267:99] + wire _T_564 = _T_561 | _T_563; // @[axi4_to_ahb.scala 267:76] + wire _T_565 = _T_544 & _T_564; // @[axi4_to_ahb.scala 266:38] + wire buf_aligned_in = _T_542 | _T_565; // @[axi4_to_ahb.scala 265:106] + wire _T_444 = buf_aligned_in & _T_51; // @[axi4_to_ahb.scala 259:62] + wire [2:0] _T_461 = _T_548 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_462 = 3'h2 & _T_461; // @[axi4_to_ahb.scala 128:15] + wire _T_468 = _T_560 | _T_546; // @[axi4_to_ahb.scala 129:56] + wire [2:0] _T_470 = _T_468 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_471 = 3'h4 & _T_470; // @[axi4_to_ahb.scala 129:15] + wire [2:0] _T_472 = _T_462 | _T_471; // @[axi4_to_ahb.scala 128:63] + wire [2:0] _T_476 = _T_554 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_477 = 3'h6 & _T_476; // @[axi4_to_ahb.scala 130:15] + wire [2:0] _T_478 = _T_472 | _T_477; // @[axi4_to_ahb.scala 129:96] + wire [2:0] _T_485 = _T_444 ? _T_478 : master_addr[2:0]; // @[axi4_to_ahb.scala 259:45] + wire [31:0] buf_addr_in = {master_addr[31:3],_T_485}; // @[Cat.scala 29:58] + wire _T_489 = buf_state == 3'h3; // @[axi4_to_ahb.scala 262:33] + wire _T_495 = buf_aligned_in & _T_544; // @[axi4_to_ahb.scala 263:38] + wire _T_498 = _T_495 & _T_51; // @[axi4_to_ahb.scala 263:72] + wire [1:0] _T_504 = _T_563 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire _T_510 = _T_560 | _T_557; // @[axi4_to_ahb.scala 121:55] + wire [1:0] _T_512 = _T_510 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_513 = 2'h2 & _T_512; // @[axi4_to_ahb.scala 121:16] + wire [1:0] _T_514 = _T_504 | _T_513; // @[axi4_to_ahb.scala 120:64] + wire _T_519 = _T_554 | _T_551; // @[axi4_to_ahb.scala 122:60] + wire _T_522 = _T_519 | _T_548; // @[axi4_to_ahb.scala 122:89] + wire _T_525 = _T_522 | _T_546; // @[axi4_to_ahb.scala 122:123] + wire [1:0] _T_527 = _T_525 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_528 = 2'h1 & _T_527; // @[axi4_to_ahb.scala 122:21] + wire [1:0] _T_529 = _T_514 | _T_528; // @[axi4_to_ahb.scala 121:93] + wire [1:0] _T_531 = _T_498 ? _T_529 : master_size[1:0]; // @[axi4_to_ahb.scala 263:21] + wire [28:0] _T_570 = bypass_en ? master_addr[31:3] : buf_addr[31:3]; // @[axi4_to_ahb.scala 269:30] + wire _T_571 = io_ahb_out_htrans == 2'h2; // @[axi4_to_ahb.scala 269:115] + wire [2:0] _T_573 = _T_571 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_574 = _T_573 & buf_cmd_byte_ptr; // @[axi4_to_ahb.scala 269:124] + wire [1:0] _T_578 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [2:0] buf_size_in = {{1'd0}, _T_531}; // @[axi4_to_ahb.scala 263:15] + wire [1:0] _T_580 = _T_578 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 270:81] + wire [2:0] _T_581 = {1'h0,_T_580}; // @[Cat.scala 29:58] + wire [1:0] _T_583 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] reg [1:0] buf_size; // @[Reg.scala 27:20] - wire [1:0] _T_583 = _T_581 & buf_size; // @[axi4_to_ahb.scala 270:138] - wire [2:0] _T_584 = {1'h0,_T_583}; // @[Cat.scala 29:58] - wire _T_587 = ~io_axi_ar_bits_prot[2]; // @[axi4_to_ahb.scala 274:37] - wire [1:0] _T_588 = {1'h1,_T_587}; // @[Cat.scala 29:58] + wire [1:0] _T_585 = _T_583 & buf_size; // @[axi4_to_ahb.scala 270:138] + wire [2:0] _T_586 = {1'h0,_T_585}; // @[Cat.scala 29:58] + wire _T_589 = ~io_axi_ar_bits_prot[2]; // @[axi4_to_ahb.scala 274:37] + wire [1:0] _T_590 = {1'h1,_T_589}; // @[Cat.scala 29:58] reg buf_write; // @[Reg.scala 27:20] - wire _T_610 = io_ahb_out_htrans != 2'h0; // @[axi4_to_ahb.scala 283:44] - wire _T_611 = _T_610 & io_ahb_in_hready; // @[axi4_to_ahb.scala 283:56] - wire last_addr_en = _T_611 & io_ahb_out_hwrite; // @[axi4_to_ahb.scala 283:75] - wire _T_613 = io_axi_aw_valid & io_axi_aw_ready; // @[axi4_to_ahb.scala 285:31] - wire wrbuf_en = _T_613 & master_ready; // @[axi4_to_ahb.scala 285:49] - wire _T_615 = io_axi_w_valid & io_axi_w_ready; // @[axi4_to_ahb.scala 286:35] - wire wrbuf_data_en = _T_615 & master_ready; // @[axi4_to_ahb.scala 286:52] - wire wrbuf_cmd_sent = _T_147 & _T_49; // @[axi4_to_ahb.scala 287:49] - wire _T_621 = ~wrbuf_en; // @[axi4_to_ahb.scala 288:34] - wire _T_622 = wrbuf_cmd_sent & _T_621; // @[axi4_to_ahb.scala 288:32] - wire wrbuf_rst = _T_622 | dec_tlu_force_halt_bus; // @[axi4_to_ahb.scala 288:45] - wire _T_624 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 290:36] - wire _T_625 = wrbuf_vld & _T_624; // @[axi4_to_ahb.scala 290:34] - wire _T_626 = ~_T_625; // @[axi4_to_ahb.scala 290:22] - wire _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 291:38] - wire _T_630 = ~_T_629; // @[axi4_to_ahb.scala 291:21] - wire _T_633 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 292:22] - wire _T_637 = ~wrbuf_rst; // @[lib.scala 391:75] - wire _T_639 = wrbuf_en | wrbuf_rst; // @[lib.scala 391:95] - wire _T_640 = _T_639 & io_bus_clk_en; // @[lib.scala 391:102] - wire _T_647 = wrbuf_data_en | wrbuf_rst; // @[lib.scala 391:95] - wire _T_648 = _T_647 & io_bus_clk_en; // @[lib.scala 391:102] - wire _T_653 = io_bus_clk_en & wrbuf_en; // @[lib.scala 383:57] - wire _T_660 = wrbuf_en & io_bus_clk_en; // @[axi4_to_ahb.scala 299:61] - wire _T_663 = wrbuf_data_en & io_bus_clk_en; // @[axi4_to_ahb.scala 300:65] - wire _T_667 = io_bus_clk_en & wrbuf_data_en; // @[lib.scala 383:57] - wire _T_671 = io_bus_clk_en & last_addr_en; // @[lib.scala 383:57] - wire _T_728 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 320:51] - wire _T_729 = _T_728 | io_clk_override; // @[axi4_to_ahb.scala 320:66] - wire buf_clken = io_bus_clk_en & _T_729; // @[axi4_to_ahb.scala 320:38] - wire _T_674 = buf_clken & buf_wr_en; // @[lib.scala 383:57] + wire _T_612 = io_ahb_out_htrans != 2'h0; // @[axi4_to_ahb.scala 283:44] + wire _T_613 = _T_612 & io_ahb_in_hready; // @[axi4_to_ahb.scala 283:56] + wire last_addr_en = _T_613 & io_ahb_out_hwrite; // @[axi4_to_ahb.scala 283:75] + wire _T_615 = io_axi_aw_valid & io_axi_aw_ready; // @[axi4_to_ahb.scala 285:31] + wire wrbuf_en = _T_615 & master_ready; // @[axi4_to_ahb.scala 285:49] + wire _T_617 = io_axi_w_valid & io_axi_w_ready; // @[axi4_to_ahb.scala 286:35] + wire wrbuf_data_en = _T_617 & master_ready; // @[axi4_to_ahb.scala 286:52] + wire wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 287:49] + wire _T_623 = ~wrbuf_en; // @[axi4_to_ahb.scala 288:34] + wire _T_624 = wrbuf_cmd_sent & _T_623; // @[axi4_to_ahb.scala 288:32] + wire wrbuf_rst = _T_624 | dec_tlu_force_halt_bus; // @[axi4_to_ahb.scala 288:45] + wire _T_626 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 290:36] + wire _T_627 = wrbuf_vld & _T_626; // @[axi4_to_ahb.scala 290:34] + wire _T_628 = ~_T_627; // @[axi4_to_ahb.scala 290:22] + wire _T_631 = wrbuf_data_vld & _T_626; // @[axi4_to_ahb.scala 291:38] + wire _T_632 = ~_T_631; // @[axi4_to_ahb.scala 291:21] + wire _T_635 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 292:22] + wire _T_639 = ~wrbuf_rst; // @[lib.scala 391:73] + wire _T_641 = wrbuf_en | wrbuf_rst; // @[lib.scala 391:92] + wire _T_642 = _T_641 & io_bus_clk_en; // @[lib.scala 391:99] + wire _T_649 = wrbuf_data_en | wrbuf_rst; // @[lib.scala 391:92] + wire _T_650 = _T_649 & io_bus_clk_en; // @[lib.scala 391:99] + wire _T_655 = io_bus_clk_en & wrbuf_en; // @[lib.scala 383:57] + wire _T_662 = wrbuf_en & io_bus_clk_en; // @[axi4_to_ahb.scala 299:61] + wire _T_665 = wrbuf_data_en & io_bus_clk_en; // @[axi4_to_ahb.scala 300:65] + wire _T_669 = io_bus_clk_en & wrbuf_data_en; // @[lib.scala 383:57] + wire _T_673 = io_bus_clk_en & last_addr_en; // @[lib.scala 383:57] + wire _T_730 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 320:51] + wire _T_731 = _T_730 | io_clk_override; // @[axi4_to_ahb.scala 320:66] + wire buf_clken = io_bus_clk_en & _T_731; // @[axi4_to_ahb.scala 320:38] + wire _T_676 = buf_clken & buf_wr_en; // @[lib.scala 383:57] reg buf_tag; // @[Reg.scala 27:20] - wire _T_681 = buf_wr_en & io_bus_clk_en; // @[axi4_to_ahb.scala 305:62] - wire _T_696 = buf_data_wr_en & io_bus_clk_en; // @[axi4_to_ahb.scala 309:67] - wire _T_700 = buf_clken & slvbuf_wr_en; // @[lib.scala 383:57] - wire _T_707 = io_bus_clk_en & slvbuf_error_en; // @[lib.scala 383:57] - wire _T_711 = ~slave_valid_pre; // @[lib.scala 391:75] - wire _T_713 = cmd_done | slave_valid_pre; // @[lib.scala 391:95] - wire _T_714 = _T_713 & io_bus_clk_en; // @[lib.scala 391:102] - wire _T_719 = io_bus_clk_en & buf_cmd_byte_ptr_en; // @[lib.scala 383:57] - wire _T_731 = buf_state != 3'h0; // @[axi4_to_ahb.scala 321:52] - wire _T_732 = _T_731 | io_clk_override; // @[axi4_to_ahb.scala 321:62] - wire ahbm_data_clken = io_bus_clk_en & _T_732; // @[axi4_to_ahb.scala 321:38] + wire _T_683 = buf_wr_en & io_bus_clk_en; // @[axi4_to_ahb.scala 305:62] + wire _T_698 = buf_data_wr_en & io_bus_clk_en; // @[axi4_to_ahb.scala 309:67] + wire _T_702 = buf_clken & slvbuf_wr_en; // @[lib.scala 383:57] + wire _T_709 = io_bus_clk_en & slvbuf_error_en; // @[lib.scala 383:57] + wire _T_713 = ~slave_valid_pre; // @[lib.scala 391:73] + wire _T_715 = cmd_done | slave_valid_pre; // @[lib.scala 391:92] + wire _T_716 = _T_715 & io_bus_clk_en; // @[lib.scala 391:99] + wire _T_721 = io_bus_clk_en & buf_cmd_byte_ptr_en; // @[lib.scala 383:57] + wire _T_733 = buf_state != 3'h0; // @[axi4_to_ahb.scala 321:52] + wire _T_734 = _T_733 | io_clk_override; // @[axi4_to_ahb.scala 321:62] + wire ahbm_data_clken = io_bus_clk_en & _T_734; // @[axi4_to_ahb.scala 321:38] rvclkhdr rvclkhdr ( // @[lib.scala 399:23] .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en) @@ -506,24 +506,24 @@ module axi4_to_ahb( .io_clk(rvclkhdr_3_io_clk), .io_en(rvclkhdr_3_io_en) ); - assign io_axi_aw_ready = _T_626 & master_ready; // @[axi4_to_ahb.scala 290:19] - assign io_axi_w_ready = _T_630 & master_ready; // @[axi4_to_ahb.scala 291:18] - assign io_axi_b_valid = _T_28 & slave_opc[3]; // @[axi4_to_ahb.scala 150:18] - assign io_axi_b_bits_resp = slave_opc[0] ? 2'h2 : _T_33; // @[axi4_to_ahb.scala 151:22] + assign io_axi_aw_ready = _T_628 & master_ready; // @[axi4_to_ahb.scala 290:19] + assign io_axi_w_ready = _T_632 & master_ready; // @[axi4_to_ahb.scala 291:18] + assign io_axi_b_valid = _T_30 & slave_opc[3]; // @[axi4_to_ahb.scala 150:18] + assign io_axi_b_bits_resp = slave_opc[0] ? 2'h2 : _T_35; // @[axi4_to_ahb.scala 151:22] assign io_axi_b_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 152:20] - assign io_axi_ar_ready = _T_633 & master_ready; // @[axi4_to_ahb.scala 292:19] - assign io_axi_r_valid = _T_28 & _T_38; // @[axi4_to_ahb.scala 154:18] + assign io_axi_ar_ready = _T_635 & master_ready; // @[axi4_to_ahb.scala 292:19] + assign io_axi_r_valid = _T_30 & _T_40; // @[axi4_to_ahb.scala 154:18] assign io_axi_r_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 156:20] - assign io_axi_r_bits_data = slvbuf_error ? _T_602 : _T_606; // @[axi4_to_ahb.scala 157:22] - assign io_axi_r_bits_resp = slave_opc[0] ? 2'h2 : _T_33; // @[axi4_to_ahb.scala 155:22] + assign io_axi_r_bits_data = slvbuf_error ? _T_604 : _T_608; // @[axi4_to_ahb.scala 157:22] + assign io_axi_r_bits_resp = slave_opc[0] ? 2'h2 : _T_35; // @[axi4_to_ahb.scala 155:22] assign io_axi_r_bits_last = 1'h1; // @[axi4_to_ahb.scala 293:22] - assign io_ahb_out_haddr = {_T_568,_T_572}; // @[axi4_to_ahb.scala 269:20] + assign io_ahb_out_haddr = {_T_570,_T_574}; // @[axi4_to_ahb.scala 269:20] assign io_ahb_out_hburst = 3'h0; // @[axi4_to_ahb.scala 272:21] assign io_ahb_out_hmastlock = 1'h0; // @[axi4_to_ahb.scala 273:24] - assign io_ahb_out_hprot = {{2'd0}, _T_588}; // @[axi4_to_ahb.scala 274:20] - assign io_ahb_out_hsize = bypass_en ? _T_579 : _T_584; // @[axi4_to_ahb.scala 270:20] - assign io_ahb_out_htrans = _T_47 ? _T_98 : _GEN_91; // @[axi4_to_ahb.scala 29:21 axi4_to_ahb.scala 172:25 axi4_to_ahb.scala 184:25 axi4_to_ahb.scala 199:25 axi4_to_ahb.scala 209:25 axi4_to_ahb.scala 229:25 axi4_to_ahb.scala 244:25] - assign io_ahb_out_hwrite = bypass_en ? _T_49 : buf_write; // @[axi4_to_ahb.scala 275:21] + assign io_ahb_out_hprot = {{2'd0}, _T_590}; // @[axi4_to_ahb.scala 274:20] + assign io_ahb_out_hsize = bypass_en ? _T_581 : _T_586; // @[axi4_to_ahb.scala 270:20] + assign io_ahb_out_htrans = _T_49 ? _T_100 : _GEN_91; // @[axi4_to_ahb.scala 29:21 axi4_to_ahb.scala 172:25 axi4_to_ahb.scala 184:25 axi4_to_ahb.scala 199:25 axi4_to_ahb.scala 209:25 axi4_to_ahb.scala 229:25 axi4_to_ahb.scala 244:25] + assign io_ahb_out_hwrite = bypass_en ? _T_51 : buf_write; // @[axi4_to_ahb.scala 275:21] assign io_ahb_out_hwdata = buf_data; // @[axi4_to_ahb.scala 276:21] assign rvclkhdr_io_clk = clock; // @[lib.scala 401:18] assign rvclkhdr_io_en = wrbuf_en & io_bus_clk_en; // @[lib.scala 402:17] @@ -720,22 +720,22 @@ end // initial always @(posedge clock or posedge reset) begin if (reset) begin buf_state <= 3'h0; - end else if (_T_7) begin - buf_state <= _T_5; + end else if (_T_9) begin + buf_state <= _T_7; end end always @(posedge clock or posedge reset) begin if (reset) begin wrbuf_vld <= 1'h0; - end else if (_T_640) begin - wrbuf_vld <= _T_637; + end else if (_T_642) begin + wrbuf_vld <= _T_639; end end always @(posedge clock or posedge reset) begin if (reset) begin wrbuf_data_vld <= 1'h0; - end else if (_T_648) begin - wrbuf_data_vld <= _T_637; + end else if (_T_650) begin + wrbuf_data_vld <= _T_639; end end always @(posedge clock or posedge reset) begin @@ -769,67 +769,67 @@ end // initial always @(posedge clock or posedge reset) begin if (reset) begin cmd_doneQ <= 1'h0; - end else if (_T_714) begin - cmd_doneQ <= _T_711; + end else if (_T_716) begin + cmd_doneQ <= _T_713; end end always @(posedge clock or posedge reset) begin if (reset) begin wrbuf_tag <= 1'h0; - end else if (_T_653) begin + end else if (_T_655) begin wrbuf_tag <= io_axi_aw_bits_id; end end always @(posedge clock or posedge reset) begin if (reset) begin wrbuf_addr <= 32'h0; - end else if (_T_660) begin + end else if (_T_662) begin wrbuf_addr <= io_axi_aw_bits_addr; end end always @(posedge clock or posedge reset) begin if (reset) begin wrbuf_size <= 3'h0; - end else if (_T_653) begin + end else if (_T_655) begin wrbuf_size <= io_axi_aw_bits_size; end end always @(posedge clock or posedge reset) begin if (reset) begin wrbuf_byteen <= 8'h0; - end else if (_T_667) begin + end else if (_T_669) begin wrbuf_byteen <= io_axi_w_bits_strb; end end always @(posedge clock or posedge reset) begin if (reset) begin wrbuf_data <= 64'h0; - end else if (_T_663) begin + end else if (_T_665) begin wrbuf_data <= io_axi_w_bits_data; end end always @(posedge clock or posedge reset) begin if (reset) begin slvbuf_write <= 1'h0; - end else if (_T_700) begin + end else if (_T_702) begin slvbuf_write <= buf_write; end end always @(posedge clock or posedge reset) begin if (reset) begin slvbuf_error <= 1'h0; - end else if (_T_707) begin - if (_T_47) begin + end else if (_T_709) begin + if (_T_49) begin slvbuf_error <= 1'h0; - end else if (_T_99) begin + end else if (_T_101) begin slvbuf_error <= 1'h0; - end else if (_T_134) begin + end else if (_T_136) begin slvbuf_error <= ahb_hresp_q; - end else if (_T_173) begin + end else if (_T_175) begin slvbuf_error <= 1'h0; - end else if (_T_184) begin - slvbuf_error <= ahb_hresp_q; end else if (_T_186) begin + slvbuf_error <= ahb_hresp_q; + end else if (_T_188) begin slvbuf_error <= 1'h0; end else begin slvbuf_error <= _GEN_7; @@ -839,22 +839,22 @@ end // initial always @(posedge clock or posedge reset) begin if (reset) begin slvbuf_tag <= 1'h0; - end else if (_T_700) begin + end else if (_T_702) begin slvbuf_tag <= buf_tag; end end always @(posedge clock or posedge reset) begin if (reset) begin last_bus_addr <= 32'h0; - end else if (_T_671) begin + end else if (_T_673) begin last_bus_addr <= io_ahb_out_haddr; end end always @(posedge clock or posedge reset) begin if (reset) begin buf_data <= 64'h0; - end else if (_T_696) begin - if (_T_487) begin + end else if (_T_698) begin + if (_T_489) begin buf_data <= ahb_hrdata_q; end else begin buf_data <= wrbuf_data; @@ -871,15 +871,15 @@ end // initial always @(posedge clock or posedge reset) begin if (reset) begin buf_addr <= 32'h0; - end else if (_T_681) begin + end else if (_T_683) begin buf_addr <= buf_addr_in; end end always @(posedge clock or posedge reset) begin if (reset) begin buf_cmd_byte_ptrQ <= 3'h0; - end else if (_T_719) begin - if (_T_47) begin + end else if (_T_721) begin + if (_T_49) begin if (buf_write_in) begin if (wrbuf_byteen[0]) begin buf_cmd_byte_ptrQ <= 3'h0; @@ -901,43 +901,43 @@ end // initial end else begin buf_cmd_byte_ptrQ <= master_addr[2:0]; end - end else if (_T_99) begin + end else if (_T_101) begin if (bypass_en) begin buf_cmd_byte_ptrQ <= master_addr[2:0]; end else begin buf_cmd_byte_ptrQ <= buf_addr[2:0]; end - end else if (_T_134) begin + end else if (_T_136) begin if (bypass_en) begin buf_cmd_byte_ptrQ <= master_addr[2:0]; end else begin buf_cmd_byte_ptrQ <= buf_addr[2:0]; end - end else if (_T_173) begin + end else if (_T_175) begin buf_cmd_byte_ptrQ <= buf_addr[2:0]; - end else if (_T_184) begin - buf_cmd_byte_ptrQ <= 3'h0; end else if (_T_186) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (_T_188) begin if (trxn_done) begin - if (_T_199) begin + if (_T_201) begin buf_cmd_byte_ptrQ <= 3'h0; - end else if (_T_202) begin + end else if (_T_204) begin buf_cmd_byte_ptrQ <= 3'h1; - end else if (_T_205) begin + end else if (_T_207) begin buf_cmd_byte_ptrQ <= 3'h2; - end else if (_T_208) begin + end else if (_T_210) begin buf_cmd_byte_ptrQ <= 3'h3; - end else if (_T_211) begin + end else if (_T_213) begin buf_cmd_byte_ptrQ <= 3'h4; - end else if (_T_214) begin + end else if (_T_216) begin buf_cmd_byte_ptrQ <= 3'h5; - end else if (_T_217) begin + end else if (_T_219) begin buf_cmd_byte_ptrQ <= 3'h6; end else begin buf_cmd_byte_ptrQ <= 3'h7; end end - end else if (_T_279) begin + end else if (_T_281) begin if (bypass_en) begin if (wrbuf_byteen[0]) begin buf_cmd_byte_ptrQ <= 3'h0; @@ -957,19 +957,19 @@ end // initial buf_cmd_byte_ptrQ <= 3'h7; end end else if (trxn_done) begin - if (_T_199) begin + if (_T_201) begin buf_cmd_byte_ptrQ <= 3'h0; - end else if (_T_202) begin + end else if (_T_204) begin buf_cmd_byte_ptrQ <= 3'h1; - end else if (_T_205) begin + end else if (_T_207) begin buf_cmd_byte_ptrQ <= 3'h2; - end else if (_T_208) begin + end else if (_T_210) begin buf_cmd_byte_ptrQ <= 3'h3; - end else if (_T_211) begin + end else if (_T_213) begin buf_cmd_byte_ptrQ <= 3'h4; - end else if (_T_214) begin + end else if (_T_216) begin buf_cmd_byte_ptrQ <= 3'h5; - end else if (_T_217) begin + end else if (_T_219) begin buf_cmd_byte_ptrQ <= 3'h6; end else begin buf_cmd_byte_ptrQ <= 3'h7; @@ -983,40 +983,40 @@ end // initial always @(posedge clock or posedge reset) begin if (reset) begin buf_byteen <= 8'h0; - end else if (_T_674) begin + end else if (_T_676) begin buf_byteen <= wrbuf_byteen; end end always @(posedge clock or posedge reset) begin if (reset) begin buf_aligned <= 1'h0; - end else if (_T_674) begin + end else if (_T_676) begin buf_aligned <= buf_aligned_in; end end always @(posedge clock or posedge reset) begin if (reset) begin buf_size <= 2'h0; - end else if (_T_674) begin + end else if (_T_676) begin buf_size <= buf_size_in[1:0]; end end always @(posedge clock or posedge reset) begin if (reset) begin buf_write <= 1'h0; - end else if (_T_674) begin - if (_T_47) begin - buf_write <= _T_49; - end else if (_T_99) begin + end else if (_T_676) begin + if (_T_49) begin + buf_write <= _T_51; + end else if (_T_101) begin buf_write <= 1'h0; - end else if (_T_134) begin + end else if (_T_136) begin buf_write <= 1'h0; - end else if (_T_173) begin - buf_write <= 1'h0; - end else if (_T_184) begin + end else if (_T_175) begin buf_write <= 1'h0; end else if (_T_186) begin buf_write <= 1'h0; + end else if (_T_188) begin + buf_write <= 1'h0; end else begin buf_write <= _GEN_9; end @@ -1025,7 +1025,7 @@ end // initial always @(posedge clock or posedge reset) begin if (reset) begin buf_tag <= 1'h0; - end else if (_T_674) begin + end else if (_T_676) begin if (wr_cmd_vld) begin buf_tag <= wrbuf_tag; end else begin diff --git a/src/main/scala/lib/lib.scala b/src/main/scala/lib/lib.scala index 5876978c..8e5c4a42 100644 --- a/src/main/scala/lib/lib.scala +++ b/src/main/scala/lib/lib.scala @@ -388,7 +388,7 @@ trait lib extends param{ def apply(din: UInt, en:Bool,clear: UInt, clk: Clock, clken: Bool,rawclk:Clock):UInt = { val dout =Wire(UInt()) if (RV_FPGA_OPTIMIZE) - dout := withClock (rawclk) {RegEnable ((din & Fill(clear.getWidth,!clear)) , 0.U, ((en|clear)& clken))} + dout := withClock (rawclk) {RegEnable ((din & Fill(din.getWidth,!clear)), 0.U, ((en|clear)& clken))} else dout := withClock(clk) {RegNext (Mux(en,din,dout) & !clear, 0.U)} dout } diff --git a/target/scala-2.12/classes/lib/lib$rvdffsc_fpga$.class b/target/scala-2.12/classes/lib/lib$rvdffsc_fpga$.class index e4ac3f5b..7e184dea 100644 Binary files a/target/scala-2.12/classes/lib/lib$rvdffsc_fpga$.class and b/target/scala-2.12/classes/lib/lib$rvdffsc_fpga$.class differ