Hard-coded values

el2_ifu_iccm_mem.fir

@@ -501,89 +501,92 @@ circuit el2_ifu_iccm_mem :
       _T_371 <= redundant_data1_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
     redundant_data[1] <= _T_371 @[el2_ifu_iccm_mem.scala 100:21]
-    reg iccm_rd_addr_lo_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    node _T_372 = bits(io.iccm_rw_addr, 2, 0) @[el2_ifu_iccm_mem.scala 102:60]
+    reg _T_373 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when UInt<1>("h01") : @[Reg.scala 28:19]
-      iccm_rd_addr_lo_q <= io.iccm_rw_addr @[Reg.scala 28:23]
+      _T_373 <= _T_372 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_372 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 103:48]
+    reg iccm_rd_addr_lo_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 102:34]
+    iccm_rd_addr_lo_q <= _T_373 @[el2_ifu_iccm_mem.scala 102:34]
+    node _T_374 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 103:48]
     reg iccm_rd_addr_hi_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 103:34]
-    iccm_rd_addr_hi_q <= _T_372 @[el2_ifu_iccm_mem.scala 103:34]
+    iccm_rd_addr_hi_q <= _T_374 @[el2_ifu_iccm_mem.scala 103:34]
-    node _T_373 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 105:86]
+    node _T_375 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 105:86]
-    node _T_374 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 105:115]
+    node _T_376 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 105:115]
-    node _T_375 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 105:86]
+    node _T_377 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 105:86]
-    node _T_376 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 105:115]
+    node _T_378 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 105:115]
-    node _T_377 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 105:86]
+    node _T_379 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 105:86]
-    node _T_378 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 105:115]
+    node _T_380 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 105:115]
-    node _T_379 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 105:86]
+    node _T_381 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 105:86]
-    node _T_380 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 105:115]
+    node _T_382 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 105:115]
-    node _T_381 = mux(_T_373, _T_374, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_383 = mux(_T_375, _T_376, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_382 = mux(_T_375, _T_376, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_384 = mux(_T_377, _T_378, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_383 = mux(_T_377, _T_378, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_385 = mux(_T_379, _T_380, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_384 = mux(_T_379, _T_380, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_386 = mux(_T_381, _T_382, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_385 = or(_T_381, _T_382) @[Mux.scala 27:72]
+    node _T_387 = or(_T_383, _T_384) @[Mux.scala 27:72]
-    node _T_386 = or(_T_385, _T_383) @[Mux.scala 27:72]
+    node _T_388 = or(_T_387, _T_385) @[Mux.scala 27:72]
-    node _T_387 = or(_T_386, _T_384) @[Mux.scala 27:72]
+    node _T_389 = or(_T_388, _T_386) @[Mux.scala 27:72]
-    wire _T_388 : UInt<32> @[Mux.scala 27:72]
+    wire _T_390 : UInt<32> @[Mux.scala 27:72]
-    _T_388 <= _T_387 @[Mux.scala 27:72]
+    _T_390 <= _T_389 @[Mux.scala 27:72]
-    node _T_389 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 106:59]
+    node _T_391 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 106:59]
-    node _T_390 = eq(_T_389, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 106:77]
+    node _T_392 = eq(_T_391, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 106:77]
-    node _T_391 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
+    node _T_393 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
-    node _T_392 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 106:59]
+    node _T_394 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 106:59]
-    node _T_393 = eq(_T_392, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 106:77]
+    node _T_395 = eq(_T_394, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 106:77]
-    node _T_394 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
+    node _T_396 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
-    node _T_395 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 106:59]
+    node _T_397 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 106:59]
-    node _T_396 = eq(_T_395, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 106:77]
+    node _T_398 = eq(_T_397, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 106:77]
-    node _T_397 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
+    node _T_399 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
-    node _T_398 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 106:59]
+    node _T_400 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 106:59]
-    node _T_399 = eq(_T_398, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 106:77]
+    node _T_401 = eq(_T_400, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 106:77]
-    node _T_400 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
+    node _T_402 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
-    node _T_401 = mux(_T_390, _T_391, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_403 = mux(_T_392, _T_393, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_402 = mux(_T_393, _T_394, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_404 = mux(_T_395, _T_396, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_403 = mux(_T_396, _T_397, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_405 = mux(_T_398, _T_399, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_404 = mux(_T_399, _T_400, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_406 = mux(_T_401, _T_402, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_405 = or(_T_401, _T_402) @[Mux.scala 27:72]
+    node _T_407 = or(_T_403, _T_404) @[Mux.scala 27:72]
-    node _T_406 = or(_T_405, _T_403) @[Mux.scala 27:72]
+    node _T_408 = or(_T_407, _T_405) @[Mux.scala 27:72]
-    node _T_407 = or(_T_406, _T_404) @[Mux.scala 27:72]
+    node _T_409 = or(_T_408, _T_406) @[Mux.scala 27:72]
-    wire _T_408 : UInt<32> @[Mux.scala 27:72]
+    wire _T_410 : UInt<32> @[Mux.scala 27:72]
-    _T_408 <= _T_407 @[Mux.scala 27:72]
+    _T_410 <= _T_409 @[Mux.scala 27:72]
-    node iccm_rd_data_pre = cat(_T_388, _T_408) @[Cat.scala 29:58]
+    node iccm_rd_data_pre = cat(_T_390, _T_410) @[Cat.scala 29:58]
-    node _T_409 = bits(iccm_rd_addr_lo_q, 0, 0) @[el2_ifu_iccm_mem.scala 108:43]
+    node _T_411 = bits(iccm_rd_addr_lo_q, 0, 0) @[el2_ifu_iccm_mem.scala 108:43]
-    node _T_410 = bits(_T_409, 0, 0) @[el2_ifu_iccm_mem.scala 108:53]
+    node _T_412 = bits(_T_411, 0, 0) @[el2_ifu_iccm_mem.scala 108:53]
-    node _T_411 = mux(UInt<1>("h00"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
+    node _T_413 = mux(UInt<1>("h00"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
-    node _T_412 = bits(iccm_rd_data_pre, 63, 16) @[el2_ifu_iccm_mem.scala 108:89]
+    node _T_414 = bits(iccm_rd_data_pre, 63, 16) @[el2_ifu_iccm_mem.scala 108:89]
-    node _T_413 = cat(_T_411, _T_412) @[Cat.scala 29:58]
+    node _T_415 = cat(_T_413, _T_414) @[Cat.scala 29:58]
-    node _T_414 = mux(_T_410, _T_413, iccm_rd_data_pre) @[el2_ifu_iccm_mem.scala 108:25]
+    node _T_416 = mux(_T_412, _T_415, iccm_rd_data_pre) @[el2_ifu_iccm_mem.scala 108:25]
-    io.iccm_rd_data <= _T_414 @[el2_ifu_iccm_mem.scala 108:19]
+    io.iccm_rd_data <= _T_416 @[el2_ifu_iccm_mem.scala 108:19]
-    node _T_415 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 109:85]
+    node _T_417 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 109:85]
-    node _T_416 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 109:85]
+    node _T_418 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 109:85]
-    node _T_417 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 109:85]
+    node _T_419 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 109:85]
-    node _T_418 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 109:85]
+    node _T_420 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 109:85]
-    node _T_419 = mux(_T_415, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_421 = mux(_T_417, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_420 = mux(_T_416, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_422 = mux(_T_418, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_421 = mux(_T_417, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_423 = mux(_T_419, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_422 = mux(_T_418, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_424 = mux(_T_420, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_423 = or(_T_419, _T_420) @[Mux.scala 27:72]
+    node _T_425 = or(_T_421, _T_422) @[Mux.scala 27:72]
-    node _T_424 = or(_T_423, _T_421) @[Mux.scala 27:72]
+    node _T_426 = or(_T_425, _T_423) @[Mux.scala 27:72]
-    node _T_425 = or(_T_424, _T_422) @[Mux.scala 27:72]
+    node _T_427 = or(_T_426, _T_424) @[Mux.scala 27:72]
-    wire _T_426 : UInt<39> @[Mux.scala 27:72]
+    wire _T_428 : UInt<39> @[Mux.scala 27:72]
-    _T_426 <= _T_425 @[Mux.scala 27:72]
+    _T_428 <= _T_427 @[Mux.scala 27:72]
-    node _T_427 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 110:61]
-    node _T_428 = eq(_T_427, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 110:79]
     node _T_429 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 110:61]
-    node _T_430 = eq(_T_429, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 110:79]
+    node _T_430 = eq(_T_429, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 110:79]
     node _T_431 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 110:61]
-    node _T_432 = eq(_T_431, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 110:79]
+    node _T_432 = eq(_T_431, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 110:79]
     node _T_433 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 110:61]
-    node _T_434 = eq(_T_433, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 110:79]
+    node _T_434 = eq(_T_433, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 110:79]
-    node _T_435 = mux(_T_428, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_435 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 110:61]
-    node _T_436 = mux(_T_430, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_436 = eq(_T_435, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 110:79]
-    node _T_437 = mux(_T_432, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_437 = mux(_T_430, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_438 = mux(_T_434, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_438 = mux(_T_432, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_439 = or(_T_435, _T_436) @[Mux.scala 27:72]
+    node _T_439 = mux(_T_434, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_440 = or(_T_439, _T_437) @[Mux.scala 27:72]
+    node _T_440 = mux(_T_436, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_441 = or(_T_440, _T_438) @[Mux.scala 27:72]
+    node _T_441 = or(_T_437, _T_438) @[Mux.scala 27:72]
-    wire _T_442 : UInt<39> @[Mux.scala 27:72]
+    node _T_442 = or(_T_441, _T_439) @[Mux.scala 27:72]
-    _T_442 <= _T_441 @[Mux.scala 27:72]
+    node _T_443 = or(_T_442, _T_440) @[Mux.scala 27:72]
-    node _T_443 = cat(_T_426, _T_442) @[Cat.scala 29:58]
+    wire _T_444 : UInt<39> @[Mux.scala 27:72]
-    io.iccm_rd_data_ecc <= _T_443 @[el2_ifu_iccm_mem.scala 109:23]
+    _T_444 <= _T_443 @[Mux.scala 27:72]
+    node _T_445 = cat(_T_428, _T_444) @[Cat.scala 29:58]
+    io.iccm_rd_data_ecc <= _T_445 @[el2_ifu_iccm_mem.scala 109:23]
     

el2_ifu_iccm_mem.v

@@ -39,6 +39,7 @@ module el2_ifu_iccm_mem(
   reg [31:0] _RAND_20;
   reg [31:0] _RAND_21;
   reg [31:0] _RAND_22;
+  reg [31:0] _RAND_23;
 `endif // RANDOMIZE_REG_INIT
   reg [38:0] _T_85 [0:4095]; // @[el2_ifu_iccm_mem.scala 43:59]
   wire [38:0] _T_85__T_105_data; // @[el2_ifu_iccm_mem.scala 43:59]
@@ -235,46 +236,47 @@ module el2_ifu_iccm_mem(
   wire  redundant_data1_en = _T_356 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 96:121]
   wire  _T_365 = redundant_address_1[0] & _T_1; // @[el2_ifu_iccm_mem.scala 98:104]
   wire  _T_366 = _T_349 | _T_365; // @[el2_ifu_iccm_mem.scala 98:78]
-  reg [14:0] iccm_rd_addr_lo_q; // @[Reg.scala 27:20]
+  reg [2:0] _T_373; // @[Reg.scala 27:20]
+  reg [2:0] iccm_rd_addr_lo_q; // @[el2_ifu_iccm_mem.scala 102:34]
   reg [1:0] iccm_rd_addr_hi_q; // @[el2_ifu_iccm_mem.scala 103:34]
-  wire  _T_373 = iccm_rd_addr_hi_q == 2'h0; // @[el2_ifu_iccm_mem.scala 105:86]
+  wire  _T_375 = iccm_rd_addr_hi_q == 2'h0; // @[el2_ifu_iccm_mem.scala 105:86]
-  wire  _T_375 = iccm_rd_addr_hi_q == 2'h1; // @[el2_ifu_iccm_mem.scala 105:86]
+  wire  _T_377 = iccm_rd_addr_hi_q == 2'h1; // @[el2_ifu_iccm_mem.scala 105:86]
-  wire  _T_377 = iccm_rd_addr_hi_q == 2'h2; // @[el2_ifu_iccm_mem.scala 105:86]
+  wire  _T_379 = iccm_rd_addr_hi_q == 2'h2; // @[el2_ifu_iccm_mem.scala 105:86]
-  wire  _T_379 = iccm_rd_addr_hi_q == 2'h3; // @[el2_ifu_iccm_mem.scala 105:86]
+  wire  _T_381 = iccm_rd_addr_hi_q == 2'h3; // @[el2_ifu_iccm_mem.scala 105:86]
-  wire [31:0] _T_381 = _T_373 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_383 = _T_375 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_382 = _T_375 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_384 = _T_377 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_383 = _T_377 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_385 = _T_379 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_384 = _T_379 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_386 = _T_381 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_385 = _T_381 | _T_382; // @[Mux.scala 27:72]
+  wire [31:0] _T_387 = _T_383 | _T_384; // @[Mux.scala 27:72]
-  wire [31:0] _T_386 = _T_385 | _T_383; // @[Mux.scala 27:72]
+  wire [31:0] _T_388 = _T_387 | _T_385; // @[Mux.scala 27:72]
-  wire [31:0] _T_387 = _T_386 | _T_384; // @[Mux.scala 27:72]
+  wire [31:0] _T_389 = _T_388 | _T_386; // @[Mux.scala 27:72]
-  wire  _T_390 = iccm_rd_addr_lo_q[1:0] == 2'h0; // @[el2_ifu_iccm_mem.scala 106:77]
+  wire  _T_392 = iccm_rd_addr_lo_q[1:0] == 2'h0; // @[el2_ifu_iccm_mem.scala 106:77]
-  wire  _T_393 = iccm_rd_addr_lo_q[1:0] == 2'h1; // @[el2_ifu_iccm_mem.scala 106:77]
+  wire  _T_395 = iccm_rd_addr_lo_q[1:0] == 2'h1; // @[el2_ifu_iccm_mem.scala 106:77]
-  wire  _T_396 = iccm_rd_addr_lo_q[1:0] == 2'h2; // @[el2_ifu_iccm_mem.scala 106:77]
+  wire  _T_398 = iccm_rd_addr_lo_q[1:0] == 2'h2; // @[el2_ifu_iccm_mem.scala 106:77]
-  wire  _T_399 = iccm_rd_addr_lo_q[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 106:77]
+  wire  _T_401 = iccm_rd_addr_lo_q[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 106:77]
-  wire [31:0] _T_401 = _T_390 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_403 = _T_392 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_402 = _T_393 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_404 = _T_395 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_403 = _T_396 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_405 = _T_398 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_404 = _T_399 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_406 = _T_401 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_405 = _T_401 | _T_402; // @[Mux.scala 27:72]
+  wire [31:0] _T_407 = _T_403 | _T_404; // @[Mux.scala 27:72]
-  wire [31:0] _T_406 = _T_405 | _T_403; // @[Mux.scala 27:72]
+  wire [31:0] _T_408 = _T_407 | _T_405; // @[Mux.scala 27:72]
-  wire [31:0] _T_407 = _T_406 | _T_404; // @[Mux.scala 27:72]
+  wire [31:0] _T_409 = _T_408 | _T_406; // @[Mux.scala 27:72]
-  wire [63:0] iccm_rd_data_pre = {_T_387,_T_407}; // @[Cat.scala 29:58]
+  wire [63:0] iccm_rd_data_pre = {_T_389,_T_409}; // @[Cat.scala 29:58]
-  wire [63:0] _T_413 = {16'h0,iccm_rd_data_pre[63:16]}; // @[Cat.scala 29:58]
+  wire [63:0] _T_415 = {16'h0,iccm_rd_data_pre[63:16]}; // @[Cat.scala 29:58]
-  wire [38:0] _T_419 = _T_373 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_421 = _T_375 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72]
-  wire [38:0] _T_420 = _T_375 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_422 = _T_377 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72]
-  wire [38:0] _T_421 = _T_377 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_423 = _T_379 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72]
-  wire [38:0] _T_422 = _T_379 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_424 = _T_381 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72]
-  wire [38:0] _T_423 = _T_419 | _T_420; // @[Mux.scala 27:72]
+  wire [38:0] _T_425 = _T_421 | _T_422; // @[Mux.scala 27:72]
-  wire [38:0] _T_424 = _T_423 | _T_421; // @[Mux.scala 27:72]
+  wire [38:0] _T_426 = _T_425 | _T_423; // @[Mux.scala 27:72]
-  wire [38:0] _T_425 = _T_424 | _T_422; // @[Mux.scala 27:72]
+  wire [38:0] _T_427 = _T_426 | _T_424; // @[Mux.scala 27:72]
-  wire [38:0] _T_435 = _T_390 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_437 = _T_392 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72]
-  wire [38:0] _T_436 = _T_393 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_438 = _T_395 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72]
-  wire [38:0] _T_437 = _T_396 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_439 = _T_398 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72]
-  wire [38:0] _T_438 = _T_399 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_440 = _T_401 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72]
-  wire [38:0] _T_439 = _T_435 | _T_436; // @[Mux.scala 27:72]
+  wire [38:0] _T_441 = _T_437 | _T_438; // @[Mux.scala 27:72]
-  wire [38:0] _T_440 = _T_439 | _T_437; // @[Mux.scala 27:72]
+  wire [38:0] _T_442 = _T_441 | _T_439; // @[Mux.scala 27:72]
-  wire [38:0] _T_441 = _T_440 | _T_438; // @[Mux.scala 27:72]
+  wire [38:0] _T_443 = _T_442 | _T_440; // @[Mux.scala 27:72]
   assign _T_85__T_105_addr = _T_85__T_105_addr_pipe_0;
   assign _T_85__T_105_data = _T_85[_T_85__T_105_addr]; // @[el2_ifu_iccm_mem.scala 43:59]
   assign _T_85__T_101_data = io_iccm_wr_data[38:0];
@@ -299,8 +301,8 @@ module el2_ifu_iccm_mem(
   assign _T_88__T_104_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_83;
   assign _T_88__T_104_mask = 1'h1;
   assign _T_88__T_104_en = iccm_clken_3 & wren_bank_3;
-  assign io_iccm_rd_data = iccm_rd_addr_lo_q[0] ? _T_413 : iccm_rd_data_pre; // @[el2_ifu_iccm_mem.scala 22:19 el2_ifu_iccm_mem.scala 108:19]
+  assign io_iccm_rd_data = iccm_rd_addr_lo_q[0] ? _T_415 : iccm_rd_data_pre; // @[el2_ifu_iccm_mem.scala 22:19 el2_ifu_iccm_mem.scala 108:19]
-  assign io_iccm_rd_data_ecc = {_T_425,_T_441}; // @[el2_ifu_iccm_mem.scala 23:23 el2_ifu_iccm_mem.scala 109:23]
+  assign io_iccm_rd_data_ecc = {_T_427,_T_443}; // @[el2_ifu_iccm_mem.scala 23:23 el2_ifu_iccm_mem.scala 109:23]
 `ifdef RANDOMIZE_GARBAGE_ASSIGN
 `define RANDOMIZE
 `endif
@@ -385,9 +387,11 @@ initial begin
   _RAND_20 = {1{`RANDOM}};
   redundant_lru = _RAND_20[0:0];
   _RAND_21 = {1{`RANDOM}};
-  iccm_rd_addr_lo_q = _RAND_21[14:0];
+  _T_373 = _RAND_21[2:0];
   _RAND_22 = {1{`RANDOM}};
-  iccm_rd_addr_hi_q = _RAND_22[1:0];
+  iccm_rd_addr_lo_q = _RAND_22[2:0];
+  _RAND_23 = {1{`RANDOM}};
+  iccm_rd_addr_hi_q = _RAND_23[1:0];
 `endif // RANDOMIZE_REG_INIT
   `endif // RANDOMIZE
 end // initial
@@ -514,9 +518,14 @@ end // initial
       end
     end
     if (reset) begin
-      iccm_rd_addr_lo_q <= 15'h0;
+      _T_373 <= 3'h0;
     end else begin
-      iccm_rd_addr_lo_q <= io_iccm_rw_addr;
+      _T_373 <= io_iccm_rw_addr[2:0];
+    end
+    if (reset) begin
+      iccm_rd_addr_lo_q <= 3'h0;
+    end else begin
+      iccm_rd_addr_lo_q <= _T_373;
     end
     if (reset) begin
       iccm_rd_addr_hi_q <= 2'h0;

src/main/scala/ifu/el2_ifu_iccm_mem.scala

@@ -99,7 +99,7 @@ class el2_ifu_iccm_mem extends Module with el2_lib {
     io.iccm_wr_data(77,39), io.iccm_wr_data(38,0))
   redundant_data(1) := RegEnable(redundant_data1_in, 0.U, redundant_data1_en.asBool)
 
-  val iccm_rd_addr_lo_q = RegEnable(io.iccm_rw_addr, 0.U, 1.U.asBool)
+  val iccm_rd_addr_lo_q = RegNext(RegEnable(io.iccm_rw_addr(ICCM_BANK_HI-1,0), 0.U, 1.U.asBool), 0.U)
   val iccm_rd_addr_hi_q = RegNext(addr_bank_inc(ICCM_BANK_HI-1,1), 0.U)
 
   val iccm_rd_data_pre = Cat(Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_hi_q===i.U)->iccm_bank_dout_fn(i)(31,0))),