axi to ahb update
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Laraib Khan
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1551
axi4_to_ahb.fir
1551
axi4_to_ahb.fir
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396
axi4_to_ahb.v
396
axi4_to_ahb.v
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@ -132,31 +132,31 @@ module axi4_to_ahb(
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wire rvclkhdr_9_io_clk; // @[el2_lib.scala 483:22]
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wire rvclkhdr_9_io_en; // @[el2_lib.scala 483:22]
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wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 483:22]
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wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 62:22 axi4_to_ahb.scala 466:12]
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reg [2:0] buf_state; // @[axi4_to_ahb.scala 69:12]
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wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 62:22 axi4_to_ahb.scala 464:12]
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reg [2:0] buf_state; // @[axi4_to_ahb.scala 68:45]
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wire _T_47 = 3'h0 == buf_state; // @[Conditional.scala 37:30]
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wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 90:21 axi4_to_ahb.scala 223:11]
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reg wrbuf_vld; // @[axi4_to_ahb.scala 384:48]
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reg wrbuf_data_vld; // @[axi4_to_ahb.scala 385:48]
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wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 200:27]
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wire master_valid = wr_cmd_vld | io_axi_arvalid; // @[axi4_to_ahb.scala 201:30]
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wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 88:21 axi4_to_ahb.scala 221:11]
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reg wrbuf_vld; // @[axi4_to_ahb.scala 382:48]
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reg wrbuf_data_vld; // @[axi4_to_ahb.scala 383:48]
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wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 198:27]
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wire master_valid = wr_cmd_vld | io_axi_arvalid; // @[axi4_to_ahb.scala 199:30]
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wire _T_99 = 3'h1 == buf_state; // @[Conditional.scala 37:30]
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reg ahb_hready_q; // @[axi4_to_ahb.scala 445:12]
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reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 448:12]
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wire _T_106 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 263:58]
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wire _T_107 = ahb_hready_q & _T_106; // @[axi4_to_ahb.scala 263:36]
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wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 63:27 axi4_to_ahb.scala 467:17]
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reg ahb_hwrite_q; // @[axi4_to_ahb.scala 451:12]
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wire _T_108 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 263:72]
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wire _T_109 = _T_107 & _T_108; // @[axi4_to_ahb.scala 263:70]
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reg ahb_hready_q; // @[axi4_to_ahb.scala 443:12]
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reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 446:12]
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wire _T_106 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 261:58]
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wire _T_107 = ahb_hready_q & _T_106; // @[axi4_to_ahb.scala 261:36]
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wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 63:27 axi4_to_ahb.scala 465:17]
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reg ahb_hwrite_q; // @[axi4_to_ahb.scala 449:12]
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wire _T_108 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 261:72]
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wire _T_109 = _T_107 & _T_108; // @[axi4_to_ahb.scala 261:70]
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wire _T_134 = 3'h6 == buf_state; // @[Conditional.scala 37:30]
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reg ahb_hresp_q; // @[axi4_to_ahb.scala 454:12]
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wire _T_154 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 277:37]
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reg ahb_hresp_q; // @[axi4_to_ahb.scala 452:12]
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wire _T_154 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 275:37]
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wire _T_173 = 3'h7 == buf_state; // @[Conditional.scala 37:30]
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wire _T_184 = 3'h3 == buf_state; // @[Conditional.scala 37:30]
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wire _T_186 = 3'h2 == buf_state; // @[Conditional.scala 37:30]
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wire _T_187 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 309:33]
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wire _T_190 = _T_187 & _T_106; // @[axi4_to_ahb.scala 309:48]
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wire _T_187 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 307:33]
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wire _T_190 = _T_187 & _T_106; // @[axi4_to_ahb.scala 307:48]
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wire _T_279 = 3'h4 == buf_state; // @[Conditional.scala 37:30]
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wire _GEN_15 = _T_279 & _T_190; // @[Conditional.scala 39:67]
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wire _GEN_19 = _T_186 ? _T_190 : _GEN_15; // @[Conditional.scala 39:67]
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@ -165,11 +165,11 @@ module axi4_to_ahb(
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wire _GEN_79 = _T_134 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67]
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wire _GEN_95 = _T_99 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67]
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wire trxn_done = _T_47 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58]
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reg cmd_doneQ; // @[axi4_to_ahb.scala 436:12]
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wire _T_280 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 319:34]
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wire _T_281 = _T_280 | ahb_hresp_q; // @[axi4_to_ahb.scala 319:50]
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reg cmd_doneQ; // @[axi4_to_ahb.scala 434:12]
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wire _T_280 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 317:34]
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wire _T_281 = _T_280 | ahb_hresp_q; // @[axi4_to_ahb.scala 317:50]
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wire _T_442 = 3'h5 == buf_state; // @[Conditional.scala 37:30]
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wire slave_ready = io_axi_bready & io_axi_rready; // @[axi4_to_ahb.scala 218:32]
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wire slave_ready = io_axi_bready & io_axi_rready; // @[axi4_to_ahb.scala 216:32]
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wire _GEN_1 = _T_442 & slave_ready; // @[Conditional.scala 39:67]
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wire _GEN_3 = _T_279 ? _T_281 : _GEN_1; // @[Conditional.scala 39:67]
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wire _GEN_20 = _T_186 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67]
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@ -178,9 +178,9 @@ module axi4_to_ahb(
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wire _GEN_69 = _T_134 ? _T_154 : _GEN_51; // @[Conditional.scala 39:67]
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wire _GEN_83 = _T_99 ? _T_109 : _GEN_69; // @[Conditional.scala 39:67]
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wire buf_state_en = _T_47 ? master_valid : _GEN_83; // @[Conditional.scala 40:58]
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wire [1:0] _T_12 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 203:20]
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wire [2:0] master_opc = {{1'd0}, _T_12}; // @[axi4_to_ahb.scala 203:14]
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wire _T_49 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 248:41]
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wire [1:0] _T_12 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 201:20]
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wire [2:0] master_opc = {{1'd0}, _T_12}; // @[axi4_to_ahb.scala 201:14]
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wire _T_49 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 246:41]
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wire _GEN_8 = _T_279 & _T_49; // @[Conditional.scala 39:67]
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wire _GEN_29 = _T_186 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67]
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wire _GEN_46 = _T_184 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67]
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@ -188,19 +188,19 @@ module axi4_to_ahb(
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wire _GEN_81 = _T_134 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67]
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wire _GEN_97 = _T_99 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67]
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wire buf_write_in = _T_47 ? _T_49 : _GEN_97; // @[Conditional.scala 40:58]
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wire [2:0] _T_51 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 249:26]
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wire _T_101 = master_opc == 3'h0; // @[axi4_to_ahb.scala 262:61]
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wire _T_102 = master_valid & _T_101; // @[axi4_to_ahb.scala 262:41]
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wire [2:0] _T_104 = _T_102 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 262:26]
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wire _T_122 = _T_104 == 3'h6; // @[axi4_to_ahb.scala 266:174]
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wire _T_123 = _T_109 & _T_122; // @[axi4_to_ahb.scala 266:88]
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wire _T_135 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 274:39]
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wire _T_136 = ahb_hready_q & _T_135; // @[axi4_to_ahb.scala 274:37]
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wire _T_139 = master_valid & _T_49; // @[axi4_to_ahb.scala 274:70]
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wire _T_140 = ~_T_139; // @[axi4_to_ahb.scala 274:55]
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wire _T_141 = _T_136 & _T_140; // @[axi4_to_ahb.scala 274:53]
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wire _T_285 = _T_281 & _T_135; // @[axi4_to_ahb.scala 320:66]
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wire _T_286 = _T_285 & slave_ready; // @[axi4_to_ahb.scala 320:81]
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wire [2:0] _T_51 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 247:26]
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wire _T_101 = master_opc == 3'h0; // @[axi4_to_ahb.scala 260:61]
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wire _T_102 = master_valid & _T_101; // @[axi4_to_ahb.scala 260:41]
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wire [2:0] _T_104 = _T_102 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 260:26]
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wire _T_122 = _T_104 == 3'h6; // @[axi4_to_ahb.scala 264:174]
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wire _T_123 = _T_109 & _T_122; // @[axi4_to_ahb.scala 264:88]
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wire _T_135 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 272:39]
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wire _T_136 = ahb_hready_q & _T_135; // @[axi4_to_ahb.scala 272:37]
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wire _T_139 = master_valid & _T_49; // @[axi4_to_ahb.scala 272:70]
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wire _T_140 = ~_T_139; // @[axi4_to_ahb.scala 272:55]
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wire _T_141 = _T_136 & _T_140; // @[axi4_to_ahb.scala 272:53]
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wire _T_285 = _T_281 & _T_135; // @[axi4_to_ahb.scala 318:66]
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wire _T_286 = _T_285 & slave_ready; // @[axi4_to_ahb.scala 318:81]
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wire _GEN_4 = _T_279 ? _T_286 : 1'h1; // @[Conditional.scala 39:67]
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wire _GEN_26 = _T_186 | _GEN_4; // @[Conditional.scala 39:67]
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wire _GEN_45 = _T_184 | _GEN_26; // @[Conditional.scala 39:67]
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@ -208,15 +208,15 @@ module axi4_to_ahb(
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wire _GEN_66 = _T_134 ? _T_141 : _GEN_62; // @[Conditional.scala 39:67]
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wire _GEN_86 = _T_99 ? _T_123 : _GEN_66; // @[Conditional.scala 39:67]
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wire master_ready = _T_47 | _GEN_86; // @[Conditional.scala 40:58]
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wire _T_147 = master_valid & master_ready; // @[axi4_to_ahb.scala 276:82]
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wire _T_150 = _T_147 & _T_101; // @[axi4_to_ahb.scala 276:97]
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wire [2:0] _T_152 = _T_150 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 276:67]
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wire [2:0] _T_153 = ahb_hresp_q ? 3'h7 : _T_152; // @[axi4_to_ahb.scala 276:26]
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wire _T_287 = ~slave_ready; // @[axi4_to_ahb.scala 321:42]
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wire _T_288 = ahb_hresp_q | _T_287; // @[axi4_to_ahb.scala 321:40]
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wire [2:0] _T_294 = _T_49 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 321:119]
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wire [2:0] _T_295 = _T_147 ? _T_294 : 3'h0; // @[axi4_to_ahb.scala 321:75]
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wire [2:0] _T_296 = _T_288 ? 3'h5 : _T_295; // @[axi4_to_ahb.scala 321:26]
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wire _T_147 = master_valid & master_ready; // @[axi4_to_ahb.scala 274:82]
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wire _T_150 = _T_147 & _T_101; // @[axi4_to_ahb.scala 274:97]
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wire [2:0] _T_152 = _T_150 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 274:67]
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wire [2:0] _T_153 = ahb_hresp_q ? 3'h7 : _T_152; // @[axi4_to_ahb.scala 274:26]
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wire _T_287 = ~slave_ready; // @[axi4_to_ahb.scala 319:42]
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wire _T_288 = ahb_hresp_q | _T_287; // @[axi4_to_ahb.scala 319:40]
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wire [2:0] _T_294 = _T_49 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 319:119]
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wire [2:0] _T_295 = _T_147 ? _T_294 : 3'h0; // @[axi4_to_ahb.scala 319:75]
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wire [2:0] _T_296 = _T_288 ? 3'h5 : _T_295; // @[axi4_to_ahb.scala 319:26]
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wire [2:0] _GEN_5 = _T_279 ? _T_296 : 3'h0; // @[Conditional.scala 39:67]
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wire [2:0] _GEN_18 = _T_186 ? 3'h4 : _GEN_5; // @[Conditional.scala 39:67]
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wire [2:0] _GEN_34 = _T_184 ? 3'h5 : _GEN_18; // @[Conditional.scala 39:67]
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@ -224,17 +224,17 @@ module axi4_to_ahb(
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wire [2:0] _GEN_68 = _T_134 ? _T_153 : _GEN_50; // @[Conditional.scala 39:67]
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wire [2:0] _GEN_82 = _T_99 ? _T_104 : _GEN_68; // @[Conditional.scala 39:67]
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wire [2:0] buf_nxtstate = _T_47 ? _T_51 : _GEN_82; // @[Conditional.scala 40:58]
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wire [2:0] _T_1 = buf_state_en ? buf_nxtstate : buf_state; // @[axi4_to_ahb.scala 69:16]
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wire [2:0] _T_1 = buf_state_en ? buf_nxtstate : buf_state; // @[axi4_to_ahb.scala 68:49]
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reg wrbuf_tag; // @[Reg.scala 27:20]
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reg [31:0] wrbuf_addr; // @[el2_lib.scala 514:16]
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wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_araddr; // @[axi4_to_ahb.scala 204:21]
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wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_araddr; // @[axi4_to_ahb.scala 202:21]
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reg [2:0] wrbuf_size; // @[Reg.scala 27:20]
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wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_arsize; // @[axi4_to_ahb.scala 205:21]
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wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_arsize; // @[axi4_to_ahb.scala 203:21]
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reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20]
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reg [63:0] wrbuf_data; // @[el2_lib.scala 514:16]
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wire _T_156 = buf_state_en & _T_135; // @[axi4_to_ahb.scala 281:39]
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wire _T_359 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 330:55]
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wire _T_360 = buf_state_en & _T_359; // @[axi4_to_ahb.scala 330:39]
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wire _T_156 = buf_state_en & _T_135; // @[axi4_to_ahb.scala 279:39]
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wire _T_359 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 328:55]
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wire _T_360 = buf_state_en & _T_359; // @[axi4_to_ahb.scala 328:39]
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wire _GEN_14 = _T_279 ? _T_360 : _T_442; // @[Conditional.scala 39:67]
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wire _GEN_33 = _T_186 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67]
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wire _GEN_49 = _T_184 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67]
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@ -242,29 +242,29 @@ module axi4_to_ahb(
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wire _GEN_73 = _T_134 ? _T_156 : _GEN_52; // @[Conditional.scala 39:67]
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wire _GEN_94 = _T_99 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67]
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wire slave_valid_pre = _T_47 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58]
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wire _T_23 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 210:32]
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wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 158:21 axi4_to_ahb.scala 465:12]
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wire _T_23 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 208:32]
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wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 156:21 axi4_to_ahb.scala 463:12]
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reg slvbuf_write; // @[Reg.scala 27:20]
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wire [1:0] _T_595 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 367:23]
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wire [1:0] _T_595 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 365:23]
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reg slvbuf_error; // @[Reg.scala 27:20]
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wire [1:0] _T_597 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
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wire [1:0] _T_598 = _T_597 & 2'h2; // @[axi4_to_ahb.scala 367:88]
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wire [1:0] _T_598 = _T_597 & 2'h2; // @[axi4_to_ahb.scala 365:88]
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wire [3:0] slave_opc = {_T_595,_T_598}; // @[Cat.scala 29:58]
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wire [1:0] _T_28 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 211:49]
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wire [1:0] _T_28 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 209:49]
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reg slvbuf_tag; // @[Reg.scala 27:20]
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wire _T_33 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 214:65]
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wire _T_33 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 212:65]
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reg [31:0] last_bus_addr; // @[Reg.scala 27:20]
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wire [63:0] _T_602 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58]
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wire _T_603 = buf_state == 3'h5; // @[axi4_to_ahb.scala 368:91]
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wire _T_603 = buf_state == 3'h5; // @[axi4_to_ahb.scala 366:91]
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reg [63:0] buf_data; // @[el2_lib.scala 514:16]
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wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 64:27 axi4_to_ahb.scala 468:17]
|
||||
reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 457:12]
|
||||
wire [63:0] _T_606 = _T_603 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 368:79]
|
||||
wire _T_42 = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 221:56]
|
||||
wire _T_43 = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 221:91]
|
||||
wire _T_44 = _T_42 | _T_43; // @[axi4_to_ahb.scala 221:74]
|
||||
wire _T_53 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 252:54]
|
||||
wire _T_54 = buf_state_en & _T_53; // @[axi4_to_ahb.scala 252:38]
|
||||
wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 64:27 axi4_to_ahb.scala 466:17]
|
||||
reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 455:12]
|
||||
wire [63:0] _T_606 = _T_603 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 366:79]
|
||||
wire _T_42 = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 219:56]
|
||||
wire _T_43 = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 219:91]
|
||||
wire _T_44 = _T_42 | _T_43; // @[axi4_to_ahb.scala 219:74]
|
||||
wire _T_53 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 250:54]
|
||||
wire _T_54 = buf_state_en & _T_53; // @[axi4_to_ahb.scala 250:38]
|
||||
wire [2:0] _T_84 = wrbuf_byteen[7] ? 3'h7 : 3'h0; // @[Mux.scala 98:16]
|
||||
wire [2:0] _T_85 = wrbuf_byteen[6] ? 3'h6 : _T_84; // @[Mux.scala 98:16]
|
||||
wire [2:0] _T_86 = wrbuf_byteen[5] ? 3'h5 : _T_85; // @[Mux.scala 98:16]
|
||||
|
|
@ -273,14 +273,14 @@ module axi4_to_ahb(
|
|||
wire [2:0] _T_89 = wrbuf_byteen[2] ? 3'h2 : _T_88; // @[Mux.scala 98:16]
|
||||
wire [2:0] _T_90 = wrbuf_byteen[1] ? 3'h1 : _T_89; // @[Mux.scala 98:16]
|
||||
wire [2:0] _T_91 = wrbuf_byteen[0] ? 3'h0 : _T_90; // @[Mux.scala 98:16]
|
||||
wire [2:0] _T_93 = buf_write_in ? _T_91 : master_addr[2:0]; // @[axi4_to_ahb.scala 255:30]
|
||||
wire _T_94 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 257:51]
|
||||
wire _T_124 = master_ready & master_valid; // @[axi4_to_ahb.scala 268:33]
|
||||
wire _T_160 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 283:64]
|
||||
wire _T_161 = _T_124 & _T_160; // @[axi4_to_ahb.scala 283:48]
|
||||
wire _T_162 = _T_161 & buf_state_en; // @[axi4_to_ahb.scala 283:79]
|
||||
wire _T_350 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 328:33]
|
||||
wire _T_352 = _T_350 & _T_53; // @[axi4_to_ahb.scala 328:48]
|
||||
wire [2:0] _T_93 = buf_write_in ? _T_91 : master_addr[2:0]; // @[axi4_to_ahb.scala 253:30]
|
||||
wire _T_94 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 255:51]
|
||||
wire _T_124 = master_ready & master_valid; // @[axi4_to_ahb.scala 266:33]
|
||||
wire _T_160 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 281:64]
|
||||
wire _T_161 = _T_124 & _T_160; // @[axi4_to_ahb.scala 281:48]
|
||||
wire _T_162 = _T_161 & buf_state_en; // @[axi4_to_ahb.scala 281:79]
|
||||
wire _T_350 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 326:33]
|
||||
wire _T_352 = _T_350 & _T_53; // @[axi4_to_ahb.scala 326:48]
|
||||
wire _GEN_12 = _T_279 & _T_352; // @[Conditional.scala 39:67]
|
||||
wire _GEN_32 = _T_186 ? 1'h0 : _GEN_12; // @[Conditional.scala 39:67]
|
||||
wire _GEN_48 = _T_184 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67]
|
||||
|
|
@ -289,39 +289,39 @@ module axi4_to_ahb(
|
|||
wire _GEN_88 = _T_99 ? _T_124 : _GEN_75; // @[Conditional.scala 39:67]
|
||||
wire bypass_en = _T_47 ? buf_state_en : _GEN_88; // @[Conditional.scala 40:58]
|
||||
wire [1:0] _T_97 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
||||
wire [1:0] _T_98 = _T_97 & 2'h2; // @[axi4_to_ahb.scala 258:45]
|
||||
wire _T_110 = ~master_valid; // @[axi4_to_ahb.scala 264:34]
|
||||
wire _T_111 = buf_state_en & _T_110; // @[axi4_to_ahb.scala 264:32]
|
||||
wire [1:0] _T_98 = _T_97 & 2'h2; // @[axi4_to_ahb.scala 256:45]
|
||||
wire _T_110 = ~master_valid; // @[axi4_to_ahb.scala 262:34]
|
||||
wire _T_111 = buf_state_en & _T_110; // @[axi4_to_ahb.scala 262:32]
|
||||
reg [31:0] buf_addr; // @[el2_lib.scala 514:16]
|
||||
wire [2:0] _T_128 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 269:30]
|
||||
wire _T_129 = ~buf_state_en; // @[axi4_to_ahb.scala 270:44]
|
||||
wire _T_130 = _T_129 | bypass_en; // @[axi4_to_ahb.scala 270:58]
|
||||
wire [2:0] _T_128 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 267:30]
|
||||
wire _T_129 = ~buf_state_en; // @[axi4_to_ahb.scala 268:44]
|
||||
wire _T_130 = _T_129 | bypass_en; // @[axi4_to_ahb.scala 268:58]
|
||||
wire [1:0] _T_132 = _T_130 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
||||
wire [1:0] _T_133 = 2'h2 & _T_132; // @[axi4_to_ahb.scala 270:32]
|
||||
wire _T_167 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 285:59]
|
||||
wire _T_168 = _T_167 & buf_state_en; // @[axi4_to_ahb.scala 285:74]
|
||||
wire _T_169 = ~_T_168; // @[axi4_to_ahb.scala 285:43]
|
||||
wire [1:0] _T_133 = 2'h2 & _T_132; // @[axi4_to_ahb.scala 268:32]
|
||||
wire _T_167 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 283:59]
|
||||
wire _T_168 = _T_167 & buf_state_en; // @[axi4_to_ahb.scala 283:74]
|
||||
wire _T_169 = ~_T_168; // @[axi4_to_ahb.scala 283:43]
|
||||
wire [1:0] _T_171 = _T_169 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
||||
wire [1:0] _T_172 = 2'h2 & _T_171; // @[axi4_to_ahb.scala 285:32]
|
||||
wire [1:0] _T_172 = 2'h2 & _T_171; // @[axi4_to_ahb.scala 283:32]
|
||||
wire [1:0] _T_182 = _T_129 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
||||
wire [1:0] _T_183 = 2'h2 & _T_182; // @[axi4_to_ahb.scala 295:37]
|
||||
wire [1:0] _T_183 = 2'h2 & _T_182; // @[axi4_to_ahb.scala 293:37]
|
||||
reg [2:0] buf_cmd_byte_ptrQ; // @[Reg.scala 27:20]
|
||||
reg [7:0] buf_byteen; // @[Reg.scala 27:20]
|
||||
wire [2:0] _T_195 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 184:52]
|
||||
wire _T_198 = 3'h0 >= _T_195; // @[axi4_to_ahb.scala 185:62]
|
||||
wire _T_199 = buf_byteen[0] & _T_198; // @[axi4_to_ahb.scala 185:48]
|
||||
wire _T_201 = 3'h1 >= _T_195; // @[axi4_to_ahb.scala 185:62]
|
||||
wire _T_202 = buf_byteen[1] & _T_201; // @[axi4_to_ahb.scala 185:48]
|
||||
wire _T_204 = 3'h2 >= _T_195; // @[axi4_to_ahb.scala 185:62]
|
||||
wire _T_205 = buf_byteen[2] & _T_204; // @[axi4_to_ahb.scala 185:48]
|
||||
wire _T_207 = 3'h3 >= _T_195; // @[axi4_to_ahb.scala 185:62]
|
||||
wire _T_208 = buf_byteen[3] & _T_207; // @[axi4_to_ahb.scala 185:48]
|
||||
wire _T_210 = 3'h4 >= _T_195; // @[axi4_to_ahb.scala 185:62]
|
||||
wire _T_211 = buf_byteen[4] & _T_210; // @[axi4_to_ahb.scala 185:48]
|
||||
wire _T_213 = 3'h5 >= _T_195; // @[axi4_to_ahb.scala 185:62]
|
||||
wire _T_214 = buf_byteen[5] & _T_213; // @[axi4_to_ahb.scala 185:48]
|
||||
wire _T_216 = 3'h6 >= _T_195; // @[axi4_to_ahb.scala 185:62]
|
||||
wire _T_217 = buf_byteen[6] & _T_216; // @[axi4_to_ahb.scala 185:48]
|
||||
wire [2:0] _T_195 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 182:52]
|
||||
wire _T_198 = 3'h0 >= _T_195; // @[axi4_to_ahb.scala 183:62]
|
||||
wire _T_199 = buf_byteen[0] & _T_198; // @[axi4_to_ahb.scala 183:48]
|
||||
wire _T_201 = 3'h1 >= _T_195; // @[axi4_to_ahb.scala 183:62]
|
||||
wire _T_202 = buf_byteen[1] & _T_201; // @[axi4_to_ahb.scala 183:48]
|
||||
wire _T_204 = 3'h2 >= _T_195; // @[axi4_to_ahb.scala 183:62]
|
||||
wire _T_205 = buf_byteen[2] & _T_204; // @[axi4_to_ahb.scala 183:48]
|
||||
wire _T_207 = 3'h3 >= _T_195; // @[axi4_to_ahb.scala 183:62]
|
||||
wire _T_208 = buf_byteen[3] & _T_207; // @[axi4_to_ahb.scala 183:48]
|
||||
wire _T_210 = 3'h4 >= _T_195; // @[axi4_to_ahb.scala 183:62]
|
||||
wire _T_211 = buf_byteen[4] & _T_210; // @[axi4_to_ahb.scala 183:48]
|
||||
wire _T_213 = 3'h5 >= _T_195; // @[axi4_to_ahb.scala 183:62]
|
||||
wire _T_214 = buf_byteen[5] & _T_213; // @[axi4_to_ahb.scala 183:48]
|
||||
wire _T_216 = 3'h6 >= _T_195; // @[axi4_to_ahb.scala 183:62]
|
||||
wire _T_217 = buf_byteen[6] & _T_216; // @[axi4_to_ahb.scala 183:48]
|
||||
wire [2:0] _T_221 = buf_byteen[7] ? 3'h7 : 3'h0; // @[Mux.scala 98:16]
|
||||
wire [2:0] _T_222 = _T_217 ? 3'h6 : _T_221; // @[Mux.scala 98:16]
|
||||
wire [2:0] _T_223 = _T_214 ? 3'h5 : _T_222; // @[Mux.scala 98:16]
|
||||
|
|
@ -330,17 +330,17 @@ module axi4_to_ahb(
|
|||
wire [2:0] _T_226 = _T_205 ? 3'h2 : _T_225; // @[Mux.scala 98:16]
|
||||
wire [2:0] _T_227 = _T_202 ? 3'h1 : _T_226; // @[Mux.scala 98:16]
|
||||
wire [2:0] _T_228 = _T_199 ? 3'h0 : _T_227; // @[Mux.scala 98:16]
|
||||
wire [2:0] _T_229 = trxn_done ? _T_228 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 313:30]
|
||||
wire _T_230 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 314:65]
|
||||
wire [2:0] _T_229 = trxn_done ? _T_228 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 311:30]
|
||||
wire _T_230 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 312:65]
|
||||
reg buf_aligned; // @[Reg.scala 27:20]
|
||||
wire _T_231 = buf_aligned | _T_230; // @[axi4_to_ahb.scala 314:44]
|
||||
wire [7:0] _T_269 = buf_byteen >> _T_228; // @[axi4_to_ahb.scala 314:92]
|
||||
wire _T_271 = ~_T_269[0]; // @[axi4_to_ahb.scala 314:163]
|
||||
wire _T_272 = _T_231 | _T_271; // @[axi4_to_ahb.scala 314:79]
|
||||
wire _T_273 = trxn_done & _T_272; // @[axi4_to_ahb.scala 314:29]
|
||||
wire _T_347 = _T_230 | _T_271; // @[axi4_to_ahb.scala 327:118]
|
||||
wire _T_348 = _T_107 & _T_347; // @[axi4_to_ahb.scala 327:82]
|
||||
wire _T_349 = ahb_hresp_q | _T_348; // @[axi4_to_ahb.scala 327:32]
|
||||
wire _T_231 = buf_aligned | _T_230; // @[axi4_to_ahb.scala 312:44]
|
||||
wire [7:0] _T_269 = buf_byteen >> _T_228; // @[axi4_to_ahb.scala 312:92]
|
||||
wire _T_271 = ~_T_269[0]; // @[axi4_to_ahb.scala 312:163]
|
||||
wire _T_272 = _T_231 | _T_271; // @[axi4_to_ahb.scala 312:79]
|
||||
wire _T_273 = trxn_done & _T_272; // @[axi4_to_ahb.scala 312:29]
|
||||
wire _T_347 = _T_230 | _T_271; // @[axi4_to_ahb.scala 325:118]
|
||||
wire _T_348 = _T_107 & _T_347; // @[axi4_to_ahb.scala 325:82]
|
||||
wire _T_349 = ahb_hresp_q | _T_348; // @[axi4_to_ahb.scala 325:32]
|
||||
wire _GEN_11 = _T_279 & _T_349; // @[Conditional.scala 39:67]
|
||||
wire _GEN_24 = _T_186 ? _T_273 : _GEN_11; // @[Conditional.scala 39:67]
|
||||
wire _GEN_43 = _T_184 ? 1'h0 : _GEN_24; // @[Conditional.scala 39:67]
|
||||
|
|
@ -348,17 +348,17 @@ module axi4_to_ahb(
|
|||
wire _GEN_74 = _T_134 ? _T_111 : _GEN_61; // @[Conditional.scala 39:67]
|
||||
wire _GEN_84 = _T_99 ? _T_111 : _GEN_74; // @[Conditional.scala 39:67]
|
||||
wire cmd_done = _T_47 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58]
|
||||
wire _T_274 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 315:43]
|
||||
wire _T_275 = ~_T_274; // @[axi4_to_ahb.scala 315:32]
|
||||
wire _T_274 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 313:43]
|
||||
wire _T_275 = ~_T_274; // @[axi4_to_ahb.scala 313:32]
|
||||
wire [1:0] _T_277 = _T_275 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
||||
wire [1:0] _T_278 = _T_277 & 2'h2; // @[axi4_to_ahb.scala 315:57]
|
||||
wire _T_301 = _T_53 | _T_94; // @[axi4_to_ahb.scala 325:62]
|
||||
wire _T_302 = buf_state_en & _T_301; // @[axi4_to_ahb.scala 325:33]
|
||||
wire _T_355 = _T_275 | bypass_en; // @[axi4_to_ahb.scala 329:57]
|
||||
wire [1:0] _T_278 = _T_277 & 2'h2; // @[axi4_to_ahb.scala 313:57]
|
||||
wire _T_301 = _T_53 | _T_94; // @[axi4_to_ahb.scala 323:62]
|
||||
wire _T_302 = buf_state_en & _T_301; // @[axi4_to_ahb.scala 323:33]
|
||||
wire _T_355 = _T_275 | bypass_en; // @[axi4_to_ahb.scala 327:57]
|
||||
wire [1:0] _T_357 = _T_355 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
||||
wire [1:0] _T_358 = _T_357 & 2'h2; // @[axi4_to_ahb.scala 329:71]
|
||||
wire _T_365 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 332:40]
|
||||
wire [2:0] _T_441 = bypass_en ? _T_91 : _T_229; // @[axi4_to_ahb.scala 335:30]
|
||||
wire [1:0] _T_358 = _T_357 & 2'h2; // @[axi4_to_ahb.scala 327:71]
|
||||
wire _T_365 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 330:40]
|
||||
wire [2:0] _T_441 = bypass_en ? _T_91 : _T_229; // @[axi4_to_ahb.scala 333:30]
|
||||
wire _GEN_6 = _T_279 & ahb_hresp_q; // @[Conditional.scala 39:67]
|
||||
wire _GEN_7 = _T_279 ? buf_state_en : _T_442; // @[Conditional.scala 39:67]
|
||||
wire _GEN_9 = _T_279 & _T_302; // @[Conditional.scala 39:67]
|
||||
|
|
@ -407,72 +407,72 @@ module axi4_to_ahb(
|
|||
wire [2:0] buf_cmd_byte_ptr = _T_47 ? _T_93 : _GEN_89; // @[Conditional.scala 40:58]
|
||||
wire slvbuf_wr_en = _T_47 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58]
|
||||
wire slvbuf_error_en = _T_47 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58]
|
||||
wire _T_534 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 353:24]
|
||||
wire _T_535 = _T_101 | _T_534; // @[axi4_to_ahb.scala 352:51]
|
||||
wire _T_537 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 353:57]
|
||||
wire _T_538 = _T_535 | _T_537; // @[axi4_to_ahb.scala 353:36]
|
||||
wire _T_540 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 353:91]
|
||||
wire _T_541 = _T_538 | _T_540; // @[axi4_to_ahb.scala 353:70]
|
||||
wire _T_543 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 354:25]
|
||||
wire _T_545 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 354:62]
|
||||
wire _T_547 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 354:97]
|
||||
wire _T_548 = _T_545 | _T_547; // @[axi4_to_ahb.scala 354:74]
|
||||
wire _T_550 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 354:132]
|
||||
wire _T_551 = _T_548 | _T_550; // @[axi4_to_ahb.scala 354:109]
|
||||
wire _T_553 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 354:168]
|
||||
wire _T_554 = _T_551 | _T_553; // @[axi4_to_ahb.scala 354:145]
|
||||
wire _T_556 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 355:28]
|
||||
wire _T_557 = _T_554 | _T_556; // @[axi4_to_ahb.scala 354:181]
|
||||
wire _T_559 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 355:63]
|
||||
wire _T_560 = _T_557 | _T_559; // @[axi4_to_ahb.scala 355:40]
|
||||
wire _T_562 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 355:99]
|
||||
wire _T_563 = _T_560 | _T_562; // @[axi4_to_ahb.scala 355:76]
|
||||
wire _T_564 = _T_543 & _T_563; // @[axi4_to_ahb.scala 354:38]
|
||||
wire buf_aligned_in = _T_541 | _T_564; // @[axi4_to_ahb.scala 353:104]
|
||||
wire _T_446 = buf_aligned_in & _T_49; // @[axi4_to_ahb.scala 347:60]
|
||||
wire [2:0] _T_483 = _T_446 ? 3'h0 : master_addr[2:0]; // @[axi4_to_ahb.scala 347:43]
|
||||
wire _T_487 = buf_state == 3'h3; // @[axi4_to_ahb.scala 350:33]
|
||||
wire _T_493 = buf_aligned_in & _T_543; // @[axi4_to_ahb.scala 351:38]
|
||||
wire _T_496 = _T_493 & _T_49; // @[axi4_to_ahb.scala 351:72]
|
||||
wire [1:0] _T_530 = _T_496 ? 2'h0 : master_size[1:0]; // @[axi4_to_ahb.scala 351:21]
|
||||
wire _T_534 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 351:24]
|
||||
wire _T_535 = _T_101 | _T_534; // @[axi4_to_ahb.scala 350:51]
|
||||
wire _T_537 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 351:57]
|
||||
wire _T_538 = _T_535 | _T_537; // @[axi4_to_ahb.scala 351:36]
|
||||
wire _T_540 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 351:91]
|
||||
wire _T_541 = _T_538 | _T_540; // @[axi4_to_ahb.scala 351:70]
|
||||
wire _T_543 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 352:25]
|
||||
wire _T_545 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 352:62]
|
||||
wire _T_547 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 352:97]
|
||||
wire _T_548 = _T_545 | _T_547; // @[axi4_to_ahb.scala 352:74]
|
||||
wire _T_550 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 352:132]
|
||||
wire _T_551 = _T_548 | _T_550; // @[axi4_to_ahb.scala 352:109]
|
||||
wire _T_553 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 352:168]
|
||||
wire _T_554 = _T_551 | _T_553; // @[axi4_to_ahb.scala 352:145]
|
||||
wire _T_556 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 353:28]
|
||||
wire _T_557 = _T_554 | _T_556; // @[axi4_to_ahb.scala 352:181]
|
||||
wire _T_559 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 353:63]
|
||||
wire _T_560 = _T_557 | _T_559; // @[axi4_to_ahb.scala 353:40]
|
||||
wire _T_562 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 353:99]
|
||||
wire _T_563 = _T_560 | _T_562; // @[axi4_to_ahb.scala 353:76]
|
||||
wire _T_564 = _T_543 & _T_563; // @[axi4_to_ahb.scala 352:38]
|
||||
wire buf_aligned_in = _T_541 | _T_564; // @[axi4_to_ahb.scala 351:104]
|
||||
wire _T_446 = buf_aligned_in & _T_49; // @[axi4_to_ahb.scala 345:60]
|
||||
wire [2:0] _T_483 = _T_446 ? 3'h0 : master_addr[2:0]; // @[axi4_to_ahb.scala 345:43]
|
||||
wire _T_487 = buf_state == 3'h3; // @[axi4_to_ahb.scala 348:33]
|
||||
wire _T_493 = buf_aligned_in & _T_543; // @[axi4_to_ahb.scala 349:38]
|
||||
wire _T_496 = _T_493 & _T_49; // @[axi4_to_ahb.scala 349:72]
|
||||
wire [1:0] _T_530 = _T_496 ? 2'h0 : master_size[1:0]; // @[axi4_to_ahb.scala 349:21]
|
||||
wire [31:0] _T_569 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_572 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58]
|
||||
wire [1:0] _T_576 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
||||
wire [2:0] buf_size_in = {{1'd0}, _T_530}; // @[axi4_to_ahb.scala 351:15]
|
||||
wire [1:0] _T_578 = _T_576 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 358:80]
|
||||
wire [2:0] buf_size_in = {{1'd0}, _T_530}; // @[axi4_to_ahb.scala 349:15]
|
||||
wire [1:0] _T_578 = _T_576 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 356:80]
|
||||
wire [2:0] _T_579 = {1'h0,_T_578}; // @[Cat.scala 29:58]
|
||||
wire [1:0] _T_581 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
||||
reg [1:0] buf_size; // @[Reg.scala 27:20]
|
||||
wire [1:0] _T_583 = _T_581 & buf_size; // @[axi4_to_ahb.scala 358:138]
|
||||
wire [1:0] _T_583 = _T_581 & buf_size; // @[axi4_to_ahb.scala 356:138]
|
||||
wire [2:0] _T_584 = {1'h0,_T_583}; // @[Cat.scala 29:58]
|
||||
wire _T_587 = ~io_axi_arprot[2]; // @[axi4_to_ahb.scala 362:33]
|
||||
wire _T_587 = ~io_axi_arprot[2]; // @[axi4_to_ahb.scala 360:33]
|
||||
wire [1:0] _T_588 = {1'h1,_T_587}; // @[Cat.scala 29:58]
|
||||
reg buf_write; // @[Reg.scala 27:20]
|
||||
wire _T_610 = io_ahb_htrans != 2'h0; // @[axi4_to_ahb.scala 371:40]
|
||||
wire _T_611 = _T_610 & io_ahb_hready; // @[axi4_to_ahb.scala 371:52]
|
||||
wire last_addr_en = _T_611 & io_ahb_hwrite; // @[axi4_to_ahb.scala 371:68]
|
||||
wire wrbuf_en = _T_42 & master_ready; // @[axi4_to_ahb.scala 373:47]
|
||||
wire wrbuf_data_en = _T_43 & master_ready; // @[axi4_to_ahb.scala 374:50]
|
||||
wire wrbuf_cmd_sent = _T_147 & _T_49; // @[axi4_to_ahb.scala 375:49]
|
||||
wire _T_621 = ~wrbuf_en; // @[axi4_to_ahb.scala 376:33]
|
||||
wire wrbuf_rst = wrbuf_cmd_sent & _T_621; // @[axi4_to_ahb.scala 376:31]
|
||||
wire _T_623 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 378:35]
|
||||
wire _T_624 = wrbuf_vld & _T_623; // @[axi4_to_ahb.scala 378:33]
|
||||
wire _T_625 = ~_T_624; // @[axi4_to_ahb.scala 378:21]
|
||||
wire _T_628 = wrbuf_data_vld & _T_623; // @[axi4_to_ahb.scala 379:37]
|
||||
wire _T_629 = ~_T_628; // @[axi4_to_ahb.scala 379:20]
|
||||
wire _T_632 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 380:21]
|
||||
wire _T_635 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 384:52]
|
||||
wire _T_636 = ~wrbuf_rst; // @[axi4_to_ahb.scala 384:88]
|
||||
wire _T_640 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 385:52]
|
||||
wire _T_610 = io_ahb_htrans != 2'h0; // @[axi4_to_ahb.scala 369:40]
|
||||
wire _T_611 = _T_610 & io_ahb_hready; // @[axi4_to_ahb.scala 369:52]
|
||||
wire last_addr_en = _T_611 & io_ahb_hwrite; // @[axi4_to_ahb.scala 369:68]
|
||||
wire wrbuf_en = _T_42 & master_ready; // @[axi4_to_ahb.scala 371:47]
|
||||
wire wrbuf_data_en = _T_43 & master_ready; // @[axi4_to_ahb.scala 372:50]
|
||||
wire wrbuf_cmd_sent = _T_147 & _T_49; // @[axi4_to_ahb.scala 373:49]
|
||||
wire _T_621 = ~wrbuf_en; // @[axi4_to_ahb.scala 374:33]
|
||||
wire wrbuf_rst = wrbuf_cmd_sent & _T_621; // @[axi4_to_ahb.scala 374:31]
|
||||
wire _T_623 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 376:35]
|
||||
wire _T_624 = wrbuf_vld & _T_623; // @[axi4_to_ahb.scala 376:33]
|
||||
wire _T_625 = ~_T_624; // @[axi4_to_ahb.scala 376:21]
|
||||
wire _T_628 = wrbuf_data_vld & _T_623; // @[axi4_to_ahb.scala 377:37]
|
||||
wire _T_629 = ~_T_628; // @[axi4_to_ahb.scala 377:20]
|
||||
wire _T_632 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 378:21]
|
||||
wire _T_635 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 382:52]
|
||||
wire _T_636 = ~wrbuf_rst; // @[axi4_to_ahb.scala 382:88]
|
||||
wire _T_640 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 383:52]
|
||||
reg buf_tag; // @[Reg.scala 27:20]
|
||||
wire _T_690 = ~slave_valid_pre; // @[axi4_to_ahb.scala 436:52]
|
||||
wire _T_703 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 460:43]
|
||||
wire _T_704 = _T_703 | io_clk_override; // @[axi4_to_ahb.scala 460:58]
|
||||
wire _T_707 = io_ahb_hready & io_ahb_htrans[1]; // @[axi4_to_ahb.scala 461:54]
|
||||
wire _T_708 = _T_707 | io_clk_override; // @[axi4_to_ahb.scala 461:74]
|
||||
wire _T_710 = buf_state != 3'h0; // @[axi4_to_ahb.scala 462:50]
|
||||
wire _T_711 = _T_710 | io_clk_override; // @[axi4_to_ahb.scala 462:60]
|
||||
wire _T_690 = ~slave_valid_pre; // @[axi4_to_ahb.scala 434:52]
|
||||
wire _T_703 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 458:43]
|
||||
wire _T_704 = _T_703 | io_clk_override; // @[axi4_to_ahb.scala 458:58]
|
||||
wire _T_707 = io_ahb_hready & io_ahb_htrans[1]; // @[axi4_to_ahb.scala 459:54]
|
||||
wire _T_708 = _T_707 | io_clk_override; // @[axi4_to_ahb.scala 459:74]
|
||||
wire _T_710 = buf_state != 3'h0; // @[axi4_to_ahb.scala 460:50]
|
||||
wire _T_711 = _T_710 | io_clk_override; // @[axi4_to_ahb.scala 460:60]
|
||||
rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22]
|
||||
.io_l1clk(rvclkhdr_io_l1clk),
|
||||
.io_clk(rvclkhdr_io_clk),
|
||||
|
|
@ -533,25 +533,25 @@ module axi4_to_ahb(
|
|||
.io_en(rvclkhdr_9_io_en),
|
||||
.io_scan_mode(rvclkhdr_9_io_scan_mode)
|
||||
);
|
||||
assign io_axi_awready = _T_625 & master_ready; // @[axi4_to_ahb.scala 378:18]
|
||||
assign io_axi_wready = _T_629 & master_ready; // @[axi4_to_ahb.scala 379:17]
|
||||
assign io_axi_bvalid = _T_23 & slave_opc[3]; // @[axi4_to_ahb.scala 210:17]
|
||||
assign io_axi_bresp = slave_opc[0] ? 2'h2 : _T_28; // @[axi4_to_ahb.scala 211:16]
|
||||
assign io_axi_bid = slvbuf_tag; // @[axi4_to_ahb.scala 212:14]
|
||||
assign io_axi_arready = _T_632 & master_ready; // @[axi4_to_ahb.scala 380:18]
|
||||
assign io_axi_rvalid = _T_23 & _T_33; // @[axi4_to_ahb.scala 214:17]
|
||||
assign io_axi_rid = slvbuf_tag; // @[axi4_to_ahb.scala 216:14]
|
||||
assign io_axi_rdata = slvbuf_error ? _T_602 : _T_606; // @[axi4_to_ahb.scala 217:16]
|
||||
assign io_axi_rresp = slave_opc[0] ? 2'h2 : _T_28; // @[axi4_to_ahb.scala 215:16]
|
||||
assign io_axi_rlast = 1'h1; // @[axi4_to_ahb.scala 381:16]
|
||||
assign io_ahb_haddr = bypass_en ? _T_569 : _T_572; // @[axi4_to_ahb.scala 357:16]
|
||||
assign io_ahb_hburst = 3'h0; // @[axi4_to_ahb.scala 360:17]
|
||||
assign io_ahb_hmastlock = 1'h0; // @[axi4_to_ahb.scala 361:20]
|
||||
assign io_ahb_hprot = {{2'd0}, _T_588}; // @[axi4_to_ahb.scala 362:16]
|
||||
assign io_ahb_hsize = bypass_en ? _T_579 : _T_584; // @[axi4_to_ahb.scala 358:16]
|
||||
assign io_ahb_htrans = _T_47 ? _T_98 : _GEN_90; // @[axi4_to_ahb.scala 227:17 axi4_to_ahb.scala 258:21 axi4_to_ahb.scala 270:21 axi4_to_ahb.scala 285:21 axi4_to_ahb.scala 295:21 axi4_to_ahb.scala 315:21 axi4_to_ahb.scala 329:21]
|
||||
assign io_ahb_hwrite = bypass_en ? _T_49 : buf_write; // @[axi4_to_ahb.scala 363:17]
|
||||
assign io_ahb_hwdata = buf_data; // @[axi4_to_ahb.scala 364:17]
|
||||
assign io_axi_awready = _T_625 & master_ready; // @[axi4_to_ahb.scala 376:18]
|
||||
assign io_axi_wready = _T_629 & master_ready; // @[axi4_to_ahb.scala 377:17]
|
||||
assign io_axi_bvalid = _T_23 & slave_opc[3]; // @[axi4_to_ahb.scala 208:17]
|
||||
assign io_axi_bresp = slave_opc[0] ? 2'h2 : _T_28; // @[axi4_to_ahb.scala 209:16]
|
||||
assign io_axi_bid = slvbuf_tag; // @[axi4_to_ahb.scala 210:14]
|
||||
assign io_axi_arready = _T_632 & master_ready; // @[axi4_to_ahb.scala 378:18]
|
||||
assign io_axi_rvalid = _T_23 & _T_33; // @[axi4_to_ahb.scala 212:17]
|
||||
assign io_axi_rid = slvbuf_tag; // @[axi4_to_ahb.scala 214:14]
|
||||
assign io_axi_rdata = slvbuf_error ? _T_602 : _T_606; // @[axi4_to_ahb.scala 215:16]
|
||||
assign io_axi_rresp = slave_opc[0] ? 2'h2 : _T_28; // @[axi4_to_ahb.scala 213:16]
|
||||
assign io_axi_rlast = 1'h1; // @[axi4_to_ahb.scala 379:16]
|
||||
assign io_ahb_haddr = bypass_en ? _T_569 : _T_572; // @[axi4_to_ahb.scala 355:16]
|
||||
assign io_ahb_hburst = 3'h0; // @[axi4_to_ahb.scala 358:17]
|
||||
assign io_ahb_hmastlock = 1'h0; // @[axi4_to_ahb.scala 359:20]
|
||||
assign io_ahb_hprot = {{2'd0}, _T_588}; // @[axi4_to_ahb.scala 360:16]
|
||||
assign io_ahb_hsize = bypass_en ? _T_579 : _T_584; // @[axi4_to_ahb.scala 356:16]
|
||||
assign io_ahb_htrans = _T_47 ? _T_98 : _GEN_90; // @[axi4_to_ahb.scala 225:17 axi4_to_ahb.scala 256:21 axi4_to_ahb.scala 268:21 axi4_to_ahb.scala 283:21 axi4_to_ahb.scala 293:21 axi4_to_ahb.scala 313:21 axi4_to_ahb.scala 327:21]
|
||||
assign io_ahb_hwrite = bypass_en ? _T_49 : buf_write; // @[axi4_to_ahb.scala 361:17]
|
||||
assign io_ahb_hwdata = buf_data; // @[axi4_to_ahb.scala 362:17]
|
||||
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17]
|
||||
assign rvclkhdr_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16]
|
||||
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
|
||||
|
|
|
|||
|
|
@ -65,9 +65,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
|
|||
val idle :: cmd_rd :: cmd_wr :: data_rd :: data_wr :: done :: stream_rd :: stream_err_rd :: Nil = Enum(8)
|
||||
val buf_state = WireInit(idle)
|
||||
val buf_nxtstate = WireInit(idle)
|
||||
buf_state := withClock(ahbm_clk) {
|
||||
RegNext(Mux(buf_state_en.asBool(),buf_nxtstate,buf_state) & !buf_rst, 0.U)
|
||||
}
|
||||
buf_state := withClock(ahbm_clk) { RegNext(Mux(buf_state_en.asBool(),buf_nxtstate,buf_state) & !buf_rst, 0.U) }
|
||||
//logic signals
|
||||
val slave_valid = WireInit(Bool(), init = false.B)
|
||||
val slave_ready = WireInit(Bool(), init = false.B)
|
||||
|
|
@ -244,7 +242,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
|
|||
|
||||
switch(buf_state) {
|
||||
is(idle) {
|
||||
// master_ready := 1.U
|
||||
master_ready := 1.U
|
||||
buf_write_in := (master_opc(2, 1) === "b01".U)
|
||||
buf_nxtstate := Mux(buf_write_in.asBool(), cmd_wr, cmd_rd)
|
||||
buf_state_en := master_valid & 1.U
|
||||
|
|
|
|||
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Reference in New Issue