buf_error corrected

lsu_bus_buffer.fir

@@ -5855,28 +5855,28 @@ circuit lsu_bus_buffer :
     buf_data[1] <= _T_4384 @[lsu_bus_buffer.scala 522:12]
     buf_data[2] <= _T_4385 @[lsu_bus_buffer.scala 522:12]
     buf_data[3] <= _T_4386 @[lsu_bus_buffer.scala 522:12]
-    node _T_4387 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 523:119]
-    node _T_4388 = mux(buf_error_en[0], UInt<1>("h01"), _T_4387) @[lsu_bus_buffer.scala 523:84]
-    node _T_4389 = eq(buf_rst[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 523:126]
-    node _T_4390 = and(_T_4388, _T_4389) @[lsu_bus_buffer.scala 523:124]
+    node _T_4387 = eq(buf_rst[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 523:81]
+    node _T_4388 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 523:133]
+    node _T_4389 = mux(buf_error_en[0], UInt<1>("h01"), _T_4388) @[lsu_bus_buffer.scala 523:98]
+    node _T_4390 = and(_T_4387, _T_4389) @[lsu_bus_buffer.scala 523:93]
     reg _T_4391 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 523:80]
     _T_4391 <= _T_4390 @[lsu_bus_buffer.scala 523:80]
-    node _T_4392 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 523:119]
-    node _T_4393 = mux(buf_error_en[1], UInt<1>("h01"), _T_4392) @[lsu_bus_buffer.scala 523:84]
-    node _T_4394 = eq(buf_rst[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 523:126]
-    node _T_4395 = and(_T_4393, _T_4394) @[lsu_bus_buffer.scala 523:124]
+    node _T_4392 = eq(buf_rst[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 523:81]
+    node _T_4393 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 523:133]
+    node _T_4394 = mux(buf_error_en[1], UInt<1>("h01"), _T_4393) @[lsu_bus_buffer.scala 523:98]
+    node _T_4395 = and(_T_4392, _T_4394) @[lsu_bus_buffer.scala 523:93]
     reg _T_4396 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 523:80]
     _T_4396 <= _T_4395 @[lsu_bus_buffer.scala 523:80]
-    node _T_4397 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 523:119]
-    node _T_4398 = mux(buf_error_en[2], UInt<1>("h01"), _T_4397) @[lsu_bus_buffer.scala 523:84]
-    node _T_4399 = eq(buf_rst[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 523:126]
-    node _T_4400 = and(_T_4398, _T_4399) @[lsu_bus_buffer.scala 523:124]
+    node _T_4397 = eq(buf_rst[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 523:81]
+    node _T_4398 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 523:133]
+    node _T_4399 = mux(buf_error_en[2], UInt<1>("h01"), _T_4398) @[lsu_bus_buffer.scala 523:98]
+    node _T_4400 = and(_T_4397, _T_4399) @[lsu_bus_buffer.scala 523:93]
     reg _T_4401 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 523:80]
     _T_4401 <= _T_4400 @[lsu_bus_buffer.scala 523:80]
-    node _T_4402 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 523:119]
-    node _T_4403 = mux(buf_error_en[3], UInt<1>("h01"), _T_4402) @[lsu_bus_buffer.scala 523:84]
-    node _T_4404 = eq(buf_rst[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 523:126]
-    node _T_4405 = and(_T_4403, _T_4404) @[lsu_bus_buffer.scala 523:124]
+    node _T_4402 = eq(buf_rst[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 523:81]
+    node _T_4403 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 523:133]
+    node _T_4404 = mux(buf_error_en[3], UInt<1>("h01"), _T_4403) @[lsu_bus_buffer.scala 523:98]
+    node _T_4405 = and(_T_4402, _T_4404) @[lsu_bus_buffer.scala 523:93]
     reg _T_4406 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 523:80]
     _T_4406 <= _T_4405 @[lsu_bus_buffer.scala 523:80]
     node _T_4407 = cat(_T_4406, _T_4401) @[Cat.scala 29:58]

lsu_bus_buffer.v

@@ -2473,19 +2473,19 @@ module lsu_bus_buffer(
   reg  _T_4337; // @[Reg.scala 27:20]
   reg  _T_4340; // @[Reg.scala 27:20]
   wire [3:0] buf_unsign = {_T_4340,_T_4337,_T_4334,_T_4331}; // @[Cat.scala 29:58]
+  wire  _T_4387 = ~buf_rst_0; // @[lsu_bus_buffer.scala 523:81]
   reg  _T_4406; // @[lsu_bus_buffer.scala 523:80]
   reg  _T_4401; // @[lsu_bus_buffer.scala 523:80]
   reg  _T_4396; // @[lsu_bus_buffer.scala 523:80]
   reg  _T_4391; // @[lsu_bus_buffer.scala 523:80]
   wire [3:0] buf_error = {_T_4406,_T_4401,_T_4396,_T_4391}; // @[Cat.scala 29:58]
-  wire  _T_4388 = buf_error_en_0 | buf_error[0]; // @[lsu_bus_buffer.scala 523:84]
-  wire  _T_4389 = ~buf_rst_0; // @[lsu_bus_buffer.scala 523:126]
-  wire  _T_4393 = buf_error_en_1 | buf_error[1]; // @[lsu_bus_buffer.scala 523:84]
-  wire  _T_4394 = ~buf_rst_1; // @[lsu_bus_buffer.scala 523:126]
-  wire  _T_4398 = buf_error_en_2 | buf_error[2]; // @[lsu_bus_buffer.scala 523:84]
-  wire  _T_4399 = ~buf_rst_2; // @[lsu_bus_buffer.scala 523:126]
-  wire  _T_4403 = buf_error_en_3 | buf_error[3]; // @[lsu_bus_buffer.scala 523:84]
-  wire  _T_4404 = ~buf_rst_3; // @[lsu_bus_buffer.scala 523:126]
+  wire  _T_4389 = buf_error_en_0 | buf_error[0]; // @[lsu_bus_buffer.scala 523:98]
+  wire  _T_4392 = ~buf_rst_1; // @[lsu_bus_buffer.scala 523:81]
+  wire  _T_4394 = buf_error_en_1 | buf_error[1]; // @[lsu_bus_buffer.scala 523:98]
+  wire  _T_4397 = ~buf_rst_2; // @[lsu_bus_buffer.scala 523:81]
+  wire  _T_4399 = buf_error_en_2 | buf_error[2]; // @[lsu_bus_buffer.scala 523:98]
+  wire  _T_4402 = ~buf_rst_3; // @[lsu_bus_buffer.scala 523:81]
+  wire  _T_4404 = buf_error_en_3 | buf_error[3]; // @[lsu_bus_buffer.scala 523:98]
   wire [1:0] _T_4410 = {io_lsu_busreq_m,1'h0}; // @[Cat.scala 29:58]
   wire [1:0] _T_4411 = io_ldst_dual_m ? _T_4410 : {{1'd0}, io_lsu_busreq_m}; // @[lsu_bus_buffer.scala 524:28]
   wire [1:0] _T_4412 = {io_lsu_busreq_r,1'h0}; // @[Cat.scala 29:58]
@@ -4589,28 +4589,28 @@ end // initial
     if (reset) begin
       _T_4406 <= 1'h0;
     end else begin
-      _T_4406 <= _T_4403 & _T_4404;
+      _T_4406 <= _T_4402 & _T_4404;
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
       _T_4401 <= 1'h0;
     end else begin
-      _T_4401 <= _T_4398 & _T_4399;
+      _T_4401 <= _T_4397 & _T_4399;
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
       _T_4396 <= 1'h0;
     end else begin
-      _T_4396 <= _T_4393 & _T_4394;
+      _T_4396 <= _T_4392 & _T_4394;
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
       _T_4391 <= 1'h0;
     end else begin
-      _T_4391 <= _T_4388 & _T_4389;
+      _T_4391 <= _T_4387 & _T_4389;
     end
   end
   always @(posedge io_lsu_c2_r_clk or posedge reset) begin

src/main/scala/lsu/lsu_bus_buffer.scala

@@ -520,7 +520,7 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
   buf_addr := (0 until DEPTH).map(i=>rvdffe(buf_addr_in(i), buf_wr_en(i).asBool(), clock, io.scan_mode))
   buf_byteen := (0 until DEPTH).map(i=>withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_byteen_in(i), 0.U, buf_wr_en(i).asBool())})
   buf_data := (0 until DEPTH).map(i=>rvdffe(buf_data_in(i), buf_data_en(i), clock, io.scan_mode))
-  buf_error := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegNext(Mux(buf_error_en(i), true.B, buf_error(i)) & !buf_rst(i), false.B)}).asUInt()).reverse.reduce(Cat(_,_))
+  buf_error := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegNext(!buf_rst(i) & Mux(buf_error_en(i), true.B, buf_error(i)), false.B)}).asUInt()).reverse.reduce(Cat(_,_))
   val buf_numvld_any = (Mux(io.ldst_dual_m, Cat(io.lsu_busreq_m, 0.U),io.lsu_busreq_m) +& Mux(io.ldst_dual_r, Cat(io.lsu_busreq_r, 0.U),io.lsu_busreq_r) +& ibuf_valid) + buf_state.map(i=>(i=/=idle_C).asUInt).reduce(_+&_)
   buf_numvld_wrcmd_any := (0 until DEPTH).map(i=>(buf_write(i) & (buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(_ +& _)
   buf_numvld_cmd_any :=  (0 until DEPTH).map(i=>((buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(_ +& _)