READ ME Updated
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README.md
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README.md
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Chisel Project Template
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# EL2 SweRV RISC-V Core Chiselified Version from <> LAMPRO MELLON
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=======================
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You've done the Chisel [tutorials](https://github.com/ucb-bar/chisel-tutorial), and now you
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This repository contains the SweRV EL2 Core design in CHISEL
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are ready to start your own chisel project. The following procedure should get you started
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with a clean running [Chisel3](https://github.com/freechipsproject/chisel3) project.
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> More and more users are finding IntelliJ to be a powerful tool for Chisel coding. See the
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## Back ground
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[IntelliJ Installation Guide](https://github.com/ucb-bar/chisel-template/wiki/IntelliJ-Installation-Guide) for how to install it.
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## Make your own Chisel3 project
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The project is being made for learning purpose. Copy rights to the SweRV-EL2 belongs to Wrestern Digital
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### How to get started
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The first thing you want to do is clone this repo into a directory of your own. I'd recommend creating a chisel projects directory somewhere
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```sh
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mkdir ~/ChiselProjects
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cd ~/ChiselProjects
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git clone https://github.com/ucb-bar/chisel-template.git MyChiselProject
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## Directory Structure
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cd MyChiselProject
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```
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### Make your project into a fresh git repo
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There may be more elegant way to do it, but the following works for me. **Note:** this project comes with a magnificent 339 line (at this writing) .gitignore file.
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You may want to edit that first in case we missed something, whack away at it, or start it from scratch.
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#### Clear out the old git stuff
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```sh
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rm -rf .git
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git init
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git add .gitignore *
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```
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#### Rename project in build.sbt file
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├── configs # Configurations Dir
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Use your favorite text editor to change the first line of the **build.sbt** file
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│ └── snapshots # Where generated configuration files are created
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(it ships as ```name := "chisel-module-template"```) to correspond
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├── design # Design root dir
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to your project.<br/>
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│ ├── dbg # Debugger
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Perhaps as ```name := "my-chisel-project"```
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│ ├── dec # Decode, Registers and Exceptions
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│ ├── dmi # DMI block
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│ ├── exu # EXU (ALU/MUL/DIV)
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│ ├── ifu # Fetch & Branch Prediction
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│ ├── include
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│ ├── lib
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│ └── lsu # Load/Store
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├── docs
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├── tools # Scripts/Makefiles
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└── testbench # (Very) simple testbench
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├── asm # Example assembly files
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└── hex # Canned demo hex files
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#### Clean up the README.md file
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Again use you editor of choice to make the README specific to your project.
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Be sure to update (or delete) the License section and add a LICENSE file of your own.
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#### Commit your changes
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```
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git commit -m 'Starting MyChiselProject'
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```
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Connecting this up to github or some other remote host is an exercise left to the reader.
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### Did it work?
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You should now have a project based on Chisel3 that can be run.<br/>
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So go for it, at the command line in the project root.
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```sh
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sbt 'testOnly gcd.GCDTester -- -z Basic'
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```
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>This tells the test harness to only run the test in GCDTester that contains the word Basic
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There are a number of other examples of ways to run tests in there, but we just want to see that
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one works.
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You should see a whole bunch of output that ends with something like the following lines
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```
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[info] [0.001] SEED 1540570744913
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test GCD Success: 168 tests passed in 1107 cycles in 0.067751 seconds 16339.24 Hz
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[info] [0.050] RAN 1102 CYCLES PASSED
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[info] GCDTester:
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[info] GCD
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[info] Basic test using Driver.execute
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[info] - should be used as an alternative way to run specification
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[info] using --backend-name verilator
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[info] running with --is-verbose
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[info] running with --generate-vcd-output on
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[info] running with --generate-vcd-output off
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[info] ScalaTest
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[info] Run completed in 3 seconds, 184 milliseconds.
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[info] Total number of tests run: 1
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[info] Suites: completed 1, aborted 0
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[info] Tests: succeeded 1, failed 0, canceled 0, ignored 0, pending 0
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[info] All tests passed.
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[info] Passed: Total 1, Failed 0, Errors 0, Passed 1
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[success] Total time: 5 s, completed Oct 26, 2018 9:19:07 AM
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```
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If you see the above then...
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### It worked!
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You are ready to go. We have a few recommended practices and things to do.
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* Use packages and following conventions for [structure](http://www.scala-sbt.org/0.13/docs/Directories.html) and [naming](http://docs.scala-lang.org/style/naming-conventions.html)
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* Package names should be clearly reflected in the testing hierarchy
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* Build tests for all your work.
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* This template includes a dependency on the Chisel3 IOTesters, this is a reasonable starting point for most tests
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* You can remove this dependency in the build.sbt file if necessary
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* Change the name of your project in the build.sbt file
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* Change your README.md
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There are [instructions for generating Verilog](https://github.com/freechipsproject/chisel3/wiki/Frequently-Asked-Questions#get-me-verilog) on the Chisel wiki.
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Some backends (verilator for example) produce VCD files by default, while other backends (firrtl and treadle) do not.
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You can control the generation of VCD files with the `--generate-vcd-output` flag.
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To run the simulation and generate a VCD output file regardless of the backend:
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```bash
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sbt 'test:runMain gcd.GCDMain --generate-vcd-output on'
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```
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To run the simulation and suppress the generation of a VCD output file:
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```bash
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sbt 'test:runMain gcd.GCDMain --generate-vcd-output off'
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```
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## Development/Bug Fixes
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This is the release version of chisel-template. If you have bug fixes or
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changes you would like to see incorporated in this repo, please checkout
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the master branch and submit pull requests against it.
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## License
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This is free and unencumbered software released into the public domain.
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Anyone is free to copy, modify, publish, use, compile, sell, or
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distribute this software, either in source code form or as a compiled
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binary, for any purpose, commercial or non-commercial, and by any
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means.
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In jurisdictions that recognize copyright laws, the author or authors
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of this software dedicate any and all copyright interest in the
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software to the public domain. We make this dedication for the benefit
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of the public at large and to the detriment of our heirs and
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successors. We intend this dedication to be an overt act of
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relinquishment in perpetuity of all present and future rights to this
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software under copyright law.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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OTHER DEALINGS IN THE SOFTWARE.
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For more information, please refer to <http://unlicense.org/>
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@ -9,7 +9,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib {
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val in = Input(UInt(32.W))
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val in = Input(UInt(32.W))
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val out = Output(UInt())
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val out = Output(UInt())
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})
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})
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io.out := el2_btb_tag_hash(io.in)
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io.out := el2_btb_tag_hash(io.in) | el2_btb_tag_hash(io.in)
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}
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}
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object ifu extends App {
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object ifu extends App {
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