dma updated
This commit is contained in:
Abdul Hameed Akram
parent
f36c650bf3
commit
46d51ac4b4
|
|
@ -2,6 +2,16 @@
|
|||
<code_scheme name="Project" version="173">
|
||||
<ScalaCodeStyleSettings>
|
||||
<option name="MULTILINE_STRING_CLOSING_QUOTES_ON_NEW_LINE" value="true" />
|
||||
<option name="REPLACE_CASE_ARROW_WITH_UNICODE_CHAR" value="true" />
|
||||
<option name="REPLACE_MAP_ARROW_WITH_UNICODE_CHAR" value="true" />
|
||||
<option name="REPLACE_FOR_GENERATOR_ARROW_WITH_UNICODE_CHAR" value="true" />
|
||||
</ScalaCodeStyleSettings>
|
||||
<codeStyleSettings language="Scala">
|
||||
<indentOptions>
|
||||
<option name="USE_TAB_CHARACTER" value="true" />
|
||||
<option name="SMART_TABS" value="true" />
|
||||
<option name="KEEP_INDENTS_ON_EMPTY_LINES" value="true" />
|
||||
</indentOptions>
|
||||
</codeStyleSettings>
|
||||
</code_scheme>
|
||||
</component>
|
||||
|
|
@ -26,7 +26,9 @@ def javacOptionsVersion(scalaVersion: String): Seq[String] = {
|
|||
}
|
||||
}
|
||||
|
||||
name := "chisel-module-template"
|
||||
name := "Quasar"
|
||||
|
||||
organization := "https://www.lampromellon.com/"
|
||||
|
||||
version := "3.3.0"
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
/home/waleedbinehsan/Downloads/Quasar/gated_latch.v
|
||||
/home/waleedbinehsan/Downloads/Quasar/dmi_wrapper.sv
|
||||
/home/waleedbinehsan/Downloads/Quasar/mem.sv
|
||||
/home/abdulhameed.akram/Videos/Quasar/gated_latch.v
|
||||
/home/abdulhameed.akram/Videos/Quasar/dmi_wrapper.sv
|
||||
/home/abdulhameed.akram/Videos/Quasar/mem.sv
|
||||
|
|
@ -108807,48 +108807,50 @@ circuit quasar_wrapper :
|
|||
node _T_1218 = orr(fifo_valid) @[dma_ctrl.scala 387:151]
|
||||
node _T_1219 = or(_T_1217, _T_1218) @[dma_ctrl.scala 387:137]
|
||||
node dma_free_clken = or(_T_1219, io.clk_override) @[dma_ctrl.scala 387:156]
|
||||
inst dma_buffer_c1cgc of rvclkhdr_841 @[dma_ctrl.scala 389:32]
|
||||
dma_buffer_c1cgc.clock <= clock
|
||||
dma_buffer_c1cgc.reset <= reset
|
||||
dma_buffer_c1cgc.io.en <= dma_buffer_c1_clken @[dma_ctrl.scala 390:33]
|
||||
dma_buffer_c1cgc.io.scan_mode <= io.scan_mode @[dma_ctrl.scala 391:33]
|
||||
dma_buffer_c1cgc.io.clk <= clock @[dma_ctrl.scala 392:33]
|
||||
dma_buffer_c1_clk <= dma_buffer_c1cgc.io.l1clk @[dma_ctrl.scala 393:33]
|
||||
inst dma_free_cgc of rvclkhdr_842 @[dma_ctrl.scala 395:28]
|
||||
dma_free_cgc.clock <= clock
|
||||
dma_free_cgc.reset <= reset
|
||||
dma_free_cgc.io.en <= dma_free_clken @[dma_ctrl.scala 396:29]
|
||||
dma_free_cgc.io.scan_mode <= io.scan_mode @[dma_ctrl.scala 397:29]
|
||||
dma_free_cgc.io.clk <= clock @[dma_ctrl.scala 398:29]
|
||||
dma_free_clk <= dma_free_cgc.io.l1clk @[dma_ctrl.scala 399:29]
|
||||
inst dma_bus_cgc of rvclkhdr_843 @[dma_ctrl.scala 401:27]
|
||||
dma_bus_cgc.clock <= clock
|
||||
dma_bus_cgc.reset <= reset
|
||||
dma_bus_cgc.io.en <= io.dma_bus_clk_en @[dma_ctrl.scala 402:28]
|
||||
dma_bus_cgc.io.scan_mode <= io.scan_mode @[dma_ctrl.scala 403:28]
|
||||
dma_bus_cgc.io.clk <= clock @[dma_ctrl.scala 404:28]
|
||||
dma_bus_clk <= dma_bus_cgc.io.l1clk @[dma_ctrl.scala 405:28]
|
||||
node wrbuf_en = and(io.dma_axi.aw.valid, io.dma_axi.aw.ready) @[dma_ctrl.scala 409:47]
|
||||
node wrbuf_data_en = and(io.dma_axi.w.valid, io.dma_axi.w.ready) @[dma_ctrl.scala 410:46]
|
||||
node wrbuf_cmd_sent = and(axi_mstr_prty_en, bus_cmd_write) @[dma_ctrl.scala 411:40]
|
||||
node _T_1220 = bits(wrbuf_cmd_sent, 0, 0) @[dma_ctrl.scala 412:42]
|
||||
node _T_1221 = eq(wrbuf_en, UInt<1>("h00")) @[dma_ctrl.scala 412:51]
|
||||
node wrbuf_rst = and(_T_1220, _T_1221) @[dma_ctrl.scala 412:49]
|
||||
node _T_1222 = bits(wrbuf_cmd_sent, 0, 0) @[dma_ctrl.scala 413:42]
|
||||
node _T_1223 = eq(wrbuf_data_en, UInt<1>("h00")) @[dma_ctrl.scala 413:51]
|
||||
node wrbuf_data_rst = and(_T_1222, _T_1223) @[dma_ctrl.scala 413:49]
|
||||
node _T_1224 = mux(wrbuf_en, UInt<1>("h01"), wrbuf_vld) @[dma_ctrl.scala 415:63]
|
||||
node _T_1225 = eq(wrbuf_rst, UInt<1>("h00")) @[dma_ctrl.scala 415:92]
|
||||
node _T_1226 = and(_T_1224, _T_1225) @[dma_ctrl.scala 415:90]
|
||||
reg _T_1227 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 415:59]
|
||||
_T_1227 <= _T_1226 @[dma_ctrl.scala 415:59]
|
||||
wrbuf_vld <= _T_1227 @[dma_ctrl.scala 415:25]
|
||||
node _T_1228 = mux(wrbuf_data_en, UInt<1>("h01"), wrbuf_data_vld) @[dma_ctrl.scala 417:63]
|
||||
node _T_1229 = eq(wrbuf_data_rst, UInt<1>("h00")) @[dma_ctrl.scala 417:102]
|
||||
node _T_1230 = and(_T_1228, _T_1229) @[dma_ctrl.scala 417:100]
|
||||
reg _T_1231 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 417:59]
|
||||
_T_1231 <= _T_1230 @[dma_ctrl.scala 417:59]
|
||||
wrbuf_data_vld <= _T_1231 @[dma_ctrl.scala 417:25]
|
||||
node _T_1220 = bits(dma_buffer_c1_clken, 0, 0) @[dma_ctrl.scala 389:59]
|
||||
inst rvclkhdr_10 of rvclkhdr_841 @[lib.scala 343:22]
|
||||
rvclkhdr_10.clock <= clock
|
||||
rvclkhdr_10.reset <= reset
|
||||
rvclkhdr_10.io.clk <= clock @[lib.scala 344:17]
|
||||
rvclkhdr_10.io.en <= _T_1220 @[lib.scala 345:16]
|
||||
rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
|
||||
dma_buffer_c1_clk <= rvclkhdr_10.io.l1clk @[dma_ctrl.scala 389:21]
|
||||
node _T_1221 = bits(dma_free_clken, 0, 0) @[dma_ctrl.scala 390:60]
|
||||
inst rvclkhdr_11 of rvclkhdr_842 @[lib.scala 343:22]
|
||||
rvclkhdr_11.clock <= clock
|
||||
rvclkhdr_11.reset <= reset
|
||||
rvclkhdr_11.io.clk <= clock @[lib.scala 344:17]
|
||||
rvclkhdr_11.io.en <= _T_1221 @[lib.scala 345:16]
|
||||
rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
|
||||
dma_free_clk <= rvclkhdr_11.io.l1clk @[dma_ctrl.scala 390:21]
|
||||
inst rvclkhdr_12 of rvclkhdr_843 @[lib.scala 343:22]
|
||||
rvclkhdr_12.clock <= clock
|
||||
rvclkhdr_12.reset <= reset
|
||||
rvclkhdr_12.io.clk <= clock @[lib.scala 344:17]
|
||||
rvclkhdr_12.io.en <= io.dma_bus_clk_en @[lib.scala 345:16]
|
||||
rvclkhdr_12.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
|
||||
dma_bus_clk <= rvclkhdr_12.io.l1clk @[dma_ctrl.scala 391:21]
|
||||
node wrbuf_en = and(io.dma_axi.aw.valid, io.dma_axi.aw.ready) @[dma_ctrl.scala 396:47]
|
||||
node wrbuf_data_en = and(io.dma_axi.w.valid, io.dma_axi.w.ready) @[dma_ctrl.scala 397:46]
|
||||
node wrbuf_cmd_sent = and(axi_mstr_prty_en, bus_cmd_write) @[dma_ctrl.scala 398:40]
|
||||
node _T_1222 = bits(wrbuf_cmd_sent, 0, 0) @[dma_ctrl.scala 399:42]
|
||||
node _T_1223 = eq(wrbuf_en, UInt<1>("h00")) @[dma_ctrl.scala 399:51]
|
||||
node wrbuf_rst = and(_T_1222, _T_1223) @[dma_ctrl.scala 399:49]
|
||||
node _T_1224 = bits(wrbuf_cmd_sent, 0, 0) @[dma_ctrl.scala 400:42]
|
||||
node _T_1225 = eq(wrbuf_data_en, UInt<1>("h00")) @[dma_ctrl.scala 400:51]
|
||||
node wrbuf_data_rst = and(_T_1224, _T_1225) @[dma_ctrl.scala 400:49]
|
||||
node _T_1226 = mux(wrbuf_en, UInt<1>("h01"), wrbuf_vld) @[dma_ctrl.scala 402:63]
|
||||
node _T_1227 = eq(wrbuf_rst, UInt<1>("h00")) @[dma_ctrl.scala 402:92]
|
||||
node _T_1228 = and(_T_1226, _T_1227) @[dma_ctrl.scala 402:90]
|
||||
reg _T_1229 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 402:59]
|
||||
_T_1229 <= _T_1228 @[dma_ctrl.scala 402:59]
|
||||
wrbuf_vld <= _T_1229 @[dma_ctrl.scala 402:25]
|
||||
node _T_1230 = mux(wrbuf_data_en, UInt<1>("h01"), wrbuf_data_vld) @[dma_ctrl.scala 404:63]
|
||||
node _T_1231 = eq(wrbuf_data_rst, UInt<1>("h00")) @[dma_ctrl.scala 404:102]
|
||||
node _T_1232 = and(_T_1230, _T_1231) @[dma_ctrl.scala 404:100]
|
||||
reg _T_1233 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 404:59]
|
||||
_T_1233 <= _T_1232 @[dma_ctrl.scala 404:59]
|
||||
wrbuf_data_vld <= _T_1233 @[dma_ctrl.scala 404:25]
|
||||
reg wrbuf_tag : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when wrbuf_en : @[Reg.scala 28:19]
|
||||
wrbuf_tag <= io.dma_axi.aw.bits.id @[Reg.scala 28:23]
|
||||
|
|
@ -108857,40 +108859,40 @@ circuit quasar_wrapper :
|
|||
when wrbuf_en : @[Reg.scala 28:19]
|
||||
wrbuf_sz <= io.dma_axi.aw.bits.size @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
node _T_1232 = and(wrbuf_en, io.dma_bus_clk_en) @[dma_ctrl.scala 427:68]
|
||||
inst rvclkhdr_10 of rvclkhdr_844 @[lib.scala 368:23]
|
||||
rvclkhdr_10.clock <= clock
|
||||
rvclkhdr_10.reset <= reset
|
||||
rvclkhdr_10.io.clk <= clock @[lib.scala 370:18]
|
||||
rvclkhdr_10.io.en <= _T_1232 @[lib.scala 371:17]
|
||||
rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||||
reg wrbuf_addr : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||||
node _T_1234 = and(wrbuf_en, io.dma_bus_clk_en) @[dma_ctrl.scala 414:68]
|
||||
inst rvclkhdr_13 of rvclkhdr_844 @[lib.scala 368:23]
|
||||
rvclkhdr_13.clock <= clock
|
||||
rvclkhdr_13.reset <= reset
|
||||
rvclkhdr_13.io.clk <= clock @[lib.scala 370:18]
|
||||
rvclkhdr_13.io.en <= _T_1234 @[lib.scala 371:17]
|
||||
rvclkhdr_13.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||||
reg wrbuf_addr : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||||
wrbuf_addr <= io.dma_axi.aw.bits.addr @[lib.scala 374:16]
|
||||
node _T_1233 = and(wrbuf_data_en, io.dma_bus_clk_en) @[dma_ctrl.scala 429:72]
|
||||
inst rvclkhdr_11 of rvclkhdr_845 @[lib.scala 368:23]
|
||||
rvclkhdr_11.clock <= clock
|
||||
rvclkhdr_11.reset <= reset
|
||||
rvclkhdr_11.io.clk <= clock @[lib.scala 370:18]
|
||||
rvclkhdr_11.io.en <= _T_1233 @[lib.scala 371:17]
|
||||
rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||||
reg wrbuf_data : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||||
node _T_1235 = and(wrbuf_data_en, io.dma_bus_clk_en) @[dma_ctrl.scala 416:72]
|
||||
inst rvclkhdr_14 of rvclkhdr_845 @[lib.scala 368:23]
|
||||
rvclkhdr_14.clock <= clock
|
||||
rvclkhdr_14.reset <= reset
|
||||
rvclkhdr_14.io.clk <= clock @[lib.scala 370:18]
|
||||
rvclkhdr_14.io.en <= _T_1235 @[lib.scala 371:17]
|
||||
rvclkhdr_14.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||||
reg wrbuf_data : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||||
wrbuf_data <= io.dma_axi.w.bits.data @[lib.scala 374:16]
|
||||
reg wrbuf_byteen : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when wrbuf_data_en : @[Reg.scala 28:19]
|
||||
wrbuf_byteen <= io.dma_axi.w.bits.strb @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
node rdbuf_en = and(io.dma_axi.ar.valid, io.dma_axi.ar.ready) @[dma_ctrl.scala 437:59]
|
||||
node _T_1234 = eq(bus_cmd_write, UInt<1>("h00")) @[dma_ctrl.scala 438:44]
|
||||
node rdbuf_cmd_sent = and(axi_mstr_prty_en, _T_1234) @[dma_ctrl.scala 438:42]
|
||||
node _T_1235 = bits(rdbuf_cmd_sent, 0, 0) @[dma_ctrl.scala 439:54]
|
||||
node _T_1236 = eq(rdbuf_en, UInt<1>("h00")) @[dma_ctrl.scala 439:63]
|
||||
node rdbuf_rst = and(_T_1235, _T_1236) @[dma_ctrl.scala 439:61]
|
||||
node _T_1237 = mux(rdbuf_en, UInt<1>("h01"), rdbuf_vld) @[dma_ctrl.scala 441:51]
|
||||
node _T_1238 = eq(rdbuf_rst, UInt<1>("h00")) @[dma_ctrl.scala 441:80]
|
||||
node _T_1239 = and(_T_1237, _T_1238) @[dma_ctrl.scala 441:78]
|
||||
reg _T_1240 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 441:47]
|
||||
_T_1240 <= _T_1239 @[dma_ctrl.scala 441:47]
|
||||
rdbuf_vld <= _T_1240 @[dma_ctrl.scala 441:13]
|
||||
node rdbuf_en = and(io.dma_axi.ar.valid, io.dma_axi.ar.ready) @[dma_ctrl.scala 424:59]
|
||||
node _T_1236 = eq(bus_cmd_write, UInt<1>("h00")) @[dma_ctrl.scala 425:44]
|
||||
node rdbuf_cmd_sent = and(axi_mstr_prty_en, _T_1236) @[dma_ctrl.scala 425:42]
|
||||
node _T_1237 = bits(rdbuf_cmd_sent, 0, 0) @[dma_ctrl.scala 426:54]
|
||||
node _T_1238 = eq(rdbuf_en, UInt<1>("h00")) @[dma_ctrl.scala 426:63]
|
||||
node rdbuf_rst = and(_T_1237, _T_1238) @[dma_ctrl.scala 426:61]
|
||||
node _T_1239 = mux(rdbuf_en, UInt<1>("h01"), rdbuf_vld) @[dma_ctrl.scala 428:51]
|
||||
node _T_1240 = eq(rdbuf_rst, UInt<1>("h00")) @[dma_ctrl.scala 428:80]
|
||||
node _T_1241 = and(_T_1239, _T_1240) @[dma_ctrl.scala 428:78]
|
||||
reg _T_1242 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 428:47]
|
||||
_T_1242 <= _T_1241 @[dma_ctrl.scala 428:47]
|
||||
rdbuf_vld <= _T_1242 @[dma_ctrl.scala 428:13]
|
||||
reg rdbuf_tag : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when rdbuf_en : @[Reg.scala 28:19]
|
||||
rdbuf_tag <= io.dma_axi.ar.bits.id @[Reg.scala 28:23]
|
||||
|
|
@ -108899,102 +108901,102 @@ circuit quasar_wrapper :
|
|||
when rdbuf_en : @[Reg.scala 28:19]
|
||||
rdbuf_sz <= io.dma_axi.ar.bits.size @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
node _T_1241 = and(rdbuf_en, io.dma_bus_clk_en) @[dma_ctrl.scala 451:61]
|
||||
inst rvclkhdr_12 of rvclkhdr_846 @[lib.scala 368:23]
|
||||
rvclkhdr_12.clock <= clock
|
||||
rvclkhdr_12.reset <= reset
|
||||
rvclkhdr_12.io.clk <= clock @[lib.scala 370:18]
|
||||
rvclkhdr_12.io.en <= _T_1241 @[lib.scala 371:17]
|
||||
rvclkhdr_12.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||||
reg rdbuf_addr : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||||
node _T_1243 = and(rdbuf_en, io.dma_bus_clk_en) @[dma_ctrl.scala 438:61]
|
||||
inst rvclkhdr_15 of rvclkhdr_846 @[lib.scala 368:23]
|
||||
rvclkhdr_15.clock <= clock
|
||||
rvclkhdr_15.reset <= reset
|
||||
rvclkhdr_15.io.clk <= clock @[lib.scala 370:18]
|
||||
rvclkhdr_15.io.en <= _T_1243 @[lib.scala 371:17]
|
||||
rvclkhdr_15.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
|
||||
reg rdbuf_addr : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
|
||||
rdbuf_addr <= io.dma_axi.ar.bits.addr @[lib.scala 374:16]
|
||||
node _T_1242 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[dma_ctrl.scala 453:44]
|
||||
node _T_1243 = and(wrbuf_vld, _T_1242) @[dma_ctrl.scala 453:42]
|
||||
node _T_1244 = not(_T_1243) @[dma_ctrl.scala 453:30]
|
||||
io.dma_axi.aw.ready <= _T_1244 @[dma_ctrl.scala 453:27]
|
||||
node _T_1245 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[dma_ctrl.scala 454:49]
|
||||
node _T_1246 = and(wrbuf_data_vld, _T_1245) @[dma_ctrl.scala 454:47]
|
||||
node _T_1247 = not(_T_1246) @[dma_ctrl.scala 454:30]
|
||||
io.dma_axi.w.ready <= _T_1247 @[dma_ctrl.scala 454:27]
|
||||
node _T_1248 = eq(rdbuf_cmd_sent, UInt<1>("h00")) @[dma_ctrl.scala 455:44]
|
||||
node _T_1249 = and(rdbuf_vld, _T_1248) @[dma_ctrl.scala 455:42]
|
||||
node _T_1250 = not(_T_1249) @[dma_ctrl.scala 455:30]
|
||||
io.dma_axi.ar.ready <= _T_1250 @[dma_ctrl.scala 455:27]
|
||||
node _T_1251 = and(wrbuf_vld, wrbuf_data_vld) @[dma_ctrl.scala 459:51]
|
||||
node _T_1252 = or(_T_1251, rdbuf_vld) @[dma_ctrl.scala 459:69]
|
||||
bus_cmd_valid <= _T_1252 @[dma_ctrl.scala 459:37]
|
||||
node _T_1253 = and(bus_cmd_valid, dma_fifo_ready) @[dma_ctrl.scala 460:54]
|
||||
axi_mstr_prty_en <= _T_1253 @[dma_ctrl.scala 460:37]
|
||||
bus_cmd_write <= axi_mstr_sel @[dma_ctrl.scala 461:37]
|
||||
bus_cmd_posted_write <= UInt<1>("h00") @[dma_ctrl.scala 462:25]
|
||||
node _T_1254 = bits(axi_mstr_sel, 0, 0) @[dma_ctrl.scala 463:57]
|
||||
node _T_1255 = mux(_T_1254, wrbuf_addr, rdbuf_addr) @[dma_ctrl.scala 463:43]
|
||||
bus_cmd_addr <= _T_1255 @[dma_ctrl.scala 463:37]
|
||||
node _T_1256 = bits(axi_mstr_sel, 0, 0) @[dma_ctrl.scala 464:59]
|
||||
node _T_1257 = mux(_T_1256, wrbuf_sz, rdbuf_sz) @[dma_ctrl.scala 464:45]
|
||||
bus_cmd_sz <= _T_1257 @[dma_ctrl.scala 464:39]
|
||||
bus_cmd_wdata <= wrbuf_data @[dma_ctrl.scala 465:37]
|
||||
bus_cmd_byteen <= wrbuf_byteen @[dma_ctrl.scala 466:37]
|
||||
node _T_1258 = bits(axi_mstr_sel, 0, 0) @[dma_ctrl.scala 467:57]
|
||||
node _T_1259 = mux(_T_1258, wrbuf_tag, rdbuf_tag) @[dma_ctrl.scala 467:43]
|
||||
bus_cmd_tag <= _T_1259 @[dma_ctrl.scala 467:37]
|
||||
bus_cmd_mid <= UInt<1>("h00") @[dma_ctrl.scala 468:37]
|
||||
bus_cmd_prty <= UInt<1>("h00") @[dma_ctrl.scala 469:37]
|
||||
node _T_1260 = and(wrbuf_vld, wrbuf_data_vld) @[dma_ctrl.scala 473:43]
|
||||
node _T_1261 = and(_T_1260, rdbuf_vld) @[dma_ctrl.scala 473:60]
|
||||
node _T_1262 = eq(_T_1261, UInt<1>("h01")) @[dma_ctrl.scala 473:73]
|
||||
node _T_1263 = and(wrbuf_vld, wrbuf_data_vld) @[dma_ctrl.scala 473:111]
|
||||
node _T_1264 = mux(_T_1262, axi_mstr_priority, _T_1263) @[dma_ctrl.scala 473:31]
|
||||
axi_mstr_sel <= _T_1264 @[dma_ctrl.scala 473:25]
|
||||
node axi_mstr_prty_in = not(axi_mstr_priority) @[dma_ctrl.scala 474:27]
|
||||
node _T_1265 = bits(axi_mstr_prty_en, 0, 0) @[dma_ctrl.scala 478:55]
|
||||
reg _T_1266 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_1265 : @[Reg.scala 28:19]
|
||||
_T_1266 <= axi_mstr_prty_in @[Reg.scala 28:23]
|
||||
node _T_1244 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[dma_ctrl.scala 440:44]
|
||||
node _T_1245 = and(wrbuf_vld, _T_1244) @[dma_ctrl.scala 440:42]
|
||||
node _T_1246 = not(_T_1245) @[dma_ctrl.scala 440:30]
|
||||
io.dma_axi.aw.ready <= _T_1246 @[dma_ctrl.scala 440:27]
|
||||
node _T_1247 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[dma_ctrl.scala 441:49]
|
||||
node _T_1248 = and(wrbuf_data_vld, _T_1247) @[dma_ctrl.scala 441:47]
|
||||
node _T_1249 = not(_T_1248) @[dma_ctrl.scala 441:30]
|
||||
io.dma_axi.w.ready <= _T_1249 @[dma_ctrl.scala 441:27]
|
||||
node _T_1250 = eq(rdbuf_cmd_sent, UInt<1>("h00")) @[dma_ctrl.scala 442:44]
|
||||
node _T_1251 = and(rdbuf_vld, _T_1250) @[dma_ctrl.scala 442:42]
|
||||
node _T_1252 = not(_T_1251) @[dma_ctrl.scala 442:30]
|
||||
io.dma_axi.ar.ready <= _T_1252 @[dma_ctrl.scala 442:27]
|
||||
node _T_1253 = and(wrbuf_vld, wrbuf_data_vld) @[dma_ctrl.scala 446:51]
|
||||
node _T_1254 = or(_T_1253, rdbuf_vld) @[dma_ctrl.scala 446:69]
|
||||
bus_cmd_valid <= _T_1254 @[dma_ctrl.scala 446:37]
|
||||
node _T_1255 = and(bus_cmd_valid, dma_fifo_ready) @[dma_ctrl.scala 447:54]
|
||||
axi_mstr_prty_en <= _T_1255 @[dma_ctrl.scala 447:37]
|
||||
bus_cmd_write <= axi_mstr_sel @[dma_ctrl.scala 448:37]
|
||||
bus_cmd_posted_write <= UInt<1>("h00") @[dma_ctrl.scala 449:25]
|
||||
node _T_1256 = bits(axi_mstr_sel, 0, 0) @[dma_ctrl.scala 450:57]
|
||||
node _T_1257 = mux(_T_1256, wrbuf_addr, rdbuf_addr) @[dma_ctrl.scala 450:43]
|
||||
bus_cmd_addr <= _T_1257 @[dma_ctrl.scala 450:37]
|
||||
node _T_1258 = bits(axi_mstr_sel, 0, 0) @[dma_ctrl.scala 451:59]
|
||||
node _T_1259 = mux(_T_1258, wrbuf_sz, rdbuf_sz) @[dma_ctrl.scala 451:45]
|
||||
bus_cmd_sz <= _T_1259 @[dma_ctrl.scala 451:39]
|
||||
bus_cmd_wdata <= wrbuf_data @[dma_ctrl.scala 452:37]
|
||||
bus_cmd_byteen <= wrbuf_byteen @[dma_ctrl.scala 453:37]
|
||||
node _T_1260 = bits(axi_mstr_sel, 0, 0) @[dma_ctrl.scala 454:57]
|
||||
node _T_1261 = mux(_T_1260, wrbuf_tag, rdbuf_tag) @[dma_ctrl.scala 454:43]
|
||||
bus_cmd_tag <= _T_1261 @[dma_ctrl.scala 454:37]
|
||||
bus_cmd_mid <= UInt<1>("h00") @[dma_ctrl.scala 455:37]
|
||||
bus_cmd_prty <= UInt<1>("h00") @[dma_ctrl.scala 456:37]
|
||||
node _T_1262 = and(wrbuf_vld, wrbuf_data_vld) @[dma_ctrl.scala 460:43]
|
||||
node _T_1263 = and(_T_1262, rdbuf_vld) @[dma_ctrl.scala 460:60]
|
||||
node _T_1264 = eq(_T_1263, UInt<1>("h01")) @[dma_ctrl.scala 460:73]
|
||||
node _T_1265 = and(wrbuf_vld, wrbuf_data_vld) @[dma_ctrl.scala 460:111]
|
||||
node _T_1266 = mux(_T_1264, axi_mstr_priority, _T_1265) @[dma_ctrl.scala 460:31]
|
||||
axi_mstr_sel <= _T_1266 @[dma_ctrl.scala 460:25]
|
||||
node axi_mstr_prty_in = not(axi_mstr_priority) @[dma_ctrl.scala 461:27]
|
||||
node _T_1267 = bits(axi_mstr_prty_en, 0, 0) @[dma_ctrl.scala 465:55]
|
||||
reg _T_1268 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_1267 : @[Reg.scala 28:19]
|
||||
_T_1268 <= axi_mstr_prty_in @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
axi_mstr_priority <= _T_1266 @[dma_ctrl.scala 477:27]
|
||||
node _T_1267 = dshr(fifo_valid, RspPtr) @[dma_ctrl.scala 481:39]
|
||||
node _T_1268 = bits(_T_1267, 0, 0) @[dma_ctrl.scala 481:39]
|
||||
node _T_1269 = dshr(fifo_dbg, RspPtr) @[dma_ctrl.scala 481:59]
|
||||
node _T_1270 = bits(_T_1269, 0, 0) @[dma_ctrl.scala 481:59]
|
||||
node _T_1271 = eq(_T_1270, UInt<1>("h00")) @[dma_ctrl.scala 481:50]
|
||||
node _T_1272 = and(_T_1268, _T_1271) @[dma_ctrl.scala 481:48]
|
||||
node _T_1273 = dshr(fifo_done_bus, RspPtr) @[dma_ctrl.scala 481:83]
|
||||
node _T_1274 = bits(_T_1273, 0, 0) @[dma_ctrl.scala 481:83]
|
||||
node axi_rsp_valid = and(_T_1272, _T_1274) @[dma_ctrl.scala 481:68]
|
||||
node _T_1275 = dshr(fifo_write, RspPtr) @[dma_ctrl.scala 483:39]
|
||||
node axi_rsp_write = bits(_T_1275, 0, 0) @[dma_ctrl.scala 483:39]
|
||||
node _T_1276 = bits(fifo_error[RspPtr], 0, 0) @[dma_ctrl.scala 484:51]
|
||||
node _T_1277 = bits(fifo_error[RspPtr], 1, 1) @[dma_ctrl.scala 484:83]
|
||||
node _T_1278 = mux(_T_1277, UInt<2>("h03"), UInt<1>("h00")) @[dma_ctrl.scala 484:64]
|
||||
node axi_rsp_error = mux(_T_1276, UInt<2>("h02"), _T_1278) @[dma_ctrl.scala 484:32]
|
||||
node _T_1279 = and(axi_rsp_valid, axi_rsp_write) @[dma_ctrl.scala 490:44]
|
||||
io.dma_axi.b.valid <= _T_1279 @[dma_ctrl.scala 490:27]
|
||||
node _T_1280 = bits(axi_rsp_error, 1, 0) @[dma_ctrl.scala 491:57]
|
||||
io.dma_axi.b.bits.resp <= _T_1280 @[dma_ctrl.scala 491:41]
|
||||
io.dma_axi.b.bits.id <= fifo_tag[RspPtr] @[dma_ctrl.scala 492:33]
|
||||
node _T_1281 = eq(axi_rsp_write, UInt<1>("h00")) @[dma_ctrl.scala 494:46]
|
||||
node _T_1282 = and(axi_rsp_valid, _T_1281) @[dma_ctrl.scala 494:44]
|
||||
io.dma_axi.r.valid <= _T_1282 @[dma_ctrl.scala 494:27]
|
||||
io.dma_axi.r.bits.resp <= axi_rsp_error @[dma_ctrl.scala 495:41]
|
||||
node _T_1283 = bits(fifo_data[RspPtr], 63, 0) @[dma_ctrl.scala 496:59]
|
||||
io.dma_axi.r.bits.data <= _T_1283 @[dma_ctrl.scala 496:43]
|
||||
io.dma_axi.r.bits.last <= UInt<1>("h01") @[dma_ctrl.scala 497:41]
|
||||
io.dma_axi.r.bits.id <= fifo_tag[RspPtr] @[dma_ctrl.scala 498:37]
|
||||
bus_posted_write_done <= UInt<1>("h00") @[dma_ctrl.scala 500:25]
|
||||
node _T_1284 = or(io.dma_axi.b.valid, io.dma_axi.r.valid) @[dma_ctrl.scala 501:60]
|
||||
bus_rsp_valid <= _T_1284 @[dma_ctrl.scala 501:37]
|
||||
node _T_1285 = and(io.dma_axi.b.valid, io.dma_axi.b.ready) @[dma_ctrl.scala 502:61]
|
||||
node _T_1286 = and(io.dma_axi.r.valid, io.dma_axi.r.ready) @[dma_ctrl.scala 502:105]
|
||||
node _T_1287 = or(_T_1285, _T_1286) @[dma_ctrl.scala 502:83]
|
||||
bus_rsp_sent <= _T_1287 @[dma_ctrl.scala 502:37]
|
||||
io.lsu_dma.dma_dccm_ctl.dma_mem_addr <= io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[dma_ctrl.scala 503:40]
|
||||
io.lsu_dma.dma_dccm_ctl.dma_mem_wdata <= io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[dma_ctrl.scala 504:41]
|
||||
io.ifu_dma.dma_mem_ctl.dma_mem_sz <= io.lsu_dma.dma_lsc_ctl.dma_mem_sz @[dma_ctrl.scala 505:37]
|
||||
io.ifu_dma.dma_mem_ctl.dma_mem_addr <= io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[dma_ctrl.scala 506:39]
|
||||
io.ifu_dma.dma_mem_ctl.dma_mem_wdata <= io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[dma_ctrl.scala 507:40]
|
||||
io.ifu_dma.dma_mem_ctl.dma_mem_write <= io.lsu_dma.dma_lsc_ctl.dma_mem_write @[dma_ctrl.scala 508:40]
|
||||
io.ifu_dma.dma_mem_ctl.dma_mem_tag <= io.lsu_dma.dma_mem_tag @[dma_ctrl.scala 509:38]
|
||||
axi_mstr_priority <= _T_1268 @[dma_ctrl.scala 464:27]
|
||||
node _T_1269 = dshr(fifo_valid, RspPtr) @[dma_ctrl.scala 468:39]
|
||||
node _T_1270 = bits(_T_1269, 0, 0) @[dma_ctrl.scala 468:39]
|
||||
node _T_1271 = dshr(fifo_dbg, RspPtr) @[dma_ctrl.scala 468:59]
|
||||
node _T_1272 = bits(_T_1271, 0, 0) @[dma_ctrl.scala 468:59]
|
||||
node _T_1273 = eq(_T_1272, UInt<1>("h00")) @[dma_ctrl.scala 468:50]
|
||||
node _T_1274 = and(_T_1270, _T_1273) @[dma_ctrl.scala 468:48]
|
||||
node _T_1275 = dshr(fifo_done_bus, RspPtr) @[dma_ctrl.scala 468:83]
|
||||
node _T_1276 = bits(_T_1275, 0, 0) @[dma_ctrl.scala 468:83]
|
||||
node axi_rsp_valid = and(_T_1274, _T_1276) @[dma_ctrl.scala 468:68]
|
||||
node _T_1277 = dshr(fifo_write, RspPtr) @[dma_ctrl.scala 470:39]
|
||||
node axi_rsp_write = bits(_T_1277, 0, 0) @[dma_ctrl.scala 470:39]
|
||||
node _T_1278 = bits(fifo_error[RspPtr], 0, 0) @[dma_ctrl.scala 471:51]
|
||||
node _T_1279 = bits(fifo_error[RspPtr], 1, 1) @[dma_ctrl.scala 471:83]
|
||||
node _T_1280 = mux(_T_1279, UInt<2>("h03"), UInt<1>("h00")) @[dma_ctrl.scala 471:64]
|
||||
node axi_rsp_error = mux(_T_1278, UInt<2>("h02"), _T_1280) @[dma_ctrl.scala 471:32]
|
||||
node _T_1281 = and(axi_rsp_valid, axi_rsp_write) @[dma_ctrl.scala 477:44]
|
||||
io.dma_axi.b.valid <= _T_1281 @[dma_ctrl.scala 477:27]
|
||||
node _T_1282 = bits(axi_rsp_error, 1, 0) @[dma_ctrl.scala 478:57]
|
||||
io.dma_axi.b.bits.resp <= _T_1282 @[dma_ctrl.scala 478:41]
|
||||
io.dma_axi.b.bits.id <= fifo_tag[RspPtr] @[dma_ctrl.scala 479:33]
|
||||
node _T_1283 = eq(axi_rsp_write, UInt<1>("h00")) @[dma_ctrl.scala 481:46]
|
||||
node _T_1284 = and(axi_rsp_valid, _T_1283) @[dma_ctrl.scala 481:44]
|
||||
io.dma_axi.r.valid <= _T_1284 @[dma_ctrl.scala 481:27]
|
||||
io.dma_axi.r.bits.resp <= axi_rsp_error @[dma_ctrl.scala 482:41]
|
||||
node _T_1285 = bits(fifo_data[RspPtr], 63, 0) @[dma_ctrl.scala 483:59]
|
||||
io.dma_axi.r.bits.data <= _T_1285 @[dma_ctrl.scala 483:43]
|
||||
io.dma_axi.r.bits.last <= UInt<1>("h01") @[dma_ctrl.scala 484:41]
|
||||
io.dma_axi.r.bits.id <= fifo_tag[RspPtr] @[dma_ctrl.scala 485:37]
|
||||
bus_posted_write_done <= UInt<1>("h00") @[dma_ctrl.scala 487:25]
|
||||
node _T_1286 = or(io.dma_axi.b.valid, io.dma_axi.r.valid) @[dma_ctrl.scala 488:60]
|
||||
bus_rsp_valid <= _T_1286 @[dma_ctrl.scala 488:37]
|
||||
node _T_1287 = and(io.dma_axi.b.valid, io.dma_axi.b.ready) @[dma_ctrl.scala 489:61]
|
||||
node _T_1288 = and(io.dma_axi.r.valid, io.dma_axi.r.ready) @[dma_ctrl.scala 489:105]
|
||||
node _T_1289 = or(_T_1287, _T_1288) @[dma_ctrl.scala 489:83]
|
||||
bus_rsp_sent <= _T_1289 @[dma_ctrl.scala 489:37]
|
||||
io.lsu_dma.dma_dccm_ctl.dma_mem_addr <= io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[dma_ctrl.scala 490:40]
|
||||
io.lsu_dma.dma_dccm_ctl.dma_mem_wdata <= io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[dma_ctrl.scala 491:41]
|
||||
io.ifu_dma.dma_mem_ctl.dma_mem_sz <= io.lsu_dma.dma_lsc_ctl.dma_mem_sz @[dma_ctrl.scala 492:37]
|
||||
io.ifu_dma.dma_mem_ctl.dma_mem_addr <= io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[dma_ctrl.scala 493:39]
|
||||
io.ifu_dma.dma_mem_ctl.dma_mem_wdata <= io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[dma_ctrl.scala 494:40]
|
||||
io.ifu_dma.dma_mem_ctl.dma_mem_write <= io.lsu_dma.dma_lsc_ctl.dma_mem_write @[dma_ctrl.scala 495:40]
|
||||
io.ifu_dma.dma_mem_ctl.dma_mem_tag <= io.lsu_dma.dma_mem_tag @[dma_ctrl.scala 496:38]
|
||||
|
||||
extmodule gated_latch_847 :
|
||||
output Q : Clock
|
||||
|
|
|
|||
274
quasar_wrapper.v
274
quasar_wrapper.v
|
|
@ -78495,31 +78495,31 @@ module dma_ctrl(
|
|||
wire rvclkhdr_9_io_clk; // @[lib.scala 368:23]
|
||||
wire rvclkhdr_9_io_en; // @[lib.scala 368:23]
|
||||
wire rvclkhdr_9_io_scan_mode; // @[lib.scala 368:23]
|
||||
wire dma_buffer_c1cgc_io_l1clk; // @[dma_ctrl.scala 389:32]
|
||||
wire dma_buffer_c1cgc_io_clk; // @[dma_ctrl.scala 389:32]
|
||||
wire dma_buffer_c1cgc_io_en; // @[dma_ctrl.scala 389:32]
|
||||
wire dma_buffer_c1cgc_io_scan_mode; // @[dma_ctrl.scala 389:32]
|
||||
wire dma_free_cgc_io_l1clk; // @[dma_ctrl.scala 395:28]
|
||||
wire dma_free_cgc_io_clk; // @[dma_ctrl.scala 395:28]
|
||||
wire dma_free_cgc_io_en; // @[dma_ctrl.scala 395:28]
|
||||
wire dma_free_cgc_io_scan_mode; // @[dma_ctrl.scala 395:28]
|
||||
wire dma_bus_cgc_io_l1clk; // @[dma_ctrl.scala 401:27]
|
||||
wire dma_bus_cgc_io_clk; // @[dma_ctrl.scala 401:27]
|
||||
wire dma_bus_cgc_io_en; // @[dma_ctrl.scala 401:27]
|
||||
wire dma_bus_cgc_io_scan_mode; // @[dma_ctrl.scala 401:27]
|
||||
wire rvclkhdr_10_io_l1clk; // @[lib.scala 368:23]
|
||||
wire rvclkhdr_10_io_clk; // @[lib.scala 368:23]
|
||||
wire rvclkhdr_10_io_en; // @[lib.scala 368:23]
|
||||
wire rvclkhdr_10_io_scan_mode; // @[lib.scala 368:23]
|
||||
wire rvclkhdr_11_io_l1clk; // @[lib.scala 368:23]
|
||||
wire rvclkhdr_11_io_clk; // @[lib.scala 368:23]
|
||||
wire rvclkhdr_11_io_en; // @[lib.scala 368:23]
|
||||
wire rvclkhdr_11_io_scan_mode; // @[lib.scala 368:23]
|
||||
wire rvclkhdr_12_io_l1clk; // @[lib.scala 368:23]
|
||||
wire rvclkhdr_12_io_clk; // @[lib.scala 368:23]
|
||||
wire rvclkhdr_12_io_en; // @[lib.scala 368:23]
|
||||
wire rvclkhdr_12_io_scan_mode; // @[lib.scala 368:23]
|
||||
wire dma_free_clk = dma_free_cgc_io_l1clk; // @[dma_ctrl.scala 168:26 dma_ctrl.scala 399:29]
|
||||
wire rvclkhdr_10_io_l1clk; // @[lib.scala 343:22]
|
||||
wire rvclkhdr_10_io_clk; // @[lib.scala 343:22]
|
||||
wire rvclkhdr_10_io_en; // @[lib.scala 343:22]
|
||||
wire rvclkhdr_10_io_scan_mode; // @[lib.scala 343:22]
|
||||
wire rvclkhdr_11_io_l1clk; // @[lib.scala 343:22]
|
||||
wire rvclkhdr_11_io_clk; // @[lib.scala 343:22]
|
||||
wire rvclkhdr_11_io_en; // @[lib.scala 343:22]
|
||||
wire rvclkhdr_11_io_scan_mode; // @[lib.scala 343:22]
|
||||
wire rvclkhdr_12_io_l1clk; // @[lib.scala 343:22]
|
||||
wire rvclkhdr_12_io_clk; // @[lib.scala 343:22]
|
||||
wire rvclkhdr_12_io_en; // @[lib.scala 343:22]
|
||||
wire rvclkhdr_12_io_scan_mode; // @[lib.scala 343:22]
|
||||
wire rvclkhdr_13_io_l1clk; // @[lib.scala 368:23]
|
||||
wire rvclkhdr_13_io_clk; // @[lib.scala 368:23]
|
||||
wire rvclkhdr_13_io_en; // @[lib.scala 368:23]
|
||||
wire rvclkhdr_13_io_scan_mode; // @[lib.scala 368:23]
|
||||
wire rvclkhdr_14_io_l1clk; // @[lib.scala 368:23]
|
||||
wire rvclkhdr_14_io_clk; // @[lib.scala 368:23]
|
||||
wire rvclkhdr_14_io_en; // @[lib.scala 368:23]
|
||||
wire rvclkhdr_14_io_scan_mode; // @[lib.scala 368:23]
|
||||
wire rvclkhdr_15_io_l1clk; // @[lib.scala 368:23]
|
||||
wire rvclkhdr_15_io_clk; // @[lib.scala 368:23]
|
||||
wire rvclkhdr_15_io_en; // @[lib.scala 368:23]
|
||||
wire rvclkhdr_15_io_scan_mode; // @[lib.scala 368:23]
|
||||
wire dma_free_clk = rvclkhdr_11_io_l1clk; // @[dma_ctrl.scala 168:26 dma_ctrl.scala 390:21]
|
||||
reg [2:0] RdPtr; // @[Reg.scala 27:20]
|
||||
reg [31:0] fifo_addr_4; // @[lib.scala 374:16]
|
||||
reg [31:0] fifo_addr_3; // @[lib.scala 374:16]
|
||||
|
|
@ -78533,17 +78533,17 @@ module dma_ctrl(
|
|||
wire dma_mem_addr_in_dccm = dma_mem_addr_int[31:16] == 16'hf004; // @[lib.scala 361:39]
|
||||
wire dma_mem_addr_in_pic = dma_mem_addr_int[31:15] == 17'h1e018; // @[lib.scala 361:39]
|
||||
wire dma_mem_addr_in_iccm = dma_mem_addr_int[31:16] == 16'hee00; // @[lib.scala 361:39]
|
||||
wire dma_bus_clk = dma_bus_cgc_io_l1clk; // @[dma_ctrl.scala 170:25 dma_ctrl.scala 405:28]
|
||||
reg wrbuf_vld; // @[dma_ctrl.scala 415:59]
|
||||
reg wrbuf_data_vld; // @[dma_ctrl.scala 417:59]
|
||||
wire _T_1260 = wrbuf_vld & wrbuf_data_vld; // @[dma_ctrl.scala 473:43]
|
||||
reg rdbuf_vld; // @[dma_ctrl.scala 441:47]
|
||||
wire _T_1261 = _T_1260 & rdbuf_vld; // @[dma_ctrl.scala 473:60]
|
||||
wire dma_bus_clk = rvclkhdr_12_io_l1clk; // @[dma_ctrl.scala 170:25 dma_ctrl.scala 391:21]
|
||||
reg wrbuf_vld; // @[dma_ctrl.scala 402:59]
|
||||
reg wrbuf_data_vld; // @[dma_ctrl.scala 404:59]
|
||||
wire _T_1262 = wrbuf_vld & wrbuf_data_vld; // @[dma_ctrl.scala 460:43]
|
||||
reg rdbuf_vld; // @[dma_ctrl.scala 428:47]
|
||||
wire _T_1263 = _T_1262 & rdbuf_vld; // @[dma_ctrl.scala 460:60]
|
||||
reg axi_mstr_priority; // @[Reg.scala 27:20]
|
||||
wire axi_mstr_sel = _T_1261 ? axi_mstr_priority : _T_1260; // @[dma_ctrl.scala 473:31]
|
||||
wire axi_mstr_sel = _T_1263 ? axi_mstr_priority : _T_1262; // @[dma_ctrl.scala 460:31]
|
||||
reg [31:0] wrbuf_addr; // @[lib.scala 374:16]
|
||||
reg [31:0] rdbuf_addr; // @[lib.scala 374:16]
|
||||
wire [31:0] bus_cmd_addr = axi_mstr_sel ? wrbuf_addr : rdbuf_addr; // @[dma_ctrl.scala 463:43]
|
||||
wire [31:0] bus_cmd_addr = axi_mstr_sel ? wrbuf_addr : rdbuf_addr; // @[dma_ctrl.scala 450:43]
|
||||
wire [2:0] _GEN_90 = {{2'd0}, io_dbg_dma_dbg_ib_dbg_cmd_addr[2]}; // @[dma_ctrl.scala 195:91]
|
||||
wire [3:0] _T_17 = 3'h4 * _GEN_90; // @[dma_ctrl.scala 195:91]
|
||||
wire [18:0] _T_18 = 19'hf << _T_17; // @[dma_ctrl.scala 195:83]
|
||||
|
|
@ -78552,15 +78552,15 @@ module dma_ctrl(
|
|||
wire [2:0] _T_23 = {1'h0,io_dbg_cmd_size}; // @[Cat.scala 29:58]
|
||||
reg [2:0] wrbuf_sz; // @[Reg.scala 27:20]
|
||||
reg [2:0] rdbuf_sz; // @[Reg.scala 27:20]
|
||||
wire [2:0] bus_cmd_sz = axi_mstr_sel ? wrbuf_sz : rdbuf_sz; // @[dma_ctrl.scala 464:45]
|
||||
wire [2:0] bus_cmd_sz = axi_mstr_sel ? wrbuf_sz : rdbuf_sz; // @[dma_ctrl.scala 451:45]
|
||||
wire [2:0] fifo_sz_in = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_23 : bus_cmd_sz; // @[dma_ctrl.scala 197:33]
|
||||
wire fifo_write_in = io_dbg_dma_dbg_ib_dbg_cmd_valid ? io_dbg_dma_dbg_ib_dbg_cmd_write : axi_mstr_sel; // @[dma_ctrl.scala 199:33]
|
||||
wire bus_cmd_valid = _T_1260 | rdbuf_vld; // @[dma_ctrl.scala 459:69]
|
||||
wire bus_cmd_valid = _T_1262 | rdbuf_vld; // @[dma_ctrl.scala 446:69]
|
||||
reg fifo_full; // @[dma_ctrl.scala 373:12]
|
||||
reg dbg_dma_bubble_bus; // @[dma_ctrl.scala 377:12]
|
||||
wire _T_989 = fifo_full | dbg_dma_bubble_bus; // @[dma_ctrl.scala 299:39]
|
||||
wire dma_fifo_ready = ~_T_989; // @[dma_ctrl.scala 299:27]
|
||||
wire axi_mstr_prty_en = bus_cmd_valid & dma_fifo_ready; // @[dma_ctrl.scala 460:54]
|
||||
wire axi_mstr_prty_en = bus_cmd_valid & dma_fifo_ready; // @[dma_ctrl.scala 447:54]
|
||||
wire _T_28 = axi_mstr_prty_en & io_dma_bus_clk_en; // @[dma_ctrl.scala 206:80]
|
||||
wire _T_31 = io_dbg_dma_dbg_ib_dbg_cmd_valid & io_dbg_dma_dbg_ib_dbg_cmd_type[1]; // @[dma_ctrl.scala 206:136]
|
||||
wire _T_32 = _T_28 | _T_31; // @[dma_ctrl.scala 206:101]
|
||||
|
|
@ -78597,7 +78597,7 @@ module dma_ctrl(
|
|||
wire [4:0] _T_992 = fifo_done >> RdPtr; // @[dma_ctrl.scala 303:58]
|
||||
wire _T_994 = ~_T_992[0]; // @[dma_ctrl.scala 303:48]
|
||||
wire _T_995 = _T_990[0] & _T_994; // @[dma_ctrl.scala 303:46]
|
||||
wire dma_buffer_c1_clk = dma_buffer_c1cgc_io_l1clk; // @[dma_ctrl.scala 172:31 dma_ctrl.scala 393:33]
|
||||
wire dma_buffer_c1_clk = rvclkhdr_10_io_l1clk; // @[dma_ctrl.scala 172:31 dma_ctrl.scala 389:21]
|
||||
reg _T_886; // @[Reg.scala 27:20]
|
||||
reg _T_884; // @[Reg.scala 27:20]
|
||||
reg _T_882; // @[Reg.scala 27:20]
|
||||
|
|
@ -78850,7 +78850,7 @@ module dma_ctrl(
|
|||
wire _T_399 = fifo_done_en[4] | fifo_done[4]; // @[dma_ctrl.scala 218:75]
|
||||
wire _T_400 = _T_399 & io_dma_bus_clk_en; // @[dma_ctrl.scala 218:91]
|
||||
wire [4:0] fifo_done_bus_en = {_T_400,_T_396,_T_392,_T_388,_T_384}; // @[Cat.scala 29:58]
|
||||
wire bus_rsp_sent = io_dma_axi_b_valid | io_dma_axi_r_valid; // @[dma_ctrl.scala 502:83]
|
||||
wire bus_rsp_sent = io_dma_axi_b_valid | io_dma_axi_r_valid; // @[dma_ctrl.scala 489:83]
|
||||
wire _T_406 = bus_rsp_sent & io_dma_bus_clk_en; // @[dma_ctrl.scala 220:99]
|
||||
wire _T_407 = _T_406 | io_dma_dbg_cmd_done; // @[dma_ctrl.scala 220:120]
|
||||
reg [2:0] RspPtr; // @[Reg.scala 27:20]
|
||||
|
|
@ -79003,38 +79003,38 @@ module dma_ctrl(
|
|||
wire _T_1216 = _T_1215 | io_dma_dbg_cmd_done; // @[dma_ctrl.scala 387:94]
|
||||
wire _T_1217 = _T_1216 | dma_dbg_cmd_done_q; // @[dma_ctrl.scala 387:116]
|
||||
wire _T_1219 = _T_1217 | _T_1143; // @[dma_ctrl.scala 387:137]
|
||||
wire wrbuf_en = io_dma_axi_aw_valid & io_dma_axi_aw_ready; // @[dma_ctrl.scala 409:47]
|
||||
wire wrbuf_data_en = io_dma_axi_w_valid & io_dma_axi_w_ready; // @[dma_ctrl.scala 410:46]
|
||||
wire wrbuf_cmd_sent = axi_mstr_prty_en & axi_mstr_sel; // @[dma_ctrl.scala 411:40]
|
||||
wire _T_1221 = ~wrbuf_en; // @[dma_ctrl.scala 412:51]
|
||||
wire wrbuf_rst = wrbuf_cmd_sent & _T_1221; // @[dma_ctrl.scala 412:49]
|
||||
wire _T_1223 = ~wrbuf_data_en; // @[dma_ctrl.scala 413:51]
|
||||
wire wrbuf_data_rst = wrbuf_cmd_sent & _T_1223; // @[dma_ctrl.scala 413:49]
|
||||
wire _T_1224 = wrbuf_en | wrbuf_vld; // @[dma_ctrl.scala 415:63]
|
||||
wire _T_1225 = ~wrbuf_rst; // @[dma_ctrl.scala 415:92]
|
||||
wire _T_1228 = wrbuf_data_en | wrbuf_data_vld; // @[dma_ctrl.scala 417:63]
|
||||
wire _T_1229 = ~wrbuf_data_rst; // @[dma_ctrl.scala 417:102]
|
||||
wire rdbuf_en = io_dma_axi_ar_valid & io_dma_axi_ar_ready; // @[dma_ctrl.scala 437:59]
|
||||
wire _T_1234 = ~axi_mstr_sel; // @[dma_ctrl.scala 438:44]
|
||||
wire rdbuf_cmd_sent = axi_mstr_prty_en & _T_1234; // @[dma_ctrl.scala 438:42]
|
||||
wire _T_1236 = ~rdbuf_en; // @[dma_ctrl.scala 439:63]
|
||||
wire rdbuf_rst = rdbuf_cmd_sent & _T_1236; // @[dma_ctrl.scala 439:61]
|
||||
wire _T_1237 = rdbuf_en | rdbuf_vld; // @[dma_ctrl.scala 441:51]
|
||||
wire _T_1238 = ~rdbuf_rst; // @[dma_ctrl.scala 441:80]
|
||||
wire _T_1242 = ~wrbuf_cmd_sent; // @[dma_ctrl.scala 453:44]
|
||||
wire _T_1243 = wrbuf_vld & _T_1242; // @[dma_ctrl.scala 453:42]
|
||||
wire _T_1246 = wrbuf_data_vld & _T_1242; // @[dma_ctrl.scala 454:47]
|
||||
wire _T_1248 = ~rdbuf_cmd_sent; // @[dma_ctrl.scala 455:44]
|
||||
wire _T_1249 = rdbuf_vld & _T_1248; // @[dma_ctrl.scala 455:42]
|
||||
wire axi_mstr_prty_in = ~axi_mstr_priority; // @[dma_ctrl.scala 474:27]
|
||||
wire _T_1271 = ~_T_1108[0]; // @[dma_ctrl.scala 481:50]
|
||||
wire _T_1272 = _T_1106[0] & _T_1271; // @[dma_ctrl.scala 481:48]
|
||||
wire [4:0] _T_1273 = fifo_done_bus >> RspPtr; // @[dma_ctrl.scala 481:83]
|
||||
wire axi_rsp_valid = _T_1272 & _T_1273[0]; // @[dma_ctrl.scala 481:68]
|
||||
wire [4:0] _T_1275 = fifo_write >> RspPtr; // @[dma_ctrl.scala 483:39]
|
||||
wire axi_rsp_write = _T_1275[0]; // @[dma_ctrl.scala 483:39]
|
||||
wire [1:0] _T_1278 = _GEN_57[1] ? 2'h3 : 2'h0; // @[dma_ctrl.scala 484:64]
|
||||
wire _T_1281 = ~axi_rsp_write; // @[dma_ctrl.scala 494:46]
|
||||
wire wrbuf_en = io_dma_axi_aw_valid & io_dma_axi_aw_ready; // @[dma_ctrl.scala 396:47]
|
||||
wire wrbuf_data_en = io_dma_axi_w_valid & io_dma_axi_w_ready; // @[dma_ctrl.scala 397:46]
|
||||
wire wrbuf_cmd_sent = axi_mstr_prty_en & axi_mstr_sel; // @[dma_ctrl.scala 398:40]
|
||||
wire _T_1223 = ~wrbuf_en; // @[dma_ctrl.scala 399:51]
|
||||
wire wrbuf_rst = wrbuf_cmd_sent & _T_1223; // @[dma_ctrl.scala 399:49]
|
||||
wire _T_1225 = ~wrbuf_data_en; // @[dma_ctrl.scala 400:51]
|
||||
wire wrbuf_data_rst = wrbuf_cmd_sent & _T_1225; // @[dma_ctrl.scala 400:49]
|
||||
wire _T_1226 = wrbuf_en | wrbuf_vld; // @[dma_ctrl.scala 402:63]
|
||||
wire _T_1227 = ~wrbuf_rst; // @[dma_ctrl.scala 402:92]
|
||||
wire _T_1230 = wrbuf_data_en | wrbuf_data_vld; // @[dma_ctrl.scala 404:63]
|
||||
wire _T_1231 = ~wrbuf_data_rst; // @[dma_ctrl.scala 404:102]
|
||||
wire rdbuf_en = io_dma_axi_ar_valid & io_dma_axi_ar_ready; // @[dma_ctrl.scala 424:59]
|
||||
wire _T_1236 = ~axi_mstr_sel; // @[dma_ctrl.scala 425:44]
|
||||
wire rdbuf_cmd_sent = axi_mstr_prty_en & _T_1236; // @[dma_ctrl.scala 425:42]
|
||||
wire _T_1238 = ~rdbuf_en; // @[dma_ctrl.scala 426:63]
|
||||
wire rdbuf_rst = rdbuf_cmd_sent & _T_1238; // @[dma_ctrl.scala 426:61]
|
||||
wire _T_1239 = rdbuf_en | rdbuf_vld; // @[dma_ctrl.scala 428:51]
|
||||
wire _T_1240 = ~rdbuf_rst; // @[dma_ctrl.scala 428:80]
|
||||
wire _T_1244 = ~wrbuf_cmd_sent; // @[dma_ctrl.scala 440:44]
|
||||
wire _T_1245 = wrbuf_vld & _T_1244; // @[dma_ctrl.scala 440:42]
|
||||
wire _T_1248 = wrbuf_data_vld & _T_1244; // @[dma_ctrl.scala 441:47]
|
||||
wire _T_1250 = ~rdbuf_cmd_sent; // @[dma_ctrl.scala 442:44]
|
||||
wire _T_1251 = rdbuf_vld & _T_1250; // @[dma_ctrl.scala 442:42]
|
||||
wire axi_mstr_prty_in = ~axi_mstr_priority; // @[dma_ctrl.scala 461:27]
|
||||
wire _T_1273 = ~_T_1108[0]; // @[dma_ctrl.scala 468:50]
|
||||
wire _T_1274 = _T_1106[0] & _T_1273; // @[dma_ctrl.scala 468:48]
|
||||
wire [4:0] _T_1275 = fifo_done_bus >> RspPtr; // @[dma_ctrl.scala 468:83]
|
||||
wire axi_rsp_valid = _T_1274 & _T_1275[0]; // @[dma_ctrl.scala 468:68]
|
||||
wire [4:0] _T_1277 = fifo_write >> RspPtr; // @[dma_ctrl.scala 470:39]
|
||||
wire axi_rsp_write = _T_1277[0]; // @[dma_ctrl.scala 470:39]
|
||||
wire [1:0] _T_1280 = _GEN_57[1] ? 2'h3 : 2'h0; // @[dma_ctrl.scala 471:64]
|
||||
wire _T_1283 = ~axi_rsp_write; // @[dma_ctrl.scala 481:46]
|
||||
rvclkhdr rvclkhdr ( // @[lib.scala 368:23]
|
||||
.io_l1clk(rvclkhdr_io_l1clk),
|
||||
.io_clk(rvclkhdr_io_clk),
|
||||
|
|
@ -79095,42 +79095,42 @@ module dma_ctrl(
|
|||
.io_en(rvclkhdr_9_io_en),
|
||||
.io_scan_mode(rvclkhdr_9_io_scan_mode)
|
||||
);
|
||||
rvclkhdr dma_buffer_c1cgc ( // @[dma_ctrl.scala 389:32]
|
||||
.io_l1clk(dma_buffer_c1cgc_io_l1clk),
|
||||
.io_clk(dma_buffer_c1cgc_io_clk),
|
||||
.io_en(dma_buffer_c1cgc_io_en),
|
||||
.io_scan_mode(dma_buffer_c1cgc_io_scan_mode)
|
||||
);
|
||||
rvclkhdr dma_free_cgc ( // @[dma_ctrl.scala 395:28]
|
||||
.io_l1clk(dma_free_cgc_io_l1clk),
|
||||
.io_clk(dma_free_cgc_io_clk),
|
||||
.io_en(dma_free_cgc_io_en),
|
||||
.io_scan_mode(dma_free_cgc_io_scan_mode)
|
||||
);
|
||||
rvclkhdr dma_bus_cgc ( // @[dma_ctrl.scala 401:27]
|
||||
.io_l1clk(dma_bus_cgc_io_l1clk),
|
||||
.io_clk(dma_bus_cgc_io_clk),
|
||||
.io_en(dma_bus_cgc_io_en),
|
||||
.io_scan_mode(dma_bus_cgc_io_scan_mode)
|
||||
);
|
||||
rvclkhdr rvclkhdr_10 ( // @[lib.scala 368:23]
|
||||
rvclkhdr rvclkhdr_10 ( // @[lib.scala 343:22]
|
||||
.io_l1clk(rvclkhdr_10_io_l1clk),
|
||||
.io_clk(rvclkhdr_10_io_clk),
|
||||
.io_en(rvclkhdr_10_io_en),
|
||||
.io_scan_mode(rvclkhdr_10_io_scan_mode)
|
||||
);
|
||||
rvclkhdr rvclkhdr_11 ( // @[lib.scala 368:23]
|
||||
rvclkhdr rvclkhdr_11 ( // @[lib.scala 343:22]
|
||||
.io_l1clk(rvclkhdr_11_io_l1clk),
|
||||
.io_clk(rvclkhdr_11_io_clk),
|
||||
.io_en(rvclkhdr_11_io_en),
|
||||
.io_scan_mode(rvclkhdr_11_io_scan_mode)
|
||||
);
|
||||
rvclkhdr rvclkhdr_12 ( // @[lib.scala 368:23]
|
||||
rvclkhdr rvclkhdr_12 ( // @[lib.scala 343:22]
|
||||
.io_l1clk(rvclkhdr_12_io_l1clk),
|
||||
.io_clk(rvclkhdr_12_io_clk),
|
||||
.io_en(rvclkhdr_12_io_en),
|
||||
.io_scan_mode(rvclkhdr_12_io_scan_mode)
|
||||
);
|
||||
rvclkhdr rvclkhdr_13 ( // @[lib.scala 368:23]
|
||||
.io_l1clk(rvclkhdr_13_io_l1clk),
|
||||
.io_clk(rvclkhdr_13_io_clk),
|
||||
.io_en(rvclkhdr_13_io_en),
|
||||
.io_scan_mode(rvclkhdr_13_io_scan_mode)
|
||||
);
|
||||
rvclkhdr rvclkhdr_14 ( // @[lib.scala 368:23]
|
||||
.io_l1clk(rvclkhdr_14_io_l1clk),
|
||||
.io_clk(rvclkhdr_14_io_clk),
|
||||
.io_en(rvclkhdr_14_io_en),
|
||||
.io_scan_mode(rvclkhdr_14_io_scan_mode)
|
||||
);
|
||||
rvclkhdr rvclkhdr_15 ( // @[lib.scala 368:23]
|
||||
.io_l1clk(rvclkhdr_15_io_l1clk),
|
||||
.io_clk(rvclkhdr_15_io_clk),
|
||||
.io_en(rvclkhdr_15_io_en),
|
||||
.io_scan_mode(rvclkhdr_15_io_scan_mode)
|
||||
);
|
||||
assign io_dma_dbg_rddata = _GEN_47[2] ? _GEN_52[63:32] : _GEN_52[31:0]; // @[dma_ctrl.scala 325:25]
|
||||
assign io_dma_dbg_cmd_done = _T_1110 & _T_1111[0]; // @[dma_ctrl.scala 324:25]
|
||||
assign io_dma_dbg_cmd_fail = |_GEN_57; // @[dma_ctrl.scala 326:25]
|
||||
|
|
@ -79142,28 +79142,28 @@ module dma_ctrl(
|
|||
assign io_dec_dma_tlu_dma_dma_pmu_any_write = _T_165 & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 368:42]
|
||||
assign io_dec_dma_tlu_dma_dma_dccm_stall_any = _T_1137 & _T_1138; // @[dma_ctrl.scala 332:41]
|
||||
assign io_dec_dma_tlu_dma_dma_iccm_stall_any = io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[dma_ctrl.scala 334:41]
|
||||
assign io_dma_axi_aw_ready = ~_T_1243; // @[dma_ctrl.scala 453:27]
|
||||
assign io_dma_axi_w_ready = ~_T_1246; // @[dma_ctrl.scala 454:27]
|
||||
assign io_dma_axi_b_valid = axi_rsp_valid & axi_rsp_write; // @[dma_ctrl.scala 490:27]
|
||||
assign io_dma_axi_ar_ready = ~_T_1249; // @[dma_ctrl.scala 455:27]
|
||||
assign io_dma_axi_r_valid = axi_rsp_valid & _T_1281; // @[dma_ctrl.scala 494:27]
|
||||
assign io_dma_axi_r_bits_data = 3'h4 == RspPtr ? fifo_data_4 : _GEN_51; // @[dma_ctrl.scala 496:43]
|
||||
assign io_dma_axi_r_bits_resp = _GEN_57[0] ? 2'h2 : _T_1278; // @[dma_ctrl.scala 495:41]
|
||||
assign io_dma_axi_aw_ready = ~_T_1245; // @[dma_ctrl.scala 440:27]
|
||||
assign io_dma_axi_w_ready = ~_T_1248; // @[dma_ctrl.scala 441:27]
|
||||
assign io_dma_axi_b_valid = axi_rsp_valid & axi_rsp_write; // @[dma_ctrl.scala 477:27]
|
||||
assign io_dma_axi_ar_ready = ~_T_1251; // @[dma_ctrl.scala 442:27]
|
||||
assign io_dma_axi_r_valid = axi_rsp_valid & _T_1283; // @[dma_ctrl.scala 481:27]
|
||||
assign io_dma_axi_r_bits_data = 3'h4 == RspPtr ? fifo_data_4 : _GEN_51; // @[dma_ctrl.scala 483:43]
|
||||
assign io_dma_axi_r_bits_resp = _GEN_57[0] ? 2'h2 : _T_1280; // @[dma_ctrl.scala 482:41]
|
||||
assign io_lsu_dma_dma_lsc_ctl_dma_dccm_req = _T_1137 & io_lsu_dma_dccm_ready; // @[dma_ctrl.scala 352:40]
|
||||
assign io_lsu_dma_dma_lsc_ctl_dma_mem_addr = _T_1184 ? _T_1188 : dma_mem_addr_int; // @[dma_ctrl.scala 357:40]
|
||||
assign io_lsu_dma_dma_lsc_ctl_dma_mem_sz = _T_1196 ? 3'h2 : dma_mem_sz_int; // @[dma_ctrl.scala 358:40]
|
||||
assign io_lsu_dma_dma_lsc_ctl_dma_mem_write = _T_1199[0]; // @[dma_ctrl.scala 360:40]
|
||||
assign io_lsu_dma_dma_lsc_ctl_dma_mem_wdata = 3'h4 == RdPtr ? fifo_data_4 : _GEN_77; // @[dma_ctrl.scala 361:40]
|
||||
assign io_lsu_dma_dma_dccm_ctl_dma_mem_addr = io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[dma_ctrl.scala 503:40]
|
||||
assign io_lsu_dma_dma_dccm_ctl_dma_mem_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[dma_ctrl.scala 504:41]
|
||||
assign io_lsu_dma_dma_dccm_ctl_dma_mem_addr = io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[dma_ctrl.scala 490:40]
|
||||
assign io_lsu_dma_dma_dccm_ctl_dma_mem_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[dma_ctrl.scala 491:41]
|
||||
assign io_lsu_dma_dma_mem_tag = RdPtr; // @[dma_ctrl.scala 354:28]
|
||||
assign io_ifu_dma_dma_ifc_dma_iccm_stall_any = _T_1140 & _T_1138; // @[dma_ctrl.scala 333:41]
|
||||
assign io_ifu_dma_dma_mem_ctl_dma_iccm_req = _T_1140 & io_iccm_ready; // @[dma_ctrl.scala 353:40]
|
||||
assign io_ifu_dma_dma_mem_ctl_dma_mem_addr = io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[dma_ctrl.scala 506:39]
|
||||
assign io_ifu_dma_dma_mem_ctl_dma_mem_sz = io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[dma_ctrl.scala 505:37]
|
||||
assign io_ifu_dma_dma_mem_ctl_dma_mem_write = io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 508:40]
|
||||
assign io_ifu_dma_dma_mem_ctl_dma_mem_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[dma_ctrl.scala 507:40]
|
||||
assign io_ifu_dma_dma_mem_ctl_dma_mem_tag = io_lsu_dma_dma_mem_tag; // @[dma_ctrl.scala 509:38]
|
||||
assign io_ifu_dma_dma_mem_ctl_dma_mem_addr = io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[dma_ctrl.scala 493:39]
|
||||
assign io_ifu_dma_dma_mem_ctl_dma_mem_sz = io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[dma_ctrl.scala 492:37]
|
||||
assign io_ifu_dma_dma_mem_ctl_dma_mem_write = io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 495:40]
|
||||
assign io_ifu_dma_dma_mem_ctl_dma_mem_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[dma_ctrl.scala 494:40]
|
||||
assign io_ifu_dma_dma_mem_ctl_dma_mem_tag = io_lsu_dma_dma_mem_tag; // @[dma_ctrl.scala 496:38]
|
||||
assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18]
|
||||
assign rvclkhdr_io_en = fifo_cmd_en[0]; // @[lib.scala 371:17]
|
||||
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
|
||||
|
|
@ -79194,24 +79194,24 @@ module dma_ctrl(
|
|||
assign rvclkhdr_9_io_clk = clock; // @[lib.scala 370:18]
|
||||
assign rvclkhdr_9_io_en = fifo_data_en[4]; // @[lib.scala 371:17]
|
||||
assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
|
||||
assign dma_buffer_c1cgc_io_clk = clock; // @[dma_ctrl.scala 392:33]
|
||||
assign dma_buffer_c1cgc_io_en = _T_1213 | io_clk_override; // @[dma_ctrl.scala 390:33]
|
||||
assign dma_buffer_c1cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 391:33]
|
||||
assign dma_free_cgc_io_clk = clock; // @[dma_ctrl.scala 398:29]
|
||||
assign dma_free_cgc_io_en = _T_1219 | io_clk_override; // @[dma_ctrl.scala 396:29]
|
||||
assign dma_free_cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 397:29]
|
||||
assign dma_bus_cgc_io_clk = clock; // @[dma_ctrl.scala 404:28]
|
||||
assign dma_bus_cgc_io_en = io_dma_bus_clk_en; // @[dma_ctrl.scala 402:28]
|
||||
assign dma_bus_cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 403:28]
|
||||
assign rvclkhdr_10_io_clk = clock; // @[lib.scala 370:18]
|
||||
assign rvclkhdr_10_io_en = wrbuf_en & io_dma_bus_clk_en; // @[lib.scala 371:17]
|
||||
assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
|
||||
assign rvclkhdr_11_io_clk = clock; // @[lib.scala 370:18]
|
||||
assign rvclkhdr_11_io_en = wrbuf_data_en & io_dma_bus_clk_en; // @[lib.scala 371:17]
|
||||
assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
|
||||
assign rvclkhdr_12_io_clk = clock; // @[lib.scala 370:18]
|
||||
assign rvclkhdr_12_io_en = rdbuf_en & io_dma_bus_clk_en; // @[lib.scala 371:17]
|
||||
assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
|
||||
assign rvclkhdr_10_io_clk = clock; // @[lib.scala 344:17]
|
||||
assign rvclkhdr_10_io_en = _T_1213 | io_clk_override; // @[lib.scala 345:16]
|
||||
assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
|
||||
assign rvclkhdr_11_io_clk = clock; // @[lib.scala 344:17]
|
||||
assign rvclkhdr_11_io_en = _T_1219 | io_clk_override; // @[lib.scala 345:16]
|
||||
assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
|
||||
assign rvclkhdr_12_io_clk = clock; // @[lib.scala 344:17]
|
||||
assign rvclkhdr_12_io_en = io_dma_bus_clk_en; // @[lib.scala 345:16]
|
||||
assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
|
||||
assign rvclkhdr_13_io_clk = clock; // @[lib.scala 370:18]
|
||||
assign rvclkhdr_13_io_en = wrbuf_en & io_dma_bus_clk_en; // @[lib.scala 371:17]
|
||||
assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
|
||||
assign rvclkhdr_14_io_clk = clock; // @[lib.scala 370:18]
|
||||
assign rvclkhdr_14_io_en = wrbuf_data_en & io_dma_bus_clk_en; // @[lib.scala 371:17]
|
||||
assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
|
||||
assign rvclkhdr_15_io_clk = clock; // @[lib.scala 370:18]
|
||||
assign rvclkhdr_15_io_en = rdbuf_en & io_dma_bus_clk_en; // @[lib.scala 371:17]
|
||||
assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
|
||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
|
|
@ -79682,21 +79682,21 @@ end // initial
|
|||
if (reset) begin
|
||||
wrbuf_vld <= 1'h0;
|
||||
end else begin
|
||||
wrbuf_vld <= _T_1224 & _T_1225;
|
||||
wrbuf_vld <= _T_1226 & _T_1227;
|
||||
end
|
||||
end
|
||||
always @(posedge dma_bus_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
wrbuf_data_vld <= 1'h0;
|
||||
end else begin
|
||||
wrbuf_data_vld <= _T_1228 & _T_1229;
|
||||
wrbuf_data_vld <= _T_1230 & _T_1231;
|
||||
end
|
||||
end
|
||||
always @(posedge dma_bus_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
rdbuf_vld <= 1'h0;
|
||||
end else begin
|
||||
rdbuf_vld <= _T_1237 & _T_1238;
|
||||
rdbuf_vld <= _T_1239 & _T_1240;
|
||||
end
|
||||
end
|
||||
always @(posedge dma_bus_clk or posedge reset) begin
|
||||
|
|
@ -79706,14 +79706,14 @@ end // initial
|
|||
axi_mstr_priority <= axi_mstr_prty_in;
|
||||
end
|
||||
end
|
||||
always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin
|
||||
always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
wrbuf_addr <= 32'h0;
|
||||
end else begin
|
||||
wrbuf_addr <= io_dma_axi_aw_bits_addr;
|
||||
end
|
||||
end
|
||||
always @(posedge rvclkhdr_12_io_l1clk or posedge reset) begin
|
||||
always @(posedge rvclkhdr_15_io_l1clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
rdbuf_addr <= 32'h0;
|
||||
end else begin
|
||||
|
|
@ -80011,7 +80011,7 @@ end // initial
|
|||
end
|
||||
end
|
||||
end
|
||||
always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin
|
||||
always @(posedge rvclkhdr_14_io_l1clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
wrbuf_data <= 64'h0;
|
||||
end else begin
|
||||
|
|
@ -80094,10 +80094,10 @@ end // initial
|
|||
end else if (fifo_cmd_en[0]) begin
|
||||
if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
|
||||
_T_850 <= io_dbg_dma_dbg_ib_dbg_cmd_write;
|
||||
end else if (_T_1261) begin
|
||||
end else if (_T_1263) begin
|
||||
_T_850 <= axi_mstr_priority;
|
||||
end else begin
|
||||
_T_850 <= _T_1260;
|
||||
_T_850 <= _T_1262;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -80107,10 +80107,10 @@ end // initial
|
|||
end else if (fifo_cmd_en[1]) begin
|
||||
if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
|
||||
_T_852 <= io_dbg_dma_dbg_ib_dbg_cmd_write;
|
||||
end else if (_T_1261) begin
|
||||
end else if (_T_1263) begin
|
||||
_T_852 <= axi_mstr_priority;
|
||||
end else begin
|
||||
_T_852 <= _T_1260;
|
||||
_T_852 <= _T_1262;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -80120,10 +80120,10 @@ end // initial
|
|||
end else if (fifo_cmd_en[2]) begin
|
||||
if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
|
||||
_T_854 <= io_dbg_dma_dbg_ib_dbg_cmd_write;
|
||||
end else if (_T_1261) begin
|
||||
end else if (_T_1263) begin
|
||||
_T_854 <= axi_mstr_priority;
|
||||
end else begin
|
||||
_T_854 <= _T_1260;
|
||||
_T_854 <= _T_1262;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -80133,10 +80133,10 @@ end // initial
|
|||
end else if (fifo_cmd_en[3]) begin
|
||||
if (io_dbg_dma_dbg_ib_dbg_cmd_valid) begin
|
||||
_T_856 <= io_dbg_dma_dbg_ib_dbg_cmd_write;
|
||||
end else if (_T_1261) begin
|
||||
end else if (_T_1263) begin
|
||||
_T_856 <= axi_mstr_priority;
|
||||
end else begin
|
||||
_T_856 <= _T_1260;
|
||||
_T_856 <= _T_1262;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
|
|||
|
|
@ -386,23 +386,10 @@ class dma_ctrl extends Module with lib with RequireAsyncReset {
|
|||
val dma_buffer_c1_clken = (bus_cmd_valid & io.dma_bus_clk_en) | io.dbg_dma.dbg_ib.dbg_cmd_valid | io.clk_override
|
||||
val dma_free_clken = (bus_cmd_valid | bus_rsp_valid | io.dbg_dma.dbg_ib.dbg_cmd_valid | io.dma_dbg_cmd_done | dma_dbg_cmd_done_q | (fifo_valid.orR) | io.clk_override)
|
||||
|
||||
val dma_buffer_c1cgc = Module(new rvclkhdr)
|
||||
dma_buffer_c1cgc.io.en := dma_buffer_c1_clken
|
||||
dma_buffer_c1cgc.io.scan_mode := io.scan_mode
|
||||
dma_buffer_c1cgc.io.clk := clock
|
||||
dma_buffer_c1_clk := dma_buffer_c1cgc.io.l1clk
|
||||
|
||||
val dma_free_cgc = Module(new rvclkhdr)
|
||||
dma_free_cgc.io.en := dma_free_clken
|
||||
dma_free_cgc.io.scan_mode := io.scan_mode
|
||||
dma_free_cgc.io.clk := clock
|
||||
dma_free_clk := dma_free_cgc.io.l1clk
|
||||
|
||||
val dma_bus_cgc = Module(new rvclkhdr)
|
||||
dma_bus_cgc.io.en := io.dma_bus_clk_en
|
||||
dma_bus_cgc.io.scan_mode := io.scan_mode
|
||||
dma_bus_cgc.io.clk := clock
|
||||
dma_bus_clk := dma_bus_cgc.io.l1clk
|
||||
dma_buffer_c1_clk := rvclkhdr(clock,dma_buffer_c1_clken.asBool,io.scan_mode)
|
||||
dma_free_clk := rvclkhdr(clock,dma_free_clken.asBool(),io.scan_mode)
|
||||
dma_bus_clk := rvclkhdr(clock,io.dma_bus_clk_en,io.scan_mode)
|
||||
|
||||
|
||||
// Write channel buffer
|
||||
|
||||
|
|
|
|||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Loading…
Reference in New Issue