From 46ffb7c24f6a13898d6fc38e84735b16ade16275 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E2=80=8BLaraib=20Khan?= <​laraib.khan@lampromellon.com>
Date: Thu, 24 Dec 2020 16:34:10 +0500
Subject: [PATCH] bus buffer added

---
 lsu_bus_buffer.fir                            |  20 +++++++++---------
 lsu_bus_buffer.v                              |  20 +++++++++---------
 src/main/scala/lib/lib.scala                  |   2 +-
 .../classes/lib/lib$rvdff_fpga$.class         | Bin 3059 -> 3282 bytes
 .../scala-2.12/classes/lib/lib$rvdffe$.class  | Bin 10996 -> 10997 bytes
 .../classes/lib/lib$rvdffs_fpga$.class        | Bin 3313 -> 3313 bytes
 .../classes/lsu/lsu_bus_buffer.class          | Bin 574149 -> 574148 bytes
 7 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/lsu_bus_buffer.fir b/lsu_bus_buffer.fir
index 63e59658..9c21b6e3 100644
--- a/lsu_bus_buffer.fir
+++ b/lsu_bus_buffer.fir
@@ -2513,8 +2513,8 @@ circuit lsu_bus_buffer :
     node _T_1769 = and(_T_1768, io.ldst_dual_r) @[lsu_bus_buffer.scala 345:35]
     node _T_1770 = or(_T_1767, _T_1769) @[lsu_bus_buffer.scala 344:250]
     obuf_merge_en <= _T_1770 @[lsu_bus_buffer.scala 342:17]
-    reg obuf_wr_enQ : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 377:18]
-    obuf_wr_enQ <= obuf_wr_en @[lib.scala 377:18]
+    reg obuf_wr_enQ : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 377:33]
+    obuf_wr_enQ <= obuf_wr_en @[lib.scala 377:33]
     node _T_1771 = mux(obuf_wr_en, UInt<1>("h01"), obuf_valid) @[lsu_bus_buffer.scala 348:58]
     node _T_1772 = eq(obuf_rst, UInt<1>("h00")) @[lsu_bus_buffer.scala 348:93]
     node _T_1773 = and(_T_1771, _T_1772) @[lsu_bus_buffer.scala 348:91]
@@ -2531,14 +2531,14 @@ circuit lsu_bus_buffer :
       _T_1776 <= obuf_rdrsp_pend_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
     obuf_rdrsp_pend <= _T_1776 @[lsu_bus_buffer.scala 350:19]
-    reg _T_1777 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 377:18]
-    _T_1777 <= obuf_cmd_done_in @[lib.scala 377:18]
+    reg _T_1777 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 377:33]
+    _T_1777 <= obuf_cmd_done_in @[lib.scala 377:33]
     obuf_cmd_done <= _T_1777 @[lsu_bus_buffer.scala 351:17]
-    reg _T_1778 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 377:18]
-    _T_1778 <= obuf_data_done_in @[lib.scala 377:18]
+    reg _T_1778 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 377:33]
+    _T_1778 <= obuf_data_done_in @[lib.scala 377:33]
     obuf_data_done <= _T_1778 @[lsu_bus_buffer.scala 352:18]
-    reg _T_1779 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 377:18]
-    _T_1779 <= obuf_rdrsp_tag_in @[lib.scala 377:18]
+    reg _T_1779 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 377:33]
+    _T_1779 <= obuf_rdrsp_tag_in @[lib.scala 377:33]
     obuf_rdrsp_tag <= _T_1779 @[lsu_bus_buffer.scala 353:18]
     reg _T_1780 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when obuf_wr_en : @[Reg.scala 28:19]
@@ -2588,8 +2588,8 @@ circuit lsu_bus_buffer :
     rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
     reg obuf_data : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 396:16]
     obuf_data <= obuf_data_in @[lib.scala 396:16]
-    reg _T_1784 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 377:18]
-    _T_1784 <= obuf_data_done_in @[lib.scala 377:18]
+    reg _T_1784 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 377:33]
+    _T_1784 <= obuf_data_done_in @[lib.scala 377:33]
     obuf_wr_timer <= _T_1784 @[lsu_bus_buffer.scala 363:17]
     wire WrPtr0_m : UInt<2>
     WrPtr0_m <= UInt<1>("h00")
diff --git a/lsu_bus_buffer.v b/lsu_bus_buffer.v
index bc9d1b87..91f25979 100644
--- a/lsu_bus_buffer.v
+++ b/lsu_bus_buffer.v
@@ -371,7 +371,7 @@ module lsu_bus_buffer(
   wire  _T_4131 = _T_4128 | _T_4130; // @[lsu_bus_buffer.scala 459:77]
   reg  obuf_valid; // @[lsu_bus_buffer.scala 348:54]
   wire  _T_4132 = _T_4131 & obuf_valid; // @[lsu_bus_buffer.scala 459:135]
-  reg  obuf_wr_enQ; // @[lib.scala 377:18]
+  reg  obuf_wr_enQ; // @[lib.scala 377:33]
   wire  _T_4133 = _T_4132 & obuf_wr_enQ; // @[lsu_bus_buffer.scala 459:148]
   wire  _T_4155 = 3'h3 == buf_state_3; // @[Conditional.scala 37:30]
   wire  _T_4239 = 3'h4 == buf_state_3; // @[Conditional.scala 37:30]
@@ -1053,7 +1053,7 @@ module lsu_bus_buffer(
   wire [3:0] buf_numvld_cmd_any = _T_4449 + _GEN_370; // @[lsu_bus_buffer.scala 530:126]
   wire  _T_1017 = buf_numvld_cmd_any == 4'h1; // @[lsu_bus_buffer.scala 266:72]
   wire  _T_1018 = _T_1016 & _T_1017; // @[lsu_bus_buffer.scala 266:51]
-  reg  _T_1784; // @[lib.scala 377:18]
+  reg  _T_1784; // @[lib.scala 377:33]
   wire [2:0] obuf_wr_timer = {{2'd0}, _T_1784}; // @[lsu_bus_buffer.scala 363:17]
   wire  _T_1019 = obuf_wr_timer != 3'h7; // @[lsu_bus_buffer.scala 266:97]
   wire  _T_1020 = _T_1018 & _T_1019; // @[lsu_bus_buffer.scala 266:80]
@@ -1275,8 +1275,8 @@ module lsu_bus_buffer(
   wire  _T_1229 = _T_1148 & _T_1228; // @[lsu_bus_buffer.scala 289:164]
   wire  _T_1230 = _T_1094 | _T_1229; // @[lsu_bus_buffer.scala 287:98]
   reg  obuf_write; // @[Reg.scala 27:20]
-  reg  obuf_cmd_done; // @[lib.scala 377:18]
-  reg  obuf_data_done; // @[lib.scala 377:18]
+  reg  obuf_cmd_done; // @[lib.scala 377:33]
+  reg  obuf_data_done; // @[lib.scala 377:33]
   wire  _T_4814 = obuf_cmd_done | obuf_data_done; // @[lsu_bus_buffer.scala 563:54]
   wire  _T_4815 = obuf_cmd_done ? io_lsu_axi_w_ready : io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 563:75]
   wire  _T_4816 = io_lsu_axi_aw_ready & io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 563:153]
@@ -1399,7 +1399,7 @@ module lsu_bus_buffer(
   wire  _T_1348 = obuf_valid & _T_1347; // @[lsu_bus_buffer.scala 327:18]
   reg  obuf_rdrsp_pend; // @[Reg.scala 27:20]
   wire  bus_rsp_read = io_lsu_axi_r_valid & io_lsu_axi_r_ready; // @[lsu_bus_buffer.scala 567:38]
-  reg [2:0] obuf_rdrsp_tag; // @[lib.scala 377:18]
+  reg [2:0] obuf_rdrsp_tag; // @[lib.scala 377:33]
   wire  _T_1349 = io_lsu_axi_r_bits_id == obuf_rdrsp_tag; // @[lsu_bus_buffer.scala 327:90]
   wire  _T_1350 = bus_rsp_read & _T_1349; // @[lsu_bus_buffer.scala 327:70]
   wire  _T_1351 = ~_T_1350; // @[lsu_bus_buffer.scala 327:55]
@@ -3779,7 +3779,7 @@ end // initial
       obuf_valid <= _T_1771 & _T_1772;
     end
   end
-  always @(posedge clock or posedge reset) begin
+  always @(posedge io_lsu_busm_clk or posedge reset) begin
     if (reset) begin
       obuf_wr_enQ <= 1'h0;
     end else begin
@@ -4079,7 +4079,7 @@ end // initial
       ibuf_sz <= ibuf_sz_in;
     end
   end
-  always @(posedge clock or posedge reset) begin
+  always @(posedge io_lsu_busm_clk or posedge reset) begin
     if (reset) begin
       _T_1784 <= 1'h0;
     end else begin
@@ -4220,14 +4220,14 @@ end // initial
       end
     end
   end
-  always @(posedge clock or posedge reset) begin
+  always @(posedge io_lsu_busm_clk or posedge reset) begin
     if (reset) begin
       obuf_cmd_done <= 1'h0;
     end else begin
       obuf_cmd_done <= _T_1303 & _T_4821;
     end
   end
-  always @(posedge clock or posedge reset) begin
+  always @(posedge io_lsu_busm_clk or posedge reset) begin
     if (reset) begin
       obuf_data_done <= 1'h0;
     end else begin
@@ -4301,7 +4301,7 @@ end // initial
       obuf_rdrsp_pend <= obuf_rdrsp_pend_in;
     end
   end
-  always @(posedge clock or posedge reset) begin
+  always @(posedge io_lsu_busm_clk or posedge reset) begin
     if (reset) begin
       obuf_rdrsp_tag <= 3'h0;
     end else if (_T_1330) begin
diff --git a/src/main/scala/lib/lib.scala b/src/main/scala/lib/lib.scala
index 1c815f0f..c1754997 100644
--- a/src/main/scala/lib/lib.scala
+++ b/src/main/scala/lib/lib.scala
@@ -374,7 +374,7 @@ trait lib extends param{
   def apply(din: UInt, clk: Clock, clken: Bool,rawclk:Clock):UInt = {
     if (RV_FPGA_OPTIMIZE)
     withClock (clk) {RegEnable (din, 0.U, clken)}
-    else RegNext (din, 0.U)
+    else withClock(clk){RegNext (din, 0.U)}
   }
 }
   object rvdffs_fpga {
diff --git a/target/scala-2.12/classes/lib/lib$rvdff_fpga$.class b/target/scala-2.12/classes/lib/lib$rvdff_fpga$.class
index b5e63363ccb90c9329aa8c52b2dce25a54e60d54..0478df24a82935439bbed4ec9f45f4391e7ce325 100644
GIT binary patch
delta 1030
zcmZuvOHUI~6#i~IotaK2G8Ab6m4~UO1(GTd1nb7=2B?5w5meMtOF?R>(gIbq;1fkf
zy!d`6Zb_tznm}TVOPBrvm+oB|6XKb+kdipboqNuA?)koR&$++tKT4JFYb##>G~oTR
zGAndC{E^YfU_9dRN2B3{qmiN9=?x4Gj|Ic^ZeL3z=5cLyRd{hkfdTCWB03nVHXr8|
zf?Ygn1w$8K5@*;+?v^S&{broPX$EbbIqDCL_(MU5gtH9R4TW{sqoNiAX7~}{e}vkt
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zWds=w>$Wb&|0-q4yUP^G_SOg{=JhoW3!6d#i|5@$+vux?5|rj{Lc}GSrYX3GIfC?o
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hVV#?>$CTBGPQ0bO62^#^rp5GLX6~4IU<~glihrW2x48fS

delta 795
zcmZ9K%TH5L5XOI}kK6Y4Mz2N7Lj*NwT1r9$f+%i`CK9NKC<rPdU@b^R6cA7p5Fhv!
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diff --git a/target/scala-2.12/classes/lib/lib$rvdffe$.class b/target/scala-2.12/classes/lib/lib$rvdffe$.class
index 5e9972dd7d05b203e692ec1b2915735267023b38..561c97b9f032fecaa8e01cd0d4edd5b02c248d79 100644
GIT binary patch
delta 68
zcmV-K0K5P6RrOV{YX}550RSbFu?ZBjg9sM}0Xegq4(b7u(-0DqmJm(>F_YyG{Q)wQ
a;}K2)GqW-hPZ$IY0D=LNfGQc2o+?%+eHKsv

delta 102
zcmeww`XzKjHV2D2BZKPXjhrHzn>obU7%eu>=6l5`D4>#<m!Fqbnx~RjP>@rpVmW!b
zfFGm5<YxkZ84V{t5%gm;+H5T3FCinzD8<OA&CtZiXu)X7$j}I6F}z`T%gD&X&@_3T
GRyY8Eq#dCE

diff --git a/target/scala-2.12/classes/lib/lib$rvdffs_fpga$.class b/target/scala-2.12/classes/lib/lib$rvdffs_fpga$.class
index 0de59f58fea8e7a36a15603b66fda2538d6eb416..d4ca4aeef376ee1957c0060bf1ef6ec63d0b44db 100644
GIT binary patch
delta 14
Vcmew;`B8Gic_v2l%@>#yxd1VF1%3bk

delta 14
Vcmew;`B8Gic_v1)%@>#yxd1V91$_Vj

diff --git a/target/scala-2.12/classes/lsu/lsu_bus_buffer.class b/target/scala-2.12/classes/lsu/lsu_bus_buffer.class
index b40603b488c1f6afd2fee2ff1bc4d1df95ffd4cf..1e92abf1a2710e8723f6052d54e09d2fb51334c1 100644
GIT binary patch
delta 82
zcmX@ws(hqXdBZ6Y#^lMTMe-PpHd~2)P-8UQtZnmiI*_M&MT?Qqcyqwj5bnwRS40_2
fns+~F-~E6Qh?#(x8Hibcm=%cGw(owx&h-cYdb=b{

delta 85
zcmX@os(iFndBZ6Y#{9{rMe-OeHd~2)P-8UTtZnmiI*_M&MT?Qqa&y4d5N<}X$pTkI
im<$b?cRgs|^?(tGnShuXh*^M`6^Plk?|Q(_^#}mJh9s>3