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This commit is contained in:
waleed-lm 2020-09-27 01:44:51 +05:00
parent 8d15433c55
commit 4beee041ea
20 changed files with 2555 additions and 1370 deletions
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27
el2_ifu_bp_ctl.fir
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@ -580,31 +580,4 @@ circuit el2_ifu_bp_ctl :
node _T_413 = bits(_T_380, 11, 1) @[el2_lib.scala 205:91] node _T_413 = bits(_T_380, 11, 1) @[el2_lib.scala 205:91]
node _T_414 = cat(_T_412, _T_413) @[Cat.scala 29:58] node _T_414 = cat(_T_412, _T_413) @[Cat.scala 29:58]
node bp_btb_target_adder_f = cat(_T_414, UInt<1>("h00")) @[Cat.scala 29:58] node bp_btb_target_adder_f = cat(_T_414, UInt<1>("h00")) @[Cat.scala 29:58]
wire rets_out : UInt<32>[8] @[el2_ifu_bp_ctl.scala 305:22]
rets_out[0] <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 306:12]
rets_out[1] <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 306:12]
rets_out[2] <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 306:12]
rets_out[3] <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 306:12]
rets_out[4] <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 306:12]
rets_out[5] <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 306:12]
rets_out[6] <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 306:12]
rets_out[7] <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 306:12]
node _T_415 = not(btb_rd_call_f) @[el2_ifu_bp_ctl.scala 307:49]
node _T_416 = and(btb_rd_ret_f, _T_415) @[el2_ifu_bp_ctl.scala 307:47]
node _T_417 = bits(rets_out[0], 0, 0) @[el2_ifu_bp_ctl.scala 307:77]
node _T_418 = and(_T_416, _T_417) @[el2_ifu_bp_ctl.scala 307:64]
node _T_419 = bits(_T_418, 0, 0) @[el2_ifu_bp_ctl.scala 307:82]
node _T_420 = bits(rets_out[0], 31, 1) @[el2_ifu_bp_ctl.scala 308:16]
node _T_421 = bits(bp_btb_target_adder_f, 31, 1) @[el2_ifu_bp_ctl.scala 308:44]
node _T_422 = mux(_T_419, _T_420, _T_421) @[el2_ifu_bp_ctl.scala 307:32]
io.ifu_bp_btb_target_f <= _T_422 @[el2_ifu_bp_ctl.scala 307:26]
node _T_423 = not(btb_rd_ret_f) @[el2_ifu_bp_ctl.scala 312:33]
node _T_424 = and(btb_rd_call_f, _T_423) @[el2_ifu_bp_ctl.scala 312:31]
node rs_push = and(_T_424, ifu_bp_hit_taken_f) @[el2_ifu_bp_ctl.scala 312:47]
node _T_425 = not(btb_rd_call_f) @[el2_ifu_bp_ctl.scala 313:31]
node _T_426 = and(btb_rd_ret_f, _T_425) @[el2_ifu_bp_ctl.scala 313:29]
node rs_pop = and(_T_426, ifu_bp_hit_taken_f) @[el2_ifu_bp_ctl.scala 313:46]
node _T_427 = not(rs_push) @[el2_ifu_bp_ctl.scala 314:17]
node _T_428 = not(rs_pop) @[el2_ifu_bp_ctl.scala 314:28]
node rs_hold = and(_T_427, _T_428) @[el2_ifu_bp_ctl.scala 314:26]

4
el2_ifu_compress_ctl.anno.json
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@ -1,9 +1,9 @@
[ [
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_out", "sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_dout",
"sources":[ "sources":[
"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_in" "~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_din"
] ]
}, },
{ {

3067
el2_ifu_compress_ctl.fir
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File diff suppressed because it is too large Load Diff

655
el2_ifu_compress_ctl.v
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@ -1,146 +1,519 @@
module el2_ifu_compress_ctl( module el2_ifu_compress_ctl(
input clock, input clock,
input reset, input reset,
input [15:0] io_in, input [15:0] io_din,
output [31:0] io_out output [31:0] io_dout
); );
wire _T_1 = io_in[1:0] != 2'h3; // @[el2_ifu_compress_ctl.scala 192:26] wire _T_2 = ~io_din[14]; // @[el2_ifu_compress_ctl.scala 15:83]
wire [31:0] _T_3 = {16'h0,io_in}; // @[Cat.scala 29:58] wire _T_4 = ~io_din[13]; // @[el2_ifu_compress_ctl.scala 15:83]
wire _T_5 = |_T_3[12:5]; // @[el2_ifu_compress_ctl.scala 48:29] wire _T_7 = ~io_din[6]; // @[el2_ifu_compress_ctl.scala 15:83]
wire [6:0] _T_6 = _T_5 ? 7'h13 : 7'h1f; // @[el2_ifu_compress_ctl.scala 48:20] wire _T_9 = ~io_din[5]; // @[el2_ifu_compress_ctl.scala 15:83]
wire [29:0] _T_20 = {_T_3[10:7],_T_3[12:11],_T_3[5],_T_3[6],2'h0,5'h2,3'h0,2'h1,_T_3[4:2],_T_6}; // @[Cat.scala 29:58] wire _T_11 = io_din[15] & _T_2; // @[el2_ifu_compress_ctl.scala 15:110]
wire [7:0] _T_30 = {_T_3[6:5],_T_3[12:10],3'h0}; // @[Cat.scala 29:58] wire _T_12 = _T_11 & _T_4; // @[el2_ifu_compress_ctl.scala 15:110]
wire [27:0] _T_38 = {_T_3[6:5],_T_3[12:10],3'h0,2'h1,_T_3[9:7],3'h3,2'h1,_T_3[4:2],7'h7}; // @[Cat.scala 29:58] wire _T_13 = _T_12 & io_din[10]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [6:0] _T_52 = {_T_3[5],_T_3[12:10],_T_3[6],2'h0}; // @[Cat.scala 29:58] wire _T_14 = _T_13 & _T_7; // @[el2_ifu_compress_ctl.scala 15:110]
wire [26:0] _T_60 = {_T_3[5],_T_3[12:10],_T_3[6],2'h0,2'h1,_T_3[9:7],3'h2,2'h1,_T_3[4:2],7'h3}; // @[Cat.scala 29:58] wire _T_15 = _T_14 & _T_9; // @[el2_ifu_compress_ctl.scala 15:110]
wire [27:0] _T_80 = {_T_3[6:5],_T_3[12:10],3'h0,2'h1,_T_3[9:7],3'h3,2'h1,_T_3[4:2],7'h3}; // @[Cat.scala 29:58] wire _T_16 = _T_15 & io_din[0]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [26:0] _T_111 = {_T_52[6:5],2'h1,_T_3[4:2],2'h1,_T_3[9:7],3'h2,_T_52[4:0],7'h3f}; // @[Cat.scala 29:58] wire _T_23 = ~io_din[11]; // @[el2_ifu_compress_ctl.scala 15:83]
wire [27:0] _T_138 = {_T_30[7:5],2'h1,_T_3[4:2],2'h1,_T_3[9:7],3'h3,_T_30[4:0],7'h27}; // @[Cat.scala 29:58] wire _T_28 = _T_12 & _T_23; // @[el2_ifu_compress_ctl.scala 15:110]
wire [26:0] _T_169 = {_T_52[6:5],2'h1,_T_3[4:2],2'h1,_T_3[9:7],3'h2,_T_52[4:0],7'h23}; // @[Cat.scala 29:58] wire _T_29 = _T_28 & io_din[10]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [27:0] _T_196 = {_T_30[7:5],2'h1,_T_3[4:2],2'h1,_T_3[9:7],3'h3,_T_30[4:0],7'h23}; // @[Cat.scala 29:58] wire _T_30 = _T_29 & io_din[0]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [6:0] _T_207 = _T_3[12] ? 7'h7f : 7'h0; // @[Bitwise.scala 72:12] wire out_30 = _T_16 | _T_30; // @[el2_ifu_compress_ctl.scala 18:53]
wire [11:0] _T_209 = {_T_207,_T_3[6:2]}; // @[Cat.scala 29:58] wire _T_38 = ~io_din[10]; // @[el2_ifu_compress_ctl.scala 15:83]
wire [31:0] _T_215 = {_T_207,_T_3[6:2],_T_3[11:7],3'h0,_T_3[11:7],7'h13}; // @[Cat.scala 29:58] wire _T_40 = ~io_din[9]; // @[el2_ifu_compress_ctl.scala 15:83]
wire _T_223 = |_T_3[11:7]; // @[el2_ifu_compress_ctl.scala 72:24] wire _T_42 = ~io_din[8]; // @[el2_ifu_compress_ctl.scala 15:83]
wire [6:0] _T_224 = _T_223 ? 7'h1b : 7'h1f; // @[el2_ifu_compress_ctl.scala 72:20] wire _T_44 = ~io_din[7]; // @[el2_ifu_compress_ctl.scala 15:83]
wire [31:0] _T_235 = {_T_207,_T_3[6:2],_T_3[11:7],3'h0,_T_3[11:7],_T_224}; // @[Cat.scala 29:58] wire _T_50 = ~io_din[4]; // @[el2_ifu_compress_ctl.scala 15:83]
wire [31:0] _T_251 = {_T_207,_T_3[6:2],5'h0,3'h0,_T_3[11:7],7'h13}; // @[Cat.scala 29:58] wire _T_52 = ~io_din[3]; // @[el2_ifu_compress_ctl.scala 15:83]
wire _T_262 = |_T_209; // @[el2_ifu_compress_ctl.scala 85:29] wire _T_54 = ~io_din[2]; // @[el2_ifu_compress_ctl.scala 15:83]
wire [6:0] _T_263 = _T_262 ? 7'h37 : 7'h3f; // @[el2_ifu_compress_ctl.scala 85:20] wire _T_56 = _T_2 & io_din[12]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [14:0] _T_266 = _T_3[12] ? 15'h7fff : 15'h0; // @[Bitwise.scala 72:12] wire _T_57 = _T_56 & _T_23; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _T_269 = {_T_266,_T_3[6:2],12'h0}; // @[Cat.scala 29:58] wire _T_58 = _T_57 & _T_38; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _T_273 = {_T_269[31:12],_T_3[11:7],_T_263}; // @[Cat.scala 29:58] wire _T_59 = _T_58 & _T_40; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_281 = _T_3[11:7] == 5'h0; // @[el2_ifu_compress_ctl.scala 87:14] wire _T_60 = _T_59 & _T_42; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_283 = _T_3[11:7] == 5'h2; // @[el2_ifu_compress_ctl.scala 87:27] wire _T_61 = _T_60 & _T_44; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_284 = _T_281 | _T_283; // @[el2_ifu_compress_ctl.scala 87:21] wire _T_62 = _T_61 & _T_7; // @[el2_ifu_compress_ctl.scala 15:110]
wire [6:0] _T_291 = _T_262 ? 7'h13 : 7'h1f; // @[el2_ifu_compress_ctl.scala 81:20] wire _T_63 = _T_62 & _T_9; // @[el2_ifu_compress_ctl.scala 15:110]
wire [2:0] _T_294 = _T_3[12] ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] wire _T_64 = _T_63 & _T_50; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _T_309 = {_T_294,_T_3[4:3],_T_3[5],_T_3[2],_T_3[6],4'h0,_T_3[11:7],3'h0,_T_3[11:7],_T_291}; // @[Cat.scala 29:58] wire _T_65 = _T_64 & _T_52; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _T_316_bits = _T_284 ? _T_309 : _T_273; // @[el2_ifu_compress_ctl.scala 87:10] wire _T_66 = _T_65 & _T_54; // @[el2_ifu_compress_ctl.scala 15:110]
wire [25:0] _T_327 = {_T_3[12],_T_3[6:2],2'h1,_T_3[9:7],3'h5,2'h1,_T_3[9:7],7'h13}; // @[Cat.scala 29:58] wire out_20 = _T_66 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [30:0] _GEN_172 = {{5'd0}, _T_327}; // @[el2_ifu_compress_ctl.scala 94:23] wire _T_79 = _T_28 & io_din[0]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [30:0] _T_339 = _GEN_172 | 31'h40000000; // @[el2_ifu_compress_ctl.scala 94:23] wire _T_90 = _T_12 & _T_38; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _T_352 = {_T_207,_T_3[6:2],2'h1,_T_3[9:7],3'h7,2'h1,_T_3[9:7],7'h13}; // @[Cat.scala 29:58] wire _T_91 = _T_90 & io_din[0]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [2:0] _T_356 = {_T_3[12],_T_3[6:5]}; // @[Cat.scala 29:58] wire _T_92 = _T_79 | _T_91; // @[el2_ifu_compress_ctl.scala 20:46]
wire _T_358 = _T_3[6:5] == 2'h0; // @[el2_ifu_compress_ctl.scala 98:30] wire _T_102 = _T_12 & io_din[6]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [30:0] _T_359 = _T_358 ? 31'h40000000 : 31'h0; // @[el2_ifu_compress_ctl.scala 98:22] wire _T_103 = _T_102 & io_din[0]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [6:0] _T_361 = _T_3[12] ? 7'h3b : 7'h33; // @[el2_ifu_compress_ctl.scala 99:22] wire _T_104 = _T_92 | _T_103; // @[el2_ifu_compress_ctl.scala 20:80]
wire [2:0] _GEN_1 = 3'h1 == _T_356 ? 3'h4 : 3'h0; // @[Cat.scala 29:58] wire _T_114 = _T_12 & io_din[5]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [2:0] _GEN_2 = 3'h2 == _T_356 ? 3'h6 : _GEN_1; // @[Cat.scala 29:58] wire _T_115 = _T_114 & io_din[0]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [2:0] _GEN_3 = 3'h3 == _T_356 ? 3'h7 : _GEN_2; // @[Cat.scala 29:58] wire out_14 = _T_104 | _T_115; // @[el2_ifu_compress_ctl.scala 20:113]
wire [2:0] _GEN_4 = 3'h4 == _T_356 ? 3'h0 : _GEN_3; // @[Cat.scala 29:58] wire _T_128 = _T_12 & io_din[11]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [2:0] _GEN_5 = 3'h5 == _T_356 ? 3'h0 : _GEN_4; // @[Cat.scala 29:58] wire _T_129 = _T_128 & _T_38; // @[el2_ifu_compress_ctl.scala 15:110]
wire [2:0] _GEN_6 = 3'h6 == _T_356 ? 3'h2 : _GEN_5; // @[Cat.scala 29:58] wire _T_130 = _T_129 & io_din[0]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [2:0] _GEN_7 = 3'h7 == _T_356 ? 3'h3 : _GEN_6; // @[Cat.scala 29:58] wire _T_142 = _T_128 & io_din[6]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [24:0] _T_371 = {2'h1,_T_3[4:2],2'h1,_T_3[9:7],_GEN_7,2'h1,_T_3[9:7],_T_361}; // @[Cat.scala 29:58] wire _T_143 = _T_142 & io_din[0]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [30:0] _GEN_173 = {{6'd0}, _T_371}; // @[el2_ifu_compress_ctl.scala 100:43] wire _T_144 = _T_130 | _T_143; // @[el2_ifu_compress_ctl.scala 22:50]
wire [30:0] _T_372 = _GEN_173 | _T_359; // @[el2_ifu_compress_ctl.scala 100:43] wire _T_147 = ~io_din[0]; // @[el2_ifu_compress_ctl.scala 22:101]
wire [31:0] _T_373_0 = {{6'd0}, _T_327}; // @[el2_ifu_compress_ctl.scala 102:19 el2_ifu_compress_ctl.scala 102:19] wire _T_148 = io_din[14] & _T_147; // @[el2_ifu_compress_ctl.scala 22:99]
wire [31:0] _T_373_1 = {{1'd0}, _T_339}; // @[el2_ifu_compress_ctl.scala 102:19 el2_ifu_compress_ctl.scala 102:19] wire out_13 = _T_144 | _T_148; // @[el2_ifu_compress_ctl.scala 22:86]
wire [31:0] _GEN_9 = 2'h1 == _T_3[11:10] ? _T_373_1 : _T_373_0; // @[el2_ifu_compress_ctl.scala 17:14] wire _T_161 = _T_102 & io_din[5]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _GEN_10 = 2'h2 == _T_3[11:10] ? _T_352 : _GEN_9; // @[el2_ifu_compress_ctl.scala 17:14] wire _T_162 = _T_161 & io_din[0]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _T_373_3 = {{1'd0}, _T_372}; // @[el2_ifu_compress_ctl.scala 102:19 el2_ifu_compress_ctl.scala 102:19] wire _T_175 = _T_162 | _T_79; // @[el2_ifu_compress_ctl.scala 23:47]
wire [31:0] _GEN_11 = 2'h3 == _T_3[11:10] ? _T_373_3 : _GEN_10; // @[el2_ifu_compress_ctl.scala 17:14] wire _T_188 = _T_175 | _T_91; // @[el2_ifu_compress_ctl.scala 23:81]
wire [9:0] _T_385 = _T_3[12] ? 10'h3ff : 10'h0; // @[Bitwise.scala 72:12] wire _T_190 = ~io_din[15]; // @[el2_ifu_compress_ctl.scala 15:83]
wire [20:0] _T_400 = {_T_385,_T_3[8],_T_3[10:9],_T_3[6],_T_3[7],_T_3[2],_T_3[11],_T_3[5:3],1'h0}; // @[Cat.scala 29:58] wire _T_194 = _T_190 & _T_2; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _T_463 = {_T_400[20],_T_400[10:1],_T_400[11],_T_400[19:12],5'h0,7'h6f}; // @[Cat.scala 29:58] wire _T_195 = _T_194 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [4:0] _T_472 = _T_3[12] ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] wire _T_196 = _T_188 | _T_195; // @[el2_ifu_compress_ctl.scala 23:115]
wire [12:0] _T_481 = {_T_472,_T_3[6:5],_T_3[2],_T_3[11:10],_T_3[4:3],1'h0}; // @[Cat.scala 29:58] wire _T_200 = io_din[15] & io_din[14]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _T_530 = {_T_481[12],_T_481[10:5],5'h0,2'h1,_T_3[9:7],3'h0,_T_481[4:1],_T_481[11],7'h63}; // @[Cat.scala 29:58] wire _T_201 = _T_200 & io_din[13]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _T_597 = {_T_481[12],_T_481[10:5],5'h0,2'h1,_T_3[9:7],3'h1,_T_481[4:1],_T_481[11],7'h63}; // @[Cat.scala 29:58] wire out_12 = _T_196 | _T_201; // @[el2_ifu_compress_ctl.scala 24:26]
wire [6:0] _T_604 = _T_223 ? 7'h3 : 7'h1f; // @[el2_ifu_compress_ctl.scala 108:23] wire _T_217 = _T_11 & _T_7; // @[el2_ifu_compress_ctl.scala 15:110]
wire [25:0] _T_613 = {_T_3[12],_T_3[6:2],_T_3[11:7],3'h1,_T_3[11:7],7'h13}; // @[Cat.scala 29:58] wire _T_218 = _T_217 & _T_9; // @[el2_ifu_compress_ctl.scala 15:110]
wire [28:0] _T_629 = {_T_3[4:2],_T_3[12],_T_3[6:5],3'h0,5'h2,3'h3,_T_3[11:7],7'h7}; // @[Cat.scala 29:58] wire _T_219 = _T_218 & _T_50; // @[el2_ifu_compress_ctl.scala 15:110]
wire [27:0] _T_644 = {_T_3[3:2],_T_3[12],_T_3[6:4],2'h0,5'h2,3'h2,_T_3[11:7],_T_604}; // @[Cat.scala 29:58] wire _T_220 = _T_219 & _T_52; // @[el2_ifu_compress_ctl.scala 15:110]
wire [28:0] _T_659 = {_T_3[4:2],_T_3[12],_T_3[6:5],3'h0,5'h2,3'h3,_T_3[11:7],_T_604}; // @[Cat.scala 29:58] wire _T_221 = _T_220 & _T_54; // @[el2_ifu_compress_ctl.scala 15:110]
wire [24:0] _T_669 = {_T_3[6:2],5'h0,3'h0,_T_3[11:7],7'h33}; // @[Cat.scala 29:58] wire _T_224 = _T_221 & _T_147; // @[el2_ifu_compress_ctl.scala 25:53]
wire [24:0] _T_680 = {_T_3[6:2],_T_3[11:7],3'h0,_T_3[11:7],7'h33}; // @[Cat.scala 29:58] wire _T_228 = _T_2 & io_din[13]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [24:0] _T_691 = {_T_3[6:2],_T_3[11:7],3'h0,12'h67}; // @[Cat.scala 29:58] wire _T_229 = _T_224 | _T_228; // @[el2_ifu_compress_ctl.scala 25:67]
wire [24:0] _T_693 = {_T_691[24:7],7'h1f}; // @[Cat.scala 29:58] wire _T_234 = _T_200 & io_din[0]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [24:0] _T_696 = _T_223 ? _T_691 : _T_693; // @[el2_ifu_compress_ctl.scala 129:33] wire out_6 = _T_229 | _T_234; // @[el2_ifu_compress_ctl.scala 25:88]
wire _T_702 = |_T_3[6:2]; // @[el2_ifu_compress_ctl.scala 130:27] wire _T_239 = io_din[15] & _T_147; // @[el2_ifu_compress_ctl.scala 26:24]
wire [31:0] _T_673_bits = {{7'd0}, _T_669}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14] wire _T_243 = io_din[15] & io_din[11]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _T_700_bits = {{7'd0}, _T_696}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14] wire _T_244 = _T_243 & io_din[10]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _T_703_bits = _T_702 ? _T_673_bits : _T_700_bits; // @[el2_ifu_compress_ctl.scala 130:22] wire _T_245 = _T_239 | _T_244; // @[el2_ifu_compress_ctl.scala 26:39]
wire [24:0] _T_709 = {_T_3[6:2],_T_3[11:7],3'h0,12'he7}; // @[Cat.scala 29:58] wire _T_249 = io_din[13] & _T_42; // @[el2_ifu_compress_ctl.scala 15:110]
wire [24:0] _T_711 = {_T_691[24:7],7'h73}; // @[Cat.scala 29:58] wire _T_250 = _T_245 | _T_249; // @[el2_ifu_compress_ctl.scala 26:63]
wire [24:0] _T_712 = _T_711 | 25'h100000; // @[el2_ifu_compress_ctl.scala 132:46] wire _T_253 = io_din[13] & io_din[7]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [24:0] _T_715 = _T_223 ? _T_709 : _T_712; // @[el2_ifu_compress_ctl.scala 133:33] wire _T_254 = _T_250 | _T_253; // @[el2_ifu_compress_ctl.scala 26:83]
wire [31:0] _T_685_bits = {{7'd0}, _T_680}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14] wire _T_257 = io_din[13] & io_din[9]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _T_719_bits = {{7'd0}, _T_715}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14] wire _T_258 = _T_254 | _T_257; // @[el2_ifu_compress_ctl.scala 26:102]
wire [31:0] _T_722_bits = _T_702 ? _T_685_bits : _T_719_bits; // @[el2_ifu_compress_ctl.scala 134:25] wire _T_261 = io_din[13] & io_din[10]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _T_724_bits = _T_3[12] ? _T_722_bits : _T_703_bits; // @[el2_ifu_compress_ctl.scala 135:10] wire _T_262 = _T_258 | _T_261; // @[el2_ifu_compress_ctl.scala 27:22]
wire [8:0] _T_728 = {_T_3[9:7],_T_3[12:10],3'h0}; // @[Cat.scala 29:58] wire _T_265 = io_din[13] & io_din[11]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [28:0] _T_740 = {_T_728[8:5],_T_3[6:2],5'h2,3'h3,_T_728[4:0],7'h27}; // @[Cat.scala 29:58] wire _T_266 = _T_262 | _T_265; // @[el2_ifu_compress_ctl.scala 27:42]
wire [7:0] _T_748 = {_T_3[8:7],_T_3[12:9],2'h0}; // @[Cat.scala 29:58] wire _T_271 = _T_266 | _T_228; // @[el2_ifu_compress_ctl.scala 27:62]
wire [27:0] _T_760 = {_T_748[7:5],_T_3[6:2],5'h2,3'h2,_T_748[4:0],7'h23}; // @[Cat.scala 29:58] wire out_5 = _T_271 | _T_200; // @[el2_ifu_compress_ctl.scala 27:83]
wire [28:0] _T_780 = {_T_728[8:5],_T_3[6:2],5'h2,3'h3,_T_728[4:0],7'h23}; // @[Cat.scala 29:58] wire _T_288 = _T_2 & _T_23; // @[el2_ifu_compress_ctl.scala 15:110]
wire [4:0] _T_828 = {_T_3[1:0],_T_3[15:13]}; // @[Cat.scala 29:58] wire _T_289 = _T_288 & _T_38; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _T_26_bits = {{2'd0}, _T_20}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14] wire _T_290 = _T_289 & _T_40; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _T_46_bits = {{4'd0}, _T_38}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14] wire _T_291 = _T_290 & _T_42; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _GEN_17 = 5'h1 == _T_828 ? _T_46_bits : _T_26_bits; // @[el2_ifu_compress_ctl.scala 195:18] wire _T_292 = _T_291 & _T_44; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _T_68_bits = {{5'd0}, _T_60}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14] wire _T_295 = _T_292 & _T_147; // @[el2_ifu_compress_ctl.scala 28:50]
wire [31:0] _GEN_22 = 5'h2 == _T_828 ? _T_68_bits : _GEN_17; // @[el2_ifu_compress_ctl.scala 195:18] wire _T_303 = _T_194 & _T_147; // @[el2_ifu_compress_ctl.scala 28:87]
wire [31:0] _T_88_bits = {{4'd0}, _T_80}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14] wire _T_304 = _T_295 | _T_303; // @[el2_ifu_compress_ctl.scala 28:65]
wire [31:0] _GEN_27 = 5'h3 == _T_828 ? _T_88_bits : _GEN_22; // @[el2_ifu_compress_ctl.scala 195:18] wire _T_308 = _T_2 & io_din[6]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _T_119_bits = {{5'd0}, _T_111}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14] wire _T_311 = _T_308 & _T_147; // @[el2_ifu_compress_ctl.scala 29:23]
wire [31:0] _GEN_32 = 5'h4 == _T_828 ? _T_119_bits : _GEN_27; // @[el2_ifu_compress_ctl.scala 195:18] wire _T_312 = _T_304 | _T_311; // @[el2_ifu_compress_ctl.scala 28:102]
wire [31:0] _T_146_bits = {{4'd0}, _T_138}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14] wire _T_317 = _T_190 & io_din[14]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _GEN_37 = 5'h5 == _T_828 ? _T_146_bits : _GEN_32; // @[el2_ifu_compress_ctl.scala 195:18] wire _T_318 = _T_317 & io_din[0]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _T_177_bits = {{5'd0}, _T_169}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14] wire _T_319 = _T_312 | _T_318; // @[el2_ifu_compress_ctl.scala 29:38]
wire [31:0] _GEN_42 = 5'h6 == _T_828 ? _T_177_bits : _GEN_37; // @[el2_ifu_compress_ctl.scala 195:18] wire _T_323 = _T_2 & io_din[5]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _T_204_bits = {{4'd0}, _T_196}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14] wire _T_326 = _T_323 & _T_147; // @[el2_ifu_compress_ctl.scala 29:82]
wire [31:0] _GEN_47 = 5'h7 == _T_828 ? _T_204_bits : _GEN_42; // @[el2_ifu_compress_ctl.scala 195:18] wire _T_327 = _T_319 | _T_326; // @[el2_ifu_compress_ctl.scala 29:62]
wire [31:0] _GEN_52 = 5'h8 == _T_828 ? _T_215 : _GEN_47; // @[el2_ifu_compress_ctl.scala 195:18] wire _T_331 = _T_2 & io_din[4]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _GEN_57 = 5'h9 == _T_828 ? _T_235 : _GEN_52; // @[el2_ifu_compress_ctl.scala 195:18] wire _T_334 = _T_331 & _T_147; // @[el2_ifu_compress_ctl.scala 30:23]
wire [31:0] _GEN_62 = 5'ha == _T_828 ? _T_251 : _GEN_57; // @[el2_ifu_compress_ctl.scala 195:18] wire _T_335 = _T_327 | _T_334; // @[el2_ifu_compress_ctl.scala 29:97]
wire [31:0] _GEN_67 = 5'hb == _T_828 ? _T_316_bits : _GEN_62; // @[el2_ifu_compress_ctl.scala 195:18] wire _T_339 = _T_2 & io_din[3]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _GEN_72 = 5'hc == _T_828 ? _GEN_11 : _GEN_67; // @[el2_ifu_compress_ctl.scala 195:18] wire _T_342 = _T_339 & _T_147; // @[el2_ifu_compress_ctl.scala 30:58]
wire [31:0] _GEN_77 = 5'hd == _T_828 ? _T_463 : _GEN_72; // @[el2_ifu_compress_ctl.scala 195:18] wire _T_343 = _T_335 | _T_342; // @[el2_ifu_compress_ctl.scala 30:38]
wire [31:0] _GEN_82 = 5'he == _T_828 ? _T_530 : _GEN_77; // @[el2_ifu_compress_ctl.scala 195:18] wire _T_347 = _T_2 & io_din[2]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _GEN_87 = 5'hf == _T_828 ? _T_597 : _GEN_82; // @[el2_ifu_compress_ctl.scala 195:18] wire _T_350 = _T_347 & _T_147; // @[el2_ifu_compress_ctl.scala 30:93]
wire [31:0] _T_618_bits = {{6'd0}, _T_613}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14] wire _T_351 = _T_343 | _T_350; // @[el2_ifu_compress_ctl.scala 30:73]
wire [31:0] _GEN_92 = 5'h10 == _T_828 ? _T_618_bits : _GEN_87; // @[el2_ifu_compress_ctl.scala 195:18] wire _T_357 = _T_2 & _T_4; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _T_633_bits = {{3'd0}, _T_629}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14] wire _T_358 = _T_357 & io_din[0]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _GEN_97 = 5'h11 == _T_828 ? _T_633_bits : _GEN_92; // @[el2_ifu_compress_ctl.scala 195:18] wire out_4 = _T_351 | _T_358; // @[el2_ifu_compress_ctl.scala 30:108]
wire [31:0] _T_648_bits = {{4'd0}, _T_644}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14] wire _T_380 = _T_56 & io_din[11]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _GEN_102 = 5'h12 == _T_828 ? _T_648_bits : _GEN_97; // @[el2_ifu_compress_ctl.scala 195:18] wire _T_381 = _T_380 & _T_7; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _T_663_bits = {{3'd0}, _T_659}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14] wire _T_382 = _T_381 & _T_9; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _GEN_107 = 5'h13 == _T_828 ? _T_663_bits : _GEN_102; // @[el2_ifu_compress_ctl.scala 195:18] wire _T_383 = _T_382 & _T_50; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _GEN_112 = 5'h14 == _T_828 ? _T_724_bits : _GEN_107; // @[el2_ifu_compress_ctl.scala 195:18] wire _T_384 = _T_383 & _T_52; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _T_744_bits = {{3'd0}, _T_740}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14] wire _T_385 = _T_384 & _T_54; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _GEN_117 = 5'h15 == _T_828 ? _T_744_bits : _GEN_112; // @[el2_ifu_compress_ctl.scala 195:18] wire _T_386 = _T_385 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _T_764_bits = {{4'd0}, _T_760}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14] wire _T_403 = _T_56 & io_din[10]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _GEN_122 = 5'h16 == _T_828 ? _T_764_bits : _GEN_117; // @[el2_ifu_compress_ctl.scala 195:18] wire _T_404 = _T_403 & _T_7; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _T_784_bits = {{3'd0}, _T_780}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14] wire _T_405 = _T_404 & _T_9; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _GEN_127 = 5'h17 == _T_828 ? _T_784_bits : _GEN_122; // @[el2_ifu_compress_ctl.scala 195:18] wire _T_406 = _T_405 & _T_50; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _GEN_132 = 5'h18 == _T_828 ? _T_3 : _GEN_127; // @[el2_ifu_compress_ctl.scala 195:18] wire _T_407 = _T_406 & _T_52; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _GEN_137 = 5'h19 == _T_828 ? _T_3 : _GEN_132; // @[el2_ifu_compress_ctl.scala 195:18] wire _T_408 = _T_407 & _T_54; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _GEN_142 = 5'h1a == _T_828 ? _T_3 : _GEN_137; // @[el2_ifu_compress_ctl.scala 195:18] wire _T_409 = _T_408 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _GEN_147 = 5'h1b == _T_828 ? _T_3 : _GEN_142; // @[el2_ifu_compress_ctl.scala 195:18] wire _T_410 = _T_386 | _T_409; // @[el2_ifu_compress_ctl.scala 33:59]
wire [31:0] _GEN_152 = 5'h1c == _T_828 ? _T_3 : _GEN_147; // @[el2_ifu_compress_ctl.scala 195:18] wire _T_427 = _T_56 & io_din[9]; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _GEN_157 = 5'h1d == _T_828 ? _T_3 : _GEN_152; // @[el2_ifu_compress_ctl.scala 195:18] wire _T_428 = _T_427 & _T_7; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _GEN_162 = 5'h1e == _T_828 ? _T_3 : _GEN_157; // @[el2_ifu_compress_ctl.scala 195:18] wire _T_429 = _T_428 & _T_9; // @[el2_ifu_compress_ctl.scala 15:110]
wire [31:0] _GEN_167 = 5'h1f == _T_828 ? _T_3 : _GEN_162; // @[el2_ifu_compress_ctl.scala 195:18] wire _T_430 = _T_429 & _T_50; // @[el2_ifu_compress_ctl.scala 15:110]
assign io_out = _T_1 ? 32'h0 : _GEN_167; // @[el2_ifu_compress_ctl.scala 195:12] wire _T_431 = _T_430 & _T_52; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_432 = _T_431 & _T_54; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_433 = _T_432 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_434 = _T_410 | _T_433; // @[el2_ifu_compress_ctl.scala 33:107]
wire _T_450 = _T_56 & io_din[8]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_451 = _T_450 & io_din[6]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_452 = _T_451 & _T_9; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_453 = _T_452 & _T_50; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_454 = _T_453 & _T_52; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_455 = _T_454 & _T_54; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_456 = _T_455 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_457 = _T_434 | _T_456; // @[el2_ifu_compress_ctl.scala 34:48]
wire _T_474 = _T_56 & io_din[7]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_475 = _T_474 & _T_7; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_476 = _T_475 & _T_9; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_477 = _T_476 & _T_50; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_478 = _T_477 & _T_52; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_479 = _T_478 & _T_54; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_480 = _T_479 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_481 = _T_457 | _T_480; // @[el2_ifu_compress_ctl.scala 34:86]
wire _T_486 = ~io_din[12]; // @[el2_ifu_compress_ctl.scala 15:83]
wire _T_498 = _T_11 & _T_486; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_499 = _T_498 & _T_7; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_500 = _T_499 & _T_9; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_501 = _T_500 & _T_50; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_502 = _T_501 & _T_52; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_503 = _T_502 & _T_54; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_506 = _T_503 & _T_147; // @[el2_ifu_compress_ctl.scala 35:42]
wire _T_507 = _T_481 | _T_506; // @[el2_ifu_compress_ctl.scala 34:125]
wire _T_513 = _T_190 & io_din[13]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_514 = _T_513 & _T_42; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_515 = _T_507 | _T_514; // @[el2_ifu_compress_ctl.scala 35:57]
wire _T_521 = _T_513 & io_din[7]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_522 = _T_515 | _T_521; // @[el2_ifu_compress_ctl.scala 35:80]
wire _T_528 = _T_513 & io_din[9]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_529 = _T_522 | _T_528; // @[el2_ifu_compress_ctl.scala 35:102]
wire _T_535 = _T_513 & io_din[10]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_536 = _T_529 | _T_535; // @[el2_ifu_compress_ctl.scala 35:124]
wire _T_542 = _T_513 & io_din[11]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_543 = _T_536 | _T_542; // @[el2_ifu_compress_ctl.scala 36:24]
wire out_2 = _T_543 | _T_228; // @[el2_ifu_compress_ctl.scala 36:47]
wire [4:0] rs2d = io_din[6:2]; // @[el2_ifu_compress_ctl.scala 44:20]
wire [4:0] rdd = io_din[11:7]; // @[el2_ifu_compress_ctl.scala 45:19]
wire [4:0] rdpd = {2'h1,io_din[9:7]}; // @[Cat.scala 29:58]
wire [4:0] rs2pd = {2'h1,io_din[4:2]}; // @[Cat.scala 29:58]
wire _T_556 = _T_308 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_563 = _T_317 & io_din[11]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_564 = _T_563 & io_din[0]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_565 = _T_556 | _T_564; // @[el2_ifu_compress_ctl.scala 49:33]
wire _T_571 = _T_323 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_572 = _T_565 | _T_571; // @[el2_ifu_compress_ctl.scala 49:58]
wire _T_579 = _T_317 & io_din[10]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_580 = _T_579 & io_din[0]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_581 = _T_572 | _T_580; // @[el2_ifu_compress_ctl.scala 49:79]
wire _T_587 = _T_331 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_588 = _T_581 | _T_587; // @[el2_ifu_compress_ctl.scala 49:104]
wire _T_595 = _T_317 & io_din[9]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_596 = _T_595 & io_din[0]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_597 = _T_588 | _T_596; // @[el2_ifu_compress_ctl.scala 50:24]
wire _T_603 = _T_339 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_604 = _T_597 | _T_603; // @[el2_ifu_compress_ctl.scala 50:48]
wire _T_612 = _T_317 & _T_42; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_613 = _T_612 & io_din[0]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_614 = _T_604 | _T_613; // @[el2_ifu_compress_ctl.scala 50:69]
wire _T_620 = _T_347 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_621 = _T_614 | _T_620; // @[el2_ifu_compress_ctl.scala 50:94]
wire _T_628 = _T_317 & io_din[7]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_629 = _T_628 & io_din[0]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_630 = _T_621 | _T_629; // @[el2_ifu_compress_ctl.scala 51:22]
wire _T_634 = _T_190 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_635 = _T_630 | _T_634; // @[el2_ifu_compress_ctl.scala 51:46]
wire _T_641 = _T_190 & _T_4; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_642 = _T_641 & io_din[0]; // @[el2_ifu_compress_ctl.scala 15:110]
wire rdrd = _T_635 | _T_642; // @[el2_ifu_compress_ctl.scala 51:65]
wire _T_650 = _T_380 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_658 = _T_403 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_659 = _T_650 | _T_658; // @[el2_ifu_compress_ctl.scala 53:38]
wire _T_667 = _T_427 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_668 = _T_659 | _T_667; // @[el2_ifu_compress_ctl.scala 53:63]
wire _T_676 = _T_450 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_677 = _T_668 | _T_676; // @[el2_ifu_compress_ctl.scala 53:87]
wire _T_685 = _T_474 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_686 = _T_677 | _T_685; // @[el2_ifu_compress_ctl.scala 53:111]
wire _T_702 = _T_2 & _T_486; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_703 = _T_702 & _T_7; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_704 = _T_703 & _T_9; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_705 = _T_704 & _T_50; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_706 = _T_705 & _T_52; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_707 = _T_706 & _T_54; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_708 = _T_707 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_709 = _T_686 | _T_708; // @[el2_ifu_compress_ctl.scala 54:27]
wire _T_716 = _T_56 & io_din[6]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_717 = _T_716 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_718 = _T_709 | _T_717; // @[el2_ifu_compress_ctl.scala 54:65]
wire _T_725 = _T_56 & io_din[5]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_726 = _T_725 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_727 = _T_718 | _T_726; // @[el2_ifu_compress_ctl.scala 54:89]
wire _T_734 = _T_56 & io_din[4]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_735 = _T_734 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_736 = _T_727 | _T_735; // @[el2_ifu_compress_ctl.scala 54:113]
wire _T_743 = _T_56 & io_din[3]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_744 = _T_743 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_745 = _T_736 | _T_744; // @[el2_ifu_compress_ctl.scala 55:27]
wire _T_752 = _T_56 & io_din[2]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_753 = _T_752 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_754 = _T_745 | _T_753; // @[el2_ifu_compress_ctl.scala 55:51]
wire _T_763 = _T_194 & _T_4; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_764 = _T_763 & io_din[0]; // @[el2_ifu_compress_ctl.scala 15:110]
wire rdrs1 = _T_754 | _T_764; // @[el2_ifu_compress_ctl.scala 55:75]
wire _T_768 = io_din[15] & io_din[6]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_769 = _T_768 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_773 = io_din[15] & io_din[5]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_774 = _T_773 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_775 = _T_769 | _T_774; // @[el2_ifu_compress_ctl.scala 57:34]
wire _T_779 = io_din[15] & io_din[4]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_780 = _T_779 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_781 = _T_775 | _T_780; // @[el2_ifu_compress_ctl.scala 57:54]
wire _T_785 = io_din[15] & io_din[3]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_786 = _T_785 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_787 = _T_781 | _T_786; // @[el2_ifu_compress_ctl.scala 57:74]
wire _T_791 = io_din[15] & io_din[2]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_792 = _T_791 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_793 = _T_787 | _T_792; // @[el2_ifu_compress_ctl.scala 57:94]
wire _T_798 = _T_200 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire rs2rs2 = _T_793 | _T_798; // @[el2_ifu_compress_ctl.scala 57:114]
wire rdprd = _T_12 & io_din[0]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_811 = io_din[15] & _T_4; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_812 = _T_811 & io_din[0]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_818 = _T_812 | _T_234; // @[el2_ifu_compress_ctl.scala 61:36]
wire _T_821 = ~io_din[1]; // @[el2_ifu_compress_ctl.scala 15:83]
wire _T_822 = io_din[14] & _T_821; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_825 = _T_822 & _T_147; // @[el2_ifu_compress_ctl.scala 61:76]
wire rdprs1 = _T_818 | _T_825; // @[el2_ifu_compress_ctl.scala 61:57]
wire _T_837 = _T_128 & io_din[10]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_838 = _T_837 & io_din[0]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_842 = io_din[15] & _T_821; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_845 = _T_842 & _T_147; // @[el2_ifu_compress_ctl.scala 63:66]
wire rs2prs2 = _T_838 | _T_845; // @[el2_ifu_compress_ctl.scala 63:47]
wire _T_850 = _T_190 & _T_821; // @[el2_ifu_compress_ctl.scala 15:110]
wire rs2prd = _T_850 & _T_147; // @[el2_ifu_compress_ctl.scala 64:33]
wire _T_857 = _T_2 & _T_821; // @[el2_ifu_compress_ctl.scala 15:110]
wire uimm9_2 = _T_857 & _T_147; // @[el2_ifu_compress_ctl.scala 65:34]
wire _T_866 = _T_317 & _T_821; // @[el2_ifu_compress_ctl.scala 15:110]
wire ulwimm6_2 = _T_866 & _T_147; // @[el2_ifu_compress_ctl.scala 66:39]
wire ulwspimm7_2 = _T_317 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_888 = _T_317 & io_din[13]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_889 = _T_888 & _T_23; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_890 = _T_889 & _T_38; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_891 = _T_890 & _T_40; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_892 = _T_891 & io_din[8]; // @[el2_ifu_compress_ctl.scala 15:110]
wire rdeq2 = _T_892 & _T_44; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_981 = _T_450 & _T_7; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_982 = _T_981 & _T_9; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_983 = _T_982 & _T_50; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_984 = _T_983 & _T_52; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_985 = _T_984 & _T_54; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_986 = _T_985 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_987 = _T_434 | _T_986; // @[el2_ifu_compress_ctl.scala 70:42]
wire _T_1011 = _T_987 | _T_480; // @[el2_ifu_compress_ctl.scala 70:81]
wire _T_1018 = _T_194 & io_din[13]; // @[el2_ifu_compress_ctl.scala 15:110]
wire rdeq1 = _T_1011 | _T_1018; // @[el2_ifu_compress_ctl.scala 71:42]
wire _T_1041 = io_din[14] & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1042 = rdeq2 | _T_1041; // @[el2_ifu_compress_ctl.scala 72:53]
wire rs1eq2 = _T_1042 | uimm9_2; // @[el2_ifu_compress_ctl.scala 72:71]
wire _T_1083 = _T_357 & io_din[11]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1084 = _T_1083 & _T_38; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1085 = _T_1084 & io_din[0]; // @[el2_ifu_compress_ctl.scala 15:110]
wire simm5_0 = _T_1085 | _T_642; // @[el2_ifu_compress_ctl.scala 75:45]
wire _T_1103 = _T_888 & io_din[7]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1112 = _T_888 & _T_42; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1113 = _T_1103 | _T_1112; // @[el2_ifu_compress_ctl.scala 77:44]
wire _T_1121 = _T_888 & io_din[9]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1122 = _T_1113 | _T_1121; // @[el2_ifu_compress_ctl.scala 77:70]
wire _T_1130 = _T_888 & io_din[10]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1131 = _T_1122 | _T_1130; // @[el2_ifu_compress_ctl.scala 77:95]
wire _T_1139 = _T_888 & io_din[11]; // @[el2_ifu_compress_ctl.scala 15:110]
wire sluimm17_12 = _T_1131 | _T_1139; // @[el2_ifu_compress_ctl.scala 78:29]
wire uimm5_0 = _T_79 | _T_195; // @[el2_ifu_compress_ctl.scala 79:45]
wire [4:0] _T_1185 = rdrd ? rdd : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1186 = rdprd ? rdpd : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1187 = rs2prd ? rs2pd : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1188 = rdeq1 ? 5'h1 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1189 = rdeq2 ? 5'h2 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1190 = _T_1185 | _T_1186; // @[Mux.scala 27:72]
wire [4:0] _T_1191 = _T_1190 | _T_1187; // @[Mux.scala 27:72]
wire [4:0] _T_1192 = _T_1191 | _T_1188; // @[Mux.scala 27:72]
wire [4:0] l1_11 = _T_1192 | _T_1189; // @[Mux.scala 27:72]
wire [4:0] _T_1204 = rdrs1 ? rdd : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1205 = rdprs1 ? rdpd : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1206 = rs1eq2 ? 5'h2 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1207 = _T_1204 | _T_1205; // @[Mux.scala 27:72]
wire [4:0] l1_19 = _T_1207 | _T_1206; // @[Mux.scala 27:72]
wire [4:0] _T_1214 = {out_20,1'h0,1'h0,2'h0}; // @[el2_ifu_compress_ctl.scala 90:64]
wire [4:0] _T_1217 = rs2rs2 ? rs2d : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1218 = rs2prs2 ? rs2pd : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1219 = _T_1217 | _T_1218; // @[Mux.scala 27:72]
wire [4:0] l1_24 = _T_1214 | _T_1219; // @[el2_ifu_compress_ctl.scala 90:71]
wire [14:0] _T_1228 = {out_14,out_13,out_12,l1_11,2'h3,out_2,_T_228,out_4,out_5,out_6}; // @[Cat.scala 29:58]
wire [31:0] l1 = {4'h0,1'h0,out_30,1'h0,l1_24,l1_19,_T_1228}; // @[Cat.scala 29:58]
wire [5:0] simm5d = {io_din[12],rs2d}; // @[Cat.scala 29:58]
wire [5:0] simm9d = {io_din[12],io_din[4:3],io_din[5],io_din[2],io_din[6]}; // @[Cat.scala 29:58]
wire [8:0] sjald_12 = io_din[12] ? 9'h1ff : 9'h0; // @[Bitwise.scala 72:12]
wire [19:0] sjald = {sjald_12,io_din[12],io_din[8],io_din[10:9],io_din[6],io_din[7],io_din[2],io_din[11],io_din[5:4],io_din[3]}; // @[Cat.scala 29:58]
wire [14:0] _T_1277 = io_din[12] ? 15'h7fff : 15'h0; // @[Bitwise.scala 72:12]
wire [19:0] sluimmd = {_T_1277,rs2d}; // @[Cat.scala 29:58]
wire [6:0] _T_1283 = simm5d[5] ? 7'h7f : 7'h0; // @[Bitwise.scala 72:12]
wire [11:0] _T_1285 = {_T_1283,simm5d[4:0]}; // @[Cat.scala 29:58]
wire [11:0] _T_1288 = {2'h0,io_din[10:7],io_din[12:11],io_din[5],io_din[6],2'h0}; // @[Cat.scala 29:58]
wire [2:0] _T_1292 = simm9d[5] ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
wire [11:0] _T_1295 = {_T_1292,simm9d[4:0],4'h0}; // @[Cat.scala 29:58]
wire [11:0] _T_1298 = {5'h0,io_din[5],io_din[12:10],io_din[6],2'h0}; // @[Cat.scala 29:58]
wire [11:0] _T_1301 = {4'h0,io_din[3:2],io_din[12],io_din[6:4],2'h0}; // @[Cat.scala 29:58]
wire [11:0] _T_1303 = {6'h0,io_din[12],rs2d}; // @[Cat.scala 29:58]
wire [11:0] _T_1308 = {sjald[19],sjald[9:0],sjald[10]}; // @[Cat.scala 29:58]
wire [11:0] _T_1310 = simm5_0 ? _T_1285 : 12'h0; // @[Mux.scala 27:72]
wire [11:0] _T_1311 = uimm9_2 ? _T_1288 : 12'h0; // @[Mux.scala 27:72]
wire [11:0] _T_1312 = rdeq2 ? _T_1295 : 12'h0; // @[Mux.scala 27:72]
wire [11:0] _T_1313 = ulwimm6_2 ? _T_1298 : 12'h0; // @[Mux.scala 27:72]
wire [11:0] _T_1314 = ulwspimm7_2 ? _T_1301 : 12'h0; // @[Mux.scala 27:72]
wire [11:0] _T_1315 = uimm5_0 ? _T_1303 : 12'h0; // @[Mux.scala 27:72]
wire [11:0] _T_1316 = _T_228 ? _T_1308 : 12'h0; // @[Mux.scala 27:72]
wire [11:0] _T_1317 = sluimm17_12 ? sluimmd[19:8] : 12'h0; // @[Mux.scala 27:72]
wire [11:0] _T_1318 = _T_1310 | _T_1311; // @[Mux.scala 27:72]
wire [11:0] _T_1319 = _T_1318 | _T_1312; // @[Mux.scala 27:72]
wire [11:0] _T_1320 = _T_1319 | _T_1313; // @[Mux.scala 27:72]
wire [11:0] _T_1321 = _T_1320 | _T_1314; // @[Mux.scala 27:72]
wire [11:0] _T_1322 = _T_1321 | _T_1315; // @[Mux.scala 27:72]
wire [11:0] _T_1323 = _T_1322 | _T_1316; // @[Mux.scala 27:72]
wire [11:0] _T_1324 = _T_1323 | _T_1317; // @[Mux.scala 27:72]
wire [11:0] l2_31 = l1[31:20] | _T_1324; // @[el2_ifu_compress_ctl.scala 106:25]
wire [8:0] _T_1331 = _T_228 ? sjald[19:11] : 9'h0; // @[Mux.scala 27:72]
wire [7:0] _T_1332 = sluimm17_12 ? sluimmd[7:0] : 8'h0; // @[Mux.scala 27:72]
wire [8:0] _GEN_0 = {{1'd0}, _T_1332}; // @[Mux.scala 27:72]
wire [8:0] _T_1333 = _T_1331 | _GEN_0; // @[Mux.scala 27:72]
wire [8:0] _GEN_1 = {{1'd0}, l1[19:12]}; // @[el2_ifu_compress_ctl.scala 116:25]
wire [8:0] l2_19 = _GEN_1 | _T_1333; // @[el2_ifu_compress_ctl.scala 116:25]
wire [32:0] l2 = {l2_31,l2_19,l1[11:0]}; // @[Cat.scala 29:58]
wire [8:0] sbr8d = {io_din[12],io_din[6],io_din[5],io_din[2],io_din[11],io_din[10],io_din[4],io_din[3],1'h0}; // @[Cat.scala 29:58]
wire [6:0] uswimm6d = {io_din[5],io_din[12:10],io_din[6],2'h0}; // @[Cat.scala 29:58]
wire [7:0] uswspimm7d = {io_din[8:7],io_din[12:9],2'h0}; // @[Cat.scala 29:58]
wire [3:0] _T_1364 = sbr8d[8] ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
wire [6:0] _T_1366 = {_T_1364,sbr8d[7:5]}; // @[Cat.scala 29:58]
wire [6:0] _T_1369 = {5'h0,uswimm6d[6:5]}; // @[Cat.scala 29:58]
wire [6:0] _T_1372 = {4'h0,uswspimm7d[7:5]}; // @[Cat.scala 29:58]
wire [6:0] _T_1373 = _T_234 ? _T_1366 : 7'h0; // @[Mux.scala 27:72]
wire [6:0] _T_1374 = _T_845 ? _T_1369 : 7'h0; // @[Mux.scala 27:72]
wire [6:0] _T_1375 = _T_798 ? _T_1372 : 7'h0; // @[Mux.scala 27:72]
wire [6:0] _T_1376 = _T_1373 | _T_1374; // @[Mux.scala 27:72]
wire [6:0] _T_1377 = _T_1376 | _T_1375; // @[Mux.scala 27:72]
wire [6:0] l3_31 = l2[31:25] | _T_1377; // @[el2_ifu_compress_ctl.scala 122:25]
wire [12:0] l3_24 = l2[24:12]; // @[el2_ifu_compress_ctl.scala 125:17]
wire [4:0] _T_1383 = {sbr8d[4:1],sbr8d[8]}; // @[Cat.scala 29:58]
wire [4:0] _T_1388 = _T_234 ? _T_1383 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1389 = _T_845 ? uswimm6d[4:0] : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1390 = _T_798 ? uswspimm7d[4:0] : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_1391 = _T_1388 | _T_1389; // @[Mux.scala 27:72]
wire [4:0] _T_1392 = _T_1391 | _T_1390; // @[Mux.scala 27:72]
wire [4:0] l3_11 = l2[11:7] | _T_1392; // @[el2_ifu_compress_ctl.scala 126:24]
wire [31:0] l3 = {l3_31,l3_24,l3_11,l2[6:0]}; // @[Cat.scala 29:58]
wire _T_1403 = _T_4 & _T_486; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1404 = _T_1403 & io_din[11]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1405 = _T_1404 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1408 = _T_1405 & _T_147; // @[el2_ifu_compress_ctl.scala 131:39]
wire _T_1416 = _T_1403 & io_din[6]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1417 = _T_1416 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1420 = _T_1417 & _T_147; // @[el2_ifu_compress_ctl.scala 131:79]
wire _T_1421 = _T_1408 | _T_1420; // @[el2_ifu_compress_ctl.scala 131:54]
wire _T_1430 = _T_641 & io_din[11]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1431 = _T_1430 & _T_821; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1432 = _T_1421 | _T_1431; // @[el2_ifu_compress_ctl.scala 131:94]
wire _T_1440 = _T_1403 & io_din[5]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1441 = _T_1440 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1444 = _T_1441 & _T_147; // @[el2_ifu_compress_ctl.scala 132:55]
wire _T_1445 = _T_1432 | _T_1444; // @[el2_ifu_compress_ctl.scala 132:30]
wire _T_1453 = _T_1403 & io_din[10]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1454 = _T_1453 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1457 = _T_1454 & _T_147; // @[el2_ifu_compress_ctl.scala 132:96]
wire _T_1458 = _T_1445 | _T_1457; // @[el2_ifu_compress_ctl.scala 132:70]
wire _T_1467 = _T_641 & io_din[6]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1468 = _T_1467 & _T_821; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1469 = _T_1458 | _T_1468; // @[el2_ifu_compress_ctl.scala 132:111]
wire _T_1476 = io_din[15] & _T_486; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1477 = _T_1476 & _T_821; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1478 = _T_1477 & io_din[0]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1479 = _T_1469 | _T_1478; // @[el2_ifu_compress_ctl.scala 133:29]
wire _T_1487 = _T_1403 & io_din[9]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1488 = _T_1487 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1491 = _T_1488 & _T_147; // @[el2_ifu_compress_ctl.scala 133:79]
wire _T_1492 = _T_1479 | _T_1491; // @[el2_ifu_compress_ctl.scala 133:54]
wire _T_1499 = _T_486 & io_din[6]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1500 = _T_1499 & _T_821; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1501 = _T_1500 & io_din[0]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1502 = _T_1492 | _T_1501; // @[el2_ifu_compress_ctl.scala 133:94]
wire _T_1511 = _T_641 & io_din[5]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1512 = _T_1511 & _T_821; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1513 = _T_1502 | _T_1512; // @[el2_ifu_compress_ctl.scala 133:118]
wire _T_1521 = _T_1403 & io_din[8]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1522 = _T_1521 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1525 = _T_1522 & _T_147; // @[el2_ifu_compress_ctl.scala 134:28]
wire _T_1526 = _T_1513 | _T_1525; // @[el2_ifu_compress_ctl.scala 133:144]
wire _T_1533 = _T_486 & io_din[5]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1534 = _T_1533 & _T_821; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1535 = _T_1534 & io_din[0]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1536 = _T_1526 | _T_1535; // @[el2_ifu_compress_ctl.scala 134:43]
wire _T_1545 = _T_641 & io_din[10]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1546 = _T_1545 & _T_821; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1547 = _T_1536 | _T_1546; // @[el2_ifu_compress_ctl.scala 134:67]
wire _T_1555 = _T_1403 & io_din[7]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1556 = _T_1555 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1559 = _T_1556 & _T_147; // @[el2_ifu_compress_ctl.scala 135:28]
wire _T_1560 = _T_1547 | _T_1559; // @[el2_ifu_compress_ctl.scala 134:94]
wire _T_1568 = io_din[12] & io_din[11]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1569 = _T_1568 & _T_38; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1570 = _T_1569 & _T_821; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1571 = _T_1570 & io_din[0]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1572 = _T_1560 | _T_1571; // @[el2_ifu_compress_ctl.scala 135:43]
wire _T_1581 = _T_641 & io_din[9]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1582 = _T_1581 & _T_821; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1583 = _T_1572 | _T_1582; // @[el2_ifu_compress_ctl.scala 135:71]
wire _T_1591 = _T_1403 & io_din[4]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1592 = _T_1591 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1595 = _T_1592 & _T_147; // @[el2_ifu_compress_ctl.scala 136:28]
wire _T_1596 = _T_1583 | _T_1595; // @[el2_ifu_compress_ctl.scala 135:97]
wire _T_1602 = io_din[13] & io_din[12]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1603 = _T_1602 & _T_821; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1604 = _T_1603 & io_din[0]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1605 = _T_1596 | _T_1604; // @[el2_ifu_compress_ctl.scala 136:43]
wire _T_1614 = _T_641 & io_din[8]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1615 = _T_1614 & _T_821; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1616 = _T_1605 | _T_1615; // @[el2_ifu_compress_ctl.scala 136:67]
wire _T_1624 = _T_1403 & io_din[3]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1625 = _T_1624 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1628 = _T_1625 & _T_147; // @[el2_ifu_compress_ctl.scala 137:28]
wire _T_1629 = _T_1616 | _T_1628; // @[el2_ifu_compress_ctl.scala 136:93]
wire _T_1635 = io_din[13] & io_din[4]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1636 = _T_1635 & _T_821; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1637 = _T_1636 & io_din[0]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1638 = _T_1629 | _T_1637; // @[el2_ifu_compress_ctl.scala 137:43]
wire _T_1646 = _T_1403 & io_din[2]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1647 = _T_1646 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1650 = _T_1647 & _T_147; // @[el2_ifu_compress_ctl.scala 137:91]
wire _T_1651 = _T_1638 | _T_1650; // @[el2_ifu_compress_ctl.scala 137:66]
wire _T_1660 = _T_641 & io_din[7]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1661 = _T_1660 & _T_821; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1662 = _T_1651 | _T_1661; // @[el2_ifu_compress_ctl.scala 137:106]
wire _T_1668 = io_din[13] & io_din[3]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1669 = _T_1668 & _T_821; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1670 = _T_1669 & io_din[0]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1671 = _T_1662 | _T_1670; // @[el2_ifu_compress_ctl.scala 138:29]
wire _T_1677 = io_din[13] & io_din[2]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1678 = _T_1677 & _T_821; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1679 = _T_1678 & io_din[0]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1680 = _T_1671 | _T_1679; // @[el2_ifu_compress_ctl.scala 138:52]
wire _T_1686 = io_din[14] & _T_4; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1687 = _T_1686 & _T_821; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1688 = _T_1680 | _T_1687; // @[el2_ifu_compress_ctl.scala 138:75]
wire _T_1697 = _T_702 & _T_821; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1698 = _T_1697 & io_din[0]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1699 = _T_1688 | _T_1698; // @[el2_ifu_compress_ctl.scala 138:98]
wire _T_1706 = _T_811 & io_din[12]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1707 = _T_1706 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1710 = _T_1707 & _T_147; // @[el2_ifu_compress_ctl.scala 139:54]
wire _T_1711 = _T_1699 | _T_1710; // @[el2_ifu_compress_ctl.scala 139:29]
wire _T_1720 = _T_641 & _T_486; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1721 = _T_1720 & io_din[1]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1724 = _T_1721 & _T_147; // @[el2_ifu_compress_ctl.scala 139:96]
wire _T_1725 = _T_1711 | _T_1724; // @[el2_ifu_compress_ctl.scala 139:69]
wire _T_1734 = _T_641 & io_din[12]; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1735 = _T_1734 & _T_821; // @[el2_ifu_compress_ctl.scala 15:110]
wire _T_1736 = _T_1725 | _T_1735; // @[el2_ifu_compress_ctl.scala 139:111]
wire _T_1743 = _T_1686 & _T_147; // @[el2_ifu_compress_ctl.scala 140:50]
wire legal = _T_1736 | _T_1743; // @[el2_ifu_compress_ctl.scala 140:30]
wire [31:0] _T_1745 = legal ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
assign io_dout = l3 & _T_1745; // @[el2_ifu_compress_ctl.scala 142:10]
endmodule endmodule

15
src/main/scala/ifu/el2_ifu_aln_ctl.scala
View File

@ -95,23 +95,24 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
val aligndata = Mux1H(Seq(f0val(0).asBool -> q0final, (~f0val(1) & f0val(0)).asBool -> Cat(q1final,q0final))) val aligndata = Mux1H(Seq(f0val(0).asBool -> q0final, (~f0val(1) & f0val(0)).asBool -> Cat(q1final,q0final)))
val decompressed = Module(new el2_ifu_compress_ctl(32, true)) // val decompressed = Module(new el2_ifu_compress_ctl(32, true))
decompressed.io.in := aligndata //decompressed.io.in := aligndata
decompressed.io.out <> io.ifu_i0_instr //decompressed.io.out <> io.ifu_i0_instr
// 16-bit compressed instruction from the aligner to the dec for tracer // 16-bit compressed instruction from the aligner to the dec for tracer
io.ifu_i0_cinst := aligndata(15,0) io.ifu_i0_cinst := aligndata(15,0)
// Checking if its a 32-bit instruction or not // Checking if its a 32-bit instruction or not
val first4B = decompressed.io.rvc //val first4B = decompressed.io.rvc
val first4B = WireInit(Bool(), 0.U)
val first2B = ~first4B val first2B = ~first4B
val alignicaf = Mux1H(Seq(f0val(1).asBool -> f0icaf, (~f0val(1) & f0val(0)).asBool -> Cat(f1icaf,f0icaf))) val alignicaf = Mux1H(Seq(f0val(1).asBool -> f0icaf, (~f0val(1) & f0val(0)).asBool -> Cat(f1icaf,f0icaf)))
io.ifu_i0_icaf := Mux1H(Seq(first4B -> alignicaf.orR, first2B -> alignicaf(0))) io.ifu_i0_icaf := Mux1H(Seq(first4B.asBool -> alignicaf.orR, first2B.asBool -> alignicaf(0)))
io.ifu_i0_valid := Mux1H(Seq(first4B -> alignval(1), first2B -> alignval(0))) io.ifu_i0_valid := Mux1H(Seq(first4B.asBool -> alignval(1), first2B.asBool -> alignval(0)))
io.ifu_i0_pc4 := first4B io.ifu_i0_pc4 := first4B
val shift_2B = i0_shift & first2B val shift_2B = i0_shift & first2B
@ -325,7 +326,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
io.ifu_i0_icaf_f1 := first4B & icaf_eff & alignfromf1 io.ifu_i0_icaf_f1 := first4B & icaf_eff & alignfromf1
io.ifu_i0_dbecc := Mux1H(Seq(first4B->aligndbecc.orR, first2B->aligndbecc(0))) io.ifu_i0_dbecc := Mux1H(Seq(first4B.asBool->aligndbecc.orR, first2B.asBool->aligndbecc(0)))
val firstpc_hash = el2_btb_addr_hash(f0pc) val firstpc_hash = el2_btb_addr_hash(f0pc)

14
src/main/scala/ifu/el2_ifu_bp_ctl.scala
View File

@ -302,16 +302,16 @@ class el2_ifu_bp_ctl extends Module with el2_lib {
val bp_btb_target_adder_f = rvbradder(Cat(adder_pc_in_f(31,2),bp_total_branch_offset_f, 0.U), Cat(btb_rd_tgt_f,0.U)) val bp_btb_target_adder_f = rvbradder(Cat(adder_pc_in_f(31,2),bp_total_branch_offset_f, 0.U), Cat(btb_rd_tgt_f,0.U))
// //
val rets_out = Wire(Vec(RET_STACK_SIZE, UInt(32.W))) // val rets_out = Wire(Vec(RET_STACK_SIZE, UInt(32.W)))
rets_out := (0 until RET_STACK_SIZE).map(i=>0.U) // rets_out := (0 until RET_STACK_SIZE).map(i=>0.U)
io.ifu_bp_btb_target_f := Mux((btb_rd_ret_f & ~btb_rd_call_f & rets_out(0)(0)).asBool, // io.ifu_bp_btb_target_f := Mux((btb_rd_ret_f & ~btb_rd_call_f & rets_out(0)(0)).asBool,
rets_out(0)(31,1),bp_btb_target_adder_f(31,1)) // rets_out(0)(31,1),bp_btb_target_adder_f(31,1))
//val bp_rs_call_target_f = rvbradder(Cat(adder_pc_in_f(31,2),bp_total_branch_offset_f, 0.U), Cat(Fill(11, 0.U),~btb_rd_pc4_f, 0.U)) //val bp_rs_call_target_f = rvbradder(Cat(adder_pc_in_f(31,2),bp_total_branch_offset_f, 0.U), Cat(Fill(11, 0.U),~btb_rd_pc4_f, 0.U))
val rs_push = btb_rd_call_f & ~btb_rd_ret_f & ifu_bp_hit_taken_f // val rs_push = btb_rd_call_f & ~btb_rd_ret_f & ifu_bp_hit_taken_f
val rs_pop = btb_rd_ret_f & ~btb_rd_call_f & ifu_bp_hit_taken_f // val rs_pop = btb_rd_ret_f & ~btb_rd_call_f & ifu_bp_hit_taken_f
val rs_hold = ~rs_push & ~rs_pop // val rs_hold = ~rs_push & ~rs_pop
// Return stack // Return stack

143
src/main/scala/ifu/el2_ifu_compress_ctl.scala
View File

@ -3,6 +3,145 @@ package ifu
import chisel3._ import chisel3._
import chisel3.util._ import chisel3.util._
class el2_ifu_compress_ctl extends Module {
val io = IO(new Bundle{
val din = Input(UInt(16.W))
val dout = Output(UInt(32.W))
//val test = Output(Bool())
})
//io.dout := (0 until 32).map(i=> 0.U.asBool)
def pat(y : List[Int]) = (0 until y.size).map(i=> if(y(i)>=0) io.din(y(i)) else !io.din(y(i).abs)).reduce(_&_)
val out = Wire(Vec(32, Bool()))
out := (0 until 32).map(i=> 0.U.asBool)
out(30) := pat(List(15, -14, -13, 10, -6, -5, 0)) | pat(List(15, -14, -13, -11, 10, 0))
out(20) := pat(List(-14, 12, -11, -10, -9, -8, -7, -6, -5, -4, -3, -2, 1))
out(14) := pat(List(15, -14, -13, -11, 0)) | pat(List(15, -14, -13, -10, 0)) | pat(List(15, -14, -13, 6, 0)) |
pat(List(15, -14, -13, 5, 0))
out(13) := pat(List(15, -14, -13, 11, -10, 0)) | pat(List(15, -14, -13, 11, 6, 0)) | (io.din(14)&(!io.din(0)))
out(12) := pat(List(15, -14, -13, 6, 5, 0)) | pat(List(15, -14, -13, -11, 0)) | pat(List(15, -14, -13, -10, 0)) |
pat(List(-15, -14, 1)) | pat(List(15, 14, 13))
out(6) := (pat(List(15, -14, -6, -5, -4, -3, -2)) & !io.din(0)) | pat(List(-14, 13)) | pat(List(15, 14, 0))
out(5) := (io.din(15)&(!io.din(0))) | pat(List(15, 11, 10)) | pat(List(13, -8)) | pat(List(13, 7)) |
pat(List(13, 9)) | pat(List(13, 10)) | pat(List(13, 11)) | pat(List(-14, 13)) | pat(List(15, 14))
out(4) := (pat(List(-14, -11, -10, -9, -8, -7))&(!io.din(0))) | (pat(List(-15, -14))&(!io.din(0))) |
(pat(List(-14, 6))&(!io.din(0))) | pat(List(-15, 14, 0)) | (pat(List(-14, 5))&(!io.din(0))) |
(pat(List(-14, 4))&(!io.din(0))) | (pat(List(-14, 3))&(!io.din(0))) | (pat(List(-14, 2))&(!io.din(0))) |
pat(List(-14, -13, 0))
out(3) := pat(List(-14, 13))
out(2) := pat(List(-14, 12, 11, -6, -5, -4, -3, -2, 1)) | pat(List(-14, 12, 10, -6, -5, -4, -3, -2, 1)) |
pat(List(-14, 12, 9, -6, -5, -4, -3, -2, 1)) | pat(List(-14,12,8,6,-5,-4,-3,-2,1)) | pat(List(-14,12,7,-6,-5,-4,-3,-2,1)) |
(pat(List(15,-14,-12,-6,-5,-4,-3,-2))&(!io.din(0))) | pat(List(-15,13,-8)) | pat(List(-15,13,7)) | pat(List(-15,13,9)) |
pat(List(-15,13,10)) | pat(List(-15,13,11)) | pat(List(-14,13))
out(1) := 1.U.asBool
out(0) := 1.U.asBool
val rs2d = io.din(6,2)
val rdd = io.din(11,7)
val rdpd = Cat(1.U(2.W), io.din(9,7))
val rs2pd = Cat(1.U(2.W), io.din(4,2))
val rdrd = pat(List(-14,6,1)) | pat(List(-15,14,11,0)) | pat(List(-14,5,1)) | pat(List(-15,14,10,0)) |
pat(List(-14,4,1)) | pat(List(-15,14,9,0)) | pat(List(-14,3,1)) | pat(List(-15,14,-8,0)) |
pat(List(-14,2,1)) | pat(List(-15,14,7,0)) | pat(List(-15,1)) | pat(List(-15,-13,0))
val rdrs1 = pat(List(-14,12,11,1)) | pat(List(-14,12,10,1)) | pat(List(-14,12,9,1)) | pat(List(-14,12,8,1)) |
pat(List(-14,12,7,1)) | pat(List(-14,-12,-6,-5,-4,-3,-2,1)) | pat(List(-14,12,6,1)) | pat(List(-14,12,5,1)) |
pat(List(-14,12,4,1)) | pat(List(-14,12,3,1)) | pat(List(-14,12,2,1)) | pat(List(-15,-14,-13,0))
val rs2rs2 = pat(List(15,6,1)) | pat(List(15,5,1)) | pat(List(15,4,1)) | pat(List(15,3,1)) | pat(List(15,2,1)) | pat(List(15,14,1))
val rdprd = pat(List(15,-14,-13,0))
val rdprs1 = pat(List(15,-13,0)) | pat(List(15,14,0)) | (pat(List(14,-1))&(!io.din(0)))
val rs2prs2 = pat(List(15,-14,-13,11,10,0)) | (pat(List(15,-1))&(!io.din(0)))
val rs2prd = pat(List(-15,-1))&(!io.din(0))
val uimm9_2 = pat(List(-14,-1))&(!io.din(0))
val ulwimm6_2 = pat(List(-15,14,-1))&(!io.din(0))
val ulwspimm7_2 = pat(List(-15,14,1))
val rdeq2 = pat(List(-15,14,13,-11,-10,-9,8,-7))
val rdeq1 = pat(List(-14,12,11,-6,-5,-4,-3,-2,1)) | pat(List(-14,12,10,-6,-5,-4,-3,-2,1)) |
pat(List(-14,12,9,-6,-5,-4,-3,-2,1)) | pat(List(-14,12,8,-6,-5,-4,-3,-2,1)) |
pat(List(-14,12,7,-6,-5,-4,-3,-2,1)) | pat(List(-15,-14,13))
val rs1eq2 = pat(List(-15,14,13,-11,-10,-9,8,-7)) | pat(List(14,1)) | (pat(List(-14,-1))&(!io.din(0)))
val sbroffset8_1 = pat(List(15,14,0))
val simm9_4 = pat(List(-15,14,13,-11,-10,-9,8,-7))
val simm5_0 = pat(List(-14,-13,11,-10,0)) | pat(List(-15,-13,0))
val sjaloffset11_1 = pat(List(-14,13))
val sluimm17_12 = pat(List(-15,14,13,7)) | pat(List(-15,14,13,-8)) | pat(List(-15,14,13,9)) |
pat(List(-15,14,13,10)) | pat(List(-15,14,13,11))
val uimm5_0 = pat(List(15,-14,-13,-11,0)) | pat(List(-15,-14,1))
val uswimm6_2 = pat(List(15,-1))&(!io.din(0))
val uswspimm7_2 = pat(List(15,14,1))
val l1_6 = VecInit(out(6),out(5),out(4),out(3),out(2),out(1),out(0)).asUInt()
val l1_11 = VecInit(out(11),out(10),out(9),out(8),out(7)).asUInt | Mux1H(Seq(rdrd.asBool->rdd,
rdprd.asBool->rdpd, rs2prd.asBool->rs2pd, rdeq1.asBool->1.U(5.W), rdeq2.asBool->2.U(5.W)))
val l1_14 = Cat(out(14),out(13),out(12))
val l1_19 = VecInit(out(19),out(18),out(17),out(16),out(15)).asUInt | Mux1H(Seq(rdrs1.asBool->rdd,
rdprs1.asBool->rdpd, rs1eq2.asBool->2.U(5.W)))
val l1_24 = VecInit(out(24),out(23),out(22),out(21),out(20)).asUInt | Mux1H(Seq(rs2rs2.asBool->rs2d,
rs2prs2.asBool->rs2pd))
val l1_31 = VecInit(out(31),out(30),out(29),out(28),out(27),out(26),out(25)).asUInt
val l1 = Cat(l1_31,l1_24,l1_19,l1_14,l1_11,l1_6)
val simm5d = Cat(io.din(12), io.din(6,2))
val uimm9d = Cat(io.din(10,7), io.din(12,11), io.din(5), io.din(6))
val simm9d = Cat(io.din(12), io.din(4,3), io.din(5), io.din(2), io.din(6))
val ulwimm6d = Cat(io.din(5), io.din(12,10), io.din(6))
val ulwspimm7d = Cat(io.din(3,2), io.din(12), io.din(6,4))
val uimm5d = Cat(io.din(12), io.din(6,2))
val sjald_1 = Cat(io.din(12), io.din(8), io.din(10,9), io.din(6), io.din(7), io.din(2), io.din(11),
io.din(5,4), io.din(3))
val sjald_12 = Fill(9, io.din(12))
val sjald = Cat(sjald_12,sjald_1)
val sluimmd = Cat(Fill(15, io.din(12)), io.din(6,2))
val l2_31 = l1(31,20) |
Mux1H(Seq(simm5_0.asBool->Cat(Fill(7, simm5d(5)),simm5d(4,0)),
uimm9_2.asBool->Cat(0.U(2.W),uimm9d,0.U(2.W)),
simm9_4.asBool->Cat(Fill(3, simm9d(5)),simm9d(4,0),0.U(4.W)),
ulwimm6_2.asBool->Cat(0.U(5.W),ulwimm6d,0.U(2.W)),
ulwspimm7_2.asBool->Cat(0.U(4.W),ulwspimm7d,0.U(2.W)),
uimm5_0.asBool->Cat(0.U(6.W),uimm5d),
sjaloffset11_1->Cat(sjald(19),sjald(9,0),sjald(10)),
sluimm17_12->sluimmd(19,8)))
val l2_19 = l1(19,12) | Mux1H(Seq(sjaloffset11_1.asBool->sjald(19,11),
sluimm17_12.asBool->sluimmd(7,0)))
val l2 = Cat(l2_31, l2_19, l1(11,0))
val sbr8d = Cat(io.din(12),io.din(6),io.din(5),io.din(2),io.din(11),io.din(10),io.din(4),io.din(3),0.U)
val uswimm6d = Cat(io.din(5), io.din(12,10), io.din(6), 0.U(2.W))
val uswspimm7d = Cat(io.din(8,7),io.din(12,9), 0.U(2.W))
val l3_31 = l2(31,25) | Mux1H(Seq(sbroffset8_1.asBool->Cat(Fill(4,sbr8d(8)),sbr8d(7,5)),
uswimm6_2.asBool->Cat(0.U(5.W),uswimm6d(6,5)),
uswspimm7_2.asBool->Cat(0.U(4.W),uswspimm7d(7,5))))
val l3_24 = l2(24,12)
val l3_11 = l2(11,7) | Mux1H(Seq(sbroffset8_1.asBool->Cat(sbr8d(4,1), sbr8d(8)),
uswimm6_2.asBool->uswimm6d(4,0),
uswspimm7_2.asBool->uswspimm7d(4,0)))
val l3 = Cat(l3_31, l3_24, l3_11, l2(6,0))
val legal = (pat(List(-13,-12,11,1))&(!io.din(0))) | (pat(List(-13,-12,6,1))&(!io.din(0))) |
pat(List(-15,-13,11,-1)) | (pat(List(-13,-12,5,1))&(!io.din(0))) | (pat(List(-13,-12,10,1))&(!io.din(0))) |
pat(List(-15,-13,6,-1)) | pat(List(15,-12,-1,0)) | (pat(List(-13,-12,9,1))&(!io.din(0))) | pat(List(-12,6,-1,0)) | pat(List(-15,-13,5,-1)) |
(pat(List(-13,-12,8,1))&(!io.din(0))) | pat(List(-12,5,-1,0)) | pat(List(-15,-13,10,-1)) |
(pat(List(-13,-12,7,1))&(!io.din(0))) | pat(List(12,11,-10,-1,0)) | pat(List(-15,-13,9,-1)) |
(pat(List(-13,-12,4,1))&(!io.din(0))) | pat(List(13,12,-1,0)) | pat(List(-15,-13,8,-1)) |
(pat(List(-13,-12,3,1))&(!io.din(0))) | pat(List(13,4,-1,0)) | (pat(List(-13,-12,2,1))&(!io.din(0))) |
pat(List(-15,-13,7,-1)) | pat(List(13,3,-1,0)) | pat(List(13,2,-1,0)) | pat(List(14,-13,-1)) |
pat(List(-14,-12,-1,0)) | (pat(List(15,-13,12,1))&(!io.din(0))) | (pat(List(-15,-13,-12,1))&(!io.din(0))) |
pat(List(-15,-13,12,-1)) | (pat(List(14,-13))&(!io.din(0)))
io.dout:= l3 & Fill(32, legal)
}
/*
class ExpandedInstruction extends Bundle { class ExpandedInstruction extends Bundle {
val bits = UInt(32.W) val bits = UInt(32.W)
val rd = UInt(5.W) val rd = UInt(5.W)
@ -223,8 +362,8 @@ class el2_ifu_compress_ctl( val XLen: Int, val usingCompressed: Boolean) extends
//io.rvc := false.B //io.rvc := false.B
io.out := new RVCDecoder(io.in, XLen).passthrough io.out := new RVCDecoder(io.in, XLen).passthrough
} }
} }*/
object ifu_compress extends App { object ifu_compress extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_compress_ctl(64, true))) println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_compress_ctl()))
} }

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