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This commit is contained in:
waleed-lm 2020-10-14 18:32:40 +05:00
parent be35f6e577
commit 4e846f6ab3
4 changed files with 4 additions and 4 deletions
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4
el2_ifu_aln_ctl.fir
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@ -3102,8 +3102,8 @@ circuit el2_ifu_aln_ctl :
node _T_762 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 396:57] node _T_762 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 396:57]
node _T_763 = or(first2B, _T_762) @[el2_ifu_aln_ctl.scala 396:45] node _T_763 = or(first2B, _T_762) @[el2_ifu_aln_ctl.scala 396:45]
node _T_764 = bits(_T_763, 0, 0) @[el2_ifu_aln_ctl.scala 396:62] node _T_764 = bits(_T_763, 0, 0) @[el2_ifu_aln_ctl.scala 396:62]
node _T_765 = bits(f0pc, 1, 1) @[el2_ifu_aln_ctl.scala 396:77] node _T_765 = bits(f0pc, 0, 0) @[el2_ifu_aln_ctl.scala 396:77]
node _T_766 = bits(secondpc, 1, 1) @[el2_ifu_aln_ctl.scala 396:90] node _T_766 = bits(secondpc, 0, 0) @[el2_ifu_aln_ctl.scala 396:90]
node _T_767 = mux(_T_764, _T_765, _T_766) @[el2_ifu_aln_ctl.scala 396:35] node _T_767 = mux(_T_764, _T_765, _T_766) @[el2_ifu_aln_ctl.scala 396:35]
io.i0_brp.bank <= _T_767 @[el2_ifu_aln_ctl.scala 396:29] io.i0_brp.bank <= _T_767 @[el2_ifu_aln_ctl.scala 396:29]
node _T_768 = and(io.i0_brp.valid, i0_brp_pc4) @[el2_ifu_aln_ctl.scala 398:42] node _T_768 = and(io.i0_brp.valid, i0_brp_pc4) @[el2_ifu_aln_ctl.scala 398:42]

2
el2_ifu_aln_ctl.v
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@ -991,7 +991,7 @@ module el2_ifu_aln_ctl(
assign io_i0_brp_hist = {_T_747,_T_752}; // @[el2_ifu_aln_ctl.scala 386:18] assign io_i0_brp_hist = {_T_747,_T_752}; // @[el2_ifu_aln_ctl.scala 386:18]
assign io_i0_brp_br_error = _T_769 | _T_772; // @[el2_ifu_aln_ctl.scala 398:22] assign io_i0_brp_br_error = _T_769 | _T_772; // @[el2_ifu_aln_ctl.scala 398:22]
assign io_i0_brp_br_start_error = _T_657 & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 394:29] assign io_i0_brp_br_start_error = _T_657 & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 394:29]
assign io_i0_brp_bank = _T_738 ? f0pc[1] : secondpc[1]; // @[el2_ifu_aln_ctl.scala 396:29] assign io_i0_brp_bank = _T_738 ? f0pc[0] : secondpc[0]; // @[el2_ifu_aln_ctl.scala 396:29]
assign io_i0_brp_prett = i0_ends_f1 ? f1prett : f0prett; // @[el2_ifu_aln_ctl.scala 392:19] assign io_i0_brp_prett = i0_ends_f1 ? f1prett : f0prett; // @[el2_ifu_aln_ctl.scala 392:19]
assign io_i0_brp_way = _T_738 ? alignway[0] : alignway[1]; // @[el2_ifu_aln_ctl.scala 384:17] assign io_i0_brp_way = _T_738 ? alignway[0] : alignway[1]; // @[el2_ifu_aln_ctl.scala 384:17]
assign io_i0_brp_ret = _T_729 | _T_731; // @[el2_ifu_aln_ctl.scala 380:17] assign io_i0_brp_ret = _T_729 | _T_731; // @[el2_ifu_aln_ctl.scala 380:17]

2
src/main/scala/ifu/el2_ifu_aln_ctl.scala
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@ -393,7 +393,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib with RequireAsyncReset {
io.i0_brp.br_start_error := (first4B & alignval(1) & alignbrend(0)) io.i0_brp.br_start_error := (first4B & alignval(1) & alignbrend(0))
io.i0_brp.bank := Mux((first2B | alignbrend(0)).asBool, firstpc(1), secondpc(1)) io.i0_brp.bank := Mux((first2B | alignbrend(0)).asBool, firstpc(0), secondpc(0))
io.i0_brp.br_error := (io.i0_brp.valid & i0_brp_pc4 & first2B) | (io.i0_brp.valid & !i0_brp_pc4 & first4B) io.i0_brp.br_error := (io.i0_brp.valid & i0_brp_pc4 & first2B) | (io.i0_brp.valid & !i0_brp_pc4 & first4B)

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target/scala-2.12/classes/ifu/el2_ifu_aln_ctl.class
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