el2_lib comp

el2_ifu_bp_ctl.anno.json

@@ -3,7 +3,8 @@
     "class":"firrtl.transforms.CombinationalPath",
     "sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_out",
     "sources":[
-      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_in"
+      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_in",
+      "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_in2"
     ]
   },
   {

el2_ifu_bp_ctl.fir

@@ -3,16 +3,10 @@ circuit el2_ifu_bp_ctl :
   module el2_ifu_bp_ctl : 
     input clock : Clock
     input reset : UInt<1>
-    output io : {flip in : UInt<32>, out : UInt}
+    output io : {flip in : UInt<32>, flip in2 : UInt<32>, out : UInt}
     
-    node _T = bits(io.in, 14, 10) @[el2_lib.scala 18:33]
-    node _T_1 = bits(io.in, 19, 15) @[el2_lib.scala 18:33]
-    node _T_2 = bits(io.in, 24, 20) @[el2_lib.scala 18:33]
-    wire _T_3 : UInt<5>[3] @[el2_lib.scala 18:25]
-    _T_3[0] <= _T @[el2_lib.scala 18:25]
-    _T_3[1] <= _T_1 @[el2_lib.scala 18:25]
-    _T_3[2] <= _T_2 @[el2_lib.scala 18:25]
-    node _T_4 = xor(_T_3[0], _T_3[1]) @[el2_lib.scala 18:113]
-    node _T_5 = xor(_T_4, _T_3[2]) @[el2_lib.scala 18:113]
-    io.out <= _T_5 @[el2_ifu_bp_ctl.scala 12:10]
+    node _T = bits(io.in, 9, 2) @[el2_lib.scala 32:16]
+    node _T_1 = bits(io.in2, 7, 0) @[el2_lib.scala 32:40]
+    node _T_2 = xor(_T, _T_1) @[el2_lib.scala 32:35]
+    io.out <= _T_2 @[el2_ifu_bp_ctl.scala 13:10]
     

el2_ifu_bp_ctl.v

@@ -2,8 +2,8 @@ module el2_ifu_bp_ctl(
   input         clock,
   input         reset,
   input  [31:0] io_in,
-  output [4:0]  io_out
+  input  [31:0] io_in2,
+  output [7:0]  io_out
 );
-  wire [4:0] _T_4 = io_in[14:10] ^ io_in[19:15]; // @[el2_lib.scala 18:113]
-  assign io_out = _T_4 ^ io_in[24:20]; // @[el2_ifu_bp_ctl.scala 12:10]
+  assign io_out = io_in[9:2] ^ io_in2[7:0]; // @[el2_ifu_bp_ctl.scala 13:10]
 endmodule

src/main/scala/ifu/el2_ifu_bp_ctl.scala

@@ -7,9 +7,10 @@ import chisel3.util._
 class el2_ifu_bp_ctl extends Module with el2_lib {
   val io = IO (new Bundle {
     val in = Input(UInt(32.W))
+    val in2 = Input(UInt(32.W))
     val out = Output(UInt())
   })
-  io.out := el2_btb_tag_hash(io.in) | el2_btb_tag_hash(io.in)
+  io.out := el2_btb_ghr_hash(io.in,io.in2)
 }
 
 object ifu extends App {

src/main/scala/lib/el2_lib.scala

@@ -1,16 +1,19 @@
 package lib
-
 import chisel3._
+import chisel3.util._
 trait param {
   val BTB_ADDR_HI      = 9
   val BTB_ADDR_LO      = 2
   val BTB_BTAG_SIZE    = 5
+  val BTB_FOLD2_INDEX_HASH = false
   val BTB_INDEX1_HI    = 9
   val BTB_INDEX1_LO    = 2
   val BTB_INDEX2_HI    = 17
   val BTB_INDEX2_LO    = 10
   val BTB_INDEX3_HI    = 25
   val BTB_INDEX3_LO    = 18
+  val BHT_GHR_HASH_1   = false
+  val BHT_GHR_SIZE     = 8
 }
 
 trait el2_lib extends param{
@@ -20,6 +23,11 @@ trait el2_lib extends param{
   def el2_btb_tag_hash_fold(pc : UInt) =
     pc(BTB_ADDR_HI+(2*BTB_BTAG_SIZE),BTB_ADDR_HI+BTB_BTAG_SIZE+1)^pc(BTB_ADDR_HI+BTB_BTAG_SIZE,BTB_ADDR_HI+1)
 
-  def el2_btb_addr_hash(pc : UInt) : UInt = 0.U
-  //  def el2_btb_ghr_hash
+  def el2_btb_addr_hash(pc : UInt) =
+    if(BTB_FOLD2_INDEX_HASH) pc(BTB_INDEX1_HI,BTB_INDEX1_LO) ^ pc(BTB_INDEX3_HI,BTB_INDEX3_LO)
+    else pc(BTB_INDEX1_HI,BTB_INDEX1_LO) ^ pc(BTB_INDEX2_HI,BTB_INDEX2_LO) ^ pc(BTB_INDEX3_HI,BTB_INDEX3_LO)
+
+  def el2_btb_ghr_hash(hashin : UInt, ghr :UInt) =
+    if(BHT_GHR_HASH_1) Cat(ghr(BHT_GHR_SIZE-1,BTB_INDEX1_HI), hashin(BTB_INDEX1_HI,2) ^ ghr(BTB_INDEX1_HI-2,0))
+    else hashin(BHT_GHR_SIZE+1,2) ^ ghr(BHT_GHR_SIZE-1,0)
 }