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Bus-buffer testing start

This commit is contained in:
waleed-lm 2020-11-08 18:39:05 +05:00
parent d952fb425f
commit 4f7bcc4096
4 changed files with 3 additions and 3 deletions
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2
el2_lsu_bus_buffer.fir
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@ -5954,7 +5954,7 @@ circuit el2_lsu_bus_buffer :
io.lsu_bus_buffer_pend_any <= _T_4515 @[el2_lsu_bus_buffer.scala 585:30]
node _T_4516 = and(io.ldst_dual_d, io.dec_lsu_valid_raw_d) @[el2_lsu_bus_buffer.scala 586:52]
node _T_4517 = geq(buf_numvld_any, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 586:92]
node _T_4518 = eq(buf_numvld_any, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 586:119]
node _T_4518 = eq(buf_numvld_any, UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 586:121]
node _T_4519 = mux(_T_4516, _T_4517, _T_4518) @[el2_lsu_bus_buffer.scala 586:36]
io.lsu_bus_buffer_full_any <= _T_4519 @[el2_lsu_bus_buffer.scala 586:30]
node _T_4520 = orr(buf_state[0]) @[el2_lsu_bus_buffer.scala 587:52]

2
el2_lsu_bus_buffer.v
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@ -2463,7 +2463,7 @@ module el2_lsu_bus_buffer(
wire [3:0] buf_numvld_any = _T_4438 + _T_4445; // @[el2_lsu_bus_buffer.scala 580:169]
wire _T_4516 = io_ldst_dual_d & io_dec_lsu_valid_raw_d; // @[el2_lsu_bus_buffer.scala 586:52]
wire _T_4517 = buf_numvld_any >= 4'h3; // @[el2_lsu_bus_buffer.scala 586:92]
wire _T_4518 = buf_numvld_any == 4'h3; // @[el2_lsu_bus_buffer.scala 586:119]
wire _T_4518 = buf_numvld_any == 4'h4; // @[el2_lsu_bus_buffer.scala 586:121]
wire _T_4520 = |buf_state_0; // @[el2_lsu_bus_buffer.scala 587:52]
wire _T_4521 = |buf_state_1; // @[el2_lsu_bus_buffer.scala 587:52]
wire _T_4522 = |buf_state_2; // @[el2_lsu_bus_buffer.scala 587:52]

2
src/main/scala/lsu/el2_lsu_bus_buffer.scala
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@ -583,7 +583,7 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
buf_numvld_pend_any := (0 until DEPTH).map(i=>((buf_state(i)===wait_C) | ((buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i))).asUInt).reverse.reduce(_ +& _)
any_done_wait_state := (0 until DEPTH).map(i=>buf_state(i)===done_wait_C).reverse.reduce(_|_)
io.lsu_bus_buffer_pend_any := buf_numvld_pend_any.orR
io.lsu_bus_buffer_full_any := Mux(io.ldst_dual_d & io.dec_lsu_valid_raw_d, buf_numvld_any>=(DEPTH-1), buf_numvld_any===(DEPTH-1))
io.lsu_bus_buffer_full_any := Mux(io.ldst_dual_d & io.dec_lsu_valid_raw_d, buf_numvld_any>=(DEPTH-1).U, buf_numvld_any===DEPTH.U)
io.lsu_bus_buffer_empty_any := !(buf_state.map(_.orR).reduce(_|_)) & !ibuf_valid & !obuf_valid
io.lsu_nonblock_load_valid_m := io.lsu_busreq_m & io.lsu_pkt_m.valid & io.lsu_pkt_m.load & !io.flush_m_up & !io.ld_full_hit_m

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target/scala-2.12/classes/lsu/el2_lsu_bus_buffer.class
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