diff --git a/el2_ifu_bp_ctl.fir b/el2_ifu_bp_ctl.fir
index 9f276f1c..cd77b3b7 100644
--- a/el2_ifu_bp_ctl.fir
+++ b/el2_ifu_bp_ctl.fir
@@ -439,7 +439,7 @@ circuit el2_ifu_bp_ctl :
     node _T_301 = bits(bht_valid_f, 0, 0) @[el2_ifu_bp_ctl.scala 268:49]
     node num_valids = add(_T_300, _T_301) @[el2_ifu_bp_ctl.scala 268:35]
     node _T_302 = and(btb_sel_f, bht_dir_f) @[el2_ifu_bp_ctl.scala 270:28]
-    node final_h = andr(_T_302) @[el2_ifu_bp_ctl.scala 270:41]
+    node final_h = orr(_T_302) @[el2_ifu_bp_ctl.scala 270:41]
     wire fghr : UInt<8>
     fghr <= UInt<1>("h00")
     node _T_303 = eq(num_valids, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 274:41]
@@ -482,8 +482,8 @@ circuit el2_ifu_bp_ctl :
     node _T_338 = or(_T_337, _T_336) @[Mux.scala 27:72]
     wire fghr_ns : UInt<8> @[Mux.scala 27:72]
     fghr_ns <= _T_338 @[Mux.scala 27:72]
-    reg _T_339 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_bp_ctl.scala 284:18]
-    _T_339 <= fghr_ns @[el2_ifu_bp_ctl.scala 284:18]
+    reg _T_339 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_bp_ctl.scala 284:44]
+    _T_339 <= fghr_ns @[el2_ifu_bp_ctl.scala 284:44]
     fghr <= _T_339 @[el2_ifu_bp_ctl.scala 284:8]
     io.ifu_bp_fghr_f <= fghr @[el2_ifu_bp_ctl.scala 286:20]
     io.ifu_bp_way_f <= way_raw @[el2_ifu_bp_ctl.scala 288:19]
diff --git a/el2_ifu_bp_ctl.v b/el2_ifu_bp_ctl.v
index 16ed71c3..d71d9035 100644
--- a/el2_ifu_bp_ctl.v
+++ b/el2_ifu_bp_ctl.v
@@ -4244,7 +4244,7 @@ module el2_ifu_bp_ctl(
   wire  _T_244 = btb_vbank0_rd_data_f[2] | btb_vbank0_rd_data_f[1]; // @[el2_ifu_bp_ctl.scala 237:59]
   wire [1:0] bht_force_taken_f = {_T_241,_T_244}; // @[Cat.scala 29:58]
   wire [9:0] _T_566 = {btb_rd_addr_f,2'h0}; // @[Cat.scala 29:58]
-  reg [7:0] fghr; // @[el2_ifu_bp_ctl.scala 284:18]
+  reg [7:0] fghr; // @[el2_ifu_bp_ctl.scala 284:44]
   wire [7:0] bht_rd_addr_f = _T_566[9:2] ^ fghr; // @[el2_lib.scala 188:35]
   wire  _T_20797 = bht_rd_addr_f == 8'h0; // @[el2_ifu_bp_ctl.scala 388:106]
   reg [1:0] bht_bank_rd_data_out_1_0; // @[Reg.scala 27:20]
@@ -6915,7 +6915,7 @@ module el2_ifu_bp_ctl(
   wire  _T_299 = _T_297 & btb_vbank0_rd_data_f[1]; // @[el2_ifu_bp_ctl.scala 265:65]
   wire [1:0] num_valids = bht_valid_f[1] + bht_valid_f[0]; // @[el2_ifu_bp_ctl.scala 268:35]
   wire [1:0] _T_302 = btb_sel_f & bht_dir_f; // @[el2_ifu_bp_ctl.scala 270:28]
-  wire  final_h = &_T_302; // @[el2_ifu_bp_ctl.scala 270:41]
+  wire  final_h = |_T_302; // @[el2_ifu_bp_ctl.scala 270:41]
   wire  _T_303 = num_valids == 2'h2; // @[el2_ifu_bp_ctl.scala 274:41]
   wire [7:0] _T_307 = {fghr[5:0],1'h0,final_h}; // @[Cat.scala 29:58]
   wire  _T_308 = num_valids == 2'h1; // @[el2_ifu_bp_ctl.scala 275:41]
@@ -14215,11 +14215,6 @@ end // initial
     end else if (_T_2106) begin
       btb_bank0_rd_data_way1_out_255 <= btb_wr_data;
     end
-    if (reset) begin
-      fghr <= 8'h0;
-    end else begin
-      fghr <= fghr_ns;
-    end
     if (reset) begin
       bht_bank_rd_data_out_1_0 <= 2'h0;
     end else if (bht_bank_sel_1_0_0) begin
@@ -18889,4 +18884,11 @@ end // initial
       rets_out_7 <= rets_out_6;
     end
   end
+  always @(posedge io_active_clk) begin
+    if (reset) begin
+      fghr <= 8'h0;
+    end else begin
+      fghr <= fghr_ns;
+    end
+  end
 endmodule
diff --git a/src/main/scala/ifu/el2_ifu_bp_ctl.scala b/src/main/scala/ifu/el2_ifu_bp_ctl.scala
index f0cf1803..d55404a5 100644
--- a/src/main/scala/ifu/el2_ifu_bp_ctl.scala
+++ b/src/main/scala/ifu/el2_ifu_bp_ctl.scala
@@ -267,7 +267,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib {
   //GHR
   val num_valids = bht_valid_f(1) +& bht_valid_f(0) // countones
 
-  val final_h = (btb_sel_f & bht_dir_f).andR
+  val final_h = (btb_sel_f & bht_dir_f).orR
 
   val fghr = WireInit(UInt(BHT_GHR_SIZE.W), 0.U)
 
@@ -281,7 +281,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib {
                          (!exu_flush_final_d1 & io.ifc_fetch_req_f & io.ic_hit_f & !leak_one_f_d1).asBool -> merged_ghr,
                          (!exu_flush_final_d1 & !(io.ifc_fetch_req_f & io.ic_hit_f & !leak_one_f_d1)).asBool -> fghr))
 
-  fghr := RegNext(fghr_ns, init = 0.U)
+  fghr := withClock(io.active_clk) {RegNext(fghr_ns, init = 0.U)}
 
   io.ifu_bp_fghr_f := fghr
 
diff --git a/target/scala-2.12/classes/ifu/el2_ifu_bp_ctl.class b/target/scala-2.12/classes/ifu/el2_ifu_bp_ctl.class
index fdc85a45..6747bf03 100644
Binary files a/target/scala-2.12/classes/ifu/el2_ifu_bp_ctl.class and b/target/scala-2.12/classes/ifu/el2_ifu_bp_ctl.class differ
diff --git a/target/scala-2.12/classes/ifu/ifu_bp$.class b/target/scala-2.12/classes/ifu/ifu_bp$.class
index 0e10394b..98968cce 100644
Binary files a/target/scala-2.12/classes/ifu/ifu_bp$.class and b/target/scala-2.12/classes/ifu/ifu_bp$.class differ