From 53681a9b6f3128ce9d7b170cd4cc60c692960e61 Mon Sep 17 00:00:00 2001 From: waleed-lm Date: Wed, 30 Sep 2020 15:17:21 +0500 Subject: [PATCH] Async reset done in IFC --- EL2_IC_DATA.anno.json | 10 + EL2_IC_DATA.fir | 208 ++++++++++++++---- EL2_IC_DATA.v | 7 +- el2_ifu_ifc_ctrl.fir | 2 +- el2_ifu_ifc_ctrl.v | 44 +++- src/main/scala/ifu/el2_ifu_ic_mem.scala | 54 ++++- src/main/scala/ifu/el2_ifu_ifc_ctrl.scala | 2 +- .../classes/ifu/EL2_IC_DATA$$anon$3.class | Bin 4876 -> 4830 bytes .../scala-2.12/classes/ifu/EL2_IC_DATA.class | Bin 55968 -> 71145 bytes .../classes/ifu/el2_ifu_ifc_ctrl.class | Bin 111824 -> 112207 bytes target/scala-2.12/classes/ifu/ifu_ic$.class | Bin 3862 -> 3862 bytes .../classes/ifu/ifu_ic$delayedInit$body.class | Bin 729 -> 729 bytes 12 files changed, 268 insertions(+), 59 deletions(-) diff --git a/EL2_IC_DATA.anno.json b/EL2_IC_DATA.anno.json index 16430c21..d417ca7f 100644 --- a/EL2_IC_DATA.anno.json +++ b/EL2_IC_DATA.anno.json @@ -1,4 +1,14 @@ [ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~EL2_IC_DATA|EL2_IC_DATA>io_test", + "sources":[ + "~EL2_IC_DATA|EL2_IC_DATA>io_ic_rw_addr", + "~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_addr", + "~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_rd_en", + "~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_wr_en" + ] + }, { "class":"firrtl.EmitCircuitAnnotation", "emitter":"firrtl.VerilogEmitter" diff --git a/EL2_IC_DATA.fir b/EL2_IC_DATA.fir index 5005cb53..c2123084 100644 --- a/EL2_IC_DATA.fir +++ b/EL2_IC_DATA.fir @@ -3,54 +3,184 @@ circuit EL2_IC_DATA : module EL2_IC_DATA : input clock : Clock input reset : UInt<1> - output io : {flip clk_override : UInt<1>, flip ic_rw_addr : UInt<12>, flip ic_wr_en : UInt<2>, flip ic_rd_en : UInt<1>, flip ic_wr_data : UInt<71>[2], ic_rd_data : UInt<64>, flip ic_debug_wr_data : UInt<71>, ic_debug_rd_data : UInt<71>, ic_parerr : UInt<2>, ic_eccerr : UInt<2>, flip ic_debug_addr : UInt<9>, flip ic_debug_rd_en : UInt<1>, flip ic_debug_wr_en : UInt<1>, flip ic_debug_tag_array : UInt<1>, flip ic_debug_way : UInt<2>, flip ic_premux_data : UInt<64>, flip ic_sel_premux_data : UInt<1>, flip ic_rd_hit : UInt<2>, flip scan_mode : UInt<1>} + output io : {flip clk_override : UInt<1>, flip ic_rw_addr : UInt<12>, flip ic_wr_en : UInt<2>, flip ic_rd_en : UInt<1>, flip ic_wr_data : UInt<71>[2], ic_rd_data : UInt<64>, flip ic_debug_wr_data : UInt<71>, ic_debug_rd_data : UInt<71>, ic_parerr : UInt<2>, ic_eccerr : UInt<2>, flip ic_debug_addr : UInt<9>, flip ic_debug_rd_en : UInt<1>, flip ic_debug_wr_en : UInt<1>, flip ic_debug_tag_array : UInt<1>, flip ic_debug_way : UInt<2>, flip ic_premux_data : UInt<64>, flip ic_sel_premux_data : UInt<1>, flip ic_rd_hit : UInt<2>, flip scan_mode : UInt<1>, test : UInt} io.ic_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 194:17] io.ic_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 195:23] io.ic_parerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 196:16] io.ic_eccerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 197:16] - node _T = eq(io.ic_debug_tag_array, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 198:70] - node _T_1 = and(io.ic_debug_rd_en, _T) @[el2_ifu_ic_mem.scala 198:68] + io.test <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 198:11] + node _T = eq(io.ic_debug_tag_array, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 200:70] + node _T_1 = and(io.ic_debug_rd_en, _T) @[el2_ifu_ic_mem.scala 200:68] node _T_2 = bits(_T_1, 0, 0) @[Bitwise.scala 72:15] node _T_3 = mux(_T_2, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node ic_debug_rd_way_en = and(_T_3, io.ic_debug_way) @[el2_ifu_ic_mem.scala 198:94] - node _T_4 = eq(io.ic_debug_tag_array, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 199:70] - node _T_5 = and(io.ic_debug_wr_en, _T_4) @[el2_ifu_ic_mem.scala 199:68] + node ic_debug_rd_way_en = and(_T_3, io.ic_debug_way) @[el2_ifu_ic_mem.scala 200:94] + node _T_4 = eq(io.ic_debug_tag_array, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 201:70] + node _T_5 = and(io.ic_debug_wr_en, _T_4) @[el2_ifu_ic_mem.scala 201:68] wire _T_6 : UInt<1>[2] @[el2_lib.scala 185:48] _T_6[0] <= _T_5 @[el2_lib.scala 185:48] _T_6[1] <= _T_5 @[el2_lib.scala 185:48] node _T_7 = cat(_T_6[0], _T_6[1]) @[Cat.scala 29:58] - node ic_debug_wr_way_en = and(_T_7, io.ic_debug_way) @[el2_ifu_ic_mem.scala 199:94] - node _T_8 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 202:78] - node _T_9 = eq(_T_8, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 202:113] - node _T_10 = bits(_T_9, 0, 0) @[Bitwise.scala 72:15] - node _T_11 = mux(_T_10, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_12 = and(ic_debug_wr_way_en, _T_11) @[el2_ifu_ic_mem.scala 202:38] - node _T_13 = or(io.ic_wr_en, _T_12) @[el2_ifu_ic_mem.scala 202:17] - node _T_14 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 203:21] - node _T_15 = eq(_T_14, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 203:56] - node _T_16 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 202:78] - node _T_17 = eq(_T_16, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 202:113] - node _T_18 = bits(_T_17, 0, 0) @[Bitwise.scala 72:15] - node _T_19 = mux(_T_18, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_20 = and(ic_debug_wr_way_en, _T_19) @[el2_ifu_ic_mem.scala 202:38] - node _T_21 = or(io.ic_wr_en, _T_20) @[el2_ifu_ic_mem.scala 202:17] - node _T_22 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 203:21] - node _T_23 = eq(_T_22, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 203:56] - node _T_24 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 202:78] - node _T_25 = eq(_T_24, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 202:113] - node _T_26 = bits(_T_25, 0, 0) @[Bitwise.scala 72:15] - node _T_27 = mux(_T_26, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_28 = and(ic_debug_wr_way_en, _T_27) @[el2_ifu_ic_mem.scala 202:38] - node _T_29 = or(io.ic_wr_en, _T_28) @[el2_ifu_ic_mem.scala 202:17] - node _T_30 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 203:21] - node _T_31 = eq(_T_30, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 203:56] - node _T_32 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 202:78] - node _T_33 = eq(_T_32, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 202:113] - node _T_34 = bits(_T_33, 0, 0) @[Bitwise.scala 72:15] - node _T_35 = mux(_T_34, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_36 = and(ic_debug_wr_way_en, _T_35) @[el2_ifu_ic_mem.scala 202:38] - node _T_37 = or(io.ic_wr_en, _T_36) @[el2_ifu_ic_mem.scala 202:17] - node _T_38 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 203:21] - node _T_39 = eq(_T_38, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 203:56] + node ic_debug_wr_way_en = and(_T_7, io.ic_debug_way) @[el2_ifu_ic_mem.scala 201:94] + wire ic_bank_wr_data : UInt<71> + ic_bank_wr_data <= UInt<1>("h00") + wire ic_rd_en_with_debug : UInt<1> + ic_rd_en_with_debug <= UInt<1>("h00") + node _T_8 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_ic_mem.scala 206:45] + node _T_9 = bits(_T_8, 0, 0) @[el2_ifu_ic_mem.scala 206:66] + node _T_10 = cat(io.ic_debug_addr, UInt<2>("h00")) @[Cat.scala 29:58] + node ic_rw_addr_q = mux(_T_9, _T_10, io.ic_rw_addr) @[el2_ifu_ic_mem.scala 206:25] + node _T_11 = bits(ic_rw_addr_q, 11, 3) @[el2_ifu_ic_mem.scala 208:38] + node _T_12 = add(_T_11, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 208:79] + node ic_rw_addr_q_inc = tail(_T_12, 1) @[el2_ifu_ic_mem.scala 208:79] + io.test <= ic_rw_addr_q_inc @[el2_ifu_ic_mem.scala 209:11] + node _T_13 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 211:78] + node _T_14 = eq(_T_13, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 211:113] + node _T_15 = bits(_T_14, 0, 0) @[Bitwise.scala 72:15] + node _T_16 = mux(_T_15, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_17 = and(ic_debug_wr_way_en, _T_16) @[el2_ifu_ic_mem.scala 211:38] + node ic_b_sb_wren_0 = or(io.ic_wr_en, _T_17) @[el2_ifu_ic_mem.scala 211:17] + node _T_18 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 211:78] + node _T_19 = eq(_T_18, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 211:113] + node _T_20 = bits(_T_19, 0, 0) @[Bitwise.scala 72:15] + node _T_21 = mux(_T_20, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_22 = and(ic_debug_wr_way_en, _T_21) @[el2_ifu_ic_mem.scala 211:38] + node ic_b_sb_wren_1 = or(io.ic_wr_en, _T_22) @[el2_ifu_ic_mem.scala 211:17] + node _T_23 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 212:76] + node _T_24 = eq(_T_23, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 212:111] + node _T_25 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 212:76] + node _T_26 = eq(_T_25, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 212:111] + node ic_debug_sel_sb = cat(_T_26, _T_24) @[Cat.scala 29:58] + node _T_27 = bits(ic_debug_sel_sb, 0, 0) @[el2_ifu_ic_mem.scala 213:77] + node _T_28 = and(_T_27, io.ic_debug_wr_en) @[el2_ifu_ic_mem.scala 213:80] + node _T_29 = bits(_T_28, 0, 0) @[el2_ifu_ic_mem.scala 213:100] + node _T_30 = bits(ic_bank_wr_data, 0, 0) @[el2_ifu_ic_mem.scala 213:144] + node ic_sb_wr_data_0 = mux(_T_29, io.ic_debug_wr_data, _T_30) @[el2_ifu_ic_mem.scala 213:60] + node _T_31 = bits(ic_debug_sel_sb, 1, 1) @[el2_ifu_ic_mem.scala 213:77] + node _T_32 = and(_T_31, io.ic_debug_wr_en) @[el2_ifu_ic_mem.scala 213:80] + node _T_33 = bits(_T_32, 0, 0) @[el2_ifu_ic_mem.scala 213:100] + node _T_34 = bits(ic_bank_wr_data, 1, 1) @[el2_ifu_ic_mem.scala 213:144] + node ic_sb_wr_data_1 = mux(_T_33, io.ic_debug_wr_data, _T_34) @[el2_ifu_ic_mem.scala 213:60] + node _T_35 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 215:29] + node _T_36 = bits(_T_35, 0, 0) @[el2_ifu_ic_mem.scala 215:48] + node _T_37 = eq(_T_36, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 215:16] + node _T_38 = eq(UInt<1>("h00"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 215:63] + node _T_39 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 216:42] + node _T_40 = bits(_T_39, 0, 0) @[el2_ifu_ic_mem.scala 216:62] + node _T_41 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 216:86] + node _T_42 = eq(_T_41, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 216:91] + node _T_43 = eq(UInt<1>("h00"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 216:103] + node _T_44 = and(_T_42, _T_43) @[el2_ifu_ic_mem.scala 216:98] + node _T_45 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 217:42] + node _T_46 = bits(_T_45, 0, 0) @[el2_ifu_ic_mem.scala 217:61] + node _T_47 = eq(UInt<1>("h00"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 217:76] + node _T_48 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 218:43] + node _T_49 = eq(_T_48, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 218:30] + node _T_50 = bits(_T_49, 0, 0) @[el2_ifu_ic_mem.scala 218:63] + node _T_51 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 218:87] + node _T_52 = eq(_T_51, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 218:92] + node _T_53 = eq(UInt<1>("h00"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 218:105] + node _T_54 = and(_T_52, _T_53) @[el2_ifu_ic_mem.scala 218:99] + node _T_55 = mux(_T_37, _T_38, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_56 = mux(_T_40, _T_44, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_57 = mux(_T_46, _T_47, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_58 = mux(_T_50, _T_54, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_59 = or(_T_55, _T_56) @[Mux.scala 27:72] + node _T_60 = or(_T_59, _T_57) @[Mux.scala 27:72] + node _T_61 = or(_T_60, _T_58) @[Mux.scala 27:72] + wire _T_62 : UInt<1> @[Mux.scala 27:72] + _T_62 <= _T_61 @[Mux.scala 27:72] + node _T_63 = and(_T_62, ic_rd_en_with_debug) @[el2_ifu_ic_mem.scala 218:117] + node _T_64 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 215:29] + node _T_65 = bits(_T_64, 0, 0) @[el2_ifu_ic_mem.scala 215:48] + node _T_66 = eq(_T_65, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 215:16] + node _T_67 = eq(UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 215:63] + node _T_68 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 216:42] + node _T_69 = bits(_T_68, 0, 0) @[el2_ifu_ic_mem.scala 216:62] + node _T_70 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 216:86] + node _T_71 = eq(_T_70, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 216:91] + node _T_72 = eq(UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 216:103] + node _T_73 = and(_T_71, _T_72) @[el2_ifu_ic_mem.scala 216:98] + node _T_74 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 217:42] + node _T_75 = bits(_T_74, 0, 0) @[el2_ifu_ic_mem.scala 217:61] + node _T_76 = eq(UInt<1>("h01"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 217:76] + node _T_77 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 218:43] + node _T_78 = eq(_T_77, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 218:30] + node _T_79 = bits(_T_78, 0, 0) @[el2_ifu_ic_mem.scala 218:63] + node _T_80 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 218:87] + node _T_81 = eq(_T_80, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 218:92] + node _T_82 = eq(UInt<1>("h01"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 218:105] + node _T_83 = and(_T_81, _T_82) @[el2_ifu_ic_mem.scala 218:99] + node _T_84 = mux(_T_66, _T_67, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_85 = mux(_T_69, _T_73, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_86 = mux(_T_75, _T_76, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_87 = mux(_T_79, _T_83, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_88 = or(_T_84, _T_85) @[Mux.scala 27:72] + node _T_89 = or(_T_88, _T_86) @[Mux.scala 27:72] + node _T_90 = or(_T_89, _T_87) @[Mux.scala 27:72] + wire _T_91 : UInt<1> @[Mux.scala 27:72] + _T_91 <= _T_90 @[Mux.scala 27:72] + node _T_92 = and(_T_91, ic_rd_en_with_debug) @[el2_ifu_ic_mem.scala 218:117] + node ic_b_rden = cat(_T_92, _T_63) @[Cat.scala 29:58] + node _T_93 = bits(ic_b_rden, 0, 0) @[el2_ifu_ic_mem.scala 219:89] + node _T_94 = bits(_T_93, 0, 0) @[Bitwise.scala 72:15] + node ic_b_sb_rden_0 = mux(_T_94, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_95 = bits(ic_b_rden, 1, 1) @[el2_ifu_ic_mem.scala 219:89] + node _T_96 = bits(_T_95, 0, 0) @[Bitwise.scala 72:15] + node ic_b_sb_rden_1 = mux(_T_96, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_97 = bits(ic_b_sb_rden_0, 0, 0) @[el2_ifu_ic_mem.scala 221:21] + node _T_98 = or(_T_97, io.clk_override) @[el2_ifu_ic_mem.scala 221:25] + node _T_99 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 221:60] + node _T_100 = or(_T_98, _T_99) @[el2_ifu_ic_mem.scala 221:43] + node _T_101 = bits(ic_b_sb_rden_0, 1, 1) @[el2_ifu_ic_mem.scala 221:21] + node _T_102 = or(_T_101, io.clk_override) @[el2_ifu_ic_mem.scala 221:25] + node _T_103 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 221:60] + node _T_104 = or(_T_102, _T_103) @[el2_ifu_ic_mem.scala 221:43] + node ic_bank_way_clken_0 = cat(_T_100, _T_104) @[Cat.scala 29:58] + node _T_105 = bits(ic_b_sb_rden_1, 0, 0) @[el2_ifu_ic_mem.scala 221:21] + node _T_106 = or(_T_105, io.clk_override) @[el2_ifu_ic_mem.scala 221:25] + node _T_107 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 221:60] + node _T_108 = or(_T_106, _T_107) @[el2_ifu_ic_mem.scala 221:43] + node _T_109 = bits(ic_b_sb_rden_1, 1, 1) @[el2_ifu_ic_mem.scala 221:21] + node _T_110 = or(_T_109, io.clk_override) @[el2_ifu_ic_mem.scala 221:25] + node _T_111 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 221:60] + node _T_112 = or(_T_110, _T_111) @[el2_ifu_ic_mem.scala 221:43] + node ic_bank_way_clken_1 = cat(_T_108, _T_112) @[Cat.scala 29:58] + node _T_113 = orr(io.ic_wr_en) @[el2_ifu_ic_mem.scala 223:74] + node _T_114 = eq(_T_113, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 223:61] + node _T_115 = and(io.ic_debug_rd_en, _T_114) @[el2_ifu_ic_mem.scala 223:58] + node _T_116 = or(io.ic_rd_en, _T_115) @[el2_ifu_ic_mem.scala 223:38] + ic_rd_en_with_debug <= _T_116 @[el2_ifu_ic_mem.scala 223:23] + node _T_117 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 225:37] + node _T_118 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 225:71] + node _T_119 = eq(_T_118, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 225:77] + node _T_120 = and(_T_117, _T_119) @[el2_ifu_ic_mem.scala 225:56] + node _T_121 = and(_T_120, ic_rd_en_with_debug) @[el2_ifu_ic_mem.scala 225:86] + node _T_122 = orr(io.ic_wr_en) @[el2_ifu_ic_mem.scala 225:124] + node _T_123 = eq(_T_122, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 225:110] + node ic_rw_addr_wrap = and(_T_121, _T_123) @[el2_ifu_ic_mem.scala 225:108] + node _T_124 = eq(ic_rw_addr_wrap, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 227:40] + node _T_125 = bits(_T_124, 0, 0) @[el2_ifu_ic_mem.scala 227:58] + node _T_126 = bits(ic_rw_addr_q, 11, 3) @[el2_ifu_ic_mem.scala 227:77] + node _T_127 = bits(ic_rw_addr_q, 11, 5) @[el2_ifu_ic_mem.scala 228:21] + node _T_128 = bits(ic_rw_addr_q_inc, 4, 3) @[el2_ifu_ic_mem.scala 228:82] + node _T_129 = cat(_T_127, _T_128) @[Cat.scala 29:58] + node _T_130 = mux(_T_125, _T_126, _T_129) @[el2_ifu_ic_mem.scala 227:38] + node _T_131 = bits(ic_rw_addr_q, 11, 3) @[el2_ifu_ic_mem.scala 229:17] + wire ic_rw_addr_bank_q : UInt<9>[2] @[el2_ifu_ic_mem.scala 227:34] + ic_rw_addr_bank_q[0] <= _T_130 @[el2_ifu_ic_mem.scala 227:34] + ic_rw_addr_bank_q[1] <= _T_131 @[el2_ifu_ic_mem.scala 227:34] + reg ic_b_rden_ff : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 234:29] + ic_b_rden_ff <= ic_b_rden @[el2_ifu_ic_mem.scala 234:29] + node _T_132 = bits(ic_rw_addr_q, 4, 0) @[el2_ifu_ic_mem.scala 235:43] + reg ic_rw_addr_ff : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 235:30] + ic_rw_addr_ff <= _T_132 @[el2_ifu_ic_mem.scala 235:30] + reg ic_debug_rd_way_en_ff : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 236:38] + ic_debug_rd_way_en_ff <= ic_debug_rd_way_en @[el2_ifu_ic_mem.scala 236:38] + reg ic_debug_rd_en_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 237:34] + ic_debug_rd_en_ff <= io.ic_debug_rd_en @[el2_ifu_ic_mem.scala 237:34] + node _T_133 = bits(ic_rw_addr_ff, 4, 2) @[el2_ifu_ic_mem.scala 239:43] + node _T_134 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node ic_cacheline_wrap_ff = eq(_T_133, _T_134) @[el2_ifu_ic_mem.scala 239:84] + io.test <= ic_rw_addr_bank_q[1] @[el2_ifu_ic_mem.scala 241:11] diff --git a/EL2_IC_DATA.v b/EL2_IC_DATA.v index f540b79e..c280a505 100644 --- a/EL2_IC_DATA.v +++ b/EL2_IC_DATA.v @@ -20,10 +20,15 @@ module EL2_IC_DATA( input [63:0] io_ic_premux_data, input io_ic_sel_premux_data, input [1:0] io_ic_rd_hit, - input io_scan_mode + input io_scan_mode, + output [8:0] io_test ); + wire _T_8 = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 206:45] + wire [10:0] _T_10 = {io_ic_debug_addr,2'h0}; // @[Cat.scala 29:58] + wire [11:0] ic_rw_addr_q = _T_8 ? {{1'd0}, _T_10} : io_ic_rw_addr; // @[el2_ifu_ic_mem.scala 206:25] assign io_ic_rd_data = 64'h0; // @[el2_ifu_ic_mem.scala 194:17] assign io_ic_debug_rd_data = 71'h0; // @[el2_ifu_ic_mem.scala 195:23] assign io_ic_parerr = 2'h0; // @[el2_ifu_ic_mem.scala 196:16] assign io_ic_eccerr = 2'h0; // @[el2_ifu_ic_mem.scala 197:16] + assign io_test = ic_rw_addr_q[11:3]; // @[el2_ifu_ic_mem.scala 198:11 el2_ifu_ic_mem.scala 209:11 el2_ifu_ic_mem.scala 241:11] endmodule diff --git a/el2_ifu_ifc_ctrl.fir b/el2_ifu_ifc_ctrl.fir index c7d352a3..a8dd5e9a 100644 --- a/el2_ifu_ifc_ctrl.fir +++ b/el2_ifu_ifc_ctrl.fir @@ -2,7 +2,7 @@ circuit el2_ifu_ifc_ctrl : module el2_ifu_ifc_ctrl : input clock : Clock - input reset : UInt<1> + input reset : AsyncReset output io : {flip active_clk : UInt<1>, flip scan_mode : UInt<1>, flip ic_hit_f : UInt<1>, flip ifu_ic_mb_empty : UInt<1>, flip ifu_fb_consume1 : UInt<1>, flip ifu_fb_consume2 : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<31>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_btb_target_f : UInt<31>, flip ic_dma_active : UInt<1>, flip ic_write_stall : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifc_fetch_addr_f : UInt<31>, ifc_fetch_addr_bf : UInt<31>, ifc_fetch_req_f : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifc_fetch_uncacheable_bf : UInt<1>, ifc_fetch_req_bf : UInt<1>, ifc_fetch_req_bf_raw : UInt<1>, ifc_iccm_access_bf : UInt<1>, ifc_region_acc_fault_bf : UInt<1>, ifc_dma_access_ok : UInt<1>} wire fetch_addr_bf : UInt<32> diff --git a/el2_ifu_ifc_ctrl.v b/el2_ifu_ifc_ctrl.v index baddb80b..36273f6d 100644 --- a/el2_ifu_ifc_ctrl.v +++ b/el2_ifu_ifc_ctrl.v @@ -131,7 +131,6 @@ module el2_ifu_ifc_ctrl( wire _T_72 = _T_64 & leave_idle; // @[el2_ifu_ifc_ctrl.scala 100:34] wire _T_75 = state[0] & _T_64; // @[el2_ifu_ifc_ctrl.scala 100:60] wire next_state_0 = _T_72 | _T_75; // @[el2_ifu_ifc_ctrl.scala 100:48] - wire [1:0] _T_76 = {next_state_1,next_state_0}; // @[Cat.scala 29:58] wire wfm = state == 2'h3; // @[el2_ifu_ifc_ctrl.scala 122:16] reg fb_full_f; // @[el2_ifu_ifc_ctrl.scala 125:26] wire _T_135 = _T_32 | io_exu_flush_final; // @[el2_ifu_ifc_ctrl.scala 129:61] @@ -215,43 +214,76 @@ initial begin _RAND_6 = {1{`RANDOM}}; _T_165 = _RAND_6[30:0]; `endif // RANDOMIZE_REG_INIT + if (reset) begin + dma_iccm_stall_any_f = 1'h0; + end + if (reset) begin + miss_a = 1'h0; + end + if (reset) begin + state = 2'h0; + end + if (reset) begin + fb_write_f = 4'h0; + end + if (reset) begin + fb_full_f = 1'h0; + end + if (reset) begin + _T_163 = 1'h0; + end + if (reset) begin + _T_165 = 31'h0; + end `endif // RANDOMIZE end // initial `ifdef FIRRTL_AFTER_INITIAL `FIRRTL_AFTER_INITIAL `endif `endif // SYNTHESIS - always @(posedge clock) begin + always @(posedge clock or posedge reset) begin if (reset) begin dma_iccm_stall_any_f <= 1'h0; end else begin dma_iccm_stall_any_f <= io_dma_iccm_stall_any; end + end + always @(posedge clock or posedge reset) begin if (reset) begin miss_a <= 1'h0; end else begin - miss_a <= miss_f; + miss_a <= _T_45 & _T_2; end + end + always @(posedge clock or posedge reset) begin if (reset) begin state <= 2'h0; end else begin - state <= _T_76; + state <= {next_state_1,next_state_0}; end + end + always @(posedge clock or posedge reset) begin if (reset) begin fb_write_f <= 4'h0; end else begin - fb_write_f <= fb_write_ns; + fb_write_f <= _T_125 | _T_122; end + end + always @(posedge clock or posedge reset) begin if (reset) begin fb_full_f <= 1'h0; end else begin - fb_full_f <= fb_full_f_ns; + fb_full_f <= fb_write_ns[3]; end + end + always @(posedge clock or posedge reset) begin if (reset) begin _T_163 <= 1'h0; end else begin _T_163 <= io_ifc_fetch_req_bf; end + end + always @(posedge clock or posedge reset) begin if (reset) begin _T_165 <= 31'h0; end else if (fetch_bf_en) begin diff --git a/src/main/scala/ifu/el2_ifu_ic_mem.scala b/src/main/scala/ifu/el2_ifu_ic_mem.scala index 53a69f6e..742b1d1e 100644 --- a/src/main/scala/ifu/el2_ifu_ic_mem.scala +++ b/src/main/scala/ifu/el2_ifu_ic_mem.scala @@ -187,7 +187,7 @@ class EL2_IC_DATA extends Module with el2_lib { val ic_rd_hit = Input(UInt(ICACHE_NUM_WAYS.W)) val scan_mode = Input(UInt(1.W)) - val test = Output(Vec(ICACHE_BANKS_WAY, UInt())) + val test = Output(UInt()) // val test_port = Output(Vec(ICACHE_BANKS_WAY, Vec(ICACHE_NUM_WAYS, UInt(71.W)))) }) @@ -195,28 +195,60 @@ class EL2_IC_DATA extends Module with el2_lib { io.ic_debug_rd_data := 0.U io.ic_parerr := 0.U io.ic_eccerr := 0.U + io.test := 0.U + val ic_debug_rd_way_en = Fill(ICACHE_NUM_WAYS, io.ic_debug_rd_en & !io.ic_debug_tag_array) & io.ic_debug_way val ic_debug_wr_way_en = repl(ICACHE_NUM_WAYS, io.ic_debug_wr_en & !io.ic_debug_tag_array) & io.ic_debug_way - val ic_bank_wr_data = WireInit(UInt(71.W)) - val ic_rw_addr_q = WireInit(UInt(ICACHE_INDEX_HI.W), 0.U) + val ic_bank_wr_data = WireInit(UInt(71.W), 0.U) val ic_rd_en_with_debug = WireInit(Bool(), 0.U) + val ic_rw_addr_q = Mux((io.ic_debug_rd_en | io.ic_debug_wr_en).asBool, Cat(io.ic_debug_addr,0.U(2.W)), io.ic_rw_addr) + + val ic_rw_addr_q_inc = ic_rw_addr_q(ICACHE_TAG_LO-2,ICACHE_DATA_INDEX_LO-1) + 1.U + io.test := ic_rw_addr_q_inc val ic_b_sb_wren = (0 until ICACHE_NUM_WAYS).map(i=> io.ic_wr_en | ic_debug_wr_way_en & Fill(ICACHE_NUM_WAYS, io.ic_debug_addr(ICACHE_BANK_HI-3,ICACHE_BANK_LO-3)===i.U)) - //val ic_debug_sel_sb = (0 until ICACHE_NUM_WAYS).map(i=> (io.ic_debug_addr(ICACHE_BANK_HI-3,ICACHE_BANK_LO-3)===i.U).asBool).reverse.reduce(Cat(_,_)) - //val ic_sb_wr_data = (0 until ICACHE_NUM_WAYS).map(i=> Mux((ic_debug_sel_sb(i)&io.ic_debug_wr_en).asBool, io.ic_debug_wr_data, ic_bank_wr_data(i))) - val ic_b_rden = VecInit.tabulate(ICACHE_BANKS_WAY)(i=> - Mux1H(Seq(!ic_rw_addr_q(ICACHE_BANK_HI-1).asBool -> (i.U === 0.U), + val ic_debug_sel_sb = (0 until ICACHE_NUM_WAYS).map(i=> (io.ic_debug_addr(ICACHE_BANK_HI-3,ICACHE_BANK_LO-3)===i.U).asUInt).reverse.reduce(Cat(_,_)) + val ic_sb_wr_data = (0 until ICACHE_NUM_WAYS).map(i=> Mux((ic_debug_sel_sb(i)&io.ic_debug_wr_en).asBool, io.ic_debug_wr_data, ic_bank_wr_data(i))) + val ic_b_rden = (0 until ICACHE_NUM_WAYS).map(i=> + (Mux1H(Seq(!ic_rw_addr_q(ICACHE_BANK_HI-1).asBool -> (i.U === 0.U), (ic_rw_addr_q(ICACHE_BANK_HI-1)).asBool -> ((ic_rw_addr_q(1,0)===3.U)&(i.U===0.U)), ic_rw_addr_q(ICACHE_BANK_HI-1).asBool -> (i.U === 1.U), - (!ic_rw_addr_q(ICACHE_BANK_HI-1)).asBool -> ((ic_rw_addr_q(1,0)===3.U)&(i.U === 1.U)))) & ic_rd_en_with_debug) - val ic_b_sb_rden = ic_b_rden.map(Fill(ICACHE_NUM_WAYS, _)) -// val ic_bank_way_clken = (0 until ICACHE_BANKS_WAY).map(i=>(0 until ICACHE_NUM_WAYS).map(j=> -// ic_b_sb_rden(i)(j) | io.clk_override | ic_b_sb_wren(i)(j)).reduce(Cat(_,_))) + (!ic_rw_addr_q(ICACHE_BANK_HI-1)).asBool -> ((ic_rw_addr_q(1,0)===3.U)&(i.U === 1.U)))) & ic_rd_en_with_debug).asUInt).reverse.reduce(Cat(_,_)) + val ic_b_sb_rden = (0 until ic_b_rden.getWidth).map(i=>Fill(ICACHE_NUM_WAYS, ic_b_rden(i))) + val ic_bank_way_clken = (0 until ICACHE_BANKS_WAY).map(i=>(0 until ICACHE_NUM_WAYS).map(j=> + (ic_b_sb_rden(i)(j) | io.clk_override | ic_b_sb_wren(i)(j)).asUInt).reduce(Cat(_,_))) + + ic_rd_en_with_debug := io.ic_rd_en | io.ic_debug_rd_en & (!io.ic_wr_en.orR) + + val ic_rw_addr_wrap = ic_rw_addr_q(ICACHE_BANK_HI-1) & (ic_rw_addr_q(1,0) === 3.U) & ic_rd_en_with_debug & !(io.ic_wr_en.orR) + + val ic_rw_addr_bank_q = VecInit(Mux((!ic_rw_addr_wrap).asBool,ic_rw_addr_q(ICACHE_INDEX_HI-1,ICACHE_DATA_INDEX_LO-1), + Cat(ic_rw_addr_q(ICACHE_INDEX_HI-1, ICACHE_TAG_INDEX_LO-1) , ic_rw_addr_q_inc(ICACHE_TAG_INDEX_LO-2,ICACHE_DATA_INDEX_LO-1))), + ic_rw_addr_q(ICACHE_INDEX_HI-1,ICACHE_DATA_INDEX_LO-1) + ) + val ic_b_rden_ff = RegNext(ic_b_rden, 0.U) + val ic_rw_addr_ff = RegNext(ic_rw_addr_q(ICACHE_TAG_INDEX_LO-2,0), 0.U) + val ic_debug_rd_way_en_ff = RegNext(ic_debug_rd_way_en, 0.U) + val ic_debug_rd_en_ff = RegNext(io.ic_debug_rd_en, 0.U) + + val ic_cacheline_wrap_ff = ic_rw_addr_ff(ICACHE_TAG_INDEX_LO-2,ICACHE_BANK_LO-1) === Fill(ICACHE_TAG_INDEX_LO-ICACHE_BANK_LO, 1.U) + + io.test := ic_rw_addr_bank_q(1) + +//////////////////////////////////////////// Memory stated + val (data_mem_word, tag_mem_word, ecc_offset) = DATA_MEM_LINE + +// val data_mem = Mem(ICACHE_DATA_DEPTH, Vec(ICACHE_BANKS_WAY,Vec(ICACHE_NUM_WAYS, UInt(data_mem_word.W)))) +// for(i<-0 until ICACHE_NUM_WAYS; k<-0 until ICACHE_BANKS_WAY){ +// when((ic_b_sb_wren(k)(i)&ic_bank_way_clken(k)(i)).asBool){ +// data_mem() +// } +// } // val ic_bank_way_clken = new Array[UInt](ICACHE_NUM_WAYS) // ic_bank_way_clken(0) = (repl(ICACHE_NUM_WAYS,ic_b_rden(0)) | io.clk_override | ic_b_sb_wren(0)) // for(i<-1 until ICACHE_NUM_WAYS){ diff --git a/src/main/scala/ifu/el2_ifu_ifc_ctrl.scala b/src/main/scala/ifu/el2_ifu_ifc_ctrl.scala index 137ead24..730bdd9d 100644 --- a/src/main/scala/ifu/el2_ifu_ifc_ctrl.scala +++ b/src/main/scala/ifu/el2_ifu_ifc_ctrl.scala @@ -3,7 +3,7 @@ import lib._ import chisel3._ import chisel3.util._ -class el2_ifu_ifc_ctrl extends Module with el2_lib { +class el2_ifu_ifc_ctrl extends Module with el2_lib with RequireAsyncReset { val io = IO(new Bundle{ val active_clk = Input(Bool()) val scan_mode = Input(Bool()) diff --git a/target/scala-2.12/classes/ifu/EL2_IC_DATA$$anon$3.class b/target/scala-2.12/classes/ifu/EL2_IC_DATA$$anon$3.class index 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