From 5510d4f1b96141259623553a755460d6cd00aa3b Mon Sep 17 00:00:00 2001 From: waleed-lm Date: Fri, 11 Dec 2020 17:07:59 +0500 Subject: [PATCH] Quasar top done --- quasar_wrapper.fir | 11792 ++++++++-------- quasar_wrapper.v | 4194 +++--- src/main/scala/ifu/ifu_mem_ctl.scala | 1 - .../scala-2.12/classes/ifu/ifu_mem_ctl.class | Bin 236819 -> 236810 bytes 4 files changed, 7993 insertions(+), 7994 deletions(-) diff --git a/quasar_wrapper.fir b/quasar_wrapper.fir index 13df2aaa..f481c14f 100644 --- a/quasar_wrapper.fir +++ b/quasar_wrapper.fir @@ -6335,50 +6335,50 @@ circuit quasar_wrapper : io.ifu_axi.ar.bits.region <= _T_2614 @[ifu_mem_ctl.scala 502:29] io.ifu_axi.ar.bits.burst <= UInt<1>("h01") @[ifu_mem_ctl.scala 503:28] io.ifu_axi.r.ready <= UInt<1>("h01") @[ifu_mem_ctl.scala 504:22] - reg ifu_bus_arready_unq_ff : UInt<1>, rvclkhdr_68.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 510:57] - ifu_bus_arready_unq_ff <= io.ifu_axi.ar.ready @[ifu_mem_ctl.scala 510:57] - reg ifu_bus_rvalid_unq_ff : UInt<1>, rvclkhdr_68.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 511:56] - ifu_bus_rvalid_unq_ff <= io.ifu_axi.r.valid @[ifu_mem_ctl.scala 511:56] - reg ifu_bus_arvalid_ff : UInt<1>, rvclkhdr_68.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 512:53] - ifu_bus_arvalid_ff <= io.ifu_axi.ar.valid @[ifu_mem_ctl.scala 512:53] - reg ifu_bus_rresp_ff : UInt, rvclkhdr_68.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 513:51] - ifu_bus_rresp_ff <= io.ifu_axi.r.bits.resp @[ifu_mem_ctl.scala 513:51] - reg _T_2615 : UInt, rvclkhdr_68.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 514:48] - _T_2615 <= io.ifu_axi.r.bits.data @[ifu_mem_ctl.scala 514:48] - ifu_bus_rdata_ff <= _T_2615 @[ifu_mem_ctl.scala 514:20] - reg _T_2616 : UInt, rvclkhdr_68.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 515:46] - _T_2616 <= io.ifu_axi.r.bits.id @[ifu_mem_ctl.scala 515:46] - ifu_bus_rid_ff <= _T_2616 @[ifu_mem_ctl.scala 515:18] - ifu_bus_cmd_ready <= io.ifu_axi.ar.ready @[ifu_mem_ctl.scala 516:21] - ifu_bus_rsp_valid <= io.ifu_axi.r.valid @[ifu_mem_ctl.scala 517:21] - ifu_bus_rsp_ready <= io.ifu_axi.r.ready @[ifu_mem_ctl.scala 518:21] - ifu_bus_rsp_tag <= io.ifu_axi.r.bits.id @[ifu_mem_ctl.scala 519:19] - ic_miss_buff_data_in <= io.ifu_axi.r.bits.data @[ifu_mem_ctl.scala 520:21] - node ifu_bus_rvalid = and(ifu_bus_rsp_valid, bus_ifu_bus_clk_en) @[ifu_mem_ctl.scala 522:42] - node ifu_bus_arready = and(io.ifu_axi.ar.ready, bus_ifu_bus_clk_en) @[ifu_mem_ctl.scala 523:45] - node ifu_bus_arready_ff = and(ifu_bus_arready_unq_ff, bus_ifu_bus_clk_en_ff) @[ifu_mem_ctl.scala 524:51] - node ifu_bus_rvalid_ff = and(ifu_bus_rvalid_unq_ff, bus_ifu_bus_clk_en_ff) @[ifu_mem_ctl.scala 525:49] - node _T_2617 = and(io.ifu_axi.ar.valid, ifu_bus_arready) @[ifu_mem_ctl.scala 527:35] - node _T_2618 = and(_T_2617, miss_pending) @[ifu_mem_ctl.scala 527:53] - node _T_2619 = eq(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<1>("h00")) @[ifu_mem_ctl.scala 527:70] - node _T_2620 = and(_T_2618, _T_2619) @[ifu_mem_ctl.scala 527:68] - bus_cmd_sent <= _T_2620 @[ifu_mem_ctl.scala 527:16] + reg ifu_bus_arready_unq_ff : UInt<1>, rvclkhdr_68.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 509:57] + ifu_bus_arready_unq_ff <= io.ifu_axi.ar.ready @[ifu_mem_ctl.scala 509:57] + reg ifu_bus_rvalid_unq_ff : UInt<1>, rvclkhdr_68.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 510:56] + ifu_bus_rvalid_unq_ff <= io.ifu_axi.r.valid @[ifu_mem_ctl.scala 510:56] + reg ifu_bus_arvalid_ff : UInt<1>, rvclkhdr_68.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 511:53] + ifu_bus_arvalid_ff <= io.ifu_axi.ar.valid @[ifu_mem_ctl.scala 511:53] + reg ifu_bus_rresp_ff : UInt, rvclkhdr_68.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 512:51] + ifu_bus_rresp_ff <= io.ifu_axi.r.bits.resp @[ifu_mem_ctl.scala 512:51] + reg _T_2615 : UInt, rvclkhdr_68.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 513:48] + _T_2615 <= io.ifu_axi.r.bits.data @[ifu_mem_ctl.scala 513:48] + ifu_bus_rdata_ff <= _T_2615 @[ifu_mem_ctl.scala 513:20] + reg _T_2616 : UInt, rvclkhdr_68.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 514:46] + _T_2616 <= io.ifu_axi.r.bits.id @[ifu_mem_ctl.scala 514:46] + ifu_bus_rid_ff <= _T_2616 @[ifu_mem_ctl.scala 514:18] + ifu_bus_cmd_ready <= io.ifu_axi.ar.ready @[ifu_mem_ctl.scala 515:21] + ifu_bus_rsp_valid <= io.ifu_axi.r.valid @[ifu_mem_ctl.scala 516:21] + ifu_bus_rsp_ready <= io.ifu_axi.r.ready @[ifu_mem_ctl.scala 517:21] + ifu_bus_rsp_tag <= io.ifu_axi.r.bits.id @[ifu_mem_ctl.scala 518:19] + ic_miss_buff_data_in <= io.ifu_axi.r.bits.data @[ifu_mem_ctl.scala 519:21] + node ifu_bus_rvalid = and(ifu_bus_rsp_valid, bus_ifu_bus_clk_en) @[ifu_mem_ctl.scala 521:42] + node ifu_bus_arready = and(io.ifu_axi.ar.ready, bus_ifu_bus_clk_en) @[ifu_mem_ctl.scala 522:45] + node ifu_bus_arready_ff = and(ifu_bus_arready_unq_ff, bus_ifu_bus_clk_en_ff) @[ifu_mem_ctl.scala 523:51] + node ifu_bus_rvalid_ff = and(ifu_bus_rvalid_unq_ff, bus_ifu_bus_clk_en_ff) @[ifu_mem_ctl.scala 524:49] + node _T_2617 = and(io.ifu_axi.ar.valid, ifu_bus_arready) @[ifu_mem_ctl.scala 526:35] + node _T_2618 = and(_T_2617, miss_pending) @[ifu_mem_ctl.scala 526:53] + node _T_2619 = eq(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<1>("h00")) @[ifu_mem_ctl.scala 526:70] + node _T_2620 = and(_T_2618, _T_2619) @[ifu_mem_ctl.scala 526:68] + bus_cmd_sent <= _T_2620 @[ifu_mem_ctl.scala 526:16] wire bus_last_data_beat : UInt<1> bus_last_data_beat <= UInt<1>("h00") - node _T_2621 = eq(bus_last_data_beat, UInt<1>("h00")) @[ifu_mem_ctl.scala 529:50] - node _T_2622 = and(bus_ifu_wr_en_ff, _T_2621) @[ifu_mem_ctl.scala 529:48] - node _T_2623 = eq(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<1>("h00")) @[ifu_mem_ctl.scala 529:72] - node bus_inc_data_beat_cnt = and(_T_2622, _T_2623) @[ifu_mem_ctl.scala 529:70] - node _T_2624 = and(bus_ifu_wr_en_ff, bus_last_data_beat) @[ifu_mem_ctl.scala 530:68] - node _T_2625 = or(ic_act_miss_f, _T_2624) @[ifu_mem_ctl.scala 530:48] - node bus_reset_data_beat_cnt = or(_T_2625, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 530:91] - node _T_2626 = eq(bus_inc_data_beat_cnt, UInt<1>("h00")) @[ifu_mem_ctl.scala 531:32] - node _T_2627 = eq(bus_reset_data_beat_cnt, UInt<1>("h00")) @[ifu_mem_ctl.scala 531:57] - node bus_hold_data_beat_cnt = and(_T_2626, _T_2627) @[ifu_mem_ctl.scala 531:55] + node _T_2621 = eq(bus_last_data_beat, UInt<1>("h00")) @[ifu_mem_ctl.scala 528:50] + node _T_2622 = and(bus_ifu_wr_en_ff, _T_2621) @[ifu_mem_ctl.scala 528:48] + node _T_2623 = eq(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<1>("h00")) @[ifu_mem_ctl.scala 528:72] + node bus_inc_data_beat_cnt = and(_T_2622, _T_2623) @[ifu_mem_ctl.scala 528:70] + node _T_2624 = and(bus_ifu_wr_en_ff, bus_last_data_beat) @[ifu_mem_ctl.scala 529:68] + node _T_2625 = or(ic_act_miss_f, _T_2624) @[ifu_mem_ctl.scala 529:48] + node bus_reset_data_beat_cnt = or(_T_2625, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 529:91] + node _T_2626 = eq(bus_inc_data_beat_cnt, UInt<1>("h00")) @[ifu_mem_ctl.scala 530:32] + node _T_2627 = eq(bus_reset_data_beat_cnt, UInt<1>("h00")) @[ifu_mem_ctl.scala 530:57] + node bus_hold_data_beat_cnt = and(_T_2626, _T_2627) @[ifu_mem_ctl.scala 530:55] wire bus_data_beat_count : UInt<3> bus_data_beat_count <= UInt<1>("h00") - node _T_2628 = add(bus_data_beat_count, UInt<1>("h01")) @[ifu_mem_ctl.scala 533:115] - node _T_2629 = tail(_T_2628, 1) @[ifu_mem_ctl.scala 533:115] + node _T_2628 = add(bus_data_beat_count, UInt<1>("h01")) @[ifu_mem_ctl.scala 532:115] + node _T_2629 = tail(_T_2628, 1) @[ifu_mem_ctl.scala 532:115] node _T_2630 = mux(bus_reset_data_beat_cnt, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_2631 = mux(bus_inc_data_beat_cnt, _T_2629, UInt<1>("h00")) @[Mux.scala 27:72] node _T_2632 = mux(bus_hold_data_beat_cnt, bus_data_beat_count, UInt<1>("h00")) @[Mux.scala 27:72] @@ -6386,48 +6386,48 @@ circuit quasar_wrapper : node _T_2634 = or(_T_2633, _T_2632) @[Mux.scala 27:72] wire _T_2635 : UInt<3> @[Mux.scala 27:72] _T_2635 <= _T_2634 @[Mux.scala 27:72] - bus_new_data_beat_count <= _T_2635 @[ifu_mem_ctl.scala 533:27] - reg _T_2636 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 534:56] - _T_2636 <= bus_new_data_beat_count @[ifu_mem_ctl.scala 534:56] - bus_data_beat_count <= _T_2636 @[ifu_mem_ctl.scala 534:23] - node _T_2637 = and(bus_ifu_wr_en_ff, bus_last_data_beat) @[ifu_mem_ctl.scala 535:49] - node _T_2638 = eq(scnd_miss_req, UInt<1>("h00")) @[ifu_mem_ctl.scala 535:73] - node _T_2639 = and(_T_2637, _T_2638) @[ifu_mem_ctl.scala 535:71] - node _T_2640 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 535:116] - node _T_2641 = and(last_data_recieved_ff, _T_2640) @[ifu_mem_ctl.scala 535:114] - node last_data_recieved_in = or(_T_2639, _T_2641) @[ifu_mem_ctl.scala 535:89] - reg _T_2642 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 536:58] - _T_2642 <= last_data_recieved_in @[ifu_mem_ctl.scala 536:58] - last_data_recieved_ff <= _T_2642 @[ifu_mem_ctl.scala 536:25] - node _T_2643 = eq(miss_pending, UInt<1>("h00")) @[ifu_mem_ctl.scala 538:35] - node _T_2644 = bits(imb_ff, 4, 2) @[ifu_mem_ctl.scala 538:56] - node _T_2645 = bits(imb_scnd_ff, 4, 2) @[ifu_mem_ctl.scala 539:39] - node _T_2646 = add(bus_rd_addr_count, UInt<1>("h01")) @[ifu_mem_ctl.scala 540:45] - node _T_2647 = tail(_T_2646, 1) @[ifu_mem_ctl.scala 540:45] - node _T_2648 = mux(bus_cmd_sent, _T_2647, bus_rd_addr_count) @[ifu_mem_ctl.scala 540:12] - node _T_2649 = mux(scnd_miss_req_q, _T_2645, _T_2648) @[ifu_mem_ctl.scala 539:10] - node bus_new_rd_addr_count = mux(_T_2643, _T_2644, _T_2649) @[ifu_mem_ctl.scala 538:34] - reg _T_2650 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 541:55] - _T_2650 <= bus_new_rd_addr_count @[ifu_mem_ctl.scala 541:55] - bus_rd_addr_count <= _T_2650 @[ifu_mem_ctl.scala 541:21] - node _T_2651 = and(ifu_bus_cmd_valid, ifu_bus_cmd_ready) @[ifu_mem_ctl.scala 543:48] - node _T_2652 = and(_T_2651, miss_pending) @[ifu_mem_ctl.scala 543:68] - node _T_2653 = eq(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<1>("h00")) @[ifu_mem_ctl.scala 543:85] - node bus_inc_cmd_beat_cnt = and(_T_2652, _T_2653) @[ifu_mem_ctl.scala 543:83] - node _T_2654 = eq(uncacheable_miss_in, UInt<1>("h00")) @[ifu_mem_ctl.scala 544:51] - node _T_2655 = and(ic_act_miss_f, _T_2654) @[ifu_mem_ctl.scala 544:49] - node bus_reset_cmd_beat_cnt_0 = or(_T_2655, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 544:73] - node bus_reset_cmd_beat_cnt_secondlast = and(ic_act_miss_f, uncacheable_miss_in) @[ifu_mem_ctl.scala 545:57] - node _T_2656 = eq(bus_inc_cmd_beat_cnt, UInt<1>("h00")) @[ifu_mem_ctl.scala 546:31] - node _T_2657 = or(ic_act_miss_f, scnd_miss_req) @[ifu_mem_ctl.scala 546:71] - node _T_2658 = or(_T_2657, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 546:87] - node _T_2659 = eq(_T_2658, UInt<1>("h00")) @[ifu_mem_ctl.scala 546:55] - node bus_hold_cmd_beat_cnt = and(_T_2656, _T_2659) @[ifu_mem_ctl.scala 546:53] - node _T_2660 = or(bus_inc_cmd_beat_cnt, ic_act_miss_f) @[ifu_mem_ctl.scala 547:46] - node bus_cmd_beat_en = or(_T_2660, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 547:62] - node _T_2661 = bits(bus_reset_cmd_beat_cnt_secondlast, 0, 0) @[ifu_mem_ctl.scala 548:107] - node _T_2662 = add(bus_cmd_beat_count, UInt<1>("h01")) @[ifu_mem_ctl.scala 549:46] - node _T_2663 = tail(_T_2662, 1) @[ifu_mem_ctl.scala 549:46] + bus_new_data_beat_count <= _T_2635 @[ifu_mem_ctl.scala 532:27] + reg _T_2636 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 533:56] + _T_2636 <= bus_new_data_beat_count @[ifu_mem_ctl.scala 533:56] + bus_data_beat_count <= _T_2636 @[ifu_mem_ctl.scala 533:23] + node _T_2637 = and(bus_ifu_wr_en_ff, bus_last_data_beat) @[ifu_mem_ctl.scala 534:49] + node _T_2638 = eq(scnd_miss_req, UInt<1>("h00")) @[ifu_mem_ctl.scala 534:73] + node _T_2639 = and(_T_2637, _T_2638) @[ifu_mem_ctl.scala 534:71] + node _T_2640 = eq(ic_act_miss_f, UInt<1>("h00")) @[ifu_mem_ctl.scala 534:116] + node _T_2641 = and(last_data_recieved_ff, _T_2640) @[ifu_mem_ctl.scala 534:114] + node last_data_recieved_in = or(_T_2639, _T_2641) @[ifu_mem_ctl.scala 534:89] + reg _T_2642 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 535:58] + _T_2642 <= last_data_recieved_in @[ifu_mem_ctl.scala 535:58] + last_data_recieved_ff <= _T_2642 @[ifu_mem_ctl.scala 535:25] + node _T_2643 = eq(miss_pending, UInt<1>("h00")) @[ifu_mem_ctl.scala 537:35] + node _T_2644 = bits(imb_ff, 4, 2) @[ifu_mem_ctl.scala 537:56] + node _T_2645 = bits(imb_scnd_ff, 4, 2) @[ifu_mem_ctl.scala 538:39] + node _T_2646 = add(bus_rd_addr_count, UInt<1>("h01")) @[ifu_mem_ctl.scala 539:45] + node _T_2647 = tail(_T_2646, 1) @[ifu_mem_ctl.scala 539:45] + node _T_2648 = mux(bus_cmd_sent, _T_2647, bus_rd_addr_count) @[ifu_mem_ctl.scala 539:12] + node _T_2649 = mux(scnd_miss_req_q, _T_2645, _T_2648) @[ifu_mem_ctl.scala 538:10] + node bus_new_rd_addr_count = mux(_T_2643, _T_2644, _T_2649) @[ifu_mem_ctl.scala 537:34] + reg _T_2650 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 540:55] + _T_2650 <= bus_new_rd_addr_count @[ifu_mem_ctl.scala 540:55] + bus_rd_addr_count <= _T_2650 @[ifu_mem_ctl.scala 540:21] + node _T_2651 = and(ifu_bus_cmd_valid, ifu_bus_cmd_ready) @[ifu_mem_ctl.scala 542:48] + node _T_2652 = and(_T_2651, miss_pending) @[ifu_mem_ctl.scala 542:68] + node _T_2653 = eq(io.dec_mem_ctrl.dec_tlu_force_halt, UInt<1>("h00")) @[ifu_mem_ctl.scala 542:85] + node bus_inc_cmd_beat_cnt = and(_T_2652, _T_2653) @[ifu_mem_ctl.scala 542:83] + node _T_2654 = eq(uncacheable_miss_in, UInt<1>("h00")) @[ifu_mem_ctl.scala 543:51] + node _T_2655 = and(ic_act_miss_f, _T_2654) @[ifu_mem_ctl.scala 543:49] + node bus_reset_cmd_beat_cnt_0 = or(_T_2655, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 543:73] + node bus_reset_cmd_beat_cnt_secondlast = and(ic_act_miss_f, uncacheable_miss_in) @[ifu_mem_ctl.scala 544:57] + node _T_2656 = eq(bus_inc_cmd_beat_cnt, UInt<1>("h00")) @[ifu_mem_ctl.scala 545:31] + node _T_2657 = or(ic_act_miss_f, scnd_miss_req) @[ifu_mem_ctl.scala 545:71] + node _T_2658 = or(_T_2657, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 545:87] + node _T_2659 = eq(_T_2658, UInt<1>("h00")) @[ifu_mem_ctl.scala 545:55] + node bus_hold_cmd_beat_cnt = and(_T_2656, _T_2659) @[ifu_mem_ctl.scala 545:53] + node _T_2660 = or(bus_inc_cmd_beat_cnt, ic_act_miss_f) @[ifu_mem_ctl.scala 546:46] + node bus_cmd_beat_en = or(_T_2660, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 546:62] + node _T_2661 = bits(bus_reset_cmd_beat_cnt_secondlast, 0, 0) @[ifu_mem_ctl.scala 547:107] + node _T_2662 = add(bus_cmd_beat_count, UInt<1>("h01")) @[ifu_mem_ctl.scala 548:46] + node _T_2663 = tail(_T_2662, 1) @[ifu_mem_ctl.scala 548:46] node _T_2664 = mux(bus_reset_cmd_beat_cnt_0, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_2665 = mux(_T_2661, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_2666 = mux(bus_inc_cmd_beat_cnt, _T_2663, UInt<1>("h00")) @[Mux.scala 27:72] @@ -6441,84 +6441,84 @@ circuit quasar_wrapper : when bus_cmd_beat_en : @[Reg.scala 28:19] _T_2671 <= bus_new_cmd_beat_count @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bus_cmd_beat_count <= _T_2671 @[ifu_mem_ctl.scala 550:22] - node _T_2672 = eq(bus_data_beat_count, UInt<1>("h01")) @[ifu_mem_ctl.scala 551:69] - node _T_2673 = andr(bus_data_beat_count) @[ifu_mem_ctl.scala 551:101] - node _T_2674 = mux(uncacheable_miss_ff, _T_2672, _T_2673) @[ifu_mem_ctl.scala 551:28] - bus_last_data_beat <= _T_2674 @[ifu_mem_ctl.scala 551:22] - node _T_2675 = and(ifu_bus_rvalid, miss_pending) @[ifu_mem_ctl.scala 552:35] - bus_ifu_wr_en <= _T_2675 @[ifu_mem_ctl.scala 552:17] - node _T_2676 = and(ifu_bus_rvalid_ff, miss_pending) @[ifu_mem_ctl.scala 553:41] - bus_ifu_wr_en_ff <= _T_2676 @[ifu_mem_ctl.scala 553:20] - node _T_2677 = and(ifu_bus_rvalid_ff, miss_pending) @[ifu_mem_ctl.scala 554:44] - node _T_2678 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 554:61] - node _T_2679 = and(_T_2677, _T_2678) @[ifu_mem_ctl.scala 554:59] - node _T_2680 = orr(ifu_bus_rresp_ff) @[ifu_mem_ctl.scala 554:103] - node _T_2681 = eq(_T_2680, UInt<1>("h00")) @[ifu_mem_ctl.scala 554:84] - node _T_2682 = and(_T_2679, _T_2681) @[ifu_mem_ctl.scala 554:82] - node _T_2683 = and(_T_2682, write_ic_16_bytes) @[ifu_mem_ctl.scala 554:108] - bus_ifu_wr_en_ff_q <= _T_2683 @[ifu_mem_ctl.scala 554:22] - node _T_2684 = and(ifu_bus_rvalid_ff, miss_pending) @[ifu_mem_ctl.scala 555:51] - node _T_2685 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 555:68] - node bus_ifu_wr_en_ff_wo_err = and(_T_2684, _T_2685) @[ifu_mem_ctl.scala 555:66] - reg ic_act_miss_f_delayed : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 556:61] - ic_act_miss_f_delayed <= ic_act_miss_f @[ifu_mem_ctl.scala 556:61] - node _T_2686 = eq(miss_state, UInt<3>("h01")) @[ifu_mem_ctl.scala 557:66] - node _T_2687 = and(ic_act_miss_f_delayed, _T_2686) @[ifu_mem_ctl.scala 557:53] - node _T_2688 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 557:86] - node _T_2689 = and(_T_2687, _T_2688) @[ifu_mem_ctl.scala 557:84] - reset_tag_valid_for_miss <= _T_2689 @[ifu_mem_ctl.scala 557:28] - node _T_2690 = orr(io.ifu_axi.r.bits.resp) @[ifu_mem_ctl.scala 558:47] - node _T_2691 = and(_T_2690, ifu_bus_rvalid) @[ifu_mem_ctl.scala 558:50] - node _T_2692 = and(_T_2691, miss_pending) @[ifu_mem_ctl.scala 558:68] - bus_ifu_wr_data_error <= _T_2692 @[ifu_mem_ctl.scala 558:25] - node _T_2693 = orr(ifu_bus_rresp_ff) @[ifu_mem_ctl.scala 559:48] - node _T_2694 = and(_T_2693, ifu_bus_rvalid_ff) @[ifu_mem_ctl.scala 559:52] - node _T_2695 = and(_T_2694, miss_pending) @[ifu_mem_ctl.scala 559:73] - bus_ifu_wr_data_error_ff <= _T_2695 @[ifu_mem_ctl.scala 559:28] + bus_cmd_beat_count <= _T_2671 @[ifu_mem_ctl.scala 549:22] + node _T_2672 = eq(bus_data_beat_count, UInt<1>("h01")) @[ifu_mem_ctl.scala 550:69] + node _T_2673 = andr(bus_data_beat_count) @[ifu_mem_ctl.scala 550:101] + node _T_2674 = mux(uncacheable_miss_ff, _T_2672, _T_2673) @[ifu_mem_ctl.scala 550:28] + bus_last_data_beat <= _T_2674 @[ifu_mem_ctl.scala 550:22] + node _T_2675 = and(ifu_bus_rvalid, miss_pending) @[ifu_mem_ctl.scala 551:35] + bus_ifu_wr_en <= _T_2675 @[ifu_mem_ctl.scala 551:17] + node _T_2676 = and(ifu_bus_rvalid_ff, miss_pending) @[ifu_mem_ctl.scala 552:41] + bus_ifu_wr_en_ff <= _T_2676 @[ifu_mem_ctl.scala 552:20] + node _T_2677 = and(ifu_bus_rvalid_ff, miss_pending) @[ifu_mem_ctl.scala 553:44] + node _T_2678 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 553:61] + node _T_2679 = and(_T_2677, _T_2678) @[ifu_mem_ctl.scala 553:59] + node _T_2680 = orr(ifu_bus_rresp_ff) @[ifu_mem_ctl.scala 553:103] + node _T_2681 = eq(_T_2680, UInt<1>("h00")) @[ifu_mem_ctl.scala 553:84] + node _T_2682 = and(_T_2679, _T_2681) @[ifu_mem_ctl.scala 553:82] + node _T_2683 = and(_T_2682, write_ic_16_bytes) @[ifu_mem_ctl.scala 553:108] + bus_ifu_wr_en_ff_q <= _T_2683 @[ifu_mem_ctl.scala 553:22] + node _T_2684 = and(ifu_bus_rvalid_ff, miss_pending) @[ifu_mem_ctl.scala 554:51] + node _T_2685 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 554:68] + node bus_ifu_wr_en_ff_wo_err = and(_T_2684, _T_2685) @[ifu_mem_ctl.scala 554:66] + reg ic_act_miss_f_delayed : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 555:61] + ic_act_miss_f_delayed <= ic_act_miss_f @[ifu_mem_ctl.scala 555:61] + node _T_2686 = eq(miss_state, UInt<3>("h01")) @[ifu_mem_ctl.scala 556:66] + node _T_2687 = and(ic_act_miss_f_delayed, _T_2686) @[ifu_mem_ctl.scala 556:53] + node _T_2688 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 556:86] + node _T_2689 = and(_T_2687, _T_2688) @[ifu_mem_ctl.scala 556:84] + reset_tag_valid_for_miss <= _T_2689 @[ifu_mem_ctl.scala 556:28] + node _T_2690 = orr(io.ifu_axi.r.bits.resp) @[ifu_mem_ctl.scala 557:47] + node _T_2691 = and(_T_2690, ifu_bus_rvalid) @[ifu_mem_ctl.scala 557:50] + node _T_2692 = and(_T_2691, miss_pending) @[ifu_mem_ctl.scala 557:68] + bus_ifu_wr_data_error <= _T_2692 @[ifu_mem_ctl.scala 557:25] + node _T_2693 = orr(ifu_bus_rresp_ff) @[ifu_mem_ctl.scala 558:48] + node _T_2694 = and(_T_2693, ifu_bus_rvalid_ff) @[ifu_mem_ctl.scala 558:52] + node _T_2695 = and(_T_2694, miss_pending) @[ifu_mem_ctl.scala 558:73] + bus_ifu_wr_data_error_ff <= _T_2695 @[ifu_mem_ctl.scala 558:28] wire ifc_dma_access_ok_d : UInt<1> ifc_dma_access_ok_d <= UInt<1>("h00") - reg ifc_dma_access_ok_prev : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 561:62] - ifc_dma_access_ok_prev <= ifc_dma_access_ok_d @[ifu_mem_ctl.scala 561:62] - node _T_2696 = or(ic_crit_wd_rdy_new_in, ic_crit_wd_rdy_new_ff) @[ifu_mem_ctl.scala 562:43] - ic_crit_wd_rdy <= _T_2696 @[ifu_mem_ctl.scala 562:18] - node _T_2697 = and(bus_last_data_beat, bus_ifu_wr_en_ff) @[ifu_mem_ctl.scala 563:35] - last_beat <= _T_2697 @[ifu_mem_ctl.scala 563:13] - reset_beat_cnt <= bus_reset_data_beat_cnt @[ifu_mem_ctl.scala 564:18] - node _T_2698 = eq(iccm_correct_ecc, UInt<1>("h00")) @[ifu_mem_ctl.scala 566:50] - node _T_2699 = and(io.ifc_dma_access_ok, _T_2698) @[ifu_mem_ctl.scala 566:47] - node _T_2700 = eq(io.iccm_dma_sb_error, UInt<1>("h00")) @[ifu_mem_ctl.scala 566:70] - node _T_2701 = and(_T_2699, _T_2700) @[ifu_mem_ctl.scala 566:68] - ifc_dma_access_ok_d <= _T_2701 @[ifu_mem_ctl.scala 566:23] - node _T_2702 = eq(iccm_correct_ecc, UInt<1>("h00")) @[ifu_mem_ctl.scala 567:54] - node _T_2703 = and(io.ifc_dma_access_ok, _T_2702) @[ifu_mem_ctl.scala 567:51] - node _T_2704 = and(_T_2703, ifc_dma_access_ok_prev) @[ifu_mem_ctl.scala 567:72] - node _T_2705 = eq(perr_state, UInt<3>("h00")) @[ifu_mem_ctl.scala 567:111] - node _T_2706 = and(_T_2704, _T_2705) @[ifu_mem_ctl.scala 567:97] - node _T_2707 = eq(io.iccm_dma_sb_error, UInt<1>("h00")) @[ifu_mem_ctl.scala 567:129] - node ifc_dma_access_q_ok = and(_T_2706, _T_2707) @[ifu_mem_ctl.scala 567:127] - io.iccm_ready <= ifc_dma_access_q_ok @[ifu_mem_ctl.scala 568:17] - reg _T_2708 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 569:51] - _T_2708 <= io.dma_mem_ctl.dma_iccm_req @[ifu_mem_ctl.scala 569:51] - dma_iccm_req_f <= _T_2708 @[ifu_mem_ctl.scala 569:18] - node _T_2709 = and(ifc_dma_access_q_ok, io.dma_mem_ctl.dma_iccm_req) @[ifu_mem_ctl.scala 570:40] - node _T_2710 = and(_T_2709, io.dma_mem_ctl.dma_mem_write) @[ifu_mem_ctl.scala 570:70] - node _T_2711 = or(_T_2710, iccm_correct_ecc) @[ifu_mem_ctl.scala 570:103] - io.iccm.wren <= _T_2711 @[ifu_mem_ctl.scala 570:16] - node _T_2712 = and(ifc_dma_access_q_ok, io.dma_mem_ctl.dma_iccm_req) @[ifu_mem_ctl.scala 571:40] - node _T_2713 = eq(io.dma_mem_ctl.dma_mem_write, UInt<1>("h00")) @[ifu_mem_ctl.scala 571:72] - node _T_2714 = and(_T_2712, _T_2713) @[ifu_mem_ctl.scala 571:70] - node _T_2715 = and(io.ifc_iccm_access_bf, io.ifc_fetch_req_bf) @[ifu_mem_ctl.scala 571:128] - node _T_2716 = or(_T_2714, _T_2715) @[ifu_mem_ctl.scala 571:103] - io.iccm.rden <= _T_2716 @[ifu_mem_ctl.scala 571:16] - node _T_2717 = and(ifc_dma_access_q_ok, io.dma_mem_ctl.dma_iccm_req) @[ifu_mem_ctl.scala 572:43] - node _T_2718 = eq(io.dma_mem_ctl.dma_mem_write, UInt<1>("h00")) @[ifu_mem_ctl.scala 572:75] - node iccm_dma_rden = and(_T_2717, _T_2718) @[ifu_mem_ctl.scala 572:73] + reg ifc_dma_access_ok_prev : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 560:62] + ifc_dma_access_ok_prev <= ifc_dma_access_ok_d @[ifu_mem_ctl.scala 560:62] + node _T_2696 = or(ic_crit_wd_rdy_new_in, ic_crit_wd_rdy_new_ff) @[ifu_mem_ctl.scala 561:43] + ic_crit_wd_rdy <= _T_2696 @[ifu_mem_ctl.scala 561:18] + node _T_2697 = and(bus_last_data_beat, bus_ifu_wr_en_ff) @[ifu_mem_ctl.scala 562:35] + last_beat <= _T_2697 @[ifu_mem_ctl.scala 562:13] + reset_beat_cnt <= bus_reset_data_beat_cnt @[ifu_mem_ctl.scala 563:18] + node _T_2698 = eq(iccm_correct_ecc, UInt<1>("h00")) @[ifu_mem_ctl.scala 565:50] + node _T_2699 = and(io.ifc_dma_access_ok, _T_2698) @[ifu_mem_ctl.scala 565:47] + node _T_2700 = eq(io.iccm_dma_sb_error, UInt<1>("h00")) @[ifu_mem_ctl.scala 565:70] + node _T_2701 = and(_T_2699, _T_2700) @[ifu_mem_ctl.scala 565:68] + ifc_dma_access_ok_d <= _T_2701 @[ifu_mem_ctl.scala 565:23] + node _T_2702 = eq(iccm_correct_ecc, UInt<1>("h00")) @[ifu_mem_ctl.scala 566:54] + node _T_2703 = and(io.ifc_dma_access_ok, _T_2702) @[ifu_mem_ctl.scala 566:51] + node _T_2704 = and(_T_2703, ifc_dma_access_ok_prev) @[ifu_mem_ctl.scala 566:72] + node _T_2705 = eq(perr_state, UInt<3>("h00")) @[ifu_mem_ctl.scala 566:111] + node _T_2706 = and(_T_2704, _T_2705) @[ifu_mem_ctl.scala 566:97] + node _T_2707 = eq(io.iccm_dma_sb_error, UInt<1>("h00")) @[ifu_mem_ctl.scala 566:129] + node ifc_dma_access_q_ok = and(_T_2706, _T_2707) @[ifu_mem_ctl.scala 566:127] + io.iccm_ready <= ifc_dma_access_q_ok @[ifu_mem_ctl.scala 567:17] + reg _T_2708 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 568:51] + _T_2708 <= io.dma_mem_ctl.dma_iccm_req @[ifu_mem_ctl.scala 568:51] + dma_iccm_req_f <= _T_2708 @[ifu_mem_ctl.scala 568:18] + node _T_2709 = and(ifc_dma_access_q_ok, io.dma_mem_ctl.dma_iccm_req) @[ifu_mem_ctl.scala 569:40] + node _T_2710 = and(_T_2709, io.dma_mem_ctl.dma_mem_write) @[ifu_mem_ctl.scala 569:70] + node _T_2711 = or(_T_2710, iccm_correct_ecc) @[ifu_mem_ctl.scala 569:103] + io.iccm.wren <= _T_2711 @[ifu_mem_ctl.scala 569:16] + node _T_2712 = and(ifc_dma_access_q_ok, io.dma_mem_ctl.dma_iccm_req) @[ifu_mem_ctl.scala 570:40] + node _T_2713 = eq(io.dma_mem_ctl.dma_mem_write, UInt<1>("h00")) @[ifu_mem_ctl.scala 570:72] + node _T_2714 = and(_T_2712, _T_2713) @[ifu_mem_ctl.scala 570:70] + node _T_2715 = and(io.ifc_iccm_access_bf, io.ifc_fetch_req_bf) @[ifu_mem_ctl.scala 570:128] + node _T_2716 = or(_T_2714, _T_2715) @[ifu_mem_ctl.scala 570:103] + io.iccm.rden <= _T_2716 @[ifu_mem_ctl.scala 570:16] + node _T_2717 = and(ifc_dma_access_q_ok, io.dma_mem_ctl.dma_iccm_req) @[ifu_mem_ctl.scala 571:43] + node _T_2718 = eq(io.dma_mem_ctl.dma_mem_write, UInt<1>("h00")) @[ifu_mem_ctl.scala 571:75] + node iccm_dma_rden = and(_T_2717, _T_2718) @[ifu_mem_ctl.scala 571:73] node _T_2719 = bits(io.dma_mem_ctl.dma_iccm_req, 0, 0) @[Bitwise.scala 72:15] node _T_2720 = mux(_T_2719, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_2721 = and(_T_2720, io.dma_mem_ctl.dma_mem_sz) @[ifu_mem_ctl.scala 573:59] - io.iccm.wr_size <= _T_2721 @[ifu_mem_ctl.scala 573:19] - node _T_2722 = bits(io.dma_mem_ctl.dma_mem_wdata, 63, 32) @[ifu_mem_ctl.scala 575:66] + node _T_2721 = and(_T_2720, io.dma_mem_ctl.dma_mem_sz) @[ifu_mem_ctl.scala 572:59] + io.iccm.wr_size <= _T_2721 @[ifu_mem_ctl.scala 572:19] + node _T_2722 = bits(io.dma_mem_ctl.dma_mem_wdata, 63, 32) @[ifu_mem_ctl.scala 574:66] node _T_2723 = bits(_T_2722, 0, 0) @[lib.scala 119:58] node _T_2724 = bits(_T_2722, 1, 1) @[lib.scala 119:58] node _T_2725 = bits(_T_2722, 3, 3) @[lib.scala 119:58] @@ -6702,7 +6702,7 @@ circuit quasar_wrapper : node _T_2903 = xorr(_T_2901) @[lib.scala 127:23] node _T_2904 = xor(_T_2902, _T_2903) @[lib.scala 127:18] node _T_2905 = cat(_T_2904, _T_2901) @[Cat.scala 29:58] - node _T_2906 = bits(io.dma_mem_ctl.dma_mem_wdata, 31, 0) @[ifu_mem_ctl.scala 575:117] + node _T_2906 = bits(io.dma_mem_ctl.dma_mem_wdata, 31, 0) @[ifu_mem_ctl.scala 574:117] node _T_2907 = bits(_T_2906, 0, 0) @[lib.scala 119:58] node _T_2908 = bits(_T_2906, 1, 1) @[lib.scala 119:58] node _T_2909 = bits(_T_2906, 3, 3) @[lib.scala 119:58] @@ -6889,90 +6889,90 @@ circuit quasar_wrapper : node dma_mem_ecc = cat(_T_2905, _T_3089) @[Cat.scala 29:58] wire iccm_ecc_corr_data_ff : UInt<39> iccm_ecc_corr_data_ff <= UInt<1>("h00") - node _T_3090 = and(ifc_dma_access_q_ok, io.dma_mem_ctl.dma_iccm_req) @[ifu_mem_ctl.scala 577:67] - node _T_3091 = eq(_T_3090, UInt<1>("h00")) @[ifu_mem_ctl.scala 577:45] - node _T_3092 = and(iccm_correct_ecc, _T_3091) @[ifu_mem_ctl.scala 577:43] + node _T_3090 = and(ifc_dma_access_q_ok, io.dma_mem_ctl.dma_iccm_req) @[ifu_mem_ctl.scala 576:67] + node _T_3091 = eq(_T_3090, UInt<1>("h00")) @[ifu_mem_ctl.scala 576:45] + node _T_3092 = and(iccm_correct_ecc, _T_3091) @[ifu_mem_ctl.scala 576:43] node _T_3093 = cat(iccm_ecc_corr_data_ff, iccm_ecc_corr_data_ff) @[Cat.scala 29:58] - node _T_3094 = bits(dma_mem_ecc, 13, 7) @[ifu_mem_ctl.scala 578:20] - node _T_3095 = bits(io.dma_mem_ctl.dma_mem_wdata, 63, 32) @[ifu_mem_ctl.scala 578:55] - node _T_3096 = bits(dma_mem_ecc, 6, 0) @[ifu_mem_ctl.scala 578:75] - node _T_3097 = bits(io.dma_mem_ctl.dma_mem_wdata, 31, 0) @[ifu_mem_ctl.scala 578:110] + node _T_3094 = bits(dma_mem_ecc, 13, 7) @[ifu_mem_ctl.scala 577:20] + node _T_3095 = bits(io.dma_mem_ctl.dma_mem_wdata, 63, 32) @[ifu_mem_ctl.scala 577:55] + node _T_3096 = bits(dma_mem_ecc, 6, 0) @[ifu_mem_ctl.scala 577:75] + node _T_3097 = bits(io.dma_mem_ctl.dma_mem_wdata, 31, 0) @[ifu_mem_ctl.scala 577:110] node _T_3098 = cat(_T_3096, _T_3097) @[Cat.scala 29:58] node _T_3099 = cat(_T_3094, _T_3095) @[Cat.scala 29:58] node _T_3100 = cat(_T_3099, _T_3098) @[Cat.scala 29:58] - node _T_3101 = mux(_T_3092, _T_3093, _T_3100) @[ifu_mem_ctl.scala 577:25] - io.iccm.wr_data <= _T_3101 @[ifu_mem_ctl.scala 577:19] - wire iccm_corrected_data : UInt<32>[2] @[ifu_mem_ctl.scala 579:33] - iccm_corrected_data[0] <= UInt<1>("h00") @[ifu_mem_ctl.scala 580:26] - iccm_corrected_data[1] <= UInt<1>("h00") @[ifu_mem_ctl.scala 581:26] + node _T_3101 = mux(_T_3092, _T_3093, _T_3100) @[ifu_mem_ctl.scala 576:25] + io.iccm.wr_data <= _T_3101 @[ifu_mem_ctl.scala 576:19] + wire iccm_corrected_data : UInt<32>[2] @[ifu_mem_ctl.scala 578:33] + iccm_corrected_data[0] <= UInt<1>("h00") @[ifu_mem_ctl.scala 579:26] + iccm_corrected_data[1] <= UInt<1>("h00") @[ifu_mem_ctl.scala 580:26] wire dma_mem_addr_ff : UInt<2> dma_mem_addr_ff <= UInt<1>("h00") - node _T_3102 = bits(dma_mem_addr_ff, 0, 0) @[ifu_mem_ctl.scala 583:51] - node _T_3103 = bits(_T_3102, 0, 0) @[ifu_mem_ctl.scala 583:55] - node iccm_dma_rdata_1_muxed = mux(_T_3103, iccm_corrected_data[0], iccm_corrected_data[1]) @[ifu_mem_ctl.scala 583:35] + node _T_3102 = bits(dma_mem_addr_ff, 0, 0) @[ifu_mem_ctl.scala 582:51] + node _T_3103 = bits(_T_3102, 0, 0) @[ifu_mem_ctl.scala 582:55] + node iccm_dma_rdata_1_muxed = mux(_T_3103, iccm_corrected_data[0], iccm_corrected_data[1]) @[ifu_mem_ctl.scala 582:35] wire iccm_double_ecc_error : UInt<2> iccm_double_ecc_error <= UInt<1>("h00") - node iccm_dma_ecc_error_in = orr(iccm_double_ecc_error) @[ifu_mem_ctl.scala 585:53] + node iccm_dma_ecc_error_in = orr(iccm_double_ecc_error) @[ifu_mem_ctl.scala 584:53] node _T_3104 = cat(io.dma_mem_ctl.dma_mem_addr, io.dma_mem_ctl.dma_mem_addr) @[Cat.scala 29:58] node _T_3105 = cat(iccm_dma_rdata_1_muxed, iccm_corrected_data[0]) @[Cat.scala 29:58] - node iccm_dma_rdata_in = mux(iccm_dma_ecc_error_in, _T_3104, _T_3105) @[ifu_mem_ctl.scala 586:30] - reg dma_mem_tag_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 587:54] - dma_mem_tag_ff <= io.dma_mem_ctl.dma_mem_tag @[ifu_mem_ctl.scala 587:54] - reg iccm_dma_rtag_temp : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 588:74] - iccm_dma_rtag_temp <= dma_mem_tag_ff @[ifu_mem_ctl.scala 588:74] - io.iccm_dma_rtag <= iccm_dma_rtag_temp @[ifu_mem_ctl.scala 589:20] - node _T_3106 = bits(io.dma_mem_ctl.dma_mem_addr, 3, 2) @[ifu_mem_ctl.scala 591:81] - reg _T_3107 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 591:53] - _T_3107 <= _T_3106 @[ifu_mem_ctl.scala 591:53] - dma_mem_addr_ff <= _T_3107 @[ifu_mem_ctl.scala 591:19] - reg iccm_dma_rvalid_in : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 592:59] - iccm_dma_rvalid_in <= iccm_dma_rden @[ifu_mem_ctl.scala 592:59] - reg iccm_dma_rvalid_temp : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 593:76] - iccm_dma_rvalid_temp <= iccm_dma_rvalid_in @[ifu_mem_ctl.scala 593:76] - io.iccm_dma_rvalid <= iccm_dma_rvalid_temp @[ifu_mem_ctl.scala 594:22] - reg iccm_dma_ecc_error : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 595:74] - iccm_dma_ecc_error <= iccm_dma_ecc_error_in @[ifu_mem_ctl.scala 595:74] - io.iccm_dma_ecc_error <= iccm_dma_ecc_error @[ifu_mem_ctl.scala 596:25] - reg iccm_dma_rdata_temp : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 597:75] - iccm_dma_rdata_temp <= iccm_dma_rdata_in @[ifu_mem_ctl.scala 597:75] - io.iccm_dma_rdata <= iccm_dma_rdata_temp @[ifu_mem_ctl.scala 598:21] + node iccm_dma_rdata_in = mux(iccm_dma_ecc_error_in, _T_3104, _T_3105) @[ifu_mem_ctl.scala 585:30] + reg dma_mem_tag_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 586:54] + dma_mem_tag_ff <= io.dma_mem_ctl.dma_mem_tag @[ifu_mem_ctl.scala 586:54] + reg iccm_dma_rtag_temp : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 587:74] + iccm_dma_rtag_temp <= dma_mem_tag_ff @[ifu_mem_ctl.scala 587:74] + io.iccm_dma_rtag <= iccm_dma_rtag_temp @[ifu_mem_ctl.scala 588:20] + node _T_3106 = bits(io.dma_mem_ctl.dma_mem_addr, 3, 2) @[ifu_mem_ctl.scala 590:81] + reg _T_3107 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 590:53] + _T_3107 <= _T_3106 @[ifu_mem_ctl.scala 590:53] + dma_mem_addr_ff <= _T_3107 @[ifu_mem_ctl.scala 590:19] + reg iccm_dma_rvalid_in : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 591:59] + iccm_dma_rvalid_in <= iccm_dma_rden @[ifu_mem_ctl.scala 591:59] + reg iccm_dma_rvalid_temp : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 592:76] + iccm_dma_rvalid_temp <= iccm_dma_rvalid_in @[ifu_mem_ctl.scala 592:76] + io.iccm_dma_rvalid <= iccm_dma_rvalid_temp @[ifu_mem_ctl.scala 593:22] + reg iccm_dma_ecc_error : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 594:74] + iccm_dma_ecc_error <= iccm_dma_ecc_error_in @[ifu_mem_ctl.scala 594:74] + io.iccm_dma_ecc_error <= iccm_dma_ecc_error @[ifu_mem_ctl.scala 595:25] + reg iccm_dma_rdata_temp : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 596:75] + iccm_dma_rdata_temp <= iccm_dma_rdata_in @[ifu_mem_ctl.scala 596:75] + io.iccm_dma_rdata <= iccm_dma_rdata_temp @[ifu_mem_ctl.scala 597:21] wire iccm_ecc_corr_index_ff : UInt<14> iccm_ecc_corr_index_ff <= UInt<1>("h00") - node _T_3108 = and(ifc_dma_access_q_ok, io.dma_mem_ctl.dma_iccm_req) @[ifu_mem_ctl.scala 600:46] - node _T_3109 = eq(iccm_correct_ecc, UInt<1>("h00")) @[ifu_mem_ctl.scala 600:79] - node _T_3110 = and(_T_3108, _T_3109) @[ifu_mem_ctl.scala 600:77] - node _T_3111 = bits(io.dma_mem_ctl.dma_mem_addr, 15, 1) @[ifu_mem_ctl.scala 600:125] - node _T_3112 = and(ifc_dma_access_q_ok, io.dma_mem_ctl.dma_iccm_req) @[ifu_mem_ctl.scala 601:31] - node _T_3113 = eq(_T_3112, UInt<1>("h00")) @[ifu_mem_ctl.scala 601:9] - node _T_3114 = and(_T_3113, iccm_correct_ecc) @[ifu_mem_ctl.scala 601:62] + node _T_3108 = and(ifc_dma_access_q_ok, io.dma_mem_ctl.dma_iccm_req) @[ifu_mem_ctl.scala 599:46] + node _T_3109 = eq(iccm_correct_ecc, UInt<1>("h00")) @[ifu_mem_ctl.scala 599:79] + node _T_3110 = and(_T_3108, _T_3109) @[ifu_mem_ctl.scala 599:77] + node _T_3111 = bits(io.dma_mem_ctl.dma_mem_addr, 15, 1) @[ifu_mem_ctl.scala 599:125] + node _T_3112 = and(ifc_dma_access_q_ok, io.dma_mem_ctl.dma_iccm_req) @[ifu_mem_ctl.scala 600:31] + node _T_3113 = eq(_T_3112, UInt<1>("h00")) @[ifu_mem_ctl.scala 600:9] + node _T_3114 = and(_T_3113, iccm_correct_ecc) @[ifu_mem_ctl.scala 600:62] node _T_3115 = cat(iccm_ecc_corr_index_ff, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_3116 = bits(io.ifc_fetch_addr_bf, 14, 0) @[ifu_mem_ctl.scala 601:136] - node _T_3117 = mux(_T_3114, _T_3115, _T_3116) @[ifu_mem_ctl.scala 601:8] - node _T_3118 = mux(_T_3110, _T_3111, _T_3117) @[ifu_mem_ctl.scala 600:25] - io.iccm.rw_addr <= _T_3118 @[ifu_mem_ctl.scala 600:19] + node _T_3116 = bits(io.ifc_fetch_addr_bf, 14, 0) @[ifu_mem_ctl.scala 600:136] + node _T_3117 = mux(_T_3114, _T_3115, _T_3116) @[ifu_mem_ctl.scala 600:8] + node _T_3118 = mux(_T_3110, _T_3111, _T_3117) @[ifu_mem_ctl.scala 599:25] + io.iccm.rw_addr <= _T_3118 @[ifu_mem_ctl.scala 599:19] node ic_fetch_val_int_f = cat(UInt<2>("h00"), io.ic_fetch_val_f) @[Cat.scala 29:58] - node _T_3119 = bits(ifu_fetch_addr_int_f, 0, 0) @[ifu_mem_ctl.scala 603:76] - node ic_fetch_val_shift_right = dshl(ic_fetch_val_int_f, _T_3119) @[ifu_mem_ctl.scala 603:53] - node _T_3120 = bits(ic_fetch_val_shift_right, 1, 0) @[ifu_mem_ctl.scala 606:75] - node _T_3121 = orr(_T_3120) @[ifu_mem_ctl.scala 606:91] - node _T_3122 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 606:97] - node _T_3123 = and(_T_3121, _T_3122) @[ifu_mem_ctl.scala 606:95] - node _T_3124 = and(_T_3123, fetch_req_iccm_f) @[ifu_mem_ctl.scala 606:117] - node _T_3125 = or(_T_3124, iccm_dma_rvalid_in) @[ifu_mem_ctl.scala 606:134] - node _T_3126 = eq(io.dec_mem_ctrl.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[ifu_mem_ctl.scala 606:158] - node _T_3127 = and(_T_3125, _T_3126) @[ifu_mem_ctl.scala 606:156] - node _T_3128 = bits(ic_fetch_val_shift_right, 3, 2) @[ifu_mem_ctl.scala 606:75] - node _T_3129 = orr(_T_3128) @[ifu_mem_ctl.scala 606:91] - node _T_3130 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 606:97] - node _T_3131 = and(_T_3129, _T_3130) @[ifu_mem_ctl.scala 606:95] - node _T_3132 = and(_T_3131, fetch_req_iccm_f) @[ifu_mem_ctl.scala 606:117] - node _T_3133 = or(_T_3132, iccm_dma_rvalid_in) @[ifu_mem_ctl.scala 606:134] - node _T_3134 = eq(io.dec_mem_ctrl.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[ifu_mem_ctl.scala 606:158] - node _T_3135 = and(_T_3133, _T_3134) @[ifu_mem_ctl.scala 606:156] + node _T_3119 = bits(ifu_fetch_addr_int_f, 0, 0) @[ifu_mem_ctl.scala 602:76] + node ic_fetch_val_shift_right = dshl(ic_fetch_val_int_f, _T_3119) @[ifu_mem_ctl.scala 602:53] + node _T_3120 = bits(ic_fetch_val_shift_right, 1, 0) @[ifu_mem_ctl.scala 605:75] + node _T_3121 = orr(_T_3120) @[ifu_mem_ctl.scala 605:91] + node _T_3122 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 605:97] + node _T_3123 = and(_T_3121, _T_3122) @[ifu_mem_ctl.scala 605:95] + node _T_3124 = and(_T_3123, fetch_req_iccm_f) @[ifu_mem_ctl.scala 605:117] + node _T_3125 = or(_T_3124, iccm_dma_rvalid_in) @[ifu_mem_ctl.scala 605:134] + node _T_3126 = eq(io.dec_mem_ctrl.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[ifu_mem_ctl.scala 605:158] + node _T_3127 = and(_T_3125, _T_3126) @[ifu_mem_ctl.scala 605:156] + node _T_3128 = bits(ic_fetch_val_shift_right, 3, 2) @[ifu_mem_ctl.scala 605:75] + node _T_3129 = orr(_T_3128) @[ifu_mem_ctl.scala 605:91] + node _T_3130 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 605:97] + node _T_3131 = and(_T_3129, _T_3130) @[ifu_mem_ctl.scala 605:95] + node _T_3132 = and(_T_3131, fetch_req_iccm_f) @[ifu_mem_ctl.scala 605:117] + node _T_3133 = or(_T_3132, iccm_dma_rvalid_in) @[ifu_mem_ctl.scala 605:134] + node _T_3134 = eq(io.dec_mem_ctrl.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[ifu_mem_ctl.scala 605:158] + node _T_3135 = and(_T_3133, _T_3134) @[ifu_mem_ctl.scala 605:156] node iccm_ecc_word_enable = cat(_T_3135, _T_3127) @[Cat.scala 29:58] - node _T_3136 = bits(iccm_ecc_word_enable, 0, 0) @[ifu_mem_ctl.scala 607:73] - node _T_3137 = bits(io.iccm.rd_data_ecc, 31, 0) @[ifu_mem_ctl.scala 607:93] - node _T_3138 = bits(io.iccm.rd_data_ecc, 38, 32) @[ifu_mem_ctl.scala 607:128] + node _T_3136 = bits(iccm_ecc_word_enable, 0, 0) @[ifu_mem_ctl.scala 606:73] + node _T_3137 = bits(io.iccm.rd_data_ecc, 31, 0) @[ifu_mem_ctl.scala 606:93] + node _T_3138 = bits(io.iccm.rd_data_ecc, 38, 32) @[ifu_mem_ctl.scala 606:128] wire _T_3139 : UInt<1>[18] @[lib.scala 173:18] wire _T_3140 : UInt<1>[18] @[lib.scala 174:18] wire _T_3141 : UInt<1>[18] @[lib.scala 175:18] @@ -7484,9 +7484,9 @@ circuit quasar_wrapper : node _T_3518 = cat(_T_3510, _T_3511) @[Cat.scala 29:58] node _T_3519 = cat(_T_3518, _T_3512) @[Cat.scala 29:58] node _T_3520 = cat(_T_3519, _T_3517) @[Cat.scala 29:58] - node _T_3521 = bits(iccm_ecc_word_enable, 1, 1) @[ifu_mem_ctl.scala 607:73] - node _T_3522 = bits(io.iccm.rd_data_ecc, 70, 39) @[ifu_mem_ctl.scala 607:93] - node _T_3523 = bits(io.iccm.rd_data_ecc, 77, 71) @[ifu_mem_ctl.scala 607:128] + node _T_3521 = bits(iccm_ecc_word_enable, 1, 1) @[ifu_mem_ctl.scala 606:73] + node _T_3522 = bits(io.iccm.rd_data_ecc, 70, 39) @[ifu_mem_ctl.scala 606:93] + node _T_3523 = bits(io.iccm.rd_data_ecc, 77, 71) @[ifu_mem_ctl.scala 606:128] wire _T_3524 : UInt<1>[18] @[lib.scala 173:18] wire _T_3525 : UInt<1>[18] @[lib.scala 174:18] wire _T_3526 : UInt<1>[18] @[lib.scala 175:18] @@ -7998,191 +7998,191 @@ circuit quasar_wrapper : node _T_3903 = cat(_T_3895, _T_3896) @[Cat.scala 29:58] node _T_3904 = cat(_T_3903, _T_3897) @[Cat.scala 29:58] node _T_3905 = cat(_T_3904, _T_3902) @[Cat.scala 29:58] - wire iccm_corrected_ecc : UInt<7>[2] @[ifu_mem_ctl.scala 608:32] - wire _T_3906 : UInt<7>[2] @[ifu_mem_ctl.scala 609:32] - _T_3906[0] <= _T_3520 @[ifu_mem_ctl.scala 609:32] - _T_3906[1] <= _T_3905 @[ifu_mem_ctl.scala 609:32] - iccm_corrected_ecc[0] <= _T_3906[0] @[ifu_mem_ctl.scala 609:22] - iccm_corrected_ecc[1] <= _T_3906[1] @[ifu_mem_ctl.scala 609:22] - wire _T_3907 : UInt<32>[2] @[ifu_mem_ctl.scala 610:33] - _T_3907[0] <= _T_3506 @[ifu_mem_ctl.scala 610:33] - _T_3907[1] <= _T_3891 @[ifu_mem_ctl.scala 610:33] - iccm_corrected_data[0] <= _T_3907[0] @[ifu_mem_ctl.scala 610:23] - iccm_corrected_data[1] <= _T_3907[1] @[ifu_mem_ctl.scala 610:23] + wire iccm_corrected_ecc : UInt<7>[2] @[ifu_mem_ctl.scala 607:32] + wire _T_3906 : UInt<7>[2] @[ifu_mem_ctl.scala 608:32] + _T_3906[0] <= _T_3520 @[ifu_mem_ctl.scala 608:32] + _T_3906[1] <= _T_3905 @[ifu_mem_ctl.scala 608:32] + iccm_corrected_ecc[0] <= _T_3906[0] @[ifu_mem_ctl.scala 608:22] + iccm_corrected_ecc[1] <= _T_3906[1] @[ifu_mem_ctl.scala 608:22] + wire _T_3907 : UInt<32>[2] @[ifu_mem_ctl.scala 609:33] + _T_3907[0] <= _T_3506 @[ifu_mem_ctl.scala 609:33] + _T_3907[1] <= _T_3891 @[ifu_mem_ctl.scala 609:33] + iccm_corrected_data[0] <= _T_3907[0] @[ifu_mem_ctl.scala 609:23] + iccm_corrected_data[1] <= _T_3907[1] @[ifu_mem_ctl.scala 609:23] node _T_3908 = cat(_T_3736, _T_3351) @[Cat.scala 29:58] - iccm_single_ecc_error <= _T_3908 @[ifu_mem_ctl.scala 611:25] + iccm_single_ecc_error <= _T_3908 @[ifu_mem_ctl.scala 610:25] node _T_3909 = cat(_T_3741, _T_3356) @[Cat.scala 29:58] - iccm_double_ecc_error <= _T_3909 @[ifu_mem_ctl.scala 612:25] - node _T_3910 = orr(iccm_single_ecc_error) @[ifu_mem_ctl.scala 613:71] - node _T_3911 = and(_T_3910, ifc_iccm_access_f) @[ifu_mem_ctl.scala 613:75] - node _T_3912 = and(_T_3911, ifc_fetch_req_f) @[ifu_mem_ctl.scala 613:95] - io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err <= _T_3912 @[ifu_mem_ctl.scala 613:46] - node _T_3913 = orr(iccm_double_ecc_error) @[ifu_mem_ctl.scala 614:54] - node _T_3914 = and(_T_3913, ifc_iccm_access_f) @[ifu_mem_ctl.scala 614:58] - io.iccm_rd_ecc_double_err <= _T_3914 @[ifu_mem_ctl.scala 614:29] - node _T_3915 = bits(iccm_single_ecc_error, 0, 0) @[ifu_mem_ctl.scala 615:60] - node _T_3916 = bits(_T_3915, 0, 0) @[ifu_mem_ctl.scala 615:64] - node iccm_corrected_data_f_mux = mux(_T_3916, iccm_corrected_data[0], iccm_corrected_data[1]) @[ifu_mem_ctl.scala 615:38] - node _T_3917 = bits(iccm_single_ecc_error, 0, 0) @[ifu_mem_ctl.scala 616:59] - node _T_3918 = bits(_T_3917, 0, 0) @[ifu_mem_ctl.scala 616:63] - node iccm_corrected_ecc_f_mux = mux(_T_3918, iccm_corrected_ecc[0], iccm_corrected_ecc[1]) @[ifu_mem_ctl.scala 616:37] + iccm_double_ecc_error <= _T_3909 @[ifu_mem_ctl.scala 611:25] + node _T_3910 = orr(iccm_single_ecc_error) @[ifu_mem_ctl.scala 612:71] + node _T_3911 = and(_T_3910, ifc_iccm_access_f) @[ifu_mem_ctl.scala 612:75] + node _T_3912 = and(_T_3911, ifc_fetch_req_f) @[ifu_mem_ctl.scala 612:95] + io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err <= _T_3912 @[ifu_mem_ctl.scala 612:46] + node _T_3913 = orr(iccm_double_ecc_error) @[ifu_mem_ctl.scala 613:54] + node _T_3914 = and(_T_3913, ifc_iccm_access_f) @[ifu_mem_ctl.scala 613:58] + io.iccm_rd_ecc_double_err <= _T_3914 @[ifu_mem_ctl.scala 613:29] + node _T_3915 = bits(iccm_single_ecc_error, 0, 0) @[ifu_mem_ctl.scala 614:60] + node _T_3916 = bits(_T_3915, 0, 0) @[ifu_mem_ctl.scala 614:64] + node iccm_corrected_data_f_mux = mux(_T_3916, iccm_corrected_data[0], iccm_corrected_data[1]) @[ifu_mem_ctl.scala 614:38] + node _T_3917 = bits(iccm_single_ecc_error, 0, 0) @[ifu_mem_ctl.scala 615:59] + node _T_3918 = bits(_T_3917, 0, 0) @[ifu_mem_ctl.scala 615:63] + node iccm_corrected_ecc_f_mux = mux(_T_3918, iccm_corrected_ecc[0], iccm_corrected_ecc[1]) @[ifu_mem_ctl.scala 615:37] wire iccm_rd_ecc_single_err_ff : UInt<1> iccm_rd_ecc_single_err_ff <= UInt<1>("h00") - node _T_3919 = eq(iccm_rd_ecc_single_err_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 618:93] - node _T_3920 = and(io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err, _T_3919) @[ifu_mem_ctl.scala 618:91] - node _T_3921 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 618:123] - node _T_3922 = and(_T_3920, _T_3921) @[ifu_mem_ctl.scala 618:121] - node iccm_ecc_write_status = or(_T_3922, io.iccm_dma_sb_error) @[ifu_mem_ctl.scala 618:144] - node _T_3923 = or(io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err, iccm_rd_ecc_single_err_ff) @[ifu_mem_ctl.scala 619:84] - node _T_3924 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 619:115] - node iccm_rd_ecc_single_err_hold_in = and(_T_3923, _T_3924) @[ifu_mem_ctl.scala 619:113] - iccm_error_start <= io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err @[ifu_mem_ctl.scala 620:20] + node _T_3919 = eq(iccm_rd_ecc_single_err_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 617:93] + node _T_3920 = and(io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err, _T_3919) @[ifu_mem_ctl.scala 617:91] + node _T_3921 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 617:123] + node _T_3922 = and(_T_3920, _T_3921) @[ifu_mem_ctl.scala 617:121] + node iccm_ecc_write_status = or(_T_3922, io.iccm_dma_sb_error) @[ifu_mem_ctl.scala 617:144] + node _T_3923 = or(io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err, iccm_rd_ecc_single_err_ff) @[ifu_mem_ctl.scala 618:84] + node _T_3924 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 618:115] + node iccm_rd_ecc_single_err_hold_in = and(_T_3923, _T_3924) @[ifu_mem_ctl.scala 618:113] + iccm_error_start <= io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err @[ifu_mem_ctl.scala 619:20] wire iccm_rw_addr_f : UInt<14> iccm_rw_addr_f <= UInt<1>("h00") - node _T_3925 = bits(iccm_single_ecc_error, 0, 0) @[ifu_mem_ctl.scala 622:57] - node _T_3926 = bits(_T_3925, 0, 0) @[ifu_mem_ctl.scala 622:67] - node _T_3927 = add(iccm_rw_addr_f, UInt<1>("h01")) @[ifu_mem_ctl.scala 622:102] - node _T_3928 = tail(_T_3927, 1) @[ifu_mem_ctl.scala 622:102] - node iccm_ecc_corr_index_in = mux(_T_3926, iccm_rw_addr_f, _T_3928) @[ifu_mem_ctl.scala 622:35] - node _T_3929 = bits(io.iccm.rw_addr, 14, 1) @[ifu_mem_ctl.scala 623:67] - reg _T_3930 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 623:51] - _T_3930 <= _T_3929 @[ifu_mem_ctl.scala 623:51] - iccm_rw_addr_f <= _T_3930 @[ifu_mem_ctl.scala 623:18] - reg _T_3931 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 624:62] - _T_3931 <= iccm_rd_ecc_single_err_hold_in @[ifu_mem_ctl.scala 624:62] - iccm_rd_ecc_single_err_ff <= _T_3931 @[ifu_mem_ctl.scala 624:29] + node _T_3925 = bits(iccm_single_ecc_error, 0, 0) @[ifu_mem_ctl.scala 621:57] + node _T_3926 = bits(_T_3925, 0, 0) @[ifu_mem_ctl.scala 621:67] + node _T_3927 = add(iccm_rw_addr_f, UInt<1>("h01")) @[ifu_mem_ctl.scala 621:102] + node _T_3928 = tail(_T_3927, 1) @[ifu_mem_ctl.scala 621:102] + node iccm_ecc_corr_index_in = mux(_T_3926, iccm_rw_addr_f, _T_3928) @[ifu_mem_ctl.scala 621:35] + node _T_3929 = bits(io.iccm.rw_addr, 14, 1) @[ifu_mem_ctl.scala 622:67] + reg _T_3930 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 622:51] + _T_3930 <= _T_3929 @[ifu_mem_ctl.scala 622:51] + iccm_rw_addr_f <= _T_3930 @[ifu_mem_ctl.scala 622:18] + reg _T_3931 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 623:62] + _T_3931 <= iccm_rd_ecc_single_err_hold_in @[ifu_mem_ctl.scala 623:62] + iccm_rd_ecc_single_err_ff <= _T_3931 @[ifu_mem_ctl.scala 623:29] node _T_3932 = cat(iccm_corrected_ecc_f_mux, iccm_corrected_data_f_mux) @[Cat.scala 29:58] - node _T_3933 = bits(iccm_ecc_write_status, 0, 0) @[ifu_mem_ctl.scala 625:152] + node _T_3933 = bits(iccm_ecc_write_status, 0, 0) @[ifu_mem_ctl.scala 624:152] reg _T_3934 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3933 : @[Reg.scala 28:19] _T_3934 <= _T_3932 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - iccm_ecc_corr_data_ff <= _T_3934 @[ifu_mem_ctl.scala 625:25] - node _T_3935 = bits(iccm_ecc_write_status, 0, 0) @[ifu_mem_ctl.scala 626:119] + iccm_ecc_corr_data_ff <= _T_3934 @[ifu_mem_ctl.scala 624:25] + node _T_3935 = bits(iccm_ecc_write_status, 0, 0) @[ifu_mem_ctl.scala 625:119] reg _T_3936 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3935 : @[Reg.scala 28:19] _T_3936 <= iccm_ecc_corr_index_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - iccm_ecc_corr_index_ff <= _T_3936 @[ifu_mem_ctl.scala 626:26] - node _T_3937 = eq(io.ifc_fetch_uncacheable_bf, UInt<1>("h00")) @[ifu_mem_ctl.scala 627:41] - node _T_3938 = and(io.ifc_fetch_req_bf, _T_3937) @[ifu_mem_ctl.scala 627:39] - node _T_3939 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[ifu_mem_ctl.scala 627:72] - node _T_3940 = and(_T_3938, _T_3939) @[ifu_mem_ctl.scala 627:70] - node _T_3941 = eq(miss_state, UInt<3>("h06")) @[ifu_mem_ctl.scala 628:19] - node _T_3942 = eq(miss_state_en, UInt<1>("h00")) @[ifu_mem_ctl.scala 628:34] - node _T_3943 = and(_T_3941, _T_3942) @[ifu_mem_ctl.scala 628:32] - node _T_3944 = eq(miss_state, UInt<3>("h01")) @[ifu_mem_ctl.scala 629:19] - node _T_3945 = eq(miss_state_en, UInt<1>("h00")) @[ifu_mem_ctl.scala 629:39] - node _T_3946 = and(_T_3944, _T_3945) @[ifu_mem_ctl.scala 629:37] - node _T_3947 = or(_T_3943, _T_3946) @[ifu_mem_ctl.scala 628:88] - node _T_3948 = eq(miss_state, UInt<3>("h07")) @[ifu_mem_ctl.scala 630:19] - node _T_3949 = eq(miss_state_en, UInt<1>("h00")) @[ifu_mem_ctl.scala 630:43] - node _T_3950 = and(_T_3948, _T_3949) @[ifu_mem_ctl.scala 630:41] - node _T_3951 = or(_T_3947, _T_3950) @[ifu_mem_ctl.scala 629:88] - node _T_3952 = eq(miss_state, UInt<3>("h03")) @[ifu_mem_ctl.scala 631:19] - node _T_3953 = eq(miss_state_en, UInt<1>("h00")) @[ifu_mem_ctl.scala 631:37] - node _T_3954 = and(_T_3952, _T_3953) @[ifu_mem_ctl.scala 631:35] - node _T_3955 = or(_T_3951, _T_3954) @[ifu_mem_ctl.scala 630:88] - node _T_3956 = eq(miss_state, UInt<3>("h04")) @[ifu_mem_ctl.scala 632:19] - node _T_3957 = eq(miss_state_en, UInt<1>("h00")) @[ifu_mem_ctl.scala 632:40] - node _T_3958 = and(_T_3956, _T_3957) @[ifu_mem_ctl.scala 632:38] - node _T_3959 = or(_T_3955, _T_3958) @[ifu_mem_ctl.scala 631:88] - node _T_3960 = eq(miss_state, UInt<3>("h01")) @[ifu_mem_ctl.scala 633:19] - node _T_3961 = and(_T_3960, miss_state_en) @[ifu_mem_ctl.scala 633:37] - node _T_3962 = eq(miss_nxtstate, UInt<3>("h03")) @[ifu_mem_ctl.scala 633:71] - node _T_3963 = and(_T_3961, _T_3962) @[ifu_mem_ctl.scala 633:54] - node _T_3964 = or(_T_3959, _T_3963) @[ifu_mem_ctl.scala 632:57] - node _T_3965 = eq(_T_3964, UInt<1>("h00")) @[ifu_mem_ctl.scala 628:5] - node _T_3966 = and(_T_3940, _T_3965) @[ifu_mem_ctl.scala 627:96] - node _T_3967 = and(io.ifc_fetch_req_bf, io.exu_flush_final) @[ifu_mem_ctl.scala 634:28] - node _T_3968 = eq(io.ifc_fetch_uncacheable_bf, UInt<1>("h00")) @[ifu_mem_ctl.scala 634:52] - node _T_3969 = and(_T_3967, _T_3968) @[ifu_mem_ctl.scala 634:50] - node _T_3970 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[ifu_mem_ctl.scala 634:83] - node _T_3971 = and(_T_3969, _T_3970) @[ifu_mem_ctl.scala 634:81] - node _T_3972 = or(_T_3966, _T_3971) @[ifu_mem_ctl.scala 633:93] - io.ic.rd_en <= _T_3972 @[ifu_mem_ctl.scala 627:15] + iccm_ecc_corr_index_ff <= _T_3936 @[ifu_mem_ctl.scala 625:26] + node _T_3937 = eq(io.ifc_fetch_uncacheable_bf, UInt<1>("h00")) @[ifu_mem_ctl.scala 626:41] + node _T_3938 = and(io.ifc_fetch_req_bf, _T_3937) @[ifu_mem_ctl.scala 626:39] + node _T_3939 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[ifu_mem_ctl.scala 626:72] + node _T_3940 = and(_T_3938, _T_3939) @[ifu_mem_ctl.scala 626:70] + node _T_3941 = eq(miss_state, UInt<3>("h06")) @[ifu_mem_ctl.scala 627:19] + node _T_3942 = eq(miss_state_en, UInt<1>("h00")) @[ifu_mem_ctl.scala 627:34] + node _T_3943 = and(_T_3941, _T_3942) @[ifu_mem_ctl.scala 627:32] + node _T_3944 = eq(miss_state, UInt<3>("h01")) @[ifu_mem_ctl.scala 628:19] + node _T_3945 = eq(miss_state_en, UInt<1>("h00")) @[ifu_mem_ctl.scala 628:39] + node _T_3946 = and(_T_3944, _T_3945) @[ifu_mem_ctl.scala 628:37] + node _T_3947 = or(_T_3943, _T_3946) @[ifu_mem_ctl.scala 627:88] + node _T_3948 = eq(miss_state, UInt<3>("h07")) @[ifu_mem_ctl.scala 629:19] + node _T_3949 = eq(miss_state_en, UInt<1>("h00")) @[ifu_mem_ctl.scala 629:43] + node _T_3950 = and(_T_3948, _T_3949) @[ifu_mem_ctl.scala 629:41] + node _T_3951 = or(_T_3947, _T_3950) @[ifu_mem_ctl.scala 628:88] + node _T_3952 = eq(miss_state, UInt<3>("h03")) @[ifu_mem_ctl.scala 630:19] + node _T_3953 = eq(miss_state_en, UInt<1>("h00")) @[ifu_mem_ctl.scala 630:37] + node _T_3954 = and(_T_3952, _T_3953) @[ifu_mem_ctl.scala 630:35] + node _T_3955 = or(_T_3951, _T_3954) @[ifu_mem_ctl.scala 629:88] + node _T_3956 = eq(miss_state, UInt<3>("h04")) @[ifu_mem_ctl.scala 631:19] + node _T_3957 = eq(miss_state_en, UInt<1>("h00")) @[ifu_mem_ctl.scala 631:40] + node _T_3958 = and(_T_3956, _T_3957) @[ifu_mem_ctl.scala 631:38] + node _T_3959 = or(_T_3955, _T_3958) @[ifu_mem_ctl.scala 630:88] + node _T_3960 = eq(miss_state, UInt<3>("h01")) @[ifu_mem_ctl.scala 632:19] + node _T_3961 = and(_T_3960, miss_state_en) @[ifu_mem_ctl.scala 632:37] + node _T_3962 = eq(miss_nxtstate, UInt<3>("h03")) @[ifu_mem_ctl.scala 632:71] + node _T_3963 = and(_T_3961, _T_3962) @[ifu_mem_ctl.scala 632:54] + node _T_3964 = or(_T_3959, _T_3963) @[ifu_mem_ctl.scala 631:57] + node _T_3965 = eq(_T_3964, UInt<1>("h00")) @[ifu_mem_ctl.scala 627:5] + node _T_3966 = and(_T_3940, _T_3965) @[ifu_mem_ctl.scala 626:96] + node _T_3967 = and(io.ifc_fetch_req_bf, io.exu_flush_final) @[ifu_mem_ctl.scala 633:28] + node _T_3968 = eq(io.ifc_fetch_uncacheable_bf, UInt<1>("h00")) @[ifu_mem_ctl.scala 633:52] + node _T_3969 = and(_T_3967, _T_3968) @[ifu_mem_ctl.scala 633:50] + node _T_3970 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[ifu_mem_ctl.scala 633:83] + node _T_3971 = and(_T_3969, _T_3970) @[ifu_mem_ctl.scala 633:81] + node _T_3972 = or(_T_3966, _T_3971) @[ifu_mem_ctl.scala 632:93] + io.ic.rd_en <= _T_3972 @[ifu_mem_ctl.scala 626:15] wire bus_ic_wr_en : UInt<2> bus_ic_wr_en <= UInt<1>("h00") node _T_3973 = bits(write_ic_16_bytes, 0, 0) @[Bitwise.scala 72:15] node _T_3974 = mux(_T_3973, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_3975 = and(bus_ic_wr_en, _T_3974) @[ifu_mem_ctl.scala 636:31] - io.ic.wr_en <= _T_3975 @[ifu_mem_ctl.scala 636:15] - node _T_3976 = eq(miss_state, UInt<3>("h01")) @[ifu_mem_ctl.scala 637:59] - node _T_3977 = eq(miss_state, UInt<3>("h06")) @[ifu_mem_ctl.scala 637:91] - node _T_3978 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[ifu_mem_ctl.scala 637:127] - node _T_3979 = or(_T_3978, stream_eol_f) @[ifu_mem_ctl.scala 637:151] - node _T_3980 = eq(_T_3979, UInt<1>("h00")) @[ifu_mem_ctl.scala 637:106] - node _T_3981 = and(_T_3977, _T_3980) @[ifu_mem_ctl.scala 637:104] - node _T_3982 = or(_T_3976, _T_3981) @[ifu_mem_ctl.scala 637:77] - node _T_3983 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 637:191] - node _T_3984 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 637:205] - node _T_3985 = and(_T_3983, _T_3984) @[ifu_mem_ctl.scala 637:203] - node _T_3986 = eq(_T_3985, UInt<1>("h00")) @[ifu_mem_ctl.scala 637:172] - node _T_3987 = and(_T_3982, _T_3986) @[ifu_mem_ctl.scala 637:170] - node _T_3988 = eq(_T_3987, UInt<1>("h00")) @[ifu_mem_ctl.scala 637:44] - node _T_3989 = and(write_ic_16_bytes, _T_3988) @[ifu_mem_ctl.scala 637:42] - io.ic_write_stall <= _T_3989 @[ifu_mem_ctl.scala 637:21] - reg _T_3990 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 638:53] - _T_3990 <= io.dec_mem_ctrl.dec_tlu_fence_i_wb @[ifu_mem_ctl.scala 638:53] - reset_all_tags <= _T_3990 @[ifu_mem_ctl.scala 638:18] - node _T_3991 = eq(ifu_wr_cumulative_err_data, UInt<1>("h00")) @[ifu_mem_ctl.scala 640:20] - node _T_3992 = or(reset_ic_in, reset_ic_ff) @[ifu_mem_ctl.scala 640:64] - node _T_3993 = eq(_T_3992, UInt<1>("h00")) @[ifu_mem_ctl.scala 640:50] - node _T_3994 = and(_T_3991, _T_3993) @[ifu_mem_ctl.scala 640:48] - node _T_3995 = eq(reset_tag_valid_for_miss, UInt<1>("h00")) @[ifu_mem_ctl.scala 640:81] - node ic_valid = and(_T_3994, _T_3995) @[ifu_mem_ctl.scala 640:79] - node _T_3996 = or(io.ic.debug_rd_en, io.ic.debug_wr_en) @[ifu_mem_ctl.scala 641:61] - node _T_3997 = and(_T_3996, io.ic.debug_tag_array) @[ifu_mem_ctl.scala 641:82] - node _T_3998 = bits(io.ic.debug_addr, 9, 3) @[ifu_mem_ctl.scala 641:123] - node _T_3999 = bits(ifu_status_wr_addr, 11, 5) @[ifu_mem_ctl.scala 642:25] - node ifu_status_wr_addr_w_debug = mux(_T_3997, _T_3998, _T_3999) @[ifu_mem_ctl.scala 641:41] - reg ifu_status_wr_addr_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 644:14] - ifu_status_wr_addr_ff <= ifu_status_wr_addr_w_debug @[ifu_mem_ctl.scala 644:14] + node _T_3975 = and(bus_ic_wr_en, _T_3974) @[ifu_mem_ctl.scala 635:31] + io.ic.wr_en <= _T_3975 @[ifu_mem_ctl.scala 635:15] + node _T_3976 = eq(miss_state, UInt<3>("h01")) @[ifu_mem_ctl.scala 636:59] + node _T_3977 = eq(miss_state, UInt<3>("h06")) @[ifu_mem_ctl.scala 636:91] + node _T_3978 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[ifu_mem_ctl.scala 636:127] + node _T_3979 = or(_T_3978, stream_eol_f) @[ifu_mem_ctl.scala 636:151] + node _T_3980 = eq(_T_3979, UInt<1>("h00")) @[ifu_mem_ctl.scala 636:106] + node _T_3981 = and(_T_3977, _T_3980) @[ifu_mem_ctl.scala 636:104] + node _T_3982 = or(_T_3976, _T_3981) @[ifu_mem_ctl.scala 636:77] + node _T_3983 = and(bus_ifu_wr_en_ff, last_beat) @[ifu_mem_ctl.scala 636:191] + node _T_3984 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 636:205] + node _T_3985 = and(_T_3983, _T_3984) @[ifu_mem_ctl.scala 636:203] + node _T_3986 = eq(_T_3985, UInt<1>("h00")) @[ifu_mem_ctl.scala 636:172] + node _T_3987 = and(_T_3982, _T_3986) @[ifu_mem_ctl.scala 636:170] + node _T_3988 = eq(_T_3987, UInt<1>("h00")) @[ifu_mem_ctl.scala 636:44] + node _T_3989 = and(write_ic_16_bytes, _T_3988) @[ifu_mem_ctl.scala 636:42] + io.ic_write_stall <= _T_3989 @[ifu_mem_ctl.scala 636:21] + reg _T_3990 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 637:53] + _T_3990 <= io.dec_mem_ctrl.dec_tlu_fence_i_wb @[ifu_mem_ctl.scala 637:53] + reset_all_tags <= _T_3990 @[ifu_mem_ctl.scala 637:18] + node _T_3991 = eq(ifu_wr_cumulative_err_data, UInt<1>("h00")) @[ifu_mem_ctl.scala 639:20] + node _T_3992 = or(reset_ic_in, reset_ic_ff) @[ifu_mem_ctl.scala 639:64] + node _T_3993 = eq(_T_3992, UInt<1>("h00")) @[ifu_mem_ctl.scala 639:50] + node _T_3994 = and(_T_3991, _T_3993) @[ifu_mem_ctl.scala 639:48] + node _T_3995 = eq(reset_tag_valid_for_miss, UInt<1>("h00")) @[ifu_mem_ctl.scala 639:81] + node ic_valid = and(_T_3994, _T_3995) @[ifu_mem_ctl.scala 639:79] + node _T_3996 = or(io.ic.debug_rd_en, io.ic.debug_wr_en) @[ifu_mem_ctl.scala 640:61] + node _T_3997 = and(_T_3996, io.ic.debug_tag_array) @[ifu_mem_ctl.scala 640:82] + node _T_3998 = bits(io.ic.debug_addr, 9, 3) @[ifu_mem_ctl.scala 640:123] + node _T_3999 = bits(ifu_status_wr_addr, 11, 5) @[ifu_mem_ctl.scala 641:25] + node ifu_status_wr_addr_w_debug = mux(_T_3997, _T_3998, _T_3999) @[ifu_mem_ctl.scala 640:41] + reg ifu_status_wr_addr_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 643:14] + ifu_status_wr_addr_ff <= ifu_status_wr_addr_w_debug @[ifu_mem_ctl.scala 643:14] wire way_status_wr_en : UInt<1> way_status_wr_en <= UInt<1>("h00") - node _T_4000 = and(io.ic.debug_wr_en, io.ic.debug_tag_array) @[ifu_mem_ctl.scala 647:74] - node way_status_wr_en_w_debug = or(way_status_wr_en, _T_4000) @[ifu_mem_ctl.scala 647:53] - reg way_status_wr_en_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 649:14] - way_status_wr_en_ff <= way_status_wr_en_w_debug @[ifu_mem_ctl.scala 649:14] + node _T_4000 = and(io.ic.debug_wr_en, io.ic.debug_tag_array) @[ifu_mem_ctl.scala 646:74] + node way_status_wr_en_w_debug = or(way_status_wr_en, _T_4000) @[ifu_mem_ctl.scala 646:53] + reg way_status_wr_en_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 648:14] + way_status_wr_en_ff <= way_status_wr_en_w_debug @[ifu_mem_ctl.scala 648:14] wire way_status_new : UInt<1> way_status_new <= UInt<1>("h00") - node _T_4001 = and(io.ic.debug_wr_en, io.ic.debug_tag_array) @[ifu_mem_ctl.scala 652:56] - node _T_4002 = bits(io.ic.debug_wr_data, 4, 4) @[ifu_mem_ctl.scala 653:55] - node way_status_new_w_debug = mux(_T_4001, _T_4002, way_status_new) @[ifu_mem_ctl.scala 652:37] - reg way_status_new_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 655:14] - way_status_new_ff <= way_status_new_w_debug @[ifu_mem_ctl.scala 655:14] - node _T_4003 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 657:89] - node way_status_clken_0 = eq(_T_4003, UInt<1>("h00")) @[ifu_mem_ctl.scala 657:132] - node _T_4004 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 657:89] - node way_status_clken_1 = eq(_T_4004, UInt<1>("h01")) @[ifu_mem_ctl.scala 657:132] - node _T_4005 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 657:89] - node way_status_clken_2 = eq(_T_4005, UInt<2>("h02")) @[ifu_mem_ctl.scala 657:132] - node _T_4006 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 657:89] - node way_status_clken_3 = eq(_T_4006, UInt<2>("h03")) @[ifu_mem_ctl.scala 657:132] - node _T_4007 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 657:89] - node way_status_clken_4 = eq(_T_4007, UInt<3>("h04")) @[ifu_mem_ctl.scala 657:132] - node _T_4008 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 657:89] - node way_status_clken_5 = eq(_T_4008, UInt<3>("h05")) @[ifu_mem_ctl.scala 657:132] - node _T_4009 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 657:89] - node way_status_clken_6 = eq(_T_4009, UInt<3>("h06")) @[ifu_mem_ctl.scala 657:132] - node _T_4010 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 657:89] - node way_status_clken_7 = eq(_T_4010, UInt<3>("h07")) @[ifu_mem_ctl.scala 657:132] - node _T_4011 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 657:89] - node way_status_clken_8 = eq(_T_4011, UInt<4>("h08")) @[ifu_mem_ctl.scala 657:132] - node _T_4012 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 657:89] - node way_status_clken_9 = eq(_T_4012, UInt<4>("h09")) @[ifu_mem_ctl.scala 657:132] - node _T_4013 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 657:89] - node way_status_clken_10 = eq(_T_4013, UInt<4>("h0a")) @[ifu_mem_ctl.scala 657:132] - node _T_4014 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 657:89] - node way_status_clken_11 = eq(_T_4014, UInt<4>("h0b")) @[ifu_mem_ctl.scala 657:132] - node _T_4015 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 657:89] - node way_status_clken_12 = eq(_T_4015, UInt<4>("h0c")) @[ifu_mem_ctl.scala 657:132] - node _T_4016 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 657:89] - node way_status_clken_13 = eq(_T_4016, UInt<4>("h0d")) @[ifu_mem_ctl.scala 657:132] - node _T_4017 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 657:89] - node way_status_clken_14 = eq(_T_4017, UInt<4>("h0e")) @[ifu_mem_ctl.scala 657:132] - node _T_4018 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 657:89] - node way_status_clken_15 = eq(_T_4018, UInt<4>("h0f")) @[ifu_mem_ctl.scala 657:132] + node _T_4001 = and(io.ic.debug_wr_en, io.ic.debug_tag_array) @[ifu_mem_ctl.scala 651:56] + node _T_4002 = bits(io.ic.debug_wr_data, 4, 4) @[ifu_mem_ctl.scala 652:55] + node way_status_new_w_debug = mux(_T_4001, _T_4002, way_status_new) @[ifu_mem_ctl.scala 651:37] + reg way_status_new_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 654:14] + way_status_new_ff <= way_status_new_w_debug @[ifu_mem_ctl.scala 654:14] + node _T_4003 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 656:89] + node way_status_clken_0 = eq(_T_4003, UInt<1>("h00")) @[ifu_mem_ctl.scala 656:132] + node _T_4004 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 656:89] + node way_status_clken_1 = eq(_T_4004, UInt<1>("h01")) @[ifu_mem_ctl.scala 656:132] + node _T_4005 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 656:89] + node way_status_clken_2 = eq(_T_4005, UInt<2>("h02")) @[ifu_mem_ctl.scala 656:132] + node _T_4006 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 656:89] + node way_status_clken_3 = eq(_T_4006, UInt<2>("h03")) @[ifu_mem_ctl.scala 656:132] + node _T_4007 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 656:89] + node way_status_clken_4 = eq(_T_4007, UInt<3>("h04")) @[ifu_mem_ctl.scala 656:132] + node _T_4008 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 656:89] + node way_status_clken_5 = eq(_T_4008, UInt<3>("h05")) @[ifu_mem_ctl.scala 656:132] + node _T_4009 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 656:89] + node way_status_clken_6 = eq(_T_4009, UInt<3>("h06")) @[ifu_mem_ctl.scala 656:132] + node _T_4010 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 656:89] + node way_status_clken_7 = eq(_T_4010, UInt<3>("h07")) @[ifu_mem_ctl.scala 656:132] + node _T_4011 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 656:89] + node way_status_clken_8 = eq(_T_4011, UInt<4>("h08")) @[ifu_mem_ctl.scala 656:132] + node _T_4012 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 656:89] + node way_status_clken_9 = eq(_T_4012, UInt<4>("h09")) @[ifu_mem_ctl.scala 656:132] + node _T_4013 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 656:89] + node way_status_clken_10 = eq(_T_4013, UInt<4>("h0a")) @[ifu_mem_ctl.scala 656:132] + node _T_4014 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 656:89] + node way_status_clken_11 = eq(_T_4014, UInt<4>("h0b")) @[ifu_mem_ctl.scala 656:132] + node _T_4015 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 656:89] + node way_status_clken_12 = eq(_T_4015, UInt<4>("h0c")) @[ifu_mem_ctl.scala 656:132] + node _T_4016 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 656:89] + node way_status_clken_13 = eq(_T_4016, UInt<4>("h0d")) @[ifu_mem_ctl.scala 656:132] + node _T_4017 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 656:89] + node way_status_clken_14 = eq(_T_4017, UInt<4>("h0e")) @[ifu_mem_ctl.scala 656:132] + node _T_4018 = bits(ifu_status_wr_addr_ff, 6, 3) @[ifu_mem_ctl.scala 656:89] + node way_status_clken_15 = eq(_T_4018, UInt<4>("h0f")) @[ifu_mem_ctl.scala 656:132] inst rvclkhdr_70 of rvclkhdr_70 @[lib.scala 343:22] rvclkhdr_70.clock <= clock rvclkhdr_70.reset <= reset @@ -8279,1031 +8279,1031 @@ circuit quasar_wrapper : rvclkhdr_85.io.clk <= clock @[lib.scala 344:17] rvclkhdr_85.io.en <= way_status_clken_15 @[lib.scala 345:16] rvclkhdr_85.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - wire way_status_out : UInt<1>[128] @[ifu_mem_ctl.scala 659:30] - node _T_4019 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4020 = eq(_T_4019, UInt<1>("h00")) @[ifu_mem_ctl.scala 661:128] - node _T_4021 = and(_T_4020, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + wire way_status_out : UInt<1>[128] @[ifu_mem_ctl.scala 658:30] + node _T_4019 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4020 = eq(_T_4019, UInt<1>("h00")) @[ifu_mem_ctl.scala 660:128] + node _T_4021 = and(_T_4020, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4022 : UInt, rvclkhdr_70.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4021 : @[Reg.scala 28:19] _T_4022 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[0] <= _T_4022 @[ifu_mem_ctl.scala 661:35] - node _T_4023 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4024 = eq(_T_4023, UInt<1>("h01")) @[ifu_mem_ctl.scala 661:128] - node _T_4025 = and(_T_4024, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[0] <= _T_4022 @[ifu_mem_ctl.scala 660:35] + node _T_4023 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4024 = eq(_T_4023, UInt<1>("h01")) @[ifu_mem_ctl.scala 660:128] + node _T_4025 = and(_T_4024, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4026 : UInt, rvclkhdr_70.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4025 : @[Reg.scala 28:19] _T_4026 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[1] <= _T_4026 @[ifu_mem_ctl.scala 661:35] - node _T_4027 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4028 = eq(_T_4027, UInt<2>("h02")) @[ifu_mem_ctl.scala 661:128] - node _T_4029 = and(_T_4028, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[1] <= _T_4026 @[ifu_mem_ctl.scala 660:35] + node _T_4027 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4028 = eq(_T_4027, UInt<2>("h02")) @[ifu_mem_ctl.scala 660:128] + node _T_4029 = and(_T_4028, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4030 : UInt, rvclkhdr_70.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4029 : @[Reg.scala 28:19] _T_4030 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[2] <= _T_4030 @[ifu_mem_ctl.scala 661:35] - node _T_4031 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4032 = eq(_T_4031, UInt<2>("h03")) @[ifu_mem_ctl.scala 661:128] - node _T_4033 = and(_T_4032, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[2] <= _T_4030 @[ifu_mem_ctl.scala 660:35] + node _T_4031 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4032 = eq(_T_4031, UInt<2>("h03")) @[ifu_mem_ctl.scala 660:128] + node _T_4033 = and(_T_4032, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4034 : UInt, rvclkhdr_70.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4033 : @[Reg.scala 28:19] _T_4034 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[3] <= _T_4034 @[ifu_mem_ctl.scala 661:35] - node _T_4035 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4036 = eq(_T_4035, UInt<3>("h04")) @[ifu_mem_ctl.scala 661:128] - node _T_4037 = and(_T_4036, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[3] <= _T_4034 @[ifu_mem_ctl.scala 660:35] + node _T_4035 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4036 = eq(_T_4035, UInt<3>("h04")) @[ifu_mem_ctl.scala 660:128] + node _T_4037 = and(_T_4036, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4038 : UInt, rvclkhdr_70.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4037 : @[Reg.scala 28:19] _T_4038 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[4] <= _T_4038 @[ifu_mem_ctl.scala 661:35] - node _T_4039 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4040 = eq(_T_4039, UInt<3>("h05")) @[ifu_mem_ctl.scala 661:128] - node _T_4041 = and(_T_4040, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[4] <= _T_4038 @[ifu_mem_ctl.scala 660:35] + node _T_4039 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4040 = eq(_T_4039, UInt<3>("h05")) @[ifu_mem_ctl.scala 660:128] + node _T_4041 = and(_T_4040, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4042 : UInt, rvclkhdr_70.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4041 : @[Reg.scala 28:19] _T_4042 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[5] <= _T_4042 @[ifu_mem_ctl.scala 661:35] - node _T_4043 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4044 = eq(_T_4043, UInt<3>("h06")) @[ifu_mem_ctl.scala 661:128] - node _T_4045 = and(_T_4044, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[5] <= _T_4042 @[ifu_mem_ctl.scala 660:35] + node _T_4043 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4044 = eq(_T_4043, UInt<3>("h06")) @[ifu_mem_ctl.scala 660:128] + node _T_4045 = and(_T_4044, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4046 : UInt, rvclkhdr_70.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4045 : @[Reg.scala 28:19] _T_4046 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[6] <= _T_4046 @[ifu_mem_ctl.scala 661:35] - node _T_4047 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4048 = eq(_T_4047, UInt<3>("h07")) @[ifu_mem_ctl.scala 661:128] - node _T_4049 = and(_T_4048, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[6] <= _T_4046 @[ifu_mem_ctl.scala 660:35] + node _T_4047 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4048 = eq(_T_4047, UInt<3>("h07")) @[ifu_mem_ctl.scala 660:128] + node _T_4049 = and(_T_4048, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4050 : UInt, rvclkhdr_70.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4049 : @[Reg.scala 28:19] _T_4050 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[7] <= _T_4050 @[ifu_mem_ctl.scala 661:35] - node _T_4051 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4052 = eq(_T_4051, UInt<1>("h00")) @[ifu_mem_ctl.scala 661:128] - node _T_4053 = and(_T_4052, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[7] <= _T_4050 @[ifu_mem_ctl.scala 660:35] + node _T_4051 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4052 = eq(_T_4051, UInt<1>("h00")) @[ifu_mem_ctl.scala 660:128] + node _T_4053 = and(_T_4052, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4054 : UInt, rvclkhdr_71.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4053 : @[Reg.scala 28:19] _T_4054 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[8] <= _T_4054 @[ifu_mem_ctl.scala 661:35] - node _T_4055 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4056 = eq(_T_4055, UInt<1>("h01")) @[ifu_mem_ctl.scala 661:128] - node _T_4057 = and(_T_4056, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[8] <= _T_4054 @[ifu_mem_ctl.scala 660:35] + node _T_4055 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4056 = eq(_T_4055, UInt<1>("h01")) @[ifu_mem_ctl.scala 660:128] + node _T_4057 = and(_T_4056, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4058 : UInt, rvclkhdr_71.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4057 : @[Reg.scala 28:19] _T_4058 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[9] <= _T_4058 @[ifu_mem_ctl.scala 661:35] - node _T_4059 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4060 = eq(_T_4059, UInt<2>("h02")) @[ifu_mem_ctl.scala 661:128] - node _T_4061 = and(_T_4060, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[9] <= _T_4058 @[ifu_mem_ctl.scala 660:35] + node _T_4059 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4060 = eq(_T_4059, UInt<2>("h02")) @[ifu_mem_ctl.scala 660:128] + node _T_4061 = and(_T_4060, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4062 : UInt, rvclkhdr_71.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4061 : @[Reg.scala 28:19] _T_4062 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[10] <= _T_4062 @[ifu_mem_ctl.scala 661:35] - node _T_4063 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4064 = eq(_T_4063, UInt<2>("h03")) @[ifu_mem_ctl.scala 661:128] - node _T_4065 = and(_T_4064, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[10] <= _T_4062 @[ifu_mem_ctl.scala 660:35] + node _T_4063 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4064 = eq(_T_4063, UInt<2>("h03")) @[ifu_mem_ctl.scala 660:128] + node _T_4065 = and(_T_4064, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4066 : UInt, rvclkhdr_71.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4065 : @[Reg.scala 28:19] _T_4066 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[11] <= _T_4066 @[ifu_mem_ctl.scala 661:35] - node _T_4067 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4068 = eq(_T_4067, UInt<3>("h04")) @[ifu_mem_ctl.scala 661:128] - node _T_4069 = and(_T_4068, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[11] <= _T_4066 @[ifu_mem_ctl.scala 660:35] + node _T_4067 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4068 = eq(_T_4067, UInt<3>("h04")) @[ifu_mem_ctl.scala 660:128] + node _T_4069 = and(_T_4068, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4070 : UInt, rvclkhdr_71.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4069 : @[Reg.scala 28:19] _T_4070 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[12] <= _T_4070 @[ifu_mem_ctl.scala 661:35] - node _T_4071 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4072 = eq(_T_4071, UInt<3>("h05")) @[ifu_mem_ctl.scala 661:128] - node _T_4073 = and(_T_4072, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[12] <= _T_4070 @[ifu_mem_ctl.scala 660:35] + node _T_4071 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4072 = eq(_T_4071, UInt<3>("h05")) @[ifu_mem_ctl.scala 660:128] + node _T_4073 = and(_T_4072, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4074 : UInt, rvclkhdr_71.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4073 : @[Reg.scala 28:19] _T_4074 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[13] <= _T_4074 @[ifu_mem_ctl.scala 661:35] - node _T_4075 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4076 = eq(_T_4075, UInt<3>("h06")) @[ifu_mem_ctl.scala 661:128] - node _T_4077 = and(_T_4076, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[13] <= _T_4074 @[ifu_mem_ctl.scala 660:35] + node _T_4075 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4076 = eq(_T_4075, UInt<3>("h06")) @[ifu_mem_ctl.scala 660:128] + node _T_4077 = and(_T_4076, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4078 : UInt, rvclkhdr_71.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4077 : @[Reg.scala 28:19] _T_4078 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[14] <= _T_4078 @[ifu_mem_ctl.scala 661:35] - node _T_4079 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4080 = eq(_T_4079, UInt<3>("h07")) @[ifu_mem_ctl.scala 661:128] - node _T_4081 = and(_T_4080, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[14] <= _T_4078 @[ifu_mem_ctl.scala 660:35] + node _T_4079 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4080 = eq(_T_4079, UInt<3>("h07")) @[ifu_mem_ctl.scala 660:128] + node _T_4081 = and(_T_4080, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4082 : UInt, rvclkhdr_71.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4081 : @[Reg.scala 28:19] _T_4082 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[15] <= _T_4082 @[ifu_mem_ctl.scala 661:35] - node _T_4083 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4084 = eq(_T_4083, UInt<1>("h00")) @[ifu_mem_ctl.scala 661:128] - node _T_4085 = and(_T_4084, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[15] <= _T_4082 @[ifu_mem_ctl.scala 660:35] + node _T_4083 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4084 = eq(_T_4083, UInt<1>("h00")) @[ifu_mem_ctl.scala 660:128] + node _T_4085 = and(_T_4084, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4086 : UInt, rvclkhdr_72.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4085 : @[Reg.scala 28:19] _T_4086 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[16] <= _T_4086 @[ifu_mem_ctl.scala 661:35] - node _T_4087 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4088 = eq(_T_4087, UInt<1>("h01")) @[ifu_mem_ctl.scala 661:128] - node _T_4089 = and(_T_4088, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[16] <= _T_4086 @[ifu_mem_ctl.scala 660:35] + node _T_4087 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4088 = eq(_T_4087, UInt<1>("h01")) @[ifu_mem_ctl.scala 660:128] + node _T_4089 = and(_T_4088, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4090 : UInt, rvclkhdr_72.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4089 : @[Reg.scala 28:19] _T_4090 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[17] <= _T_4090 @[ifu_mem_ctl.scala 661:35] - node _T_4091 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4092 = eq(_T_4091, UInt<2>("h02")) @[ifu_mem_ctl.scala 661:128] - node _T_4093 = and(_T_4092, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[17] <= _T_4090 @[ifu_mem_ctl.scala 660:35] + node _T_4091 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4092 = eq(_T_4091, UInt<2>("h02")) @[ifu_mem_ctl.scala 660:128] + node _T_4093 = and(_T_4092, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4094 : UInt, rvclkhdr_72.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4093 : @[Reg.scala 28:19] _T_4094 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[18] <= _T_4094 @[ifu_mem_ctl.scala 661:35] - node _T_4095 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4096 = eq(_T_4095, UInt<2>("h03")) @[ifu_mem_ctl.scala 661:128] - node _T_4097 = and(_T_4096, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[18] <= _T_4094 @[ifu_mem_ctl.scala 660:35] + node _T_4095 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4096 = eq(_T_4095, UInt<2>("h03")) @[ifu_mem_ctl.scala 660:128] + node _T_4097 = and(_T_4096, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4098 : UInt, rvclkhdr_72.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4097 : @[Reg.scala 28:19] _T_4098 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[19] <= _T_4098 @[ifu_mem_ctl.scala 661:35] - node _T_4099 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4100 = eq(_T_4099, UInt<3>("h04")) @[ifu_mem_ctl.scala 661:128] - node _T_4101 = and(_T_4100, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[19] <= _T_4098 @[ifu_mem_ctl.scala 660:35] + node _T_4099 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4100 = eq(_T_4099, UInt<3>("h04")) @[ifu_mem_ctl.scala 660:128] + node _T_4101 = and(_T_4100, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4102 : UInt, rvclkhdr_72.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4101 : @[Reg.scala 28:19] _T_4102 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[20] <= _T_4102 @[ifu_mem_ctl.scala 661:35] - node _T_4103 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4104 = eq(_T_4103, UInt<3>("h05")) @[ifu_mem_ctl.scala 661:128] - node _T_4105 = and(_T_4104, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[20] <= _T_4102 @[ifu_mem_ctl.scala 660:35] + node _T_4103 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4104 = eq(_T_4103, UInt<3>("h05")) @[ifu_mem_ctl.scala 660:128] + node _T_4105 = and(_T_4104, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4106 : UInt, rvclkhdr_72.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4105 : @[Reg.scala 28:19] _T_4106 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[21] <= _T_4106 @[ifu_mem_ctl.scala 661:35] - node _T_4107 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4108 = eq(_T_4107, UInt<3>("h06")) @[ifu_mem_ctl.scala 661:128] - node _T_4109 = and(_T_4108, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[21] <= _T_4106 @[ifu_mem_ctl.scala 660:35] + node _T_4107 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4108 = eq(_T_4107, UInt<3>("h06")) @[ifu_mem_ctl.scala 660:128] + node _T_4109 = and(_T_4108, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4110 : UInt, rvclkhdr_72.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4109 : @[Reg.scala 28:19] _T_4110 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[22] <= _T_4110 @[ifu_mem_ctl.scala 661:35] - node _T_4111 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4112 = eq(_T_4111, UInt<3>("h07")) @[ifu_mem_ctl.scala 661:128] - node _T_4113 = and(_T_4112, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[22] <= _T_4110 @[ifu_mem_ctl.scala 660:35] + node _T_4111 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4112 = eq(_T_4111, UInt<3>("h07")) @[ifu_mem_ctl.scala 660:128] + node _T_4113 = and(_T_4112, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4114 : UInt, rvclkhdr_72.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4113 : @[Reg.scala 28:19] _T_4114 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[23] <= _T_4114 @[ifu_mem_ctl.scala 661:35] - node _T_4115 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4116 = eq(_T_4115, UInt<1>("h00")) @[ifu_mem_ctl.scala 661:128] - node _T_4117 = and(_T_4116, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[23] <= _T_4114 @[ifu_mem_ctl.scala 660:35] + node _T_4115 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4116 = eq(_T_4115, UInt<1>("h00")) @[ifu_mem_ctl.scala 660:128] + node _T_4117 = and(_T_4116, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4118 : UInt, rvclkhdr_73.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4117 : @[Reg.scala 28:19] _T_4118 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[24] <= _T_4118 @[ifu_mem_ctl.scala 661:35] - node _T_4119 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4120 = eq(_T_4119, UInt<1>("h01")) @[ifu_mem_ctl.scala 661:128] - node _T_4121 = and(_T_4120, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[24] <= _T_4118 @[ifu_mem_ctl.scala 660:35] + node _T_4119 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4120 = eq(_T_4119, UInt<1>("h01")) @[ifu_mem_ctl.scala 660:128] + node _T_4121 = and(_T_4120, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4122 : UInt, rvclkhdr_73.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4121 : @[Reg.scala 28:19] _T_4122 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[25] <= _T_4122 @[ifu_mem_ctl.scala 661:35] - node _T_4123 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4124 = eq(_T_4123, UInt<2>("h02")) @[ifu_mem_ctl.scala 661:128] - node _T_4125 = and(_T_4124, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[25] <= _T_4122 @[ifu_mem_ctl.scala 660:35] + node _T_4123 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4124 = eq(_T_4123, UInt<2>("h02")) @[ifu_mem_ctl.scala 660:128] + node _T_4125 = and(_T_4124, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4126 : UInt, rvclkhdr_73.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4125 : @[Reg.scala 28:19] _T_4126 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[26] <= _T_4126 @[ifu_mem_ctl.scala 661:35] - node _T_4127 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4128 = eq(_T_4127, UInt<2>("h03")) @[ifu_mem_ctl.scala 661:128] - node _T_4129 = and(_T_4128, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[26] <= _T_4126 @[ifu_mem_ctl.scala 660:35] + node _T_4127 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4128 = eq(_T_4127, UInt<2>("h03")) @[ifu_mem_ctl.scala 660:128] + node _T_4129 = and(_T_4128, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4130 : UInt, rvclkhdr_73.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4129 : @[Reg.scala 28:19] _T_4130 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[27] <= _T_4130 @[ifu_mem_ctl.scala 661:35] - node _T_4131 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4132 = eq(_T_4131, UInt<3>("h04")) @[ifu_mem_ctl.scala 661:128] - node _T_4133 = and(_T_4132, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[27] <= _T_4130 @[ifu_mem_ctl.scala 660:35] + node _T_4131 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4132 = eq(_T_4131, UInt<3>("h04")) @[ifu_mem_ctl.scala 660:128] + node _T_4133 = and(_T_4132, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4134 : UInt, rvclkhdr_73.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4133 : @[Reg.scala 28:19] _T_4134 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[28] <= _T_4134 @[ifu_mem_ctl.scala 661:35] - node _T_4135 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4136 = eq(_T_4135, UInt<3>("h05")) @[ifu_mem_ctl.scala 661:128] - node _T_4137 = and(_T_4136, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[28] <= _T_4134 @[ifu_mem_ctl.scala 660:35] + node _T_4135 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4136 = eq(_T_4135, UInt<3>("h05")) @[ifu_mem_ctl.scala 660:128] + node _T_4137 = and(_T_4136, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4138 : UInt, rvclkhdr_73.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4137 : @[Reg.scala 28:19] _T_4138 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[29] <= _T_4138 @[ifu_mem_ctl.scala 661:35] - node _T_4139 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4140 = eq(_T_4139, UInt<3>("h06")) @[ifu_mem_ctl.scala 661:128] - node _T_4141 = and(_T_4140, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[29] <= _T_4138 @[ifu_mem_ctl.scala 660:35] + node _T_4139 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4140 = eq(_T_4139, UInt<3>("h06")) @[ifu_mem_ctl.scala 660:128] + node _T_4141 = and(_T_4140, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4142 : UInt, rvclkhdr_73.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4141 : @[Reg.scala 28:19] _T_4142 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[30] <= _T_4142 @[ifu_mem_ctl.scala 661:35] - node _T_4143 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4144 = eq(_T_4143, UInt<3>("h07")) @[ifu_mem_ctl.scala 661:128] - node _T_4145 = and(_T_4144, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[30] <= _T_4142 @[ifu_mem_ctl.scala 660:35] + node _T_4143 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4144 = eq(_T_4143, UInt<3>("h07")) @[ifu_mem_ctl.scala 660:128] + node _T_4145 = and(_T_4144, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4146 : UInt, rvclkhdr_73.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4145 : @[Reg.scala 28:19] _T_4146 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[31] <= _T_4146 @[ifu_mem_ctl.scala 661:35] - node _T_4147 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4148 = eq(_T_4147, UInt<1>("h00")) @[ifu_mem_ctl.scala 661:128] - node _T_4149 = and(_T_4148, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[31] <= _T_4146 @[ifu_mem_ctl.scala 660:35] + node _T_4147 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4148 = eq(_T_4147, UInt<1>("h00")) @[ifu_mem_ctl.scala 660:128] + node _T_4149 = and(_T_4148, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4150 : UInt, rvclkhdr_74.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4149 : @[Reg.scala 28:19] _T_4150 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[32] <= _T_4150 @[ifu_mem_ctl.scala 661:35] - node _T_4151 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4152 = eq(_T_4151, UInt<1>("h01")) @[ifu_mem_ctl.scala 661:128] - node _T_4153 = and(_T_4152, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[32] <= _T_4150 @[ifu_mem_ctl.scala 660:35] + node _T_4151 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4152 = eq(_T_4151, UInt<1>("h01")) @[ifu_mem_ctl.scala 660:128] + node _T_4153 = and(_T_4152, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4154 : UInt, rvclkhdr_74.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4153 : @[Reg.scala 28:19] _T_4154 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[33] <= _T_4154 @[ifu_mem_ctl.scala 661:35] - node _T_4155 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4156 = eq(_T_4155, UInt<2>("h02")) @[ifu_mem_ctl.scala 661:128] - node _T_4157 = and(_T_4156, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[33] <= _T_4154 @[ifu_mem_ctl.scala 660:35] + node _T_4155 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4156 = eq(_T_4155, UInt<2>("h02")) @[ifu_mem_ctl.scala 660:128] + node _T_4157 = and(_T_4156, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4158 : UInt, rvclkhdr_74.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4157 : @[Reg.scala 28:19] _T_4158 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[34] <= _T_4158 @[ifu_mem_ctl.scala 661:35] - node _T_4159 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4160 = eq(_T_4159, UInt<2>("h03")) @[ifu_mem_ctl.scala 661:128] - node _T_4161 = and(_T_4160, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[34] <= _T_4158 @[ifu_mem_ctl.scala 660:35] + node _T_4159 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4160 = eq(_T_4159, UInt<2>("h03")) @[ifu_mem_ctl.scala 660:128] + node _T_4161 = and(_T_4160, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4162 : UInt, rvclkhdr_74.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4161 : @[Reg.scala 28:19] _T_4162 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[35] <= _T_4162 @[ifu_mem_ctl.scala 661:35] - node _T_4163 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4164 = eq(_T_4163, UInt<3>("h04")) @[ifu_mem_ctl.scala 661:128] - node _T_4165 = and(_T_4164, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[35] <= _T_4162 @[ifu_mem_ctl.scala 660:35] + node _T_4163 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4164 = eq(_T_4163, UInt<3>("h04")) @[ifu_mem_ctl.scala 660:128] + node _T_4165 = and(_T_4164, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4166 : UInt, rvclkhdr_74.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4165 : @[Reg.scala 28:19] _T_4166 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[36] <= _T_4166 @[ifu_mem_ctl.scala 661:35] - node _T_4167 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4168 = eq(_T_4167, UInt<3>("h05")) @[ifu_mem_ctl.scala 661:128] - node _T_4169 = and(_T_4168, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[36] <= _T_4166 @[ifu_mem_ctl.scala 660:35] + node _T_4167 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4168 = eq(_T_4167, UInt<3>("h05")) @[ifu_mem_ctl.scala 660:128] + node _T_4169 = and(_T_4168, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4170 : UInt, rvclkhdr_74.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4169 : @[Reg.scala 28:19] _T_4170 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[37] <= _T_4170 @[ifu_mem_ctl.scala 661:35] - node _T_4171 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4172 = eq(_T_4171, UInt<3>("h06")) @[ifu_mem_ctl.scala 661:128] - node _T_4173 = and(_T_4172, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[37] <= _T_4170 @[ifu_mem_ctl.scala 660:35] + node _T_4171 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4172 = eq(_T_4171, UInt<3>("h06")) @[ifu_mem_ctl.scala 660:128] + node _T_4173 = and(_T_4172, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4174 : UInt, rvclkhdr_74.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4173 : @[Reg.scala 28:19] _T_4174 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[38] <= _T_4174 @[ifu_mem_ctl.scala 661:35] - node _T_4175 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4176 = eq(_T_4175, UInt<3>("h07")) @[ifu_mem_ctl.scala 661:128] - node _T_4177 = and(_T_4176, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[38] <= _T_4174 @[ifu_mem_ctl.scala 660:35] + node _T_4175 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4176 = eq(_T_4175, UInt<3>("h07")) @[ifu_mem_ctl.scala 660:128] + node _T_4177 = and(_T_4176, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4178 : UInt, rvclkhdr_74.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4177 : @[Reg.scala 28:19] _T_4178 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[39] <= _T_4178 @[ifu_mem_ctl.scala 661:35] - node _T_4179 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4180 = eq(_T_4179, UInt<1>("h00")) @[ifu_mem_ctl.scala 661:128] - node _T_4181 = and(_T_4180, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[39] <= _T_4178 @[ifu_mem_ctl.scala 660:35] + node _T_4179 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4180 = eq(_T_4179, UInt<1>("h00")) @[ifu_mem_ctl.scala 660:128] + node _T_4181 = and(_T_4180, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4182 : UInt, rvclkhdr_75.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4181 : @[Reg.scala 28:19] _T_4182 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[40] <= _T_4182 @[ifu_mem_ctl.scala 661:35] - node _T_4183 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4184 = eq(_T_4183, UInt<1>("h01")) @[ifu_mem_ctl.scala 661:128] - node _T_4185 = and(_T_4184, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[40] <= _T_4182 @[ifu_mem_ctl.scala 660:35] + node _T_4183 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4184 = eq(_T_4183, UInt<1>("h01")) @[ifu_mem_ctl.scala 660:128] + node _T_4185 = and(_T_4184, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4186 : UInt, rvclkhdr_75.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4185 : @[Reg.scala 28:19] _T_4186 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[41] <= _T_4186 @[ifu_mem_ctl.scala 661:35] - node _T_4187 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4188 = eq(_T_4187, UInt<2>("h02")) @[ifu_mem_ctl.scala 661:128] - node _T_4189 = and(_T_4188, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[41] <= _T_4186 @[ifu_mem_ctl.scala 660:35] + node _T_4187 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4188 = eq(_T_4187, UInt<2>("h02")) @[ifu_mem_ctl.scala 660:128] + node _T_4189 = and(_T_4188, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4190 : UInt, rvclkhdr_75.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4189 : @[Reg.scala 28:19] _T_4190 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[42] <= _T_4190 @[ifu_mem_ctl.scala 661:35] - node _T_4191 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4192 = eq(_T_4191, UInt<2>("h03")) @[ifu_mem_ctl.scala 661:128] - node _T_4193 = and(_T_4192, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[42] <= _T_4190 @[ifu_mem_ctl.scala 660:35] + node _T_4191 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4192 = eq(_T_4191, UInt<2>("h03")) @[ifu_mem_ctl.scala 660:128] + node _T_4193 = and(_T_4192, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4194 : UInt, rvclkhdr_75.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4193 : @[Reg.scala 28:19] _T_4194 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[43] <= _T_4194 @[ifu_mem_ctl.scala 661:35] - node _T_4195 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4196 = eq(_T_4195, UInt<3>("h04")) @[ifu_mem_ctl.scala 661:128] - node _T_4197 = and(_T_4196, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[43] <= _T_4194 @[ifu_mem_ctl.scala 660:35] + node _T_4195 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4196 = eq(_T_4195, UInt<3>("h04")) @[ifu_mem_ctl.scala 660:128] + node _T_4197 = and(_T_4196, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4198 : UInt, rvclkhdr_75.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4197 : @[Reg.scala 28:19] _T_4198 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[44] <= _T_4198 @[ifu_mem_ctl.scala 661:35] - node _T_4199 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4200 = eq(_T_4199, UInt<3>("h05")) @[ifu_mem_ctl.scala 661:128] - node _T_4201 = and(_T_4200, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[44] <= _T_4198 @[ifu_mem_ctl.scala 660:35] + node _T_4199 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4200 = eq(_T_4199, UInt<3>("h05")) @[ifu_mem_ctl.scala 660:128] + node _T_4201 = and(_T_4200, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4202 : UInt, rvclkhdr_75.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4201 : @[Reg.scala 28:19] _T_4202 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[45] <= _T_4202 @[ifu_mem_ctl.scala 661:35] - node _T_4203 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4204 = eq(_T_4203, UInt<3>("h06")) @[ifu_mem_ctl.scala 661:128] - node _T_4205 = and(_T_4204, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[45] <= _T_4202 @[ifu_mem_ctl.scala 660:35] + node _T_4203 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4204 = eq(_T_4203, UInt<3>("h06")) @[ifu_mem_ctl.scala 660:128] + node _T_4205 = and(_T_4204, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4206 : UInt, rvclkhdr_75.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4205 : @[Reg.scala 28:19] _T_4206 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[46] <= _T_4206 @[ifu_mem_ctl.scala 661:35] - node _T_4207 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4208 = eq(_T_4207, UInt<3>("h07")) @[ifu_mem_ctl.scala 661:128] - node _T_4209 = and(_T_4208, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[46] <= _T_4206 @[ifu_mem_ctl.scala 660:35] + node _T_4207 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4208 = eq(_T_4207, UInt<3>("h07")) @[ifu_mem_ctl.scala 660:128] + node _T_4209 = and(_T_4208, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4210 : UInt, rvclkhdr_75.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4209 : @[Reg.scala 28:19] _T_4210 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[47] <= _T_4210 @[ifu_mem_ctl.scala 661:35] - node _T_4211 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4212 = eq(_T_4211, UInt<1>("h00")) @[ifu_mem_ctl.scala 661:128] - node _T_4213 = and(_T_4212, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[47] <= _T_4210 @[ifu_mem_ctl.scala 660:35] + node _T_4211 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4212 = eq(_T_4211, UInt<1>("h00")) @[ifu_mem_ctl.scala 660:128] + node _T_4213 = and(_T_4212, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4214 : UInt, rvclkhdr_76.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4213 : @[Reg.scala 28:19] _T_4214 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[48] <= _T_4214 @[ifu_mem_ctl.scala 661:35] - node _T_4215 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4216 = eq(_T_4215, UInt<1>("h01")) @[ifu_mem_ctl.scala 661:128] - node _T_4217 = and(_T_4216, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[48] <= _T_4214 @[ifu_mem_ctl.scala 660:35] + node _T_4215 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4216 = eq(_T_4215, UInt<1>("h01")) @[ifu_mem_ctl.scala 660:128] + node _T_4217 = and(_T_4216, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4218 : UInt, rvclkhdr_76.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4217 : @[Reg.scala 28:19] _T_4218 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[49] <= _T_4218 @[ifu_mem_ctl.scala 661:35] - node _T_4219 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4220 = eq(_T_4219, UInt<2>("h02")) @[ifu_mem_ctl.scala 661:128] - node _T_4221 = and(_T_4220, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[49] <= _T_4218 @[ifu_mem_ctl.scala 660:35] + node _T_4219 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4220 = eq(_T_4219, UInt<2>("h02")) @[ifu_mem_ctl.scala 660:128] + node _T_4221 = and(_T_4220, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4222 : UInt, rvclkhdr_76.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4221 : @[Reg.scala 28:19] _T_4222 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[50] <= _T_4222 @[ifu_mem_ctl.scala 661:35] - node _T_4223 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4224 = eq(_T_4223, UInt<2>("h03")) @[ifu_mem_ctl.scala 661:128] - node _T_4225 = and(_T_4224, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[50] <= _T_4222 @[ifu_mem_ctl.scala 660:35] + node _T_4223 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4224 = eq(_T_4223, UInt<2>("h03")) @[ifu_mem_ctl.scala 660:128] + node _T_4225 = and(_T_4224, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4226 : UInt, rvclkhdr_76.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4225 : @[Reg.scala 28:19] _T_4226 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[51] <= _T_4226 @[ifu_mem_ctl.scala 661:35] - node _T_4227 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4228 = eq(_T_4227, UInt<3>("h04")) @[ifu_mem_ctl.scala 661:128] - node _T_4229 = and(_T_4228, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[51] <= _T_4226 @[ifu_mem_ctl.scala 660:35] + node _T_4227 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4228 = eq(_T_4227, UInt<3>("h04")) @[ifu_mem_ctl.scala 660:128] + node _T_4229 = and(_T_4228, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4230 : UInt, rvclkhdr_76.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4229 : @[Reg.scala 28:19] _T_4230 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[52] <= _T_4230 @[ifu_mem_ctl.scala 661:35] - node _T_4231 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4232 = eq(_T_4231, UInt<3>("h05")) @[ifu_mem_ctl.scala 661:128] - node _T_4233 = and(_T_4232, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[52] <= _T_4230 @[ifu_mem_ctl.scala 660:35] + node _T_4231 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4232 = eq(_T_4231, UInt<3>("h05")) @[ifu_mem_ctl.scala 660:128] + node _T_4233 = and(_T_4232, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4234 : UInt, rvclkhdr_76.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4233 : @[Reg.scala 28:19] _T_4234 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[53] <= _T_4234 @[ifu_mem_ctl.scala 661:35] - node _T_4235 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4236 = eq(_T_4235, UInt<3>("h06")) @[ifu_mem_ctl.scala 661:128] - node _T_4237 = and(_T_4236, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[53] <= _T_4234 @[ifu_mem_ctl.scala 660:35] + node _T_4235 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4236 = eq(_T_4235, UInt<3>("h06")) @[ifu_mem_ctl.scala 660:128] + node _T_4237 = and(_T_4236, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4238 : UInt, rvclkhdr_76.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4237 : @[Reg.scala 28:19] _T_4238 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[54] <= _T_4238 @[ifu_mem_ctl.scala 661:35] - node _T_4239 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4240 = eq(_T_4239, UInt<3>("h07")) @[ifu_mem_ctl.scala 661:128] - node _T_4241 = and(_T_4240, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[54] <= _T_4238 @[ifu_mem_ctl.scala 660:35] + node _T_4239 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4240 = eq(_T_4239, UInt<3>("h07")) @[ifu_mem_ctl.scala 660:128] + node _T_4241 = and(_T_4240, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4242 : UInt, rvclkhdr_76.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4241 : @[Reg.scala 28:19] _T_4242 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[55] <= _T_4242 @[ifu_mem_ctl.scala 661:35] - node _T_4243 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4244 = eq(_T_4243, UInt<1>("h00")) @[ifu_mem_ctl.scala 661:128] - node _T_4245 = and(_T_4244, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[55] <= _T_4242 @[ifu_mem_ctl.scala 660:35] + node _T_4243 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4244 = eq(_T_4243, UInt<1>("h00")) @[ifu_mem_ctl.scala 660:128] + node _T_4245 = and(_T_4244, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4246 : UInt, rvclkhdr_77.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4245 : @[Reg.scala 28:19] _T_4246 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[56] <= _T_4246 @[ifu_mem_ctl.scala 661:35] - node _T_4247 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4248 = eq(_T_4247, UInt<1>("h01")) @[ifu_mem_ctl.scala 661:128] - node _T_4249 = and(_T_4248, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[56] <= _T_4246 @[ifu_mem_ctl.scala 660:35] + node _T_4247 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4248 = eq(_T_4247, UInt<1>("h01")) @[ifu_mem_ctl.scala 660:128] + node _T_4249 = and(_T_4248, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4250 : UInt, rvclkhdr_77.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4249 : @[Reg.scala 28:19] _T_4250 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[57] <= _T_4250 @[ifu_mem_ctl.scala 661:35] - node _T_4251 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4252 = eq(_T_4251, UInt<2>("h02")) @[ifu_mem_ctl.scala 661:128] - node _T_4253 = and(_T_4252, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[57] <= _T_4250 @[ifu_mem_ctl.scala 660:35] + node _T_4251 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4252 = eq(_T_4251, UInt<2>("h02")) @[ifu_mem_ctl.scala 660:128] + node _T_4253 = and(_T_4252, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4254 : UInt, rvclkhdr_77.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4253 : @[Reg.scala 28:19] _T_4254 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[58] <= _T_4254 @[ifu_mem_ctl.scala 661:35] - node _T_4255 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4256 = eq(_T_4255, UInt<2>("h03")) @[ifu_mem_ctl.scala 661:128] - node _T_4257 = and(_T_4256, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[58] <= _T_4254 @[ifu_mem_ctl.scala 660:35] + node _T_4255 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4256 = eq(_T_4255, UInt<2>("h03")) @[ifu_mem_ctl.scala 660:128] + node _T_4257 = and(_T_4256, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4258 : UInt, rvclkhdr_77.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4257 : @[Reg.scala 28:19] _T_4258 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[59] <= _T_4258 @[ifu_mem_ctl.scala 661:35] - node _T_4259 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4260 = eq(_T_4259, UInt<3>("h04")) @[ifu_mem_ctl.scala 661:128] - node _T_4261 = and(_T_4260, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[59] <= _T_4258 @[ifu_mem_ctl.scala 660:35] + node _T_4259 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4260 = eq(_T_4259, UInt<3>("h04")) @[ifu_mem_ctl.scala 660:128] + node _T_4261 = and(_T_4260, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4262 : UInt, rvclkhdr_77.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4261 : @[Reg.scala 28:19] _T_4262 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[60] <= _T_4262 @[ifu_mem_ctl.scala 661:35] - node _T_4263 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4264 = eq(_T_4263, UInt<3>("h05")) @[ifu_mem_ctl.scala 661:128] - node _T_4265 = and(_T_4264, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[60] <= _T_4262 @[ifu_mem_ctl.scala 660:35] + node _T_4263 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4264 = eq(_T_4263, UInt<3>("h05")) @[ifu_mem_ctl.scala 660:128] + node _T_4265 = and(_T_4264, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4266 : UInt, rvclkhdr_77.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4265 : @[Reg.scala 28:19] _T_4266 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[61] <= _T_4266 @[ifu_mem_ctl.scala 661:35] - node _T_4267 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4268 = eq(_T_4267, UInt<3>("h06")) @[ifu_mem_ctl.scala 661:128] - node _T_4269 = and(_T_4268, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[61] <= _T_4266 @[ifu_mem_ctl.scala 660:35] + node _T_4267 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4268 = eq(_T_4267, UInt<3>("h06")) @[ifu_mem_ctl.scala 660:128] + node _T_4269 = and(_T_4268, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4270 : UInt, rvclkhdr_77.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4269 : @[Reg.scala 28:19] _T_4270 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[62] <= _T_4270 @[ifu_mem_ctl.scala 661:35] - node _T_4271 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4272 = eq(_T_4271, UInt<3>("h07")) @[ifu_mem_ctl.scala 661:128] - node _T_4273 = and(_T_4272, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[62] <= _T_4270 @[ifu_mem_ctl.scala 660:35] + node _T_4271 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4272 = eq(_T_4271, UInt<3>("h07")) @[ifu_mem_ctl.scala 660:128] + node _T_4273 = and(_T_4272, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4274 : UInt, rvclkhdr_77.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4273 : @[Reg.scala 28:19] _T_4274 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[63] <= _T_4274 @[ifu_mem_ctl.scala 661:35] - node _T_4275 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4276 = eq(_T_4275, UInt<1>("h00")) @[ifu_mem_ctl.scala 661:128] - node _T_4277 = and(_T_4276, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[63] <= _T_4274 @[ifu_mem_ctl.scala 660:35] + node _T_4275 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4276 = eq(_T_4275, UInt<1>("h00")) @[ifu_mem_ctl.scala 660:128] + node _T_4277 = and(_T_4276, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4278 : UInt, rvclkhdr_78.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4277 : @[Reg.scala 28:19] _T_4278 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[64] <= _T_4278 @[ifu_mem_ctl.scala 661:35] - node _T_4279 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4280 = eq(_T_4279, UInt<1>("h01")) @[ifu_mem_ctl.scala 661:128] - node _T_4281 = and(_T_4280, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[64] <= _T_4278 @[ifu_mem_ctl.scala 660:35] + node _T_4279 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4280 = eq(_T_4279, UInt<1>("h01")) @[ifu_mem_ctl.scala 660:128] + node _T_4281 = and(_T_4280, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4282 : UInt, rvclkhdr_78.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4281 : @[Reg.scala 28:19] _T_4282 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[65] <= _T_4282 @[ifu_mem_ctl.scala 661:35] - node _T_4283 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4284 = eq(_T_4283, UInt<2>("h02")) @[ifu_mem_ctl.scala 661:128] - node _T_4285 = and(_T_4284, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[65] <= _T_4282 @[ifu_mem_ctl.scala 660:35] + node _T_4283 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4284 = eq(_T_4283, UInt<2>("h02")) @[ifu_mem_ctl.scala 660:128] + node _T_4285 = and(_T_4284, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4286 : UInt, rvclkhdr_78.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4285 : @[Reg.scala 28:19] _T_4286 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[66] <= _T_4286 @[ifu_mem_ctl.scala 661:35] - node _T_4287 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4288 = eq(_T_4287, UInt<2>("h03")) @[ifu_mem_ctl.scala 661:128] - node _T_4289 = and(_T_4288, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[66] <= _T_4286 @[ifu_mem_ctl.scala 660:35] + node _T_4287 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4288 = eq(_T_4287, UInt<2>("h03")) @[ifu_mem_ctl.scala 660:128] + node _T_4289 = and(_T_4288, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4290 : UInt, rvclkhdr_78.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4289 : @[Reg.scala 28:19] _T_4290 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[67] <= _T_4290 @[ifu_mem_ctl.scala 661:35] - node _T_4291 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4292 = eq(_T_4291, UInt<3>("h04")) @[ifu_mem_ctl.scala 661:128] - node _T_4293 = and(_T_4292, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[67] <= _T_4290 @[ifu_mem_ctl.scala 660:35] + node _T_4291 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4292 = eq(_T_4291, UInt<3>("h04")) @[ifu_mem_ctl.scala 660:128] + node _T_4293 = and(_T_4292, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4294 : UInt, rvclkhdr_78.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4293 : @[Reg.scala 28:19] _T_4294 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[68] <= _T_4294 @[ifu_mem_ctl.scala 661:35] - node _T_4295 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4296 = eq(_T_4295, UInt<3>("h05")) @[ifu_mem_ctl.scala 661:128] - node _T_4297 = and(_T_4296, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[68] <= _T_4294 @[ifu_mem_ctl.scala 660:35] + node _T_4295 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4296 = eq(_T_4295, UInt<3>("h05")) @[ifu_mem_ctl.scala 660:128] + node _T_4297 = and(_T_4296, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4298 : UInt, rvclkhdr_78.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4297 : @[Reg.scala 28:19] _T_4298 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[69] <= _T_4298 @[ifu_mem_ctl.scala 661:35] - node _T_4299 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4300 = eq(_T_4299, UInt<3>("h06")) @[ifu_mem_ctl.scala 661:128] - node _T_4301 = and(_T_4300, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[69] <= _T_4298 @[ifu_mem_ctl.scala 660:35] + node _T_4299 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4300 = eq(_T_4299, UInt<3>("h06")) @[ifu_mem_ctl.scala 660:128] + node _T_4301 = and(_T_4300, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4302 : UInt, rvclkhdr_78.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4301 : @[Reg.scala 28:19] _T_4302 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[70] <= _T_4302 @[ifu_mem_ctl.scala 661:35] - node _T_4303 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4304 = eq(_T_4303, UInt<3>("h07")) @[ifu_mem_ctl.scala 661:128] - node _T_4305 = and(_T_4304, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[70] <= _T_4302 @[ifu_mem_ctl.scala 660:35] + node _T_4303 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4304 = eq(_T_4303, UInt<3>("h07")) @[ifu_mem_ctl.scala 660:128] + node _T_4305 = and(_T_4304, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4306 : UInt, rvclkhdr_78.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4305 : @[Reg.scala 28:19] _T_4306 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[71] <= _T_4306 @[ifu_mem_ctl.scala 661:35] - node _T_4307 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4308 = eq(_T_4307, UInt<1>("h00")) @[ifu_mem_ctl.scala 661:128] - node _T_4309 = and(_T_4308, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[71] <= _T_4306 @[ifu_mem_ctl.scala 660:35] + node _T_4307 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4308 = eq(_T_4307, UInt<1>("h00")) @[ifu_mem_ctl.scala 660:128] + node _T_4309 = and(_T_4308, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4310 : UInt, rvclkhdr_79.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4309 : @[Reg.scala 28:19] _T_4310 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[72] <= _T_4310 @[ifu_mem_ctl.scala 661:35] - node _T_4311 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4312 = eq(_T_4311, UInt<1>("h01")) @[ifu_mem_ctl.scala 661:128] - node _T_4313 = and(_T_4312, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[72] <= _T_4310 @[ifu_mem_ctl.scala 660:35] + node _T_4311 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4312 = eq(_T_4311, UInt<1>("h01")) @[ifu_mem_ctl.scala 660:128] + node _T_4313 = and(_T_4312, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4314 : UInt, rvclkhdr_79.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4313 : @[Reg.scala 28:19] _T_4314 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[73] <= _T_4314 @[ifu_mem_ctl.scala 661:35] - node _T_4315 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4316 = eq(_T_4315, UInt<2>("h02")) @[ifu_mem_ctl.scala 661:128] - node _T_4317 = and(_T_4316, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[73] <= _T_4314 @[ifu_mem_ctl.scala 660:35] + node _T_4315 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4316 = eq(_T_4315, UInt<2>("h02")) @[ifu_mem_ctl.scala 660:128] + node _T_4317 = and(_T_4316, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4318 : UInt, rvclkhdr_79.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4317 : @[Reg.scala 28:19] _T_4318 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[74] <= _T_4318 @[ifu_mem_ctl.scala 661:35] - node _T_4319 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4320 = eq(_T_4319, UInt<2>("h03")) @[ifu_mem_ctl.scala 661:128] - node _T_4321 = and(_T_4320, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[74] <= _T_4318 @[ifu_mem_ctl.scala 660:35] + node _T_4319 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4320 = eq(_T_4319, UInt<2>("h03")) @[ifu_mem_ctl.scala 660:128] + node _T_4321 = and(_T_4320, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4322 : UInt, rvclkhdr_79.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4321 : @[Reg.scala 28:19] _T_4322 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[75] <= _T_4322 @[ifu_mem_ctl.scala 661:35] - node _T_4323 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4324 = eq(_T_4323, UInt<3>("h04")) @[ifu_mem_ctl.scala 661:128] - node _T_4325 = and(_T_4324, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[75] <= _T_4322 @[ifu_mem_ctl.scala 660:35] + node _T_4323 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4324 = eq(_T_4323, UInt<3>("h04")) @[ifu_mem_ctl.scala 660:128] + node _T_4325 = and(_T_4324, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4326 : UInt, rvclkhdr_79.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4325 : @[Reg.scala 28:19] _T_4326 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[76] <= _T_4326 @[ifu_mem_ctl.scala 661:35] - node _T_4327 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4328 = eq(_T_4327, UInt<3>("h05")) @[ifu_mem_ctl.scala 661:128] - node _T_4329 = and(_T_4328, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[76] <= _T_4326 @[ifu_mem_ctl.scala 660:35] + node _T_4327 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4328 = eq(_T_4327, UInt<3>("h05")) @[ifu_mem_ctl.scala 660:128] + node _T_4329 = and(_T_4328, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4330 : UInt, rvclkhdr_79.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4329 : @[Reg.scala 28:19] _T_4330 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[77] <= _T_4330 @[ifu_mem_ctl.scala 661:35] - node _T_4331 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4332 = eq(_T_4331, UInt<3>("h06")) @[ifu_mem_ctl.scala 661:128] - node _T_4333 = and(_T_4332, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[77] <= _T_4330 @[ifu_mem_ctl.scala 660:35] + node _T_4331 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4332 = eq(_T_4331, UInt<3>("h06")) @[ifu_mem_ctl.scala 660:128] + node _T_4333 = and(_T_4332, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4334 : UInt, rvclkhdr_79.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4333 : @[Reg.scala 28:19] _T_4334 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[78] <= _T_4334 @[ifu_mem_ctl.scala 661:35] - node _T_4335 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4336 = eq(_T_4335, UInt<3>("h07")) @[ifu_mem_ctl.scala 661:128] - node _T_4337 = and(_T_4336, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[78] <= _T_4334 @[ifu_mem_ctl.scala 660:35] + node _T_4335 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4336 = eq(_T_4335, UInt<3>("h07")) @[ifu_mem_ctl.scala 660:128] + node _T_4337 = and(_T_4336, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4338 : UInt, rvclkhdr_79.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4337 : @[Reg.scala 28:19] _T_4338 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[79] <= _T_4338 @[ifu_mem_ctl.scala 661:35] - node _T_4339 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4340 = eq(_T_4339, UInt<1>("h00")) @[ifu_mem_ctl.scala 661:128] - node _T_4341 = and(_T_4340, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[79] <= _T_4338 @[ifu_mem_ctl.scala 660:35] + node _T_4339 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4340 = eq(_T_4339, UInt<1>("h00")) @[ifu_mem_ctl.scala 660:128] + node _T_4341 = and(_T_4340, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4342 : UInt, rvclkhdr_80.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4341 : @[Reg.scala 28:19] _T_4342 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[80] <= _T_4342 @[ifu_mem_ctl.scala 661:35] - node _T_4343 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4344 = eq(_T_4343, UInt<1>("h01")) @[ifu_mem_ctl.scala 661:128] - node _T_4345 = and(_T_4344, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[80] <= _T_4342 @[ifu_mem_ctl.scala 660:35] + node _T_4343 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4344 = eq(_T_4343, UInt<1>("h01")) @[ifu_mem_ctl.scala 660:128] + node _T_4345 = and(_T_4344, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4346 : UInt, rvclkhdr_80.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4345 : @[Reg.scala 28:19] _T_4346 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[81] <= _T_4346 @[ifu_mem_ctl.scala 661:35] - node _T_4347 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4348 = eq(_T_4347, UInt<2>("h02")) @[ifu_mem_ctl.scala 661:128] - node _T_4349 = and(_T_4348, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[81] <= _T_4346 @[ifu_mem_ctl.scala 660:35] + node _T_4347 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4348 = eq(_T_4347, UInt<2>("h02")) @[ifu_mem_ctl.scala 660:128] + node _T_4349 = and(_T_4348, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4350 : UInt, rvclkhdr_80.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4349 : @[Reg.scala 28:19] _T_4350 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[82] <= _T_4350 @[ifu_mem_ctl.scala 661:35] - node _T_4351 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4352 = eq(_T_4351, UInt<2>("h03")) @[ifu_mem_ctl.scala 661:128] - node _T_4353 = and(_T_4352, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[82] <= _T_4350 @[ifu_mem_ctl.scala 660:35] + node _T_4351 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4352 = eq(_T_4351, UInt<2>("h03")) @[ifu_mem_ctl.scala 660:128] + node _T_4353 = and(_T_4352, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4354 : UInt, rvclkhdr_80.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4353 : @[Reg.scala 28:19] _T_4354 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[83] <= _T_4354 @[ifu_mem_ctl.scala 661:35] - node _T_4355 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4356 = eq(_T_4355, UInt<3>("h04")) @[ifu_mem_ctl.scala 661:128] - node _T_4357 = and(_T_4356, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[83] <= _T_4354 @[ifu_mem_ctl.scala 660:35] + node _T_4355 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4356 = eq(_T_4355, UInt<3>("h04")) @[ifu_mem_ctl.scala 660:128] + node _T_4357 = and(_T_4356, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4358 : UInt, rvclkhdr_80.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4357 : @[Reg.scala 28:19] _T_4358 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[84] <= _T_4358 @[ifu_mem_ctl.scala 661:35] - node _T_4359 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4360 = eq(_T_4359, UInt<3>("h05")) @[ifu_mem_ctl.scala 661:128] - node _T_4361 = and(_T_4360, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[84] <= _T_4358 @[ifu_mem_ctl.scala 660:35] + node _T_4359 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4360 = eq(_T_4359, UInt<3>("h05")) @[ifu_mem_ctl.scala 660:128] + node _T_4361 = and(_T_4360, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4362 : UInt, rvclkhdr_80.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4361 : @[Reg.scala 28:19] _T_4362 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[85] <= _T_4362 @[ifu_mem_ctl.scala 661:35] - node _T_4363 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4364 = eq(_T_4363, UInt<3>("h06")) @[ifu_mem_ctl.scala 661:128] - node _T_4365 = and(_T_4364, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[85] <= _T_4362 @[ifu_mem_ctl.scala 660:35] + node _T_4363 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4364 = eq(_T_4363, UInt<3>("h06")) @[ifu_mem_ctl.scala 660:128] + node _T_4365 = and(_T_4364, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4366 : UInt, rvclkhdr_80.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4365 : @[Reg.scala 28:19] _T_4366 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[86] <= _T_4366 @[ifu_mem_ctl.scala 661:35] - node _T_4367 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4368 = eq(_T_4367, UInt<3>("h07")) @[ifu_mem_ctl.scala 661:128] - node _T_4369 = and(_T_4368, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[86] <= _T_4366 @[ifu_mem_ctl.scala 660:35] + node _T_4367 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4368 = eq(_T_4367, UInt<3>("h07")) @[ifu_mem_ctl.scala 660:128] + node _T_4369 = and(_T_4368, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4370 : UInt, rvclkhdr_80.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4369 : @[Reg.scala 28:19] _T_4370 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[87] <= _T_4370 @[ifu_mem_ctl.scala 661:35] - node _T_4371 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4372 = eq(_T_4371, UInt<1>("h00")) @[ifu_mem_ctl.scala 661:128] - node _T_4373 = and(_T_4372, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[87] <= _T_4370 @[ifu_mem_ctl.scala 660:35] + node _T_4371 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4372 = eq(_T_4371, UInt<1>("h00")) @[ifu_mem_ctl.scala 660:128] + node _T_4373 = and(_T_4372, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4374 : UInt, rvclkhdr_81.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4373 : @[Reg.scala 28:19] _T_4374 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[88] <= _T_4374 @[ifu_mem_ctl.scala 661:35] - node _T_4375 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4376 = eq(_T_4375, UInt<1>("h01")) @[ifu_mem_ctl.scala 661:128] - node _T_4377 = and(_T_4376, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[88] <= _T_4374 @[ifu_mem_ctl.scala 660:35] + node _T_4375 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4376 = eq(_T_4375, UInt<1>("h01")) @[ifu_mem_ctl.scala 660:128] + node _T_4377 = and(_T_4376, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4378 : UInt, rvclkhdr_81.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4377 : @[Reg.scala 28:19] _T_4378 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[89] <= _T_4378 @[ifu_mem_ctl.scala 661:35] - node _T_4379 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4380 = eq(_T_4379, UInt<2>("h02")) @[ifu_mem_ctl.scala 661:128] - node _T_4381 = and(_T_4380, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[89] <= _T_4378 @[ifu_mem_ctl.scala 660:35] + node _T_4379 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4380 = eq(_T_4379, UInt<2>("h02")) @[ifu_mem_ctl.scala 660:128] + node _T_4381 = and(_T_4380, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4382 : UInt, rvclkhdr_81.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4381 : @[Reg.scala 28:19] _T_4382 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[90] <= _T_4382 @[ifu_mem_ctl.scala 661:35] - node _T_4383 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4384 = eq(_T_4383, UInt<2>("h03")) @[ifu_mem_ctl.scala 661:128] - node _T_4385 = and(_T_4384, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[90] <= _T_4382 @[ifu_mem_ctl.scala 660:35] + node _T_4383 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4384 = eq(_T_4383, UInt<2>("h03")) @[ifu_mem_ctl.scala 660:128] + node _T_4385 = and(_T_4384, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4386 : UInt, rvclkhdr_81.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4385 : @[Reg.scala 28:19] _T_4386 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[91] <= _T_4386 @[ifu_mem_ctl.scala 661:35] - node _T_4387 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4388 = eq(_T_4387, UInt<3>("h04")) @[ifu_mem_ctl.scala 661:128] - node _T_4389 = and(_T_4388, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[91] <= _T_4386 @[ifu_mem_ctl.scala 660:35] + node _T_4387 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4388 = eq(_T_4387, UInt<3>("h04")) @[ifu_mem_ctl.scala 660:128] + node _T_4389 = and(_T_4388, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4390 : UInt, rvclkhdr_81.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4389 : @[Reg.scala 28:19] _T_4390 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[92] <= _T_4390 @[ifu_mem_ctl.scala 661:35] - node _T_4391 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4392 = eq(_T_4391, UInt<3>("h05")) @[ifu_mem_ctl.scala 661:128] - node _T_4393 = and(_T_4392, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[92] <= _T_4390 @[ifu_mem_ctl.scala 660:35] + node _T_4391 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4392 = eq(_T_4391, UInt<3>("h05")) @[ifu_mem_ctl.scala 660:128] + node _T_4393 = and(_T_4392, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4394 : UInt, rvclkhdr_81.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4393 : @[Reg.scala 28:19] _T_4394 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[93] <= _T_4394 @[ifu_mem_ctl.scala 661:35] - node _T_4395 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4396 = eq(_T_4395, UInt<3>("h06")) @[ifu_mem_ctl.scala 661:128] - node _T_4397 = and(_T_4396, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[93] <= _T_4394 @[ifu_mem_ctl.scala 660:35] + node _T_4395 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4396 = eq(_T_4395, UInt<3>("h06")) @[ifu_mem_ctl.scala 660:128] + node _T_4397 = and(_T_4396, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4398 : UInt, rvclkhdr_81.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4397 : @[Reg.scala 28:19] _T_4398 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[94] <= _T_4398 @[ifu_mem_ctl.scala 661:35] - node _T_4399 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4400 = eq(_T_4399, UInt<3>("h07")) @[ifu_mem_ctl.scala 661:128] - node _T_4401 = and(_T_4400, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[94] <= _T_4398 @[ifu_mem_ctl.scala 660:35] + node _T_4399 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4400 = eq(_T_4399, UInt<3>("h07")) @[ifu_mem_ctl.scala 660:128] + node _T_4401 = and(_T_4400, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4402 : UInt, rvclkhdr_81.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4401 : @[Reg.scala 28:19] _T_4402 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[95] <= _T_4402 @[ifu_mem_ctl.scala 661:35] - node _T_4403 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4404 = eq(_T_4403, UInt<1>("h00")) @[ifu_mem_ctl.scala 661:128] - node _T_4405 = and(_T_4404, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[95] <= _T_4402 @[ifu_mem_ctl.scala 660:35] + node _T_4403 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4404 = eq(_T_4403, UInt<1>("h00")) @[ifu_mem_ctl.scala 660:128] + node _T_4405 = and(_T_4404, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4406 : UInt, rvclkhdr_82.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4405 : @[Reg.scala 28:19] _T_4406 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[96] <= _T_4406 @[ifu_mem_ctl.scala 661:35] - node _T_4407 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4408 = eq(_T_4407, UInt<1>("h01")) @[ifu_mem_ctl.scala 661:128] - node _T_4409 = and(_T_4408, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[96] <= _T_4406 @[ifu_mem_ctl.scala 660:35] + node _T_4407 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4408 = eq(_T_4407, UInt<1>("h01")) @[ifu_mem_ctl.scala 660:128] + node _T_4409 = and(_T_4408, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4410 : UInt, rvclkhdr_82.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4409 : @[Reg.scala 28:19] _T_4410 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[97] <= _T_4410 @[ifu_mem_ctl.scala 661:35] - node _T_4411 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4412 = eq(_T_4411, UInt<2>("h02")) @[ifu_mem_ctl.scala 661:128] - node _T_4413 = and(_T_4412, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[97] <= _T_4410 @[ifu_mem_ctl.scala 660:35] + node _T_4411 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4412 = eq(_T_4411, UInt<2>("h02")) @[ifu_mem_ctl.scala 660:128] + node _T_4413 = and(_T_4412, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4414 : UInt, rvclkhdr_82.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4413 : @[Reg.scala 28:19] _T_4414 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[98] <= _T_4414 @[ifu_mem_ctl.scala 661:35] - node _T_4415 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4416 = eq(_T_4415, UInt<2>("h03")) @[ifu_mem_ctl.scala 661:128] - node _T_4417 = and(_T_4416, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[98] <= _T_4414 @[ifu_mem_ctl.scala 660:35] + node _T_4415 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4416 = eq(_T_4415, UInt<2>("h03")) @[ifu_mem_ctl.scala 660:128] + node _T_4417 = and(_T_4416, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4418 : UInt, rvclkhdr_82.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4417 : @[Reg.scala 28:19] _T_4418 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[99] <= _T_4418 @[ifu_mem_ctl.scala 661:35] - node _T_4419 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4420 = eq(_T_4419, UInt<3>("h04")) @[ifu_mem_ctl.scala 661:128] - node _T_4421 = and(_T_4420, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[99] <= _T_4418 @[ifu_mem_ctl.scala 660:35] + node _T_4419 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4420 = eq(_T_4419, UInt<3>("h04")) @[ifu_mem_ctl.scala 660:128] + node _T_4421 = and(_T_4420, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4422 : UInt, rvclkhdr_82.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4421 : @[Reg.scala 28:19] _T_4422 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[100] <= _T_4422 @[ifu_mem_ctl.scala 661:35] - node _T_4423 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4424 = eq(_T_4423, UInt<3>("h05")) @[ifu_mem_ctl.scala 661:128] - node _T_4425 = and(_T_4424, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[100] <= _T_4422 @[ifu_mem_ctl.scala 660:35] + node _T_4423 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4424 = eq(_T_4423, UInt<3>("h05")) @[ifu_mem_ctl.scala 660:128] + node _T_4425 = and(_T_4424, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4426 : UInt, rvclkhdr_82.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4425 : @[Reg.scala 28:19] _T_4426 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[101] <= _T_4426 @[ifu_mem_ctl.scala 661:35] - node _T_4427 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4428 = eq(_T_4427, UInt<3>("h06")) @[ifu_mem_ctl.scala 661:128] - node _T_4429 = and(_T_4428, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[101] <= _T_4426 @[ifu_mem_ctl.scala 660:35] + node _T_4427 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4428 = eq(_T_4427, UInt<3>("h06")) @[ifu_mem_ctl.scala 660:128] + node _T_4429 = and(_T_4428, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4430 : UInt, rvclkhdr_82.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4429 : @[Reg.scala 28:19] _T_4430 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[102] <= _T_4430 @[ifu_mem_ctl.scala 661:35] - node _T_4431 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4432 = eq(_T_4431, UInt<3>("h07")) @[ifu_mem_ctl.scala 661:128] - node _T_4433 = and(_T_4432, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[102] <= _T_4430 @[ifu_mem_ctl.scala 660:35] + node _T_4431 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4432 = eq(_T_4431, UInt<3>("h07")) @[ifu_mem_ctl.scala 660:128] + node _T_4433 = and(_T_4432, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4434 : UInt, rvclkhdr_82.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4433 : @[Reg.scala 28:19] _T_4434 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[103] <= _T_4434 @[ifu_mem_ctl.scala 661:35] - node _T_4435 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4436 = eq(_T_4435, UInt<1>("h00")) @[ifu_mem_ctl.scala 661:128] - node _T_4437 = and(_T_4436, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[103] <= _T_4434 @[ifu_mem_ctl.scala 660:35] + node _T_4435 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4436 = eq(_T_4435, UInt<1>("h00")) @[ifu_mem_ctl.scala 660:128] + node _T_4437 = and(_T_4436, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4438 : UInt, rvclkhdr_83.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4437 : @[Reg.scala 28:19] _T_4438 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[104] <= _T_4438 @[ifu_mem_ctl.scala 661:35] - node _T_4439 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4440 = eq(_T_4439, UInt<1>("h01")) @[ifu_mem_ctl.scala 661:128] - node _T_4441 = and(_T_4440, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[104] <= _T_4438 @[ifu_mem_ctl.scala 660:35] + node _T_4439 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4440 = eq(_T_4439, UInt<1>("h01")) @[ifu_mem_ctl.scala 660:128] + node _T_4441 = and(_T_4440, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4442 : UInt, rvclkhdr_83.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4441 : @[Reg.scala 28:19] _T_4442 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[105] <= _T_4442 @[ifu_mem_ctl.scala 661:35] - node _T_4443 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4444 = eq(_T_4443, UInt<2>("h02")) @[ifu_mem_ctl.scala 661:128] - node _T_4445 = and(_T_4444, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[105] <= _T_4442 @[ifu_mem_ctl.scala 660:35] + node _T_4443 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4444 = eq(_T_4443, UInt<2>("h02")) @[ifu_mem_ctl.scala 660:128] + node _T_4445 = and(_T_4444, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4446 : UInt, rvclkhdr_83.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4445 : @[Reg.scala 28:19] _T_4446 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[106] <= _T_4446 @[ifu_mem_ctl.scala 661:35] - node _T_4447 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4448 = eq(_T_4447, UInt<2>("h03")) @[ifu_mem_ctl.scala 661:128] - node _T_4449 = and(_T_4448, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[106] <= _T_4446 @[ifu_mem_ctl.scala 660:35] + node _T_4447 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4448 = eq(_T_4447, UInt<2>("h03")) @[ifu_mem_ctl.scala 660:128] + node _T_4449 = and(_T_4448, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4450 : UInt, rvclkhdr_83.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4449 : @[Reg.scala 28:19] _T_4450 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[107] <= _T_4450 @[ifu_mem_ctl.scala 661:35] - node _T_4451 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4452 = eq(_T_4451, UInt<3>("h04")) @[ifu_mem_ctl.scala 661:128] - node _T_4453 = and(_T_4452, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[107] <= _T_4450 @[ifu_mem_ctl.scala 660:35] + node _T_4451 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4452 = eq(_T_4451, UInt<3>("h04")) @[ifu_mem_ctl.scala 660:128] + node _T_4453 = and(_T_4452, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4454 : UInt, rvclkhdr_83.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4453 : @[Reg.scala 28:19] _T_4454 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[108] <= _T_4454 @[ifu_mem_ctl.scala 661:35] - node _T_4455 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4456 = eq(_T_4455, UInt<3>("h05")) @[ifu_mem_ctl.scala 661:128] - node _T_4457 = and(_T_4456, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[108] <= _T_4454 @[ifu_mem_ctl.scala 660:35] + node _T_4455 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4456 = eq(_T_4455, UInt<3>("h05")) @[ifu_mem_ctl.scala 660:128] + node _T_4457 = and(_T_4456, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4458 : UInt, rvclkhdr_83.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4457 : @[Reg.scala 28:19] _T_4458 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[109] <= _T_4458 @[ifu_mem_ctl.scala 661:35] - node _T_4459 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4460 = eq(_T_4459, UInt<3>("h06")) @[ifu_mem_ctl.scala 661:128] - node _T_4461 = and(_T_4460, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[109] <= _T_4458 @[ifu_mem_ctl.scala 660:35] + node _T_4459 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4460 = eq(_T_4459, UInt<3>("h06")) @[ifu_mem_ctl.scala 660:128] + node _T_4461 = and(_T_4460, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4462 : UInt, rvclkhdr_83.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4461 : @[Reg.scala 28:19] _T_4462 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[110] <= _T_4462 @[ifu_mem_ctl.scala 661:35] - node _T_4463 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4464 = eq(_T_4463, UInt<3>("h07")) @[ifu_mem_ctl.scala 661:128] - node _T_4465 = and(_T_4464, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[110] <= _T_4462 @[ifu_mem_ctl.scala 660:35] + node _T_4463 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4464 = eq(_T_4463, UInt<3>("h07")) @[ifu_mem_ctl.scala 660:128] + node _T_4465 = and(_T_4464, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4466 : UInt, rvclkhdr_83.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4465 : @[Reg.scala 28:19] _T_4466 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[111] <= _T_4466 @[ifu_mem_ctl.scala 661:35] - node _T_4467 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4468 = eq(_T_4467, UInt<1>("h00")) @[ifu_mem_ctl.scala 661:128] - node _T_4469 = and(_T_4468, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[111] <= _T_4466 @[ifu_mem_ctl.scala 660:35] + node _T_4467 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4468 = eq(_T_4467, UInt<1>("h00")) @[ifu_mem_ctl.scala 660:128] + node _T_4469 = and(_T_4468, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4470 : UInt, rvclkhdr_84.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4469 : @[Reg.scala 28:19] _T_4470 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[112] <= _T_4470 @[ifu_mem_ctl.scala 661:35] - node _T_4471 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4472 = eq(_T_4471, UInt<1>("h01")) @[ifu_mem_ctl.scala 661:128] - node _T_4473 = and(_T_4472, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[112] <= _T_4470 @[ifu_mem_ctl.scala 660:35] + node _T_4471 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4472 = eq(_T_4471, UInt<1>("h01")) @[ifu_mem_ctl.scala 660:128] + node _T_4473 = and(_T_4472, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4474 : UInt, rvclkhdr_84.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4473 : @[Reg.scala 28:19] _T_4474 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[113] <= _T_4474 @[ifu_mem_ctl.scala 661:35] - node _T_4475 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4476 = eq(_T_4475, UInt<2>("h02")) @[ifu_mem_ctl.scala 661:128] - node _T_4477 = and(_T_4476, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[113] <= _T_4474 @[ifu_mem_ctl.scala 660:35] + node _T_4475 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4476 = eq(_T_4475, UInt<2>("h02")) @[ifu_mem_ctl.scala 660:128] + node _T_4477 = and(_T_4476, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4478 : UInt, rvclkhdr_84.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4477 : @[Reg.scala 28:19] _T_4478 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[114] <= _T_4478 @[ifu_mem_ctl.scala 661:35] - node _T_4479 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4480 = eq(_T_4479, UInt<2>("h03")) @[ifu_mem_ctl.scala 661:128] - node _T_4481 = and(_T_4480, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[114] <= _T_4478 @[ifu_mem_ctl.scala 660:35] + node _T_4479 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4480 = eq(_T_4479, UInt<2>("h03")) @[ifu_mem_ctl.scala 660:128] + node _T_4481 = and(_T_4480, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4482 : UInt, rvclkhdr_84.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4481 : @[Reg.scala 28:19] _T_4482 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[115] <= _T_4482 @[ifu_mem_ctl.scala 661:35] - node _T_4483 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4484 = eq(_T_4483, UInt<3>("h04")) @[ifu_mem_ctl.scala 661:128] - node _T_4485 = and(_T_4484, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[115] <= _T_4482 @[ifu_mem_ctl.scala 660:35] + node _T_4483 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4484 = eq(_T_4483, UInt<3>("h04")) @[ifu_mem_ctl.scala 660:128] + node _T_4485 = and(_T_4484, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4486 : UInt, rvclkhdr_84.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4485 : @[Reg.scala 28:19] _T_4486 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[116] <= _T_4486 @[ifu_mem_ctl.scala 661:35] - node _T_4487 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4488 = eq(_T_4487, UInt<3>("h05")) @[ifu_mem_ctl.scala 661:128] - node _T_4489 = and(_T_4488, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[116] <= _T_4486 @[ifu_mem_ctl.scala 660:35] + node _T_4487 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4488 = eq(_T_4487, UInt<3>("h05")) @[ifu_mem_ctl.scala 660:128] + node _T_4489 = and(_T_4488, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4490 : UInt, rvclkhdr_84.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4489 : @[Reg.scala 28:19] _T_4490 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[117] <= _T_4490 @[ifu_mem_ctl.scala 661:35] - node _T_4491 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4492 = eq(_T_4491, UInt<3>("h06")) @[ifu_mem_ctl.scala 661:128] - node _T_4493 = and(_T_4492, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[117] <= _T_4490 @[ifu_mem_ctl.scala 660:35] + node _T_4491 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4492 = eq(_T_4491, UInt<3>("h06")) @[ifu_mem_ctl.scala 660:128] + node _T_4493 = and(_T_4492, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4494 : UInt, rvclkhdr_84.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4493 : @[Reg.scala 28:19] _T_4494 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[118] <= _T_4494 @[ifu_mem_ctl.scala 661:35] - node _T_4495 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4496 = eq(_T_4495, UInt<3>("h07")) @[ifu_mem_ctl.scala 661:128] - node _T_4497 = and(_T_4496, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[118] <= _T_4494 @[ifu_mem_ctl.scala 660:35] + node _T_4495 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4496 = eq(_T_4495, UInt<3>("h07")) @[ifu_mem_ctl.scala 660:128] + node _T_4497 = and(_T_4496, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4498 : UInt, rvclkhdr_84.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4497 : @[Reg.scala 28:19] _T_4498 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[119] <= _T_4498 @[ifu_mem_ctl.scala 661:35] - node _T_4499 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4500 = eq(_T_4499, UInt<1>("h00")) @[ifu_mem_ctl.scala 661:128] - node _T_4501 = and(_T_4500, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[119] <= _T_4498 @[ifu_mem_ctl.scala 660:35] + node _T_4499 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4500 = eq(_T_4499, UInt<1>("h00")) @[ifu_mem_ctl.scala 660:128] + node _T_4501 = and(_T_4500, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4502 : UInt, rvclkhdr_85.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4501 : @[Reg.scala 28:19] _T_4502 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[120] <= _T_4502 @[ifu_mem_ctl.scala 661:35] - node _T_4503 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4504 = eq(_T_4503, UInt<1>("h01")) @[ifu_mem_ctl.scala 661:128] - node _T_4505 = and(_T_4504, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[120] <= _T_4502 @[ifu_mem_ctl.scala 660:35] + node _T_4503 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4504 = eq(_T_4503, UInt<1>("h01")) @[ifu_mem_ctl.scala 660:128] + node _T_4505 = and(_T_4504, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4506 : UInt, rvclkhdr_85.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4505 : @[Reg.scala 28:19] _T_4506 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[121] <= _T_4506 @[ifu_mem_ctl.scala 661:35] - node _T_4507 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4508 = eq(_T_4507, UInt<2>("h02")) @[ifu_mem_ctl.scala 661:128] - node _T_4509 = and(_T_4508, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[121] <= _T_4506 @[ifu_mem_ctl.scala 660:35] + node _T_4507 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4508 = eq(_T_4507, UInt<2>("h02")) @[ifu_mem_ctl.scala 660:128] + node _T_4509 = and(_T_4508, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4510 : UInt, rvclkhdr_85.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4509 : @[Reg.scala 28:19] _T_4510 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[122] <= _T_4510 @[ifu_mem_ctl.scala 661:35] - node _T_4511 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4512 = eq(_T_4511, UInt<2>("h03")) @[ifu_mem_ctl.scala 661:128] - node _T_4513 = and(_T_4512, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[122] <= _T_4510 @[ifu_mem_ctl.scala 660:35] + node _T_4511 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4512 = eq(_T_4511, UInt<2>("h03")) @[ifu_mem_ctl.scala 660:128] + node _T_4513 = and(_T_4512, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4514 : UInt, rvclkhdr_85.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4513 : @[Reg.scala 28:19] _T_4514 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[123] <= _T_4514 @[ifu_mem_ctl.scala 661:35] - node _T_4515 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4516 = eq(_T_4515, UInt<3>("h04")) @[ifu_mem_ctl.scala 661:128] - node _T_4517 = and(_T_4516, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[123] <= _T_4514 @[ifu_mem_ctl.scala 660:35] + node _T_4515 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4516 = eq(_T_4515, UInt<3>("h04")) @[ifu_mem_ctl.scala 660:128] + node _T_4517 = and(_T_4516, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4518 : UInt, rvclkhdr_85.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4517 : @[Reg.scala 28:19] _T_4518 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[124] <= _T_4518 @[ifu_mem_ctl.scala 661:35] - node _T_4519 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4520 = eq(_T_4519, UInt<3>("h05")) @[ifu_mem_ctl.scala 661:128] - node _T_4521 = and(_T_4520, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[124] <= _T_4518 @[ifu_mem_ctl.scala 660:35] + node _T_4519 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4520 = eq(_T_4519, UInt<3>("h05")) @[ifu_mem_ctl.scala 660:128] + node _T_4521 = and(_T_4520, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4522 : UInt, rvclkhdr_85.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4521 : @[Reg.scala 28:19] _T_4522 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[125] <= _T_4522 @[ifu_mem_ctl.scala 661:35] - node _T_4523 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4524 = eq(_T_4523, UInt<3>("h06")) @[ifu_mem_ctl.scala 661:128] - node _T_4525 = and(_T_4524, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[125] <= _T_4522 @[ifu_mem_ctl.scala 660:35] + node _T_4523 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4524 = eq(_T_4523, UInt<3>("h06")) @[ifu_mem_ctl.scala 660:128] + node _T_4525 = and(_T_4524, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4526 : UInt, rvclkhdr_85.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4525 : @[Reg.scala 28:19] _T_4526 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[126] <= _T_4526 @[ifu_mem_ctl.scala 661:35] - node _T_4527 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 661:123] - node _T_4528 = eq(_T_4527, UInt<3>("h07")) @[ifu_mem_ctl.scala 661:128] - node _T_4529 = and(_T_4528, way_status_wr_en_ff) @[ifu_mem_ctl.scala 661:136] + way_status_out[126] <= _T_4526 @[ifu_mem_ctl.scala 660:35] + node _T_4527 = bits(ifu_status_wr_addr_ff, 2, 0) @[ifu_mem_ctl.scala 660:123] + node _T_4528 = eq(_T_4527, UInt<3>("h07")) @[ifu_mem_ctl.scala 660:128] + node _T_4529 = and(_T_4528, way_status_wr_en_ff) @[ifu_mem_ctl.scala 660:136] reg _T_4530 : UInt, rvclkhdr_85.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4529 : @[Reg.scala 28:19] _T_4530 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[127] <= _T_4530 @[ifu_mem_ctl.scala 661:35] + way_status_out[127] <= _T_4530 @[ifu_mem_ctl.scala 660:35] node _T_4531 = cat(way_status_out[127], way_status_out[126]) @[Cat.scala 29:58] node _T_4532 = cat(_T_4531, way_status_out[125]) @[Cat.scala 29:58] node _T_4533 = cat(_T_4532, way_status_out[124]) @[Cat.scala 29:58] @@ -9446,134 +9446,134 @@ circuit quasar_wrapper : node _T_4669 = cat(_T_4668, way_status_clken_2) @[Cat.scala 29:58] node _T_4670 = cat(_T_4669, way_status_clken_1) @[Cat.scala 29:58] node test_way_status_clken = cat(_T_4670, way_status_clken_0) @[Cat.scala 29:58] - node _T_4671 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 666:80] - node _T_4672 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[ifu_mem_ctl.scala 666:80] - node _T_4673 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[ifu_mem_ctl.scala 666:80] - node _T_4674 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[ifu_mem_ctl.scala 666:80] - node _T_4675 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[ifu_mem_ctl.scala 666:80] - node _T_4676 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[ifu_mem_ctl.scala 666:80] - node _T_4677 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[ifu_mem_ctl.scala 666:80] - node _T_4678 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[ifu_mem_ctl.scala 666:80] - node _T_4679 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[ifu_mem_ctl.scala 666:80] - node _T_4680 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[ifu_mem_ctl.scala 666:80] - node _T_4681 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[ifu_mem_ctl.scala 666:80] - node _T_4682 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[ifu_mem_ctl.scala 666:80] - node _T_4683 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[ifu_mem_ctl.scala 666:80] - node _T_4684 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[ifu_mem_ctl.scala 666:80] - node _T_4685 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[ifu_mem_ctl.scala 666:80] - node _T_4686 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[ifu_mem_ctl.scala 666:80] - node _T_4687 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[ifu_mem_ctl.scala 666:80] - node _T_4688 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[ifu_mem_ctl.scala 666:80] - node _T_4689 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[ifu_mem_ctl.scala 666:80] - node _T_4690 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[ifu_mem_ctl.scala 666:80] - node _T_4691 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[ifu_mem_ctl.scala 666:80] - node _T_4692 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[ifu_mem_ctl.scala 666:80] - node _T_4693 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[ifu_mem_ctl.scala 666:80] - node _T_4694 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[ifu_mem_ctl.scala 666:80] - node _T_4695 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[ifu_mem_ctl.scala 666:80] - node _T_4696 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[ifu_mem_ctl.scala 666:80] - node _T_4697 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[ifu_mem_ctl.scala 666:80] - node _T_4698 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[ifu_mem_ctl.scala 666:80] - node _T_4699 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[ifu_mem_ctl.scala 666:80] - node _T_4700 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[ifu_mem_ctl.scala 666:80] - node _T_4701 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[ifu_mem_ctl.scala 666:80] - node _T_4702 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[ifu_mem_ctl.scala 666:80] - node _T_4703 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[ifu_mem_ctl.scala 666:80] - node _T_4704 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[ifu_mem_ctl.scala 666:80] - node _T_4705 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[ifu_mem_ctl.scala 666:80] - node _T_4706 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[ifu_mem_ctl.scala 666:80] - node _T_4707 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[ifu_mem_ctl.scala 666:80] - node _T_4708 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[ifu_mem_ctl.scala 666:80] - node _T_4709 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[ifu_mem_ctl.scala 666:80] - node _T_4710 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[ifu_mem_ctl.scala 666:80] - node _T_4711 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[ifu_mem_ctl.scala 666:80] - node _T_4712 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[ifu_mem_ctl.scala 666:80] - node _T_4713 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[ifu_mem_ctl.scala 666:80] - node _T_4714 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[ifu_mem_ctl.scala 666:80] - node _T_4715 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[ifu_mem_ctl.scala 666:80] - node _T_4716 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[ifu_mem_ctl.scala 666:80] - node _T_4717 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[ifu_mem_ctl.scala 666:80] - node _T_4718 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[ifu_mem_ctl.scala 666:80] - node _T_4719 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[ifu_mem_ctl.scala 666:80] - node _T_4720 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[ifu_mem_ctl.scala 666:80] - node _T_4721 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[ifu_mem_ctl.scala 666:80] - node _T_4722 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[ifu_mem_ctl.scala 666:80] - node _T_4723 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[ifu_mem_ctl.scala 666:80] - node _T_4724 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[ifu_mem_ctl.scala 666:80] - node _T_4725 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[ifu_mem_ctl.scala 666:80] - node _T_4726 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[ifu_mem_ctl.scala 666:80] - node _T_4727 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[ifu_mem_ctl.scala 666:80] - node _T_4728 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[ifu_mem_ctl.scala 666:80] - node _T_4729 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[ifu_mem_ctl.scala 666:80] - node _T_4730 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[ifu_mem_ctl.scala 666:80] - node _T_4731 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[ifu_mem_ctl.scala 666:80] - node _T_4732 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[ifu_mem_ctl.scala 666:80] - node _T_4733 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[ifu_mem_ctl.scala 666:80] - node _T_4734 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[ifu_mem_ctl.scala 666:80] - node _T_4735 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[ifu_mem_ctl.scala 666:80] - node _T_4736 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[ifu_mem_ctl.scala 666:80] - node _T_4737 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[ifu_mem_ctl.scala 666:80] - node _T_4738 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[ifu_mem_ctl.scala 666:80] - node _T_4739 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[ifu_mem_ctl.scala 666:80] - node _T_4740 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[ifu_mem_ctl.scala 666:80] - node _T_4741 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[ifu_mem_ctl.scala 666:80] - node _T_4742 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[ifu_mem_ctl.scala 666:80] - node _T_4743 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[ifu_mem_ctl.scala 666:80] - node _T_4744 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[ifu_mem_ctl.scala 666:80] - node _T_4745 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[ifu_mem_ctl.scala 666:80] - node _T_4746 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[ifu_mem_ctl.scala 666:80] - node _T_4747 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[ifu_mem_ctl.scala 666:80] - node _T_4748 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[ifu_mem_ctl.scala 666:80] - node _T_4749 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[ifu_mem_ctl.scala 666:80] - node _T_4750 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[ifu_mem_ctl.scala 666:80] - node _T_4751 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[ifu_mem_ctl.scala 666:80] - node _T_4752 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[ifu_mem_ctl.scala 666:80] - node _T_4753 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[ifu_mem_ctl.scala 666:80] - node _T_4754 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[ifu_mem_ctl.scala 666:80] - node _T_4755 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[ifu_mem_ctl.scala 666:80] - node _T_4756 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[ifu_mem_ctl.scala 666:80] - node _T_4757 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[ifu_mem_ctl.scala 666:80] - node _T_4758 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[ifu_mem_ctl.scala 666:80] - node _T_4759 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[ifu_mem_ctl.scala 666:80] - node _T_4760 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[ifu_mem_ctl.scala 666:80] - node _T_4761 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[ifu_mem_ctl.scala 666:80] - node _T_4762 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[ifu_mem_ctl.scala 666:80] - node _T_4763 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[ifu_mem_ctl.scala 666:80] - node _T_4764 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[ifu_mem_ctl.scala 666:80] - node _T_4765 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[ifu_mem_ctl.scala 666:80] - node _T_4766 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[ifu_mem_ctl.scala 666:80] - node _T_4767 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[ifu_mem_ctl.scala 666:80] - node _T_4768 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[ifu_mem_ctl.scala 666:80] - node _T_4769 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[ifu_mem_ctl.scala 666:80] - node _T_4770 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[ifu_mem_ctl.scala 666:80] - node _T_4771 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[ifu_mem_ctl.scala 666:80] - node _T_4772 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[ifu_mem_ctl.scala 666:80] - node _T_4773 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[ifu_mem_ctl.scala 666:80] - node _T_4774 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[ifu_mem_ctl.scala 666:80] - node _T_4775 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[ifu_mem_ctl.scala 666:80] - node _T_4776 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[ifu_mem_ctl.scala 666:80] - node _T_4777 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[ifu_mem_ctl.scala 666:80] - node _T_4778 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[ifu_mem_ctl.scala 666:80] - node _T_4779 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[ifu_mem_ctl.scala 666:80] - node _T_4780 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[ifu_mem_ctl.scala 666:80] - node _T_4781 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[ifu_mem_ctl.scala 666:80] - node _T_4782 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[ifu_mem_ctl.scala 666:80] - node _T_4783 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[ifu_mem_ctl.scala 666:80] - node _T_4784 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[ifu_mem_ctl.scala 666:80] - node _T_4785 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[ifu_mem_ctl.scala 666:80] - node _T_4786 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[ifu_mem_ctl.scala 666:80] - node _T_4787 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[ifu_mem_ctl.scala 666:80] - node _T_4788 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[ifu_mem_ctl.scala 666:80] - node _T_4789 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[ifu_mem_ctl.scala 666:80] - node _T_4790 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[ifu_mem_ctl.scala 666:80] - node _T_4791 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[ifu_mem_ctl.scala 666:80] - node _T_4792 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[ifu_mem_ctl.scala 666:80] - node _T_4793 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[ifu_mem_ctl.scala 666:80] - node _T_4794 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[ifu_mem_ctl.scala 666:80] - node _T_4795 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[ifu_mem_ctl.scala 666:80] - node _T_4796 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[ifu_mem_ctl.scala 666:80] - node _T_4797 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[ifu_mem_ctl.scala 666:80] - node _T_4798 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[ifu_mem_ctl.scala 666:80] + node _T_4671 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 665:80] + node _T_4672 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[ifu_mem_ctl.scala 665:80] + node _T_4673 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[ifu_mem_ctl.scala 665:80] + node _T_4674 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[ifu_mem_ctl.scala 665:80] + node _T_4675 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[ifu_mem_ctl.scala 665:80] + node _T_4676 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[ifu_mem_ctl.scala 665:80] + node _T_4677 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[ifu_mem_ctl.scala 665:80] + node _T_4678 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[ifu_mem_ctl.scala 665:80] + node _T_4679 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[ifu_mem_ctl.scala 665:80] + node _T_4680 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[ifu_mem_ctl.scala 665:80] + node _T_4681 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[ifu_mem_ctl.scala 665:80] + node _T_4682 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[ifu_mem_ctl.scala 665:80] + node _T_4683 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[ifu_mem_ctl.scala 665:80] + node _T_4684 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[ifu_mem_ctl.scala 665:80] + node _T_4685 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[ifu_mem_ctl.scala 665:80] + node _T_4686 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[ifu_mem_ctl.scala 665:80] + node _T_4687 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[ifu_mem_ctl.scala 665:80] + node _T_4688 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[ifu_mem_ctl.scala 665:80] + node _T_4689 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[ifu_mem_ctl.scala 665:80] + node _T_4690 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[ifu_mem_ctl.scala 665:80] + node _T_4691 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[ifu_mem_ctl.scala 665:80] + node _T_4692 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[ifu_mem_ctl.scala 665:80] + node _T_4693 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[ifu_mem_ctl.scala 665:80] + node _T_4694 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[ifu_mem_ctl.scala 665:80] + node _T_4695 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[ifu_mem_ctl.scala 665:80] + node _T_4696 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[ifu_mem_ctl.scala 665:80] + node _T_4697 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[ifu_mem_ctl.scala 665:80] + node _T_4698 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[ifu_mem_ctl.scala 665:80] + node _T_4699 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[ifu_mem_ctl.scala 665:80] + node _T_4700 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[ifu_mem_ctl.scala 665:80] + node _T_4701 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[ifu_mem_ctl.scala 665:80] + node _T_4702 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[ifu_mem_ctl.scala 665:80] + node _T_4703 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[ifu_mem_ctl.scala 665:80] + node _T_4704 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[ifu_mem_ctl.scala 665:80] + node _T_4705 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[ifu_mem_ctl.scala 665:80] + node _T_4706 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[ifu_mem_ctl.scala 665:80] + node _T_4707 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[ifu_mem_ctl.scala 665:80] + node _T_4708 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[ifu_mem_ctl.scala 665:80] + node _T_4709 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[ifu_mem_ctl.scala 665:80] + node _T_4710 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[ifu_mem_ctl.scala 665:80] + node _T_4711 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[ifu_mem_ctl.scala 665:80] + node _T_4712 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[ifu_mem_ctl.scala 665:80] + node _T_4713 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[ifu_mem_ctl.scala 665:80] + node _T_4714 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[ifu_mem_ctl.scala 665:80] + node _T_4715 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[ifu_mem_ctl.scala 665:80] + node _T_4716 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[ifu_mem_ctl.scala 665:80] + node _T_4717 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[ifu_mem_ctl.scala 665:80] + node _T_4718 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[ifu_mem_ctl.scala 665:80] + node _T_4719 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[ifu_mem_ctl.scala 665:80] + node _T_4720 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[ifu_mem_ctl.scala 665:80] + node _T_4721 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[ifu_mem_ctl.scala 665:80] + node _T_4722 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[ifu_mem_ctl.scala 665:80] + node _T_4723 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[ifu_mem_ctl.scala 665:80] + node _T_4724 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[ifu_mem_ctl.scala 665:80] + node _T_4725 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[ifu_mem_ctl.scala 665:80] + node _T_4726 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[ifu_mem_ctl.scala 665:80] + node _T_4727 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[ifu_mem_ctl.scala 665:80] + node _T_4728 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[ifu_mem_ctl.scala 665:80] + node _T_4729 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[ifu_mem_ctl.scala 665:80] + node _T_4730 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[ifu_mem_ctl.scala 665:80] + node _T_4731 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[ifu_mem_ctl.scala 665:80] + node _T_4732 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[ifu_mem_ctl.scala 665:80] + node _T_4733 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[ifu_mem_ctl.scala 665:80] + node _T_4734 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[ifu_mem_ctl.scala 665:80] + node _T_4735 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[ifu_mem_ctl.scala 665:80] + node _T_4736 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[ifu_mem_ctl.scala 665:80] + node _T_4737 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[ifu_mem_ctl.scala 665:80] + node _T_4738 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[ifu_mem_ctl.scala 665:80] + node _T_4739 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[ifu_mem_ctl.scala 665:80] + node _T_4740 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[ifu_mem_ctl.scala 665:80] + node _T_4741 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[ifu_mem_ctl.scala 665:80] + node _T_4742 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[ifu_mem_ctl.scala 665:80] + node _T_4743 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[ifu_mem_ctl.scala 665:80] + node _T_4744 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[ifu_mem_ctl.scala 665:80] + node _T_4745 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[ifu_mem_ctl.scala 665:80] + node _T_4746 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[ifu_mem_ctl.scala 665:80] + node _T_4747 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[ifu_mem_ctl.scala 665:80] + node _T_4748 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[ifu_mem_ctl.scala 665:80] + node _T_4749 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[ifu_mem_ctl.scala 665:80] + node _T_4750 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[ifu_mem_ctl.scala 665:80] + node _T_4751 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[ifu_mem_ctl.scala 665:80] + node _T_4752 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[ifu_mem_ctl.scala 665:80] + node _T_4753 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[ifu_mem_ctl.scala 665:80] + node _T_4754 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[ifu_mem_ctl.scala 665:80] + node _T_4755 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[ifu_mem_ctl.scala 665:80] + node _T_4756 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[ifu_mem_ctl.scala 665:80] + node _T_4757 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[ifu_mem_ctl.scala 665:80] + node _T_4758 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[ifu_mem_ctl.scala 665:80] + node _T_4759 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[ifu_mem_ctl.scala 665:80] + node _T_4760 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[ifu_mem_ctl.scala 665:80] + node _T_4761 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[ifu_mem_ctl.scala 665:80] + node _T_4762 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[ifu_mem_ctl.scala 665:80] + node _T_4763 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[ifu_mem_ctl.scala 665:80] + node _T_4764 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[ifu_mem_ctl.scala 665:80] + node _T_4765 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[ifu_mem_ctl.scala 665:80] + node _T_4766 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[ifu_mem_ctl.scala 665:80] + node _T_4767 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[ifu_mem_ctl.scala 665:80] + node _T_4768 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[ifu_mem_ctl.scala 665:80] + node _T_4769 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[ifu_mem_ctl.scala 665:80] + node _T_4770 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[ifu_mem_ctl.scala 665:80] + node _T_4771 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[ifu_mem_ctl.scala 665:80] + node _T_4772 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[ifu_mem_ctl.scala 665:80] + node _T_4773 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[ifu_mem_ctl.scala 665:80] + node _T_4774 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[ifu_mem_ctl.scala 665:80] + node _T_4775 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[ifu_mem_ctl.scala 665:80] + node _T_4776 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[ifu_mem_ctl.scala 665:80] + node _T_4777 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[ifu_mem_ctl.scala 665:80] + node _T_4778 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[ifu_mem_ctl.scala 665:80] + node _T_4779 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[ifu_mem_ctl.scala 665:80] + node _T_4780 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[ifu_mem_ctl.scala 665:80] + node _T_4781 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[ifu_mem_ctl.scala 665:80] + node _T_4782 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[ifu_mem_ctl.scala 665:80] + node _T_4783 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[ifu_mem_ctl.scala 665:80] + node _T_4784 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[ifu_mem_ctl.scala 665:80] + node _T_4785 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[ifu_mem_ctl.scala 665:80] + node _T_4786 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[ifu_mem_ctl.scala 665:80] + node _T_4787 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[ifu_mem_ctl.scala 665:80] + node _T_4788 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[ifu_mem_ctl.scala 665:80] + node _T_4789 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[ifu_mem_ctl.scala 665:80] + node _T_4790 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[ifu_mem_ctl.scala 665:80] + node _T_4791 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[ifu_mem_ctl.scala 665:80] + node _T_4792 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[ifu_mem_ctl.scala 665:80] + node _T_4793 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[ifu_mem_ctl.scala 665:80] + node _T_4794 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[ifu_mem_ctl.scala 665:80] + node _T_4795 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[ifu_mem_ctl.scala 665:80] + node _T_4796 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[ifu_mem_ctl.scala 665:80] + node _T_4797 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[ifu_mem_ctl.scala 665:80] + node _T_4798 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[ifu_mem_ctl.scala 665:80] node _T_4799 = mux(_T_4671, way_status_out[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_4800 = mux(_T_4672, way_status_out[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_4801 = mux(_T_4673, way_status_out[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -9831,5915 +9831,5915 @@ circuit quasar_wrapper : node _T_5053 = or(_T_5052, _T_4926) @[Mux.scala 27:72] wire _T_5054 : UInt<1> @[Mux.scala 27:72] _T_5054 <= _T_5053 @[Mux.scala 27:72] - way_status <= _T_5054 @[ifu_mem_ctl.scala 666:14] - node _T_5055 = or(io.ic.debug_rd_en, io.ic.debug_wr_en) @[ifu_mem_ctl.scala 667:61] - node _T_5056 = and(_T_5055, io.ic.debug_tag_array) @[ifu_mem_ctl.scala 667:82] - node _T_5057 = bits(io.ic.debug_addr, 9, 3) @[ifu_mem_ctl.scala 668:23] - node _T_5058 = bits(ifu_ic_rw_int_addr, 11, 5) @[ifu_mem_ctl.scala 668:89] - node ifu_ic_rw_int_addr_w_debug = mux(_T_5056, _T_5057, _T_5058) @[ifu_mem_ctl.scala 667:41] - reg _T_5059 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 670:14] - _T_5059 <= ifu_ic_rw_int_addr_w_debug @[ifu_mem_ctl.scala 670:14] - ifu_ic_rw_int_addr_ff <= _T_5059 @[ifu_mem_ctl.scala 669:27] + way_status <= _T_5054 @[ifu_mem_ctl.scala 665:14] + node _T_5055 = or(io.ic.debug_rd_en, io.ic.debug_wr_en) @[ifu_mem_ctl.scala 666:61] + node _T_5056 = and(_T_5055, io.ic.debug_tag_array) @[ifu_mem_ctl.scala 666:82] + node _T_5057 = bits(io.ic.debug_addr, 9, 3) @[ifu_mem_ctl.scala 667:23] + node _T_5058 = bits(ifu_ic_rw_int_addr, 11, 5) @[ifu_mem_ctl.scala 667:89] + node ifu_ic_rw_int_addr_w_debug = mux(_T_5056, _T_5057, _T_5058) @[ifu_mem_ctl.scala 666:41] + reg _T_5059 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 669:14] + _T_5059 <= ifu_ic_rw_int_addr_w_debug @[ifu_mem_ctl.scala 669:14] + ifu_ic_rw_int_addr_ff <= _T_5059 @[ifu_mem_ctl.scala 668:27] wire ifu_tag_wren : UInt<2> ifu_tag_wren <= UInt<1>("h00") wire ic_debug_tag_wr_en : UInt<2> ic_debug_tag_wr_en <= UInt<1>("h00") - node ifu_tag_wren_w_debug = or(ifu_tag_wren, ic_debug_tag_wr_en) @[ifu_mem_ctl.scala 674:45] - reg ifu_tag_wren_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 676:14] - ifu_tag_wren_ff <= ifu_tag_wren_w_debug @[ifu_mem_ctl.scala 676:14] - node _T_5060 = and(io.ic.debug_wr_en, io.ic.debug_tag_array) @[ifu_mem_ctl.scala 678:50] - node _T_5061 = bits(io.ic.debug_wr_data, 0, 0) @[ifu_mem_ctl.scala 678:94] - node ic_valid_w_debug = mux(_T_5060, _T_5061, ic_valid) @[ifu_mem_ctl.scala 678:31] - reg ic_valid_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 680:14] - ic_valid_ff <= ic_valid_w_debug @[ifu_mem_ctl.scala 680:14] - node _T_5062 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[ifu_mem_ctl.scala 684:35] - node _T_5063 = eq(_T_5062, UInt<1>("h00")) @[ifu_mem_ctl.scala 684:78] - node _T_5064 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 684:104] - node _T_5065 = and(_T_5063, _T_5064) @[ifu_mem_ctl.scala 684:87] - node _T_5066 = bits(perr_ic_index_ff, 6, 5) @[ifu_mem_ctl.scala 685:27] - node _T_5067 = eq(_T_5066, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:70] - node _T_5068 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 685:97] - node _T_5069 = and(_T_5067, _T_5068) @[ifu_mem_ctl.scala 685:79] - node _T_5070 = or(_T_5065, _T_5069) @[ifu_mem_ctl.scala 684:109] - node _T_5071 = or(_T_5070, reset_all_tags) @[ifu_mem_ctl.scala 685:102] - node _T_5072 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[ifu_mem_ctl.scala 684:35] - node _T_5073 = eq(_T_5072, UInt<1>("h00")) @[ifu_mem_ctl.scala 684:78] - node _T_5074 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 684:104] - node _T_5075 = and(_T_5073, _T_5074) @[ifu_mem_ctl.scala 684:87] - node _T_5076 = bits(perr_ic_index_ff, 6, 5) @[ifu_mem_ctl.scala 685:27] - node _T_5077 = eq(_T_5076, UInt<1>("h00")) @[ifu_mem_ctl.scala 685:70] - node _T_5078 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 685:97] - node _T_5079 = and(_T_5077, _T_5078) @[ifu_mem_ctl.scala 685:79] - node _T_5080 = or(_T_5075, _T_5079) @[ifu_mem_ctl.scala 684:109] - node _T_5081 = or(_T_5080, reset_all_tags) @[ifu_mem_ctl.scala 685:102] + node ifu_tag_wren_w_debug = or(ifu_tag_wren, ic_debug_tag_wr_en) @[ifu_mem_ctl.scala 673:45] + reg ifu_tag_wren_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 675:14] + ifu_tag_wren_ff <= ifu_tag_wren_w_debug @[ifu_mem_ctl.scala 675:14] + node _T_5060 = and(io.ic.debug_wr_en, io.ic.debug_tag_array) @[ifu_mem_ctl.scala 677:50] + node _T_5061 = bits(io.ic.debug_wr_data, 0, 0) @[ifu_mem_ctl.scala 677:94] + node ic_valid_w_debug = mux(_T_5060, _T_5061, ic_valid) @[ifu_mem_ctl.scala 677:31] + reg ic_valid_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 679:14] + ic_valid_ff <= ic_valid_w_debug @[ifu_mem_ctl.scala 679:14] + node _T_5062 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[ifu_mem_ctl.scala 683:35] + node _T_5063 = eq(_T_5062, UInt<1>("h00")) @[ifu_mem_ctl.scala 683:78] + node _T_5064 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 683:104] + node _T_5065 = and(_T_5063, _T_5064) @[ifu_mem_ctl.scala 683:87] + node _T_5066 = bits(perr_ic_index_ff, 6, 5) @[ifu_mem_ctl.scala 684:27] + node _T_5067 = eq(_T_5066, UInt<1>("h00")) @[ifu_mem_ctl.scala 684:70] + node _T_5068 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 684:97] + node _T_5069 = and(_T_5067, _T_5068) @[ifu_mem_ctl.scala 684:79] + node _T_5070 = or(_T_5065, _T_5069) @[ifu_mem_ctl.scala 683:109] + node _T_5071 = or(_T_5070, reset_all_tags) @[ifu_mem_ctl.scala 684:102] + node _T_5072 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[ifu_mem_ctl.scala 683:35] + node _T_5073 = eq(_T_5072, UInt<1>("h00")) @[ifu_mem_ctl.scala 683:78] + node _T_5074 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 683:104] + node _T_5075 = and(_T_5073, _T_5074) @[ifu_mem_ctl.scala 683:87] + node _T_5076 = bits(perr_ic_index_ff, 6, 5) @[ifu_mem_ctl.scala 684:27] + node _T_5077 = eq(_T_5076, UInt<1>("h00")) @[ifu_mem_ctl.scala 684:70] + node _T_5078 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 684:97] + node _T_5079 = and(_T_5077, _T_5078) @[ifu_mem_ctl.scala 684:79] + node _T_5080 = or(_T_5075, _T_5079) @[ifu_mem_ctl.scala 683:109] + node _T_5081 = or(_T_5080, reset_all_tags) @[ifu_mem_ctl.scala 684:102] node tag_valid_clken_0 = cat(_T_5081, _T_5071) @[Cat.scala 29:58] - node _T_5082 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[ifu_mem_ctl.scala 684:35] - node _T_5083 = eq(_T_5082, UInt<1>("h01")) @[ifu_mem_ctl.scala 684:78] - node _T_5084 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 684:104] - node _T_5085 = and(_T_5083, _T_5084) @[ifu_mem_ctl.scala 684:87] - node _T_5086 = bits(perr_ic_index_ff, 6, 5) @[ifu_mem_ctl.scala 685:27] - node _T_5087 = eq(_T_5086, UInt<1>("h01")) @[ifu_mem_ctl.scala 685:70] - node _T_5088 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 685:97] - node _T_5089 = and(_T_5087, _T_5088) @[ifu_mem_ctl.scala 685:79] - node _T_5090 = or(_T_5085, _T_5089) @[ifu_mem_ctl.scala 684:109] - node _T_5091 = or(_T_5090, reset_all_tags) @[ifu_mem_ctl.scala 685:102] - node _T_5092 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[ifu_mem_ctl.scala 684:35] - node _T_5093 = eq(_T_5092, UInt<1>("h01")) @[ifu_mem_ctl.scala 684:78] - node _T_5094 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 684:104] - node _T_5095 = and(_T_5093, _T_5094) @[ifu_mem_ctl.scala 684:87] - node _T_5096 = bits(perr_ic_index_ff, 6, 5) @[ifu_mem_ctl.scala 685:27] - node _T_5097 = eq(_T_5096, UInt<1>("h01")) @[ifu_mem_ctl.scala 685:70] - node _T_5098 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 685:97] - node _T_5099 = and(_T_5097, _T_5098) @[ifu_mem_ctl.scala 685:79] - node _T_5100 = or(_T_5095, _T_5099) @[ifu_mem_ctl.scala 684:109] - node _T_5101 = or(_T_5100, reset_all_tags) @[ifu_mem_ctl.scala 685:102] + node _T_5082 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[ifu_mem_ctl.scala 683:35] + node _T_5083 = eq(_T_5082, UInt<1>("h01")) @[ifu_mem_ctl.scala 683:78] + node _T_5084 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 683:104] + node _T_5085 = and(_T_5083, _T_5084) @[ifu_mem_ctl.scala 683:87] + node _T_5086 = bits(perr_ic_index_ff, 6, 5) @[ifu_mem_ctl.scala 684:27] + node _T_5087 = eq(_T_5086, UInt<1>("h01")) @[ifu_mem_ctl.scala 684:70] + node _T_5088 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 684:97] + node _T_5089 = and(_T_5087, _T_5088) @[ifu_mem_ctl.scala 684:79] + node _T_5090 = or(_T_5085, _T_5089) @[ifu_mem_ctl.scala 683:109] + node _T_5091 = or(_T_5090, reset_all_tags) @[ifu_mem_ctl.scala 684:102] + node _T_5092 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[ifu_mem_ctl.scala 683:35] + node _T_5093 = eq(_T_5092, UInt<1>("h01")) @[ifu_mem_ctl.scala 683:78] + node _T_5094 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 683:104] + node _T_5095 = and(_T_5093, _T_5094) @[ifu_mem_ctl.scala 683:87] + node _T_5096 = bits(perr_ic_index_ff, 6, 5) @[ifu_mem_ctl.scala 684:27] + node _T_5097 = eq(_T_5096, UInt<1>("h01")) @[ifu_mem_ctl.scala 684:70] + node _T_5098 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 684:97] + node _T_5099 = and(_T_5097, _T_5098) @[ifu_mem_ctl.scala 684:79] + node _T_5100 = or(_T_5095, _T_5099) @[ifu_mem_ctl.scala 683:109] + node _T_5101 = or(_T_5100, reset_all_tags) @[ifu_mem_ctl.scala 684:102] node tag_valid_clken_1 = cat(_T_5101, _T_5091) @[Cat.scala 29:58] - node _T_5102 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[ifu_mem_ctl.scala 684:35] - node _T_5103 = eq(_T_5102, UInt<2>("h02")) @[ifu_mem_ctl.scala 684:78] - node _T_5104 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 684:104] - node _T_5105 = and(_T_5103, _T_5104) @[ifu_mem_ctl.scala 684:87] - node _T_5106 = bits(perr_ic_index_ff, 6, 5) @[ifu_mem_ctl.scala 685:27] - node _T_5107 = eq(_T_5106, UInt<2>("h02")) @[ifu_mem_ctl.scala 685:70] - node _T_5108 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 685:97] - node _T_5109 = and(_T_5107, _T_5108) @[ifu_mem_ctl.scala 685:79] - node _T_5110 = or(_T_5105, _T_5109) @[ifu_mem_ctl.scala 684:109] - node _T_5111 = or(_T_5110, reset_all_tags) @[ifu_mem_ctl.scala 685:102] - node _T_5112 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[ifu_mem_ctl.scala 684:35] - node _T_5113 = eq(_T_5112, UInt<2>("h02")) @[ifu_mem_ctl.scala 684:78] - node _T_5114 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 684:104] - node _T_5115 = and(_T_5113, _T_5114) @[ifu_mem_ctl.scala 684:87] - node _T_5116 = bits(perr_ic_index_ff, 6, 5) @[ifu_mem_ctl.scala 685:27] - node _T_5117 = eq(_T_5116, UInt<2>("h02")) @[ifu_mem_ctl.scala 685:70] - node _T_5118 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 685:97] - node _T_5119 = and(_T_5117, _T_5118) @[ifu_mem_ctl.scala 685:79] - node _T_5120 = or(_T_5115, _T_5119) @[ifu_mem_ctl.scala 684:109] - node _T_5121 = or(_T_5120, reset_all_tags) @[ifu_mem_ctl.scala 685:102] + node _T_5102 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[ifu_mem_ctl.scala 683:35] + node _T_5103 = eq(_T_5102, UInt<2>("h02")) @[ifu_mem_ctl.scala 683:78] + node _T_5104 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 683:104] + node _T_5105 = and(_T_5103, _T_5104) @[ifu_mem_ctl.scala 683:87] + node _T_5106 = bits(perr_ic_index_ff, 6, 5) @[ifu_mem_ctl.scala 684:27] + node _T_5107 = eq(_T_5106, UInt<2>("h02")) @[ifu_mem_ctl.scala 684:70] + node _T_5108 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 684:97] + node _T_5109 = and(_T_5107, _T_5108) @[ifu_mem_ctl.scala 684:79] + node _T_5110 = or(_T_5105, _T_5109) @[ifu_mem_ctl.scala 683:109] + node _T_5111 = or(_T_5110, reset_all_tags) @[ifu_mem_ctl.scala 684:102] + node _T_5112 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[ifu_mem_ctl.scala 683:35] + node _T_5113 = eq(_T_5112, UInt<2>("h02")) @[ifu_mem_ctl.scala 683:78] + node _T_5114 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 683:104] + node _T_5115 = and(_T_5113, _T_5114) @[ifu_mem_ctl.scala 683:87] + node _T_5116 = bits(perr_ic_index_ff, 6, 5) @[ifu_mem_ctl.scala 684:27] + node _T_5117 = eq(_T_5116, UInt<2>("h02")) @[ifu_mem_ctl.scala 684:70] + node _T_5118 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 684:97] + node _T_5119 = and(_T_5117, _T_5118) @[ifu_mem_ctl.scala 684:79] + node _T_5120 = or(_T_5115, _T_5119) @[ifu_mem_ctl.scala 683:109] + node _T_5121 = or(_T_5120, reset_all_tags) @[ifu_mem_ctl.scala 684:102] node tag_valid_clken_2 = cat(_T_5121, _T_5111) @[Cat.scala 29:58] - node _T_5122 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[ifu_mem_ctl.scala 684:35] - node _T_5123 = eq(_T_5122, UInt<2>("h03")) @[ifu_mem_ctl.scala 684:78] - node _T_5124 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 684:104] - node _T_5125 = and(_T_5123, _T_5124) @[ifu_mem_ctl.scala 684:87] - node _T_5126 = bits(perr_ic_index_ff, 6, 5) @[ifu_mem_ctl.scala 685:27] - node _T_5127 = eq(_T_5126, UInt<2>("h03")) @[ifu_mem_ctl.scala 685:70] - node _T_5128 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 685:97] - node _T_5129 = and(_T_5127, _T_5128) @[ifu_mem_ctl.scala 685:79] - node _T_5130 = or(_T_5125, _T_5129) @[ifu_mem_ctl.scala 684:109] - node _T_5131 = or(_T_5130, reset_all_tags) @[ifu_mem_ctl.scala 685:102] - node _T_5132 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[ifu_mem_ctl.scala 684:35] - node _T_5133 = eq(_T_5132, UInt<2>("h03")) @[ifu_mem_ctl.scala 684:78] - node _T_5134 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 684:104] - node _T_5135 = and(_T_5133, _T_5134) @[ifu_mem_ctl.scala 684:87] - node _T_5136 = bits(perr_ic_index_ff, 6, 5) @[ifu_mem_ctl.scala 685:27] - node _T_5137 = eq(_T_5136, UInt<2>("h03")) @[ifu_mem_ctl.scala 685:70] - node _T_5138 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 685:97] - node _T_5139 = and(_T_5137, _T_5138) @[ifu_mem_ctl.scala 685:79] - node _T_5140 = or(_T_5135, _T_5139) @[ifu_mem_ctl.scala 684:109] - node _T_5141 = or(_T_5140, reset_all_tags) @[ifu_mem_ctl.scala 685:102] + node _T_5122 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[ifu_mem_ctl.scala 683:35] + node _T_5123 = eq(_T_5122, UInt<2>("h03")) @[ifu_mem_ctl.scala 683:78] + node _T_5124 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 683:104] + node _T_5125 = and(_T_5123, _T_5124) @[ifu_mem_ctl.scala 683:87] + node _T_5126 = bits(perr_ic_index_ff, 6, 5) @[ifu_mem_ctl.scala 684:27] + node _T_5127 = eq(_T_5126, UInt<2>("h03")) @[ifu_mem_ctl.scala 684:70] + node _T_5128 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 684:97] + node _T_5129 = and(_T_5127, _T_5128) @[ifu_mem_ctl.scala 684:79] + node _T_5130 = or(_T_5125, _T_5129) @[ifu_mem_ctl.scala 683:109] + node _T_5131 = or(_T_5130, reset_all_tags) @[ifu_mem_ctl.scala 684:102] + node _T_5132 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[ifu_mem_ctl.scala 683:35] + node _T_5133 = eq(_T_5132, UInt<2>("h03")) @[ifu_mem_ctl.scala 683:78] + node _T_5134 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 683:104] + node _T_5135 = and(_T_5133, _T_5134) @[ifu_mem_ctl.scala 683:87] + node _T_5136 = bits(perr_ic_index_ff, 6, 5) @[ifu_mem_ctl.scala 684:27] + node _T_5137 = eq(_T_5136, UInt<2>("h03")) @[ifu_mem_ctl.scala 684:70] + node _T_5138 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 684:97] + node _T_5139 = and(_T_5137, _T_5138) @[ifu_mem_ctl.scala 684:79] + node _T_5140 = or(_T_5135, _T_5139) @[ifu_mem_ctl.scala 683:109] + node _T_5141 = or(_T_5140, reset_all_tags) @[ifu_mem_ctl.scala 684:102] node tag_valid_clken_3 = cat(_T_5141, _T_5131) @[Cat.scala 29:58] - node _T_5142 = bits(tag_valid_clken_0, 0, 0) @[ifu_mem_ctl.scala 687:135] + node _T_5142 = bits(tag_valid_clken_0, 0, 0) @[ifu_mem_ctl.scala 686:135] inst rvclkhdr_86 of rvclkhdr_86 @[lib.scala 343:22] rvclkhdr_86.clock <= clock rvclkhdr_86.reset <= reset rvclkhdr_86.io.clk <= clock @[lib.scala 344:17] rvclkhdr_86.io.en <= _T_5142 @[lib.scala 345:16] rvclkhdr_86.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - node _T_5143 = bits(tag_valid_clken_0, 1, 1) @[ifu_mem_ctl.scala 687:135] + node _T_5143 = bits(tag_valid_clken_0, 1, 1) @[ifu_mem_ctl.scala 686:135] inst rvclkhdr_87 of rvclkhdr_87 @[lib.scala 343:22] rvclkhdr_87.clock <= clock rvclkhdr_87.reset <= reset rvclkhdr_87.io.clk <= clock @[lib.scala 344:17] rvclkhdr_87.io.en <= _T_5143 @[lib.scala 345:16] rvclkhdr_87.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - node _T_5144 = bits(tag_valid_clken_1, 0, 0) @[ifu_mem_ctl.scala 687:135] + node _T_5144 = bits(tag_valid_clken_1, 0, 0) @[ifu_mem_ctl.scala 686:135] inst rvclkhdr_88 of rvclkhdr_88 @[lib.scala 343:22] rvclkhdr_88.clock <= clock rvclkhdr_88.reset <= reset rvclkhdr_88.io.clk <= clock @[lib.scala 344:17] rvclkhdr_88.io.en <= _T_5144 @[lib.scala 345:16] rvclkhdr_88.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - node _T_5145 = bits(tag_valid_clken_1, 1, 1) @[ifu_mem_ctl.scala 687:135] + node _T_5145 = bits(tag_valid_clken_1, 1, 1) @[ifu_mem_ctl.scala 686:135] inst rvclkhdr_89 of rvclkhdr_89 @[lib.scala 343:22] rvclkhdr_89.clock <= clock rvclkhdr_89.reset <= reset rvclkhdr_89.io.clk <= clock @[lib.scala 344:17] rvclkhdr_89.io.en <= _T_5145 @[lib.scala 345:16] rvclkhdr_89.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - node _T_5146 = bits(tag_valid_clken_2, 0, 0) @[ifu_mem_ctl.scala 687:135] + node _T_5146 = bits(tag_valid_clken_2, 0, 0) @[ifu_mem_ctl.scala 686:135] inst rvclkhdr_90 of rvclkhdr_90 @[lib.scala 343:22] rvclkhdr_90.clock <= clock rvclkhdr_90.reset <= reset rvclkhdr_90.io.clk <= clock @[lib.scala 344:17] rvclkhdr_90.io.en <= _T_5146 @[lib.scala 345:16] rvclkhdr_90.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - node _T_5147 = bits(tag_valid_clken_2, 1, 1) @[ifu_mem_ctl.scala 687:135] + node _T_5147 = bits(tag_valid_clken_2, 1, 1) @[ifu_mem_ctl.scala 686:135] inst rvclkhdr_91 of rvclkhdr_91 @[lib.scala 343:22] rvclkhdr_91.clock <= clock rvclkhdr_91.reset <= reset rvclkhdr_91.io.clk <= clock @[lib.scala 344:17] rvclkhdr_91.io.en <= _T_5147 @[lib.scala 345:16] rvclkhdr_91.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - node _T_5148 = bits(tag_valid_clken_3, 0, 0) @[ifu_mem_ctl.scala 687:135] + node _T_5148 = bits(tag_valid_clken_3, 0, 0) @[ifu_mem_ctl.scala 686:135] inst rvclkhdr_92 of rvclkhdr_92 @[lib.scala 343:22] rvclkhdr_92.clock <= clock rvclkhdr_92.reset <= reset rvclkhdr_92.io.clk <= clock @[lib.scala 344:17] rvclkhdr_92.io.en <= _T_5148 @[lib.scala 345:16] rvclkhdr_92.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - node _T_5149 = bits(tag_valid_clken_3, 1, 1) @[ifu_mem_ctl.scala 687:135] + node _T_5149 = bits(tag_valid_clken_3, 1, 1) @[ifu_mem_ctl.scala 686:135] inst rvclkhdr_93 of rvclkhdr_93 @[lib.scala 343:22] rvclkhdr_93.clock <= clock rvclkhdr_93.reset <= reset rvclkhdr_93.io.clk <= clock @[lib.scala 344:17] rvclkhdr_93.io.en <= _T_5149 @[lib.scala 345:16] rvclkhdr_93.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - wire ic_tag_valid_out : UInt<1>[128][2] @[ifu_mem_ctl.scala 688:32] - node _T_5150 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5151 = eq(_T_5150, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5152 = and(ic_valid_ff, _T_5151) @[ifu_mem_ctl.scala 693:97] - node _T_5153 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5154 = and(_T_5152, _T_5153) @[ifu_mem_ctl.scala 693:122] - node _T_5155 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 694:37] - node _T_5156 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_5157 = and(_T_5155, _T_5156) @[ifu_mem_ctl.scala 694:59] - node _T_5158 = eq(perr_ic_index_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 694:102] - node _T_5159 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_5160 = and(_T_5158, _T_5159) @[ifu_mem_ctl.scala 694:124] - node _T_5161 = or(_T_5157, _T_5160) @[ifu_mem_ctl.scala 694:81] - node _T_5162 = or(_T_5161, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5163 = bits(_T_5162, 0, 0) @[ifu_mem_ctl.scala 694:166] + wire ic_tag_valid_out : UInt<1>[128][2] @[ifu_mem_ctl.scala 687:32] + node _T_5150 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5151 = eq(_T_5150, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5152 = and(ic_valid_ff, _T_5151) @[ifu_mem_ctl.scala 692:97] + node _T_5153 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5154 = and(_T_5152, _T_5153) @[ifu_mem_ctl.scala 692:122] + node _T_5155 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:37] + node _T_5156 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_5157 = and(_T_5155, _T_5156) @[ifu_mem_ctl.scala 693:59] + node _T_5158 = eq(perr_ic_index_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:102] + node _T_5159 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_5160 = and(_T_5158, _T_5159) @[ifu_mem_ctl.scala 693:124] + node _T_5161 = or(_T_5157, _T_5160) @[ifu_mem_ctl.scala 693:81] + node _T_5162 = or(_T_5161, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5163 = bits(_T_5162, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5164 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5163 : @[Reg.scala 28:19] _T_5164 <= _T_5154 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][0] <= _T_5164 @[ifu_mem_ctl.scala 693:41] - node _T_5165 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5166 = eq(_T_5165, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5167 = and(ic_valid_ff, _T_5166) @[ifu_mem_ctl.scala 693:97] - node _T_5168 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5169 = and(_T_5167, _T_5168) @[ifu_mem_ctl.scala 693:122] - node _T_5170 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[ifu_mem_ctl.scala 694:37] - node _T_5171 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_5172 = and(_T_5170, _T_5171) @[ifu_mem_ctl.scala 694:59] - node _T_5173 = eq(perr_ic_index_ff, UInt<1>("h01")) @[ifu_mem_ctl.scala 694:102] - node _T_5174 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_5175 = and(_T_5173, _T_5174) @[ifu_mem_ctl.scala 694:124] - node _T_5176 = or(_T_5172, _T_5175) @[ifu_mem_ctl.scala 694:81] - node _T_5177 = or(_T_5176, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5178 = bits(_T_5177, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][0] <= _T_5164 @[ifu_mem_ctl.scala 692:41] + node _T_5165 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5166 = eq(_T_5165, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5167 = and(ic_valid_ff, _T_5166) @[ifu_mem_ctl.scala 692:97] + node _T_5168 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5169 = and(_T_5167, _T_5168) @[ifu_mem_ctl.scala 692:122] + node _T_5170 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[ifu_mem_ctl.scala 693:37] + node _T_5171 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_5172 = and(_T_5170, _T_5171) @[ifu_mem_ctl.scala 693:59] + node _T_5173 = eq(perr_ic_index_ff, UInt<1>("h01")) @[ifu_mem_ctl.scala 693:102] + node _T_5174 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_5175 = and(_T_5173, _T_5174) @[ifu_mem_ctl.scala 693:124] + node _T_5176 = or(_T_5172, _T_5175) @[ifu_mem_ctl.scala 693:81] + node _T_5177 = or(_T_5176, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5178 = bits(_T_5177, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5179 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5178 : @[Reg.scala 28:19] _T_5179 <= _T_5169 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][1] <= _T_5179 @[ifu_mem_ctl.scala 693:41] - node _T_5180 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5181 = eq(_T_5180, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5182 = and(ic_valid_ff, _T_5181) @[ifu_mem_ctl.scala 693:97] - node _T_5183 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5184 = and(_T_5182, _T_5183) @[ifu_mem_ctl.scala 693:122] - node _T_5185 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[ifu_mem_ctl.scala 694:37] - node _T_5186 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_5187 = and(_T_5185, _T_5186) @[ifu_mem_ctl.scala 694:59] - node _T_5188 = eq(perr_ic_index_ff, UInt<2>("h02")) @[ifu_mem_ctl.scala 694:102] - node _T_5189 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_5190 = and(_T_5188, _T_5189) @[ifu_mem_ctl.scala 694:124] - node _T_5191 = or(_T_5187, _T_5190) @[ifu_mem_ctl.scala 694:81] - node _T_5192 = or(_T_5191, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5193 = bits(_T_5192, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][1] <= _T_5179 @[ifu_mem_ctl.scala 692:41] + node _T_5180 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5181 = eq(_T_5180, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5182 = and(ic_valid_ff, _T_5181) @[ifu_mem_ctl.scala 692:97] + node _T_5183 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5184 = and(_T_5182, _T_5183) @[ifu_mem_ctl.scala 692:122] + node _T_5185 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[ifu_mem_ctl.scala 693:37] + node _T_5186 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_5187 = and(_T_5185, _T_5186) @[ifu_mem_ctl.scala 693:59] + node _T_5188 = eq(perr_ic_index_ff, UInt<2>("h02")) @[ifu_mem_ctl.scala 693:102] + node _T_5189 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_5190 = and(_T_5188, _T_5189) @[ifu_mem_ctl.scala 693:124] + node _T_5191 = or(_T_5187, _T_5190) @[ifu_mem_ctl.scala 693:81] + node _T_5192 = or(_T_5191, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5193 = bits(_T_5192, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5194 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5193 : @[Reg.scala 28:19] _T_5194 <= _T_5184 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][2] <= _T_5194 @[ifu_mem_ctl.scala 693:41] - node _T_5195 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5196 = eq(_T_5195, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5197 = and(ic_valid_ff, _T_5196) @[ifu_mem_ctl.scala 693:97] - node _T_5198 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5199 = and(_T_5197, _T_5198) @[ifu_mem_ctl.scala 693:122] - node _T_5200 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[ifu_mem_ctl.scala 694:37] - node _T_5201 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_5202 = and(_T_5200, _T_5201) @[ifu_mem_ctl.scala 694:59] - node _T_5203 = eq(perr_ic_index_ff, UInt<2>("h03")) @[ifu_mem_ctl.scala 694:102] - node _T_5204 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_5205 = and(_T_5203, _T_5204) @[ifu_mem_ctl.scala 694:124] - node _T_5206 = or(_T_5202, _T_5205) @[ifu_mem_ctl.scala 694:81] - node _T_5207 = or(_T_5206, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5208 = bits(_T_5207, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][2] <= _T_5194 @[ifu_mem_ctl.scala 692:41] + node _T_5195 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5196 = eq(_T_5195, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5197 = and(ic_valid_ff, _T_5196) @[ifu_mem_ctl.scala 692:97] + node _T_5198 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5199 = and(_T_5197, _T_5198) @[ifu_mem_ctl.scala 692:122] + node _T_5200 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[ifu_mem_ctl.scala 693:37] + node _T_5201 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_5202 = and(_T_5200, _T_5201) @[ifu_mem_ctl.scala 693:59] + node _T_5203 = eq(perr_ic_index_ff, UInt<2>("h03")) @[ifu_mem_ctl.scala 693:102] + node _T_5204 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_5205 = and(_T_5203, _T_5204) @[ifu_mem_ctl.scala 693:124] + node _T_5206 = or(_T_5202, _T_5205) @[ifu_mem_ctl.scala 693:81] + node _T_5207 = or(_T_5206, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5208 = bits(_T_5207, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5209 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5208 : @[Reg.scala 28:19] _T_5209 <= _T_5199 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][3] <= _T_5209 @[ifu_mem_ctl.scala 693:41] - node _T_5210 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5211 = eq(_T_5210, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5212 = and(ic_valid_ff, _T_5211) @[ifu_mem_ctl.scala 693:97] - node _T_5213 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5214 = and(_T_5212, _T_5213) @[ifu_mem_ctl.scala 693:122] - node _T_5215 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[ifu_mem_ctl.scala 694:37] - node _T_5216 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_5217 = and(_T_5215, _T_5216) @[ifu_mem_ctl.scala 694:59] - node _T_5218 = eq(perr_ic_index_ff, UInt<3>("h04")) @[ifu_mem_ctl.scala 694:102] - node _T_5219 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_5220 = and(_T_5218, _T_5219) @[ifu_mem_ctl.scala 694:124] - node _T_5221 = or(_T_5217, _T_5220) @[ifu_mem_ctl.scala 694:81] - node _T_5222 = or(_T_5221, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5223 = bits(_T_5222, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][3] <= _T_5209 @[ifu_mem_ctl.scala 692:41] + node _T_5210 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5211 = eq(_T_5210, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5212 = and(ic_valid_ff, _T_5211) @[ifu_mem_ctl.scala 692:97] + node _T_5213 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5214 = and(_T_5212, _T_5213) @[ifu_mem_ctl.scala 692:122] + node _T_5215 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[ifu_mem_ctl.scala 693:37] + node _T_5216 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_5217 = and(_T_5215, _T_5216) @[ifu_mem_ctl.scala 693:59] + node _T_5218 = eq(perr_ic_index_ff, UInt<3>("h04")) @[ifu_mem_ctl.scala 693:102] + node _T_5219 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_5220 = and(_T_5218, _T_5219) @[ifu_mem_ctl.scala 693:124] + node _T_5221 = or(_T_5217, _T_5220) @[ifu_mem_ctl.scala 693:81] + node _T_5222 = or(_T_5221, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5223 = bits(_T_5222, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5224 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5223 : @[Reg.scala 28:19] _T_5224 <= _T_5214 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][4] <= _T_5224 @[ifu_mem_ctl.scala 693:41] - node _T_5225 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5226 = eq(_T_5225, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5227 = and(ic_valid_ff, _T_5226) @[ifu_mem_ctl.scala 693:97] - node _T_5228 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5229 = and(_T_5227, _T_5228) @[ifu_mem_ctl.scala 693:122] - node _T_5230 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[ifu_mem_ctl.scala 694:37] - node _T_5231 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_5232 = and(_T_5230, _T_5231) @[ifu_mem_ctl.scala 694:59] - node _T_5233 = eq(perr_ic_index_ff, UInt<3>("h05")) @[ifu_mem_ctl.scala 694:102] - node _T_5234 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_5235 = and(_T_5233, _T_5234) @[ifu_mem_ctl.scala 694:124] - node _T_5236 = or(_T_5232, _T_5235) @[ifu_mem_ctl.scala 694:81] - node _T_5237 = or(_T_5236, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5238 = bits(_T_5237, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][4] <= _T_5224 @[ifu_mem_ctl.scala 692:41] + node _T_5225 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5226 = eq(_T_5225, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5227 = and(ic_valid_ff, _T_5226) @[ifu_mem_ctl.scala 692:97] + node _T_5228 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5229 = and(_T_5227, _T_5228) @[ifu_mem_ctl.scala 692:122] + node _T_5230 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[ifu_mem_ctl.scala 693:37] + node _T_5231 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_5232 = and(_T_5230, _T_5231) @[ifu_mem_ctl.scala 693:59] + node _T_5233 = eq(perr_ic_index_ff, UInt<3>("h05")) @[ifu_mem_ctl.scala 693:102] + node _T_5234 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_5235 = and(_T_5233, _T_5234) @[ifu_mem_ctl.scala 693:124] + node _T_5236 = or(_T_5232, _T_5235) @[ifu_mem_ctl.scala 693:81] + node _T_5237 = or(_T_5236, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5238 = bits(_T_5237, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5239 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5238 : @[Reg.scala 28:19] _T_5239 <= _T_5229 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][5] <= _T_5239 @[ifu_mem_ctl.scala 693:41] - node _T_5240 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5241 = eq(_T_5240, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5242 = and(ic_valid_ff, _T_5241) @[ifu_mem_ctl.scala 693:97] - node _T_5243 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5244 = and(_T_5242, _T_5243) @[ifu_mem_ctl.scala 693:122] - node _T_5245 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[ifu_mem_ctl.scala 694:37] - node _T_5246 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_5247 = and(_T_5245, _T_5246) @[ifu_mem_ctl.scala 694:59] - node _T_5248 = eq(perr_ic_index_ff, UInt<3>("h06")) @[ifu_mem_ctl.scala 694:102] - node _T_5249 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_5250 = and(_T_5248, _T_5249) @[ifu_mem_ctl.scala 694:124] - node _T_5251 = or(_T_5247, _T_5250) @[ifu_mem_ctl.scala 694:81] - node _T_5252 = or(_T_5251, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5253 = bits(_T_5252, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][5] <= _T_5239 @[ifu_mem_ctl.scala 692:41] + node _T_5240 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5241 = eq(_T_5240, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5242 = and(ic_valid_ff, _T_5241) @[ifu_mem_ctl.scala 692:97] + node _T_5243 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5244 = and(_T_5242, _T_5243) @[ifu_mem_ctl.scala 692:122] + node _T_5245 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[ifu_mem_ctl.scala 693:37] + node _T_5246 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_5247 = and(_T_5245, _T_5246) @[ifu_mem_ctl.scala 693:59] + node _T_5248 = eq(perr_ic_index_ff, UInt<3>("h06")) @[ifu_mem_ctl.scala 693:102] + node _T_5249 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_5250 = and(_T_5248, _T_5249) @[ifu_mem_ctl.scala 693:124] + node _T_5251 = or(_T_5247, _T_5250) @[ifu_mem_ctl.scala 693:81] + node _T_5252 = or(_T_5251, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5253 = bits(_T_5252, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5254 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5253 : @[Reg.scala 28:19] _T_5254 <= _T_5244 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][6] <= _T_5254 @[ifu_mem_ctl.scala 693:41] - node _T_5255 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5256 = eq(_T_5255, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5257 = and(ic_valid_ff, _T_5256) @[ifu_mem_ctl.scala 693:97] - node _T_5258 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5259 = and(_T_5257, _T_5258) @[ifu_mem_ctl.scala 693:122] - node _T_5260 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[ifu_mem_ctl.scala 694:37] - node _T_5261 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_5262 = and(_T_5260, _T_5261) @[ifu_mem_ctl.scala 694:59] - node _T_5263 = eq(perr_ic_index_ff, UInt<3>("h07")) @[ifu_mem_ctl.scala 694:102] - node _T_5264 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_5265 = and(_T_5263, _T_5264) @[ifu_mem_ctl.scala 694:124] - node _T_5266 = or(_T_5262, _T_5265) @[ifu_mem_ctl.scala 694:81] - node _T_5267 = or(_T_5266, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5268 = bits(_T_5267, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][6] <= _T_5254 @[ifu_mem_ctl.scala 692:41] + node _T_5255 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5256 = eq(_T_5255, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5257 = and(ic_valid_ff, _T_5256) @[ifu_mem_ctl.scala 692:97] + node _T_5258 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5259 = and(_T_5257, _T_5258) @[ifu_mem_ctl.scala 692:122] + node _T_5260 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[ifu_mem_ctl.scala 693:37] + node _T_5261 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_5262 = and(_T_5260, _T_5261) @[ifu_mem_ctl.scala 693:59] + node _T_5263 = eq(perr_ic_index_ff, UInt<3>("h07")) @[ifu_mem_ctl.scala 693:102] + node _T_5264 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_5265 = and(_T_5263, _T_5264) @[ifu_mem_ctl.scala 693:124] + node _T_5266 = or(_T_5262, _T_5265) @[ifu_mem_ctl.scala 693:81] + node _T_5267 = or(_T_5266, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5268 = bits(_T_5267, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5269 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5268 : @[Reg.scala 28:19] _T_5269 <= _T_5259 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][7] <= _T_5269 @[ifu_mem_ctl.scala 693:41] - node _T_5270 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5271 = eq(_T_5270, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5272 = and(ic_valid_ff, _T_5271) @[ifu_mem_ctl.scala 693:97] - node _T_5273 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5274 = and(_T_5272, _T_5273) @[ifu_mem_ctl.scala 693:122] - node _T_5275 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[ifu_mem_ctl.scala 694:37] - node _T_5276 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_5277 = and(_T_5275, _T_5276) @[ifu_mem_ctl.scala 694:59] - node _T_5278 = eq(perr_ic_index_ff, UInt<4>("h08")) @[ifu_mem_ctl.scala 694:102] - node _T_5279 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_5280 = and(_T_5278, _T_5279) @[ifu_mem_ctl.scala 694:124] - node _T_5281 = or(_T_5277, _T_5280) @[ifu_mem_ctl.scala 694:81] - node _T_5282 = or(_T_5281, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5283 = bits(_T_5282, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][7] <= _T_5269 @[ifu_mem_ctl.scala 692:41] + node _T_5270 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5271 = eq(_T_5270, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5272 = and(ic_valid_ff, _T_5271) @[ifu_mem_ctl.scala 692:97] + node _T_5273 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5274 = and(_T_5272, _T_5273) @[ifu_mem_ctl.scala 692:122] + node _T_5275 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[ifu_mem_ctl.scala 693:37] + node _T_5276 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_5277 = and(_T_5275, _T_5276) @[ifu_mem_ctl.scala 693:59] + node _T_5278 = eq(perr_ic_index_ff, UInt<4>("h08")) @[ifu_mem_ctl.scala 693:102] + node _T_5279 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_5280 = and(_T_5278, _T_5279) @[ifu_mem_ctl.scala 693:124] + node _T_5281 = or(_T_5277, _T_5280) @[ifu_mem_ctl.scala 693:81] + node _T_5282 = or(_T_5281, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5283 = bits(_T_5282, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5284 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5283 : @[Reg.scala 28:19] _T_5284 <= _T_5274 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][8] <= _T_5284 @[ifu_mem_ctl.scala 693:41] - node _T_5285 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5286 = eq(_T_5285, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5287 = and(ic_valid_ff, _T_5286) @[ifu_mem_ctl.scala 693:97] - node _T_5288 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5289 = and(_T_5287, _T_5288) @[ifu_mem_ctl.scala 693:122] - node _T_5290 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[ifu_mem_ctl.scala 694:37] - node _T_5291 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_5292 = and(_T_5290, _T_5291) @[ifu_mem_ctl.scala 694:59] - node _T_5293 = eq(perr_ic_index_ff, UInt<4>("h09")) @[ifu_mem_ctl.scala 694:102] - node _T_5294 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_5295 = and(_T_5293, _T_5294) @[ifu_mem_ctl.scala 694:124] - node _T_5296 = or(_T_5292, _T_5295) @[ifu_mem_ctl.scala 694:81] - node _T_5297 = or(_T_5296, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5298 = bits(_T_5297, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][8] <= _T_5284 @[ifu_mem_ctl.scala 692:41] + node _T_5285 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5286 = eq(_T_5285, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5287 = and(ic_valid_ff, _T_5286) @[ifu_mem_ctl.scala 692:97] + node _T_5288 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5289 = and(_T_5287, _T_5288) @[ifu_mem_ctl.scala 692:122] + node _T_5290 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[ifu_mem_ctl.scala 693:37] + node _T_5291 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_5292 = and(_T_5290, _T_5291) @[ifu_mem_ctl.scala 693:59] + node _T_5293 = eq(perr_ic_index_ff, UInt<4>("h09")) @[ifu_mem_ctl.scala 693:102] + node _T_5294 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_5295 = and(_T_5293, _T_5294) @[ifu_mem_ctl.scala 693:124] + node _T_5296 = or(_T_5292, _T_5295) @[ifu_mem_ctl.scala 693:81] + node _T_5297 = or(_T_5296, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5298 = bits(_T_5297, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5299 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5298 : @[Reg.scala 28:19] _T_5299 <= _T_5289 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][9] <= _T_5299 @[ifu_mem_ctl.scala 693:41] - node _T_5300 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5301 = eq(_T_5300, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5302 = and(ic_valid_ff, _T_5301) @[ifu_mem_ctl.scala 693:97] - node _T_5303 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5304 = and(_T_5302, _T_5303) @[ifu_mem_ctl.scala 693:122] - node _T_5305 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[ifu_mem_ctl.scala 694:37] - node _T_5306 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_5307 = and(_T_5305, _T_5306) @[ifu_mem_ctl.scala 694:59] - node _T_5308 = eq(perr_ic_index_ff, UInt<4>("h0a")) @[ifu_mem_ctl.scala 694:102] - node _T_5309 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_5310 = and(_T_5308, _T_5309) @[ifu_mem_ctl.scala 694:124] - node _T_5311 = or(_T_5307, _T_5310) @[ifu_mem_ctl.scala 694:81] - node _T_5312 = or(_T_5311, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5313 = bits(_T_5312, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][9] <= _T_5299 @[ifu_mem_ctl.scala 692:41] + node _T_5300 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5301 = eq(_T_5300, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5302 = and(ic_valid_ff, _T_5301) @[ifu_mem_ctl.scala 692:97] + node _T_5303 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5304 = and(_T_5302, _T_5303) @[ifu_mem_ctl.scala 692:122] + node _T_5305 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[ifu_mem_ctl.scala 693:37] + node _T_5306 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_5307 = and(_T_5305, _T_5306) @[ifu_mem_ctl.scala 693:59] + node _T_5308 = eq(perr_ic_index_ff, UInt<4>("h0a")) @[ifu_mem_ctl.scala 693:102] + node _T_5309 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_5310 = and(_T_5308, _T_5309) @[ifu_mem_ctl.scala 693:124] + node _T_5311 = or(_T_5307, _T_5310) @[ifu_mem_ctl.scala 693:81] + node _T_5312 = or(_T_5311, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5313 = bits(_T_5312, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5314 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5313 : @[Reg.scala 28:19] _T_5314 <= _T_5304 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][10] <= _T_5314 @[ifu_mem_ctl.scala 693:41] - node _T_5315 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5316 = eq(_T_5315, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5317 = and(ic_valid_ff, _T_5316) @[ifu_mem_ctl.scala 693:97] - node _T_5318 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5319 = and(_T_5317, _T_5318) @[ifu_mem_ctl.scala 693:122] - node _T_5320 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[ifu_mem_ctl.scala 694:37] - node _T_5321 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_5322 = and(_T_5320, _T_5321) @[ifu_mem_ctl.scala 694:59] - node _T_5323 = eq(perr_ic_index_ff, UInt<4>("h0b")) @[ifu_mem_ctl.scala 694:102] - node _T_5324 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_5325 = and(_T_5323, _T_5324) @[ifu_mem_ctl.scala 694:124] - node _T_5326 = or(_T_5322, _T_5325) @[ifu_mem_ctl.scala 694:81] - node _T_5327 = or(_T_5326, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5328 = bits(_T_5327, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][10] <= _T_5314 @[ifu_mem_ctl.scala 692:41] + node _T_5315 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5316 = eq(_T_5315, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5317 = and(ic_valid_ff, _T_5316) @[ifu_mem_ctl.scala 692:97] + node _T_5318 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5319 = and(_T_5317, _T_5318) @[ifu_mem_ctl.scala 692:122] + node _T_5320 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[ifu_mem_ctl.scala 693:37] + node _T_5321 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_5322 = and(_T_5320, _T_5321) @[ifu_mem_ctl.scala 693:59] + node _T_5323 = eq(perr_ic_index_ff, UInt<4>("h0b")) @[ifu_mem_ctl.scala 693:102] + node _T_5324 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_5325 = and(_T_5323, _T_5324) @[ifu_mem_ctl.scala 693:124] + node _T_5326 = or(_T_5322, _T_5325) @[ifu_mem_ctl.scala 693:81] + node _T_5327 = or(_T_5326, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5328 = bits(_T_5327, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5329 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5328 : @[Reg.scala 28:19] _T_5329 <= _T_5319 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][11] <= _T_5329 @[ifu_mem_ctl.scala 693:41] - node _T_5330 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5331 = eq(_T_5330, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5332 = and(ic_valid_ff, _T_5331) @[ifu_mem_ctl.scala 693:97] - node _T_5333 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5334 = and(_T_5332, _T_5333) @[ifu_mem_ctl.scala 693:122] - node _T_5335 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[ifu_mem_ctl.scala 694:37] - node _T_5336 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_5337 = and(_T_5335, _T_5336) @[ifu_mem_ctl.scala 694:59] - node _T_5338 = eq(perr_ic_index_ff, UInt<4>("h0c")) @[ifu_mem_ctl.scala 694:102] - node _T_5339 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_5340 = and(_T_5338, _T_5339) @[ifu_mem_ctl.scala 694:124] - node _T_5341 = or(_T_5337, _T_5340) @[ifu_mem_ctl.scala 694:81] - node _T_5342 = or(_T_5341, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5343 = bits(_T_5342, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][11] <= _T_5329 @[ifu_mem_ctl.scala 692:41] + node _T_5330 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5331 = eq(_T_5330, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5332 = and(ic_valid_ff, _T_5331) @[ifu_mem_ctl.scala 692:97] + node _T_5333 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5334 = and(_T_5332, _T_5333) @[ifu_mem_ctl.scala 692:122] + node _T_5335 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[ifu_mem_ctl.scala 693:37] + node _T_5336 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_5337 = and(_T_5335, _T_5336) @[ifu_mem_ctl.scala 693:59] + node _T_5338 = eq(perr_ic_index_ff, UInt<4>("h0c")) @[ifu_mem_ctl.scala 693:102] + node _T_5339 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_5340 = and(_T_5338, _T_5339) @[ifu_mem_ctl.scala 693:124] + node _T_5341 = or(_T_5337, _T_5340) @[ifu_mem_ctl.scala 693:81] + node _T_5342 = or(_T_5341, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5343 = bits(_T_5342, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5344 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5343 : @[Reg.scala 28:19] _T_5344 <= _T_5334 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][12] <= _T_5344 @[ifu_mem_ctl.scala 693:41] - node _T_5345 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5346 = eq(_T_5345, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5347 = and(ic_valid_ff, _T_5346) @[ifu_mem_ctl.scala 693:97] - node _T_5348 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5349 = and(_T_5347, _T_5348) @[ifu_mem_ctl.scala 693:122] - node _T_5350 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[ifu_mem_ctl.scala 694:37] - node _T_5351 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_5352 = and(_T_5350, _T_5351) @[ifu_mem_ctl.scala 694:59] - node _T_5353 = eq(perr_ic_index_ff, UInt<4>("h0d")) @[ifu_mem_ctl.scala 694:102] - node _T_5354 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_5355 = and(_T_5353, _T_5354) @[ifu_mem_ctl.scala 694:124] - node _T_5356 = or(_T_5352, _T_5355) @[ifu_mem_ctl.scala 694:81] - node _T_5357 = or(_T_5356, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5358 = bits(_T_5357, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][12] <= _T_5344 @[ifu_mem_ctl.scala 692:41] + node _T_5345 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5346 = eq(_T_5345, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5347 = and(ic_valid_ff, _T_5346) @[ifu_mem_ctl.scala 692:97] + node _T_5348 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5349 = and(_T_5347, _T_5348) @[ifu_mem_ctl.scala 692:122] + node _T_5350 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[ifu_mem_ctl.scala 693:37] + node _T_5351 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_5352 = and(_T_5350, _T_5351) @[ifu_mem_ctl.scala 693:59] + node _T_5353 = eq(perr_ic_index_ff, UInt<4>("h0d")) @[ifu_mem_ctl.scala 693:102] + node _T_5354 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_5355 = and(_T_5353, _T_5354) @[ifu_mem_ctl.scala 693:124] + node _T_5356 = or(_T_5352, _T_5355) @[ifu_mem_ctl.scala 693:81] + node _T_5357 = or(_T_5356, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5358 = bits(_T_5357, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5359 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5358 : @[Reg.scala 28:19] _T_5359 <= _T_5349 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][13] <= _T_5359 @[ifu_mem_ctl.scala 693:41] - node _T_5360 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5361 = eq(_T_5360, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5362 = and(ic_valid_ff, _T_5361) @[ifu_mem_ctl.scala 693:97] - node _T_5363 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5364 = and(_T_5362, _T_5363) @[ifu_mem_ctl.scala 693:122] - node _T_5365 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[ifu_mem_ctl.scala 694:37] - node _T_5366 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_5367 = and(_T_5365, _T_5366) @[ifu_mem_ctl.scala 694:59] - node _T_5368 = eq(perr_ic_index_ff, UInt<4>("h0e")) @[ifu_mem_ctl.scala 694:102] - node _T_5369 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_5370 = and(_T_5368, _T_5369) @[ifu_mem_ctl.scala 694:124] - node _T_5371 = or(_T_5367, _T_5370) @[ifu_mem_ctl.scala 694:81] - node _T_5372 = or(_T_5371, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5373 = bits(_T_5372, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][13] <= _T_5359 @[ifu_mem_ctl.scala 692:41] + node _T_5360 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5361 = eq(_T_5360, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5362 = and(ic_valid_ff, _T_5361) @[ifu_mem_ctl.scala 692:97] + node _T_5363 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5364 = and(_T_5362, _T_5363) @[ifu_mem_ctl.scala 692:122] + node _T_5365 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[ifu_mem_ctl.scala 693:37] + node _T_5366 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_5367 = and(_T_5365, _T_5366) @[ifu_mem_ctl.scala 693:59] + node _T_5368 = eq(perr_ic_index_ff, UInt<4>("h0e")) @[ifu_mem_ctl.scala 693:102] + node _T_5369 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_5370 = and(_T_5368, _T_5369) @[ifu_mem_ctl.scala 693:124] + node _T_5371 = or(_T_5367, _T_5370) @[ifu_mem_ctl.scala 693:81] + node _T_5372 = or(_T_5371, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5373 = bits(_T_5372, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5374 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5373 : @[Reg.scala 28:19] _T_5374 <= _T_5364 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][14] <= _T_5374 @[ifu_mem_ctl.scala 693:41] - node _T_5375 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5376 = eq(_T_5375, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5377 = and(ic_valid_ff, _T_5376) @[ifu_mem_ctl.scala 693:97] - node _T_5378 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5379 = and(_T_5377, _T_5378) @[ifu_mem_ctl.scala 693:122] - node _T_5380 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[ifu_mem_ctl.scala 694:37] - node _T_5381 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_5382 = and(_T_5380, _T_5381) @[ifu_mem_ctl.scala 694:59] - node _T_5383 = eq(perr_ic_index_ff, UInt<4>("h0f")) @[ifu_mem_ctl.scala 694:102] - node _T_5384 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_5385 = and(_T_5383, _T_5384) @[ifu_mem_ctl.scala 694:124] - node _T_5386 = or(_T_5382, _T_5385) @[ifu_mem_ctl.scala 694:81] - node _T_5387 = or(_T_5386, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5388 = bits(_T_5387, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][14] <= _T_5374 @[ifu_mem_ctl.scala 692:41] + node _T_5375 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5376 = eq(_T_5375, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5377 = and(ic_valid_ff, _T_5376) @[ifu_mem_ctl.scala 692:97] + node _T_5378 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5379 = and(_T_5377, _T_5378) @[ifu_mem_ctl.scala 692:122] + node _T_5380 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[ifu_mem_ctl.scala 693:37] + node _T_5381 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_5382 = and(_T_5380, _T_5381) @[ifu_mem_ctl.scala 693:59] + node _T_5383 = eq(perr_ic_index_ff, UInt<4>("h0f")) @[ifu_mem_ctl.scala 693:102] + node _T_5384 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_5385 = and(_T_5383, _T_5384) @[ifu_mem_ctl.scala 693:124] + node _T_5386 = or(_T_5382, _T_5385) @[ifu_mem_ctl.scala 693:81] + node _T_5387 = or(_T_5386, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5388 = bits(_T_5387, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5389 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5388 : @[Reg.scala 28:19] _T_5389 <= _T_5379 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][15] <= _T_5389 @[ifu_mem_ctl.scala 693:41] - node _T_5390 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5391 = eq(_T_5390, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5392 = and(ic_valid_ff, _T_5391) @[ifu_mem_ctl.scala 693:97] - node _T_5393 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5394 = and(_T_5392, _T_5393) @[ifu_mem_ctl.scala 693:122] - node _T_5395 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[ifu_mem_ctl.scala 694:37] - node _T_5396 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_5397 = and(_T_5395, _T_5396) @[ifu_mem_ctl.scala 694:59] - node _T_5398 = eq(perr_ic_index_ff, UInt<5>("h010")) @[ifu_mem_ctl.scala 694:102] - node _T_5399 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_5400 = and(_T_5398, _T_5399) @[ifu_mem_ctl.scala 694:124] - node _T_5401 = or(_T_5397, _T_5400) @[ifu_mem_ctl.scala 694:81] - node _T_5402 = or(_T_5401, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5403 = bits(_T_5402, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][15] <= _T_5389 @[ifu_mem_ctl.scala 692:41] + node _T_5390 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5391 = eq(_T_5390, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5392 = and(ic_valid_ff, _T_5391) @[ifu_mem_ctl.scala 692:97] + node _T_5393 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5394 = and(_T_5392, _T_5393) @[ifu_mem_ctl.scala 692:122] + node _T_5395 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[ifu_mem_ctl.scala 693:37] + node _T_5396 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_5397 = and(_T_5395, _T_5396) @[ifu_mem_ctl.scala 693:59] + node _T_5398 = eq(perr_ic_index_ff, UInt<5>("h010")) @[ifu_mem_ctl.scala 693:102] + node _T_5399 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_5400 = and(_T_5398, _T_5399) @[ifu_mem_ctl.scala 693:124] + node _T_5401 = or(_T_5397, _T_5400) @[ifu_mem_ctl.scala 693:81] + node _T_5402 = or(_T_5401, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5403 = bits(_T_5402, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5404 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5403 : @[Reg.scala 28:19] _T_5404 <= _T_5394 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][16] <= _T_5404 @[ifu_mem_ctl.scala 693:41] - node _T_5405 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5406 = eq(_T_5405, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5407 = and(ic_valid_ff, _T_5406) @[ifu_mem_ctl.scala 693:97] - node _T_5408 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5409 = and(_T_5407, _T_5408) @[ifu_mem_ctl.scala 693:122] - node _T_5410 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[ifu_mem_ctl.scala 694:37] - node _T_5411 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_5412 = and(_T_5410, _T_5411) @[ifu_mem_ctl.scala 694:59] - node _T_5413 = eq(perr_ic_index_ff, UInt<5>("h011")) @[ifu_mem_ctl.scala 694:102] - node _T_5414 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_5415 = and(_T_5413, _T_5414) @[ifu_mem_ctl.scala 694:124] - node _T_5416 = or(_T_5412, _T_5415) @[ifu_mem_ctl.scala 694:81] - node _T_5417 = or(_T_5416, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5418 = bits(_T_5417, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][16] <= _T_5404 @[ifu_mem_ctl.scala 692:41] + node _T_5405 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5406 = eq(_T_5405, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5407 = and(ic_valid_ff, _T_5406) @[ifu_mem_ctl.scala 692:97] + node _T_5408 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5409 = and(_T_5407, _T_5408) @[ifu_mem_ctl.scala 692:122] + node _T_5410 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[ifu_mem_ctl.scala 693:37] + node _T_5411 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_5412 = and(_T_5410, _T_5411) @[ifu_mem_ctl.scala 693:59] + node _T_5413 = eq(perr_ic_index_ff, UInt<5>("h011")) @[ifu_mem_ctl.scala 693:102] + node _T_5414 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_5415 = and(_T_5413, _T_5414) @[ifu_mem_ctl.scala 693:124] + node _T_5416 = or(_T_5412, _T_5415) @[ifu_mem_ctl.scala 693:81] + node _T_5417 = or(_T_5416, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5418 = bits(_T_5417, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5419 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5418 : @[Reg.scala 28:19] _T_5419 <= _T_5409 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][17] <= _T_5419 @[ifu_mem_ctl.scala 693:41] - node _T_5420 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5421 = eq(_T_5420, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5422 = and(ic_valid_ff, _T_5421) @[ifu_mem_ctl.scala 693:97] - node _T_5423 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5424 = and(_T_5422, _T_5423) @[ifu_mem_ctl.scala 693:122] - node _T_5425 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[ifu_mem_ctl.scala 694:37] - node _T_5426 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_5427 = and(_T_5425, _T_5426) @[ifu_mem_ctl.scala 694:59] - node _T_5428 = eq(perr_ic_index_ff, UInt<5>("h012")) @[ifu_mem_ctl.scala 694:102] - node _T_5429 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_5430 = and(_T_5428, _T_5429) @[ifu_mem_ctl.scala 694:124] - node _T_5431 = or(_T_5427, _T_5430) @[ifu_mem_ctl.scala 694:81] - node _T_5432 = or(_T_5431, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5433 = bits(_T_5432, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][17] <= _T_5419 @[ifu_mem_ctl.scala 692:41] + node _T_5420 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5421 = eq(_T_5420, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5422 = and(ic_valid_ff, _T_5421) @[ifu_mem_ctl.scala 692:97] + node _T_5423 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5424 = and(_T_5422, _T_5423) @[ifu_mem_ctl.scala 692:122] + node _T_5425 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[ifu_mem_ctl.scala 693:37] + node _T_5426 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_5427 = and(_T_5425, _T_5426) @[ifu_mem_ctl.scala 693:59] + node _T_5428 = eq(perr_ic_index_ff, UInt<5>("h012")) @[ifu_mem_ctl.scala 693:102] + node _T_5429 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_5430 = and(_T_5428, _T_5429) @[ifu_mem_ctl.scala 693:124] + node _T_5431 = or(_T_5427, _T_5430) @[ifu_mem_ctl.scala 693:81] + node _T_5432 = or(_T_5431, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5433 = bits(_T_5432, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5434 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5433 : @[Reg.scala 28:19] _T_5434 <= _T_5424 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][18] <= _T_5434 @[ifu_mem_ctl.scala 693:41] - node _T_5435 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5436 = eq(_T_5435, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5437 = and(ic_valid_ff, _T_5436) @[ifu_mem_ctl.scala 693:97] - node _T_5438 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5439 = and(_T_5437, _T_5438) @[ifu_mem_ctl.scala 693:122] - node _T_5440 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[ifu_mem_ctl.scala 694:37] - node _T_5441 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_5442 = and(_T_5440, _T_5441) @[ifu_mem_ctl.scala 694:59] - node _T_5443 = eq(perr_ic_index_ff, UInt<5>("h013")) @[ifu_mem_ctl.scala 694:102] - node _T_5444 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_5445 = and(_T_5443, _T_5444) @[ifu_mem_ctl.scala 694:124] - node _T_5446 = or(_T_5442, _T_5445) @[ifu_mem_ctl.scala 694:81] - node _T_5447 = or(_T_5446, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5448 = bits(_T_5447, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][18] <= _T_5434 @[ifu_mem_ctl.scala 692:41] + node _T_5435 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5436 = eq(_T_5435, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5437 = and(ic_valid_ff, _T_5436) @[ifu_mem_ctl.scala 692:97] + node _T_5438 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5439 = and(_T_5437, _T_5438) @[ifu_mem_ctl.scala 692:122] + node _T_5440 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[ifu_mem_ctl.scala 693:37] + node _T_5441 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_5442 = and(_T_5440, _T_5441) @[ifu_mem_ctl.scala 693:59] + node _T_5443 = eq(perr_ic_index_ff, UInt<5>("h013")) @[ifu_mem_ctl.scala 693:102] + node _T_5444 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_5445 = and(_T_5443, _T_5444) @[ifu_mem_ctl.scala 693:124] + node _T_5446 = or(_T_5442, _T_5445) @[ifu_mem_ctl.scala 693:81] + node _T_5447 = or(_T_5446, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5448 = bits(_T_5447, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5449 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5448 : @[Reg.scala 28:19] _T_5449 <= _T_5439 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][19] <= _T_5449 @[ifu_mem_ctl.scala 693:41] - node _T_5450 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5451 = eq(_T_5450, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5452 = and(ic_valid_ff, _T_5451) @[ifu_mem_ctl.scala 693:97] - node _T_5453 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5454 = and(_T_5452, _T_5453) @[ifu_mem_ctl.scala 693:122] - node _T_5455 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[ifu_mem_ctl.scala 694:37] - node _T_5456 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_5457 = and(_T_5455, _T_5456) @[ifu_mem_ctl.scala 694:59] - node _T_5458 = eq(perr_ic_index_ff, UInt<5>("h014")) @[ifu_mem_ctl.scala 694:102] - node _T_5459 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_5460 = and(_T_5458, _T_5459) @[ifu_mem_ctl.scala 694:124] - node _T_5461 = or(_T_5457, _T_5460) @[ifu_mem_ctl.scala 694:81] - node _T_5462 = or(_T_5461, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5463 = bits(_T_5462, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][19] <= _T_5449 @[ifu_mem_ctl.scala 692:41] + node _T_5450 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5451 = eq(_T_5450, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5452 = and(ic_valid_ff, _T_5451) @[ifu_mem_ctl.scala 692:97] + node _T_5453 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5454 = and(_T_5452, _T_5453) @[ifu_mem_ctl.scala 692:122] + node _T_5455 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[ifu_mem_ctl.scala 693:37] + node _T_5456 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_5457 = and(_T_5455, _T_5456) @[ifu_mem_ctl.scala 693:59] + node _T_5458 = eq(perr_ic_index_ff, UInt<5>("h014")) @[ifu_mem_ctl.scala 693:102] + node _T_5459 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_5460 = and(_T_5458, _T_5459) @[ifu_mem_ctl.scala 693:124] + node _T_5461 = or(_T_5457, _T_5460) @[ifu_mem_ctl.scala 693:81] + node _T_5462 = or(_T_5461, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5463 = bits(_T_5462, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5464 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5463 : @[Reg.scala 28:19] _T_5464 <= _T_5454 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][20] <= _T_5464 @[ifu_mem_ctl.scala 693:41] - node _T_5465 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5466 = eq(_T_5465, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5467 = and(ic_valid_ff, _T_5466) @[ifu_mem_ctl.scala 693:97] - node _T_5468 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5469 = and(_T_5467, _T_5468) @[ifu_mem_ctl.scala 693:122] - node _T_5470 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[ifu_mem_ctl.scala 694:37] - node _T_5471 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_5472 = and(_T_5470, _T_5471) @[ifu_mem_ctl.scala 694:59] - node _T_5473 = eq(perr_ic_index_ff, UInt<5>("h015")) @[ifu_mem_ctl.scala 694:102] - node _T_5474 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_5475 = and(_T_5473, _T_5474) @[ifu_mem_ctl.scala 694:124] - node _T_5476 = or(_T_5472, _T_5475) @[ifu_mem_ctl.scala 694:81] - node _T_5477 = or(_T_5476, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5478 = bits(_T_5477, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][20] <= _T_5464 @[ifu_mem_ctl.scala 692:41] + node _T_5465 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5466 = eq(_T_5465, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5467 = and(ic_valid_ff, _T_5466) @[ifu_mem_ctl.scala 692:97] + node _T_5468 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5469 = and(_T_5467, _T_5468) @[ifu_mem_ctl.scala 692:122] + node _T_5470 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[ifu_mem_ctl.scala 693:37] + node _T_5471 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_5472 = and(_T_5470, _T_5471) @[ifu_mem_ctl.scala 693:59] + node _T_5473 = eq(perr_ic_index_ff, UInt<5>("h015")) @[ifu_mem_ctl.scala 693:102] + node _T_5474 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_5475 = and(_T_5473, _T_5474) @[ifu_mem_ctl.scala 693:124] + node _T_5476 = or(_T_5472, _T_5475) @[ifu_mem_ctl.scala 693:81] + node _T_5477 = or(_T_5476, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5478 = bits(_T_5477, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5479 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5478 : @[Reg.scala 28:19] _T_5479 <= _T_5469 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][21] <= _T_5479 @[ifu_mem_ctl.scala 693:41] - node _T_5480 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5481 = eq(_T_5480, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5482 = and(ic_valid_ff, _T_5481) @[ifu_mem_ctl.scala 693:97] - node _T_5483 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5484 = and(_T_5482, _T_5483) @[ifu_mem_ctl.scala 693:122] - node _T_5485 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[ifu_mem_ctl.scala 694:37] - node _T_5486 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_5487 = and(_T_5485, _T_5486) @[ifu_mem_ctl.scala 694:59] - node _T_5488 = eq(perr_ic_index_ff, UInt<5>("h016")) @[ifu_mem_ctl.scala 694:102] - node _T_5489 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_5490 = and(_T_5488, _T_5489) @[ifu_mem_ctl.scala 694:124] - node _T_5491 = or(_T_5487, _T_5490) @[ifu_mem_ctl.scala 694:81] - node _T_5492 = or(_T_5491, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5493 = bits(_T_5492, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][21] <= _T_5479 @[ifu_mem_ctl.scala 692:41] + node _T_5480 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5481 = eq(_T_5480, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5482 = and(ic_valid_ff, _T_5481) @[ifu_mem_ctl.scala 692:97] + node _T_5483 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5484 = and(_T_5482, _T_5483) @[ifu_mem_ctl.scala 692:122] + node _T_5485 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[ifu_mem_ctl.scala 693:37] + node _T_5486 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_5487 = and(_T_5485, _T_5486) @[ifu_mem_ctl.scala 693:59] + node _T_5488 = eq(perr_ic_index_ff, UInt<5>("h016")) @[ifu_mem_ctl.scala 693:102] + node _T_5489 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_5490 = and(_T_5488, _T_5489) @[ifu_mem_ctl.scala 693:124] + node _T_5491 = or(_T_5487, _T_5490) @[ifu_mem_ctl.scala 693:81] + node _T_5492 = or(_T_5491, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5493 = bits(_T_5492, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5494 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5493 : @[Reg.scala 28:19] _T_5494 <= _T_5484 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][22] <= _T_5494 @[ifu_mem_ctl.scala 693:41] - node _T_5495 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5496 = eq(_T_5495, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5497 = and(ic_valid_ff, _T_5496) @[ifu_mem_ctl.scala 693:97] - node _T_5498 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5499 = and(_T_5497, _T_5498) @[ifu_mem_ctl.scala 693:122] - node _T_5500 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[ifu_mem_ctl.scala 694:37] - node _T_5501 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_5502 = and(_T_5500, _T_5501) @[ifu_mem_ctl.scala 694:59] - node _T_5503 = eq(perr_ic_index_ff, UInt<5>("h017")) @[ifu_mem_ctl.scala 694:102] - node _T_5504 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_5505 = and(_T_5503, _T_5504) @[ifu_mem_ctl.scala 694:124] - node _T_5506 = or(_T_5502, _T_5505) @[ifu_mem_ctl.scala 694:81] - node _T_5507 = or(_T_5506, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5508 = bits(_T_5507, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][22] <= _T_5494 @[ifu_mem_ctl.scala 692:41] + node _T_5495 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5496 = eq(_T_5495, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5497 = and(ic_valid_ff, _T_5496) @[ifu_mem_ctl.scala 692:97] + node _T_5498 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5499 = and(_T_5497, _T_5498) @[ifu_mem_ctl.scala 692:122] + node _T_5500 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[ifu_mem_ctl.scala 693:37] + node _T_5501 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_5502 = and(_T_5500, _T_5501) @[ifu_mem_ctl.scala 693:59] + node _T_5503 = eq(perr_ic_index_ff, UInt<5>("h017")) @[ifu_mem_ctl.scala 693:102] + node _T_5504 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_5505 = and(_T_5503, _T_5504) @[ifu_mem_ctl.scala 693:124] + node _T_5506 = or(_T_5502, _T_5505) @[ifu_mem_ctl.scala 693:81] + node _T_5507 = or(_T_5506, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5508 = bits(_T_5507, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5509 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5508 : @[Reg.scala 28:19] _T_5509 <= _T_5499 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][23] <= _T_5509 @[ifu_mem_ctl.scala 693:41] - node _T_5510 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5511 = eq(_T_5510, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5512 = and(ic_valid_ff, _T_5511) @[ifu_mem_ctl.scala 693:97] - node _T_5513 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5514 = and(_T_5512, _T_5513) @[ifu_mem_ctl.scala 693:122] - node _T_5515 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[ifu_mem_ctl.scala 694:37] - node _T_5516 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_5517 = and(_T_5515, _T_5516) @[ifu_mem_ctl.scala 694:59] - node _T_5518 = eq(perr_ic_index_ff, UInt<5>("h018")) @[ifu_mem_ctl.scala 694:102] - node _T_5519 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_5520 = and(_T_5518, _T_5519) @[ifu_mem_ctl.scala 694:124] - node _T_5521 = or(_T_5517, _T_5520) @[ifu_mem_ctl.scala 694:81] - node _T_5522 = or(_T_5521, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5523 = bits(_T_5522, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][23] <= _T_5509 @[ifu_mem_ctl.scala 692:41] + node _T_5510 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5511 = eq(_T_5510, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5512 = and(ic_valid_ff, _T_5511) @[ifu_mem_ctl.scala 692:97] + node _T_5513 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5514 = and(_T_5512, _T_5513) @[ifu_mem_ctl.scala 692:122] + node _T_5515 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[ifu_mem_ctl.scala 693:37] + node _T_5516 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_5517 = and(_T_5515, _T_5516) @[ifu_mem_ctl.scala 693:59] + node _T_5518 = eq(perr_ic_index_ff, UInt<5>("h018")) @[ifu_mem_ctl.scala 693:102] + node _T_5519 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_5520 = and(_T_5518, _T_5519) @[ifu_mem_ctl.scala 693:124] + node _T_5521 = or(_T_5517, _T_5520) @[ifu_mem_ctl.scala 693:81] + node _T_5522 = or(_T_5521, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5523 = bits(_T_5522, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5524 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5523 : @[Reg.scala 28:19] _T_5524 <= _T_5514 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][24] <= _T_5524 @[ifu_mem_ctl.scala 693:41] - node _T_5525 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5526 = eq(_T_5525, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5527 = and(ic_valid_ff, _T_5526) @[ifu_mem_ctl.scala 693:97] - node _T_5528 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5529 = and(_T_5527, _T_5528) @[ifu_mem_ctl.scala 693:122] - node _T_5530 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[ifu_mem_ctl.scala 694:37] - node _T_5531 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_5532 = and(_T_5530, _T_5531) @[ifu_mem_ctl.scala 694:59] - node _T_5533 = eq(perr_ic_index_ff, UInt<5>("h019")) @[ifu_mem_ctl.scala 694:102] - node _T_5534 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_5535 = and(_T_5533, _T_5534) @[ifu_mem_ctl.scala 694:124] - node _T_5536 = or(_T_5532, _T_5535) @[ifu_mem_ctl.scala 694:81] - node _T_5537 = or(_T_5536, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5538 = bits(_T_5537, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][24] <= _T_5524 @[ifu_mem_ctl.scala 692:41] + node _T_5525 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5526 = eq(_T_5525, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5527 = and(ic_valid_ff, _T_5526) @[ifu_mem_ctl.scala 692:97] + node _T_5528 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5529 = and(_T_5527, _T_5528) @[ifu_mem_ctl.scala 692:122] + node _T_5530 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[ifu_mem_ctl.scala 693:37] + node _T_5531 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_5532 = and(_T_5530, _T_5531) @[ifu_mem_ctl.scala 693:59] + node _T_5533 = eq(perr_ic_index_ff, UInt<5>("h019")) @[ifu_mem_ctl.scala 693:102] + node _T_5534 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_5535 = and(_T_5533, _T_5534) @[ifu_mem_ctl.scala 693:124] + node _T_5536 = or(_T_5532, _T_5535) @[ifu_mem_ctl.scala 693:81] + node _T_5537 = or(_T_5536, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5538 = bits(_T_5537, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5539 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5538 : @[Reg.scala 28:19] _T_5539 <= _T_5529 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][25] <= _T_5539 @[ifu_mem_ctl.scala 693:41] - node _T_5540 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5541 = eq(_T_5540, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5542 = and(ic_valid_ff, _T_5541) @[ifu_mem_ctl.scala 693:97] - node _T_5543 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5544 = and(_T_5542, _T_5543) @[ifu_mem_ctl.scala 693:122] - node _T_5545 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[ifu_mem_ctl.scala 694:37] - node _T_5546 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_5547 = and(_T_5545, _T_5546) @[ifu_mem_ctl.scala 694:59] - node _T_5548 = eq(perr_ic_index_ff, UInt<5>("h01a")) @[ifu_mem_ctl.scala 694:102] - node _T_5549 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_5550 = and(_T_5548, _T_5549) @[ifu_mem_ctl.scala 694:124] - node _T_5551 = or(_T_5547, _T_5550) @[ifu_mem_ctl.scala 694:81] - node _T_5552 = or(_T_5551, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5553 = bits(_T_5552, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][25] <= _T_5539 @[ifu_mem_ctl.scala 692:41] + node _T_5540 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5541 = eq(_T_5540, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5542 = and(ic_valid_ff, _T_5541) @[ifu_mem_ctl.scala 692:97] + node _T_5543 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5544 = and(_T_5542, _T_5543) @[ifu_mem_ctl.scala 692:122] + node _T_5545 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[ifu_mem_ctl.scala 693:37] + node _T_5546 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_5547 = and(_T_5545, _T_5546) @[ifu_mem_ctl.scala 693:59] + node _T_5548 = eq(perr_ic_index_ff, UInt<5>("h01a")) @[ifu_mem_ctl.scala 693:102] + node _T_5549 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_5550 = and(_T_5548, _T_5549) @[ifu_mem_ctl.scala 693:124] + node _T_5551 = or(_T_5547, _T_5550) @[ifu_mem_ctl.scala 693:81] + node _T_5552 = or(_T_5551, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5553 = bits(_T_5552, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5554 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5553 : @[Reg.scala 28:19] _T_5554 <= _T_5544 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][26] <= _T_5554 @[ifu_mem_ctl.scala 693:41] - node _T_5555 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5556 = eq(_T_5555, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5557 = and(ic_valid_ff, _T_5556) @[ifu_mem_ctl.scala 693:97] - node _T_5558 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5559 = and(_T_5557, _T_5558) @[ifu_mem_ctl.scala 693:122] - node _T_5560 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[ifu_mem_ctl.scala 694:37] - node _T_5561 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_5562 = and(_T_5560, _T_5561) @[ifu_mem_ctl.scala 694:59] - node _T_5563 = eq(perr_ic_index_ff, UInt<5>("h01b")) @[ifu_mem_ctl.scala 694:102] - node _T_5564 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_5565 = and(_T_5563, _T_5564) @[ifu_mem_ctl.scala 694:124] - node _T_5566 = or(_T_5562, _T_5565) @[ifu_mem_ctl.scala 694:81] - node _T_5567 = or(_T_5566, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5568 = bits(_T_5567, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][26] <= _T_5554 @[ifu_mem_ctl.scala 692:41] + node _T_5555 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5556 = eq(_T_5555, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5557 = and(ic_valid_ff, _T_5556) @[ifu_mem_ctl.scala 692:97] + node _T_5558 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5559 = and(_T_5557, _T_5558) @[ifu_mem_ctl.scala 692:122] + node _T_5560 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[ifu_mem_ctl.scala 693:37] + node _T_5561 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_5562 = and(_T_5560, _T_5561) @[ifu_mem_ctl.scala 693:59] + node _T_5563 = eq(perr_ic_index_ff, UInt<5>("h01b")) @[ifu_mem_ctl.scala 693:102] + node _T_5564 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_5565 = and(_T_5563, _T_5564) @[ifu_mem_ctl.scala 693:124] + node _T_5566 = or(_T_5562, _T_5565) @[ifu_mem_ctl.scala 693:81] + node _T_5567 = or(_T_5566, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5568 = bits(_T_5567, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5569 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5568 : @[Reg.scala 28:19] _T_5569 <= _T_5559 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][27] <= _T_5569 @[ifu_mem_ctl.scala 693:41] - node _T_5570 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5571 = eq(_T_5570, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5572 = and(ic_valid_ff, _T_5571) @[ifu_mem_ctl.scala 693:97] - node _T_5573 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5574 = and(_T_5572, _T_5573) @[ifu_mem_ctl.scala 693:122] - node _T_5575 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[ifu_mem_ctl.scala 694:37] - node _T_5576 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_5577 = and(_T_5575, _T_5576) @[ifu_mem_ctl.scala 694:59] - node _T_5578 = eq(perr_ic_index_ff, UInt<5>("h01c")) @[ifu_mem_ctl.scala 694:102] - node _T_5579 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_5580 = and(_T_5578, _T_5579) @[ifu_mem_ctl.scala 694:124] - node _T_5581 = or(_T_5577, _T_5580) @[ifu_mem_ctl.scala 694:81] - node _T_5582 = or(_T_5581, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5583 = bits(_T_5582, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][27] <= _T_5569 @[ifu_mem_ctl.scala 692:41] + node _T_5570 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5571 = eq(_T_5570, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5572 = and(ic_valid_ff, _T_5571) @[ifu_mem_ctl.scala 692:97] + node _T_5573 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5574 = and(_T_5572, _T_5573) @[ifu_mem_ctl.scala 692:122] + node _T_5575 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[ifu_mem_ctl.scala 693:37] + node _T_5576 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_5577 = and(_T_5575, _T_5576) @[ifu_mem_ctl.scala 693:59] + node _T_5578 = eq(perr_ic_index_ff, UInt<5>("h01c")) @[ifu_mem_ctl.scala 693:102] + node _T_5579 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_5580 = and(_T_5578, _T_5579) @[ifu_mem_ctl.scala 693:124] + node _T_5581 = or(_T_5577, _T_5580) @[ifu_mem_ctl.scala 693:81] + node _T_5582 = or(_T_5581, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5583 = bits(_T_5582, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5584 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5583 : @[Reg.scala 28:19] _T_5584 <= _T_5574 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][28] <= _T_5584 @[ifu_mem_ctl.scala 693:41] - node _T_5585 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5586 = eq(_T_5585, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5587 = and(ic_valid_ff, _T_5586) @[ifu_mem_ctl.scala 693:97] - node _T_5588 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5589 = and(_T_5587, _T_5588) @[ifu_mem_ctl.scala 693:122] - node _T_5590 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[ifu_mem_ctl.scala 694:37] - node _T_5591 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_5592 = and(_T_5590, _T_5591) @[ifu_mem_ctl.scala 694:59] - node _T_5593 = eq(perr_ic_index_ff, UInt<5>("h01d")) @[ifu_mem_ctl.scala 694:102] - node _T_5594 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_5595 = and(_T_5593, _T_5594) @[ifu_mem_ctl.scala 694:124] - node _T_5596 = or(_T_5592, _T_5595) @[ifu_mem_ctl.scala 694:81] - node _T_5597 = or(_T_5596, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5598 = bits(_T_5597, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][28] <= _T_5584 @[ifu_mem_ctl.scala 692:41] + node _T_5585 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5586 = eq(_T_5585, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5587 = and(ic_valid_ff, _T_5586) @[ifu_mem_ctl.scala 692:97] + node _T_5588 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5589 = and(_T_5587, _T_5588) @[ifu_mem_ctl.scala 692:122] + node _T_5590 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[ifu_mem_ctl.scala 693:37] + node _T_5591 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_5592 = and(_T_5590, _T_5591) @[ifu_mem_ctl.scala 693:59] + node _T_5593 = eq(perr_ic_index_ff, UInt<5>("h01d")) @[ifu_mem_ctl.scala 693:102] + node _T_5594 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_5595 = and(_T_5593, _T_5594) @[ifu_mem_ctl.scala 693:124] + node _T_5596 = or(_T_5592, _T_5595) @[ifu_mem_ctl.scala 693:81] + node _T_5597 = or(_T_5596, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5598 = bits(_T_5597, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5599 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5598 : @[Reg.scala 28:19] _T_5599 <= _T_5589 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][29] <= _T_5599 @[ifu_mem_ctl.scala 693:41] - node _T_5600 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5601 = eq(_T_5600, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5602 = and(ic_valid_ff, _T_5601) @[ifu_mem_ctl.scala 693:97] - node _T_5603 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5604 = and(_T_5602, _T_5603) @[ifu_mem_ctl.scala 693:122] - node _T_5605 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[ifu_mem_ctl.scala 694:37] - node _T_5606 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_5607 = and(_T_5605, _T_5606) @[ifu_mem_ctl.scala 694:59] - node _T_5608 = eq(perr_ic_index_ff, UInt<5>("h01e")) @[ifu_mem_ctl.scala 694:102] - node _T_5609 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_5610 = and(_T_5608, _T_5609) @[ifu_mem_ctl.scala 694:124] - node _T_5611 = or(_T_5607, _T_5610) @[ifu_mem_ctl.scala 694:81] - node _T_5612 = or(_T_5611, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5613 = bits(_T_5612, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][29] <= _T_5599 @[ifu_mem_ctl.scala 692:41] + node _T_5600 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5601 = eq(_T_5600, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5602 = and(ic_valid_ff, _T_5601) @[ifu_mem_ctl.scala 692:97] + node _T_5603 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5604 = and(_T_5602, _T_5603) @[ifu_mem_ctl.scala 692:122] + node _T_5605 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[ifu_mem_ctl.scala 693:37] + node _T_5606 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_5607 = and(_T_5605, _T_5606) @[ifu_mem_ctl.scala 693:59] + node _T_5608 = eq(perr_ic_index_ff, UInt<5>("h01e")) @[ifu_mem_ctl.scala 693:102] + node _T_5609 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_5610 = and(_T_5608, _T_5609) @[ifu_mem_ctl.scala 693:124] + node _T_5611 = or(_T_5607, _T_5610) @[ifu_mem_ctl.scala 693:81] + node _T_5612 = or(_T_5611, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5613 = bits(_T_5612, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5614 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5613 : @[Reg.scala 28:19] _T_5614 <= _T_5604 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][30] <= _T_5614 @[ifu_mem_ctl.scala 693:41] - node _T_5615 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5616 = eq(_T_5615, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5617 = and(ic_valid_ff, _T_5616) @[ifu_mem_ctl.scala 693:97] - node _T_5618 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5619 = and(_T_5617, _T_5618) @[ifu_mem_ctl.scala 693:122] - node _T_5620 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[ifu_mem_ctl.scala 694:37] - node _T_5621 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_5622 = and(_T_5620, _T_5621) @[ifu_mem_ctl.scala 694:59] - node _T_5623 = eq(perr_ic_index_ff, UInt<5>("h01f")) @[ifu_mem_ctl.scala 694:102] - node _T_5624 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_5625 = and(_T_5623, _T_5624) @[ifu_mem_ctl.scala 694:124] - node _T_5626 = or(_T_5622, _T_5625) @[ifu_mem_ctl.scala 694:81] - node _T_5627 = or(_T_5626, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5628 = bits(_T_5627, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][30] <= _T_5614 @[ifu_mem_ctl.scala 692:41] + node _T_5615 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5616 = eq(_T_5615, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5617 = and(ic_valid_ff, _T_5616) @[ifu_mem_ctl.scala 692:97] + node _T_5618 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5619 = and(_T_5617, _T_5618) @[ifu_mem_ctl.scala 692:122] + node _T_5620 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[ifu_mem_ctl.scala 693:37] + node _T_5621 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_5622 = and(_T_5620, _T_5621) @[ifu_mem_ctl.scala 693:59] + node _T_5623 = eq(perr_ic_index_ff, UInt<5>("h01f")) @[ifu_mem_ctl.scala 693:102] + node _T_5624 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_5625 = and(_T_5623, _T_5624) @[ifu_mem_ctl.scala 693:124] + node _T_5626 = or(_T_5622, _T_5625) @[ifu_mem_ctl.scala 693:81] + node _T_5627 = or(_T_5626, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5628 = bits(_T_5627, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5629 : UInt<1>, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5628 : @[Reg.scala 28:19] _T_5629 <= _T_5619 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][31] <= _T_5629 @[ifu_mem_ctl.scala 693:41] - node _T_5630 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5631 = eq(_T_5630, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5632 = and(ic_valid_ff, _T_5631) @[ifu_mem_ctl.scala 693:97] - node _T_5633 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5634 = and(_T_5632, _T_5633) @[ifu_mem_ctl.scala 693:122] - node _T_5635 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 694:37] - node _T_5636 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_5637 = and(_T_5635, _T_5636) @[ifu_mem_ctl.scala 694:59] - node _T_5638 = eq(perr_ic_index_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 694:102] - node _T_5639 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_5640 = and(_T_5638, _T_5639) @[ifu_mem_ctl.scala 694:124] - node _T_5641 = or(_T_5637, _T_5640) @[ifu_mem_ctl.scala 694:81] - node _T_5642 = or(_T_5641, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5643 = bits(_T_5642, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][31] <= _T_5629 @[ifu_mem_ctl.scala 692:41] + node _T_5630 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5631 = eq(_T_5630, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5632 = and(ic_valid_ff, _T_5631) @[ifu_mem_ctl.scala 692:97] + node _T_5633 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5634 = and(_T_5632, _T_5633) @[ifu_mem_ctl.scala 692:122] + node _T_5635 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:37] + node _T_5636 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_5637 = and(_T_5635, _T_5636) @[ifu_mem_ctl.scala 693:59] + node _T_5638 = eq(perr_ic_index_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:102] + node _T_5639 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_5640 = and(_T_5638, _T_5639) @[ifu_mem_ctl.scala 693:124] + node _T_5641 = or(_T_5637, _T_5640) @[ifu_mem_ctl.scala 693:81] + node _T_5642 = or(_T_5641, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5643 = bits(_T_5642, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5644 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5643 : @[Reg.scala 28:19] _T_5644 <= _T_5634 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][0] <= _T_5644 @[ifu_mem_ctl.scala 693:41] - node _T_5645 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5646 = eq(_T_5645, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5647 = and(ic_valid_ff, _T_5646) @[ifu_mem_ctl.scala 693:97] - node _T_5648 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5649 = and(_T_5647, _T_5648) @[ifu_mem_ctl.scala 693:122] - node _T_5650 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[ifu_mem_ctl.scala 694:37] - node _T_5651 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_5652 = and(_T_5650, _T_5651) @[ifu_mem_ctl.scala 694:59] - node _T_5653 = eq(perr_ic_index_ff, UInt<1>("h01")) @[ifu_mem_ctl.scala 694:102] - node _T_5654 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_5655 = and(_T_5653, _T_5654) @[ifu_mem_ctl.scala 694:124] - node _T_5656 = or(_T_5652, _T_5655) @[ifu_mem_ctl.scala 694:81] - node _T_5657 = or(_T_5656, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5658 = bits(_T_5657, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][0] <= _T_5644 @[ifu_mem_ctl.scala 692:41] + node _T_5645 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5646 = eq(_T_5645, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5647 = and(ic_valid_ff, _T_5646) @[ifu_mem_ctl.scala 692:97] + node _T_5648 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5649 = and(_T_5647, _T_5648) @[ifu_mem_ctl.scala 692:122] + node _T_5650 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[ifu_mem_ctl.scala 693:37] + node _T_5651 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_5652 = and(_T_5650, _T_5651) @[ifu_mem_ctl.scala 693:59] + node _T_5653 = eq(perr_ic_index_ff, UInt<1>("h01")) @[ifu_mem_ctl.scala 693:102] + node _T_5654 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_5655 = and(_T_5653, _T_5654) @[ifu_mem_ctl.scala 693:124] + node _T_5656 = or(_T_5652, _T_5655) @[ifu_mem_ctl.scala 693:81] + node _T_5657 = or(_T_5656, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5658 = bits(_T_5657, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5659 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5658 : @[Reg.scala 28:19] _T_5659 <= _T_5649 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][1] <= _T_5659 @[ifu_mem_ctl.scala 693:41] - node _T_5660 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5661 = eq(_T_5660, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5662 = and(ic_valid_ff, _T_5661) @[ifu_mem_ctl.scala 693:97] - node _T_5663 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5664 = and(_T_5662, _T_5663) @[ifu_mem_ctl.scala 693:122] - node _T_5665 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[ifu_mem_ctl.scala 694:37] - node _T_5666 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_5667 = and(_T_5665, _T_5666) @[ifu_mem_ctl.scala 694:59] - node _T_5668 = eq(perr_ic_index_ff, UInt<2>("h02")) @[ifu_mem_ctl.scala 694:102] - node _T_5669 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_5670 = and(_T_5668, _T_5669) @[ifu_mem_ctl.scala 694:124] - node _T_5671 = or(_T_5667, _T_5670) @[ifu_mem_ctl.scala 694:81] - node _T_5672 = or(_T_5671, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5673 = bits(_T_5672, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][1] <= _T_5659 @[ifu_mem_ctl.scala 692:41] + node _T_5660 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5661 = eq(_T_5660, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5662 = and(ic_valid_ff, _T_5661) @[ifu_mem_ctl.scala 692:97] + node _T_5663 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5664 = and(_T_5662, _T_5663) @[ifu_mem_ctl.scala 692:122] + node _T_5665 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[ifu_mem_ctl.scala 693:37] + node _T_5666 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_5667 = and(_T_5665, _T_5666) @[ifu_mem_ctl.scala 693:59] + node _T_5668 = eq(perr_ic_index_ff, UInt<2>("h02")) @[ifu_mem_ctl.scala 693:102] + node _T_5669 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_5670 = and(_T_5668, _T_5669) @[ifu_mem_ctl.scala 693:124] + node _T_5671 = or(_T_5667, _T_5670) @[ifu_mem_ctl.scala 693:81] + node _T_5672 = or(_T_5671, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5673 = bits(_T_5672, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5674 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5673 : @[Reg.scala 28:19] _T_5674 <= _T_5664 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][2] <= _T_5674 @[ifu_mem_ctl.scala 693:41] - node _T_5675 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5676 = eq(_T_5675, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5677 = and(ic_valid_ff, _T_5676) @[ifu_mem_ctl.scala 693:97] - node _T_5678 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5679 = and(_T_5677, _T_5678) @[ifu_mem_ctl.scala 693:122] - node _T_5680 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[ifu_mem_ctl.scala 694:37] - node _T_5681 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_5682 = and(_T_5680, _T_5681) @[ifu_mem_ctl.scala 694:59] - node _T_5683 = eq(perr_ic_index_ff, UInt<2>("h03")) @[ifu_mem_ctl.scala 694:102] - node _T_5684 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_5685 = and(_T_5683, _T_5684) @[ifu_mem_ctl.scala 694:124] - node _T_5686 = or(_T_5682, _T_5685) @[ifu_mem_ctl.scala 694:81] - node _T_5687 = or(_T_5686, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5688 = bits(_T_5687, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][2] <= _T_5674 @[ifu_mem_ctl.scala 692:41] + node _T_5675 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5676 = eq(_T_5675, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5677 = and(ic_valid_ff, _T_5676) @[ifu_mem_ctl.scala 692:97] + node _T_5678 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5679 = and(_T_5677, _T_5678) @[ifu_mem_ctl.scala 692:122] + node _T_5680 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[ifu_mem_ctl.scala 693:37] + node _T_5681 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_5682 = and(_T_5680, _T_5681) @[ifu_mem_ctl.scala 693:59] + node _T_5683 = eq(perr_ic_index_ff, UInt<2>("h03")) @[ifu_mem_ctl.scala 693:102] + node _T_5684 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_5685 = and(_T_5683, _T_5684) @[ifu_mem_ctl.scala 693:124] + node _T_5686 = or(_T_5682, _T_5685) @[ifu_mem_ctl.scala 693:81] + node _T_5687 = or(_T_5686, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5688 = bits(_T_5687, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5689 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5688 : @[Reg.scala 28:19] _T_5689 <= _T_5679 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][3] <= _T_5689 @[ifu_mem_ctl.scala 693:41] - node _T_5690 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5691 = eq(_T_5690, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5692 = and(ic_valid_ff, _T_5691) @[ifu_mem_ctl.scala 693:97] - node _T_5693 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5694 = and(_T_5692, _T_5693) @[ifu_mem_ctl.scala 693:122] - node _T_5695 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[ifu_mem_ctl.scala 694:37] - node _T_5696 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_5697 = and(_T_5695, _T_5696) @[ifu_mem_ctl.scala 694:59] - node _T_5698 = eq(perr_ic_index_ff, UInt<3>("h04")) @[ifu_mem_ctl.scala 694:102] - node _T_5699 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_5700 = and(_T_5698, _T_5699) @[ifu_mem_ctl.scala 694:124] - node _T_5701 = or(_T_5697, _T_5700) @[ifu_mem_ctl.scala 694:81] - node _T_5702 = or(_T_5701, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5703 = bits(_T_5702, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][3] <= _T_5689 @[ifu_mem_ctl.scala 692:41] + node _T_5690 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5691 = eq(_T_5690, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5692 = and(ic_valid_ff, _T_5691) @[ifu_mem_ctl.scala 692:97] + node _T_5693 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5694 = and(_T_5692, _T_5693) @[ifu_mem_ctl.scala 692:122] + node _T_5695 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[ifu_mem_ctl.scala 693:37] + node _T_5696 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_5697 = and(_T_5695, _T_5696) @[ifu_mem_ctl.scala 693:59] + node _T_5698 = eq(perr_ic_index_ff, UInt<3>("h04")) @[ifu_mem_ctl.scala 693:102] + node _T_5699 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_5700 = and(_T_5698, _T_5699) @[ifu_mem_ctl.scala 693:124] + node _T_5701 = or(_T_5697, _T_5700) @[ifu_mem_ctl.scala 693:81] + node _T_5702 = or(_T_5701, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5703 = bits(_T_5702, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5704 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5703 : @[Reg.scala 28:19] _T_5704 <= _T_5694 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][4] <= _T_5704 @[ifu_mem_ctl.scala 693:41] - node _T_5705 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5706 = eq(_T_5705, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5707 = and(ic_valid_ff, _T_5706) @[ifu_mem_ctl.scala 693:97] - node _T_5708 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5709 = and(_T_5707, _T_5708) @[ifu_mem_ctl.scala 693:122] - node _T_5710 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[ifu_mem_ctl.scala 694:37] - node _T_5711 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_5712 = and(_T_5710, _T_5711) @[ifu_mem_ctl.scala 694:59] - node _T_5713 = eq(perr_ic_index_ff, UInt<3>("h05")) @[ifu_mem_ctl.scala 694:102] - node _T_5714 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_5715 = and(_T_5713, _T_5714) @[ifu_mem_ctl.scala 694:124] - node _T_5716 = or(_T_5712, _T_5715) @[ifu_mem_ctl.scala 694:81] - node _T_5717 = or(_T_5716, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5718 = bits(_T_5717, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][4] <= _T_5704 @[ifu_mem_ctl.scala 692:41] + node _T_5705 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5706 = eq(_T_5705, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5707 = and(ic_valid_ff, _T_5706) @[ifu_mem_ctl.scala 692:97] + node _T_5708 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5709 = and(_T_5707, _T_5708) @[ifu_mem_ctl.scala 692:122] + node _T_5710 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[ifu_mem_ctl.scala 693:37] + node _T_5711 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_5712 = and(_T_5710, _T_5711) @[ifu_mem_ctl.scala 693:59] + node _T_5713 = eq(perr_ic_index_ff, UInt<3>("h05")) @[ifu_mem_ctl.scala 693:102] + node _T_5714 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_5715 = and(_T_5713, _T_5714) @[ifu_mem_ctl.scala 693:124] + node _T_5716 = or(_T_5712, _T_5715) @[ifu_mem_ctl.scala 693:81] + node _T_5717 = or(_T_5716, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5718 = bits(_T_5717, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5719 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5718 : @[Reg.scala 28:19] _T_5719 <= _T_5709 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][5] <= _T_5719 @[ifu_mem_ctl.scala 693:41] - node _T_5720 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5721 = eq(_T_5720, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5722 = and(ic_valid_ff, _T_5721) @[ifu_mem_ctl.scala 693:97] - node _T_5723 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5724 = and(_T_5722, _T_5723) @[ifu_mem_ctl.scala 693:122] - node _T_5725 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[ifu_mem_ctl.scala 694:37] - node _T_5726 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_5727 = and(_T_5725, _T_5726) @[ifu_mem_ctl.scala 694:59] - node _T_5728 = eq(perr_ic_index_ff, UInt<3>("h06")) @[ifu_mem_ctl.scala 694:102] - node _T_5729 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_5730 = and(_T_5728, _T_5729) @[ifu_mem_ctl.scala 694:124] - node _T_5731 = or(_T_5727, _T_5730) @[ifu_mem_ctl.scala 694:81] - node _T_5732 = or(_T_5731, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5733 = bits(_T_5732, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][5] <= _T_5719 @[ifu_mem_ctl.scala 692:41] + node _T_5720 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5721 = eq(_T_5720, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5722 = and(ic_valid_ff, _T_5721) @[ifu_mem_ctl.scala 692:97] + node _T_5723 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5724 = and(_T_5722, _T_5723) @[ifu_mem_ctl.scala 692:122] + node _T_5725 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[ifu_mem_ctl.scala 693:37] + node _T_5726 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_5727 = and(_T_5725, _T_5726) @[ifu_mem_ctl.scala 693:59] + node _T_5728 = eq(perr_ic_index_ff, UInt<3>("h06")) @[ifu_mem_ctl.scala 693:102] + node _T_5729 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_5730 = and(_T_5728, _T_5729) @[ifu_mem_ctl.scala 693:124] + node _T_5731 = or(_T_5727, _T_5730) @[ifu_mem_ctl.scala 693:81] + node _T_5732 = or(_T_5731, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5733 = bits(_T_5732, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5734 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5733 : @[Reg.scala 28:19] _T_5734 <= _T_5724 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][6] <= _T_5734 @[ifu_mem_ctl.scala 693:41] - node _T_5735 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5736 = eq(_T_5735, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5737 = and(ic_valid_ff, _T_5736) @[ifu_mem_ctl.scala 693:97] - node _T_5738 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5739 = and(_T_5737, _T_5738) @[ifu_mem_ctl.scala 693:122] - node _T_5740 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[ifu_mem_ctl.scala 694:37] - node _T_5741 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_5742 = and(_T_5740, _T_5741) @[ifu_mem_ctl.scala 694:59] - node _T_5743 = eq(perr_ic_index_ff, UInt<3>("h07")) @[ifu_mem_ctl.scala 694:102] - node _T_5744 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_5745 = and(_T_5743, _T_5744) @[ifu_mem_ctl.scala 694:124] - node _T_5746 = or(_T_5742, _T_5745) @[ifu_mem_ctl.scala 694:81] - node _T_5747 = or(_T_5746, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5748 = bits(_T_5747, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][6] <= _T_5734 @[ifu_mem_ctl.scala 692:41] + node _T_5735 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5736 = eq(_T_5735, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5737 = and(ic_valid_ff, _T_5736) @[ifu_mem_ctl.scala 692:97] + node _T_5738 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5739 = and(_T_5737, _T_5738) @[ifu_mem_ctl.scala 692:122] + node _T_5740 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[ifu_mem_ctl.scala 693:37] + node _T_5741 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_5742 = and(_T_5740, _T_5741) @[ifu_mem_ctl.scala 693:59] + node _T_5743 = eq(perr_ic_index_ff, UInt<3>("h07")) @[ifu_mem_ctl.scala 693:102] + node _T_5744 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_5745 = and(_T_5743, _T_5744) @[ifu_mem_ctl.scala 693:124] + node _T_5746 = or(_T_5742, _T_5745) @[ifu_mem_ctl.scala 693:81] + node _T_5747 = or(_T_5746, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5748 = bits(_T_5747, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5749 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5748 : @[Reg.scala 28:19] _T_5749 <= _T_5739 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][7] <= _T_5749 @[ifu_mem_ctl.scala 693:41] - node _T_5750 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5751 = eq(_T_5750, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5752 = and(ic_valid_ff, _T_5751) @[ifu_mem_ctl.scala 693:97] - node _T_5753 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5754 = and(_T_5752, _T_5753) @[ifu_mem_ctl.scala 693:122] - node _T_5755 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[ifu_mem_ctl.scala 694:37] - node _T_5756 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_5757 = and(_T_5755, _T_5756) @[ifu_mem_ctl.scala 694:59] - node _T_5758 = eq(perr_ic_index_ff, UInt<4>("h08")) @[ifu_mem_ctl.scala 694:102] - node _T_5759 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_5760 = and(_T_5758, _T_5759) @[ifu_mem_ctl.scala 694:124] - node _T_5761 = or(_T_5757, _T_5760) @[ifu_mem_ctl.scala 694:81] - node _T_5762 = or(_T_5761, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5763 = bits(_T_5762, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][7] <= _T_5749 @[ifu_mem_ctl.scala 692:41] + node _T_5750 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5751 = eq(_T_5750, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5752 = and(ic_valid_ff, _T_5751) @[ifu_mem_ctl.scala 692:97] + node _T_5753 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5754 = and(_T_5752, _T_5753) @[ifu_mem_ctl.scala 692:122] + node _T_5755 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[ifu_mem_ctl.scala 693:37] + node _T_5756 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_5757 = and(_T_5755, _T_5756) @[ifu_mem_ctl.scala 693:59] + node _T_5758 = eq(perr_ic_index_ff, UInt<4>("h08")) @[ifu_mem_ctl.scala 693:102] + node _T_5759 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_5760 = and(_T_5758, _T_5759) @[ifu_mem_ctl.scala 693:124] + node _T_5761 = or(_T_5757, _T_5760) @[ifu_mem_ctl.scala 693:81] + node _T_5762 = or(_T_5761, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5763 = bits(_T_5762, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5764 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5763 : @[Reg.scala 28:19] _T_5764 <= _T_5754 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][8] <= _T_5764 @[ifu_mem_ctl.scala 693:41] - node _T_5765 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5766 = eq(_T_5765, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5767 = and(ic_valid_ff, _T_5766) @[ifu_mem_ctl.scala 693:97] - node _T_5768 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5769 = and(_T_5767, _T_5768) @[ifu_mem_ctl.scala 693:122] - node _T_5770 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[ifu_mem_ctl.scala 694:37] - node _T_5771 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_5772 = and(_T_5770, _T_5771) @[ifu_mem_ctl.scala 694:59] - node _T_5773 = eq(perr_ic_index_ff, UInt<4>("h09")) @[ifu_mem_ctl.scala 694:102] - node _T_5774 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_5775 = and(_T_5773, _T_5774) @[ifu_mem_ctl.scala 694:124] - node _T_5776 = or(_T_5772, _T_5775) @[ifu_mem_ctl.scala 694:81] - node _T_5777 = or(_T_5776, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5778 = bits(_T_5777, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][8] <= _T_5764 @[ifu_mem_ctl.scala 692:41] + node _T_5765 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5766 = eq(_T_5765, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5767 = and(ic_valid_ff, _T_5766) @[ifu_mem_ctl.scala 692:97] + node _T_5768 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5769 = and(_T_5767, _T_5768) @[ifu_mem_ctl.scala 692:122] + node _T_5770 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[ifu_mem_ctl.scala 693:37] + node _T_5771 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_5772 = and(_T_5770, _T_5771) @[ifu_mem_ctl.scala 693:59] + node _T_5773 = eq(perr_ic_index_ff, UInt<4>("h09")) @[ifu_mem_ctl.scala 693:102] + node _T_5774 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_5775 = and(_T_5773, _T_5774) @[ifu_mem_ctl.scala 693:124] + node _T_5776 = or(_T_5772, _T_5775) @[ifu_mem_ctl.scala 693:81] + node _T_5777 = or(_T_5776, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5778 = bits(_T_5777, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5779 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5778 : @[Reg.scala 28:19] _T_5779 <= _T_5769 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][9] <= _T_5779 @[ifu_mem_ctl.scala 693:41] - node _T_5780 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5781 = eq(_T_5780, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5782 = and(ic_valid_ff, _T_5781) @[ifu_mem_ctl.scala 693:97] - node _T_5783 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5784 = and(_T_5782, _T_5783) @[ifu_mem_ctl.scala 693:122] - node _T_5785 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[ifu_mem_ctl.scala 694:37] - node _T_5786 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_5787 = and(_T_5785, _T_5786) @[ifu_mem_ctl.scala 694:59] - node _T_5788 = eq(perr_ic_index_ff, UInt<4>("h0a")) @[ifu_mem_ctl.scala 694:102] - node _T_5789 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_5790 = and(_T_5788, _T_5789) @[ifu_mem_ctl.scala 694:124] - node _T_5791 = or(_T_5787, _T_5790) @[ifu_mem_ctl.scala 694:81] - node _T_5792 = or(_T_5791, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5793 = bits(_T_5792, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][9] <= _T_5779 @[ifu_mem_ctl.scala 692:41] + node _T_5780 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5781 = eq(_T_5780, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5782 = and(ic_valid_ff, _T_5781) @[ifu_mem_ctl.scala 692:97] + node _T_5783 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5784 = and(_T_5782, _T_5783) @[ifu_mem_ctl.scala 692:122] + node _T_5785 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[ifu_mem_ctl.scala 693:37] + node _T_5786 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_5787 = and(_T_5785, _T_5786) @[ifu_mem_ctl.scala 693:59] + node _T_5788 = eq(perr_ic_index_ff, UInt<4>("h0a")) @[ifu_mem_ctl.scala 693:102] + node _T_5789 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_5790 = and(_T_5788, _T_5789) @[ifu_mem_ctl.scala 693:124] + node _T_5791 = or(_T_5787, _T_5790) @[ifu_mem_ctl.scala 693:81] + node _T_5792 = or(_T_5791, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5793 = bits(_T_5792, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5794 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5793 : @[Reg.scala 28:19] _T_5794 <= _T_5784 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][10] <= _T_5794 @[ifu_mem_ctl.scala 693:41] - node _T_5795 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5796 = eq(_T_5795, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5797 = and(ic_valid_ff, _T_5796) @[ifu_mem_ctl.scala 693:97] - node _T_5798 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5799 = and(_T_5797, _T_5798) @[ifu_mem_ctl.scala 693:122] - node _T_5800 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[ifu_mem_ctl.scala 694:37] - node _T_5801 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_5802 = and(_T_5800, _T_5801) @[ifu_mem_ctl.scala 694:59] - node _T_5803 = eq(perr_ic_index_ff, UInt<4>("h0b")) @[ifu_mem_ctl.scala 694:102] - node _T_5804 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_5805 = and(_T_5803, _T_5804) @[ifu_mem_ctl.scala 694:124] - node _T_5806 = or(_T_5802, _T_5805) @[ifu_mem_ctl.scala 694:81] - node _T_5807 = or(_T_5806, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5808 = bits(_T_5807, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][10] <= _T_5794 @[ifu_mem_ctl.scala 692:41] + node _T_5795 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5796 = eq(_T_5795, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5797 = and(ic_valid_ff, _T_5796) @[ifu_mem_ctl.scala 692:97] + node _T_5798 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5799 = and(_T_5797, _T_5798) @[ifu_mem_ctl.scala 692:122] + node _T_5800 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[ifu_mem_ctl.scala 693:37] + node _T_5801 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_5802 = and(_T_5800, _T_5801) @[ifu_mem_ctl.scala 693:59] + node _T_5803 = eq(perr_ic_index_ff, UInt<4>("h0b")) @[ifu_mem_ctl.scala 693:102] + node _T_5804 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_5805 = and(_T_5803, _T_5804) @[ifu_mem_ctl.scala 693:124] + node _T_5806 = or(_T_5802, _T_5805) @[ifu_mem_ctl.scala 693:81] + node _T_5807 = or(_T_5806, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5808 = bits(_T_5807, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5809 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5808 : @[Reg.scala 28:19] _T_5809 <= _T_5799 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][11] <= _T_5809 @[ifu_mem_ctl.scala 693:41] - node _T_5810 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5811 = eq(_T_5810, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5812 = and(ic_valid_ff, _T_5811) @[ifu_mem_ctl.scala 693:97] - node _T_5813 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5814 = and(_T_5812, _T_5813) @[ifu_mem_ctl.scala 693:122] - node _T_5815 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[ifu_mem_ctl.scala 694:37] - node _T_5816 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_5817 = and(_T_5815, _T_5816) @[ifu_mem_ctl.scala 694:59] - node _T_5818 = eq(perr_ic_index_ff, UInt<4>("h0c")) @[ifu_mem_ctl.scala 694:102] - node _T_5819 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_5820 = and(_T_5818, _T_5819) @[ifu_mem_ctl.scala 694:124] - node _T_5821 = or(_T_5817, _T_5820) @[ifu_mem_ctl.scala 694:81] - node _T_5822 = or(_T_5821, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5823 = bits(_T_5822, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][11] <= _T_5809 @[ifu_mem_ctl.scala 692:41] + node _T_5810 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5811 = eq(_T_5810, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5812 = and(ic_valid_ff, _T_5811) @[ifu_mem_ctl.scala 692:97] + node _T_5813 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5814 = and(_T_5812, _T_5813) @[ifu_mem_ctl.scala 692:122] + node _T_5815 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[ifu_mem_ctl.scala 693:37] + node _T_5816 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_5817 = and(_T_5815, _T_5816) @[ifu_mem_ctl.scala 693:59] + node _T_5818 = eq(perr_ic_index_ff, UInt<4>("h0c")) @[ifu_mem_ctl.scala 693:102] + node _T_5819 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_5820 = and(_T_5818, _T_5819) @[ifu_mem_ctl.scala 693:124] + node _T_5821 = or(_T_5817, _T_5820) @[ifu_mem_ctl.scala 693:81] + node _T_5822 = or(_T_5821, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5823 = bits(_T_5822, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5824 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5823 : @[Reg.scala 28:19] _T_5824 <= _T_5814 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][12] <= _T_5824 @[ifu_mem_ctl.scala 693:41] - node _T_5825 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5826 = eq(_T_5825, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5827 = and(ic_valid_ff, _T_5826) @[ifu_mem_ctl.scala 693:97] - node _T_5828 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5829 = and(_T_5827, _T_5828) @[ifu_mem_ctl.scala 693:122] - node _T_5830 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[ifu_mem_ctl.scala 694:37] - node _T_5831 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_5832 = and(_T_5830, _T_5831) @[ifu_mem_ctl.scala 694:59] - node _T_5833 = eq(perr_ic_index_ff, UInt<4>("h0d")) @[ifu_mem_ctl.scala 694:102] - node _T_5834 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_5835 = and(_T_5833, _T_5834) @[ifu_mem_ctl.scala 694:124] - node _T_5836 = or(_T_5832, _T_5835) @[ifu_mem_ctl.scala 694:81] - node _T_5837 = or(_T_5836, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5838 = bits(_T_5837, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][12] <= _T_5824 @[ifu_mem_ctl.scala 692:41] + node _T_5825 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5826 = eq(_T_5825, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5827 = and(ic_valid_ff, _T_5826) @[ifu_mem_ctl.scala 692:97] + node _T_5828 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5829 = and(_T_5827, _T_5828) @[ifu_mem_ctl.scala 692:122] + node _T_5830 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[ifu_mem_ctl.scala 693:37] + node _T_5831 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_5832 = and(_T_5830, _T_5831) @[ifu_mem_ctl.scala 693:59] + node _T_5833 = eq(perr_ic_index_ff, UInt<4>("h0d")) @[ifu_mem_ctl.scala 693:102] + node _T_5834 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_5835 = and(_T_5833, _T_5834) @[ifu_mem_ctl.scala 693:124] + node _T_5836 = or(_T_5832, _T_5835) @[ifu_mem_ctl.scala 693:81] + node _T_5837 = or(_T_5836, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5838 = bits(_T_5837, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5839 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5838 : @[Reg.scala 28:19] _T_5839 <= _T_5829 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][13] <= _T_5839 @[ifu_mem_ctl.scala 693:41] - node _T_5840 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5841 = eq(_T_5840, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5842 = and(ic_valid_ff, _T_5841) @[ifu_mem_ctl.scala 693:97] - node _T_5843 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5844 = and(_T_5842, _T_5843) @[ifu_mem_ctl.scala 693:122] - node _T_5845 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[ifu_mem_ctl.scala 694:37] - node _T_5846 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_5847 = and(_T_5845, _T_5846) @[ifu_mem_ctl.scala 694:59] - node _T_5848 = eq(perr_ic_index_ff, UInt<4>("h0e")) @[ifu_mem_ctl.scala 694:102] - node _T_5849 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_5850 = and(_T_5848, _T_5849) @[ifu_mem_ctl.scala 694:124] - node _T_5851 = or(_T_5847, _T_5850) @[ifu_mem_ctl.scala 694:81] - node _T_5852 = or(_T_5851, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5853 = bits(_T_5852, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][13] <= _T_5839 @[ifu_mem_ctl.scala 692:41] + node _T_5840 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5841 = eq(_T_5840, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5842 = and(ic_valid_ff, _T_5841) @[ifu_mem_ctl.scala 692:97] + node _T_5843 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5844 = and(_T_5842, _T_5843) @[ifu_mem_ctl.scala 692:122] + node _T_5845 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[ifu_mem_ctl.scala 693:37] + node _T_5846 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_5847 = and(_T_5845, _T_5846) @[ifu_mem_ctl.scala 693:59] + node _T_5848 = eq(perr_ic_index_ff, UInt<4>("h0e")) @[ifu_mem_ctl.scala 693:102] + node _T_5849 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_5850 = and(_T_5848, _T_5849) @[ifu_mem_ctl.scala 693:124] + node _T_5851 = or(_T_5847, _T_5850) @[ifu_mem_ctl.scala 693:81] + node _T_5852 = or(_T_5851, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5853 = bits(_T_5852, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5854 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5853 : @[Reg.scala 28:19] _T_5854 <= _T_5844 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][14] <= _T_5854 @[ifu_mem_ctl.scala 693:41] - node _T_5855 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5856 = eq(_T_5855, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5857 = and(ic_valid_ff, _T_5856) @[ifu_mem_ctl.scala 693:97] - node _T_5858 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5859 = and(_T_5857, _T_5858) @[ifu_mem_ctl.scala 693:122] - node _T_5860 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[ifu_mem_ctl.scala 694:37] - node _T_5861 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_5862 = and(_T_5860, _T_5861) @[ifu_mem_ctl.scala 694:59] - node _T_5863 = eq(perr_ic_index_ff, UInt<4>("h0f")) @[ifu_mem_ctl.scala 694:102] - node _T_5864 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_5865 = and(_T_5863, _T_5864) @[ifu_mem_ctl.scala 694:124] - node _T_5866 = or(_T_5862, _T_5865) @[ifu_mem_ctl.scala 694:81] - node _T_5867 = or(_T_5866, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5868 = bits(_T_5867, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][14] <= _T_5854 @[ifu_mem_ctl.scala 692:41] + node _T_5855 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5856 = eq(_T_5855, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5857 = and(ic_valid_ff, _T_5856) @[ifu_mem_ctl.scala 692:97] + node _T_5858 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5859 = and(_T_5857, _T_5858) @[ifu_mem_ctl.scala 692:122] + node _T_5860 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[ifu_mem_ctl.scala 693:37] + node _T_5861 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_5862 = and(_T_5860, _T_5861) @[ifu_mem_ctl.scala 693:59] + node _T_5863 = eq(perr_ic_index_ff, UInt<4>("h0f")) @[ifu_mem_ctl.scala 693:102] + node _T_5864 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_5865 = and(_T_5863, _T_5864) @[ifu_mem_ctl.scala 693:124] + node _T_5866 = or(_T_5862, _T_5865) @[ifu_mem_ctl.scala 693:81] + node _T_5867 = or(_T_5866, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5868 = bits(_T_5867, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5869 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5868 : @[Reg.scala 28:19] _T_5869 <= _T_5859 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][15] <= _T_5869 @[ifu_mem_ctl.scala 693:41] - node _T_5870 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5871 = eq(_T_5870, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5872 = and(ic_valid_ff, _T_5871) @[ifu_mem_ctl.scala 693:97] - node _T_5873 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5874 = and(_T_5872, _T_5873) @[ifu_mem_ctl.scala 693:122] - node _T_5875 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[ifu_mem_ctl.scala 694:37] - node _T_5876 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_5877 = and(_T_5875, _T_5876) @[ifu_mem_ctl.scala 694:59] - node _T_5878 = eq(perr_ic_index_ff, UInt<5>("h010")) @[ifu_mem_ctl.scala 694:102] - node _T_5879 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_5880 = and(_T_5878, _T_5879) @[ifu_mem_ctl.scala 694:124] - node _T_5881 = or(_T_5877, _T_5880) @[ifu_mem_ctl.scala 694:81] - node _T_5882 = or(_T_5881, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5883 = bits(_T_5882, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][15] <= _T_5869 @[ifu_mem_ctl.scala 692:41] + node _T_5870 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5871 = eq(_T_5870, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5872 = and(ic_valid_ff, _T_5871) @[ifu_mem_ctl.scala 692:97] + node _T_5873 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5874 = and(_T_5872, _T_5873) @[ifu_mem_ctl.scala 692:122] + node _T_5875 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[ifu_mem_ctl.scala 693:37] + node _T_5876 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_5877 = and(_T_5875, _T_5876) @[ifu_mem_ctl.scala 693:59] + node _T_5878 = eq(perr_ic_index_ff, UInt<5>("h010")) @[ifu_mem_ctl.scala 693:102] + node _T_5879 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_5880 = and(_T_5878, _T_5879) @[ifu_mem_ctl.scala 693:124] + node _T_5881 = or(_T_5877, _T_5880) @[ifu_mem_ctl.scala 693:81] + node _T_5882 = or(_T_5881, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5883 = bits(_T_5882, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5884 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5883 : @[Reg.scala 28:19] _T_5884 <= _T_5874 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][16] <= _T_5884 @[ifu_mem_ctl.scala 693:41] - node _T_5885 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5886 = eq(_T_5885, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5887 = and(ic_valid_ff, _T_5886) @[ifu_mem_ctl.scala 693:97] - node _T_5888 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5889 = and(_T_5887, _T_5888) @[ifu_mem_ctl.scala 693:122] - node _T_5890 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[ifu_mem_ctl.scala 694:37] - node _T_5891 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_5892 = and(_T_5890, _T_5891) @[ifu_mem_ctl.scala 694:59] - node _T_5893 = eq(perr_ic_index_ff, UInt<5>("h011")) @[ifu_mem_ctl.scala 694:102] - node _T_5894 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_5895 = and(_T_5893, _T_5894) @[ifu_mem_ctl.scala 694:124] - node _T_5896 = or(_T_5892, _T_5895) @[ifu_mem_ctl.scala 694:81] - node _T_5897 = or(_T_5896, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5898 = bits(_T_5897, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][16] <= _T_5884 @[ifu_mem_ctl.scala 692:41] + node _T_5885 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5886 = eq(_T_5885, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5887 = and(ic_valid_ff, _T_5886) @[ifu_mem_ctl.scala 692:97] + node _T_5888 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5889 = and(_T_5887, _T_5888) @[ifu_mem_ctl.scala 692:122] + node _T_5890 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[ifu_mem_ctl.scala 693:37] + node _T_5891 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_5892 = and(_T_5890, _T_5891) @[ifu_mem_ctl.scala 693:59] + node _T_5893 = eq(perr_ic_index_ff, UInt<5>("h011")) @[ifu_mem_ctl.scala 693:102] + node _T_5894 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_5895 = and(_T_5893, _T_5894) @[ifu_mem_ctl.scala 693:124] + node _T_5896 = or(_T_5892, _T_5895) @[ifu_mem_ctl.scala 693:81] + node _T_5897 = or(_T_5896, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5898 = bits(_T_5897, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5899 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5898 : @[Reg.scala 28:19] _T_5899 <= _T_5889 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][17] <= _T_5899 @[ifu_mem_ctl.scala 693:41] - node _T_5900 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5901 = eq(_T_5900, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5902 = and(ic_valid_ff, _T_5901) @[ifu_mem_ctl.scala 693:97] - node _T_5903 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5904 = and(_T_5902, _T_5903) @[ifu_mem_ctl.scala 693:122] - node _T_5905 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[ifu_mem_ctl.scala 694:37] - node _T_5906 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_5907 = and(_T_5905, _T_5906) @[ifu_mem_ctl.scala 694:59] - node _T_5908 = eq(perr_ic_index_ff, UInt<5>("h012")) @[ifu_mem_ctl.scala 694:102] - node _T_5909 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_5910 = and(_T_5908, _T_5909) @[ifu_mem_ctl.scala 694:124] - node _T_5911 = or(_T_5907, _T_5910) @[ifu_mem_ctl.scala 694:81] - node _T_5912 = or(_T_5911, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5913 = bits(_T_5912, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][17] <= _T_5899 @[ifu_mem_ctl.scala 692:41] + node _T_5900 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5901 = eq(_T_5900, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5902 = and(ic_valid_ff, _T_5901) @[ifu_mem_ctl.scala 692:97] + node _T_5903 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5904 = and(_T_5902, _T_5903) @[ifu_mem_ctl.scala 692:122] + node _T_5905 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[ifu_mem_ctl.scala 693:37] + node _T_5906 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_5907 = and(_T_5905, _T_5906) @[ifu_mem_ctl.scala 693:59] + node _T_5908 = eq(perr_ic_index_ff, UInt<5>("h012")) @[ifu_mem_ctl.scala 693:102] + node _T_5909 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_5910 = and(_T_5908, _T_5909) @[ifu_mem_ctl.scala 693:124] + node _T_5911 = or(_T_5907, _T_5910) @[ifu_mem_ctl.scala 693:81] + node _T_5912 = or(_T_5911, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5913 = bits(_T_5912, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5914 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5913 : @[Reg.scala 28:19] _T_5914 <= _T_5904 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][18] <= _T_5914 @[ifu_mem_ctl.scala 693:41] - node _T_5915 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5916 = eq(_T_5915, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5917 = and(ic_valid_ff, _T_5916) @[ifu_mem_ctl.scala 693:97] - node _T_5918 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5919 = and(_T_5917, _T_5918) @[ifu_mem_ctl.scala 693:122] - node _T_5920 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[ifu_mem_ctl.scala 694:37] - node _T_5921 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_5922 = and(_T_5920, _T_5921) @[ifu_mem_ctl.scala 694:59] - node _T_5923 = eq(perr_ic_index_ff, UInt<5>("h013")) @[ifu_mem_ctl.scala 694:102] - node _T_5924 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_5925 = and(_T_5923, _T_5924) @[ifu_mem_ctl.scala 694:124] - node _T_5926 = or(_T_5922, _T_5925) @[ifu_mem_ctl.scala 694:81] - node _T_5927 = or(_T_5926, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5928 = bits(_T_5927, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][18] <= _T_5914 @[ifu_mem_ctl.scala 692:41] + node _T_5915 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5916 = eq(_T_5915, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5917 = and(ic_valid_ff, _T_5916) @[ifu_mem_ctl.scala 692:97] + node _T_5918 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5919 = and(_T_5917, _T_5918) @[ifu_mem_ctl.scala 692:122] + node _T_5920 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[ifu_mem_ctl.scala 693:37] + node _T_5921 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_5922 = and(_T_5920, _T_5921) @[ifu_mem_ctl.scala 693:59] + node _T_5923 = eq(perr_ic_index_ff, UInt<5>("h013")) @[ifu_mem_ctl.scala 693:102] + node _T_5924 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_5925 = and(_T_5923, _T_5924) @[ifu_mem_ctl.scala 693:124] + node _T_5926 = or(_T_5922, _T_5925) @[ifu_mem_ctl.scala 693:81] + node _T_5927 = or(_T_5926, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5928 = bits(_T_5927, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5929 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5928 : @[Reg.scala 28:19] _T_5929 <= _T_5919 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][19] <= _T_5929 @[ifu_mem_ctl.scala 693:41] - node _T_5930 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5931 = eq(_T_5930, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5932 = and(ic_valid_ff, _T_5931) @[ifu_mem_ctl.scala 693:97] - node _T_5933 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5934 = and(_T_5932, _T_5933) @[ifu_mem_ctl.scala 693:122] - node _T_5935 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[ifu_mem_ctl.scala 694:37] - node _T_5936 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_5937 = and(_T_5935, _T_5936) @[ifu_mem_ctl.scala 694:59] - node _T_5938 = eq(perr_ic_index_ff, UInt<5>("h014")) @[ifu_mem_ctl.scala 694:102] - node _T_5939 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_5940 = and(_T_5938, _T_5939) @[ifu_mem_ctl.scala 694:124] - node _T_5941 = or(_T_5937, _T_5940) @[ifu_mem_ctl.scala 694:81] - node _T_5942 = or(_T_5941, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5943 = bits(_T_5942, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][19] <= _T_5929 @[ifu_mem_ctl.scala 692:41] + node _T_5930 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5931 = eq(_T_5930, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5932 = and(ic_valid_ff, _T_5931) @[ifu_mem_ctl.scala 692:97] + node _T_5933 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5934 = and(_T_5932, _T_5933) @[ifu_mem_ctl.scala 692:122] + node _T_5935 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[ifu_mem_ctl.scala 693:37] + node _T_5936 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_5937 = and(_T_5935, _T_5936) @[ifu_mem_ctl.scala 693:59] + node _T_5938 = eq(perr_ic_index_ff, UInt<5>("h014")) @[ifu_mem_ctl.scala 693:102] + node _T_5939 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_5940 = and(_T_5938, _T_5939) @[ifu_mem_ctl.scala 693:124] + node _T_5941 = or(_T_5937, _T_5940) @[ifu_mem_ctl.scala 693:81] + node _T_5942 = or(_T_5941, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5943 = bits(_T_5942, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5944 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5943 : @[Reg.scala 28:19] _T_5944 <= _T_5934 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][20] <= _T_5944 @[ifu_mem_ctl.scala 693:41] - node _T_5945 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5946 = eq(_T_5945, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5947 = and(ic_valid_ff, _T_5946) @[ifu_mem_ctl.scala 693:97] - node _T_5948 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5949 = and(_T_5947, _T_5948) @[ifu_mem_ctl.scala 693:122] - node _T_5950 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[ifu_mem_ctl.scala 694:37] - node _T_5951 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_5952 = and(_T_5950, _T_5951) @[ifu_mem_ctl.scala 694:59] - node _T_5953 = eq(perr_ic_index_ff, UInt<5>("h015")) @[ifu_mem_ctl.scala 694:102] - node _T_5954 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_5955 = and(_T_5953, _T_5954) @[ifu_mem_ctl.scala 694:124] - node _T_5956 = or(_T_5952, _T_5955) @[ifu_mem_ctl.scala 694:81] - node _T_5957 = or(_T_5956, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5958 = bits(_T_5957, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][20] <= _T_5944 @[ifu_mem_ctl.scala 692:41] + node _T_5945 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5946 = eq(_T_5945, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5947 = and(ic_valid_ff, _T_5946) @[ifu_mem_ctl.scala 692:97] + node _T_5948 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5949 = and(_T_5947, _T_5948) @[ifu_mem_ctl.scala 692:122] + node _T_5950 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[ifu_mem_ctl.scala 693:37] + node _T_5951 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_5952 = and(_T_5950, _T_5951) @[ifu_mem_ctl.scala 693:59] + node _T_5953 = eq(perr_ic_index_ff, UInt<5>("h015")) @[ifu_mem_ctl.scala 693:102] + node _T_5954 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_5955 = and(_T_5953, _T_5954) @[ifu_mem_ctl.scala 693:124] + node _T_5956 = or(_T_5952, _T_5955) @[ifu_mem_ctl.scala 693:81] + node _T_5957 = or(_T_5956, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5958 = bits(_T_5957, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5959 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5958 : @[Reg.scala 28:19] _T_5959 <= _T_5949 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][21] <= _T_5959 @[ifu_mem_ctl.scala 693:41] - node _T_5960 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5961 = eq(_T_5960, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5962 = and(ic_valid_ff, _T_5961) @[ifu_mem_ctl.scala 693:97] - node _T_5963 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5964 = and(_T_5962, _T_5963) @[ifu_mem_ctl.scala 693:122] - node _T_5965 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[ifu_mem_ctl.scala 694:37] - node _T_5966 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_5967 = and(_T_5965, _T_5966) @[ifu_mem_ctl.scala 694:59] - node _T_5968 = eq(perr_ic_index_ff, UInt<5>("h016")) @[ifu_mem_ctl.scala 694:102] - node _T_5969 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_5970 = and(_T_5968, _T_5969) @[ifu_mem_ctl.scala 694:124] - node _T_5971 = or(_T_5967, _T_5970) @[ifu_mem_ctl.scala 694:81] - node _T_5972 = or(_T_5971, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5973 = bits(_T_5972, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][21] <= _T_5959 @[ifu_mem_ctl.scala 692:41] + node _T_5960 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5961 = eq(_T_5960, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5962 = and(ic_valid_ff, _T_5961) @[ifu_mem_ctl.scala 692:97] + node _T_5963 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5964 = and(_T_5962, _T_5963) @[ifu_mem_ctl.scala 692:122] + node _T_5965 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[ifu_mem_ctl.scala 693:37] + node _T_5966 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_5967 = and(_T_5965, _T_5966) @[ifu_mem_ctl.scala 693:59] + node _T_5968 = eq(perr_ic_index_ff, UInt<5>("h016")) @[ifu_mem_ctl.scala 693:102] + node _T_5969 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_5970 = and(_T_5968, _T_5969) @[ifu_mem_ctl.scala 693:124] + node _T_5971 = or(_T_5967, _T_5970) @[ifu_mem_ctl.scala 693:81] + node _T_5972 = or(_T_5971, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5973 = bits(_T_5972, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5974 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5973 : @[Reg.scala 28:19] _T_5974 <= _T_5964 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][22] <= _T_5974 @[ifu_mem_ctl.scala 693:41] - node _T_5975 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5976 = eq(_T_5975, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5977 = and(ic_valid_ff, _T_5976) @[ifu_mem_ctl.scala 693:97] - node _T_5978 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5979 = and(_T_5977, _T_5978) @[ifu_mem_ctl.scala 693:122] - node _T_5980 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[ifu_mem_ctl.scala 694:37] - node _T_5981 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_5982 = and(_T_5980, _T_5981) @[ifu_mem_ctl.scala 694:59] - node _T_5983 = eq(perr_ic_index_ff, UInt<5>("h017")) @[ifu_mem_ctl.scala 694:102] - node _T_5984 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_5985 = and(_T_5983, _T_5984) @[ifu_mem_ctl.scala 694:124] - node _T_5986 = or(_T_5982, _T_5985) @[ifu_mem_ctl.scala 694:81] - node _T_5987 = or(_T_5986, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_5988 = bits(_T_5987, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][22] <= _T_5974 @[ifu_mem_ctl.scala 692:41] + node _T_5975 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5976 = eq(_T_5975, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5977 = and(ic_valid_ff, _T_5976) @[ifu_mem_ctl.scala 692:97] + node _T_5978 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5979 = and(_T_5977, _T_5978) @[ifu_mem_ctl.scala 692:122] + node _T_5980 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[ifu_mem_ctl.scala 693:37] + node _T_5981 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_5982 = and(_T_5980, _T_5981) @[ifu_mem_ctl.scala 693:59] + node _T_5983 = eq(perr_ic_index_ff, UInt<5>("h017")) @[ifu_mem_ctl.scala 693:102] + node _T_5984 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_5985 = and(_T_5983, _T_5984) @[ifu_mem_ctl.scala 693:124] + node _T_5986 = or(_T_5982, _T_5985) @[ifu_mem_ctl.scala 693:81] + node _T_5987 = or(_T_5986, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_5988 = bits(_T_5987, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_5989 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5988 : @[Reg.scala 28:19] _T_5989 <= _T_5979 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][23] <= _T_5989 @[ifu_mem_ctl.scala 693:41] - node _T_5990 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_5991 = eq(_T_5990, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_5992 = and(ic_valid_ff, _T_5991) @[ifu_mem_ctl.scala 693:97] - node _T_5993 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_5994 = and(_T_5992, _T_5993) @[ifu_mem_ctl.scala 693:122] - node _T_5995 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[ifu_mem_ctl.scala 694:37] - node _T_5996 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_5997 = and(_T_5995, _T_5996) @[ifu_mem_ctl.scala 694:59] - node _T_5998 = eq(perr_ic_index_ff, UInt<5>("h018")) @[ifu_mem_ctl.scala 694:102] - node _T_5999 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6000 = and(_T_5998, _T_5999) @[ifu_mem_ctl.scala 694:124] - node _T_6001 = or(_T_5997, _T_6000) @[ifu_mem_ctl.scala 694:81] - node _T_6002 = or(_T_6001, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6003 = bits(_T_6002, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][23] <= _T_5989 @[ifu_mem_ctl.scala 692:41] + node _T_5990 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_5991 = eq(_T_5990, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_5992 = and(ic_valid_ff, _T_5991) @[ifu_mem_ctl.scala 692:97] + node _T_5993 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_5994 = and(_T_5992, _T_5993) @[ifu_mem_ctl.scala 692:122] + node _T_5995 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[ifu_mem_ctl.scala 693:37] + node _T_5996 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_5997 = and(_T_5995, _T_5996) @[ifu_mem_ctl.scala 693:59] + node _T_5998 = eq(perr_ic_index_ff, UInt<5>("h018")) @[ifu_mem_ctl.scala 693:102] + node _T_5999 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6000 = and(_T_5998, _T_5999) @[ifu_mem_ctl.scala 693:124] + node _T_6001 = or(_T_5997, _T_6000) @[ifu_mem_ctl.scala 693:81] + node _T_6002 = or(_T_6001, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6003 = bits(_T_6002, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6004 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6003 : @[Reg.scala 28:19] _T_6004 <= _T_5994 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][24] <= _T_6004 @[ifu_mem_ctl.scala 693:41] - node _T_6005 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6006 = eq(_T_6005, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6007 = and(ic_valid_ff, _T_6006) @[ifu_mem_ctl.scala 693:97] - node _T_6008 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6009 = and(_T_6007, _T_6008) @[ifu_mem_ctl.scala 693:122] - node _T_6010 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[ifu_mem_ctl.scala 694:37] - node _T_6011 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_6012 = and(_T_6010, _T_6011) @[ifu_mem_ctl.scala 694:59] - node _T_6013 = eq(perr_ic_index_ff, UInt<5>("h019")) @[ifu_mem_ctl.scala 694:102] - node _T_6014 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6015 = and(_T_6013, _T_6014) @[ifu_mem_ctl.scala 694:124] - node _T_6016 = or(_T_6012, _T_6015) @[ifu_mem_ctl.scala 694:81] - node _T_6017 = or(_T_6016, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6018 = bits(_T_6017, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][24] <= _T_6004 @[ifu_mem_ctl.scala 692:41] + node _T_6005 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6006 = eq(_T_6005, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6007 = and(ic_valid_ff, _T_6006) @[ifu_mem_ctl.scala 692:97] + node _T_6008 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6009 = and(_T_6007, _T_6008) @[ifu_mem_ctl.scala 692:122] + node _T_6010 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[ifu_mem_ctl.scala 693:37] + node _T_6011 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_6012 = and(_T_6010, _T_6011) @[ifu_mem_ctl.scala 693:59] + node _T_6013 = eq(perr_ic_index_ff, UInt<5>("h019")) @[ifu_mem_ctl.scala 693:102] + node _T_6014 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6015 = and(_T_6013, _T_6014) @[ifu_mem_ctl.scala 693:124] + node _T_6016 = or(_T_6012, _T_6015) @[ifu_mem_ctl.scala 693:81] + node _T_6017 = or(_T_6016, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6018 = bits(_T_6017, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6019 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6018 : @[Reg.scala 28:19] _T_6019 <= _T_6009 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][25] <= _T_6019 @[ifu_mem_ctl.scala 693:41] - node _T_6020 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6021 = eq(_T_6020, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6022 = and(ic_valid_ff, _T_6021) @[ifu_mem_ctl.scala 693:97] - node _T_6023 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6024 = and(_T_6022, _T_6023) @[ifu_mem_ctl.scala 693:122] - node _T_6025 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[ifu_mem_ctl.scala 694:37] - node _T_6026 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_6027 = and(_T_6025, _T_6026) @[ifu_mem_ctl.scala 694:59] - node _T_6028 = eq(perr_ic_index_ff, UInt<5>("h01a")) @[ifu_mem_ctl.scala 694:102] - node _T_6029 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6030 = and(_T_6028, _T_6029) @[ifu_mem_ctl.scala 694:124] - node _T_6031 = or(_T_6027, _T_6030) @[ifu_mem_ctl.scala 694:81] - node _T_6032 = or(_T_6031, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6033 = bits(_T_6032, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][25] <= _T_6019 @[ifu_mem_ctl.scala 692:41] + node _T_6020 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6021 = eq(_T_6020, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6022 = and(ic_valid_ff, _T_6021) @[ifu_mem_ctl.scala 692:97] + node _T_6023 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6024 = and(_T_6022, _T_6023) @[ifu_mem_ctl.scala 692:122] + node _T_6025 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[ifu_mem_ctl.scala 693:37] + node _T_6026 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_6027 = and(_T_6025, _T_6026) @[ifu_mem_ctl.scala 693:59] + node _T_6028 = eq(perr_ic_index_ff, UInt<5>("h01a")) @[ifu_mem_ctl.scala 693:102] + node _T_6029 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6030 = and(_T_6028, _T_6029) @[ifu_mem_ctl.scala 693:124] + node _T_6031 = or(_T_6027, _T_6030) @[ifu_mem_ctl.scala 693:81] + node _T_6032 = or(_T_6031, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6033 = bits(_T_6032, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6034 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6033 : @[Reg.scala 28:19] _T_6034 <= _T_6024 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][26] <= _T_6034 @[ifu_mem_ctl.scala 693:41] - node _T_6035 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6036 = eq(_T_6035, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6037 = and(ic_valid_ff, _T_6036) @[ifu_mem_ctl.scala 693:97] - node _T_6038 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6039 = and(_T_6037, _T_6038) @[ifu_mem_ctl.scala 693:122] - node _T_6040 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[ifu_mem_ctl.scala 694:37] - node _T_6041 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_6042 = and(_T_6040, _T_6041) @[ifu_mem_ctl.scala 694:59] - node _T_6043 = eq(perr_ic_index_ff, UInt<5>("h01b")) @[ifu_mem_ctl.scala 694:102] - node _T_6044 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6045 = and(_T_6043, _T_6044) @[ifu_mem_ctl.scala 694:124] - node _T_6046 = or(_T_6042, _T_6045) @[ifu_mem_ctl.scala 694:81] - node _T_6047 = or(_T_6046, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6048 = bits(_T_6047, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][26] <= _T_6034 @[ifu_mem_ctl.scala 692:41] + node _T_6035 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6036 = eq(_T_6035, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6037 = and(ic_valid_ff, _T_6036) @[ifu_mem_ctl.scala 692:97] + node _T_6038 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6039 = and(_T_6037, _T_6038) @[ifu_mem_ctl.scala 692:122] + node _T_6040 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[ifu_mem_ctl.scala 693:37] + node _T_6041 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_6042 = and(_T_6040, _T_6041) @[ifu_mem_ctl.scala 693:59] + node _T_6043 = eq(perr_ic_index_ff, UInt<5>("h01b")) @[ifu_mem_ctl.scala 693:102] + node _T_6044 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6045 = and(_T_6043, _T_6044) @[ifu_mem_ctl.scala 693:124] + node _T_6046 = or(_T_6042, _T_6045) @[ifu_mem_ctl.scala 693:81] + node _T_6047 = or(_T_6046, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6048 = bits(_T_6047, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6049 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6048 : @[Reg.scala 28:19] _T_6049 <= _T_6039 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][27] <= _T_6049 @[ifu_mem_ctl.scala 693:41] - node _T_6050 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6051 = eq(_T_6050, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6052 = and(ic_valid_ff, _T_6051) @[ifu_mem_ctl.scala 693:97] - node _T_6053 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6054 = and(_T_6052, _T_6053) @[ifu_mem_ctl.scala 693:122] - node _T_6055 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[ifu_mem_ctl.scala 694:37] - node _T_6056 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_6057 = and(_T_6055, _T_6056) @[ifu_mem_ctl.scala 694:59] - node _T_6058 = eq(perr_ic_index_ff, UInt<5>("h01c")) @[ifu_mem_ctl.scala 694:102] - node _T_6059 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6060 = and(_T_6058, _T_6059) @[ifu_mem_ctl.scala 694:124] - node _T_6061 = or(_T_6057, _T_6060) @[ifu_mem_ctl.scala 694:81] - node _T_6062 = or(_T_6061, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6063 = bits(_T_6062, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][27] <= _T_6049 @[ifu_mem_ctl.scala 692:41] + node _T_6050 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6051 = eq(_T_6050, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6052 = and(ic_valid_ff, _T_6051) @[ifu_mem_ctl.scala 692:97] + node _T_6053 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6054 = and(_T_6052, _T_6053) @[ifu_mem_ctl.scala 692:122] + node _T_6055 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[ifu_mem_ctl.scala 693:37] + node _T_6056 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_6057 = and(_T_6055, _T_6056) @[ifu_mem_ctl.scala 693:59] + node _T_6058 = eq(perr_ic_index_ff, UInt<5>("h01c")) @[ifu_mem_ctl.scala 693:102] + node _T_6059 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6060 = and(_T_6058, _T_6059) @[ifu_mem_ctl.scala 693:124] + node _T_6061 = or(_T_6057, _T_6060) @[ifu_mem_ctl.scala 693:81] + node _T_6062 = or(_T_6061, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6063 = bits(_T_6062, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6064 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6063 : @[Reg.scala 28:19] _T_6064 <= _T_6054 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][28] <= _T_6064 @[ifu_mem_ctl.scala 693:41] - node _T_6065 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6066 = eq(_T_6065, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6067 = and(ic_valid_ff, _T_6066) @[ifu_mem_ctl.scala 693:97] - node _T_6068 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6069 = and(_T_6067, _T_6068) @[ifu_mem_ctl.scala 693:122] - node _T_6070 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[ifu_mem_ctl.scala 694:37] - node _T_6071 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_6072 = and(_T_6070, _T_6071) @[ifu_mem_ctl.scala 694:59] - node _T_6073 = eq(perr_ic_index_ff, UInt<5>("h01d")) @[ifu_mem_ctl.scala 694:102] - node _T_6074 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6075 = and(_T_6073, _T_6074) @[ifu_mem_ctl.scala 694:124] - node _T_6076 = or(_T_6072, _T_6075) @[ifu_mem_ctl.scala 694:81] - node _T_6077 = or(_T_6076, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6078 = bits(_T_6077, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][28] <= _T_6064 @[ifu_mem_ctl.scala 692:41] + node _T_6065 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6066 = eq(_T_6065, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6067 = and(ic_valid_ff, _T_6066) @[ifu_mem_ctl.scala 692:97] + node _T_6068 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6069 = and(_T_6067, _T_6068) @[ifu_mem_ctl.scala 692:122] + node _T_6070 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[ifu_mem_ctl.scala 693:37] + node _T_6071 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_6072 = and(_T_6070, _T_6071) @[ifu_mem_ctl.scala 693:59] + node _T_6073 = eq(perr_ic_index_ff, UInt<5>("h01d")) @[ifu_mem_ctl.scala 693:102] + node _T_6074 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6075 = and(_T_6073, _T_6074) @[ifu_mem_ctl.scala 693:124] + node _T_6076 = or(_T_6072, _T_6075) @[ifu_mem_ctl.scala 693:81] + node _T_6077 = or(_T_6076, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6078 = bits(_T_6077, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6079 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6078 : @[Reg.scala 28:19] _T_6079 <= _T_6069 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][29] <= _T_6079 @[ifu_mem_ctl.scala 693:41] - node _T_6080 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6081 = eq(_T_6080, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6082 = and(ic_valid_ff, _T_6081) @[ifu_mem_ctl.scala 693:97] - node _T_6083 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6084 = and(_T_6082, _T_6083) @[ifu_mem_ctl.scala 693:122] - node _T_6085 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[ifu_mem_ctl.scala 694:37] - node _T_6086 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_6087 = and(_T_6085, _T_6086) @[ifu_mem_ctl.scala 694:59] - node _T_6088 = eq(perr_ic_index_ff, UInt<5>("h01e")) @[ifu_mem_ctl.scala 694:102] - node _T_6089 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6090 = and(_T_6088, _T_6089) @[ifu_mem_ctl.scala 694:124] - node _T_6091 = or(_T_6087, _T_6090) @[ifu_mem_ctl.scala 694:81] - node _T_6092 = or(_T_6091, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6093 = bits(_T_6092, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][29] <= _T_6079 @[ifu_mem_ctl.scala 692:41] + node _T_6080 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6081 = eq(_T_6080, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6082 = and(ic_valid_ff, _T_6081) @[ifu_mem_ctl.scala 692:97] + node _T_6083 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6084 = and(_T_6082, _T_6083) @[ifu_mem_ctl.scala 692:122] + node _T_6085 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[ifu_mem_ctl.scala 693:37] + node _T_6086 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_6087 = and(_T_6085, _T_6086) @[ifu_mem_ctl.scala 693:59] + node _T_6088 = eq(perr_ic_index_ff, UInt<5>("h01e")) @[ifu_mem_ctl.scala 693:102] + node _T_6089 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6090 = and(_T_6088, _T_6089) @[ifu_mem_ctl.scala 693:124] + node _T_6091 = or(_T_6087, _T_6090) @[ifu_mem_ctl.scala 693:81] + node _T_6092 = or(_T_6091, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6093 = bits(_T_6092, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6094 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6093 : @[Reg.scala 28:19] _T_6094 <= _T_6084 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][30] <= _T_6094 @[ifu_mem_ctl.scala 693:41] - node _T_6095 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6096 = eq(_T_6095, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6097 = and(ic_valid_ff, _T_6096) @[ifu_mem_ctl.scala 693:97] - node _T_6098 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6099 = and(_T_6097, _T_6098) @[ifu_mem_ctl.scala 693:122] - node _T_6100 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[ifu_mem_ctl.scala 694:37] - node _T_6101 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_6102 = and(_T_6100, _T_6101) @[ifu_mem_ctl.scala 694:59] - node _T_6103 = eq(perr_ic_index_ff, UInt<5>("h01f")) @[ifu_mem_ctl.scala 694:102] - node _T_6104 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6105 = and(_T_6103, _T_6104) @[ifu_mem_ctl.scala 694:124] - node _T_6106 = or(_T_6102, _T_6105) @[ifu_mem_ctl.scala 694:81] - node _T_6107 = or(_T_6106, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6108 = bits(_T_6107, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][30] <= _T_6094 @[ifu_mem_ctl.scala 692:41] + node _T_6095 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6096 = eq(_T_6095, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6097 = and(ic_valid_ff, _T_6096) @[ifu_mem_ctl.scala 692:97] + node _T_6098 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6099 = and(_T_6097, _T_6098) @[ifu_mem_ctl.scala 692:122] + node _T_6100 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[ifu_mem_ctl.scala 693:37] + node _T_6101 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_6102 = and(_T_6100, _T_6101) @[ifu_mem_ctl.scala 693:59] + node _T_6103 = eq(perr_ic_index_ff, UInt<5>("h01f")) @[ifu_mem_ctl.scala 693:102] + node _T_6104 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6105 = and(_T_6103, _T_6104) @[ifu_mem_ctl.scala 693:124] + node _T_6106 = or(_T_6102, _T_6105) @[ifu_mem_ctl.scala 693:81] + node _T_6107 = or(_T_6106, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6108 = bits(_T_6107, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6109 : UInt<1>, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6108 : @[Reg.scala 28:19] _T_6109 <= _T_6099 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][31] <= _T_6109 @[ifu_mem_ctl.scala 693:41] - node _T_6110 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6111 = eq(_T_6110, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6112 = and(ic_valid_ff, _T_6111) @[ifu_mem_ctl.scala 693:97] - node _T_6113 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6114 = and(_T_6112, _T_6113) @[ifu_mem_ctl.scala 693:122] - node _T_6115 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[ifu_mem_ctl.scala 694:37] - node _T_6116 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_6117 = and(_T_6115, _T_6116) @[ifu_mem_ctl.scala 694:59] - node _T_6118 = eq(perr_ic_index_ff, UInt<6>("h020")) @[ifu_mem_ctl.scala 694:102] - node _T_6119 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_6120 = and(_T_6118, _T_6119) @[ifu_mem_ctl.scala 694:124] - node _T_6121 = or(_T_6117, _T_6120) @[ifu_mem_ctl.scala 694:81] - node _T_6122 = or(_T_6121, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6123 = bits(_T_6122, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][31] <= _T_6109 @[ifu_mem_ctl.scala 692:41] + node _T_6110 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6111 = eq(_T_6110, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6112 = and(ic_valid_ff, _T_6111) @[ifu_mem_ctl.scala 692:97] + node _T_6113 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6114 = and(_T_6112, _T_6113) @[ifu_mem_ctl.scala 692:122] + node _T_6115 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[ifu_mem_ctl.scala 693:37] + node _T_6116 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_6117 = and(_T_6115, _T_6116) @[ifu_mem_ctl.scala 693:59] + node _T_6118 = eq(perr_ic_index_ff, UInt<6>("h020")) @[ifu_mem_ctl.scala 693:102] + node _T_6119 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_6120 = and(_T_6118, _T_6119) @[ifu_mem_ctl.scala 693:124] + node _T_6121 = or(_T_6117, _T_6120) @[ifu_mem_ctl.scala 693:81] + node _T_6122 = or(_T_6121, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6123 = bits(_T_6122, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6124 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6123 : @[Reg.scala 28:19] _T_6124 <= _T_6114 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][32] <= _T_6124 @[ifu_mem_ctl.scala 693:41] - node _T_6125 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6126 = eq(_T_6125, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6127 = and(ic_valid_ff, _T_6126) @[ifu_mem_ctl.scala 693:97] - node _T_6128 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6129 = and(_T_6127, _T_6128) @[ifu_mem_ctl.scala 693:122] - node _T_6130 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[ifu_mem_ctl.scala 694:37] - node _T_6131 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_6132 = and(_T_6130, _T_6131) @[ifu_mem_ctl.scala 694:59] - node _T_6133 = eq(perr_ic_index_ff, UInt<6>("h021")) @[ifu_mem_ctl.scala 694:102] - node _T_6134 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_6135 = and(_T_6133, _T_6134) @[ifu_mem_ctl.scala 694:124] - node _T_6136 = or(_T_6132, _T_6135) @[ifu_mem_ctl.scala 694:81] - node _T_6137 = or(_T_6136, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6138 = bits(_T_6137, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][32] <= _T_6124 @[ifu_mem_ctl.scala 692:41] + node _T_6125 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6126 = eq(_T_6125, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6127 = and(ic_valid_ff, _T_6126) @[ifu_mem_ctl.scala 692:97] + node _T_6128 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6129 = and(_T_6127, _T_6128) @[ifu_mem_ctl.scala 692:122] + node _T_6130 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[ifu_mem_ctl.scala 693:37] + node _T_6131 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_6132 = and(_T_6130, _T_6131) @[ifu_mem_ctl.scala 693:59] + node _T_6133 = eq(perr_ic_index_ff, UInt<6>("h021")) @[ifu_mem_ctl.scala 693:102] + node _T_6134 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_6135 = and(_T_6133, _T_6134) @[ifu_mem_ctl.scala 693:124] + node _T_6136 = or(_T_6132, _T_6135) @[ifu_mem_ctl.scala 693:81] + node _T_6137 = or(_T_6136, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6138 = bits(_T_6137, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6139 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6138 : @[Reg.scala 28:19] _T_6139 <= _T_6129 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][33] <= _T_6139 @[ifu_mem_ctl.scala 693:41] - node _T_6140 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6141 = eq(_T_6140, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6142 = and(ic_valid_ff, _T_6141) @[ifu_mem_ctl.scala 693:97] - node _T_6143 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6144 = and(_T_6142, _T_6143) @[ifu_mem_ctl.scala 693:122] - node _T_6145 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[ifu_mem_ctl.scala 694:37] - node _T_6146 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_6147 = and(_T_6145, _T_6146) @[ifu_mem_ctl.scala 694:59] - node _T_6148 = eq(perr_ic_index_ff, UInt<6>("h022")) @[ifu_mem_ctl.scala 694:102] - node _T_6149 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_6150 = and(_T_6148, _T_6149) @[ifu_mem_ctl.scala 694:124] - node _T_6151 = or(_T_6147, _T_6150) @[ifu_mem_ctl.scala 694:81] - node _T_6152 = or(_T_6151, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6153 = bits(_T_6152, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][33] <= _T_6139 @[ifu_mem_ctl.scala 692:41] + node _T_6140 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6141 = eq(_T_6140, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6142 = and(ic_valid_ff, _T_6141) @[ifu_mem_ctl.scala 692:97] + node _T_6143 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6144 = and(_T_6142, _T_6143) @[ifu_mem_ctl.scala 692:122] + node _T_6145 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[ifu_mem_ctl.scala 693:37] + node _T_6146 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_6147 = and(_T_6145, _T_6146) @[ifu_mem_ctl.scala 693:59] + node _T_6148 = eq(perr_ic_index_ff, UInt<6>("h022")) @[ifu_mem_ctl.scala 693:102] + node _T_6149 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_6150 = and(_T_6148, _T_6149) @[ifu_mem_ctl.scala 693:124] + node _T_6151 = or(_T_6147, _T_6150) @[ifu_mem_ctl.scala 693:81] + node _T_6152 = or(_T_6151, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6153 = bits(_T_6152, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6154 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6153 : @[Reg.scala 28:19] _T_6154 <= _T_6144 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][34] <= _T_6154 @[ifu_mem_ctl.scala 693:41] - node _T_6155 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6156 = eq(_T_6155, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6157 = and(ic_valid_ff, _T_6156) @[ifu_mem_ctl.scala 693:97] - node _T_6158 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6159 = and(_T_6157, _T_6158) @[ifu_mem_ctl.scala 693:122] - node _T_6160 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[ifu_mem_ctl.scala 694:37] - node _T_6161 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_6162 = and(_T_6160, _T_6161) @[ifu_mem_ctl.scala 694:59] - node _T_6163 = eq(perr_ic_index_ff, UInt<6>("h023")) @[ifu_mem_ctl.scala 694:102] - node _T_6164 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_6165 = and(_T_6163, _T_6164) @[ifu_mem_ctl.scala 694:124] - node _T_6166 = or(_T_6162, _T_6165) @[ifu_mem_ctl.scala 694:81] - node _T_6167 = or(_T_6166, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6168 = bits(_T_6167, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][34] <= _T_6154 @[ifu_mem_ctl.scala 692:41] + node _T_6155 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6156 = eq(_T_6155, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6157 = and(ic_valid_ff, _T_6156) @[ifu_mem_ctl.scala 692:97] + node _T_6158 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6159 = and(_T_6157, _T_6158) @[ifu_mem_ctl.scala 692:122] + node _T_6160 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[ifu_mem_ctl.scala 693:37] + node _T_6161 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_6162 = and(_T_6160, _T_6161) @[ifu_mem_ctl.scala 693:59] + node _T_6163 = eq(perr_ic_index_ff, UInt<6>("h023")) @[ifu_mem_ctl.scala 693:102] + node _T_6164 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_6165 = and(_T_6163, _T_6164) @[ifu_mem_ctl.scala 693:124] + node _T_6166 = or(_T_6162, _T_6165) @[ifu_mem_ctl.scala 693:81] + node _T_6167 = or(_T_6166, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6168 = bits(_T_6167, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6169 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6168 : @[Reg.scala 28:19] _T_6169 <= _T_6159 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][35] <= _T_6169 @[ifu_mem_ctl.scala 693:41] - node _T_6170 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6171 = eq(_T_6170, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6172 = and(ic_valid_ff, _T_6171) @[ifu_mem_ctl.scala 693:97] - node _T_6173 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6174 = and(_T_6172, _T_6173) @[ifu_mem_ctl.scala 693:122] - node _T_6175 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[ifu_mem_ctl.scala 694:37] - node _T_6176 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_6177 = and(_T_6175, _T_6176) @[ifu_mem_ctl.scala 694:59] - node _T_6178 = eq(perr_ic_index_ff, UInt<6>("h024")) @[ifu_mem_ctl.scala 694:102] - node _T_6179 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_6180 = and(_T_6178, _T_6179) @[ifu_mem_ctl.scala 694:124] - node _T_6181 = or(_T_6177, _T_6180) @[ifu_mem_ctl.scala 694:81] - node _T_6182 = or(_T_6181, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6183 = bits(_T_6182, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][35] <= _T_6169 @[ifu_mem_ctl.scala 692:41] + node _T_6170 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6171 = eq(_T_6170, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6172 = and(ic_valid_ff, _T_6171) @[ifu_mem_ctl.scala 692:97] + node _T_6173 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6174 = and(_T_6172, _T_6173) @[ifu_mem_ctl.scala 692:122] + node _T_6175 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[ifu_mem_ctl.scala 693:37] + node _T_6176 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_6177 = and(_T_6175, _T_6176) @[ifu_mem_ctl.scala 693:59] + node _T_6178 = eq(perr_ic_index_ff, UInt<6>("h024")) @[ifu_mem_ctl.scala 693:102] + node _T_6179 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_6180 = and(_T_6178, _T_6179) @[ifu_mem_ctl.scala 693:124] + node _T_6181 = or(_T_6177, _T_6180) @[ifu_mem_ctl.scala 693:81] + node _T_6182 = or(_T_6181, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6183 = bits(_T_6182, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6184 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6183 : @[Reg.scala 28:19] _T_6184 <= _T_6174 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][36] <= _T_6184 @[ifu_mem_ctl.scala 693:41] - node _T_6185 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6186 = eq(_T_6185, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6187 = and(ic_valid_ff, _T_6186) @[ifu_mem_ctl.scala 693:97] - node _T_6188 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6189 = and(_T_6187, _T_6188) @[ifu_mem_ctl.scala 693:122] - node _T_6190 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[ifu_mem_ctl.scala 694:37] - node _T_6191 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_6192 = and(_T_6190, _T_6191) @[ifu_mem_ctl.scala 694:59] - node _T_6193 = eq(perr_ic_index_ff, UInt<6>("h025")) @[ifu_mem_ctl.scala 694:102] - node _T_6194 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_6195 = and(_T_6193, _T_6194) @[ifu_mem_ctl.scala 694:124] - node _T_6196 = or(_T_6192, _T_6195) @[ifu_mem_ctl.scala 694:81] - node _T_6197 = or(_T_6196, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6198 = bits(_T_6197, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][36] <= _T_6184 @[ifu_mem_ctl.scala 692:41] + node _T_6185 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6186 = eq(_T_6185, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6187 = and(ic_valid_ff, _T_6186) @[ifu_mem_ctl.scala 692:97] + node _T_6188 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6189 = and(_T_6187, _T_6188) @[ifu_mem_ctl.scala 692:122] + node _T_6190 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[ifu_mem_ctl.scala 693:37] + node _T_6191 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_6192 = and(_T_6190, _T_6191) @[ifu_mem_ctl.scala 693:59] + node _T_6193 = eq(perr_ic_index_ff, UInt<6>("h025")) @[ifu_mem_ctl.scala 693:102] + node _T_6194 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_6195 = and(_T_6193, _T_6194) @[ifu_mem_ctl.scala 693:124] + node _T_6196 = or(_T_6192, _T_6195) @[ifu_mem_ctl.scala 693:81] + node _T_6197 = or(_T_6196, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6198 = bits(_T_6197, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6199 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6198 : @[Reg.scala 28:19] _T_6199 <= _T_6189 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][37] <= _T_6199 @[ifu_mem_ctl.scala 693:41] - node _T_6200 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6201 = eq(_T_6200, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6202 = and(ic_valid_ff, _T_6201) @[ifu_mem_ctl.scala 693:97] - node _T_6203 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6204 = and(_T_6202, _T_6203) @[ifu_mem_ctl.scala 693:122] - node _T_6205 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[ifu_mem_ctl.scala 694:37] - node _T_6206 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_6207 = and(_T_6205, _T_6206) @[ifu_mem_ctl.scala 694:59] - node _T_6208 = eq(perr_ic_index_ff, UInt<6>("h026")) @[ifu_mem_ctl.scala 694:102] - node _T_6209 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_6210 = and(_T_6208, _T_6209) @[ifu_mem_ctl.scala 694:124] - node _T_6211 = or(_T_6207, _T_6210) @[ifu_mem_ctl.scala 694:81] - node _T_6212 = or(_T_6211, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6213 = bits(_T_6212, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][37] <= _T_6199 @[ifu_mem_ctl.scala 692:41] + node _T_6200 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6201 = eq(_T_6200, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6202 = and(ic_valid_ff, _T_6201) @[ifu_mem_ctl.scala 692:97] + node _T_6203 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6204 = and(_T_6202, _T_6203) @[ifu_mem_ctl.scala 692:122] + node _T_6205 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[ifu_mem_ctl.scala 693:37] + node _T_6206 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_6207 = and(_T_6205, _T_6206) @[ifu_mem_ctl.scala 693:59] + node _T_6208 = eq(perr_ic_index_ff, UInt<6>("h026")) @[ifu_mem_ctl.scala 693:102] + node _T_6209 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_6210 = and(_T_6208, _T_6209) @[ifu_mem_ctl.scala 693:124] + node _T_6211 = or(_T_6207, _T_6210) @[ifu_mem_ctl.scala 693:81] + node _T_6212 = or(_T_6211, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6213 = bits(_T_6212, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6214 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6213 : @[Reg.scala 28:19] _T_6214 <= _T_6204 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][38] <= _T_6214 @[ifu_mem_ctl.scala 693:41] - node _T_6215 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6216 = eq(_T_6215, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6217 = and(ic_valid_ff, _T_6216) @[ifu_mem_ctl.scala 693:97] - node _T_6218 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6219 = and(_T_6217, _T_6218) @[ifu_mem_ctl.scala 693:122] - node _T_6220 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[ifu_mem_ctl.scala 694:37] - node _T_6221 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_6222 = and(_T_6220, _T_6221) @[ifu_mem_ctl.scala 694:59] - node _T_6223 = eq(perr_ic_index_ff, UInt<6>("h027")) @[ifu_mem_ctl.scala 694:102] - node _T_6224 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_6225 = and(_T_6223, _T_6224) @[ifu_mem_ctl.scala 694:124] - node _T_6226 = or(_T_6222, _T_6225) @[ifu_mem_ctl.scala 694:81] - node _T_6227 = or(_T_6226, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6228 = bits(_T_6227, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][38] <= _T_6214 @[ifu_mem_ctl.scala 692:41] + node _T_6215 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6216 = eq(_T_6215, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6217 = and(ic_valid_ff, _T_6216) @[ifu_mem_ctl.scala 692:97] + node _T_6218 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6219 = and(_T_6217, _T_6218) @[ifu_mem_ctl.scala 692:122] + node _T_6220 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[ifu_mem_ctl.scala 693:37] + node _T_6221 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_6222 = and(_T_6220, _T_6221) @[ifu_mem_ctl.scala 693:59] + node _T_6223 = eq(perr_ic_index_ff, UInt<6>("h027")) @[ifu_mem_ctl.scala 693:102] + node _T_6224 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_6225 = and(_T_6223, _T_6224) @[ifu_mem_ctl.scala 693:124] + node _T_6226 = or(_T_6222, _T_6225) @[ifu_mem_ctl.scala 693:81] + node _T_6227 = or(_T_6226, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6228 = bits(_T_6227, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6229 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6228 : @[Reg.scala 28:19] _T_6229 <= _T_6219 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][39] <= _T_6229 @[ifu_mem_ctl.scala 693:41] - node _T_6230 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6231 = eq(_T_6230, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6232 = and(ic_valid_ff, _T_6231) @[ifu_mem_ctl.scala 693:97] - node _T_6233 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6234 = and(_T_6232, _T_6233) @[ifu_mem_ctl.scala 693:122] - node _T_6235 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[ifu_mem_ctl.scala 694:37] - node _T_6236 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_6237 = and(_T_6235, _T_6236) @[ifu_mem_ctl.scala 694:59] - node _T_6238 = eq(perr_ic_index_ff, UInt<6>("h028")) @[ifu_mem_ctl.scala 694:102] - node _T_6239 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_6240 = and(_T_6238, _T_6239) @[ifu_mem_ctl.scala 694:124] - node _T_6241 = or(_T_6237, _T_6240) @[ifu_mem_ctl.scala 694:81] - node _T_6242 = or(_T_6241, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6243 = bits(_T_6242, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][39] <= _T_6229 @[ifu_mem_ctl.scala 692:41] + node _T_6230 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6231 = eq(_T_6230, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6232 = and(ic_valid_ff, _T_6231) @[ifu_mem_ctl.scala 692:97] + node _T_6233 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6234 = and(_T_6232, _T_6233) @[ifu_mem_ctl.scala 692:122] + node _T_6235 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[ifu_mem_ctl.scala 693:37] + node _T_6236 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_6237 = and(_T_6235, _T_6236) @[ifu_mem_ctl.scala 693:59] + node _T_6238 = eq(perr_ic_index_ff, UInt<6>("h028")) @[ifu_mem_ctl.scala 693:102] + node _T_6239 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_6240 = and(_T_6238, _T_6239) @[ifu_mem_ctl.scala 693:124] + node _T_6241 = or(_T_6237, _T_6240) @[ifu_mem_ctl.scala 693:81] + node _T_6242 = or(_T_6241, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6243 = bits(_T_6242, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6244 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6243 : @[Reg.scala 28:19] _T_6244 <= _T_6234 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][40] <= _T_6244 @[ifu_mem_ctl.scala 693:41] - node _T_6245 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6246 = eq(_T_6245, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6247 = and(ic_valid_ff, _T_6246) @[ifu_mem_ctl.scala 693:97] - node _T_6248 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6249 = and(_T_6247, _T_6248) @[ifu_mem_ctl.scala 693:122] - node _T_6250 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[ifu_mem_ctl.scala 694:37] - node _T_6251 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_6252 = and(_T_6250, _T_6251) @[ifu_mem_ctl.scala 694:59] - node _T_6253 = eq(perr_ic_index_ff, UInt<6>("h029")) @[ifu_mem_ctl.scala 694:102] - node _T_6254 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_6255 = and(_T_6253, _T_6254) @[ifu_mem_ctl.scala 694:124] - node _T_6256 = or(_T_6252, _T_6255) @[ifu_mem_ctl.scala 694:81] - node _T_6257 = or(_T_6256, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6258 = bits(_T_6257, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][40] <= _T_6244 @[ifu_mem_ctl.scala 692:41] + node _T_6245 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6246 = eq(_T_6245, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6247 = and(ic_valid_ff, _T_6246) @[ifu_mem_ctl.scala 692:97] + node _T_6248 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6249 = and(_T_6247, _T_6248) @[ifu_mem_ctl.scala 692:122] + node _T_6250 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[ifu_mem_ctl.scala 693:37] + node _T_6251 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_6252 = and(_T_6250, _T_6251) @[ifu_mem_ctl.scala 693:59] + node _T_6253 = eq(perr_ic_index_ff, UInt<6>("h029")) @[ifu_mem_ctl.scala 693:102] + node _T_6254 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_6255 = and(_T_6253, _T_6254) @[ifu_mem_ctl.scala 693:124] + node _T_6256 = or(_T_6252, _T_6255) @[ifu_mem_ctl.scala 693:81] + node _T_6257 = or(_T_6256, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6258 = bits(_T_6257, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6259 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6258 : @[Reg.scala 28:19] _T_6259 <= _T_6249 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][41] <= _T_6259 @[ifu_mem_ctl.scala 693:41] - node _T_6260 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6261 = eq(_T_6260, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6262 = and(ic_valid_ff, _T_6261) @[ifu_mem_ctl.scala 693:97] - node _T_6263 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6264 = and(_T_6262, _T_6263) @[ifu_mem_ctl.scala 693:122] - node _T_6265 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[ifu_mem_ctl.scala 694:37] - node _T_6266 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_6267 = and(_T_6265, _T_6266) @[ifu_mem_ctl.scala 694:59] - node _T_6268 = eq(perr_ic_index_ff, UInt<6>("h02a")) @[ifu_mem_ctl.scala 694:102] - node _T_6269 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_6270 = and(_T_6268, _T_6269) @[ifu_mem_ctl.scala 694:124] - node _T_6271 = or(_T_6267, _T_6270) @[ifu_mem_ctl.scala 694:81] - node _T_6272 = or(_T_6271, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6273 = bits(_T_6272, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][41] <= _T_6259 @[ifu_mem_ctl.scala 692:41] + node _T_6260 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6261 = eq(_T_6260, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6262 = and(ic_valid_ff, _T_6261) @[ifu_mem_ctl.scala 692:97] + node _T_6263 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6264 = and(_T_6262, _T_6263) @[ifu_mem_ctl.scala 692:122] + node _T_6265 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[ifu_mem_ctl.scala 693:37] + node _T_6266 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_6267 = and(_T_6265, _T_6266) @[ifu_mem_ctl.scala 693:59] + node _T_6268 = eq(perr_ic_index_ff, UInt<6>("h02a")) @[ifu_mem_ctl.scala 693:102] + node _T_6269 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_6270 = and(_T_6268, _T_6269) @[ifu_mem_ctl.scala 693:124] + node _T_6271 = or(_T_6267, _T_6270) @[ifu_mem_ctl.scala 693:81] + node _T_6272 = or(_T_6271, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6273 = bits(_T_6272, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6274 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6273 : @[Reg.scala 28:19] _T_6274 <= _T_6264 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][42] <= _T_6274 @[ifu_mem_ctl.scala 693:41] - node _T_6275 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6276 = eq(_T_6275, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6277 = and(ic_valid_ff, _T_6276) @[ifu_mem_ctl.scala 693:97] - node _T_6278 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6279 = and(_T_6277, _T_6278) @[ifu_mem_ctl.scala 693:122] - node _T_6280 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[ifu_mem_ctl.scala 694:37] - node _T_6281 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_6282 = and(_T_6280, _T_6281) @[ifu_mem_ctl.scala 694:59] - node _T_6283 = eq(perr_ic_index_ff, UInt<6>("h02b")) @[ifu_mem_ctl.scala 694:102] - node _T_6284 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_6285 = and(_T_6283, _T_6284) @[ifu_mem_ctl.scala 694:124] - node _T_6286 = or(_T_6282, _T_6285) @[ifu_mem_ctl.scala 694:81] - node _T_6287 = or(_T_6286, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6288 = bits(_T_6287, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][42] <= _T_6274 @[ifu_mem_ctl.scala 692:41] + node _T_6275 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6276 = eq(_T_6275, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6277 = and(ic_valid_ff, _T_6276) @[ifu_mem_ctl.scala 692:97] + node _T_6278 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6279 = and(_T_6277, _T_6278) @[ifu_mem_ctl.scala 692:122] + node _T_6280 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[ifu_mem_ctl.scala 693:37] + node _T_6281 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_6282 = and(_T_6280, _T_6281) @[ifu_mem_ctl.scala 693:59] + node _T_6283 = eq(perr_ic_index_ff, UInt<6>("h02b")) @[ifu_mem_ctl.scala 693:102] + node _T_6284 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_6285 = and(_T_6283, _T_6284) @[ifu_mem_ctl.scala 693:124] + node _T_6286 = or(_T_6282, _T_6285) @[ifu_mem_ctl.scala 693:81] + node _T_6287 = or(_T_6286, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6288 = bits(_T_6287, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6289 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6288 : @[Reg.scala 28:19] _T_6289 <= _T_6279 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][43] <= _T_6289 @[ifu_mem_ctl.scala 693:41] - node _T_6290 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6291 = eq(_T_6290, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6292 = and(ic_valid_ff, _T_6291) @[ifu_mem_ctl.scala 693:97] - node _T_6293 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6294 = and(_T_6292, _T_6293) @[ifu_mem_ctl.scala 693:122] - node _T_6295 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[ifu_mem_ctl.scala 694:37] - node _T_6296 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_6297 = and(_T_6295, _T_6296) @[ifu_mem_ctl.scala 694:59] - node _T_6298 = eq(perr_ic_index_ff, UInt<6>("h02c")) @[ifu_mem_ctl.scala 694:102] - node _T_6299 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_6300 = and(_T_6298, _T_6299) @[ifu_mem_ctl.scala 694:124] - node _T_6301 = or(_T_6297, _T_6300) @[ifu_mem_ctl.scala 694:81] - node _T_6302 = or(_T_6301, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6303 = bits(_T_6302, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][43] <= _T_6289 @[ifu_mem_ctl.scala 692:41] + node _T_6290 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6291 = eq(_T_6290, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6292 = and(ic_valid_ff, _T_6291) @[ifu_mem_ctl.scala 692:97] + node _T_6293 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6294 = and(_T_6292, _T_6293) @[ifu_mem_ctl.scala 692:122] + node _T_6295 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[ifu_mem_ctl.scala 693:37] + node _T_6296 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_6297 = and(_T_6295, _T_6296) @[ifu_mem_ctl.scala 693:59] + node _T_6298 = eq(perr_ic_index_ff, UInt<6>("h02c")) @[ifu_mem_ctl.scala 693:102] + node _T_6299 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_6300 = and(_T_6298, _T_6299) @[ifu_mem_ctl.scala 693:124] + node _T_6301 = or(_T_6297, _T_6300) @[ifu_mem_ctl.scala 693:81] + node _T_6302 = or(_T_6301, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6303 = bits(_T_6302, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6304 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6303 : @[Reg.scala 28:19] _T_6304 <= _T_6294 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][44] <= _T_6304 @[ifu_mem_ctl.scala 693:41] - node _T_6305 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6306 = eq(_T_6305, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6307 = and(ic_valid_ff, _T_6306) @[ifu_mem_ctl.scala 693:97] - node _T_6308 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6309 = and(_T_6307, _T_6308) @[ifu_mem_ctl.scala 693:122] - node _T_6310 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[ifu_mem_ctl.scala 694:37] - node _T_6311 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_6312 = and(_T_6310, _T_6311) @[ifu_mem_ctl.scala 694:59] - node _T_6313 = eq(perr_ic_index_ff, UInt<6>("h02d")) @[ifu_mem_ctl.scala 694:102] - node _T_6314 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_6315 = and(_T_6313, _T_6314) @[ifu_mem_ctl.scala 694:124] - node _T_6316 = or(_T_6312, _T_6315) @[ifu_mem_ctl.scala 694:81] - node _T_6317 = or(_T_6316, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6318 = bits(_T_6317, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][44] <= _T_6304 @[ifu_mem_ctl.scala 692:41] + node _T_6305 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6306 = eq(_T_6305, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6307 = and(ic_valid_ff, _T_6306) @[ifu_mem_ctl.scala 692:97] + node _T_6308 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6309 = and(_T_6307, _T_6308) @[ifu_mem_ctl.scala 692:122] + node _T_6310 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[ifu_mem_ctl.scala 693:37] + node _T_6311 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_6312 = and(_T_6310, _T_6311) @[ifu_mem_ctl.scala 693:59] + node _T_6313 = eq(perr_ic_index_ff, UInt<6>("h02d")) @[ifu_mem_ctl.scala 693:102] + node _T_6314 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_6315 = and(_T_6313, _T_6314) @[ifu_mem_ctl.scala 693:124] + node _T_6316 = or(_T_6312, _T_6315) @[ifu_mem_ctl.scala 693:81] + node _T_6317 = or(_T_6316, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6318 = bits(_T_6317, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6319 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6318 : @[Reg.scala 28:19] _T_6319 <= _T_6309 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][45] <= _T_6319 @[ifu_mem_ctl.scala 693:41] - node _T_6320 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6321 = eq(_T_6320, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6322 = and(ic_valid_ff, _T_6321) @[ifu_mem_ctl.scala 693:97] - node _T_6323 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6324 = and(_T_6322, _T_6323) @[ifu_mem_ctl.scala 693:122] - node _T_6325 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[ifu_mem_ctl.scala 694:37] - node _T_6326 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_6327 = and(_T_6325, _T_6326) @[ifu_mem_ctl.scala 694:59] - node _T_6328 = eq(perr_ic_index_ff, UInt<6>("h02e")) @[ifu_mem_ctl.scala 694:102] - node _T_6329 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_6330 = and(_T_6328, _T_6329) @[ifu_mem_ctl.scala 694:124] - node _T_6331 = or(_T_6327, _T_6330) @[ifu_mem_ctl.scala 694:81] - node _T_6332 = or(_T_6331, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6333 = bits(_T_6332, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][45] <= _T_6319 @[ifu_mem_ctl.scala 692:41] + node _T_6320 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6321 = eq(_T_6320, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6322 = and(ic_valid_ff, _T_6321) @[ifu_mem_ctl.scala 692:97] + node _T_6323 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6324 = and(_T_6322, _T_6323) @[ifu_mem_ctl.scala 692:122] + node _T_6325 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[ifu_mem_ctl.scala 693:37] + node _T_6326 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_6327 = and(_T_6325, _T_6326) @[ifu_mem_ctl.scala 693:59] + node _T_6328 = eq(perr_ic_index_ff, UInt<6>("h02e")) @[ifu_mem_ctl.scala 693:102] + node _T_6329 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_6330 = and(_T_6328, _T_6329) @[ifu_mem_ctl.scala 693:124] + node _T_6331 = or(_T_6327, _T_6330) @[ifu_mem_ctl.scala 693:81] + node _T_6332 = or(_T_6331, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6333 = bits(_T_6332, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6334 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6333 : @[Reg.scala 28:19] _T_6334 <= _T_6324 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][46] <= _T_6334 @[ifu_mem_ctl.scala 693:41] - node _T_6335 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6336 = eq(_T_6335, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6337 = and(ic_valid_ff, _T_6336) @[ifu_mem_ctl.scala 693:97] - node _T_6338 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6339 = and(_T_6337, _T_6338) @[ifu_mem_ctl.scala 693:122] - node _T_6340 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[ifu_mem_ctl.scala 694:37] - node _T_6341 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_6342 = and(_T_6340, _T_6341) @[ifu_mem_ctl.scala 694:59] - node _T_6343 = eq(perr_ic_index_ff, UInt<6>("h02f")) @[ifu_mem_ctl.scala 694:102] - node _T_6344 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_6345 = and(_T_6343, _T_6344) @[ifu_mem_ctl.scala 694:124] - node _T_6346 = or(_T_6342, _T_6345) @[ifu_mem_ctl.scala 694:81] - node _T_6347 = or(_T_6346, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6348 = bits(_T_6347, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][46] <= _T_6334 @[ifu_mem_ctl.scala 692:41] + node _T_6335 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6336 = eq(_T_6335, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6337 = and(ic_valid_ff, _T_6336) @[ifu_mem_ctl.scala 692:97] + node _T_6338 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6339 = and(_T_6337, _T_6338) @[ifu_mem_ctl.scala 692:122] + node _T_6340 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[ifu_mem_ctl.scala 693:37] + node _T_6341 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_6342 = and(_T_6340, _T_6341) @[ifu_mem_ctl.scala 693:59] + node _T_6343 = eq(perr_ic_index_ff, UInt<6>("h02f")) @[ifu_mem_ctl.scala 693:102] + node _T_6344 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_6345 = and(_T_6343, _T_6344) @[ifu_mem_ctl.scala 693:124] + node _T_6346 = or(_T_6342, _T_6345) @[ifu_mem_ctl.scala 693:81] + node _T_6347 = or(_T_6346, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6348 = bits(_T_6347, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6349 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6348 : @[Reg.scala 28:19] _T_6349 <= _T_6339 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][47] <= _T_6349 @[ifu_mem_ctl.scala 693:41] - node _T_6350 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6351 = eq(_T_6350, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6352 = and(ic_valid_ff, _T_6351) @[ifu_mem_ctl.scala 693:97] - node _T_6353 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6354 = and(_T_6352, _T_6353) @[ifu_mem_ctl.scala 693:122] - node _T_6355 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[ifu_mem_ctl.scala 694:37] - node _T_6356 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_6357 = and(_T_6355, _T_6356) @[ifu_mem_ctl.scala 694:59] - node _T_6358 = eq(perr_ic_index_ff, UInt<6>("h030")) @[ifu_mem_ctl.scala 694:102] - node _T_6359 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_6360 = and(_T_6358, _T_6359) @[ifu_mem_ctl.scala 694:124] - node _T_6361 = or(_T_6357, _T_6360) @[ifu_mem_ctl.scala 694:81] - node _T_6362 = or(_T_6361, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6363 = bits(_T_6362, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][47] <= _T_6349 @[ifu_mem_ctl.scala 692:41] + node _T_6350 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6351 = eq(_T_6350, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6352 = and(ic_valid_ff, _T_6351) @[ifu_mem_ctl.scala 692:97] + node _T_6353 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6354 = and(_T_6352, _T_6353) @[ifu_mem_ctl.scala 692:122] + node _T_6355 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[ifu_mem_ctl.scala 693:37] + node _T_6356 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_6357 = and(_T_6355, _T_6356) @[ifu_mem_ctl.scala 693:59] + node _T_6358 = eq(perr_ic_index_ff, UInt<6>("h030")) @[ifu_mem_ctl.scala 693:102] + node _T_6359 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_6360 = and(_T_6358, _T_6359) @[ifu_mem_ctl.scala 693:124] + node _T_6361 = or(_T_6357, _T_6360) @[ifu_mem_ctl.scala 693:81] + node _T_6362 = or(_T_6361, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6363 = bits(_T_6362, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6364 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6363 : @[Reg.scala 28:19] _T_6364 <= _T_6354 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][48] <= _T_6364 @[ifu_mem_ctl.scala 693:41] - node _T_6365 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6366 = eq(_T_6365, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6367 = and(ic_valid_ff, _T_6366) @[ifu_mem_ctl.scala 693:97] - node _T_6368 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6369 = and(_T_6367, _T_6368) @[ifu_mem_ctl.scala 693:122] - node _T_6370 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[ifu_mem_ctl.scala 694:37] - node _T_6371 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_6372 = and(_T_6370, _T_6371) @[ifu_mem_ctl.scala 694:59] - node _T_6373 = eq(perr_ic_index_ff, UInt<6>("h031")) @[ifu_mem_ctl.scala 694:102] - node _T_6374 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_6375 = and(_T_6373, _T_6374) @[ifu_mem_ctl.scala 694:124] - node _T_6376 = or(_T_6372, _T_6375) @[ifu_mem_ctl.scala 694:81] - node _T_6377 = or(_T_6376, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6378 = bits(_T_6377, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][48] <= _T_6364 @[ifu_mem_ctl.scala 692:41] + node _T_6365 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6366 = eq(_T_6365, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6367 = and(ic_valid_ff, _T_6366) @[ifu_mem_ctl.scala 692:97] + node _T_6368 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6369 = and(_T_6367, _T_6368) @[ifu_mem_ctl.scala 692:122] + node _T_6370 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[ifu_mem_ctl.scala 693:37] + node _T_6371 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_6372 = and(_T_6370, _T_6371) @[ifu_mem_ctl.scala 693:59] + node _T_6373 = eq(perr_ic_index_ff, UInt<6>("h031")) @[ifu_mem_ctl.scala 693:102] + node _T_6374 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_6375 = and(_T_6373, _T_6374) @[ifu_mem_ctl.scala 693:124] + node _T_6376 = or(_T_6372, _T_6375) @[ifu_mem_ctl.scala 693:81] + node _T_6377 = or(_T_6376, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6378 = bits(_T_6377, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6379 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6378 : @[Reg.scala 28:19] _T_6379 <= _T_6369 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][49] <= _T_6379 @[ifu_mem_ctl.scala 693:41] - node _T_6380 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6381 = eq(_T_6380, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6382 = and(ic_valid_ff, _T_6381) @[ifu_mem_ctl.scala 693:97] - node _T_6383 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6384 = and(_T_6382, _T_6383) @[ifu_mem_ctl.scala 693:122] - node _T_6385 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[ifu_mem_ctl.scala 694:37] - node _T_6386 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_6387 = and(_T_6385, _T_6386) @[ifu_mem_ctl.scala 694:59] - node _T_6388 = eq(perr_ic_index_ff, UInt<6>("h032")) @[ifu_mem_ctl.scala 694:102] - node _T_6389 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_6390 = and(_T_6388, _T_6389) @[ifu_mem_ctl.scala 694:124] - node _T_6391 = or(_T_6387, _T_6390) @[ifu_mem_ctl.scala 694:81] - node _T_6392 = or(_T_6391, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6393 = bits(_T_6392, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][49] <= _T_6379 @[ifu_mem_ctl.scala 692:41] + node _T_6380 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6381 = eq(_T_6380, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6382 = and(ic_valid_ff, _T_6381) @[ifu_mem_ctl.scala 692:97] + node _T_6383 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6384 = and(_T_6382, _T_6383) @[ifu_mem_ctl.scala 692:122] + node _T_6385 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[ifu_mem_ctl.scala 693:37] + node _T_6386 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_6387 = and(_T_6385, _T_6386) @[ifu_mem_ctl.scala 693:59] + node _T_6388 = eq(perr_ic_index_ff, UInt<6>("h032")) @[ifu_mem_ctl.scala 693:102] + node _T_6389 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_6390 = and(_T_6388, _T_6389) @[ifu_mem_ctl.scala 693:124] + node _T_6391 = or(_T_6387, _T_6390) @[ifu_mem_ctl.scala 693:81] + node _T_6392 = or(_T_6391, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6393 = bits(_T_6392, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6394 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6393 : @[Reg.scala 28:19] _T_6394 <= _T_6384 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][50] <= _T_6394 @[ifu_mem_ctl.scala 693:41] - node _T_6395 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6396 = eq(_T_6395, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6397 = and(ic_valid_ff, _T_6396) @[ifu_mem_ctl.scala 693:97] - node _T_6398 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6399 = and(_T_6397, _T_6398) @[ifu_mem_ctl.scala 693:122] - node _T_6400 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[ifu_mem_ctl.scala 694:37] - node _T_6401 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_6402 = and(_T_6400, _T_6401) @[ifu_mem_ctl.scala 694:59] - node _T_6403 = eq(perr_ic_index_ff, UInt<6>("h033")) @[ifu_mem_ctl.scala 694:102] - node _T_6404 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_6405 = and(_T_6403, _T_6404) @[ifu_mem_ctl.scala 694:124] - node _T_6406 = or(_T_6402, _T_6405) @[ifu_mem_ctl.scala 694:81] - node _T_6407 = or(_T_6406, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6408 = bits(_T_6407, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][50] <= _T_6394 @[ifu_mem_ctl.scala 692:41] + node _T_6395 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6396 = eq(_T_6395, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6397 = and(ic_valid_ff, _T_6396) @[ifu_mem_ctl.scala 692:97] + node _T_6398 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6399 = and(_T_6397, _T_6398) @[ifu_mem_ctl.scala 692:122] + node _T_6400 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[ifu_mem_ctl.scala 693:37] + node _T_6401 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_6402 = and(_T_6400, _T_6401) @[ifu_mem_ctl.scala 693:59] + node _T_6403 = eq(perr_ic_index_ff, UInt<6>("h033")) @[ifu_mem_ctl.scala 693:102] + node _T_6404 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_6405 = and(_T_6403, _T_6404) @[ifu_mem_ctl.scala 693:124] + node _T_6406 = or(_T_6402, _T_6405) @[ifu_mem_ctl.scala 693:81] + node _T_6407 = or(_T_6406, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6408 = bits(_T_6407, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6409 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6408 : @[Reg.scala 28:19] _T_6409 <= _T_6399 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][51] <= _T_6409 @[ifu_mem_ctl.scala 693:41] - node _T_6410 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6411 = eq(_T_6410, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6412 = and(ic_valid_ff, _T_6411) @[ifu_mem_ctl.scala 693:97] - node _T_6413 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6414 = and(_T_6412, _T_6413) @[ifu_mem_ctl.scala 693:122] - node _T_6415 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[ifu_mem_ctl.scala 694:37] - node _T_6416 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_6417 = and(_T_6415, _T_6416) @[ifu_mem_ctl.scala 694:59] - node _T_6418 = eq(perr_ic_index_ff, UInt<6>("h034")) @[ifu_mem_ctl.scala 694:102] - node _T_6419 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_6420 = and(_T_6418, _T_6419) @[ifu_mem_ctl.scala 694:124] - node _T_6421 = or(_T_6417, _T_6420) @[ifu_mem_ctl.scala 694:81] - node _T_6422 = or(_T_6421, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6423 = bits(_T_6422, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][51] <= _T_6409 @[ifu_mem_ctl.scala 692:41] + node _T_6410 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6411 = eq(_T_6410, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6412 = and(ic_valid_ff, _T_6411) @[ifu_mem_ctl.scala 692:97] + node _T_6413 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6414 = and(_T_6412, _T_6413) @[ifu_mem_ctl.scala 692:122] + node _T_6415 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[ifu_mem_ctl.scala 693:37] + node _T_6416 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_6417 = and(_T_6415, _T_6416) @[ifu_mem_ctl.scala 693:59] + node _T_6418 = eq(perr_ic_index_ff, UInt<6>("h034")) @[ifu_mem_ctl.scala 693:102] + node _T_6419 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_6420 = and(_T_6418, _T_6419) @[ifu_mem_ctl.scala 693:124] + node _T_6421 = or(_T_6417, _T_6420) @[ifu_mem_ctl.scala 693:81] + node _T_6422 = or(_T_6421, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6423 = bits(_T_6422, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6424 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6423 : @[Reg.scala 28:19] _T_6424 <= _T_6414 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][52] <= _T_6424 @[ifu_mem_ctl.scala 693:41] - node _T_6425 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6426 = eq(_T_6425, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6427 = and(ic_valid_ff, _T_6426) @[ifu_mem_ctl.scala 693:97] - node _T_6428 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6429 = and(_T_6427, _T_6428) @[ifu_mem_ctl.scala 693:122] - node _T_6430 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[ifu_mem_ctl.scala 694:37] - node _T_6431 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_6432 = and(_T_6430, _T_6431) @[ifu_mem_ctl.scala 694:59] - node _T_6433 = eq(perr_ic_index_ff, UInt<6>("h035")) @[ifu_mem_ctl.scala 694:102] - node _T_6434 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_6435 = and(_T_6433, _T_6434) @[ifu_mem_ctl.scala 694:124] - node _T_6436 = or(_T_6432, _T_6435) @[ifu_mem_ctl.scala 694:81] - node _T_6437 = or(_T_6436, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6438 = bits(_T_6437, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][52] <= _T_6424 @[ifu_mem_ctl.scala 692:41] + node _T_6425 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6426 = eq(_T_6425, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6427 = and(ic_valid_ff, _T_6426) @[ifu_mem_ctl.scala 692:97] + node _T_6428 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6429 = and(_T_6427, _T_6428) @[ifu_mem_ctl.scala 692:122] + node _T_6430 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[ifu_mem_ctl.scala 693:37] + node _T_6431 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_6432 = and(_T_6430, _T_6431) @[ifu_mem_ctl.scala 693:59] + node _T_6433 = eq(perr_ic_index_ff, UInt<6>("h035")) @[ifu_mem_ctl.scala 693:102] + node _T_6434 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_6435 = and(_T_6433, _T_6434) @[ifu_mem_ctl.scala 693:124] + node _T_6436 = or(_T_6432, _T_6435) @[ifu_mem_ctl.scala 693:81] + node _T_6437 = or(_T_6436, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6438 = bits(_T_6437, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6439 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6438 : @[Reg.scala 28:19] _T_6439 <= _T_6429 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][53] <= _T_6439 @[ifu_mem_ctl.scala 693:41] - node _T_6440 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6441 = eq(_T_6440, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6442 = and(ic_valid_ff, _T_6441) @[ifu_mem_ctl.scala 693:97] - node _T_6443 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6444 = and(_T_6442, _T_6443) @[ifu_mem_ctl.scala 693:122] - node _T_6445 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[ifu_mem_ctl.scala 694:37] - node _T_6446 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_6447 = and(_T_6445, _T_6446) @[ifu_mem_ctl.scala 694:59] - node _T_6448 = eq(perr_ic_index_ff, UInt<6>("h036")) @[ifu_mem_ctl.scala 694:102] - node _T_6449 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_6450 = and(_T_6448, _T_6449) @[ifu_mem_ctl.scala 694:124] - node _T_6451 = or(_T_6447, _T_6450) @[ifu_mem_ctl.scala 694:81] - node _T_6452 = or(_T_6451, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6453 = bits(_T_6452, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][53] <= _T_6439 @[ifu_mem_ctl.scala 692:41] + node _T_6440 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6441 = eq(_T_6440, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6442 = and(ic_valid_ff, _T_6441) @[ifu_mem_ctl.scala 692:97] + node _T_6443 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6444 = and(_T_6442, _T_6443) @[ifu_mem_ctl.scala 692:122] + node _T_6445 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[ifu_mem_ctl.scala 693:37] + node _T_6446 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_6447 = and(_T_6445, _T_6446) @[ifu_mem_ctl.scala 693:59] + node _T_6448 = eq(perr_ic_index_ff, UInt<6>("h036")) @[ifu_mem_ctl.scala 693:102] + node _T_6449 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_6450 = and(_T_6448, _T_6449) @[ifu_mem_ctl.scala 693:124] + node _T_6451 = or(_T_6447, _T_6450) @[ifu_mem_ctl.scala 693:81] + node _T_6452 = or(_T_6451, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6453 = bits(_T_6452, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6454 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6453 : @[Reg.scala 28:19] _T_6454 <= _T_6444 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][54] <= _T_6454 @[ifu_mem_ctl.scala 693:41] - node _T_6455 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6456 = eq(_T_6455, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6457 = and(ic_valid_ff, _T_6456) @[ifu_mem_ctl.scala 693:97] - node _T_6458 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6459 = and(_T_6457, _T_6458) @[ifu_mem_ctl.scala 693:122] - node _T_6460 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[ifu_mem_ctl.scala 694:37] - node _T_6461 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_6462 = and(_T_6460, _T_6461) @[ifu_mem_ctl.scala 694:59] - node _T_6463 = eq(perr_ic_index_ff, UInt<6>("h037")) @[ifu_mem_ctl.scala 694:102] - node _T_6464 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_6465 = and(_T_6463, _T_6464) @[ifu_mem_ctl.scala 694:124] - node _T_6466 = or(_T_6462, _T_6465) @[ifu_mem_ctl.scala 694:81] - node _T_6467 = or(_T_6466, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6468 = bits(_T_6467, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][54] <= _T_6454 @[ifu_mem_ctl.scala 692:41] + node _T_6455 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6456 = eq(_T_6455, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6457 = and(ic_valid_ff, _T_6456) @[ifu_mem_ctl.scala 692:97] + node _T_6458 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6459 = and(_T_6457, _T_6458) @[ifu_mem_ctl.scala 692:122] + node _T_6460 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[ifu_mem_ctl.scala 693:37] + node _T_6461 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_6462 = and(_T_6460, _T_6461) @[ifu_mem_ctl.scala 693:59] + node _T_6463 = eq(perr_ic_index_ff, UInt<6>("h037")) @[ifu_mem_ctl.scala 693:102] + node _T_6464 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_6465 = and(_T_6463, _T_6464) @[ifu_mem_ctl.scala 693:124] + node _T_6466 = or(_T_6462, _T_6465) @[ifu_mem_ctl.scala 693:81] + node _T_6467 = or(_T_6466, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6468 = bits(_T_6467, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6469 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6468 : @[Reg.scala 28:19] _T_6469 <= _T_6459 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][55] <= _T_6469 @[ifu_mem_ctl.scala 693:41] - node _T_6470 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6471 = eq(_T_6470, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6472 = and(ic_valid_ff, _T_6471) @[ifu_mem_ctl.scala 693:97] - node _T_6473 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6474 = and(_T_6472, _T_6473) @[ifu_mem_ctl.scala 693:122] - node _T_6475 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[ifu_mem_ctl.scala 694:37] - node _T_6476 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_6477 = and(_T_6475, _T_6476) @[ifu_mem_ctl.scala 694:59] - node _T_6478 = eq(perr_ic_index_ff, UInt<6>("h038")) @[ifu_mem_ctl.scala 694:102] - node _T_6479 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_6480 = and(_T_6478, _T_6479) @[ifu_mem_ctl.scala 694:124] - node _T_6481 = or(_T_6477, _T_6480) @[ifu_mem_ctl.scala 694:81] - node _T_6482 = or(_T_6481, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6483 = bits(_T_6482, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][55] <= _T_6469 @[ifu_mem_ctl.scala 692:41] + node _T_6470 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6471 = eq(_T_6470, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6472 = and(ic_valid_ff, _T_6471) @[ifu_mem_ctl.scala 692:97] + node _T_6473 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6474 = and(_T_6472, _T_6473) @[ifu_mem_ctl.scala 692:122] + node _T_6475 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[ifu_mem_ctl.scala 693:37] + node _T_6476 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_6477 = and(_T_6475, _T_6476) @[ifu_mem_ctl.scala 693:59] + node _T_6478 = eq(perr_ic_index_ff, UInt<6>("h038")) @[ifu_mem_ctl.scala 693:102] + node _T_6479 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_6480 = and(_T_6478, _T_6479) @[ifu_mem_ctl.scala 693:124] + node _T_6481 = or(_T_6477, _T_6480) @[ifu_mem_ctl.scala 693:81] + node _T_6482 = or(_T_6481, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6483 = bits(_T_6482, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6484 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6483 : @[Reg.scala 28:19] _T_6484 <= _T_6474 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][56] <= _T_6484 @[ifu_mem_ctl.scala 693:41] - node _T_6485 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6486 = eq(_T_6485, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6487 = and(ic_valid_ff, _T_6486) @[ifu_mem_ctl.scala 693:97] - node _T_6488 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6489 = and(_T_6487, _T_6488) @[ifu_mem_ctl.scala 693:122] - node _T_6490 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[ifu_mem_ctl.scala 694:37] - node _T_6491 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_6492 = and(_T_6490, _T_6491) @[ifu_mem_ctl.scala 694:59] - node _T_6493 = eq(perr_ic_index_ff, UInt<6>("h039")) @[ifu_mem_ctl.scala 694:102] - node _T_6494 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_6495 = and(_T_6493, _T_6494) @[ifu_mem_ctl.scala 694:124] - node _T_6496 = or(_T_6492, _T_6495) @[ifu_mem_ctl.scala 694:81] - node _T_6497 = or(_T_6496, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6498 = bits(_T_6497, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][56] <= _T_6484 @[ifu_mem_ctl.scala 692:41] + node _T_6485 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6486 = eq(_T_6485, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6487 = and(ic_valid_ff, _T_6486) @[ifu_mem_ctl.scala 692:97] + node _T_6488 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6489 = and(_T_6487, _T_6488) @[ifu_mem_ctl.scala 692:122] + node _T_6490 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[ifu_mem_ctl.scala 693:37] + node _T_6491 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_6492 = and(_T_6490, _T_6491) @[ifu_mem_ctl.scala 693:59] + node _T_6493 = eq(perr_ic_index_ff, UInt<6>("h039")) @[ifu_mem_ctl.scala 693:102] + node _T_6494 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_6495 = and(_T_6493, _T_6494) @[ifu_mem_ctl.scala 693:124] + node _T_6496 = or(_T_6492, _T_6495) @[ifu_mem_ctl.scala 693:81] + node _T_6497 = or(_T_6496, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6498 = bits(_T_6497, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6499 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6498 : @[Reg.scala 28:19] _T_6499 <= _T_6489 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][57] <= _T_6499 @[ifu_mem_ctl.scala 693:41] - node _T_6500 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6501 = eq(_T_6500, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6502 = and(ic_valid_ff, _T_6501) @[ifu_mem_ctl.scala 693:97] - node _T_6503 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6504 = and(_T_6502, _T_6503) @[ifu_mem_ctl.scala 693:122] - node _T_6505 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[ifu_mem_ctl.scala 694:37] - node _T_6506 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_6507 = and(_T_6505, _T_6506) @[ifu_mem_ctl.scala 694:59] - node _T_6508 = eq(perr_ic_index_ff, UInt<6>("h03a")) @[ifu_mem_ctl.scala 694:102] - node _T_6509 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_6510 = and(_T_6508, _T_6509) @[ifu_mem_ctl.scala 694:124] - node _T_6511 = or(_T_6507, _T_6510) @[ifu_mem_ctl.scala 694:81] - node _T_6512 = or(_T_6511, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6513 = bits(_T_6512, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][57] <= _T_6499 @[ifu_mem_ctl.scala 692:41] + node _T_6500 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6501 = eq(_T_6500, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6502 = and(ic_valid_ff, _T_6501) @[ifu_mem_ctl.scala 692:97] + node _T_6503 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6504 = and(_T_6502, _T_6503) @[ifu_mem_ctl.scala 692:122] + node _T_6505 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[ifu_mem_ctl.scala 693:37] + node _T_6506 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_6507 = and(_T_6505, _T_6506) @[ifu_mem_ctl.scala 693:59] + node _T_6508 = eq(perr_ic_index_ff, UInt<6>("h03a")) @[ifu_mem_ctl.scala 693:102] + node _T_6509 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_6510 = and(_T_6508, _T_6509) @[ifu_mem_ctl.scala 693:124] + node _T_6511 = or(_T_6507, _T_6510) @[ifu_mem_ctl.scala 693:81] + node _T_6512 = or(_T_6511, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6513 = bits(_T_6512, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6514 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6513 : @[Reg.scala 28:19] _T_6514 <= _T_6504 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][58] <= _T_6514 @[ifu_mem_ctl.scala 693:41] - node _T_6515 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6516 = eq(_T_6515, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6517 = and(ic_valid_ff, _T_6516) @[ifu_mem_ctl.scala 693:97] - node _T_6518 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6519 = and(_T_6517, _T_6518) @[ifu_mem_ctl.scala 693:122] - node _T_6520 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[ifu_mem_ctl.scala 694:37] - node _T_6521 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_6522 = and(_T_6520, _T_6521) @[ifu_mem_ctl.scala 694:59] - node _T_6523 = eq(perr_ic_index_ff, UInt<6>("h03b")) @[ifu_mem_ctl.scala 694:102] - node _T_6524 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_6525 = and(_T_6523, _T_6524) @[ifu_mem_ctl.scala 694:124] - node _T_6526 = or(_T_6522, _T_6525) @[ifu_mem_ctl.scala 694:81] - node _T_6527 = or(_T_6526, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6528 = bits(_T_6527, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][58] <= _T_6514 @[ifu_mem_ctl.scala 692:41] + node _T_6515 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6516 = eq(_T_6515, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6517 = and(ic_valid_ff, _T_6516) @[ifu_mem_ctl.scala 692:97] + node _T_6518 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6519 = and(_T_6517, _T_6518) @[ifu_mem_ctl.scala 692:122] + node _T_6520 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[ifu_mem_ctl.scala 693:37] + node _T_6521 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_6522 = and(_T_6520, _T_6521) @[ifu_mem_ctl.scala 693:59] + node _T_6523 = eq(perr_ic_index_ff, UInt<6>("h03b")) @[ifu_mem_ctl.scala 693:102] + node _T_6524 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_6525 = and(_T_6523, _T_6524) @[ifu_mem_ctl.scala 693:124] + node _T_6526 = or(_T_6522, _T_6525) @[ifu_mem_ctl.scala 693:81] + node _T_6527 = or(_T_6526, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6528 = bits(_T_6527, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6529 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6528 : @[Reg.scala 28:19] _T_6529 <= _T_6519 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][59] <= _T_6529 @[ifu_mem_ctl.scala 693:41] - node _T_6530 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6531 = eq(_T_6530, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6532 = and(ic_valid_ff, _T_6531) @[ifu_mem_ctl.scala 693:97] - node _T_6533 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6534 = and(_T_6532, _T_6533) @[ifu_mem_ctl.scala 693:122] - node _T_6535 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[ifu_mem_ctl.scala 694:37] - node _T_6536 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_6537 = and(_T_6535, _T_6536) @[ifu_mem_ctl.scala 694:59] - node _T_6538 = eq(perr_ic_index_ff, UInt<6>("h03c")) @[ifu_mem_ctl.scala 694:102] - node _T_6539 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_6540 = and(_T_6538, _T_6539) @[ifu_mem_ctl.scala 694:124] - node _T_6541 = or(_T_6537, _T_6540) @[ifu_mem_ctl.scala 694:81] - node _T_6542 = or(_T_6541, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6543 = bits(_T_6542, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][59] <= _T_6529 @[ifu_mem_ctl.scala 692:41] + node _T_6530 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6531 = eq(_T_6530, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6532 = and(ic_valid_ff, _T_6531) @[ifu_mem_ctl.scala 692:97] + node _T_6533 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6534 = and(_T_6532, _T_6533) @[ifu_mem_ctl.scala 692:122] + node _T_6535 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[ifu_mem_ctl.scala 693:37] + node _T_6536 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_6537 = and(_T_6535, _T_6536) @[ifu_mem_ctl.scala 693:59] + node _T_6538 = eq(perr_ic_index_ff, UInt<6>("h03c")) @[ifu_mem_ctl.scala 693:102] + node _T_6539 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_6540 = and(_T_6538, _T_6539) @[ifu_mem_ctl.scala 693:124] + node _T_6541 = or(_T_6537, _T_6540) @[ifu_mem_ctl.scala 693:81] + node _T_6542 = or(_T_6541, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6543 = bits(_T_6542, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6544 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6543 : @[Reg.scala 28:19] _T_6544 <= _T_6534 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][60] <= _T_6544 @[ifu_mem_ctl.scala 693:41] - node _T_6545 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6546 = eq(_T_6545, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6547 = and(ic_valid_ff, _T_6546) @[ifu_mem_ctl.scala 693:97] - node _T_6548 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6549 = and(_T_6547, _T_6548) @[ifu_mem_ctl.scala 693:122] - node _T_6550 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[ifu_mem_ctl.scala 694:37] - node _T_6551 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_6552 = and(_T_6550, _T_6551) @[ifu_mem_ctl.scala 694:59] - node _T_6553 = eq(perr_ic_index_ff, UInt<6>("h03d")) @[ifu_mem_ctl.scala 694:102] - node _T_6554 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_6555 = and(_T_6553, _T_6554) @[ifu_mem_ctl.scala 694:124] - node _T_6556 = or(_T_6552, _T_6555) @[ifu_mem_ctl.scala 694:81] - node _T_6557 = or(_T_6556, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6558 = bits(_T_6557, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][60] <= _T_6544 @[ifu_mem_ctl.scala 692:41] + node _T_6545 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6546 = eq(_T_6545, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6547 = and(ic_valid_ff, _T_6546) @[ifu_mem_ctl.scala 692:97] + node _T_6548 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6549 = and(_T_6547, _T_6548) @[ifu_mem_ctl.scala 692:122] + node _T_6550 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[ifu_mem_ctl.scala 693:37] + node _T_6551 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_6552 = and(_T_6550, _T_6551) @[ifu_mem_ctl.scala 693:59] + node _T_6553 = eq(perr_ic_index_ff, UInt<6>("h03d")) @[ifu_mem_ctl.scala 693:102] + node _T_6554 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_6555 = and(_T_6553, _T_6554) @[ifu_mem_ctl.scala 693:124] + node _T_6556 = or(_T_6552, _T_6555) @[ifu_mem_ctl.scala 693:81] + node _T_6557 = or(_T_6556, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6558 = bits(_T_6557, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6559 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6558 : @[Reg.scala 28:19] _T_6559 <= _T_6549 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][61] <= _T_6559 @[ifu_mem_ctl.scala 693:41] - node _T_6560 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6561 = eq(_T_6560, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6562 = and(ic_valid_ff, _T_6561) @[ifu_mem_ctl.scala 693:97] - node _T_6563 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6564 = and(_T_6562, _T_6563) @[ifu_mem_ctl.scala 693:122] - node _T_6565 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[ifu_mem_ctl.scala 694:37] - node _T_6566 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_6567 = and(_T_6565, _T_6566) @[ifu_mem_ctl.scala 694:59] - node _T_6568 = eq(perr_ic_index_ff, UInt<6>("h03e")) @[ifu_mem_ctl.scala 694:102] - node _T_6569 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_6570 = and(_T_6568, _T_6569) @[ifu_mem_ctl.scala 694:124] - node _T_6571 = or(_T_6567, _T_6570) @[ifu_mem_ctl.scala 694:81] - node _T_6572 = or(_T_6571, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6573 = bits(_T_6572, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][61] <= _T_6559 @[ifu_mem_ctl.scala 692:41] + node _T_6560 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6561 = eq(_T_6560, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6562 = and(ic_valid_ff, _T_6561) @[ifu_mem_ctl.scala 692:97] + node _T_6563 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6564 = and(_T_6562, _T_6563) @[ifu_mem_ctl.scala 692:122] + node _T_6565 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[ifu_mem_ctl.scala 693:37] + node _T_6566 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_6567 = and(_T_6565, _T_6566) @[ifu_mem_ctl.scala 693:59] + node _T_6568 = eq(perr_ic_index_ff, UInt<6>("h03e")) @[ifu_mem_ctl.scala 693:102] + node _T_6569 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_6570 = and(_T_6568, _T_6569) @[ifu_mem_ctl.scala 693:124] + node _T_6571 = or(_T_6567, _T_6570) @[ifu_mem_ctl.scala 693:81] + node _T_6572 = or(_T_6571, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6573 = bits(_T_6572, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6574 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6573 : @[Reg.scala 28:19] _T_6574 <= _T_6564 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][62] <= _T_6574 @[ifu_mem_ctl.scala 693:41] - node _T_6575 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6576 = eq(_T_6575, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6577 = and(ic_valid_ff, _T_6576) @[ifu_mem_ctl.scala 693:97] - node _T_6578 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6579 = and(_T_6577, _T_6578) @[ifu_mem_ctl.scala 693:122] - node _T_6580 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[ifu_mem_ctl.scala 694:37] - node _T_6581 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_6582 = and(_T_6580, _T_6581) @[ifu_mem_ctl.scala 694:59] - node _T_6583 = eq(perr_ic_index_ff, UInt<6>("h03f")) @[ifu_mem_ctl.scala 694:102] - node _T_6584 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_6585 = and(_T_6583, _T_6584) @[ifu_mem_ctl.scala 694:124] - node _T_6586 = or(_T_6582, _T_6585) @[ifu_mem_ctl.scala 694:81] - node _T_6587 = or(_T_6586, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6588 = bits(_T_6587, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][62] <= _T_6574 @[ifu_mem_ctl.scala 692:41] + node _T_6575 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6576 = eq(_T_6575, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6577 = and(ic_valid_ff, _T_6576) @[ifu_mem_ctl.scala 692:97] + node _T_6578 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6579 = and(_T_6577, _T_6578) @[ifu_mem_ctl.scala 692:122] + node _T_6580 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[ifu_mem_ctl.scala 693:37] + node _T_6581 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_6582 = and(_T_6580, _T_6581) @[ifu_mem_ctl.scala 693:59] + node _T_6583 = eq(perr_ic_index_ff, UInt<6>("h03f")) @[ifu_mem_ctl.scala 693:102] + node _T_6584 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_6585 = and(_T_6583, _T_6584) @[ifu_mem_ctl.scala 693:124] + node _T_6586 = or(_T_6582, _T_6585) @[ifu_mem_ctl.scala 693:81] + node _T_6587 = or(_T_6586, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6588 = bits(_T_6587, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6589 : UInt<1>, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6588 : @[Reg.scala 28:19] _T_6589 <= _T_6579 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][63] <= _T_6589 @[ifu_mem_ctl.scala 693:41] - node _T_6590 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6591 = eq(_T_6590, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6592 = and(ic_valid_ff, _T_6591) @[ifu_mem_ctl.scala 693:97] - node _T_6593 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6594 = and(_T_6592, _T_6593) @[ifu_mem_ctl.scala 693:122] - node _T_6595 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[ifu_mem_ctl.scala 694:37] - node _T_6596 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_6597 = and(_T_6595, _T_6596) @[ifu_mem_ctl.scala 694:59] - node _T_6598 = eq(perr_ic_index_ff, UInt<6>("h020")) @[ifu_mem_ctl.scala 694:102] - node _T_6599 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6600 = and(_T_6598, _T_6599) @[ifu_mem_ctl.scala 694:124] - node _T_6601 = or(_T_6597, _T_6600) @[ifu_mem_ctl.scala 694:81] - node _T_6602 = or(_T_6601, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6603 = bits(_T_6602, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][63] <= _T_6589 @[ifu_mem_ctl.scala 692:41] + node _T_6590 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6591 = eq(_T_6590, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6592 = and(ic_valid_ff, _T_6591) @[ifu_mem_ctl.scala 692:97] + node _T_6593 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6594 = and(_T_6592, _T_6593) @[ifu_mem_ctl.scala 692:122] + node _T_6595 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[ifu_mem_ctl.scala 693:37] + node _T_6596 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_6597 = and(_T_6595, _T_6596) @[ifu_mem_ctl.scala 693:59] + node _T_6598 = eq(perr_ic_index_ff, UInt<6>("h020")) @[ifu_mem_ctl.scala 693:102] + node _T_6599 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6600 = and(_T_6598, _T_6599) @[ifu_mem_ctl.scala 693:124] + node _T_6601 = or(_T_6597, _T_6600) @[ifu_mem_ctl.scala 693:81] + node _T_6602 = or(_T_6601, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6603 = bits(_T_6602, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6604 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6603 : @[Reg.scala 28:19] _T_6604 <= _T_6594 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][32] <= _T_6604 @[ifu_mem_ctl.scala 693:41] - node _T_6605 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6606 = eq(_T_6605, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6607 = and(ic_valid_ff, _T_6606) @[ifu_mem_ctl.scala 693:97] - node _T_6608 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6609 = and(_T_6607, _T_6608) @[ifu_mem_ctl.scala 693:122] - node _T_6610 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[ifu_mem_ctl.scala 694:37] - node _T_6611 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_6612 = and(_T_6610, _T_6611) @[ifu_mem_ctl.scala 694:59] - node _T_6613 = eq(perr_ic_index_ff, UInt<6>("h021")) @[ifu_mem_ctl.scala 694:102] - node _T_6614 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6615 = and(_T_6613, _T_6614) @[ifu_mem_ctl.scala 694:124] - node _T_6616 = or(_T_6612, _T_6615) @[ifu_mem_ctl.scala 694:81] - node _T_6617 = or(_T_6616, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6618 = bits(_T_6617, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][32] <= _T_6604 @[ifu_mem_ctl.scala 692:41] + node _T_6605 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6606 = eq(_T_6605, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6607 = and(ic_valid_ff, _T_6606) @[ifu_mem_ctl.scala 692:97] + node _T_6608 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6609 = and(_T_6607, _T_6608) @[ifu_mem_ctl.scala 692:122] + node _T_6610 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[ifu_mem_ctl.scala 693:37] + node _T_6611 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_6612 = and(_T_6610, _T_6611) @[ifu_mem_ctl.scala 693:59] + node _T_6613 = eq(perr_ic_index_ff, UInt<6>("h021")) @[ifu_mem_ctl.scala 693:102] + node _T_6614 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6615 = and(_T_6613, _T_6614) @[ifu_mem_ctl.scala 693:124] + node _T_6616 = or(_T_6612, _T_6615) @[ifu_mem_ctl.scala 693:81] + node _T_6617 = or(_T_6616, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6618 = bits(_T_6617, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6619 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6618 : @[Reg.scala 28:19] _T_6619 <= _T_6609 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][33] <= _T_6619 @[ifu_mem_ctl.scala 693:41] - node _T_6620 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6621 = eq(_T_6620, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6622 = and(ic_valid_ff, _T_6621) @[ifu_mem_ctl.scala 693:97] - node _T_6623 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6624 = and(_T_6622, _T_6623) @[ifu_mem_ctl.scala 693:122] - node _T_6625 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[ifu_mem_ctl.scala 694:37] - node _T_6626 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_6627 = and(_T_6625, _T_6626) @[ifu_mem_ctl.scala 694:59] - node _T_6628 = eq(perr_ic_index_ff, UInt<6>("h022")) @[ifu_mem_ctl.scala 694:102] - node _T_6629 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6630 = and(_T_6628, _T_6629) @[ifu_mem_ctl.scala 694:124] - node _T_6631 = or(_T_6627, _T_6630) @[ifu_mem_ctl.scala 694:81] - node _T_6632 = or(_T_6631, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6633 = bits(_T_6632, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][33] <= _T_6619 @[ifu_mem_ctl.scala 692:41] + node _T_6620 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6621 = eq(_T_6620, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6622 = and(ic_valid_ff, _T_6621) @[ifu_mem_ctl.scala 692:97] + node _T_6623 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6624 = and(_T_6622, _T_6623) @[ifu_mem_ctl.scala 692:122] + node _T_6625 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[ifu_mem_ctl.scala 693:37] + node _T_6626 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_6627 = and(_T_6625, _T_6626) @[ifu_mem_ctl.scala 693:59] + node _T_6628 = eq(perr_ic_index_ff, UInt<6>("h022")) @[ifu_mem_ctl.scala 693:102] + node _T_6629 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6630 = and(_T_6628, _T_6629) @[ifu_mem_ctl.scala 693:124] + node _T_6631 = or(_T_6627, _T_6630) @[ifu_mem_ctl.scala 693:81] + node _T_6632 = or(_T_6631, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6633 = bits(_T_6632, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6634 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6633 : @[Reg.scala 28:19] _T_6634 <= _T_6624 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][34] <= _T_6634 @[ifu_mem_ctl.scala 693:41] - node _T_6635 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6636 = eq(_T_6635, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6637 = and(ic_valid_ff, _T_6636) @[ifu_mem_ctl.scala 693:97] - node _T_6638 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6639 = and(_T_6637, _T_6638) @[ifu_mem_ctl.scala 693:122] - node _T_6640 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[ifu_mem_ctl.scala 694:37] - node _T_6641 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_6642 = and(_T_6640, _T_6641) @[ifu_mem_ctl.scala 694:59] - node _T_6643 = eq(perr_ic_index_ff, UInt<6>("h023")) @[ifu_mem_ctl.scala 694:102] - node _T_6644 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6645 = and(_T_6643, _T_6644) @[ifu_mem_ctl.scala 694:124] - node _T_6646 = or(_T_6642, _T_6645) @[ifu_mem_ctl.scala 694:81] - node _T_6647 = or(_T_6646, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6648 = bits(_T_6647, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][34] <= _T_6634 @[ifu_mem_ctl.scala 692:41] + node _T_6635 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6636 = eq(_T_6635, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6637 = and(ic_valid_ff, _T_6636) @[ifu_mem_ctl.scala 692:97] + node _T_6638 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6639 = and(_T_6637, _T_6638) @[ifu_mem_ctl.scala 692:122] + node _T_6640 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[ifu_mem_ctl.scala 693:37] + node _T_6641 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_6642 = and(_T_6640, _T_6641) @[ifu_mem_ctl.scala 693:59] + node _T_6643 = eq(perr_ic_index_ff, UInt<6>("h023")) @[ifu_mem_ctl.scala 693:102] + node _T_6644 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6645 = and(_T_6643, _T_6644) @[ifu_mem_ctl.scala 693:124] + node _T_6646 = or(_T_6642, _T_6645) @[ifu_mem_ctl.scala 693:81] + node _T_6647 = or(_T_6646, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6648 = bits(_T_6647, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6649 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6648 : @[Reg.scala 28:19] _T_6649 <= _T_6639 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][35] <= _T_6649 @[ifu_mem_ctl.scala 693:41] - node _T_6650 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6651 = eq(_T_6650, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6652 = and(ic_valid_ff, _T_6651) @[ifu_mem_ctl.scala 693:97] - node _T_6653 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6654 = and(_T_6652, _T_6653) @[ifu_mem_ctl.scala 693:122] - node _T_6655 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[ifu_mem_ctl.scala 694:37] - node _T_6656 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_6657 = and(_T_6655, _T_6656) @[ifu_mem_ctl.scala 694:59] - node _T_6658 = eq(perr_ic_index_ff, UInt<6>("h024")) @[ifu_mem_ctl.scala 694:102] - node _T_6659 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6660 = and(_T_6658, _T_6659) @[ifu_mem_ctl.scala 694:124] - node _T_6661 = or(_T_6657, _T_6660) @[ifu_mem_ctl.scala 694:81] - node _T_6662 = or(_T_6661, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6663 = bits(_T_6662, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][35] <= _T_6649 @[ifu_mem_ctl.scala 692:41] + node _T_6650 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6651 = eq(_T_6650, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6652 = and(ic_valid_ff, _T_6651) @[ifu_mem_ctl.scala 692:97] + node _T_6653 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6654 = and(_T_6652, _T_6653) @[ifu_mem_ctl.scala 692:122] + node _T_6655 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[ifu_mem_ctl.scala 693:37] + node _T_6656 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_6657 = and(_T_6655, _T_6656) @[ifu_mem_ctl.scala 693:59] + node _T_6658 = eq(perr_ic_index_ff, UInt<6>("h024")) @[ifu_mem_ctl.scala 693:102] + node _T_6659 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6660 = and(_T_6658, _T_6659) @[ifu_mem_ctl.scala 693:124] + node _T_6661 = or(_T_6657, _T_6660) @[ifu_mem_ctl.scala 693:81] + node _T_6662 = or(_T_6661, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6663 = bits(_T_6662, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6664 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6663 : @[Reg.scala 28:19] _T_6664 <= _T_6654 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][36] <= _T_6664 @[ifu_mem_ctl.scala 693:41] - node _T_6665 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6666 = eq(_T_6665, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6667 = and(ic_valid_ff, _T_6666) @[ifu_mem_ctl.scala 693:97] - node _T_6668 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6669 = and(_T_6667, _T_6668) @[ifu_mem_ctl.scala 693:122] - node _T_6670 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[ifu_mem_ctl.scala 694:37] - node _T_6671 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_6672 = and(_T_6670, _T_6671) @[ifu_mem_ctl.scala 694:59] - node _T_6673 = eq(perr_ic_index_ff, UInt<6>("h025")) @[ifu_mem_ctl.scala 694:102] - node _T_6674 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6675 = and(_T_6673, _T_6674) @[ifu_mem_ctl.scala 694:124] - node _T_6676 = or(_T_6672, _T_6675) @[ifu_mem_ctl.scala 694:81] - node _T_6677 = or(_T_6676, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6678 = bits(_T_6677, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][36] <= _T_6664 @[ifu_mem_ctl.scala 692:41] + node _T_6665 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6666 = eq(_T_6665, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6667 = and(ic_valid_ff, _T_6666) @[ifu_mem_ctl.scala 692:97] + node _T_6668 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6669 = and(_T_6667, _T_6668) @[ifu_mem_ctl.scala 692:122] + node _T_6670 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[ifu_mem_ctl.scala 693:37] + node _T_6671 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_6672 = and(_T_6670, _T_6671) @[ifu_mem_ctl.scala 693:59] + node _T_6673 = eq(perr_ic_index_ff, UInt<6>("h025")) @[ifu_mem_ctl.scala 693:102] + node _T_6674 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6675 = and(_T_6673, _T_6674) @[ifu_mem_ctl.scala 693:124] + node _T_6676 = or(_T_6672, _T_6675) @[ifu_mem_ctl.scala 693:81] + node _T_6677 = or(_T_6676, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6678 = bits(_T_6677, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6679 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6678 : @[Reg.scala 28:19] _T_6679 <= _T_6669 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][37] <= _T_6679 @[ifu_mem_ctl.scala 693:41] - node _T_6680 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6681 = eq(_T_6680, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6682 = and(ic_valid_ff, _T_6681) @[ifu_mem_ctl.scala 693:97] - node _T_6683 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6684 = and(_T_6682, _T_6683) @[ifu_mem_ctl.scala 693:122] - node _T_6685 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[ifu_mem_ctl.scala 694:37] - node _T_6686 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_6687 = and(_T_6685, _T_6686) @[ifu_mem_ctl.scala 694:59] - node _T_6688 = eq(perr_ic_index_ff, UInt<6>("h026")) @[ifu_mem_ctl.scala 694:102] - node _T_6689 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6690 = and(_T_6688, _T_6689) @[ifu_mem_ctl.scala 694:124] - node _T_6691 = or(_T_6687, _T_6690) @[ifu_mem_ctl.scala 694:81] - node _T_6692 = or(_T_6691, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6693 = bits(_T_6692, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][37] <= _T_6679 @[ifu_mem_ctl.scala 692:41] + node _T_6680 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6681 = eq(_T_6680, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6682 = and(ic_valid_ff, _T_6681) @[ifu_mem_ctl.scala 692:97] + node _T_6683 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6684 = and(_T_6682, _T_6683) @[ifu_mem_ctl.scala 692:122] + node _T_6685 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[ifu_mem_ctl.scala 693:37] + node _T_6686 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_6687 = and(_T_6685, _T_6686) @[ifu_mem_ctl.scala 693:59] + node _T_6688 = eq(perr_ic_index_ff, UInt<6>("h026")) @[ifu_mem_ctl.scala 693:102] + node _T_6689 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6690 = and(_T_6688, _T_6689) @[ifu_mem_ctl.scala 693:124] + node _T_6691 = or(_T_6687, _T_6690) @[ifu_mem_ctl.scala 693:81] + node _T_6692 = or(_T_6691, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6693 = bits(_T_6692, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6694 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6693 : @[Reg.scala 28:19] _T_6694 <= _T_6684 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][38] <= _T_6694 @[ifu_mem_ctl.scala 693:41] - node _T_6695 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6696 = eq(_T_6695, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6697 = and(ic_valid_ff, _T_6696) @[ifu_mem_ctl.scala 693:97] - node _T_6698 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6699 = and(_T_6697, _T_6698) @[ifu_mem_ctl.scala 693:122] - node _T_6700 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[ifu_mem_ctl.scala 694:37] - node _T_6701 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_6702 = and(_T_6700, _T_6701) @[ifu_mem_ctl.scala 694:59] - node _T_6703 = eq(perr_ic_index_ff, UInt<6>("h027")) @[ifu_mem_ctl.scala 694:102] - node _T_6704 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6705 = and(_T_6703, _T_6704) @[ifu_mem_ctl.scala 694:124] - node _T_6706 = or(_T_6702, _T_6705) @[ifu_mem_ctl.scala 694:81] - node _T_6707 = or(_T_6706, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6708 = bits(_T_6707, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][38] <= _T_6694 @[ifu_mem_ctl.scala 692:41] + node _T_6695 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6696 = eq(_T_6695, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6697 = and(ic_valid_ff, _T_6696) @[ifu_mem_ctl.scala 692:97] + node _T_6698 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6699 = and(_T_6697, _T_6698) @[ifu_mem_ctl.scala 692:122] + node _T_6700 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[ifu_mem_ctl.scala 693:37] + node _T_6701 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_6702 = and(_T_6700, _T_6701) @[ifu_mem_ctl.scala 693:59] + node _T_6703 = eq(perr_ic_index_ff, UInt<6>("h027")) @[ifu_mem_ctl.scala 693:102] + node _T_6704 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6705 = and(_T_6703, _T_6704) @[ifu_mem_ctl.scala 693:124] + node _T_6706 = or(_T_6702, _T_6705) @[ifu_mem_ctl.scala 693:81] + node _T_6707 = or(_T_6706, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6708 = bits(_T_6707, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6709 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6708 : @[Reg.scala 28:19] _T_6709 <= _T_6699 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][39] <= _T_6709 @[ifu_mem_ctl.scala 693:41] - node _T_6710 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6711 = eq(_T_6710, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6712 = and(ic_valid_ff, _T_6711) @[ifu_mem_ctl.scala 693:97] - node _T_6713 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6714 = and(_T_6712, _T_6713) @[ifu_mem_ctl.scala 693:122] - node _T_6715 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[ifu_mem_ctl.scala 694:37] - node _T_6716 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_6717 = and(_T_6715, _T_6716) @[ifu_mem_ctl.scala 694:59] - node _T_6718 = eq(perr_ic_index_ff, UInt<6>("h028")) @[ifu_mem_ctl.scala 694:102] - node _T_6719 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6720 = and(_T_6718, _T_6719) @[ifu_mem_ctl.scala 694:124] - node _T_6721 = or(_T_6717, _T_6720) @[ifu_mem_ctl.scala 694:81] - node _T_6722 = or(_T_6721, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6723 = bits(_T_6722, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][39] <= _T_6709 @[ifu_mem_ctl.scala 692:41] + node _T_6710 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6711 = eq(_T_6710, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6712 = and(ic_valid_ff, _T_6711) @[ifu_mem_ctl.scala 692:97] + node _T_6713 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6714 = and(_T_6712, _T_6713) @[ifu_mem_ctl.scala 692:122] + node _T_6715 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[ifu_mem_ctl.scala 693:37] + node _T_6716 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_6717 = and(_T_6715, _T_6716) @[ifu_mem_ctl.scala 693:59] + node _T_6718 = eq(perr_ic_index_ff, UInt<6>("h028")) @[ifu_mem_ctl.scala 693:102] + node _T_6719 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6720 = and(_T_6718, _T_6719) @[ifu_mem_ctl.scala 693:124] + node _T_6721 = or(_T_6717, _T_6720) @[ifu_mem_ctl.scala 693:81] + node _T_6722 = or(_T_6721, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6723 = bits(_T_6722, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6724 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6723 : @[Reg.scala 28:19] _T_6724 <= _T_6714 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][40] <= _T_6724 @[ifu_mem_ctl.scala 693:41] - node _T_6725 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6726 = eq(_T_6725, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6727 = and(ic_valid_ff, _T_6726) @[ifu_mem_ctl.scala 693:97] - node _T_6728 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6729 = and(_T_6727, _T_6728) @[ifu_mem_ctl.scala 693:122] - node _T_6730 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[ifu_mem_ctl.scala 694:37] - node _T_6731 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_6732 = and(_T_6730, _T_6731) @[ifu_mem_ctl.scala 694:59] - node _T_6733 = eq(perr_ic_index_ff, UInt<6>("h029")) @[ifu_mem_ctl.scala 694:102] - node _T_6734 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6735 = and(_T_6733, _T_6734) @[ifu_mem_ctl.scala 694:124] - node _T_6736 = or(_T_6732, _T_6735) @[ifu_mem_ctl.scala 694:81] - node _T_6737 = or(_T_6736, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6738 = bits(_T_6737, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][40] <= _T_6724 @[ifu_mem_ctl.scala 692:41] + node _T_6725 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6726 = eq(_T_6725, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6727 = and(ic_valid_ff, _T_6726) @[ifu_mem_ctl.scala 692:97] + node _T_6728 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6729 = and(_T_6727, _T_6728) @[ifu_mem_ctl.scala 692:122] + node _T_6730 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[ifu_mem_ctl.scala 693:37] + node _T_6731 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_6732 = and(_T_6730, _T_6731) @[ifu_mem_ctl.scala 693:59] + node _T_6733 = eq(perr_ic_index_ff, UInt<6>("h029")) @[ifu_mem_ctl.scala 693:102] + node _T_6734 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6735 = and(_T_6733, _T_6734) @[ifu_mem_ctl.scala 693:124] + node _T_6736 = or(_T_6732, _T_6735) @[ifu_mem_ctl.scala 693:81] + node _T_6737 = or(_T_6736, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6738 = bits(_T_6737, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6739 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6738 : @[Reg.scala 28:19] _T_6739 <= _T_6729 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][41] <= _T_6739 @[ifu_mem_ctl.scala 693:41] - node _T_6740 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6741 = eq(_T_6740, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6742 = and(ic_valid_ff, _T_6741) @[ifu_mem_ctl.scala 693:97] - node _T_6743 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6744 = and(_T_6742, _T_6743) @[ifu_mem_ctl.scala 693:122] - node _T_6745 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[ifu_mem_ctl.scala 694:37] - node _T_6746 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_6747 = and(_T_6745, _T_6746) @[ifu_mem_ctl.scala 694:59] - node _T_6748 = eq(perr_ic_index_ff, UInt<6>("h02a")) @[ifu_mem_ctl.scala 694:102] - node _T_6749 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6750 = and(_T_6748, _T_6749) @[ifu_mem_ctl.scala 694:124] - node _T_6751 = or(_T_6747, _T_6750) @[ifu_mem_ctl.scala 694:81] - node _T_6752 = or(_T_6751, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6753 = bits(_T_6752, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][41] <= _T_6739 @[ifu_mem_ctl.scala 692:41] + node _T_6740 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6741 = eq(_T_6740, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6742 = and(ic_valid_ff, _T_6741) @[ifu_mem_ctl.scala 692:97] + node _T_6743 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6744 = and(_T_6742, _T_6743) @[ifu_mem_ctl.scala 692:122] + node _T_6745 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[ifu_mem_ctl.scala 693:37] + node _T_6746 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_6747 = and(_T_6745, _T_6746) @[ifu_mem_ctl.scala 693:59] + node _T_6748 = eq(perr_ic_index_ff, UInt<6>("h02a")) @[ifu_mem_ctl.scala 693:102] + node _T_6749 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6750 = and(_T_6748, _T_6749) @[ifu_mem_ctl.scala 693:124] + node _T_6751 = or(_T_6747, _T_6750) @[ifu_mem_ctl.scala 693:81] + node _T_6752 = or(_T_6751, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6753 = bits(_T_6752, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6754 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6753 : @[Reg.scala 28:19] _T_6754 <= _T_6744 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][42] <= _T_6754 @[ifu_mem_ctl.scala 693:41] - node _T_6755 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6756 = eq(_T_6755, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6757 = and(ic_valid_ff, _T_6756) @[ifu_mem_ctl.scala 693:97] - node _T_6758 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6759 = and(_T_6757, _T_6758) @[ifu_mem_ctl.scala 693:122] - node _T_6760 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[ifu_mem_ctl.scala 694:37] - node _T_6761 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_6762 = and(_T_6760, _T_6761) @[ifu_mem_ctl.scala 694:59] - node _T_6763 = eq(perr_ic_index_ff, UInt<6>("h02b")) @[ifu_mem_ctl.scala 694:102] - node _T_6764 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6765 = and(_T_6763, _T_6764) @[ifu_mem_ctl.scala 694:124] - node _T_6766 = or(_T_6762, _T_6765) @[ifu_mem_ctl.scala 694:81] - node _T_6767 = or(_T_6766, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6768 = bits(_T_6767, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][42] <= _T_6754 @[ifu_mem_ctl.scala 692:41] + node _T_6755 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6756 = eq(_T_6755, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6757 = and(ic_valid_ff, _T_6756) @[ifu_mem_ctl.scala 692:97] + node _T_6758 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6759 = and(_T_6757, _T_6758) @[ifu_mem_ctl.scala 692:122] + node _T_6760 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[ifu_mem_ctl.scala 693:37] + node _T_6761 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_6762 = and(_T_6760, _T_6761) @[ifu_mem_ctl.scala 693:59] + node _T_6763 = eq(perr_ic_index_ff, UInt<6>("h02b")) @[ifu_mem_ctl.scala 693:102] + node _T_6764 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6765 = and(_T_6763, _T_6764) @[ifu_mem_ctl.scala 693:124] + node _T_6766 = or(_T_6762, _T_6765) @[ifu_mem_ctl.scala 693:81] + node _T_6767 = or(_T_6766, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6768 = bits(_T_6767, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6769 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6768 : @[Reg.scala 28:19] _T_6769 <= _T_6759 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][43] <= _T_6769 @[ifu_mem_ctl.scala 693:41] - node _T_6770 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6771 = eq(_T_6770, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6772 = and(ic_valid_ff, _T_6771) @[ifu_mem_ctl.scala 693:97] - node _T_6773 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6774 = and(_T_6772, _T_6773) @[ifu_mem_ctl.scala 693:122] - node _T_6775 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[ifu_mem_ctl.scala 694:37] - node _T_6776 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_6777 = and(_T_6775, _T_6776) @[ifu_mem_ctl.scala 694:59] - node _T_6778 = eq(perr_ic_index_ff, UInt<6>("h02c")) @[ifu_mem_ctl.scala 694:102] - node _T_6779 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6780 = and(_T_6778, _T_6779) @[ifu_mem_ctl.scala 694:124] - node _T_6781 = or(_T_6777, _T_6780) @[ifu_mem_ctl.scala 694:81] - node _T_6782 = or(_T_6781, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6783 = bits(_T_6782, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][43] <= _T_6769 @[ifu_mem_ctl.scala 692:41] + node _T_6770 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6771 = eq(_T_6770, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6772 = and(ic_valid_ff, _T_6771) @[ifu_mem_ctl.scala 692:97] + node _T_6773 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6774 = and(_T_6772, _T_6773) @[ifu_mem_ctl.scala 692:122] + node _T_6775 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[ifu_mem_ctl.scala 693:37] + node _T_6776 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_6777 = and(_T_6775, _T_6776) @[ifu_mem_ctl.scala 693:59] + node _T_6778 = eq(perr_ic_index_ff, UInt<6>("h02c")) @[ifu_mem_ctl.scala 693:102] + node _T_6779 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6780 = and(_T_6778, _T_6779) @[ifu_mem_ctl.scala 693:124] + node _T_6781 = or(_T_6777, _T_6780) @[ifu_mem_ctl.scala 693:81] + node _T_6782 = or(_T_6781, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6783 = bits(_T_6782, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6784 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6783 : @[Reg.scala 28:19] _T_6784 <= _T_6774 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][44] <= _T_6784 @[ifu_mem_ctl.scala 693:41] - node _T_6785 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6786 = eq(_T_6785, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6787 = and(ic_valid_ff, _T_6786) @[ifu_mem_ctl.scala 693:97] - node _T_6788 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6789 = and(_T_6787, _T_6788) @[ifu_mem_ctl.scala 693:122] - node _T_6790 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[ifu_mem_ctl.scala 694:37] - node _T_6791 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_6792 = and(_T_6790, _T_6791) @[ifu_mem_ctl.scala 694:59] - node _T_6793 = eq(perr_ic_index_ff, UInt<6>("h02d")) @[ifu_mem_ctl.scala 694:102] - node _T_6794 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6795 = and(_T_6793, _T_6794) @[ifu_mem_ctl.scala 694:124] - node _T_6796 = or(_T_6792, _T_6795) @[ifu_mem_ctl.scala 694:81] - node _T_6797 = or(_T_6796, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6798 = bits(_T_6797, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][44] <= _T_6784 @[ifu_mem_ctl.scala 692:41] + node _T_6785 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6786 = eq(_T_6785, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6787 = and(ic_valid_ff, _T_6786) @[ifu_mem_ctl.scala 692:97] + node _T_6788 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6789 = and(_T_6787, _T_6788) @[ifu_mem_ctl.scala 692:122] + node _T_6790 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[ifu_mem_ctl.scala 693:37] + node _T_6791 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_6792 = and(_T_6790, _T_6791) @[ifu_mem_ctl.scala 693:59] + node _T_6793 = eq(perr_ic_index_ff, UInt<6>("h02d")) @[ifu_mem_ctl.scala 693:102] + node _T_6794 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6795 = and(_T_6793, _T_6794) @[ifu_mem_ctl.scala 693:124] + node _T_6796 = or(_T_6792, _T_6795) @[ifu_mem_ctl.scala 693:81] + node _T_6797 = or(_T_6796, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6798 = bits(_T_6797, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6799 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6798 : @[Reg.scala 28:19] _T_6799 <= _T_6789 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][45] <= _T_6799 @[ifu_mem_ctl.scala 693:41] - node _T_6800 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6801 = eq(_T_6800, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6802 = and(ic_valid_ff, _T_6801) @[ifu_mem_ctl.scala 693:97] - node _T_6803 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6804 = and(_T_6802, _T_6803) @[ifu_mem_ctl.scala 693:122] - node _T_6805 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[ifu_mem_ctl.scala 694:37] - node _T_6806 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_6807 = and(_T_6805, _T_6806) @[ifu_mem_ctl.scala 694:59] - node _T_6808 = eq(perr_ic_index_ff, UInt<6>("h02e")) @[ifu_mem_ctl.scala 694:102] - node _T_6809 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6810 = and(_T_6808, _T_6809) @[ifu_mem_ctl.scala 694:124] - node _T_6811 = or(_T_6807, _T_6810) @[ifu_mem_ctl.scala 694:81] - node _T_6812 = or(_T_6811, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6813 = bits(_T_6812, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][45] <= _T_6799 @[ifu_mem_ctl.scala 692:41] + node _T_6800 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6801 = eq(_T_6800, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6802 = and(ic_valid_ff, _T_6801) @[ifu_mem_ctl.scala 692:97] + node _T_6803 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6804 = and(_T_6802, _T_6803) @[ifu_mem_ctl.scala 692:122] + node _T_6805 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[ifu_mem_ctl.scala 693:37] + node _T_6806 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_6807 = and(_T_6805, _T_6806) @[ifu_mem_ctl.scala 693:59] + node _T_6808 = eq(perr_ic_index_ff, UInt<6>("h02e")) @[ifu_mem_ctl.scala 693:102] + node _T_6809 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6810 = and(_T_6808, _T_6809) @[ifu_mem_ctl.scala 693:124] + node _T_6811 = or(_T_6807, _T_6810) @[ifu_mem_ctl.scala 693:81] + node _T_6812 = or(_T_6811, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6813 = bits(_T_6812, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6814 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6813 : @[Reg.scala 28:19] _T_6814 <= _T_6804 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][46] <= _T_6814 @[ifu_mem_ctl.scala 693:41] - node _T_6815 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6816 = eq(_T_6815, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6817 = and(ic_valid_ff, _T_6816) @[ifu_mem_ctl.scala 693:97] - node _T_6818 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6819 = and(_T_6817, _T_6818) @[ifu_mem_ctl.scala 693:122] - node _T_6820 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[ifu_mem_ctl.scala 694:37] - node _T_6821 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_6822 = and(_T_6820, _T_6821) @[ifu_mem_ctl.scala 694:59] - node _T_6823 = eq(perr_ic_index_ff, UInt<6>("h02f")) @[ifu_mem_ctl.scala 694:102] - node _T_6824 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6825 = and(_T_6823, _T_6824) @[ifu_mem_ctl.scala 694:124] - node _T_6826 = or(_T_6822, _T_6825) @[ifu_mem_ctl.scala 694:81] - node _T_6827 = or(_T_6826, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6828 = bits(_T_6827, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][46] <= _T_6814 @[ifu_mem_ctl.scala 692:41] + node _T_6815 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6816 = eq(_T_6815, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6817 = and(ic_valid_ff, _T_6816) @[ifu_mem_ctl.scala 692:97] + node _T_6818 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6819 = and(_T_6817, _T_6818) @[ifu_mem_ctl.scala 692:122] + node _T_6820 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[ifu_mem_ctl.scala 693:37] + node _T_6821 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_6822 = and(_T_6820, _T_6821) @[ifu_mem_ctl.scala 693:59] + node _T_6823 = eq(perr_ic_index_ff, UInt<6>("h02f")) @[ifu_mem_ctl.scala 693:102] + node _T_6824 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6825 = and(_T_6823, _T_6824) @[ifu_mem_ctl.scala 693:124] + node _T_6826 = or(_T_6822, _T_6825) @[ifu_mem_ctl.scala 693:81] + node _T_6827 = or(_T_6826, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6828 = bits(_T_6827, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6829 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6828 : @[Reg.scala 28:19] _T_6829 <= _T_6819 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][47] <= _T_6829 @[ifu_mem_ctl.scala 693:41] - node _T_6830 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6831 = eq(_T_6830, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6832 = and(ic_valid_ff, _T_6831) @[ifu_mem_ctl.scala 693:97] - node _T_6833 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6834 = and(_T_6832, _T_6833) @[ifu_mem_ctl.scala 693:122] - node _T_6835 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[ifu_mem_ctl.scala 694:37] - node _T_6836 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_6837 = and(_T_6835, _T_6836) @[ifu_mem_ctl.scala 694:59] - node _T_6838 = eq(perr_ic_index_ff, UInt<6>("h030")) @[ifu_mem_ctl.scala 694:102] - node _T_6839 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6840 = and(_T_6838, _T_6839) @[ifu_mem_ctl.scala 694:124] - node _T_6841 = or(_T_6837, _T_6840) @[ifu_mem_ctl.scala 694:81] - node _T_6842 = or(_T_6841, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6843 = bits(_T_6842, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][47] <= _T_6829 @[ifu_mem_ctl.scala 692:41] + node _T_6830 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6831 = eq(_T_6830, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6832 = and(ic_valid_ff, _T_6831) @[ifu_mem_ctl.scala 692:97] + node _T_6833 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6834 = and(_T_6832, _T_6833) @[ifu_mem_ctl.scala 692:122] + node _T_6835 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[ifu_mem_ctl.scala 693:37] + node _T_6836 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_6837 = and(_T_6835, _T_6836) @[ifu_mem_ctl.scala 693:59] + node _T_6838 = eq(perr_ic_index_ff, UInt<6>("h030")) @[ifu_mem_ctl.scala 693:102] + node _T_6839 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6840 = and(_T_6838, _T_6839) @[ifu_mem_ctl.scala 693:124] + node _T_6841 = or(_T_6837, _T_6840) @[ifu_mem_ctl.scala 693:81] + node _T_6842 = or(_T_6841, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6843 = bits(_T_6842, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6844 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6843 : @[Reg.scala 28:19] _T_6844 <= _T_6834 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][48] <= _T_6844 @[ifu_mem_ctl.scala 693:41] - node _T_6845 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6846 = eq(_T_6845, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6847 = and(ic_valid_ff, _T_6846) @[ifu_mem_ctl.scala 693:97] - node _T_6848 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6849 = and(_T_6847, _T_6848) @[ifu_mem_ctl.scala 693:122] - node _T_6850 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[ifu_mem_ctl.scala 694:37] - node _T_6851 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_6852 = and(_T_6850, _T_6851) @[ifu_mem_ctl.scala 694:59] - node _T_6853 = eq(perr_ic_index_ff, UInt<6>("h031")) @[ifu_mem_ctl.scala 694:102] - node _T_6854 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6855 = and(_T_6853, _T_6854) @[ifu_mem_ctl.scala 694:124] - node _T_6856 = or(_T_6852, _T_6855) @[ifu_mem_ctl.scala 694:81] - node _T_6857 = or(_T_6856, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6858 = bits(_T_6857, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][48] <= _T_6844 @[ifu_mem_ctl.scala 692:41] + node _T_6845 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6846 = eq(_T_6845, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6847 = and(ic_valid_ff, _T_6846) @[ifu_mem_ctl.scala 692:97] + node _T_6848 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6849 = and(_T_6847, _T_6848) @[ifu_mem_ctl.scala 692:122] + node _T_6850 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[ifu_mem_ctl.scala 693:37] + node _T_6851 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_6852 = and(_T_6850, _T_6851) @[ifu_mem_ctl.scala 693:59] + node _T_6853 = eq(perr_ic_index_ff, UInt<6>("h031")) @[ifu_mem_ctl.scala 693:102] + node _T_6854 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6855 = and(_T_6853, _T_6854) @[ifu_mem_ctl.scala 693:124] + node _T_6856 = or(_T_6852, _T_6855) @[ifu_mem_ctl.scala 693:81] + node _T_6857 = or(_T_6856, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6858 = bits(_T_6857, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6859 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6858 : @[Reg.scala 28:19] _T_6859 <= _T_6849 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][49] <= _T_6859 @[ifu_mem_ctl.scala 693:41] - node _T_6860 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6861 = eq(_T_6860, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6862 = and(ic_valid_ff, _T_6861) @[ifu_mem_ctl.scala 693:97] - node _T_6863 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6864 = and(_T_6862, _T_6863) @[ifu_mem_ctl.scala 693:122] - node _T_6865 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[ifu_mem_ctl.scala 694:37] - node _T_6866 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_6867 = and(_T_6865, _T_6866) @[ifu_mem_ctl.scala 694:59] - node _T_6868 = eq(perr_ic_index_ff, UInt<6>("h032")) @[ifu_mem_ctl.scala 694:102] - node _T_6869 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6870 = and(_T_6868, _T_6869) @[ifu_mem_ctl.scala 694:124] - node _T_6871 = or(_T_6867, _T_6870) @[ifu_mem_ctl.scala 694:81] - node _T_6872 = or(_T_6871, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6873 = bits(_T_6872, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][49] <= _T_6859 @[ifu_mem_ctl.scala 692:41] + node _T_6860 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6861 = eq(_T_6860, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6862 = and(ic_valid_ff, _T_6861) @[ifu_mem_ctl.scala 692:97] + node _T_6863 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6864 = and(_T_6862, _T_6863) @[ifu_mem_ctl.scala 692:122] + node _T_6865 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[ifu_mem_ctl.scala 693:37] + node _T_6866 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_6867 = and(_T_6865, _T_6866) @[ifu_mem_ctl.scala 693:59] + node _T_6868 = eq(perr_ic_index_ff, UInt<6>("h032")) @[ifu_mem_ctl.scala 693:102] + node _T_6869 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6870 = and(_T_6868, _T_6869) @[ifu_mem_ctl.scala 693:124] + node _T_6871 = or(_T_6867, _T_6870) @[ifu_mem_ctl.scala 693:81] + node _T_6872 = or(_T_6871, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6873 = bits(_T_6872, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6874 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6873 : @[Reg.scala 28:19] _T_6874 <= _T_6864 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][50] <= _T_6874 @[ifu_mem_ctl.scala 693:41] - node _T_6875 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6876 = eq(_T_6875, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6877 = and(ic_valid_ff, _T_6876) @[ifu_mem_ctl.scala 693:97] - node _T_6878 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6879 = and(_T_6877, _T_6878) @[ifu_mem_ctl.scala 693:122] - node _T_6880 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[ifu_mem_ctl.scala 694:37] - node _T_6881 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_6882 = and(_T_6880, _T_6881) @[ifu_mem_ctl.scala 694:59] - node _T_6883 = eq(perr_ic_index_ff, UInt<6>("h033")) @[ifu_mem_ctl.scala 694:102] - node _T_6884 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6885 = and(_T_6883, _T_6884) @[ifu_mem_ctl.scala 694:124] - node _T_6886 = or(_T_6882, _T_6885) @[ifu_mem_ctl.scala 694:81] - node _T_6887 = or(_T_6886, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6888 = bits(_T_6887, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][50] <= _T_6874 @[ifu_mem_ctl.scala 692:41] + node _T_6875 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6876 = eq(_T_6875, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6877 = and(ic_valid_ff, _T_6876) @[ifu_mem_ctl.scala 692:97] + node _T_6878 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6879 = and(_T_6877, _T_6878) @[ifu_mem_ctl.scala 692:122] + node _T_6880 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[ifu_mem_ctl.scala 693:37] + node _T_6881 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_6882 = and(_T_6880, _T_6881) @[ifu_mem_ctl.scala 693:59] + node _T_6883 = eq(perr_ic_index_ff, UInt<6>("h033")) @[ifu_mem_ctl.scala 693:102] + node _T_6884 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6885 = and(_T_6883, _T_6884) @[ifu_mem_ctl.scala 693:124] + node _T_6886 = or(_T_6882, _T_6885) @[ifu_mem_ctl.scala 693:81] + node _T_6887 = or(_T_6886, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6888 = bits(_T_6887, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6889 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6888 : @[Reg.scala 28:19] _T_6889 <= _T_6879 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][51] <= _T_6889 @[ifu_mem_ctl.scala 693:41] - node _T_6890 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6891 = eq(_T_6890, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6892 = and(ic_valid_ff, _T_6891) @[ifu_mem_ctl.scala 693:97] - node _T_6893 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6894 = and(_T_6892, _T_6893) @[ifu_mem_ctl.scala 693:122] - node _T_6895 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[ifu_mem_ctl.scala 694:37] - node _T_6896 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_6897 = and(_T_6895, _T_6896) @[ifu_mem_ctl.scala 694:59] - node _T_6898 = eq(perr_ic_index_ff, UInt<6>("h034")) @[ifu_mem_ctl.scala 694:102] - node _T_6899 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6900 = and(_T_6898, _T_6899) @[ifu_mem_ctl.scala 694:124] - node _T_6901 = or(_T_6897, _T_6900) @[ifu_mem_ctl.scala 694:81] - node _T_6902 = or(_T_6901, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6903 = bits(_T_6902, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][51] <= _T_6889 @[ifu_mem_ctl.scala 692:41] + node _T_6890 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6891 = eq(_T_6890, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6892 = and(ic_valid_ff, _T_6891) @[ifu_mem_ctl.scala 692:97] + node _T_6893 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6894 = and(_T_6892, _T_6893) @[ifu_mem_ctl.scala 692:122] + node _T_6895 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[ifu_mem_ctl.scala 693:37] + node _T_6896 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_6897 = and(_T_6895, _T_6896) @[ifu_mem_ctl.scala 693:59] + node _T_6898 = eq(perr_ic_index_ff, UInt<6>("h034")) @[ifu_mem_ctl.scala 693:102] + node _T_6899 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6900 = and(_T_6898, _T_6899) @[ifu_mem_ctl.scala 693:124] + node _T_6901 = or(_T_6897, _T_6900) @[ifu_mem_ctl.scala 693:81] + node _T_6902 = or(_T_6901, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6903 = bits(_T_6902, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6904 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6903 : @[Reg.scala 28:19] _T_6904 <= _T_6894 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][52] <= _T_6904 @[ifu_mem_ctl.scala 693:41] - node _T_6905 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6906 = eq(_T_6905, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6907 = and(ic_valid_ff, _T_6906) @[ifu_mem_ctl.scala 693:97] - node _T_6908 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6909 = and(_T_6907, _T_6908) @[ifu_mem_ctl.scala 693:122] - node _T_6910 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[ifu_mem_ctl.scala 694:37] - node _T_6911 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_6912 = and(_T_6910, _T_6911) @[ifu_mem_ctl.scala 694:59] - node _T_6913 = eq(perr_ic_index_ff, UInt<6>("h035")) @[ifu_mem_ctl.scala 694:102] - node _T_6914 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6915 = and(_T_6913, _T_6914) @[ifu_mem_ctl.scala 694:124] - node _T_6916 = or(_T_6912, _T_6915) @[ifu_mem_ctl.scala 694:81] - node _T_6917 = or(_T_6916, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6918 = bits(_T_6917, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][52] <= _T_6904 @[ifu_mem_ctl.scala 692:41] + node _T_6905 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6906 = eq(_T_6905, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6907 = and(ic_valid_ff, _T_6906) @[ifu_mem_ctl.scala 692:97] + node _T_6908 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6909 = and(_T_6907, _T_6908) @[ifu_mem_ctl.scala 692:122] + node _T_6910 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[ifu_mem_ctl.scala 693:37] + node _T_6911 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_6912 = and(_T_6910, _T_6911) @[ifu_mem_ctl.scala 693:59] + node _T_6913 = eq(perr_ic_index_ff, UInt<6>("h035")) @[ifu_mem_ctl.scala 693:102] + node _T_6914 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6915 = and(_T_6913, _T_6914) @[ifu_mem_ctl.scala 693:124] + node _T_6916 = or(_T_6912, _T_6915) @[ifu_mem_ctl.scala 693:81] + node _T_6917 = or(_T_6916, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6918 = bits(_T_6917, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6919 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6918 : @[Reg.scala 28:19] _T_6919 <= _T_6909 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][53] <= _T_6919 @[ifu_mem_ctl.scala 693:41] - node _T_6920 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6921 = eq(_T_6920, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6922 = and(ic_valid_ff, _T_6921) @[ifu_mem_ctl.scala 693:97] - node _T_6923 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6924 = and(_T_6922, _T_6923) @[ifu_mem_ctl.scala 693:122] - node _T_6925 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[ifu_mem_ctl.scala 694:37] - node _T_6926 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_6927 = and(_T_6925, _T_6926) @[ifu_mem_ctl.scala 694:59] - node _T_6928 = eq(perr_ic_index_ff, UInt<6>("h036")) @[ifu_mem_ctl.scala 694:102] - node _T_6929 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6930 = and(_T_6928, _T_6929) @[ifu_mem_ctl.scala 694:124] - node _T_6931 = or(_T_6927, _T_6930) @[ifu_mem_ctl.scala 694:81] - node _T_6932 = or(_T_6931, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6933 = bits(_T_6932, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][53] <= _T_6919 @[ifu_mem_ctl.scala 692:41] + node _T_6920 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6921 = eq(_T_6920, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6922 = and(ic_valid_ff, _T_6921) @[ifu_mem_ctl.scala 692:97] + node _T_6923 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6924 = and(_T_6922, _T_6923) @[ifu_mem_ctl.scala 692:122] + node _T_6925 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[ifu_mem_ctl.scala 693:37] + node _T_6926 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_6927 = and(_T_6925, _T_6926) @[ifu_mem_ctl.scala 693:59] + node _T_6928 = eq(perr_ic_index_ff, UInt<6>("h036")) @[ifu_mem_ctl.scala 693:102] + node _T_6929 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6930 = and(_T_6928, _T_6929) @[ifu_mem_ctl.scala 693:124] + node _T_6931 = or(_T_6927, _T_6930) @[ifu_mem_ctl.scala 693:81] + node _T_6932 = or(_T_6931, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6933 = bits(_T_6932, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6934 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6933 : @[Reg.scala 28:19] _T_6934 <= _T_6924 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][54] <= _T_6934 @[ifu_mem_ctl.scala 693:41] - node _T_6935 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6936 = eq(_T_6935, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6937 = and(ic_valid_ff, _T_6936) @[ifu_mem_ctl.scala 693:97] - node _T_6938 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6939 = and(_T_6937, _T_6938) @[ifu_mem_ctl.scala 693:122] - node _T_6940 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[ifu_mem_ctl.scala 694:37] - node _T_6941 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_6942 = and(_T_6940, _T_6941) @[ifu_mem_ctl.scala 694:59] - node _T_6943 = eq(perr_ic_index_ff, UInt<6>("h037")) @[ifu_mem_ctl.scala 694:102] - node _T_6944 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6945 = and(_T_6943, _T_6944) @[ifu_mem_ctl.scala 694:124] - node _T_6946 = or(_T_6942, _T_6945) @[ifu_mem_ctl.scala 694:81] - node _T_6947 = or(_T_6946, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6948 = bits(_T_6947, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][54] <= _T_6934 @[ifu_mem_ctl.scala 692:41] + node _T_6935 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6936 = eq(_T_6935, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6937 = and(ic_valid_ff, _T_6936) @[ifu_mem_ctl.scala 692:97] + node _T_6938 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6939 = and(_T_6937, _T_6938) @[ifu_mem_ctl.scala 692:122] + node _T_6940 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[ifu_mem_ctl.scala 693:37] + node _T_6941 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_6942 = and(_T_6940, _T_6941) @[ifu_mem_ctl.scala 693:59] + node _T_6943 = eq(perr_ic_index_ff, UInt<6>("h037")) @[ifu_mem_ctl.scala 693:102] + node _T_6944 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6945 = and(_T_6943, _T_6944) @[ifu_mem_ctl.scala 693:124] + node _T_6946 = or(_T_6942, _T_6945) @[ifu_mem_ctl.scala 693:81] + node _T_6947 = or(_T_6946, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6948 = bits(_T_6947, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6949 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6948 : @[Reg.scala 28:19] _T_6949 <= _T_6939 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][55] <= _T_6949 @[ifu_mem_ctl.scala 693:41] - node _T_6950 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6951 = eq(_T_6950, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6952 = and(ic_valid_ff, _T_6951) @[ifu_mem_ctl.scala 693:97] - node _T_6953 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6954 = and(_T_6952, _T_6953) @[ifu_mem_ctl.scala 693:122] - node _T_6955 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[ifu_mem_ctl.scala 694:37] - node _T_6956 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_6957 = and(_T_6955, _T_6956) @[ifu_mem_ctl.scala 694:59] - node _T_6958 = eq(perr_ic_index_ff, UInt<6>("h038")) @[ifu_mem_ctl.scala 694:102] - node _T_6959 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6960 = and(_T_6958, _T_6959) @[ifu_mem_ctl.scala 694:124] - node _T_6961 = or(_T_6957, _T_6960) @[ifu_mem_ctl.scala 694:81] - node _T_6962 = or(_T_6961, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6963 = bits(_T_6962, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][55] <= _T_6949 @[ifu_mem_ctl.scala 692:41] + node _T_6950 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6951 = eq(_T_6950, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6952 = and(ic_valid_ff, _T_6951) @[ifu_mem_ctl.scala 692:97] + node _T_6953 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6954 = and(_T_6952, _T_6953) @[ifu_mem_ctl.scala 692:122] + node _T_6955 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[ifu_mem_ctl.scala 693:37] + node _T_6956 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_6957 = and(_T_6955, _T_6956) @[ifu_mem_ctl.scala 693:59] + node _T_6958 = eq(perr_ic_index_ff, UInt<6>("h038")) @[ifu_mem_ctl.scala 693:102] + node _T_6959 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6960 = and(_T_6958, _T_6959) @[ifu_mem_ctl.scala 693:124] + node _T_6961 = or(_T_6957, _T_6960) @[ifu_mem_ctl.scala 693:81] + node _T_6962 = or(_T_6961, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6963 = bits(_T_6962, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6964 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6963 : @[Reg.scala 28:19] _T_6964 <= _T_6954 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][56] <= _T_6964 @[ifu_mem_ctl.scala 693:41] - node _T_6965 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6966 = eq(_T_6965, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6967 = and(ic_valid_ff, _T_6966) @[ifu_mem_ctl.scala 693:97] - node _T_6968 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6969 = and(_T_6967, _T_6968) @[ifu_mem_ctl.scala 693:122] - node _T_6970 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[ifu_mem_ctl.scala 694:37] - node _T_6971 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_6972 = and(_T_6970, _T_6971) @[ifu_mem_ctl.scala 694:59] - node _T_6973 = eq(perr_ic_index_ff, UInt<6>("h039")) @[ifu_mem_ctl.scala 694:102] - node _T_6974 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6975 = and(_T_6973, _T_6974) @[ifu_mem_ctl.scala 694:124] - node _T_6976 = or(_T_6972, _T_6975) @[ifu_mem_ctl.scala 694:81] - node _T_6977 = or(_T_6976, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6978 = bits(_T_6977, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][56] <= _T_6964 @[ifu_mem_ctl.scala 692:41] + node _T_6965 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6966 = eq(_T_6965, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6967 = and(ic_valid_ff, _T_6966) @[ifu_mem_ctl.scala 692:97] + node _T_6968 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6969 = and(_T_6967, _T_6968) @[ifu_mem_ctl.scala 692:122] + node _T_6970 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[ifu_mem_ctl.scala 693:37] + node _T_6971 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_6972 = and(_T_6970, _T_6971) @[ifu_mem_ctl.scala 693:59] + node _T_6973 = eq(perr_ic_index_ff, UInt<6>("h039")) @[ifu_mem_ctl.scala 693:102] + node _T_6974 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6975 = and(_T_6973, _T_6974) @[ifu_mem_ctl.scala 693:124] + node _T_6976 = or(_T_6972, _T_6975) @[ifu_mem_ctl.scala 693:81] + node _T_6977 = or(_T_6976, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6978 = bits(_T_6977, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6979 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6978 : @[Reg.scala 28:19] _T_6979 <= _T_6969 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][57] <= _T_6979 @[ifu_mem_ctl.scala 693:41] - node _T_6980 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6981 = eq(_T_6980, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6982 = and(ic_valid_ff, _T_6981) @[ifu_mem_ctl.scala 693:97] - node _T_6983 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6984 = and(_T_6982, _T_6983) @[ifu_mem_ctl.scala 693:122] - node _T_6985 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[ifu_mem_ctl.scala 694:37] - node _T_6986 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_6987 = and(_T_6985, _T_6986) @[ifu_mem_ctl.scala 694:59] - node _T_6988 = eq(perr_ic_index_ff, UInt<6>("h03a")) @[ifu_mem_ctl.scala 694:102] - node _T_6989 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_6990 = and(_T_6988, _T_6989) @[ifu_mem_ctl.scala 694:124] - node _T_6991 = or(_T_6987, _T_6990) @[ifu_mem_ctl.scala 694:81] - node _T_6992 = or(_T_6991, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_6993 = bits(_T_6992, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][57] <= _T_6979 @[ifu_mem_ctl.scala 692:41] + node _T_6980 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6981 = eq(_T_6980, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6982 = and(ic_valid_ff, _T_6981) @[ifu_mem_ctl.scala 692:97] + node _T_6983 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6984 = and(_T_6982, _T_6983) @[ifu_mem_ctl.scala 692:122] + node _T_6985 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[ifu_mem_ctl.scala 693:37] + node _T_6986 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_6987 = and(_T_6985, _T_6986) @[ifu_mem_ctl.scala 693:59] + node _T_6988 = eq(perr_ic_index_ff, UInt<6>("h03a")) @[ifu_mem_ctl.scala 693:102] + node _T_6989 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_6990 = and(_T_6988, _T_6989) @[ifu_mem_ctl.scala 693:124] + node _T_6991 = or(_T_6987, _T_6990) @[ifu_mem_ctl.scala 693:81] + node _T_6992 = or(_T_6991, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_6993 = bits(_T_6992, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_6994 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6993 : @[Reg.scala 28:19] _T_6994 <= _T_6984 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][58] <= _T_6994 @[ifu_mem_ctl.scala 693:41] - node _T_6995 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_6996 = eq(_T_6995, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_6997 = and(ic_valid_ff, _T_6996) @[ifu_mem_ctl.scala 693:97] - node _T_6998 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_6999 = and(_T_6997, _T_6998) @[ifu_mem_ctl.scala 693:122] - node _T_7000 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[ifu_mem_ctl.scala 694:37] - node _T_7001 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7002 = and(_T_7000, _T_7001) @[ifu_mem_ctl.scala 694:59] - node _T_7003 = eq(perr_ic_index_ff, UInt<6>("h03b")) @[ifu_mem_ctl.scala 694:102] - node _T_7004 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7005 = and(_T_7003, _T_7004) @[ifu_mem_ctl.scala 694:124] - node _T_7006 = or(_T_7002, _T_7005) @[ifu_mem_ctl.scala 694:81] - node _T_7007 = or(_T_7006, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7008 = bits(_T_7007, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][58] <= _T_6994 @[ifu_mem_ctl.scala 692:41] + node _T_6995 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_6996 = eq(_T_6995, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_6997 = and(ic_valid_ff, _T_6996) @[ifu_mem_ctl.scala 692:97] + node _T_6998 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_6999 = and(_T_6997, _T_6998) @[ifu_mem_ctl.scala 692:122] + node _T_7000 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[ifu_mem_ctl.scala 693:37] + node _T_7001 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7002 = and(_T_7000, _T_7001) @[ifu_mem_ctl.scala 693:59] + node _T_7003 = eq(perr_ic_index_ff, UInt<6>("h03b")) @[ifu_mem_ctl.scala 693:102] + node _T_7004 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7005 = and(_T_7003, _T_7004) @[ifu_mem_ctl.scala 693:124] + node _T_7006 = or(_T_7002, _T_7005) @[ifu_mem_ctl.scala 693:81] + node _T_7007 = or(_T_7006, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7008 = bits(_T_7007, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7009 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7008 : @[Reg.scala 28:19] _T_7009 <= _T_6999 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][59] <= _T_7009 @[ifu_mem_ctl.scala 693:41] - node _T_7010 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7011 = eq(_T_7010, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7012 = and(ic_valid_ff, _T_7011) @[ifu_mem_ctl.scala 693:97] - node _T_7013 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7014 = and(_T_7012, _T_7013) @[ifu_mem_ctl.scala 693:122] - node _T_7015 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[ifu_mem_ctl.scala 694:37] - node _T_7016 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7017 = and(_T_7015, _T_7016) @[ifu_mem_ctl.scala 694:59] - node _T_7018 = eq(perr_ic_index_ff, UInt<6>("h03c")) @[ifu_mem_ctl.scala 694:102] - node _T_7019 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7020 = and(_T_7018, _T_7019) @[ifu_mem_ctl.scala 694:124] - node _T_7021 = or(_T_7017, _T_7020) @[ifu_mem_ctl.scala 694:81] - node _T_7022 = or(_T_7021, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7023 = bits(_T_7022, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][59] <= _T_7009 @[ifu_mem_ctl.scala 692:41] + node _T_7010 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7011 = eq(_T_7010, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7012 = and(ic_valid_ff, _T_7011) @[ifu_mem_ctl.scala 692:97] + node _T_7013 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7014 = and(_T_7012, _T_7013) @[ifu_mem_ctl.scala 692:122] + node _T_7015 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[ifu_mem_ctl.scala 693:37] + node _T_7016 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7017 = and(_T_7015, _T_7016) @[ifu_mem_ctl.scala 693:59] + node _T_7018 = eq(perr_ic_index_ff, UInt<6>("h03c")) @[ifu_mem_ctl.scala 693:102] + node _T_7019 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7020 = and(_T_7018, _T_7019) @[ifu_mem_ctl.scala 693:124] + node _T_7021 = or(_T_7017, _T_7020) @[ifu_mem_ctl.scala 693:81] + node _T_7022 = or(_T_7021, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7023 = bits(_T_7022, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7024 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7023 : @[Reg.scala 28:19] _T_7024 <= _T_7014 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][60] <= _T_7024 @[ifu_mem_ctl.scala 693:41] - node _T_7025 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7026 = eq(_T_7025, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7027 = and(ic_valid_ff, _T_7026) @[ifu_mem_ctl.scala 693:97] - node _T_7028 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7029 = and(_T_7027, _T_7028) @[ifu_mem_ctl.scala 693:122] - node _T_7030 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[ifu_mem_ctl.scala 694:37] - node _T_7031 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7032 = and(_T_7030, _T_7031) @[ifu_mem_ctl.scala 694:59] - node _T_7033 = eq(perr_ic_index_ff, UInt<6>("h03d")) @[ifu_mem_ctl.scala 694:102] - node _T_7034 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7035 = and(_T_7033, _T_7034) @[ifu_mem_ctl.scala 694:124] - node _T_7036 = or(_T_7032, _T_7035) @[ifu_mem_ctl.scala 694:81] - node _T_7037 = or(_T_7036, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7038 = bits(_T_7037, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][60] <= _T_7024 @[ifu_mem_ctl.scala 692:41] + node _T_7025 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7026 = eq(_T_7025, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7027 = and(ic_valid_ff, _T_7026) @[ifu_mem_ctl.scala 692:97] + node _T_7028 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7029 = and(_T_7027, _T_7028) @[ifu_mem_ctl.scala 692:122] + node _T_7030 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[ifu_mem_ctl.scala 693:37] + node _T_7031 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7032 = and(_T_7030, _T_7031) @[ifu_mem_ctl.scala 693:59] + node _T_7033 = eq(perr_ic_index_ff, UInt<6>("h03d")) @[ifu_mem_ctl.scala 693:102] + node _T_7034 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7035 = and(_T_7033, _T_7034) @[ifu_mem_ctl.scala 693:124] + node _T_7036 = or(_T_7032, _T_7035) @[ifu_mem_ctl.scala 693:81] + node _T_7037 = or(_T_7036, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7038 = bits(_T_7037, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7039 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7038 : @[Reg.scala 28:19] _T_7039 <= _T_7029 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][61] <= _T_7039 @[ifu_mem_ctl.scala 693:41] - node _T_7040 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7041 = eq(_T_7040, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7042 = and(ic_valid_ff, _T_7041) @[ifu_mem_ctl.scala 693:97] - node _T_7043 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7044 = and(_T_7042, _T_7043) @[ifu_mem_ctl.scala 693:122] - node _T_7045 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[ifu_mem_ctl.scala 694:37] - node _T_7046 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7047 = and(_T_7045, _T_7046) @[ifu_mem_ctl.scala 694:59] - node _T_7048 = eq(perr_ic_index_ff, UInt<6>("h03e")) @[ifu_mem_ctl.scala 694:102] - node _T_7049 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7050 = and(_T_7048, _T_7049) @[ifu_mem_ctl.scala 694:124] - node _T_7051 = or(_T_7047, _T_7050) @[ifu_mem_ctl.scala 694:81] - node _T_7052 = or(_T_7051, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7053 = bits(_T_7052, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][61] <= _T_7039 @[ifu_mem_ctl.scala 692:41] + node _T_7040 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7041 = eq(_T_7040, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7042 = and(ic_valid_ff, _T_7041) @[ifu_mem_ctl.scala 692:97] + node _T_7043 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7044 = and(_T_7042, _T_7043) @[ifu_mem_ctl.scala 692:122] + node _T_7045 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[ifu_mem_ctl.scala 693:37] + node _T_7046 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7047 = and(_T_7045, _T_7046) @[ifu_mem_ctl.scala 693:59] + node _T_7048 = eq(perr_ic_index_ff, UInt<6>("h03e")) @[ifu_mem_ctl.scala 693:102] + node _T_7049 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7050 = and(_T_7048, _T_7049) @[ifu_mem_ctl.scala 693:124] + node _T_7051 = or(_T_7047, _T_7050) @[ifu_mem_ctl.scala 693:81] + node _T_7052 = or(_T_7051, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7053 = bits(_T_7052, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7054 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7053 : @[Reg.scala 28:19] _T_7054 <= _T_7044 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][62] <= _T_7054 @[ifu_mem_ctl.scala 693:41] - node _T_7055 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7056 = eq(_T_7055, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7057 = and(ic_valid_ff, _T_7056) @[ifu_mem_ctl.scala 693:97] - node _T_7058 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7059 = and(_T_7057, _T_7058) @[ifu_mem_ctl.scala 693:122] - node _T_7060 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[ifu_mem_ctl.scala 694:37] - node _T_7061 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7062 = and(_T_7060, _T_7061) @[ifu_mem_ctl.scala 694:59] - node _T_7063 = eq(perr_ic_index_ff, UInt<6>("h03f")) @[ifu_mem_ctl.scala 694:102] - node _T_7064 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7065 = and(_T_7063, _T_7064) @[ifu_mem_ctl.scala 694:124] - node _T_7066 = or(_T_7062, _T_7065) @[ifu_mem_ctl.scala 694:81] - node _T_7067 = or(_T_7066, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7068 = bits(_T_7067, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][62] <= _T_7054 @[ifu_mem_ctl.scala 692:41] + node _T_7055 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7056 = eq(_T_7055, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7057 = and(ic_valid_ff, _T_7056) @[ifu_mem_ctl.scala 692:97] + node _T_7058 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7059 = and(_T_7057, _T_7058) @[ifu_mem_ctl.scala 692:122] + node _T_7060 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[ifu_mem_ctl.scala 693:37] + node _T_7061 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7062 = and(_T_7060, _T_7061) @[ifu_mem_ctl.scala 693:59] + node _T_7063 = eq(perr_ic_index_ff, UInt<6>("h03f")) @[ifu_mem_ctl.scala 693:102] + node _T_7064 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7065 = and(_T_7063, _T_7064) @[ifu_mem_ctl.scala 693:124] + node _T_7066 = or(_T_7062, _T_7065) @[ifu_mem_ctl.scala 693:81] + node _T_7067 = or(_T_7066, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7068 = bits(_T_7067, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7069 : UInt<1>, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7068 : @[Reg.scala 28:19] _T_7069 <= _T_7059 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][63] <= _T_7069 @[ifu_mem_ctl.scala 693:41] - node _T_7070 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7071 = eq(_T_7070, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7072 = and(ic_valid_ff, _T_7071) @[ifu_mem_ctl.scala 693:97] - node _T_7073 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7074 = and(_T_7072, _T_7073) @[ifu_mem_ctl.scala 693:122] - node _T_7075 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[ifu_mem_ctl.scala 694:37] - node _T_7076 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_7077 = and(_T_7075, _T_7076) @[ifu_mem_ctl.scala 694:59] - node _T_7078 = eq(perr_ic_index_ff, UInt<7>("h040")) @[ifu_mem_ctl.scala 694:102] - node _T_7079 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_7080 = and(_T_7078, _T_7079) @[ifu_mem_ctl.scala 694:124] - node _T_7081 = or(_T_7077, _T_7080) @[ifu_mem_ctl.scala 694:81] - node _T_7082 = or(_T_7081, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7083 = bits(_T_7082, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][63] <= _T_7069 @[ifu_mem_ctl.scala 692:41] + node _T_7070 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7071 = eq(_T_7070, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7072 = and(ic_valid_ff, _T_7071) @[ifu_mem_ctl.scala 692:97] + node _T_7073 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7074 = and(_T_7072, _T_7073) @[ifu_mem_ctl.scala 692:122] + node _T_7075 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[ifu_mem_ctl.scala 693:37] + node _T_7076 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_7077 = and(_T_7075, _T_7076) @[ifu_mem_ctl.scala 693:59] + node _T_7078 = eq(perr_ic_index_ff, UInt<7>("h040")) @[ifu_mem_ctl.scala 693:102] + node _T_7079 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_7080 = and(_T_7078, _T_7079) @[ifu_mem_ctl.scala 693:124] + node _T_7081 = or(_T_7077, _T_7080) @[ifu_mem_ctl.scala 693:81] + node _T_7082 = or(_T_7081, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7083 = bits(_T_7082, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7084 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7083 : @[Reg.scala 28:19] _T_7084 <= _T_7074 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][64] <= _T_7084 @[ifu_mem_ctl.scala 693:41] - node _T_7085 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7086 = eq(_T_7085, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7087 = and(ic_valid_ff, _T_7086) @[ifu_mem_ctl.scala 693:97] - node _T_7088 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7089 = and(_T_7087, _T_7088) @[ifu_mem_ctl.scala 693:122] - node _T_7090 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[ifu_mem_ctl.scala 694:37] - node _T_7091 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_7092 = and(_T_7090, _T_7091) @[ifu_mem_ctl.scala 694:59] - node _T_7093 = eq(perr_ic_index_ff, UInt<7>("h041")) @[ifu_mem_ctl.scala 694:102] - node _T_7094 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_7095 = and(_T_7093, _T_7094) @[ifu_mem_ctl.scala 694:124] - node _T_7096 = or(_T_7092, _T_7095) @[ifu_mem_ctl.scala 694:81] - node _T_7097 = or(_T_7096, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7098 = bits(_T_7097, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][64] <= _T_7084 @[ifu_mem_ctl.scala 692:41] + node _T_7085 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7086 = eq(_T_7085, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7087 = and(ic_valid_ff, _T_7086) @[ifu_mem_ctl.scala 692:97] + node _T_7088 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7089 = and(_T_7087, _T_7088) @[ifu_mem_ctl.scala 692:122] + node _T_7090 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[ifu_mem_ctl.scala 693:37] + node _T_7091 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_7092 = and(_T_7090, _T_7091) @[ifu_mem_ctl.scala 693:59] + node _T_7093 = eq(perr_ic_index_ff, UInt<7>("h041")) @[ifu_mem_ctl.scala 693:102] + node _T_7094 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_7095 = and(_T_7093, _T_7094) @[ifu_mem_ctl.scala 693:124] + node _T_7096 = or(_T_7092, _T_7095) @[ifu_mem_ctl.scala 693:81] + node _T_7097 = or(_T_7096, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7098 = bits(_T_7097, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7099 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7098 : @[Reg.scala 28:19] _T_7099 <= _T_7089 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][65] <= _T_7099 @[ifu_mem_ctl.scala 693:41] - node _T_7100 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7101 = eq(_T_7100, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7102 = and(ic_valid_ff, _T_7101) @[ifu_mem_ctl.scala 693:97] - node _T_7103 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7104 = and(_T_7102, _T_7103) @[ifu_mem_ctl.scala 693:122] - node _T_7105 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[ifu_mem_ctl.scala 694:37] - node _T_7106 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_7107 = and(_T_7105, _T_7106) @[ifu_mem_ctl.scala 694:59] - node _T_7108 = eq(perr_ic_index_ff, UInt<7>("h042")) @[ifu_mem_ctl.scala 694:102] - node _T_7109 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_7110 = and(_T_7108, _T_7109) @[ifu_mem_ctl.scala 694:124] - node _T_7111 = or(_T_7107, _T_7110) @[ifu_mem_ctl.scala 694:81] - node _T_7112 = or(_T_7111, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7113 = bits(_T_7112, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][65] <= _T_7099 @[ifu_mem_ctl.scala 692:41] + node _T_7100 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7101 = eq(_T_7100, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7102 = and(ic_valid_ff, _T_7101) @[ifu_mem_ctl.scala 692:97] + node _T_7103 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7104 = and(_T_7102, _T_7103) @[ifu_mem_ctl.scala 692:122] + node _T_7105 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[ifu_mem_ctl.scala 693:37] + node _T_7106 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_7107 = and(_T_7105, _T_7106) @[ifu_mem_ctl.scala 693:59] + node _T_7108 = eq(perr_ic_index_ff, UInt<7>("h042")) @[ifu_mem_ctl.scala 693:102] + node _T_7109 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_7110 = and(_T_7108, _T_7109) @[ifu_mem_ctl.scala 693:124] + node _T_7111 = or(_T_7107, _T_7110) @[ifu_mem_ctl.scala 693:81] + node _T_7112 = or(_T_7111, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7113 = bits(_T_7112, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7114 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7113 : @[Reg.scala 28:19] _T_7114 <= _T_7104 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][66] <= _T_7114 @[ifu_mem_ctl.scala 693:41] - node _T_7115 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7116 = eq(_T_7115, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7117 = and(ic_valid_ff, _T_7116) @[ifu_mem_ctl.scala 693:97] - node _T_7118 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7119 = and(_T_7117, _T_7118) @[ifu_mem_ctl.scala 693:122] - node _T_7120 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[ifu_mem_ctl.scala 694:37] - node _T_7121 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_7122 = and(_T_7120, _T_7121) @[ifu_mem_ctl.scala 694:59] - node _T_7123 = eq(perr_ic_index_ff, UInt<7>("h043")) @[ifu_mem_ctl.scala 694:102] - node _T_7124 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_7125 = and(_T_7123, _T_7124) @[ifu_mem_ctl.scala 694:124] - node _T_7126 = or(_T_7122, _T_7125) @[ifu_mem_ctl.scala 694:81] - node _T_7127 = or(_T_7126, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7128 = bits(_T_7127, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][66] <= _T_7114 @[ifu_mem_ctl.scala 692:41] + node _T_7115 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7116 = eq(_T_7115, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7117 = and(ic_valid_ff, _T_7116) @[ifu_mem_ctl.scala 692:97] + node _T_7118 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7119 = and(_T_7117, _T_7118) @[ifu_mem_ctl.scala 692:122] + node _T_7120 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[ifu_mem_ctl.scala 693:37] + node _T_7121 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_7122 = and(_T_7120, _T_7121) @[ifu_mem_ctl.scala 693:59] + node _T_7123 = eq(perr_ic_index_ff, UInt<7>("h043")) @[ifu_mem_ctl.scala 693:102] + node _T_7124 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_7125 = and(_T_7123, _T_7124) @[ifu_mem_ctl.scala 693:124] + node _T_7126 = or(_T_7122, _T_7125) @[ifu_mem_ctl.scala 693:81] + node _T_7127 = or(_T_7126, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7128 = bits(_T_7127, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7129 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7128 : @[Reg.scala 28:19] _T_7129 <= _T_7119 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][67] <= _T_7129 @[ifu_mem_ctl.scala 693:41] - node _T_7130 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7131 = eq(_T_7130, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7132 = and(ic_valid_ff, _T_7131) @[ifu_mem_ctl.scala 693:97] - node _T_7133 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7134 = and(_T_7132, _T_7133) @[ifu_mem_ctl.scala 693:122] - node _T_7135 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[ifu_mem_ctl.scala 694:37] - node _T_7136 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_7137 = and(_T_7135, _T_7136) @[ifu_mem_ctl.scala 694:59] - node _T_7138 = eq(perr_ic_index_ff, UInt<7>("h044")) @[ifu_mem_ctl.scala 694:102] - node _T_7139 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_7140 = and(_T_7138, _T_7139) @[ifu_mem_ctl.scala 694:124] - node _T_7141 = or(_T_7137, _T_7140) @[ifu_mem_ctl.scala 694:81] - node _T_7142 = or(_T_7141, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7143 = bits(_T_7142, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][67] <= _T_7129 @[ifu_mem_ctl.scala 692:41] + node _T_7130 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7131 = eq(_T_7130, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7132 = and(ic_valid_ff, _T_7131) @[ifu_mem_ctl.scala 692:97] + node _T_7133 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7134 = and(_T_7132, _T_7133) @[ifu_mem_ctl.scala 692:122] + node _T_7135 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[ifu_mem_ctl.scala 693:37] + node _T_7136 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_7137 = and(_T_7135, _T_7136) @[ifu_mem_ctl.scala 693:59] + node _T_7138 = eq(perr_ic_index_ff, UInt<7>("h044")) @[ifu_mem_ctl.scala 693:102] + node _T_7139 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_7140 = and(_T_7138, _T_7139) @[ifu_mem_ctl.scala 693:124] + node _T_7141 = or(_T_7137, _T_7140) @[ifu_mem_ctl.scala 693:81] + node _T_7142 = or(_T_7141, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7143 = bits(_T_7142, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7144 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7143 : @[Reg.scala 28:19] _T_7144 <= _T_7134 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][68] <= _T_7144 @[ifu_mem_ctl.scala 693:41] - node _T_7145 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7146 = eq(_T_7145, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7147 = and(ic_valid_ff, _T_7146) @[ifu_mem_ctl.scala 693:97] - node _T_7148 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7149 = and(_T_7147, _T_7148) @[ifu_mem_ctl.scala 693:122] - node _T_7150 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[ifu_mem_ctl.scala 694:37] - node _T_7151 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_7152 = and(_T_7150, _T_7151) @[ifu_mem_ctl.scala 694:59] - node _T_7153 = eq(perr_ic_index_ff, UInt<7>("h045")) @[ifu_mem_ctl.scala 694:102] - node _T_7154 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_7155 = and(_T_7153, _T_7154) @[ifu_mem_ctl.scala 694:124] - node _T_7156 = or(_T_7152, _T_7155) @[ifu_mem_ctl.scala 694:81] - node _T_7157 = or(_T_7156, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7158 = bits(_T_7157, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][68] <= _T_7144 @[ifu_mem_ctl.scala 692:41] + node _T_7145 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7146 = eq(_T_7145, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7147 = and(ic_valid_ff, _T_7146) @[ifu_mem_ctl.scala 692:97] + node _T_7148 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7149 = and(_T_7147, _T_7148) @[ifu_mem_ctl.scala 692:122] + node _T_7150 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[ifu_mem_ctl.scala 693:37] + node _T_7151 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_7152 = and(_T_7150, _T_7151) @[ifu_mem_ctl.scala 693:59] + node _T_7153 = eq(perr_ic_index_ff, UInt<7>("h045")) @[ifu_mem_ctl.scala 693:102] + node _T_7154 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_7155 = and(_T_7153, _T_7154) @[ifu_mem_ctl.scala 693:124] + node _T_7156 = or(_T_7152, _T_7155) @[ifu_mem_ctl.scala 693:81] + node _T_7157 = or(_T_7156, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7158 = bits(_T_7157, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7159 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7158 : @[Reg.scala 28:19] _T_7159 <= _T_7149 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][69] <= _T_7159 @[ifu_mem_ctl.scala 693:41] - node _T_7160 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7161 = eq(_T_7160, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7162 = and(ic_valid_ff, _T_7161) @[ifu_mem_ctl.scala 693:97] - node _T_7163 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7164 = and(_T_7162, _T_7163) @[ifu_mem_ctl.scala 693:122] - node _T_7165 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[ifu_mem_ctl.scala 694:37] - node _T_7166 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_7167 = and(_T_7165, _T_7166) @[ifu_mem_ctl.scala 694:59] - node _T_7168 = eq(perr_ic_index_ff, UInt<7>("h046")) @[ifu_mem_ctl.scala 694:102] - node _T_7169 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_7170 = and(_T_7168, _T_7169) @[ifu_mem_ctl.scala 694:124] - node _T_7171 = or(_T_7167, _T_7170) @[ifu_mem_ctl.scala 694:81] - node _T_7172 = or(_T_7171, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7173 = bits(_T_7172, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][69] <= _T_7159 @[ifu_mem_ctl.scala 692:41] + node _T_7160 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7161 = eq(_T_7160, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7162 = and(ic_valid_ff, _T_7161) @[ifu_mem_ctl.scala 692:97] + node _T_7163 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7164 = and(_T_7162, _T_7163) @[ifu_mem_ctl.scala 692:122] + node _T_7165 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[ifu_mem_ctl.scala 693:37] + node _T_7166 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_7167 = and(_T_7165, _T_7166) @[ifu_mem_ctl.scala 693:59] + node _T_7168 = eq(perr_ic_index_ff, UInt<7>("h046")) @[ifu_mem_ctl.scala 693:102] + node _T_7169 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_7170 = and(_T_7168, _T_7169) @[ifu_mem_ctl.scala 693:124] + node _T_7171 = or(_T_7167, _T_7170) @[ifu_mem_ctl.scala 693:81] + node _T_7172 = or(_T_7171, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7173 = bits(_T_7172, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7174 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7173 : @[Reg.scala 28:19] _T_7174 <= _T_7164 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][70] <= _T_7174 @[ifu_mem_ctl.scala 693:41] - node _T_7175 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7176 = eq(_T_7175, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7177 = and(ic_valid_ff, _T_7176) @[ifu_mem_ctl.scala 693:97] - node _T_7178 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7179 = and(_T_7177, _T_7178) @[ifu_mem_ctl.scala 693:122] - node _T_7180 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[ifu_mem_ctl.scala 694:37] - node _T_7181 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_7182 = and(_T_7180, _T_7181) @[ifu_mem_ctl.scala 694:59] - node _T_7183 = eq(perr_ic_index_ff, UInt<7>("h047")) @[ifu_mem_ctl.scala 694:102] - node _T_7184 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_7185 = and(_T_7183, _T_7184) @[ifu_mem_ctl.scala 694:124] - node _T_7186 = or(_T_7182, _T_7185) @[ifu_mem_ctl.scala 694:81] - node _T_7187 = or(_T_7186, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7188 = bits(_T_7187, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][70] <= _T_7174 @[ifu_mem_ctl.scala 692:41] + node _T_7175 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7176 = eq(_T_7175, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7177 = and(ic_valid_ff, _T_7176) @[ifu_mem_ctl.scala 692:97] + node _T_7178 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7179 = and(_T_7177, _T_7178) @[ifu_mem_ctl.scala 692:122] + node _T_7180 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[ifu_mem_ctl.scala 693:37] + node _T_7181 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_7182 = and(_T_7180, _T_7181) @[ifu_mem_ctl.scala 693:59] + node _T_7183 = eq(perr_ic_index_ff, UInt<7>("h047")) @[ifu_mem_ctl.scala 693:102] + node _T_7184 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_7185 = and(_T_7183, _T_7184) @[ifu_mem_ctl.scala 693:124] + node _T_7186 = or(_T_7182, _T_7185) @[ifu_mem_ctl.scala 693:81] + node _T_7187 = or(_T_7186, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7188 = bits(_T_7187, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7189 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7188 : @[Reg.scala 28:19] _T_7189 <= _T_7179 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][71] <= _T_7189 @[ifu_mem_ctl.scala 693:41] - node _T_7190 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7191 = eq(_T_7190, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7192 = and(ic_valid_ff, _T_7191) @[ifu_mem_ctl.scala 693:97] - node _T_7193 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7194 = and(_T_7192, _T_7193) @[ifu_mem_ctl.scala 693:122] - node _T_7195 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[ifu_mem_ctl.scala 694:37] - node _T_7196 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_7197 = and(_T_7195, _T_7196) @[ifu_mem_ctl.scala 694:59] - node _T_7198 = eq(perr_ic_index_ff, UInt<7>("h048")) @[ifu_mem_ctl.scala 694:102] - node _T_7199 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_7200 = and(_T_7198, _T_7199) @[ifu_mem_ctl.scala 694:124] - node _T_7201 = or(_T_7197, _T_7200) @[ifu_mem_ctl.scala 694:81] - node _T_7202 = or(_T_7201, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7203 = bits(_T_7202, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][71] <= _T_7189 @[ifu_mem_ctl.scala 692:41] + node _T_7190 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7191 = eq(_T_7190, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7192 = and(ic_valid_ff, _T_7191) @[ifu_mem_ctl.scala 692:97] + node _T_7193 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7194 = and(_T_7192, _T_7193) @[ifu_mem_ctl.scala 692:122] + node _T_7195 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[ifu_mem_ctl.scala 693:37] + node _T_7196 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_7197 = and(_T_7195, _T_7196) @[ifu_mem_ctl.scala 693:59] + node _T_7198 = eq(perr_ic_index_ff, UInt<7>("h048")) @[ifu_mem_ctl.scala 693:102] + node _T_7199 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_7200 = and(_T_7198, _T_7199) @[ifu_mem_ctl.scala 693:124] + node _T_7201 = or(_T_7197, _T_7200) @[ifu_mem_ctl.scala 693:81] + node _T_7202 = or(_T_7201, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7203 = bits(_T_7202, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7204 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7203 : @[Reg.scala 28:19] _T_7204 <= _T_7194 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][72] <= _T_7204 @[ifu_mem_ctl.scala 693:41] - node _T_7205 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7206 = eq(_T_7205, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7207 = and(ic_valid_ff, _T_7206) @[ifu_mem_ctl.scala 693:97] - node _T_7208 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7209 = and(_T_7207, _T_7208) @[ifu_mem_ctl.scala 693:122] - node _T_7210 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[ifu_mem_ctl.scala 694:37] - node _T_7211 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_7212 = and(_T_7210, _T_7211) @[ifu_mem_ctl.scala 694:59] - node _T_7213 = eq(perr_ic_index_ff, UInt<7>("h049")) @[ifu_mem_ctl.scala 694:102] - node _T_7214 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_7215 = and(_T_7213, _T_7214) @[ifu_mem_ctl.scala 694:124] - node _T_7216 = or(_T_7212, _T_7215) @[ifu_mem_ctl.scala 694:81] - node _T_7217 = or(_T_7216, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7218 = bits(_T_7217, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][72] <= _T_7204 @[ifu_mem_ctl.scala 692:41] + node _T_7205 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7206 = eq(_T_7205, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7207 = and(ic_valid_ff, _T_7206) @[ifu_mem_ctl.scala 692:97] + node _T_7208 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7209 = and(_T_7207, _T_7208) @[ifu_mem_ctl.scala 692:122] + node _T_7210 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[ifu_mem_ctl.scala 693:37] + node _T_7211 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_7212 = and(_T_7210, _T_7211) @[ifu_mem_ctl.scala 693:59] + node _T_7213 = eq(perr_ic_index_ff, UInt<7>("h049")) @[ifu_mem_ctl.scala 693:102] + node _T_7214 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_7215 = and(_T_7213, _T_7214) @[ifu_mem_ctl.scala 693:124] + node _T_7216 = or(_T_7212, _T_7215) @[ifu_mem_ctl.scala 693:81] + node _T_7217 = or(_T_7216, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7218 = bits(_T_7217, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7219 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7218 : @[Reg.scala 28:19] _T_7219 <= _T_7209 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][73] <= _T_7219 @[ifu_mem_ctl.scala 693:41] - node _T_7220 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7221 = eq(_T_7220, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7222 = and(ic_valid_ff, _T_7221) @[ifu_mem_ctl.scala 693:97] - node _T_7223 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7224 = and(_T_7222, _T_7223) @[ifu_mem_ctl.scala 693:122] - node _T_7225 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[ifu_mem_ctl.scala 694:37] - node _T_7226 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_7227 = and(_T_7225, _T_7226) @[ifu_mem_ctl.scala 694:59] - node _T_7228 = eq(perr_ic_index_ff, UInt<7>("h04a")) @[ifu_mem_ctl.scala 694:102] - node _T_7229 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_7230 = and(_T_7228, _T_7229) @[ifu_mem_ctl.scala 694:124] - node _T_7231 = or(_T_7227, _T_7230) @[ifu_mem_ctl.scala 694:81] - node _T_7232 = or(_T_7231, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7233 = bits(_T_7232, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][73] <= _T_7219 @[ifu_mem_ctl.scala 692:41] + node _T_7220 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7221 = eq(_T_7220, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7222 = and(ic_valid_ff, _T_7221) @[ifu_mem_ctl.scala 692:97] + node _T_7223 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7224 = and(_T_7222, _T_7223) @[ifu_mem_ctl.scala 692:122] + node _T_7225 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[ifu_mem_ctl.scala 693:37] + node _T_7226 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_7227 = and(_T_7225, _T_7226) @[ifu_mem_ctl.scala 693:59] + node _T_7228 = eq(perr_ic_index_ff, UInt<7>("h04a")) @[ifu_mem_ctl.scala 693:102] + node _T_7229 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_7230 = and(_T_7228, _T_7229) @[ifu_mem_ctl.scala 693:124] + node _T_7231 = or(_T_7227, _T_7230) @[ifu_mem_ctl.scala 693:81] + node _T_7232 = or(_T_7231, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7233 = bits(_T_7232, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7234 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7233 : @[Reg.scala 28:19] _T_7234 <= _T_7224 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][74] <= _T_7234 @[ifu_mem_ctl.scala 693:41] - node _T_7235 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7236 = eq(_T_7235, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7237 = and(ic_valid_ff, _T_7236) @[ifu_mem_ctl.scala 693:97] - node _T_7238 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7239 = and(_T_7237, _T_7238) @[ifu_mem_ctl.scala 693:122] - node _T_7240 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[ifu_mem_ctl.scala 694:37] - node _T_7241 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_7242 = and(_T_7240, _T_7241) @[ifu_mem_ctl.scala 694:59] - node _T_7243 = eq(perr_ic_index_ff, UInt<7>("h04b")) @[ifu_mem_ctl.scala 694:102] - node _T_7244 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_7245 = and(_T_7243, _T_7244) @[ifu_mem_ctl.scala 694:124] - node _T_7246 = or(_T_7242, _T_7245) @[ifu_mem_ctl.scala 694:81] - node _T_7247 = or(_T_7246, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7248 = bits(_T_7247, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][74] <= _T_7234 @[ifu_mem_ctl.scala 692:41] + node _T_7235 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7236 = eq(_T_7235, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7237 = and(ic_valid_ff, _T_7236) @[ifu_mem_ctl.scala 692:97] + node _T_7238 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7239 = and(_T_7237, _T_7238) @[ifu_mem_ctl.scala 692:122] + node _T_7240 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[ifu_mem_ctl.scala 693:37] + node _T_7241 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_7242 = and(_T_7240, _T_7241) @[ifu_mem_ctl.scala 693:59] + node _T_7243 = eq(perr_ic_index_ff, UInt<7>("h04b")) @[ifu_mem_ctl.scala 693:102] + node _T_7244 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_7245 = and(_T_7243, _T_7244) @[ifu_mem_ctl.scala 693:124] + node _T_7246 = or(_T_7242, _T_7245) @[ifu_mem_ctl.scala 693:81] + node _T_7247 = or(_T_7246, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7248 = bits(_T_7247, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7249 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7248 : @[Reg.scala 28:19] _T_7249 <= _T_7239 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][75] <= _T_7249 @[ifu_mem_ctl.scala 693:41] - node _T_7250 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7251 = eq(_T_7250, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7252 = and(ic_valid_ff, _T_7251) @[ifu_mem_ctl.scala 693:97] - node _T_7253 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7254 = and(_T_7252, _T_7253) @[ifu_mem_ctl.scala 693:122] - node _T_7255 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[ifu_mem_ctl.scala 694:37] - node _T_7256 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_7257 = and(_T_7255, _T_7256) @[ifu_mem_ctl.scala 694:59] - node _T_7258 = eq(perr_ic_index_ff, UInt<7>("h04c")) @[ifu_mem_ctl.scala 694:102] - node _T_7259 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_7260 = and(_T_7258, _T_7259) @[ifu_mem_ctl.scala 694:124] - node _T_7261 = or(_T_7257, _T_7260) @[ifu_mem_ctl.scala 694:81] - node _T_7262 = or(_T_7261, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7263 = bits(_T_7262, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][75] <= _T_7249 @[ifu_mem_ctl.scala 692:41] + node _T_7250 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7251 = eq(_T_7250, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7252 = and(ic_valid_ff, _T_7251) @[ifu_mem_ctl.scala 692:97] + node _T_7253 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7254 = and(_T_7252, _T_7253) @[ifu_mem_ctl.scala 692:122] + node _T_7255 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[ifu_mem_ctl.scala 693:37] + node _T_7256 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_7257 = and(_T_7255, _T_7256) @[ifu_mem_ctl.scala 693:59] + node _T_7258 = eq(perr_ic_index_ff, UInt<7>("h04c")) @[ifu_mem_ctl.scala 693:102] + node _T_7259 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_7260 = and(_T_7258, _T_7259) @[ifu_mem_ctl.scala 693:124] + node _T_7261 = or(_T_7257, _T_7260) @[ifu_mem_ctl.scala 693:81] + node _T_7262 = or(_T_7261, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7263 = bits(_T_7262, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7264 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7263 : @[Reg.scala 28:19] _T_7264 <= _T_7254 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][76] <= _T_7264 @[ifu_mem_ctl.scala 693:41] - node _T_7265 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7266 = eq(_T_7265, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7267 = and(ic_valid_ff, _T_7266) @[ifu_mem_ctl.scala 693:97] - node _T_7268 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7269 = and(_T_7267, _T_7268) @[ifu_mem_ctl.scala 693:122] - node _T_7270 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[ifu_mem_ctl.scala 694:37] - node _T_7271 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_7272 = and(_T_7270, _T_7271) @[ifu_mem_ctl.scala 694:59] - node _T_7273 = eq(perr_ic_index_ff, UInt<7>("h04d")) @[ifu_mem_ctl.scala 694:102] - node _T_7274 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_7275 = and(_T_7273, _T_7274) @[ifu_mem_ctl.scala 694:124] - node _T_7276 = or(_T_7272, _T_7275) @[ifu_mem_ctl.scala 694:81] - node _T_7277 = or(_T_7276, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7278 = bits(_T_7277, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][76] <= _T_7264 @[ifu_mem_ctl.scala 692:41] + node _T_7265 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7266 = eq(_T_7265, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7267 = and(ic_valid_ff, _T_7266) @[ifu_mem_ctl.scala 692:97] + node _T_7268 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7269 = and(_T_7267, _T_7268) @[ifu_mem_ctl.scala 692:122] + node _T_7270 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[ifu_mem_ctl.scala 693:37] + node _T_7271 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_7272 = and(_T_7270, _T_7271) @[ifu_mem_ctl.scala 693:59] + node _T_7273 = eq(perr_ic_index_ff, UInt<7>("h04d")) @[ifu_mem_ctl.scala 693:102] + node _T_7274 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_7275 = and(_T_7273, _T_7274) @[ifu_mem_ctl.scala 693:124] + node _T_7276 = or(_T_7272, _T_7275) @[ifu_mem_ctl.scala 693:81] + node _T_7277 = or(_T_7276, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7278 = bits(_T_7277, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7279 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7278 : @[Reg.scala 28:19] _T_7279 <= _T_7269 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][77] <= _T_7279 @[ifu_mem_ctl.scala 693:41] - node _T_7280 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7281 = eq(_T_7280, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7282 = and(ic_valid_ff, _T_7281) @[ifu_mem_ctl.scala 693:97] - node _T_7283 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7284 = and(_T_7282, _T_7283) @[ifu_mem_ctl.scala 693:122] - node _T_7285 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[ifu_mem_ctl.scala 694:37] - node _T_7286 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_7287 = and(_T_7285, _T_7286) @[ifu_mem_ctl.scala 694:59] - node _T_7288 = eq(perr_ic_index_ff, UInt<7>("h04e")) @[ifu_mem_ctl.scala 694:102] - node _T_7289 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_7290 = and(_T_7288, _T_7289) @[ifu_mem_ctl.scala 694:124] - node _T_7291 = or(_T_7287, _T_7290) @[ifu_mem_ctl.scala 694:81] - node _T_7292 = or(_T_7291, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7293 = bits(_T_7292, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][77] <= _T_7279 @[ifu_mem_ctl.scala 692:41] + node _T_7280 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7281 = eq(_T_7280, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7282 = and(ic_valid_ff, _T_7281) @[ifu_mem_ctl.scala 692:97] + node _T_7283 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7284 = and(_T_7282, _T_7283) @[ifu_mem_ctl.scala 692:122] + node _T_7285 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[ifu_mem_ctl.scala 693:37] + node _T_7286 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_7287 = and(_T_7285, _T_7286) @[ifu_mem_ctl.scala 693:59] + node _T_7288 = eq(perr_ic_index_ff, UInt<7>("h04e")) @[ifu_mem_ctl.scala 693:102] + node _T_7289 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_7290 = and(_T_7288, _T_7289) @[ifu_mem_ctl.scala 693:124] + node _T_7291 = or(_T_7287, _T_7290) @[ifu_mem_ctl.scala 693:81] + node _T_7292 = or(_T_7291, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7293 = bits(_T_7292, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7294 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7293 : @[Reg.scala 28:19] _T_7294 <= _T_7284 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][78] <= _T_7294 @[ifu_mem_ctl.scala 693:41] - node _T_7295 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7296 = eq(_T_7295, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7297 = and(ic_valid_ff, _T_7296) @[ifu_mem_ctl.scala 693:97] - node _T_7298 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7299 = and(_T_7297, _T_7298) @[ifu_mem_ctl.scala 693:122] - node _T_7300 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[ifu_mem_ctl.scala 694:37] - node _T_7301 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_7302 = and(_T_7300, _T_7301) @[ifu_mem_ctl.scala 694:59] - node _T_7303 = eq(perr_ic_index_ff, UInt<7>("h04f")) @[ifu_mem_ctl.scala 694:102] - node _T_7304 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_7305 = and(_T_7303, _T_7304) @[ifu_mem_ctl.scala 694:124] - node _T_7306 = or(_T_7302, _T_7305) @[ifu_mem_ctl.scala 694:81] - node _T_7307 = or(_T_7306, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7308 = bits(_T_7307, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][78] <= _T_7294 @[ifu_mem_ctl.scala 692:41] + node _T_7295 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7296 = eq(_T_7295, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7297 = and(ic_valid_ff, _T_7296) @[ifu_mem_ctl.scala 692:97] + node _T_7298 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7299 = and(_T_7297, _T_7298) @[ifu_mem_ctl.scala 692:122] + node _T_7300 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[ifu_mem_ctl.scala 693:37] + node _T_7301 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_7302 = and(_T_7300, _T_7301) @[ifu_mem_ctl.scala 693:59] + node _T_7303 = eq(perr_ic_index_ff, UInt<7>("h04f")) @[ifu_mem_ctl.scala 693:102] + node _T_7304 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_7305 = and(_T_7303, _T_7304) @[ifu_mem_ctl.scala 693:124] + node _T_7306 = or(_T_7302, _T_7305) @[ifu_mem_ctl.scala 693:81] + node _T_7307 = or(_T_7306, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7308 = bits(_T_7307, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7309 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7308 : @[Reg.scala 28:19] _T_7309 <= _T_7299 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][79] <= _T_7309 @[ifu_mem_ctl.scala 693:41] - node _T_7310 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7311 = eq(_T_7310, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7312 = and(ic_valid_ff, _T_7311) @[ifu_mem_ctl.scala 693:97] - node _T_7313 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7314 = and(_T_7312, _T_7313) @[ifu_mem_ctl.scala 693:122] - node _T_7315 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[ifu_mem_ctl.scala 694:37] - node _T_7316 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_7317 = and(_T_7315, _T_7316) @[ifu_mem_ctl.scala 694:59] - node _T_7318 = eq(perr_ic_index_ff, UInt<7>("h050")) @[ifu_mem_ctl.scala 694:102] - node _T_7319 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_7320 = and(_T_7318, _T_7319) @[ifu_mem_ctl.scala 694:124] - node _T_7321 = or(_T_7317, _T_7320) @[ifu_mem_ctl.scala 694:81] - node _T_7322 = or(_T_7321, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7323 = bits(_T_7322, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][79] <= _T_7309 @[ifu_mem_ctl.scala 692:41] + node _T_7310 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7311 = eq(_T_7310, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7312 = and(ic_valid_ff, _T_7311) @[ifu_mem_ctl.scala 692:97] + node _T_7313 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7314 = and(_T_7312, _T_7313) @[ifu_mem_ctl.scala 692:122] + node _T_7315 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[ifu_mem_ctl.scala 693:37] + node _T_7316 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_7317 = and(_T_7315, _T_7316) @[ifu_mem_ctl.scala 693:59] + node _T_7318 = eq(perr_ic_index_ff, UInt<7>("h050")) @[ifu_mem_ctl.scala 693:102] + node _T_7319 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_7320 = and(_T_7318, _T_7319) @[ifu_mem_ctl.scala 693:124] + node _T_7321 = or(_T_7317, _T_7320) @[ifu_mem_ctl.scala 693:81] + node _T_7322 = or(_T_7321, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7323 = bits(_T_7322, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7324 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7323 : @[Reg.scala 28:19] _T_7324 <= _T_7314 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][80] <= _T_7324 @[ifu_mem_ctl.scala 693:41] - node _T_7325 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7326 = eq(_T_7325, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7327 = and(ic_valid_ff, _T_7326) @[ifu_mem_ctl.scala 693:97] - node _T_7328 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7329 = and(_T_7327, _T_7328) @[ifu_mem_ctl.scala 693:122] - node _T_7330 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[ifu_mem_ctl.scala 694:37] - node _T_7331 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_7332 = and(_T_7330, _T_7331) @[ifu_mem_ctl.scala 694:59] - node _T_7333 = eq(perr_ic_index_ff, UInt<7>("h051")) @[ifu_mem_ctl.scala 694:102] - node _T_7334 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_7335 = and(_T_7333, _T_7334) @[ifu_mem_ctl.scala 694:124] - node _T_7336 = or(_T_7332, _T_7335) @[ifu_mem_ctl.scala 694:81] - node _T_7337 = or(_T_7336, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7338 = bits(_T_7337, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][80] <= _T_7324 @[ifu_mem_ctl.scala 692:41] + node _T_7325 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7326 = eq(_T_7325, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7327 = and(ic_valid_ff, _T_7326) @[ifu_mem_ctl.scala 692:97] + node _T_7328 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7329 = and(_T_7327, _T_7328) @[ifu_mem_ctl.scala 692:122] + node _T_7330 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[ifu_mem_ctl.scala 693:37] + node _T_7331 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_7332 = and(_T_7330, _T_7331) @[ifu_mem_ctl.scala 693:59] + node _T_7333 = eq(perr_ic_index_ff, UInt<7>("h051")) @[ifu_mem_ctl.scala 693:102] + node _T_7334 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_7335 = and(_T_7333, _T_7334) @[ifu_mem_ctl.scala 693:124] + node _T_7336 = or(_T_7332, _T_7335) @[ifu_mem_ctl.scala 693:81] + node _T_7337 = or(_T_7336, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7338 = bits(_T_7337, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7339 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7338 : @[Reg.scala 28:19] _T_7339 <= _T_7329 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][81] <= _T_7339 @[ifu_mem_ctl.scala 693:41] - node _T_7340 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7341 = eq(_T_7340, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7342 = and(ic_valid_ff, _T_7341) @[ifu_mem_ctl.scala 693:97] - node _T_7343 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7344 = and(_T_7342, _T_7343) @[ifu_mem_ctl.scala 693:122] - node _T_7345 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[ifu_mem_ctl.scala 694:37] - node _T_7346 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_7347 = and(_T_7345, _T_7346) @[ifu_mem_ctl.scala 694:59] - node _T_7348 = eq(perr_ic_index_ff, UInt<7>("h052")) @[ifu_mem_ctl.scala 694:102] - node _T_7349 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_7350 = and(_T_7348, _T_7349) @[ifu_mem_ctl.scala 694:124] - node _T_7351 = or(_T_7347, _T_7350) @[ifu_mem_ctl.scala 694:81] - node _T_7352 = or(_T_7351, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7353 = bits(_T_7352, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][81] <= _T_7339 @[ifu_mem_ctl.scala 692:41] + node _T_7340 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7341 = eq(_T_7340, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7342 = and(ic_valid_ff, _T_7341) @[ifu_mem_ctl.scala 692:97] + node _T_7343 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7344 = and(_T_7342, _T_7343) @[ifu_mem_ctl.scala 692:122] + node _T_7345 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[ifu_mem_ctl.scala 693:37] + node _T_7346 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_7347 = and(_T_7345, _T_7346) @[ifu_mem_ctl.scala 693:59] + node _T_7348 = eq(perr_ic_index_ff, UInt<7>("h052")) @[ifu_mem_ctl.scala 693:102] + node _T_7349 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_7350 = and(_T_7348, _T_7349) @[ifu_mem_ctl.scala 693:124] + node _T_7351 = or(_T_7347, _T_7350) @[ifu_mem_ctl.scala 693:81] + node _T_7352 = or(_T_7351, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7353 = bits(_T_7352, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7354 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7353 : @[Reg.scala 28:19] _T_7354 <= _T_7344 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][82] <= _T_7354 @[ifu_mem_ctl.scala 693:41] - node _T_7355 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7356 = eq(_T_7355, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7357 = and(ic_valid_ff, _T_7356) @[ifu_mem_ctl.scala 693:97] - node _T_7358 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7359 = and(_T_7357, _T_7358) @[ifu_mem_ctl.scala 693:122] - node _T_7360 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[ifu_mem_ctl.scala 694:37] - node _T_7361 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_7362 = and(_T_7360, _T_7361) @[ifu_mem_ctl.scala 694:59] - node _T_7363 = eq(perr_ic_index_ff, UInt<7>("h053")) @[ifu_mem_ctl.scala 694:102] - node _T_7364 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_7365 = and(_T_7363, _T_7364) @[ifu_mem_ctl.scala 694:124] - node _T_7366 = or(_T_7362, _T_7365) @[ifu_mem_ctl.scala 694:81] - node _T_7367 = or(_T_7366, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7368 = bits(_T_7367, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][82] <= _T_7354 @[ifu_mem_ctl.scala 692:41] + node _T_7355 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7356 = eq(_T_7355, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7357 = and(ic_valid_ff, _T_7356) @[ifu_mem_ctl.scala 692:97] + node _T_7358 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7359 = and(_T_7357, _T_7358) @[ifu_mem_ctl.scala 692:122] + node _T_7360 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[ifu_mem_ctl.scala 693:37] + node _T_7361 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_7362 = and(_T_7360, _T_7361) @[ifu_mem_ctl.scala 693:59] + node _T_7363 = eq(perr_ic_index_ff, UInt<7>("h053")) @[ifu_mem_ctl.scala 693:102] + node _T_7364 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_7365 = and(_T_7363, _T_7364) @[ifu_mem_ctl.scala 693:124] + node _T_7366 = or(_T_7362, _T_7365) @[ifu_mem_ctl.scala 693:81] + node _T_7367 = or(_T_7366, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7368 = bits(_T_7367, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7369 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7368 : @[Reg.scala 28:19] _T_7369 <= _T_7359 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][83] <= _T_7369 @[ifu_mem_ctl.scala 693:41] - node _T_7370 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7371 = eq(_T_7370, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7372 = and(ic_valid_ff, _T_7371) @[ifu_mem_ctl.scala 693:97] - node _T_7373 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7374 = and(_T_7372, _T_7373) @[ifu_mem_ctl.scala 693:122] - node _T_7375 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[ifu_mem_ctl.scala 694:37] - node _T_7376 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_7377 = and(_T_7375, _T_7376) @[ifu_mem_ctl.scala 694:59] - node _T_7378 = eq(perr_ic_index_ff, UInt<7>("h054")) @[ifu_mem_ctl.scala 694:102] - node _T_7379 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_7380 = and(_T_7378, _T_7379) @[ifu_mem_ctl.scala 694:124] - node _T_7381 = or(_T_7377, _T_7380) @[ifu_mem_ctl.scala 694:81] - node _T_7382 = or(_T_7381, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7383 = bits(_T_7382, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][83] <= _T_7369 @[ifu_mem_ctl.scala 692:41] + node _T_7370 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7371 = eq(_T_7370, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7372 = and(ic_valid_ff, _T_7371) @[ifu_mem_ctl.scala 692:97] + node _T_7373 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7374 = and(_T_7372, _T_7373) @[ifu_mem_ctl.scala 692:122] + node _T_7375 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[ifu_mem_ctl.scala 693:37] + node _T_7376 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_7377 = and(_T_7375, _T_7376) @[ifu_mem_ctl.scala 693:59] + node _T_7378 = eq(perr_ic_index_ff, UInt<7>("h054")) @[ifu_mem_ctl.scala 693:102] + node _T_7379 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_7380 = and(_T_7378, _T_7379) @[ifu_mem_ctl.scala 693:124] + node _T_7381 = or(_T_7377, _T_7380) @[ifu_mem_ctl.scala 693:81] + node _T_7382 = or(_T_7381, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7383 = bits(_T_7382, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7384 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7383 : @[Reg.scala 28:19] _T_7384 <= _T_7374 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][84] <= _T_7384 @[ifu_mem_ctl.scala 693:41] - node _T_7385 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7386 = eq(_T_7385, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7387 = and(ic_valid_ff, _T_7386) @[ifu_mem_ctl.scala 693:97] - node _T_7388 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7389 = and(_T_7387, _T_7388) @[ifu_mem_ctl.scala 693:122] - node _T_7390 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[ifu_mem_ctl.scala 694:37] - node _T_7391 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_7392 = and(_T_7390, _T_7391) @[ifu_mem_ctl.scala 694:59] - node _T_7393 = eq(perr_ic_index_ff, UInt<7>("h055")) @[ifu_mem_ctl.scala 694:102] - node _T_7394 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_7395 = and(_T_7393, _T_7394) @[ifu_mem_ctl.scala 694:124] - node _T_7396 = or(_T_7392, _T_7395) @[ifu_mem_ctl.scala 694:81] - node _T_7397 = or(_T_7396, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7398 = bits(_T_7397, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][84] <= _T_7384 @[ifu_mem_ctl.scala 692:41] + node _T_7385 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7386 = eq(_T_7385, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7387 = and(ic_valid_ff, _T_7386) @[ifu_mem_ctl.scala 692:97] + node _T_7388 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7389 = and(_T_7387, _T_7388) @[ifu_mem_ctl.scala 692:122] + node _T_7390 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[ifu_mem_ctl.scala 693:37] + node _T_7391 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_7392 = and(_T_7390, _T_7391) @[ifu_mem_ctl.scala 693:59] + node _T_7393 = eq(perr_ic_index_ff, UInt<7>("h055")) @[ifu_mem_ctl.scala 693:102] + node _T_7394 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_7395 = and(_T_7393, _T_7394) @[ifu_mem_ctl.scala 693:124] + node _T_7396 = or(_T_7392, _T_7395) @[ifu_mem_ctl.scala 693:81] + node _T_7397 = or(_T_7396, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7398 = bits(_T_7397, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7399 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7398 : @[Reg.scala 28:19] _T_7399 <= _T_7389 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][85] <= _T_7399 @[ifu_mem_ctl.scala 693:41] - node _T_7400 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7401 = eq(_T_7400, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7402 = and(ic_valid_ff, _T_7401) @[ifu_mem_ctl.scala 693:97] - node _T_7403 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7404 = and(_T_7402, _T_7403) @[ifu_mem_ctl.scala 693:122] - node _T_7405 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[ifu_mem_ctl.scala 694:37] - node _T_7406 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_7407 = and(_T_7405, _T_7406) @[ifu_mem_ctl.scala 694:59] - node _T_7408 = eq(perr_ic_index_ff, UInt<7>("h056")) @[ifu_mem_ctl.scala 694:102] - node _T_7409 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_7410 = and(_T_7408, _T_7409) @[ifu_mem_ctl.scala 694:124] - node _T_7411 = or(_T_7407, _T_7410) @[ifu_mem_ctl.scala 694:81] - node _T_7412 = or(_T_7411, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7413 = bits(_T_7412, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][85] <= _T_7399 @[ifu_mem_ctl.scala 692:41] + node _T_7400 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7401 = eq(_T_7400, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7402 = and(ic_valid_ff, _T_7401) @[ifu_mem_ctl.scala 692:97] + node _T_7403 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7404 = and(_T_7402, _T_7403) @[ifu_mem_ctl.scala 692:122] + node _T_7405 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[ifu_mem_ctl.scala 693:37] + node _T_7406 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_7407 = and(_T_7405, _T_7406) @[ifu_mem_ctl.scala 693:59] + node _T_7408 = eq(perr_ic_index_ff, UInt<7>("h056")) @[ifu_mem_ctl.scala 693:102] + node _T_7409 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_7410 = and(_T_7408, _T_7409) @[ifu_mem_ctl.scala 693:124] + node _T_7411 = or(_T_7407, _T_7410) @[ifu_mem_ctl.scala 693:81] + node _T_7412 = or(_T_7411, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7413 = bits(_T_7412, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7414 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7413 : @[Reg.scala 28:19] _T_7414 <= _T_7404 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][86] <= _T_7414 @[ifu_mem_ctl.scala 693:41] - node _T_7415 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7416 = eq(_T_7415, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7417 = and(ic_valid_ff, _T_7416) @[ifu_mem_ctl.scala 693:97] - node _T_7418 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7419 = and(_T_7417, _T_7418) @[ifu_mem_ctl.scala 693:122] - node _T_7420 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[ifu_mem_ctl.scala 694:37] - node _T_7421 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_7422 = and(_T_7420, _T_7421) @[ifu_mem_ctl.scala 694:59] - node _T_7423 = eq(perr_ic_index_ff, UInt<7>("h057")) @[ifu_mem_ctl.scala 694:102] - node _T_7424 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_7425 = and(_T_7423, _T_7424) @[ifu_mem_ctl.scala 694:124] - node _T_7426 = or(_T_7422, _T_7425) @[ifu_mem_ctl.scala 694:81] - node _T_7427 = or(_T_7426, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7428 = bits(_T_7427, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][86] <= _T_7414 @[ifu_mem_ctl.scala 692:41] + node _T_7415 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7416 = eq(_T_7415, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7417 = and(ic_valid_ff, _T_7416) @[ifu_mem_ctl.scala 692:97] + node _T_7418 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7419 = and(_T_7417, _T_7418) @[ifu_mem_ctl.scala 692:122] + node _T_7420 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[ifu_mem_ctl.scala 693:37] + node _T_7421 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_7422 = and(_T_7420, _T_7421) @[ifu_mem_ctl.scala 693:59] + node _T_7423 = eq(perr_ic_index_ff, UInt<7>("h057")) @[ifu_mem_ctl.scala 693:102] + node _T_7424 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_7425 = and(_T_7423, _T_7424) @[ifu_mem_ctl.scala 693:124] + node _T_7426 = or(_T_7422, _T_7425) @[ifu_mem_ctl.scala 693:81] + node _T_7427 = or(_T_7426, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7428 = bits(_T_7427, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7429 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7428 : @[Reg.scala 28:19] _T_7429 <= _T_7419 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][87] <= _T_7429 @[ifu_mem_ctl.scala 693:41] - node _T_7430 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7431 = eq(_T_7430, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7432 = and(ic_valid_ff, _T_7431) @[ifu_mem_ctl.scala 693:97] - node _T_7433 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7434 = and(_T_7432, _T_7433) @[ifu_mem_ctl.scala 693:122] - node _T_7435 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[ifu_mem_ctl.scala 694:37] - node _T_7436 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_7437 = and(_T_7435, _T_7436) @[ifu_mem_ctl.scala 694:59] - node _T_7438 = eq(perr_ic_index_ff, UInt<7>("h058")) @[ifu_mem_ctl.scala 694:102] - node _T_7439 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_7440 = and(_T_7438, _T_7439) @[ifu_mem_ctl.scala 694:124] - node _T_7441 = or(_T_7437, _T_7440) @[ifu_mem_ctl.scala 694:81] - node _T_7442 = or(_T_7441, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7443 = bits(_T_7442, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][87] <= _T_7429 @[ifu_mem_ctl.scala 692:41] + node _T_7430 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7431 = eq(_T_7430, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7432 = and(ic_valid_ff, _T_7431) @[ifu_mem_ctl.scala 692:97] + node _T_7433 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7434 = and(_T_7432, _T_7433) @[ifu_mem_ctl.scala 692:122] + node _T_7435 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[ifu_mem_ctl.scala 693:37] + node _T_7436 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_7437 = and(_T_7435, _T_7436) @[ifu_mem_ctl.scala 693:59] + node _T_7438 = eq(perr_ic_index_ff, UInt<7>("h058")) @[ifu_mem_ctl.scala 693:102] + node _T_7439 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_7440 = and(_T_7438, _T_7439) @[ifu_mem_ctl.scala 693:124] + node _T_7441 = or(_T_7437, _T_7440) @[ifu_mem_ctl.scala 693:81] + node _T_7442 = or(_T_7441, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7443 = bits(_T_7442, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7444 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7443 : @[Reg.scala 28:19] _T_7444 <= _T_7434 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][88] <= _T_7444 @[ifu_mem_ctl.scala 693:41] - node _T_7445 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7446 = eq(_T_7445, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7447 = and(ic_valid_ff, _T_7446) @[ifu_mem_ctl.scala 693:97] - node _T_7448 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7449 = and(_T_7447, _T_7448) @[ifu_mem_ctl.scala 693:122] - node _T_7450 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[ifu_mem_ctl.scala 694:37] - node _T_7451 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_7452 = and(_T_7450, _T_7451) @[ifu_mem_ctl.scala 694:59] - node _T_7453 = eq(perr_ic_index_ff, UInt<7>("h059")) @[ifu_mem_ctl.scala 694:102] - node _T_7454 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_7455 = and(_T_7453, _T_7454) @[ifu_mem_ctl.scala 694:124] - node _T_7456 = or(_T_7452, _T_7455) @[ifu_mem_ctl.scala 694:81] - node _T_7457 = or(_T_7456, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7458 = bits(_T_7457, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][88] <= _T_7444 @[ifu_mem_ctl.scala 692:41] + node _T_7445 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7446 = eq(_T_7445, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7447 = and(ic_valid_ff, _T_7446) @[ifu_mem_ctl.scala 692:97] + node _T_7448 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7449 = and(_T_7447, _T_7448) @[ifu_mem_ctl.scala 692:122] + node _T_7450 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[ifu_mem_ctl.scala 693:37] + node _T_7451 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_7452 = and(_T_7450, _T_7451) @[ifu_mem_ctl.scala 693:59] + node _T_7453 = eq(perr_ic_index_ff, UInt<7>("h059")) @[ifu_mem_ctl.scala 693:102] + node _T_7454 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_7455 = and(_T_7453, _T_7454) @[ifu_mem_ctl.scala 693:124] + node _T_7456 = or(_T_7452, _T_7455) @[ifu_mem_ctl.scala 693:81] + node _T_7457 = or(_T_7456, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7458 = bits(_T_7457, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7459 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7458 : @[Reg.scala 28:19] _T_7459 <= _T_7449 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][89] <= _T_7459 @[ifu_mem_ctl.scala 693:41] - node _T_7460 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7461 = eq(_T_7460, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7462 = and(ic_valid_ff, _T_7461) @[ifu_mem_ctl.scala 693:97] - node _T_7463 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7464 = and(_T_7462, _T_7463) @[ifu_mem_ctl.scala 693:122] - node _T_7465 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[ifu_mem_ctl.scala 694:37] - node _T_7466 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_7467 = and(_T_7465, _T_7466) @[ifu_mem_ctl.scala 694:59] - node _T_7468 = eq(perr_ic_index_ff, UInt<7>("h05a")) @[ifu_mem_ctl.scala 694:102] - node _T_7469 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_7470 = and(_T_7468, _T_7469) @[ifu_mem_ctl.scala 694:124] - node _T_7471 = or(_T_7467, _T_7470) @[ifu_mem_ctl.scala 694:81] - node _T_7472 = or(_T_7471, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7473 = bits(_T_7472, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][89] <= _T_7459 @[ifu_mem_ctl.scala 692:41] + node _T_7460 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7461 = eq(_T_7460, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7462 = and(ic_valid_ff, _T_7461) @[ifu_mem_ctl.scala 692:97] + node _T_7463 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7464 = and(_T_7462, _T_7463) @[ifu_mem_ctl.scala 692:122] + node _T_7465 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[ifu_mem_ctl.scala 693:37] + node _T_7466 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_7467 = and(_T_7465, _T_7466) @[ifu_mem_ctl.scala 693:59] + node _T_7468 = eq(perr_ic_index_ff, UInt<7>("h05a")) @[ifu_mem_ctl.scala 693:102] + node _T_7469 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_7470 = and(_T_7468, _T_7469) @[ifu_mem_ctl.scala 693:124] + node _T_7471 = or(_T_7467, _T_7470) @[ifu_mem_ctl.scala 693:81] + node _T_7472 = or(_T_7471, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7473 = bits(_T_7472, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7474 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7473 : @[Reg.scala 28:19] _T_7474 <= _T_7464 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][90] <= _T_7474 @[ifu_mem_ctl.scala 693:41] - node _T_7475 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7476 = eq(_T_7475, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7477 = and(ic_valid_ff, _T_7476) @[ifu_mem_ctl.scala 693:97] - node _T_7478 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7479 = and(_T_7477, _T_7478) @[ifu_mem_ctl.scala 693:122] - node _T_7480 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[ifu_mem_ctl.scala 694:37] - node _T_7481 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_7482 = and(_T_7480, _T_7481) @[ifu_mem_ctl.scala 694:59] - node _T_7483 = eq(perr_ic_index_ff, UInt<7>("h05b")) @[ifu_mem_ctl.scala 694:102] - node _T_7484 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_7485 = and(_T_7483, _T_7484) @[ifu_mem_ctl.scala 694:124] - node _T_7486 = or(_T_7482, _T_7485) @[ifu_mem_ctl.scala 694:81] - node _T_7487 = or(_T_7486, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7488 = bits(_T_7487, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][90] <= _T_7474 @[ifu_mem_ctl.scala 692:41] + node _T_7475 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7476 = eq(_T_7475, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7477 = and(ic_valid_ff, _T_7476) @[ifu_mem_ctl.scala 692:97] + node _T_7478 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7479 = and(_T_7477, _T_7478) @[ifu_mem_ctl.scala 692:122] + node _T_7480 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[ifu_mem_ctl.scala 693:37] + node _T_7481 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_7482 = and(_T_7480, _T_7481) @[ifu_mem_ctl.scala 693:59] + node _T_7483 = eq(perr_ic_index_ff, UInt<7>("h05b")) @[ifu_mem_ctl.scala 693:102] + node _T_7484 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_7485 = and(_T_7483, _T_7484) @[ifu_mem_ctl.scala 693:124] + node _T_7486 = or(_T_7482, _T_7485) @[ifu_mem_ctl.scala 693:81] + node _T_7487 = or(_T_7486, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7488 = bits(_T_7487, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7489 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7488 : @[Reg.scala 28:19] _T_7489 <= _T_7479 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][91] <= _T_7489 @[ifu_mem_ctl.scala 693:41] - node _T_7490 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7491 = eq(_T_7490, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7492 = and(ic_valid_ff, _T_7491) @[ifu_mem_ctl.scala 693:97] - node _T_7493 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7494 = and(_T_7492, _T_7493) @[ifu_mem_ctl.scala 693:122] - node _T_7495 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[ifu_mem_ctl.scala 694:37] - node _T_7496 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_7497 = and(_T_7495, _T_7496) @[ifu_mem_ctl.scala 694:59] - node _T_7498 = eq(perr_ic_index_ff, UInt<7>("h05c")) @[ifu_mem_ctl.scala 694:102] - node _T_7499 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_7500 = and(_T_7498, _T_7499) @[ifu_mem_ctl.scala 694:124] - node _T_7501 = or(_T_7497, _T_7500) @[ifu_mem_ctl.scala 694:81] - node _T_7502 = or(_T_7501, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7503 = bits(_T_7502, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][91] <= _T_7489 @[ifu_mem_ctl.scala 692:41] + node _T_7490 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7491 = eq(_T_7490, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7492 = and(ic_valid_ff, _T_7491) @[ifu_mem_ctl.scala 692:97] + node _T_7493 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7494 = and(_T_7492, _T_7493) @[ifu_mem_ctl.scala 692:122] + node _T_7495 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[ifu_mem_ctl.scala 693:37] + node _T_7496 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_7497 = and(_T_7495, _T_7496) @[ifu_mem_ctl.scala 693:59] + node _T_7498 = eq(perr_ic_index_ff, UInt<7>("h05c")) @[ifu_mem_ctl.scala 693:102] + node _T_7499 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_7500 = and(_T_7498, _T_7499) @[ifu_mem_ctl.scala 693:124] + node _T_7501 = or(_T_7497, _T_7500) @[ifu_mem_ctl.scala 693:81] + node _T_7502 = or(_T_7501, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7503 = bits(_T_7502, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7504 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7503 : @[Reg.scala 28:19] _T_7504 <= _T_7494 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][92] <= _T_7504 @[ifu_mem_ctl.scala 693:41] - node _T_7505 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7506 = eq(_T_7505, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7507 = and(ic_valid_ff, _T_7506) @[ifu_mem_ctl.scala 693:97] - node _T_7508 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7509 = and(_T_7507, _T_7508) @[ifu_mem_ctl.scala 693:122] - node _T_7510 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[ifu_mem_ctl.scala 694:37] - node _T_7511 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_7512 = and(_T_7510, _T_7511) @[ifu_mem_ctl.scala 694:59] - node _T_7513 = eq(perr_ic_index_ff, UInt<7>("h05d")) @[ifu_mem_ctl.scala 694:102] - node _T_7514 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_7515 = and(_T_7513, _T_7514) @[ifu_mem_ctl.scala 694:124] - node _T_7516 = or(_T_7512, _T_7515) @[ifu_mem_ctl.scala 694:81] - node _T_7517 = or(_T_7516, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7518 = bits(_T_7517, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][92] <= _T_7504 @[ifu_mem_ctl.scala 692:41] + node _T_7505 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7506 = eq(_T_7505, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7507 = and(ic_valid_ff, _T_7506) @[ifu_mem_ctl.scala 692:97] + node _T_7508 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7509 = and(_T_7507, _T_7508) @[ifu_mem_ctl.scala 692:122] + node _T_7510 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[ifu_mem_ctl.scala 693:37] + node _T_7511 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_7512 = and(_T_7510, _T_7511) @[ifu_mem_ctl.scala 693:59] + node _T_7513 = eq(perr_ic_index_ff, UInt<7>("h05d")) @[ifu_mem_ctl.scala 693:102] + node _T_7514 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_7515 = and(_T_7513, _T_7514) @[ifu_mem_ctl.scala 693:124] + node _T_7516 = or(_T_7512, _T_7515) @[ifu_mem_ctl.scala 693:81] + node _T_7517 = or(_T_7516, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7518 = bits(_T_7517, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7519 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7518 : @[Reg.scala 28:19] _T_7519 <= _T_7509 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][93] <= _T_7519 @[ifu_mem_ctl.scala 693:41] - node _T_7520 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7521 = eq(_T_7520, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7522 = and(ic_valid_ff, _T_7521) @[ifu_mem_ctl.scala 693:97] - node _T_7523 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7524 = and(_T_7522, _T_7523) @[ifu_mem_ctl.scala 693:122] - node _T_7525 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[ifu_mem_ctl.scala 694:37] - node _T_7526 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_7527 = and(_T_7525, _T_7526) @[ifu_mem_ctl.scala 694:59] - node _T_7528 = eq(perr_ic_index_ff, UInt<7>("h05e")) @[ifu_mem_ctl.scala 694:102] - node _T_7529 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_7530 = and(_T_7528, _T_7529) @[ifu_mem_ctl.scala 694:124] - node _T_7531 = or(_T_7527, _T_7530) @[ifu_mem_ctl.scala 694:81] - node _T_7532 = or(_T_7531, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7533 = bits(_T_7532, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][93] <= _T_7519 @[ifu_mem_ctl.scala 692:41] + node _T_7520 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7521 = eq(_T_7520, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7522 = and(ic_valid_ff, _T_7521) @[ifu_mem_ctl.scala 692:97] + node _T_7523 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7524 = and(_T_7522, _T_7523) @[ifu_mem_ctl.scala 692:122] + node _T_7525 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[ifu_mem_ctl.scala 693:37] + node _T_7526 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_7527 = and(_T_7525, _T_7526) @[ifu_mem_ctl.scala 693:59] + node _T_7528 = eq(perr_ic_index_ff, UInt<7>("h05e")) @[ifu_mem_ctl.scala 693:102] + node _T_7529 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_7530 = and(_T_7528, _T_7529) @[ifu_mem_ctl.scala 693:124] + node _T_7531 = or(_T_7527, _T_7530) @[ifu_mem_ctl.scala 693:81] + node _T_7532 = or(_T_7531, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7533 = bits(_T_7532, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7534 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7533 : @[Reg.scala 28:19] _T_7534 <= _T_7524 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][94] <= _T_7534 @[ifu_mem_ctl.scala 693:41] - node _T_7535 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7536 = eq(_T_7535, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7537 = and(ic_valid_ff, _T_7536) @[ifu_mem_ctl.scala 693:97] - node _T_7538 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7539 = and(_T_7537, _T_7538) @[ifu_mem_ctl.scala 693:122] - node _T_7540 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[ifu_mem_ctl.scala 694:37] - node _T_7541 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_7542 = and(_T_7540, _T_7541) @[ifu_mem_ctl.scala 694:59] - node _T_7543 = eq(perr_ic_index_ff, UInt<7>("h05f")) @[ifu_mem_ctl.scala 694:102] - node _T_7544 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_7545 = and(_T_7543, _T_7544) @[ifu_mem_ctl.scala 694:124] - node _T_7546 = or(_T_7542, _T_7545) @[ifu_mem_ctl.scala 694:81] - node _T_7547 = or(_T_7546, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7548 = bits(_T_7547, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][94] <= _T_7534 @[ifu_mem_ctl.scala 692:41] + node _T_7535 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7536 = eq(_T_7535, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7537 = and(ic_valid_ff, _T_7536) @[ifu_mem_ctl.scala 692:97] + node _T_7538 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7539 = and(_T_7537, _T_7538) @[ifu_mem_ctl.scala 692:122] + node _T_7540 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[ifu_mem_ctl.scala 693:37] + node _T_7541 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_7542 = and(_T_7540, _T_7541) @[ifu_mem_ctl.scala 693:59] + node _T_7543 = eq(perr_ic_index_ff, UInt<7>("h05f")) @[ifu_mem_ctl.scala 693:102] + node _T_7544 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_7545 = and(_T_7543, _T_7544) @[ifu_mem_ctl.scala 693:124] + node _T_7546 = or(_T_7542, _T_7545) @[ifu_mem_ctl.scala 693:81] + node _T_7547 = or(_T_7546, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7548 = bits(_T_7547, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7549 : UInt<1>, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7548 : @[Reg.scala 28:19] _T_7549 <= _T_7539 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][95] <= _T_7549 @[ifu_mem_ctl.scala 693:41] - node _T_7550 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7551 = eq(_T_7550, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7552 = and(ic_valid_ff, _T_7551) @[ifu_mem_ctl.scala 693:97] - node _T_7553 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7554 = and(_T_7552, _T_7553) @[ifu_mem_ctl.scala 693:122] - node _T_7555 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[ifu_mem_ctl.scala 694:37] - node _T_7556 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7557 = and(_T_7555, _T_7556) @[ifu_mem_ctl.scala 694:59] - node _T_7558 = eq(perr_ic_index_ff, UInt<7>("h040")) @[ifu_mem_ctl.scala 694:102] - node _T_7559 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7560 = and(_T_7558, _T_7559) @[ifu_mem_ctl.scala 694:124] - node _T_7561 = or(_T_7557, _T_7560) @[ifu_mem_ctl.scala 694:81] - node _T_7562 = or(_T_7561, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7563 = bits(_T_7562, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][95] <= _T_7549 @[ifu_mem_ctl.scala 692:41] + node _T_7550 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7551 = eq(_T_7550, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7552 = and(ic_valid_ff, _T_7551) @[ifu_mem_ctl.scala 692:97] + node _T_7553 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7554 = and(_T_7552, _T_7553) @[ifu_mem_ctl.scala 692:122] + node _T_7555 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[ifu_mem_ctl.scala 693:37] + node _T_7556 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7557 = and(_T_7555, _T_7556) @[ifu_mem_ctl.scala 693:59] + node _T_7558 = eq(perr_ic_index_ff, UInt<7>("h040")) @[ifu_mem_ctl.scala 693:102] + node _T_7559 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7560 = and(_T_7558, _T_7559) @[ifu_mem_ctl.scala 693:124] + node _T_7561 = or(_T_7557, _T_7560) @[ifu_mem_ctl.scala 693:81] + node _T_7562 = or(_T_7561, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7563 = bits(_T_7562, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7564 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7563 : @[Reg.scala 28:19] _T_7564 <= _T_7554 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][64] <= _T_7564 @[ifu_mem_ctl.scala 693:41] - node _T_7565 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7566 = eq(_T_7565, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7567 = and(ic_valid_ff, _T_7566) @[ifu_mem_ctl.scala 693:97] - node _T_7568 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7569 = and(_T_7567, _T_7568) @[ifu_mem_ctl.scala 693:122] - node _T_7570 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[ifu_mem_ctl.scala 694:37] - node _T_7571 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7572 = and(_T_7570, _T_7571) @[ifu_mem_ctl.scala 694:59] - node _T_7573 = eq(perr_ic_index_ff, UInt<7>("h041")) @[ifu_mem_ctl.scala 694:102] - node _T_7574 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7575 = and(_T_7573, _T_7574) @[ifu_mem_ctl.scala 694:124] - node _T_7576 = or(_T_7572, _T_7575) @[ifu_mem_ctl.scala 694:81] - node _T_7577 = or(_T_7576, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7578 = bits(_T_7577, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][64] <= _T_7564 @[ifu_mem_ctl.scala 692:41] + node _T_7565 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7566 = eq(_T_7565, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7567 = and(ic_valid_ff, _T_7566) @[ifu_mem_ctl.scala 692:97] + node _T_7568 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7569 = and(_T_7567, _T_7568) @[ifu_mem_ctl.scala 692:122] + node _T_7570 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[ifu_mem_ctl.scala 693:37] + node _T_7571 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7572 = and(_T_7570, _T_7571) @[ifu_mem_ctl.scala 693:59] + node _T_7573 = eq(perr_ic_index_ff, UInt<7>("h041")) @[ifu_mem_ctl.scala 693:102] + node _T_7574 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7575 = and(_T_7573, _T_7574) @[ifu_mem_ctl.scala 693:124] + node _T_7576 = or(_T_7572, _T_7575) @[ifu_mem_ctl.scala 693:81] + node _T_7577 = or(_T_7576, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7578 = bits(_T_7577, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7579 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7578 : @[Reg.scala 28:19] _T_7579 <= _T_7569 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][65] <= _T_7579 @[ifu_mem_ctl.scala 693:41] - node _T_7580 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7581 = eq(_T_7580, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7582 = and(ic_valid_ff, _T_7581) @[ifu_mem_ctl.scala 693:97] - node _T_7583 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7584 = and(_T_7582, _T_7583) @[ifu_mem_ctl.scala 693:122] - node _T_7585 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[ifu_mem_ctl.scala 694:37] - node _T_7586 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7587 = and(_T_7585, _T_7586) @[ifu_mem_ctl.scala 694:59] - node _T_7588 = eq(perr_ic_index_ff, UInt<7>("h042")) @[ifu_mem_ctl.scala 694:102] - node _T_7589 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7590 = and(_T_7588, _T_7589) @[ifu_mem_ctl.scala 694:124] - node _T_7591 = or(_T_7587, _T_7590) @[ifu_mem_ctl.scala 694:81] - node _T_7592 = or(_T_7591, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7593 = bits(_T_7592, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][65] <= _T_7579 @[ifu_mem_ctl.scala 692:41] + node _T_7580 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7581 = eq(_T_7580, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7582 = and(ic_valid_ff, _T_7581) @[ifu_mem_ctl.scala 692:97] + node _T_7583 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7584 = and(_T_7582, _T_7583) @[ifu_mem_ctl.scala 692:122] + node _T_7585 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[ifu_mem_ctl.scala 693:37] + node _T_7586 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7587 = and(_T_7585, _T_7586) @[ifu_mem_ctl.scala 693:59] + node _T_7588 = eq(perr_ic_index_ff, UInt<7>("h042")) @[ifu_mem_ctl.scala 693:102] + node _T_7589 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7590 = and(_T_7588, _T_7589) @[ifu_mem_ctl.scala 693:124] + node _T_7591 = or(_T_7587, _T_7590) @[ifu_mem_ctl.scala 693:81] + node _T_7592 = or(_T_7591, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7593 = bits(_T_7592, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7594 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7593 : @[Reg.scala 28:19] _T_7594 <= _T_7584 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][66] <= _T_7594 @[ifu_mem_ctl.scala 693:41] - node _T_7595 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7596 = eq(_T_7595, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7597 = and(ic_valid_ff, _T_7596) @[ifu_mem_ctl.scala 693:97] - node _T_7598 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7599 = and(_T_7597, _T_7598) @[ifu_mem_ctl.scala 693:122] - node _T_7600 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[ifu_mem_ctl.scala 694:37] - node _T_7601 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7602 = and(_T_7600, _T_7601) @[ifu_mem_ctl.scala 694:59] - node _T_7603 = eq(perr_ic_index_ff, UInt<7>("h043")) @[ifu_mem_ctl.scala 694:102] - node _T_7604 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7605 = and(_T_7603, _T_7604) @[ifu_mem_ctl.scala 694:124] - node _T_7606 = or(_T_7602, _T_7605) @[ifu_mem_ctl.scala 694:81] - node _T_7607 = or(_T_7606, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7608 = bits(_T_7607, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][66] <= _T_7594 @[ifu_mem_ctl.scala 692:41] + node _T_7595 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7596 = eq(_T_7595, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7597 = and(ic_valid_ff, _T_7596) @[ifu_mem_ctl.scala 692:97] + node _T_7598 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7599 = and(_T_7597, _T_7598) @[ifu_mem_ctl.scala 692:122] + node _T_7600 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[ifu_mem_ctl.scala 693:37] + node _T_7601 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7602 = and(_T_7600, _T_7601) @[ifu_mem_ctl.scala 693:59] + node _T_7603 = eq(perr_ic_index_ff, UInt<7>("h043")) @[ifu_mem_ctl.scala 693:102] + node _T_7604 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7605 = and(_T_7603, _T_7604) @[ifu_mem_ctl.scala 693:124] + node _T_7606 = or(_T_7602, _T_7605) @[ifu_mem_ctl.scala 693:81] + node _T_7607 = or(_T_7606, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7608 = bits(_T_7607, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7609 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7608 : @[Reg.scala 28:19] _T_7609 <= _T_7599 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][67] <= _T_7609 @[ifu_mem_ctl.scala 693:41] - node _T_7610 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7611 = eq(_T_7610, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7612 = and(ic_valid_ff, _T_7611) @[ifu_mem_ctl.scala 693:97] - node _T_7613 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7614 = and(_T_7612, _T_7613) @[ifu_mem_ctl.scala 693:122] - node _T_7615 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[ifu_mem_ctl.scala 694:37] - node _T_7616 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7617 = and(_T_7615, _T_7616) @[ifu_mem_ctl.scala 694:59] - node _T_7618 = eq(perr_ic_index_ff, UInt<7>("h044")) @[ifu_mem_ctl.scala 694:102] - node _T_7619 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7620 = and(_T_7618, _T_7619) @[ifu_mem_ctl.scala 694:124] - node _T_7621 = or(_T_7617, _T_7620) @[ifu_mem_ctl.scala 694:81] - node _T_7622 = or(_T_7621, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7623 = bits(_T_7622, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][67] <= _T_7609 @[ifu_mem_ctl.scala 692:41] + node _T_7610 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7611 = eq(_T_7610, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7612 = and(ic_valid_ff, _T_7611) @[ifu_mem_ctl.scala 692:97] + node _T_7613 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7614 = and(_T_7612, _T_7613) @[ifu_mem_ctl.scala 692:122] + node _T_7615 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[ifu_mem_ctl.scala 693:37] + node _T_7616 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7617 = and(_T_7615, _T_7616) @[ifu_mem_ctl.scala 693:59] + node _T_7618 = eq(perr_ic_index_ff, UInt<7>("h044")) @[ifu_mem_ctl.scala 693:102] + node _T_7619 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7620 = and(_T_7618, _T_7619) @[ifu_mem_ctl.scala 693:124] + node _T_7621 = or(_T_7617, _T_7620) @[ifu_mem_ctl.scala 693:81] + node _T_7622 = or(_T_7621, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7623 = bits(_T_7622, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7624 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7623 : @[Reg.scala 28:19] _T_7624 <= _T_7614 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][68] <= _T_7624 @[ifu_mem_ctl.scala 693:41] - node _T_7625 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7626 = eq(_T_7625, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7627 = and(ic_valid_ff, _T_7626) @[ifu_mem_ctl.scala 693:97] - node _T_7628 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7629 = and(_T_7627, _T_7628) @[ifu_mem_ctl.scala 693:122] - node _T_7630 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[ifu_mem_ctl.scala 694:37] - node _T_7631 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7632 = and(_T_7630, _T_7631) @[ifu_mem_ctl.scala 694:59] - node _T_7633 = eq(perr_ic_index_ff, UInt<7>("h045")) @[ifu_mem_ctl.scala 694:102] - node _T_7634 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7635 = and(_T_7633, _T_7634) @[ifu_mem_ctl.scala 694:124] - node _T_7636 = or(_T_7632, _T_7635) @[ifu_mem_ctl.scala 694:81] - node _T_7637 = or(_T_7636, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7638 = bits(_T_7637, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][68] <= _T_7624 @[ifu_mem_ctl.scala 692:41] + node _T_7625 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7626 = eq(_T_7625, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7627 = and(ic_valid_ff, _T_7626) @[ifu_mem_ctl.scala 692:97] + node _T_7628 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7629 = and(_T_7627, _T_7628) @[ifu_mem_ctl.scala 692:122] + node _T_7630 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[ifu_mem_ctl.scala 693:37] + node _T_7631 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7632 = and(_T_7630, _T_7631) @[ifu_mem_ctl.scala 693:59] + node _T_7633 = eq(perr_ic_index_ff, UInt<7>("h045")) @[ifu_mem_ctl.scala 693:102] + node _T_7634 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7635 = and(_T_7633, _T_7634) @[ifu_mem_ctl.scala 693:124] + node _T_7636 = or(_T_7632, _T_7635) @[ifu_mem_ctl.scala 693:81] + node _T_7637 = or(_T_7636, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7638 = bits(_T_7637, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7639 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7638 : @[Reg.scala 28:19] _T_7639 <= _T_7629 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][69] <= _T_7639 @[ifu_mem_ctl.scala 693:41] - node _T_7640 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7641 = eq(_T_7640, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7642 = and(ic_valid_ff, _T_7641) @[ifu_mem_ctl.scala 693:97] - node _T_7643 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7644 = and(_T_7642, _T_7643) @[ifu_mem_ctl.scala 693:122] - node _T_7645 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[ifu_mem_ctl.scala 694:37] - node _T_7646 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7647 = and(_T_7645, _T_7646) @[ifu_mem_ctl.scala 694:59] - node _T_7648 = eq(perr_ic_index_ff, UInt<7>("h046")) @[ifu_mem_ctl.scala 694:102] - node _T_7649 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7650 = and(_T_7648, _T_7649) @[ifu_mem_ctl.scala 694:124] - node _T_7651 = or(_T_7647, _T_7650) @[ifu_mem_ctl.scala 694:81] - node _T_7652 = or(_T_7651, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7653 = bits(_T_7652, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][69] <= _T_7639 @[ifu_mem_ctl.scala 692:41] + node _T_7640 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7641 = eq(_T_7640, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7642 = and(ic_valid_ff, _T_7641) @[ifu_mem_ctl.scala 692:97] + node _T_7643 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7644 = and(_T_7642, _T_7643) @[ifu_mem_ctl.scala 692:122] + node _T_7645 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[ifu_mem_ctl.scala 693:37] + node _T_7646 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7647 = and(_T_7645, _T_7646) @[ifu_mem_ctl.scala 693:59] + node _T_7648 = eq(perr_ic_index_ff, UInt<7>("h046")) @[ifu_mem_ctl.scala 693:102] + node _T_7649 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7650 = and(_T_7648, _T_7649) @[ifu_mem_ctl.scala 693:124] + node _T_7651 = or(_T_7647, _T_7650) @[ifu_mem_ctl.scala 693:81] + node _T_7652 = or(_T_7651, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7653 = bits(_T_7652, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7654 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7653 : @[Reg.scala 28:19] _T_7654 <= _T_7644 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][70] <= _T_7654 @[ifu_mem_ctl.scala 693:41] - node _T_7655 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7656 = eq(_T_7655, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7657 = and(ic_valid_ff, _T_7656) @[ifu_mem_ctl.scala 693:97] - node _T_7658 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7659 = and(_T_7657, _T_7658) @[ifu_mem_ctl.scala 693:122] - node _T_7660 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[ifu_mem_ctl.scala 694:37] - node _T_7661 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7662 = and(_T_7660, _T_7661) @[ifu_mem_ctl.scala 694:59] - node _T_7663 = eq(perr_ic_index_ff, UInt<7>("h047")) @[ifu_mem_ctl.scala 694:102] - node _T_7664 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7665 = and(_T_7663, _T_7664) @[ifu_mem_ctl.scala 694:124] - node _T_7666 = or(_T_7662, _T_7665) @[ifu_mem_ctl.scala 694:81] - node _T_7667 = or(_T_7666, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7668 = bits(_T_7667, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][70] <= _T_7654 @[ifu_mem_ctl.scala 692:41] + node _T_7655 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7656 = eq(_T_7655, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7657 = and(ic_valid_ff, _T_7656) @[ifu_mem_ctl.scala 692:97] + node _T_7658 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7659 = and(_T_7657, _T_7658) @[ifu_mem_ctl.scala 692:122] + node _T_7660 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[ifu_mem_ctl.scala 693:37] + node _T_7661 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7662 = and(_T_7660, _T_7661) @[ifu_mem_ctl.scala 693:59] + node _T_7663 = eq(perr_ic_index_ff, UInt<7>("h047")) @[ifu_mem_ctl.scala 693:102] + node _T_7664 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7665 = and(_T_7663, _T_7664) @[ifu_mem_ctl.scala 693:124] + node _T_7666 = or(_T_7662, _T_7665) @[ifu_mem_ctl.scala 693:81] + node _T_7667 = or(_T_7666, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7668 = bits(_T_7667, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7669 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7668 : @[Reg.scala 28:19] _T_7669 <= _T_7659 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][71] <= _T_7669 @[ifu_mem_ctl.scala 693:41] - node _T_7670 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7671 = eq(_T_7670, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7672 = and(ic_valid_ff, _T_7671) @[ifu_mem_ctl.scala 693:97] - node _T_7673 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7674 = and(_T_7672, _T_7673) @[ifu_mem_ctl.scala 693:122] - node _T_7675 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[ifu_mem_ctl.scala 694:37] - node _T_7676 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7677 = and(_T_7675, _T_7676) @[ifu_mem_ctl.scala 694:59] - node _T_7678 = eq(perr_ic_index_ff, UInt<7>("h048")) @[ifu_mem_ctl.scala 694:102] - node _T_7679 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7680 = and(_T_7678, _T_7679) @[ifu_mem_ctl.scala 694:124] - node _T_7681 = or(_T_7677, _T_7680) @[ifu_mem_ctl.scala 694:81] - node _T_7682 = or(_T_7681, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7683 = bits(_T_7682, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][71] <= _T_7669 @[ifu_mem_ctl.scala 692:41] + node _T_7670 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7671 = eq(_T_7670, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7672 = and(ic_valid_ff, _T_7671) @[ifu_mem_ctl.scala 692:97] + node _T_7673 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7674 = and(_T_7672, _T_7673) @[ifu_mem_ctl.scala 692:122] + node _T_7675 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[ifu_mem_ctl.scala 693:37] + node _T_7676 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7677 = and(_T_7675, _T_7676) @[ifu_mem_ctl.scala 693:59] + node _T_7678 = eq(perr_ic_index_ff, UInt<7>("h048")) @[ifu_mem_ctl.scala 693:102] + node _T_7679 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7680 = and(_T_7678, _T_7679) @[ifu_mem_ctl.scala 693:124] + node _T_7681 = or(_T_7677, _T_7680) @[ifu_mem_ctl.scala 693:81] + node _T_7682 = or(_T_7681, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7683 = bits(_T_7682, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7684 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7683 : @[Reg.scala 28:19] _T_7684 <= _T_7674 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][72] <= _T_7684 @[ifu_mem_ctl.scala 693:41] - node _T_7685 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7686 = eq(_T_7685, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7687 = and(ic_valid_ff, _T_7686) @[ifu_mem_ctl.scala 693:97] - node _T_7688 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7689 = and(_T_7687, _T_7688) @[ifu_mem_ctl.scala 693:122] - node _T_7690 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[ifu_mem_ctl.scala 694:37] - node _T_7691 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7692 = and(_T_7690, _T_7691) @[ifu_mem_ctl.scala 694:59] - node _T_7693 = eq(perr_ic_index_ff, UInt<7>("h049")) @[ifu_mem_ctl.scala 694:102] - node _T_7694 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7695 = and(_T_7693, _T_7694) @[ifu_mem_ctl.scala 694:124] - node _T_7696 = or(_T_7692, _T_7695) @[ifu_mem_ctl.scala 694:81] - node _T_7697 = or(_T_7696, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7698 = bits(_T_7697, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][72] <= _T_7684 @[ifu_mem_ctl.scala 692:41] + node _T_7685 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7686 = eq(_T_7685, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7687 = and(ic_valid_ff, _T_7686) @[ifu_mem_ctl.scala 692:97] + node _T_7688 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7689 = and(_T_7687, _T_7688) @[ifu_mem_ctl.scala 692:122] + node _T_7690 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[ifu_mem_ctl.scala 693:37] + node _T_7691 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7692 = and(_T_7690, _T_7691) @[ifu_mem_ctl.scala 693:59] + node _T_7693 = eq(perr_ic_index_ff, UInt<7>("h049")) @[ifu_mem_ctl.scala 693:102] + node _T_7694 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7695 = and(_T_7693, _T_7694) @[ifu_mem_ctl.scala 693:124] + node _T_7696 = or(_T_7692, _T_7695) @[ifu_mem_ctl.scala 693:81] + node _T_7697 = or(_T_7696, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7698 = bits(_T_7697, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7699 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7698 : @[Reg.scala 28:19] _T_7699 <= _T_7689 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][73] <= _T_7699 @[ifu_mem_ctl.scala 693:41] - node _T_7700 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7701 = eq(_T_7700, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7702 = and(ic_valid_ff, _T_7701) @[ifu_mem_ctl.scala 693:97] - node _T_7703 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7704 = and(_T_7702, _T_7703) @[ifu_mem_ctl.scala 693:122] - node _T_7705 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[ifu_mem_ctl.scala 694:37] - node _T_7706 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7707 = and(_T_7705, _T_7706) @[ifu_mem_ctl.scala 694:59] - node _T_7708 = eq(perr_ic_index_ff, UInt<7>("h04a")) @[ifu_mem_ctl.scala 694:102] - node _T_7709 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7710 = and(_T_7708, _T_7709) @[ifu_mem_ctl.scala 694:124] - node _T_7711 = or(_T_7707, _T_7710) @[ifu_mem_ctl.scala 694:81] - node _T_7712 = or(_T_7711, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7713 = bits(_T_7712, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][73] <= _T_7699 @[ifu_mem_ctl.scala 692:41] + node _T_7700 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7701 = eq(_T_7700, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7702 = and(ic_valid_ff, _T_7701) @[ifu_mem_ctl.scala 692:97] + node _T_7703 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7704 = and(_T_7702, _T_7703) @[ifu_mem_ctl.scala 692:122] + node _T_7705 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[ifu_mem_ctl.scala 693:37] + node _T_7706 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7707 = and(_T_7705, _T_7706) @[ifu_mem_ctl.scala 693:59] + node _T_7708 = eq(perr_ic_index_ff, UInt<7>("h04a")) @[ifu_mem_ctl.scala 693:102] + node _T_7709 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7710 = and(_T_7708, _T_7709) @[ifu_mem_ctl.scala 693:124] + node _T_7711 = or(_T_7707, _T_7710) @[ifu_mem_ctl.scala 693:81] + node _T_7712 = or(_T_7711, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7713 = bits(_T_7712, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7714 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7713 : @[Reg.scala 28:19] _T_7714 <= _T_7704 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][74] <= _T_7714 @[ifu_mem_ctl.scala 693:41] - node _T_7715 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7716 = eq(_T_7715, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7717 = and(ic_valid_ff, _T_7716) @[ifu_mem_ctl.scala 693:97] - node _T_7718 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7719 = and(_T_7717, _T_7718) @[ifu_mem_ctl.scala 693:122] - node _T_7720 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[ifu_mem_ctl.scala 694:37] - node _T_7721 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7722 = and(_T_7720, _T_7721) @[ifu_mem_ctl.scala 694:59] - node _T_7723 = eq(perr_ic_index_ff, UInt<7>("h04b")) @[ifu_mem_ctl.scala 694:102] - node _T_7724 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7725 = and(_T_7723, _T_7724) @[ifu_mem_ctl.scala 694:124] - node _T_7726 = or(_T_7722, _T_7725) @[ifu_mem_ctl.scala 694:81] - node _T_7727 = or(_T_7726, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7728 = bits(_T_7727, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][74] <= _T_7714 @[ifu_mem_ctl.scala 692:41] + node _T_7715 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7716 = eq(_T_7715, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7717 = and(ic_valid_ff, _T_7716) @[ifu_mem_ctl.scala 692:97] + node _T_7718 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7719 = and(_T_7717, _T_7718) @[ifu_mem_ctl.scala 692:122] + node _T_7720 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[ifu_mem_ctl.scala 693:37] + node _T_7721 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7722 = and(_T_7720, _T_7721) @[ifu_mem_ctl.scala 693:59] + node _T_7723 = eq(perr_ic_index_ff, UInt<7>("h04b")) @[ifu_mem_ctl.scala 693:102] + node _T_7724 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7725 = and(_T_7723, _T_7724) @[ifu_mem_ctl.scala 693:124] + node _T_7726 = or(_T_7722, _T_7725) @[ifu_mem_ctl.scala 693:81] + node _T_7727 = or(_T_7726, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7728 = bits(_T_7727, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7729 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7728 : @[Reg.scala 28:19] _T_7729 <= _T_7719 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][75] <= _T_7729 @[ifu_mem_ctl.scala 693:41] - node _T_7730 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7731 = eq(_T_7730, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7732 = and(ic_valid_ff, _T_7731) @[ifu_mem_ctl.scala 693:97] - node _T_7733 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7734 = and(_T_7732, _T_7733) @[ifu_mem_ctl.scala 693:122] - node _T_7735 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[ifu_mem_ctl.scala 694:37] - node _T_7736 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7737 = and(_T_7735, _T_7736) @[ifu_mem_ctl.scala 694:59] - node _T_7738 = eq(perr_ic_index_ff, UInt<7>("h04c")) @[ifu_mem_ctl.scala 694:102] - node _T_7739 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7740 = and(_T_7738, _T_7739) @[ifu_mem_ctl.scala 694:124] - node _T_7741 = or(_T_7737, _T_7740) @[ifu_mem_ctl.scala 694:81] - node _T_7742 = or(_T_7741, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7743 = bits(_T_7742, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][75] <= _T_7729 @[ifu_mem_ctl.scala 692:41] + node _T_7730 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7731 = eq(_T_7730, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7732 = and(ic_valid_ff, _T_7731) @[ifu_mem_ctl.scala 692:97] + node _T_7733 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7734 = and(_T_7732, _T_7733) @[ifu_mem_ctl.scala 692:122] + node _T_7735 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[ifu_mem_ctl.scala 693:37] + node _T_7736 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7737 = and(_T_7735, _T_7736) @[ifu_mem_ctl.scala 693:59] + node _T_7738 = eq(perr_ic_index_ff, UInt<7>("h04c")) @[ifu_mem_ctl.scala 693:102] + node _T_7739 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7740 = and(_T_7738, _T_7739) @[ifu_mem_ctl.scala 693:124] + node _T_7741 = or(_T_7737, _T_7740) @[ifu_mem_ctl.scala 693:81] + node _T_7742 = or(_T_7741, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7743 = bits(_T_7742, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7744 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7743 : @[Reg.scala 28:19] _T_7744 <= _T_7734 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][76] <= _T_7744 @[ifu_mem_ctl.scala 693:41] - node _T_7745 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7746 = eq(_T_7745, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7747 = and(ic_valid_ff, _T_7746) @[ifu_mem_ctl.scala 693:97] - node _T_7748 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7749 = and(_T_7747, _T_7748) @[ifu_mem_ctl.scala 693:122] - node _T_7750 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[ifu_mem_ctl.scala 694:37] - node _T_7751 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7752 = and(_T_7750, _T_7751) @[ifu_mem_ctl.scala 694:59] - node _T_7753 = eq(perr_ic_index_ff, UInt<7>("h04d")) @[ifu_mem_ctl.scala 694:102] - node _T_7754 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7755 = and(_T_7753, _T_7754) @[ifu_mem_ctl.scala 694:124] - node _T_7756 = or(_T_7752, _T_7755) @[ifu_mem_ctl.scala 694:81] - node _T_7757 = or(_T_7756, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7758 = bits(_T_7757, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][76] <= _T_7744 @[ifu_mem_ctl.scala 692:41] + node _T_7745 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7746 = eq(_T_7745, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7747 = and(ic_valid_ff, _T_7746) @[ifu_mem_ctl.scala 692:97] + node _T_7748 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7749 = and(_T_7747, _T_7748) @[ifu_mem_ctl.scala 692:122] + node _T_7750 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[ifu_mem_ctl.scala 693:37] + node _T_7751 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7752 = and(_T_7750, _T_7751) @[ifu_mem_ctl.scala 693:59] + node _T_7753 = eq(perr_ic_index_ff, UInt<7>("h04d")) @[ifu_mem_ctl.scala 693:102] + node _T_7754 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7755 = and(_T_7753, _T_7754) @[ifu_mem_ctl.scala 693:124] + node _T_7756 = or(_T_7752, _T_7755) @[ifu_mem_ctl.scala 693:81] + node _T_7757 = or(_T_7756, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7758 = bits(_T_7757, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7759 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7758 : @[Reg.scala 28:19] _T_7759 <= _T_7749 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][77] <= _T_7759 @[ifu_mem_ctl.scala 693:41] - node _T_7760 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7761 = eq(_T_7760, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7762 = and(ic_valid_ff, _T_7761) @[ifu_mem_ctl.scala 693:97] - node _T_7763 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7764 = and(_T_7762, _T_7763) @[ifu_mem_ctl.scala 693:122] - node _T_7765 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[ifu_mem_ctl.scala 694:37] - node _T_7766 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7767 = and(_T_7765, _T_7766) @[ifu_mem_ctl.scala 694:59] - node _T_7768 = eq(perr_ic_index_ff, UInt<7>("h04e")) @[ifu_mem_ctl.scala 694:102] - node _T_7769 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7770 = and(_T_7768, _T_7769) @[ifu_mem_ctl.scala 694:124] - node _T_7771 = or(_T_7767, _T_7770) @[ifu_mem_ctl.scala 694:81] - node _T_7772 = or(_T_7771, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7773 = bits(_T_7772, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][77] <= _T_7759 @[ifu_mem_ctl.scala 692:41] + node _T_7760 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7761 = eq(_T_7760, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7762 = and(ic_valid_ff, _T_7761) @[ifu_mem_ctl.scala 692:97] + node _T_7763 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7764 = and(_T_7762, _T_7763) @[ifu_mem_ctl.scala 692:122] + node _T_7765 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[ifu_mem_ctl.scala 693:37] + node _T_7766 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7767 = and(_T_7765, _T_7766) @[ifu_mem_ctl.scala 693:59] + node _T_7768 = eq(perr_ic_index_ff, UInt<7>("h04e")) @[ifu_mem_ctl.scala 693:102] + node _T_7769 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7770 = and(_T_7768, _T_7769) @[ifu_mem_ctl.scala 693:124] + node _T_7771 = or(_T_7767, _T_7770) @[ifu_mem_ctl.scala 693:81] + node _T_7772 = or(_T_7771, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7773 = bits(_T_7772, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7774 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7773 : @[Reg.scala 28:19] _T_7774 <= _T_7764 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][78] <= _T_7774 @[ifu_mem_ctl.scala 693:41] - node _T_7775 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7776 = eq(_T_7775, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7777 = and(ic_valid_ff, _T_7776) @[ifu_mem_ctl.scala 693:97] - node _T_7778 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7779 = and(_T_7777, _T_7778) @[ifu_mem_ctl.scala 693:122] - node _T_7780 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[ifu_mem_ctl.scala 694:37] - node _T_7781 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7782 = and(_T_7780, _T_7781) @[ifu_mem_ctl.scala 694:59] - node _T_7783 = eq(perr_ic_index_ff, UInt<7>("h04f")) @[ifu_mem_ctl.scala 694:102] - node _T_7784 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7785 = and(_T_7783, _T_7784) @[ifu_mem_ctl.scala 694:124] - node _T_7786 = or(_T_7782, _T_7785) @[ifu_mem_ctl.scala 694:81] - node _T_7787 = or(_T_7786, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7788 = bits(_T_7787, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][78] <= _T_7774 @[ifu_mem_ctl.scala 692:41] + node _T_7775 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7776 = eq(_T_7775, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7777 = and(ic_valid_ff, _T_7776) @[ifu_mem_ctl.scala 692:97] + node _T_7778 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7779 = and(_T_7777, _T_7778) @[ifu_mem_ctl.scala 692:122] + node _T_7780 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[ifu_mem_ctl.scala 693:37] + node _T_7781 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7782 = and(_T_7780, _T_7781) @[ifu_mem_ctl.scala 693:59] + node _T_7783 = eq(perr_ic_index_ff, UInt<7>("h04f")) @[ifu_mem_ctl.scala 693:102] + node _T_7784 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7785 = and(_T_7783, _T_7784) @[ifu_mem_ctl.scala 693:124] + node _T_7786 = or(_T_7782, _T_7785) @[ifu_mem_ctl.scala 693:81] + node _T_7787 = or(_T_7786, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7788 = bits(_T_7787, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7789 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7788 : @[Reg.scala 28:19] _T_7789 <= _T_7779 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][79] <= _T_7789 @[ifu_mem_ctl.scala 693:41] - node _T_7790 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7791 = eq(_T_7790, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7792 = and(ic_valid_ff, _T_7791) @[ifu_mem_ctl.scala 693:97] - node _T_7793 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7794 = and(_T_7792, _T_7793) @[ifu_mem_ctl.scala 693:122] - node _T_7795 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[ifu_mem_ctl.scala 694:37] - node _T_7796 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7797 = and(_T_7795, _T_7796) @[ifu_mem_ctl.scala 694:59] - node _T_7798 = eq(perr_ic_index_ff, UInt<7>("h050")) @[ifu_mem_ctl.scala 694:102] - node _T_7799 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7800 = and(_T_7798, _T_7799) @[ifu_mem_ctl.scala 694:124] - node _T_7801 = or(_T_7797, _T_7800) @[ifu_mem_ctl.scala 694:81] - node _T_7802 = or(_T_7801, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7803 = bits(_T_7802, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][79] <= _T_7789 @[ifu_mem_ctl.scala 692:41] + node _T_7790 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7791 = eq(_T_7790, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7792 = and(ic_valid_ff, _T_7791) @[ifu_mem_ctl.scala 692:97] + node _T_7793 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7794 = and(_T_7792, _T_7793) @[ifu_mem_ctl.scala 692:122] + node _T_7795 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[ifu_mem_ctl.scala 693:37] + node _T_7796 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7797 = and(_T_7795, _T_7796) @[ifu_mem_ctl.scala 693:59] + node _T_7798 = eq(perr_ic_index_ff, UInt<7>("h050")) @[ifu_mem_ctl.scala 693:102] + node _T_7799 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7800 = and(_T_7798, _T_7799) @[ifu_mem_ctl.scala 693:124] + node _T_7801 = or(_T_7797, _T_7800) @[ifu_mem_ctl.scala 693:81] + node _T_7802 = or(_T_7801, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7803 = bits(_T_7802, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7804 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7803 : @[Reg.scala 28:19] _T_7804 <= _T_7794 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][80] <= _T_7804 @[ifu_mem_ctl.scala 693:41] - node _T_7805 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7806 = eq(_T_7805, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7807 = and(ic_valid_ff, _T_7806) @[ifu_mem_ctl.scala 693:97] - node _T_7808 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7809 = and(_T_7807, _T_7808) @[ifu_mem_ctl.scala 693:122] - node _T_7810 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[ifu_mem_ctl.scala 694:37] - node _T_7811 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7812 = and(_T_7810, _T_7811) @[ifu_mem_ctl.scala 694:59] - node _T_7813 = eq(perr_ic_index_ff, UInt<7>("h051")) @[ifu_mem_ctl.scala 694:102] - node _T_7814 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7815 = and(_T_7813, _T_7814) @[ifu_mem_ctl.scala 694:124] - node _T_7816 = or(_T_7812, _T_7815) @[ifu_mem_ctl.scala 694:81] - node _T_7817 = or(_T_7816, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7818 = bits(_T_7817, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][80] <= _T_7804 @[ifu_mem_ctl.scala 692:41] + node _T_7805 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7806 = eq(_T_7805, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7807 = and(ic_valid_ff, _T_7806) @[ifu_mem_ctl.scala 692:97] + node _T_7808 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7809 = and(_T_7807, _T_7808) @[ifu_mem_ctl.scala 692:122] + node _T_7810 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[ifu_mem_ctl.scala 693:37] + node _T_7811 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7812 = and(_T_7810, _T_7811) @[ifu_mem_ctl.scala 693:59] + node _T_7813 = eq(perr_ic_index_ff, UInt<7>("h051")) @[ifu_mem_ctl.scala 693:102] + node _T_7814 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7815 = and(_T_7813, _T_7814) @[ifu_mem_ctl.scala 693:124] + node _T_7816 = or(_T_7812, _T_7815) @[ifu_mem_ctl.scala 693:81] + node _T_7817 = or(_T_7816, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7818 = bits(_T_7817, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7819 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7818 : @[Reg.scala 28:19] _T_7819 <= _T_7809 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][81] <= _T_7819 @[ifu_mem_ctl.scala 693:41] - node _T_7820 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7821 = eq(_T_7820, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7822 = and(ic_valid_ff, _T_7821) @[ifu_mem_ctl.scala 693:97] - node _T_7823 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7824 = and(_T_7822, _T_7823) @[ifu_mem_ctl.scala 693:122] - node _T_7825 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[ifu_mem_ctl.scala 694:37] - node _T_7826 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7827 = and(_T_7825, _T_7826) @[ifu_mem_ctl.scala 694:59] - node _T_7828 = eq(perr_ic_index_ff, UInt<7>("h052")) @[ifu_mem_ctl.scala 694:102] - node _T_7829 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7830 = and(_T_7828, _T_7829) @[ifu_mem_ctl.scala 694:124] - node _T_7831 = or(_T_7827, _T_7830) @[ifu_mem_ctl.scala 694:81] - node _T_7832 = or(_T_7831, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7833 = bits(_T_7832, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][81] <= _T_7819 @[ifu_mem_ctl.scala 692:41] + node _T_7820 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7821 = eq(_T_7820, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7822 = and(ic_valid_ff, _T_7821) @[ifu_mem_ctl.scala 692:97] + node _T_7823 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7824 = and(_T_7822, _T_7823) @[ifu_mem_ctl.scala 692:122] + node _T_7825 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[ifu_mem_ctl.scala 693:37] + node _T_7826 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7827 = and(_T_7825, _T_7826) @[ifu_mem_ctl.scala 693:59] + node _T_7828 = eq(perr_ic_index_ff, UInt<7>("h052")) @[ifu_mem_ctl.scala 693:102] + node _T_7829 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7830 = and(_T_7828, _T_7829) @[ifu_mem_ctl.scala 693:124] + node _T_7831 = or(_T_7827, _T_7830) @[ifu_mem_ctl.scala 693:81] + node _T_7832 = or(_T_7831, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7833 = bits(_T_7832, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7834 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7833 : @[Reg.scala 28:19] _T_7834 <= _T_7824 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][82] <= _T_7834 @[ifu_mem_ctl.scala 693:41] - node _T_7835 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7836 = eq(_T_7835, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7837 = and(ic_valid_ff, _T_7836) @[ifu_mem_ctl.scala 693:97] - node _T_7838 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7839 = and(_T_7837, _T_7838) @[ifu_mem_ctl.scala 693:122] - node _T_7840 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[ifu_mem_ctl.scala 694:37] - node _T_7841 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7842 = and(_T_7840, _T_7841) @[ifu_mem_ctl.scala 694:59] - node _T_7843 = eq(perr_ic_index_ff, UInt<7>("h053")) @[ifu_mem_ctl.scala 694:102] - node _T_7844 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7845 = and(_T_7843, _T_7844) @[ifu_mem_ctl.scala 694:124] - node _T_7846 = or(_T_7842, _T_7845) @[ifu_mem_ctl.scala 694:81] - node _T_7847 = or(_T_7846, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7848 = bits(_T_7847, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][82] <= _T_7834 @[ifu_mem_ctl.scala 692:41] + node _T_7835 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7836 = eq(_T_7835, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7837 = and(ic_valid_ff, _T_7836) @[ifu_mem_ctl.scala 692:97] + node _T_7838 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7839 = and(_T_7837, _T_7838) @[ifu_mem_ctl.scala 692:122] + node _T_7840 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[ifu_mem_ctl.scala 693:37] + node _T_7841 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7842 = and(_T_7840, _T_7841) @[ifu_mem_ctl.scala 693:59] + node _T_7843 = eq(perr_ic_index_ff, UInt<7>("h053")) @[ifu_mem_ctl.scala 693:102] + node _T_7844 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7845 = and(_T_7843, _T_7844) @[ifu_mem_ctl.scala 693:124] + node _T_7846 = or(_T_7842, _T_7845) @[ifu_mem_ctl.scala 693:81] + node _T_7847 = or(_T_7846, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7848 = bits(_T_7847, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7849 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7848 : @[Reg.scala 28:19] _T_7849 <= _T_7839 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][83] <= _T_7849 @[ifu_mem_ctl.scala 693:41] - node _T_7850 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7851 = eq(_T_7850, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7852 = and(ic_valid_ff, _T_7851) @[ifu_mem_ctl.scala 693:97] - node _T_7853 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7854 = and(_T_7852, _T_7853) @[ifu_mem_ctl.scala 693:122] - node _T_7855 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[ifu_mem_ctl.scala 694:37] - node _T_7856 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7857 = and(_T_7855, _T_7856) @[ifu_mem_ctl.scala 694:59] - node _T_7858 = eq(perr_ic_index_ff, UInt<7>("h054")) @[ifu_mem_ctl.scala 694:102] - node _T_7859 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7860 = and(_T_7858, _T_7859) @[ifu_mem_ctl.scala 694:124] - node _T_7861 = or(_T_7857, _T_7860) @[ifu_mem_ctl.scala 694:81] - node _T_7862 = or(_T_7861, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7863 = bits(_T_7862, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][83] <= _T_7849 @[ifu_mem_ctl.scala 692:41] + node _T_7850 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7851 = eq(_T_7850, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7852 = and(ic_valid_ff, _T_7851) @[ifu_mem_ctl.scala 692:97] + node _T_7853 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7854 = and(_T_7852, _T_7853) @[ifu_mem_ctl.scala 692:122] + node _T_7855 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[ifu_mem_ctl.scala 693:37] + node _T_7856 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7857 = and(_T_7855, _T_7856) @[ifu_mem_ctl.scala 693:59] + node _T_7858 = eq(perr_ic_index_ff, UInt<7>("h054")) @[ifu_mem_ctl.scala 693:102] + node _T_7859 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7860 = and(_T_7858, _T_7859) @[ifu_mem_ctl.scala 693:124] + node _T_7861 = or(_T_7857, _T_7860) @[ifu_mem_ctl.scala 693:81] + node _T_7862 = or(_T_7861, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7863 = bits(_T_7862, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7864 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7863 : @[Reg.scala 28:19] _T_7864 <= _T_7854 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][84] <= _T_7864 @[ifu_mem_ctl.scala 693:41] - node _T_7865 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7866 = eq(_T_7865, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7867 = and(ic_valid_ff, _T_7866) @[ifu_mem_ctl.scala 693:97] - node _T_7868 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7869 = and(_T_7867, _T_7868) @[ifu_mem_ctl.scala 693:122] - node _T_7870 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[ifu_mem_ctl.scala 694:37] - node _T_7871 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7872 = and(_T_7870, _T_7871) @[ifu_mem_ctl.scala 694:59] - node _T_7873 = eq(perr_ic_index_ff, UInt<7>("h055")) @[ifu_mem_ctl.scala 694:102] - node _T_7874 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7875 = and(_T_7873, _T_7874) @[ifu_mem_ctl.scala 694:124] - node _T_7876 = or(_T_7872, _T_7875) @[ifu_mem_ctl.scala 694:81] - node _T_7877 = or(_T_7876, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7878 = bits(_T_7877, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][84] <= _T_7864 @[ifu_mem_ctl.scala 692:41] + node _T_7865 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7866 = eq(_T_7865, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7867 = and(ic_valid_ff, _T_7866) @[ifu_mem_ctl.scala 692:97] + node _T_7868 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7869 = and(_T_7867, _T_7868) @[ifu_mem_ctl.scala 692:122] + node _T_7870 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[ifu_mem_ctl.scala 693:37] + node _T_7871 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7872 = and(_T_7870, _T_7871) @[ifu_mem_ctl.scala 693:59] + node _T_7873 = eq(perr_ic_index_ff, UInt<7>("h055")) @[ifu_mem_ctl.scala 693:102] + node _T_7874 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7875 = and(_T_7873, _T_7874) @[ifu_mem_ctl.scala 693:124] + node _T_7876 = or(_T_7872, _T_7875) @[ifu_mem_ctl.scala 693:81] + node _T_7877 = or(_T_7876, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7878 = bits(_T_7877, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7879 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7878 : @[Reg.scala 28:19] _T_7879 <= _T_7869 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][85] <= _T_7879 @[ifu_mem_ctl.scala 693:41] - node _T_7880 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7881 = eq(_T_7880, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7882 = and(ic_valid_ff, _T_7881) @[ifu_mem_ctl.scala 693:97] - node _T_7883 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7884 = and(_T_7882, _T_7883) @[ifu_mem_ctl.scala 693:122] - node _T_7885 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[ifu_mem_ctl.scala 694:37] - node _T_7886 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7887 = and(_T_7885, _T_7886) @[ifu_mem_ctl.scala 694:59] - node _T_7888 = eq(perr_ic_index_ff, UInt<7>("h056")) @[ifu_mem_ctl.scala 694:102] - node _T_7889 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7890 = and(_T_7888, _T_7889) @[ifu_mem_ctl.scala 694:124] - node _T_7891 = or(_T_7887, _T_7890) @[ifu_mem_ctl.scala 694:81] - node _T_7892 = or(_T_7891, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7893 = bits(_T_7892, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][85] <= _T_7879 @[ifu_mem_ctl.scala 692:41] + node _T_7880 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7881 = eq(_T_7880, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7882 = and(ic_valid_ff, _T_7881) @[ifu_mem_ctl.scala 692:97] + node _T_7883 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7884 = and(_T_7882, _T_7883) @[ifu_mem_ctl.scala 692:122] + node _T_7885 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[ifu_mem_ctl.scala 693:37] + node _T_7886 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7887 = and(_T_7885, _T_7886) @[ifu_mem_ctl.scala 693:59] + node _T_7888 = eq(perr_ic_index_ff, UInt<7>("h056")) @[ifu_mem_ctl.scala 693:102] + node _T_7889 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7890 = and(_T_7888, _T_7889) @[ifu_mem_ctl.scala 693:124] + node _T_7891 = or(_T_7887, _T_7890) @[ifu_mem_ctl.scala 693:81] + node _T_7892 = or(_T_7891, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7893 = bits(_T_7892, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7894 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7893 : @[Reg.scala 28:19] _T_7894 <= _T_7884 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][86] <= _T_7894 @[ifu_mem_ctl.scala 693:41] - node _T_7895 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7896 = eq(_T_7895, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7897 = and(ic_valid_ff, _T_7896) @[ifu_mem_ctl.scala 693:97] - node _T_7898 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7899 = and(_T_7897, _T_7898) @[ifu_mem_ctl.scala 693:122] - node _T_7900 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[ifu_mem_ctl.scala 694:37] - node _T_7901 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7902 = and(_T_7900, _T_7901) @[ifu_mem_ctl.scala 694:59] - node _T_7903 = eq(perr_ic_index_ff, UInt<7>("h057")) @[ifu_mem_ctl.scala 694:102] - node _T_7904 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7905 = and(_T_7903, _T_7904) @[ifu_mem_ctl.scala 694:124] - node _T_7906 = or(_T_7902, _T_7905) @[ifu_mem_ctl.scala 694:81] - node _T_7907 = or(_T_7906, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7908 = bits(_T_7907, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][86] <= _T_7894 @[ifu_mem_ctl.scala 692:41] + node _T_7895 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7896 = eq(_T_7895, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7897 = and(ic_valid_ff, _T_7896) @[ifu_mem_ctl.scala 692:97] + node _T_7898 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7899 = and(_T_7897, _T_7898) @[ifu_mem_ctl.scala 692:122] + node _T_7900 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[ifu_mem_ctl.scala 693:37] + node _T_7901 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7902 = and(_T_7900, _T_7901) @[ifu_mem_ctl.scala 693:59] + node _T_7903 = eq(perr_ic_index_ff, UInt<7>("h057")) @[ifu_mem_ctl.scala 693:102] + node _T_7904 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7905 = and(_T_7903, _T_7904) @[ifu_mem_ctl.scala 693:124] + node _T_7906 = or(_T_7902, _T_7905) @[ifu_mem_ctl.scala 693:81] + node _T_7907 = or(_T_7906, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7908 = bits(_T_7907, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7909 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7908 : @[Reg.scala 28:19] _T_7909 <= _T_7899 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][87] <= _T_7909 @[ifu_mem_ctl.scala 693:41] - node _T_7910 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7911 = eq(_T_7910, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7912 = and(ic_valid_ff, _T_7911) @[ifu_mem_ctl.scala 693:97] - node _T_7913 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7914 = and(_T_7912, _T_7913) @[ifu_mem_ctl.scala 693:122] - node _T_7915 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[ifu_mem_ctl.scala 694:37] - node _T_7916 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7917 = and(_T_7915, _T_7916) @[ifu_mem_ctl.scala 694:59] - node _T_7918 = eq(perr_ic_index_ff, UInt<7>("h058")) @[ifu_mem_ctl.scala 694:102] - node _T_7919 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7920 = and(_T_7918, _T_7919) @[ifu_mem_ctl.scala 694:124] - node _T_7921 = or(_T_7917, _T_7920) @[ifu_mem_ctl.scala 694:81] - node _T_7922 = or(_T_7921, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7923 = bits(_T_7922, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][87] <= _T_7909 @[ifu_mem_ctl.scala 692:41] + node _T_7910 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7911 = eq(_T_7910, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7912 = and(ic_valid_ff, _T_7911) @[ifu_mem_ctl.scala 692:97] + node _T_7913 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7914 = and(_T_7912, _T_7913) @[ifu_mem_ctl.scala 692:122] + node _T_7915 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[ifu_mem_ctl.scala 693:37] + node _T_7916 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7917 = and(_T_7915, _T_7916) @[ifu_mem_ctl.scala 693:59] + node _T_7918 = eq(perr_ic_index_ff, UInt<7>("h058")) @[ifu_mem_ctl.scala 693:102] + node _T_7919 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7920 = and(_T_7918, _T_7919) @[ifu_mem_ctl.scala 693:124] + node _T_7921 = or(_T_7917, _T_7920) @[ifu_mem_ctl.scala 693:81] + node _T_7922 = or(_T_7921, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7923 = bits(_T_7922, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7924 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7923 : @[Reg.scala 28:19] _T_7924 <= _T_7914 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][88] <= _T_7924 @[ifu_mem_ctl.scala 693:41] - node _T_7925 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7926 = eq(_T_7925, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7927 = and(ic_valid_ff, _T_7926) @[ifu_mem_ctl.scala 693:97] - node _T_7928 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7929 = and(_T_7927, _T_7928) @[ifu_mem_ctl.scala 693:122] - node _T_7930 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[ifu_mem_ctl.scala 694:37] - node _T_7931 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7932 = and(_T_7930, _T_7931) @[ifu_mem_ctl.scala 694:59] - node _T_7933 = eq(perr_ic_index_ff, UInt<7>("h059")) @[ifu_mem_ctl.scala 694:102] - node _T_7934 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7935 = and(_T_7933, _T_7934) @[ifu_mem_ctl.scala 694:124] - node _T_7936 = or(_T_7932, _T_7935) @[ifu_mem_ctl.scala 694:81] - node _T_7937 = or(_T_7936, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7938 = bits(_T_7937, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][88] <= _T_7924 @[ifu_mem_ctl.scala 692:41] + node _T_7925 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7926 = eq(_T_7925, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7927 = and(ic_valid_ff, _T_7926) @[ifu_mem_ctl.scala 692:97] + node _T_7928 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7929 = and(_T_7927, _T_7928) @[ifu_mem_ctl.scala 692:122] + node _T_7930 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[ifu_mem_ctl.scala 693:37] + node _T_7931 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7932 = and(_T_7930, _T_7931) @[ifu_mem_ctl.scala 693:59] + node _T_7933 = eq(perr_ic_index_ff, UInt<7>("h059")) @[ifu_mem_ctl.scala 693:102] + node _T_7934 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7935 = and(_T_7933, _T_7934) @[ifu_mem_ctl.scala 693:124] + node _T_7936 = or(_T_7932, _T_7935) @[ifu_mem_ctl.scala 693:81] + node _T_7937 = or(_T_7936, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7938 = bits(_T_7937, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7939 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7938 : @[Reg.scala 28:19] _T_7939 <= _T_7929 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][89] <= _T_7939 @[ifu_mem_ctl.scala 693:41] - node _T_7940 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7941 = eq(_T_7940, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7942 = and(ic_valid_ff, _T_7941) @[ifu_mem_ctl.scala 693:97] - node _T_7943 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7944 = and(_T_7942, _T_7943) @[ifu_mem_ctl.scala 693:122] - node _T_7945 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[ifu_mem_ctl.scala 694:37] - node _T_7946 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7947 = and(_T_7945, _T_7946) @[ifu_mem_ctl.scala 694:59] - node _T_7948 = eq(perr_ic_index_ff, UInt<7>("h05a")) @[ifu_mem_ctl.scala 694:102] - node _T_7949 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7950 = and(_T_7948, _T_7949) @[ifu_mem_ctl.scala 694:124] - node _T_7951 = or(_T_7947, _T_7950) @[ifu_mem_ctl.scala 694:81] - node _T_7952 = or(_T_7951, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7953 = bits(_T_7952, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][89] <= _T_7939 @[ifu_mem_ctl.scala 692:41] + node _T_7940 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7941 = eq(_T_7940, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7942 = and(ic_valid_ff, _T_7941) @[ifu_mem_ctl.scala 692:97] + node _T_7943 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7944 = and(_T_7942, _T_7943) @[ifu_mem_ctl.scala 692:122] + node _T_7945 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[ifu_mem_ctl.scala 693:37] + node _T_7946 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7947 = and(_T_7945, _T_7946) @[ifu_mem_ctl.scala 693:59] + node _T_7948 = eq(perr_ic_index_ff, UInt<7>("h05a")) @[ifu_mem_ctl.scala 693:102] + node _T_7949 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7950 = and(_T_7948, _T_7949) @[ifu_mem_ctl.scala 693:124] + node _T_7951 = or(_T_7947, _T_7950) @[ifu_mem_ctl.scala 693:81] + node _T_7952 = or(_T_7951, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7953 = bits(_T_7952, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7954 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7953 : @[Reg.scala 28:19] _T_7954 <= _T_7944 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][90] <= _T_7954 @[ifu_mem_ctl.scala 693:41] - node _T_7955 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7956 = eq(_T_7955, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7957 = and(ic_valid_ff, _T_7956) @[ifu_mem_ctl.scala 693:97] - node _T_7958 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7959 = and(_T_7957, _T_7958) @[ifu_mem_ctl.scala 693:122] - node _T_7960 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[ifu_mem_ctl.scala 694:37] - node _T_7961 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7962 = and(_T_7960, _T_7961) @[ifu_mem_ctl.scala 694:59] - node _T_7963 = eq(perr_ic_index_ff, UInt<7>("h05b")) @[ifu_mem_ctl.scala 694:102] - node _T_7964 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7965 = and(_T_7963, _T_7964) @[ifu_mem_ctl.scala 694:124] - node _T_7966 = or(_T_7962, _T_7965) @[ifu_mem_ctl.scala 694:81] - node _T_7967 = or(_T_7966, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7968 = bits(_T_7967, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][90] <= _T_7954 @[ifu_mem_ctl.scala 692:41] + node _T_7955 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7956 = eq(_T_7955, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7957 = and(ic_valid_ff, _T_7956) @[ifu_mem_ctl.scala 692:97] + node _T_7958 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7959 = and(_T_7957, _T_7958) @[ifu_mem_ctl.scala 692:122] + node _T_7960 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[ifu_mem_ctl.scala 693:37] + node _T_7961 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7962 = and(_T_7960, _T_7961) @[ifu_mem_ctl.scala 693:59] + node _T_7963 = eq(perr_ic_index_ff, UInt<7>("h05b")) @[ifu_mem_ctl.scala 693:102] + node _T_7964 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7965 = and(_T_7963, _T_7964) @[ifu_mem_ctl.scala 693:124] + node _T_7966 = or(_T_7962, _T_7965) @[ifu_mem_ctl.scala 693:81] + node _T_7967 = or(_T_7966, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7968 = bits(_T_7967, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7969 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7968 : @[Reg.scala 28:19] _T_7969 <= _T_7959 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][91] <= _T_7969 @[ifu_mem_ctl.scala 693:41] - node _T_7970 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7971 = eq(_T_7970, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7972 = and(ic_valid_ff, _T_7971) @[ifu_mem_ctl.scala 693:97] - node _T_7973 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7974 = and(_T_7972, _T_7973) @[ifu_mem_ctl.scala 693:122] - node _T_7975 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[ifu_mem_ctl.scala 694:37] - node _T_7976 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7977 = and(_T_7975, _T_7976) @[ifu_mem_ctl.scala 694:59] - node _T_7978 = eq(perr_ic_index_ff, UInt<7>("h05c")) @[ifu_mem_ctl.scala 694:102] - node _T_7979 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7980 = and(_T_7978, _T_7979) @[ifu_mem_ctl.scala 694:124] - node _T_7981 = or(_T_7977, _T_7980) @[ifu_mem_ctl.scala 694:81] - node _T_7982 = or(_T_7981, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7983 = bits(_T_7982, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][91] <= _T_7969 @[ifu_mem_ctl.scala 692:41] + node _T_7970 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7971 = eq(_T_7970, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7972 = and(ic_valid_ff, _T_7971) @[ifu_mem_ctl.scala 692:97] + node _T_7973 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7974 = and(_T_7972, _T_7973) @[ifu_mem_ctl.scala 692:122] + node _T_7975 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[ifu_mem_ctl.scala 693:37] + node _T_7976 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7977 = and(_T_7975, _T_7976) @[ifu_mem_ctl.scala 693:59] + node _T_7978 = eq(perr_ic_index_ff, UInt<7>("h05c")) @[ifu_mem_ctl.scala 693:102] + node _T_7979 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7980 = and(_T_7978, _T_7979) @[ifu_mem_ctl.scala 693:124] + node _T_7981 = or(_T_7977, _T_7980) @[ifu_mem_ctl.scala 693:81] + node _T_7982 = or(_T_7981, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7983 = bits(_T_7982, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7984 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7983 : @[Reg.scala 28:19] _T_7984 <= _T_7974 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][92] <= _T_7984 @[ifu_mem_ctl.scala 693:41] - node _T_7985 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_7986 = eq(_T_7985, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_7987 = and(ic_valid_ff, _T_7986) @[ifu_mem_ctl.scala 693:97] - node _T_7988 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_7989 = and(_T_7987, _T_7988) @[ifu_mem_ctl.scala 693:122] - node _T_7990 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[ifu_mem_ctl.scala 694:37] - node _T_7991 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_7992 = and(_T_7990, _T_7991) @[ifu_mem_ctl.scala 694:59] - node _T_7993 = eq(perr_ic_index_ff, UInt<7>("h05d")) @[ifu_mem_ctl.scala 694:102] - node _T_7994 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_7995 = and(_T_7993, _T_7994) @[ifu_mem_ctl.scala 694:124] - node _T_7996 = or(_T_7992, _T_7995) @[ifu_mem_ctl.scala 694:81] - node _T_7997 = or(_T_7996, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_7998 = bits(_T_7997, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][92] <= _T_7984 @[ifu_mem_ctl.scala 692:41] + node _T_7985 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_7986 = eq(_T_7985, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_7987 = and(ic_valid_ff, _T_7986) @[ifu_mem_ctl.scala 692:97] + node _T_7988 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_7989 = and(_T_7987, _T_7988) @[ifu_mem_ctl.scala 692:122] + node _T_7990 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[ifu_mem_ctl.scala 693:37] + node _T_7991 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_7992 = and(_T_7990, _T_7991) @[ifu_mem_ctl.scala 693:59] + node _T_7993 = eq(perr_ic_index_ff, UInt<7>("h05d")) @[ifu_mem_ctl.scala 693:102] + node _T_7994 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_7995 = and(_T_7993, _T_7994) @[ifu_mem_ctl.scala 693:124] + node _T_7996 = or(_T_7992, _T_7995) @[ifu_mem_ctl.scala 693:81] + node _T_7997 = or(_T_7996, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_7998 = bits(_T_7997, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_7999 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7998 : @[Reg.scala 28:19] _T_7999 <= _T_7989 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][93] <= _T_7999 @[ifu_mem_ctl.scala 693:41] - node _T_8000 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8001 = eq(_T_8000, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8002 = and(ic_valid_ff, _T_8001) @[ifu_mem_ctl.scala 693:97] - node _T_8003 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8004 = and(_T_8002, _T_8003) @[ifu_mem_ctl.scala 693:122] - node _T_8005 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[ifu_mem_ctl.scala 694:37] - node _T_8006 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_8007 = and(_T_8005, _T_8006) @[ifu_mem_ctl.scala 694:59] - node _T_8008 = eq(perr_ic_index_ff, UInt<7>("h05e")) @[ifu_mem_ctl.scala 694:102] - node _T_8009 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_8010 = and(_T_8008, _T_8009) @[ifu_mem_ctl.scala 694:124] - node _T_8011 = or(_T_8007, _T_8010) @[ifu_mem_ctl.scala 694:81] - node _T_8012 = or(_T_8011, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8013 = bits(_T_8012, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][93] <= _T_7999 @[ifu_mem_ctl.scala 692:41] + node _T_8000 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8001 = eq(_T_8000, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8002 = and(ic_valid_ff, _T_8001) @[ifu_mem_ctl.scala 692:97] + node _T_8003 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8004 = and(_T_8002, _T_8003) @[ifu_mem_ctl.scala 692:122] + node _T_8005 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[ifu_mem_ctl.scala 693:37] + node _T_8006 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_8007 = and(_T_8005, _T_8006) @[ifu_mem_ctl.scala 693:59] + node _T_8008 = eq(perr_ic_index_ff, UInt<7>("h05e")) @[ifu_mem_ctl.scala 693:102] + node _T_8009 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_8010 = and(_T_8008, _T_8009) @[ifu_mem_ctl.scala 693:124] + node _T_8011 = or(_T_8007, _T_8010) @[ifu_mem_ctl.scala 693:81] + node _T_8012 = or(_T_8011, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8013 = bits(_T_8012, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8014 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8013 : @[Reg.scala 28:19] _T_8014 <= _T_8004 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][94] <= _T_8014 @[ifu_mem_ctl.scala 693:41] - node _T_8015 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8016 = eq(_T_8015, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8017 = and(ic_valid_ff, _T_8016) @[ifu_mem_ctl.scala 693:97] - node _T_8018 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8019 = and(_T_8017, _T_8018) @[ifu_mem_ctl.scala 693:122] - node _T_8020 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[ifu_mem_ctl.scala 694:37] - node _T_8021 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_8022 = and(_T_8020, _T_8021) @[ifu_mem_ctl.scala 694:59] - node _T_8023 = eq(perr_ic_index_ff, UInt<7>("h05f")) @[ifu_mem_ctl.scala 694:102] - node _T_8024 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_8025 = and(_T_8023, _T_8024) @[ifu_mem_ctl.scala 694:124] - node _T_8026 = or(_T_8022, _T_8025) @[ifu_mem_ctl.scala 694:81] - node _T_8027 = or(_T_8026, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8028 = bits(_T_8027, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][94] <= _T_8014 @[ifu_mem_ctl.scala 692:41] + node _T_8015 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8016 = eq(_T_8015, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8017 = and(ic_valid_ff, _T_8016) @[ifu_mem_ctl.scala 692:97] + node _T_8018 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8019 = and(_T_8017, _T_8018) @[ifu_mem_ctl.scala 692:122] + node _T_8020 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[ifu_mem_ctl.scala 693:37] + node _T_8021 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_8022 = and(_T_8020, _T_8021) @[ifu_mem_ctl.scala 693:59] + node _T_8023 = eq(perr_ic_index_ff, UInt<7>("h05f")) @[ifu_mem_ctl.scala 693:102] + node _T_8024 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_8025 = and(_T_8023, _T_8024) @[ifu_mem_ctl.scala 693:124] + node _T_8026 = or(_T_8022, _T_8025) @[ifu_mem_ctl.scala 693:81] + node _T_8027 = or(_T_8026, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8028 = bits(_T_8027, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8029 : UInt<1>, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8028 : @[Reg.scala 28:19] _T_8029 <= _T_8019 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][95] <= _T_8029 @[ifu_mem_ctl.scala 693:41] - node _T_8030 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8031 = eq(_T_8030, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8032 = and(ic_valid_ff, _T_8031) @[ifu_mem_ctl.scala 693:97] - node _T_8033 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8034 = and(_T_8032, _T_8033) @[ifu_mem_ctl.scala 693:122] - node _T_8035 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[ifu_mem_ctl.scala 694:37] - node _T_8036 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_8037 = and(_T_8035, _T_8036) @[ifu_mem_ctl.scala 694:59] - node _T_8038 = eq(perr_ic_index_ff, UInt<7>("h060")) @[ifu_mem_ctl.scala 694:102] - node _T_8039 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_8040 = and(_T_8038, _T_8039) @[ifu_mem_ctl.scala 694:124] - node _T_8041 = or(_T_8037, _T_8040) @[ifu_mem_ctl.scala 694:81] - node _T_8042 = or(_T_8041, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8043 = bits(_T_8042, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][95] <= _T_8029 @[ifu_mem_ctl.scala 692:41] + node _T_8030 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8031 = eq(_T_8030, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8032 = and(ic_valid_ff, _T_8031) @[ifu_mem_ctl.scala 692:97] + node _T_8033 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8034 = and(_T_8032, _T_8033) @[ifu_mem_ctl.scala 692:122] + node _T_8035 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[ifu_mem_ctl.scala 693:37] + node _T_8036 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_8037 = and(_T_8035, _T_8036) @[ifu_mem_ctl.scala 693:59] + node _T_8038 = eq(perr_ic_index_ff, UInt<7>("h060")) @[ifu_mem_ctl.scala 693:102] + node _T_8039 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_8040 = and(_T_8038, _T_8039) @[ifu_mem_ctl.scala 693:124] + node _T_8041 = or(_T_8037, _T_8040) @[ifu_mem_ctl.scala 693:81] + node _T_8042 = or(_T_8041, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8043 = bits(_T_8042, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8044 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8043 : @[Reg.scala 28:19] _T_8044 <= _T_8034 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][96] <= _T_8044 @[ifu_mem_ctl.scala 693:41] - node _T_8045 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8046 = eq(_T_8045, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8047 = and(ic_valid_ff, _T_8046) @[ifu_mem_ctl.scala 693:97] - node _T_8048 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8049 = and(_T_8047, _T_8048) @[ifu_mem_ctl.scala 693:122] - node _T_8050 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[ifu_mem_ctl.scala 694:37] - node _T_8051 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_8052 = and(_T_8050, _T_8051) @[ifu_mem_ctl.scala 694:59] - node _T_8053 = eq(perr_ic_index_ff, UInt<7>("h061")) @[ifu_mem_ctl.scala 694:102] - node _T_8054 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_8055 = and(_T_8053, _T_8054) @[ifu_mem_ctl.scala 694:124] - node _T_8056 = or(_T_8052, _T_8055) @[ifu_mem_ctl.scala 694:81] - node _T_8057 = or(_T_8056, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8058 = bits(_T_8057, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][96] <= _T_8044 @[ifu_mem_ctl.scala 692:41] + node _T_8045 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8046 = eq(_T_8045, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8047 = and(ic_valid_ff, _T_8046) @[ifu_mem_ctl.scala 692:97] + node _T_8048 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8049 = and(_T_8047, _T_8048) @[ifu_mem_ctl.scala 692:122] + node _T_8050 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[ifu_mem_ctl.scala 693:37] + node _T_8051 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_8052 = and(_T_8050, _T_8051) @[ifu_mem_ctl.scala 693:59] + node _T_8053 = eq(perr_ic_index_ff, UInt<7>("h061")) @[ifu_mem_ctl.scala 693:102] + node _T_8054 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_8055 = and(_T_8053, _T_8054) @[ifu_mem_ctl.scala 693:124] + node _T_8056 = or(_T_8052, _T_8055) @[ifu_mem_ctl.scala 693:81] + node _T_8057 = or(_T_8056, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8058 = bits(_T_8057, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8059 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8058 : @[Reg.scala 28:19] _T_8059 <= _T_8049 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][97] <= _T_8059 @[ifu_mem_ctl.scala 693:41] - node _T_8060 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8061 = eq(_T_8060, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8062 = and(ic_valid_ff, _T_8061) @[ifu_mem_ctl.scala 693:97] - node _T_8063 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8064 = and(_T_8062, _T_8063) @[ifu_mem_ctl.scala 693:122] - node _T_8065 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[ifu_mem_ctl.scala 694:37] - node _T_8066 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_8067 = and(_T_8065, _T_8066) @[ifu_mem_ctl.scala 694:59] - node _T_8068 = eq(perr_ic_index_ff, UInt<7>("h062")) @[ifu_mem_ctl.scala 694:102] - node _T_8069 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_8070 = and(_T_8068, _T_8069) @[ifu_mem_ctl.scala 694:124] - node _T_8071 = or(_T_8067, _T_8070) @[ifu_mem_ctl.scala 694:81] - node _T_8072 = or(_T_8071, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8073 = bits(_T_8072, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][97] <= _T_8059 @[ifu_mem_ctl.scala 692:41] + node _T_8060 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8061 = eq(_T_8060, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8062 = and(ic_valid_ff, _T_8061) @[ifu_mem_ctl.scala 692:97] + node _T_8063 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8064 = and(_T_8062, _T_8063) @[ifu_mem_ctl.scala 692:122] + node _T_8065 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[ifu_mem_ctl.scala 693:37] + node _T_8066 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_8067 = and(_T_8065, _T_8066) @[ifu_mem_ctl.scala 693:59] + node _T_8068 = eq(perr_ic_index_ff, UInt<7>("h062")) @[ifu_mem_ctl.scala 693:102] + node _T_8069 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_8070 = and(_T_8068, _T_8069) @[ifu_mem_ctl.scala 693:124] + node _T_8071 = or(_T_8067, _T_8070) @[ifu_mem_ctl.scala 693:81] + node _T_8072 = or(_T_8071, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8073 = bits(_T_8072, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8074 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8073 : @[Reg.scala 28:19] _T_8074 <= _T_8064 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][98] <= _T_8074 @[ifu_mem_ctl.scala 693:41] - node _T_8075 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8076 = eq(_T_8075, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8077 = and(ic_valid_ff, _T_8076) @[ifu_mem_ctl.scala 693:97] - node _T_8078 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8079 = and(_T_8077, _T_8078) @[ifu_mem_ctl.scala 693:122] - node _T_8080 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[ifu_mem_ctl.scala 694:37] - node _T_8081 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_8082 = and(_T_8080, _T_8081) @[ifu_mem_ctl.scala 694:59] - node _T_8083 = eq(perr_ic_index_ff, UInt<7>("h063")) @[ifu_mem_ctl.scala 694:102] - node _T_8084 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_8085 = and(_T_8083, _T_8084) @[ifu_mem_ctl.scala 694:124] - node _T_8086 = or(_T_8082, _T_8085) @[ifu_mem_ctl.scala 694:81] - node _T_8087 = or(_T_8086, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8088 = bits(_T_8087, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][98] <= _T_8074 @[ifu_mem_ctl.scala 692:41] + node _T_8075 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8076 = eq(_T_8075, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8077 = and(ic_valid_ff, _T_8076) @[ifu_mem_ctl.scala 692:97] + node _T_8078 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8079 = and(_T_8077, _T_8078) @[ifu_mem_ctl.scala 692:122] + node _T_8080 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[ifu_mem_ctl.scala 693:37] + node _T_8081 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_8082 = and(_T_8080, _T_8081) @[ifu_mem_ctl.scala 693:59] + node _T_8083 = eq(perr_ic_index_ff, UInt<7>("h063")) @[ifu_mem_ctl.scala 693:102] + node _T_8084 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_8085 = and(_T_8083, _T_8084) @[ifu_mem_ctl.scala 693:124] + node _T_8086 = or(_T_8082, _T_8085) @[ifu_mem_ctl.scala 693:81] + node _T_8087 = or(_T_8086, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8088 = bits(_T_8087, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8089 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8088 : @[Reg.scala 28:19] _T_8089 <= _T_8079 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][99] <= _T_8089 @[ifu_mem_ctl.scala 693:41] - node _T_8090 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8091 = eq(_T_8090, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8092 = and(ic_valid_ff, _T_8091) @[ifu_mem_ctl.scala 693:97] - node _T_8093 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8094 = and(_T_8092, _T_8093) @[ifu_mem_ctl.scala 693:122] - node _T_8095 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[ifu_mem_ctl.scala 694:37] - node _T_8096 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_8097 = and(_T_8095, _T_8096) @[ifu_mem_ctl.scala 694:59] - node _T_8098 = eq(perr_ic_index_ff, UInt<7>("h064")) @[ifu_mem_ctl.scala 694:102] - node _T_8099 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_8100 = and(_T_8098, _T_8099) @[ifu_mem_ctl.scala 694:124] - node _T_8101 = or(_T_8097, _T_8100) @[ifu_mem_ctl.scala 694:81] - node _T_8102 = or(_T_8101, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8103 = bits(_T_8102, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][99] <= _T_8089 @[ifu_mem_ctl.scala 692:41] + node _T_8090 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8091 = eq(_T_8090, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8092 = and(ic_valid_ff, _T_8091) @[ifu_mem_ctl.scala 692:97] + node _T_8093 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8094 = and(_T_8092, _T_8093) @[ifu_mem_ctl.scala 692:122] + node _T_8095 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[ifu_mem_ctl.scala 693:37] + node _T_8096 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_8097 = and(_T_8095, _T_8096) @[ifu_mem_ctl.scala 693:59] + node _T_8098 = eq(perr_ic_index_ff, UInt<7>("h064")) @[ifu_mem_ctl.scala 693:102] + node _T_8099 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_8100 = and(_T_8098, _T_8099) @[ifu_mem_ctl.scala 693:124] + node _T_8101 = or(_T_8097, _T_8100) @[ifu_mem_ctl.scala 693:81] + node _T_8102 = or(_T_8101, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8103 = bits(_T_8102, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8104 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8103 : @[Reg.scala 28:19] _T_8104 <= _T_8094 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][100] <= _T_8104 @[ifu_mem_ctl.scala 693:41] - node _T_8105 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8106 = eq(_T_8105, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8107 = and(ic_valid_ff, _T_8106) @[ifu_mem_ctl.scala 693:97] - node _T_8108 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8109 = and(_T_8107, _T_8108) @[ifu_mem_ctl.scala 693:122] - node _T_8110 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[ifu_mem_ctl.scala 694:37] - node _T_8111 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_8112 = and(_T_8110, _T_8111) @[ifu_mem_ctl.scala 694:59] - node _T_8113 = eq(perr_ic_index_ff, UInt<7>("h065")) @[ifu_mem_ctl.scala 694:102] - node _T_8114 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_8115 = and(_T_8113, _T_8114) @[ifu_mem_ctl.scala 694:124] - node _T_8116 = or(_T_8112, _T_8115) @[ifu_mem_ctl.scala 694:81] - node _T_8117 = or(_T_8116, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8118 = bits(_T_8117, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][100] <= _T_8104 @[ifu_mem_ctl.scala 692:41] + node _T_8105 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8106 = eq(_T_8105, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8107 = and(ic_valid_ff, _T_8106) @[ifu_mem_ctl.scala 692:97] + node _T_8108 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8109 = and(_T_8107, _T_8108) @[ifu_mem_ctl.scala 692:122] + node _T_8110 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[ifu_mem_ctl.scala 693:37] + node _T_8111 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_8112 = and(_T_8110, _T_8111) @[ifu_mem_ctl.scala 693:59] + node _T_8113 = eq(perr_ic_index_ff, UInt<7>("h065")) @[ifu_mem_ctl.scala 693:102] + node _T_8114 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_8115 = and(_T_8113, _T_8114) @[ifu_mem_ctl.scala 693:124] + node _T_8116 = or(_T_8112, _T_8115) @[ifu_mem_ctl.scala 693:81] + node _T_8117 = or(_T_8116, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8118 = bits(_T_8117, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8119 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8118 : @[Reg.scala 28:19] _T_8119 <= _T_8109 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][101] <= _T_8119 @[ifu_mem_ctl.scala 693:41] - node _T_8120 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8121 = eq(_T_8120, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8122 = and(ic_valid_ff, _T_8121) @[ifu_mem_ctl.scala 693:97] - node _T_8123 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8124 = and(_T_8122, _T_8123) @[ifu_mem_ctl.scala 693:122] - node _T_8125 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[ifu_mem_ctl.scala 694:37] - node _T_8126 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_8127 = and(_T_8125, _T_8126) @[ifu_mem_ctl.scala 694:59] - node _T_8128 = eq(perr_ic_index_ff, UInt<7>("h066")) @[ifu_mem_ctl.scala 694:102] - node _T_8129 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_8130 = and(_T_8128, _T_8129) @[ifu_mem_ctl.scala 694:124] - node _T_8131 = or(_T_8127, _T_8130) @[ifu_mem_ctl.scala 694:81] - node _T_8132 = or(_T_8131, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8133 = bits(_T_8132, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][101] <= _T_8119 @[ifu_mem_ctl.scala 692:41] + node _T_8120 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8121 = eq(_T_8120, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8122 = and(ic_valid_ff, _T_8121) @[ifu_mem_ctl.scala 692:97] + node _T_8123 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8124 = and(_T_8122, _T_8123) @[ifu_mem_ctl.scala 692:122] + node _T_8125 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[ifu_mem_ctl.scala 693:37] + node _T_8126 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_8127 = and(_T_8125, _T_8126) @[ifu_mem_ctl.scala 693:59] + node _T_8128 = eq(perr_ic_index_ff, UInt<7>("h066")) @[ifu_mem_ctl.scala 693:102] + node _T_8129 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_8130 = and(_T_8128, _T_8129) @[ifu_mem_ctl.scala 693:124] + node _T_8131 = or(_T_8127, _T_8130) @[ifu_mem_ctl.scala 693:81] + node _T_8132 = or(_T_8131, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8133 = bits(_T_8132, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8134 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8133 : @[Reg.scala 28:19] _T_8134 <= _T_8124 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][102] <= _T_8134 @[ifu_mem_ctl.scala 693:41] - node _T_8135 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8136 = eq(_T_8135, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8137 = and(ic_valid_ff, _T_8136) @[ifu_mem_ctl.scala 693:97] - node _T_8138 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8139 = and(_T_8137, _T_8138) @[ifu_mem_ctl.scala 693:122] - node _T_8140 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[ifu_mem_ctl.scala 694:37] - node _T_8141 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_8142 = and(_T_8140, _T_8141) @[ifu_mem_ctl.scala 694:59] - node _T_8143 = eq(perr_ic_index_ff, UInt<7>("h067")) @[ifu_mem_ctl.scala 694:102] - node _T_8144 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_8145 = and(_T_8143, _T_8144) @[ifu_mem_ctl.scala 694:124] - node _T_8146 = or(_T_8142, _T_8145) @[ifu_mem_ctl.scala 694:81] - node _T_8147 = or(_T_8146, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8148 = bits(_T_8147, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][102] <= _T_8134 @[ifu_mem_ctl.scala 692:41] + node _T_8135 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8136 = eq(_T_8135, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8137 = and(ic_valid_ff, _T_8136) @[ifu_mem_ctl.scala 692:97] + node _T_8138 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8139 = and(_T_8137, _T_8138) @[ifu_mem_ctl.scala 692:122] + node _T_8140 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[ifu_mem_ctl.scala 693:37] + node _T_8141 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_8142 = and(_T_8140, _T_8141) @[ifu_mem_ctl.scala 693:59] + node _T_8143 = eq(perr_ic_index_ff, UInt<7>("h067")) @[ifu_mem_ctl.scala 693:102] + node _T_8144 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_8145 = and(_T_8143, _T_8144) @[ifu_mem_ctl.scala 693:124] + node _T_8146 = or(_T_8142, _T_8145) @[ifu_mem_ctl.scala 693:81] + node _T_8147 = or(_T_8146, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8148 = bits(_T_8147, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8149 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8148 : @[Reg.scala 28:19] _T_8149 <= _T_8139 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][103] <= _T_8149 @[ifu_mem_ctl.scala 693:41] - node _T_8150 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8151 = eq(_T_8150, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8152 = and(ic_valid_ff, _T_8151) @[ifu_mem_ctl.scala 693:97] - node _T_8153 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8154 = and(_T_8152, _T_8153) @[ifu_mem_ctl.scala 693:122] - node _T_8155 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[ifu_mem_ctl.scala 694:37] - node _T_8156 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_8157 = and(_T_8155, _T_8156) @[ifu_mem_ctl.scala 694:59] - node _T_8158 = eq(perr_ic_index_ff, UInt<7>("h068")) @[ifu_mem_ctl.scala 694:102] - node _T_8159 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_8160 = and(_T_8158, _T_8159) @[ifu_mem_ctl.scala 694:124] - node _T_8161 = or(_T_8157, _T_8160) @[ifu_mem_ctl.scala 694:81] - node _T_8162 = or(_T_8161, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8163 = bits(_T_8162, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][103] <= _T_8149 @[ifu_mem_ctl.scala 692:41] + node _T_8150 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8151 = eq(_T_8150, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8152 = and(ic_valid_ff, _T_8151) @[ifu_mem_ctl.scala 692:97] + node _T_8153 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8154 = and(_T_8152, _T_8153) @[ifu_mem_ctl.scala 692:122] + node _T_8155 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[ifu_mem_ctl.scala 693:37] + node _T_8156 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_8157 = and(_T_8155, _T_8156) @[ifu_mem_ctl.scala 693:59] + node _T_8158 = eq(perr_ic_index_ff, UInt<7>("h068")) @[ifu_mem_ctl.scala 693:102] + node _T_8159 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_8160 = and(_T_8158, _T_8159) @[ifu_mem_ctl.scala 693:124] + node _T_8161 = or(_T_8157, _T_8160) @[ifu_mem_ctl.scala 693:81] + node _T_8162 = or(_T_8161, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8163 = bits(_T_8162, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8164 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8163 : @[Reg.scala 28:19] _T_8164 <= _T_8154 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][104] <= _T_8164 @[ifu_mem_ctl.scala 693:41] - node _T_8165 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8166 = eq(_T_8165, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8167 = and(ic_valid_ff, _T_8166) @[ifu_mem_ctl.scala 693:97] - node _T_8168 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8169 = and(_T_8167, _T_8168) @[ifu_mem_ctl.scala 693:122] - node _T_8170 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[ifu_mem_ctl.scala 694:37] - node _T_8171 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_8172 = and(_T_8170, _T_8171) @[ifu_mem_ctl.scala 694:59] - node _T_8173 = eq(perr_ic_index_ff, UInt<7>("h069")) @[ifu_mem_ctl.scala 694:102] - node _T_8174 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_8175 = and(_T_8173, _T_8174) @[ifu_mem_ctl.scala 694:124] - node _T_8176 = or(_T_8172, _T_8175) @[ifu_mem_ctl.scala 694:81] - node _T_8177 = or(_T_8176, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8178 = bits(_T_8177, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][104] <= _T_8164 @[ifu_mem_ctl.scala 692:41] + node _T_8165 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8166 = eq(_T_8165, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8167 = and(ic_valid_ff, _T_8166) @[ifu_mem_ctl.scala 692:97] + node _T_8168 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8169 = and(_T_8167, _T_8168) @[ifu_mem_ctl.scala 692:122] + node _T_8170 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[ifu_mem_ctl.scala 693:37] + node _T_8171 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_8172 = and(_T_8170, _T_8171) @[ifu_mem_ctl.scala 693:59] + node _T_8173 = eq(perr_ic_index_ff, UInt<7>("h069")) @[ifu_mem_ctl.scala 693:102] + node _T_8174 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_8175 = and(_T_8173, _T_8174) @[ifu_mem_ctl.scala 693:124] + node _T_8176 = or(_T_8172, _T_8175) @[ifu_mem_ctl.scala 693:81] + node _T_8177 = or(_T_8176, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8178 = bits(_T_8177, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8179 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8178 : @[Reg.scala 28:19] _T_8179 <= _T_8169 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][105] <= _T_8179 @[ifu_mem_ctl.scala 693:41] - node _T_8180 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8181 = eq(_T_8180, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8182 = and(ic_valid_ff, _T_8181) @[ifu_mem_ctl.scala 693:97] - node _T_8183 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8184 = and(_T_8182, _T_8183) @[ifu_mem_ctl.scala 693:122] - node _T_8185 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[ifu_mem_ctl.scala 694:37] - node _T_8186 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_8187 = and(_T_8185, _T_8186) @[ifu_mem_ctl.scala 694:59] - node _T_8188 = eq(perr_ic_index_ff, UInt<7>("h06a")) @[ifu_mem_ctl.scala 694:102] - node _T_8189 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_8190 = and(_T_8188, _T_8189) @[ifu_mem_ctl.scala 694:124] - node _T_8191 = or(_T_8187, _T_8190) @[ifu_mem_ctl.scala 694:81] - node _T_8192 = or(_T_8191, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8193 = bits(_T_8192, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][105] <= _T_8179 @[ifu_mem_ctl.scala 692:41] + node _T_8180 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8181 = eq(_T_8180, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8182 = and(ic_valid_ff, _T_8181) @[ifu_mem_ctl.scala 692:97] + node _T_8183 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8184 = and(_T_8182, _T_8183) @[ifu_mem_ctl.scala 692:122] + node _T_8185 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[ifu_mem_ctl.scala 693:37] + node _T_8186 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_8187 = and(_T_8185, _T_8186) @[ifu_mem_ctl.scala 693:59] + node _T_8188 = eq(perr_ic_index_ff, UInt<7>("h06a")) @[ifu_mem_ctl.scala 693:102] + node _T_8189 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_8190 = and(_T_8188, _T_8189) @[ifu_mem_ctl.scala 693:124] + node _T_8191 = or(_T_8187, _T_8190) @[ifu_mem_ctl.scala 693:81] + node _T_8192 = or(_T_8191, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8193 = bits(_T_8192, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8194 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8193 : @[Reg.scala 28:19] _T_8194 <= _T_8184 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][106] <= _T_8194 @[ifu_mem_ctl.scala 693:41] - node _T_8195 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8196 = eq(_T_8195, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8197 = and(ic_valid_ff, _T_8196) @[ifu_mem_ctl.scala 693:97] - node _T_8198 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8199 = and(_T_8197, _T_8198) @[ifu_mem_ctl.scala 693:122] - node _T_8200 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[ifu_mem_ctl.scala 694:37] - node _T_8201 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_8202 = and(_T_8200, _T_8201) @[ifu_mem_ctl.scala 694:59] - node _T_8203 = eq(perr_ic_index_ff, UInt<7>("h06b")) @[ifu_mem_ctl.scala 694:102] - node _T_8204 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_8205 = and(_T_8203, _T_8204) @[ifu_mem_ctl.scala 694:124] - node _T_8206 = or(_T_8202, _T_8205) @[ifu_mem_ctl.scala 694:81] - node _T_8207 = or(_T_8206, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8208 = bits(_T_8207, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][106] <= _T_8194 @[ifu_mem_ctl.scala 692:41] + node _T_8195 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8196 = eq(_T_8195, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8197 = and(ic_valid_ff, _T_8196) @[ifu_mem_ctl.scala 692:97] + node _T_8198 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8199 = and(_T_8197, _T_8198) @[ifu_mem_ctl.scala 692:122] + node _T_8200 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[ifu_mem_ctl.scala 693:37] + node _T_8201 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_8202 = and(_T_8200, _T_8201) @[ifu_mem_ctl.scala 693:59] + node _T_8203 = eq(perr_ic_index_ff, UInt<7>("h06b")) @[ifu_mem_ctl.scala 693:102] + node _T_8204 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_8205 = and(_T_8203, _T_8204) @[ifu_mem_ctl.scala 693:124] + node _T_8206 = or(_T_8202, _T_8205) @[ifu_mem_ctl.scala 693:81] + node _T_8207 = or(_T_8206, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8208 = bits(_T_8207, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8209 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8208 : @[Reg.scala 28:19] _T_8209 <= _T_8199 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][107] <= _T_8209 @[ifu_mem_ctl.scala 693:41] - node _T_8210 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8211 = eq(_T_8210, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8212 = and(ic_valid_ff, _T_8211) @[ifu_mem_ctl.scala 693:97] - node _T_8213 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8214 = and(_T_8212, _T_8213) @[ifu_mem_ctl.scala 693:122] - node _T_8215 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[ifu_mem_ctl.scala 694:37] - node _T_8216 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_8217 = and(_T_8215, _T_8216) @[ifu_mem_ctl.scala 694:59] - node _T_8218 = eq(perr_ic_index_ff, UInt<7>("h06c")) @[ifu_mem_ctl.scala 694:102] - node _T_8219 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_8220 = and(_T_8218, _T_8219) @[ifu_mem_ctl.scala 694:124] - node _T_8221 = or(_T_8217, _T_8220) @[ifu_mem_ctl.scala 694:81] - node _T_8222 = or(_T_8221, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8223 = bits(_T_8222, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][107] <= _T_8209 @[ifu_mem_ctl.scala 692:41] + node _T_8210 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8211 = eq(_T_8210, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8212 = and(ic_valid_ff, _T_8211) @[ifu_mem_ctl.scala 692:97] + node _T_8213 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8214 = and(_T_8212, _T_8213) @[ifu_mem_ctl.scala 692:122] + node _T_8215 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[ifu_mem_ctl.scala 693:37] + node _T_8216 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_8217 = and(_T_8215, _T_8216) @[ifu_mem_ctl.scala 693:59] + node _T_8218 = eq(perr_ic_index_ff, UInt<7>("h06c")) @[ifu_mem_ctl.scala 693:102] + node _T_8219 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_8220 = and(_T_8218, _T_8219) @[ifu_mem_ctl.scala 693:124] + node _T_8221 = or(_T_8217, _T_8220) @[ifu_mem_ctl.scala 693:81] + node _T_8222 = or(_T_8221, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8223 = bits(_T_8222, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8224 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8223 : @[Reg.scala 28:19] _T_8224 <= _T_8214 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][108] <= _T_8224 @[ifu_mem_ctl.scala 693:41] - node _T_8225 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8226 = eq(_T_8225, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8227 = and(ic_valid_ff, _T_8226) @[ifu_mem_ctl.scala 693:97] - node _T_8228 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8229 = and(_T_8227, _T_8228) @[ifu_mem_ctl.scala 693:122] - node _T_8230 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[ifu_mem_ctl.scala 694:37] - node _T_8231 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_8232 = and(_T_8230, _T_8231) @[ifu_mem_ctl.scala 694:59] - node _T_8233 = eq(perr_ic_index_ff, UInt<7>("h06d")) @[ifu_mem_ctl.scala 694:102] - node _T_8234 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_8235 = and(_T_8233, _T_8234) @[ifu_mem_ctl.scala 694:124] - node _T_8236 = or(_T_8232, _T_8235) @[ifu_mem_ctl.scala 694:81] - node _T_8237 = or(_T_8236, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8238 = bits(_T_8237, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][108] <= _T_8224 @[ifu_mem_ctl.scala 692:41] + node _T_8225 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8226 = eq(_T_8225, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8227 = and(ic_valid_ff, _T_8226) @[ifu_mem_ctl.scala 692:97] + node _T_8228 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8229 = and(_T_8227, _T_8228) @[ifu_mem_ctl.scala 692:122] + node _T_8230 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[ifu_mem_ctl.scala 693:37] + node _T_8231 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_8232 = and(_T_8230, _T_8231) @[ifu_mem_ctl.scala 693:59] + node _T_8233 = eq(perr_ic_index_ff, UInt<7>("h06d")) @[ifu_mem_ctl.scala 693:102] + node _T_8234 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_8235 = and(_T_8233, _T_8234) @[ifu_mem_ctl.scala 693:124] + node _T_8236 = or(_T_8232, _T_8235) @[ifu_mem_ctl.scala 693:81] + node _T_8237 = or(_T_8236, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8238 = bits(_T_8237, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8239 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8238 : @[Reg.scala 28:19] _T_8239 <= _T_8229 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][109] <= _T_8239 @[ifu_mem_ctl.scala 693:41] - node _T_8240 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8241 = eq(_T_8240, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8242 = and(ic_valid_ff, _T_8241) @[ifu_mem_ctl.scala 693:97] - node _T_8243 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8244 = and(_T_8242, _T_8243) @[ifu_mem_ctl.scala 693:122] - node _T_8245 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[ifu_mem_ctl.scala 694:37] - node _T_8246 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_8247 = and(_T_8245, _T_8246) @[ifu_mem_ctl.scala 694:59] - node _T_8248 = eq(perr_ic_index_ff, UInt<7>("h06e")) @[ifu_mem_ctl.scala 694:102] - node _T_8249 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_8250 = and(_T_8248, _T_8249) @[ifu_mem_ctl.scala 694:124] - node _T_8251 = or(_T_8247, _T_8250) @[ifu_mem_ctl.scala 694:81] - node _T_8252 = or(_T_8251, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8253 = bits(_T_8252, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][109] <= _T_8239 @[ifu_mem_ctl.scala 692:41] + node _T_8240 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8241 = eq(_T_8240, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8242 = and(ic_valid_ff, _T_8241) @[ifu_mem_ctl.scala 692:97] + node _T_8243 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8244 = and(_T_8242, _T_8243) @[ifu_mem_ctl.scala 692:122] + node _T_8245 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[ifu_mem_ctl.scala 693:37] + node _T_8246 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_8247 = and(_T_8245, _T_8246) @[ifu_mem_ctl.scala 693:59] + node _T_8248 = eq(perr_ic_index_ff, UInt<7>("h06e")) @[ifu_mem_ctl.scala 693:102] + node _T_8249 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_8250 = and(_T_8248, _T_8249) @[ifu_mem_ctl.scala 693:124] + node _T_8251 = or(_T_8247, _T_8250) @[ifu_mem_ctl.scala 693:81] + node _T_8252 = or(_T_8251, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8253 = bits(_T_8252, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8254 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8253 : @[Reg.scala 28:19] _T_8254 <= _T_8244 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][110] <= _T_8254 @[ifu_mem_ctl.scala 693:41] - node _T_8255 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8256 = eq(_T_8255, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8257 = and(ic_valid_ff, _T_8256) @[ifu_mem_ctl.scala 693:97] - node _T_8258 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8259 = and(_T_8257, _T_8258) @[ifu_mem_ctl.scala 693:122] - node _T_8260 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[ifu_mem_ctl.scala 694:37] - node _T_8261 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_8262 = and(_T_8260, _T_8261) @[ifu_mem_ctl.scala 694:59] - node _T_8263 = eq(perr_ic_index_ff, UInt<7>("h06f")) @[ifu_mem_ctl.scala 694:102] - node _T_8264 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_8265 = and(_T_8263, _T_8264) @[ifu_mem_ctl.scala 694:124] - node _T_8266 = or(_T_8262, _T_8265) @[ifu_mem_ctl.scala 694:81] - node _T_8267 = or(_T_8266, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8268 = bits(_T_8267, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][110] <= _T_8254 @[ifu_mem_ctl.scala 692:41] + node _T_8255 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8256 = eq(_T_8255, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8257 = and(ic_valid_ff, _T_8256) @[ifu_mem_ctl.scala 692:97] + node _T_8258 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8259 = and(_T_8257, _T_8258) @[ifu_mem_ctl.scala 692:122] + node _T_8260 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[ifu_mem_ctl.scala 693:37] + node _T_8261 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_8262 = and(_T_8260, _T_8261) @[ifu_mem_ctl.scala 693:59] + node _T_8263 = eq(perr_ic_index_ff, UInt<7>("h06f")) @[ifu_mem_ctl.scala 693:102] + node _T_8264 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_8265 = and(_T_8263, _T_8264) @[ifu_mem_ctl.scala 693:124] + node _T_8266 = or(_T_8262, _T_8265) @[ifu_mem_ctl.scala 693:81] + node _T_8267 = or(_T_8266, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8268 = bits(_T_8267, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8269 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8268 : @[Reg.scala 28:19] _T_8269 <= _T_8259 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][111] <= _T_8269 @[ifu_mem_ctl.scala 693:41] - node _T_8270 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8271 = eq(_T_8270, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8272 = and(ic_valid_ff, _T_8271) @[ifu_mem_ctl.scala 693:97] - node _T_8273 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8274 = and(_T_8272, _T_8273) @[ifu_mem_ctl.scala 693:122] - node _T_8275 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[ifu_mem_ctl.scala 694:37] - node _T_8276 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_8277 = and(_T_8275, _T_8276) @[ifu_mem_ctl.scala 694:59] - node _T_8278 = eq(perr_ic_index_ff, UInt<7>("h070")) @[ifu_mem_ctl.scala 694:102] - node _T_8279 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_8280 = and(_T_8278, _T_8279) @[ifu_mem_ctl.scala 694:124] - node _T_8281 = or(_T_8277, _T_8280) @[ifu_mem_ctl.scala 694:81] - node _T_8282 = or(_T_8281, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8283 = bits(_T_8282, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][111] <= _T_8269 @[ifu_mem_ctl.scala 692:41] + node _T_8270 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8271 = eq(_T_8270, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8272 = and(ic_valid_ff, _T_8271) @[ifu_mem_ctl.scala 692:97] + node _T_8273 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8274 = and(_T_8272, _T_8273) @[ifu_mem_ctl.scala 692:122] + node _T_8275 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[ifu_mem_ctl.scala 693:37] + node _T_8276 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_8277 = and(_T_8275, _T_8276) @[ifu_mem_ctl.scala 693:59] + node _T_8278 = eq(perr_ic_index_ff, UInt<7>("h070")) @[ifu_mem_ctl.scala 693:102] + node _T_8279 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_8280 = and(_T_8278, _T_8279) @[ifu_mem_ctl.scala 693:124] + node _T_8281 = or(_T_8277, _T_8280) @[ifu_mem_ctl.scala 693:81] + node _T_8282 = or(_T_8281, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8283 = bits(_T_8282, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8284 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8283 : @[Reg.scala 28:19] _T_8284 <= _T_8274 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][112] <= _T_8284 @[ifu_mem_ctl.scala 693:41] - node _T_8285 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8286 = eq(_T_8285, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8287 = and(ic_valid_ff, _T_8286) @[ifu_mem_ctl.scala 693:97] - node _T_8288 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8289 = and(_T_8287, _T_8288) @[ifu_mem_ctl.scala 693:122] - node _T_8290 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[ifu_mem_ctl.scala 694:37] - node _T_8291 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_8292 = and(_T_8290, _T_8291) @[ifu_mem_ctl.scala 694:59] - node _T_8293 = eq(perr_ic_index_ff, UInt<7>("h071")) @[ifu_mem_ctl.scala 694:102] - node _T_8294 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_8295 = and(_T_8293, _T_8294) @[ifu_mem_ctl.scala 694:124] - node _T_8296 = or(_T_8292, _T_8295) @[ifu_mem_ctl.scala 694:81] - node _T_8297 = or(_T_8296, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8298 = bits(_T_8297, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][112] <= _T_8284 @[ifu_mem_ctl.scala 692:41] + node _T_8285 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8286 = eq(_T_8285, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8287 = and(ic_valid_ff, _T_8286) @[ifu_mem_ctl.scala 692:97] + node _T_8288 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8289 = and(_T_8287, _T_8288) @[ifu_mem_ctl.scala 692:122] + node _T_8290 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[ifu_mem_ctl.scala 693:37] + node _T_8291 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_8292 = and(_T_8290, _T_8291) @[ifu_mem_ctl.scala 693:59] + node _T_8293 = eq(perr_ic_index_ff, UInt<7>("h071")) @[ifu_mem_ctl.scala 693:102] + node _T_8294 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_8295 = and(_T_8293, _T_8294) @[ifu_mem_ctl.scala 693:124] + node _T_8296 = or(_T_8292, _T_8295) @[ifu_mem_ctl.scala 693:81] + node _T_8297 = or(_T_8296, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8298 = bits(_T_8297, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8299 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8298 : @[Reg.scala 28:19] _T_8299 <= _T_8289 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][113] <= _T_8299 @[ifu_mem_ctl.scala 693:41] - node _T_8300 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8301 = eq(_T_8300, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8302 = and(ic_valid_ff, _T_8301) @[ifu_mem_ctl.scala 693:97] - node _T_8303 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8304 = and(_T_8302, _T_8303) @[ifu_mem_ctl.scala 693:122] - node _T_8305 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[ifu_mem_ctl.scala 694:37] - node _T_8306 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_8307 = and(_T_8305, _T_8306) @[ifu_mem_ctl.scala 694:59] - node _T_8308 = eq(perr_ic_index_ff, UInt<7>("h072")) @[ifu_mem_ctl.scala 694:102] - node _T_8309 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_8310 = and(_T_8308, _T_8309) @[ifu_mem_ctl.scala 694:124] - node _T_8311 = or(_T_8307, _T_8310) @[ifu_mem_ctl.scala 694:81] - node _T_8312 = or(_T_8311, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8313 = bits(_T_8312, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][113] <= _T_8299 @[ifu_mem_ctl.scala 692:41] + node _T_8300 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8301 = eq(_T_8300, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8302 = and(ic_valid_ff, _T_8301) @[ifu_mem_ctl.scala 692:97] + node _T_8303 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8304 = and(_T_8302, _T_8303) @[ifu_mem_ctl.scala 692:122] + node _T_8305 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[ifu_mem_ctl.scala 693:37] + node _T_8306 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_8307 = and(_T_8305, _T_8306) @[ifu_mem_ctl.scala 693:59] + node _T_8308 = eq(perr_ic_index_ff, UInt<7>("h072")) @[ifu_mem_ctl.scala 693:102] + node _T_8309 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_8310 = and(_T_8308, _T_8309) @[ifu_mem_ctl.scala 693:124] + node _T_8311 = or(_T_8307, _T_8310) @[ifu_mem_ctl.scala 693:81] + node _T_8312 = or(_T_8311, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8313 = bits(_T_8312, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8314 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8313 : @[Reg.scala 28:19] _T_8314 <= _T_8304 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][114] <= _T_8314 @[ifu_mem_ctl.scala 693:41] - node _T_8315 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8316 = eq(_T_8315, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8317 = and(ic_valid_ff, _T_8316) @[ifu_mem_ctl.scala 693:97] - node _T_8318 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8319 = and(_T_8317, _T_8318) @[ifu_mem_ctl.scala 693:122] - node _T_8320 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[ifu_mem_ctl.scala 694:37] - node _T_8321 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_8322 = and(_T_8320, _T_8321) @[ifu_mem_ctl.scala 694:59] - node _T_8323 = eq(perr_ic_index_ff, UInt<7>("h073")) @[ifu_mem_ctl.scala 694:102] - node _T_8324 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_8325 = and(_T_8323, _T_8324) @[ifu_mem_ctl.scala 694:124] - node _T_8326 = or(_T_8322, _T_8325) @[ifu_mem_ctl.scala 694:81] - node _T_8327 = or(_T_8326, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8328 = bits(_T_8327, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][114] <= _T_8314 @[ifu_mem_ctl.scala 692:41] + node _T_8315 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8316 = eq(_T_8315, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8317 = and(ic_valid_ff, _T_8316) @[ifu_mem_ctl.scala 692:97] + node _T_8318 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8319 = and(_T_8317, _T_8318) @[ifu_mem_ctl.scala 692:122] + node _T_8320 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[ifu_mem_ctl.scala 693:37] + node _T_8321 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_8322 = and(_T_8320, _T_8321) @[ifu_mem_ctl.scala 693:59] + node _T_8323 = eq(perr_ic_index_ff, UInt<7>("h073")) @[ifu_mem_ctl.scala 693:102] + node _T_8324 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_8325 = and(_T_8323, _T_8324) @[ifu_mem_ctl.scala 693:124] + node _T_8326 = or(_T_8322, _T_8325) @[ifu_mem_ctl.scala 693:81] + node _T_8327 = or(_T_8326, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8328 = bits(_T_8327, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8329 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8328 : @[Reg.scala 28:19] _T_8329 <= _T_8319 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][115] <= _T_8329 @[ifu_mem_ctl.scala 693:41] - node _T_8330 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8331 = eq(_T_8330, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8332 = and(ic_valid_ff, _T_8331) @[ifu_mem_ctl.scala 693:97] - node _T_8333 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8334 = and(_T_8332, _T_8333) @[ifu_mem_ctl.scala 693:122] - node _T_8335 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[ifu_mem_ctl.scala 694:37] - node _T_8336 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_8337 = and(_T_8335, _T_8336) @[ifu_mem_ctl.scala 694:59] - node _T_8338 = eq(perr_ic_index_ff, UInt<7>("h074")) @[ifu_mem_ctl.scala 694:102] - node _T_8339 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_8340 = and(_T_8338, _T_8339) @[ifu_mem_ctl.scala 694:124] - node _T_8341 = or(_T_8337, _T_8340) @[ifu_mem_ctl.scala 694:81] - node _T_8342 = or(_T_8341, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8343 = bits(_T_8342, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][115] <= _T_8329 @[ifu_mem_ctl.scala 692:41] + node _T_8330 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8331 = eq(_T_8330, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8332 = and(ic_valid_ff, _T_8331) @[ifu_mem_ctl.scala 692:97] + node _T_8333 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8334 = and(_T_8332, _T_8333) @[ifu_mem_ctl.scala 692:122] + node _T_8335 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[ifu_mem_ctl.scala 693:37] + node _T_8336 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_8337 = and(_T_8335, _T_8336) @[ifu_mem_ctl.scala 693:59] + node _T_8338 = eq(perr_ic_index_ff, UInt<7>("h074")) @[ifu_mem_ctl.scala 693:102] + node _T_8339 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_8340 = and(_T_8338, _T_8339) @[ifu_mem_ctl.scala 693:124] + node _T_8341 = or(_T_8337, _T_8340) @[ifu_mem_ctl.scala 693:81] + node _T_8342 = or(_T_8341, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8343 = bits(_T_8342, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8344 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8343 : @[Reg.scala 28:19] _T_8344 <= _T_8334 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][116] <= _T_8344 @[ifu_mem_ctl.scala 693:41] - node _T_8345 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8346 = eq(_T_8345, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8347 = and(ic_valid_ff, _T_8346) @[ifu_mem_ctl.scala 693:97] - node _T_8348 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8349 = and(_T_8347, _T_8348) @[ifu_mem_ctl.scala 693:122] - node _T_8350 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[ifu_mem_ctl.scala 694:37] - node _T_8351 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_8352 = and(_T_8350, _T_8351) @[ifu_mem_ctl.scala 694:59] - node _T_8353 = eq(perr_ic_index_ff, UInt<7>("h075")) @[ifu_mem_ctl.scala 694:102] - node _T_8354 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_8355 = and(_T_8353, _T_8354) @[ifu_mem_ctl.scala 694:124] - node _T_8356 = or(_T_8352, _T_8355) @[ifu_mem_ctl.scala 694:81] - node _T_8357 = or(_T_8356, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8358 = bits(_T_8357, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][116] <= _T_8344 @[ifu_mem_ctl.scala 692:41] + node _T_8345 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8346 = eq(_T_8345, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8347 = and(ic_valid_ff, _T_8346) @[ifu_mem_ctl.scala 692:97] + node _T_8348 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8349 = and(_T_8347, _T_8348) @[ifu_mem_ctl.scala 692:122] + node _T_8350 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[ifu_mem_ctl.scala 693:37] + node _T_8351 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_8352 = and(_T_8350, _T_8351) @[ifu_mem_ctl.scala 693:59] + node _T_8353 = eq(perr_ic_index_ff, UInt<7>("h075")) @[ifu_mem_ctl.scala 693:102] + node _T_8354 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_8355 = and(_T_8353, _T_8354) @[ifu_mem_ctl.scala 693:124] + node _T_8356 = or(_T_8352, _T_8355) @[ifu_mem_ctl.scala 693:81] + node _T_8357 = or(_T_8356, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8358 = bits(_T_8357, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8359 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8358 : @[Reg.scala 28:19] _T_8359 <= _T_8349 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][117] <= _T_8359 @[ifu_mem_ctl.scala 693:41] - node _T_8360 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8361 = eq(_T_8360, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8362 = and(ic_valid_ff, _T_8361) @[ifu_mem_ctl.scala 693:97] - node _T_8363 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8364 = and(_T_8362, _T_8363) @[ifu_mem_ctl.scala 693:122] - node _T_8365 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[ifu_mem_ctl.scala 694:37] - node _T_8366 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_8367 = and(_T_8365, _T_8366) @[ifu_mem_ctl.scala 694:59] - node _T_8368 = eq(perr_ic_index_ff, UInt<7>("h076")) @[ifu_mem_ctl.scala 694:102] - node _T_8369 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_8370 = and(_T_8368, _T_8369) @[ifu_mem_ctl.scala 694:124] - node _T_8371 = or(_T_8367, _T_8370) @[ifu_mem_ctl.scala 694:81] - node _T_8372 = or(_T_8371, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8373 = bits(_T_8372, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][117] <= _T_8359 @[ifu_mem_ctl.scala 692:41] + node _T_8360 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8361 = eq(_T_8360, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8362 = and(ic_valid_ff, _T_8361) @[ifu_mem_ctl.scala 692:97] + node _T_8363 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8364 = and(_T_8362, _T_8363) @[ifu_mem_ctl.scala 692:122] + node _T_8365 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[ifu_mem_ctl.scala 693:37] + node _T_8366 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_8367 = and(_T_8365, _T_8366) @[ifu_mem_ctl.scala 693:59] + node _T_8368 = eq(perr_ic_index_ff, UInt<7>("h076")) @[ifu_mem_ctl.scala 693:102] + node _T_8369 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_8370 = and(_T_8368, _T_8369) @[ifu_mem_ctl.scala 693:124] + node _T_8371 = or(_T_8367, _T_8370) @[ifu_mem_ctl.scala 693:81] + node _T_8372 = or(_T_8371, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8373 = bits(_T_8372, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8374 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8373 : @[Reg.scala 28:19] _T_8374 <= _T_8364 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][118] <= _T_8374 @[ifu_mem_ctl.scala 693:41] - node _T_8375 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8376 = eq(_T_8375, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8377 = and(ic_valid_ff, _T_8376) @[ifu_mem_ctl.scala 693:97] - node _T_8378 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8379 = and(_T_8377, _T_8378) @[ifu_mem_ctl.scala 693:122] - node _T_8380 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[ifu_mem_ctl.scala 694:37] - node _T_8381 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_8382 = and(_T_8380, _T_8381) @[ifu_mem_ctl.scala 694:59] - node _T_8383 = eq(perr_ic_index_ff, UInt<7>("h077")) @[ifu_mem_ctl.scala 694:102] - node _T_8384 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_8385 = and(_T_8383, _T_8384) @[ifu_mem_ctl.scala 694:124] - node _T_8386 = or(_T_8382, _T_8385) @[ifu_mem_ctl.scala 694:81] - node _T_8387 = or(_T_8386, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8388 = bits(_T_8387, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][118] <= _T_8374 @[ifu_mem_ctl.scala 692:41] + node _T_8375 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8376 = eq(_T_8375, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8377 = and(ic_valid_ff, _T_8376) @[ifu_mem_ctl.scala 692:97] + node _T_8378 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8379 = and(_T_8377, _T_8378) @[ifu_mem_ctl.scala 692:122] + node _T_8380 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[ifu_mem_ctl.scala 693:37] + node _T_8381 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_8382 = and(_T_8380, _T_8381) @[ifu_mem_ctl.scala 693:59] + node _T_8383 = eq(perr_ic_index_ff, UInt<7>("h077")) @[ifu_mem_ctl.scala 693:102] + node _T_8384 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_8385 = and(_T_8383, _T_8384) @[ifu_mem_ctl.scala 693:124] + node _T_8386 = or(_T_8382, _T_8385) @[ifu_mem_ctl.scala 693:81] + node _T_8387 = or(_T_8386, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8388 = bits(_T_8387, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8389 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8388 : @[Reg.scala 28:19] _T_8389 <= _T_8379 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][119] <= _T_8389 @[ifu_mem_ctl.scala 693:41] - node _T_8390 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8391 = eq(_T_8390, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8392 = and(ic_valid_ff, _T_8391) @[ifu_mem_ctl.scala 693:97] - node _T_8393 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8394 = and(_T_8392, _T_8393) @[ifu_mem_ctl.scala 693:122] - node _T_8395 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[ifu_mem_ctl.scala 694:37] - node _T_8396 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_8397 = and(_T_8395, _T_8396) @[ifu_mem_ctl.scala 694:59] - node _T_8398 = eq(perr_ic_index_ff, UInt<7>("h078")) @[ifu_mem_ctl.scala 694:102] - node _T_8399 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_8400 = and(_T_8398, _T_8399) @[ifu_mem_ctl.scala 694:124] - node _T_8401 = or(_T_8397, _T_8400) @[ifu_mem_ctl.scala 694:81] - node _T_8402 = or(_T_8401, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8403 = bits(_T_8402, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][119] <= _T_8389 @[ifu_mem_ctl.scala 692:41] + node _T_8390 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8391 = eq(_T_8390, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8392 = and(ic_valid_ff, _T_8391) @[ifu_mem_ctl.scala 692:97] + node _T_8393 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8394 = and(_T_8392, _T_8393) @[ifu_mem_ctl.scala 692:122] + node _T_8395 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[ifu_mem_ctl.scala 693:37] + node _T_8396 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_8397 = and(_T_8395, _T_8396) @[ifu_mem_ctl.scala 693:59] + node _T_8398 = eq(perr_ic_index_ff, UInt<7>("h078")) @[ifu_mem_ctl.scala 693:102] + node _T_8399 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_8400 = and(_T_8398, _T_8399) @[ifu_mem_ctl.scala 693:124] + node _T_8401 = or(_T_8397, _T_8400) @[ifu_mem_ctl.scala 693:81] + node _T_8402 = or(_T_8401, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8403 = bits(_T_8402, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8404 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8403 : @[Reg.scala 28:19] _T_8404 <= _T_8394 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][120] <= _T_8404 @[ifu_mem_ctl.scala 693:41] - node _T_8405 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8406 = eq(_T_8405, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8407 = and(ic_valid_ff, _T_8406) @[ifu_mem_ctl.scala 693:97] - node _T_8408 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8409 = and(_T_8407, _T_8408) @[ifu_mem_ctl.scala 693:122] - node _T_8410 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[ifu_mem_ctl.scala 694:37] - node _T_8411 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_8412 = and(_T_8410, _T_8411) @[ifu_mem_ctl.scala 694:59] - node _T_8413 = eq(perr_ic_index_ff, UInt<7>("h079")) @[ifu_mem_ctl.scala 694:102] - node _T_8414 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_8415 = and(_T_8413, _T_8414) @[ifu_mem_ctl.scala 694:124] - node _T_8416 = or(_T_8412, _T_8415) @[ifu_mem_ctl.scala 694:81] - node _T_8417 = or(_T_8416, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8418 = bits(_T_8417, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][120] <= _T_8404 @[ifu_mem_ctl.scala 692:41] + node _T_8405 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8406 = eq(_T_8405, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8407 = and(ic_valid_ff, _T_8406) @[ifu_mem_ctl.scala 692:97] + node _T_8408 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8409 = and(_T_8407, _T_8408) @[ifu_mem_ctl.scala 692:122] + node _T_8410 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[ifu_mem_ctl.scala 693:37] + node _T_8411 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_8412 = and(_T_8410, _T_8411) @[ifu_mem_ctl.scala 693:59] + node _T_8413 = eq(perr_ic_index_ff, UInt<7>("h079")) @[ifu_mem_ctl.scala 693:102] + node _T_8414 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_8415 = and(_T_8413, _T_8414) @[ifu_mem_ctl.scala 693:124] + node _T_8416 = or(_T_8412, _T_8415) @[ifu_mem_ctl.scala 693:81] + node _T_8417 = or(_T_8416, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8418 = bits(_T_8417, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8419 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8418 : @[Reg.scala 28:19] _T_8419 <= _T_8409 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][121] <= _T_8419 @[ifu_mem_ctl.scala 693:41] - node _T_8420 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8421 = eq(_T_8420, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8422 = and(ic_valid_ff, _T_8421) @[ifu_mem_ctl.scala 693:97] - node _T_8423 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8424 = and(_T_8422, _T_8423) @[ifu_mem_ctl.scala 693:122] - node _T_8425 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[ifu_mem_ctl.scala 694:37] - node _T_8426 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_8427 = and(_T_8425, _T_8426) @[ifu_mem_ctl.scala 694:59] - node _T_8428 = eq(perr_ic_index_ff, UInt<7>("h07a")) @[ifu_mem_ctl.scala 694:102] - node _T_8429 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_8430 = and(_T_8428, _T_8429) @[ifu_mem_ctl.scala 694:124] - node _T_8431 = or(_T_8427, _T_8430) @[ifu_mem_ctl.scala 694:81] - node _T_8432 = or(_T_8431, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8433 = bits(_T_8432, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][121] <= _T_8419 @[ifu_mem_ctl.scala 692:41] + node _T_8420 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8421 = eq(_T_8420, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8422 = and(ic_valid_ff, _T_8421) @[ifu_mem_ctl.scala 692:97] + node _T_8423 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8424 = and(_T_8422, _T_8423) @[ifu_mem_ctl.scala 692:122] + node _T_8425 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[ifu_mem_ctl.scala 693:37] + node _T_8426 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_8427 = and(_T_8425, _T_8426) @[ifu_mem_ctl.scala 693:59] + node _T_8428 = eq(perr_ic_index_ff, UInt<7>("h07a")) @[ifu_mem_ctl.scala 693:102] + node _T_8429 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_8430 = and(_T_8428, _T_8429) @[ifu_mem_ctl.scala 693:124] + node _T_8431 = or(_T_8427, _T_8430) @[ifu_mem_ctl.scala 693:81] + node _T_8432 = or(_T_8431, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8433 = bits(_T_8432, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8434 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8433 : @[Reg.scala 28:19] _T_8434 <= _T_8424 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][122] <= _T_8434 @[ifu_mem_ctl.scala 693:41] - node _T_8435 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8436 = eq(_T_8435, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8437 = and(ic_valid_ff, _T_8436) @[ifu_mem_ctl.scala 693:97] - node _T_8438 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8439 = and(_T_8437, _T_8438) @[ifu_mem_ctl.scala 693:122] - node _T_8440 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[ifu_mem_ctl.scala 694:37] - node _T_8441 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_8442 = and(_T_8440, _T_8441) @[ifu_mem_ctl.scala 694:59] - node _T_8443 = eq(perr_ic_index_ff, UInt<7>("h07b")) @[ifu_mem_ctl.scala 694:102] - node _T_8444 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_8445 = and(_T_8443, _T_8444) @[ifu_mem_ctl.scala 694:124] - node _T_8446 = or(_T_8442, _T_8445) @[ifu_mem_ctl.scala 694:81] - node _T_8447 = or(_T_8446, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8448 = bits(_T_8447, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][122] <= _T_8434 @[ifu_mem_ctl.scala 692:41] + node _T_8435 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8436 = eq(_T_8435, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8437 = and(ic_valid_ff, _T_8436) @[ifu_mem_ctl.scala 692:97] + node _T_8438 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8439 = and(_T_8437, _T_8438) @[ifu_mem_ctl.scala 692:122] + node _T_8440 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[ifu_mem_ctl.scala 693:37] + node _T_8441 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_8442 = and(_T_8440, _T_8441) @[ifu_mem_ctl.scala 693:59] + node _T_8443 = eq(perr_ic_index_ff, UInt<7>("h07b")) @[ifu_mem_ctl.scala 693:102] + node _T_8444 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_8445 = and(_T_8443, _T_8444) @[ifu_mem_ctl.scala 693:124] + node _T_8446 = or(_T_8442, _T_8445) @[ifu_mem_ctl.scala 693:81] + node _T_8447 = or(_T_8446, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8448 = bits(_T_8447, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8449 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8448 : @[Reg.scala 28:19] _T_8449 <= _T_8439 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][123] <= _T_8449 @[ifu_mem_ctl.scala 693:41] - node _T_8450 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8451 = eq(_T_8450, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8452 = and(ic_valid_ff, _T_8451) @[ifu_mem_ctl.scala 693:97] - node _T_8453 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8454 = and(_T_8452, _T_8453) @[ifu_mem_ctl.scala 693:122] - node _T_8455 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[ifu_mem_ctl.scala 694:37] - node _T_8456 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_8457 = and(_T_8455, _T_8456) @[ifu_mem_ctl.scala 694:59] - node _T_8458 = eq(perr_ic_index_ff, UInt<7>("h07c")) @[ifu_mem_ctl.scala 694:102] - node _T_8459 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_8460 = and(_T_8458, _T_8459) @[ifu_mem_ctl.scala 694:124] - node _T_8461 = or(_T_8457, _T_8460) @[ifu_mem_ctl.scala 694:81] - node _T_8462 = or(_T_8461, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8463 = bits(_T_8462, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][123] <= _T_8449 @[ifu_mem_ctl.scala 692:41] + node _T_8450 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8451 = eq(_T_8450, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8452 = and(ic_valid_ff, _T_8451) @[ifu_mem_ctl.scala 692:97] + node _T_8453 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8454 = and(_T_8452, _T_8453) @[ifu_mem_ctl.scala 692:122] + node _T_8455 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[ifu_mem_ctl.scala 693:37] + node _T_8456 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_8457 = and(_T_8455, _T_8456) @[ifu_mem_ctl.scala 693:59] + node _T_8458 = eq(perr_ic_index_ff, UInt<7>("h07c")) @[ifu_mem_ctl.scala 693:102] + node _T_8459 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_8460 = and(_T_8458, _T_8459) @[ifu_mem_ctl.scala 693:124] + node _T_8461 = or(_T_8457, _T_8460) @[ifu_mem_ctl.scala 693:81] + node _T_8462 = or(_T_8461, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8463 = bits(_T_8462, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8464 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8463 : @[Reg.scala 28:19] _T_8464 <= _T_8454 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][124] <= _T_8464 @[ifu_mem_ctl.scala 693:41] - node _T_8465 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8466 = eq(_T_8465, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8467 = and(ic_valid_ff, _T_8466) @[ifu_mem_ctl.scala 693:97] - node _T_8468 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8469 = and(_T_8467, _T_8468) @[ifu_mem_ctl.scala 693:122] - node _T_8470 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[ifu_mem_ctl.scala 694:37] - node _T_8471 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_8472 = and(_T_8470, _T_8471) @[ifu_mem_ctl.scala 694:59] - node _T_8473 = eq(perr_ic_index_ff, UInt<7>("h07d")) @[ifu_mem_ctl.scala 694:102] - node _T_8474 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_8475 = and(_T_8473, _T_8474) @[ifu_mem_ctl.scala 694:124] - node _T_8476 = or(_T_8472, _T_8475) @[ifu_mem_ctl.scala 694:81] - node _T_8477 = or(_T_8476, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8478 = bits(_T_8477, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][124] <= _T_8464 @[ifu_mem_ctl.scala 692:41] + node _T_8465 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8466 = eq(_T_8465, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8467 = and(ic_valid_ff, _T_8466) @[ifu_mem_ctl.scala 692:97] + node _T_8468 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8469 = and(_T_8467, _T_8468) @[ifu_mem_ctl.scala 692:122] + node _T_8470 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[ifu_mem_ctl.scala 693:37] + node _T_8471 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_8472 = and(_T_8470, _T_8471) @[ifu_mem_ctl.scala 693:59] + node _T_8473 = eq(perr_ic_index_ff, UInt<7>("h07d")) @[ifu_mem_ctl.scala 693:102] + node _T_8474 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_8475 = and(_T_8473, _T_8474) @[ifu_mem_ctl.scala 693:124] + node _T_8476 = or(_T_8472, _T_8475) @[ifu_mem_ctl.scala 693:81] + node _T_8477 = or(_T_8476, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8478 = bits(_T_8477, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8479 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8478 : @[Reg.scala 28:19] _T_8479 <= _T_8469 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][125] <= _T_8479 @[ifu_mem_ctl.scala 693:41] - node _T_8480 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8481 = eq(_T_8480, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8482 = and(ic_valid_ff, _T_8481) @[ifu_mem_ctl.scala 693:97] - node _T_8483 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8484 = and(_T_8482, _T_8483) @[ifu_mem_ctl.scala 693:122] - node _T_8485 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[ifu_mem_ctl.scala 694:37] - node _T_8486 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_8487 = and(_T_8485, _T_8486) @[ifu_mem_ctl.scala 694:59] - node _T_8488 = eq(perr_ic_index_ff, UInt<7>("h07e")) @[ifu_mem_ctl.scala 694:102] - node _T_8489 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_8490 = and(_T_8488, _T_8489) @[ifu_mem_ctl.scala 694:124] - node _T_8491 = or(_T_8487, _T_8490) @[ifu_mem_ctl.scala 694:81] - node _T_8492 = or(_T_8491, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8493 = bits(_T_8492, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][125] <= _T_8479 @[ifu_mem_ctl.scala 692:41] + node _T_8480 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8481 = eq(_T_8480, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8482 = and(ic_valid_ff, _T_8481) @[ifu_mem_ctl.scala 692:97] + node _T_8483 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8484 = and(_T_8482, _T_8483) @[ifu_mem_ctl.scala 692:122] + node _T_8485 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[ifu_mem_ctl.scala 693:37] + node _T_8486 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_8487 = and(_T_8485, _T_8486) @[ifu_mem_ctl.scala 693:59] + node _T_8488 = eq(perr_ic_index_ff, UInt<7>("h07e")) @[ifu_mem_ctl.scala 693:102] + node _T_8489 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_8490 = and(_T_8488, _T_8489) @[ifu_mem_ctl.scala 693:124] + node _T_8491 = or(_T_8487, _T_8490) @[ifu_mem_ctl.scala 693:81] + node _T_8492 = or(_T_8491, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8493 = bits(_T_8492, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8494 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8493 : @[Reg.scala 28:19] _T_8494 <= _T_8484 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][126] <= _T_8494 @[ifu_mem_ctl.scala 693:41] - node _T_8495 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8496 = eq(_T_8495, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8497 = and(ic_valid_ff, _T_8496) @[ifu_mem_ctl.scala 693:97] - node _T_8498 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8499 = and(_T_8497, _T_8498) @[ifu_mem_ctl.scala 693:122] - node _T_8500 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[ifu_mem_ctl.scala 694:37] - node _T_8501 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 694:76] - node _T_8502 = and(_T_8500, _T_8501) @[ifu_mem_ctl.scala 694:59] - node _T_8503 = eq(perr_ic_index_ff, UInt<7>("h07f")) @[ifu_mem_ctl.scala 694:102] - node _T_8504 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 694:142] - node _T_8505 = and(_T_8503, _T_8504) @[ifu_mem_ctl.scala 694:124] - node _T_8506 = or(_T_8502, _T_8505) @[ifu_mem_ctl.scala 694:81] - node _T_8507 = or(_T_8506, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8508 = bits(_T_8507, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][126] <= _T_8494 @[ifu_mem_ctl.scala 692:41] + node _T_8495 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8496 = eq(_T_8495, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8497 = and(ic_valid_ff, _T_8496) @[ifu_mem_ctl.scala 692:97] + node _T_8498 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8499 = and(_T_8497, _T_8498) @[ifu_mem_ctl.scala 692:122] + node _T_8500 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[ifu_mem_ctl.scala 693:37] + node _T_8501 = bits(ifu_tag_wren_ff, 0, 0) @[ifu_mem_ctl.scala 693:76] + node _T_8502 = and(_T_8500, _T_8501) @[ifu_mem_ctl.scala 693:59] + node _T_8503 = eq(perr_ic_index_ff, UInt<7>("h07f")) @[ifu_mem_ctl.scala 693:102] + node _T_8504 = bits(perr_err_inv_way, 0, 0) @[ifu_mem_ctl.scala 693:142] + node _T_8505 = and(_T_8503, _T_8504) @[ifu_mem_ctl.scala 693:124] + node _T_8506 = or(_T_8502, _T_8505) @[ifu_mem_ctl.scala 693:81] + node _T_8507 = or(_T_8506, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8508 = bits(_T_8507, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8509 : UInt<1>, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8508 : @[Reg.scala 28:19] _T_8509 <= _T_8499 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][127] <= _T_8509 @[ifu_mem_ctl.scala 693:41] - node _T_8510 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8511 = eq(_T_8510, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8512 = and(ic_valid_ff, _T_8511) @[ifu_mem_ctl.scala 693:97] - node _T_8513 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8514 = and(_T_8512, _T_8513) @[ifu_mem_ctl.scala 693:122] - node _T_8515 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[ifu_mem_ctl.scala 694:37] - node _T_8516 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_8517 = and(_T_8515, _T_8516) @[ifu_mem_ctl.scala 694:59] - node _T_8518 = eq(perr_ic_index_ff, UInt<7>("h060")) @[ifu_mem_ctl.scala 694:102] - node _T_8519 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_8520 = and(_T_8518, _T_8519) @[ifu_mem_ctl.scala 694:124] - node _T_8521 = or(_T_8517, _T_8520) @[ifu_mem_ctl.scala 694:81] - node _T_8522 = or(_T_8521, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8523 = bits(_T_8522, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[0][127] <= _T_8509 @[ifu_mem_ctl.scala 692:41] + node _T_8510 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8511 = eq(_T_8510, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8512 = and(ic_valid_ff, _T_8511) @[ifu_mem_ctl.scala 692:97] + node _T_8513 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8514 = and(_T_8512, _T_8513) @[ifu_mem_ctl.scala 692:122] + node _T_8515 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[ifu_mem_ctl.scala 693:37] + node _T_8516 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_8517 = and(_T_8515, _T_8516) @[ifu_mem_ctl.scala 693:59] + node _T_8518 = eq(perr_ic_index_ff, UInt<7>("h060")) @[ifu_mem_ctl.scala 693:102] + node _T_8519 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_8520 = and(_T_8518, _T_8519) @[ifu_mem_ctl.scala 693:124] + node _T_8521 = or(_T_8517, _T_8520) @[ifu_mem_ctl.scala 693:81] + node _T_8522 = or(_T_8521, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8523 = bits(_T_8522, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8524 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8523 : @[Reg.scala 28:19] _T_8524 <= _T_8514 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][96] <= _T_8524 @[ifu_mem_ctl.scala 693:41] - node _T_8525 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8526 = eq(_T_8525, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8527 = and(ic_valid_ff, _T_8526) @[ifu_mem_ctl.scala 693:97] - node _T_8528 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8529 = and(_T_8527, _T_8528) @[ifu_mem_ctl.scala 693:122] - node _T_8530 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[ifu_mem_ctl.scala 694:37] - node _T_8531 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_8532 = and(_T_8530, _T_8531) @[ifu_mem_ctl.scala 694:59] - node _T_8533 = eq(perr_ic_index_ff, UInt<7>("h061")) @[ifu_mem_ctl.scala 694:102] - node _T_8534 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_8535 = and(_T_8533, _T_8534) @[ifu_mem_ctl.scala 694:124] - node _T_8536 = or(_T_8532, _T_8535) @[ifu_mem_ctl.scala 694:81] - node _T_8537 = or(_T_8536, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8538 = bits(_T_8537, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][96] <= _T_8524 @[ifu_mem_ctl.scala 692:41] + node _T_8525 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8526 = eq(_T_8525, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8527 = and(ic_valid_ff, _T_8526) @[ifu_mem_ctl.scala 692:97] + node _T_8528 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8529 = and(_T_8527, _T_8528) @[ifu_mem_ctl.scala 692:122] + node _T_8530 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[ifu_mem_ctl.scala 693:37] + node _T_8531 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_8532 = and(_T_8530, _T_8531) @[ifu_mem_ctl.scala 693:59] + node _T_8533 = eq(perr_ic_index_ff, UInt<7>("h061")) @[ifu_mem_ctl.scala 693:102] + node _T_8534 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_8535 = and(_T_8533, _T_8534) @[ifu_mem_ctl.scala 693:124] + node _T_8536 = or(_T_8532, _T_8535) @[ifu_mem_ctl.scala 693:81] + node _T_8537 = or(_T_8536, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8538 = bits(_T_8537, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8539 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8538 : @[Reg.scala 28:19] _T_8539 <= _T_8529 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][97] <= _T_8539 @[ifu_mem_ctl.scala 693:41] - node _T_8540 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8541 = eq(_T_8540, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8542 = and(ic_valid_ff, _T_8541) @[ifu_mem_ctl.scala 693:97] - node _T_8543 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8544 = and(_T_8542, _T_8543) @[ifu_mem_ctl.scala 693:122] - node _T_8545 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[ifu_mem_ctl.scala 694:37] - node _T_8546 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_8547 = and(_T_8545, _T_8546) @[ifu_mem_ctl.scala 694:59] - node _T_8548 = eq(perr_ic_index_ff, UInt<7>("h062")) @[ifu_mem_ctl.scala 694:102] - node _T_8549 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_8550 = and(_T_8548, _T_8549) @[ifu_mem_ctl.scala 694:124] - node _T_8551 = or(_T_8547, _T_8550) @[ifu_mem_ctl.scala 694:81] - node _T_8552 = or(_T_8551, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8553 = bits(_T_8552, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][97] <= _T_8539 @[ifu_mem_ctl.scala 692:41] + node _T_8540 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8541 = eq(_T_8540, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8542 = and(ic_valid_ff, _T_8541) @[ifu_mem_ctl.scala 692:97] + node _T_8543 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8544 = and(_T_8542, _T_8543) @[ifu_mem_ctl.scala 692:122] + node _T_8545 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[ifu_mem_ctl.scala 693:37] + node _T_8546 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_8547 = and(_T_8545, _T_8546) @[ifu_mem_ctl.scala 693:59] + node _T_8548 = eq(perr_ic_index_ff, UInt<7>("h062")) @[ifu_mem_ctl.scala 693:102] + node _T_8549 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_8550 = and(_T_8548, _T_8549) @[ifu_mem_ctl.scala 693:124] + node _T_8551 = or(_T_8547, _T_8550) @[ifu_mem_ctl.scala 693:81] + node _T_8552 = or(_T_8551, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8553 = bits(_T_8552, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8554 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8553 : @[Reg.scala 28:19] _T_8554 <= _T_8544 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][98] <= _T_8554 @[ifu_mem_ctl.scala 693:41] - node _T_8555 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8556 = eq(_T_8555, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8557 = and(ic_valid_ff, _T_8556) @[ifu_mem_ctl.scala 693:97] - node _T_8558 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8559 = and(_T_8557, _T_8558) @[ifu_mem_ctl.scala 693:122] - node _T_8560 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[ifu_mem_ctl.scala 694:37] - node _T_8561 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_8562 = and(_T_8560, _T_8561) @[ifu_mem_ctl.scala 694:59] - node _T_8563 = eq(perr_ic_index_ff, UInt<7>("h063")) @[ifu_mem_ctl.scala 694:102] - node _T_8564 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_8565 = and(_T_8563, _T_8564) @[ifu_mem_ctl.scala 694:124] - node _T_8566 = or(_T_8562, _T_8565) @[ifu_mem_ctl.scala 694:81] - node _T_8567 = or(_T_8566, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8568 = bits(_T_8567, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][98] <= _T_8554 @[ifu_mem_ctl.scala 692:41] + node _T_8555 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8556 = eq(_T_8555, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8557 = and(ic_valid_ff, _T_8556) @[ifu_mem_ctl.scala 692:97] + node _T_8558 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8559 = and(_T_8557, _T_8558) @[ifu_mem_ctl.scala 692:122] + node _T_8560 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[ifu_mem_ctl.scala 693:37] + node _T_8561 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_8562 = and(_T_8560, _T_8561) @[ifu_mem_ctl.scala 693:59] + node _T_8563 = eq(perr_ic_index_ff, UInt<7>("h063")) @[ifu_mem_ctl.scala 693:102] + node _T_8564 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_8565 = and(_T_8563, _T_8564) @[ifu_mem_ctl.scala 693:124] + node _T_8566 = or(_T_8562, _T_8565) @[ifu_mem_ctl.scala 693:81] + node _T_8567 = or(_T_8566, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8568 = bits(_T_8567, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8569 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8568 : @[Reg.scala 28:19] _T_8569 <= _T_8559 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][99] <= _T_8569 @[ifu_mem_ctl.scala 693:41] - node _T_8570 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8571 = eq(_T_8570, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8572 = and(ic_valid_ff, _T_8571) @[ifu_mem_ctl.scala 693:97] - node _T_8573 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8574 = and(_T_8572, _T_8573) @[ifu_mem_ctl.scala 693:122] - node _T_8575 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[ifu_mem_ctl.scala 694:37] - node _T_8576 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_8577 = and(_T_8575, _T_8576) @[ifu_mem_ctl.scala 694:59] - node _T_8578 = eq(perr_ic_index_ff, UInt<7>("h064")) @[ifu_mem_ctl.scala 694:102] - node _T_8579 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_8580 = and(_T_8578, _T_8579) @[ifu_mem_ctl.scala 694:124] - node _T_8581 = or(_T_8577, _T_8580) @[ifu_mem_ctl.scala 694:81] - node _T_8582 = or(_T_8581, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8583 = bits(_T_8582, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][99] <= _T_8569 @[ifu_mem_ctl.scala 692:41] + node _T_8570 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8571 = eq(_T_8570, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8572 = and(ic_valid_ff, _T_8571) @[ifu_mem_ctl.scala 692:97] + node _T_8573 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8574 = and(_T_8572, _T_8573) @[ifu_mem_ctl.scala 692:122] + node _T_8575 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[ifu_mem_ctl.scala 693:37] + node _T_8576 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_8577 = and(_T_8575, _T_8576) @[ifu_mem_ctl.scala 693:59] + node _T_8578 = eq(perr_ic_index_ff, UInt<7>("h064")) @[ifu_mem_ctl.scala 693:102] + node _T_8579 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_8580 = and(_T_8578, _T_8579) @[ifu_mem_ctl.scala 693:124] + node _T_8581 = or(_T_8577, _T_8580) @[ifu_mem_ctl.scala 693:81] + node _T_8582 = or(_T_8581, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8583 = bits(_T_8582, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8584 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8583 : @[Reg.scala 28:19] _T_8584 <= _T_8574 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][100] <= _T_8584 @[ifu_mem_ctl.scala 693:41] - node _T_8585 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8586 = eq(_T_8585, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8587 = and(ic_valid_ff, _T_8586) @[ifu_mem_ctl.scala 693:97] - node _T_8588 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8589 = and(_T_8587, _T_8588) @[ifu_mem_ctl.scala 693:122] - node _T_8590 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[ifu_mem_ctl.scala 694:37] - node _T_8591 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_8592 = and(_T_8590, _T_8591) @[ifu_mem_ctl.scala 694:59] - node _T_8593 = eq(perr_ic_index_ff, UInt<7>("h065")) @[ifu_mem_ctl.scala 694:102] - node _T_8594 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_8595 = and(_T_8593, _T_8594) @[ifu_mem_ctl.scala 694:124] - node _T_8596 = or(_T_8592, _T_8595) @[ifu_mem_ctl.scala 694:81] - node _T_8597 = or(_T_8596, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8598 = bits(_T_8597, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][100] <= _T_8584 @[ifu_mem_ctl.scala 692:41] + node _T_8585 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8586 = eq(_T_8585, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8587 = and(ic_valid_ff, _T_8586) @[ifu_mem_ctl.scala 692:97] + node _T_8588 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8589 = and(_T_8587, _T_8588) @[ifu_mem_ctl.scala 692:122] + node _T_8590 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[ifu_mem_ctl.scala 693:37] + node _T_8591 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_8592 = and(_T_8590, _T_8591) @[ifu_mem_ctl.scala 693:59] + node _T_8593 = eq(perr_ic_index_ff, UInt<7>("h065")) @[ifu_mem_ctl.scala 693:102] + node _T_8594 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_8595 = and(_T_8593, _T_8594) @[ifu_mem_ctl.scala 693:124] + node _T_8596 = or(_T_8592, _T_8595) @[ifu_mem_ctl.scala 693:81] + node _T_8597 = or(_T_8596, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8598 = bits(_T_8597, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8599 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8598 : @[Reg.scala 28:19] _T_8599 <= _T_8589 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][101] <= _T_8599 @[ifu_mem_ctl.scala 693:41] - node _T_8600 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8601 = eq(_T_8600, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8602 = and(ic_valid_ff, _T_8601) @[ifu_mem_ctl.scala 693:97] - node _T_8603 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8604 = and(_T_8602, _T_8603) @[ifu_mem_ctl.scala 693:122] - node _T_8605 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[ifu_mem_ctl.scala 694:37] - node _T_8606 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_8607 = and(_T_8605, _T_8606) @[ifu_mem_ctl.scala 694:59] - node _T_8608 = eq(perr_ic_index_ff, UInt<7>("h066")) @[ifu_mem_ctl.scala 694:102] - node _T_8609 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_8610 = and(_T_8608, _T_8609) @[ifu_mem_ctl.scala 694:124] - node _T_8611 = or(_T_8607, _T_8610) @[ifu_mem_ctl.scala 694:81] - node _T_8612 = or(_T_8611, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8613 = bits(_T_8612, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][101] <= _T_8599 @[ifu_mem_ctl.scala 692:41] + node _T_8600 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8601 = eq(_T_8600, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8602 = and(ic_valid_ff, _T_8601) @[ifu_mem_ctl.scala 692:97] + node _T_8603 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8604 = and(_T_8602, _T_8603) @[ifu_mem_ctl.scala 692:122] + node _T_8605 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[ifu_mem_ctl.scala 693:37] + node _T_8606 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_8607 = and(_T_8605, _T_8606) @[ifu_mem_ctl.scala 693:59] + node _T_8608 = eq(perr_ic_index_ff, UInt<7>("h066")) @[ifu_mem_ctl.scala 693:102] + node _T_8609 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_8610 = and(_T_8608, _T_8609) @[ifu_mem_ctl.scala 693:124] + node _T_8611 = or(_T_8607, _T_8610) @[ifu_mem_ctl.scala 693:81] + node _T_8612 = or(_T_8611, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8613 = bits(_T_8612, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8614 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8613 : @[Reg.scala 28:19] _T_8614 <= _T_8604 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][102] <= _T_8614 @[ifu_mem_ctl.scala 693:41] - node _T_8615 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8616 = eq(_T_8615, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8617 = and(ic_valid_ff, _T_8616) @[ifu_mem_ctl.scala 693:97] - node _T_8618 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8619 = and(_T_8617, _T_8618) @[ifu_mem_ctl.scala 693:122] - node _T_8620 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[ifu_mem_ctl.scala 694:37] - node _T_8621 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_8622 = and(_T_8620, _T_8621) @[ifu_mem_ctl.scala 694:59] - node _T_8623 = eq(perr_ic_index_ff, UInt<7>("h067")) @[ifu_mem_ctl.scala 694:102] - node _T_8624 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_8625 = and(_T_8623, _T_8624) @[ifu_mem_ctl.scala 694:124] - node _T_8626 = or(_T_8622, _T_8625) @[ifu_mem_ctl.scala 694:81] - node _T_8627 = or(_T_8626, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8628 = bits(_T_8627, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][102] <= _T_8614 @[ifu_mem_ctl.scala 692:41] + node _T_8615 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8616 = eq(_T_8615, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8617 = and(ic_valid_ff, _T_8616) @[ifu_mem_ctl.scala 692:97] + node _T_8618 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8619 = and(_T_8617, _T_8618) @[ifu_mem_ctl.scala 692:122] + node _T_8620 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[ifu_mem_ctl.scala 693:37] + node _T_8621 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_8622 = and(_T_8620, _T_8621) @[ifu_mem_ctl.scala 693:59] + node _T_8623 = eq(perr_ic_index_ff, UInt<7>("h067")) @[ifu_mem_ctl.scala 693:102] + node _T_8624 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_8625 = and(_T_8623, _T_8624) @[ifu_mem_ctl.scala 693:124] + node _T_8626 = or(_T_8622, _T_8625) @[ifu_mem_ctl.scala 693:81] + node _T_8627 = or(_T_8626, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8628 = bits(_T_8627, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8629 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8628 : @[Reg.scala 28:19] _T_8629 <= _T_8619 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][103] <= _T_8629 @[ifu_mem_ctl.scala 693:41] - node _T_8630 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8631 = eq(_T_8630, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8632 = and(ic_valid_ff, _T_8631) @[ifu_mem_ctl.scala 693:97] - node _T_8633 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8634 = and(_T_8632, _T_8633) @[ifu_mem_ctl.scala 693:122] - node _T_8635 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[ifu_mem_ctl.scala 694:37] - node _T_8636 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_8637 = and(_T_8635, _T_8636) @[ifu_mem_ctl.scala 694:59] - node _T_8638 = eq(perr_ic_index_ff, UInt<7>("h068")) @[ifu_mem_ctl.scala 694:102] - node _T_8639 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_8640 = and(_T_8638, _T_8639) @[ifu_mem_ctl.scala 694:124] - node _T_8641 = or(_T_8637, _T_8640) @[ifu_mem_ctl.scala 694:81] - node _T_8642 = or(_T_8641, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8643 = bits(_T_8642, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][103] <= _T_8629 @[ifu_mem_ctl.scala 692:41] + node _T_8630 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8631 = eq(_T_8630, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8632 = and(ic_valid_ff, _T_8631) @[ifu_mem_ctl.scala 692:97] + node _T_8633 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8634 = and(_T_8632, _T_8633) @[ifu_mem_ctl.scala 692:122] + node _T_8635 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[ifu_mem_ctl.scala 693:37] + node _T_8636 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_8637 = and(_T_8635, _T_8636) @[ifu_mem_ctl.scala 693:59] + node _T_8638 = eq(perr_ic_index_ff, UInt<7>("h068")) @[ifu_mem_ctl.scala 693:102] + node _T_8639 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_8640 = and(_T_8638, _T_8639) @[ifu_mem_ctl.scala 693:124] + node _T_8641 = or(_T_8637, _T_8640) @[ifu_mem_ctl.scala 693:81] + node _T_8642 = or(_T_8641, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8643 = bits(_T_8642, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8644 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8643 : @[Reg.scala 28:19] _T_8644 <= _T_8634 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][104] <= _T_8644 @[ifu_mem_ctl.scala 693:41] - node _T_8645 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8646 = eq(_T_8645, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8647 = and(ic_valid_ff, _T_8646) @[ifu_mem_ctl.scala 693:97] - node _T_8648 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8649 = and(_T_8647, _T_8648) @[ifu_mem_ctl.scala 693:122] - node _T_8650 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[ifu_mem_ctl.scala 694:37] - node _T_8651 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_8652 = and(_T_8650, _T_8651) @[ifu_mem_ctl.scala 694:59] - node _T_8653 = eq(perr_ic_index_ff, UInt<7>("h069")) @[ifu_mem_ctl.scala 694:102] - node _T_8654 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_8655 = and(_T_8653, _T_8654) @[ifu_mem_ctl.scala 694:124] - node _T_8656 = or(_T_8652, _T_8655) @[ifu_mem_ctl.scala 694:81] - node _T_8657 = or(_T_8656, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8658 = bits(_T_8657, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][104] <= _T_8644 @[ifu_mem_ctl.scala 692:41] + node _T_8645 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8646 = eq(_T_8645, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8647 = and(ic_valid_ff, _T_8646) @[ifu_mem_ctl.scala 692:97] + node _T_8648 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8649 = and(_T_8647, _T_8648) @[ifu_mem_ctl.scala 692:122] + node _T_8650 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[ifu_mem_ctl.scala 693:37] + node _T_8651 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_8652 = and(_T_8650, _T_8651) @[ifu_mem_ctl.scala 693:59] + node _T_8653 = eq(perr_ic_index_ff, UInt<7>("h069")) @[ifu_mem_ctl.scala 693:102] + node _T_8654 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_8655 = and(_T_8653, _T_8654) @[ifu_mem_ctl.scala 693:124] + node _T_8656 = or(_T_8652, _T_8655) @[ifu_mem_ctl.scala 693:81] + node _T_8657 = or(_T_8656, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8658 = bits(_T_8657, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8659 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8658 : @[Reg.scala 28:19] _T_8659 <= _T_8649 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][105] <= _T_8659 @[ifu_mem_ctl.scala 693:41] - node _T_8660 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8661 = eq(_T_8660, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8662 = and(ic_valid_ff, _T_8661) @[ifu_mem_ctl.scala 693:97] - node _T_8663 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8664 = and(_T_8662, _T_8663) @[ifu_mem_ctl.scala 693:122] - node _T_8665 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[ifu_mem_ctl.scala 694:37] - node _T_8666 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_8667 = and(_T_8665, _T_8666) @[ifu_mem_ctl.scala 694:59] - node _T_8668 = eq(perr_ic_index_ff, UInt<7>("h06a")) @[ifu_mem_ctl.scala 694:102] - node _T_8669 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_8670 = and(_T_8668, _T_8669) @[ifu_mem_ctl.scala 694:124] - node _T_8671 = or(_T_8667, _T_8670) @[ifu_mem_ctl.scala 694:81] - node _T_8672 = or(_T_8671, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8673 = bits(_T_8672, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][105] <= _T_8659 @[ifu_mem_ctl.scala 692:41] + node _T_8660 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8661 = eq(_T_8660, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8662 = and(ic_valid_ff, _T_8661) @[ifu_mem_ctl.scala 692:97] + node _T_8663 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8664 = and(_T_8662, _T_8663) @[ifu_mem_ctl.scala 692:122] + node _T_8665 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[ifu_mem_ctl.scala 693:37] + node _T_8666 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_8667 = and(_T_8665, _T_8666) @[ifu_mem_ctl.scala 693:59] + node _T_8668 = eq(perr_ic_index_ff, UInt<7>("h06a")) @[ifu_mem_ctl.scala 693:102] + node _T_8669 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_8670 = and(_T_8668, _T_8669) @[ifu_mem_ctl.scala 693:124] + node _T_8671 = or(_T_8667, _T_8670) @[ifu_mem_ctl.scala 693:81] + node _T_8672 = or(_T_8671, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8673 = bits(_T_8672, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8674 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8673 : @[Reg.scala 28:19] _T_8674 <= _T_8664 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][106] <= _T_8674 @[ifu_mem_ctl.scala 693:41] - node _T_8675 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8676 = eq(_T_8675, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8677 = and(ic_valid_ff, _T_8676) @[ifu_mem_ctl.scala 693:97] - node _T_8678 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8679 = and(_T_8677, _T_8678) @[ifu_mem_ctl.scala 693:122] - node _T_8680 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[ifu_mem_ctl.scala 694:37] - node _T_8681 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_8682 = and(_T_8680, _T_8681) @[ifu_mem_ctl.scala 694:59] - node _T_8683 = eq(perr_ic_index_ff, UInt<7>("h06b")) @[ifu_mem_ctl.scala 694:102] - node _T_8684 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_8685 = and(_T_8683, _T_8684) @[ifu_mem_ctl.scala 694:124] - node _T_8686 = or(_T_8682, _T_8685) @[ifu_mem_ctl.scala 694:81] - node _T_8687 = or(_T_8686, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8688 = bits(_T_8687, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][106] <= _T_8674 @[ifu_mem_ctl.scala 692:41] + node _T_8675 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8676 = eq(_T_8675, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8677 = and(ic_valid_ff, _T_8676) @[ifu_mem_ctl.scala 692:97] + node _T_8678 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8679 = and(_T_8677, _T_8678) @[ifu_mem_ctl.scala 692:122] + node _T_8680 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[ifu_mem_ctl.scala 693:37] + node _T_8681 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_8682 = and(_T_8680, _T_8681) @[ifu_mem_ctl.scala 693:59] + node _T_8683 = eq(perr_ic_index_ff, UInt<7>("h06b")) @[ifu_mem_ctl.scala 693:102] + node _T_8684 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_8685 = and(_T_8683, _T_8684) @[ifu_mem_ctl.scala 693:124] + node _T_8686 = or(_T_8682, _T_8685) @[ifu_mem_ctl.scala 693:81] + node _T_8687 = or(_T_8686, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8688 = bits(_T_8687, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8689 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8688 : @[Reg.scala 28:19] _T_8689 <= _T_8679 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][107] <= _T_8689 @[ifu_mem_ctl.scala 693:41] - node _T_8690 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8691 = eq(_T_8690, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8692 = and(ic_valid_ff, _T_8691) @[ifu_mem_ctl.scala 693:97] - node _T_8693 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8694 = and(_T_8692, _T_8693) @[ifu_mem_ctl.scala 693:122] - node _T_8695 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[ifu_mem_ctl.scala 694:37] - node _T_8696 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_8697 = and(_T_8695, _T_8696) @[ifu_mem_ctl.scala 694:59] - node _T_8698 = eq(perr_ic_index_ff, UInt<7>("h06c")) @[ifu_mem_ctl.scala 694:102] - node _T_8699 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_8700 = and(_T_8698, _T_8699) @[ifu_mem_ctl.scala 694:124] - node _T_8701 = or(_T_8697, _T_8700) @[ifu_mem_ctl.scala 694:81] - node _T_8702 = or(_T_8701, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8703 = bits(_T_8702, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][107] <= _T_8689 @[ifu_mem_ctl.scala 692:41] + node _T_8690 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8691 = eq(_T_8690, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8692 = and(ic_valid_ff, _T_8691) @[ifu_mem_ctl.scala 692:97] + node _T_8693 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8694 = and(_T_8692, _T_8693) @[ifu_mem_ctl.scala 692:122] + node _T_8695 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[ifu_mem_ctl.scala 693:37] + node _T_8696 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_8697 = and(_T_8695, _T_8696) @[ifu_mem_ctl.scala 693:59] + node _T_8698 = eq(perr_ic_index_ff, UInt<7>("h06c")) @[ifu_mem_ctl.scala 693:102] + node _T_8699 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_8700 = and(_T_8698, _T_8699) @[ifu_mem_ctl.scala 693:124] + node _T_8701 = or(_T_8697, _T_8700) @[ifu_mem_ctl.scala 693:81] + node _T_8702 = or(_T_8701, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8703 = bits(_T_8702, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8704 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8703 : @[Reg.scala 28:19] _T_8704 <= _T_8694 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][108] <= _T_8704 @[ifu_mem_ctl.scala 693:41] - node _T_8705 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8706 = eq(_T_8705, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8707 = and(ic_valid_ff, _T_8706) @[ifu_mem_ctl.scala 693:97] - node _T_8708 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8709 = and(_T_8707, _T_8708) @[ifu_mem_ctl.scala 693:122] - node _T_8710 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[ifu_mem_ctl.scala 694:37] - node _T_8711 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_8712 = and(_T_8710, _T_8711) @[ifu_mem_ctl.scala 694:59] - node _T_8713 = eq(perr_ic_index_ff, UInt<7>("h06d")) @[ifu_mem_ctl.scala 694:102] - node _T_8714 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_8715 = and(_T_8713, _T_8714) @[ifu_mem_ctl.scala 694:124] - node _T_8716 = or(_T_8712, _T_8715) @[ifu_mem_ctl.scala 694:81] - node _T_8717 = or(_T_8716, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8718 = bits(_T_8717, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][108] <= _T_8704 @[ifu_mem_ctl.scala 692:41] + node _T_8705 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8706 = eq(_T_8705, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8707 = and(ic_valid_ff, _T_8706) @[ifu_mem_ctl.scala 692:97] + node _T_8708 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8709 = and(_T_8707, _T_8708) @[ifu_mem_ctl.scala 692:122] + node _T_8710 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[ifu_mem_ctl.scala 693:37] + node _T_8711 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_8712 = and(_T_8710, _T_8711) @[ifu_mem_ctl.scala 693:59] + node _T_8713 = eq(perr_ic_index_ff, UInt<7>("h06d")) @[ifu_mem_ctl.scala 693:102] + node _T_8714 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_8715 = and(_T_8713, _T_8714) @[ifu_mem_ctl.scala 693:124] + node _T_8716 = or(_T_8712, _T_8715) @[ifu_mem_ctl.scala 693:81] + node _T_8717 = or(_T_8716, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8718 = bits(_T_8717, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8719 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8718 : @[Reg.scala 28:19] _T_8719 <= _T_8709 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][109] <= _T_8719 @[ifu_mem_ctl.scala 693:41] - node _T_8720 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8721 = eq(_T_8720, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8722 = and(ic_valid_ff, _T_8721) @[ifu_mem_ctl.scala 693:97] - node _T_8723 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8724 = and(_T_8722, _T_8723) @[ifu_mem_ctl.scala 693:122] - node _T_8725 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[ifu_mem_ctl.scala 694:37] - node _T_8726 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_8727 = and(_T_8725, _T_8726) @[ifu_mem_ctl.scala 694:59] - node _T_8728 = eq(perr_ic_index_ff, UInt<7>("h06e")) @[ifu_mem_ctl.scala 694:102] - node _T_8729 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_8730 = and(_T_8728, _T_8729) @[ifu_mem_ctl.scala 694:124] - node _T_8731 = or(_T_8727, _T_8730) @[ifu_mem_ctl.scala 694:81] - node _T_8732 = or(_T_8731, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8733 = bits(_T_8732, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][109] <= _T_8719 @[ifu_mem_ctl.scala 692:41] + node _T_8720 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8721 = eq(_T_8720, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8722 = and(ic_valid_ff, _T_8721) @[ifu_mem_ctl.scala 692:97] + node _T_8723 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8724 = and(_T_8722, _T_8723) @[ifu_mem_ctl.scala 692:122] + node _T_8725 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[ifu_mem_ctl.scala 693:37] + node _T_8726 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_8727 = and(_T_8725, _T_8726) @[ifu_mem_ctl.scala 693:59] + node _T_8728 = eq(perr_ic_index_ff, UInt<7>("h06e")) @[ifu_mem_ctl.scala 693:102] + node _T_8729 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_8730 = and(_T_8728, _T_8729) @[ifu_mem_ctl.scala 693:124] + node _T_8731 = or(_T_8727, _T_8730) @[ifu_mem_ctl.scala 693:81] + node _T_8732 = or(_T_8731, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8733 = bits(_T_8732, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8734 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8733 : @[Reg.scala 28:19] _T_8734 <= _T_8724 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][110] <= _T_8734 @[ifu_mem_ctl.scala 693:41] - node _T_8735 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8736 = eq(_T_8735, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8737 = and(ic_valid_ff, _T_8736) @[ifu_mem_ctl.scala 693:97] - node _T_8738 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8739 = and(_T_8737, _T_8738) @[ifu_mem_ctl.scala 693:122] - node _T_8740 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[ifu_mem_ctl.scala 694:37] - node _T_8741 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_8742 = and(_T_8740, _T_8741) @[ifu_mem_ctl.scala 694:59] - node _T_8743 = eq(perr_ic_index_ff, UInt<7>("h06f")) @[ifu_mem_ctl.scala 694:102] - node _T_8744 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_8745 = and(_T_8743, _T_8744) @[ifu_mem_ctl.scala 694:124] - node _T_8746 = or(_T_8742, _T_8745) @[ifu_mem_ctl.scala 694:81] - node _T_8747 = or(_T_8746, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8748 = bits(_T_8747, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][110] <= _T_8734 @[ifu_mem_ctl.scala 692:41] + node _T_8735 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8736 = eq(_T_8735, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8737 = and(ic_valid_ff, _T_8736) @[ifu_mem_ctl.scala 692:97] + node _T_8738 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8739 = and(_T_8737, _T_8738) @[ifu_mem_ctl.scala 692:122] + node _T_8740 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[ifu_mem_ctl.scala 693:37] + node _T_8741 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_8742 = and(_T_8740, _T_8741) @[ifu_mem_ctl.scala 693:59] + node _T_8743 = eq(perr_ic_index_ff, UInt<7>("h06f")) @[ifu_mem_ctl.scala 693:102] + node _T_8744 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_8745 = and(_T_8743, _T_8744) @[ifu_mem_ctl.scala 693:124] + node _T_8746 = or(_T_8742, _T_8745) @[ifu_mem_ctl.scala 693:81] + node _T_8747 = or(_T_8746, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8748 = bits(_T_8747, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8749 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8748 : @[Reg.scala 28:19] _T_8749 <= _T_8739 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][111] <= _T_8749 @[ifu_mem_ctl.scala 693:41] - node _T_8750 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8751 = eq(_T_8750, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8752 = and(ic_valid_ff, _T_8751) @[ifu_mem_ctl.scala 693:97] - node _T_8753 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8754 = and(_T_8752, _T_8753) @[ifu_mem_ctl.scala 693:122] - node _T_8755 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[ifu_mem_ctl.scala 694:37] - node _T_8756 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_8757 = and(_T_8755, _T_8756) @[ifu_mem_ctl.scala 694:59] - node _T_8758 = eq(perr_ic_index_ff, UInt<7>("h070")) @[ifu_mem_ctl.scala 694:102] - node _T_8759 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_8760 = and(_T_8758, _T_8759) @[ifu_mem_ctl.scala 694:124] - node _T_8761 = or(_T_8757, _T_8760) @[ifu_mem_ctl.scala 694:81] - node _T_8762 = or(_T_8761, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8763 = bits(_T_8762, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][111] <= _T_8749 @[ifu_mem_ctl.scala 692:41] + node _T_8750 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8751 = eq(_T_8750, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8752 = and(ic_valid_ff, _T_8751) @[ifu_mem_ctl.scala 692:97] + node _T_8753 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8754 = and(_T_8752, _T_8753) @[ifu_mem_ctl.scala 692:122] + node _T_8755 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[ifu_mem_ctl.scala 693:37] + node _T_8756 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_8757 = and(_T_8755, _T_8756) @[ifu_mem_ctl.scala 693:59] + node _T_8758 = eq(perr_ic_index_ff, UInt<7>("h070")) @[ifu_mem_ctl.scala 693:102] + node _T_8759 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_8760 = and(_T_8758, _T_8759) @[ifu_mem_ctl.scala 693:124] + node _T_8761 = or(_T_8757, _T_8760) @[ifu_mem_ctl.scala 693:81] + node _T_8762 = or(_T_8761, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8763 = bits(_T_8762, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8764 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8763 : @[Reg.scala 28:19] _T_8764 <= _T_8754 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][112] <= _T_8764 @[ifu_mem_ctl.scala 693:41] - node _T_8765 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8766 = eq(_T_8765, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8767 = and(ic_valid_ff, _T_8766) @[ifu_mem_ctl.scala 693:97] - node _T_8768 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8769 = and(_T_8767, _T_8768) @[ifu_mem_ctl.scala 693:122] - node _T_8770 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[ifu_mem_ctl.scala 694:37] - node _T_8771 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_8772 = and(_T_8770, _T_8771) @[ifu_mem_ctl.scala 694:59] - node _T_8773 = eq(perr_ic_index_ff, UInt<7>("h071")) @[ifu_mem_ctl.scala 694:102] - node _T_8774 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_8775 = and(_T_8773, _T_8774) @[ifu_mem_ctl.scala 694:124] - node _T_8776 = or(_T_8772, _T_8775) @[ifu_mem_ctl.scala 694:81] - node _T_8777 = or(_T_8776, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8778 = bits(_T_8777, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][112] <= _T_8764 @[ifu_mem_ctl.scala 692:41] + node _T_8765 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8766 = eq(_T_8765, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8767 = and(ic_valid_ff, _T_8766) @[ifu_mem_ctl.scala 692:97] + node _T_8768 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8769 = and(_T_8767, _T_8768) @[ifu_mem_ctl.scala 692:122] + node _T_8770 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[ifu_mem_ctl.scala 693:37] + node _T_8771 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_8772 = and(_T_8770, _T_8771) @[ifu_mem_ctl.scala 693:59] + node _T_8773 = eq(perr_ic_index_ff, UInt<7>("h071")) @[ifu_mem_ctl.scala 693:102] + node _T_8774 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_8775 = and(_T_8773, _T_8774) @[ifu_mem_ctl.scala 693:124] + node _T_8776 = or(_T_8772, _T_8775) @[ifu_mem_ctl.scala 693:81] + node _T_8777 = or(_T_8776, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8778 = bits(_T_8777, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8779 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8778 : @[Reg.scala 28:19] _T_8779 <= _T_8769 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][113] <= _T_8779 @[ifu_mem_ctl.scala 693:41] - node _T_8780 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8781 = eq(_T_8780, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8782 = and(ic_valid_ff, _T_8781) @[ifu_mem_ctl.scala 693:97] - node _T_8783 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8784 = and(_T_8782, _T_8783) @[ifu_mem_ctl.scala 693:122] - node _T_8785 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[ifu_mem_ctl.scala 694:37] - node _T_8786 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_8787 = and(_T_8785, _T_8786) @[ifu_mem_ctl.scala 694:59] - node _T_8788 = eq(perr_ic_index_ff, UInt<7>("h072")) @[ifu_mem_ctl.scala 694:102] - node _T_8789 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_8790 = and(_T_8788, _T_8789) @[ifu_mem_ctl.scala 694:124] - node _T_8791 = or(_T_8787, _T_8790) @[ifu_mem_ctl.scala 694:81] - node _T_8792 = or(_T_8791, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8793 = bits(_T_8792, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][113] <= _T_8779 @[ifu_mem_ctl.scala 692:41] + node _T_8780 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8781 = eq(_T_8780, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8782 = and(ic_valid_ff, _T_8781) @[ifu_mem_ctl.scala 692:97] + node _T_8783 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8784 = and(_T_8782, _T_8783) @[ifu_mem_ctl.scala 692:122] + node _T_8785 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[ifu_mem_ctl.scala 693:37] + node _T_8786 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_8787 = and(_T_8785, _T_8786) @[ifu_mem_ctl.scala 693:59] + node _T_8788 = eq(perr_ic_index_ff, UInt<7>("h072")) @[ifu_mem_ctl.scala 693:102] + node _T_8789 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_8790 = and(_T_8788, _T_8789) @[ifu_mem_ctl.scala 693:124] + node _T_8791 = or(_T_8787, _T_8790) @[ifu_mem_ctl.scala 693:81] + node _T_8792 = or(_T_8791, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8793 = bits(_T_8792, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8794 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8793 : @[Reg.scala 28:19] _T_8794 <= _T_8784 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][114] <= _T_8794 @[ifu_mem_ctl.scala 693:41] - node _T_8795 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8796 = eq(_T_8795, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8797 = and(ic_valid_ff, _T_8796) @[ifu_mem_ctl.scala 693:97] - node _T_8798 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8799 = and(_T_8797, _T_8798) @[ifu_mem_ctl.scala 693:122] - node _T_8800 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[ifu_mem_ctl.scala 694:37] - node _T_8801 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_8802 = and(_T_8800, _T_8801) @[ifu_mem_ctl.scala 694:59] - node _T_8803 = eq(perr_ic_index_ff, UInt<7>("h073")) @[ifu_mem_ctl.scala 694:102] - node _T_8804 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_8805 = and(_T_8803, _T_8804) @[ifu_mem_ctl.scala 694:124] - node _T_8806 = or(_T_8802, _T_8805) @[ifu_mem_ctl.scala 694:81] - node _T_8807 = or(_T_8806, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8808 = bits(_T_8807, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][114] <= _T_8794 @[ifu_mem_ctl.scala 692:41] + node _T_8795 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8796 = eq(_T_8795, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8797 = and(ic_valid_ff, _T_8796) @[ifu_mem_ctl.scala 692:97] + node _T_8798 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8799 = and(_T_8797, _T_8798) @[ifu_mem_ctl.scala 692:122] + node _T_8800 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[ifu_mem_ctl.scala 693:37] + node _T_8801 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_8802 = and(_T_8800, _T_8801) @[ifu_mem_ctl.scala 693:59] + node _T_8803 = eq(perr_ic_index_ff, UInt<7>("h073")) @[ifu_mem_ctl.scala 693:102] + node _T_8804 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_8805 = and(_T_8803, _T_8804) @[ifu_mem_ctl.scala 693:124] + node _T_8806 = or(_T_8802, _T_8805) @[ifu_mem_ctl.scala 693:81] + node _T_8807 = or(_T_8806, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8808 = bits(_T_8807, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8809 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8808 : @[Reg.scala 28:19] _T_8809 <= _T_8799 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][115] <= _T_8809 @[ifu_mem_ctl.scala 693:41] - node _T_8810 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8811 = eq(_T_8810, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8812 = and(ic_valid_ff, _T_8811) @[ifu_mem_ctl.scala 693:97] - node _T_8813 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8814 = and(_T_8812, _T_8813) @[ifu_mem_ctl.scala 693:122] - node _T_8815 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[ifu_mem_ctl.scala 694:37] - node _T_8816 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_8817 = and(_T_8815, _T_8816) @[ifu_mem_ctl.scala 694:59] - node _T_8818 = eq(perr_ic_index_ff, UInt<7>("h074")) @[ifu_mem_ctl.scala 694:102] - node _T_8819 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_8820 = and(_T_8818, _T_8819) @[ifu_mem_ctl.scala 694:124] - node _T_8821 = or(_T_8817, _T_8820) @[ifu_mem_ctl.scala 694:81] - node _T_8822 = or(_T_8821, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8823 = bits(_T_8822, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][115] <= _T_8809 @[ifu_mem_ctl.scala 692:41] + node _T_8810 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8811 = eq(_T_8810, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8812 = and(ic_valid_ff, _T_8811) @[ifu_mem_ctl.scala 692:97] + node _T_8813 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8814 = and(_T_8812, _T_8813) @[ifu_mem_ctl.scala 692:122] + node _T_8815 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[ifu_mem_ctl.scala 693:37] + node _T_8816 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_8817 = and(_T_8815, _T_8816) @[ifu_mem_ctl.scala 693:59] + node _T_8818 = eq(perr_ic_index_ff, UInt<7>("h074")) @[ifu_mem_ctl.scala 693:102] + node _T_8819 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_8820 = and(_T_8818, _T_8819) @[ifu_mem_ctl.scala 693:124] + node _T_8821 = or(_T_8817, _T_8820) @[ifu_mem_ctl.scala 693:81] + node _T_8822 = or(_T_8821, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8823 = bits(_T_8822, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8824 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8823 : @[Reg.scala 28:19] _T_8824 <= _T_8814 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][116] <= _T_8824 @[ifu_mem_ctl.scala 693:41] - node _T_8825 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8826 = eq(_T_8825, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8827 = and(ic_valid_ff, _T_8826) @[ifu_mem_ctl.scala 693:97] - node _T_8828 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8829 = and(_T_8827, _T_8828) @[ifu_mem_ctl.scala 693:122] - node _T_8830 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[ifu_mem_ctl.scala 694:37] - node _T_8831 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_8832 = and(_T_8830, _T_8831) @[ifu_mem_ctl.scala 694:59] - node _T_8833 = eq(perr_ic_index_ff, UInt<7>("h075")) @[ifu_mem_ctl.scala 694:102] - node _T_8834 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_8835 = and(_T_8833, _T_8834) @[ifu_mem_ctl.scala 694:124] - node _T_8836 = or(_T_8832, _T_8835) @[ifu_mem_ctl.scala 694:81] - node _T_8837 = or(_T_8836, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8838 = bits(_T_8837, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][116] <= _T_8824 @[ifu_mem_ctl.scala 692:41] + node _T_8825 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8826 = eq(_T_8825, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8827 = and(ic_valid_ff, _T_8826) @[ifu_mem_ctl.scala 692:97] + node _T_8828 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8829 = and(_T_8827, _T_8828) @[ifu_mem_ctl.scala 692:122] + node _T_8830 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[ifu_mem_ctl.scala 693:37] + node _T_8831 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_8832 = and(_T_8830, _T_8831) @[ifu_mem_ctl.scala 693:59] + node _T_8833 = eq(perr_ic_index_ff, UInt<7>("h075")) @[ifu_mem_ctl.scala 693:102] + node _T_8834 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_8835 = and(_T_8833, _T_8834) @[ifu_mem_ctl.scala 693:124] + node _T_8836 = or(_T_8832, _T_8835) @[ifu_mem_ctl.scala 693:81] + node _T_8837 = or(_T_8836, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8838 = bits(_T_8837, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8839 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8838 : @[Reg.scala 28:19] _T_8839 <= _T_8829 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][117] <= _T_8839 @[ifu_mem_ctl.scala 693:41] - node _T_8840 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8841 = eq(_T_8840, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8842 = and(ic_valid_ff, _T_8841) @[ifu_mem_ctl.scala 693:97] - node _T_8843 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8844 = and(_T_8842, _T_8843) @[ifu_mem_ctl.scala 693:122] - node _T_8845 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[ifu_mem_ctl.scala 694:37] - node _T_8846 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_8847 = and(_T_8845, _T_8846) @[ifu_mem_ctl.scala 694:59] - node _T_8848 = eq(perr_ic_index_ff, UInt<7>("h076")) @[ifu_mem_ctl.scala 694:102] - node _T_8849 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_8850 = and(_T_8848, _T_8849) @[ifu_mem_ctl.scala 694:124] - node _T_8851 = or(_T_8847, _T_8850) @[ifu_mem_ctl.scala 694:81] - node _T_8852 = or(_T_8851, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8853 = bits(_T_8852, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][117] <= _T_8839 @[ifu_mem_ctl.scala 692:41] + node _T_8840 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8841 = eq(_T_8840, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8842 = and(ic_valid_ff, _T_8841) @[ifu_mem_ctl.scala 692:97] + node _T_8843 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8844 = and(_T_8842, _T_8843) @[ifu_mem_ctl.scala 692:122] + node _T_8845 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[ifu_mem_ctl.scala 693:37] + node _T_8846 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_8847 = and(_T_8845, _T_8846) @[ifu_mem_ctl.scala 693:59] + node _T_8848 = eq(perr_ic_index_ff, UInt<7>("h076")) @[ifu_mem_ctl.scala 693:102] + node _T_8849 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_8850 = and(_T_8848, _T_8849) @[ifu_mem_ctl.scala 693:124] + node _T_8851 = or(_T_8847, _T_8850) @[ifu_mem_ctl.scala 693:81] + node _T_8852 = or(_T_8851, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8853 = bits(_T_8852, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8854 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8853 : @[Reg.scala 28:19] _T_8854 <= _T_8844 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][118] <= _T_8854 @[ifu_mem_ctl.scala 693:41] - node _T_8855 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8856 = eq(_T_8855, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8857 = and(ic_valid_ff, _T_8856) @[ifu_mem_ctl.scala 693:97] - node _T_8858 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8859 = and(_T_8857, _T_8858) @[ifu_mem_ctl.scala 693:122] - node _T_8860 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[ifu_mem_ctl.scala 694:37] - node _T_8861 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_8862 = and(_T_8860, _T_8861) @[ifu_mem_ctl.scala 694:59] - node _T_8863 = eq(perr_ic_index_ff, UInt<7>("h077")) @[ifu_mem_ctl.scala 694:102] - node _T_8864 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_8865 = and(_T_8863, _T_8864) @[ifu_mem_ctl.scala 694:124] - node _T_8866 = or(_T_8862, _T_8865) @[ifu_mem_ctl.scala 694:81] - node _T_8867 = or(_T_8866, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8868 = bits(_T_8867, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][118] <= _T_8854 @[ifu_mem_ctl.scala 692:41] + node _T_8855 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8856 = eq(_T_8855, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8857 = and(ic_valid_ff, _T_8856) @[ifu_mem_ctl.scala 692:97] + node _T_8858 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8859 = and(_T_8857, _T_8858) @[ifu_mem_ctl.scala 692:122] + node _T_8860 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[ifu_mem_ctl.scala 693:37] + node _T_8861 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_8862 = and(_T_8860, _T_8861) @[ifu_mem_ctl.scala 693:59] + node _T_8863 = eq(perr_ic_index_ff, UInt<7>("h077")) @[ifu_mem_ctl.scala 693:102] + node _T_8864 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_8865 = and(_T_8863, _T_8864) @[ifu_mem_ctl.scala 693:124] + node _T_8866 = or(_T_8862, _T_8865) @[ifu_mem_ctl.scala 693:81] + node _T_8867 = or(_T_8866, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8868 = bits(_T_8867, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8869 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8868 : @[Reg.scala 28:19] _T_8869 <= _T_8859 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][119] <= _T_8869 @[ifu_mem_ctl.scala 693:41] - node _T_8870 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8871 = eq(_T_8870, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8872 = and(ic_valid_ff, _T_8871) @[ifu_mem_ctl.scala 693:97] - node _T_8873 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8874 = and(_T_8872, _T_8873) @[ifu_mem_ctl.scala 693:122] - node _T_8875 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[ifu_mem_ctl.scala 694:37] - node _T_8876 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_8877 = and(_T_8875, _T_8876) @[ifu_mem_ctl.scala 694:59] - node _T_8878 = eq(perr_ic_index_ff, UInt<7>("h078")) @[ifu_mem_ctl.scala 694:102] - node _T_8879 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_8880 = and(_T_8878, _T_8879) @[ifu_mem_ctl.scala 694:124] - node _T_8881 = or(_T_8877, _T_8880) @[ifu_mem_ctl.scala 694:81] - node _T_8882 = or(_T_8881, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8883 = bits(_T_8882, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][119] <= _T_8869 @[ifu_mem_ctl.scala 692:41] + node _T_8870 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8871 = eq(_T_8870, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8872 = and(ic_valid_ff, _T_8871) @[ifu_mem_ctl.scala 692:97] + node _T_8873 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8874 = and(_T_8872, _T_8873) @[ifu_mem_ctl.scala 692:122] + node _T_8875 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[ifu_mem_ctl.scala 693:37] + node _T_8876 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_8877 = and(_T_8875, _T_8876) @[ifu_mem_ctl.scala 693:59] + node _T_8878 = eq(perr_ic_index_ff, UInt<7>("h078")) @[ifu_mem_ctl.scala 693:102] + node _T_8879 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_8880 = and(_T_8878, _T_8879) @[ifu_mem_ctl.scala 693:124] + node _T_8881 = or(_T_8877, _T_8880) @[ifu_mem_ctl.scala 693:81] + node _T_8882 = or(_T_8881, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8883 = bits(_T_8882, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8884 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8883 : @[Reg.scala 28:19] _T_8884 <= _T_8874 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][120] <= _T_8884 @[ifu_mem_ctl.scala 693:41] - node _T_8885 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8886 = eq(_T_8885, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8887 = and(ic_valid_ff, _T_8886) @[ifu_mem_ctl.scala 693:97] - node _T_8888 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8889 = and(_T_8887, _T_8888) @[ifu_mem_ctl.scala 693:122] - node _T_8890 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[ifu_mem_ctl.scala 694:37] - node _T_8891 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_8892 = and(_T_8890, _T_8891) @[ifu_mem_ctl.scala 694:59] - node _T_8893 = eq(perr_ic_index_ff, UInt<7>("h079")) @[ifu_mem_ctl.scala 694:102] - node _T_8894 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_8895 = and(_T_8893, _T_8894) @[ifu_mem_ctl.scala 694:124] - node _T_8896 = or(_T_8892, _T_8895) @[ifu_mem_ctl.scala 694:81] - node _T_8897 = or(_T_8896, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8898 = bits(_T_8897, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][120] <= _T_8884 @[ifu_mem_ctl.scala 692:41] + node _T_8885 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8886 = eq(_T_8885, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8887 = and(ic_valid_ff, _T_8886) @[ifu_mem_ctl.scala 692:97] + node _T_8888 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8889 = and(_T_8887, _T_8888) @[ifu_mem_ctl.scala 692:122] + node _T_8890 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[ifu_mem_ctl.scala 693:37] + node _T_8891 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_8892 = and(_T_8890, _T_8891) @[ifu_mem_ctl.scala 693:59] + node _T_8893 = eq(perr_ic_index_ff, UInt<7>("h079")) @[ifu_mem_ctl.scala 693:102] + node _T_8894 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_8895 = and(_T_8893, _T_8894) @[ifu_mem_ctl.scala 693:124] + node _T_8896 = or(_T_8892, _T_8895) @[ifu_mem_ctl.scala 693:81] + node _T_8897 = or(_T_8896, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8898 = bits(_T_8897, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8899 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8898 : @[Reg.scala 28:19] _T_8899 <= _T_8889 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][121] <= _T_8899 @[ifu_mem_ctl.scala 693:41] - node _T_8900 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8901 = eq(_T_8900, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8902 = and(ic_valid_ff, _T_8901) @[ifu_mem_ctl.scala 693:97] - node _T_8903 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8904 = and(_T_8902, _T_8903) @[ifu_mem_ctl.scala 693:122] - node _T_8905 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[ifu_mem_ctl.scala 694:37] - node _T_8906 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_8907 = and(_T_8905, _T_8906) @[ifu_mem_ctl.scala 694:59] - node _T_8908 = eq(perr_ic_index_ff, UInt<7>("h07a")) @[ifu_mem_ctl.scala 694:102] - node _T_8909 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_8910 = and(_T_8908, _T_8909) @[ifu_mem_ctl.scala 694:124] - node _T_8911 = or(_T_8907, _T_8910) @[ifu_mem_ctl.scala 694:81] - node _T_8912 = or(_T_8911, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8913 = bits(_T_8912, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][121] <= _T_8899 @[ifu_mem_ctl.scala 692:41] + node _T_8900 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8901 = eq(_T_8900, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8902 = and(ic_valid_ff, _T_8901) @[ifu_mem_ctl.scala 692:97] + node _T_8903 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8904 = and(_T_8902, _T_8903) @[ifu_mem_ctl.scala 692:122] + node _T_8905 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[ifu_mem_ctl.scala 693:37] + node _T_8906 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_8907 = and(_T_8905, _T_8906) @[ifu_mem_ctl.scala 693:59] + node _T_8908 = eq(perr_ic_index_ff, UInt<7>("h07a")) @[ifu_mem_ctl.scala 693:102] + node _T_8909 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_8910 = and(_T_8908, _T_8909) @[ifu_mem_ctl.scala 693:124] + node _T_8911 = or(_T_8907, _T_8910) @[ifu_mem_ctl.scala 693:81] + node _T_8912 = or(_T_8911, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8913 = bits(_T_8912, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8914 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8913 : @[Reg.scala 28:19] _T_8914 <= _T_8904 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][122] <= _T_8914 @[ifu_mem_ctl.scala 693:41] - node _T_8915 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8916 = eq(_T_8915, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8917 = and(ic_valid_ff, _T_8916) @[ifu_mem_ctl.scala 693:97] - node _T_8918 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8919 = and(_T_8917, _T_8918) @[ifu_mem_ctl.scala 693:122] - node _T_8920 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[ifu_mem_ctl.scala 694:37] - node _T_8921 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_8922 = and(_T_8920, _T_8921) @[ifu_mem_ctl.scala 694:59] - node _T_8923 = eq(perr_ic_index_ff, UInt<7>("h07b")) @[ifu_mem_ctl.scala 694:102] - node _T_8924 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_8925 = and(_T_8923, _T_8924) @[ifu_mem_ctl.scala 694:124] - node _T_8926 = or(_T_8922, _T_8925) @[ifu_mem_ctl.scala 694:81] - node _T_8927 = or(_T_8926, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8928 = bits(_T_8927, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][122] <= _T_8914 @[ifu_mem_ctl.scala 692:41] + node _T_8915 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8916 = eq(_T_8915, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8917 = and(ic_valid_ff, _T_8916) @[ifu_mem_ctl.scala 692:97] + node _T_8918 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8919 = and(_T_8917, _T_8918) @[ifu_mem_ctl.scala 692:122] + node _T_8920 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[ifu_mem_ctl.scala 693:37] + node _T_8921 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_8922 = and(_T_8920, _T_8921) @[ifu_mem_ctl.scala 693:59] + node _T_8923 = eq(perr_ic_index_ff, UInt<7>("h07b")) @[ifu_mem_ctl.scala 693:102] + node _T_8924 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_8925 = and(_T_8923, _T_8924) @[ifu_mem_ctl.scala 693:124] + node _T_8926 = or(_T_8922, _T_8925) @[ifu_mem_ctl.scala 693:81] + node _T_8927 = or(_T_8926, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8928 = bits(_T_8927, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8929 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8928 : @[Reg.scala 28:19] _T_8929 <= _T_8919 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][123] <= _T_8929 @[ifu_mem_ctl.scala 693:41] - node _T_8930 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8931 = eq(_T_8930, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8932 = and(ic_valid_ff, _T_8931) @[ifu_mem_ctl.scala 693:97] - node _T_8933 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8934 = and(_T_8932, _T_8933) @[ifu_mem_ctl.scala 693:122] - node _T_8935 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[ifu_mem_ctl.scala 694:37] - node _T_8936 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_8937 = and(_T_8935, _T_8936) @[ifu_mem_ctl.scala 694:59] - node _T_8938 = eq(perr_ic_index_ff, UInt<7>("h07c")) @[ifu_mem_ctl.scala 694:102] - node _T_8939 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_8940 = and(_T_8938, _T_8939) @[ifu_mem_ctl.scala 694:124] - node _T_8941 = or(_T_8937, _T_8940) @[ifu_mem_ctl.scala 694:81] - node _T_8942 = or(_T_8941, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8943 = bits(_T_8942, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][123] <= _T_8929 @[ifu_mem_ctl.scala 692:41] + node _T_8930 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8931 = eq(_T_8930, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8932 = and(ic_valid_ff, _T_8931) @[ifu_mem_ctl.scala 692:97] + node _T_8933 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8934 = and(_T_8932, _T_8933) @[ifu_mem_ctl.scala 692:122] + node _T_8935 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[ifu_mem_ctl.scala 693:37] + node _T_8936 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_8937 = and(_T_8935, _T_8936) @[ifu_mem_ctl.scala 693:59] + node _T_8938 = eq(perr_ic_index_ff, UInt<7>("h07c")) @[ifu_mem_ctl.scala 693:102] + node _T_8939 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_8940 = and(_T_8938, _T_8939) @[ifu_mem_ctl.scala 693:124] + node _T_8941 = or(_T_8937, _T_8940) @[ifu_mem_ctl.scala 693:81] + node _T_8942 = or(_T_8941, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8943 = bits(_T_8942, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8944 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8943 : @[Reg.scala 28:19] _T_8944 <= _T_8934 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][124] <= _T_8944 @[ifu_mem_ctl.scala 693:41] - node _T_8945 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8946 = eq(_T_8945, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8947 = and(ic_valid_ff, _T_8946) @[ifu_mem_ctl.scala 693:97] - node _T_8948 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8949 = and(_T_8947, _T_8948) @[ifu_mem_ctl.scala 693:122] - node _T_8950 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[ifu_mem_ctl.scala 694:37] - node _T_8951 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_8952 = and(_T_8950, _T_8951) @[ifu_mem_ctl.scala 694:59] - node _T_8953 = eq(perr_ic_index_ff, UInt<7>("h07d")) @[ifu_mem_ctl.scala 694:102] - node _T_8954 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_8955 = and(_T_8953, _T_8954) @[ifu_mem_ctl.scala 694:124] - node _T_8956 = or(_T_8952, _T_8955) @[ifu_mem_ctl.scala 694:81] - node _T_8957 = or(_T_8956, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8958 = bits(_T_8957, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][124] <= _T_8944 @[ifu_mem_ctl.scala 692:41] + node _T_8945 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8946 = eq(_T_8945, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8947 = and(ic_valid_ff, _T_8946) @[ifu_mem_ctl.scala 692:97] + node _T_8948 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8949 = and(_T_8947, _T_8948) @[ifu_mem_ctl.scala 692:122] + node _T_8950 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[ifu_mem_ctl.scala 693:37] + node _T_8951 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_8952 = and(_T_8950, _T_8951) @[ifu_mem_ctl.scala 693:59] + node _T_8953 = eq(perr_ic_index_ff, UInt<7>("h07d")) @[ifu_mem_ctl.scala 693:102] + node _T_8954 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_8955 = and(_T_8953, _T_8954) @[ifu_mem_ctl.scala 693:124] + node _T_8956 = or(_T_8952, _T_8955) @[ifu_mem_ctl.scala 693:81] + node _T_8957 = or(_T_8956, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8958 = bits(_T_8957, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8959 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8958 : @[Reg.scala 28:19] _T_8959 <= _T_8949 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][125] <= _T_8959 @[ifu_mem_ctl.scala 693:41] - node _T_8960 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8961 = eq(_T_8960, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8962 = and(ic_valid_ff, _T_8961) @[ifu_mem_ctl.scala 693:97] - node _T_8963 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8964 = and(_T_8962, _T_8963) @[ifu_mem_ctl.scala 693:122] - node _T_8965 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[ifu_mem_ctl.scala 694:37] - node _T_8966 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_8967 = and(_T_8965, _T_8966) @[ifu_mem_ctl.scala 694:59] - node _T_8968 = eq(perr_ic_index_ff, UInt<7>("h07e")) @[ifu_mem_ctl.scala 694:102] - node _T_8969 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_8970 = and(_T_8968, _T_8969) @[ifu_mem_ctl.scala 694:124] - node _T_8971 = or(_T_8967, _T_8970) @[ifu_mem_ctl.scala 694:81] - node _T_8972 = or(_T_8971, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8973 = bits(_T_8972, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][125] <= _T_8959 @[ifu_mem_ctl.scala 692:41] + node _T_8960 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8961 = eq(_T_8960, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8962 = and(ic_valid_ff, _T_8961) @[ifu_mem_ctl.scala 692:97] + node _T_8963 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8964 = and(_T_8962, _T_8963) @[ifu_mem_ctl.scala 692:122] + node _T_8965 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[ifu_mem_ctl.scala 693:37] + node _T_8966 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_8967 = and(_T_8965, _T_8966) @[ifu_mem_ctl.scala 693:59] + node _T_8968 = eq(perr_ic_index_ff, UInt<7>("h07e")) @[ifu_mem_ctl.scala 693:102] + node _T_8969 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_8970 = and(_T_8968, _T_8969) @[ifu_mem_ctl.scala 693:124] + node _T_8971 = or(_T_8967, _T_8970) @[ifu_mem_ctl.scala 693:81] + node _T_8972 = or(_T_8971, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8973 = bits(_T_8972, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8974 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8973 : @[Reg.scala 28:19] _T_8974 <= _T_8964 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][126] <= _T_8974 @[ifu_mem_ctl.scala 693:41] - node _T_8975 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 693:115] - node _T_8976 = eq(_T_8975, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:99] - node _T_8977 = and(ic_valid_ff, _T_8976) @[ifu_mem_ctl.scala 693:97] - node _T_8978 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 693:124] - node _T_8979 = and(_T_8977, _T_8978) @[ifu_mem_ctl.scala 693:122] - node _T_8980 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[ifu_mem_ctl.scala 694:37] - node _T_8981 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 694:76] - node _T_8982 = and(_T_8980, _T_8981) @[ifu_mem_ctl.scala 694:59] - node _T_8983 = eq(perr_ic_index_ff, UInt<7>("h07f")) @[ifu_mem_ctl.scala 694:102] - node _T_8984 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 694:142] - node _T_8985 = and(_T_8983, _T_8984) @[ifu_mem_ctl.scala 694:124] - node _T_8986 = or(_T_8982, _T_8985) @[ifu_mem_ctl.scala 694:81] - node _T_8987 = or(_T_8986, reset_all_tags) @[ifu_mem_ctl.scala 694:147] - node _T_8988 = bits(_T_8987, 0, 0) @[ifu_mem_ctl.scala 694:166] + ic_tag_valid_out[1][126] <= _T_8974 @[ifu_mem_ctl.scala 692:41] + node _T_8975 = bits(reset_all_tags, 0, 0) @[ifu_mem_ctl.scala 692:115] + node _T_8976 = eq(_T_8975, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:99] + node _T_8977 = and(ic_valid_ff, _T_8976) @[ifu_mem_ctl.scala 692:97] + node _T_8978 = eq(perr_sel_invalidate, UInt<1>("h00")) @[ifu_mem_ctl.scala 692:124] + node _T_8979 = and(_T_8977, _T_8978) @[ifu_mem_ctl.scala 692:122] + node _T_8980 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[ifu_mem_ctl.scala 693:37] + node _T_8981 = bits(ifu_tag_wren_ff, 1, 1) @[ifu_mem_ctl.scala 693:76] + node _T_8982 = and(_T_8980, _T_8981) @[ifu_mem_ctl.scala 693:59] + node _T_8983 = eq(perr_ic_index_ff, UInt<7>("h07f")) @[ifu_mem_ctl.scala 693:102] + node _T_8984 = bits(perr_err_inv_way, 1, 1) @[ifu_mem_ctl.scala 693:142] + node _T_8985 = and(_T_8983, _T_8984) @[ifu_mem_ctl.scala 693:124] + node _T_8986 = or(_T_8982, _T_8985) @[ifu_mem_ctl.scala 693:81] + node _T_8987 = or(_T_8986, reset_all_tags) @[ifu_mem_ctl.scala 693:147] + node _T_8988 = bits(_T_8987, 0, 0) @[ifu_mem_ctl.scala 693:166] reg _T_8989 : UInt<1>, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8988 : @[Reg.scala 28:19] _T_8989 <= _T_8979 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][127] <= _T_8989 @[ifu_mem_ctl.scala 693:41] - node _T_8990 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 697:33] - node _T_8991 = mux(_T_8990, ic_tag_valid_out[0][0], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_8992 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[ifu_mem_ctl.scala 697:33] - node _T_8993 = mux(_T_8992, ic_tag_valid_out[0][1], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_8994 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[ifu_mem_ctl.scala 697:33] - node _T_8995 = mux(_T_8994, ic_tag_valid_out[0][2], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_8996 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[ifu_mem_ctl.scala 697:33] - node _T_8997 = mux(_T_8996, ic_tag_valid_out[0][3], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_8998 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[ifu_mem_ctl.scala 697:33] - node _T_8999 = mux(_T_8998, ic_tag_valid_out[0][4], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9000 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[ifu_mem_ctl.scala 697:33] - node _T_9001 = mux(_T_9000, ic_tag_valid_out[0][5], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9002 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[ifu_mem_ctl.scala 697:33] - node _T_9003 = mux(_T_9002, ic_tag_valid_out[0][6], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9004 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[ifu_mem_ctl.scala 697:33] - node _T_9005 = mux(_T_9004, ic_tag_valid_out[0][7], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9006 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[ifu_mem_ctl.scala 697:33] - node _T_9007 = mux(_T_9006, ic_tag_valid_out[0][8], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9008 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[ifu_mem_ctl.scala 697:33] - node _T_9009 = mux(_T_9008, ic_tag_valid_out[0][9], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9010 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[ifu_mem_ctl.scala 697:33] - node _T_9011 = mux(_T_9010, ic_tag_valid_out[0][10], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9012 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[ifu_mem_ctl.scala 697:33] - node _T_9013 = mux(_T_9012, ic_tag_valid_out[0][11], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9014 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[ifu_mem_ctl.scala 697:33] - node _T_9015 = mux(_T_9014, ic_tag_valid_out[0][12], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9016 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[ifu_mem_ctl.scala 697:33] - node _T_9017 = mux(_T_9016, ic_tag_valid_out[0][13], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9018 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[ifu_mem_ctl.scala 697:33] - node _T_9019 = mux(_T_9018, ic_tag_valid_out[0][14], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9020 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[ifu_mem_ctl.scala 697:33] - node _T_9021 = mux(_T_9020, ic_tag_valid_out[0][15], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9022 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[ifu_mem_ctl.scala 697:33] - node _T_9023 = mux(_T_9022, ic_tag_valid_out[0][16], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9024 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[ifu_mem_ctl.scala 697:33] - node _T_9025 = mux(_T_9024, ic_tag_valid_out[0][17], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9026 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[ifu_mem_ctl.scala 697:33] - node _T_9027 = mux(_T_9026, ic_tag_valid_out[0][18], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9028 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[ifu_mem_ctl.scala 697:33] - node _T_9029 = mux(_T_9028, ic_tag_valid_out[0][19], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9030 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[ifu_mem_ctl.scala 697:33] - node _T_9031 = mux(_T_9030, ic_tag_valid_out[0][20], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9032 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[ifu_mem_ctl.scala 697:33] - node _T_9033 = mux(_T_9032, ic_tag_valid_out[0][21], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9034 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[ifu_mem_ctl.scala 697:33] - node _T_9035 = mux(_T_9034, ic_tag_valid_out[0][22], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9036 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[ifu_mem_ctl.scala 697:33] - node _T_9037 = mux(_T_9036, ic_tag_valid_out[0][23], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9038 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[ifu_mem_ctl.scala 697:33] - node _T_9039 = mux(_T_9038, ic_tag_valid_out[0][24], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9040 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[ifu_mem_ctl.scala 697:33] - node _T_9041 = mux(_T_9040, ic_tag_valid_out[0][25], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9042 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[ifu_mem_ctl.scala 697:33] - node _T_9043 = mux(_T_9042, ic_tag_valid_out[0][26], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9044 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[ifu_mem_ctl.scala 697:33] - node _T_9045 = mux(_T_9044, ic_tag_valid_out[0][27], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9046 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[ifu_mem_ctl.scala 697:33] - node _T_9047 = mux(_T_9046, ic_tag_valid_out[0][28], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9048 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[ifu_mem_ctl.scala 697:33] - node _T_9049 = mux(_T_9048, ic_tag_valid_out[0][29], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9050 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[ifu_mem_ctl.scala 697:33] - node _T_9051 = mux(_T_9050, ic_tag_valid_out[0][30], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9052 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[ifu_mem_ctl.scala 697:33] - node _T_9053 = mux(_T_9052, ic_tag_valid_out[0][31], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9054 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[ifu_mem_ctl.scala 697:33] - node _T_9055 = mux(_T_9054, ic_tag_valid_out[0][32], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9056 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[ifu_mem_ctl.scala 697:33] - node _T_9057 = mux(_T_9056, ic_tag_valid_out[0][33], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9058 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[ifu_mem_ctl.scala 697:33] - node _T_9059 = mux(_T_9058, ic_tag_valid_out[0][34], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9060 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[ifu_mem_ctl.scala 697:33] - node _T_9061 = mux(_T_9060, ic_tag_valid_out[0][35], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9062 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[ifu_mem_ctl.scala 697:33] - node _T_9063 = mux(_T_9062, ic_tag_valid_out[0][36], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9064 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[ifu_mem_ctl.scala 697:33] - node _T_9065 = mux(_T_9064, ic_tag_valid_out[0][37], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9066 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[ifu_mem_ctl.scala 697:33] - node _T_9067 = mux(_T_9066, ic_tag_valid_out[0][38], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9068 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[ifu_mem_ctl.scala 697:33] - node _T_9069 = mux(_T_9068, ic_tag_valid_out[0][39], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9070 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[ifu_mem_ctl.scala 697:33] - node _T_9071 = mux(_T_9070, ic_tag_valid_out[0][40], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9072 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[ifu_mem_ctl.scala 697:33] - node _T_9073 = mux(_T_9072, ic_tag_valid_out[0][41], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9074 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[ifu_mem_ctl.scala 697:33] - node _T_9075 = mux(_T_9074, ic_tag_valid_out[0][42], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9076 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[ifu_mem_ctl.scala 697:33] - node _T_9077 = mux(_T_9076, ic_tag_valid_out[0][43], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9078 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[ifu_mem_ctl.scala 697:33] - node _T_9079 = mux(_T_9078, ic_tag_valid_out[0][44], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9080 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[ifu_mem_ctl.scala 697:33] - node _T_9081 = mux(_T_9080, ic_tag_valid_out[0][45], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9082 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[ifu_mem_ctl.scala 697:33] - node _T_9083 = mux(_T_9082, ic_tag_valid_out[0][46], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9084 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[ifu_mem_ctl.scala 697:33] - node _T_9085 = mux(_T_9084, ic_tag_valid_out[0][47], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9086 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[ifu_mem_ctl.scala 697:33] - node _T_9087 = mux(_T_9086, ic_tag_valid_out[0][48], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9088 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[ifu_mem_ctl.scala 697:33] - node _T_9089 = mux(_T_9088, ic_tag_valid_out[0][49], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9090 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[ifu_mem_ctl.scala 697:33] - node _T_9091 = mux(_T_9090, ic_tag_valid_out[0][50], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9092 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[ifu_mem_ctl.scala 697:33] - node _T_9093 = mux(_T_9092, ic_tag_valid_out[0][51], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9094 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[ifu_mem_ctl.scala 697:33] - node _T_9095 = mux(_T_9094, ic_tag_valid_out[0][52], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9096 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[ifu_mem_ctl.scala 697:33] - node _T_9097 = mux(_T_9096, ic_tag_valid_out[0][53], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9098 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[ifu_mem_ctl.scala 697:33] - node _T_9099 = mux(_T_9098, ic_tag_valid_out[0][54], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9100 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[ifu_mem_ctl.scala 697:33] - node _T_9101 = mux(_T_9100, ic_tag_valid_out[0][55], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9102 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[ifu_mem_ctl.scala 697:33] - node _T_9103 = mux(_T_9102, ic_tag_valid_out[0][56], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9104 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[ifu_mem_ctl.scala 697:33] - node _T_9105 = mux(_T_9104, ic_tag_valid_out[0][57], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9106 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[ifu_mem_ctl.scala 697:33] - node _T_9107 = mux(_T_9106, ic_tag_valid_out[0][58], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9108 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[ifu_mem_ctl.scala 697:33] - node _T_9109 = mux(_T_9108, ic_tag_valid_out[0][59], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9110 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[ifu_mem_ctl.scala 697:33] - node _T_9111 = mux(_T_9110, ic_tag_valid_out[0][60], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9112 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[ifu_mem_ctl.scala 697:33] - node _T_9113 = mux(_T_9112, ic_tag_valid_out[0][61], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9114 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[ifu_mem_ctl.scala 697:33] - node _T_9115 = mux(_T_9114, ic_tag_valid_out[0][62], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9116 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[ifu_mem_ctl.scala 697:33] - node _T_9117 = mux(_T_9116, ic_tag_valid_out[0][63], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9118 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[ifu_mem_ctl.scala 697:33] - node _T_9119 = mux(_T_9118, ic_tag_valid_out[0][64], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9120 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[ifu_mem_ctl.scala 697:33] - node _T_9121 = mux(_T_9120, ic_tag_valid_out[0][65], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9122 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[ifu_mem_ctl.scala 697:33] - node _T_9123 = mux(_T_9122, ic_tag_valid_out[0][66], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9124 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[ifu_mem_ctl.scala 697:33] - node _T_9125 = mux(_T_9124, ic_tag_valid_out[0][67], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9126 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[ifu_mem_ctl.scala 697:33] - node _T_9127 = mux(_T_9126, ic_tag_valid_out[0][68], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9128 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[ifu_mem_ctl.scala 697:33] - node _T_9129 = mux(_T_9128, ic_tag_valid_out[0][69], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9130 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[ifu_mem_ctl.scala 697:33] - node _T_9131 = mux(_T_9130, ic_tag_valid_out[0][70], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9132 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[ifu_mem_ctl.scala 697:33] - node _T_9133 = mux(_T_9132, ic_tag_valid_out[0][71], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9134 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[ifu_mem_ctl.scala 697:33] - node _T_9135 = mux(_T_9134, ic_tag_valid_out[0][72], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9136 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[ifu_mem_ctl.scala 697:33] - node _T_9137 = mux(_T_9136, ic_tag_valid_out[0][73], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9138 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[ifu_mem_ctl.scala 697:33] - node _T_9139 = mux(_T_9138, ic_tag_valid_out[0][74], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9140 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[ifu_mem_ctl.scala 697:33] - node _T_9141 = mux(_T_9140, ic_tag_valid_out[0][75], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9142 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[ifu_mem_ctl.scala 697:33] - node _T_9143 = mux(_T_9142, ic_tag_valid_out[0][76], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9144 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[ifu_mem_ctl.scala 697:33] - node _T_9145 = mux(_T_9144, ic_tag_valid_out[0][77], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9146 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[ifu_mem_ctl.scala 697:33] - node _T_9147 = mux(_T_9146, ic_tag_valid_out[0][78], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9148 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[ifu_mem_ctl.scala 697:33] - node _T_9149 = mux(_T_9148, ic_tag_valid_out[0][79], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9150 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[ifu_mem_ctl.scala 697:33] - node _T_9151 = mux(_T_9150, ic_tag_valid_out[0][80], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9152 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[ifu_mem_ctl.scala 697:33] - node _T_9153 = mux(_T_9152, ic_tag_valid_out[0][81], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9154 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[ifu_mem_ctl.scala 697:33] - node _T_9155 = mux(_T_9154, ic_tag_valid_out[0][82], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9156 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[ifu_mem_ctl.scala 697:33] - node _T_9157 = mux(_T_9156, ic_tag_valid_out[0][83], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9158 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[ifu_mem_ctl.scala 697:33] - node _T_9159 = mux(_T_9158, ic_tag_valid_out[0][84], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9160 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[ifu_mem_ctl.scala 697:33] - node _T_9161 = mux(_T_9160, ic_tag_valid_out[0][85], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9162 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[ifu_mem_ctl.scala 697:33] - node _T_9163 = mux(_T_9162, ic_tag_valid_out[0][86], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9164 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[ifu_mem_ctl.scala 697:33] - node _T_9165 = mux(_T_9164, ic_tag_valid_out[0][87], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9166 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[ifu_mem_ctl.scala 697:33] - node _T_9167 = mux(_T_9166, ic_tag_valid_out[0][88], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9168 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[ifu_mem_ctl.scala 697:33] - node _T_9169 = mux(_T_9168, ic_tag_valid_out[0][89], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9170 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[ifu_mem_ctl.scala 697:33] - node _T_9171 = mux(_T_9170, ic_tag_valid_out[0][90], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9172 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[ifu_mem_ctl.scala 697:33] - node _T_9173 = mux(_T_9172, ic_tag_valid_out[0][91], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9174 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[ifu_mem_ctl.scala 697:33] - node _T_9175 = mux(_T_9174, ic_tag_valid_out[0][92], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9176 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[ifu_mem_ctl.scala 697:33] - node _T_9177 = mux(_T_9176, ic_tag_valid_out[0][93], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9178 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[ifu_mem_ctl.scala 697:33] - node _T_9179 = mux(_T_9178, ic_tag_valid_out[0][94], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9180 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[ifu_mem_ctl.scala 697:33] - node _T_9181 = mux(_T_9180, ic_tag_valid_out[0][95], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9182 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[ifu_mem_ctl.scala 697:33] - node _T_9183 = mux(_T_9182, ic_tag_valid_out[0][96], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9184 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[ifu_mem_ctl.scala 697:33] - node _T_9185 = mux(_T_9184, ic_tag_valid_out[0][97], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9186 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[ifu_mem_ctl.scala 697:33] - node _T_9187 = mux(_T_9186, ic_tag_valid_out[0][98], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9188 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[ifu_mem_ctl.scala 697:33] - node _T_9189 = mux(_T_9188, ic_tag_valid_out[0][99], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9190 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[ifu_mem_ctl.scala 697:33] - node _T_9191 = mux(_T_9190, ic_tag_valid_out[0][100], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9192 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[ifu_mem_ctl.scala 697:33] - node _T_9193 = mux(_T_9192, ic_tag_valid_out[0][101], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9194 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[ifu_mem_ctl.scala 697:33] - node _T_9195 = mux(_T_9194, ic_tag_valid_out[0][102], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9196 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[ifu_mem_ctl.scala 697:33] - node _T_9197 = mux(_T_9196, ic_tag_valid_out[0][103], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9198 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[ifu_mem_ctl.scala 697:33] - node _T_9199 = mux(_T_9198, ic_tag_valid_out[0][104], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9200 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[ifu_mem_ctl.scala 697:33] - node _T_9201 = mux(_T_9200, ic_tag_valid_out[0][105], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9202 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[ifu_mem_ctl.scala 697:33] - node _T_9203 = mux(_T_9202, ic_tag_valid_out[0][106], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9204 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[ifu_mem_ctl.scala 697:33] - node _T_9205 = mux(_T_9204, ic_tag_valid_out[0][107], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9206 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[ifu_mem_ctl.scala 697:33] - node _T_9207 = mux(_T_9206, ic_tag_valid_out[0][108], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9208 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[ifu_mem_ctl.scala 697:33] - node _T_9209 = mux(_T_9208, ic_tag_valid_out[0][109], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9210 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[ifu_mem_ctl.scala 697:33] - node _T_9211 = mux(_T_9210, ic_tag_valid_out[0][110], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9212 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[ifu_mem_ctl.scala 697:33] - node _T_9213 = mux(_T_9212, ic_tag_valid_out[0][111], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9214 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[ifu_mem_ctl.scala 697:33] - node _T_9215 = mux(_T_9214, ic_tag_valid_out[0][112], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9216 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[ifu_mem_ctl.scala 697:33] - node _T_9217 = mux(_T_9216, ic_tag_valid_out[0][113], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9218 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[ifu_mem_ctl.scala 697:33] - node _T_9219 = mux(_T_9218, ic_tag_valid_out[0][114], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9220 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[ifu_mem_ctl.scala 697:33] - node _T_9221 = mux(_T_9220, ic_tag_valid_out[0][115], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9222 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[ifu_mem_ctl.scala 697:33] - node _T_9223 = mux(_T_9222, ic_tag_valid_out[0][116], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9224 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[ifu_mem_ctl.scala 697:33] - node _T_9225 = mux(_T_9224, ic_tag_valid_out[0][117], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9226 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[ifu_mem_ctl.scala 697:33] - node _T_9227 = mux(_T_9226, ic_tag_valid_out[0][118], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9228 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[ifu_mem_ctl.scala 697:33] - node _T_9229 = mux(_T_9228, ic_tag_valid_out[0][119], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9230 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[ifu_mem_ctl.scala 697:33] - node _T_9231 = mux(_T_9230, ic_tag_valid_out[0][120], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9232 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[ifu_mem_ctl.scala 697:33] - node _T_9233 = mux(_T_9232, ic_tag_valid_out[0][121], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9234 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[ifu_mem_ctl.scala 697:33] - node _T_9235 = mux(_T_9234, ic_tag_valid_out[0][122], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9236 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[ifu_mem_ctl.scala 697:33] - node _T_9237 = mux(_T_9236, ic_tag_valid_out[0][123], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9238 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[ifu_mem_ctl.scala 697:33] - node _T_9239 = mux(_T_9238, ic_tag_valid_out[0][124], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9240 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[ifu_mem_ctl.scala 697:33] - node _T_9241 = mux(_T_9240, ic_tag_valid_out[0][125], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9242 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[ifu_mem_ctl.scala 697:33] - node _T_9243 = mux(_T_9242, ic_tag_valid_out[0][126], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9244 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[ifu_mem_ctl.scala 697:33] - node _T_9245 = mux(_T_9244, ic_tag_valid_out[0][127], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9246 = or(_T_8991, _T_8993) @[ifu_mem_ctl.scala 697:91] - node _T_9247 = or(_T_9246, _T_8995) @[ifu_mem_ctl.scala 697:91] - node _T_9248 = or(_T_9247, _T_8997) @[ifu_mem_ctl.scala 697:91] - node _T_9249 = or(_T_9248, _T_8999) @[ifu_mem_ctl.scala 697:91] - node _T_9250 = or(_T_9249, _T_9001) @[ifu_mem_ctl.scala 697:91] - node _T_9251 = or(_T_9250, _T_9003) @[ifu_mem_ctl.scala 697:91] - node _T_9252 = or(_T_9251, _T_9005) @[ifu_mem_ctl.scala 697:91] - node _T_9253 = or(_T_9252, _T_9007) @[ifu_mem_ctl.scala 697:91] - node _T_9254 = or(_T_9253, _T_9009) @[ifu_mem_ctl.scala 697:91] - node _T_9255 = or(_T_9254, _T_9011) @[ifu_mem_ctl.scala 697:91] - node _T_9256 = or(_T_9255, _T_9013) @[ifu_mem_ctl.scala 697:91] - node _T_9257 = or(_T_9256, _T_9015) @[ifu_mem_ctl.scala 697:91] - node _T_9258 = or(_T_9257, _T_9017) @[ifu_mem_ctl.scala 697:91] - node _T_9259 = or(_T_9258, _T_9019) @[ifu_mem_ctl.scala 697:91] - node _T_9260 = or(_T_9259, _T_9021) @[ifu_mem_ctl.scala 697:91] - node _T_9261 = or(_T_9260, _T_9023) @[ifu_mem_ctl.scala 697:91] - node _T_9262 = or(_T_9261, _T_9025) @[ifu_mem_ctl.scala 697:91] - node _T_9263 = or(_T_9262, _T_9027) @[ifu_mem_ctl.scala 697:91] - node _T_9264 = or(_T_9263, _T_9029) @[ifu_mem_ctl.scala 697:91] - node _T_9265 = or(_T_9264, _T_9031) @[ifu_mem_ctl.scala 697:91] - node _T_9266 = or(_T_9265, _T_9033) @[ifu_mem_ctl.scala 697:91] - node _T_9267 = or(_T_9266, _T_9035) @[ifu_mem_ctl.scala 697:91] - node _T_9268 = or(_T_9267, _T_9037) @[ifu_mem_ctl.scala 697:91] - node _T_9269 = or(_T_9268, _T_9039) @[ifu_mem_ctl.scala 697:91] - node _T_9270 = or(_T_9269, _T_9041) @[ifu_mem_ctl.scala 697:91] - node _T_9271 = or(_T_9270, _T_9043) @[ifu_mem_ctl.scala 697:91] - node _T_9272 = or(_T_9271, _T_9045) @[ifu_mem_ctl.scala 697:91] - node _T_9273 = or(_T_9272, _T_9047) @[ifu_mem_ctl.scala 697:91] - node _T_9274 = or(_T_9273, _T_9049) @[ifu_mem_ctl.scala 697:91] - node _T_9275 = or(_T_9274, _T_9051) @[ifu_mem_ctl.scala 697:91] - node _T_9276 = or(_T_9275, _T_9053) @[ifu_mem_ctl.scala 697:91] - node _T_9277 = or(_T_9276, _T_9055) @[ifu_mem_ctl.scala 697:91] - node _T_9278 = or(_T_9277, _T_9057) @[ifu_mem_ctl.scala 697:91] - node _T_9279 = or(_T_9278, _T_9059) @[ifu_mem_ctl.scala 697:91] - node _T_9280 = or(_T_9279, _T_9061) @[ifu_mem_ctl.scala 697:91] - node _T_9281 = or(_T_9280, _T_9063) @[ifu_mem_ctl.scala 697:91] - node _T_9282 = or(_T_9281, _T_9065) @[ifu_mem_ctl.scala 697:91] - node _T_9283 = or(_T_9282, _T_9067) @[ifu_mem_ctl.scala 697:91] - node _T_9284 = or(_T_9283, _T_9069) @[ifu_mem_ctl.scala 697:91] - node _T_9285 = or(_T_9284, _T_9071) @[ifu_mem_ctl.scala 697:91] - node _T_9286 = or(_T_9285, _T_9073) @[ifu_mem_ctl.scala 697:91] - node _T_9287 = or(_T_9286, _T_9075) @[ifu_mem_ctl.scala 697:91] - node _T_9288 = or(_T_9287, _T_9077) @[ifu_mem_ctl.scala 697:91] - node _T_9289 = or(_T_9288, _T_9079) @[ifu_mem_ctl.scala 697:91] - node _T_9290 = or(_T_9289, _T_9081) @[ifu_mem_ctl.scala 697:91] - node _T_9291 = or(_T_9290, _T_9083) @[ifu_mem_ctl.scala 697:91] - node _T_9292 = or(_T_9291, _T_9085) @[ifu_mem_ctl.scala 697:91] - node _T_9293 = or(_T_9292, _T_9087) @[ifu_mem_ctl.scala 697:91] - node _T_9294 = or(_T_9293, _T_9089) @[ifu_mem_ctl.scala 697:91] - node _T_9295 = or(_T_9294, _T_9091) @[ifu_mem_ctl.scala 697:91] - node _T_9296 = or(_T_9295, _T_9093) @[ifu_mem_ctl.scala 697:91] - node _T_9297 = or(_T_9296, _T_9095) @[ifu_mem_ctl.scala 697:91] - node _T_9298 = or(_T_9297, _T_9097) @[ifu_mem_ctl.scala 697:91] - node _T_9299 = or(_T_9298, _T_9099) @[ifu_mem_ctl.scala 697:91] - node _T_9300 = or(_T_9299, _T_9101) @[ifu_mem_ctl.scala 697:91] - node _T_9301 = or(_T_9300, _T_9103) @[ifu_mem_ctl.scala 697:91] - node _T_9302 = or(_T_9301, _T_9105) @[ifu_mem_ctl.scala 697:91] - node _T_9303 = or(_T_9302, _T_9107) @[ifu_mem_ctl.scala 697:91] - node _T_9304 = or(_T_9303, _T_9109) @[ifu_mem_ctl.scala 697:91] - node _T_9305 = or(_T_9304, _T_9111) @[ifu_mem_ctl.scala 697:91] - node _T_9306 = or(_T_9305, _T_9113) @[ifu_mem_ctl.scala 697:91] - node _T_9307 = or(_T_9306, _T_9115) @[ifu_mem_ctl.scala 697:91] - node _T_9308 = or(_T_9307, _T_9117) @[ifu_mem_ctl.scala 697:91] - node _T_9309 = or(_T_9308, _T_9119) @[ifu_mem_ctl.scala 697:91] - node _T_9310 = or(_T_9309, _T_9121) @[ifu_mem_ctl.scala 697:91] - node _T_9311 = or(_T_9310, _T_9123) @[ifu_mem_ctl.scala 697:91] - node _T_9312 = or(_T_9311, _T_9125) @[ifu_mem_ctl.scala 697:91] - node _T_9313 = or(_T_9312, _T_9127) @[ifu_mem_ctl.scala 697:91] - node _T_9314 = or(_T_9313, _T_9129) @[ifu_mem_ctl.scala 697:91] - node _T_9315 = or(_T_9314, _T_9131) @[ifu_mem_ctl.scala 697:91] - node _T_9316 = or(_T_9315, _T_9133) @[ifu_mem_ctl.scala 697:91] - node _T_9317 = or(_T_9316, _T_9135) @[ifu_mem_ctl.scala 697:91] - node _T_9318 = or(_T_9317, _T_9137) @[ifu_mem_ctl.scala 697:91] - node _T_9319 = or(_T_9318, _T_9139) @[ifu_mem_ctl.scala 697:91] - node _T_9320 = or(_T_9319, _T_9141) @[ifu_mem_ctl.scala 697:91] - node _T_9321 = or(_T_9320, _T_9143) @[ifu_mem_ctl.scala 697:91] - node _T_9322 = or(_T_9321, _T_9145) @[ifu_mem_ctl.scala 697:91] - node _T_9323 = or(_T_9322, _T_9147) @[ifu_mem_ctl.scala 697:91] - node _T_9324 = or(_T_9323, _T_9149) @[ifu_mem_ctl.scala 697:91] - node _T_9325 = or(_T_9324, _T_9151) @[ifu_mem_ctl.scala 697:91] - node _T_9326 = or(_T_9325, _T_9153) @[ifu_mem_ctl.scala 697:91] - node _T_9327 = or(_T_9326, _T_9155) @[ifu_mem_ctl.scala 697:91] - node _T_9328 = or(_T_9327, _T_9157) @[ifu_mem_ctl.scala 697:91] - node _T_9329 = or(_T_9328, _T_9159) @[ifu_mem_ctl.scala 697:91] - node _T_9330 = or(_T_9329, _T_9161) @[ifu_mem_ctl.scala 697:91] - node _T_9331 = or(_T_9330, _T_9163) @[ifu_mem_ctl.scala 697:91] - node _T_9332 = or(_T_9331, _T_9165) @[ifu_mem_ctl.scala 697:91] - node _T_9333 = or(_T_9332, _T_9167) @[ifu_mem_ctl.scala 697:91] - node _T_9334 = or(_T_9333, _T_9169) @[ifu_mem_ctl.scala 697:91] - node _T_9335 = or(_T_9334, _T_9171) @[ifu_mem_ctl.scala 697:91] - node _T_9336 = or(_T_9335, _T_9173) @[ifu_mem_ctl.scala 697:91] - node _T_9337 = or(_T_9336, _T_9175) @[ifu_mem_ctl.scala 697:91] - node _T_9338 = or(_T_9337, _T_9177) @[ifu_mem_ctl.scala 697:91] - node _T_9339 = or(_T_9338, _T_9179) @[ifu_mem_ctl.scala 697:91] - node _T_9340 = or(_T_9339, _T_9181) @[ifu_mem_ctl.scala 697:91] - node _T_9341 = or(_T_9340, _T_9183) @[ifu_mem_ctl.scala 697:91] - node _T_9342 = or(_T_9341, _T_9185) @[ifu_mem_ctl.scala 697:91] - node _T_9343 = or(_T_9342, _T_9187) @[ifu_mem_ctl.scala 697:91] - node _T_9344 = or(_T_9343, _T_9189) @[ifu_mem_ctl.scala 697:91] - node _T_9345 = or(_T_9344, _T_9191) @[ifu_mem_ctl.scala 697:91] - node _T_9346 = or(_T_9345, _T_9193) @[ifu_mem_ctl.scala 697:91] - node _T_9347 = or(_T_9346, _T_9195) @[ifu_mem_ctl.scala 697:91] - node _T_9348 = or(_T_9347, _T_9197) @[ifu_mem_ctl.scala 697:91] - node _T_9349 = or(_T_9348, _T_9199) @[ifu_mem_ctl.scala 697:91] - node _T_9350 = or(_T_9349, _T_9201) @[ifu_mem_ctl.scala 697:91] - node _T_9351 = or(_T_9350, _T_9203) @[ifu_mem_ctl.scala 697:91] - node _T_9352 = or(_T_9351, _T_9205) @[ifu_mem_ctl.scala 697:91] - node _T_9353 = or(_T_9352, _T_9207) @[ifu_mem_ctl.scala 697:91] - node _T_9354 = or(_T_9353, _T_9209) @[ifu_mem_ctl.scala 697:91] - node _T_9355 = or(_T_9354, _T_9211) @[ifu_mem_ctl.scala 697:91] - node _T_9356 = or(_T_9355, _T_9213) @[ifu_mem_ctl.scala 697:91] - node _T_9357 = or(_T_9356, _T_9215) @[ifu_mem_ctl.scala 697:91] - node _T_9358 = or(_T_9357, _T_9217) @[ifu_mem_ctl.scala 697:91] - node _T_9359 = or(_T_9358, _T_9219) @[ifu_mem_ctl.scala 697:91] - node _T_9360 = or(_T_9359, _T_9221) @[ifu_mem_ctl.scala 697:91] - node _T_9361 = or(_T_9360, _T_9223) @[ifu_mem_ctl.scala 697:91] - node _T_9362 = or(_T_9361, _T_9225) @[ifu_mem_ctl.scala 697:91] - node _T_9363 = or(_T_9362, _T_9227) @[ifu_mem_ctl.scala 697:91] - node _T_9364 = or(_T_9363, _T_9229) @[ifu_mem_ctl.scala 697:91] - node _T_9365 = or(_T_9364, _T_9231) @[ifu_mem_ctl.scala 697:91] - node _T_9366 = or(_T_9365, _T_9233) @[ifu_mem_ctl.scala 697:91] - node _T_9367 = or(_T_9366, _T_9235) @[ifu_mem_ctl.scala 697:91] - node _T_9368 = or(_T_9367, _T_9237) @[ifu_mem_ctl.scala 697:91] - node _T_9369 = or(_T_9368, _T_9239) @[ifu_mem_ctl.scala 697:91] - node _T_9370 = or(_T_9369, _T_9241) @[ifu_mem_ctl.scala 697:91] - node _T_9371 = or(_T_9370, _T_9243) @[ifu_mem_ctl.scala 697:91] - node _T_9372 = or(_T_9371, _T_9245) @[ifu_mem_ctl.scala 697:91] - node _T_9373 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 697:33] - node _T_9374 = mux(_T_9373, ic_tag_valid_out[1][0], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9375 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[ifu_mem_ctl.scala 697:33] - node _T_9376 = mux(_T_9375, ic_tag_valid_out[1][1], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9377 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[ifu_mem_ctl.scala 697:33] - node _T_9378 = mux(_T_9377, ic_tag_valid_out[1][2], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9379 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[ifu_mem_ctl.scala 697:33] - node _T_9380 = mux(_T_9379, ic_tag_valid_out[1][3], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9381 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[ifu_mem_ctl.scala 697:33] - node _T_9382 = mux(_T_9381, ic_tag_valid_out[1][4], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9383 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[ifu_mem_ctl.scala 697:33] - node _T_9384 = mux(_T_9383, ic_tag_valid_out[1][5], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9385 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[ifu_mem_ctl.scala 697:33] - node _T_9386 = mux(_T_9385, ic_tag_valid_out[1][6], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9387 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[ifu_mem_ctl.scala 697:33] - node _T_9388 = mux(_T_9387, ic_tag_valid_out[1][7], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9389 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[ifu_mem_ctl.scala 697:33] - node _T_9390 = mux(_T_9389, ic_tag_valid_out[1][8], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9391 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[ifu_mem_ctl.scala 697:33] - node _T_9392 = mux(_T_9391, ic_tag_valid_out[1][9], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9393 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[ifu_mem_ctl.scala 697:33] - node _T_9394 = mux(_T_9393, ic_tag_valid_out[1][10], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9395 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[ifu_mem_ctl.scala 697:33] - node _T_9396 = mux(_T_9395, ic_tag_valid_out[1][11], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9397 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[ifu_mem_ctl.scala 697:33] - node _T_9398 = mux(_T_9397, ic_tag_valid_out[1][12], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9399 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[ifu_mem_ctl.scala 697:33] - node _T_9400 = mux(_T_9399, ic_tag_valid_out[1][13], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9401 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[ifu_mem_ctl.scala 697:33] - node _T_9402 = mux(_T_9401, ic_tag_valid_out[1][14], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9403 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[ifu_mem_ctl.scala 697:33] - node _T_9404 = mux(_T_9403, ic_tag_valid_out[1][15], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9405 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[ifu_mem_ctl.scala 697:33] - node _T_9406 = mux(_T_9405, ic_tag_valid_out[1][16], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9407 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[ifu_mem_ctl.scala 697:33] - node _T_9408 = mux(_T_9407, ic_tag_valid_out[1][17], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9409 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[ifu_mem_ctl.scala 697:33] - node _T_9410 = mux(_T_9409, ic_tag_valid_out[1][18], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9411 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[ifu_mem_ctl.scala 697:33] - node _T_9412 = mux(_T_9411, ic_tag_valid_out[1][19], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9413 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[ifu_mem_ctl.scala 697:33] - node _T_9414 = mux(_T_9413, ic_tag_valid_out[1][20], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9415 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[ifu_mem_ctl.scala 697:33] - node _T_9416 = mux(_T_9415, ic_tag_valid_out[1][21], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9417 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[ifu_mem_ctl.scala 697:33] - node _T_9418 = mux(_T_9417, ic_tag_valid_out[1][22], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9419 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[ifu_mem_ctl.scala 697:33] - node _T_9420 = mux(_T_9419, ic_tag_valid_out[1][23], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9421 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[ifu_mem_ctl.scala 697:33] - node _T_9422 = mux(_T_9421, ic_tag_valid_out[1][24], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9423 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[ifu_mem_ctl.scala 697:33] - node _T_9424 = mux(_T_9423, ic_tag_valid_out[1][25], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9425 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[ifu_mem_ctl.scala 697:33] - node _T_9426 = mux(_T_9425, ic_tag_valid_out[1][26], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9427 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[ifu_mem_ctl.scala 697:33] - node _T_9428 = mux(_T_9427, ic_tag_valid_out[1][27], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9429 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[ifu_mem_ctl.scala 697:33] - node _T_9430 = mux(_T_9429, ic_tag_valid_out[1][28], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9431 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[ifu_mem_ctl.scala 697:33] - node _T_9432 = mux(_T_9431, ic_tag_valid_out[1][29], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9433 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[ifu_mem_ctl.scala 697:33] - node _T_9434 = mux(_T_9433, ic_tag_valid_out[1][30], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9435 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[ifu_mem_ctl.scala 697:33] - node _T_9436 = mux(_T_9435, ic_tag_valid_out[1][31], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9437 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[ifu_mem_ctl.scala 697:33] - node _T_9438 = mux(_T_9437, ic_tag_valid_out[1][32], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9439 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[ifu_mem_ctl.scala 697:33] - node _T_9440 = mux(_T_9439, ic_tag_valid_out[1][33], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9441 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[ifu_mem_ctl.scala 697:33] - node _T_9442 = mux(_T_9441, ic_tag_valid_out[1][34], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9443 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[ifu_mem_ctl.scala 697:33] - node _T_9444 = mux(_T_9443, ic_tag_valid_out[1][35], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9445 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[ifu_mem_ctl.scala 697:33] - node _T_9446 = mux(_T_9445, ic_tag_valid_out[1][36], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9447 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[ifu_mem_ctl.scala 697:33] - node _T_9448 = mux(_T_9447, ic_tag_valid_out[1][37], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9449 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[ifu_mem_ctl.scala 697:33] - node _T_9450 = mux(_T_9449, ic_tag_valid_out[1][38], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9451 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[ifu_mem_ctl.scala 697:33] - node _T_9452 = mux(_T_9451, ic_tag_valid_out[1][39], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9453 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[ifu_mem_ctl.scala 697:33] - node _T_9454 = mux(_T_9453, ic_tag_valid_out[1][40], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9455 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[ifu_mem_ctl.scala 697:33] - node _T_9456 = mux(_T_9455, ic_tag_valid_out[1][41], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9457 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[ifu_mem_ctl.scala 697:33] - node _T_9458 = mux(_T_9457, ic_tag_valid_out[1][42], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9459 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[ifu_mem_ctl.scala 697:33] - node _T_9460 = mux(_T_9459, ic_tag_valid_out[1][43], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9461 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[ifu_mem_ctl.scala 697:33] - node _T_9462 = mux(_T_9461, ic_tag_valid_out[1][44], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9463 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[ifu_mem_ctl.scala 697:33] - node _T_9464 = mux(_T_9463, ic_tag_valid_out[1][45], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9465 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[ifu_mem_ctl.scala 697:33] - node _T_9466 = mux(_T_9465, ic_tag_valid_out[1][46], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9467 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[ifu_mem_ctl.scala 697:33] - node _T_9468 = mux(_T_9467, ic_tag_valid_out[1][47], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9469 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[ifu_mem_ctl.scala 697:33] - node _T_9470 = mux(_T_9469, ic_tag_valid_out[1][48], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9471 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[ifu_mem_ctl.scala 697:33] - node _T_9472 = mux(_T_9471, ic_tag_valid_out[1][49], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9473 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[ifu_mem_ctl.scala 697:33] - node _T_9474 = mux(_T_9473, ic_tag_valid_out[1][50], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9475 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[ifu_mem_ctl.scala 697:33] - node _T_9476 = mux(_T_9475, ic_tag_valid_out[1][51], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9477 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[ifu_mem_ctl.scala 697:33] - node _T_9478 = mux(_T_9477, ic_tag_valid_out[1][52], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9479 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[ifu_mem_ctl.scala 697:33] - node _T_9480 = mux(_T_9479, ic_tag_valid_out[1][53], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9481 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[ifu_mem_ctl.scala 697:33] - node _T_9482 = mux(_T_9481, ic_tag_valid_out[1][54], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9483 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[ifu_mem_ctl.scala 697:33] - node _T_9484 = mux(_T_9483, ic_tag_valid_out[1][55], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9485 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[ifu_mem_ctl.scala 697:33] - node _T_9486 = mux(_T_9485, ic_tag_valid_out[1][56], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9487 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[ifu_mem_ctl.scala 697:33] - node _T_9488 = mux(_T_9487, ic_tag_valid_out[1][57], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9489 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[ifu_mem_ctl.scala 697:33] - node _T_9490 = mux(_T_9489, ic_tag_valid_out[1][58], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9491 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[ifu_mem_ctl.scala 697:33] - node _T_9492 = mux(_T_9491, ic_tag_valid_out[1][59], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9493 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[ifu_mem_ctl.scala 697:33] - node _T_9494 = mux(_T_9493, ic_tag_valid_out[1][60], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9495 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[ifu_mem_ctl.scala 697:33] - node _T_9496 = mux(_T_9495, ic_tag_valid_out[1][61], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9497 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[ifu_mem_ctl.scala 697:33] - node _T_9498 = mux(_T_9497, ic_tag_valid_out[1][62], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9499 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[ifu_mem_ctl.scala 697:33] - node _T_9500 = mux(_T_9499, ic_tag_valid_out[1][63], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9501 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[ifu_mem_ctl.scala 697:33] - node _T_9502 = mux(_T_9501, ic_tag_valid_out[1][64], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9503 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[ifu_mem_ctl.scala 697:33] - node _T_9504 = mux(_T_9503, ic_tag_valid_out[1][65], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9505 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[ifu_mem_ctl.scala 697:33] - node _T_9506 = mux(_T_9505, ic_tag_valid_out[1][66], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9507 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[ifu_mem_ctl.scala 697:33] - node _T_9508 = mux(_T_9507, ic_tag_valid_out[1][67], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9509 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[ifu_mem_ctl.scala 697:33] - node _T_9510 = mux(_T_9509, ic_tag_valid_out[1][68], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9511 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[ifu_mem_ctl.scala 697:33] - node _T_9512 = mux(_T_9511, ic_tag_valid_out[1][69], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9513 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[ifu_mem_ctl.scala 697:33] - node _T_9514 = mux(_T_9513, ic_tag_valid_out[1][70], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9515 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[ifu_mem_ctl.scala 697:33] - node _T_9516 = mux(_T_9515, ic_tag_valid_out[1][71], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9517 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[ifu_mem_ctl.scala 697:33] - node _T_9518 = mux(_T_9517, ic_tag_valid_out[1][72], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9519 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[ifu_mem_ctl.scala 697:33] - node _T_9520 = mux(_T_9519, ic_tag_valid_out[1][73], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9521 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[ifu_mem_ctl.scala 697:33] - node _T_9522 = mux(_T_9521, ic_tag_valid_out[1][74], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9523 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[ifu_mem_ctl.scala 697:33] - node _T_9524 = mux(_T_9523, ic_tag_valid_out[1][75], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9525 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[ifu_mem_ctl.scala 697:33] - node _T_9526 = mux(_T_9525, ic_tag_valid_out[1][76], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9527 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[ifu_mem_ctl.scala 697:33] - node _T_9528 = mux(_T_9527, ic_tag_valid_out[1][77], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9529 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[ifu_mem_ctl.scala 697:33] - node _T_9530 = mux(_T_9529, ic_tag_valid_out[1][78], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9531 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[ifu_mem_ctl.scala 697:33] - node _T_9532 = mux(_T_9531, ic_tag_valid_out[1][79], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9533 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[ifu_mem_ctl.scala 697:33] - node _T_9534 = mux(_T_9533, ic_tag_valid_out[1][80], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9535 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[ifu_mem_ctl.scala 697:33] - node _T_9536 = mux(_T_9535, ic_tag_valid_out[1][81], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9537 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[ifu_mem_ctl.scala 697:33] - node _T_9538 = mux(_T_9537, ic_tag_valid_out[1][82], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9539 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[ifu_mem_ctl.scala 697:33] - node _T_9540 = mux(_T_9539, ic_tag_valid_out[1][83], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9541 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[ifu_mem_ctl.scala 697:33] - node _T_9542 = mux(_T_9541, ic_tag_valid_out[1][84], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9543 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[ifu_mem_ctl.scala 697:33] - node _T_9544 = mux(_T_9543, ic_tag_valid_out[1][85], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9545 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[ifu_mem_ctl.scala 697:33] - node _T_9546 = mux(_T_9545, ic_tag_valid_out[1][86], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9547 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[ifu_mem_ctl.scala 697:33] - node _T_9548 = mux(_T_9547, ic_tag_valid_out[1][87], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9549 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[ifu_mem_ctl.scala 697:33] - node _T_9550 = mux(_T_9549, ic_tag_valid_out[1][88], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9551 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[ifu_mem_ctl.scala 697:33] - node _T_9552 = mux(_T_9551, ic_tag_valid_out[1][89], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9553 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[ifu_mem_ctl.scala 697:33] - node _T_9554 = mux(_T_9553, ic_tag_valid_out[1][90], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9555 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[ifu_mem_ctl.scala 697:33] - node _T_9556 = mux(_T_9555, ic_tag_valid_out[1][91], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9557 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[ifu_mem_ctl.scala 697:33] - node _T_9558 = mux(_T_9557, ic_tag_valid_out[1][92], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9559 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[ifu_mem_ctl.scala 697:33] - node _T_9560 = mux(_T_9559, ic_tag_valid_out[1][93], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9561 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[ifu_mem_ctl.scala 697:33] - node _T_9562 = mux(_T_9561, ic_tag_valid_out[1][94], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9563 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[ifu_mem_ctl.scala 697:33] - node _T_9564 = mux(_T_9563, ic_tag_valid_out[1][95], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9565 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[ifu_mem_ctl.scala 697:33] - node _T_9566 = mux(_T_9565, ic_tag_valid_out[1][96], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9567 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[ifu_mem_ctl.scala 697:33] - node _T_9568 = mux(_T_9567, ic_tag_valid_out[1][97], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9569 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[ifu_mem_ctl.scala 697:33] - node _T_9570 = mux(_T_9569, ic_tag_valid_out[1][98], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9571 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[ifu_mem_ctl.scala 697:33] - node _T_9572 = mux(_T_9571, ic_tag_valid_out[1][99], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9573 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[ifu_mem_ctl.scala 697:33] - node _T_9574 = mux(_T_9573, ic_tag_valid_out[1][100], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9575 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[ifu_mem_ctl.scala 697:33] - node _T_9576 = mux(_T_9575, ic_tag_valid_out[1][101], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9577 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[ifu_mem_ctl.scala 697:33] - node _T_9578 = mux(_T_9577, ic_tag_valid_out[1][102], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9579 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[ifu_mem_ctl.scala 697:33] - node _T_9580 = mux(_T_9579, ic_tag_valid_out[1][103], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9581 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[ifu_mem_ctl.scala 697:33] - node _T_9582 = mux(_T_9581, ic_tag_valid_out[1][104], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9583 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[ifu_mem_ctl.scala 697:33] - node _T_9584 = mux(_T_9583, ic_tag_valid_out[1][105], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9585 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[ifu_mem_ctl.scala 697:33] - node _T_9586 = mux(_T_9585, ic_tag_valid_out[1][106], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9587 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[ifu_mem_ctl.scala 697:33] - node _T_9588 = mux(_T_9587, ic_tag_valid_out[1][107], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9589 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[ifu_mem_ctl.scala 697:33] - node _T_9590 = mux(_T_9589, ic_tag_valid_out[1][108], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9591 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[ifu_mem_ctl.scala 697:33] - node _T_9592 = mux(_T_9591, ic_tag_valid_out[1][109], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9593 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[ifu_mem_ctl.scala 697:33] - node _T_9594 = mux(_T_9593, ic_tag_valid_out[1][110], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9595 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[ifu_mem_ctl.scala 697:33] - node _T_9596 = mux(_T_9595, ic_tag_valid_out[1][111], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9597 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[ifu_mem_ctl.scala 697:33] - node _T_9598 = mux(_T_9597, ic_tag_valid_out[1][112], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9599 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[ifu_mem_ctl.scala 697:33] - node _T_9600 = mux(_T_9599, ic_tag_valid_out[1][113], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9601 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[ifu_mem_ctl.scala 697:33] - node _T_9602 = mux(_T_9601, ic_tag_valid_out[1][114], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9603 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[ifu_mem_ctl.scala 697:33] - node _T_9604 = mux(_T_9603, ic_tag_valid_out[1][115], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9605 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[ifu_mem_ctl.scala 697:33] - node _T_9606 = mux(_T_9605, ic_tag_valid_out[1][116], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9607 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[ifu_mem_ctl.scala 697:33] - node _T_9608 = mux(_T_9607, ic_tag_valid_out[1][117], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9609 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[ifu_mem_ctl.scala 697:33] - node _T_9610 = mux(_T_9609, ic_tag_valid_out[1][118], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9611 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[ifu_mem_ctl.scala 697:33] - node _T_9612 = mux(_T_9611, ic_tag_valid_out[1][119], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9613 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[ifu_mem_ctl.scala 697:33] - node _T_9614 = mux(_T_9613, ic_tag_valid_out[1][120], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9615 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[ifu_mem_ctl.scala 697:33] - node _T_9616 = mux(_T_9615, ic_tag_valid_out[1][121], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9617 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[ifu_mem_ctl.scala 697:33] - node _T_9618 = mux(_T_9617, ic_tag_valid_out[1][122], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9619 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[ifu_mem_ctl.scala 697:33] - node _T_9620 = mux(_T_9619, ic_tag_valid_out[1][123], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9621 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[ifu_mem_ctl.scala 697:33] - node _T_9622 = mux(_T_9621, ic_tag_valid_out[1][124], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9623 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[ifu_mem_ctl.scala 697:33] - node _T_9624 = mux(_T_9623, ic_tag_valid_out[1][125], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9625 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[ifu_mem_ctl.scala 697:33] - node _T_9626 = mux(_T_9625, ic_tag_valid_out[1][126], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9627 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[ifu_mem_ctl.scala 697:33] - node _T_9628 = mux(_T_9627, ic_tag_valid_out[1][127], UInt<1>("h00")) @[ifu_mem_ctl.scala 697:10] - node _T_9629 = or(_T_9374, _T_9376) @[ifu_mem_ctl.scala 697:91] - node _T_9630 = or(_T_9629, _T_9378) @[ifu_mem_ctl.scala 697:91] - node _T_9631 = or(_T_9630, _T_9380) @[ifu_mem_ctl.scala 697:91] - node _T_9632 = or(_T_9631, _T_9382) @[ifu_mem_ctl.scala 697:91] - node _T_9633 = or(_T_9632, _T_9384) @[ifu_mem_ctl.scala 697:91] - node _T_9634 = or(_T_9633, _T_9386) @[ifu_mem_ctl.scala 697:91] - node _T_9635 = or(_T_9634, _T_9388) @[ifu_mem_ctl.scala 697:91] - node _T_9636 = or(_T_9635, _T_9390) @[ifu_mem_ctl.scala 697:91] - node _T_9637 = or(_T_9636, _T_9392) @[ifu_mem_ctl.scala 697:91] - node _T_9638 = or(_T_9637, _T_9394) @[ifu_mem_ctl.scala 697:91] - node _T_9639 = or(_T_9638, _T_9396) @[ifu_mem_ctl.scala 697:91] - node _T_9640 = or(_T_9639, _T_9398) @[ifu_mem_ctl.scala 697:91] - node _T_9641 = or(_T_9640, _T_9400) @[ifu_mem_ctl.scala 697:91] - node _T_9642 = or(_T_9641, _T_9402) @[ifu_mem_ctl.scala 697:91] - node _T_9643 = or(_T_9642, _T_9404) @[ifu_mem_ctl.scala 697:91] - node _T_9644 = or(_T_9643, _T_9406) @[ifu_mem_ctl.scala 697:91] - node _T_9645 = or(_T_9644, _T_9408) @[ifu_mem_ctl.scala 697:91] - node _T_9646 = or(_T_9645, _T_9410) @[ifu_mem_ctl.scala 697:91] - node _T_9647 = or(_T_9646, _T_9412) @[ifu_mem_ctl.scala 697:91] - node _T_9648 = or(_T_9647, _T_9414) @[ifu_mem_ctl.scala 697:91] - node _T_9649 = or(_T_9648, _T_9416) @[ifu_mem_ctl.scala 697:91] - node _T_9650 = or(_T_9649, _T_9418) @[ifu_mem_ctl.scala 697:91] - node _T_9651 = or(_T_9650, _T_9420) @[ifu_mem_ctl.scala 697:91] - node _T_9652 = or(_T_9651, _T_9422) @[ifu_mem_ctl.scala 697:91] - node _T_9653 = or(_T_9652, _T_9424) @[ifu_mem_ctl.scala 697:91] - node _T_9654 = or(_T_9653, _T_9426) @[ifu_mem_ctl.scala 697:91] - node _T_9655 = or(_T_9654, _T_9428) @[ifu_mem_ctl.scala 697:91] - node _T_9656 = or(_T_9655, _T_9430) @[ifu_mem_ctl.scala 697:91] - node _T_9657 = or(_T_9656, _T_9432) @[ifu_mem_ctl.scala 697:91] - node _T_9658 = or(_T_9657, _T_9434) @[ifu_mem_ctl.scala 697:91] - node _T_9659 = or(_T_9658, _T_9436) @[ifu_mem_ctl.scala 697:91] - node _T_9660 = or(_T_9659, _T_9438) @[ifu_mem_ctl.scala 697:91] - node _T_9661 = or(_T_9660, _T_9440) @[ifu_mem_ctl.scala 697:91] - node _T_9662 = or(_T_9661, _T_9442) @[ifu_mem_ctl.scala 697:91] - node _T_9663 = or(_T_9662, _T_9444) @[ifu_mem_ctl.scala 697:91] - node _T_9664 = or(_T_9663, _T_9446) @[ifu_mem_ctl.scala 697:91] - node _T_9665 = or(_T_9664, _T_9448) @[ifu_mem_ctl.scala 697:91] - node _T_9666 = or(_T_9665, _T_9450) @[ifu_mem_ctl.scala 697:91] - node _T_9667 = or(_T_9666, _T_9452) @[ifu_mem_ctl.scala 697:91] - node _T_9668 = or(_T_9667, _T_9454) @[ifu_mem_ctl.scala 697:91] - node _T_9669 = or(_T_9668, _T_9456) @[ifu_mem_ctl.scala 697:91] - node _T_9670 = or(_T_9669, _T_9458) @[ifu_mem_ctl.scala 697:91] - node _T_9671 = or(_T_9670, _T_9460) @[ifu_mem_ctl.scala 697:91] - node _T_9672 = or(_T_9671, _T_9462) @[ifu_mem_ctl.scala 697:91] - node _T_9673 = or(_T_9672, _T_9464) @[ifu_mem_ctl.scala 697:91] - node _T_9674 = or(_T_9673, _T_9466) @[ifu_mem_ctl.scala 697:91] - node _T_9675 = or(_T_9674, _T_9468) @[ifu_mem_ctl.scala 697:91] - node _T_9676 = or(_T_9675, _T_9470) @[ifu_mem_ctl.scala 697:91] - node _T_9677 = or(_T_9676, _T_9472) @[ifu_mem_ctl.scala 697:91] - node _T_9678 = or(_T_9677, _T_9474) @[ifu_mem_ctl.scala 697:91] - node _T_9679 = or(_T_9678, _T_9476) @[ifu_mem_ctl.scala 697:91] - node _T_9680 = or(_T_9679, _T_9478) @[ifu_mem_ctl.scala 697:91] - node _T_9681 = or(_T_9680, _T_9480) @[ifu_mem_ctl.scala 697:91] - node _T_9682 = or(_T_9681, _T_9482) @[ifu_mem_ctl.scala 697:91] - node _T_9683 = or(_T_9682, _T_9484) @[ifu_mem_ctl.scala 697:91] - node _T_9684 = or(_T_9683, _T_9486) @[ifu_mem_ctl.scala 697:91] - node _T_9685 = or(_T_9684, _T_9488) @[ifu_mem_ctl.scala 697:91] - node _T_9686 = or(_T_9685, _T_9490) @[ifu_mem_ctl.scala 697:91] - node _T_9687 = or(_T_9686, _T_9492) @[ifu_mem_ctl.scala 697:91] - node _T_9688 = or(_T_9687, _T_9494) @[ifu_mem_ctl.scala 697:91] - node _T_9689 = or(_T_9688, _T_9496) @[ifu_mem_ctl.scala 697:91] - node _T_9690 = or(_T_9689, _T_9498) @[ifu_mem_ctl.scala 697:91] - node _T_9691 = or(_T_9690, _T_9500) @[ifu_mem_ctl.scala 697:91] - node _T_9692 = or(_T_9691, _T_9502) @[ifu_mem_ctl.scala 697:91] - node _T_9693 = or(_T_9692, _T_9504) @[ifu_mem_ctl.scala 697:91] - node _T_9694 = or(_T_9693, _T_9506) @[ifu_mem_ctl.scala 697:91] - node _T_9695 = or(_T_9694, _T_9508) @[ifu_mem_ctl.scala 697:91] - node _T_9696 = or(_T_9695, _T_9510) @[ifu_mem_ctl.scala 697:91] - node _T_9697 = or(_T_9696, _T_9512) @[ifu_mem_ctl.scala 697:91] - node _T_9698 = or(_T_9697, _T_9514) @[ifu_mem_ctl.scala 697:91] - node _T_9699 = or(_T_9698, _T_9516) @[ifu_mem_ctl.scala 697:91] - node _T_9700 = or(_T_9699, _T_9518) @[ifu_mem_ctl.scala 697:91] - node _T_9701 = or(_T_9700, _T_9520) @[ifu_mem_ctl.scala 697:91] - node _T_9702 = or(_T_9701, _T_9522) @[ifu_mem_ctl.scala 697:91] - node _T_9703 = or(_T_9702, _T_9524) @[ifu_mem_ctl.scala 697:91] - node _T_9704 = or(_T_9703, _T_9526) @[ifu_mem_ctl.scala 697:91] - node _T_9705 = or(_T_9704, _T_9528) @[ifu_mem_ctl.scala 697:91] - node _T_9706 = or(_T_9705, _T_9530) @[ifu_mem_ctl.scala 697:91] - node _T_9707 = or(_T_9706, _T_9532) @[ifu_mem_ctl.scala 697:91] - node _T_9708 = or(_T_9707, _T_9534) @[ifu_mem_ctl.scala 697:91] - node _T_9709 = or(_T_9708, _T_9536) @[ifu_mem_ctl.scala 697:91] - node _T_9710 = or(_T_9709, _T_9538) @[ifu_mem_ctl.scala 697:91] - node _T_9711 = or(_T_9710, _T_9540) @[ifu_mem_ctl.scala 697:91] - node _T_9712 = or(_T_9711, _T_9542) @[ifu_mem_ctl.scala 697:91] - node _T_9713 = or(_T_9712, _T_9544) @[ifu_mem_ctl.scala 697:91] - node _T_9714 = or(_T_9713, _T_9546) @[ifu_mem_ctl.scala 697:91] - node _T_9715 = or(_T_9714, _T_9548) @[ifu_mem_ctl.scala 697:91] - node _T_9716 = or(_T_9715, _T_9550) @[ifu_mem_ctl.scala 697:91] - node _T_9717 = or(_T_9716, _T_9552) @[ifu_mem_ctl.scala 697:91] - node _T_9718 = or(_T_9717, _T_9554) @[ifu_mem_ctl.scala 697:91] - node _T_9719 = or(_T_9718, _T_9556) @[ifu_mem_ctl.scala 697:91] - node _T_9720 = or(_T_9719, _T_9558) @[ifu_mem_ctl.scala 697:91] - node _T_9721 = or(_T_9720, _T_9560) @[ifu_mem_ctl.scala 697:91] - node _T_9722 = or(_T_9721, _T_9562) @[ifu_mem_ctl.scala 697:91] - node _T_9723 = or(_T_9722, _T_9564) @[ifu_mem_ctl.scala 697:91] - node _T_9724 = or(_T_9723, _T_9566) @[ifu_mem_ctl.scala 697:91] - node _T_9725 = or(_T_9724, _T_9568) @[ifu_mem_ctl.scala 697:91] - node _T_9726 = or(_T_9725, _T_9570) @[ifu_mem_ctl.scala 697:91] - node _T_9727 = or(_T_9726, _T_9572) @[ifu_mem_ctl.scala 697:91] - node _T_9728 = or(_T_9727, _T_9574) @[ifu_mem_ctl.scala 697:91] - node _T_9729 = or(_T_9728, _T_9576) @[ifu_mem_ctl.scala 697:91] - node _T_9730 = or(_T_9729, _T_9578) @[ifu_mem_ctl.scala 697:91] - node _T_9731 = or(_T_9730, _T_9580) @[ifu_mem_ctl.scala 697:91] - node _T_9732 = or(_T_9731, _T_9582) @[ifu_mem_ctl.scala 697:91] - node _T_9733 = or(_T_9732, _T_9584) @[ifu_mem_ctl.scala 697:91] - node _T_9734 = or(_T_9733, _T_9586) @[ifu_mem_ctl.scala 697:91] - node _T_9735 = or(_T_9734, _T_9588) @[ifu_mem_ctl.scala 697:91] - node _T_9736 = or(_T_9735, _T_9590) @[ifu_mem_ctl.scala 697:91] - node _T_9737 = or(_T_9736, _T_9592) @[ifu_mem_ctl.scala 697:91] - node _T_9738 = or(_T_9737, _T_9594) @[ifu_mem_ctl.scala 697:91] - node _T_9739 = or(_T_9738, _T_9596) @[ifu_mem_ctl.scala 697:91] - node _T_9740 = or(_T_9739, _T_9598) @[ifu_mem_ctl.scala 697:91] - node _T_9741 = or(_T_9740, _T_9600) @[ifu_mem_ctl.scala 697:91] - node _T_9742 = or(_T_9741, _T_9602) @[ifu_mem_ctl.scala 697:91] - node _T_9743 = or(_T_9742, _T_9604) @[ifu_mem_ctl.scala 697:91] - node _T_9744 = or(_T_9743, _T_9606) @[ifu_mem_ctl.scala 697:91] - node _T_9745 = or(_T_9744, _T_9608) @[ifu_mem_ctl.scala 697:91] - node _T_9746 = or(_T_9745, _T_9610) @[ifu_mem_ctl.scala 697:91] - node _T_9747 = or(_T_9746, _T_9612) @[ifu_mem_ctl.scala 697:91] - node _T_9748 = or(_T_9747, _T_9614) @[ifu_mem_ctl.scala 697:91] - node _T_9749 = or(_T_9748, _T_9616) @[ifu_mem_ctl.scala 697:91] - node _T_9750 = or(_T_9749, _T_9618) @[ifu_mem_ctl.scala 697:91] - node _T_9751 = or(_T_9750, _T_9620) @[ifu_mem_ctl.scala 697:91] - node _T_9752 = or(_T_9751, _T_9622) @[ifu_mem_ctl.scala 697:91] - node _T_9753 = or(_T_9752, _T_9624) @[ifu_mem_ctl.scala 697:91] - node _T_9754 = or(_T_9753, _T_9626) @[ifu_mem_ctl.scala 697:91] - node _T_9755 = or(_T_9754, _T_9628) @[ifu_mem_ctl.scala 697:91] + ic_tag_valid_out[1][127] <= _T_8989 @[ifu_mem_ctl.scala 692:41] + node _T_8990 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 696:33] + node _T_8991 = mux(_T_8990, ic_tag_valid_out[0][0], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_8992 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[ifu_mem_ctl.scala 696:33] + node _T_8993 = mux(_T_8992, ic_tag_valid_out[0][1], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_8994 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[ifu_mem_ctl.scala 696:33] + node _T_8995 = mux(_T_8994, ic_tag_valid_out[0][2], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_8996 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[ifu_mem_ctl.scala 696:33] + node _T_8997 = mux(_T_8996, ic_tag_valid_out[0][3], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_8998 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[ifu_mem_ctl.scala 696:33] + node _T_8999 = mux(_T_8998, ic_tag_valid_out[0][4], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9000 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[ifu_mem_ctl.scala 696:33] + node _T_9001 = mux(_T_9000, ic_tag_valid_out[0][5], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9002 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[ifu_mem_ctl.scala 696:33] + node _T_9003 = mux(_T_9002, ic_tag_valid_out[0][6], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9004 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[ifu_mem_ctl.scala 696:33] + node _T_9005 = mux(_T_9004, ic_tag_valid_out[0][7], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9006 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[ifu_mem_ctl.scala 696:33] + node _T_9007 = mux(_T_9006, ic_tag_valid_out[0][8], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9008 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[ifu_mem_ctl.scala 696:33] + node _T_9009 = mux(_T_9008, ic_tag_valid_out[0][9], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9010 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[ifu_mem_ctl.scala 696:33] + node _T_9011 = mux(_T_9010, ic_tag_valid_out[0][10], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9012 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[ifu_mem_ctl.scala 696:33] + node _T_9013 = mux(_T_9012, ic_tag_valid_out[0][11], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9014 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[ifu_mem_ctl.scala 696:33] + node _T_9015 = mux(_T_9014, ic_tag_valid_out[0][12], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9016 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[ifu_mem_ctl.scala 696:33] + node _T_9017 = mux(_T_9016, ic_tag_valid_out[0][13], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9018 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[ifu_mem_ctl.scala 696:33] + node _T_9019 = mux(_T_9018, ic_tag_valid_out[0][14], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9020 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[ifu_mem_ctl.scala 696:33] + node _T_9021 = mux(_T_9020, ic_tag_valid_out[0][15], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9022 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[ifu_mem_ctl.scala 696:33] + node _T_9023 = mux(_T_9022, ic_tag_valid_out[0][16], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9024 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[ifu_mem_ctl.scala 696:33] + node _T_9025 = mux(_T_9024, ic_tag_valid_out[0][17], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9026 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[ifu_mem_ctl.scala 696:33] + node _T_9027 = mux(_T_9026, ic_tag_valid_out[0][18], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9028 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[ifu_mem_ctl.scala 696:33] + node _T_9029 = mux(_T_9028, ic_tag_valid_out[0][19], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9030 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[ifu_mem_ctl.scala 696:33] + node _T_9031 = mux(_T_9030, ic_tag_valid_out[0][20], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9032 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[ifu_mem_ctl.scala 696:33] + node _T_9033 = mux(_T_9032, ic_tag_valid_out[0][21], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9034 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[ifu_mem_ctl.scala 696:33] + node _T_9035 = mux(_T_9034, ic_tag_valid_out[0][22], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9036 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[ifu_mem_ctl.scala 696:33] + node _T_9037 = mux(_T_9036, ic_tag_valid_out[0][23], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9038 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[ifu_mem_ctl.scala 696:33] + node _T_9039 = mux(_T_9038, ic_tag_valid_out[0][24], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9040 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[ifu_mem_ctl.scala 696:33] + node _T_9041 = mux(_T_9040, ic_tag_valid_out[0][25], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9042 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[ifu_mem_ctl.scala 696:33] + node _T_9043 = mux(_T_9042, ic_tag_valid_out[0][26], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9044 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[ifu_mem_ctl.scala 696:33] + node _T_9045 = mux(_T_9044, ic_tag_valid_out[0][27], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9046 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[ifu_mem_ctl.scala 696:33] + node _T_9047 = mux(_T_9046, ic_tag_valid_out[0][28], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9048 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[ifu_mem_ctl.scala 696:33] + node _T_9049 = mux(_T_9048, ic_tag_valid_out[0][29], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9050 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[ifu_mem_ctl.scala 696:33] + node _T_9051 = mux(_T_9050, ic_tag_valid_out[0][30], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9052 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[ifu_mem_ctl.scala 696:33] + node _T_9053 = mux(_T_9052, ic_tag_valid_out[0][31], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9054 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[ifu_mem_ctl.scala 696:33] + node _T_9055 = mux(_T_9054, ic_tag_valid_out[0][32], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9056 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[ifu_mem_ctl.scala 696:33] + node _T_9057 = mux(_T_9056, ic_tag_valid_out[0][33], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9058 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[ifu_mem_ctl.scala 696:33] + node _T_9059 = mux(_T_9058, ic_tag_valid_out[0][34], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9060 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[ifu_mem_ctl.scala 696:33] + node _T_9061 = mux(_T_9060, ic_tag_valid_out[0][35], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9062 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[ifu_mem_ctl.scala 696:33] + node _T_9063 = mux(_T_9062, ic_tag_valid_out[0][36], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9064 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[ifu_mem_ctl.scala 696:33] + node _T_9065 = mux(_T_9064, ic_tag_valid_out[0][37], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9066 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[ifu_mem_ctl.scala 696:33] + node _T_9067 = mux(_T_9066, ic_tag_valid_out[0][38], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9068 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[ifu_mem_ctl.scala 696:33] + node _T_9069 = mux(_T_9068, ic_tag_valid_out[0][39], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9070 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[ifu_mem_ctl.scala 696:33] + node _T_9071 = mux(_T_9070, ic_tag_valid_out[0][40], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9072 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[ifu_mem_ctl.scala 696:33] + node _T_9073 = mux(_T_9072, ic_tag_valid_out[0][41], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9074 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[ifu_mem_ctl.scala 696:33] + node _T_9075 = mux(_T_9074, ic_tag_valid_out[0][42], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9076 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[ifu_mem_ctl.scala 696:33] + node _T_9077 = mux(_T_9076, ic_tag_valid_out[0][43], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9078 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[ifu_mem_ctl.scala 696:33] + node _T_9079 = mux(_T_9078, ic_tag_valid_out[0][44], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9080 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[ifu_mem_ctl.scala 696:33] + node _T_9081 = mux(_T_9080, ic_tag_valid_out[0][45], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9082 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[ifu_mem_ctl.scala 696:33] + node _T_9083 = mux(_T_9082, ic_tag_valid_out[0][46], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9084 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[ifu_mem_ctl.scala 696:33] + node _T_9085 = mux(_T_9084, ic_tag_valid_out[0][47], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9086 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[ifu_mem_ctl.scala 696:33] + node _T_9087 = mux(_T_9086, ic_tag_valid_out[0][48], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9088 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[ifu_mem_ctl.scala 696:33] + node _T_9089 = mux(_T_9088, ic_tag_valid_out[0][49], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9090 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[ifu_mem_ctl.scala 696:33] + node _T_9091 = mux(_T_9090, ic_tag_valid_out[0][50], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9092 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[ifu_mem_ctl.scala 696:33] + node _T_9093 = mux(_T_9092, ic_tag_valid_out[0][51], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9094 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[ifu_mem_ctl.scala 696:33] + node _T_9095 = mux(_T_9094, ic_tag_valid_out[0][52], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9096 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[ifu_mem_ctl.scala 696:33] + node _T_9097 = mux(_T_9096, ic_tag_valid_out[0][53], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9098 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[ifu_mem_ctl.scala 696:33] + node _T_9099 = mux(_T_9098, ic_tag_valid_out[0][54], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9100 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[ifu_mem_ctl.scala 696:33] + node _T_9101 = mux(_T_9100, ic_tag_valid_out[0][55], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9102 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[ifu_mem_ctl.scala 696:33] + node _T_9103 = mux(_T_9102, ic_tag_valid_out[0][56], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9104 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[ifu_mem_ctl.scala 696:33] + node _T_9105 = mux(_T_9104, ic_tag_valid_out[0][57], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9106 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[ifu_mem_ctl.scala 696:33] + node _T_9107 = mux(_T_9106, ic_tag_valid_out[0][58], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9108 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[ifu_mem_ctl.scala 696:33] + node _T_9109 = mux(_T_9108, ic_tag_valid_out[0][59], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9110 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[ifu_mem_ctl.scala 696:33] + node _T_9111 = mux(_T_9110, ic_tag_valid_out[0][60], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9112 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[ifu_mem_ctl.scala 696:33] + node _T_9113 = mux(_T_9112, ic_tag_valid_out[0][61], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9114 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[ifu_mem_ctl.scala 696:33] + node _T_9115 = mux(_T_9114, ic_tag_valid_out[0][62], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9116 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[ifu_mem_ctl.scala 696:33] + node _T_9117 = mux(_T_9116, ic_tag_valid_out[0][63], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9118 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[ifu_mem_ctl.scala 696:33] + node _T_9119 = mux(_T_9118, ic_tag_valid_out[0][64], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9120 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[ifu_mem_ctl.scala 696:33] + node _T_9121 = mux(_T_9120, ic_tag_valid_out[0][65], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9122 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[ifu_mem_ctl.scala 696:33] + node _T_9123 = mux(_T_9122, ic_tag_valid_out[0][66], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9124 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[ifu_mem_ctl.scala 696:33] + node _T_9125 = mux(_T_9124, ic_tag_valid_out[0][67], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9126 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[ifu_mem_ctl.scala 696:33] + node _T_9127 = mux(_T_9126, ic_tag_valid_out[0][68], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9128 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[ifu_mem_ctl.scala 696:33] + node _T_9129 = mux(_T_9128, ic_tag_valid_out[0][69], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9130 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[ifu_mem_ctl.scala 696:33] + node _T_9131 = mux(_T_9130, ic_tag_valid_out[0][70], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9132 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[ifu_mem_ctl.scala 696:33] + node _T_9133 = mux(_T_9132, ic_tag_valid_out[0][71], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9134 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[ifu_mem_ctl.scala 696:33] + node _T_9135 = mux(_T_9134, ic_tag_valid_out[0][72], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9136 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[ifu_mem_ctl.scala 696:33] + node _T_9137 = mux(_T_9136, ic_tag_valid_out[0][73], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9138 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[ifu_mem_ctl.scala 696:33] + node _T_9139 = mux(_T_9138, ic_tag_valid_out[0][74], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9140 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[ifu_mem_ctl.scala 696:33] + node _T_9141 = mux(_T_9140, ic_tag_valid_out[0][75], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9142 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[ifu_mem_ctl.scala 696:33] + node _T_9143 = mux(_T_9142, ic_tag_valid_out[0][76], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9144 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[ifu_mem_ctl.scala 696:33] + node _T_9145 = mux(_T_9144, ic_tag_valid_out[0][77], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9146 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[ifu_mem_ctl.scala 696:33] + node _T_9147 = mux(_T_9146, ic_tag_valid_out[0][78], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9148 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[ifu_mem_ctl.scala 696:33] + node _T_9149 = mux(_T_9148, ic_tag_valid_out[0][79], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9150 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[ifu_mem_ctl.scala 696:33] + node _T_9151 = mux(_T_9150, ic_tag_valid_out[0][80], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9152 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[ifu_mem_ctl.scala 696:33] + node _T_9153 = mux(_T_9152, ic_tag_valid_out[0][81], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9154 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[ifu_mem_ctl.scala 696:33] + node _T_9155 = mux(_T_9154, ic_tag_valid_out[0][82], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9156 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[ifu_mem_ctl.scala 696:33] + node _T_9157 = mux(_T_9156, ic_tag_valid_out[0][83], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9158 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[ifu_mem_ctl.scala 696:33] + node _T_9159 = mux(_T_9158, ic_tag_valid_out[0][84], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9160 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[ifu_mem_ctl.scala 696:33] + node _T_9161 = mux(_T_9160, ic_tag_valid_out[0][85], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9162 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[ifu_mem_ctl.scala 696:33] + node _T_9163 = mux(_T_9162, ic_tag_valid_out[0][86], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9164 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[ifu_mem_ctl.scala 696:33] + node _T_9165 = mux(_T_9164, ic_tag_valid_out[0][87], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9166 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[ifu_mem_ctl.scala 696:33] + node _T_9167 = mux(_T_9166, ic_tag_valid_out[0][88], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9168 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[ifu_mem_ctl.scala 696:33] + node _T_9169 = mux(_T_9168, ic_tag_valid_out[0][89], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9170 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[ifu_mem_ctl.scala 696:33] + node _T_9171 = mux(_T_9170, ic_tag_valid_out[0][90], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9172 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[ifu_mem_ctl.scala 696:33] + node _T_9173 = mux(_T_9172, ic_tag_valid_out[0][91], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9174 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[ifu_mem_ctl.scala 696:33] + node _T_9175 = mux(_T_9174, ic_tag_valid_out[0][92], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9176 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[ifu_mem_ctl.scala 696:33] + node _T_9177 = mux(_T_9176, ic_tag_valid_out[0][93], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9178 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[ifu_mem_ctl.scala 696:33] + node _T_9179 = mux(_T_9178, ic_tag_valid_out[0][94], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9180 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[ifu_mem_ctl.scala 696:33] + node _T_9181 = mux(_T_9180, ic_tag_valid_out[0][95], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9182 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[ifu_mem_ctl.scala 696:33] + node _T_9183 = mux(_T_9182, ic_tag_valid_out[0][96], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9184 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[ifu_mem_ctl.scala 696:33] + node _T_9185 = mux(_T_9184, ic_tag_valid_out[0][97], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9186 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[ifu_mem_ctl.scala 696:33] + node _T_9187 = mux(_T_9186, ic_tag_valid_out[0][98], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9188 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[ifu_mem_ctl.scala 696:33] + node _T_9189 = mux(_T_9188, ic_tag_valid_out[0][99], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9190 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[ifu_mem_ctl.scala 696:33] + node _T_9191 = mux(_T_9190, ic_tag_valid_out[0][100], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9192 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[ifu_mem_ctl.scala 696:33] + node _T_9193 = mux(_T_9192, ic_tag_valid_out[0][101], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9194 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[ifu_mem_ctl.scala 696:33] + node _T_9195 = mux(_T_9194, ic_tag_valid_out[0][102], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9196 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[ifu_mem_ctl.scala 696:33] + node _T_9197 = mux(_T_9196, ic_tag_valid_out[0][103], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9198 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[ifu_mem_ctl.scala 696:33] + node _T_9199 = mux(_T_9198, ic_tag_valid_out[0][104], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9200 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[ifu_mem_ctl.scala 696:33] + node _T_9201 = mux(_T_9200, ic_tag_valid_out[0][105], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9202 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[ifu_mem_ctl.scala 696:33] + node _T_9203 = mux(_T_9202, ic_tag_valid_out[0][106], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9204 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[ifu_mem_ctl.scala 696:33] + node _T_9205 = mux(_T_9204, ic_tag_valid_out[0][107], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9206 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[ifu_mem_ctl.scala 696:33] + node _T_9207 = mux(_T_9206, ic_tag_valid_out[0][108], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9208 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[ifu_mem_ctl.scala 696:33] + node _T_9209 = mux(_T_9208, ic_tag_valid_out[0][109], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9210 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[ifu_mem_ctl.scala 696:33] + node _T_9211 = mux(_T_9210, ic_tag_valid_out[0][110], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9212 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[ifu_mem_ctl.scala 696:33] + node _T_9213 = mux(_T_9212, ic_tag_valid_out[0][111], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9214 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[ifu_mem_ctl.scala 696:33] + node _T_9215 = mux(_T_9214, ic_tag_valid_out[0][112], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9216 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[ifu_mem_ctl.scala 696:33] + node _T_9217 = mux(_T_9216, ic_tag_valid_out[0][113], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9218 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[ifu_mem_ctl.scala 696:33] + node _T_9219 = mux(_T_9218, ic_tag_valid_out[0][114], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9220 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[ifu_mem_ctl.scala 696:33] + node _T_9221 = mux(_T_9220, ic_tag_valid_out[0][115], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9222 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[ifu_mem_ctl.scala 696:33] + node _T_9223 = mux(_T_9222, ic_tag_valid_out[0][116], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9224 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[ifu_mem_ctl.scala 696:33] + node _T_9225 = mux(_T_9224, ic_tag_valid_out[0][117], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9226 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[ifu_mem_ctl.scala 696:33] + node _T_9227 = mux(_T_9226, ic_tag_valid_out[0][118], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9228 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[ifu_mem_ctl.scala 696:33] + node _T_9229 = mux(_T_9228, ic_tag_valid_out[0][119], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9230 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[ifu_mem_ctl.scala 696:33] + node _T_9231 = mux(_T_9230, ic_tag_valid_out[0][120], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9232 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[ifu_mem_ctl.scala 696:33] + node _T_9233 = mux(_T_9232, ic_tag_valid_out[0][121], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9234 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[ifu_mem_ctl.scala 696:33] + node _T_9235 = mux(_T_9234, ic_tag_valid_out[0][122], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9236 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[ifu_mem_ctl.scala 696:33] + node _T_9237 = mux(_T_9236, ic_tag_valid_out[0][123], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9238 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[ifu_mem_ctl.scala 696:33] + node _T_9239 = mux(_T_9238, ic_tag_valid_out[0][124], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9240 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[ifu_mem_ctl.scala 696:33] + node _T_9241 = mux(_T_9240, ic_tag_valid_out[0][125], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9242 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[ifu_mem_ctl.scala 696:33] + node _T_9243 = mux(_T_9242, ic_tag_valid_out[0][126], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9244 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[ifu_mem_ctl.scala 696:33] + node _T_9245 = mux(_T_9244, ic_tag_valid_out[0][127], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9246 = or(_T_8991, _T_8993) @[ifu_mem_ctl.scala 696:91] + node _T_9247 = or(_T_9246, _T_8995) @[ifu_mem_ctl.scala 696:91] + node _T_9248 = or(_T_9247, _T_8997) @[ifu_mem_ctl.scala 696:91] + node _T_9249 = or(_T_9248, _T_8999) @[ifu_mem_ctl.scala 696:91] + node _T_9250 = or(_T_9249, _T_9001) @[ifu_mem_ctl.scala 696:91] + node _T_9251 = or(_T_9250, _T_9003) @[ifu_mem_ctl.scala 696:91] + node _T_9252 = or(_T_9251, _T_9005) @[ifu_mem_ctl.scala 696:91] + node _T_9253 = or(_T_9252, _T_9007) @[ifu_mem_ctl.scala 696:91] + node _T_9254 = or(_T_9253, _T_9009) @[ifu_mem_ctl.scala 696:91] + node _T_9255 = or(_T_9254, _T_9011) @[ifu_mem_ctl.scala 696:91] + node _T_9256 = or(_T_9255, _T_9013) @[ifu_mem_ctl.scala 696:91] + node _T_9257 = or(_T_9256, _T_9015) @[ifu_mem_ctl.scala 696:91] + node _T_9258 = or(_T_9257, _T_9017) @[ifu_mem_ctl.scala 696:91] + node _T_9259 = or(_T_9258, _T_9019) @[ifu_mem_ctl.scala 696:91] + node _T_9260 = or(_T_9259, _T_9021) @[ifu_mem_ctl.scala 696:91] + node _T_9261 = or(_T_9260, _T_9023) @[ifu_mem_ctl.scala 696:91] + node _T_9262 = or(_T_9261, _T_9025) @[ifu_mem_ctl.scala 696:91] + node _T_9263 = or(_T_9262, _T_9027) @[ifu_mem_ctl.scala 696:91] + node _T_9264 = or(_T_9263, _T_9029) @[ifu_mem_ctl.scala 696:91] + node _T_9265 = or(_T_9264, _T_9031) @[ifu_mem_ctl.scala 696:91] + node _T_9266 = or(_T_9265, _T_9033) @[ifu_mem_ctl.scala 696:91] + node _T_9267 = or(_T_9266, _T_9035) @[ifu_mem_ctl.scala 696:91] + node _T_9268 = or(_T_9267, _T_9037) @[ifu_mem_ctl.scala 696:91] + node _T_9269 = or(_T_9268, _T_9039) @[ifu_mem_ctl.scala 696:91] + node _T_9270 = or(_T_9269, _T_9041) @[ifu_mem_ctl.scala 696:91] + node _T_9271 = or(_T_9270, _T_9043) @[ifu_mem_ctl.scala 696:91] + node _T_9272 = or(_T_9271, _T_9045) @[ifu_mem_ctl.scala 696:91] + node _T_9273 = or(_T_9272, _T_9047) @[ifu_mem_ctl.scala 696:91] + node _T_9274 = or(_T_9273, _T_9049) @[ifu_mem_ctl.scala 696:91] + node _T_9275 = or(_T_9274, _T_9051) @[ifu_mem_ctl.scala 696:91] + node _T_9276 = or(_T_9275, _T_9053) @[ifu_mem_ctl.scala 696:91] + node _T_9277 = or(_T_9276, _T_9055) @[ifu_mem_ctl.scala 696:91] + node _T_9278 = or(_T_9277, _T_9057) @[ifu_mem_ctl.scala 696:91] + node _T_9279 = or(_T_9278, _T_9059) @[ifu_mem_ctl.scala 696:91] + node _T_9280 = or(_T_9279, _T_9061) @[ifu_mem_ctl.scala 696:91] + node _T_9281 = or(_T_9280, _T_9063) @[ifu_mem_ctl.scala 696:91] + node _T_9282 = or(_T_9281, _T_9065) @[ifu_mem_ctl.scala 696:91] + node _T_9283 = or(_T_9282, _T_9067) @[ifu_mem_ctl.scala 696:91] + node _T_9284 = or(_T_9283, _T_9069) @[ifu_mem_ctl.scala 696:91] + node _T_9285 = or(_T_9284, _T_9071) @[ifu_mem_ctl.scala 696:91] + node _T_9286 = or(_T_9285, _T_9073) @[ifu_mem_ctl.scala 696:91] + node _T_9287 = or(_T_9286, _T_9075) @[ifu_mem_ctl.scala 696:91] + node _T_9288 = or(_T_9287, _T_9077) @[ifu_mem_ctl.scala 696:91] + node _T_9289 = or(_T_9288, _T_9079) @[ifu_mem_ctl.scala 696:91] + node _T_9290 = or(_T_9289, _T_9081) @[ifu_mem_ctl.scala 696:91] + node _T_9291 = or(_T_9290, _T_9083) @[ifu_mem_ctl.scala 696:91] + node _T_9292 = or(_T_9291, _T_9085) @[ifu_mem_ctl.scala 696:91] + node _T_9293 = or(_T_9292, _T_9087) @[ifu_mem_ctl.scala 696:91] + node _T_9294 = or(_T_9293, _T_9089) @[ifu_mem_ctl.scala 696:91] + node _T_9295 = or(_T_9294, _T_9091) @[ifu_mem_ctl.scala 696:91] + node _T_9296 = or(_T_9295, _T_9093) @[ifu_mem_ctl.scala 696:91] + node _T_9297 = or(_T_9296, _T_9095) @[ifu_mem_ctl.scala 696:91] + node _T_9298 = or(_T_9297, _T_9097) @[ifu_mem_ctl.scala 696:91] + node _T_9299 = or(_T_9298, _T_9099) @[ifu_mem_ctl.scala 696:91] + node _T_9300 = or(_T_9299, _T_9101) @[ifu_mem_ctl.scala 696:91] + node _T_9301 = or(_T_9300, _T_9103) @[ifu_mem_ctl.scala 696:91] + node _T_9302 = or(_T_9301, _T_9105) @[ifu_mem_ctl.scala 696:91] + node _T_9303 = or(_T_9302, _T_9107) @[ifu_mem_ctl.scala 696:91] + node _T_9304 = or(_T_9303, _T_9109) @[ifu_mem_ctl.scala 696:91] + node _T_9305 = or(_T_9304, _T_9111) @[ifu_mem_ctl.scala 696:91] + node _T_9306 = or(_T_9305, _T_9113) @[ifu_mem_ctl.scala 696:91] + node _T_9307 = or(_T_9306, _T_9115) @[ifu_mem_ctl.scala 696:91] + node _T_9308 = or(_T_9307, _T_9117) @[ifu_mem_ctl.scala 696:91] + node _T_9309 = or(_T_9308, _T_9119) @[ifu_mem_ctl.scala 696:91] + node _T_9310 = or(_T_9309, _T_9121) @[ifu_mem_ctl.scala 696:91] + node _T_9311 = or(_T_9310, _T_9123) @[ifu_mem_ctl.scala 696:91] + node _T_9312 = or(_T_9311, _T_9125) @[ifu_mem_ctl.scala 696:91] + node _T_9313 = or(_T_9312, _T_9127) @[ifu_mem_ctl.scala 696:91] + node _T_9314 = or(_T_9313, _T_9129) @[ifu_mem_ctl.scala 696:91] + node _T_9315 = or(_T_9314, _T_9131) @[ifu_mem_ctl.scala 696:91] + node _T_9316 = or(_T_9315, _T_9133) @[ifu_mem_ctl.scala 696:91] + node _T_9317 = or(_T_9316, _T_9135) @[ifu_mem_ctl.scala 696:91] + node _T_9318 = or(_T_9317, _T_9137) @[ifu_mem_ctl.scala 696:91] + node _T_9319 = or(_T_9318, _T_9139) @[ifu_mem_ctl.scala 696:91] + node _T_9320 = or(_T_9319, _T_9141) @[ifu_mem_ctl.scala 696:91] + node _T_9321 = or(_T_9320, _T_9143) @[ifu_mem_ctl.scala 696:91] + node _T_9322 = or(_T_9321, _T_9145) @[ifu_mem_ctl.scala 696:91] + node _T_9323 = or(_T_9322, _T_9147) @[ifu_mem_ctl.scala 696:91] + node _T_9324 = or(_T_9323, _T_9149) @[ifu_mem_ctl.scala 696:91] + node _T_9325 = or(_T_9324, _T_9151) @[ifu_mem_ctl.scala 696:91] + node _T_9326 = or(_T_9325, _T_9153) @[ifu_mem_ctl.scala 696:91] + node _T_9327 = or(_T_9326, _T_9155) @[ifu_mem_ctl.scala 696:91] + node _T_9328 = or(_T_9327, _T_9157) @[ifu_mem_ctl.scala 696:91] + node _T_9329 = or(_T_9328, _T_9159) @[ifu_mem_ctl.scala 696:91] + node _T_9330 = or(_T_9329, _T_9161) @[ifu_mem_ctl.scala 696:91] + node _T_9331 = or(_T_9330, _T_9163) @[ifu_mem_ctl.scala 696:91] + node _T_9332 = or(_T_9331, _T_9165) @[ifu_mem_ctl.scala 696:91] + node _T_9333 = or(_T_9332, _T_9167) @[ifu_mem_ctl.scala 696:91] + node _T_9334 = or(_T_9333, _T_9169) @[ifu_mem_ctl.scala 696:91] + node _T_9335 = or(_T_9334, _T_9171) @[ifu_mem_ctl.scala 696:91] + node _T_9336 = or(_T_9335, _T_9173) @[ifu_mem_ctl.scala 696:91] + node _T_9337 = or(_T_9336, _T_9175) @[ifu_mem_ctl.scala 696:91] + node _T_9338 = or(_T_9337, _T_9177) @[ifu_mem_ctl.scala 696:91] + node _T_9339 = or(_T_9338, _T_9179) @[ifu_mem_ctl.scala 696:91] + node _T_9340 = or(_T_9339, _T_9181) @[ifu_mem_ctl.scala 696:91] + node _T_9341 = or(_T_9340, _T_9183) @[ifu_mem_ctl.scala 696:91] + node _T_9342 = or(_T_9341, _T_9185) @[ifu_mem_ctl.scala 696:91] + node _T_9343 = or(_T_9342, _T_9187) @[ifu_mem_ctl.scala 696:91] + node _T_9344 = or(_T_9343, _T_9189) @[ifu_mem_ctl.scala 696:91] + node _T_9345 = or(_T_9344, _T_9191) @[ifu_mem_ctl.scala 696:91] + node _T_9346 = or(_T_9345, _T_9193) @[ifu_mem_ctl.scala 696:91] + node _T_9347 = or(_T_9346, _T_9195) @[ifu_mem_ctl.scala 696:91] + node _T_9348 = or(_T_9347, _T_9197) @[ifu_mem_ctl.scala 696:91] + node _T_9349 = or(_T_9348, _T_9199) @[ifu_mem_ctl.scala 696:91] + node _T_9350 = or(_T_9349, _T_9201) @[ifu_mem_ctl.scala 696:91] + node _T_9351 = or(_T_9350, _T_9203) @[ifu_mem_ctl.scala 696:91] + node _T_9352 = or(_T_9351, _T_9205) @[ifu_mem_ctl.scala 696:91] + node _T_9353 = or(_T_9352, _T_9207) @[ifu_mem_ctl.scala 696:91] + node _T_9354 = or(_T_9353, _T_9209) @[ifu_mem_ctl.scala 696:91] + node _T_9355 = or(_T_9354, _T_9211) @[ifu_mem_ctl.scala 696:91] + node _T_9356 = or(_T_9355, _T_9213) @[ifu_mem_ctl.scala 696:91] + node _T_9357 = or(_T_9356, _T_9215) @[ifu_mem_ctl.scala 696:91] + node _T_9358 = or(_T_9357, _T_9217) @[ifu_mem_ctl.scala 696:91] + node _T_9359 = or(_T_9358, _T_9219) @[ifu_mem_ctl.scala 696:91] + node _T_9360 = or(_T_9359, _T_9221) @[ifu_mem_ctl.scala 696:91] + node _T_9361 = or(_T_9360, _T_9223) @[ifu_mem_ctl.scala 696:91] + node _T_9362 = or(_T_9361, _T_9225) @[ifu_mem_ctl.scala 696:91] + node _T_9363 = or(_T_9362, _T_9227) @[ifu_mem_ctl.scala 696:91] + node _T_9364 = or(_T_9363, _T_9229) @[ifu_mem_ctl.scala 696:91] + node _T_9365 = or(_T_9364, _T_9231) @[ifu_mem_ctl.scala 696:91] + node _T_9366 = or(_T_9365, _T_9233) @[ifu_mem_ctl.scala 696:91] + node _T_9367 = or(_T_9366, _T_9235) @[ifu_mem_ctl.scala 696:91] + node _T_9368 = or(_T_9367, _T_9237) @[ifu_mem_ctl.scala 696:91] + node _T_9369 = or(_T_9368, _T_9239) @[ifu_mem_ctl.scala 696:91] + node _T_9370 = or(_T_9369, _T_9241) @[ifu_mem_ctl.scala 696:91] + node _T_9371 = or(_T_9370, _T_9243) @[ifu_mem_ctl.scala 696:91] + node _T_9372 = or(_T_9371, _T_9245) @[ifu_mem_ctl.scala 696:91] + node _T_9373 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 696:33] + node _T_9374 = mux(_T_9373, ic_tag_valid_out[1][0], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9375 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[ifu_mem_ctl.scala 696:33] + node _T_9376 = mux(_T_9375, ic_tag_valid_out[1][1], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9377 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[ifu_mem_ctl.scala 696:33] + node _T_9378 = mux(_T_9377, ic_tag_valid_out[1][2], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9379 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[ifu_mem_ctl.scala 696:33] + node _T_9380 = mux(_T_9379, ic_tag_valid_out[1][3], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9381 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[ifu_mem_ctl.scala 696:33] + node _T_9382 = mux(_T_9381, ic_tag_valid_out[1][4], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9383 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[ifu_mem_ctl.scala 696:33] + node _T_9384 = mux(_T_9383, ic_tag_valid_out[1][5], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9385 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[ifu_mem_ctl.scala 696:33] + node _T_9386 = mux(_T_9385, ic_tag_valid_out[1][6], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9387 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[ifu_mem_ctl.scala 696:33] + node _T_9388 = mux(_T_9387, ic_tag_valid_out[1][7], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9389 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[ifu_mem_ctl.scala 696:33] + node _T_9390 = mux(_T_9389, ic_tag_valid_out[1][8], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9391 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[ifu_mem_ctl.scala 696:33] + node _T_9392 = mux(_T_9391, ic_tag_valid_out[1][9], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9393 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[ifu_mem_ctl.scala 696:33] + node _T_9394 = mux(_T_9393, ic_tag_valid_out[1][10], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9395 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[ifu_mem_ctl.scala 696:33] + node _T_9396 = mux(_T_9395, ic_tag_valid_out[1][11], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9397 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[ifu_mem_ctl.scala 696:33] + node _T_9398 = mux(_T_9397, ic_tag_valid_out[1][12], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9399 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[ifu_mem_ctl.scala 696:33] + node _T_9400 = mux(_T_9399, ic_tag_valid_out[1][13], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9401 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[ifu_mem_ctl.scala 696:33] + node _T_9402 = mux(_T_9401, ic_tag_valid_out[1][14], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9403 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[ifu_mem_ctl.scala 696:33] + node _T_9404 = mux(_T_9403, ic_tag_valid_out[1][15], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9405 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[ifu_mem_ctl.scala 696:33] + node _T_9406 = mux(_T_9405, ic_tag_valid_out[1][16], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9407 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[ifu_mem_ctl.scala 696:33] + node _T_9408 = mux(_T_9407, ic_tag_valid_out[1][17], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9409 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[ifu_mem_ctl.scala 696:33] + node _T_9410 = mux(_T_9409, ic_tag_valid_out[1][18], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9411 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[ifu_mem_ctl.scala 696:33] + node _T_9412 = mux(_T_9411, ic_tag_valid_out[1][19], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9413 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[ifu_mem_ctl.scala 696:33] + node _T_9414 = mux(_T_9413, ic_tag_valid_out[1][20], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9415 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[ifu_mem_ctl.scala 696:33] + node _T_9416 = mux(_T_9415, ic_tag_valid_out[1][21], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9417 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[ifu_mem_ctl.scala 696:33] + node _T_9418 = mux(_T_9417, ic_tag_valid_out[1][22], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9419 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[ifu_mem_ctl.scala 696:33] + node _T_9420 = mux(_T_9419, ic_tag_valid_out[1][23], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9421 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[ifu_mem_ctl.scala 696:33] + node _T_9422 = mux(_T_9421, ic_tag_valid_out[1][24], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9423 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[ifu_mem_ctl.scala 696:33] + node _T_9424 = mux(_T_9423, ic_tag_valid_out[1][25], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9425 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[ifu_mem_ctl.scala 696:33] + node _T_9426 = mux(_T_9425, ic_tag_valid_out[1][26], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9427 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[ifu_mem_ctl.scala 696:33] + node _T_9428 = mux(_T_9427, ic_tag_valid_out[1][27], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9429 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[ifu_mem_ctl.scala 696:33] + node _T_9430 = mux(_T_9429, ic_tag_valid_out[1][28], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9431 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[ifu_mem_ctl.scala 696:33] + node _T_9432 = mux(_T_9431, ic_tag_valid_out[1][29], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9433 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[ifu_mem_ctl.scala 696:33] + node _T_9434 = mux(_T_9433, ic_tag_valid_out[1][30], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9435 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[ifu_mem_ctl.scala 696:33] + node _T_9436 = mux(_T_9435, ic_tag_valid_out[1][31], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9437 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[ifu_mem_ctl.scala 696:33] + node _T_9438 = mux(_T_9437, ic_tag_valid_out[1][32], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9439 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[ifu_mem_ctl.scala 696:33] + node _T_9440 = mux(_T_9439, ic_tag_valid_out[1][33], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9441 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[ifu_mem_ctl.scala 696:33] + node _T_9442 = mux(_T_9441, ic_tag_valid_out[1][34], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9443 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[ifu_mem_ctl.scala 696:33] + node _T_9444 = mux(_T_9443, ic_tag_valid_out[1][35], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9445 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[ifu_mem_ctl.scala 696:33] + node _T_9446 = mux(_T_9445, ic_tag_valid_out[1][36], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9447 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[ifu_mem_ctl.scala 696:33] + node _T_9448 = mux(_T_9447, ic_tag_valid_out[1][37], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9449 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[ifu_mem_ctl.scala 696:33] + node _T_9450 = mux(_T_9449, ic_tag_valid_out[1][38], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9451 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[ifu_mem_ctl.scala 696:33] + node _T_9452 = mux(_T_9451, ic_tag_valid_out[1][39], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9453 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[ifu_mem_ctl.scala 696:33] + node _T_9454 = mux(_T_9453, ic_tag_valid_out[1][40], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9455 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[ifu_mem_ctl.scala 696:33] + node _T_9456 = mux(_T_9455, ic_tag_valid_out[1][41], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9457 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[ifu_mem_ctl.scala 696:33] + node _T_9458 = mux(_T_9457, ic_tag_valid_out[1][42], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9459 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[ifu_mem_ctl.scala 696:33] + node _T_9460 = mux(_T_9459, ic_tag_valid_out[1][43], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9461 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[ifu_mem_ctl.scala 696:33] + node _T_9462 = mux(_T_9461, ic_tag_valid_out[1][44], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9463 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[ifu_mem_ctl.scala 696:33] + node _T_9464 = mux(_T_9463, ic_tag_valid_out[1][45], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9465 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[ifu_mem_ctl.scala 696:33] + node _T_9466 = mux(_T_9465, ic_tag_valid_out[1][46], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9467 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[ifu_mem_ctl.scala 696:33] + node _T_9468 = mux(_T_9467, ic_tag_valid_out[1][47], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9469 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[ifu_mem_ctl.scala 696:33] + node _T_9470 = mux(_T_9469, ic_tag_valid_out[1][48], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9471 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[ifu_mem_ctl.scala 696:33] + node _T_9472 = mux(_T_9471, ic_tag_valid_out[1][49], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9473 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[ifu_mem_ctl.scala 696:33] + node _T_9474 = mux(_T_9473, ic_tag_valid_out[1][50], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9475 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[ifu_mem_ctl.scala 696:33] + node _T_9476 = mux(_T_9475, ic_tag_valid_out[1][51], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9477 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[ifu_mem_ctl.scala 696:33] + node _T_9478 = mux(_T_9477, ic_tag_valid_out[1][52], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9479 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[ifu_mem_ctl.scala 696:33] + node _T_9480 = mux(_T_9479, ic_tag_valid_out[1][53], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9481 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[ifu_mem_ctl.scala 696:33] + node _T_9482 = mux(_T_9481, ic_tag_valid_out[1][54], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9483 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[ifu_mem_ctl.scala 696:33] + node _T_9484 = mux(_T_9483, ic_tag_valid_out[1][55], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9485 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[ifu_mem_ctl.scala 696:33] + node _T_9486 = mux(_T_9485, ic_tag_valid_out[1][56], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9487 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[ifu_mem_ctl.scala 696:33] + node _T_9488 = mux(_T_9487, ic_tag_valid_out[1][57], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9489 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[ifu_mem_ctl.scala 696:33] + node _T_9490 = mux(_T_9489, ic_tag_valid_out[1][58], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9491 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[ifu_mem_ctl.scala 696:33] + node _T_9492 = mux(_T_9491, ic_tag_valid_out[1][59], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9493 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[ifu_mem_ctl.scala 696:33] + node _T_9494 = mux(_T_9493, ic_tag_valid_out[1][60], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9495 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[ifu_mem_ctl.scala 696:33] + node _T_9496 = mux(_T_9495, ic_tag_valid_out[1][61], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9497 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[ifu_mem_ctl.scala 696:33] + node _T_9498 = mux(_T_9497, ic_tag_valid_out[1][62], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9499 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[ifu_mem_ctl.scala 696:33] + node _T_9500 = mux(_T_9499, ic_tag_valid_out[1][63], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9501 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[ifu_mem_ctl.scala 696:33] + node _T_9502 = mux(_T_9501, ic_tag_valid_out[1][64], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9503 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[ifu_mem_ctl.scala 696:33] + node _T_9504 = mux(_T_9503, ic_tag_valid_out[1][65], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9505 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[ifu_mem_ctl.scala 696:33] + node _T_9506 = mux(_T_9505, ic_tag_valid_out[1][66], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9507 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[ifu_mem_ctl.scala 696:33] + node _T_9508 = mux(_T_9507, ic_tag_valid_out[1][67], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9509 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[ifu_mem_ctl.scala 696:33] + node _T_9510 = mux(_T_9509, ic_tag_valid_out[1][68], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9511 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[ifu_mem_ctl.scala 696:33] + node _T_9512 = mux(_T_9511, ic_tag_valid_out[1][69], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9513 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[ifu_mem_ctl.scala 696:33] + node _T_9514 = mux(_T_9513, ic_tag_valid_out[1][70], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9515 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[ifu_mem_ctl.scala 696:33] + node _T_9516 = mux(_T_9515, ic_tag_valid_out[1][71], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9517 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[ifu_mem_ctl.scala 696:33] + node _T_9518 = mux(_T_9517, ic_tag_valid_out[1][72], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9519 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[ifu_mem_ctl.scala 696:33] + node _T_9520 = mux(_T_9519, ic_tag_valid_out[1][73], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9521 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[ifu_mem_ctl.scala 696:33] + node _T_9522 = mux(_T_9521, ic_tag_valid_out[1][74], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9523 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[ifu_mem_ctl.scala 696:33] + node _T_9524 = mux(_T_9523, ic_tag_valid_out[1][75], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9525 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[ifu_mem_ctl.scala 696:33] + node _T_9526 = mux(_T_9525, ic_tag_valid_out[1][76], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9527 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[ifu_mem_ctl.scala 696:33] + node _T_9528 = mux(_T_9527, ic_tag_valid_out[1][77], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9529 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[ifu_mem_ctl.scala 696:33] + node _T_9530 = mux(_T_9529, ic_tag_valid_out[1][78], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9531 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[ifu_mem_ctl.scala 696:33] + node _T_9532 = mux(_T_9531, ic_tag_valid_out[1][79], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9533 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[ifu_mem_ctl.scala 696:33] + node _T_9534 = mux(_T_9533, ic_tag_valid_out[1][80], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9535 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[ifu_mem_ctl.scala 696:33] + node _T_9536 = mux(_T_9535, ic_tag_valid_out[1][81], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9537 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[ifu_mem_ctl.scala 696:33] + node _T_9538 = mux(_T_9537, ic_tag_valid_out[1][82], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9539 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[ifu_mem_ctl.scala 696:33] + node _T_9540 = mux(_T_9539, ic_tag_valid_out[1][83], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9541 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[ifu_mem_ctl.scala 696:33] + node _T_9542 = mux(_T_9541, ic_tag_valid_out[1][84], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9543 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[ifu_mem_ctl.scala 696:33] + node _T_9544 = mux(_T_9543, ic_tag_valid_out[1][85], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9545 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[ifu_mem_ctl.scala 696:33] + node _T_9546 = mux(_T_9545, ic_tag_valid_out[1][86], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9547 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[ifu_mem_ctl.scala 696:33] + node _T_9548 = mux(_T_9547, ic_tag_valid_out[1][87], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9549 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[ifu_mem_ctl.scala 696:33] + node _T_9550 = mux(_T_9549, ic_tag_valid_out[1][88], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9551 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[ifu_mem_ctl.scala 696:33] + node _T_9552 = mux(_T_9551, ic_tag_valid_out[1][89], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9553 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[ifu_mem_ctl.scala 696:33] + node _T_9554 = mux(_T_9553, ic_tag_valid_out[1][90], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9555 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[ifu_mem_ctl.scala 696:33] + node _T_9556 = mux(_T_9555, ic_tag_valid_out[1][91], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9557 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[ifu_mem_ctl.scala 696:33] + node _T_9558 = mux(_T_9557, ic_tag_valid_out[1][92], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9559 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[ifu_mem_ctl.scala 696:33] + node _T_9560 = mux(_T_9559, ic_tag_valid_out[1][93], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9561 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[ifu_mem_ctl.scala 696:33] + node _T_9562 = mux(_T_9561, ic_tag_valid_out[1][94], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9563 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[ifu_mem_ctl.scala 696:33] + node _T_9564 = mux(_T_9563, ic_tag_valid_out[1][95], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9565 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[ifu_mem_ctl.scala 696:33] + node _T_9566 = mux(_T_9565, ic_tag_valid_out[1][96], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9567 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[ifu_mem_ctl.scala 696:33] + node _T_9568 = mux(_T_9567, ic_tag_valid_out[1][97], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9569 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[ifu_mem_ctl.scala 696:33] + node _T_9570 = mux(_T_9569, ic_tag_valid_out[1][98], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9571 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[ifu_mem_ctl.scala 696:33] + node _T_9572 = mux(_T_9571, ic_tag_valid_out[1][99], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9573 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[ifu_mem_ctl.scala 696:33] + node _T_9574 = mux(_T_9573, ic_tag_valid_out[1][100], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9575 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[ifu_mem_ctl.scala 696:33] + node _T_9576 = mux(_T_9575, ic_tag_valid_out[1][101], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9577 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[ifu_mem_ctl.scala 696:33] + node _T_9578 = mux(_T_9577, ic_tag_valid_out[1][102], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9579 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[ifu_mem_ctl.scala 696:33] + node _T_9580 = mux(_T_9579, ic_tag_valid_out[1][103], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9581 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[ifu_mem_ctl.scala 696:33] + node _T_9582 = mux(_T_9581, ic_tag_valid_out[1][104], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9583 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[ifu_mem_ctl.scala 696:33] + node _T_9584 = mux(_T_9583, ic_tag_valid_out[1][105], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9585 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[ifu_mem_ctl.scala 696:33] + node _T_9586 = mux(_T_9585, ic_tag_valid_out[1][106], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9587 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[ifu_mem_ctl.scala 696:33] + node _T_9588 = mux(_T_9587, ic_tag_valid_out[1][107], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9589 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[ifu_mem_ctl.scala 696:33] + node _T_9590 = mux(_T_9589, ic_tag_valid_out[1][108], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9591 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[ifu_mem_ctl.scala 696:33] + node _T_9592 = mux(_T_9591, ic_tag_valid_out[1][109], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9593 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[ifu_mem_ctl.scala 696:33] + node _T_9594 = mux(_T_9593, ic_tag_valid_out[1][110], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9595 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[ifu_mem_ctl.scala 696:33] + node _T_9596 = mux(_T_9595, ic_tag_valid_out[1][111], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9597 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[ifu_mem_ctl.scala 696:33] + node _T_9598 = mux(_T_9597, ic_tag_valid_out[1][112], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9599 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[ifu_mem_ctl.scala 696:33] + node _T_9600 = mux(_T_9599, ic_tag_valid_out[1][113], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9601 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[ifu_mem_ctl.scala 696:33] + node _T_9602 = mux(_T_9601, ic_tag_valid_out[1][114], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9603 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[ifu_mem_ctl.scala 696:33] + node _T_9604 = mux(_T_9603, ic_tag_valid_out[1][115], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9605 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[ifu_mem_ctl.scala 696:33] + node _T_9606 = mux(_T_9605, ic_tag_valid_out[1][116], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9607 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[ifu_mem_ctl.scala 696:33] + node _T_9608 = mux(_T_9607, ic_tag_valid_out[1][117], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9609 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[ifu_mem_ctl.scala 696:33] + node _T_9610 = mux(_T_9609, ic_tag_valid_out[1][118], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9611 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[ifu_mem_ctl.scala 696:33] + node _T_9612 = mux(_T_9611, ic_tag_valid_out[1][119], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9613 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[ifu_mem_ctl.scala 696:33] + node _T_9614 = mux(_T_9613, ic_tag_valid_out[1][120], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9615 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[ifu_mem_ctl.scala 696:33] + node _T_9616 = mux(_T_9615, ic_tag_valid_out[1][121], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9617 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[ifu_mem_ctl.scala 696:33] + node _T_9618 = mux(_T_9617, ic_tag_valid_out[1][122], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9619 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[ifu_mem_ctl.scala 696:33] + node _T_9620 = mux(_T_9619, ic_tag_valid_out[1][123], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9621 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[ifu_mem_ctl.scala 696:33] + node _T_9622 = mux(_T_9621, ic_tag_valid_out[1][124], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9623 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[ifu_mem_ctl.scala 696:33] + node _T_9624 = mux(_T_9623, ic_tag_valid_out[1][125], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9625 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[ifu_mem_ctl.scala 696:33] + node _T_9626 = mux(_T_9625, ic_tag_valid_out[1][126], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9627 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[ifu_mem_ctl.scala 696:33] + node _T_9628 = mux(_T_9627, ic_tag_valid_out[1][127], UInt<1>("h00")) @[ifu_mem_ctl.scala 696:10] + node _T_9629 = or(_T_9374, _T_9376) @[ifu_mem_ctl.scala 696:91] + node _T_9630 = or(_T_9629, _T_9378) @[ifu_mem_ctl.scala 696:91] + node _T_9631 = or(_T_9630, _T_9380) @[ifu_mem_ctl.scala 696:91] + node _T_9632 = or(_T_9631, _T_9382) @[ifu_mem_ctl.scala 696:91] + node _T_9633 = or(_T_9632, _T_9384) @[ifu_mem_ctl.scala 696:91] + node _T_9634 = or(_T_9633, _T_9386) @[ifu_mem_ctl.scala 696:91] + node _T_9635 = or(_T_9634, _T_9388) @[ifu_mem_ctl.scala 696:91] + node _T_9636 = or(_T_9635, _T_9390) @[ifu_mem_ctl.scala 696:91] + node _T_9637 = or(_T_9636, _T_9392) @[ifu_mem_ctl.scala 696:91] + node _T_9638 = or(_T_9637, _T_9394) @[ifu_mem_ctl.scala 696:91] + node _T_9639 = or(_T_9638, _T_9396) @[ifu_mem_ctl.scala 696:91] + node _T_9640 = or(_T_9639, _T_9398) @[ifu_mem_ctl.scala 696:91] + node _T_9641 = or(_T_9640, _T_9400) @[ifu_mem_ctl.scala 696:91] + node _T_9642 = or(_T_9641, _T_9402) @[ifu_mem_ctl.scala 696:91] + node _T_9643 = or(_T_9642, _T_9404) @[ifu_mem_ctl.scala 696:91] + node _T_9644 = or(_T_9643, _T_9406) @[ifu_mem_ctl.scala 696:91] + node _T_9645 = or(_T_9644, _T_9408) @[ifu_mem_ctl.scala 696:91] + node _T_9646 = or(_T_9645, _T_9410) @[ifu_mem_ctl.scala 696:91] + node _T_9647 = or(_T_9646, _T_9412) @[ifu_mem_ctl.scala 696:91] + node _T_9648 = or(_T_9647, _T_9414) @[ifu_mem_ctl.scala 696:91] + node _T_9649 = or(_T_9648, _T_9416) @[ifu_mem_ctl.scala 696:91] + node _T_9650 = or(_T_9649, _T_9418) @[ifu_mem_ctl.scala 696:91] + node _T_9651 = or(_T_9650, _T_9420) @[ifu_mem_ctl.scala 696:91] + node _T_9652 = or(_T_9651, _T_9422) @[ifu_mem_ctl.scala 696:91] + node _T_9653 = or(_T_9652, _T_9424) @[ifu_mem_ctl.scala 696:91] + node _T_9654 = or(_T_9653, _T_9426) @[ifu_mem_ctl.scala 696:91] + node _T_9655 = or(_T_9654, _T_9428) @[ifu_mem_ctl.scala 696:91] + node _T_9656 = or(_T_9655, _T_9430) @[ifu_mem_ctl.scala 696:91] + node _T_9657 = or(_T_9656, _T_9432) @[ifu_mem_ctl.scala 696:91] + node _T_9658 = or(_T_9657, _T_9434) @[ifu_mem_ctl.scala 696:91] + node _T_9659 = or(_T_9658, _T_9436) @[ifu_mem_ctl.scala 696:91] + node _T_9660 = or(_T_9659, _T_9438) @[ifu_mem_ctl.scala 696:91] + node _T_9661 = or(_T_9660, _T_9440) @[ifu_mem_ctl.scala 696:91] + node _T_9662 = or(_T_9661, _T_9442) @[ifu_mem_ctl.scala 696:91] + node _T_9663 = or(_T_9662, _T_9444) @[ifu_mem_ctl.scala 696:91] + node _T_9664 = or(_T_9663, _T_9446) @[ifu_mem_ctl.scala 696:91] + node _T_9665 = or(_T_9664, _T_9448) @[ifu_mem_ctl.scala 696:91] + node _T_9666 = or(_T_9665, _T_9450) @[ifu_mem_ctl.scala 696:91] + node _T_9667 = or(_T_9666, _T_9452) @[ifu_mem_ctl.scala 696:91] + node _T_9668 = or(_T_9667, _T_9454) @[ifu_mem_ctl.scala 696:91] + node _T_9669 = or(_T_9668, _T_9456) @[ifu_mem_ctl.scala 696:91] + node _T_9670 = or(_T_9669, _T_9458) @[ifu_mem_ctl.scala 696:91] + node _T_9671 = or(_T_9670, _T_9460) @[ifu_mem_ctl.scala 696:91] + node _T_9672 = or(_T_9671, _T_9462) @[ifu_mem_ctl.scala 696:91] + node _T_9673 = or(_T_9672, _T_9464) @[ifu_mem_ctl.scala 696:91] + node _T_9674 = or(_T_9673, _T_9466) @[ifu_mem_ctl.scala 696:91] + node _T_9675 = or(_T_9674, _T_9468) @[ifu_mem_ctl.scala 696:91] + node _T_9676 = or(_T_9675, _T_9470) @[ifu_mem_ctl.scala 696:91] + node _T_9677 = or(_T_9676, _T_9472) @[ifu_mem_ctl.scala 696:91] + node _T_9678 = or(_T_9677, _T_9474) @[ifu_mem_ctl.scala 696:91] + node _T_9679 = or(_T_9678, _T_9476) @[ifu_mem_ctl.scala 696:91] + node _T_9680 = or(_T_9679, _T_9478) @[ifu_mem_ctl.scala 696:91] + node _T_9681 = or(_T_9680, _T_9480) @[ifu_mem_ctl.scala 696:91] + node _T_9682 = or(_T_9681, _T_9482) @[ifu_mem_ctl.scala 696:91] + node _T_9683 = or(_T_9682, _T_9484) @[ifu_mem_ctl.scala 696:91] + node _T_9684 = or(_T_9683, _T_9486) @[ifu_mem_ctl.scala 696:91] + node _T_9685 = or(_T_9684, _T_9488) @[ifu_mem_ctl.scala 696:91] + node _T_9686 = or(_T_9685, _T_9490) @[ifu_mem_ctl.scala 696:91] + node _T_9687 = or(_T_9686, _T_9492) @[ifu_mem_ctl.scala 696:91] + node _T_9688 = or(_T_9687, _T_9494) @[ifu_mem_ctl.scala 696:91] + node _T_9689 = or(_T_9688, _T_9496) @[ifu_mem_ctl.scala 696:91] + node _T_9690 = or(_T_9689, _T_9498) @[ifu_mem_ctl.scala 696:91] + node _T_9691 = or(_T_9690, _T_9500) @[ifu_mem_ctl.scala 696:91] + node _T_9692 = or(_T_9691, _T_9502) @[ifu_mem_ctl.scala 696:91] + node _T_9693 = or(_T_9692, _T_9504) @[ifu_mem_ctl.scala 696:91] + node _T_9694 = or(_T_9693, _T_9506) @[ifu_mem_ctl.scala 696:91] + node _T_9695 = or(_T_9694, _T_9508) @[ifu_mem_ctl.scala 696:91] + node _T_9696 = or(_T_9695, _T_9510) @[ifu_mem_ctl.scala 696:91] + node _T_9697 = or(_T_9696, _T_9512) @[ifu_mem_ctl.scala 696:91] + node _T_9698 = or(_T_9697, _T_9514) @[ifu_mem_ctl.scala 696:91] + node _T_9699 = or(_T_9698, _T_9516) @[ifu_mem_ctl.scala 696:91] + node _T_9700 = or(_T_9699, _T_9518) @[ifu_mem_ctl.scala 696:91] + node _T_9701 = or(_T_9700, _T_9520) @[ifu_mem_ctl.scala 696:91] + node _T_9702 = or(_T_9701, _T_9522) @[ifu_mem_ctl.scala 696:91] + node _T_9703 = or(_T_9702, _T_9524) @[ifu_mem_ctl.scala 696:91] + node _T_9704 = or(_T_9703, _T_9526) @[ifu_mem_ctl.scala 696:91] + node _T_9705 = or(_T_9704, _T_9528) @[ifu_mem_ctl.scala 696:91] + node _T_9706 = or(_T_9705, _T_9530) @[ifu_mem_ctl.scala 696:91] + node _T_9707 = or(_T_9706, _T_9532) @[ifu_mem_ctl.scala 696:91] + node _T_9708 = or(_T_9707, _T_9534) @[ifu_mem_ctl.scala 696:91] + node _T_9709 = or(_T_9708, _T_9536) @[ifu_mem_ctl.scala 696:91] + node _T_9710 = or(_T_9709, _T_9538) @[ifu_mem_ctl.scala 696:91] + node _T_9711 = or(_T_9710, _T_9540) @[ifu_mem_ctl.scala 696:91] + node _T_9712 = or(_T_9711, _T_9542) @[ifu_mem_ctl.scala 696:91] + node _T_9713 = or(_T_9712, _T_9544) @[ifu_mem_ctl.scala 696:91] + node _T_9714 = or(_T_9713, _T_9546) @[ifu_mem_ctl.scala 696:91] + node _T_9715 = or(_T_9714, _T_9548) @[ifu_mem_ctl.scala 696:91] + node _T_9716 = or(_T_9715, _T_9550) @[ifu_mem_ctl.scala 696:91] + node _T_9717 = or(_T_9716, _T_9552) @[ifu_mem_ctl.scala 696:91] + node _T_9718 = or(_T_9717, _T_9554) @[ifu_mem_ctl.scala 696:91] + node _T_9719 = or(_T_9718, _T_9556) @[ifu_mem_ctl.scala 696:91] + node _T_9720 = or(_T_9719, _T_9558) @[ifu_mem_ctl.scala 696:91] + node _T_9721 = or(_T_9720, _T_9560) @[ifu_mem_ctl.scala 696:91] + node _T_9722 = or(_T_9721, _T_9562) @[ifu_mem_ctl.scala 696:91] + node _T_9723 = or(_T_9722, _T_9564) @[ifu_mem_ctl.scala 696:91] + node _T_9724 = or(_T_9723, _T_9566) @[ifu_mem_ctl.scala 696:91] + node _T_9725 = or(_T_9724, _T_9568) @[ifu_mem_ctl.scala 696:91] + node _T_9726 = or(_T_9725, _T_9570) @[ifu_mem_ctl.scala 696:91] + node _T_9727 = or(_T_9726, _T_9572) @[ifu_mem_ctl.scala 696:91] + node _T_9728 = or(_T_9727, _T_9574) @[ifu_mem_ctl.scala 696:91] + node _T_9729 = or(_T_9728, _T_9576) @[ifu_mem_ctl.scala 696:91] + node _T_9730 = or(_T_9729, _T_9578) @[ifu_mem_ctl.scala 696:91] + node _T_9731 = or(_T_9730, _T_9580) @[ifu_mem_ctl.scala 696:91] + node _T_9732 = or(_T_9731, _T_9582) @[ifu_mem_ctl.scala 696:91] + node _T_9733 = or(_T_9732, _T_9584) @[ifu_mem_ctl.scala 696:91] + node _T_9734 = or(_T_9733, _T_9586) @[ifu_mem_ctl.scala 696:91] + node _T_9735 = or(_T_9734, _T_9588) @[ifu_mem_ctl.scala 696:91] + node _T_9736 = or(_T_9735, _T_9590) @[ifu_mem_ctl.scala 696:91] + node _T_9737 = or(_T_9736, _T_9592) @[ifu_mem_ctl.scala 696:91] + node _T_9738 = or(_T_9737, _T_9594) @[ifu_mem_ctl.scala 696:91] + node _T_9739 = or(_T_9738, _T_9596) @[ifu_mem_ctl.scala 696:91] + node _T_9740 = or(_T_9739, _T_9598) @[ifu_mem_ctl.scala 696:91] + node _T_9741 = or(_T_9740, _T_9600) @[ifu_mem_ctl.scala 696:91] + node _T_9742 = or(_T_9741, _T_9602) @[ifu_mem_ctl.scala 696:91] + node _T_9743 = or(_T_9742, _T_9604) @[ifu_mem_ctl.scala 696:91] + node _T_9744 = or(_T_9743, _T_9606) @[ifu_mem_ctl.scala 696:91] + node _T_9745 = or(_T_9744, _T_9608) @[ifu_mem_ctl.scala 696:91] + node _T_9746 = or(_T_9745, _T_9610) @[ifu_mem_ctl.scala 696:91] + node _T_9747 = or(_T_9746, _T_9612) @[ifu_mem_ctl.scala 696:91] + node _T_9748 = or(_T_9747, _T_9614) @[ifu_mem_ctl.scala 696:91] + node _T_9749 = or(_T_9748, _T_9616) @[ifu_mem_ctl.scala 696:91] + node _T_9750 = or(_T_9749, _T_9618) @[ifu_mem_ctl.scala 696:91] + node _T_9751 = or(_T_9750, _T_9620) @[ifu_mem_ctl.scala 696:91] + node _T_9752 = or(_T_9751, _T_9622) @[ifu_mem_ctl.scala 696:91] + node _T_9753 = or(_T_9752, _T_9624) @[ifu_mem_ctl.scala 696:91] + node _T_9754 = or(_T_9753, _T_9626) @[ifu_mem_ctl.scala 696:91] + node _T_9755 = or(_T_9754, _T_9628) @[ifu_mem_ctl.scala 696:91] node ic_tag_valid_unq = cat(_T_9755, _T_9372) @[Cat.scala 29:58] wire way_status_hit_new : UInt<1> way_status_hit_new <= UInt<1>("h00") - node _T_9756 = eq(way_status_mb_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 721:33] - node _T_9757 = bits(tagv_mb_ff, 0, 0) @[ifu_mem_ctl.scala 721:63] - node _T_9758 = and(_T_9756, _T_9757) @[ifu_mem_ctl.scala 721:51] - node _T_9759 = bits(tagv_mb_ff, 1, 1) @[ifu_mem_ctl.scala 721:79] - node _T_9760 = and(_T_9758, _T_9759) @[ifu_mem_ctl.scala 721:67] - node _T_9761 = bits(tagv_mb_ff, 0, 0) @[ifu_mem_ctl.scala 721:97] - node _T_9762 = eq(_T_9761, UInt<1>("h00")) @[ifu_mem_ctl.scala 721:86] - node _T_9763 = or(_T_9760, _T_9762) @[ifu_mem_ctl.scala 721:84] - replace_way_mb_any[0] <= _T_9763 @[ifu_mem_ctl.scala 721:29] - node _T_9764 = bits(tagv_mb_ff, 0, 0) @[ifu_mem_ctl.scala 722:62] - node _T_9765 = and(way_status_mb_ff, _T_9764) @[ifu_mem_ctl.scala 722:50] - node _T_9766 = bits(tagv_mb_ff, 1, 1) @[ifu_mem_ctl.scala 722:78] - node _T_9767 = and(_T_9765, _T_9766) @[ifu_mem_ctl.scala 722:66] - node _T_9768 = bits(tagv_mb_ff, 1, 1) @[ifu_mem_ctl.scala 722:96] - node _T_9769 = eq(_T_9768, UInt<1>("h00")) @[ifu_mem_ctl.scala 722:85] - node _T_9770 = bits(tagv_mb_ff, 0, 0) @[ifu_mem_ctl.scala 722:112] - node _T_9771 = and(_T_9769, _T_9770) @[ifu_mem_ctl.scala 722:100] - node _T_9772 = or(_T_9767, _T_9771) @[ifu_mem_ctl.scala 722:83] - replace_way_mb_any[1] <= _T_9772 @[ifu_mem_ctl.scala 722:29] - node _T_9773 = bits(io.ic.rd_hit, 0, 0) @[ifu_mem_ctl.scala 723:41] - way_status_hit_new <= _T_9773 @[ifu_mem_ctl.scala 723:26] - way_status_rep_new <= replace_way_mb_any[0] @[ifu_mem_ctl.scala 724:26] - node _T_9774 = and(bus_ifu_wr_en_ff_q, last_beat) @[ifu_mem_ctl.scala 726:47] - node _T_9775 = bits(_T_9774, 0, 0) @[ifu_mem_ctl.scala 726:60] - node _T_9776 = mux(_T_9775, way_status_rep_new, way_status_hit_new) @[ifu_mem_ctl.scala 726:26] - way_status_new <= _T_9776 @[ifu_mem_ctl.scala 726:20] - node _T_9777 = and(bus_ifu_wr_en_ff_q, last_beat) @[ifu_mem_ctl.scala 727:45] - node _T_9778 = or(_T_9777, ic_act_hit_f) @[ifu_mem_ctl.scala 727:58] - way_status_wr_en <= _T_9778 @[ifu_mem_ctl.scala 727:22] - node _T_9779 = and(bus_ifu_wr_en_ff_q, replace_way_mb_any[0]) @[ifu_mem_ctl.scala 728:74] - node bus_wren_0 = and(_T_9779, miss_pending) @[ifu_mem_ctl.scala 728:98] - node _T_9780 = and(bus_ifu_wr_en_ff_q, replace_way_mb_any[1]) @[ifu_mem_ctl.scala 728:74] - node bus_wren_1 = and(_T_9780, miss_pending) @[ifu_mem_ctl.scala 728:98] - node _T_9781 = and(bus_ifu_wr_en_ff_wo_err, replace_way_mb_any[0]) @[ifu_mem_ctl.scala 730:84] - node _T_9782 = and(_T_9781, miss_pending) @[ifu_mem_ctl.scala 730:108] - node bus_wren_last_0 = and(_T_9782, bus_last_data_beat) @[ifu_mem_ctl.scala 730:123] - node _T_9783 = and(bus_ifu_wr_en_ff_wo_err, replace_way_mb_any[1]) @[ifu_mem_ctl.scala 730:84] - node _T_9784 = and(_T_9783, miss_pending) @[ifu_mem_ctl.scala 730:108] - node bus_wren_last_1 = and(_T_9784, bus_last_data_beat) @[ifu_mem_ctl.scala 730:123] - node wren_reset_miss_0 = and(replace_way_mb_any[0], reset_tag_valid_for_miss) @[ifu_mem_ctl.scala 731:84] - node wren_reset_miss_1 = and(replace_way_mb_any[1], reset_tag_valid_for_miss) @[ifu_mem_ctl.scala 731:84] - node _T_9785 = or(bus_wren_last_0, wren_reset_miss_0) @[ifu_mem_ctl.scala 732:73] - node _T_9786 = or(bus_wren_last_1, wren_reset_miss_1) @[ifu_mem_ctl.scala 732:73] + node _T_9756 = eq(way_status_mb_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 720:33] + node _T_9757 = bits(tagv_mb_ff, 0, 0) @[ifu_mem_ctl.scala 720:63] + node _T_9758 = and(_T_9756, _T_9757) @[ifu_mem_ctl.scala 720:51] + node _T_9759 = bits(tagv_mb_ff, 1, 1) @[ifu_mem_ctl.scala 720:79] + node _T_9760 = and(_T_9758, _T_9759) @[ifu_mem_ctl.scala 720:67] + node _T_9761 = bits(tagv_mb_ff, 0, 0) @[ifu_mem_ctl.scala 720:97] + node _T_9762 = eq(_T_9761, UInt<1>("h00")) @[ifu_mem_ctl.scala 720:86] + node _T_9763 = or(_T_9760, _T_9762) @[ifu_mem_ctl.scala 720:84] + replace_way_mb_any[0] <= _T_9763 @[ifu_mem_ctl.scala 720:29] + node _T_9764 = bits(tagv_mb_ff, 0, 0) @[ifu_mem_ctl.scala 721:62] + node _T_9765 = and(way_status_mb_ff, _T_9764) @[ifu_mem_ctl.scala 721:50] + node _T_9766 = bits(tagv_mb_ff, 1, 1) @[ifu_mem_ctl.scala 721:78] + node _T_9767 = and(_T_9765, _T_9766) @[ifu_mem_ctl.scala 721:66] + node _T_9768 = bits(tagv_mb_ff, 1, 1) @[ifu_mem_ctl.scala 721:96] + node _T_9769 = eq(_T_9768, UInt<1>("h00")) @[ifu_mem_ctl.scala 721:85] + node _T_9770 = bits(tagv_mb_ff, 0, 0) @[ifu_mem_ctl.scala 721:112] + node _T_9771 = and(_T_9769, _T_9770) @[ifu_mem_ctl.scala 721:100] + node _T_9772 = or(_T_9767, _T_9771) @[ifu_mem_ctl.scala 721:83] + replace_way_mb_any[1] <= _T_9772 @[ifu_mem_ctl.scala 721:29] + node _T_9773 = bits(io.ic.rd_hit, 0, 0) @[ifu_mem_ctl.scala 722:41] + way_status_hit_new <= _T_9773 @[ifu_mem_ctl.scala 722:26] + way_status_rep_new <= replace_way_mb_any[0] @[ifu_mem_ctl.scala 723:26] + node _T_9774 = and(bus_ifu_wr_en_ff_q, last_beat) @[ifu_mem_ctl.scala 725:47] + node _T_9775 = bits(_T_9774, 0, 0) @[ifu_mem_ctl.scala 725:60] + node _T_9776 = mux(_T_9775, way_status_rep_new, way_status_hit_new) @[ifu_mem_ctl.scala 725:26] + way_status_new <= _T_9776 @[ifu_mem_ctl.scala 725:20] + node _T_9777 = and(bus_ifu_wr_en_ff_q, last_beat) @[ifu_mem_ctl.scala 726:45] + node _T_9778 = or(_T_9777, ic_act_hit_f) @[ifu_mem_ctl.scala 726:58] + way_status_wr_en <= _T_9778 @[ifu_mem_ctl.scala 726:22] + node _T_9779 = and(bus_ifu_wr_en_ff_q, replace_way_mb_any[0]) @[ifu_mem_ctl.scala 727:74] + node bus_wren_0 = and(_T_9779, miss_pending) @[ifu_mem_ctl.scala 727:98] + node _T_9780 = and(bus_ifu_wr_en_ff_q, replace_way_mb_any[1]) @[ifu_mem_ctl.scala 727:74] + node bus_wren_1 = and(_T_9780, miss_pending) @[ifu_mem_ctl.scala 727:98] + node _T_9781 = and(bus_ifu_wr_en_ff_wo_err, replace_way_mb_any[0]) @[ifu_mem_ctl.scala 729:84] + node _T_9782 = and(_T_9781, miss_pending) @[ifu_mem_ctl.scala 729:108] + node bus_wren_last_0 = and(_T_9782, bus_last_data_beat) @[ifu_mem_ctl.scala 729:123] + node _T_9783 = and(bus_ifu_wr_en_ff_wo_err, replace_way_mb_any[1]) @[ifu_mem_ctl.scala 729:84] + node _T_9784 = and(_T_9783, miss_pending) @[ifu_mem_ctl.scala 729:108] + node bus_wren_last_1 = and(_T_9784, bus_last_data_beat) @[ifu_mem_ctl.scala 729:123] + node wren_reset_miss_0 = and(replace_way_mb_any[0], reset_tag_valid_for_miss) @[ifu_mem_ctl.scala 730:84] + node wren_reset_miss_1 = and(replace_way_mb_any[1], reset_tag_valid_for_miss) @[ifu_mem_ctl.scala 730:84] + node _T_9785 = or(bus_wren_last_0, wren_reset_miss_0) @[ifu_mem_ctl.scala 731:73] + node _T_9786 = or(bus_wren_last_1, wren_reset_miss_1) @[ifu_mem_ctl.scala 731:73] node _T_9787 = cat(_T_9786, _T_9785) @[Cat.scala 29:58] - ifu_tag_wren <= _T_9787 @[ifu_mem_ctl.scala 732:18] + ifu_tag_wren <= _T_9787 @[ifu_mem_ctl.scala 731:18] node _T_9788 = cat(bus_wren_1, bus_wren_0) @[Cat.scala 29:58] - bus_ic_wr_en <= _T_9788 @[ifu_mem_ctl.scala 734:16] - node _T_9789 = eq(fetch_uncacheable_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 748:63] - node _T_9790 = and(_T_9789, ifc_fetch_req_f) @[ifu_mem_ctl.scala 748:85] + bus_ic_wr_en <= _T_9788 @[ifu_mem_ctl.scala 733:16] + node _T_9789 = eq(fetch_uncacheable_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 747:63] + node _T_9790 = and(_T_9789, ifc_fetch_req_f) @[ifu_mem_ctl.scala 747:85] node _T_9791 = bits(_T_9790, 0, 0) @[Bitwise.scala 72:15] node _T_9792 = mux(_T_9791, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_9793 = and(ic_tag_valid_unq, _T_9792) @[ifu_mem_ctl.scala 748:39] - io.ic.tag_valid <= _T_9793 @[ifu_mem_ctl.scala 748:19] + node _T_9793 = and(ic_tag_valid_unq, _T_9792) @[ifu_mem_ctl.scala 747:39] + io.ic.tag_valid <= _T_9793 @[ifu_mem_ctl.scala 747:19] wire ic_debug_way_ff : UInt<2> ic_debug_way_ff <= UInt<1>("h00") node _T_9794 = bits(ic_debug_rd_en_ff, 0, 0) @[Bitwise.scala 72:15] node _T_9795 = mux(_T_9794, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_9796 = and(ic_debug_way_ff, _T_9795) @[ifu_mem_ctl.scala 751:67] - node _T_9797 = and(ic_tag_valid_unq, _T_9796) @[ifu_mem_ctl.scala 751:48] - node _T_9798 = orr(_T_9797) @[ifu_mem_ctl.scala 751:115] - ic_debug_tag_val_rd_out <= _T_9798 @[ifu_mem_ctl.scala 751:27] - reg _T_9799 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 753:70] - _T_9799 <= ic_act_miss_f @[ifu_mem_ctl.scala 753:70] - io.dec_mem_ctrl.ifu_pmu_ic_miss <= _T_9799 @[ifu_mem_ctl.scala 753:35] - reg _T_9800 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 754:69] - _T_9800 <= ic_act_hit_f @[ifu_mem_ctl.scala 754:69] - io.dec_mem_ctrl.ifu_pmu_ic_hit <= _T_9800 @[ifu_mem_ctl.scala 754:34] - reg _T_9801 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 755:72] - _T_9801 <= ifc_bus_acc_fault_f @[ifu_mem_ctl.scala 755:72] - io.dec_mem_ctrl.ifu_pmu_bus_error <= _T_9801 @[ifu_mem_ctl.scala 755:37] - node _T_9802 = eq(ifu_bus_arready_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 756:93] - node _T_9803 = and(ifu_bus_arvalid_ff, _T_9802) @[ifu_mem_ctl.scala 756:91] - node _T_9804 = and(_T_9803, miss_pending) @[ifu_mem_ctl.scala 756:113] - reg _T_9805 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 756:71] - _T_9805 <= _T_9804 @[ifu_mem_ctl.scala 756:71] - io.dec_mem_ctrl.ifu_pmu_bus_busy <= _T_9805 @[ifu_mem_ctl.scala 756:36] - reg _T_9806 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 757:71] - _T_9806 <= bus_cmd_sent @[ifu_mem_ctl.scala 757:71] - io.dec_mem_ctrl.ifu_pmu_bus_trxn <= _T_9806 @[ifu_mem_ctl.scala 757:36] - io.ic.debug_addr <= io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[ifu_mem_ctl.scala 760:20] - node _T_9807 = bits(io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics, 16, 16) @[ifu_mem_ctl.scala 761:79] - io.ic.debug_tag_array <= _T_9807 @[ifu_mem_ctl.scala 761:25] - io.ic.debug_rd_en <= io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[ifu_mem_ctl.scala 762:21] - io.ic.debug_wr_en <= io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[ifu_mem_ctl.scala 763:21] - node _T_9808 = bits(io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[ifu_mem_ctl.scala 764:77] - node _T_9809 = eq(_T_9808, UInt<2>("h03")) @[ifu_mem_ctl.scala 764:84] - node _T_9810 = bits(io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[ifu_mem_ctl.scala 764:143] - node _T_9811 = eq(_T_9810, UInt<2>("h02")) @[ifu_mem_ctl.scala 764:150] - node _T_9812 = bits(io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[ifu_mem_ctl.scala 765:56] - node _T_9813 = eq(_T_9812, UInt<1>("h01")) @[ifu_mem_ctl.scala 765:63] - node _T_9814 = bits(io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[ifu_mem_ctl.scala 765:122] - node _T_9815 = eq(_T_9814, UInt<1>("h00")) @[ifu_mem_ctl.scala 765:129] + node _T_9796 = and(ic_debug_way_ff, _T_9795) @[ifu_mem_ctl.scala 750:67] + node _T_9797 = and(ic_tag_valid_unq, _T_9796) @[ifu_mem_ctl.scala 750:48] + node _T_9798 = orr(_T_9797) @[ifu_mem_ctl.scala 750:115] + ic_debug_tag_val_rd_out <= _T_9798 @[ifu_mem_ctl.scala 750:27] + reg _T_9799 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 752:70] + _T_9799 <= ic_act_miss_f @[ifu_mem_ctl.scala 752:70] + io.dec_mem_ctrl.ifu_pmu_ic_miss <= _T_9799 @[ifu_mem_ctl.scala 752:35] + reg _T_9800 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 753:69] + _T_9800 <= ic_act_hit_f @[ifu_mem_ctl.scala 753:69] + io.dec_mem_ctrl.ifu_pmu_ic_hit <= _T_9800 @[ifu_mem_ctl.scala 753:34] + reg _T_9801 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 754:72] + _T_9801 <= ifc_bus_acc_fault_f @[ifu_mem_ctl.scala 754:72] + io.dec_mem_ctrl.ifu_pmu_bus_error <= _T_9801 @[ifu_mem_ctl.scala 754:37] + node _T_9802 = eq(ifu_bus_arready_ff, UInt<1>("h00")) @[ifu_mem_ctl.scala 755:93] + node _T_9803 = and(ifu_bus_arvalid_ff, _T_9802) @[ifu_mem_ctl.scala 755:91] + node _T_9804 = and(_T_9803, miss_pending) @[ifu_mem_ctl.scala 755:113] + reg _T_9805 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 755:71] + _T_9805 <= _T_9804 @[ifu_mem_ctl.scala 755:71] + io.dec_mem_ctrl.ifu_pmu_bus_busy <= _T_9805 @[ifu_mem_ctl.scala 755:36] + reg _T_9806 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 756:71] + _T_9806 <= bus_cmd_sent @[ifu_mem_ctl.scala 756:71] + io.dec_mem_ctrl.ifu_pmu_bus_trxn <= _T_9806 @[ifu_mem_ctl.scala 756:36] + io.ic.debug_addr <= io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[ifu_mem_ctl.scala 759:20] + node _T_9807 = bits(io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics, 16, 16) @[ifu_mem_ctl.scala 760:79] + io.ic.debug_tag_array <= _T_9807 @[ifu_mem_ctl.scala 760:25] + io.ic.debug_rd_en <= io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[ifu_mem_ctl.scala 761:21] + io.ic.debug_wr_en <= io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[ifu_mem_ctl.scala 762:21] + node _T_9808 = bits(io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[ifu_mem_ctl.scala 763:77] + node _T_9809 = eq(_T_9808, UInt<2>("h03")) @[ifu_mem_ctl.scala 763:84] + node _T_9810 = bits(io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[ifu_mem_ctl.scala 763:143] + node _T_9811 = eq(_T_9810, UInt<2>("h02")) @[ifu_mem_ctl.scala 763:150] + node _T_9812 = bits(io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[ifu_mem_ctl.scala 764:56] + node _T_9813 = eq(_T_9812, UInt<1>("h01")) @[ifu_mem_ctl.scala 764:63] + node _T_9814 = bits(io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[ifu_mem_ctl.scala 764:122] + node _T_9815 = eq(_T_9814, UInt<1>("h00")) @[ifu_mem_ctl.scala 764:129] node _T_9816 = cat(_T_9813, _T_9815) @[Cat.scala 29:58] node _T_9817 = cat(_T_9809, _T_9811) @[Cat.scala 29:58] node _T_9818 = cat(_T_9817, _T_9816) @[Cat.scala 29:58] - io.ic.debug_way <= _T_9818 @[ifu_mem_ctl.scala 764:19] - node _T_9819 = and(io.ic.debug_wr_en, io.ic.debug_tag_array) @[ifu_mem_ctl.scala 766:65] + io.ic.debug_way <= _T_9818 @[ifu_mem_ctl.scala 763:19] + node _T_9819 = and(io.ic.debug_wr_en, io.ic.debug_tag_array) @[ifu_mem_ctl.scala 765:65] node _T_9820 = bits(_T_9819, 0, 0) @[Bitwise.scala 72:15] node _T_9821 = mux(_T_9820, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_9822 = and(_T_9821, io.ic.debug_way) @[ifu_mem_ctl.scala 766:90] - ic_debug_tag_wr_en <= _T_9822 @[ifu_mem_ctl.scala 766:22] - node ic_debug_ict_array_sel_in = and(io.ic.debug_rd_en, io.ic.debug_tag_array) @[ifu_mem_ctl.scala 767:53] - reg _T_9823 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 768:53] - _T_9823 <= io.ic.debug_way @[ifu_mem_ctl.scala 768:53] - ic_debug_way_ff <= _T_9823 @[ifu_mem_ctl.scala 768:19] - reg _T_9824 : UInt<1>, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 769:63] - _T_9824 <= ic_debug_ict_array_sel_in @[ifu_mem_ctl.scala 769:63] - ic_debug_ict_array_sel_ff <= _T_9824 @[ifu_mem_ctl.scala 769:29] - reg _T_9825 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 770:54] - _T_9825 <= io.ic.debug_rd_en @[ifu_mem_ctl.scala 770:54] - ic_debug_rd_en_ff <= _T_9825 @[ifu_mem_ctl.scala 770:21] - reg _T_9826 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 771:79] - _T_9826 <= ic_debug_rd_en_ff @[ifu_mem_ctl.scala 771:79] - io.dec_mem_ctrl.ifu_ic_debug_rd_data_valid <= _T_9826 @[ifu_mem_ctl.scala 771:46] + node _T_9822 = and(_T_9821, io.ic.debug_way) @[ifu_mem_ctl.scala 765:90] + ic_debug_tag_wr_en <= _T_9822 @[ifu_mem_ctl.scala 765:22] + node ic_debug_ict_array_sel_in = and(io.ic.debug_rd_en, io.ic.debug_tag_array) @[ifu_mem_ctl.scala 766:53] + reg _T_9823 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 767:53] + _T_9823 <= io.ic.debug_way @[ifu_mem_ctl.scala 767:53] + ic_debug_way_ff <= _T_9823 @[ifu_mem_ctl.scala 767:19] + reg _T_9824 : UInt<1>, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 768:63] + _T_9824 <= ic_debug_ict_array_sel_in @[ifu_mem_ctl.scala 768:63] + ic_debug_ict_array_sel_ff <= _T_9824 @[ifu_mem_ctl.scala 768:29] + reg _T_9825 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 769:54] + _T_9825 <= io.ic.debug_rd_en @[ifu_mem_ctl.scala 769:54] + ic_debug_rd_en_ff <= _T_9825 @[ifu_mem_ctl.scala 769:21] + reg _T_9826 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 770:79] + _T_9826 <= ic_debug_rd_en_ff @[ifu_mem_ctl.scala 770:79] + io.dec_mem_ctrl.ifu_ic_debug_rd_data_valid <= _T_9826 @[ifu_mem_ctl.scala 770:46] node _T_9827 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58] node _T_9828 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58] node _T_9829 = cat(_T_9828, _T_9827) @[Cat.scala 29:58] @@ -15747,65 +15747,65 @@ circuit quasar_wrapper : node _T_9831 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58] node _T_9832 = cat(_T_9831, _T_9830) @[Cat.scala 29:58] node _T_9833 = cat(_T_9832, _T_9829) @[Cat.scala 29:58] - node _T_9834 = orr(_T_9833) @[ifu_mem_ctl.scala 773:215] - node _T_9835 = eq(_T_9834, UInt<1>("h00")) @[ifu_mem_ctl.scala 773:29] + node _T_9834 = orr(_T_9833) @[ifu_mem_ctl.scala 772:215] + node _T_9835 = eq(_T_9834, UInt<1>("h00")) @[ifu_mem_ctl.scala 772:29] node _T_9836 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_9837 = or(_T_9836, UInt<31>("h07fffffff")) @[ifu_mem_ctl.scala 774:65] - node _T_9838 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[ifu_mem_ctl.scala 774:129] - node _T_9839 = eq(_T_9837, _T_9838) @[ifu_mem_ctl.scala 774:96] - node _T_9840 = and(UInt<1>("h01"), _T_9839) @[ifu_mem_ctl.scala 774:30] - node _T_9841 = or(_T_9835, _T_9840) @[ifu_mem_ctl.scala 773:219] + node _T_9837 = or(_T_9836, UInt<31>("h07fffffff")) @[ifu_mem_ctl.scala 773:65] + node _T_9838 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[ifu_mem_ctl.scala 773:129] + node _T_9839 = eq(_T_9837, _T_9838) @[ifu_mem_ctl.scala 773:96] + node _T_9840 = and(UInt<1>("h01"), _T_9839) @[ifu_mem_ctl.scala 773:30] + node _T_9841 = or(_T_9835, _T_9840) @[ifu_mem_ctl.scala 772:219] node _T_9842 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_9843 = or(_T_9842, UInt<30>("h03fffffff")) @[ifu_mem_ctl.scala 775:65] - node _T_9844 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[ifu_mem_ctl.scala 775:129] - node _T_9845 = eq(_T_9843, _T_9844) @[ifu_mem_ctl.scala 775:96] - node _T_9846 = and(UInt<1>("h01"), _T_9845) @[ifu_mem_ctl.scala 775:30] - node _T_9847 = or(_T_9841, _T_9846) @[ifu_mem_ctl.scala 774:162] + node _T_9843 = or(_T_9842, UInt<30>("h03fffffff")) @[ifu_mem_ctl.scala 774:65] + node _T_9844 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[ifu_mem_ctl.scala 774:129] + node _T_9845 = eq(_T_9843, _T_9844) @[ifu_mem_ctl.scala 774:96] + node _T_9846 = and(UInt<1>("h01"), _T_9845) @[ifu_mem_ctl.scala 774:30] + node _T_9847 = or(_T_9841, _T_9846) @[ifu_mem_ctl.scala 773:162] node _T_9848 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_9849 = or(_T_9848, UInt<29>("h01fffffff")) @[ifu_mem_ctl.scala 776:65] - node _T_9850 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[ifu_mem_ctl.scala 776:129] - node _T_9851 = eq(_T_9849, _T_9850) @[ifu_mem_ctl.scala 776:96] - node _T_9852 = and(UInt<1>("h01"), _T_9851) @[ifu_mem_ctl.scala 776:30] - node _T_9853 = or(_T_9847, _T_9852) @[ifu_mem_ctl.scala 775:162] + node _T_9849 = or(_T_9848, UInt<29>("h01fffffff")) @[ifu_mem_ctl.scala 775:65] + node _T_9850 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[ifu_mem_ctl.scala 775:129] + node _T_9851 = eq(_T_9849, _T_9850) @[ifu_mem_ctl.scala 775:96] + node _T_9852 = and(UInt<1>("h01"), _T_9851) @[ifu_mem_ctl.scala 775:30] + node _T_9853 = or(_T_9847, _T_9852) @[ifu_mem_ctl.scala 774:162] node _T_9854 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_9855 = or(_T_9854, UInt<28>("h0fffffff")) @[ifu_mem_ctl.scala 777:65] - node _T_9856 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[ifu_mem_ctl.scala 777:129] - node _T_9857 = eq(_T_9855, _T_9856) @[ifu_mem_ctl.scala 777:96] - node _T_9858 = and(UInt<1>("h01"), _T_9857) @[ifu_mem_ctl.scala 777:30] - node _T_9859 = or(_T_9853, _T_9858) @[ifu_mem_ctl.scala 776:162] + node _T_9855 = or(_T_9854, UInt<28>("h0fffffff")) @[ifu_mem_ctl.scala 776:65] + node _T_9856 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[ifu_mem_ctl.scala 776:129] + node _T_9857 = eq(_T_9855, _T_9856) @[ifu_mem_ctl.scala 776:96] + node _T_9858 = and(UInt<1>("h01"), _T_9857) @[ifu_mem_ctl.scala 776:30] + node _T_9859 = or(_T_9853, _T_9858) @[ifu_mem_ctl.scala 775:162] node _T_9860 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_9861 = or(_T_9860, UInt<32>("h0ffffffff")) @[ifu_mem_ctl.scala 778:65] - node _T_9862 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[ifu_mem_ctl.scala 778:129] - node _T_9863 = eq(_T_9861, _T_9862) @[ifu_mem_ctl.scala 778:96] - node _T_9864 = and(UInt<1>("h00"), _T_9863) @[ifu_mem_ctl.scala 778:30] - node _T_9865 = or(_T_9859, _T_9864) @[ifu_mem_ctl.scala 777:162] + node _T_9861 = or(_T_9860, UInt<32>("h0ffffffff")) @[ifu_mem_ctl.scala 777:65] + node _T_9862 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[ifu_mem_ctl.scala 777:129] + node _T_9863 = eq(_T_9861, _T_9862) @[ifu_mem_ctl.scala 777:96] + node _T_9864 = and(UInt<1>("h00"), _T_9863) @[ifu_mem_ctl.scala 777:30] + node _T_9865 = or(_T_9859, _T_9864) @[ifu_mem_ctl.scala 776:162] node _T_9866 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_9867 = or(_T_9866, UInt<32>("h0ffffffff")) @[ifu_mem_ctl.scala 779:65] - node _T_9868 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[ifu_mem_ctl.scala 779:129] - node _T_9869 = eq(_T_9867, _T_9868) @[ifu_mem_ctl.scala 779:96] - node _T_9870 = and(UInt<1>("h00"), _T_9869) @[ifu_mem_ctl.scala 779:30] - node _T_9871 = or(_T_9865, _T_9870) @[ifu_mem_ctl.scala 778:162] + node _T_9867 = or(_T_9866, UInt<32>("h0ffffffff")) @[ifu_mem_ctl.scala 778:65] + node _T_9868 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[ifu_mem_ctl.scala 778:129] + node _T_9869 = eq(_T_9867, _T_9868) @[ifu_mem_ctl.scala 778:96] + node _T_9870 = and(UInt<1>("h00"), _T_9869) @[ifu_mem_ctl.scala 778:30] + node _T_9871 = or(_T_9865, _T_9870) @[ifu_mem_ctl.scala 777:162] node _T_9872 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_9873 = or(_T_9872, UInt<32>("h0ffffffff")) @[ifu_mem_ctl.scala 780:65] - node _T_9874 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[ifu_mem_ctl.scala 780:129] - node _T_9875 = eq(_T_9873, _T_9874) @[ifu_mem_ctl.scala 780:96] - node _T_9876 = and(UInt<1>("h00"), _T_9875) @[ifu_mem_ctl.scala 780:30] - node _T_9877 = or(_T_9871, _T_9876) @[ifu_mem_ctl.scala 779:162] + node _T_9873 = or(_T_9872, UInt<32>("h0ffffffff")) @[ifu_mem_ctl.scala 779:65] + node _T_9874 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[ifu_mem_ctl.scala 779:129] + node _T_9875 = eq(_T_9873, _T_9874) @[ifu_mem_ctl.scala 779:96] + node _T_9876 = and(UInt<1>("h00"), _T_9875) @[ifu_mem_ctl.scala 779:30] + node _T_9877 = or(_T_9871, _T_9876) @[ifu_mem_ctl.scala 778:162] node _T_9878 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_9879 = or(_T_9878, UInt<32>("h0ffffffff")) @[ifu_mem_ctl.scala 781:65] - node _T_9880 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[ifu_mem_ctl.scala 781:129] - node _T_9881 = eq(_T_9879, _T_9880) @[ifu_mem_ctl.scala 781:96] - node _T_9882 = and(UInt<1>("h00"), _T_9881) @[ifu_mem_ctl.scala 781:30] - node ifc_region_acc_okay = or(_T_9877, _T_9882) @[ifu_mem_ctl.scala 780:162] - node _T_9883 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[ifu_mem_ctl.scala 782:40] - node _T_9884 = eq(ifc_region_acc_okay, UInt<1>("h00")) @[ifu_mem_ctl.scala 782:65] - node _T_9885 = and(_T_9883, _T_9884) @[ifu_mem_ctl.scala 782:63] - node ifc_region_acc_fault_memory_bf = and(_T_9885, io.ifc_fetch_req_bf) @[ifu_mem_ctl.scala 782:86] - node _T_9886 = or(io.ifc_region_acc_fault_bf, ifc_region_acc_fault_memory_bf) @[ifu_mem_ctl.scala 783:63] - ifc_region_acc_fault_final_bf <= _T_9886 @[ifu_mem_ctl.scala 783:33] - reg _T_9887 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 784:66] - _T_9887 <= ifc_region_acc_fault_memory_bf @[ifu_mem_ctl.scala 784:66] - ifc_region_acc_fault_memory_f <= _T_9887 @[ifu_mem_ctl.scala 784:33] + node _T_9879 = or(_T_9878, UInt<32>("h0ffffffff")) @[ifu_mem_ctl.scala 780:65] + node _T_9880 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[ifu_mem_ctl.scala 780:129] + node _T_9881 = eq(_T_9879, _T_9880) @[ifu_mem_ctl.scala 780:96] + node _T_9882 = and(UInt<1>("h00"), _T_9881) @[ifu_mem_ctl.scala 780:30] + node ifc_region_acc_okay = or(_T_9877, _T_9882) @[ifu_mem_ctl.scala 779:162] + node _T_9883 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[ifu_mem_ctl.scala 781:40] + node _T_9884 = eq(ifc_region_acc_okay, UInt<1>("h00")) @[ifu_mem_ctl.scala 781:65] + node _T_9885 = and(_T_9883, _T_9884) @[ifu_mem_ctl.scala 781:63] + node ifc_region_acc_fault_memory_bf = and(_T_9885, io.ifc_fetch_req_bf) @[ifu_mem_ctl.scala 781:86] + node _T_9886 = or(io.ifc_region_acc_fault_bf, ifc_region_acc_fault_memory_bf) @[ifu_mem_ctl.scala 782:63] + ifc_region_acc_fault_final_bf <= _T_9886 @[ifu_mem_ctl.scala 782:33] + reg _T_9887 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_mem_ctl.scala 783:66] + _T_9887 <= ifc_region_acc_fault_memory_bf @[ifu_mem_ctl.scala 783:66] + ifc_region_acc_fault_memory_f <= _T_9887 @[ifu_mem_ctl.scala 783:33] extmodule gated_latch_94 : output Q : Clock diff --git a/quasar_wrapper.v b/quasar_wrapper.v index a5ef518c..514f23fb 100644 --- a/quasar_wrapper.v +++ b/quasar_wrapper.v @@ -984,22 +984,22 @@ module ifu_mem_ctl( wire debug_c1_clken = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[ifu_mem_ctl.scala 92:42] wire [3:0] ic_fetch_val_int_f = {2'h0,io_ic_fetch_val_f}; // @[Cat.scala 29:58] reg [30:0] ifu_fetch_addr_int_f; // @[ifu_mem_ctl.scala 214:63] - wire [4:0] _GEN_435 = {{1'd0}, ic_fetch_val_int_f}; // @[ifu_mem_ctl.scala 603:53] - wire [4:0] ic_fetch_val_shift_right = _GEN_435 << ifu_fetch_addr_int_f[0]; // @[ifu_mem_ctl.scala 603:53] - wire _T_3129 = |ic_fetch_val_shift_right[3:2]; // @[ifu_mem_ctl.scala 606:91] - wire _T_3131 = _T_3129 & _T_319; // @[ifu_mem_ctl.scala 606:95] + wire [4:0] _GEN_435 = {{1'd0}, ic_fetch_val_int_f}; // @[ifu_mem_ctl.scala 602:53] + wire [4:0] ic_fetch_val_shift_right = _GEN_435 << ifu_fetch_addr_int_f[0]; // @[ifu_mem_ctl.scala 602:53] + wire _T_3129 = |ic_fetch_val_shift_right[3:2]; // @[ifu_mem_ctl.scala 605:91] + wire _T_3131 = _T_3129 & _T_319; // @[ifu_mem_ctl.scala 605:95] reg ifc_iccm_access_f; // @[ifu_mem_ctl.scala 229:60] wire fetch_req_iccm_f = ifc_fetch_req_f & ifc_iccm_access_f; // @[ifu_mem_ctl.scala 181:46] - wire _T_3132 = _T_3131 & fetch_req_iccm_f; // @[ifu_mem_ctl.scala 606:117] - reg iccm_dma_rvalid_in; // @[ifu_mem_ctl.scala 592:59] - wire _T_3133 = _T_3132 | iccm_dma_rvalid_in; // @[ifu_mem_ctl.scala 606:134] - wire _T_3134 = ~io_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[ifu_mem_ctl.scala 606:158] - wire _T_3135 = _T_3133 & _T_3134; // @[ifu_mem_ctl.scala 606:156] - wire _T_3121 = |ic_fetch_val_shift_right[1:0]; // @[ifu_mem_ctl.scala 606:91] - wire _T_3123 = _T_3121 & _T_319; // @[ifu_mem_ctl.scala 606:95] - wire _T_3124 = _T_3123 & fetch_req_iccm_f; // @[ifu_mem_ctl.scala 606:117] - wire _T_3125 = _T_3124 | iccm_dma_rvalid_in; // @[ifu_mem_ctl.scala 606:134] - wire _T_3127 = _T_3125 & _T_3134; // @[ifu_mem_ctl.scala 606:156] + wire _T_3132 = _T_3131 & fetch_req_iccm_f; // @[ifu_mem_ctl.scala 605:117] + reg iccm_dma_rvalid_in; // @[ifu_mem_ctl.scala 591:59] + wire _T_3133 = _T_3132 | iccm_dma_rvalid_in; // @[ifu_mem_ctl.scala 605:134] + wire _T_3134 = ~io_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[ifu_mem_ctl.scala 605:158] + wire _T_3135 = _T_3133 & _T_3134; // @[ifu_mem_ctl.scala 605:156] + wire _T_3121 = |ic_fetch_val_shift_right[1:0]; // @[ifu_mem_ctl.scala 605:91] + wire _T_3123 = _T_3121 & _T_319; // @[ifu_mem_ctl.scala 605:95] + wire _T_3124 = _T_3123 & fetch_req_iccm_f; // @[ifu_mem_ctl.scala 605:117] + wire _T_3125 = _T_3124 | iccm_dma_rvalid_in; // @[ifu_mem_ctl.scala 605:134] + wire _T_3127 = _T_3125 & _T_3134; // @[ifu_mem_ctl.scala 605:156] wire [1:0] iccm_ecc_word_enable = {_T_3135,_T_3127}; // @[Cat.scala 29:58] wire _T_3620 = ^io_iccm_rd_data_ecc[70:39]; // @[lib.scala 193:30] wire _T_3621 = ^io_iccm_rd_data_ecc[77:71]; // @[lib.scala 193:44] @@ -1063,7 +1063,7 @@ module ifu_mem_ctl( wire _T_3351 = _T_3349 & _T_3347[6]; // @[lib.scala 194:53] wire [1:0] iccm_single_ecc_error = {_T_3736,_T_3351}; // @[Cat.scala 29:58] wire _T_3 = |iccm_single_ecc_error; // @[ifu_mem_ctl.scala 95:52] - reg dma_iccm_req_f; // @[ifu_mem_ctl.scala 569:51] + reg dma_iccm_req_f; // @[ifu_mem_ctl.scala 568:51] wire _T_6 = io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err | io_dec_mem_ctrl_ifu_ic_error_start; // @[ifu_mem_ctl.scala 96:74] reg [2:0] perr_state; // @[Reg.scala 27:20] wire _T_7 = perr_state == 3'h4; // @[ifu_mem_ctl.scala 97:54] @@ -1094,7 +1094,7 @@ module ifu_mem_ctl( wire _T_14 = _T_13 & io_ifu_axi_r_ready; // @[ifu_mem_ctl.scala 99:65] wire _T_227 = |io_ic_rd_hit; // @[ifu_mem_ctl.scala 189:37] wire _T_228 = ~_T_227; // @[ifu_mem_ctl.scala 189:23] - reg reset_all_tags; // @[ifu_mem_ctl.scala 638:53] + reg reset_all_tags; // @[ifu_mem_ctl.scala 637:53] wire _T_229 = _T_228 | reset_all_tags; // @[ifu_mem_ctl.scala 189:41] wire _T_207 = ~ifc_iccm_access_f; // @[ifu_mem_ctl.scala 180:48] wire _T_208 = ifc_fetch_req_f & _T_207; // @[ifu_mem_ctl.scala 180:46] @@ -1106,27 +1106,27 @@ module ifu_mem_ctl( wire _T_232 = _T_230 & _T_231; // @[ifu_mem_ctl.scala 189:80] wire _T_233 = _T_232 | scnd_miss_req; // @[ifu_mem_ctl.scala 189:97] wire ic_act_miss_f = _T_233 & _T_209; // @[ifu_mem_ctl.scala 189:114] - reg ifu_bus_rvalid_unq_ff; // @[ifu_mem_ctl.scala 511:56] + reg ifu_bus_rvalid_unq_ff; // @[ifu_mem_ctl.scala 510:56] reg bus_ifu_bus_clk_en_ff; // @[ifu_mem_ctl.scala 463:61] - wire ifu_bus_rvalid_ff = ifu_bus_rvalid_unq_ff & bus_ifu_bus_clk_en_ff; // @[ifu_mem_ctl.scala 525:49] - wire bus_ifu_wr_en_ff = ifu_bus_rvalid_ff & miss_pending; // @[ifu_mem_ctl.scala 553:41] + wire ifu_bus_rvalid_ff = ifu_bus_rvalid_unq_ff & bus_ifu_bus_clk_en_ff; // @[ifu_mem_ctl.scala 524:49] + wire bus_ifu_wr_en_ff = ifu_bus_rvalid_ff & miss_pending; // @[ifu_mem_ctl.scala 552:41] reg uncacheable_miss_ff; // @[ifu_mem_ctl.scala 216:62] - reg [2:0] bus_data_beat_count; // @[ifu_mem_ctl.scala 534:56] - wire _T_2672 = bus_data_beat_count == 3'h1; // @[ifu_mem_ctl.scala 551:69] - wire _T_2673 = &bus_data_beat_count; // @[ifu_mem_ctl.scala 551:101] - wire bus_last_data_beat = uncacheable_miss_ff ? _T_2672 : _T_2673; // @[ifu_mem_ctl.scala 551:28] - wire _T_2624 = bus_ifu_wr_en_ff & bus_last_data_beat; // @[ifu_mem_ctl.scala 530:68] - wire _T_2625 = ic_act_miss_f | _T_2624; // @[ifu_mem_ctl.scala 530:48] - wire bus_reset_data_beat_cnt = _T_2625 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 530:91] - wire _T_2621 = ~bus_last_data_beat; // @[ifu_mem_ctl.scala 529:50] - wire _T_2622 = bus_ifu_wr_en_ff & _T_2621; // @[ifu_mem_ctl.scala 529:48] - wire _T_2623 = ~io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 529:72] - wire bus_inc_data_beat_cnt = _T_2622 & _T_2623; // @[ifu_mem_ctl.scala 529:70] - wire [2:0] _T_2629 = bus_data_beat_count + 3'h1; // @[ifu_mem_ctl.scala 533:115] + reg [2:0] bus_data_beat_count; // @[ifu_mem_ctl.scala 533:56] + wire _T_2672 = bus_data_beat_count == 3'h1; // @[ifu_mem_ctl.scala 550:69] + wire _T_2673 = &bus_data_beat_count; // @[ifu_mem_ctl.scala 550:101] + wire bus_last_data_beat = uncacheable_miss_ff ? _T_2672 : _T_2673; // @[ifu_mem_ctl.scala 550:28] + wire _T_2624 = bus_ifu_wr_en_ff & bus_last_data_beat; // @[ifu_mem_ctl.scala 529:68] + wire _T_2625 = ic_act_miss_f | _T_2624; // @[ifu_mem_ctl.scala 529:48] + wire bus_reset_data_beat_cnt = _T_2625 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 529:91] + wire _T_2621 = ~bus_last_data_beat; // @[ifu_mem_ctl.scala 528:50] + wire _T_2622 = bus_ifu_wr_en_ff & _T_2621; // @[ifu_mem_ctl.scala 528:48] + wire _T_2623 = ~io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 528:72] + wire bus_inc_data_beat_cnt = _T_2622 & _T_2623; // @[ifu_mem_ctl.scala 528:70] + wire [2:0] _T_2629 = bus_data_beat_count + 3'h1; // @[ifu_mem_ctl.scala 532:115] wire [2:0] _T_2631 = bus_inc_data_beat_cnt ? _T_2629 : 3'h0; // @[Mux.scala 27:72] - wire _T_2626 = ~bus_inc_data_beat_cnt; // @[ifu_mem_ctl.scala 531:32] - wire _T_2627 = ~bus_reset_data_beat_cnt; // @[ifu_mem_ctl.scala 531:57] - wire bus_hold_data_beat_cnt = _T_2626 & _T_2627; // @[ifu_mem_ctl.scala 531:55] + wire _T_2626 = ~bus_inc_data_beat_cnt; // @[ifu_mem_ctl.scala 530:32] + wire _T_2627 = ~bus_reset_data_beat_cnt; // @[ifu_mem_ctl.scala 530:57] + wire bus_hold_data_beat_cnt = _T_2626 & _T_2627; // @[ifu_mem_ctl.scala 530:55] wire [2:0] _T_2632 = bus_hold_data_beat_cnt ? bus_data_beat_count : 3'h0; // @[Mux.scala 27:72] wire [2:0] bus_new_data_beat_count = _T_2631 | _T_2632; // @[Mux.scala 27:72] wire _T_15 = &bus_new_data_beat_count; // @[ifu_mem_ctl.scala 99:112] @@ -1214,8 +1214,8 @@ module ifu_mem_ctl( wire _T_215 = crit_byp_hit_f | stream_hit_f; // @[ifu_mem_ctl.scala 184:35] wire _T_216 = _T_215 & fetch_req_icache_f; // @[ifu_mem_ctl.scala 184:52] wire ic_byp_hit_f = _T_216 & miss_pending; // @[ifu_mem_ctl.scala 184:73] - reg last_data_recieved_ff; // @[ifu_mem_ctl.scala 536:58] - wire last_beat = bus_last_data_beat & bus_ifu_wr_en_ff; // @[ifu_mem_ctl.scala 563:35] + reg last_data_recieved_ff; // @[ifu_mem_ctl.scala 535:58] + wire last_beat = bus_last_data_beat & bus_ifu_wr_en_ff; // @[ifu_mem_ctl.scala 562:35] wire _T_32 = bus_ifu_wr_en_ff & last_beat; // @[ifu_mem_ctl.scala 110:126] wire _T_33 = last_data_recieved_ff | _T_32; // @[ifu_mem_ctl.scala 110:106] wire _T_34 = ic_byp_hit_f & _T_33; // @[ifu_mem_ctl.scala 110:80] @@ -1349,515 +1349,515 @@ module ifu_mem_ctl( wire _T_191 = _T_19 | ic_miss_under_miss_f; // @[ifu_mem_ctl.scala 165:57] wire sel_hold_imb_scnd = _T_191 & _T_174; // @[ifu_mem_ctl.scala 165:81] reg way_status_mb_scnd_ff; // @[ifu_mem_ctl.scala 173:64] - reg [6:0] ifu_ic_rw_int_addr_ff; // @[ifu_mem_ctl.scala 670:14] - wire _T_4671 = ifu_ic_rw_int_addr_ff == 7'h0; // @[ifu_mem_ctl.scala 666:80] + reg [6:0] ifu_ic_rw_int_addr_ff; // @[ifu_mem_ctl.scala 669:14] + wire _T_4671 = ifu_ic_rw_int_addr_ff == 7'h0; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_0; // @[Reg.scala 27:20] wire _T_4799 = _T_4671 & way_status_out_0; // @[Mux.scala 27:72] - wire _T_4672 = ifu_ic_rw_int_addr_ff == 7'h1; // @[ifu_mem_ctl.scala 666:80] + wire _T_4672 = ifu_ic_rw_int_addr_ff == 7'h1; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_1; // @[Reg.scala 27:20] wire _T_4800 = _T_4672 & way_status_out_1; // @[Mux.scala 27:72] wire _T_4927 = _T_4799 | _T_4800; // @[Mux.scala 27:72] - wire _T_4673 = ifu_ic_rw_int_addr_ff == 7'h2; // @[ifu_mem_ctl.scala 666:80] + wire _T_4673 = ifu_ic_rw_int_addr_ff == 7'h2; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_2; // @[Reg.scala 27:20] wire _T_4801 = _T_4673 & way_status_out_2; // @[Mux.scala 27:72] wire _T_4928 = _T_4927 | _T_4801; // @[Mux.scala 27:72] - wire _T_4674 = ifu_ic_rw_int_addr_ff == 7'h3; // @[ifu_mem_ctl.scala 666:80] + wire _T_4674 = ifu_ic_rw_int_addr_ff == 7'h3; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_3; // @[Reg.scala 27:20] wire _T_4802 = _T_4674 & way_status_out_3; // @[Mux.scala 27:72] wire _T_4929 = _T_4928 | _T_4802; // @[Mux.scala 27:72] - wire _T_4675 = ifu_ic_rw_int_addr_ff == 7'h4; // @[ifu_mem_ctl.scala 666:80] + wire _T_4675 = ifu_ic_rw_int_addr_ff == 7'h4; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_4; // @[Reg.scala 27:20] wire _T_4803 = _T_4675 & way_status_out_4; // @[Mux.scala 27:72] wire _T_4930 = _T_4929 | _T_4803; // @[Mux.scala 27:72] - wire _T_4676 = ifu_ic_rw_int_addr_ff == 7'h5; // @[ifu_mem_ctl.scala 666:80] + wire _T_4676 = ifu_ic_rw_int_addr_ff == 7'h5; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_5; // @[Reg.scala 27:20] wire _T_4804 = _T_4676 & way_status_out_5; // @[Mux.scala 27:72] wire _T_4931 = _T_4930 | _T_4804; // @[Mux.scala 27:72] - wire _T_4677 = ifu_ic_rw_int_addr_ff == 7'h6; // @[ifu_mem_ctl.scala 666:80] + wire _T_4677 = ifu_ic_rw_int_addr_ff == 7'h6; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_6; // @[Reg.scala 27:20] wire _T_4805 = _T_4677 & way_status_out_6; // @[Mux.scala 27:72] wire _T_4932 = _T_4931 | _T_4805; // @[Mux.scala 27:72] - wire _T_4678 = ifu_ic_rw_int_addr_ff == 7'h7; // @[ifu_mem_ctl.scala 666:80] + wire _T_4678 = ifu_ic_rw_int_addr_ff == 7'h7; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_7; // @[Reg.scala 27:20] wire _T_4806 = _T_4678 & way_status_out_7; // @[Mux.scala 27:72] wire _T_4933 = _T_4932 | _T_4806; // @[Mux.scala 27:72] - wire _T_4679 = ifu_ic_rw_int_addr_ff == 7'h8; // @[ifu_mem_ctl.scala 666:80] + wire _T_4679 = ifu_ic_rw_int_addr_ff == 7'h8; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_8; // @[Reg.scala 27:20] wire _T_4807 = _T_4679 & way_status_out_8; // @[Mux.scala 27:72] wire _T_4934 = _T_4933 | _T_4807; // @[Mux.scala 27:72] - wire _T_4680 = ifu_ic_rw_int_addr_ff == 7'h9; // @[ifu_mem_ctl.scala 666:80] + wire _T_4680 = ifu_ic_rw_int_addr_ff == 7'h9; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_9; // @[Reg.scala 27:20] wire _T_4808 = _T_4680 & way_status_out_9; // @[Mux.scala 27:72] wire _T_4935 = _T_4934 | _T_4808; // @[Mux.scala 27:72] - wire _T_4681 = ifu_ic_rw_int_addr_ff == 7'ha; // @[ifu_mem_ctl.scala 666:80] + wire _T_4681 = ifu_ic_rw_int_addr_ff == 7'ha; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_10; // @[Reg.scala 27:20] wire _T_4809 = _T_4681 & way_status_out_10; // @[Mux.scala 27:72] wire _T_4936 = _T_4935 | _T_4809; // @[Mux.scala 27:72] - wire _T_4682 = ifu_ic_rw_int_addr_ff == 7'hb; // @[ifu_mem_ctl.scala 666:80] + wire _T_4682 = ifu_ic_rw_int_addr_ff == 7'hb; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_11; // @[Reg.scala 27:20] wire _T_4810 = _T_4682 & way_status_out_11; // @[Mux.scala 27:72] wire _T_4937 = _T_4936 | _T_4810; // @[Mux.scala 27:72] - wire _T_4683 = ifu_ic_rw_int_addr_ff == 7'hc; // @[ifu_mem_ctl.scala 666:80] + wire _T_4683 = ifu_ic_rw_int_addr_ff == 7'hc; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_12; // @[Reg.scala 27:20] wire _T_4811 = _T_4683 & way_status_out_12; // @[Mux.scala 27:72] wire _T_4938 = _T_4937 | _T_4811; // @[Mux.scala 27:72] - wire _T_4684 = ifu_ic_rw_int_addr_ff == 7'hd; // @[ifu_mem_ctl.scala 666:80] + wire _T_4684 = ifu_ic_rw_int_addr_ff == 7'hd; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_13; // @[Reg.scala 27:20] wire _T_4812 = _T_4684 & way_status_out_13; // @[Mux.scala 27:72] wire _T_4939 = _T_4938 | _T_4812; // @[Mux.scala 27:72] - wire _T_4685 = ifu_ic_rw_int_addr_ff == 7'he; // @[ifu_mem_ctl.scala 666:80] + wire _T_4685 = ifu_ic_rw_int_addr_ff == 7'he; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_14; // @[Reg.scala 27:20] wire _T_4813 = _T_4685 & way_status_out_14; // @[Mux.scala 27:72] wire _T_4940 = _T_4939 | _T_4813; // @[Mux.scala 27:72] - wire _T_4686 = ifu_ic_rw_int_addr_ff == 7'hf; // @[ifu_mem_ctl.scala 666:80] + wire _T_4686 = ifu_ic_rw_int_addr_ff == 7'hf; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_15; // @[Reg.scala 27:20] wire _T_4814 = _T_4686 & way_status_out_15; // @[Mux.scala 27:72] wire _T_4941 = _T_4940 | _T_4814; // @[Mux.scala 27:72] - wire _T_4687 = ifu_ic_rw_int_addr_ff == 7'h10; // @[ifu_mem_ctl.scala 666:80] + wire _T_4687 = ifu_ic_rw_int_addr_ff == 7'h10; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_16; // @[Reg.scala 27:20] wire _T_4815 = _T_4687 & way_status_out_16; // @[Mux.scala 27:72] wire _T_4942 = _T_4941 | _T_4815; // @[Mux.scala 27:72] - wire _T_4688 = ifu_ic_rw_int_addr_ff == 7'h11; // @[ifu_mem_ctl.scala 666:80] + wire _T_4688 = ifu_ic_rw_int_addr_ff == 7'h11; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_17; // @[Reg.scala 27:20] wire _T_4816 = _T_4688 & way_status_out_17; // @[Mux.scala 27:72] wire _T_4943 = _T_4942 | _T_4816; // @[Mux.scala 27:72] - wire _T_4689 = ifu_ic_rw_int_addr_ff == 7'h12; // @[ifu_mem_ctl.scala 666:80] + wire _T_4689 = ifu_ic_rw_int_addr_ff == 7'h12; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_18; // @[Reg.scala 27:20] wire _T_4817 = _T_4689 & way_status_out_18; // @[Mux.scala 27:72] wire _T_4944 = _T_4943 | _T_4817; // @[Mux.scala 27:72] - wire _T_4690 = ifu_ic_rw_int_addr_ff == 7'h13; // @[ifu_mem_ctl.scala 666:80] + wire _T_4690 = ifu_ic_rw_int_addr_ff == 7'h13; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_19; // @[Reg.scala 27:20] wire _T_4818 = _T_4690 & way_status_out_19; // @[Mux.scala 27:72] wire _T_4945 = _T_4944 | _T_4818; // @[Mux.scala 27:72] - wire _T_4691 = ifu_ic_rw_int_addr_ff == 7'h14; // @[ifu_mem_ctl.scala 666:80] + wire _T_4691 = ifu_ic_rw_int_addr_ff == 7'h14; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_20; // @[Reg.scala 27:20] wire _T_4819 = _T_4691 & way_status_out_20; // @[Mux.scala 27:72] wire _T_4946 = _T_4945 | _T_4819; // @[Mux.scala 27:72] - wire _T_4692 = ifu_ic_rw_int_addr_ff == 7'h15; // @[ifu_mem_ctl.scala 666:80] + wire _T_4692 = ifu_ic_rw_int_addr_ff == 7'h15; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_21; // @[Reg.scala 27:20] wire _T_4820 = _T_4692 & way_status_out_21; // @[Mux.scala 27:72] wire _T_4947 = _T_4946 | _T_4820; // @[Mux.scala 27:72] - wire _T_4693 = ifu_ic_rw_int_addr_ff == 7'h16; // @[ifu_mem_ctl.scala 666:80] + wire _T_4693 = ifu_ic_rw_int_addr_ff == 7'h16; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_22; // @[Reg.scala 27:20] wire _T_4821 = _T_4693 & way_status_out_22; // @[Mux.scala 27:72] wire _T_4948 = _T_4947 | _T_4821; // @[Mux.scala 27:72] - wire _T_4694 = ifu_ic_rw_int_addr_ff == 7'h17; // @[ifu_mem_ctl.scala 666:80] + wire _T_4694 = ifu_ic_rw_int_addr_ff == 7'h17; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_23; // @[Reg.scala 27:20] wire _T_4822 = _T_4694 & way_status_out_23; // @[Mux.scala 27:72] wire _T_4949 = _T_4948 | _T_4822; // @[Mux.scala 27:72] - wire _T_4695 = ifu_ic_rw_int_addr_ff == 7'h18; // @[ifu_mem_ctl.scala 666:80] + wire _T_4695 = ifu_ic_rw_int_addr_ff == 7'h18; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_24; // @[Reg.scala 27:20] wire _T_4823 = _T_4695 & way_status_out_24; // @[Mux.scala 27:72] wire _T_4950 = _T_4949 | _T_4823; // @[Mux.scala 27:72] - wire _T_4696 = ifu_ic_rw_int_addr_ff == 7'h19; // @[ifu_mem_ctl.scala 666:80] + wire _T_4696 = ifu_ic_rw_int_addr_ff == 7'h19; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_25; // @[Reg.scala 27:20] wire _T_4824 = _T_4696 & way_status_out_25; // @[Mux.scala 27:72] wire _T_4951 = _T_4950 | _T_4824; // @[Mux.scala 27:72] - wire _T_4697 = ifu_ic_rw_int_addr_ff == 7'h1a; // @[ifu_mem_ctl.scala 666:80] + wire _T_4697 = ifu_ic_rw_int_addr_ff == 7'h1a; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_26; // @[Reg.scala 27:20] wire _T_4825 = _T_4697 & way_status_out_26; // @[Mux.scala 27:72] wire _T_4952 = _T_4951 | _T_4825; // @[Mux.scala 27:72] - wire _T_4698 = ifu_ic_rw_int_addr_ff == 7'h1b; // @[ifu_mem_ctl.scala 666:80] + wire _T_4698 = ifu_ic_rw_int_addr_ff == 7'h1b; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_27; // @[Reg.scala 27:20] wire _T_4826 = _T_4698 & way_status_out_27; // @[Mux.scala 27:72] wire _T_4953 = _T_4952 | _T_4826; // @[Mux.scala 27:72] - wire _T_4699 = ifu_ic_rw_int_addr_ff == 7'h1c; // @[ifu_mem_ctl.scala 666:80] + wire _T_4699 = ifu_ic_rw_int_addr_ff == 7'h1c; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_28; // @[Reg.scala 27:20] wire _T_4827 = _T_4699 & way_status_out_28; // @[Mux.scala 27:72] wire _T_4954 = _T_4953 | _T_4827; // @[Mux.scala 27:72] - wire _T_4700 = ifu_ic_rw_int_addr_ff == 7'h1d; // @[ifu_mem_ctl.scala 666:80] + wire _T_4700 = ifu_ic_rw_int_addr_ff == 7'h1d; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_29; // @[Reg.scala 27:20] wire _T_4828 = _T_4700 & way_status_out_29; // @[Mux.scala 27:72] wire _T_4955 = _T_4954 | _T_4828; // @[Mux.scala 27:72] - wire _T_4701 = ifu_ic_rw_int_addr_ff == 7'h1e; // @[ifu_mem_ctl.scala 666:80] + wire _T_4701 = ifu_ic_rw_int_addr_ff == 7'h1e; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_30; // @[Reg.scala 27:20] wire _T_4829 = _T_4701 & way_status_out_30; // @[Mux.scala 27:72] wire _T_4956 = _T_4955 | _T_4829; // @[Mux.scala 27:72] - wire _T_4702 = ifu_ic_rw_int_addr_ff == 7'h1f; // @[ifu_mem_ctl.scala 666:80] + wire _T_4702 = ifu_ic_rw_int_addr_ff == 7'h1f; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_31; // @[Reg.scala 27:20] wire _T_4830 = _T_4702 & way_status_out_31; // @[Mux.scala 27:72] wire _T_4957 = _T_4956 | _T_4830; // @[Mux.scala 27:72] - wire _T_4703 = ifu_ic_rw_int_addr_ff == 7'h20; // @[ifu_mem_ctl.scala 666:80] + wire _T_4703 = ifu_ic_rw_int_addr_ff == 7'h20; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_32; // @[Reg.scala 27:20] wire _T_4831 = _T_4703 & way_status_out_32; // @[Mux.scala 27:72] wire _T_4958 = _T_4957 | _T_4831; // @[Mux.scala 27:72] - wire _T_4704 = ifu_ic_rw_int_addr_ff == 7'h21; // @[ifu_mem_ctl.scala 666:80] + wire _T_4704 = ifu_ic_rw_int_addr_ff == 7'h21; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_33; // @[Reg.scala 27:20] wire _T_4832 = _T_4704 & way_status_out_33; // @[Mux.scala 27:72] wire _T_4959 = _T_4958 | _T_4832; // @[Mux.scala 27:72] - wire _T_4705 = ifu_ic_rw_int_addr_ff == 7'h22; // @[ifu_mem_ctl.scala 666:80] + wire _T_4705 = ifu_ic_rw_int_addr_ff == 7'h22; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_34; // @[Reg.scala 27:20] wire _T_4833 = _T_4705 & way_status_out_34; // @[Mux.scala 27:72] wire _T_4960 = _T_4959 | _T_4833; // @[Mux.scala 27:72] - wire _T_4706 = ifu_ic_rw_int_addr_ff == 7'h23; // @[ifu_mem_ctl.scala 666:80] + wire _T_4706 = ifu_ic_rw_int_addr_ff == 7'h23; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_35; // @[Reg.scala 27:20] wire _T_4834 = _T_4706 & way_status_out_35; // @[Mux.scala 27:72] wire _T_4961 = _T_4960 | _T_4834; // @[Mux.scala 27:72] - wire _T_4707 = ifu_ic_rw_int_addr_ff == 7'h24; // @[ifu_mem_ctl.scala 666:80] + wire _T_4707 = ifu_ic_rw_int_addr_ff == 7'h24; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_36; // @[Reg.scala 27:20] wire _T_4835 = _T_4707 & way_status_out_36; // @[Mux.scala 27:72] wire _T_4962 = _T_4961 | _T_4835; // @[Mux.scala 27:72] - wire _T_4708 = ifu_ic_rw_int_addr_ff == 7'h25; // @[ifu_mem_ctl.scala 666:80] + wire _T_4708 = ifu_ic_rw_int_addr_ff == 7'h25; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_37; // @[Reg.scala 27:20] wire _T_4836 = _T_4708 & way_status_out_37; // @[Mux.scala 27:72] wire _T_4963 = _T_4962 | _T_4836; // @[Mux.scala 27:72] - wire _T_4709 = ifu_ic_rw_int_addr_ff == 7'h26; // @[ifu_mem_ctl.scala 666:80] + wire _T_4709 = ifu_ic_rw_int_addr_ff == 7'h26; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_38; // @[Reg.scala 27:20] wire _T_4837 = _T_4709 & way_status_out_38; // @[Mux.scala 27:72] wire _T_4964 = _T_4963 | _T_4837; // @[Mux.scala 27:72] - wire _T_4710 = ifu_ic_rw_int_addr_ff == 7'h27; // @[ifu_mem_ctl.scala 666:80] + wire _T_4710 = ifu_ic_rw_int_addr_ff == 7'h27; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_39; // @[Reg.scala 27:20] wire _T_4838 = _T_4710 & way_status_out_39; // @[Mux.scala 27:72] wire _T_4965 = _T_4964 | _T_4838; // @[Mux.scala 27:72] - wire _T_4711 = ifu_ic_rw_int_addr_ff == 7'h28; // @[ifu_mem_ctl.scala 666:80] + wire _T_4711 = ifu_ic_rw_int_addr_ff == 7'h28; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_40; // @[Reg.scala 27:20] wire _T_4839 = _T_4711 & way_status_out_40; // @[Mux.scala 27:72] wire _T_4966 = _T_4965 | _T_4839; // @[Mux.scala 27:72] - wire _T_4712 = ifu_ic_rw_int_addr_ff == 7'h29; // @[ifu_mem_ctl.scala 666:80] + wire _T_4712 = ifu_ic_rw_int_addr_ff == 7'h29; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_41; // @[Reg.scala 27:20] wire _T_4840 = _T_4712 & way_status_out_41; // @[Mux.scala 27:72] wire _T_4967 = _T_4966 | _T_4840; // @[Mux.scala 27:72] - wire _T_4713 = ifu_ic_rw_int_addr_ff == 7'h2a; // @[ifu_mem_ctl.scala 666:80] + wire _T_4713 = ifu_ic_rw_int_addr_ff == 7'h2a; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_42; // @[Reg.scala 27:20] wire _T_4841 = _T_4713 & way_status_out_42; // @[Mux.scala 27:72] wire _T_4968 = _T_4967 | _T_4841; // @[Mux.scala 27:72] - wire _T_4714 = ifu_ic_rw_int_addr_ff == 7'h2b; // @[ifu_mem_ctl.scala 666:80] + wire _T_4714 = ifu_ic_rw_int_addr_ff == 7'h2b; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_43; // @[Reg.scala 27:20] wire _T_4842 = _T_4714 & way_status_out_43; // @[Mux.scala 27:72] wire _T_4969 = _T_4968 | _T_4842; // @[Mux.scala 27:72] - wire _T_4715 = ifu_ic_rw_int_addr_ff == 7'h2c; // @[ifu_mem_ctl.scala 666:80] + wire _T_4715 = ifu_ic_rw_int_addr_ff == 7'h2c; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_44; // @[Reg.scala 27:20] wire _T_4843 = _T_4715 & way_status_out_44; // @[Mux.scala 27:72] wire _T_4970 = _T_4969 | _T_4843; // @[Mux.scala 27:72] - wire _T_4716 = ifu_ic_rw_int_addr_ff == 7'h2d; // @[ifu_mem_ctl.scala 666:80] + wire _T_4716 = ifu_ic_rw_int_addr_ff == 7'h2d; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_45; // @[Reg.scala 27:20] wire _T_4844 = _T_4716 & way_status_out_45; // @[Mux.scala 27:72] wire _T_4971 = _T_4970 | _T_4844; // @[Mux.scala 27:72] - wire _T_4717 = ifu_ic_rw_int_addr_ff == 7'h2e; // @[ifu_mem_ctl.scala 666:80] + wire _T_4717 = ifu_ic_rw_int_addr_ff == 7'h2e; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_46; // @[Reg.scala 27:20] wire _T_4845 = _T_4717 & way_status_out_46; // @[Mux.scala 27:72] wire _T_4972 = _T_4971 | _T_4845; // @[Mux.scala 27:72] - wire _T_4718 = ifu_ic_rw_int_addr_ff == 7'h2f; // @[ifu_mem_ctl.scala 666:80] + wire _T_4718 = ifu_ic_rw_int_addr_ff == 7'h2f; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_47; // @[Reg.scala 27:20] wire _T_4846 = _T_4718 & way_status_out_47; // @[Mux.scala 27:72] wire _T_4973 = _T_4972 | _T_4846; // @[Mux.scala 27:72] - wire _T_4719 = ifu_ic_rw_int_addr_ff == 7'h30; // @[ifu_mem_ctl.scala 666:80] + wire _T_4719 = ifu_ic_rw_int_addr_ff == 7'h30; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_48; // @[Reg.scala 27:20] wire _T_4847 = _T_4719 & way_status_out_48; // @[Mux.scala 27:72] wire _T_4974 = _T_4973 | _T_4847; // @[Mux.scala 27:72] - wire _T_4720 = ifu_ic_rw_int_addr_ff == 7'h31; // @[ifu_mem_ctl.scala 666:80] + wire _T_4720 = ifu_ic_rw_int_addr_ff == 7'h31; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_49; // @[Reg.scala 27:20] wire _T_4848 = _T_4720 & way_status_out_49; // @[Mux.scala 27:72] wire _T_4975 = _T_4974 | _T_4848; // @[Mux.scala 27:72] - wire _T_4721 = ifu_ic_rw_int_addr_ff == 7'h32; // @[ifu_mem_ctl.scala 666:80] + wire _T_4721 = ifu_ic_rw_int_addr_ff == 7'h32; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_50; // @[Reg.scala 27:20] wire _T_4849 = _T_4721 & way_status_out_50; // @[Mux.scala 27:72] wire _T_4976 = _T_4975 | _T_4849; // @[Mux.scala 27:72] - wire _T_4722 = ifu_ic_rw_int_addr_ff == 7'h33; // @[ifu_mem_ctl.scala 666:80] + wire _T_4722 = ifu_ic_rw_int_addr_ff == 7'h33; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_51; // @[Reg.scala 27:20] wire _T_4850 = _T_4722 & way_status_out_51; // @[Mux.scala 27:72] wire _T_4977 = _T_4976 | _T_4850; // @[Mux.scala 27:72] - wire _T_4723 = ifu_ic_rw_int_addr_ff == 7'h34; // @[ifu_mem_ctl.scala 666:80] + wire _T_4723 = ifu_ic_rw_int_addr_ff == 7'h34; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_52; // @[Reg.scala 27:20] wire _T_4851 = _T_4723 & way_status_out_52; // @[Mux.scala 27:72] wire _T_4978 = _T_4977 | _T_4851; // @[Mux.scala 27:72] - wire _T_4724 = ifu_ic_rw_int_addr_ff == 7'h35; // @[ifu_mem_ctl.scala 666:80] + wire _T_4724 = ifu_ic_rw_int_addr_ff == 7'h35; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_53; // @[Reg.scala 27:20] wire _T_4852 = _T_4724 & way_status_out_53; // @[Mux.scala 27:72] wire _T_4979 = _T_4978 | _T_4852; // @[Mux.scala 27:72] - wire _T_4725 = ifu_ic_rw_int_addr_ff == 7'h36; // @[ifu_mem_ctl.scala 666:80] + wire _T_4725 = ifu_ic_rw_int_addr_ff == 7'h36; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_54; // @[Reg.scala 27:20] wire _T_4853 = _T_4725 & way_status_out_54; // @[Mux.scala 27:72] wire _T_4980 = _T_4979 | _T_4853; // @[Mux.scala 27:72] - wire _T_4726 = ifu_ic_rw_int_addr_ff == 7'h37; // @[ifu_mem_ctl.scala 666:80] + wire _T_4726 = ifu_ic_rw_int_addr_ff == 7'h37; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_55; // @[Reg.scala 27:20] wire _T_4854 = _T_4726 & way_status_out_55; // @[Mux.scala 27:72] wire _T_4981 = _T_4980 | _T_4854; // @[Mux.scala 27:72] - wire _T_4727 = ifu_ic_rw_int_addr_ff == 7'h38; // @[ifu_mem_ctl.scala 666:80] + wire _T_4727 = ifu_ic_rw_int_addr_ff == 7'h38; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_56; // @[Reg.scala 27:20] wire _T_4855 = _T_4727 & way_status_out_56; // @[Mux.scala 27:72] wire _T_4982 = _T_4981 | _T_4855; // @[Mux.scala 27:72] - wire _T_4728 = ifu_ic_rw_int_addr_ff == 7'h39; // @[ifu_mem_ctl.scala 666:80] + wire _T_4728 = ifu_ic_rw_int_addr_ff == 7'h39; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_57; // @[Reg.scala 27:20] wire _T_4856 = _T_4728 & way_status_out_57; // @[Mux.scala 27:72] wire _T_4983 = _T_4982 | _T_4856; // @[Mux.scala 27:72] - wire _T_4729 = ifu_ic_rw_int_addr_ff == 7'h3a; // @[ifu_mem_ctl.scala 666:80] + wire _T_4729 = ifu_ic_rw_int_addr_ff == 7'h3a; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_58; // @[Reg.scala 27:20] wire _T_4857 = _T_4729 & way_status_out_58; // @[Mux.scala 27:72] wire _T_4984 = _T_4983 | _T_4857; // @[Mux.scala 27:72] - wire _T_4730 = ifu_ic_rw_int_addr_ff == 7'h3b; // @[ifu_mem_ctl.scala 666:80] + wire _T_4730 = ifu_ic_rw_int_addr_ff == 7'h3b; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_59; // @[Reg.scala 27:20] wire _T_4858 = _T_4730 & way_status_out_59; // @[Mux.scala 27:72] wire _T_4985 = _T_4984 | _T_4858; // @[Mux.scala 27:72] - wire _T_4731 = ifu_ic_rw_int_addr_ff == 7'h3c; // @[ifu_mem_ctl.scala 666:80] + wire _T_4731 = ifu_ic_rw_int_addr_ff == 7'h3c; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_60; // @[Reg.scala 27:20] wire _T_4859 = _T_4731 & way_status_out_60; // @[Mux.scala 27:72] wire _T_4986 = _T_4985 | _T_4859; // @[Mux.scala 27:72] - wire _T_4732 = ifu_ic_rw_int_addr_ff == 7'h3d; // @[ifu_mem_ctl.scala 666:80] + wire _T_4732 = ifu_ic_rw_int_addr_ff == 7'h3d; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_61; // @[Reg.scala 27:20] wire _T_4860 = _T_4732 & way_status_out_61; // @[Mux.scala 27:72] wire _T_4987 = _T_4986 | _T_4860; // @[Mux.scala 27:72] - wire _T_4733 = ifu_ic_rw_int_addr_ff == 7'h3e; // @[ifu_mem_ctl.scala 666:80] + wire _T_4733 = ifu_ic_rw_int_addr_ff == 7'h3e; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_62; // @[Reg.scala 27:20] wire _T_4861 = _T_4733 & way_status_out_62; // @[Mux.scala 27:72] wire _T_4988 = _T_4987 | _T_4861; // @[Mux.scala 27:72] - wire _T_4734 = ifu_ic_rw_int_addr_ff == 7'h3f; // @[ifu_mem_ctl.scala 666:80] + wire _T_4734 = ifu_ic_rw_int_addr_ff == 7'h3f; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_63; // @[Reg.scala 27:20] wire _T_4862 = _T_4734 & way_status_out_63; // @[Mux.scala 27:72] wire _T_4989 = _T_4988 | _T_4862; // @[Mux.scala 27:72] - wire _T_4735 = ifu_ic_rw_int_addr_ff == 7'h40; // @[ifu_mem_ctl.scala 666:80] + wire _T_4735 = ifu_ic_rw_int_addr_ff == 7'h40; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_64; // @[Reg.scala 27:20] wire _T_4863 = _T_4735 & way_status_out_64; // @[Mux.scala 27:72] wire _T_4990 = _T_4989 | _T_4863; // @[Mux.scala 27:72] - wire _T_4736 = ifu_ic_rw_int_addr_ff == 7'h41; // @[ifu_mem_ctl.scala 666:80] + wire _T_4736 = ifu_ic_rw_int_addr_ff == 7'h41; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_65; // @[Reg.scala 27:20] wire _T_4864 = _T_4736 & way_status_out_65; // @[Mux.scala 27:72] wire _T_4991 = _T_4990 | _T_4864; // @[Mux.scala 27:72] - wire _T_4737 = ifu_ic_rw_int_addr_ff == 7'h42; // @[ifu_mem_ctl.scala 666:80] + wire _T_4737 = ifu_ic_rw_int_addr_ff == 7'h42; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_66; // @[Reg.scala 27:20] wire _T_4865 = _T_4737 & way_status_out_66; // @[Mux.scala 27:72] wire _T_4992 = _T_4991 | _T_4865; // @[Mux.scala 27:72] - wire _T_4738 = ifu_ic_rw_int_addr_ff == 7'h43; // @[ifu_mem_ctl.scala 666:80] + wire _T_4738 = ifu_ic_rw_int_addr_ff == 7'h43; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_67; // @[Reg.scala 27:20] wire _T_4866 = _T_4738 & way_status_out_67; // @[Mux.scala 27:72] wire _T_4993 = _T_4992 | _T_4866; // @[Mux.scala 27:72] - wire _T_4739 = ifu_ic_rw_int_addr_ff == 7'h44; // @[ifu_mem_ctl.scala 666:80] + wire _T_4739 = ifu_ic_rw_int_addr_ff == 7'h44; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_68; // @[Reg.scala 27:20] wire _T_4867 = _T_4739 & way_status_out_68; // @[Mux.scala 27:72] wire _T_4994 = _T_4993 | _T_4867; // @[Mux.scala 27:72] - wire _T_4740 = ifu_ic_rw_int_addr_ff == 7'h45; // @[ifu_mem_ctl.scala 666:80] + wire _T_4740 = ifu_ic_rw_int_addr_ff == 7'h45; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_69; // @[Reg.scala 27:20] wire _T_4868 = _T_4740 & way_status_out_69; // @[Mux.scala 27:72] wire _T_4995 = _T_4994 | _T_4868; // @[Mux.scala 27:72] - wire _T_4741 = ifu_ic_rw_int_addr_ff == 7'h46; // @[ifu_mem_ctl.scala 666:80] + wire _T_4741 = ifu_ic_rw_int_addr_ff == 7'h46; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_70; // @[Reg.scala 27:20] wire _T_4869 = _T_4741 & way_status_out_70; // @[Mux.scala 27:72] wire _T_4996 = _T_4995 | _T_4869; // @[Mux.scala 27:72] - wire _T_4742 = ifu_ic_rw_int_addr_ff == 7'h47; // @[ifu_mem_ctl.scala 666:80] + wire _T_4742 = ifu_ic_rw_int_addr_ff == 7'h47; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_71; // @[Reg.scala 27:20] wire _T_4870 = _T_4742 & way_status_out_71; // @[Mux.scala 27:72] wire _T_4997 = _T_4996 | _T_4870; // @[Mux.scala 27:72] - wire _T_4743 = ifu_ic_rw_int_addr_ff == 7'h48; // @[ifu_mem_ctl.scala 666:80] + wire _T_4743 = ifu_ic_rw_int_addr_ff == 7'h48; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_72; // @[Reg.scala 27:20] wire _T_4871 = _T_4743 & way_status_out_72; // @[Mux.scala 27:72] wire _T_4998 = _T_4997 | _T_4871; // @[Mux.scala 27:72] - wire _T_4744 = ifu_ic_rw_int_addr_ff == 7'h49; // @[ifu_mem_ctl.scala 666:80] + wire _T_4744 = ifu_ic_rw_int_addr_ff == 7'h49; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_73; // @[Reg.scala 27:20] wire _T_4872 = _T_4744 & way_status_out_73; // @[Mux.scala 27:72] wire _T_4999 = _T_4998 | _T_4872; // @[Mux.scala 27:72] - wire _T_4745 = ifu_ic_rw_int_addr_ff == 7'h4a; // @[ifu_mem_ctl.scala 666:80] + wire _T_4745 = ifu_ic_rw_int_addr_ff == 7'h4a; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_74; // @[Reg.scala 27:20] wire _T_4873 = _T_4745 & way_status_out_74; // @[Mux.scala 27:72] wire _T_5000 = _T_4999 | _T_4873; // @[Mux.scala 27:72] - wire _T_4746 = ifu_ic_rw_int_addr_ff == 7'h4b; // @[ifu_mem_ctl.scala 666:80] + wire _T_4746 = ifu_ic_rw_int_addr_ff == 7'h4b; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_75; // @[Reg.scala 27:20] wire _T_4874 = _T_4746 & way_status_out_75; // @[Mux.scala 27:72] wire _T_5001 = _T_5000 | _T_4874; // @[Mux.scala 27:72] - wire _T_4747 = ifu_ic_rw_int_addr_ff == 7'h4c; // @[ifu_mem_ctl.scala 666:80] + wire _T_4747 = ifu_ic_rw_int_addr_ff == 7'h4c; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_76; // @[Reg.scala 27:20] wire _T_4875 = _T_4747 & way_status_out_76; // @[Mux.scala 27:72] wire _T_5002 = _T_5001 | _T_4875; // @[Mux.scala 27:72] - wire _T_4748 = ifu_ic_rw_int_addr_ff == 7'h4d; // @[ifu_mem_ctl.scala 666:80] + wire _T_4748 = ifu_ic_rw_int_addr_ff == 7'h4d; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_77; // @[Reg.scala 27:20] wire _T_4876 = _T_4748 & way_status_out_77; // @[Mux.scala 27:72] wire _T_5003 = _T_5002 | _T_4876; // @[Mux.scala 27:72] - wire _T_4749 = ifu_ic_rw_int_addr_ff == 7'h4e; // @[ifu_mem_ctl.scala 666:80] + wire _T_4749 = ifu_ic_rw_int_addr_ff == 7'h4e; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_78; // @[Reg.scala 27:20] wire _T_4877 = _T_4749 & way_status_out_78; // @[Mux.scala 27:72] wire _T_5004 = _T_5003 | _T_4877; // @[Mux.scala 27:72] - wire _T_4750 = ifu_ic_rw_int_addr_ff == 7'h4f; // @[ifu_mem_ctl.scala 666:80] + wire _T_4750 = ifu_ic_rw_int_addr_ff == 7'h4f; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_79; // @[Reg.scala 27:20] wire _T_4878 = _T_4750 & way_status_out_79; // @[Mux.scala 27:72] wire _T_5005 = _T_5004 | _T_4878; // @[Mux.scala 27:72] - wire _T_4751 = ifu_ic_rw_int_addr_ff == 7'h50; // @[ifu_mem_ctl.scala 666:80] + wire _T_4751 = ifu_ic_rw_int_addr_ff == 7'h50; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_80; // @[Reg.scala 27:20] wire _T_4879 = _T_4751 & way_status_out_80; // @[Mux.scala 27:72] wire _T_5006 = _T_5005 | _T_4879; // @[Mux.scala 27:72] - wire _T_4752 = ifu_ic_rw_int_addr_ff == 7'h51; // @[ifu_mem_ctl.scala 666:80] + wire _T_4752 = ifu_ic_rw_int_addr_ff == 7'h51; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_81; // @[Reg.scala 27:20] wire _T_4880 = _T_4752 & way_status_out_81; // @[Mux.scala 27:72] wire _T_5007 = _T_5006 | _T_4880; // @[Mux.scala 27:72] - wire _T_4753 = ifu_ic_rw_int_addr_ff == 7'h52; // @[ifu_mem_ctl.scala 666:80] + wire _T_4753 = ifu_ic_rw_int_addr_ff == 7'h52; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_82; // @[Reg.scala 27:20] wire _T_4881 = _T_4753 & way_status_out_82; // @[Mux.scala 27:72] wire _T_5008 = _T_5007 | _T_4881; // @[Mux.scala 27:72] - wire _T_4754 = ifu_ic_rw_int_addr_ff == 7'h53; // @[ifu_mem_ctl.scala 666:80] + wire _T_4754 = ifu_ic_rw_int_addr_ff == 7'h53; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_83; // @[Reg.scala 27:20] wire _T_4882 = _T_4754 & way_status_out_83; // @[Mux.scala 27:72] wire _T_5009 = _T_5008 | _T_4882; // @[Mux.scala 27:72] - wire _T_4755 = ifu_ic_rw_int_addr_ff == 7'h54; // @[ifu_mem_ctl.scala 666:80] + wire _T_4755 = ifu_ic_rw_int_addr_ff == 7'h54; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_84; // @[Reg.scala 27:20] wire _T_4883 = _T_4755 & way_status_out_84; // @[Mux.scala 27:72] wire _T_5010 = _T_5009 | _T_4883; // @[Mux.scala 27:72] - wire _T_4756 = ifu_ic_rw_int_addr_ff == 7'h55; // @[ifu_mem_ctl.scala 666:80] + wire _T_4756 = ifu_ic_rw_int_addr_ff == 7'h55; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_85; // @[Reg.scala 27:20] wire _T_4884 = _T_4756 & way_status_out_85; // @[Mux.scala 27:72] wire _T_5011 = _T_5010 | _T_4884; // @[Mux.scala 27:72] - wire _T_4757 = ifu_ic_rw_int_addr_ff == 7'h56; // @[ifu_mem_ctl.scala 666:80] + wire _T_4757 = ifu_ic_rw_int_addr_ff == 7'h56; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_86; // @[Reg.scala 27:20] wire _T_4885 = _T_4757 & way_status_out_86; // @[Mux.scala 27:72] wire _T_5012 = _T_5011 | _T_4885; // @[Mux.scala 27:72] - wire _T_4758 = ifu_ic_rw_int_addr_ff == 7'h57; // @[ifu_mem_ctl.scala 666:80] + wire _T_4758 = ifu_ic_rw_int_addr_ff == 7'h57; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_87; // @[Reg.scala 27:20] wire _T_4886 = _T_4758 & way_status_out_87; // @[Mux.scala 27:72] wire _T_5013 = _T_5012 | _T_4886; // @[Mux.scala 27:72] - wire _T_4759 = ifu_ic_rw_int_addr_ff == 7'h58; // @[ifu_mem_ctl.scala 666:80] + wire _T_4759 = ifu_ic_rw_int_addr_ff == 7'h58; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_88; // @[Reg.scala 27:20] wire _T_4887 = _T_4759 & way_status_out_88; // @[Mux.scala 27:72] wire _T_5014 = _T_5013 | _T_4887; // @[Mux.scala 27:72] - wire _T_4760 = ifu_ic_rw_int_addr_ff == 7'h59; // @[ifu_mem_ctl.scala 666:80] + wire _T_4760 = ifu_ic_rw_int_addr_ff == 7'h59; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_89; // @[Reg.scala 27:20] wire _T_4888 = _T_4760 & way_status_out_89; // @[Mux.scala 27:72] wire _T_5015 = _T_5014 | _T_4888; // @[Mux.scala 27:72] - wire _T_4761 = ifu_ic_rw_int_addr_ff == 7'h5a; // @[ifu_mem_ctl.scala 666:80] + wire _T_4761 = ifu_ic_rw_int_addr_ff == 7'h5a; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_90; // @[Reg.scala 27:20] wire _T_4889 = _T_4761 & way_status_out_90; // @[Mux.scala 27:72] wire _T_5016 = _T_5015 | _T_4889; // @[Mux.scala 27:72] - wire _T_4762 = ifu_ic_rw_int_addr_ff == 7'h5b; // @[ifu_mem_ctl.scala 666:80] + wire _T_4762 = ifu_ic_rw_int_addr_ff == 7'h5b; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_91; // @[Reg.scala 27:20] wire _T_4890 = _T_4762 & way_status_out_91; // @[Mux.scala 27:72] wire _T_5017 = _T_5016 | _T_4890; // @[Mux.scala 27:72] - wire _T_4763 = ifu_ic_rw_int_addr_ff == 7'h5c; // @[ifu_mem_ctl.scala 666:80] + wire _T_4763 = ifu_ic_rw_int_addr_ff == 7'h5c; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_92; // @[Reg.scala 27:20] wire _T_4891 = _T_4763 & way_status_out_92; // @[Mux.scala 27:72] wire _T_5018 = _T_5017 | _T_4891; // @[Mux.scala 27:72] - wire _T_4764 = ifu_ic_rw_int_addr_ff == 7'h5d; // @[ifu_mem_ctl.scala 666:80] + wire _T_4764 = ifu_ic_rw_int_addr_ff == 7'h5d; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_93; // @[Reg.scala 27:20] wire _T_4892 = _T_4764 & way_status_out_93; // @[Mux.scala 27:72] wire _T_5019 = _T_5018 | _T_4892; // @[Mux.scala 27:72] - wire _T_4765 = ifu_ic_rw_int_addr_ff == 7'h5e; // @[ifu_mem_ctl.scala 666:80] + wire _T_4765 = ifu_ic_rw_int_addr_ff == 7'h5e; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_94; // @[Reg.scala 27:20] wire _T_4893 = _T_4765 & way_status_out_94; // @[Mux.scala 27:72] wire _T_5020 = _T_5019 | _T_4893; // @[Mux.scala 27:72] - wire _T_4766 = ifu_ic_rw_int_addr_ff == 7'h5f; // @[ifu_mem_ctl.scala 666:80] + wire _T_4766 = ifu_ic_rw_int_addr_ff == 7'h5f; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_95; // @[Reg.scala 27:20] wire _T_4894 = _T_4766 & way_status_out_95; // @[Mux.scala 27:72] wire _T_5021 = _T_5020 | _T_4894; // @[Mux.scala 27:72] - wire _T_4767 = ifu_ic_rw_int_addr_ff == 7'h60; // @[ifu_mem_ctl.scala 666:80] + wire _T_4767 = ifu_ic_rw_int_addr_ff == 7'h60; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_96; // @[Reg.scala 27:20] wire _T_4895 = _T_4767 & way_status_out_96; // @[Mux.scala 27:72] wire _T_5022 = _T_5021 | _T_4895; // @[Mux.scala 27:72] - wire _T_4768 = ifu_ic_rw_int_addr_ff == 7'h61; // @[ifu_mem_ctl.scala 666:80] + wire _T_4768 = ifu_ic_rw_int_addr_ff == 7'h61; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_97; // @[Reg.scala 27:20] wire _T_4896 = _T_4768 & way_status_out_97; // @[Mux.scala 27:72] wire _T_5023 = _T_5022 | _T_4896; // @[Mux.scala 27:72] - wire _T_4769 = ifu_ic_rw_int_addr_ff == 7'h62; // @[ifu_mem_ctl.scala 666:80] + wire _T_4769 = ifu_ic_rw_int_addr_ff == 7'h62; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_98; // @[Reg.scala 27:20] wire _T_4897 = _T_4769 & way_status_out_98; // @[Mux.scala 27:72] wire _T_5024 = _T_5023 | _T_4897; // @[Mux.scala 27:72] - wire _T_4770 = ifu_ic_rw_int_addr_ff == 7'h63; // @[ifu_mem_ctl.scala 666:80] + wire _T_4770 = ifu_ic_rw_int_addr_ff == 7'h63; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_99; // @[Reg.scala 27:20] wire _T_4898 = _T_4770 & way_status_out_99; // @[Mux.scala 27:72] wire _T_5025 = _T_5024 | _T_4898; // @[Mux.scala 27:72] - wire _T_4771 = ifu_ic_rw_int_addr_ff == 7'h64; // @[ifu_mem_ctl.scala 666:80] + wire _T_4771 = ifu_ic_rw_int_addr_ff == 7'h64; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_100; // @[Reg.scala 27:20] wire _T_4899 = _T_4771 & way_status_out_100; // @[Mux.scala 27:72] wire _T_5026 = _T_5025 | _T_4899; // @[Mux.scala 27:72] - wire _T_4772 = ifu_ic_rw_int_addr_ff == 7'h65; // @[ifu_mem_ctl.scala 666:80] + wire _T_4772 = ifu_ic_rw_int_addr_ff == 7'h65; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_101; // @[Reg.scala 27:20] wire _T_4900 = _T_4772 & way_status_out_101; // @[Mux.scala 27:72] wire _T_5027 = _T_5026 | _T_4900; // @[Mux.scala 27:72] - wire _T_4773 = ifu_ic_rw_int_addr_ff == 7'h66; // @[ifu_mem_ctl.scala 666:80] + wire _T_4773 = ifu_ic_rw_int_addr_ff == 7'h66; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_102; // @[Reg.scala 27:20] wire _T_4901 = _T_4773 & way_status_out_102; // @[Mux.scala 27:72] wire _T_5028 = _T_5027 | _T_4901; // @[Mux.scala 27:72] - wire _T_4774 = ifu_ic_rw_int_addr_ff == 7'h67; // @[ifu_mem_ctl.scala 666:80] + wire _T_4774 = ifu_ic_rw_int_addr_ff == 7'h67; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_103; // @[Reg.scala 27:20] wire _T_4902 = _T_4774 & way_status_out_103; // @[Mux.scala 27:72] wire _T_5029 = _T_5028 | _T_4902; // @[Mux.scala 27:72] - wire _T_4775 = ifu_ic_rw_int_addr_ff == 7'h68; // @[ifu_mem_ctl.scala 666:80] + wire _T_4775 = ifu_ic_rw_int_addr_ff == 7'h68; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_104; // @[Reg.scala 27:20] wire _T_4903 = _T_4775 & way_status_out_104; // @[Mux.scala 27:72] wire _T_5030 = _T_5029 | _T_4903; // @[Mux.scala 27:72] - wire _T_4776 = ifu_ic_rw_int_addr_ff == 7'h69; // @[ifu_mem_ctl.scala 666:80] + wire _T_4776 = ifu_ic_rw_int_addr_ff == 7'h69; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_105; // @[Reg.scala 27:20] wire _T_4904 = _T_4776 & way_status_out_105; // @[Mux.scala 27:72] wire _T_5031 = _T_5030 | _T_4904; // @[Mux.scala 27:72] - wire _T_4777 = ifu_ic_rw_int_addr_ff == 7'h6a; // @[ifu_mem_ctl.scala 666:80] + wire _T_4777 = ifu_ic_rw_int_addr_ff == 7'h6a; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_106; // @[Reg.scala 27:20] wire _T_4905 = _T_4777 & way_status_out_106; // @[Mux.scala 27:72] wire _T_5032 = _T_5031 | _T_4905; // @[Mux.scala 27:72] - wire _T_4778 = ifu_ic_rw_int_addr_ff == 7'h6b; // @[ifu_mem_ctl.scala 666:80] + wire _T_4778 = ifu_ic_rw_int_addr_ff == 7'h6b; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_107; // @[Reg.scala 27:20] wire _T_4906 = _T_4778 & way_status_out_107; // @[Mux.scala 27:72] wire _T_5033 = _T_5032 | _T_4906; // @[Mux.scala 27:72] - wire _T_4779 = ifu_ic_rw_int_addr_ff == 7'h6c; // @[ifu_mem_ctl.scala 666:80] + wire _T_4779 = ifu_ic_rw_int_addr_ff == 7'h6c; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_108; // @[Reg.scala 27:20] wire _T_4907 = _T_4779 & way_status_out_108; // @[Mux.scala 27:72] wire _T_5034 = _T_5033 | _T_4907; // @[Mux.scala 27:72] - wire _T_4780 = ifu_ic_rw_int_addr_ff == 7'h6d; // @[ifu_mem_ctl.scala 666:80] + wire _T_4780 = ifu_ic_rw_int_addr_ff == 7'h6d; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_109; // @[Reg.scala 27:20] wire _T_4908 = _T_4780 & way_status_out_109; // @[Mux.scala 27:72] wire _T_5035 = _T_5034 | _T_4908; // @[Mux.scala 27:72] - wire _T_4781 = ifu_ic_rw_int_addr_ff == 7'h6e; // @[ifu_mem_ctl.scala 666:80] + wire _T_4781 = ifu_ic_rw_int_addr_ff == 7'h6e; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_110; // @[Reg.scala 27:20] wire _T_4909 = _T_4781 & way_status_out_110; // @[Mux.scala 27:72] wire _T_5036 = _T_5035 | _T_4909; // @[Mux.scala 27:72] - wire _T_4782 = ifu_ic_rw_int_addr_ff == 7'h6f; // @[ifu_mem_ctl.scala 666:80] + wire _T_4782 = ifu_ic_rw_int_addr_ff == 7'h6f; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_111; // @[Reg.scala 27:20] wire _T_4910 = _T_4782 & way_status_out_111; // @[Mux.scala 27:72] wire _T_5037 = _T_5036 | _T_4910; // @[Mux.scala 27:72] - wire _T_4783 = ifu_ic_rw_int_addr_ff == 7'h70; // @[ifu_mem_ctl.scala 666:80] + wire _T_4783 = ifu_ic_rw_int_addr_ff == 7'h70; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_112; // @[Reg.scala 27:20] wire _T_4911 = _T_4783 & way_status_out_112; // @[Mux.scala 27:72] wire _T_5038 = _T_5037 | _T_4911; // @[Mux.scala 27:72] - wire _T_4784 = ifu_ic_rw_int_addr_ff == 7'h71; // @[ifu_mem_ctl.scala 666:80] + wire _T_4784 = ifu_ic_rw_int_addr_ff == 7'h71; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_113; // @[Reg.scala 27:20] wire _T_4912 = _T_4784 & way_status_out_113; // @[Mux.scala 27:72] wire _T_5039 = _T_5038 | _T_4912; // @[Mux.scala 27:72] - wire _T_4785 = ifu_ic_rw_int_addr_ff == 7'h72; // @[ifu_mem_ctl.scala 666:80] + wire _T_4785 = ifu_ic_rw_int_addr_ff == 7'h72; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_114; // @[Reg.scala 27:20] wire _T_4913 = _T_4785 & way_status_out_114; // @[Mux.scala 27:72] wire _T_5040 = _T_5039 | _T_4913; // @[Mux.scala 27:72] - wire _T_4786 = ifu_ic_rw_int_addr_ff == 7'h73; // @[ifu_mem_ctl.scala 666:80] + wire _T_4786 = ifu_ic_rw_int_addr_ff == 7'h73; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_115; // @[Reg.scala 27:20] wire _T_4914 = _T_4786 & way_status_out_115; // @[Mux.scala 27:72] wire _T_5041 = _T_5040 | _T_4914; // @[Mux.scala 27:72] - wire _T_4787 = ifu_ic_rw_int_addr_ff == 7'h74; // @[ifu_mem_ctl.scala 666:80] + wire _T_4787 = ifu_ic_rw_int_addr_ff == 7'h74; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_116; // @[Reg.scala 27:20] wire _T_4915 = _T_4787 & way_status_out_116; // @[Mux.scala 27:72] wire _T_5042 = _T_5041 | _T_4915; // @[Mux.scala 27:72] - wire _T_4788 = ifu_ic_rw_int_addr_ff == 7'h75; // @[ifu_mem_ctl.scala 666:80] + wire _T_4788 = ifu_ic_rw_int_addr_ff == 7'h75; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_117; // @[Reg.scala 27:20] wire _T_4916 = _T_4788 & way_status_out_117; // @[Mux.scala 27:72] wire _T_5043 = _T_5042 | _T_4916; // @[Mux.scala 27:72] - wire _T_4789 = ifu_ic_rw_int_addr_ff == 7'h76; // @[ifu_mem_ctl.scala 666:80] + wire _T_4789 = ifu_ic_rw_int_addr_ff == 7'h76; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_118; // @[Reg.scala 27:20] wire _T_4917 = _T_4789 & way_status_out_118; // @[Mux.scala 27:72] wire _T_5044 = _T_5043 | _T_4917; // @[Mux.scala 27:72] - wire _T_4790 = ifu_ic_rw_int_addr_ff == 7'h77; // @[ifu_mem_ctl.scala 666:80] + wire _T_4790 = ifu_ic_rw_int_addr_ff == 7'h77; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_119; // @[Reg.scala 27:20] wire _T_4918 = _T_4790 & way_status_out_119; // @[Mux.scala 27:72] wire _T_5045 = _T_5044 | _T_4918; // @[Mux.scala 27:72] - wire _T_4791 = ifu_ic_rw_int_addr_ff == 7'h78; // @[ifu_mem_ctl.scala 666:80] + wire _T_4791 = ifu_ic_rw_int_addr_ff == 7'h78; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_120; // @[Reg.scala 27:20] wire _T_4919 = _T_4791 & way_status_out_120; // @[Mux.scala 27:72] wire _T_5046 = _T_5045 | _T_4919; // @[Mux.scala 27:72] - wire _T_4792 = ifu_ic_rw_int_addr_ff == 7'h79; // @[ifu_mem_ctl.scala 666:80] + wire _T_4792 = ifu_ic_rw_int_addr_ff == 7'h79; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_121; // @[Reg.scala 27:20] wire _T_4920 = _T_4792 & way_status_out_121; // @[Mux.scala 27:72] wire _T_5047 = _T_5046 | _T_4920; // @[Mux.scala 27:72] - wire _T_4793 = ifu_ic_rw_int_addr_ff == 7'h7a; // @[ifu_mem_ctl.scala 666:80] + wire _T_4793 = ifu_ic_rw_int_addr_ff == 7'h7a; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_122; // @[Reg.scala 27:20] wire _T_4921 = _T_4793 & way_status_out_122; // @[Mux.scala 27:72] wire _T_5048 = _T_5047 | _T_4921; // @[Mux.scala 27:72] - wire _T_4794 = ifu_ic_rw_int_addr_ff == 7'h7b; // @[ifu_mem_ctl.scala 666:80] + wire _T_4794 = ifu_ic_rw_int_addr_ff == 7'h7b; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_123; // @[Reg.scala 27:20] wire _T_4922 = _T_4794 & way_status_out_123; // @[Mux.scala 27:72] wire _T_5049 = _T_5048 | _T_4922; // @[Mux.scala 27:72] - wire _T_4795 = ifu_ic_rw_int_addr_ff == 7'h7c; // @[ifu_mem_ctl.scala 666:80] + wire _T_4795 = ifu_ic_rw_int_addr_ff == 7'h7c; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_124; // @[Reg.scala 27:20] wire _T_4923 = _T_4795 & way_status_out_124; // @[Mux.scala 27:72] wire _T_5050 = _T_5049 | _T_4923; // @[Mux.scala 27:72] - wire _T_4796 = ifu_ic_rw_int_addr_ff == 7'h7d; // @[ifu_mem_ctl.scala 666:80] + wire _T_4796 = ifu_ic_rw_int_addr_ff == 7'h7d; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_125; // @[Reg.scala 27:20] wire _T_4924 = _T_4796 & way_status_out_125; // @[Mux.scala 27:72] wire _T_5051 = _T_5050 | _T_4924; // @[Mux.scala 27:72] - wire _T_4797 = ifu_ic_rw_int_addr_ff == 7'h7e; // @[ifu_mem_ctl.scala 666:80] + wire _T_4797 = ifu_ic_rw_int_addr_ff == 7'h7e; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_126; // @[Reg.scala 27:20] wire _T_4925 = _T_4797 & way_status_out_126; // @[Mux.scala 27:72] wire _T_5052 = _T_5051 | _T_4925; // @[Mux.scala 27:72] - wire _T_4798 = ifu_ic_rw_int_addr_ff == 7'h7f; // @[ifu_mem_ctl.scala 666:80] + wire _T_4798 = ifu_ic_rw_int_addr_ff == 7'h7f; // @[ifu_mem_ctl.scala 665:80] reg way_status_out_127; // @[Reg.scala 27:20] wire _T_4926 = _T_4798 & way_status_out_127; // @[Mux.scala 27:72] wire way_status = _T_5052 | _T_4926; // @[Mux.scala 27:72] @@ -1868,7 +1868,7 @@ module ifu_mem_ctl( reg uncacheable_miss_scnd_ff; // @[ifu_mem_ctl.scala 170:67] reg [30:0] imb_scnd_ff; // @[ifu_mem_ctl.scala 172:54] wire [2:0] _T_206 = bus_ifu_wr_en_ff ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - reg [2:0] ifu_bus_rid_ff; // @[ifu_mem_ctl.scala 515:46] + reg [2:0] ifu_bus_rid_ff; // @[ifu_mem_ctl.scala 514:46] wire [2:0] ic_wr_addr_bits_hi_3 = ifu_bus_rid_ff & _T_206; // @[ifu_mem_ctl.scala 177:45] wire _T_212 = _T_231 | _T_239; // @[ifu_mem_ctl.scala 182:59] wire _T_214 = _T_212 | _T_2268; // @[ifu_mem_ctl.scala 182:91] @@ -1884,10 +1884,10 @@ module ifu_mem_ctl( wire uncacheable_miss_in = scnd_miss_req ? uncacheable_miss_scnd_ff : _T_268; // @[ifu_mem_ctl.scala 196:32] wire _T_274 = imb_ff[11:5] == imb_scnd_ff[11:5]; // @[ifu_mem_ctl.scala 199:79] wire _T_275 = _T_274 & scnd_miss_req; // @[ifu_mem_ctl.scala 199:135] - reg [1:0] ifu_bus_rresp_ff; // @[ifu_mem_ctl.scala 513:51] - wire _T_2693 = |ifu_bus_rresp_ff; // @[ifu_mem_ctl.scala 559:48] - wire _T_2694 = _T_2693 & ifu_bus_rvalid_ff; // @[ifu_mem_ctl.scala 559:52] - wire bus_ifu_wr_data_error_ff = _T_2694 & miss_pending; // @[ifu_mem_ctl.scala 559:73] + reg [1:0] ifu_bus_rresp_ff; // @[ifu_mem_ctl.scala 512:51] + wire _T_2693 = |ifu_bus_rresp_ff; // @[ifu_mem_ctl.scala 558:48] + wire _T_2694 = _T_2693 & ifu_bus_rvalid_ff; // @[ifu_mem_ctl.scala 558:52] + wire bus_ifu_wr_data_error_ff = _T_2694 & miss_pending; // @[ifu_mem_ctl.scala 558:73] reg ifu_wr_data_comb_err_ff; // @[ifu_mem_ctl.scala 276:61] wire ifu_wr_cumulative_err_data = bus_ifu_wr_data_error_ff | ifu_wr_data_comb_err_ff; // @[ifu_mem_ctl.scala 275:55] wire _T_276 = ~ifu_wr_cumulative_err_data; // @[ifu_mem_ctl.scala 199:153] @@ -1896,18 +1896,18 @@ module ifu_mem_ctl( wire _T_278 = scnd_miss_req & _T_277; // @[ifu_mem_ctl.scala 202:45] wire _T_280 = scnd_miss_req & scnd_miss_index_match; // @[ifu_mem_ctl.scala 203:26] reg way_status_mb_ff; // @[ifu_mem_ctl.scala 223:59] - wire _T_9756 = ~way_status_mb_ff; // @[ifu_mem_ctl.scala 721:33] + wire _T_9756 = ~way_status_mb_ff; // @[ifu_mem_ctl.scala 720:33] reg [1:0] tagv_mb_ff; // @[ifu_mem_ctl.scala 224:53] - wire _T_9758 = _T_9756 & tagv_mb_ff[0]; // @[ifu_mem_ctl.scala 721:51] - wire _T_9760 = _T_9758 & tagv_mb_ff[1]; // @[ifu_mem_ctl.scala 721:67] - wire _T_9762 = ~tagv_mb_ff[0]; // @[ifu_mem_ctl.scala 721:86] - wire replace_way_mb_any_0 = _T_9760 | _T_9762; // @[ifu_mem_ctl.scala 721:84] + wire _T_9758 = _T_9756 & tagv_mb_ff[0]; // @[ifu_mem_ctl.scala 720:51] + wire _T_9760 = _T_9758 & tagv_mb_ff[1]; // @[ifu_mem_ctl.scala 720:67] + wire _T_9762 = ~tagv_mb_ff[0]; // @[ifu_mem_ctl.scala 720:86] + wire replace_way_mb_any_0 = _T_9760 | _T_9762; // @[ifu_mem_ctl.scala 720:84] wire [1:0] _T_287 = scnd_miss_index_match ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire _T_9765 = way_status_mb_ff & tagv_mb_ff[0]; // @[ifu_mem_ctl.scala 722:50] - wire _T_9767 = _T_9765 & tagv_mb_ff[1]; // @[ifu_mem_ctl.scala 722:66] - wire _T_9769 = ~tagv_mb_ff[1]; // @[ifu_mem_ctl.scala 722:85] - wire _T_9771 = _T_9769 & tagv_mb_ff[0]; // @[ifu_mem_ctl.scala 722:100] - wire replace_way_mb_any_1 = _T_9767 | _T_9771; // @[ifu_mem_ctl.scala 722:83] + wire _T_9765 = way_status_mb_ff & tagv_mb_ff[0]; // @[ifu_mem_ctl.scala 721:50] + wire _T_9767 = _T_9765 & tagv_mb_ff[1]; // @[ifu_mem_ctl.scala 721:66] + wire _T_9769 = ~tagv_mb_ff[1]; // @[ifu_mem_ctl.scala 721:85] + wire _T_9771 = _T_9769 & tagv_mb_ff[0]; // @[ifu_mem_ctl.scala 721:100] + wire replace_way_mb_any_1 = _T_9767 | _T_9771; // @[ifu_mem_ctl.scala 721:83] wire [1:0] _T_288 = {replace_way_mb_any_1,replace_way_mb_any_0}; // @[Cat.scala 29:58] wire [1:0] _T_289 = _T_287 & _T_288; // @[ifu_mem_ctl.scala 207:110] wire [1:0] _T_290 = tagv_mb_scnd_ff | _T_289; // @[ifu_mem_ctl.scala 207:62] @@ -1928,7 +1928,7 @@ module ifu_mem_ctl( wire stream_miss_f = _T_2276 & ifc_fetch_req_f; // @[ifu_mem_ctl.scala 373:84] wire _T_318 = ~stream_miss_f; // @[ifu_mem_ctl.scala 226:106] reg ifc_region_acc_fault_f; // @[ifu_mem_ctl.scala 232:68] - reg [2:0] bus_rd_addr_count; // @[ifu_mem_ctl.scala 541:55] + reg [2:0] bus_rd_addr_count; // @[ifu_mem_ctl.scala 540:55] wire [28:0] ifu_ic_req_addr_f = {miss_addr,bus_rd_addr_count}; // @[Cat.scala 29:58] wire _T_325 = _T_239 | _T_2268; // @[ifu_mem_ctl.scala 234:55] wire _T_328 = _T_325 & _T_56; // @[ifu_mem_ctl.scala 234:82] @@ -1960,9 +1960,9 @@ module ifu_mem_ctl( wire write_ic_16_bytes = second_half_available & bus_ifu_wr_en_ff; // @[ifu_mem_ctl.scala 380:46] wire _T_332 = miss_pending & write_ic_16_bytes; // @[ifu_mem_ctl.scala 238:35] wire _T_334 = _T_332 & _T_17; // @[ifu_mem_ctl.scala 238:55] - reg ic_act_miss_f_delayed; // @[ifu_mem_ctl.scala 556:61] - wire _T_2687 = ic_act_miss_f_delayed & _T_2284; // @[ifu_mem_ctl.scala 557:53] - wire reset_tag_valid_for_miss = _T_2687 & _T_17; // @[ifu_mem_ctl.scala 557:84] + reg ic_act_miss_f_delayed; // @[ifu_mem_ctl.scala 555:61] + wire _T_2687 = ic_act_miss_f_delayed & _T_2284; // @[ifu_mem_ctl.scala 556:53] + wire reset_tag_valid_for_miss = _T_2687 & _T_17; // @[ifu_mem_ctl.scala 556:84] wire sel_mb_addr = _T_334 | reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 238:79] wire [30:0] _T_338 = {imb_ff[30:5],ic_wr_addr_bits_hi_3,imb_ff[1:0]}; // @[Cat.scala 29:58] wire _T_339 = ~sel_mb_addr; // @[ifu_mem_ctl.scala 240:37] @@ -1970,13 +1970,13 @@ module ifu_mem_ctl( wire [30:0] _T_341 = _T_339 ? io_ifc_fetch_addr_bf : 31'h0; // @[Mux.scala 27:72] wire [30:0] ifu_ic_rw_int_addr = _T_340 | _T_341; // @[Mux.scala 27:72] wire _T_346 = _T_334 & last_beat; // @[ifu_mem_ctl.scala 242:85] - wire _T_2681 = ~_T_2693; // @[ifu_mem_ctl.scala 554:84] - wire _T_2682 = _T_100 & _T_2681; // @[ifu_mem_ctl.scala 554:82] - wire bus_ifu_wr_en_ff_q = _T_2682 & write_ic_16_bytes; // @[ifu_mem_ctl.scala 554:108] + wire _T_2681 = ~_T_2693; // @[ifu_mem_ctl.scala 553:84] + wire _T_2682 = _T_100 & _T_2681; // @[ifu_mem_ctl.scala 553:82] + wire bus_ifu_wr_en_ff_q = _T_2682 & write_ic_16_bytes; // @[ifu_mem_ctl.scala 553:108] wire _T_347 = _T_346 & bus_ifu_wr_en_ff_q; // @[ifu_mem_ctl.scala 242:97] wire sel_mb_status_addr = _T_347 | reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 242:119] wire [30:0] ifu_status_wr_addr = sel_mb_status_addr ? _T_338 : ifu_fetch_addr_int_f; // @[ifu_mem_ctl.scala 243:31] - reg [63:0] ifu_bus_rdata_ff; // @[ifu_mem_ctl.scala 514:48] + reg [63:0] ifu_bus_rdata_ff; // @[ifu_mem_ctl.scala 513:48] wire [6:0] _T_570 = {ifu_bus_rdata_ff[63],ifu_bus_rdata_ff[62],ifu_bus_rdata_ff[61],ifu_bus_rdata_ff[60],ifu_bus_rdata_ff[59],ifu_bus_rdata_ff[58],ifu_bus_rdata_ff[57]}; // @[lib.scala 276:13] wire _T_571 = ^_T_570; // @[lib.scala 276:20] wire [6:0] _T_577 = {ifu_bus_rdata_ff[32],ifu_bus_rdata_ff[31],ifu_bus_rdata_ff[30],ifu_bus_rdata_ff[29],ifu_bus_rdata_ff[28],ifu_bus_rdata_ff[27],ifu_bus_rdata_ff[26]}; // @[lib.scala 276:30] @@ -2167,7 +2167,7 @@ module ifu_mem_ctl( wire _T_1200 = _T_1199 & ic_act_hit_f; // @[ifu_mem_ctl.scala 256:100] wire [4:0] bypass_index = imb_ff[4:0]; // @[ifu_mem_ctl.scala 328:28] wire _T_1404 = bypass_index[4:2] == 3'h0; // @[ifu_mem_ctl.scala 330:114] - wire bus_ifu_wr_en = _T_13 & miss_pending; // @[ifu_mem_ctl.scala 552:35] + wire bus_ifu_wr_en = _T_13 & miss_pending; // @[ifu_mem_ctl.scala 551:35] wire _T_1289 = io_ifu_axi_r_bits_id == 3'h0; // @[ifu_mem_ctl.scala 312:91] wire write_fill_data_0 = bus_ifu_wr_en & _T_1289; // @[ifu_mem_ctl.scala 312:73] wire _T_1330 = ~ic_act_miss_f; // @[ifu_mem_ctl.scala 319:118] @@ -2277,7 +2277,7 @@ module ifu_mem_ctl( wire _T_1517 = _T_1515 & _T_1516; // @[ifu_mem_ctl.scala 341:74] wire _T_1519 = _T_1517 & _T_319; // @[ifu_mem_ctl.scala 341:96] wire ic_crit_wd_rdy_new_in = _T_1514 | _T_1519; // @[ifu_mem_ctl.scala 340:143] - wire ic_crit_wd_rdy = ic_crit_wd_rdy_new_in | ic_crit_wd_rdy_new_ff; // @[ifu_mem_ctl.scala 562:43] + wire ic_crit_wd_rdy = ic_crit_wd_rdy_new_in | ic_crit_wd_rdy_new_ff; // @[ifu_mem_ctl.scala 561:43] wire _T_1252 = ic_crit_wd_rdy | _T_2268; // @[ifu_mem_ctl.scala 280:38] wire _T_1254 = _T_1252 | _T_2284; // @[ifu_mem_ctl.scala 280:64] wire _T_1255 = ~_T_1254; // @[ifu_mem_ctl.scala 280:21] @@ -2306,780 +2306,780 @@ module ifu_mem_ctl( wire _T_2492 = ifc_region_acc_fault_final_f | ifc_bus_acc_fault_f; // @[ifu_mem_ctl.scala 385:91] wire _T_2493 = ~_T_2492; // @[ifu_mem_ctl.scala 385:60] wire ic_rd_parity_final_err = _T_2491 & _T_2493; // @[ifu_mem_ctl.scala 385:58] - reg ic_debug_ict_array_sel_ff; // @[ifu_mem_ctl.scala 769:63] + reg ic_debug_ict_array_sel_ff; // @[ifu_mem_ctl.scala 768:63] reg ic_tag_valid_out_1_0; // @[Reg.scala 27:20] - wire _T_9374 = _T_4671 & ic_tag_valid_out_1_0; // @[ifu_mem_ctl.scala 697:10] + wire _T_9374 = _T_4671 & ic_tag_valid_out_1_0; // @[ifu_mem_ctl.scala 696:10] reg ic_tag_valid_out_1_1; // @[Reg.scala 27:20] - wire _T_9376 = _T_4672 & ic_tag_valid_out_1_1; // @[ifu_mem_ctl.scala 697:10] - wire _T_9629 = _T_9374 | _T_9376; // @[ifu_mem_ctl.scala 697:91] + wire _T_9376 = _T_4672 & ic_tag_valid_out_1_1; // @[ifu_mem_ctl.scala 696:10] + wire _T_9629 = _T_9374 | _T_9376; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_2; // @[Reg.scala 27:20] - wire _T_9378 = _T_4673 & ic_tag_valid_out_1_2; // @[ifu_mem_ctl.scala 697:10] - wire _T_9630 = _T_9629 | _T_9378; // @[ifu_mem_ctl.scala 697:91] + wire _T_9378 = _T_4673 & ic_tag_valid_out_1_2; // @[ifu_mem_ctl.scala 696:10] + wire _T_9630 = _T_9629 | _T_9378; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_3; // @[Reg.scala 27:20] - wire _T_9380 = _T_4674 & ic_tag_valid_out_1_3; // @[ifu_mem_ctl.scala 697:10] - wire _T_9631 = _T_9630 | _T_9380; // @[ifu_mem_ctl.scala 697:91] + wire _T_9380 = _T_4674 & ic_tag_valid_out_1_3; // @[ifu_mem_ctl.scala 696:10] + wire _T_9631 = _T_9630 | _T_9380; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_4; // @[Reg.scala 27:20] - wire _T_9382 = _T_4675 & ic_tag_valid_out_1_4; // @[ifu_mem_ctl.scala 697:10] - wire _T_9632 = _T_9631 | _T_9382; // @[ifu_mem_ctl.scala 697:91] + wire _T_9382 = _T_4675 & ic_tag_valid_out_1_4; // @[ifu_mem_ctl.scala 696:10] + wire _T_9632 = _T_9631 | _T_9382; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_5; // @[Reg.scala 27:20] - wire _T_9384 = _T_4676 & ic_tag_valid_out_1_5; // @[ifu_mem_ctl.scala 697:10] - wire _T_9633 = _T_9632 | _T_9384; // @[ifu_mem_ctl.scala 697:91] + wire _T_9384 = _T_4676 & ic_tag_valid_out_1_5; // @[ifu_mem_ctl.scala 696:10] + wire _T_9633 = _T_9632 | _T_9384; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_6; // @[Reg.scala 27:20] - wire _T_9386 = _T_4677 & ic_tag_valid_out_1_6; // @[ifu_mem_ctl.scala 697:10] - wire _T_9634 = _T_9633 | _T_9386; // @[ifu_mem_ctl.scala 697:91] + wire _T_9386 = _T_4677 & ic_tag_valid_out_1_6; // @[ifu_mem_ctl.scala 696:10] + wire _T_9634 = _T_9633 | _T_9386; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_7; // @[Reg.scala 27:20] - wire _T_9388 = _T_4678 & ic_tag_valid_out_1_7; // @[ifu_mem_ctl.scala 697:10] - wire _T_9635 = _T_9634 | _T_9388; // @[ifu_mem_ctl.scala 697:91] + wire _T_9388 = _T_4678 & ic_tag_valid_out_1_7; // @[ifu_mem_ctl.scala 696:10] + wire _T_9635 = _T_9634 | _T_9388; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_8; // @[Reg.scala 27:20] - wire _T_9390 = _T_4679 & ic_tag_valid_out_1_8; // @[ifu_mem_ctl.scala 697:10] - wire _T_9636 = _T_9635 | _T_9390; // @[ifu_mem_ctl.scala 697:91] + wire _T_9390 = _T_4679 & ic_tag_valid_out_1_8; // @[ifu_mem_ctl.scala 696:10] + wire _T_9636 = _T_9635 | _T_9390; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_9; // @[Reg.scala 27:20] - wire _T_9392 = _T_4680 & ic_tag_valid_out_1_9; // @[ifu_mem_ctl.scala 697:10] - wire _T_9637 = _T_9636 | _T_9392; // @[ifu_mem_ctl.scala 697:91] + wire _T_9392 = _T_4680 & ic_tag_valid_out_1_9; // @[ifu_mem_ctl.scala 696:10] + wire _T_9637 = _T_9636 | _T_9392; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_10; // @[Reg.scala 27:20] - wire _T_9394 = _T_4681 & ic_tag_valid_out_1_10; // @[ifu_mem_ctl.scala 697:10] - wire _T_9638 = _T_9637 | _T_9394; // @[ifu_mem_ctl.scala 697:91] + wire _T_9394 = _T_4681 & ic_tag_valid_out_1_10; // @[ifu_mem_ctl.scala 696:10] + wire _T_9638 = _T_9637 | _T_9394; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_11; // @[Reg.scala 27:20] - wire _T_9396 = _T_4682 & ic_tag_valid_out_1_11; // @[ifu_mem_ctl.scala 697:10] - wire _T_9639 = _T_9638 | _T_9396; // @[ifu_mem_ctl.scala 697:91] + wire _T_9396 = _T_4682 & ic_tag_valid_out_1_11; // @[ifu_mem_ctl.scala 696:10] + wire _T_9639 = _T_9638 | _T_9396; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_12; // @[Reg.scala 27:20] - wire _T_9398 = _T_4683 & ic_tag_valid_out_1_12; // @[ifu_mem_ctl.scala 697:10] - wire _T_9640 = _T_9639 | _T_9398; // @[ifu_mem_ctl.scala 697:91] + wire _T_9398 = _T_4683 & ic_tag_valid_out_1_12; // @[ifu_mem_ctl.scala 696:10] + wire _T_9640 = _T_9639 | _T_9398; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_13; // @[Reg.scala 27:20] - wire _T_9400 = _T_4684 & ic_tag_valid_out_1_13; // @[ifu_mem_ctl.scala 697:10] - wire _T_9641 = _T_9640 | _T_9400; // @[ifu_mem_ctl.scala 697:91] + wire _T_9400 = _T_4684 & ic_tag_valid_out_1_13; // @[ifu_mem_ctl.scala 696:10] + wire _T_9641 = _T_9640 | _T_9400; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_14; // @[Reg.scala 27:20] - wire _T_9402 = _T_4685 & ic_tag_valid_out_1_14; // @[ifu_mem_ctl.scala 697:10] - wire _T_9642 = _T_9641 | _T_9402; // @[ifu_mem_ctl.scala 697:91] + wire _T_9402 = _T_4685 & ic_tag_valid_out_1_14; // @[ifu_mem_ctl.scala 696:10] + wire _T_9642 = _T_9641 | _T_9402; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_15; // @[Reg.scala 27:20] - wire _T_9404 = _T_4686 & ic_tag_valid_out_1_15; // @[ifu_mem_ctl.scala 697:10] - wire _T_9643 = _T_9642 | _T_9404; // @[ifu_mem_ctl.scala 697:91] + wire _T_9404 = _T_4686 & ic_tag_valid_out_1_15; // @[ifu_mem_ctl.scala 696:10] + wire _T_9643 = _T_9642 | _T_9404; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_16; // @[Reg.scala 27:20] - wire _T_9406 = _T_4687 & ic_tag_valid_out_1_16; // @[ifu_mem_ctl.scala 697:10] - wire _T_9644 = _T_9643 | _T_9406; // @[ifu_mem_ctl.scala 697:91] + wire _T_9406 = _T_4687 & ic_tag_valid_out_1_16; // @[ifu_mem_ctl.scala 696:10] + wire _T_9644 = _T_9643 | _T_9406; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_17; // @[Reg.scala 27:20] - wire _T_9408 = _T_4688 & ic_tag_valid_out_1_17; // @[ifu_mem_ctl.scala 697:10] - wire _T_9645 = _T_9644 | _T_9408; // @[ifu_mem_ctl.scala 697:91] + wire _T_9408 = _T_4688 & ic_tag_valid_out_1_17; // @[ifu_mem_ctl.scala 696:10] + wire _T_9645 = _T_9644 | _T_9408; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_18; // @[Reg.scala 27:20] - wire _T_9410 = _T_4689 & ic_tag_valid_out_1_18; // @[ifu_mem_ctl.scala 697:10] - wire _T_9646 = _T_9645 | _T_9410; // @[ifu_mem_ctl.scala 697:91] + wire _T_9410 = _T_4689 & ic_tag_valid_out_1_18; // @[ifu_mem_ctl.scala 696:10] + wire _T_9646 = _T_9645 | _T_9410; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_19; // @[Reg.scala 27:20] - wire _T_9412 = _T_4690 & ic_tag_valid_out_1_19; // @[ifu_mem_ctl.scala 697:10] - wire _T_9647 = _T_9646 | _T_9412; // @[ifu_mem_ctl.scala 697:91] + wire _T_9412 = _T_4690 & ic_tag_valid_out_1_19; // @[ifu_mem_ctl.scala 696:10] + wire _T_9647 = _T_9646 | _T_9412; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_20; // @[Reg.scala 27:20] - wire _T_9414 = _T_4691 & ic_tag_valid_out_1_20; // @[ifu_mem_ctl.scala 697:10] - wire _T_9648 = _T_9647 | _T_9414; // @[ifu_mem_ctl.scala 697:91] + wire _T_9414 = _T_4691 & ic_tag_valid_out_1_20; // @[ifu_mem_ctl.scala 696:10] + wire _T_9648 = _T_9647 | _T_9414; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_21; // @[Reg.scala 27:20] - wire _T_9416 = _T_4692 & ic_tag_valid_out_1_21; // @[ifu_mem_ctl.scala 697:10] - wire _T_9649 = _T_9648 | _T_9416; // @[ifu_mem_ctl.scala 697:91] + wire _T_9416 = _T_4692 & ic_tag_valid_out_1_21; // @[ifu_mem_ctl.scala 696:10] + wire _T_9649 = _T_9648 | _T_9416; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_22; // @[Reg.scala 27:20] - wire _T_9418 = _T_4693 & ic_tag_valid_out_1_22; // @[ifu_mem_ctl.scala 697:10] - wire _T_9650 = _T_9649 | _T_9418; // @[ifu_mem_ctl.scala 697:91] + wire _T_9418 = _T_4693 & ic_tag_valid_out_1_22; // @[ifu_mem_ctl.scala 696:10] + wire _T_9650 = _T_9649 | _T_9418; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_23; // @[Reg.scala 27:20] - wire _T_9420 = _T_4694 & ic_tag_valid_out_1_23; // @[ifu_mem_ctl.scala 697:10] - wire _T_9651 = _T_9650 | _T_9420; // @[ifu_mem_ctl.scala 697:91] + wire _T_9420 = _T_4694 & ic_tag_valid_out_1_23; // @[ifu_mem_ctl.scala 696:10] + wire _T_9651 = _T_9650 | _T_9420; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_24; // @[Reg.scala 27:20] - wire _T_9422 = _T_4695 & ic_tag_valid_out_1_24; // @[ifu_mem_ctl.scala 697:10] - wire _T_9652 = _T_9651 | _T_9422; // @[ifu_mem_ctl.scala 697:91] + wire _T_9422 = _T_4695 & ic_tag_valid_out_1_24; // @[ifu_mem_ctl.scala 696:10] + wire _T_9652 = _T_9651 | _T_9422; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_25; // @[Reg.scala 27:20] - wire _T_9424 = _T_4696 & ic_tag_valid_out_1_25; // @[ifu_mem_ctl.scala 697:10] - wire _T_9653 = _T_9652 | _T_9424; // @[ifu_mem_ctl.scala 697:91] + wire _T_9424 = _T_4696 & ic_tag_valid_out_1_25; // @[ifu_mem_ctl.scala 696:10] + wire _T_9653 = _T_9652 | _T_9424; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_26; // @[Reg.scala 27:20] - wire _T_9426 = _T_4697 & ic_tag_valid_out_1_26; // @[ifu_mem_ctl.scala 697:10] - wire _T_9654 = _T_9653 | _T_9426; // @[ifu_mem_ctl.scala 697:91] + wire _T_9426 = _T_4697 & ic_tag_valid_out_1_26; // @[ifu_mem_ctl.scala 696:10] + wire _T_9654 = _T_9653 | _T_9426; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_27; // @[Reg.scala 27:20] - wire _T_9428 = _T_4698 & ic_tag_valid_out_1_27; // @[ifu_mem_ctl.scala 697:10] - wire _T_9655 = _T_9654 | _T_9428; // @[ifu_mem_ctl.scala 697:91] + wire _T_9428 = _T_4698 & ic_tag_valid_out_1_27; // @[ifu_mem_ctl.scala 696:10] + wire _T_9655 = _T_9654 | _T_9428; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_28; // @[Reg.scala 27:20] - wire _T_9430 = _T_4699 & ic_tag_valid_out_1_28; // @[ifu_mem_ctl.scala 697:10] - wire _T_9656 = _T_9655 | _T_9430; // @[ifu_mem_ctl.scala 697:91] + wire _T_9430 = _T_4699 & ic_tag_valid_out_1_28; // @[ifu_mem_ctl.scala 696:10] + wire _T_9656 = _T_9655 | _T_9430; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_29; // @[Reg.scala 27:20] - wire _T_9432 = _T_4700 & ic_tag_valid_out_1_29; // @[ifu_mem_ctl.scala 697:10] - wire _T_9657 = _T_9656 | _T_9432; // @[ifu_mem_ctl.scala 697:91] + wire _T_9432 = _T_4700 & ic_tag_valid_out_1_29; // @[ifu_mem_ctl.scala 696:10] + wire _T_9657 = _T_9656 | _T_9432; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_30; // @[Reg.scala 27:20] - wire _T_9434 = _T_4701 & ic_tag_valid_out_1_30; // @[ifu_mem_ctl.scala 697:10] - wire _T_9658 = _T_9657 | _T_9434; // @[ifu_mem_ctl.scala 697:91] + wire _T_9434 = _T_4701 & ic_tag_valid_out_1_30; // @[ifu_mem_ctl.scala 696:10] + wire _T_9658 = _T_9657 | _T_9434; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_31; // @[Reg.scala 27:20] - wire _T_9436 = _T_4702 & ic_tag_valid_out_1_31; // @[ifu_mem_ctl.scala 697:10] - wire _T_9659 = _T_9658 | _T_9436; // @[ifu_mem_ctl.scala 697:91] + wire _T_9436 = _T_4702 & ic_tag_valid_out_1_31; // @[ifu_mem_ctl.scala 696:10] + wire _T_9659 = _T_9658 | _T_9436; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_32; // @[Reg.scala 27:20] - wire _T_9438 = _T_4703 & ic_tag_valid_out_1_32; // @[ifu_mem_ctl.scala 697:10] - wire _T_9660 = _T_9659 | _T_9438; // @[ifu_mem_ctl.scala 697:91] + wire _T_9438 = _T_4703 & ic_tag_valid_out_1_32; // @[ifu_mem_ctl.scala 696:10] + wire _T_9660 = _T_9659 | _T_9438; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_33; // @[Reg.scala 27:20] - wire _T_9440 = _T_4704 & ic_tag_valid_out_1_33; // @[ifu_mem_ctl.scala 697:10] - wire _T_9661 = _T_9660 | _T_9440; // @[ifu_mem_ctl.scala 697:91] + wire _T_9440 = _T_4704 & ic_tag_valid_out_1_33; // @[ifu_mem_ctl.scala 696:10] + wire _T_9661 = _T_9660 | _T_9440; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_34; // @[Reg.scala 27:20] - wire _T_9442 = _T_4705 & ic_tag_valid_out_1_34; // @[ifu_mem_ctl.scala 697:10] - wire _T_9662 = _T_9661 | _T_9442; // @[ifu_mem_ctl.scala 697:91] + wire _T_9442 = _T_4705 & ic_tag_valid_out_1_34; // @[ifu_mem_ctl.scala 696:10] + wire _T_9662 = _T_9661 | _T_9442; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_35; // @[Reg.scala 27:20] - wire _T_9444 = _T_4706 & ic_tag_valid_out_1_35; // @[ifu_mem_ctl.scala 697:10] - wire _T_9663 = _T_9662 | _T_9444; // @[ifu_mem_ctl.scala 697:91] + wire _T_9444 = _T_4706 & ic_tag_valid_out_1_35; // @[ifu_mem_ctl.scala 696:10] + wire _T_9663 = _T_9662 | _T_9444; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_36; // @[Reg.scala 27:20] - wire _T_9446 = _T_4707 & ic_tag_valid_out_1_36; // @[ifu_mem_ctl.scala 697:10] - wire _T_9664 = _T_9663 | _T_9446; // @[ifu_mem_ctl.scala 697:91] + wire _T_9446 = _T_4707 & ic_tag_valid_out_1_36; // @[ifu_mem_ctl.scala 696:10] + wire _T_9664 = _T_9663 | _T_9446; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_37; // @[Reg.scala 27:20] - wire _T_9448 = _T_4708 & ic_tag_valid_out_1_37; // @[ifu_mem_ctl.scala 697:10] - wire _T_9665 = _T_9664 | _T_9448; // @[ifu_mem_ctl.scala 697:91] + wire _T_9448 = _T_4708 & ic_tag_valid_out_1_37; // @[ifu_mem_ctl.scala 696:10] + wire _T_9665 = _T_9664 | _T_9448; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_38; // @[Reg.scala 27:20] - wire _T_9450 = _T_4709 & ic_tag_valid_out_1_38; // @[ifu_mem_ctl.scala 697:10] - wire _T_9666 = _T_9665 | _T_9450; // @[ifu_mem_ctl.scala 697:91] + wire _T_9450 = _T_4709 & ic_tag_valid_out_1_38; // @[ifu_mem_ctl.scala 696:10] + wire _T_9666 = _T_9665 | _T_9450; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_39; // @[Reg.scala 27:20] - wire _T_9452 = _T_4710 & ic_tag_valid_out_1_39; // @[ifu_mem_ctl.scala 697:10] - wire _T_9667 = _T_9666 | _T_9452; // @[ifu_mem_ctl.scala 697:91] + wire _T_9452 = _T_4710 & ic_tag_valid_out_1_39; // @[ifu_mem_ctl.scala 696:10] + wire _T_9667 = _T_9666 | _T_9452; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_40; // @[Reg.scala 27:20] - wire _T_9454 = _T_4711 & ic_tag_valid_out_1_40; // @[ifu_mem_ctl.scala 697:10] - wire _T_9668 = _T_9667 | _T_9454; // @[ifu_mem_ctl.scala 697:91] + wire _T_9454 = _T_4711 & ic_tag_valid_out_1_40; // @[ifu_mem_ctl.scala 696:10] + wire _T_9668 = _T_9667 | _T_9454; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_41; // @[Reg.scala 27:20] - wire _T_9456 = _T_4712 & ic_tag_valid_out_1_41; // @[ifu_mem_ctl.scala 697:10] - wire _T_9669 = _T_9668 | _T_9456; // @[ifu_mem_ctl.scala 697:91] + wire _T_9456 = _T_4712 & ic_tag_valid_out_1_41; // @[ifu_mem_ctl.scala 696:10] + wire _T_9669 = _T_9668 | _T_9456; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_42; // @[Reg.scala 27:20] - wire _T_9458 = _T_4713 & ic_tag_valid_out_1_42; // @[ifu_mem_ctl.scala 697:10] - wire _T_9670 = _T_9669 | _T_9458; // @[ifu_mem_ctl.scala 697:91] + wire _T_9458 = _T_4713 & ic_tag_valid_out_1_42; // @[ifu_mem_ctl.scala 696:10] + wire _T_9670 = _T_9669 | _T_9458; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_43; // @[Reg.scala 27:20] - wire _T_9460 = _T_4714 & ic_tag_valid_out_1_43; // @[ifu_mem_ctl.scala 697:10] - wire _T_9671 = _T_9670 | _T_9460; // @[ifu_mem_ctl.scala 697:91] + wire _T_9460 = _T_4714 & ic_tag_valid_out_1_43; // @[ifu_mem_ctl.scala 696:10] + wire _T_9671 = _T_9670 | _T_9460; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_44; // @[Reg.scala 27:20] - wire _T_9462 = _T_4715 & ic_tag_valid_out_1_44; // @[ifu_mem_ctl.scala 697:10] - wire _T_9672 = _T_9671 | _T_9462; // @[ifu_mem_ctl.scala 697:91] + wire _T_9462 = _T_4715 & ic_tag_valid_out_1_44; // @[ifu_mem_ctl.scala 696:10] + wire _T_9672 = _T_9671 | _T_9462; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_45; // @[Reg.scala 27:20] - wire _T_9464 = _T_4716 & ic_tag_valid_out_1_45; // @[ifu_mem_ctl.scala 697:10] - wire _T_9673 = _T_9672 | _T_9464; // @[ifu_mem_ctl.scala 697:91] + wire _T_9464 = _T_4716 & ic_tag_valid_out_1_45; // @[ifu_mem_ctl.scala 696:10] + wire _T_9673 = _T_9672 | _T_9464; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_46; // @[Reg.scala 27:20] - wire _T_9466 = _T_4717 & ic_tag_valid_out_1_46; // @[ifu_mem_ctl.scala 697:10] - wire _T_9674 = _T_9673 | _T_9466; // @[ifu_mem_ctl.scala 697:91] + wire _T_9466 = _T_4717 & ic_tag_valid_out_1_46; // @[ifu_mem_ctl.scala 696:10] + wire _T_9674 = _T_9673 | _T_9466; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_47; // @[Reg.scala 27:20] - wire _T_9468 = _T_4718 & ic_tag_valid_out_1_47; // @[ifu_mem_ctl.scala 697:10] - wire _T_9675 = _T_9674 | _T_9468; // @[ifu_mem_ctl.scala 697:91] + wire _T_9468 = _T_4718 & ic_tag_valid_out_1_47; // @[ifu_mem_ctl.scala 696:10] + wire _T_9675 = _T_9674 | _T_9468; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_48; // @[Reg.scala 27:20] - wire _T_9470 = _T_4719 & ic_tag_valid_out_1_48; // @[ifu_mem_ctl.scala 697:10] - wire _T_9676 = _T_9675 | _T_9470; // @[ifu_mem_ctl.scala 697:91] + wire _T_9470 = _T_4719 & ic_tag_valid_out_1_48; // @[ifu_mem_ctl.scala 696:10] + wire _T_9676 = _T_9675 | _T_9470; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_49; // @[Reg.scala 27:20] - wire _T_9472 = _T_4720 & ic_tag_valid_out_1_49; // @[ifu_mem_ctl.scala 697:10] - wire _T_9677 = _T_9676 | _T_9472; // @[ifu_mem_ctl.scala 697:91] + wire _T_9472 = _T_4720 & ic_tag_valid_out_1_49; // @[ifu_mem_ctl.scala 696:10] + wire _T_9677 = _T_9676 | _T_9472; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_50; // @[Reg.scala 27:20] - wire _T_9474 = _T_4721 & ic_tag_valid_out_1_50; // @[ifu_mem_ctl.scala 697:10] - wire _T_9678 = _T_9677 | _T_9474; // @[ifu_mem_ctl.scala 697:91] + wire _T_9474 = _T_4721 & ic_tag_valid_out_1_50; // @[ifu_mem_ctl.scala 696:10] + wire _T_9678 = _T_9677 | _T_9474; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_51; // @[Reg.scala 27:20] - wire _T_9476 = _T_4722 & ic_tag_valid_out_1_51; // @[ifu_mem_ctl.scala 697:10] - wire _T_9679 = _T_9678 | _T_9476; // @[ifu_mem_ctl.scala 697:91] + wire _T_9476 = _T_4722 & ic_tag_valid_out_1_51; // @[ifu_mem_ctl.scala 696:10] + wire _T_9679 = _T_9678 | _T_9476; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_52; // @[Reg.scala 27:20] - wire _T_9478 = _T_4723 & ic_tag_valid_out_1_52; // @[ifu_mem_ctl.scala 697:10] - wire _T_9680 = _T_9679 | _T_9478; // @[ifu_mem_ctl.scala 697:91] + wire _T_9478 = _T_4723 & ic_tag_valid_out_1_52; // @[ifu_mem_ctl.scala 696:10] + wire _T_9680 = _T_9679 | _T_9478; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_53; // @[Reg.scala 27:20] - wire _T_9480 = _T_4724 & ic_tag_valid_out_1_53; // @[ifu_mem_ctl.scala 697:10] - wire _T_9681 = _T_9680 | _T_9480; // @[ifu_mem_ctl.scala 697:91] + wire _T_9480 = _T_4724 & ic_tag_valid_out_1_53; // @[ifu_mem_ctl.scala 696:10] + wire _T_9681 = _T_9680 | _T_9480; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_54; // @[Reg.scala 27:20] - wire _T_9482 = _T_4725 & ic_tag_valid_out_1_54; // @[ifu_mem_ctl.scala 697:10] - wire _T_9682 = _T_9681 | _T_9482; // @[ifu_mem_ctl.scala 697:91] + wire _T_9482 = _T_4725 & ic_tag_valid_out_1_54; // @[ifu_mem_ctl.scala 696:10] + wire _T_9682 = _T_9681 | _T_9482; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_55; // @[Reg.scala 27:20] - wire _T_9484 = _T_4726 & ic_tag_valid_out_1_55; // @[ifu_mem_ctl.scala 697:10] - wire _T_9683 = _T_9682 | _T_9484; // @[ifu_mem_ctl.scala 697:91] + wire _T_9484 = _T_4726 & ic_tag_valid_out_1_55; // @[ifu_mem_ctl.scala 696:10] + wire _T_9683 = _T_9682 | _T_9484; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_56; // @[Reg.scala 27:20] - wire _T_9486 = _T_4727 & ic_tag_valid_out_1_56; // @[ifu_mem_ctl.scala 697:10] - wire _T_9684 = _T_9683 | _T_9486; // @[ifu_mem_ctl.scala 697:91] + wire _T_9486 = _T_4727 & ic_tag_valid_out_1_56; // @[ifu_mem_ctl.scala 696:10] + wire _T_9684 = _T_9683 | _T_9486; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_57; // @[Reg.scala 27:20] - wire _T_9488 = _T_4728 & ic_tag_valid_out_1_57; // @[ifu_mem_ctl.scala 697:10] - wire _T_9685 = _T_9684 | _T_9488; // @[ifu_mem_ctl.scala 697:91] + wire _T_9488 = _T_4728 & ic_tag_valid_out_1_57; // @[ifu_mem_ctl.scala 696:10] + wire _T_9685 = _T_9684 | _T_9488; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_58; // @[Reg.scala 27:20] - wire _T_9490 = _T_4729 & ic_tag_valid_out_1_58; // @[ifu_mem_ctl.scala 697:10] - wire _T_9686 = _T_9685 | _T_9490; // @[ifu_mem_ctl.scala 697:91] + wire _T_9490 = _T_4729 & ic_tag_valid_out_1_58; // @[ifu_mem_ctl.scala 696:10] + wire _T_9686 = _T_9685 | _T_9490; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_59; // @[Reg.scala 27:20] - wire _T_9492 = _T_4730 & ic_tag_valid_out_1_59; // @[ifu_mem_ctl.scala 697:10] - wire _T_9687 = _T_9686 | _T_9492; // @[ifu_mem_ctl.scala 697:91] + wire _T_9492 = _T_4730 & ic_tag_valid_out_1_59; // @[ifu_mem_ctl.scala 696:10] + wire _T_9687 = _T_9686 | _T_9492; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_60; // @[Reg.scala 27:20] - wire _T_9494 = _T_4731 & ic_tag_valid_out_1_60; // @[ifu_mem_ctl.scala 697:10] - wire _T_9688 = _T_9687 | _T_9494; // @[ifu_mem_ctl.scala 697:91] + wire _T_9494 = _T_4731 & ic_tag_valid_out_1_60; // @[ifu_mem_ctl.scala 696:10] + wire _T_9688 = _T_9687 | _T_9494; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_61; // @[Reg.scala 27:20] - wire _T_9496 = _T_4732 & ic_tag_valid_out_1_61; // @[ifu_mem_ctl.scala 697:10] - wire _T_9689 = _T_9688 | _T_9496; // @[ifu_mem_ctl.scala 697:91] + wire _T_9496 = _T_4732 & ic_tag_valid_out_1_61; // @[ifu_mem_ctl.scala 696:10] + wire _T_9689 = _T_9688 | _T_9496; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_62; // @[Reg.scala 27:20] - wire _T_9498 = _T_4733 & ic_tag_valid_out_1_62; // @[ifu_mem_ctl.scala 697:10] - wire _T_9690 = _T_9689 | _T_9498; // @[ifu_mem_ctl.scala 697:91] + wire _T_9498 = _T_4733 & ic_tag_valid_out_1_62; // @[ifu_mem_ctl.scala 696:10] + wire _T_9690 = _T_9689 | _T_9498; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_63; // @[Reg.scala 27:20] - wire _T_9500 = _T_4734 & ic_tag_valid_out_1_63; // @[ifu_mem_ctl.scala 697:10] - wire _T_9691 = _T_9690 | _T_9500; // @[ifu_mem_ctl.scala 697:91] + wire _T_9500 = _T_4734 & ic_tag_valid_out_1_63; // @[ifu_mem_ctl.scala 696:10] + wire _T_9691 = _T_9690 | _T_9500; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_64; // @[Reg.scala 27:20] - wire _T_9502 = _T_4735 & ic_tag_valid_out_1_64; // @[ifu_mem_ctl.scala 697:10] - wire _T_9692 = _T_9691 | _T_9502; // @[ifu_mem_ctl.scala 697:91] + wire _T_9502 = _T_4735 & ic_tag_valid_out_1_64; // @[ifu_mem_ctl.scala 696:10] + wire _T_9692 = _T_9691 | _T_9502; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_65; // @[Reg.scala 27:20] - wire _T_9504 = _T_4736 & ic_tag_valid_out_1_65; // @[ifu_mem_ctl.scala 697:10] - wire _T_9693 = _T_9692 | _T_9504; // @[ifu_mem_ctl.scala 697:91] + wire _T_9504 = _T_4736 & ic_tag_valid_out_1_65; // @[ifu_mem_ctl.scala 696:10] + wire _T_9693 = _T_9692 | _T_9504; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_66; // @[Reg.scala 27:20] - wire _T_9506 = _T_4737 & ic_tag_valid_out_1_66; // @[ifu_mem_ctl.scala 697:10] - wire _T_9694 = _T_9693 | _T_9506; // @[ifu_mem_ctl.scala 697:91] + wire _T_9506 = _T_4737 & ic_tag_valid_out_1_66; // @[ifu_mem_ctl.scala 696:10] + wire _T_9694 = _T_9693 | _T_9506; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_67; // @[Reg.scala 27:20] - wire _T_9508 = _T_4738 & ic_tag_valid_out_1_67; // @[ifu_mem_ctl.scala 697:10] - wire _T_9695 = _T_9694 | _T_9508; // @[ifu_mem_ctl.scala 697:91] + wire _T_9508 = _T_4738 & ic_tag_valid_out_1_67; // @[ifu_mem_ctl.scala 696:10] + wire _T_9695 = _T_9694 | _T_9508; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_68; // @[Reg.scala 27:20] - wire _T_9510 = _T_4739 & ic_tag_valid_out_1_68; // @[ifu_mem_ctl.scala 697:10] - wire _T_9696 = _T_9695 | _T_9510; // @[ifu_mem_ctl.scala 697:91] + wire _T_9510 = _T_4739 & ic_tag_valid_out_1_68; // @[ifu_mem_ctl.scala 696:10] + wire _T_9696 = _T_9695 | _T_9510; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_69; // @[Reg.scala 27:20] - wire _T_9512 = _T_4740 & ic_tag_valid_out_1_69; // @[ifu_mem_ctl.scala 697:10] - wire _T_9697 = _T_9696 | _T_9512; // @[ifu_mem_ctl.scala 697:91] + wire _T_9512 = _T_4740 & ic_tag_valid_out_1_69; // @[ifu_mem_ctl.scala 696:10] + wire _T_9697 = _T_9696 | _T_9512; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_70; // @[Reg.scala 27:20] - wire _T_9514 = _T_4741 & ic_tag_valid_out_1_70; // @[ifu_mem_ctl.scala 697:10] - wire _T_9698 = _T_9697 | _T_9514; // @[ifu_mem_ctl.scala 697:91] + wire _T_9514 = _T_4741 & ic_tag_valid_out_1_70; // @[ifu_mem_ctl.scala 696:10] + wire _T_9698 = _T_9697 | _T_9514; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_71; // @[Reg.scala 27:20] - wire _T_9516 = _T_4742 & ic_tag_valid_out_1_71; // @[ifu_mem_ctl.scala 697:10] - wire _T_9699 = _T_9698 | _T_9516; // @[ifu_mem_ctl.scala 697:91] + wire _T_9516 = _T_4742 & ic_tag_valid_out_1_71; // @[ifu_mem_ctl.scala 696:10] + wire _T_9699 = _T_9698 | _T_9516; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_72; // @[Reg.scala 27:20] - wire _T_9518 = _T_4743 & ic_tag_valid_out_1_72; // @[ifu_mem_ctl.scala 697:10] - wire _T_9700 = _T_9699 | _T_9518; // @[ifu_mem_ctl.scala 697:91] + wire _T_9518 = _T_4743 & ic_tag_valid_out_1_72; // @[ifu_mem_ctl.scala 696:10] + wire _T_9700 = _T_9699 | _T_9518; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_73; // @[Reg.scala 27:20] - wire _T_9520 = _T_4744 & ic_tag_valid_out_1_73; // @[ifu_mem_ctl.scala 697:10] - wire _T_9701 = _T_9700 | _T_9520; // @[ifu_mem_ctl.scala 697:91] + wire _T_9520 = _T_4744 & ic_tag_valid_out_1_73; // @[ifu_mem_ctl.scala 696:10] + wire _T_9701 = _T_9700 | _T_9520; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_74; // @[Reg.scala 27:20] - wire _T_9522 = _T_4745 & ic_tag_valid_out_1_74; // @[ifu_mem_ctl.scala 697:10] - wire _T_9702 = _T_9701 | _T_9522; // @[ifu_mem_ctl.scala 697:91] + wire _T_9522 = _T_4745 & ic_tag_valid_out_1_74; // @[ifu_mem_ctl.scala 696:10] + wire _T_9702 = _T_9701 | _T_9522; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_75; // @[Reg.scala 27:20] - wire _T_9524 = _T_4746 & ic_tag_valid_out_1_75; // @[ifu_mem_ctl.scala 697:10] - wire _T_9703 = _T_9702 | _T_9524; // @[ifu_mem_ctl.scala 697:91] + wire _T_9524 = _T_4746 & ic_tag_valid_out_1_75; // @[ifu_mem_ctl.scala 696:10] + wire _T_9703 = _T_9702 | _T_9524; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_76; // @[Reg.scala 27:20] - wire _T_9526 = _T_4747 & ic_tag_valid_out_1_76; // @[ifu_mem_ctl.scala 697:10] - wire _T_9704 = _T_9703 | _T_9526; // @[ifu_mem_ctl.scala 697:91] + wire _T_9526 = _T_4747 & ic_tag_valid_out_1_76; // @[ifu_mem_ctl.scala 696:10] + wire _T_9704 = _T_9703 | _T_9526; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_77; // @[Reg.scala 27:20] - wire _T_9528 = _T_4748 & ic_tag_valid_out_1_77; // @[ifu_mem_ctl.scala 697:10] - wire _T_9705 = _T_9704 | _T_9528; // @[ifu_mem_ctl.scala 697:91] + wire _T_9528 = _T_4748 & ic_tag_valid_out_1_77; // @[ifu_mem_ctl.scala 696:10] + wire _T_9705 = _T_9704 | _T_9528; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_78; // @[Reg.scala 27:20] - wire _T_9530 = _T_4749 & ic_tag_valid_out_1_78; // @[ifu_mem_ctl.scala 697:10] - wire _T_9706 = _T_9705 | _T_9530; // @[ifu_mem_ctl.scala 697:91] + wire _T_9530 = _T_4749 & ic_tag_valid_out_1_78; // @[ifu_mem_ctl.scala 696:10] + wire _T_9706 = _T_9705 | _T_9530; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_79; // @[Reg.scala 27:20] - wire _T_9532 = _T_4750 & ic_tag_valid_out_1_79; // @[ifu_mem_ctl.scala 697:10] - wire _T_9707 = _T_9706 | _T_9532; // @[ifu_mem_ctl.scala 697:91] + wire _T_9532 = _T_4750 & ic_tag_valid_out_1_79; // @[ifu_mem_ctl.scala 696:10] + wire _T_9707 = _T_9706 | _T_9532; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_80; // @[Reg.scala 27:20] - wire _T_9534 = _T_4751 & ic_tag_valid_out_1_80; // @[ifu_mem_ctl.scala 697:10] - wire _T_9708 = _T_9707 | _T_9534; // @[ifu_mem_ctl.scala 697:91] + wire _T_9534 = _T_4751 & ic_tag_valid_out_1_80; // @[ifu_mem_ctl.scala 696:10] + wire _T_9708 = _T_9707 | _T_9534; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_81; // @[Reg.scala 27:20] - wire _T_9536 = _T_4752 & ic_tag_valid_out_1_81; // @[ifu_mem_ctl.scala 697:10] - wire _T_9709 = _T_9708 | _T_9536; // @[ifu_mem_ctl.scala 697:91] + wire _T_9536 = _T_4752 & ic_tag_valid_out_1_81; // @[ifu_mem_ctl.scala 696:10] + wire _T_9709 = _T_9708 | _T_9536; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_82; // @[Reg.scala 27:20] - wire _T_9538 = _T_4753 & ic_tag_valid_out_1_82; // @[ifu_mem_ctl.scala 697:10] - wire _T_9710 = _T_9709 | _T_9538; // @[ifu_mem_ctl.scala 697:91] + wire _T_9538 = _T_4753 & ic_tag_valid_out_1_82; // @[ifu_mem_ctl.scala 696:10] + wire _T_9710 = _T_9709 | _T_9538; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_83; // @[Reg.scala 27:20] - wire _T_9540 = _T_4754 & ic_tag_valid_out_1_83; // @[ifu_mem_ctl.scala 697:10] - wire _T_9711 = _T_9710 | _T_9540; // @[ifu_mem_ctl.scala 697:91] + wire _T_9540 = _T_4754 & ic_tag_valid_out_1_83; // @[ifu_mem_ctl.scala 696:10] + wire _T_9711 = _T_9710 | _T_9540; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_84; // @[Reg.scala 27:20] - wire _T_9542 = _T_4755 & ic_tag_valid_out_1_84; // @[ifu_mem_ctl.scala 697:10] - wire _T_9712 = _T_9711 | _T_9542; // @[ifu_mem_ctl.scala 697:91] + wire _T_9542 = _T_4755 & ic_tag_valid_out_1_84; // @[ifu_mem_ctl.scala 696:10] + wire _T_9712 = _T_9711 | _T_9542; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_85; // @[Reg.scala 27:20] - wire _T_9544 = _T_4756 & ic_tag_valid_out_1_85; // @[ifu_mem_ctl.scala 697:10] - wire _T_9713 = _T_9712 | _T_9544; // @[ifu_mem_ctl.scala 697:91] + wire _T_9544 = _T_4756 & ic_tag_valid_out_1_85; // @[ifu_mem_ctl.scala 696:10] + wire _T_9713 = _T_9712 | _T_9544; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_86; // @[Reg.scala 27:20] - wire _T_9546 = _T_4757 & ic_tag_valid_out_1_86; // @[ifu_mem_ctl.scala 697:10] - wire _T_9714 = _T_9713 | _T_9546; // @[ifu_mem_ctl.scala 697:91] + wire _T_9546 = _T_4757 & ic_tag_valid_out_1_86; // @[ifu_mem_ctl.scala 696:10] + wire _T_9714 = _T_9713 | _T_9546; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_87; // @[Reg.scala 27:20] - wire _T_9548 = _T_4758 & ic_tag_valid_out_1_87; // @[ifu_mem_ctl.scala 697:10] - wire _T_9715 = _T_9714 | _T_9548; // @[ifu_mem_ctl.scala 697:91] + wire _T_9548 = _T_4758 & ic_tag_valid_out_1_87; // @[ifu_mem_ctl.scala 696:10] + wire _T_9715 = _T_9714 | _T_9548; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_88; // @[Reg.scala 27:20] - wire _T_9550 = _T_4759 & ic_tag_valid_out_1_88; // @[ifu_mem_ctl.scala 697:10] - wire _T_9716 = _T_9715 | _T_9550; // @[ifu_mem_ctl.scala 697:91] + wire _T_9550 = _T_4759 & ic_tag_valid_out_1_88; // @[ifu_mem_ctl.scala 696:10] + wire _T_9716 = _T_9715 | _T_9550; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_89; // @[Reg.scala 27:20] - wire _T_9552 = _T_4760 & ic_tag_valid_out_1_89; // @[ifu_mem_ctl.scala 697:10] - wire _T_9717 = _T_9716 | _T_9552; // @[ifu_mem_ctl.scala 697:91] + wire _T_9552 = _T_4760 & ic_tag_valid_out_1_89; // @[ifu_mem_ctl.scala 696:10] + wire _T_9717 = _T_9716 | _T_9552; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_90; // @[Reg.scala 27:20] - wire _T_9554 = _T_4761 & ic_tag_valid_out_1_90; // @[ifu_mem_ctl.scala 697:10] - wire _T_9718 = _T_9717 | _T_9554; // @[ifu_mem_ctl.scala 697:91] + wire _T_9554 = _T_4761 & ic_tag_valid_out_1_90; // @[ifu_mem_ctl.scala 696:10] + wire _T_9718 = _T_9717 | _T_9554; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_91; // @[Reg.scala 27:20] - wire _T_9556 = _T_4762 & ic_tag_valid_out_1_91; // @[ifu_mem_ctl.scala 697:10] - wire _T_9719 = _T_9718 | _T_9556; // @[ifu_mem_ctl.scala 697:91] + wire _T_9556 = _T_4762 & ic_tag_valid_out_1_91; // @[ifu_mem_ctl.scala 696:10] + wire _T_9719 = _T_9718 | _T_9556; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_92; // @[Reg.scala 27:20] - wire _T_9558 = _T_4763 & ic_tag_valid_out_1_92; // @[ifu_mem_ctl.scala 697:10] - wire _T_9720 = _T_9719 | _T_9558; // @[ifu_mem_ctl.scala 697:91] + wire _T_9558 = _T_4763 & ic_tag_valid_out_1_92; // @[ifu_mem_ctl.scala 696:10] + wire _T_9720 = _T_9719 | _T_9558; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_93; // @[Reg.scala 27:20] - wire _T_9560 = _T_4764 & ic_tag_valid_out_1_93; // @[ifu_mem_ctl.scala 697:10] - wire _T_9721 = _T_9720 | _T_9560; // @[ifu_mem_ctl.scala 697:91] + wire _T_9560 = _T_4764 & ic_tag_valid_out_1_93; // @[ifu_mem_ctl.scala 696:10] + wire _T_9721 = _T_9720 | _T_9560; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_94; // @[Reg.scala 27:20] - wire _T_9562 = _T_4765 & ic_tag_valid_out_1_94; // @[ifu_mem_ctl.scala 697:10] - wire _T_9722 = _T_9721 | _T_9562; // @[ifu_mem_ctl.scala 697:91] + wire _T_9562 = _T_4765 & ic_tag_valid_out_1_94; // @[ifu_mem_ctl.scala 696:10] + wire _T_9722 = _T_9721 | _T_9562; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_95; // @[Reg.scala 27:20] - wire _T_9564 = _T_4766 & ic_tag_valid_out_1_95; // @[ifu_mem_ctl.scala 697:10] - wire _T_9723 = _T_9722 | _T_9564; // @[ifu_mem_ctl.scala 697:91] + wire _T_9564 = _T_4766 & ic_tag_valid_out_1_95; // @[ifu_mem_ctl.scala 696:10] + wire _T_9723 = _T_9722 | _T_9564; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_96; // @[Reg.scala 27:20] - wire _T_9566 = _T_4767 & ic_tag_valid_out_1_96; // @[ifu_mem_ctl.scala 697:10] - wire _T_9724 = _T_9723 | _T_9566; // @[ifu_mem_ctl.scala 697:91] + wire _T_9566 = _T_4767 & ic_tag_valid_out_1_96; // @[ifu_mem_ctl.scala 696:10] + wire _T_9724 = _T_9723 | _T_9566; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_97; // @[Reg.scala 27:20] - wire _T_9568 = _T_4768 & ic_tag_valid_out_1_97; // @[ifu_mem_ctl.scala 697:10] - wire _T_9725 = _T_9724 | _T_9568; // @[ifu_mem_ctl.scala 697:91] + wire _T_9568 = _T_4768 & ic_tag_valid_out_1_97; // @[ifu_mem_ctl.scala 696:10] + wire _T_9725 = _T_9724 | _T_9568; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_98; // @[Reg.scala 27:20] - wire _T_9570 = _T_4769 & ic_tag_valid_out_1_98; // @[ifu_mem_ctl.scala 697:10] - wire _T_9726 = _T_9725 | _T_9570; // @[ifu_mem_ctl.scala 697:91] + wire _T_9570 = _T_4769 & ic_tag_valid_out_1_98; // @[ifu_mem_ctl.scala 696:10] + wire _T_9726 = _T_9725 | _T_9570; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_99; // @[Reg.scala 27:20] - wire _T_9572 = _T_4770 & ic_tag_valid_out_1_99; // @[ifu_mem_ctl.scala 697:10] - wire _T_9727 = _T_9726 | _T_9572; // @[ifu_mem_ctl.scala 697:91] + wire _T_9572 = _T_4770 & ic_tag_valid_out_1_99; // @[ifu_mem_ctl.scala 696:10] + wire _T_9727 = _T_9726 | _T_9572; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_100; // @[Reg.scala 27:20] - wire _T_9574 = _T_4771 & ic_tag_valid_out_1_100; // @[ifu_mem_ctl.scala 697:10] - wire _T_9728 = _T_9727 | _T_9574; // @[ifu_mem_ctl.scala 697:91] + wire _T_9574 = _T_4771 & ic_tag_valid_out_1_100; // @[ifu_mem_ctl.scala 696:10] + wire _T_9728 = _T_9727 | _T_9574; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_101; // @[Reg.scala 27:20] - wire _T_9576 = _T_4772 & ic_tag_valid_out_1_101; // @[ifu_mem_ctl.scala 697:10] - wire _T_9729 = _T_9728 | _T_9576; // @[ifu_mem_ctl.scala 697:91] + wire _T_9576 = _T_4772 & ic_tag_valid_out_1_101; // @[ifu_mem_ctl.scala 696:10] + wire _T_9729 = _T_9728 | _T_9576; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_102; // @[Reg.scala 27:20] - wire _T_9578 = _T_4773 & ic_tag_valid_out_1_102; // @[ifu_mem_ctl.scala 697:10] - wire _T_9730 = _T_9729 | _T_9578; // @[ifu_mem_ctl.scala 697:91] + wire _T_9578 = _T_4773 & ic_tag_valid_out_1_102; // @[ifu_mem_ctl.scala 696:10] + wire _T_9730 = _T_9729 | _T_9578; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_103; // @[Reg.scala 27:20] - wire _T_9580 = _T_4774 & ic_tag_valid_out_1_103; // @[ifu_mem_ctl.scala 697:10] - wire _T_9731 = _T_9730 | _T_9580; // @[ifu_mem_ctl.scala 697:91] + wire _T_9580 = _T_4774 & ic_tag_valid_out_1_103; // @[ifu_mem_ctl.scala 696:10] + wire _T_9731 = _T_9730 | _T_9580; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_104; // @[Reg.scala 27:20] - wire _T_9582 = _T_4775 & ic_tag_valid_out_1_104; // @[ifu_mem_ctl.scala 697:10] - wire _T_9732 = _T_9731 | _T_9582; // @[ifu_mem_ctl.scala 697:91] + wire _T_9582 = _T_4775 & ic_tag_valid_out_1_104; // @[ifu_mem_ctl.scala 696:10] + wire _T_9732 = _T_9731 | _T_9582; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_105; // @[Reg.scala 27:20] - wire _T_9584 = _T_4776 & ic_tag_valid_out_1_105; // @[ifu_mem_ctl.scala 697:10] - wire _T_9733 = _T_9732 | _T_9584; // @[ifu_mem_ctl.scala 697:91] + wire _T_9584 = _T_4776 & ic_tag_valid_out_1_105; // @[ifu_mem_ctl.scala 696:10] + wire _T_9733 = _T_9732 | _T_9584; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_106; // @[Reg.scala 27:20] - wire _T_9586 = _T_4777 & ic_tag_valid_out_1_106; // @[ifu_mem_ctl.scala 697:10] - wire _T_9734 = _T_9733 | _T_9586; // @[ifu_mem_ctl.scala 697:91] + wire _T_9586 = _T_4777 & ic_tag_valid_out_1_106; // @[ifu_mem_ctl.scala 696:10] + wire _T_9734 = _T_9733 | _T_9586; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_107; // @[Reg.scala 27:20] - wire _T_9588 = _T_4778 & ic_tag_valid_out_1_107; // @[ifu_mem_ctl.scala 697:10] - wire _T_9735 = _T_9734 | _T_9588; // @[ifu_mem_ctl.scala 697:91] + wire _T_9588 = _T_4778 & ic_tag_valid_out_1_107; // @[ifu_mem_ctl.scala 696:10] + wire _T_9735 = _T_9734 | _T_9588; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_108; // @[Reg.scala 27:20] - wire _T_9590 = _T_4779 & ic_tag_valid_out_1_108; // @[ifu_mem_ctl.scala 697:10] - wire _T_9736 = _T_9735 | _T_9590; // @[ifu_mem_ctl.scala 697:91] + wire _T_9590 = _T_4779 & ic_tag_valid_out_1_108; // @[ifu_mem_ctl.scala 696:10] + wire _T_9736 = _T_9735 | _T_9590; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_109; // @[Reg.scala 27:20] - wire _T_9592 = _T_4780 & ic_tag_valid_out_1_109; // @[ifu_mem_ctl.scala 697:10] - wire _T_9737 = _T_9736 | _T_9592; // @[ifu_mem_ctl.scala 697:91] + wire _T_9592 = _T_4780 & ic_tag_valid_out_1_109; // @[ifu_mem_ctl.scala 696:10] + wire _T_9737 = _T_9736 | _T_9592; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_110; // @[Reg.scala 27:20] - wire _T_9594 = _T_4781 & ic_tag_valid_out_1_110; // @[ifu_mem_ctl.scala 697:10] - wire _T_9738 = _T_9737 | _T_9594; // @[ifu_mem_ctl.scala 697:91] + wire _T_9594 = _T_4781 & ic_tag_valid_out_1_110; // @[ifu_mem_ctl.scala 696:10] + wire _T_9738 = _T_9737 | _T_9594; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_111; // @[Reg.scala 27:20] - wire _T_9596 = _T_4782 & ic_tag_valid_out_1_111; // @[ifu_mem_ctl.scala 697:10] - wire _T_9739 = _T_9738 | _T_9596; // @[ifu_mem_ctl.scala 697:91] + wire _T_9596 = _T_4782 & ic_tag_valid_out_1_111; // @[ifu_mem_ctl.scala 696:10] + wire _T_9739 = _T_9738 | _T_9596; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_112; // @[Reg.scala 27:20] - wire _T_9598 = _T_4783 & ic_tag_valid_out_1_112; // @[ifu_mem_ctl.scala 697:10] - wire _T_9740 = _T_9739 | _T_9598; // @[ifu_mem_ctl.scala 697:91] + wire _T_9598 = _T_4783 & ic_tag_valid_out_1_112; // @[ifu_mem_ctl.scala 696:10] + wire _T_9740 = _T_9739 | _T_9598; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_113; // @[Reg.scala 27:20] - wire _T_9600 = _T_4784 & ic_tag_valid_out_1_113; // @[ifu_mem_ctl.scala 697:10] - wire _T_9741 = _T_9740 | _T_9600; // @[ifu_mem_ctl.scala 697:91] + wire _T_9600 = _T_4784 & ic_tag_valid_out_1_113; // @[ifu_mem_ctl.scala 696:10] + wire _T_9741 = _T_9740 | _T_9600; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_114; // @[Reg.scala 27:20] - wire _T_9602 = _T_4785 & ic_tag_valid_out_1_114; // @[ifu_mem_ctl.scala 697:10] - wire _T_9742 = _T_9741 | _T_9602; // @[ifu_mem_ctl.scala 697:91] + wire _T_9602 = _T_4785 & ic_tag_valid_out_1_114; // @[ifu_mem_ctl.scala 696:10] + wire _T_9742 = _T_9741 | _T_9602; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_115; // @[Reg.scala 27:20] - wire _T_9604 = _T_4786 & ic_tag_valid_out_1_115; // @[ifu_mem_ctl.scala 697:10] - wire _T_9743 = _T_9742 | _T_9604; // @[ifu_mem_ctl.scala 697:91] + wire _T_9604 = _T_4786 & ic_tag_valid_out_1_115; // @[ifu_mem_ctl.scala 696:10] + wire _T_9743 = _T_9742 | _T_9604; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_116; // @[Reg.scala 27:20] - wire _T_9606 = _T_4787 & ic_tag_valid_out_1_116; // @[ifu_mem_ctl.scala 697:10] - wire _T_9744 = _T_9743 | _T_9606; // @[ifu_mem_ctl.scala 697:91] + wire _T_9606 = _T_4787 & ic_tag_valid_out_1_116; // @[ifu_mem_ctl.scala 696:10] + wire _T_9744 = _T_9743 | _T_9606; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_117; // @[Reg.scala 27:20] - wire _T_9608 = _T_4788 & ic_tag_valid_out_1_117; // @[ifu_mem_ctl.scala 697:10] - wire _T_9745 = _T_9744 | _T_9608; // @[ifu_mem_ctl.scala 697:91] + wire _T_9608 = _T_4788 & ic_tag_valid_out_1_117; // @[ifu_mem_ctl.scala 696:10] + wire _T_9745 = _T_9744 | _T_9608; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_118; // @[Reg.scala 27:20] - wire _T_9610 = _T_4789 & ic_tag_valid_out_1_118; // @[ifu_mem_ctl.scala 697:10] - wire _T_9746 = _T_9745 | _T_9610; // @[ifu_mem_ctl.scala 697:91] + wire _T_9610 = _T_4789 & ic_tag_valid_out_1_118; // @[ifu_mem_ctl.scala 696:10] + wire _T_9746 = _T_9745 | _T_9610; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_119; // @[Reg.scala 27:20] - wire _T_9612 = _T_4790 & ic_tag_valid_out_1_119; // @[ifu_mem_ctl.scala 697:10] - wire _T_9747 = _T_9746 | _T_9612; // @[ifu_mem_ctl.scala 697:91] + wire _T_9612 = _T_4790 & ic_tag_valid_out_1_119; // @[ifu_mem_ctl.scala 696:10] + wire _T_9747 = _T_9746 | _T_9612; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_120; // @[Reg.scala 27:20] - wire _T_9614 = _T_4791 & ic_tag_valid_out_1_120; // @[ifu_mem_ctl.scala 697:10] - wire _T_9748 = _T_9747 | _T_9614; // @[ifu_mem_ctl.scala 697:91] + wire _T_9614 = _T_4791 & ic_tag_valid_out_1_120; // @[ifu_mem_ctl.scala 696:10] + wire _T_9748 = _T_9747 | _T_9614; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_121; // @[Reg.scala 27:20] - wire _T_9616 = _T_4792 & ic_tag_valid_out_1_121; // @[ifu_mem_ctl.scala 697:10] - wire _T_9749 = _T_9748 | _T_9616; // @[ifu_mem_ctl.scala 697:91] + wire _T_9616 = _T_4792 & ic_tag_valid_out_1_121; // @[ifu_mem_ctl.scala 696:10] + wire _T_9749 = _T_9748 | _T_9616; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_122; // @[Reg.scala 27:20] - wire _T_9618 = _T_4793 & ic_tag_valid_out_1_122; // @[ifu_mem_ctl.scala 697:10] - wire _T_9750 = _T_9749 | _T_9618; // @[ifu_mem_ctl.scala 697:91] + wire _T_9618 = _T_4793 & ic_tag_valid_out_1_122; // @[ifu_mem_ctl.scala 696:10] + wire _T_9750 = _T_9749 | _T_9618; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_123; // @[Reg.scala 27:20] - wire _T_9620 = _T_4794 & ic_tag_valid_out_1_123; // @[ifu_mem_ctl.scala 697:10] - wire _T_9751 = _T_9750 | _T_9620; // @[ifu_mem_ctl.scala 697:91] + wire _T_9620 = _T_4794 & ic_tag_valid_out_1_123; // @[ifu_mem_ctl.scala 696:10] + wire _T_9751 = _T_9750 | _T_9620; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_124; // @[Reg.scala 27:20] - wire _T_9622 = _T_4795 & ic_tag_valid_out_1_124; // @[ifu_mem_ctl.scala 697:10] - wire _T_9752 = _T_9751 | _T_9622; // @[ifu_mem_ctl.scala 697:91] + wire _T_9622 = _T_4795 & ic_tag_valid_out_1_124; // @[ifu_mem_ctl.scala 696:10] + wire _T_9752 = _T_9751 | _T_9622; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_125; // @[Reg.scala 27:20] - wire _T_9624 = _T_4796 & ic_tag_valid_out_1_125; // @[ifu_mem_ctl.scala 697:10] - wire _T_9753 = _T_9752 | _T_9624; // @[ifu_mem_ctl.scala 697:91] + wire _T_9624 = _T_4796 & ic_tag_valid_out_1_125; // @[ifu_mem_ctl.scala 696:10] + wire _T_9753 = _T_9752 | _T_9624; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_126; // @[Reg.scala 27:20] - wire _T_9626 = _T_4797 & ic_tag_valid_out_1_126; // @[ifu_mem_ctl.scala 697:10] - wire _T_9754 = _T_9753 | _T_9626; // @[ifu_mem_ctl.scala 697:91] + wire _T_9626 = _T_4797 & ic_tag_valid_out_1_126; // @[ifu_mem_ctl.scala 696:10] + wire _T_9754 = _T_9753 | _T_9626; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_1_127; // @[Reg.scala 27:20] - wire _T_9628 = _T_4798 & ic_tag_valid_out_1_127; // @[ifu_mem_ctl.scala 697:10] - wire _T_9755 = _T_9754 | _T_9628; // @[ifu_mem_ctl.scala 697:91] + wire _T_9628 = _T_4798 & ic_tag_valid_out_1_127; // @[ifu_mem_ctl.scala 696:10] + wire _T_9755 = _T_9754 | _T_9628; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_0; // @[Reg.scala 27:20] - wire _T_8991 = _T_4671 & ic_tag_valid_out_0_0; // @[ifu_mem_ctl.scala 697:10] + wire _T_8991 = _T_4671 & ic_tag_valid_out_0_0; // @[ifu_mem_ctl.scala 696:10] reg ic_tag_valid_out_0_1; // @[Reg.scala 27:20] - wire _T_8993 = _T_4672 & ic_tag_valid_out_0_1; // @[ifu_mem_ctl.scala 697:10] - wire _T_9246 = _T_8991 | _T_8993; // @[ifu_mem_ctl.scala 697:91] + wire _T_8993 = _T_4672 & ic_tag_valid_out_0_1; // @[ifu_mem_ctl.scala 696:10] + wire _T_9246 = _T_8991 | _T_8993; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_2; // @[Reg.scala 27:20] - wire _T_8995 = _T_4673 & ic_tag_valid_out_0_2; // @[ifu_mem_ctl.scala 697:10] - wire _T_9247 = _T_9246 | _T_8995; // @[ifu_mem_ctl.scala 697:91] + wire _T_8995 = _T_4673 & ic_tag_valid_out_0_2; // @[ifu_mem_ctl.scala 696:10] + wire _T_9247 = _T_9246 | _T_8995; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_3; // @[Reg.scala 27:20] - wire _T_8997 = _T_4674 & ic_tag_valid_out_0_3; // @[ifu_mem_ctl.scala 697:10] - wire _T_9248 = _T_9247 | _T_8997; // @[ifu_mem_ctl.scala 697:91] + wire _T_8997 = _T_4674 & ic_tag_valid_out_0_3; // @[ifu_mem_ctl.scala 696:10] + wire _T_9248 = _T_9247 | _T_8997; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_4; // @[Reg.scala 27:20] - wire _T_8999 = _T_4675 & ic_tag_valid_out_0_4; // @[ifu_mem_ctl.scala 697:10] - wire _T_9249 = _T_9248 | _T_8999; // @[ifu_mem_ctl.scala 697:91] + wire _T_8999 = _T_4675 & ic_tag_valid_out_0_4; // @[ifu_mem_ctl.scala 696:10] + wire _T_9249 = _T_9248 | _T_8999; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_5; // @[Reg.scala 27:20] - wire _T_9001 = _T_4676 & ic_tag_valid_out_0_5; // @[ifu_mem_ctl.scala 697:10] - wire _T_9250 = _T_9249 | _T_9001; // @[ifu_mem_ctl.scala 697:91] + wire _T_9001 = _T_4676 & ic_tag_valid_out_0_5; // @[ifu_mem_ctl.scala 696:10] + wire _T_9250 = _T_9249 | _T_9001; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_6; // @[Reg.scala 27:20] - wire _T_9003 = _T_4677 & ic_tag_valid_out_0_6; // @[ifu_mem_ctl.scala 697:10] - wire _T_9251 = _T_9250 | _T_9003; // @[ifu_mem_ctl.scala 697:91] + wire _T_9003 = _T_4677 & ic_tag_valid_out_0_6; // @[ifu_mem_ctl.scala 696:10] + wire _T_9251 = _T_9250 | _T_9003; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_7; // @[Reg.scala 27:20] - wire _T_9005 = _T_4678 & ic_tag_valid_out_0_7; // @[ifu_mem_ctl.scala 697:10] - wire _T_9252 = _T_9251 | _T_9005; // @[ifu_mem_ctl.scala 697:91] + wire _T_9005 = _T_4678 & ic_tag_valid_out_0_7; // @[ifu_mem_ctl.scala 696:10] + wire _T_9252 = _T_9251 | _T_9005; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_8; // @[Reg.scala 27:20] - wire _T_9007 = _T_4679 & ic_tag_valid_out_0_8; // @[ifu_mem_ctl.scala 697:10] - wire _T_9253 = _T_9252 | _T_9007; // @[ifu_mem_ctl.scala 697:91] + wire _T_9007 = _T_4679 & ic_tag_valid_out_0_8; // @[ifu_mem_ctl.scala 696:10] + wire _T_9253 = _T_9252 | _T_9007; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_9; // @[Reg.scala 27:20] - wire _T_9009 = _T_4680 & ic_tag_valid_out_0_9; // @[ifu_mem_ctl.scala 697:10] - wire _T_9254 = _T_9253 | _T_9009; // @[ifu_mem_ctl.scala 697:91] + wire _T_9009 = _T_4680 & ic_tag_valid_out_0_9; // @[ifu_mem_ctl.scala 696:10] + wire _T_9254 = _T_9253 | _T_9009; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_10; // @[Reg.scala 27:20] - wire _T_9011 = _T_4681 & ic_tag_valid_out_0_10; // @[ifu_mem_ctl.scala 697:10] - wire _T_9255 = _T_9254 | _T_9011; // @[ifu_mem_ctl.scala 697:91] + wire _T_9011 = _T_4681 & ic_tag_valid_out_0_10; // @[ifu_mem_ctl.scala 696:10] + wire _T_9255 = _T_9254 | _T_9011; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_11; // @[Reg.scala 27:20] - wire _T_9013 = _T_4682 & ic_tag_valid_out_0_11; // @[ifu_mem_ctl.scala 697:10] - wire _T_9256 = _T_9255 | _T_9013; // @[ifu_mem_ctl.scala 697:91] + wire _T_9013 = _T_4682 & ic_tag_valid_out_0_11; // @[ifu_mem_ctl.scala 696:10] + wire _T_9256 = _T_9255 | _T_9013; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_12; // @[Reg.scala 27:20] - wire _T_9015 = _T_4683 & ic_tag_valid_out_0_12; // @[ifu_mem_ctl.scala 697:10] - wire _T_9257 = _T_9256 | _T_9015; // @[ifu_mem_ctl.scala 697:91] + wire _T_9015 = _T_4683 & ic_tag_valid_out_0_12; // @[ifu_mem_ctl.scala 696:10] + wire _T_9257 = _T_9256 | _T_9015; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_13; // @[Reg.scala 27:20] - wire _T_9017 = _T_4684 & ic_tag_valid_out_0_13; // @[ifu_mem_ctl.scala 697:10] - wire _T_9258 = _T_9257 | _T_9017; // @[ifu_mem_ctl.scala 697:91] + wire _T_9017 = _T_4684 & ic_tag_valid_out_0_13; // @[ifu_mem_ctl.scala 696:10] + wire _T_9258 = _T_9257 | _T_9017; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_14; // @[Reg.scala 27:20] - wire _T_9019 = _T_4685 & ic_tag_valid_out_0_14; // @[ifu_mem_ctl.scala 697:10] - wire _T_9259 = _T_9258 | _T_9019; // @[ifu_mem_ctl.scala 697:91] + wire _T_9019 = _T_4685 & ic_tag_valid_out_0_14; // @[ifu_mem_ctl.scala 696:10] + wire _T_9259 = _T_9258 | _T_9019; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_15; // @[Reg.scala 27:20] - wire _T_9021 = _T_4686 & ic_tag_valid_out_0_15; // @[ifu_mem_ctl.scala 697:10] - wire _T_9260 = _T_9259 | _T_9021; // @[ifu_mem_ctl.scala 697:91] + wire _T_9021 = _T_4686 & ic_tag_valid_out_0_15; // @[ifu_mem_ctl.scala 696:10] + wire _T_9260 = _T_9259 | _T_9021; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_16; // @[Reg.scala 27:20] - wire _T_9023 = _T_4687 & ic_tag_valid_out_0_16; // @[ifu_mem_ctl.scala 697:10] - wire _T_9261 = _T_9260 | _T_9023; // @[ifu_mem_ctl.scala 697:91] + wire _T_9023 = _T_4687 & ic_tag_valid_out_0_16; // @[ifu_mem_ctl.scala 696:10] + wire _T_9261 = _T_9260 | _T_9023; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_17; // @[Reg.scala 27:20] - wire _T_9025 = _T_4688 & ic_tag_valid_out_0_17; // @[ifu_mem_ctl.scala 697:10] - wire _T_9262 = _T_9261 | _T_9025; // @[ifu_mem_ctl.scala 697:91] + wire _T_9025 = _T_4688 & ic_tag_valid_out_0_17; // @[ifu_mem_ctl.scala 696:10] + wire _T_9262 = _T_9261 | _T_9025; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_18; // @[Reg.scala 27:20] - wire _T_9027 = _T_4689 & ic_tag_valid_out_0_18; // @[ifu_mem_ctl.scala 697:10] - wire _T_9263 = _T_9262 | _T_9027; // @[ifu_mem_ctl.scala 697:91] + wire _T_9027 = _T_4689 & ic_tag_valid_out_0_18; // @[ifu_mem_ctl.scala 696:10] + wire _T_9263 = _T_9262 | _T_9027; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_19; // @[Reg.scala 27:20] - wire _T_9029 = _T_4690 & ic_tag_valid_out_0_19; // @[ifu_mem_ctl.scala 697:10] - wire _T_9264 = _T_9263 | _T_9029; // @[ifu_mem_ctl.scala 697:91] + wire _T_9029 = _T_4690 & ic_tag_valid_out_0_19; // @[ifu_mem_ctl.scala 696:10] + wire _T_9264 = _T_9263 | _T_9029; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_20; // @[Reg.scala 27:20] - wire _T_9031 = _T_4691 & ic_tag_valid_out_0_20; // @[ifu_mem_ctl.scala 697:10] - wire _T_9265 = _T_9264 | _T_9031; // @[ifu_mem_ctl.scala 697:91] + wire _T_9031 = _T_4691 & ic_tag_valid_out_0_20; // @[ifu_mem_ctl.scala 696:10] + wire _T_9265 = _T_9264 | _T_9031; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_21; // @[Reg.scala 27:20] - wire _T_9033 = _T_4692 & ic_tag_valid_out_0_21; // @[ifu_mem_ctl.scala 697:10] - wire _T_9266 = _T_9265 | _T_9033; // @[ifu_mem_ctl.scala 697:91] + wire _T_9033 = _T_4692 & ic_tag_valid_out_0_21; // @[ifu_mem_ctl.scala 696:10] + wire _T_9266 = _T_9265 | _T_9033; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_22; // @[Reg.scala 27:20] - wire _T_9035 = _T_4693 & ic_tag_valid_out_0_22; // @[ifu_mem_ctl.scala 697:10] - wire _T_9267 = _T_9266 | _T_9035; // @[ifu_mem_ctl.scala 697:91] + wire _T_9035 = _T_4693 & ic_tag_valid_out_0_22; // @[ifu_mem_ctl.scala 696:10] + wire _T_9267 = _T_9266 | _T_9035; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_23; // @[Reg.scala 27:20] - wire _T_9037 = _T_4694 & ic_tag_valid_out_0_23; // @[ifu_mem_ctl.scala 697:10] - wire _T_9268 = _T_9267 | _T_9037; // @[ifu_mem_ctl.scala 697:91] + wire _T_9037 = _T_4694 & ic_tag_valid_out_0_23; // @[ifu_mem_ctl.scala 696:10] + wire _T_9268 = _T_9267 | _T_9037; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_24; // @[Reg.scala 27:20] - wire _T_9039 = _T_4695 & ic_tag_valid_out_0_24; // @[ifu_mem_ctl.scala 697:10] - wire _T_9269 = _T_9268 | _T_9039; // @[ifu_mem_ctl.scala 697:91] + wire _T_9039 = _T_4695 & ic_tag_valid_out_0_24; // @[ifu_mem_ctl.scala 696:10] + wire _T_9269 = _T_9268 | _T_9039; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_25; // @[Reg.scala 27:20] - wire _T_9041 = _T_4696 & ic_tag_valid_out_0_25; // @[ifu_mem_ctl.scala 697:10] - wire _T_9270 = _T_9269 | _T_9041; // @[ifu_mem_ctl.scala 697:91] + wire _T_9041 = _T_4696 & ic_tag_valid_out_0_25; // @[ifu_mem_ctl.scala 696:10] + wire _T_9270 = _T_9269 | _T_9041; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_26; // @[Reg.scala 27:20] - wire _T_9043 = _T_4697 & ic_tag_valid_out_0_26; // @[ifu_mem_ctl.scala 697:10] - wire _T_9271 = _T_9270 | _T_9043; // @[ifu_mem_ctl.scala 697:91] + wire _T_9043 = _T_4697 & ic_tag_valid_out_0_26; // @[ifu_mem_ctl.scala 696:10] + wire _T_9271 = _T_9270 | _T_9043; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_27; // @[Reg.scala 27:20] - wire _T_9045 = _T_4698 & ic_tag_valid_out_0_27; // @[ifu_mem_ctl.scala 697:10] - wire _T_9272 = _T_9271 | _T_9045; // @[ifu_mem_ctl.scala 697:91] + wire _T_9045 = _T_4698 & ic_tag_valid_out_0_27; // @[ifu_mem_ctl.scala 696:10] + wire _T_9272 = _T_9271 | _T_9045; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_28; // @[Reg.scala 27:20] - wire _T_9047 = _T_4699 & ic_tag_valid_out_0_28; // @[ifu_mem_ctl.scala 697:10] - wire _T_9273 = _T_9272 | _T_9047; // @[ifu_mem_ctl.scala 697:91] + wire _T_9047 = _T_4699 & ic_tag_valid_out_0_28; // @[ifu_mem_ctl.scala 696:10] + wire _T_9273 = _T_9272 | _T_9047; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_29; // @[Reg.scala 27:20] - wire _T_9049 = _T_4700 & ic_tag_valid_out_0_29; // @[ifu_mem_ctl.scala 697:10] - wire _T_9274 = _T_9273 | _T_9049; // @[ifu_mem_ctl.scala 697:91] + wire _T_9049 = _T_4700 & ic_tag_valid_out_0_29; // @[ifu_mem_ctl.scala 696:10] + wire _T_9274 = _T_9273 | _T_9049; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_30; // @[Reg.scala 27:20] - wire _T_9051 = _T_4701 & ic_tag_valid_out_0_30; // @[ifu_mem_ctl.scala 697:10] - wire _T_9275 = _T_9274 | _T_9051; // @[ifu_mem_ctl.scala 697:91] + wire _T_9051 = _T_4701 & ic_tag_valid_out_0_30; // @[ifu_mem_ctl.scala 696:10] + wire _T_9275 = _T_9274 | _T_9051; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_31; // @[Reg.scala 27:20] - wire _T_9053 = _T_4702 & ic_tag_valid_out_0_31; // @[ifu_mem_ctl.scala 697:10] - wire _T_9276 = _T_9275 | _T_9053; // @[ifu_mem_ctl.scala 697:91] + wire _T_9053 = _T_4702 & ic_tag_valid_out_0_31; // @[ifu_mem_ctl.scala 696:10] + wire _T_9276 = _T_9275 | _T_9053; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_32; // @[Reg.scala 27:20] - wire _T_9055 = _T_4703 & ic_tag_valid_out_0_32; // @[ifu_mem_ctl.scala 697:10] - wire _T_9277 = _T_9276 | _T_9055; // @[ifu_mem_ctl.scala 697:91] + wire _T_9055 = _T_4703 & ic_tag_valid_out_0_32; // @[ifu_mem_ctl.scala 696:10] + wire _T_9277 = _T_9276 | _T_9055; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_33; // @[Reg.scala 27:20] - wire _T_9057 = _T_4704 & ic_tag_valid_out_0_33; // @[ifu_mem_ctl.scala 697:10] - wire _T_9278 = _T_9277 | _T_9057; // @[ifu_mem_ctl.scala 697:91] + wire _T_9057 = _T_4704 & ic_tag_valid_out_0_33; // @[ifu_mem_ctl.scala 696:10] + wire _T_9278 = _T_9277 | _T_9057; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_34; // @[Reg.scala 27:20] - wire _T_9059 = _T_4705 & ic_tag_valid_out_0_34; // @[ifu_mem_ctl.scala 697:10] - wire _T_9279 = _T_9278 | _T_9059; // @[ifu_mem_ctl.scala 697:91] + wire _T_9059 = _T_4705 & ic_tag_valid_out_0_34; // @[ifu_mem_ctl.scala 696:10] + wire _T_9279 = _T_9278 | _T_9059; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_35; // @[Reg.scala 27:20] - wire _T_9061 = _T_4706 & ic_tag_valid_out_0_35; // @[ifu_mem_ctl.scala 697:10] - wire _T_9280 = _T_9279 | _T_9061; // @[ifu_mem_ctl.scala 697:91] + wire _T_9061 = _T_4706 & ic_tag_valid_out_0_35; // @[ifu_mem_ctl.scala 696:10] + wire _T_9280 = _T_9279 | _T_9061; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_36; // @[Reg.scala 27:20] - wire _T_9063 = _T_4707 & ic_tag_valid_out_0_36; // @[ifu_mem_ctl.scala 697:10] - wire _T_9281 = _T_9280 | _T_9063; // @[ifu_mem_ctl.scala 697:91] + wire _T_9063 = _T_4707 & ic_tag_valid_out_0_36; // @[ifu_mem_ctl.scala 696:10] + wire _T_9281 = _T_9280 | _T_9063; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_37; // @[Reg.scala 27:20] - wire _T_9065 = _T_4708 & ic_tag_valid_out_0_37; // @[ifu_mem_ctl.scala 697:10] - wire _T_9282 = _T_9281 | _T_9065; // @[ifu_mem_ctl.scala 697:91] + wire _T_9065 = _T_4708 & ic_tag_valid_out_0_37; // @[ifu_mem_ctl.scala 696:10] + wire _T_9282 = _T_9281 | _T_9065; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_38; // @[Reg.scala 27:20] - wire _T_9067 = _T_4709 & ic_tag_valid_out_0_38; // @[ifu_mem_ctl.scala 697:10] - wire _T_9283 = _T_9282 | _T_9067; // @[ifu_mem_ctl.scala 697:91] + wire _T_9067 = _T_4709 & ic_tag_valid_out_0_38; // @[ifu_mem_ctl.scala 696:10] + wire _T_9283 = _T_9282 | _T_9067; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_39; // @[Reg.scala 27:20] - wire _T_9069 = _T_4710 & ic_tag_valid_out_0_39; // @[ifu_mem_ctl.scala 697:10] - wire _T_9284 = _T_9283 | _T_9069; // @[ifu_mem_ctl.scala 697:91] + wire _T_9069 = _T_4710 & ic_tag_valid_out_0_39; // @[ifu_mem_ctl.scala 696:10] + wire _T_9284 = _T_9283 | _T_9069; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_40; // @[Reg.scala 27:20] - wire _T_9071 = _T_4711 & ic_tag_valid_out_0_40; // @[ifu_mem_ctl.scala 697:10] - wire _T_9285 = _T_9284 | _T_9071; // @[ifu_mem_ctl.scala 697:91] + wire _T_9071 = _T_4711 & ic_tag_valid_out_0_40; // @[ifu_mem_ctl.scala 696:10] + wire _T_9285 = _T_9284 | _T_9071; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_41; // @[Reg.scala 27:20] - wire _T_9073 = _T_4712 & ic_tag_valid_out_0_41; // @[ifu_mem_ctl.scala 697:10] - wire _T_9286 = _T_9285 | _T_9073; // @[ifu_mem_ctl.scala 697:91] + wire _T_9073 = _T_4712 & ic_tag_valid_out_0_41; // @[ifu_mem_ctl.scala 696:10] + wire _T_9286 = _T_9285 | _T_9073; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_42; // @[Reg.scala 27:20] - wire _T_9075 = _T_4713 & ic_tag_valid_out_0_42; // @[ifu_mem_ctl.scala 697:10] - wire _T_9287 = _T_9286 | _T_9075; // @[ifu_mem_ctl.scala 697:91] + wire _T_9075 = _T_4713 & ic_tag_valid_out_0_42; // @[ifu_mem_ctl.scala 696:10] + wire _T_9287 = _T_9286 | _T_9075; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_43; // @[Reg.scala 27:20] - wire _T_9077 = _T_4714 & ic_tag_valid_out_0_43; // @[ifu_mem_ctl.scala 697:10] - wire _T_9288 = _T_9287 | _T_9077; // @[ifu_mem_ctl.scala 697:91] + wire _T_9077 = _T_4714 & ic_tag_valid_out_0_43; // @[ifu_mem_ctl.scala 696:10] + wire _T_9288 = _T_9287 | _T_9077; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_44; // @[Reg.scala 27:20] - wire _T_9079 = _T_4715 & ic_tag_valid_out_0_44; // @[ifu_mem_ctl.scala 697:10] - wire _T_9289 = _T_9288 | _T_9079; // @[ifu_mem_ctl.scala 697:91] + wire _T_9079 = _T_4715 & ic_tag_valid_out_0_44; // @[ifu_mem_ctl.scala 696:10] + wire _T_9289 = _T_9288 | _T_9079; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_45; // @[Reg.scala 27:20] - wire _T_9081 = _T_4716 & ic_tag_valid_out_0_45; // @[ifu_mem_ctl.scala 697:10] - wire _T_9290 = _T_9289 | _T_9081; // @[ifu_mem_ctl.scala 697:91] + wire _T_9081 = _T_4716 & ic_tag_valid_out_0_45; // @[ifu_mem_ctl.scala 696:10] + wire _T_9290 = _T_9289 | _T_9081; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_46; // @[Reg.scala 27:20] - wire _T_9083 = _T_4717 & ic_tag_valid_out_0_46; // @[ifu_mem_ctl.scala 697:10] - wire _T_9291 = _T_9290 | _T_9083; // @[ifu_mem_ctl.scala 697:91] + wire _T_9083 = _T_4717 & ic_tag_valid_out_0_46; // @[ifu_mem_ctl.scala 696:10] + wire _T_9291 = _T_9290 | _T_9083; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_47; // @[Reg.scala 27:20] - wire _T_9085 = _T_4718 & ic_tag_valid_out_0_47; // @[ifu_mem_ctl.scala 697:10] - wire _T_9292 = _T_9291 | _T_9085; // @[ifu_mem_ctl.scala 697:91] + wire _T_9085 = _T_4718 & ic_tag_valid_out_0_47; // @[ifu_mem_ctl.scala 696:10] + wire _T_9292 = _T_9291 | _T_9085; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_48; // @[Reg.scala 27:20] - wire _T_9087 = _T_4719 & ic_tag_valid_out_0_48; // @[ifu_mem_ctl.scala 697:10] - wire _T_9293 = _T_9292 | _T_9087; // @[ifu_mem_ctl.scala 697:91] + wire _T_9087 = _T_4719 & ic_tag_valid_out_0_48; // @[ifu_mem_ctl.scala 696:10] + wire _T_9293 = _T_9292 | _T_9087; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_49; // @[Reg.scala 27:20] - wire _T_9089 = _T_4720 & ic_tag_valid_out_0_49; // @[ifu_mem_ctl.scala 697:10] - wire _T_9294 = _T_9293 | _T_9089; // @[ifu_mem_ctl.scala 697:91] + wire _T_9089 = _T_4720 & ic_tag_valid_out_0_49; // @[ifu_mem_ctl.scala 696:10] + wire _T_9294 = _T_9293 | _T_9089; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_50; // @[Reg.scala 27:20] - wire _T_9091 = _T_4721 & ic_tag_valid_out_0_50; // @[ifu_mem_ctl.scala 697:10] - wire _T_9295 = _T_9294 | _T_9091; // @[ifu_mem_ctl.scala 697:91] + wire _T_9091 = _T_4721 & ic_tag_valid_out_0_50; // @[ifu_mem_ctl.scala 696:10] + wire _T_9295 = _T_9294 | _T_9091; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_51; // @[Reg.scala 27:20] - wire _T_9093 = _T_4722 & ic_tag_valid_out_0_51; // @[ifu_mem_ctl.scala 697:10] - wire _T_9296 = _T_9295 | _T_9093; // @[ifu_mem_ctl.scala 697:91] + wire _T_9093 = _T_4722 & ic_tag_valid_out_0_51; // @[ifu_mem_ctl.scala 696:10] + wire _T_9296 = _T_9295 | _T_9093; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_52; // @[Reg.scala 27:20] - wire _T_9095 = _T_4723 & ic_tag_valid_out_0_52; // @[ifu_mem_ctl.scala 697:10] - wire _T_9297 = _T_9296 | _T_9095; // @[ifu_mem_ctl.scala 697:91] + wire _T_9095 = _T_4723 & ic_tag_valid_out_0_52; // @[ifu_mem_ctl.scala 696:10] + wire _T_9297 = _T_9296 | _T_9095; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_53; // @[Reg.scala 27:20] - wire _T_9097 = _T_4724 & ic_tag_valid_out_0_53; // @[ifu_mem_ctl.scala 697:10] - wire _T_9298 = _T_9297 | _T_9097; // @[ifu_mem_ctl.scala 697:91] + wire _T_9097 = _T_4724 & ic_tag_valid_out_0_53; // @[ifu_mem_ctl.scala 696:10] + wire _T_9298 = _T_9297 | _T_9097; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_54; // @[Reg.scala 27:20] - wire _T_9099 = _T_4725 & ic_tag_valid_out_0_54; // @[ifu_mem_ctl.scala 697:10] - wire _T_9299 = _T_9298 | _T_9099; // @[ifu_mem_ctl.scala 697:91] + wire _T_9099 = _T_4725 & ic_tag_valid_out_0_54; // @[ifu_mem_ctl.scala 696:10] + wire _T_9299 = _T_9298 | _T_9099; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_55; // @[Reg.scala 27:20] - wire _T_9101 = _T_4726 & ic_tag_valid_out_0_55; // @[ifu_mem_ctl.scala 697:10] - wire _T_9300 = _T_9299 | _T_9101; // @[ifu_mem_ctl.scala 697:91] + wire _T_9101 = _T_4726 & ic_tag_valid_out_0_55; // @[ifu_mem_ctl.scala 696:10] + wire _T_9300 = _T_9299 | _T_9101; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_56; // @[Reg.scala 27:20] - wire _T_9103 = _T_4727 & ic_tag_valid_out_0_56; // @[ifu_mem_ctl.scala 697:10] - wire _T_9301 = _T_9300 | _T_9103; // @[ifu_mem_ctl.scala 697:91] + wire _T_9103 = _T_4727 & ic_tag_valid_out_0_56; // @[ifu_mem_ctl.scala 696:10] + wire _T_9301 = _T_9300 | _T_9103; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_57; // @[Reg.scala 27:20] - wire _T_9105 = _T_4728 & ic_tag_valid_out_0_57; // @[ifu_mem_ctl.scala 697:10] - wire _T_9302 = _T_9301 | _T_9105; // @[ifu_mem_ctl.scala 697:91] + wire _T_9105 = _T_4728 & ic_tag_valid_out_0_57; // @[ifu_mem_ctl.scala 696:10] + wire _T_9302 = _T_9301 | _T_9105; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_58; // @[Reg.scala 27:20] - wire _T_9107 = _T_4729 & ic_tag_valid_out_0_58; // @[ifu_mem_ctl.scala 697:10] - wire _T_9303 = _T_9302 | _T_9107; // @[ifu_mem_ctl.scala 697:91] + wire _T_9107 = _T_4729 & ic_tag_valid_out_0_58; // @[ifu_mem_ctl.scala 696:10] + wire _T_9303 = _T_9302 | _T_9107; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_59; // @[Reg.scala 27:20] - wire _T_9109 = _T_4730 & ic_tag_valid_out_0_59; // @[ifu_mem_ctl.scala 697:10] - wire _T_9304 = _T_9303 | _T_9109; // @[ifu_mem_ctl.scala 697:91] + wire _T_9109 = _T_4730 & ic_tag_valid_out_0_59; // @[ifu_mem_ctl.scala 696:10] + wire _T_9304 = _T_9303 | _T_9109; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_60; // @[Reg.scala 27:20] - wire _T_9111 = _T_4731 & ic_tag_valid_out_0_60; // @[ifu_mem_ctl.scala 697:10] - wire _T_9305 = _T_9304 | _T_9111; // @[ifu_mem_ctl.scala 697:91] + wire _T_9111 = _T_4731 & ic_tag_valid_out_0_60; // @[ifu_mem_ctl.scala 696:10] + wire _T_9305 = _T_9304 | _T_9111; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_61; // @[Reg.scala 27:20] - wire _T_9113 = _T_4732 & ic_tag_valid_out_0_61; // @[ifu_mem_ctl.scala 697:10] - wire _T_9306 = _T_9305 | _T_9113; // @[ifu_mem_ctl.scala 697:91] + wire _T_9113 = _T_4732 & ic_tag_valid_out_0_61; // @[ifu_mem_ctl.scala 696:10] + wire _T_9306 = _T_9305 | _T_9113; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_62; // @[Reg.scala 27:20] - wire _T_9115 = _T_4733 & ic_tag_valid_out_0_62; // @[ifu_mem_ctl.scala 697:10] - wire _T_9307 = _T_9306 | _T_9115; // @[ifu_mem_ctl.scala 697:91] + wire _T_9115 = _T_4733 & ic_tag_valid_out_0_62; // @[ifu_mem_ctl.scala 696:10] + wire _T_9307 = _T_9306 | _T_9115; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_63; // @[Reg.scala 27:20] - wire _T_9117 = _T_4734 & ic_tag_valid_out_0_63; // @[ifu_mem_ctl.scala 697:10] - wire _T_9308 = _T_9307 | _T_9117; // @[ifu_mem_ctl.scala 697:91] + wire _T_9117 = _T_4734 & ic_tag_valid_out_0_63; // @[ifu_mem_ctl.scala 696:10] + wire _T_9308 = _T_9307 | _T_9117; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_64; // @[Reg.scala 27:20] - wire _T_9119 = _T_4735 & ic_tag_valid_out_0_64; // @[ifu_mem_ctl.scala 697:10] - wire _T_9309 = _T_9308 | _T_9119; // @[ifu_mem_ctl.scala 697:91] + wire _T_9119 = _T_4735 & ic_tag_valid_out_0_64; // @[ifu_mem_ctl.scala 696:10] + wire _T_9309 = _T_9308 | _T_9119; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_65; // @[Reg.scala 27:20] - wire _T_9121 = _T_4736 & ic_tag_valid_out_0_65; // @[ifu_mem_ctl.scala 697:10] - wire _T_9310 = _T_9309 | _T_9121; // @[ifu_mem_ctl.scala 697:91] + wire _T_9121 = _T_4736 & ic_tag_valid_out_0_65; // @[ifu_mem_ctl.scala 696:10] + wire _T_9310 = _T_9309 | _T_9121; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_66; // @[Reg.scala 27:20] - wire _T_9123 = _T_4737 & ic_tag_valid_out_0_66; // @[ifu_mem_ctl.scala 697:10] - wire _T_9311 = _T_9310 | _T_9123; // @[ifu_mem_ctl.scala 697:91] + wire _T_9123 = _T_4737 & ic_tag_valid_out_0_66; // @[ifu_mem_ctl.scala 696:10] + wire _T_9311 = _T_9310 | _T_9123; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_67; // @[Reg.scala 27:20] - wire _T_9125 = _T_4738 & ic_tag_valid_out_0_67; // @[ifu_mem_ctl.scala 697:10] - wire _T_9312 = _T_9311 | _T_9125; // @[ifu_mem_ctl.scala 697:91] + wire _T_9125 = _T_4738 & ic_tag_valid_out_0_67; // @[ifu_mem_ctl.scala 696:10] + wire _T_9312 = _T_9311 | _T_9125; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_68; // @[Reg.scala 27:20] - wire _T_9127 = _T_4739 & ic_tag_valid_out_0_68; // @[ifu_mem_ctl.scala 697:10] - wire _T_9313 = _T_9312 | _T_9127; // @[ifu_mem_ctl.scala 697:91] + wire _T_9127 = _T_4739 & ic_tag_valid_out_0_68; // @[ifu_mem_ctl.scala 696:10] + wire _T_9313 = _T_9312 | _T_9127; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_69; // @[Reg.scala 27:20] - wire _T_9129 = _T_4740 & ic_tag_valid_out_0_69; // @[ifu_mem_ctl.scala 697:10] - wire _T_9314 = _T_9313 | _T_9129; // @[ifu_mem_ctl.scala 697:91] + wire _T_9129 = _T_4740 & ic_tag_valid_out_0_69; // @[ifu_mem_ctl.scala 696:10] + wire _T_9314 = _T_9313 | _T_9129; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_70; // @[Reg.scala 27:20] - wire _T_9131 = _T_4741 & ic_tag_valid_out_0_70; // @[ifu_mem_ctl.scala 697:10] - wire _T_9315 = _T_9314 | _T_9131; // @[ifu_mem_ctl.scala 697:91] + wire _T_9131 = _T_4741 & ic_tag_valid_out_0_70; // @[ifu_mem_ctl.scala 696:10] + wire _T_9315 = _T_9314 | _T_9131; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_71; // @[Reg.scala 27:20] - wire _T_9133 = _T_4742 & ic_tag_valid_out_0_71; // @[ifu_mem_ctl.scala 697:10] - wire _T_9316 = _T_9315 | _T_9133; // @[ifu_mem_ctl.scala 697:91] + wire _T_9133 = _T_4742 & ic_tag_valid_out_0_71; // @[ifu_mem_ctl.scala 696:10] + wire _T_9316 = _T_9315 | _T_9133; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_72; // @[Reg.scala 27:20] - wire _T_9135 = _T_4743 & ic_tag_valid_out_0_72; // @[ifu_mem_ctl.scala 697:10] - wire _T_9317 = _T_9316 | _T_9135; // @[ifu_mem_ctl.scala 697:91] + wire _T_9135 = _T_4743 & ic_tag_valid_out_0_72; // @[ifu_mem_ctl.scala 696:10] + wire _T_9317 = _T_9316 | _T_9135; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_73; // @[Reg.scala 27:20] - wire _T_9137 = _T_4744 & ic_tag_valid_out_0_73; // @[ifu_mem_ctl.scala 697:10] - wire _T_9318 = _T_9317 | _T_9137; // @[ifu_mem_ctl.scala 697:91] + wire _T_9137 = _T_4744 & ic_tag_valid_out_0_73; // @[ifu_mem_ctl.scala 696:10] + wire _T_9318 = _T_9317 | _T_9137; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_74; // @[Reg.scala 27:20] - wire _T_9139 = _T_4745 & ic_tag_valid_out_0_74; // @[ifu_mem_ctl.scala 697:10] - wire _T_9319 = _T_9318 | _T_9139; // @[ifu_mem_ctl.scala 697:91] + wire _T_9139 = _T_4745 & ic_tag_valid_out_0_74; // @[ifu_mem_ctl.scala 696:10] + wire _T_9319 = _T_9318 | _T_9139; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_75; // @[Reg.scala 27:20] - wire _T_9141 = _T_4746 & ic_tag_valid_out_0_75; // @[ifu_mem_ctl.scala 697:10] - wire _T_9320 = _T_9319 | _T_9141; // @[ifu_mem_ctl.scala 697:91] + wire _T_9141 = _T_4746 & ic_tag_valid_out_0_75; // @[ifu_mem_ctl.scala 696:10] + wire _T_9320 = _T_9319 | _T_9141; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_76; // @[Reg.scala 27:20] - wire _T_9143 = _T_4747 & ic_tag_valid_out_0_76; // @[ifu_mem_ctl.scala 697:10] - wire _T_9321 = _T_9320 | _T_9143; // @[ifu_mem_ctl.scala 697:91] + wire _T_9143 = _T_4747 & ic_tag_valid_out_0_76; // @[ifu_mem_ctl.scala 696:10] + wire _T_9321 = _T_9320 | _T_9143; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_77; // @[Reg.scala 27:20] - wire _T_9145 = _T_4748 & ic_tag_valid_out_0_77; // @[ifu_mem_ctl.scala 697:10] - wire _T_9322 = _T_9321 | _T_9145; // @[ifu_mem_ctl.scala 697:91] + wire _T_9145 = _T_4748 & ic_tag_valid_out_0_77; // @[ifu_mem_ctl.scala 696:10] + wire _T_9322 = _T_9321 | _T_9145; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_78; // @[Reg.scala 27:20] - wire _T_9147 = _T_4749 & ic_tag_valid_out_0_78; // @[ifu_mem_ctl.scala 697:10] - wire _T_9323 = _T_9322 | _T_9147; // @[ifu_mem_ctl.scala 697:91] + wire _T_9147 = _T_4749 & ic_tag_valid_out_0_78; // @[ifu_mem_ctl.scala 696:10] + wire _T_9323 = _T_9322 | _T_9147; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_79; // @[Reg.scala 27:20] - wire _T_9149 = _T_4750 & ic_tag_valid_out_0_79; // @[ifu_mem_ctl.scala 697:10] - wire _T_9324 = _T_9323 | _T_9149; // @[ifu_mem_ctl.scala 697:91] + wire _T_9149 = _T_4750 & ic_tag_valid_out_0_79; // @[ifu_mem_ctl.scala 696:10] + wire _T_9324 = _T_9323 | _T_9149; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_80; // @[Reg.scala 27:20] - wire _T_9151 = _T_4751 & ic_tag_valid_out_0_80; // @[ifu_mem_ctl.scala 697:10] - wire _T_9325 = _T_9324 | _T_9151; // @[ifu_mem_ctl.scala 697:91] + wire _T_9151 = _T_4751 & ic_tag_valid_out_0_80; // @[ifu_mem_ctl.scala 696:10] + wire _T_9325 = _T_9324 | _T_9151; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_81; // @[Reg.scala 27:20] - wire _T_9153 = _T_4752 & ic_tag_valid_out_0_81; // @[ifu_mem_ctl.scala 697:10] - wire _T_9326 = _T_9325 | _T_9153; // @[ifu_mem_ctl.scala 697:91] + wire _T_9153 = _T_4752 & ic_tag_valid_out_0_81; // @[ifu_mem_ctl.scala 696:10] + wire _T_9326 = _T_9325 | _T_9153; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_82; // @[Reg.scala 27:20] - wire _T_9155 = _T_4753 & ic_tag_valid_out_0_82; // @[ifu_mem_ctl.scala 697:10] - wire _T_9327 = _T_9326 | _T_9155; // @[ifu_mem_ctl.scala 697:91] + wire _T_9155 = _T_4753 & ic_tag_valid_out_0_82; // @[ifu_mem_ctl.scala 696:10] + wire _T_9327 = _T_9326 | _T_9155; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_83; // @[Reg.scala 27:20] - wire _T_9157 = _T_4754 & ic_tag_valid_out_0_83; // @[ifu_mem_ctl.scala 697:10] - wire _T_9328 = _T_9327 | _T_9157; // @[ifu_mem_ctl.scala 697:91] + wire _T_9157 = _T_4754 & ic_tag_valid_out_0_83; // @[ifu_mem_ctl.scala 696:10] + wire _T_9328 = _T_9327 | _T_9157; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_84; // @[Reg.scala 27:20] - wire _T_9159 = _T_4755 & ic_tag_valid_out_0_84; // @[ifu_mem_ctl.scala 697:10] - wire _T_9329 = _T_9328 | _T_9159; // @[ifu_mem_ctl.scala 697:91] + wire _T_9159 = _T_4755 & ic_tag_valid_out_0_84; // @[ifu_mem_ctl.scala 696:10] + wire _T_9329 = _T_9328 | _T_9159; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_85; // @[Reg.scala 27:20] - wire _T_9161 = _T_4756 & ic_tag_valid_out_0_85; // @[ifu_mem_ctl.scala 697:10] - wire _T_9330 = _T_9329 | _T_9161; // @[ifu_mem_ctl.scala 697:91] + wire _T_9161 = _T_4756 & ic_tag_valid_out_0_85; // @[ifu_mem_ctl.scala 696:10] + wire _T_9330 = _T_9329 | _T_9161; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_86; // @[Reg.scala 27:20] - wire _T_9163 = _T_4757 & ic_tag_valid_out_0_86; // @[ifu_mem_ctl.scala 697:10] - wire _T_9331 = _T_9330 | _T_9163; // @[ifu_mem_ctl.scala 697:91] + wire _T_9163 = _T_4757 & ic_tag_valid_out_0_86; // @[ifu_mem_ctl.scala 696:10] + wire _T_9331 = _T_9330 | _T_9163; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_87; // @[Reg.scala 27:20] - wire _T_9165 = _T_4758 & ic_tag_valid_out_0_87; // @[ifu_mem_ctl.scala 697:10] - wire _T_9332 = _T_9331 | _T_9165; // @[ifu_mem_ctl.scala 697:91] + wire _T_9165 = _T_4758 & ic_tag_valid_out_0_87; // @[ifu_mem_ctl.scala 696:10] + wire _T_9332 = _T_9331 | _T_9165; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_88; // @[Reg.scala 27:20] - wire _T_9167 = _T_4759 & ic_tag_valid_out_0_88; // @[ifu_mem_ctl.scala 697:10] - wire _T_9333 = _T_9332 | _T_9167; // @[ifu_mem_ctl.scala 697:91] + wire _T_9167 = _T_4759 & ic_tag_valid_out_0_88; // @[ifu_mem_ctl.scala 696:10] + wire _T_9333 = _T_9332 | _T_9167; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_89; // @[Reg.scala 27:20] - wire _T_9169 = _T_4760 & ic_tag_valid_out_0_89; // @[ifu_mem_ctl.scala 697:10] - wire _T_9334 = _T_9333 | _T_9169; // @[ifu_mem_ctl.scala 697:91] + wire _T_9169 = _T_4760 & ic_tag_valid_out_0_89; // @[ifu_mem_ctl.scala 696:10] + wire _T_9334 = _T_9333 | _T_9169; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_90; // @[Reg.scala 27:20] - wire _T_9171 = _T_4761 & ic_tag_valid_out_0_90; // @[ifu_mem_ctl.scala 697:10] - wire _T_9335 = _T_9334 | _T_9171; // @[ifu_mem_ctl.scala 697:91] + wire _T_9171 = _T_4761 & ic_tag_valid_out_0_90; // @[ifu_mem_ctl.scala 696:10] + wire _T_9335 = _T_9334 | _T_9171; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_91; // @[Reg.scala 27:20] - wire _T_9173 = _T_4762 & ic_tag_valid_out_0_91; // @[ifu_mem_ctl.scala 697:10] - wire _T_9336 = _T_9335 | _T_9173; // @[ifu_mem_ctl.scala 697:91] + wire _T_9173 = _T_4762 & ic_tag_valid_out_0_91; // @[ifu_mem_ctl.scala 696:10] + wire _T_9336 = _T_9335 | _T_9173; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_92; // @[Reg.scala 27:20] - wire _T_9175 = _T_4763 & ic_tag_valid_out_0_92; // @[ifu_mem_ctl.scala 697:10] - wire _T_9337 = _T_9336 | _T_9175; // @[ifu_mem_ctl.scala 697:91] + wire _T_9175 = _T_4763 & ic_tag_valid_out_0_92; // @[ifu_mem_ctl.scala 696:10] + wire _T_9337 = _T_9336 | _T_9175; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_93; // @[Reg.scala 27:20] - wire _T_9177 = _T_4764 & ic_tag_valid_out_0_93; // @[ifu_mem_ctl.scala 697:10] - wire _T_9338 = _T_9337 | _T_9177; // @[ifu_mem_ctl.scala 697:91] + wire _T_9177 = _T_4764 & ic_tag_valid_out_0_93; // @[ifu_mem_ctl.scala 696:10] + wire _T_9338 = _T_9337 | _T_9177; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_94; // @[Reg.scala 27:20] - wire _T_9179 = _T_4765 & ic_tag_valid_out_0_94; // @[ifu_mem_ctl.scala 697:10] - wire _T_9339 = _T_9338 | _T_9179; // @[ifu_mem_ctl.scala 697:91] + wire _T_9179 = _T_4765 & ic_tag_valid_out_0_94; // @[ifu_mem_ctl.scala 696:10] + wire _T_9339 = _T_9338 | _T_9179; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_95; // @[Reg.scala 27:20] - wire _T_9181 = _T_4766 & ic_tag_valid_out_0_95; // @[ifu_mem_ctl.scala 697:10] - wire _T_9340 = _T_9339 | _T_9181; // @[ifu_mem_ctl.scala 697:91] + wire _T_9181 = _T_4766 & ic_tag_valid_out_0_95; // @[ifu_mem_ctl.scala 696:10] + wire _T_9340 = _T_9339 | _T_9181; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_96; // @[Reg.scala 27:20] - wire _T_9183 = _T_4767 & ic_tag_valid_out_0_96; // @[ifu_mem_ctl.scala 697:10] - wire _T_9341 = _T_9340 | _T_9183; // @[ifu_mem_ctl.scala 697:91] + wire _T_9183 = _T_4767 & ic_tag_valid_out_0_96; // @[ifu_mem_ctl.scala 696:10] + wire _T_9341 = _T_9340 | _T_9183; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_97; // @[Reg.scala 27:20] - wire _T_9185 = _T_4768 & ic_tag_valid_out_0_97; // @[ifu_mem_ctl.scala 697:10] - wire _T_9342 = _T_9341 | _T_9185; // @[ifu_mem_ctl.scala 697:91] + wire _T_9185 = _T_4768 & ic_tag_valid_out_0_97; // @[ifu_mem_ctl.scala 696:10] + wire _T_9342 = _T_9341 | _T_9185; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_98; // @[Reg.scala 27:20] - wire _T_9187 = _T_4769 & ic_tag_valid_out_0_98; // @[ifu_mem_ctl.scala 697:10] - wire _T_9343 = _T_9342 | _T_9187; // @[ifu_mem_ctl.scala 697:91] + wire _T_9187 = _T_4769 & ic_tag_valid_out_0_98; // @[ifu_mem_ctl.scala 696:10] + wire _T_9343 = _T_9342 | _T_9187; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_99; // @[Reg.scala 27:20] - wire _T_9189 = _T_4770 & ic_tag_valid_out_0_99; // @[ifu_mem_ctl.scala 697:10] - wire _T_9344 = _T_9343 | _T_9189; // @[ifu_mem_ctl.scala 697:91] + wire _T_9189 = _T_4770 & ic_tag_valid_out_0_99; // @[ifu_mem_ctl.scala 696:10] + wire _T_9344 = _T_9343 | _T_9189; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_100; // @[Reg.scala 27:20] - wire _T_9191 = _T_4771 & ic_tag_valid_out_0_100; // @[ifu_mem_ctl.scala 697:10] - wire _T_9345 = _T_9344 | _T_9191; // @[ifu_mem_ctl.scala 697:91] + wire _T_9191 = _T_4771 & ic_tag_valid_out_0_100; // @[ifu_mem_ctl.scala 696:10] + wire _T_9345 = _T_9344 | _T_9191; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_101; // @[Reg.scala 27:20] - wire _T_9193 = _T_4772 & ic_tag_valid_out_0_101; // @[ifu_mem_ctl.scala 697:10] - wire _T_9346 = _T_9345 | _T_9193; // @[ifu_mem_ctl.scala 697:91] + wire _T_9193 = _T_4772 & ic_tag_valid_out_0_101; // @[ifu_mem_ctl.scala 696:10] + wire _T_9346 = _T_9345 | _T_9193; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_102; // @[Reg.scala 27:20] - wire _T_9195 = _T_4773 & ic_tag_valid_out_0_102; // @[ifu_mem_ctl.scala 697:10] - wire _T_9347 = _T_9346 | _T_9195; // @[ifu_mem_ctl.scala 697:91] + wire _T_9195 = _T_4773 & ic_tag_valid_out_0_102; // @[ifu_mem_ctl.scala 696:10] + wire _T_9347 = _T_9346 | _T_9195; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_103; // @[Reg.scala 27:20] - wire _T_9197 = _T_4774 & ic_tag_valid_out_0_103; // @[ifu_mem_ctl.scala 697:10] - wire _T_9348 = _T_9347 | _T_9197; // @[ifu_mem_ctl.scala 697:91] + wire _T_9197 = _T_4774 & ic_tag_valid_out_0_103; // @[ifu_mem_ctl.scala 696:10] + wire _T_9348 = _T_9347 | _T_9197; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_104; // @[Reg.scala 27:20] - wire _T_9199 = _T_4775 & ic_tag_valid_out_0_104; // @[ifu_mem_ctl.scala 697:10] - wire _T_9349 = _T_9348 | _T_9199; // @[ifu_mem_ctl.scala 697:91] + wire _T_9199 = _T_4775 & ic_tag_valid_out_0_104; // @[ifu_mem_ctl.scala 696:10] + wire _T_9349 = _T_9348 | _T_9199; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_105; // @[Reg.scala 27:20] - wire _T_9201 = _T_4776 & ic_tag_valid_out_0_105; // @[ifu_mem_ctl.scala 697:10] - wire _T_9350 = _T_9349 | _T_9201; // @[ifu_mem_ctl.scala 697:91] + wire _T_9201 = _T_4776 & ic_tag_valid_out_0_105; // @[ifu_mem_ctl.scala 696:10] + wire _T_9350 = _T_9349 | _T_9201; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_106; // @[Reg.scala 27:20] - wire _T_9203 = _T_4777 & ic_tag_valid_out_0_106; // @[ifu_mem_ctl.scala 697:10] - wire _T_9351 = _T_9350 | _T_9203; // @[ifu_mem_ctl.scala 697:91] + wire _T_9203 = _T_4777 & ic_tag_valid_out_0_106; // @[ifu_mem_ctl.scala 696:10] + wire _T_9351 = _T_9350 | _T_9203; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_107; // @[Reg.scala 27:20] - wire _T_9205 = _T_4778 & ic_tag_valid_out_0_107; // @[ifu_mem_ctl.scala 697:10] - wire _T_9352 = _T_9351 | _T_9205; // @[ifu_mem_ctl.scala 697:91] + wire _T_9205 = _T_4778 & ic_tag_valid_out_0_107; // @[ifu_mem_ctl.scala 696:10] + wire _T_9352 = _T_9351 | _T_9205; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_108; // @[Reg.scala 27:20] - wire _T_9207 = _T_4779 & ic_tag_valid_out_0_108; // @[ifu_mem_ctl.scala 697:10] - wire _T_9353 = _T_9352 | _T_9207; // @[ifu_mem_ctl.scala 697:91] + wire _T_9207 = _T_4779 & ic_tag_valid_out_0_108; // @[ifu_mem_ctl.scala 696:10] + wire _T_9353 = _T_9352 | _T_9207; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_109; // @[Reg.scala 27:20] - wire _T_9209 = _T_4780 & ic_tag_valid_out_0_109; // @[ifu_mem_ctl.scala 697:10] - wire _T_9354 = _T_9353 | _T_9209; // @[ifu_mem_ctl.scala 697:91] + wire _T_9209 = _T_4780 & ic_tag_valid_out_0_109; // @[ifu_mem_ctl.scala 696:10] + wire _T_9354 = _T_9353 | _T_9209; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_110; // @[Reg.scala 27:20] - wire _T_9211 = _T_4781 & ic_tag_valid_out_0_110; // @[ifu_mem_ctl.scala 697:10] - wire _T_9355 = _T_9354 | _T_9211; // @[ifu_mem_ctl.scala 697:91] + wire _T_9211 = _T_4781 & ic_tag_valid_out_0_110; // @[ifu_mem_ctl.scala 696:10] + wire _T_9355 = _T_9354 | _T_9211; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_111; // @[Reg.scala 27:20] - wire _T_9213 = _T_4782 & ic_tag_valid_out_0_111; // @[ifu_mem_ctl.scala 697:10] - wire _T_9356 = _T_9355 | _T_9213; // @[ifu_mem_ctl.scala 697:91] + wire _T_9213 = _T_4782 & ic_tag_valid_out_0_111; // @[ifu_mem_ctl.scala 696:10] + wire _T_9356 = _T_9355 | _T_9213; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_112; // @[Reg.scala 27:20] - wire _T_9215 = _T_4783 & ic_tag_valid_out_0_112; // @[ifu_mem_ctl.scala 697:10] - wire _T_9357 = _T_9356 | _T_9215; // @[ifu_mem_ctl.scala 697:91] + wire _T_9215 = _T_4783 & ic_tag_valid_out_0_112; // @[ifu_mem_ctl.scala 696:10] + wire _T_9357 = _T_9356 | _T_9215; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_113; // @[Reg.scala 27:20] - wire _T_9217 = _T_4784 & ic_tag_valid_out_0_113; // @[ifu_mem_ctl.scala 697:10] - wire _T_9358 = _T_9357 | _T_9217; // @[ifu_mem_ctl.scala 697:91] + wire _T_9217 = _T_4784 & ic_tag_valid_out_0_113; // @[ifu_mem_ctl.scala 696:10] + wire _T_9358 = _T_9357 | _T_9217; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_114; // @[Reg.scala 27:20] - wire _T_9219 = _T_4785 & ic_tag_valid_out_0_114; // @[ifu_mem_ctl.scala 697:10] - wire _T_9359 = _T_9358 | _T_9219; // @[ifu_mem_ctl.scala 697:91] + wire _T_9219 = _T_4785 & ic_tag_valid_out_0_114; // @[ifu_mem_ctl.scala 696:10] + wire _T_9359 = _T_9358 | _T_9219; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_115; // @[Reg.scala 27:20] - wire _T_9221 = _T_4786 & ic_tag_valid_out_0_115; // @[ifu_mem_ctl.scala 697:10] - wire _T_9360 = _T_9359 | _T_9221; // @[ifu_mem_ctl.scala 697:91] + wire _T_9221 = _T_4786 & ic_tag_valid_out_0_115; // @[ifu_mem_ctl.scala 696:10] + wire _T_9360 = _T_9359 | _T_9221; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_116; // @[Reg.scala 27:20] - wire _T_9223 = _T_4787 & ic_tag_valid_out_0_116; // @[ifu_mem_ctl.scala 697:10] - wire _T_9361 = _T_9360 | _T_9223; // @[ifu_mem_ctl.scala 697:91] + wire _T_9223 = _T_4787 & ic_tag_valid_out_0_116; // @[ifu_mem_ctl.scala 696:10] + wire _T_9361 = _T_9360 | _T_9223; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_117; // @[Reg.scala 27:20] - wire _T_9225 = _T_4788 & ic_tag_valid_out_0_117; // @[ifu_mem_ctl.scala 697:10] - wire _T_9362 = _T_9361 | _T_9225; // @[ifu_mem_ctl.scala 697:91] + wire _T_9225 = _T_4788 & ic_tag_valid_out_0_117; // @[ifu_mem_ctl.scala 696:10] + wire _T_9362 = _T_9361 | _T_9225; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_118; // @[Reg.scala 27:20] - wire _T_9227 = _T_4789 & ic_tag_valid_out_0_118; // @[ifu_mem_ctl.scala 697:10] - wire _T_9363 = _T_9362 | _T_9227; // @[ifu_mem_ctl.scala 697:91] + wire _T_9227 = _T_4789 & ic_tag_valid_out_0_118; // @[ifu_mem_ctl.scala 696:10] + wire _T_9363 = _T_9362 | _T_9227; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_119; // @[Reg.scala 27:20] - wire _T_9229 = _T_4790 & ic_tag_valid_out_0_119; // @[ifu_mem_ctl.scala 697:10] - wire _T_9364 = _T_9363 | _T_9229; // @[ifu_mem_ctl.scala 697:91] + wire _T_9229 = _T_4790 & ic_tag_valid_out_0_119; // @[ifu_mem_ctl.scala 696:10] + wire _T_9364 = _T_9363 | _T_9229; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_120; // @[Reg.scala 27:20] - wire _T_9231 = _T_4791 & ic_tag_valid_out_0_120; // @[ifu_mem_ctl.scala 697:10] - wire _T_9365 = _T_9364 | _T_9231; // @[ifu_mem_ctl.scala 697:91] + wire _T_9231 = _T_4791 & ic_tag_valid_out_0_120; // @[ifu_mem_ctl.scala 696:10] + wire _T_9365 = _T_9364 | _T_9231; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_121; // @[Reg.scala 27:20] - wire _T_9233 = _T_4792 & ic_tag_valid_out_0_121; // @[ifu_mem_ctl.scala 697:10] - wire _T_9366 = _T_9365 | _T_9233; // @[ifu_mem_ctl.scala 697:91] + wire _T_9233 = _T_4792 & ic_tag_valid_out_0_121; // @[ifu_mem_ctl.scala 696:10] + wire _T_9366 = _T_9365 | _T_9233; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_122; // @[Reg.scala 27:20] - wire _T_9235 = _T_4793 & ic_tag_valid_out_0_122; // @[ifu_mem_ctl.scala 697:10] - wire _T_9367 = _T_9366 | _T_9235; // @[ifu_mem_ctl.scala 697:91] + wire _T_9235 = _T_4793 & ic_tag_valid_out_0_122; // @[ifu_mem_ctl.scala 696:10] + wire _T_9367 = _T_9366 | _T_9235; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_123; // @[Reg.scala 27:20] - wire _T_9237 = _T_4794 & ic_tag_valid_out_0_123; // @[ifu_mem_ctl.scala 697:10] - wire _T_9368 = _T_9367 | _T_9237; // @[ifu_mem_ctl.scala 697:91] + wire _T_9237 = _T_4794 & ic_tag_valid_out_0_123; // @[ifu_mem_ctl.scala 696:10] + wire _T_9368 = _T_9367 | _T_9237; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_124; // @[Reg.scala 27:20] - wire _T_9239 = _T_4795 & ic_tag_valid_out_0_124; // @[ifu_mem_ctl.scala 697:10] - wire _T_9369 = _T_9368 | _T_9239; // @[ifu_mem_ctl.scala 697:91] + wire _T_9239 = _T_4795 & ic_tag_valid_out_0_124; // @[ifu_mem_ctl.scala 696:10] + wire _T_9369 = _T_9368 | _T_9239; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_125; // @[Reg.scala 27:20] - wire _T_9241 = _T_4796 & ic_tag_valid_out_0_125; // @[ifu_mem_ctl.scala 697:10] - wire _T_9370 = _T_9369 | _T_9241; // @[ifu_mem_ctl.scala 697:91] + wire _T_9241 = _T_4796 & ic_tag_valid_out_0_125; // @[ifu_mem_ctl.scala 696:10] + wire _T_9370 = _T_9369 | _T_9241; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_126; // @[Reg.scala 27:20] - wire _T_9243 = _T_4797 & ic_tag_valid_out_0_126; // @[ifu_mem_ctl.scala 697:10] - wire _T_9371 = _T_9370 | _T_9243; // @[ifu_mem_ctl.scala 697:91] + wire _T_9243 = _T_4797 & ic_tag_valid_out_0_126; // @[ifu_mem_ctl.scala 696:10] + wire _T_9371 = _T_9370 | _T_9243; // @[ifu_mem_ctl.scala 696:91] reg ic_tag_valid_out_0_127; // @[Reg.scala 27:20] - wire _T_9245 = _T_4798 & ic_tag_valid_out_0_127; // @[ifu_mem_ctl.scala 697:10] - wire _T_9372 = _T_9371 | _T_9245; // @[ifu_mem_ctl.scala 697:91] + wire _T_9245 = _T_4798 & ic_tag_valid_out_0_127; // @[ifu_mem_ctl.scala 696:10] + wire _T_9372 = _T_9371 | _T_9245; // @[ifu_mem_ctl.scala 696:91] wire [1:0] ic_tag_valid_unq = {_T_9755,_T_9372}; // @[Cat.scala 29:58] - reg [1:0] ic_debug_way_ff; // @[ifu_mem_ctl.scala 768:53] - reg ic_debug_rd_en_ff; // @[ifu_mem_ctl.scala 770:54] + reg [1:0] ic_debug_way_ff; // @[ifu_mem_ctl.scala 767:53] + reg ic_debug_rd_en_ff; // @[ifu_mem_ctl.scala 769:54] wire [1:0] _T_9795 = ic_debug_rd_en_ff ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_9796 = ic_debug_way_ff & _T_9795; // @[ifu_mem_ctl.scala 751:67] - wire [1:0] _T_9797 = ic_tag_valid_unq & _T_9796; // @[ifu_mem_ctl.scala 751:48] - wire ic_debug_tag_val_rd_out = |_T_9797; // @[ifu_mem_ctl.scala 751:115] + wire [1:0] _T_9796 = ic_debug_way_ff & _T_9795; // @[ifu_mem_ctl.scala 750:67] + wire [1:0] _T_9797 = ic_tag_valid_unq & _T_9796; // @[ifu_mem_ctl.scala 750:48] + wire ic_debug_tag_val_rd_out = |_T_9797; // @[ifu_mem_ctl.scala 750:115] wire [70:0] _T_1211 = {2'h0,io_ic_tag_debug_rd_data[25:21],32'h0,io_ic_tag_debug_rd_data[20:0],6'h0,way_status,3'h0,ic_debug_tag_val_rd_out}; // @[Cat.scala 29:58] reg [70:0] _T_1212; // @[ifu_mem_ctl.scala 263:76] wire _T_1250 = ~ifu_byp_data_err_new; // @[ifu_mem_ctl.scala 279:98] @@ -3324,7 +3324,7 @@ module ifu_mem_ctl( wire [79:0] _GEN_438 = {{16'd0}, _T_1266}; // @[ifu_mem_ctl.scala 292:88] wire [79:0] ic_premux_data_temp = _GEN_438 | _T_1269; // @[ifu_mem_ctl.scala 292:88] wire fetch_req_f_qual = io_ic_hit_f & _T_319; // @[ifu_mem_ctl.scala 299:38] - reg ifc_region_acc_fault_memory_f; // @[ifu_mem_ctl.scala 784:66] + reg ifc_region_acc_fault_memory_f; // @[ifu_mem_ctl.scala 783:66] wire [1:0] _T_1277 = ifc_region_acc_fault_memory_f ? 2'h3 : 2'h0; // @[ifu_mem_ctl.scala 304:10] wire [1:0] _T_1278 = ifc_region_acc_fault_f ? 2'h2 : _T_1277; // @[ifu_mem_ctl.scala 303:8] wire _T_1280 = fetch_req_f_qual & io_ifu_bp_inst_mask_f; // @[ifu_mem_ctl.scala 305:45] @@ -3335,9 +3335,9 @@ module ifu_mem_ctl( wire _T_1286 = _T_1284 & _T_1285; // @[ifu_mem_ctl.scala 305:114] wire [6:0] _T_1358 = {ic_miss_buff_data_valid_in_7,ic_miss_buff_data_valid_in_6,ic_miss_buff_data_valid_in_5,ic_miss_buff_data_valid_in_4,ic_miss_buff_data_valid_in_3,ic_miss_buff_data_valid_in_2,ic_miss_buff_data_valid_in_1}; // @[Cat.scala 29:58] wire _T_1364 = ic_miss_buff_data_error[0] & _T_1330; // @[ifu_mem_ctl.scala 324:32] - wire _T_2690 = |io_ifu_axi_r_bits_resp; // @[ifu_mem_ctl.scala 558:47] - wire _T_2691 = _T_2690 & _T_13; // @[ifu_mem_ctl.scala 558:50] - wire bus_ifu_wr_data_error = _T_2691 & miss_pending; // @[ifu_mem_ctl.scala 558:68] + wire _T_2690 = |io_ifu_axi_r_bits_resp; // @[ifu_mem_ctl.scala 557:47] + wire _T_2691 = _T_2690 & _T_13; // @[ifu_mem_ctl.scala 557:50] + wire bus_ifu_wr_data_error = _T_2691 & miss_pending; // @[ifu_mem_ctl.scala 557:68] wire ic_miss_buff_data_error_in_0 = write_fill_data_0 ? bus_ifu_wr_data_error : _T_1364; // @[ifu_mem_ctl.scala 323:72] wire _T_1368 = ic_miss_buff_data_error[1] & _T_1330; // @[ifu_mem_ctl.scala 324:32] wire ic_miss_buff_data_error_in_1 = write_fill_data_1 ? bus_ifu_wr_data_error : _T_1368; // @[ifu_mem_ctl.scala 323:72] @@ -3408,52 +3408,52 @@ module ifu_mem_ctl( wire _T_2598 = _T_2597 & io_ifu_axi_ar_ready; // @[ifu_mem_ctl.scala 471:197] wire _T_2599 = _T_2598 & miss_pending; // @[ifu_mem_ctl.scala 471:217] wire _T_2600 = ~_T_2599; // @[ifu_mem_ctl.scala 471:125] - wire ifu_bus_arready = io_ifu_axi_ar_ready & io_ifu_bus_clk_en; // @[ifu_mem_ctl.scala 523:45] - wire _T_2617 = io_ifu_axi_ar_valid & ifu_bus_arready; // @[ifu_mem_ctl.scala 527:35] - wire _T_2618 = _T_2617 & miss_pending; // @[ifu_mem_ctl.scala 527:53] - wire bus_cmd_sent = _T_2618 & _T_2623; // @[ifu_mem_ctl.scala 527:68] + wire ifu_bus_arready = io_ifu_axi_ar_ready & io_ifu_bus_clk_en; // @[ifu_mem_ctl.scala 522:45] + wire _T_2617 = io_ifu_axi_ar_valid & ifu_bus_arready; // @[ifu_mem_ctl.scala 526:35] + wire _T_2618 = _T_2617 & miss_pending; // @[ifu_mem_ctl.scala 526:53] + wire bus_cmd_sent = _T_2618 & _T_2623; // @[ifu_mem_ctl.scala 526:68] wire _T_2603 = ~bus_cmd_sent; // @[ifu_mem_ctl.scala 474:61] wire _T_2604 = _T_2591 & _T_2603; // @[ifu_mem_ctl.scala 474:59] wire [2:0] _T_2608 = ifu_bus_cmd_valid ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_2610 = {miss_addr,bus_rd_addr_count,3'h0}; // @[Cat.scala 29:58] wire [31:0] _T_2612 = ifu_bus_cmd_valid ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - reg ifu_bus_arready_unq_ff; // @[ifu_mem_ctl.scala 510:57] - reg ifu_bus_arvalid_ff; // @[ifu_mem_ctl.scala 512:53] - wire ifu_bus_arready_ff = ifu_bus_arready_unq_ff & bus_ifu_bus_clk_en_ff; // @[ifu_mem_ctl.scala 524:51] - wire _T_2638 = ~scnd_miss_req; // @[ifu_mem_ctl.scala 535:73] - wire _T_2639 = _T_2624 & _T_2638; // @[ifu_mem_ctl.scala 535:71] - wire _T_2641 = last_data_recieved_ff & _T_1330; // @[ifu_mem_ctl.scala 535:114] - wire [2:0] _T_2647 = bus_rd_addr_count + 3'h1; // @[ifu_mem_ctl.scala 540:45] - wire _T_2651 = ifu_bus_cmd_valid & io_ifu_axi_ar_ready; // @[ifu_mem_ctl.scala 543:48] - wire _T_2652 = _T_2651 & miss_pending; // @[ifu_mem_ctl.scala 543:68] - wire bus_inc_cmd_beat_cnt = _T_2652 & _T_2623; // @[ifu_mem_ctl.scala 543:83] - wire bus_reset_cmd_beat_cnt_secondlast = ic_act_miss_f & uncacheable_miss_in; // @[ifu_mem_ctl.scala 545:57] - wire _T_2656 = ~bus_inc_cmd_beat_cnt; // @[ifu_mem_ctl.scala 546:31] - wire _T_2657 = ic_act_miss_f | scnd_miss_req; // @[ifu_mem_ctl.scala 546:71] - wire _T_2658 = _T_2657 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 546:87] - wire _T_2659 = ~_T_2658; // @[ifu_mem_ctl.scala 546:55] - wire bus_hold_cmd_beat_cnt = _T_2656 & _T_2659; // @[ifu_mem_ctl.scala 546:53] - wire _T_2660 = bus_inc_cmd_beat_cnt | ic_act_miss_f; // @[ifu_mem_ctl.scala 547:46] - wire bus_cmd_beat_en = _T_2660 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 547:62] - wire [2:0] _T_2663 = bus_cmd_beat_count + 3'h1; // @[ifu_mem_ctl.scala 549:46] + reg ifu_bus_arready_unq_ff; // @[ifu_mem_ctl.scala 509:57] + reg ifu_bus_arvalid_ff; // @[ifu_mem_ctl.scala 511:53] + wire ifu_bus_arready_ff = ifu_bus_arready_unq_ff & bus_ifu_bus_clk_en_ff; // @[ifu_mem_ctl.scala 523:51] + wire _T_2638 = ~scnd_miss_req; // @[ifu_mem_ctl.scala 534:73] + wire _T_2639 = _T_2624 & _T_2638; // @[ifu_mem_ctl.scala 534:71] + wire _T_2641 = last_data_recieved_ff & _T_1330; // @[ifu_mem_ctl.scala 534:114] + wire [2:0] _T_2647 = bus_rd_addr_count + 3'h1; // @[ifu_mem_ctl.scala 539:45] + wire _T_2651 = ifu_bus_cmd_valid & io_ifu_axi_ar_ready; // @[ifu_mem_ctl.scala 542:48] + wire _T_2652 = _T_2651 & miss_pending; // @[ifu_mem_ctl.scala 542:68] + wire bus_inc_cmd_beat_cnt = _T_2652 & _T_2623; // @[ifu_mem_ctl.scala 542:83] + wire bus_reset_cmd_beat_cnt_secondlast = ic_act_miss_f & uncacheable_miss_in; // @[ifu_mem_ctl.scala 544:57] + wire _T_2656 = ~bus_inc_cmd_beat_cnt; // @[ifu_mem_ctl.scala 545:31] + wire _T_2657 = ic_act_miss_f | scnd_miss_req; // @[ifu_mem_ctl.scala 545:71] + wire _T_2658 = _T_2657 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 545:87] + wire _T_2659 = ~_T_2658; // @[ifu_mem_ctl.scala 545:55] + wire bus_hold_cmd_beat_cnt = _T_2656 & _T_2659; // @[ifu_mem_ctl.scala 545:53] + wire _T_2660 = bus_inc_cmd_beat_cnt | ic_act_miss_f; // @[ifu_mem_ctl.scala 546:46] + wire bus_cmd_beat_en = _T_2660 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 546:62] + wire [2:0] _T_2663 = bus_cmd_beat_count + 3'h1; // @[ifu_mem_ctl.scala 548:46] wire [2:0] _T_2665 = bus_reset_cmd_beat_cnt_secondlast ? 3'h6 : 3'h0; // @[Mux.scala 27:72] wire [2:0] _T_2666 = bus_inc_cmd_beat_cnt ? _T_2663 : 3'h0; // @[Mux.scala 27:72] wire [2:0] _T_2667 = bus_hold_cmd_beat_cnt ? bus_cmd_beat_count : 3'h0; // @[Mux.scala 27:72] wire [2:0] _T_2669 = _T_2665 | _T_2666; // @[Mux.scala 27:72] wire [2:0] bus_new_cmd_beat_count = _T_2669 | _T_2667; // @[Mux.scala 27:72] - reg ifc_dma_access_ok_prev; // @[ifu_mem_ctl.scala 561:62] - wire _T_2698 = ~iccm_correct_ecc; // @[ifu_mem_ctl.scala 566:50] - wire _T_2699 = io_ifc_dma_access_ok & _T_2698; // @[ifu_mem_ctl.scala 566:47] - wire _T_2700 = ~io_iccm_dma_sb_error; // @[ifu_mem_ctl.scala 566:70] - wire _T_2704 = _T_2699 & ifc_dma_access_ok_prev; // @[ifu_mem_ctl.scala 567:72] - wire _T_2705 = perr_state == 3'h0; // @[ifu_mem_ctl.scala 567:111] - wire _T_2706 = _T_2704 & _T_2705; // @[ifu_mem_ctl.scala 567:97] - wire ifc_dma_access_q_ok = _T_2706 & _T_2700; // @[ifu_mem_ctl.scala 567:127] - wire _T_2709 = ifc_dma_access_q_ok & io_dma_mem_ctl_dma_iccm_req; // @[ifu_mem_ctl.scala 570:40] - wire _T_2710 = _T_2709 & io_dma_mem_ctl_dma_mem_write; // @[ifu_mem_ctl.scala 570:70] - wire _T_2713 = ~io_dma_mem_ctl_dma_mem_write; // @[ifu_mem_ctl.scala 571:72] - wire _T_2714 = _T_2709 & _T_2713; // @[ifu_mem_ctl.scala 571:70] - wire _T_2715 = io_ifc_iccm_access_bf & io_ifc_fetch_req_bf; // @[ifu_mem_ctl.scala 571:128] + reg ifc_dma_access_ok_prev; // @[ifu_mem_ctl.scala 560:62] + wire _T_2698 = ~iccm_correct_ecc; // @[ifu_mem_ctl.scala 565:50] + wire _T_2699 = io_ifc_dma_access_ok & _T_2698; // @[ifu_mem_ctl.scala 565:47] + wire _T_2700 = ~io_iccm_dma_sb_error; // @[ifu_mem_ctl.scala 565:70] + wire _T_2704 = _T_2699 & ifc_dma_access_ok_prev; // @[ifu_mem_ctl.scala 566:72] + wire _T_2705 = perr_state == 3'h0; // @[ifu_mem_ctl.scala 566:111] + wire _T_2706 = _T_2704 & _T_2705; // @[ifu_mem_ctl.scala 566:97] + wire ifc_dma_access_q_ok = _T_2706 & _T_2700; // @[ifu_mem_ctl.scala 566:127] + wire _T_2709 = ifc_dma_access_q_ok & io_dma_mem_ctl_dma_iccm_req; // @[ifu_mem_ctl.scala 569:40] + wire _T_2710 = _T_2709 & io_dma_mem_ctl_dma_mem_write; // @[ifu_mem_ctl.scala 569:70] + wire _T_2713 = ~io_dma_mem_ctl_dma_mem_write; // @[ifu_mem_ctl.scala 570:72] + wire _T_2714 = _T_2709 & _T_2713; // @[ifu_mem_ctl.scala 570:70] + wire _T_2715 = io_ifc_iccm_access_bf & io_ifc_fetch_req_bf; // @[ifu_mem_ctl.scala 570:128] wire [2:0] _T_2720 = io_dma_mem_ctl_dma_iccm_req ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] wire _T_2741 = io_dma_mem_ctl_dma_mem_wdata[32] ^ io_dma_mem_ctl_dma_mem_wdata[33]; // @[lib.scala 119:74] wire _T_2742 = _T_2741 ^ io_dma_mem_ctl_dma_mem_wdata[35]; // @[lib.scala 119:74] @@ -3633,12 +3633,12 @@ module ifu_mem_ctl( wire _T_3088 = _T_3086 ^ _T_3087; // @[lib.scala 127:18] wire [6:0] _T_3089 = {_T_3088,_T_3080,_T_3069,_T_3040,_T_3011,_T_2976,_T_2941}; // @[Cat.scala 29:58] wire [13:0] dma_mem_ecc = {_T_2904,_T_2896,_T_2885,_T_2856,_T_2827,_T_2792,_T_2757,_T_3089}; // @[Cat.scala 29:58] - wire _T_3091 = ~_T_2709; // @[ifu_mem_ctl.scala 577:45] - wire _T_3092 = iccm_correct_ecc & _T_3091; // @[ifu_mem_ctl.scala 577:43] + wire _T_3091 = ~_T_2709; // @[ifu_mem_ctl.scala 576:45] + wire _T_3092 = iccm_correct_ecc & _T_3091; // @[ifu_mem_ctl.scala 576:43] reg [38:0] iccm_ecc_corr_data_ff; // @[Reg.scala 27:20] wire [77:0] _T_3093 = {iccm_ecc_corr_data_ff,iccm_ecc_corr_data_ff}; // @[Cat.scala 29:58] wire [77:0] _T_3100 = {dma_mem_ecc[13:7],io_dma_mem_ctl_dma_mem_wdata[63:32],dma_mem_ecc[6:0],io_dma_mem_ctl_dma_mem_wdata[31:0]}; // @[Cat.scala 29:58] - reg [1:0] dma_mem_addr_ff; // @[ifu_mem_ctl.scala 591:53] + reg [1:0] dma_mem_addr_ff; // @[ifu_mem_ctl.scala 590:53] wire _T_3435 = _T_3347[5:0] == 6'h27; // @[lib.scala 199:41] wire _T_3433 = _T_3347[5:0] == 6'h26; // @[lib.scala 199:41] wire _T_3431 = _T_3347[5:0] == 6'h25; // @[lib.scala 199:41] @@ -3737,1354 +3737,1354 @@ module ifu_mem_ctl( wire [38:0] _T_3881 = _T_3880 ^ _T_3841; // @[lib.scala 202:76] wire [38:0] _T_3882 = _T_3736 ? _T_3881 : _T_3841; // @[lib.scala 202:31] wire [31:0] iccm_corrected_data_1 = {_T_3882[37:32],_T_3882[30:16],_T_3882[14:8],_T_3882[6:4],_T_3882[2]}; // @[Cat.scala 29:58] - wire [31:0] iccm_dma_rdata_1_muxed = dma_mem_addr_ff[0] ? iccm_corrected_data_0 : iccm_corrected_data_1; // @[ifu_mem_ctl.scala 583:35] + wire [31:0] iccm_dma_rdata_1_muxed = dma_mem_addr_ff[0] ? iccm_corrected_data_0 : iccm_corrected_data_1; // @[ifu_mem_ctl.scala 582:35] wire _T_3740 = ~_T_3732[6]; // @[lib.scala 195:55] wire _T_3741 = _T_3734 & _T_3740; // @[lib.scala 195:53] wire _T_3355 = ~_T_3347[6]; // @[lib.scala 195:55] wire _T_3356 = _T_3349 & _T_3355; // @[lib.scala 195:53] wire [1:0] iccm_double_ecc_error = {_T_3741,_T_3356}; // @[Cat.scala 29:58] - wire iccm_dma_ecc_error_in = |iccm_double_ecc_error; // @[ifu_mem_ctl.scala 585:53] + wire iccm_dma_ecc_error_in = |iccm_double_ecc_error; // @[ifu_mem_ctl.scala 584:53] wire [63:0] _T_3104 = {io_dma_mem_ctl_dma_mem_addr,io_dma_mem_ctl_dma_mem_addr}; // @[Cat.scala 29:58] wire [63:0] _T_3105 = {iccm_dma_rdata_1_muxed,_T_3497[37:32],_T_3497[30:16],_T_3497[14:8],_T_3497[6:4],_T_3497[2]}; // @[Cat.scala 29:58] - reg [2:0] dma_mem_tag_ff; // @[ifu_mem_ctl.scala 587:54] - reg [2:0] iccm_dma_rtag_temp; // @[ifu_mem_ctl.scala 588:74] - reg iccm_dma_rvalid_temp; // @[ifu_mem_ctl.scala 593:76] - reg iccm_dma_ecc_error; // @[ifu_mem_ctl.scala 595:74] - reg [63:0] iccm_dma_rdata_temp; // @[ifu_mem_ctl.scala 597:75] - wire _T_3110 = _T_2709 & _T_2698; // @[ifu_mem_ctl.scala 600:77] - wire _T_3114 = _T_3091 & iccm_correct_ecc; // @[ifu_mem_ctl.scala 601:62] + reg [2:0] dma_mem_tag_ff; // @[ifu_mem_ctl.scala 586:54] + reg [2:0] iccm_dma_rtag_temp; // @[ifu_mem_ctl.scala 587:74] + reg iccm_dma_rvalid_temp; // @[ifu_mem_ctl.scala 592:76] + reg iccm_dma_ecc_error; // @[ifu_mem_ctl.scala 594:74] + reg [63:0] iccm_dma_rdata_temp; // @[ifu_mem_ctl.scala 596:75] + wire _T_3110 = _T_2709 & _T_2698; // @[ifu_mem_ctl.scala 599:77] + wire _T_3114 = _T_3091 & iccm_correct_ecc; // @[ifu_mem_ctl.scala 600:62] reg [13:0] iccm_ecc_corr_index_ff; // @[Reg.scala 27:20] wire [14:0] _T_3115 = {iccm_ecc_corr_index_ff,1'h0}; // @[Cat.scala 29:58] - wire [14:0] _T_3117 = _T_3114 ? _T_3115 : io_ifc_fetch_addr_bf[14:0]; // @[ifu_mem_ctl.scala 601:8] + wire [14:0] _T_3117 = _T_3114 ? _T_3115 : io_ifc_fetch_addr_bf[14:0]; // @[ifu_mem_ctl.scala 600:8] wire _T_3509 = _T_3347 == 7'h40; // @[lib.scala 205:62] wire _T_3510 = _T_3497[38] ^ _T_3509; // @[lib.scala 205:44] wire [6:0] iccm_corrected_ecc_0 = {_T_3510,_T_3497[31],_T_3497[15],_T_3497[7],_T_3497[3],_T_3497[1:0]}; // @[Cat.scala 29:58] wire _T_3894 = _T_3732 == 7'h40; // @[lib.scala 205:62] wire _T_3895 = _T_3882[38] ^ _T_3894; // @[lib.scala 205:44] wire [6:0] iccm_corrected_ecc_1 = {_T_3895,_T_3882[31],_T_3882[15],_T_3882[7],_T_3882[3],_T_3882[1:0]}; // @[Cat.scala 29:58] - wire _T_3911 = _T_3 & ifc_iccm_access_f; // @[ifu_mem_ctl.scala 613:75] - wire [31:0] iccm_corrected_data_f_mux = iccm_single_ecc_error[0] ? iccm_corrected_data_0 : iccm_corrected_data_1; // @[ifu_mem_ctl.scala 615:38] - wire [6:0] iccm_corrected_ecc_f_mux = iccm_single_ecc_error[0] ? iccm_corrected_ecc_0 : iccm_corrected_ecc_1; // @[ifu_mem_ctl.scala 616:37] - reg iccm_rd_ecc_single_err_ff; // @[ifu_mem_ctl.scala 624:62] - wire _T_3919 = ~iccm_rd_ecc_single_err_ff; // @[ifu_mem_ctl.scala 618:93] - wire _T_3920 = io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err & _T_3919; // @[ifu_mem_ctl.scala 618:91] - wire _T_3922 = _T_3920 & _T_319; // @[ifu_mem_ctl.scala 618:121] - wire iccm_ecc_write_status = _T_3922 | io_iccm_dma_sb_error; // @[ifu_mem_ctl.scala 618:144] - wire _T_3923 = io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err | iccm_rd_ecc_single_err_ff; // @[ifu_mem_ctl.scala 619:84] - reg [13:0] iccm_rw_addr_f; // @[ifu_mem_ctl.scala 623:51] - wire [13:0] _T_3928 = iccm_rw_addr_f + 14'h1; // @[ifu_mem_ctl.scala 622:102] + wire _T_3911 = _T_3 & ifc_iccm_access_f; // @[ifu_mem_ctl.scala 612:75] + wire [31:0] iccm_corrected_data_f_mux = iccm_single_ecc_error[0] ? iccm_corrected_data_0 : iccm_corrected_data_1; // @[ifu_mem_ctl.scala 614:38] + wire [6:0] iccm_corrected_ecc_f_mux = iccm_single_ecc_error[0] ? iccm_corrected_ecc_0 : iccm_corrected_ecc_1; // @[ifu_mem_ctl.scala 615:37] + reg iccm_rd_ecc_single_err_ff; // @[ifu_mem_ctl.scala 623:62] + wire _T_3919 = ~iccm_rd_ecc_single_err_ff; // @[ifu_mem_ctl.scala 617:93] + wire _T_3920 = io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err & _T_3919; // @[ifu_mem_ctl.scala 617:91] + wire _T_3922 = _T_3920 & _T_319; // @[ifu_mem_ctl.scala 617:121] + wire iccm_ecc_write_status = _T_3922 | io_iccm_dma_sb_error; // @[ifu_mem_ctl.scala 617:144] + wire _T_3923 = io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err | iccm_rd_ecc_single_err_ff; // @[ifu_mem_ctl.scala 618:84] + reg [13:0] iccm_rw_addr_f; // @[ifu_mem_ctl.scala 622:51] + wire [13:0] _T_3928 = iccm_rw_addr_f + 14'h1; // @[ifu_mem_ctl.scala 621:102] wire [38:0] _T_3932 = {iccm_corrected_ecc_f_mux,iccm_corrected_data_f_mux}; // @[Cat.scala 29:58] - wire _T_3937 = ~io_ifc_fetch_uncacheable_bf; // @[ifu_mem_ctl.scala 627:41] - wire _T_3938 = io_ifc_fetch_req_bf & _T_3937; // @[ifu_mem_ctl.scala 627:39] - wire _T_3939 = ~io_ifc_iccm_access_bf; // @[ifu_mem_ctl.scala 627:72] - wire _T_3940 = _T_3938 & _T_3939; // @[ifu_mem_ctl.scala 627:70] - wire _T_3942 = ~miss_state_en; // @[ifu_mem_ctl.scala 628:34] - wire _T_3943 = _T_2268 & _T_3942; // @[ifu_mem_ctl.scala 628:32] - wire _T_3946 = _T_2284 & _T_3942; // @[ifu_mem_ctl.scala 629:37] - wire _T_3947 = _T_3943 | _T_3946; // @[ifu_mem_ctl.scala 628:88] - wire _T_3948 = miss_state == 3'h7; // @[ifu_mem_ctl.scala 630:19] - wire _T_3950 = _T_3948 & _T_3942; // @[ifu_mem_ctl.scala 630:41] - wire _T_3951 = _T_3947 | _T_3950; // @[ifu_mem_ctl.scala 629:88] - wire _T_3952 = miss_state == 3'h3; // @[ifu_mem_ctl.scala 631:19] - wire _T_3954 = _T_3952 & _T_3942; // @[ifu_mem_ctl.scala 631:35] - wire _T_3955 = _T_3951 | _T_3954; // @[ifu_mem_ctl.scala 630:88] - wire _T_3958 = _T_2283 & _T_3942; // @[ifu_mem_ctl.scala 632:38] - wire _T_3959 = _T_3955 | _T_3958; // @[ifu_mem_ctl.scala 631:88] - wire _T_3961 = _T_2284 & miss_state_en; // @[ifu_mem_ctl.scala 633:37] - wire _T_3962 = miss_nxtstate == 3'h3; // @[ifu_mem_ctl.scala 633:71] - wire _T_3963 = _T_3961 & _T_3962; // @[ifu_mem_ctl.scala 633:54] - wire _T_3964 = _T_3959 | _T_3963; // @[ifu_mem_ctl.scala 632:57] - wire _T_3965 = ~_T_3964; // @[ifu_mem_ctl.scala 628:5] - wire _T_3966 = _T_3940 & _T_3965; // @[ifu_mem_ctl.scala 627:96] - wire _T_3967 = io_ifc_fetch_req_bf & io_exu_flush_final; // @[ifu_mem_ctl.scala 634:28] - wire _T_3969 = _T_3967 & _T_3937; // @[ifu_mem_ctl.scala 634:50] - wire _T_3971 = _T_3969 & _T_3939; // @[ifu_mem_ctl.scala 634:81] + wire _T_3937 = ~io_ifc_fetch_uncacheable_bf; // @[ifu_mem_ctl.scala 626:41] + wire _T_3938 = io_ifc_fetch_req_bf & _T_3937; // @[ifu_mem_ctl.scala 626:39] + wire _T_3939 = ~io_ifc_iccm_access_bf; // @[ifu_mem_ctl.scala 626:72] + wire _T_3940 = _T_3938 & _T_3939; // @[ifu_mem_ctl.scala 626:70] + wire _T_3942 = ~miss_state_en; // @[ifu_mem_ctl.scala 627:34] + wire _T_3943 = _T_2268 & _T_3942; // @[ifu_mem_ctl.scala 627:32] + wire _T_3946 = _T_2284 & _T_3942; // @[ifu_mem_ctl.scala 628:37] + wire _T_3947 = _T_3943 | _T_3946; // @[ifu_mem_ctl.scala 627:88] + wire _T_3948 = miss_state == 3'h7; // @[ifu_mem_ctl.scala 629:19] + wire _T_3950 = _T_3948 & _T_3942; // @[ifu_mem_ctl.scala 629:41] + wire _T_3951 = _T_3947 | _T_3950; // @[ifu_mem_ctl.scala 628:88] + wire _T_3952 = miss_state == 3'h3; // @[ifu_mem_ctl.scala 630:19] + wire _T_3954 = _T_3952 & _T_3942; // @[ifu_mem_ctl.scala 630:35] + wire _T_3955 = _T_3951 | _T_3954; // @[ifu_mem_ctl.scala 629:88] + wire _T_3958 = _T_2283 & _T_3942; // @[ifu_mem_ctl.scala 631:38] + wire _T_3959 = _T_3955 | _T_3958; // @[ifu_mem_ctl.scala 630:88] + wire _T_3961 = _T_2284 & miss_state_en; // @[ifu_mem_ctl.scala 632:37] + wire _T_3962 = miss_nxtstate == 3'h3; // @[ifu_mem_ctl.scala 632:71] + wire _T_3963 = _T_3961 & _T_3962; // @[ifu_mem_ctl.scala 632:54] + wire _T_3964 = _T_3959 | _T_3963; // @[ifu_mem_ctl.scala 631:57] + wire _T_3965 = ~_T_3964; // @[ifu_mem_ctl.scala 627:5] + wire _T_3966 = _T_3940 & _T_3965; // @[ifu_mem_ctl.scala 626:96] + wire _T_3967 = io_ifc_fetch_req_bf & io_exu_flush_final; // @[ifu_mem_ctl.scala 633:28] + wire _T_3969 = _T_3967 & _T_3937; // @[ifu_mem_ctl.scala 633:50] + wire _T_3971 = _T_3969 & _T_3939; // @[ifu_mem_ctl.scala 633:81] wire [1:0] _T_3974 = write_ic_16_bytes ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire _T_9780 = bus_ifu_wr_en_ff_q & replace_way_mb_any_1; // @[ifu_mem_ctl.scala 728:74] - wire bus_wren_1 = _T_9780 & miss_pending; // @[ifu_mem_ctl.scala 728:98] - wire _T_9779 = bus_ifu_wr_en_ff_q & replace_way_mb_any_0; // @[ifu_mem_ctl.scala 728:74] - wire bus_wren_0 = _T_9779 & miss_pending; // @[ifu_mem_ctl.scala 728:98] + wire _T_9780 = bus_ifu_wr_en_ff_q & replace_way_mb_any_1; // @[ifu_mem_ctl.scala 727:74] + wire bus_wren_1 = _T_9780 & miss_pending; // @[ifu_mem_ctl.scala 727:98] + wire _T_9779 = bus_ifu_wr_en_ff_q & replace_way_mb_any_0; // @[ifu_mem_ctl.scala 727:74] + wire bus_wren_0 = _T_9779 & miss_pending; // @[ifu_mem_ctl.scala 727:98] wire [1:0] bus_ic_wr_en = {bus_wren_1,bus_wren_0}; // @[Cat.scala 29:58] - wire _T_3980 = ~_T_108; // @[ifu_mem_ctl.scala 637:106] - wire _T_3981 = _T_2268 & _T_3980; // @[ifu_mem_ctl.scala 637:104] - wire _T_3982 = _T_2284 | _T_3981; // @[ifu_mem_ctl.scala 637:77] - wire _T_3986 = ~_T_51; // @[ifu_mem_ctl.scala 637:172] - wire _T_3987 = _T_3982 & _T_3986; // @[ifu_mem_ctl.scala 637:170] - wire _T_3988 = ~_T_3987; // @[ifu_mem_ctl.scala 637:44] - wire _T_3992 = reset_ic_in | reset_ic_ff; // @[ifu_mem_ctl.scala 640:64] - wire _T_3993 = ~_T_3992; // @[ifu_mem_ctl.scala 640:50] - wire _T_3994 = _T_276 & _T_3993; // @[ifu_mem_ctl.scala 640:48] - wire _T_3995 = ~reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 640:81] - wire ic_valid = _T_3994 & _T_3995; // @[ifu_mem_ctl.scala 640:79] - wire _T_3997 = debug_c1_clken & io_ic_debug_tag_array; // @[ifu_mem_ctl.scala 641:82] - reg [6:0] ifu_status_wr_addr_ff; // @[ifu_mem_ctl.scala 644:14] - wire _T_4000 = io_ic_debug_wr_en & io_ic_debug_tag_array; // @[ifu_mem_ctl.scala 647:74] - wire _T_9777 = bus_ifu_wr_en_ff_q & last_beat; // @[ifu_mem_ctl.scala 727:45] - wire way_status_wr_en = _T_9777 | ic_act_hit_f; // @[ifu_mem_ctl.scala 727:58] - reg way_status_wr_en_ff; // @[ifu_mem_ctl.scala 649:14] - wire way_status_hit_new = io_ic_rd_hit[0]; // @[ifu_mem_ctl.scala 723:41] - reg way_status_new_ff; // @[ifu_mem_ctl.scala 655:14] - wire _T_4020 = ifu_status_wr_addr_ff[2:0] == 3'h0; // @[ifu_mem_ctl.scala 661:128] - wire _T_4021 = _T_4020 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 661:136] - wire _T_4024 = ifu_status_wr_addr_ff[2:0] == 3'h1; // @[ifu_mem_ctl.scala 661:128] - wire _T_4025 = _T_4024 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 661:136] - wire _T_4028 = ifu_status_wr_addr_ff[2:0] == 3'h2; // @[ifu_mem_ctl.scala 661:128] - wire _T_4029 = _T_4028 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 661:136] - wire _T_4032 = ifu_status_wr_addr_ff[2:0] == 3'h3; // @[ifu_mem_ctl.scala 661:128] - wire _T_4033 = _T_4032 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 661:136] - wire _T_4036 = ifu_status_wr_addr_ff[2:0] == 3'h4; // @[ifu_mem_ctl.scala 661:128] - wire _T_4037 = _T_4036 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 661:136] - wire _T_4040 = ifu_status_wr_addr_ff[2:0] == 3'h5; // @[ifu_mem_ctl.scala 661:128] - wire _T_4041 = _T_4040 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 661:136] - wire _T_4044 = ifu_status_wr_addr_ff[2:0] == 3'h6; // @[ifu_mem_ctl.scala 661:128] - wire _T_4045 = _T_4044 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 661:136] - wire _T_4048 = ifu_status_wr_addr_ff[2:0] == 3'h7; // @[ifu_mem_ctl.scala 661:128] - wire _T_4049 = _T_4048 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 661:136] - wire _T_9783 = _T_100 & replace_way_mb_any_1; // @[ifu_mem_ctl.scala 730:84] - wire _T_9784 = _T_9783 & miss_pending; // @[ifu_mem_ctl.scala 730:108] - wire bus_wren_last_1 = _T_9784 & bus_last_data_beat; // @[ifu_mem_ctl.scala 730:123] - wire wren_reset_miss_1 = replace_way_mb_any_1 & reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 731:84] - wire _T_9786 = bus_wren_last_1 | wren_reset_miss_1; // @[ifu_mem_ctl.scala 732:73] - wire _T_9781 = _T_100 & replace_way_mb_any_0; // @[ifu_mem_ctl.scala 730:84] - wire _T_9782 = _T_9781 & miss_pending; // @[ifu_mem_ctl.scala 730:108] - wire bus_wren_last_0 = _T_9782 & bus_last_data_beat; // @[ifu_mem_ctl.scala 730:123] - wire wren_reset_miss_0 = replace_way_mb_any_0 & reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 731:84] - wire _T_9785 = bus_wren_last_0 | wren_reset_miss_0; // @[ifu_mem_ctl.scala 732:73] + wire _T_3980 = ~_T_108; // @[ifu_mem_ctl.scala 636:106] + wire _T_3981 = _T_2268 & _T_3980; // @[ifu_mem_ctl.scala 636:104] + wire _T_3982 = _T_2284 | _T_3981; // @[ifu_mem_ctl.scala 636:77] + wire _T_3986 = ~_T_51; // @[ifu_mem_ctl.scala 636:172] + wire _T_3987 = _T_3982 & _T_3986; // @[ifu_mem_ctl.scala 636:170] + wire _T_3988 = ~_T_3987; // @[ifu_mem_ctl.scala 636:44] + wire _T_3992 = reset_ic_in | reset_ic_ff; // @[ifu_mem_ctl.scala 639:64] + wire _T_3993 = ~_T_3992; // @[ifu_mem_ctl.scala 639:50] + wire _T_3994 = _T_276 & _T_3993; // @[ifu_mem_ctl.scala 639:48] + wire _T_3995 = ~reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 639:81] + wire ic_valid = _T_3994 & _T_3995; // @[ifu_mem_ctl.scala 639:79] + wire _T_3997 = debug_c1_clken & io_ic_debug_tag_array; // @[ifu_mem_ctl.scala 640:82] + reg [6:0] ifu_status_wr_addr_ff; // @[ifu_mem_ctl.scala 643:14] + wire _T_4000 = io_ic_debug_wr_en & io_ic_debug_tag_array; // @[ifu_mem_ctl.scala 646:74] + wire _T_9777 = bus_ifu_wr_en_ff_q & last_beat; // @[ifu_mem_ctl.scala 726:45] + wire way_status_wr_en = _T_9777 | ic_act_hit_f; // @[ifu_mem_ctl.scala 726:58] + reg way_status_wr_en_ff; // @[ifu_mem_ctl.scala 648:14] + wire way_status_hit_new = io_ic_rd_hit[0]; // @[ifu_mem_ctl.scala 722:41] + reg way_status_new_ff; // @[ifu_mem_ctl.scala 654:14] + wire _T_4020 = ifu_status_wr_addr_ff[2:0] == 3'h0; // @[ifu_mem_ctl.scala 660:128] + wire _T_4021 = _T_4020 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 660:136] + wire _T_4024 = ifu_status_wr_addr_ff[2:0] == 3'h1; // @[ifu_mem_ctl.scala 660:128] + wire _T_4025 = _T_4024 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 660:136] + wire _T_4028 = ifu_status_wr_addr_ff[2:0] == 3'h2; // @[ifu_mem_ctl.scala 660:128] + wire _T_4029 = _T_4028 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 660:136] + wire _T_4032 = ifu_status_wr_addr_ff[2:0] == 3'h3; // @[ifu_mem_ctl.scala 660:128] + wire _T_4033 = _T_4032 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 660:136] + wire _T_4036 = ifu_status_wr_addr_ff[2:0] == 3'h4; // @[ifu_mem_ctl.scala 660:128] + wire _T_4037 = _T_4036 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 660:136] + wire _T_4040 = ifu_status_wr_addr_ff[2:0] == 3'h5; // @[ifu_mem_ctl.scala 660:128] + wire _T_4041 = _T_4040 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 660:136] + wire _T_4044 = ifu_status_wr_addr_ff[2:0] == 3'h6; // @[ifu_mem_ctl.scala 660:128] + wire _T_4045 = _T_4044 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 660:136] + wire _T_4048 = ifu_status_wr_addr_ff[2:0] == 3'h7; // @[ifu_mem_ctl.scala 660:128] + wire _T_4049 = _T_4048 & way_status_wr_en_ff; // @[ifu_mem_ctl.scala 660:136] + wire _T_9783 = _T_100 & replace_way_mb_any_1; // @[ifu_mem_ctl.scala 729:84] + wire _T_9784 = _T_9783 & miss_pending; // @[ifu_mem_ctl.scala 729:108] + wire bus_wren_last_1 = _T_9784 & bus_last_data_beat; // @[ifu_mem_ctl.scala 729:123] + wire wren_reset_miss_1 = replace_way_mb_any_1 & reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 730:84] + wire _T_9786 = bus_wren_last_1 | wren_reset_miss_1; // @[ifu_mem_ctl.scala 731:73] + wire _T_9781 = _T_100 & replace_way_mb_any_0; // @[ifu_mem_ctl.scala 729:84] + wire _T_9782 = _T_9781 & miss_pending; // @[ifu_mem_ctl.scala 729:108] + wire bus_wren_last_0 = _T_9782 & bus_last_data_beat; // @[ifu_mem_ctl.scala 729:123] + wire wren_reset_miss_0 = replace_way_mb_any_0 & reset_tag_valid_for_miss; // @[ifu_mem_ctl.scala 730:84] + wire _T_9785 = bus_wren_last_0 | wren_reset_miss_0; // @[ifu_mem_ctl.scala 731:73] wire [1:0] ifu_tag_wren = {_T_9786,_T_9785}; // @[Cat.scala 29:58] wire [1:0] _T_9821 = _T_4000 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] ic_debug_tag_wr_en = _T_9821 & io_ic_debug_way; // @[ifu_mem_ctl.scala 766:90] - reg [1:0] ifu_tag_wren_ff; // @[ifu_mem_ctl.scala 676:14] - reg ic_valid_ff; // @[ifu_mem_ctl.scala 680:14] - wire _T_5063 = ifu_ic_rw_int_addr_ff[6:5] == 2'h0; // @[ifu_mem_ctl.scala 684:78] - wire _T_5065 = _T_5063 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 684:87] - wire _T_5067 = perr_ic_index_ff[6:5] == 2'h0; // @[ifu_mem_ctl.scala 685:70] - wire _T_5069 = _T_5067 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 685:79] - wire _T_5070 = _T_5065 | _T_5069; // @[ifu_mem_ctl.scala 684:109] - wire _T_5071 = _T_5070 | reset_all_tags; // @[ifu_mem_ctl.scala 685:102] - wire _T_5075 = _T_5063 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 684:87] - wire _T_5079 = _T_5067 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 685:79] - wire _T_5080 = _T_5075 | _T_5079; // @[ifu_mem_ctl.scala 684:109] - wire _T_5081 = _T_5080 | reset_all_tags; // @[ifu_mem_ctl.scala 685:102] + wire [1:0] ic_debug_tag_wr_en = _T_9821 & io_ic_debug_way; // @[ifu_mem_ctl.scala 765:90] + reg [1:0] ifu_tag_wren_ff; // @[ifu_mem_ctl.scala 675:14] + reg ic_valid_ff; // @[ifu_mem_ctl.scala 679:14] + wire _T_5063 = ifu_ic_rw_int_addr_ff[6:5] == 2'h0; // @[ifu_mem_ctl.scala 683:78] + wire _T_5065 = _T_5063 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 683:87] + wire _T_5067 = perr_ic_index_ff[6:5] == 2'h0; // @[ifu_mem_ctl.scala 684:70] + wire _T_5069 = _T_5067 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 684:79] + wire _T_5070 = _T_5065 | _T_5069; // @[ifu_mem_ctl.scala 683:109] + wire _T_5071 = _T_5070 | reset_all_tags; // @[ifu_mem_ctl.scala 684:102] + wire _T_5075 = _T_5063 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 683:87] + wire _T_5079 = _T_5067 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 684:79] + wire _T_5080 = _T_5075 | _T_5079; // @[ifu_mem_ctl.scala 683:109] + wire _T_5081 = _T_5080 | reset_all_tags; // @[ifu_mem_ctl.scala 684:102] wire [1:0] tag_valid_clken_0 = {_T_5081,_T_5071}; // @[Cat.scala 29:58] - wire _T_5083 = ifu_ic_rw_int_addr_ff[6:5] == 2'h1; // @[ifu_mem_ctl.scala 684:78] - wire _T_5085 = _T_5083 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 684:87] - wire _T_5087 = perr_ic_index_ff[6:5] == 2'h1; // @[ifu_mem_ctl.scala 685:70] - wire _T_5089 = _T_5087 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 685:79] - wire _T_5090 = _T_5085 | _T_5089; // @[ifu_mem_ctl.scala 684:109] - wire _T_5091 = _T_5090 | reset_all_tags; // @[ifu_mem_ctl.scala 685:102] - wire _T_5095 = _T_5083 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 684:87] - wire _T_5099 = _T_5087 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 685:79] - wire _T_5100 = _T_5095 | _T_5099; // @[ifu_mem_ctl.scala 684:109] - wire _T_5101 = _T_5100 | reset_all_tags; // @[ifu_mem_ctl.scala 685:102] + wire _T_5083 = ifu_ic_rw_int_addr_ff[6:5] == 2'h1; // @[ifu_mem_ctl.scala 683:78] + wire _T_5085 = _T_5083 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 683:87] + wire _T_5087 = perr_ic_index_ff[6:5] == 2'h1; // @[ifu_mem_ctl.scala 684:70] + wire _T_5089 = _T_5087 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 684:79] + wire _T_5090 = _T_5085 | _T_5089; // @[ifu_mem_ctl.scala 683:109] + wire _T_5091 = _T_5090 | reset_all_tags; // @[ifu_mem_ctl.scala 684:102] + wire _T_5095 = _T_5083 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 683:87] + wire _T_5099 = _T_5087 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 684:79] + wire _T_5100 = _T_5095 | _T_5099; // @[ifu_mem_ctl.scala 683:109] + wire _T_5101 = _T_5100 | reset_all_tags; // @[ifu_mem_ctl.scala 684:102] wire [1:0] tag_valid_clken_1 = {_T_5101,_T_5091}; // @[Cat.scala 29:58] - wire _T_5103 = ifu_ic_rw_int_addr_ff[6:5] == 2'h2; // @[ifu_mem_ctl.scala 684:78] - wire _T_5105 = _T_5103 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 684:87] - wire _T_5107 = perr_ic_index_ff[6:5] == 2'h2; // @[ifu_mem_ctl.scala 685:70] - wire _T_5109 = _T_5107 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 685:79] - wire _T_5110 = _T_5105 | _T_5109; // @[ifu_mem_ctl.scala 684:109] - wire _T_5111 = _T_5110 | reset_all_tags; // @[ifu_mem_ctl.scala 685:102] - wire _T_5115 = _T_5103 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 684:87] - wire _T_5119 = _T_5107 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 685:79] - wire _T_5120 = _T_5115 | _T_5119; // @[ifu_mem_ctl.scala 684:109] - wire _T_5121 = _T_5120 | reset_all_tags; // @[ifu_mem_ctl.scala 685:102] + wire _T_5103 = ifu_ic_rw_int_addr_ff[6:5] == 2'h2; // @[ifu_mem_ctl.scala 683:78] + wire _T_5105 = _T_5103 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 683:87] + wire _T_5107 = perr_ic_index_ff[6:5] == 2'h2; // @[ifu_mem_ctl.scala 684:70] + wire _T_5109 = _T_5107 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 684:79] + wire _T_5110 = _T_5105 | _T_5109; // @[ifu_mem_ctl.scala 683:109] + wire _T_5111 = _T_5110 | reset_all_tags; // @[ifu_mem_ctl.scala 684:102] + wire _T_5115 = _T_5103 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 683:87] + wire _T_5119 = _T_5107 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 684:79] + wire _T_5120 = _T_5115 | _T_5119; // @[ifu_mem_ctl.scala 683:109] + wire _T_5121 = _T_5120 | reset_all_tags; // @[ifu_mem_ctl.scala 684:102] wire [1:0] tag_valid_clken_2 = {_T_5121,_T_5111}; // @[Cat.scala 29:58] - wire _T_5123 = ifu_ic_rw_int_addr_ff[6:5] == 2'h3; // @[ifu_mem_ctl.scala 684:78] - wire _T_5125 = _T_5123 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 684:87] - wire _T_5127 = perr_ic_index_ff[6:5] == 2'h3; // @[ifu_mem_ctl.scala 685:70] - wire _T_5129 = _T_5127 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 685:79] - wire _T_5130 = _T_5125 | _T_5129; // @[ifu_mem_ctl.scala 684:109] - wire _T_5131 = _T_5130 | reset_all_tags; // @[ifu_mem_ctl.scala 685:102] - wire _T_5135 = _T_5123 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 684:87] - wire _T_5139 = _T_5127 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 685:79] - wire _T_5140 = _T_5135 | _T_5139; // @[ifu_mem_ctl.scala 684:109] - wire _T_5141 = _T_5140 | reset_all_tags; // @[ifu_mem_ctl.scala 685:102] + wire _T_5123 = ifu_ic_rw_int_addr_ff[6:5] == 2'h3; // @[ifu_mem_ctl.scala 683:78] + wire _T_5125 = _T_5123 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 683:87] + wire _T_5127 = perr_ic_index_ff[6:5] == 2'h3; // @[ifu_mem_ctl.scala 684:70] + wire _T_5129 = _T_5127 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 684:79] + wire _T_5130 = _T_5125 | _T_5129; // @[ifu_mem_ctl.scala 683:109] + wire _T_5131 = _T_5130 | reset_all_tags; // @[ifu_mem_ctl.scala 684:102] + wire _T_5135 = _T_5123 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 683:87] + wire _T_5139 = _T_5127 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 684:79] + wire _T_5140 = _T_5135 | _T_5139; // @[ifu_mem_ctl.scala 683:109] + wire _T_5141 = _T_5140 | reset_all_tags; // @[ifu_mem_ctl.scala 684:102] wire [1:0] tag_valid_clken_3 = {_T_5141,_T_5131}; // @[Cat.scala 29:58] - wire _T_5152 = ic_valid_ff & _T_195; // @[ifu_mem_ctl.scala 693:97] - wire _T_5153 = ~perr_sel_invalidate; // @[ifu_mem_ctl.scala 693:124] - wire _T_5154 = _T_5152 & _T_5153; // @[ifu_mem_ctl.scala 693:122] - wire _T_5157 = _T_4671 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5158 = perr_ic_index_ff == 7'h0; // @[ifu_mem_ctl.scala 694:102] - wire _T_5160 = _T_5158 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5161 = _T_5157 | _T_5160; // @[ifu_mem_ctl.scala 694:81] - wire _T_5162 = _T_5161 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5172 = _T_4672 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5173 = perr_ic_index_ff == 7'h1; // @[ifu_mem_ctl.scala 694:102] - wire _T_5175 = _T_5173 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5176 = _T_5172 | _T_5175; // @[ifu_mem_ctl.scala 694:81] - wire _T_5177 = _T_5176 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5187 = _T_4673 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5188 = perr_ic_index_ff == 7'h2; // @[ifu_mem_ctl.scala 694:102] - wire _T_5190 = _T_5188 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5191 = _T_5187 | _T_5190; // @[ifu_mem_ctl.scala 694:81] - wire _T_5192 = _T_5191 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5202 = _T_4674 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5203 = perr_ic_index_ff == 7'h3; // @[ifu_mem_ctl.scala 694:102] - wire _T_5205 = _T_5203 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5206 = _T_5202 | _T_5205; // @[ifu_mem_ctl.scala 694:81] - wire _T_5207 = _T_5206 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5217 = _T_4675 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5218 = perr_ic_index_ff == 7'h4; // @[ifu_mem_ctl.scala 694:102] - wire _T_5220 = _T_5218 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5221 = _T_5217 | _T_5220; // @[ifu_mem_ctl.scala 694:81] - wire _T_5222 = _T_5221 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5232 = _T_4676 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5233 = perr_ic_index_ff == 7'h5; // @[ifu_mem_ctl.scala 694:102] - wire _T_5235 = _T_5233 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5236 = _T_5232 | _T_5235; // @[ifu_mem_ctl.scala 694:81] - wire _T_5237 = _T_5236 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5247 = _T_4677 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5248 = perr_ic_index_ff == 7'h6; // @[ifu_mem_ctl.scala 694:102] - wire _T_5250 = _T_5248 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5251 = _T_5247 | _T_5250; // @[ifu_mem_ctl.scala 694:81] - wire _T_5252 = _T_5251 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5262 = _T_4678 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5263 = perr_ic_index_ff == 7'h7; // @[ifu_mem_ctl.scala 694:102] - wire _T_5265 = _T_5263 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5266 = _T_5262 | _T_5265; // @[ifu_mem_ctl.scala 694:81] - wire _T_5267 = _T_5266 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5277 = _T_4679 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5278 = perr_ic_index_ff == 7'h8; // @[ifu_mem_ctl.scala 694:102] - wire _T_5280 = _T_5278 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5281 = _T_5277 | _T_5280; // @[ifu_mem_ctl.scala 694:81] - wire _T_5282 = _T_5281 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5292 = _T_4680 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5293 = perr_ic_index_ff == 7'h9; // @[ifu_mem_ctl.scala 694:102] - wire _T_5295 = _T_5293 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5296 = _T_5292 | _T_5295; // @[ifu_mem_ctl.scala 694:81] - wire _T_5297 = _T_5296 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5307 = _T_4681 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5308 = perr_ic_index_ff == 7'ha; // @[ifu_mem_ctl.scala 694:102] - wire _T_5310 = _T_5308 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5311 = _T_5307 | _T_5310; // @[ifu_mem_ctl.scala 694:81] - wire _T_5312 = _T_5311 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5322 = _T_4682 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5323 = perr_ic_index_ff == 7'hb; // @[ifu_mem_ctl.scala 694:102] - wire _T_5325 = _T_5323 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5326 = _T_5322 | _T_5325; // @[ifu_mem_ctl.scala 694:81] - wire _T_5327 = _T_5326 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5337 = _T_4683 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5338 = perr_ic_index_ff == 7'hc; // @[ifu_mem_ctl.scala 694:102] - wire _T_5340 = _T_5338 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5341 = _T_5337 | _T_5340; // @[ifu_mem_ctl.scala 694:81] - wire _T_5342 = _T_5341 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5352 = _T_4684 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5353 = perr_ic_index_ff == 7'hd; // @[ifu_mem_ctl.scala 694:102] - wire _T_5355 = _T_5353 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5356 = _T_5352 | _T_5355; // @[ifu_mem_ctl.scala 694:81] - wire _T_5357 = _T_5356 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5367 = _T_4685 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5368 = perr_ic_index_ff == 7'he; // @[ifu_mem_ctl.scala 694:102] - wire _T_5370 = _T_5368 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5371 = _T_5367 | _T_5370; // @[ifu_mem_ctl.scala 694:81] - wire _T_5372 = _T_5371 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5382 = _T_4686 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5383 = perr_ic_index_ff == 7'hf; // @[ifu_mem_ctl.scala 694:102] - wire _T_5385 = _T_5383 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5386 = _T_5382 | _T_5385; // @[ifu_mem_ctl.scala 694:81] - wire _T_5387 = _T_5386 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5397 = _T_4687 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5398 = perr_ic_index_ff == 7'h10; // @[ifu_mem_ctl.scala 694:102] - wire _T_5400 = _T_5398 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5401 = _T_5397 | _T_5400; // @[ifu_mem_ctl.scala 694:81] - wire _T_5402 = _T_5401 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5412 = _T_4688 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5413 = perr_ic_index_ff == 7'h11; // @[ifu_mem_ctl.scala 694:102] - wire _T_5415 = _T_5413 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5416 = _T_5412 | _T_5415; // @[ifu_mem_ctl.scala 694:81] - wire _T_5417 = _T_5416 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5427 = _T_4689 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5428 = perr_ic_index_ff == 7'h12; // @[ifu_mem_ctl.scala 694:102] - wire _T_5430 = _T_5428 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5431 = _T_5427 | _T_5430; // @[ifu_mem_ctl.scala 694:81] - wire _T_5432 = _T_5431 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5442 = _T_4690 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5443 = perr_ic_index_ff == 7'h13; // @[ifu_mem_ctl.scala 694:102] - wire _T_5445 = _T_5443 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5446 = _T_5442 | _T_5445; // @[ifu_mem_ctl.scala 694:81] - wire _T_5447 = _T_5446 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5457 = _T_4691 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5458 = perr_ic_index_ff == 7'h14; // @[ifu_mem_ctl.scala 694:102] - wire _T_5460 = _T_5458 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5461 = _T_5457 | _T_5460; // @[ifu_mem_ctl.scala 694:81] - wire _T_5462 = _T_5461 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5472 = _T_4692 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5473 = perr_ic_index_ff == 7'h15; // @[ifu_mem_ctl.scala 694:102] - wire _T_5475 = _T_5473 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5476 = _T_5472 | _T_5475; // @[ifu_mem_ctl.scala 694:81] - wire _T_5477 = _T_5476 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5487 = _T_4693 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5488 = perr_ic_index_ff == 7'h16; // @[ifu_mem_ctl.scala 694:102] - wire _T_5490 = _T_5488 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5491 = _T_5487 | _T_5490; // @[ifu_mem_ctl.scala 694:81] - wire _T_5492 = _T_5491 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5502 = _T_4694 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5503 = perr_ic_index_ff == 7'h17; // @[ifu_mem_ctl.scala 694:102] - wire _T_5505 = _T_5503 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5506 = _T_5502 | _T_5505; // @[ifu_mem_ctl.scala 694:81] - wire _T_5507 = _T_5506 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5517 = _T_4695 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5518 = perr_ic_index_ff == 7'h18; // @[ifu_mem_ctl.scala 694:102] - wire _T_5520 = _T_5518 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5521 = _T_5517 | _T_5520; // @[ifu_mem_ctl.scala 694:81] - wire _T_5522 = _T_5521 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5532 = _T_4696 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5533 = perr_ic_index_ff == 7'h19; // @[ifu_mem_ctl.scala 694:102] - wire _T_5535 = _T_5533 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5536 = _T_5532 | _T_5535; // @[ifu_mem_ctl.scala 694:81] - wire _T_5537 = _T_5536 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5547 = _T_4697 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5548 = perr_ic_index_ff == 7'h1a; // @[ifu_mem_ctl.scala 694:102] - wire _T_5550 = _T_5548 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5551 = _T_5547 | _T_5550; // @[ifu_mem_ctl.scala 694:81] - wire _T_5552 = _T_5551 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5562 = _T_4698 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5563 = perr_ic_index_ff == 7'h1b; // @[ifu_mem_ctl.scala 694:102] - wire _T_5565 = _T_5563 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5566 = _T_5562 | _T_5565; // @[ifu_mem_ctl.scala 694:81] - wire _T_5567 = _T_5566 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5577 = _T_4699 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5578 = perr_ic_index_ff == 7'h1c; // @[ifu_mem_ctl.scala 694:102] - wire _T_5580 = _T_5578 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5581 = _T_5577 | _T_5580; // @[ifu_mem_ctl.scala 694:81] - wire _T_5582 = _T_5581 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5592 = _T_4700 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5593 = perr_ic_index_ff == 7'h1d; // @[ifu_mem_ctl.scala 694:102] - wire _T_5595 = _T_5593 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5596 = _T_5592 | _T_5595; // @[ifu_mem_ctl.scala 694:81] - wire _T_5597 = _T_5596 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5607 = _T_4701 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5608 = perr_ic_index_ff == 7'h1e; // @[ifu_mem_ctl.scala 694:102] - wire _T_5610 = _T_5608 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5611 = _T_5607 | _T_5610; // @[ifu_mem_ctl.scala 694:81] - wire _T_5612 = _T_5611 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5622 = _T_4702 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5623 = perr_ic_index_ff == 7'h1f; // @[ifu_mem_ctl.scala 694:102] - wire _T_5625 = _T_5623 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5626 = _T_5622 | _T_5625; // @[ifu_mem_ctl.scala 694:81] - wire _T_5627 = _T_5626 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5637 = _T_4671 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5640 = _T_5158 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5641 = _T_5637 | _T_5640; // @[ifu_mem_ctl.scala 694:81] - wire _T_5642 = _T_5641 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5652 = _T_4672 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5655 = _T_5173 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5656 = _T_5652 | _T_5655; // @[ifu_mem_ctl.scala 694:81] - wire _T_5657 = _T_5656 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5667 = _T_4673 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5670 = _T_5188 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5671 = _T_5667 | _T_5670; // @[ifu_mem_ctl.scala 694:81] - wire _T_5672 = _T_5671 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5682 = _T_4674 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5685 = _T_5203 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5686 = _T_5682 | _T_5685; // @[ifu_mem_ctl.scala 694:81] - wire _T_5687 = _T_5686 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5697 = _T_4675 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5700 = _T_5218 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5701 = _T_5697 | _T_5700; // @[ifu_mem_ctl.scala 694:81] - wire _T_5702 = _T_5701 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5712 = _T_4676 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5715 = _T_5233 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5716 = _T_5712 | _T_5715; // @[ifu_mem_ctl.scala 694:81] - wire _T_5717 = _T_5716 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5727 = _T_4677 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5730 = _T_5248 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5731 = _T_5727 | _T_5730; // @[ifu_mem_ctl.scala 694:81] - wire _T_5732 = _T_5731 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5742 = _T_4678 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5745 = _T_5263 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5746 = _T_5742 | _T_5745; // @[ifu_mem_ctl.scala 694:81] - wire _T_5747 = _T_5746 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5757 = _T_4679 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5760 = _T_5278 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5761 = _T_5757 | _T_5760; // @[ifu_mem_ctl.scala 694:81] - wire _T_5762 = _T_5761 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5772 = _T_4680 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5775 = _T_5293 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5776 = _T_5772 | _T_5775; // @[ifu_mem_ctl.scala 694:81] - wire _T_5777 = _T_5776 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5787 = _T_4681 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5790 = _T_5308 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5791 = _T_5787 | _T_5790; // @[ifu_mem_ctl.scala 694:81] - wire _T_5792 = _T_5791 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5802 = _T_4682 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5805 = _T_5323 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5806 = _T_5802 | _T_5805; // @[ifu_mem_ctl.scala 694:81] - wire _T_5807 = _T_5806 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5817 = _T_4683 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5820 = _T_5338 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5821 = _T_5817 | _T_5820; // @[ifu_mem_ctl.scala 694:81] - wire _T_5822 = _T_5821 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5832 = _T_4684 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5835 = _T_5353 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5836 = _T_5832 | _T_5835; // @[ifu_mem_ctl.scala 694:81] - wire _T_5837 = _T_5836 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5847 = _T_4685 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5850 = _T_5368 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5851 = _T_5847 | _T_5850; // @[ifu_mem_ctl.scala 694:81] - wire _T_5852 = _T_5851 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5862 = _T_4686 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5865 = _T_5383 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5866 = _T_5862 | _T_5865; // @[ifu_mem_ctl.scala 694:81] - wire _T_5867 = _T_5866 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5877 = _T_4687 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5880 = _T_5398 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5881 = _T_5877 | _T_5880; // @[ifu_mem_ctl.scala 694:81] - wire _T_5882 = _T_5881 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5892 = _T_4688 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5895 = _T_5413 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5896 = _T_5892 | _T_5895; // @[ifu_mem_ctl.scala 694:81] - wire _T_5897 = _T_5896 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5907 = _T_4689 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5910 = _T_5428 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5911 = _T_5907 | _T_5910; // @[ifu_mem_ctl.scala 694:81] - wire _T_5912 = _T_5911 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5922 = _T_4690 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5925 = _T_5443 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5926 = _T_5922 | _T_5925; // @[ifu_mem_ctl.scala 694:81] - wire _T_5927 = _T_5926 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5937 = _T_4691 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5940 = _T_5458 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5941 = _T_5937 | _T_5940; // @[ifu_mem_ctl.scala 694:81] - wire _T_5942 = _T_5941 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5952 = _T_4692 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5955 = _T_5473 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5956 = _T_5952 | _T_5955; // @[ifu_mem_ctl.scala 694:81] - wire _T_5957 = _T_5956 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5967 = _T_4693 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5970 = _T_5488 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5971 = _T_5967 | _T_5970; // @[ifu_mem_ctl.scala 694:81] - wire _T_5972 = _T_5971 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5982 = _T_4694 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_5985 = _T_5503 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_5986 = _T_5982 | _T_5985; // @[ifu_mem_ctl.scala 694:81] - wire _T_5987 = _T_5986 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_5997 = _T_4695 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6000 = _T_5518 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6001 = _T_5997 | _T_6000; // @[ifu_mem_ctl.scala 694:81] - wire _T_6002 = _T_6001 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6012 = _T_4696 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6015 = _T_5533 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6016 = _T_6012 | _T_6015; // @[ifu_mem_ctl.scala 694:81] - wire _T_6017 = _T_6016 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6027 = _T_4697 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6030 = _T_5548 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6031 = _T_6027 | _T_6030; // @[ifu_mem_ctl.scala 694:81] - wire _T_6032 = _T_6031 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6042 = _T_4698 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6045 = _T_5563 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6046 = _T_6042 | _T_6045; // @[ifu_mem_ctl.scala 694:81] - wire _T_6047 = _T_6046 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6057 = _T_4699 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6060 = _T_5578 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6061 = _T_6057 | _T_6060; // @[ifu_mem_ctl.scala 694:81] - wire _T_6062 = _T_6061 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6072 = _T_4700 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6075 = _T_5593 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6076 = _T_6072 | _T_6075; // @[ifu_mem_ctl.scala 694:81] - wire _T_6077 = _T_6076 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6087 = _T_4701 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6090 = _T_5608 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6091 = _T_6087 | _T_6090; // @[ifu_mem_ctl.scala 694:81] - wire _T_6092 = _T_6091 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6102 = _T_4702 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6105 = _T_5623 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6106 = _T_6102 | _T_6105; // @[ifu_mem_ctl.scala 694:81] - wire _T_6107 = _T_6106 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6117 = _T_4703 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6118 = perr_ic_index_ff == 7'h20; // @[ifu_mem_ctl.scala 694:102] - wire _T_6120 = _T_6118 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6121 = _T_6117 | _T_6120; // @[ifu_mem_ctl.scala 694:81] - wire _T_6122 = _T_6121 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6132 = _T_4704 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6133 = perr_ic_index_ff == 7'h21; // @[ifu_mem_ctl.scala 694:102] - wire _T_6135 = _T_6133 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6136 = _T_6132 | _T_6135; // @[ifu_mem_ctl.scala 694:81] - wire _T_6137 = _T_6136 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6147 = _T_4705 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6148 = perr_ic_index_ff == 7'h22; // @[ifu_mem_ctl.scala 694:102] - wire _T_6150 = _T_6148 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6151 = _T_6147 | _T_6150; // @[ifu_mem_ctl.scala 694:81] - wire _T_6152 = _T_6151 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6162 = _T_4706 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6163 = perr_ic_index_ff == 7'h23; // @[ifu_mem_ctl.scala 694:102] - wire _T_6165 = _T_6163 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6166 = _T_6162 | _T_6165; // @[ifu_mem_ctl.scala 694:81] - wire _T_6167 = _T_6166 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6177 = _T_4707 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6178 = perr_ic_index_ff == 7'h24; // @[ifu_mem_ctl.scala 694:102] - wire _T_6180 = _T_6178 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6181 = _T_6177 | _T_6180; // @[ifu_mem_ctl.scala 694:81] - wire _T_6182 = _T_6181 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6192 = _T_4708 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6193 = perr_ic_index_ff == 7'h25; // @[ifu_mem_ctl.scala 694:102] - wire _T_6195 = _T_6193 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6196 = _T_6192 | _T_6195; // @[ifu_mem_ctl.scala 694:81] - wire _T_6197 = _T_6196 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6207 = _T_4709 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6208 = perr_ic_index_ff == 7'h26; // @[ifu_mem_ctl.scala 694:102] - wire _T_6210 = _T_6208 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6211 = _T_6207 | _T_6210; // @[ifu_mem_ctl.scala 694:81] - wire _T_6212 = _T_6211 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6222 = _T_4710 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6223 = perr_ic_index_ff == 7'h27; // @[ifu_mem_ctl.scala 694:102] - wire _T_6225 = _T_6223 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6226 = _T_6222 | _T_6225; // @[ifu_mem_ctl.scala 694:81] - wire _T_6227 = _T_6226 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6237 = _T_4711 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6238 = perr_ic_index_ff == 7'h28; // @[ifu_mem_ctl.scala 694:102] - wire _T_6240 = _T_6238 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6241 = _T_6237 | _T_6240; // @[ifu_mem_ctl.scala 694:81] - wire _T_6242 = _T_6241 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6252 = _T_4712 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6253 = perr_ic_index_ff == 7'h29; // @[ifu_mem_ctl.scala 694:102] - wire _T_6255 = _T_6253 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6256 = _T_6252 | _T_6255; // @[ifu_mem_ctl.scala 694:81] - wire _T_6257 = _T_6256 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6267 = _T_4713 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6268 = perr_ic_index_ff == 7'h2a; // @[ifu_mem_ctl.scala 694:102] - wire _T_6270 = _T_6268 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6271 = _T_6267 | _T_6270; // @[ifu_mem_ctl.scala 694:81] - wire _T_6272 = _T_6271 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6282 = _T_4714 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6283 = perr_ic_index_ff == 7'h2b; // @[ifu_mem_ctl.scala 694:102] - wire _T_6285 = _T_6283 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6286 = _T_6282 | _T_6285; // @[ifu_mem_ctl.scala 694:81] - wire _T_6287 = _T_6286 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6297 = _T_4715 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6298 = perr_ic_index_ff == 7'h2c; // @[ifu_mem_ctl.scala 694:102] - wire _T_6300 = _T_6298 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6301 = _T_6297 | _T_6300; // @[ifu_mem_ctl.scala 694:81] - wire _T_6302 = _T_6301 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6312 = _T_4716 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6313 = perr_ic_index_ff == 7'h2d; // @[ifu_mem_ctl.scala 694:102] - wire _T_6315 = _T_6313 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6316 = _T_6312 | _T_6315; // @[ifu_mem_ctl.scala 694:81] - wire _T_6317 = _T_6316 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6327 = _T_4717 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6328 = perr_ic_index_ff == 7'h2e; // @[ifu_mem_ctl.scala 694:102] - wire _T_6330 = _T_6328 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6331 = _T_6327 | _T_6330; // @[ifu_mem_ctl.scala 694:81] - wire _T_6332 = _T_6331 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6342 = _T_4718 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6343 = perr_ic_index_ff == 7'h2f; // @[ifu_mem_ctl.scala 694:102] - wire _T_6345 = _T_6343 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6346 = _T_6342 | _T_6345; // @[ifu_mem_ctl.scala 694:81] - wire _T_6347 = _T_6346 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6357 = _T_4719 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6358 = perr_ic_index_ff == 7'h30; // @[ifu_mem_ctl.scala 694:102] - wire _T_6360 = _T_6358 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6361 = _T_6357 | _T_6360; // @[ifu_mem_ctl.scala 694:81] - wire _T_6362 = _T_6361 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6372 = _T_4720 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6373 = perr_ic_index_ff == 7'h31; // @[ifu_mem_ctl.scala 694:102] - wire _T_6375 = _T_6373 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6376 = _T_6372 | _T_6375; // @[ifu_mem_ctl.scala 694:81] - wire _T_6377 = _T_6376 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6387 = _T_4721 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6388 = perr_ic_index_ff == 7'h32; // @[ifu_mem_ctl.scala 694:102] - wire _T_6390 = _T_6388 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6391 = _T_6387 | _T_6390; // @[ifu_mem_ctl.scala 694:81] - wire _T_6392 = _T_6391 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6402 = _T_4722 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6403 = perr_ic_index_ff == 7'h33; // @[ifu_mem_ctl.scala 694:102] - wire _T_6405 = _T_6403 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6406 = _T_6402 | _T_6405; // @[ifu_mem_ctl.scala 694:81] - wire _T_6407 = _T_6406 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6417 = _T_4723 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6418 = perr_ic_index_ff == 7'h34; // @[ifu_mem_ctl.scala 694:102] - wire _T_6420 = _T_6418 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6421 = _T_6417 | _T_6420; // @[ifu_mem_ctl.scala 694:81] - wire _T_6422 = _T_6421 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6432 = _T_4724 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6433 = perr_ic_index_ff == 7'h35; // @[ifu_mem_ctl.scala 694:102] - wire _T_6435 = _T_6433 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6436 = _T_6432 | _T_6435; // @[ifu_mem_ctl.scala 694:81] - wire _T_6437 = _T_6436 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6447 = _T_4725 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6448 = perr_ic_index_ff == 7'h36; // @[ifu_mem_ctl.scala 694:102] - wire _T_6450 = _T_6448 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6451 = _T_6447 | _T_6450; // @[ifu_mem_ctl.scala 694:81] - wire _T_6452 = _T_6451 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6462 = _T_4726 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6463 = perr_ic_index_ff == 7'h37; // @[ifu_mem_ctl.scala 694:102] - wire _T_6465 = _T_6463 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6466 = _T_6462 | _T_6465; // @[ifu_mem_ctl.scala 694:81] - wire _T_6467 = _T_6466 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6477 = _T_4727 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6478 = perr_ic_index_ff == 7'h38; // @[ifu_mem_ctl.scala 694:102] - wire _T_6480 = _T_6478 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6481 = _T_6477 | _T_6480; // @[ifu_mem_ctl.scala 694:81] - wire _T_6482 = _T_6481 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6492 = _T_4728 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6493 = perr_ic_index_ff == 7'h39; // @[ifu_mem_ctl.scala 694:102] - wire _T_6495 = _T_6493 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6496 = _T_6492 | _T_6495; // @[ifu_mem_ctl.scala 694:81] - wire _T_6497 = _T_6496 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6507 = _T_4729 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6508 = perr_ic_index_ff == 7'h3a; // @[ifu_mem_ctl.scala 694:102] - wire _T_6510 = _T_6508 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6511 = _T_6507 | _T_6510; // @[ifu_mem_ctl.scala 694:81] - wire _T_6512 = _T_6511 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6522 = _T_4730 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6523 = perr_ic_index_ff == 7'h3b; // @[ifu_mem_ctl.scala 694:102] - wire _T_6525 = _T_6523 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6526 = _T_6522 | _T_6525; // @[ifu_mem_ctl.scala 694:81] - wire _T_6527 = _T_6526 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6537 = _T_4731 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6538 = perr_ic_index_ff == 7'h3c; // @[ifu_mem_ctl.scala 694:102] - wire _T_6540 = _T_6538 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6541 = _T_6537 | _T_6540; // @[ifu_mem_ctl.scala 694:81] - wire _T_6542 = _T_6541 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6552 = _T_4732 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6553 = perr_ic_index_ff == 7'h3d; // @[ifu_mem_ctl.scala 694:102] - wire _T_6555 = _T_6553 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6556 = _T_6552 | _T_6555; // @[ifu_mem_ctl.scala 694:81] - wire _T_6557 = _T_6556 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6567 = _T_4733 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6568 = perr_ic_index_ff == 7'h3e; // @[ifu_mem_ctl.scala 694:102] - wire _T_6570 = _T_6568 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6571 = _T_6567 | _T_6570; // @[ifu_mem_ctl.scala 694:81] - wire _T_6572 = _T_6571 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6582 = _T_4734 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6583 = perr_ic_index_ff == 7'h3f; // @[ifu_mem_ctl.scala 694:102] - wire _T_6585 = _T_6583 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6586 = _T_6582 | _T_6585; // @[ifu_mem_ctl.scala 694:81] - wire _T_6587 = _T_6586 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6597 = _T_4703 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6600 = _T_6118 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6601 = _T_6597 | _T_6600; // @[ifu_mem_ctl.scala 694:81] - wire _T_6602 = _T_6601 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6612 = _T_4704 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6615 = _T_6133 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6616 = _T_6612 | _T_6615; // @[ifu_mem_ctl.scala 694:81] - wire _T_6617 = _T_6616 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6627 = _T_4705 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6630 = _T_6148 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6631 = _T_6627 | _T_6630; // @[ifu_mem_ctl.scala 694:81] - wire _T_6632 = _T_6631 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6642 = _T_4706 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6645 = _T_6163 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6646 = _T_6642 | _T_6645; // @[ifu_mem_ctl.scala 694:81] - wire _T_6647 = _T_6646 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6657 = _T_4707 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6660 = _T_6178 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6661 = _T_6657 | _T_6660; // @[ifu_mem_ctl.scala 694:81] - wire _T_6662 = _T_6661 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6672 = _T_4708 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6675 = _T_6193 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6676 = _T_6672 | _T_6675; // @[ifu_mem_ctl.scala 694:81] - wire _T_6677 = _T_6676 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6687 = _T_4709 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6690 = _T_6208 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6691 = _T_6687 | _T_6690; // @[ifu_mem_ctl.scala 694:81] - wire _T_6692 = _T_6691 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6702 = _T_4710 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6705 = _T_6223 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6706 = _T_6702 | _T_6705; // @[ifu_mem_ctl.scala 694:81] - wire _T_6707 = _T_6706 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6717 = _T_4711 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6720 = _T_6238 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6721 = _T_6717 | _T_6720; // @[ifu_mem_ctl.scala 694:81] - wire _T_6722 = _T_6721 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6732 = _T_4712 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6735 = _T_6253 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6736 = _T_6732 | _T_6735; // @[ifu_mem_ctl.scala 694:81] - wire _T_6737 = _T_6736 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6747 = _T_4713 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6750 = _T_6268 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6751 = _T_6747 | _T_6750; // @[ifu_mem_ctl.scala 694:81] - wire _T_6752 = _T_6751 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6762 = _T_4714 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6765 = _T_6283 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6766 = _T_6762 | _T_6765; // @[ifu_mem_ctl.scala 694:81] - wire _T_6767 = _T_6766 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6777 = _T_4715 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6780 = _T_6298 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6781 = _T_6777 | _T_6780; // @[ifu_mem_ctl.scala 694:81] - wire _T_6782 = _T_6781 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6792 = _T_4716 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6795 = _T_6313 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6796 = _T_6792 | _T_6795; // @[ifu_mem_ctl.scala 694:81] - wire _T_6797 = _T_6796 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6807 = _T_4717 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6810 = _T_6328 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6811 = _T_6807 | _T_6810; // @[ifu_mem_ctl.scala 694:81] - wire _T_6812 = _T_6811 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6822 = _T_4718 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6825 = _T_6343 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6826 = _T_6822 | _T_6825; // @[ifu_mem_ctl.scala 694:81] - wire _T_6827 = _T_6826 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6837 = _T_4719 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6840 = _T_6358 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6841 = _T_6837 | _T_6840; // @[ifu_mem_ctl.scala 694:81] - wire _T_6842 = _T_6841 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6852 = _T_4720 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6855 = _T_6373 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6856 = _T_6852 | _T_6855; // @[ifu_mem_ctl.scala 694:81] - wire _T_6857 = _T_6856 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6867 = _T_4721 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6870 = _T_6388 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6871 = _T_6867 | _T_6870; // @[ifu_mem_ctl.scala 694:81] - wire _T_6872 = _T_6871 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6882 = _T_4722 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6885 = _T_6403 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6886 = _T_6882 | _T_6885; // @[ifu_mem_ctl.scala 694:81] - wire _T_6887 = _T_6886 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6897 = _T_4723 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6900 = _T_6418 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6901 = _T_6897 | _T_6900; // @[ifu_mem_ctl.scala 694:81] - wire _T_6902 = _T_6901 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6912 = _T_4724 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6915 = _T_6433 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6916 = _T_6912 | _T_6915; // @[ifu_mem_ctl.scala 694:81] - wire _T_6917 = _T_6916 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6927 = _T_4725 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6930 = _T_6448 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6931 = _T_6927 | _T_6930; // @[ifu_mem_ctl.scala 694:81] - wire _T_6932 = _T_6931 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6942 = _T_4726 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6945 = _T_6463 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6946 = _T_6942 | _T_6945; // @[ifu_mem_ctl.scala 694:81] - wire _T_6947 = _T_6946 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6957 = _T_4727 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6960 = _T_6478 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6961 = _T_6957 | _T_6960; // @[ifu_mem_ctl.scala 694:81] - wire _T_6962 = _T_6961 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6972 = _T_4728 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6975 = _T_6493 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6976 = _T_6972 | _T_6975; // @[ifu_mem_ctl.scala 694:81] - wire _T_6977 = _T_6976 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_6987 = _T_4729 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_6990 = _T_6508 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_6991 = _T_6987 | _T_6990; // @[ifu_mem_ctl.scala 694:81] - wire _T_6992 = _T_6991 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7002 = _T_4730 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7005 = _T_6523 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7006 = _T_7002 | _T_7005; // @[ifu_mem_ctl.scala 694:81] - wire _T_7007 = _T_7006 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7017 = _T_4731 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7020 = _T_6538 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7021 = _T_7017 | _T_7020; // @[ifu_mem_ctl.scala 694:81] - wire _T_7022 = _T_7021 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7032 = _T_4732 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7035 = _T_6553 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7036 = _T_7032 | _T_7035; // @[ifu_mem_ctl.scala 694:81] - wire _T_7037 = _T_7036 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7047 = _T_4733 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7050 = _T_6568 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7051 = _T_7047 | _T_7050; // @[ifu_mem_ctl.scala 694:81] - wire _T_7052 = _T_7051 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7062 = _T_4734 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7065 = _T_6583 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7066 = _T_7062 | _T_7065; // @[ifu_mem_ctl.scala 694:81] - wire _T_7067 = _T_7066 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7077 = _T_4735 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7078 = perr_ic_index_ff == 7'h40; // @[ifu_mem_ctl.scala 694:102] - wire _T_7080 = _T_7078 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7081 = _T_7077 | _T_7080; // @[ifu_mem_ctl.scala 694:81] - wire _T_7082 = _T_7081 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7092 = _T_4736 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7093 = perr_ic_index_ff == 7'h41; // @[ifu_mem_ctl.scala 694:102] - wire _T_7095 = _T_7093 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7096 = _T_7092 | _T_7095; // @[ifu_mem_ctl.scala 694:81] - wire _T_7097 = _T_7096 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7107 = _T_4737 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7108 = perr_ic_index_ff == 7'h42; // @[ifu_mem_ctl.scala 694:102] - wire _T_7110 = _T_7108 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7111 = _T_7107 | _T_7110; // @[ifu_mem_ctl.scala 694:81] - wire _T_7112 = _T_7111 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7122 = _T_4738 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7123 = perr_ic_index_ff == 7'h43; // @[ifu_mem_ctl.scala 694:102] - wire _T_7125 = _T_7123 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7126 = _T_7122 | _T_7125; // @[ifu_mem_ctl.scala 694:81] - wire _T_7127 = _T_7126 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7137 = _T_4739 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7138 = perr_ic_index_ff == 7'h44; // @[ifu_mem_ctl.scala 694:102] - wire _T_7140 = _T_7138 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7141 = _T_7137 | _T_7140; // @[ifu_mem_ctl.scala 694:81] - wire _T_7142 = _T_7141 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7152 = _T_4740 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7153 = perr_ic_index_ff == 7'h45; // @[ifu_mem_ctl.scala 694:102] - wire _T_7155 = _T_7153 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7156 = _T_7152 | _T_7155; // @[ifu_mem_ctl.scala 694:81] - wire _T_7157 = _T_7156 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7167 = _T_4741 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7168 = perr_ic_index_ff == 7'h46; // @[ifu_mem_ctl.scala 694:102] - wire _T_7170 = _T_7168 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7171 = _T_7167 | _T_7170; // @[ifu_mem_ctl.scala 694:81] - wire _T_7172 = _T_7171 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7182 = _T_4742 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7183 = perr_ic_index_ff == 7'h47; // @[ifu_mem_ctl.scala 694:102] - wire _T_7185 = _T_7183 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7186 = _T_7182 | _T_7185; // @[ifu_mem_ctl.scala 694:81] - wire _T_7187 = _T_7186 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7197 = _T_4743 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7198 = perr_ic_index_ff == 7'h48; // @[ifu_mem_ctl.scala 694:102] - wire _T_7200 = _T_7198 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7201 = _T_7197 | _T_7200; // @[ifu_mem_ctl.scala 694:81] - wire _T_7202 = _T_7201 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7212 = _T_4744 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7213 = perr_ic_index_ff == 7'h49; // @[ifu_mem_ctl.scala 694:102] - wire _T_7215 = _T_7213 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7216 = _T_7212 | _T_7215; // @[ifu_mem_ctl.scala 694:81] - wire _T_7217 = _T_7216 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7227 = _T_4745 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7228 = perr_ic_index_ff == 7'h4a; // @[ifu_mem_ctl.scala 694:102] - wire _T_7230 = _T_7228 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7231 = _T_7227 | _T_7230; // @[ifu_mem_ctl.scala 694:81] - wire _T_7232 = _T_7231 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7242 = _T_4746 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7243 = perr_ic_index_ff == 7'h4b; // @[ifu_mem_ctl.scala 694:102] - wire _T_7245 = _T_7243 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7246 = _T_7242 | _T_7245; // @[ifu_mem_ctl.scala 694:81] - wire _T_7247 = _T_7246 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7257 = _T_4747 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7258 = perr_ic_index_ff == 7'h4c; // @[ifu_mem_ctl.scala 694:102] - wire _T_7260 = _T_7258 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7261 = _T_7257 | _T_7260; // @[ifu_mem_ctl.scala 694:81] - wire _T_7262 = _T_7261 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7272 = _T_4748 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7273 = perr_ic_index_ff == 7'h4d; // @[ifu_mem_ctl.scala 694:102] - wire _T_7275 = _T_7273 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7276 = _T_7272 | _T_7275; // @[ifu_mem_ctl.scala 694:81] - wire _T_7277 = _T_7276 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7287 = _T_4749 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7288 = perr_ic_index_ff == 7'h4e; // @[ifu_mem_ctl.scala 694:102] - wire _T_7290 = _T_7288 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7291 = _T_7287 | _T_7290; // @[ifu_mem_ctl.scala 694:81] - wire _T_7292 = _T_7291 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7302 = _T_4750 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7303 = perr_ic_index_ff == 7'h4f; // @[ifu_mem_ctl.scala 694:102] - wire _T_7305 = _T_7303 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7306 = _T_7302 | _T_7305; // @[ifu_mem_ctl.scala 694:81] - wire _T_7307 = _T_7306 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7317 = _T_4751 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7318 = perr_ic_index_ff == 7'h50; // @[ifu_mem_ctl.scala 694:102] - wire _T_7320 = _T_7318 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7321 = _T_7317 | _T_7320; // @[ifu_mem_ctl.scala 694:81] - wire _T_7322 = _T_7321 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7332 = _T_4752 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7333 = perr_ic_index_ff == 7'h51; // @[ifu_mem_ctl.scala 694:102] - wire _T_7335 = _T_7333 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7336 = _T_7332 | _T_7335; // @[ifu_mem_ctl.scala 694:81] - wire _T_7337 = _T_7336 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7347 = _T_4753 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7348 = perr_ic_index_ff == 7'h52; // @[ifu_mem_ctl.scala 694:102] - wire _T_7350 = _T_7348 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7351 = _T_7347 | _T_7350; // @[ifu_mem_ctl.scala 694:81] - wire _T_7352 = _T_7351 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7362 = _T_4754 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7363 = perr_ic_index_ff == 7'h53; // @[ifu_mem_ctl.scala 694:102] - wire _T_7365 = _T_7363 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7366 = _T_7362 | _T_7365; // @[ifu_mem_ctl.scala 694:81] - wire _T_7367 = _T_7366 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7377 = _T_4755 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7378 = perr_ic_index_ff == 7'h54; // @[ifu_mem_ctl.scala 694:102] - wire _T_7380 = _T_7378 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7381 = _T_7377 | _T_7380; // @[ifu_mem_ctl.scala 694:81] - wire _T_7382 = _T_7381 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7392 = _T_4756 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7393 = perr_ic_index_ff == 7'h55; // @[ifu_mem_ctl.scala 694:102] - wire _T_7395 = _T_7393 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7396 = _T_7392 | _T_7395; // @[ifu_mem_ctl.scala 694:81] - wire _T_7397 = _T_7396 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7407 = _T_4757 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7408 = perr_ic_index_ff == 7'h56; // @[ifu_mem_ctl.scala 694:102] - wire _T_7410 = _T_7408 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7411 = _T_7407 | _T_7410; // @[ifu_mem_ctl.scala 694:81] - wire _T_7412 = _T_7411 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7422 = _T_4758 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7423 = perr_ic_index_ff == 7'h57; // @[ifu_mem_ctl.scala 694:102] - wire _T_7425 = _T_7423 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7426 = _T_7422 | _T_7425; // @[ifu_mem_ctl.scala 694:81] - wire _T_7427 = _T_7426 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7437 = _T_4759 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7438 = perr_ic_index_ff == 7'h58; // @[ifu_mem_ctl.scala 694:102] - wire _T_7440 = _T_7438 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7441 = _T_7437 | _T_7440; // @[ifu_mem_ctl.scala 694:81] - wire _T_7442 = _T_7441 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7452 = _T_4760 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7453 = perr_ic_index_ff == 7'h59; // @[ifu_mem_ctl.scala 694:102] - wire _T_7455 = _T_7453 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7456 = _T_7452 | _T_7455; // @[ifu_mem_ctl.scala 694:81] - wire _T_7457 = _T_7456 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7467 = _T_4761 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7468 = perr_ic_index_ff == 7'h5a; // @[ifu_mem_ctl.scala 694:102] - wire _T_7470 = _T_7468 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7471 = _T_7467 | _T_7470; // @[ifu_mem_ctl.scala 694:81] - wire _T_7472 = _T_7471 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7482 = _T_4762 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7483 = perr_ic_index_ff == 7'h5b; // @[ifu_mem_ctl.scala 694:102] - wire _T_7485 = _T_7483 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7486 = _T_7482 | _T_7485; // @[ifu_mem_ctl.scala 694:81] - wire _T_7487 = _T_7486 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7497 = _T_4763 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7498 = perr_ic_index_ff == 7'h5c; // @[ifu_mem_ctl.scala 694:102] - wire _T_7500 = _T_7498 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7501 = _T_7497 | _T_7500; // @[ifu_mem_ctl.scala 694:81] - wire _T_7502 = _T_7501 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7512 = _T_4764 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7513 = perr_ic_index_ff == 7'h5d; // @[ifu_mem_ctl.scala 694:102] - wire _T_7515 = _T_7513 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7516 = _T_7512 | _T_7515; // @[ifu_mem_ctl.scala 694:81] - wire _T_7517 = _T_7516 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7527 = _T_4765 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7528 = perr_ic_index_ff == 7'h5e; // @[ifu_mem_ctl.scala 694:102] - wire _T_7530 = _T_7528 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7531 = _T_7527 | _T_7530; // @[ifu_mem_ctl.scala 694:81] - wire _T_7532 = _T_7531 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7542 = _T_4766 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7543 = perr_ic_index_ff == 7'h5f; // @[ifu_mem_ctl.scala 694:102] - wire _T_7545 = _T_7543 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7546 = _T_7542 | _T_7545; // @[ifu_mem_ctl.scala 694:81] - wire _T_7547 = _T_7546 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7557 = _T_4735 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7560 = _T_7078 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7561 = _T_7557 | _T_7560; // @[ifu_mem_ctl.scala 694:81] - wire _T_7562 = _T_7561 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7572 = _T_4736 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7575 = _T_7093 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7576 = _T_7572 | _T_7575; // @[ifu_mem_ctl.scala 694:81] - wire _T_7577 = _T_7576 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7587 = _T_4737 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7590 = _T_7108 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7591 = _T_7587 | _T_7590; // @[ifu_mem_ctl.scala 694:81] - wire _T_7592 = _T_7591 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7602 = _T_4738 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7605 = _T_7123 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7606 = _T_7602 | _T_7605; // @[ifu_mem_ctl.scala 694:81] - wire _T_7607 = _T_7606 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7617 = _T_4739 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7620 = _T_7138 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7621 = _T_7617 | _T_7620; // @[ifu_mem_ctl.scala 694:81] - wire _T_7622 = _T_7621 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7632 = _T_4740 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7635 = _T_7153 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7636 = _T_7632 | _T_7635; // @[ifu_mem_ctl.scala 694:81] - wire _T_7637 = _T_7636 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7647 = _T_4741 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7650 = _T_7168 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7651 = _T_7647 | _T_7650; // @[ifu_mem_ctl.scala 694:81] - wire _T_7652 = _T_7651 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7662 = _T_4742 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7665 = _T_7183 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7666 = _T_7662 | _T_7665; // @[ifu_mem_ctl.scala 694:81] - wire _T_7667 = _T_7666 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7677 = _T_4743 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7680 = _T_7198 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7681 = _T_7677 | _T_7680; // @[ifu_mem_ctl.scala 694:81] - wire _T_7682 = _T_7681 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7692 = _T_4744 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7695 = _T_7213 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7696 = _T_7692 | _T_7695; // @[ifu_mem_ctl.scala 694:81] - wire _T_7697 = _T_7696 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7707 = _T_4745 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7710 = _T_7228 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7711 = _T_7707 | _T_7710; // @[ifu_mem_ctl.scala 694:81] - wire _T_7712 = _T_7711 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7722 = _T_4746 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7725 = _T_7243 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7726 = _T_7722 | _T_7725; // @[ifu_mem_ctl.scala 694:81] - wire _T_7727 = _T_7726 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7737 = _T_4747 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7740 = _T_7258 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7741 = _T_7737 | _T_7740; // @[ifu_mem_ctl.scala 694:81] - wire _T_7742 = _T_7741 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7752 = _T_4748 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7755 = _T_7273 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7756 = _T_7752 | _T_7755; // @[ifu_mem_ctl.scala 694:81] - wire _T_7757 = _T_7756 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7767 = _T_4749 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7770 = _T_7288 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7771 = _T_7767 | _T_7770; // @[ifu_mem_ctl.scala 694:81] - wire _T_7772 = _T_7771 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7782 = _T_4750 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7785 = _T_7303 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7786 = _T_7782 | _T_7785; // @[ifu_mem_ctl.scala 694:81] - wire _T_7787 = _T_7786 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7797 = _T_4751 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7800 = _T_7318 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7801 = _T_7797 | _T_7800; // @[ifu_mem_ctl.scala 694:81] - wire _T_7802 = _T_7801 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7812 = _T_4752 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7815 = _T_7333 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7816 = _T_7812 | _T_7815; // @[ifu_mem_ctl.scala 694:81] - wire _T_7817 = _T_7816 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7827 = _T_4753 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7830 = _T_7348 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7831 = _T_7827 | _T_7830; // @[ifu_mem_ctl.scala 694:81] - wire _T_7832 = _T_7831 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7842 = _T_4754 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7845 = _T_7363 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7846 = _T_7842 | _T_7845; // @[ifu_mem_ctl.scala 694:81] - wire _T_7847 = _T_7846 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7857 = _T_4755 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7860 = _T_7378 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7861 = _T_7857 | _T_7860; // @[ifu_mem_ctl.scala 694:81] - wire _T_7862 = _T_7861 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7872 = _T_4756 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7875 = _T_7393 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7876 = _T_7872 | _T_7875; // @[ifu_mem_ctl.scala 694:81] - wire _T_7877 = _T_7876 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7887 = _T_4757 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7890 = _T_7408 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7891 = _T_7887 | _T_7890; // @[ifu_mem_ctl.scala 694:81] - wire _T_7892 = _T_7891 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7902 = _T_4758 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7905 = _T_7423 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7906 = _T_7902 | _T_7905; // @[ifu_mem_ctl.scala 694:81] - wire _T_7907 = _T_7906 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7917 = _T_4759 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7920 = _T_7438 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7921 = _T_7917 | _T_7920; // @[ifu_mem_ctl.scala 694:81] - wire _T_7922 = _T_7921 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7932 = _T_4760 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7935 = _T_7453 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7936 = _T_7932 | _T_7935; // @[ifu_mem_ctl.scala 694:81] - wire _T_7937 = _T_7936 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7947 = _T_4761 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7950 = _T_7468 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7951 = _T_7947 | _T_7950; // @[ifu_mem_ctl.scala 694:81] - wire _T_7952 = _T_7951 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7962 = _T_4762 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7965 = _T_7483 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7966 = _T_7962 | _T_7965; // @[ifu_mem_ctl.scala 694:81] - wire _T_7967 = _T_7966 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7977 = _T_4763 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7980 = _T_7498 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7981 = _T_7977 | _T_7980; // @[ifu_mem_ctl.scala 694:81] - wire _T_7982 = _T_7981 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_7992 = _T_4764 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_7995 = _T_7513 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_7996 = _T_7992 | _T_7995; // @[ifu_mem_ctl.scala 694:81] - wire _T_7997 = _T_7996 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8007 = _T_4765 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8010 = _T_7528 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8011 = _T_8007 | _T_8010; // @[ifu_mem_ctl.scala 694:81] - wire _T_8012 = _T_8011 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8022 = _T_4766 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8025 = _T_7543 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8026 = _T_8022 | _T_8025; // @[ifu_mem_ctl.scala 694:81] - wire _T_8027 = _T_8026 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8037 = _T_4767 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8038 = perr_ic_index_ff == 7'h60; // @[ifu_mem_ctl.scala 694:102] - wire _T_8040 = _T_8038 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8041 = _T_8037 | _T_8040; // @[ifu_mem_ctl.scala 694:81] - wire _T_8042 = _T_8041 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8052 = _T_4768 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8053 = perr_ic_index_ff == 7'h61; // @[ifu_mem_ctl.scala 694:102] - wire _T_8055 = _T_8053 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8056 = _T_8052 | _T_8055; // @[ifu_mem_ctl.scala 694:81] - wire _T_8057 = _T_8056 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8067 = _T_4769 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8068 = perr_ic_index_ff == 7'h62; // @[ifu_mem_ctl.scala 694:102] - wire _T_8070 = _T_8068 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8071 = _T_8067 | _T_8070; // @[ifu_mem_ctl.scala 694:81] - wire _T_8072 = _T_8071 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8082 = _T_4770 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8083 = perr_ic_index_ff == 7'h63; // @[ifu_mem_ctl.scala 694:102] - wire _T_8085 = _T_8083 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8086 = _T_8082 | _T_8085; // @[ifu_mem_ctl.scala 694:81] - wire _T_8087 = _T_8086 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8097 = _T_4771 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8098 = perr_ic_index_ff == 7'h64; // @[ifu_mem_ctl.scala 694:102] - wire _T_8100 = _T_8098 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8101 = _T_8097 | _T_8100; // @[ifu_mem_ctl.scala 694:81] - wire _T_8102 = _T_8101 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8112 = _T_4772 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8113 = perr_ic_index_ff == 7'h65; // @[ifu_mem_ctl.scala 694:102] - wire _T_8115 = _T_8113 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8116 = _T_8112 | _T_8115; // @[ifu_mem_ctl.scala 694:81] - wire _T_8117 = _T_8116 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8127 = _T_4773 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8128 = perr_ic_index_ff == 7'h66; // @[ifu_mem_ctl.scala 694:102] - wire _T_8130 = _T_8128 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8131 = _T_8127 | _T_8130; // @[ifu_mem_ctl.scala 694:81] - wire _T_8132 = _T_8131 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8142 = _T_4774 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8143 = perr_ic_index_ff == 7'h67; // @[ifu_mem_ctl.scala 694:102] - wire _T_8145 = _T_8143 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8146 = _T_8142 | _T_8145; // @[ifu_mem_ctl.scala 694:81] - wire _T_8147 = _T_8146 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8157 = _T_4775 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8158 = perr_ic_index_ff == 7'h68; // @[ifu_mem_ctl.scala 694:102] - wire _T_8160 = _T_8158 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8161 = _T_8157 | _T_8160; // @[ifu_mem_ctl.scala 694:81] - wire _T_8162 = _T_8161 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8172 = _T_4776 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8173 = perr_ic_index_ff == 7'h69; // @[ifu_mem_ctl.scala 694:102] - wire _T_8175 = _T_8173 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8176 = _T_8172 | _T_8175; // @[ifu_mem_ctl.scala 694:81] - wire _T_8177 = _T_8176 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8187 = _T_4777 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8188 = perr_ic_index_ff == 7'h6a; // @[ifu_mem_ctl.scala 694:102] - wire _T_8190 = _T_8188 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8191 = _T_8187 | _T_8190; // @[ifu_mem_ctl.scala 694:81] - wire _T_8192 = _T_8191 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8202 = _T_4778 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8203 = perr_ic_index_ff == 7'h6b; // @[ifu_mem_ctl.scala 694:102] - wire _T_8205 = _T_8203 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8206 = _T_8202 | _T_8205; // @[ifu_mem_ctl.scala 694:81] - wire _T_8207 = _T_8206 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8217 = _T_4779 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8218 = perr_ic_index_ff == 7'h6c; // @[ifu_mem_ctl.scala 694:102] - wire _T_8220 = _T_8218 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8221 = _T_8217 | _T_8220; // @[ifu_mem_ctl.scala 694:81] - wire _T_8222 = _T_8221 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8232 = _T_4780 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8233 = perr_ic_index_ff == 7'h6d; // @[ifu_mem_ctl.scala 694:102] - wire _T_8235 = _T_8233 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8236 = _T_8232 | _T_8235; // @[ifu_mem_ctl.scala 694:81] - wire _T_8237 = _T_8236 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8247 = _T_4781 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8248 = perr_ic_index_ff == 7'h6e; // @[ifu_mem_ctl.scala 694:102] - wire _T_8250 = _T_8248 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8251 = _T_8247 | _T_8250; // @[ifu_mem_ctl.scala 694:81] - wire _T_8252 = _T_8251 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8262 = _T_4782 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8263 = perr_ic_index_ff == 7'h6f; // @[ifu_mem_ctl.scala 694:102] - wire _T_8265 = _T_8263 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8266 = _T_8262 | _T_8265; // @[ifu_mem_ctl.scala 694:81] - wire _T_8267 = _T_8266 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8277 = _T_4783 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8278 = perr_ic_index_ff == 7'h70; // @[ifu_mem_ctl.scala 694:102] - wire _T_8280 = _T_8278 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8281 = _T_8277 | _T_8280; // @[ifu_mem_ctl.scala 694:81] - wire _T_8282 = _T_8281 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8292 = _T_4784 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8293 = perr_ic_index_ff == 7'h71; // @[ifu_mem_ctl.scala 694:102] - wire _T_8295 = _T_8293 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8296 = _T_8292 | _T_8295; // @[ifu_mem_ctl.scala 694:81] - wire _T_8297 = _T_8296 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8307 = _T_4785 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8308 = perr_ic_index_ff == 7'h72; // @[ifu_mem_ctl.scala 694:102] - wire _T_8310 = _T_8308 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8311 = _T_8307 | _T_8310; // @[ifu_mem_ctl.scala 694:81] - wire _T_8312 = _T_8311 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8322 = _T_4786 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8323 = perr_ic_index_ff == 7'h73; // @[ifu_mem_ctl.scala 694:102] - wire _T_8325 = _T_8323 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8326 = _T_8322 | _T_8325; // @[ifu_mem_ctl.scala 694:81] - wire _T_8327 = _T_8326 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8337 = _T_4787 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8338 = perr_ic_index_ff == 7'h74; // @[ifu_mem_ctl.scala 694:102] - wire _T_8340 = _T_8338 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8341 = _T_8337 | _T_8340; // @[ifu_mem_ctl.scala 694:81] - wire _T_8342 = _T_8341 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8352 = _T_4788 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8353 = perr_ic_index_ff == 7'h75; // @[ifu_mem_ctl.scala 694:102] - wire _T_8355 = _T_8353 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8356 = _T_8352 | _T_8355; // @[ifu_mem_ctl.scala 694:81] - wire _T_8357 = _T_8356 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8367 = _T_4789 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8368 = perr_ic_index_ff == 7'h76; // @[ifu_mem_ctl.scala 694:102] - wire _T_8370 = _T_8368 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8371 = _T_8367 | _T_8370; // @[ifu_mem_ctl.scala 694:81] - wire _T_8372 = _T_8371 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8382 = _T_4790 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8383 = perr_ic_index_ff == 7'h77; // @[ifu_mem_ctl.scala 694:102] - wire _T_8385 = _T_8383 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8386 = _T_8382 | _T_8385; // @[ifu_mem_ctl.scala 694:81] - wire _T_8387 = _T_8386 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8397 = _T_4791 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8398 = perr_ic_index_ff == 7'h78; // @[ifu_mem_ctl.scala 694:102] - wire _T_8400 = _T_8398 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8401 = _T_8397 | _T_8400; // @[ifu_mem_ctl.scala 694:81] - wire _T_8402 = _T_8401 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8412 = _T_4792 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8413 = perr_ic_index_ff == 7'h79; // @[ifu_mem_ctl.scala 694:102] - wire _T_8415 = _T_8413 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8416 = _T_8412 | _T_8415; // @[ifu_mem_ctl.scala 694:81] - wire _T_8417 = _T_8416 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8427 = _T_4793 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8428 = perr_ic_index_ff == 7'h7a; // @[ifu_mem_ctl.scala 694:102] - wire _T_8430 = _T_8428 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8431 = _T_8427 | _T_8430; // @[ifu_mem_ctl.scala 694:81] - wire _T_8432 = _T_8431 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8442 = _T_4794 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8443 = perr_ic_index_ff == 7'h7b; // @[ifu_mem_ctl.scala 694:102] - wire _T_8445 = _T_8443 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8446 = _T_8442 | _T_8445; // @[ifu_mem_ctl.scala 694:81] - wire _T_8447 = _T_8446 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8457 = _T_4795 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8458 = perr_ic_index_ff == 7'h7c; // @[ifu_mem_ctl.scala 694:102] - wire _T_8460 = _T_8458 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8461 = _T_8457 | _T_8460; // @[ifu_mem_ctl.scala 694:81] - wire _T_8462 = _T_8461 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8472 = _T_4796 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8473 = perr_ic_index_ff == 7'h7d; // @[ifu_mem_ctl.scala 694:102] - wire _T_8475 = _T_8473 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8476 = _T_8472 | _T_8475; // @[ifu_mem_ctl.scala 694:81] - wire _T_8477 = _T_8476 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8487 = _T_4797 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8488 = perr_ic_index_ff == 7'h7e; // @[ifu_mem_ctl.scala 694:102] - wire _T_8490 = _T_8488 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8491 = _T_8487 | _T_8490; // @[ifu_mem_ctl.scala 694:81] - wire _T_8492 = _T_8491 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8502 = _T_4798 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8503 = perr_ic_index_ff == 7'h7f; // @[ifu_mem_ctl.scala 694:102] - wire _T_8505 = _T_8503 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8506 = _T_8502 | _T_8505; // @[ifu_mem_ctl.scala 694:81] - wire _T_8507 = _T_8506 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8517 = _T_4767 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8520 = _T_8038 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8521 = _T_8517 | _T_8520; // @[ifu_mem_ctl.scala 694:81] - wire _T_8522 = _T_8521 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8532 = _T_4768 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8535 = _T_8053 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8536 = _T_8532 | _T_8535; // @[ifu_mem_ctl.scala 694:81] - wire _T_8537 = _T_8536 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8547 = _T_4769 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8550 = _T_8068 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8551 = _T_8547 | _T_8550; // @[ifu_mem_ctl.scala 694:81] - wire _T_8552 = _T_8551 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8562 = _T_4770 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8565 = _T_8083 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8566 = _T_8562 | _T_8565; // @[ifu_mem_ctl.scala 694:81] - wire _T_8567 = _T_8566 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8577 = _T_4771 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8580 = _T_8098 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8581 = _T_8577 | _T_8580; // @[ifu_mem_ctl.scala 694:81] - wire _T_8582 = _T_8581 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8592 = _T_4772 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8595 = _T_8113 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8596 = _T_8592 | _T_8595; // @[ifu_mem_ctl.scala 694:81] - wire _T_8597 = _T_8596 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8607 = _T_4773 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8610 = _T_8128 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8611 = _T_8607 | _T_8610; // @[ifu_mem_ctl.scala 694:81] - wire _T_8612 = _T_8611 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8622 = _T_4774 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8625 = _T_8143 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8626 = _T_8622 | _T_8625; // @[ifu_mem_ctl.scala 694:81] - wire _T_8627 = _T_8626 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8637 = _T_4775 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8640 = _T_8158 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8641 = _T_8637 | _T_8640; // @[ifu_mem_ctl.scala 694:81] - wire _T_8642 = _T_8641 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8652 = _T_4776 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8655 = _T_8173 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8656 = _T_8652 | _T_8655; // @[ifu_mem_ctl.scala 694:81] - wire _T_8657 = _T_8656 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8667 = _T_4777 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8670 = _T_8188 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8671 = _T_8667 | _T_8670; // @[ifu_mem_ctl.scala 694:81] - wire _T_8672 = _T_8671 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8682 = _T_4778 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8685 = _T_8203 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8686 = _T_8682 | _T_8685; // @[ifu_mem_ctl.scala 694:81] - wire _T_8687 = _T_8686 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8697 = _T_4779 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8700 = _T_8218 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8701 = _T_8697 | _T_8700; // @[ifu_mem_ctl.scala 694:81] - wire _T_8702 = _T_8701 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8712 = _T_4780 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8715 = _T_8233 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8716 = _T_8712 | _T_8715; // @[ifu_mem_ctl.scala 694:81] - wire _T_8717 = _T_8716 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8727 = _T_4781 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8730 = _T_8248 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8731 = _T_8727 | _T_8730; // @[ifu_mem_ctl.scala 694:81] - wire _T_8732 = _T_8731 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8742 = _T_4782 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8745 = _T_8263 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8746 = _T_8742 | _T_8745; // @[ifu_mem_ctl.scala 694:81] - wire _T_8747 = _T_8746 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8757 = _T_4783 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8760 = _T_8278 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8761 = _T_8757 | _T_8760; // @[ifu_mem_ctl.scala 694:81] - wire _T_8762 = _T_8761 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8772 = _T_4784 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8775 = _T_8293 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8776 = _T_8772 | _T_8775; // @[ifu_mem_ctl.scala 694:81] - wire _T_8777 = _T_8776 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8787 = _T_4785 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8790 = _T_8308 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8791 = _T_8787 | _T_8790; // @[ifu_mem_ctl.scala 694:81] - wire _T_8792 = _T_8791 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8802 = _T_4786 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8805 = _T_8323 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8806 = _T_8802 | _T_8805; // @[ifu_mem_ctl.scala 694:81] - wire _T_8807 = _T_8806 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8817 = _T_4787 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8820 = _T_8338 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8821 = _T_8817 | _T_8820; // @[ifu_mem_ctl.scala 694:81] - wire _T_8822 = _T_8821 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8832 = _T_4788 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8835 = _T_8353 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8836 = _T_8832 | _T_8835; // @[ifu_mem_ctl.scala 694:81] - wire _T_8837 = _T_8836 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8847 = _T_4789 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8850 = _T_8368 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8851 = _T_8847 | _T_8850; // @[ifu_mem_ctl.scala 694:81] - wire _T_8852 = _T_8851 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8862 = _T_4790 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8865 = _T_8383 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8866 = _T_8862 | _T_8865; // @[ifu_mem_ctl.scala 694:81] - wire _T_8867 = _T_8866 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8877 = _T_4791 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8880 = _T_8398 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8881 = _T_8877 | _T_8880; // @[ifu_mem_ctl.scala 694:81] - wire _T_8882 = _T_8881 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8892 = _T_4792 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8895 = _T_8413 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8896 = _T_8892 | _T_8895; // @[ifu_mem_ctl.scala 694:81] - wire _T_8897 = _T_8896 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8907 = _T_4793 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8910 = _T_8428 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8911 = _T_8907 | _T_8910; // @[ifu_mem_ctl.scala 694:81] - wire _T_8912 = _T_8911 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8922 = _T_4794 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8925 = _T_8443 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8926 = _T_8922 | _T_8925; // @[ifu_mem_ctl.scala 694:81] - wire _T_8927 = _T_8926 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8937 = _T_4795 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8940 = _T_8458 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8941 = _T_8937 | _T_8940; // @[ifu_mem_ctl.scala 694:81] - wire _T_8942 = _T_8941 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8952 = _T_4796 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8955 = _T_8473 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8956 = _T_8952 | _T_8955; // @[ifu_mem_ctl.scala 694:81] - wire _T_8957 = _T_8956 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8967 = _T_4797 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8970 = _T_8488 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8971 = _T_8967 | _T_8970; // @[ifu_mem_ctl.scala 694:81] - wire _T_8972 = _T_8971 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_8982 = _T_4798 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 694:59] - wire _T_8985 = _T_8503 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 694:124] - wire _T_8986 = _T_8982 | _T_8985; // @[ifu_mem_ctl.scala 694:81] - wire _T_8987 = _T_8986 | reset_all_tags; // @[ifu_mem_ctl.scala 694:147] - wire _T_9789 = ~fetch_uncacheable_ff; // @[ifu_mem_ctl.scala 748:63] - wire _T_9790 = _T_9789 & ifc_fetch_req_f; // @[ifu_mem_ctl.scala 748:85] + wire _T_5152 = ic_valid_ff & _T_195; // @[ifu_mem_ctl.scala 692:97] + wire _T_5153 = ~perr_sel_invalidate; // @[ifu_mem_ctl.scala 692:124] + wire _T_5154 = _T_5152 & _T_5153; // @[ifu_mem_ctl.scala 692:122] + wire _T_5157 = _T_4671 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5158 = perr_ic_index_ff == 7'h0; // @[ifu_mem_ctl.scala 693:102] + wire _T_5160 = _T_5158 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5161 = _T_5157 | _T_5160; // @[ifu_mem_ctl.scala 693:81] + wire _T_5162 = _T_5161 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5172 = _T_4672 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5173 = perr_ic_index_ff == 7'h1; // @[ifu_mem_ctl.scala 693:102] + wire _T_5175 = _T_5173 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5176 = _T_5172 | _T_5175; // @[ifu_mem_ctl.scala 693:81] + wire _T_5177 = _T_5176 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5187 = _T_4673 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5188 = perr_ic_index_ff == 7'h2; // @[ifu_mem_ctl.scala 693:102] + wire _T_5190 = _T_5188 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5191 = _T_5187 | _T_5190; // @[ifu_mem_ctl.scala 693:81] + wire _T_5192 = _T_5191 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5202 = _T_4674 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5203 = perr_ic_index_ff == 7'h3; // @[ifu_mem_ctl.scala 693:102] + wire _T_5205 = _T_5203 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5206 = _T_5202 | _T_5205; // @[ifu_mem_ctl.scala 693:81] + wire _T_5207 = _T_5206 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5217 = _T_4675 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5218 = perr_ic_index_ff == 7'h4; // @[ifu_mem_ctl.scala 693:102] + wire _T_5220 = _T_5218 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5221 = _T_5217 | _T_5220; // @[ifu_mem_ctl.scala 693:81] + wire _T_5222 = _T_5221 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5232 = _T_4676 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5233 = perr_ic_index_ff == 7'h5; // @[ifu_mem_ctl.scala 693:102] + wire _T_5235 = _T_5233 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5236 = _T_5232 | _T_5235; // @[ifu_mem_ctl.scala 693:81] + wire _T_5237 = _T_5236 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5247 = _T_4677 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5248 = perr_ic_index_ff == 7'h6; // @[ifu_mem_ctl.scala 693:102] + wire _T_5250 = _T_5248 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5251 = _T_5247 | _T_5250; // @[ifu_mem_ctl.scala 693:81] + wire _T_5252 = _T_5251 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5262 = _T_4678 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5263 = perr_ic_index_ff == 7'h7; // @[ifu_mem_ctl.scala 693:102] + wire _T_5265 = _T_5263 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5266 = _T_5262 | _T_5265; // @[ifu_mem_ctl.scala 693:81] + wire _T_5267 = _T_5266 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5277 = _T_4679 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5278 = perr_ic_index_ff == 7'h8; // @[ifu_mem_ctl.scala 693:102] + wire _T_5280 = _T_5278 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5281 = _T_5277 | _T_5280; // @[ifu_mem_ctl.scala 693:81] + wire _T_5282 = _T_5281 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5292 = _T_4680 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5293 = perr_ic_index_ff == 7'h9; // @[ifu_mem_ctl.scala 693:102] + wire _T_5295 = _T_5293 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5296 = _T_5292 | _T_5295; // @[ifu_mem_ctl.scala 693:81] + wire _T_5297 = _T_5296 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5307 = _T_4681 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5308 = perr_ic_index_ff == 7'ha; // @[ifu_mem_ctl.scala 693:102] + wire _T_5310 = _T_5308 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5311 = _T_5307 | _T_5310; // @[ifu_mem_ctl.scala 693:81] + wire _T_5312 = _T_5311 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5322 = _T_4682 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5323 = perr_ic_index_ff == 7'hb; // @[ifu_mem_ctl.scala 693:102] + wire _T_5325 = _T_5323 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5326 = _T_5322 | _T_5325; // @[ifu_mem_ctl.scala 693:81] + wire _T_5327 = _T_5326 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5337 = _T_4683 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5338 = perr_ic_index_ff == 7'hc; // @[ifu_mem_ctl.scala 693:102] + wire _T_5340 = _T_5338 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5341 = _T_5337 | _T_5340; // @[ifu_mem_ctl.scala 693:81] + wire _T_5342 = _T_5341 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5352 = _T_4684 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5353 = perr_ic_index_ff == 7'hd; // @[ifu_mem_ctl.scala 693:102] + wire _T_5355 = _T_5353 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5356 = _T_5352 | _T_5355; // @[ifu_mem_ctl.scala 693:81] + wire _T_5357 = _T_5356 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5367 = _T_4685 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5368 = perr_ic_index_ff == 7'he; // @[ifu_mem_ctl.scala 693:102] + wire _T_5370 = _T_5368 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5371 = _T_5367 | _T_5370; // @[ifu_mem_ctl.scala 693:81] + wire _T_5372 = _T_5371 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5382 = _T_4686 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5383 = perr_ic_index_ff == 7'hf; // @[ifu_mem_ctl.scala 693:102] + wire _T_5385 = _T_5383 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5386 = _T_5382 | _T_5385; // @[ifu_mem_ctl.scala 693:81] + wire _T_5387 = _T_5386 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5397 = _T_4687 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5398 = perr_ic_index_ff == 7'h10; // @[ifu_mem_ctl.scala 693:102] + wire _T_5400 = _T_5398 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5401 = _T_5397 | _T_5400; // @[ifu_mem_ctl.scala 693:81] + wire _T_5402 = _T_5401 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5412 = _T_4688 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5413 = perr_ic_index_ff == 7'h11; // @[ifu_mem_ctl.scala 693:102] + wire _T_5415 = _T_5413 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5416 = _T_5412 | _T_5415; // @[ifu_mem_ctl.scala 693:81] + wire _T_5417 = _T_5416 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5427 = _T_4689 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5428 = perr_ic_index_ff == 7'h12; // @[ifu_mem_ctl.scala 693:102] + wire _T_5430 = _T_5428 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5431 = _T_5427 | _T_5430; // @[ifu_mem_ctl.scala 693:81] + wire _T_5432 = _T_5431 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5442 = _T_4690 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5443 = perr_ic_index_ff == 7'h13; // @[ifu_mem_ctl.scala 693:102] + wire _T_5445 = _T_5443 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5446 = _T_5442 | _T_5445; // @[ifu_mem_ctl.scala 693:81] + wire _T_5447 = _T_5446 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5457 = _T_4691 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5458 = perr_ic_index_ff == 7'h14; // @[ifu_mem_ctl.scala 693:102] + wire _T_5460 = _T_5458 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5461 = _T_5457 | _T_5460; // @[ifu_mem_ctl.scala 693:81] + wire _T_5462 = _T_5461 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5472 = _T_4692 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5473 = perr_ic_index_ff == 7'h15; // @[ifu_mem_ctl.scala 693:102] + wire _T_5475 = _T_5473 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5476 = _T_5472 | _T_5475; // @[ifu_mem_ctl.scala 693:81] + wire _T_5477 = _T_5476 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5487 = _T_4693 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5488 = perr_ic_index_ff == 7'h16; // @[ifu_mem_ctl.scala 693:102] + wire _T_5490 = _T_5488 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5491 = _T_5487 | _T_5490; // @[ifu_mem_ctl.scala 693:81] + wire _T_5492 = _T_5491 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5502 = _T_4694 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5503 = perr_ic_index_ff == 7'h17; // @[ifu_mem_ctl.scala 693:102] + wire _T_5505 = _T_5503 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5506 = _T_5502 | _T_5505; // @[ifu_mem_ctl.scala 693:81] + wire _T_5507 = _T_5506 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5517 = _T_4695 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5518 = perr_ic_index_ff == 7'h18; // @[ifu_mem_ctl.scala 693:102] + wire _T_5520 = _T_5518 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5521 = _T_5517 | _T_5520; // @[ifu_mem_ctl.scala 693:81] + wire _T_5522 = _T_5521 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5532 = _T_4696 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5533 = perr_ic_index_ff == 7'h19; // @[ifu_mem_ctl.scala 693:102] + wire _T_5535 = _T_5533 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5536 = _T_5532 | _T_5535; // @[ifu_mem_ctl.scala 693:81] + wire _T_5537 = _T_5536 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5547 = _T_4697 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5548 = perr_ic_index_ff == 7'h1a; // @[ifu_mem_ctl.scala 693:102] + wire _T_5550 = _T_5548 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5551 = _T_5547 | _T_5550; // @[ifu_mem_ctl.scala 693:81] + wire _T_5552 = _T_5551 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5562 = _T_4698 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5563 = perr_ic_index_ff == 7'h1b; // @[ifu_mem_ctl.scala 693:102] + wire _T_5565 = _T_5563 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5566 = _T_5562 | _T_5565; // @[ifu_mem_ctl.scala 693:81] + wire _T_5567 = _T_5566 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5577 = _T_4699 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5578 = perr_ic_index_ff == 7'h1c; // @[ifu_mem_ctl.scala 693:102] + wire _T_5580 = _T_5578 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5581 = _T_5577 | _T_5580; // @[ifu_mem_ctl.scala 693:81] + wire _T_5582 = _T_5581 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5592 = _T_4700 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5593 = perr_ic_index_ff == 7'h1d; // @[ifu_mem_ctl.scala 693:102] + wire _T_5595 = _T_5593 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5596 = _T_5592 | _T_5595; // @[ifu_mem_ctl.scala 693:81] + wire _T_5597 = _T_5596 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5607 = _T_4701 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5608 = perr_ic_index_ff == 7'h1e; // @[ifu_mem_ctl.scala 693:102] + wire _T_5610 = _T_5608 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5611 = _T_5607 | _T_5610; // @[ifu_mem_ctl.scala 693:81] + wire _T_5612 = _T_5611 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5622 = _T_4702 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5623 = perr_ic_index_ff == 7'h1f; // @[ifu_mem_ctl.scala 693:102] + wire _T_5625 = _T_5623 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5626 = _T_5622 | _T_5625; // @[ifu_mem_ctl.scala 693:81] + wire _T_5627 = _T_5626 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5637 = _T_4671 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5640 = _T_5158 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5641 = _T_5637 | _T_5640; // @[ifu_mem_ctl.scala 693:81] + wire _T_5642 = _T_5641 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5652 = _T_4672 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5655 = _T_5173 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5656 = _T_5652 | _T_5655; // @[ifu_mem_ctl.scala 693:81] + wire _T_5657 = _T_5656 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5667 = _T_4673 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5670 = _T_5188 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5671 = _T_5667 | _T_5670; // @[ifu_mem_ctl.scala 693:81] + wire _T_5672 = _T_5671 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5682 = _T_4674 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5685 = _T_5203 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5686 = _T_5682 | _T_5685; // @[ifu_mem_ctl.scala 693:81] + wire _T_5687 = _T_5686 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5697 = _T_4675 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5700 = _T_5218 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5701 = _T_5697 | _T_5700; // @[ifu_mem_ctl.scala 693:81] + wire _T_5702 = _T_5701 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5712 = _T_4676 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5715 = _T_5233 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5716 = _T_5712 | _T_5715; // @[ifu_mem_ctl.scala 693:81] + wire _T_5717 = _T_5716 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5727 = _T_4677 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5730 = _T_5248 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5731 = _T_5727 | _T_5730; // @[ifu_mem_ctl.scala 693:81] + wire _T_5732 = _T_5731 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5742 = _T_4678 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5745 = _T_5263 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5746 = _T_5742 | _T_5745; // @[ifu_mem_ctl.scala 693:81] + wire _T_5747 = _T_5746 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5757 = _T_4679 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5760 = _T_5278 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5761 = _T_5757 | _T_5760; // @[ifu_mem_ctl.scala 693:81] + wire _T_5762 = _T_5761 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5772 = _T_4680 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5775 = _T_5293 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5776 = _T_5772 | _T_5775; // @[ifu_mem_ctl.scala 693:81] + wire _T_5777 = _T_5776 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5787 = _T_4681 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5790 = _T_5308 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5791 = _T_5787 | _T_5790; // @[ifu_mem_ctl.scala 693:81] + wire _T_5792 = _T_5791 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5802 = _T_4682 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5805 = _T_5323 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5806 = _T_5802 | _T_5805; // @[ifu_mem_ctl.scala 693:81] + wire _T_5807 = _T_5806 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5817 = _T_4683 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5820 = _T_5338 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5821 = _T_5817 | _T_5820; // @[ifu_mem_ctl.scala 693:81] + wire _T_5822 = _T_5821 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5832 = _T_4684 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5835 = _T_5353 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5836 = _T_5832 | _T_5835; // @[ifu_mem_ctl.scala 693:81] + wire _T_5837 = _T_5836 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5847 = _T_4685 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5850 = _T_5368 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5851 = _T_5847 | _T_5850; // @[ifu_mem_ctl.scala 693:81] + wire _T_5852 = _T_5851 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5862 = _T_4686 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5865 = _T_5383 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5866 = _T_5862 | _T_5865; // @[ifu_mem_ctl.scala 693:81] + wire _T_5867 = _T_5866 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5877 = _T_4687 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5880 = _T_5398 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5881 = _T_5877 | _T_5880; // @[ifu_mem_ctl.scala 693:81] + wire _T_5882 = _T_5881 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5892 = _T_4688 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5895 = _T_5413 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5896 = _T_5892 | _T_5895; // @[ifu_mem_ctl.scala 693:81] + wire _T_5897 = _T_5896 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5907 = _T_4689 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5910 = _T_5428 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5911 = _T_5907 | _T_5910; // @[ifu_mem_ctl.scala 693:81] + wire _T_5912 = _T_5911 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5922 = _T_4690 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5925 = _T_5443 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5926 = _T_5922 | _T_5925; // @[ifu_mem_ctl.scala 693:81] + wire _T_5927 = _T_5926 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5937 = _T_4691 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5940 = _T_5458 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5941 = _T_5937 | _T_5940; // @[ifu_mem_ctl.scala 693:81] + wire _T_5942 = _T_5941 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5952 = _T_4692 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5955 = _T_5473 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5956 = _T_5952 | _T_5955; // @[ifu_mem_ctl.scala 693:81] + wire _T_5957 = _T_5956 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5967 = _T_4693 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5970 = _T_5488 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5971 = _T_5967 | _T_5970; // @[ifu_mem_ctl.scala 693:81] + wire _T_5972 = _T_5971 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5982 = _T_4694 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_5985 = _T_5503 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_5986 = _T_5982 | _T_5985; // @[ifu_mem_ctl.scala 693:81] + wire _T_5987 = _T_5986 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_5997 = _T_4695 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6000 = _T_5518 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6001 = _T_5997 | _T_6000; // @[ifu_mem_ctl.scala 693:81] + wire _T_6002 = _T_6001 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6012 = _T_4696 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6015 = _T_5533 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6016 = _T_6012 | _T_6015; // @[ifu_mem_ctl.scala 693:81] + wire _T_6017 = _T_6016 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6027 = _T_4697 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6030 = _T_5548 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6031 = _T_6027 | _T_6030; // @[ifu_mem_ctl.scala 693:81] + wire _T_6032 = _T_6031 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6042 = _T_4698 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6045 = _T_5563 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6046 = _T_6042 | _T_6045; // @[ifu_mem_ctl.scala 693:81] + wire _T_6047 = _T_6046 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6057 = _T_4699 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6060 = _T_5578 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6061 = _T_6057 | _T_6060; // @[ifu_mem_ctl.scala 693:81] + wire _T_6062 = _T_6061 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6072 = _T_4700 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6075 = _T_5593 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6076 = _T_6072 | _T_6075; // @[ifu_mem_ctl.scala 693:81] + wire _T_6077 = _T_6076 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6087 = _T_4701 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6090 = _T_5608 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6091 = _T_6087 | _T_6090; // @[ifu_mem_ctl.scala 693:81] + wire _T_6092 = _T_6091 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6102 = _T_4702 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6105 = _T_5623 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6106 = _T_6102 | _T_6105; // @[ifu_mem_ctl.scala 693:81] + wire _T_6107 = _T_6106 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6117 = _T_4703 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6118 = perr_ic_index_ff == 7'h20; // @[ifu_mem_ctl.scala 693:102] + wire _T_6120 = _T_6118 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6121 = _T_6117 | _T_6120; // @[ifu_mem_ctl.scala 693:81] + wire _T_6122 = _T_6121 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6132 = _T_4704 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6133 = perr_ic_index_ff == 7'h21; // @[ifu_mem_ctl.scala 693:102] + wire _T_6135 = _T_6133 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6136 = _T_6132 | _T_6135; // @[ifu_mem_ctl.scala 693:81] + wire _T_6137 = _T_6136 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6147 = _T_4705 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6148 = perr_ic_index_ff == 7'h22; // @[ifu_mem_ctl.scala 693:102] + wire _T_6150 = _T_6148 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6151 = _T_6147 | _T_6150; // @[ifu_mem_ctl.scala 693:81] + wire _T_6152 = _T_6151 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6162 = _T_4706 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6163 = perr_ic_index_ff == 7'h23; // @[ifu_mem_ctl.scala 693:102] + wire _T_6165 = _T_6163 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6166 = _T_6162 | _T_6165; // @[ifu_mem_ctl.scala 693:81] + wire _T_6167 = _T_6166 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6177 = _T_4707 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6178 = perr_ic_index_ff == 7'h24; // @[ifu_mem_ctl.scala 693:102] + wire _T_6180 = _T_6178 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6181 = _T_6177 | _T_6180; // @[ifu_mem_ctl.scala 693:81] + wire _T_6182 = _T_6181 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6192 = _T_4708 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6193 = perr_ic_index_ff == 7'h25; // @[ifu_mem_ctl.scala 693:102] + wire _T_6195 = _T_6193 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6196 = _T_6192 | _T_6195; // @[ifu_mem_ctl.scala 693:81] + wire _T_6197 = _T_6196 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6207 = _T_4709 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6208 = perr_ic_index_ff == 7'h26; // @[ifu_mem_ctl.scala 693:102] + wire _T_6210 = _T_6208 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6211 = _T_6207 | _T_6210; // @[ifu_mem_ctl.scala 693:81] + wire _T_6212 = _T_6211 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6222 = _T_4710 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6223 = perr_ic_index_ff == 7'h27; // @[ifu_mem_ctl.scala 693:102] + wire _T_6225 = _T_6223 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6226 = _T_6222 | _T_6225; // @[ifu_mem_ctl.scala 693:81] + wire _T_6227 = _T_6226 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6237 = _T_4711 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6238 = perr_ic_index_ff == 7'h28; // @[ifu_mem_ctl.scala 693:102] + wire _T_6240 = _T_6238 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6241 = _T_6237 | _T_6240; // @[ifu_mem_ctl.scala 693:81] + wire _T_6242 = _T_6241 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6252 = _T_4712 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6253 = perr_ic_index_ff == 7'h29; // @[ifu_mem_ctl.scala 693:102] + wire _T_6255 = _T_6253 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6256 = _T_6252 | _T_6255; // @[ifu_mem_ctl.scala 693:81] + wire _T_6257 = _T_6256 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6267 = _T_4713 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6268 = perr_ic_index_ff == 7'h2a; // @[ifu_mem_ctl.scala 693:102] + wire _T_6270 = _T_6268 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6271 = _T_6267 | _T_6270; // @[ifu_mem_ctl.scala 693:81] + wire _T_6272 = _T_6271 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6282 = _T_4714 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6283 = perr_ic_index_ff == 7'h2b; // @[ifu_mem_ctl.scala 693:102] + wire _T_6285 = _T_6283 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6286 = _T_6282 | _T_6285; // @[ifu_mem_ctl.scala 693:81] + wire _T_6287 = _T_6286 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6297 = _T_4715 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6298 = perr_ic_index_ff == 7'h2c; // @[ifu_mem_ctl.scala 693:102] + wire _T_6300 = _T_6298 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6301 = _T_6297 | _T_6300; // @[ifu_mem_ctl.scala 693:81] + wire _T_6302 = _T_6301 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6312 = _T_4716 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6313 = perr_ic_index_ff == 7'h2d; // @[ifu_mem_ctl.scala 693:102] + wire _T_6315 = _T_6313 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6316 = _T_6312 | _T_6315; // @[ifu_mem_ctl.scala 693:81] + wire _T_6317 = _T_6316 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6327 = _T_4717 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6328 = perr_ic_index_ff == 7'h2e; // @[ifu_mem_ctl.scala 693:102] + wire _T_6330 = _T_6328 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6331 = _T_6327 | _T_6330; // @[ifu_mem_ctl.scala 693:81] + wire _T_6332 = _T_6331 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6342 = _T_4718 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6343 = perr_ic_index_ff == 7'h2f; // @[ifu_mem_ctl.scala 693:102] + wire _T_6345 = _T_6343 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6346 = _T_6342 | _T_6345; // @[ifu_mem_ctl.scala 693:81] + wire _T_6347 = _T_6346 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6357 = _T_4719 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6358 = perr_ic_index_ff == 7'h30; // @[ifu_mem_ctl.scala 693:102] + wire _T_6360 = _T_6358 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6361 = _T_6357 | _T_6360; // @[ifu_mem_ctl.scala 693:81] + wire _T_6362 = _T_6361 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6372 = _T_4720 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6373 = perr_ic_index_ff == 7'h31; // @[ifu_mem_ctl.scala 693:102] + wire _T_6375 = _T_6373 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6376 = _T_6372 | _T_6375; // @[ifu_mem_ctl.scala 693:81] + wire _T_6377 = _T_6376 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6387 = _T_4721 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6388 = perr_ic_index_ff == 7'h32; // @[ifu_mem_ctl.scala 693:102] + wire _T_6390 = _T_6388 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6391 = _T_6387 | _T_6390; // @[ifu_mem_ctl.scala 693:81] + wire _T_6392 = _T_6391 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6402 = _T_4722 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6403 = perr_ic_index_ff == 7'h33; // @[ifu_mem_ctl.scala 693:102] + wire _T_6405 = _T_6403 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6406 = _T_6402 | _T_6405; // @[ifu_mem_ctl.scala 693:81] + wire _T_6407 = _T_6406 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6417 = _T_4723 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6418 = perr_ic_index_ff == 7'h34; // @[ifu_mem_ctl.scala 693:102] + wire _T_6420 = _T_6418 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6421 = _T_6417 | _T_6420; // @[ifu_mem_ctl.scala 693:81] + wire _T_6422 = _T_6421 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6432 = _T_4724 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6433 = perr_ic_index_ff == 7'h35; // @[ifu_mem_ctl.scala 693:102] + wire _T_6435 = _T_6433 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6436 = _T_6432 | _T_6435; // @[ifu_mem_ctl.scala 693:81] + wire _T_6437 = _T_6436 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6447 = _T_4725 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6448 = perr_ic_index_ff == 7'h36; // @[ifu_mem_ctl.scala 693:102] + wire _T_6450 = _T_6448 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6451 = _T_6447 | _T_6450; // @[ifu_mem_ctl.scala 693:81] + wire _T_6452 = _T_6451 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6462 = _T_4726 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6463 = perr_ic_index_ff == 7'h37; // @[ifu_mem_ctl.scala 693:102] + wire _T_6465 = _T_6463 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6466 = _T_6462 | _T_6465; // @[ifu_mem_ctl.scala 693:81] + wire _T_6467 = _T_6466 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6477 = _T_4727 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6478 = perr_ic_index_ff == 7'h38; // @[ifu_mem_ctl.scala 693:102] + wire _T_6480 = _T_6478 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6481 = _T_6477 | _T_6480; // @[ifu_mem_ctl.scala 693:81] + wire _T_6482 = _T_6481 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6492 = _T_4728 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6493 = perr_ic_index_ff == 7'h39; // @[ifu_mem_ctl.scala 693:102] + wire _T_6495 = _T_6493 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6496 = _T_6492 | _T_6495; // @[ifu_mem_ctl.scala 693:81] + wire _T_6497 = _T_6496 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6507 = _T_4729 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6508 = perr_ic_index_ff == 7'h3a; // @[ifu_mem_ctl.scala 693:102] + wire _T_6510 = _T_6508 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6511 = _T_6507 | _T_6510; // @[ifu_mem_ctl.scala 693:81] + wire _T_6512 = _T_6511 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6522 = _T_4730 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6523 = perr_ic_index_ff == 7'h3b; // @[ifu_mem_ctl.scala 693:102] + wire _T_6525 = _T_6523 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6526 = _T_6522 | _T_6525; // @[ifu_mem_ctl.scala 693:81] + wire _T_6527 = _T_6526 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6537 = _T_4731 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6538 = perr_ic_index_ff == 7'h3c; // @[ifu_mem_ctl.scala 693:102] + wire _T_6540 = _T_6538 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6541 = _T_6537 | _T_6540; // @[ifu_mem_ctl.scala 693:81] + wire _T_6542 = _T_6541 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6552 = _T_4732 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6553 = perr_ic_index_ff == 7'h3d; // @[ifu_mem_ctl.scala 693:102] + wire _T_6555 = _T_6553 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6556 = _T_6552 | _T_6555; // @[ifu_mem_ctl.scala 693:81] + wire _T_6557 = _T_6556 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6567 = _T_4733 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6568 = perr_ic_index_ff == 7'h3e; // @[ifu_mem_ctl.scala 693:102] + wire _T_6570 = _T_6568 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6571 = _T_6567 | _T_6570; // @[ifu_mem_ctl.scala 693:81] + wire _T_6572 = _T_6571 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6582 = _T_4734 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6583 = perr_ic_index_ff == 7'h3f; // @[ifu_mem_ctl.scala 693:102] + wire _T_6585 = _T_6583 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6586 = _T_6582 | _T_6585; // @[ifu_mem_ctl.scala 693:81] + wire _T_6587 = _T_6586 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6597 = _T_4703 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6600 = _T_6118 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6601 = _T_6597 | _T_6600; // @[ifu_mem_ctl.scala 693:81] + wire _T_6602 = _T_6601 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6612 = _T_4704 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6615 = _T_6133 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6616 = _T_6612 | _T_6615; // @[ifu_mem_ctl.scala 693:81] + wire _T_6617 = _T_6616 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6627 = _T_4705 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6630 = _T_6148 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6631 = _T_6627 | _T_6630; // @[ifu_mem_ctl.scala 693:81] + wire _T_6632 = _T_6631 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6642 = _T_4706 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6645 = _T_6163 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6646 = _T_6642 | _T_6645; // @[ifu_mem_ctl.scala 693:81] + wire _T_6647 = _T_6646 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6657 = _T_4707 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6660 = _T_6178 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6661 = _T_6657 | _T_6660; // @[ifu_mem_ctl.scala 693:81] + wire _T_6662 = _T_6661 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6672 = _T_4708 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6675 = _T_6193 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6676 = _T_6672 | _T_6675; // @[ifu_mem_ctl.scala 693:81] + wire _T_6677 = _T_6676 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6687 = _T_4709 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6690 = _T_6208 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6691 = _T_6687 | _T_6690; // @[ifu_mem_ctl.scala 693:81] + wire _T_6692 = _T_6691 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6702 = _T_4710 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6705 = _T_6223 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6706 = _T_6702 | _T_6705; // @[ifu_mem_ctl.scala 693:81] + wire _T_6707 = _T_6706 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6717 = _T_4711 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6720 = _T_6238 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6721 = _T_6717 | _T_6720; // @[ifu_mem_ctl.scala 693:81] + wire _T_6722 = _T_6721 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6732 = _T_4712 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6735 = _T_6253 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6736 = _T_6732 | _T_6735; // @[ifu_mem_ctl.scala 693:81] + wire _T_6737 = _T_6736 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6747 = _T_4713 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6750 = _T_6268 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6751 = _T_6747 | _T_6750; // @[ifu_mem_ctl.scala 693:81] + wire _T_6752 = _T_6751 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6762 = _T_4714 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6765 = _T_6283 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6766 = _T_6762 | _T_6765; // @[ifu_mem_ctl.scala 693:81] + wire _T_6767 = _T_6766 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6777 = _T_4715 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6780 = _T_6298 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6781 = _T_6777 | _T_6780; // @[ifu_mem_ctl.scala 693:81] + wire _T_6782 = _T_6781 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6792 = _T_4716 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6795 = _T_6313 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6796 = _T_6792 | _T_6795; // @[ifu_mem_ctl.scala 693:81] + wire _T_6797 = _T_6796 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6807 = _T_4717 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6810 = _T_6328 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6811 = _T_6807 | _T_6810; // @[ifu_mem_ctl.scala 693:81] + wire _T_6812 = _T_6811 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6822 = _T_4718 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6825 = _T_6343 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6826 = _T_6822 | _T_6825; // @[ifu_mem_ctl.scala 693:81] + wire _T_6827 = _T_6826 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6837 = _T_4719 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6840 = _T_6358 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6841 = _T_6837 | _T_6840; // @[ifu_mem_ctl.scala 693:81] + wire _T_6842 = _T_6841 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6852 = _T_4720 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6855 = _T_6373 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6856 = _T_6852 | _T_6855; // @[ifu_mem_ctl.scala 693:81] + wire _T_6857 = _T_6856 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6867 = _T_4721 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6870 = _T_6388 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6871 = _T_6867 | _T_6870; // @[ifu_mem_ctl.scala 693:81] + wire _T_6872 = _T_6871 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6882 = _T_4722 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6885 = _T_6403 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6886 = _T_6882 | _T_6885; // @[ifu_mem_ctl.scala 693:81] + wire _T_6887 = _T_6886 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6897 = _T_4723 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6900 = _T_6418 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6901 = _T_6897 | _T_6900; // @[ifu_mem_ctl.scala 693:81] + wire _T_6902 = _T_6901 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6912 = _T_4724 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6915 = _T_6433 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6916 = _T_6912 | _T_6915; // @[ifu_mem_ctl.scala 693:81] + wire _T_6917 = _T_6916 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6927 = _T_4725 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6930 = _T_6448 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6931 = _T_6927 | _T_6930; // @[ifu_mem_ctl.scala 693:81] + wire _T_6932 = _T_6931 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6942 = _T_4726 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6945 = _T_6463 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6946 = _T_6942 | _T_6945; // @[ifu_mem_ctl.scala 693:81] + wire _T_6947 = _T_6946 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6957 = _T_4727 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6960 = _T_6478 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6961 = _T_6957 | _T_6960; // @[ifu_mem_ctl.scala 693:81] + wire _T_6962 = _T_6961 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6972 = _T_4728 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6975 = _T_6493 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6976 = _T_6972 | _T_6975; // @[ifu_mem_ctl.scala 693:81] + wire _T_6977 = _T_6976 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_6987 = _T_4729 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_6990 = _T_6508 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_6991 = _T_6987 | _T_6990; // @[ifu_mem_ctl.scala 693:81] + wire _T_6992 = _T_6991 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7002 = _T_4730 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7005 = _T_6523 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7006 = _T_7002 | _T_7005; // @[ifu_mem_ctl.scala 693:81] + wire _T_7007 = _T_7006 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7017 = _T_4731 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7020 = _T_6538 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7021 = _T_7017 | _T_7020; // @[ifu_mem_ctl.scala 693:81] + wire _T_7022 = _T_7021 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7032 = _T_4732 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7035 = _T_6553 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7036 = _T_7032 | _T_7035; // @[ifu_mem_ctl.scala 693:81] + wire _T_7037 = _T_7036 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7047 = _T_4733 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7050 = _T_6568 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7051 = _T_7047 | _T_7050; // @[ifu_mem_ctl.scala 693:81] + wire _T_7052 = _T_7051 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7062 = _T_4734 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7065 = _T_6583 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7066 = _T_7062 | _T_7065; // @[ifu_mem_ctl.scala 693:81] + wire _T_7067 = _T_7066 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7077 = _T_4735 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7078 = perr_ic_index_ff == 7'h40; // @[ifu_mem_ctl.scala 693:102] + wire _T_7080 = _T_7078 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7081 = _T_7077 | _T_7080; // @[ifu_mem_ctl.scala 693:81] + wire _T_7082 = _T_7081 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7092 = _T_4736 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7093 = perr_ic_index_ff == 7'h41; // @[ifu_mem_ctl.scala 693:102] + wire _T_7095 = _T_7093 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7096 = _T_7092 | _T_7095; // @[ifu_mem_ctl.scala 693:81] + wire _T_7097 = _T_7096 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7107 = _T_4737 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7108 = perr_ic_index_ff == 7'h42; // @[ifu_mem_ctl.scala 693:102] + wire _T_7110 = _T_7108 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7111 = _T_7107 | _T_7110; // @[ifu_mem_ctl.scala 693:81] + wire _T_7112 = _T_7111 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7122 = _T_4738 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7123 = perr_ic_index_ff == 7'h43; // @[ifu_mem_ctl.scala 693:102] + wire _T_7125 = _T_7123 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7126 = _T_7122 | _T_7125; // @[ifu_mem_ctl.scala 693:81] + wire _T_7127 = _T_7126 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7137 = _T_4739 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7138 = perr_ic_index_ff == 7'h44; // @[ifu_mem_ctl.scala 693:102] + wire _T_7140 = _T_7138 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7141 = _T_7137 | _T_7140; // @[ifu_mem_ctl.scala 693:81] + wire _T_7142 = _T_7141 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7152 = _T_4740 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7153 = perr_ic_index_ff == 7'h45; // @[ifu_mem_ctl.scala 693:102] + wire _T_7155 = _T_7153 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7156 = _T_7152 | _T_7155; // @[ifu_mem_ctl.scala 693:81] + wire _T_7157 = _T_7156 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7167 = _T_4741 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7168 = perr_ic_index_ff == 7'h46; // @[ifu_mem_ctl.scala 693:102] + wire _T_7170 = _T_7168 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7171 = _T_7167 | _T_7170; // @[ifu_mem_ctl.scala 693:81] + wire _T_7172 = _T_7171 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7182 = _T_4742 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7183 = perr_ic_index_ff == 7'h47; // @[ifu_mem_ctl.scala 693:102] + wire _T_7185 = _T_7183 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7186 = _T_7182 | _T_7185; // @[ifu_mem_ctl.scala 693:81] + wire _T_7187 = _T_7186 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7197 = _T_4743 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7198 = perr_ic_index_ff == 7'h48; // @[ifu_mem_ctl.scala 693:102] + wire _T_7200 = _T_7198 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7201 = _T_7197 | _T_7200; // @[ifu_mem_ctl.scala 693:81] + wire _T_7202 = _T_7201 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7212 = _T_4744 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7213 = perr_ic_index_ff == 7'h49; // @[ifu_mem_ctl.scala 693:102] + wire _T_7215 = _T_7213 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7216 = _T_7212 | _T_7215; // @[ifu_mem_ctl.scala 693:81] + wire _T_7217 = _T_7216 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7227 = _T_4745 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7228 = perr_ic_index_ff == 7'h4a; // @[ifu_mem_ctl.scala 693:102] + wire _T_7230 = _T_7228 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7231 = _T_7227 | _T_7230; // @[ifu_mem_ctl.scala 693:81] + wire _T_7232 = _T_7231 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7242 = _T_4746 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7243 = perr_ic_index_ff == 7'h4b; // @[ifu_mem_ctl.scala 693:102] + wire _T_7245 = _T_7243 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7246 = _T_7242 | _T_7245; // @[ifu_mem_ctl.scala 693:81] + wire _T_7247 = _T_7246 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7257 = _T_4747 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7258 = perr_ic_index_ff == 7'h4c; // @[ifu_mem_ctl.scala 693:102] + wire _T_7260 = _T_7258 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7261 = _T_7257 | _T_7260; // @[ifu_mem_ctl.scala 693:81] + wire _T_7262 = _T_7261 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7272 = _T_4748 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7273 = perr_ic_index_ff == 7'h4d; // @[ifu_mem_ctl.scala 693:102] + wire _T_7275 = _T_7273 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7276 = _T_7272 | _T_7275; // @[ifu_mem_ctl.scala 693:81] + wire _T_7277 = _T_7276 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7287 = _T_4749 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7288 = perr_ic_index_ff == 7'h4e; // @[ifu_mem_ctl.scala 693:102] + wire _T_7290 = _T_7288 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7291 = _T_7287 | _T_7290; // @[ifu_mem_ctl.scala 693:81] + wire _T_7292 = _T_7291 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7302 = _T_4750 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7303 = perr_ic_index_ff == 7'h4f; // @[ifu_mem_ctl.scala 693:102] + wire _T_7305 = _T_7303 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7306 = _T_7302 | _T_7305; // @[ifu_mem_ctl.scala 693:81] + wire _T_7307 = _T_7306 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7317 = _T_4751 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7318 = perr_ic_index_ff == 7'h50; // @[ifu_mem_ctl.scala 693:102] + wire _T_7320 = _T_7318 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7321 = _T_7317 | _T_7320; // @[ifu_mem_ctl.scala 693:81] + wire _T_7322 = _T_7321 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7332 = _T_4752 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7333 = perr_ic_index_ff == 7'h51; // @[ifu_mem_ctl.scala 693:102] + wire _T_7335 = _T_7333 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7336 = _T_7332 | _T_7335; // @[ifu_mem_ctl.scala 693:81] + wire _T_7337 = _T_7336 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7347 = _T_4753 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7348 = perr_ic_index_ff == 7'h52; // @[ifu_mem_ctl.scala 693:102] + wire _T_7350 = _T_7348 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7351 = _T_7347 | _T_7350; // @[ifu_mem_ctl.scala 693:81] + wire _T_7352 = _T_7351 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7362 = _T_4754 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7363 = perr_ic_index_ff == 7'h53; // @[ifu_mem_ctl.scala 693:102] + wire _T_7365 = _T_7363 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7366 = _T_7362 | _T_7365; // @[ifu_mem_ctl.scala 693:81] + wire _T_7367 = _T_7366 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7377 = _T_4755 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7378 = perr_ic_index_ff == 7'h54; // @[ifu_mem_ctl.scala 693:102] + wire _T_7380 = _T_7378 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7381 = _T_7377 | _T_7380; // @[ifu_mem_ctl.scala 693:81] + wire _T_7382 = _T_7381 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7392 = _T_4756 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7393 = perr_ic_index_ff == 7'h55; // @[ifu_mem_ctl.scala 693:102] + wire _T_7395 = _T_7393 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7396 = _T_7392 | _T_7395; // @[ifu_mem_ctl.scala 693:81] + wire _T_7397 = _T_7396 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7407 = _T_4757 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7408 = perr_ic_index_ff == 7'h56; // @[ifu_mem_ctl.scala 693:102] + wire _T_7410 = _T_7408 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7411 = _T_7407 | _T_7410; // @[ifu_mem_ctl.scala 693:81] + wire _T_7412 = _T_7411 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7422 = _T_4758 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7423 = perr_ic_index_ff == 7'h57; // @[ifu_mem_ctl.scala 693:102] + wire _T_7425 = _T_7423 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7426 = _T_7422 | _T_7425; // @[ifu_mem_ctl.scala 693:81] + wire _T_7427 = _T_7426 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7437 = _T_4759 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7438 = perr_ic_index_ff == 7'h58; // @[ifu_mem_ctl.scala 693:102] + wire _T_7440 = _T_7438 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7441 = _T_7437 | _T_7440; // @[ifu_mem_ctl.scala 693:81] + wire _T_7442 = _T_7441 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7452 = _T_4760 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7453 = perr_ic_index_ff == 7'h59; // @[ifu_mem_ctl.scala 693:102] + wire _T_7455 = _T_7453 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7456 = _T_7452 | _T_7455; // @[ifu_mem_ctl.scala 693:81] + wire _T_7457 = _T_7456 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7467 = _T_4761 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7468 = perr_ic_index_ff == 7'h5a; // @[ifu_mem_ctl.scala 693:102] + wire _T_7470 = _T_7468 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7471 = _T_7467 | _T_7470; // @[ifu_mem_ctl.scala 693:81] + wire _T_7472 = _T_7471 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7482 = _T_4762 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7483 = perr_ic_index_ff == 7'h5b; // @[ifu_mem_ctl.scala 693:102] + wire _T_7485 = _T_7483 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7486 = _T_7482 | _T_7485; // @[ifu_mem_ctl.scala 693:81] + wire _T_7487 = _T_7486 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7497 = _T_4763 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7498 = perr_ic_index_ff == 7'h5c; // @[ifu_mem_ctl.scala 693:102] + wire _T_7500 = _T_7498 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7501 = _T_7497 | _T_7500; // @[ifu_mem_ctl.scala 693:81] + wire _T_7502 = _T_7501 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7512 = _T_4764 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7513 = perr_ic_index_ff == 7'h5d; // @[ifu_mem_ctl.scala 693:102] + wire _T_7515 = _T_7513 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7516 = _T_7512 | _T_7515; // @[ifu_mem_ctl.scala 693:81] + wire _T_7517 = _T_7516 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7527 = _T_4765 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7528 = perr_ic_index_ff == 7'h5e; // @[ifu_mem_ctl.scala 693:102] + wire _T_7530 = _T_7528 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7531 = _T_7527 | _T_7530; // @[ifu_mem_ctl.scala 693:81] + wire _T_7532 = _T_7531 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7542 = _T_4766 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7543 = perr_ic_index_ff == 7'h5f; // @[ifu_mem_ctl.scala 693:102] + wire _T_7545 = _T_7543 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7546 = _T_7542 | _T_7545; // @[ifu_mem_ctl.scala 693:81] + wire _T_7547 = _T_7546 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7557 = _T_4735 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7560 = _T_7078 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7561 = _T_7557 | _T_7560; // @[ifu_mem_ctl.scala 693:81] + wire _T_7562 = _T_7561 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7572 = _T_4736 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7575 = _T_7093 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7576 = _T_7572 | _T_7575; // @[ifu_mem_ctl.scala 693:81] + wire _T_7577 = _T_7576 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7587 = _T_4737 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7590 = _T_7108 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7591 = _T_7587 | _T_7590; // @[ifu_mem_ctl.scala 693:81] + wire _T_7592 = _T_7591 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7602 = _T_4738 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7605 = _T_7123 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7606 = _T_7602 | _T_7605; // @[ifu_mem_ctl.scala 693:81] + wire _T_7607 = _T_7606 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7617 = _T_4739 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7620 = _T_7138 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7621 = _T_7617 | _T_7620; // @[ifu_mem_ctl.scala 693:81] + wire _T_7622 = _T_7621 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7632 = _T_4740 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7635 = _T_7153 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7636 = _T_7632 | _T_7635; // @[ifu_mem_ctl.scala 693:81] + wire _T_7637 = _T_7636 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7647 = _T_4741 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7650 = _T_7168 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7651 = _T_7647 | _T_7650; // @[ifu_mem_ctl.scala 693:81] + wire _T_7652 = _T_7651 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7662 = _T_4742 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7665 = _T_7183 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7666 = _T_7662 | _T_7665; // @[ifu_mem_ctl.scala 693:81] + wire _T_7667 = _T_7666 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7677 = _T_4743 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7680 = _T_7198 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7681 = _T_7677 | _T_7680; // @[ifu_mem_ctl.scala 693:81] + wire _T_7682 = _T_7681 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7692 = _T_4744 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7695 = _T_7213 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7696 = _T_7692 | _T_7695; // @[ifu_mem_ctl.scala 693:81] + wire _T_7697 = _T_7696 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7707 = _T_4745 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7710 = _T_7228 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7711 = _T_7707 | _T_7710; // @[ifu_mem_ctl.scala 693:81] + wire _T_7712 = _T_7711 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7722 = _T_4746 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7725 = _T_7243 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7726 = _T_7722 | _T_7725; // @[ifu_mem_ctl.scala 693:81] + wire _T_7727 = _T_7726 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7737 = _T_4747 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7740 = _T_7258 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7741 = _T_7737 | _T_7740; // @[ifu_mem_ctl.scala 693:81] + wire _T_7742 = _T_7741 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7752 = _T_4748 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7755 = _T_7273 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7756 = _T_7752 | _T_7755; // @[ifu_mem_ctl.scala 693:81] + wire _T_7757 = _T_7756 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7767 = _T_4749 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7770 = _T_7288 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7771 = _T_7767 | _T_7770; // @[ifu_mem_ctl.scala 693:81] + wire _T_7772 = _T_7771 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7782 = _T_4750 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7785 = _T_7303 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7786 = _T_7782 | _T_7785; // @[ifu_mem_ctl.scala 693:81] + wire _T_7787 = _T_7786 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7797 = _T_4751 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7800 = _T_7318 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7801 = _T_7797 | _T_7800; // @[ifu_mem_ctl.scala 693:81] + wire _T_7802 = _T_7801 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7812 = _T_4752 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7815 = _T_7333 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7816 = _T_7812 | _T_7815; // @[ifu_mem_ctl.scala 693:81] + wire _T_7817 = _T_7816 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7827 = _T_4753 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7830 = _T_7348 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7831 = _T_7827 | _T_7830; // @[ifu_mem_ctl.scala 693:81] + wire _T_7832 = _T_7831 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7842 = _T_4754 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7845 = _T_7363 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7846 = _T_7842 | _T_7845; // @[ifu_mem_ctl.scala 693:81] + wire _T_7847 = _T_7846 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7857 = _T_4755 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7860 = _T_7378 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7861 = _T_7857 | _T_7860; // @[ifu_mem_ctl.scala 693:81] + wire _T_7862 = _T_7861 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7872 = _T_4756 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7875 = _T_7393 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7876 = _T_7872 | _T_7875; // @[ifu_mem_ctl.scala 693:81] + wire _T_7877 = _T_7876 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7887 = _T_4757 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7890 = _T_7408 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7891 = _T_7887 | _T_7890; // @[ifu_mem_ctl.scala 693:81] + wire _T_7892 = _T_7891 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7902 = _T_4758 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7905 = _T_7423 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7906 = _T_7902 | _T_7905; // @[ifu_mem_ctl.scala 693:81] + wire _T_7907 = _T_7906 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7917 = _T_4759 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7920 = _T_7438 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7921 = _T_7917 | _T_7920; // @[ifu_mem_ctl.scala 693:81] + wire _T_7922 = _T_7921 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7932 = _T_4760 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7935 = _T_7453 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7936 = _T_7932 | _T_7935; // @[ifu_mem_ctl.scala 693:81] + wire _T_7937 = _T_7936 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7947 = _T_4761 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7950 = _T_7468 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7951 = _T_7947 | _T_7950; // @[ifu_mem_ctl.scala 693:81] + wire _T_7952 = _T_7951 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7962 = _T_4762 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7965 = _T_7483 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7966 = _T_7962 | _T_7965; // @[ifu_mem_ctl.scala 693:81] + wire _T_7967 = _T_7966 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7977 = _T_4763 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7980 = _T_7498 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7981 = _T_7977 | _T_7980; // @[ifu_mem_ctl.scala 693:81] + wire _T_7982 = _T_7981 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_7992 = _T_4764 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_7995 = _T_7513 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_7996 = _T_7992 | _T_7995; // @[ifu_mem_ctl.scala 693:81] + wire _T_7997 = _T_7996 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8007 = _T_4765 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8010 = _T_7528 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8011 = _T_8007 | _T_8010; // @[ifu_mem_ctl.scala 693:81] + wire _T_8012 = _T_8011 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8022 = _T_4766 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8025 = _T_7543 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8026 = _T_8022 | _T_8025; // @[ifu_mem_ctl.scala 693:81] + wire _T_8027 = _T_8026 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8037 = _T_4767 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8038 = perr_ic_index_ff == 7'h60; // @[ifu_mem_ctl.scala 693:102] + wire _T_8040 = _T_8038 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8041 = _T_8037 | _T_8040; // @[ifu_mem_ctl.scala 693:81] + wire _T_8042 = _T_8041 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8052 = _T_4768 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8053 = perr_ic_index_ff == 7'h61; // @[ifu_mem_ctl.scala 693:102] + wire _T_8055 = _T_8053 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8056 = _T_8052 | _T_8055; // @[ifu_mem_ctl.scala 693:81] + wire _T_8057 = _T_8056 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8067 = _T_4769 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8068 = perr_ic_index_ff == 7'h62; // @[ifu_mem_ctl.scala 693:102] + wire _T_8070 = _T_8068 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8071 = _T_8067 | _T_8070; // @[ifu_mem_ctl.scala 693:81] + wire _T_8072 = _T_8071 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8082 = _T_4770 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8083 = perr_ic_index_ff == 7'h63; // @[ifu_mem_ctl.scala 693:102] + wire _T_8085 = _T_8083 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8086 = _T_8082 | _T_8085; // @[ifu_mem_ctl.scala 693:81] + wire _T_8087 = _T_8086 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8097 = _T_4771 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8098 = perr_ic_index_ff == 7'h64; // @[ifu_mem_ctl.scala 693:102] + wire _T_8100 = _T_8098 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8101 = _T_8097 | _T_8100; // @[ifu_mem_ctl.scala 693:81] + wire _T_8102 = _T_8101 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8112 = _T_4772 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8113 = perr_ic_index_ff == 7'h65; // @[ifu_mem_ctl.scala 693:102] + wire _T_8115 = _T_8113 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8116 = _T_8112 | _T_8115; // @[ifu_mem_ctl.scala 693:81] + wire _T_8117 = _T_8116 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8127 = _T_4773 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8128 = perr_ic_index_ff == 7'h66; // @[ifu_mem_ctl.scala 693:102] + wire _T_8130 = _T_8128 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8131 = _T_8127 | _T_8130; // @[ifu_mem_ctl.scala 693:81] + wire _T_8132 = _T_8131 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8142 = _T_4774 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8143 = perr_ic_index_ff == 7'h67; // @[ifu_mem_ctl.scala 693:102] + wire _T_8145 = _T_8143 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8146 = _T_8142 | _T_8145; // @[ifu_mem_ctl.scala 693:81] + wire _T_8147 = _T_8146 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8157 = _T_4775 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8158 = perr_ic_index_ff == 7'h68; // @[ifu_mem_ctl.scala 693:102] + wire _T_8160 = _T_8158 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8161 = _T_8157 | _T_8160; // @[ifu_mem_ctl.scala 693:81] + wire _T_8162 = _T_8161 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8172 = _T_4776 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8173 = perr_ic_index_ff == 7'h69; // @[ifu_mem_ctl.scala 693:102] + wire _T_8175 = _T_8173 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8176 = _T_8172 | _T_8175; // @[ifu_mem_ctl.scala 693:81] + wire _T_8177 = _T_8176 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8187 = _T_4777 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8188 = perr_ic_index_ff == 7'h6a; // @[ifu_mem_ctl.scala 693:102] + wire _T_8190 = _T_8188 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8191 = _T_8187 | _T_8190; // @[ifu_mem_ctl.scala 693:81] + wire _T_8192 = _T_8191 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8202 = _T_4778 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8203 = perr_ic_index_ff == 7'h6b; // @[ifu_mem_ctl.scala 693:102] + wire _T_8205 = _T_8203 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8206 = _T_8202 | _T_8205; // @[ifu_mem_ctl.scala 693:81] + wire _T_8207 = _T_8206 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8217 = _T_4779 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8218 = perr_ic_index_ff == 7'h6c; // @[ifu_mem_ctl.scala 693:102] + wire _T_8220 = _T_8218 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8221 = _T_8217 | _T_8220; // @[ifu_mem_ctl.scala 693:81] + wire _T_8222 = _T_8221 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8232 = _T_4780 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8233 = perr_ic_index_ff == 7'h6d; // @[ifu_mem_ctl.scala 693:102] + wire _T_8235 = _T_8233 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8236 = _T_8232 | _T_8235; // @[ifu_mem_ctl.scala 693:81] + wire _T_8237 = _T_8236 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8247 = _T_4781 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8248 = perr_ic_index_ff == 7'h6e; // @[ifu_mem_ctl.scala 693:102] + wire _T_8250 = _T_8248 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8251 = _T_8247 | _T_8250; // @[ifu_mem_ctl.scala 693:81] + wire _T_8252 = _T_8251 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8262 = _T_4782 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8263 = perr_ic_index_ff == 7'h6f; // @[ifu_mem_ctl.scala 693:102] + wire _T_8265 = _T_8263 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8266 = _T_8262 | _T_8265; // @[ifu_mem_ctl.scala 693:81] + wire _T_8267 = _T_8266 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8277 = _T_4783 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8278 = perr_ic_index_ff == 7'h70; // @[ifu_mem_ctl.scala 693:102] + wire _T_8280 = _T_8278 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8281 = _T_8277 | _T_8280; // @[ifu_mem_ctl.scala 693:81] + wire _T_8282 = _T_8281 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8292 = _T_4784 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8293 = perr_ic_index_ff == 7'h71; // @[ifu_mem_ctl.scala 693:102] + wire _T_8295 = _T_8293 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8296 = _T_8292 | _T_8295; // @[ifu_mem_ctl.scala 693:81] + wire _T_8297 = _T_8296 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8307 = _T_4785 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8308 = perr_ic_index_ff == 7'h72; // @[ifu_mem_ctl.scala 693:102] + wire _T_8310 = _T_8308 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8311 = _T_8307 | _T_8310; // @[ifu_mem_ctl.scala 693:81] + wire _T_8312 = _T_8311 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8322 = _T_4786 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8323 = perr_ic_index_ff == 7'h73; // @[ifu_mem_ctl.scala 693:102] + wire _T_8325 = _T_8323 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8326 = _T_8322 | _T_8325; // @[ifu_mem_ctl.scala 693:81] + wire _T_8327 = _T_8326 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8337 = _T_4787 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8338 = perr_ic_index_ff == 7'h74; // @[ifu_mem_ctl.scala 693:102] + wire _T_8340 = _T_8338 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8341 = _T_8337 | _T_8340; // @[ifu_mem_ctl.scala 693:81] + wire _T_8342 = _T_8341 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8352 = _T_4788 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8353 = perr_ic_index_ff == 7'h75; // @[ifu_mem_ctl.scala 693:102] + wire _T_8355 = _T_8353 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8356 = _T_8352 | _T_8355; // @[ifu_mem_ctl.scala 693:81] + wire _T_8357 = _T_8356 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8367 = _T_4789 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8368 = perr_ic_index_ff == 7'h76; // @[ifu_mem_ctl.scala 693:102] + wire _T_8370 = _T_8368 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8371 = _T_8367 | _T_8370; // @[ifu_mem_ctl.scala 693:81] + wire _T_8372 = _T_8371 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8382 = _T_4790 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8383 = perr_ic_index_ff == 7'h77; // @[ifu_mem_ctl.scala 693:102] + wire _T_8385 = _T_8383 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8386 = _T_8382 | _T_8385; // @[ifu_mem_ctl.scala 693:81] + wire _T_8387 = _T_8386 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8397 = _T_4791 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8398 = perr_ic_index_ff == 7'h78; // @[ifu_mem_ctl.scala 693:102] + wire _T_8400 = _T_8398 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8401 = _T_8397 | _T_8400; // @[ifu_mem_ctl.scala 693:81] + wire _T_8402 = _T_8401 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8412 = _T_4792 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8413 = perr_ic_index_ff == 7'h79; // @[ifu_mem_ctl.scala 693:102] + wire _T_8415 = _T_8413 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8416 = _T_8412 | _T_8415; // @[ifu_mem_ctl.scala 693:81] + wire _T_8417 = _T_8416 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8427 = _T_4793 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8428 = perr_ic_index_ff == 7'h7a; // @[ifu_mem_ctl.scala 693:102] + wire _T_8430 = _T_8428 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8431 = _T_8427 | _T_8430; // @[ifu_mem_ctl.scala 693:81] + wire _T_8432 = _T_8431 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8442 = _T_4794 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8443 = perr_ic_index_ff == 7'h7b; // @[ifu_mem_ctl.scala 693:102] + wire _T_8445 = _T_8443 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8446 = _T_8442 | _T_8445; // @[ifu_mem_ctl.scala 693:81] + wire _T_8447 = _T_8446 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8457 = _T_4795 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8458 = perr_ic_index_ff == 7'h7c; // @[ifu_mem_ctl.scala 693:102] + wire _T_8460 = _T_8458 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8461 = _T_8457 | _T_8460; // @[ifu_mem_ctl.scala 693:81] + wire _T_8462 = _T_8461 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8472 = _T_4796 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8473 = perr_ic_index_ff == 7'h7d; // @[ifu_mem_ctl.scala 693:102] + wire _T_8475 = _T_8473 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8476 = _T_8472 | _T_8475; // @[ifu_mem_ctl.scala 693:81] + wire _T_8477 = _T_8476 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8487 = _T_4797 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8488 = perr_ic_index_ff == 7'h7e; // @[ifu_mem_ctl.scala 693:102] + wire _T_8490 = _T_8488 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8491 = _T_8487 | _T_8490; // @[ifu_mem_ctl.scala 693:81] + wire _T_8492 = _T_8491 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8502 = _T_4798 & ifu_tag_wren_ff[0]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8503 = perr_ic_index_ff == 7'h7f; // @[ifu_mem_ctl.scala 693:102] + wire _T_8505 = _T_8503 & perr_err_inv_way[0]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8506 = _T_8502 | _T_8505; // @[ifu_mem_ctl.scala 693:81] + wire _T_8507 = _T_8506 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8517 = _T_4767 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8520 = _T_8038 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8521 = _T_8517 | _T_8520; // @[ifu_mem_ctl.scala 693:81] + wire _T_8522 = _T_8521 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8532 = _T_4768 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8535 = _T_8053 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8536 = _T_8532 | _T_8535; // @[ifu_mem_ctl.scala 693:81] + wire _T_8537 = _T_8536 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8547 = _T_4769 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8550 = _T_8068 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8551 = _T_8547 | _T_8550; // @[ifu_mem_ctl.scala 693:81] + wire _T_8552 = _T_8551 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8562 = _T_4770 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8565 = _T_8083 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8566 = _T_8562 | _T_8565; // @[ifu_mem_ctl.scala 693:81] + wire _T_8567 = _T_8566 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8577 = _T_4771 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8580 = _T_8098 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8581 = _T_8577 | _T_8580; // @[ifu_mem_ctl.scala 693:81] + wire _T_8582 = _T_8581 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8592 = _T_4772 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8595 = _T_8113 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8596 = _T_8592 | _T_8595; // @[ifu_mem_ctl.scala 693:81] + wire _T_8597 = _T_8596 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8607 = _T_4773 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8610 = _T_8128 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8611 = _T_8607 | _T_8610; // @[ifu_mem_ctl.scala 693:81] + wire _T_8612 = _T_8611 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8622 = _T_4774 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8625 = _T_8143 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8626 = _T_8622 | _T_8625; // @[ifu_mem_ctl.scala 693:81] + wire _T_8627 = _T_8626 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8637 = _T_4775 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8640 = _T_8158 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8641 = _T_8637 | _T_8640; // @[ifu_mem_ctl.scala 693:81] + wire _T_8642 = _T_8641 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8652 = _T_4776 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8655 = _T_8173 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8656 = _T_8652 | _T_8655; // @[ifu_mem_ctl.scala 693:81] + wire _T_8657 = _T_8656 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8667 = _T_4777 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8670 = _T_8188 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8671 = _T_8667 | _T_8670; // @[ifu_mem_ctl.scala 693:81] + wire _T_8672 = _T_8671 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8682 = _T_4778 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8685 = _T_8203 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8686 = _T_8682 | _T_8685; // @[ifu_mem_ctl.scala 693:81] + wire _T_8687 = _T_8686 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8697 = _T_4779 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8700 = _T_8218 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8701 = _T_8697 | _T_8700; // @[ifu_mem_ctl.scala 693:81] + wire _T_8702 = _T_8701 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8712 = _T_4780 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8715 = _T_8233 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8716 = _T_8712 | _T_8715; // @[ifu_mem_ctl.scala 693:81] + wire _T_8717 = _T_8716 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8727 = _T_4781 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8730 = _T_8248 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8731 = _T_8727 | _T_8730; // @[ifu_mem_ctl.scala 693:81] + wire _T_8732 = _T_8731 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8742 = _T_4782 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8745 = _T_8263 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8746 = _T_8742 | _T_8745; // @[ifu_mem_ctl.scala 693:81] + wire _T_8747 = _T_8746 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8757 = _T_4783 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8760 = _T_8278 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8761 = _T_8757 | _T_8760; // @[ifu_mem_ctl.scala 693:81] + wire _T_8762 = _T_8761 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8772 = _T_4784 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8775 = _T_8293 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8776 = _T_8772 | _T_8775; // @[ifu_mem_ctl.scala 693:81] + wire _T_8777 = _T_8776 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8787 = _T_4785 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8790 = _T_8308 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8791 = _T_8787 | _T_8790; // @[ifu_mem_ctl.scala 693:81] + wire _T_8792 = _T_8791 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8802 = _T_4786 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8805 = _T_8323 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8806 = _T_8802 | _T_8805; // @[ifu_mem_ctl.scala 693:81] + wire _T_8807 = _T_8806 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8817 = _T_4787 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8820 = _T_8338 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8821 = _T_8817 | _T_8820; // @[ifu_mem_ctl.scala 693:81] + wire _T_8822 = _T_8821 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8832 = _T_4788 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8835 = _T_8353 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8836 = _T_8832 | _T_8835; // @[ifu_mem_ctl.scala 693:81] + wire _T_8837 = _T_8836 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8847 = _T_4789 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8850 = _T_8368 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8851 = _T_8847 | _T_8850; // @[ifu_mem_ctl.scala 693:81] + wire _T_8852 = _T_8851 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8862 = _T_4790 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8865 = _T_8383 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8866 = _T_8862 | _T_8865; // @[ifu_mem_ctl.scala 693:81] + wire _T_8867 = _T_8866 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8877 = _T_4791 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8880 = _T_8398 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8881 = _T_8877 | _T_8880; // @[ifu_mem_ctl.scala 693:81] + wire _T_8882 = _T_8881 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8892 = _T_4792 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8895 = _T_8413 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8896 = _T_8892 | _T_8895; // @[ifu_mem_ctl.scala 693:81] + wire _T_8897 = _T_8896 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8907 = _T_4793 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8910 = _T_8428 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8911 = _T_8907 | _T_8910; // @[ifu_mem_ctl.scala 693:81] + wire _T_8912 = _T_8911 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8922 = _T_4794 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8925 = _T_8443 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8926 = _T_8922 | _T_8925; // @[ifu_mem_ctl.scala 693:81] + wire _T_8927 = _T_8926 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8937 = _T_4795 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8940 = _T_8458 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8941 = _T_8937 | _T_8940; // @[ifu_mem_ctl.scala 693:81] + wire _T_8942 = _T_8941 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8952 = _T_4796 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8955 = _T_8473 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8956 = _T_8952 | _T_8955; // @[ifu_mem_ctl.scala 693:81] + wire _T_8957 = _T_8956 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8967 = _T_4797 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8970 = _T_8488 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8971 = _T_8967 | _T_8970; // @[ifu_mem_ctl.scala 693:81] + wire _T_8972 = _T_8971 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_8982 = _T_4798 & ifu_tag_wren_ff[1]; // @[ifu_mem_ctl.scala 693:59] + wire _T_8985 = _T_8503 & perr_err_inv_way[1]; // @[ifu_mem_ctl.scala 693:124] + wire _T_8986 = _T_8982 | _T_8985; // @[ifu_mem_ctl.scala 693:81] + wire _T_8987 = _T_8986 | reset_all_tags; // @[ifu_mem_ctl.scala 693:147] + wire _T_9789 = ~fetch_uncacheable_ff; // @[ifu_mem_ctl.scala 747:63] + wire _T_9790 = _T_9789 & ifc_fetch_req_f; // @[ifu_mem_ctl.scala 747:85] wire [1:0] _T_9792 = _T_9790 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - reg _T_9799; // @[ifu_mem_ctl.scala 753:70] - reg _T_9800; // @[ifu_mem_ctl.scala 754:69] - reg _T_9801; // @[ifu_mem_ctl.scala 755:72] - wire _T_9802 = ~ifu_bus_arready_ff; // @[ifu_mem_ctl.scala 756:93] - wire _T_9803 = ifu_bus_arvalid_ff & _T_9802; // @[ifu_mem_ctl.scala 756:91] - reg _T_9805; // @[ifu_mem_ctl.scala 756:71] - reg _T_9806; // @[ifu_mem_ctl.scala 757:71] - wire _T_9809 = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h3; // @[ifu_mem_ctl.scala 764:84] - wire _T_9811 = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h2; // @[ifu_mem_ctl.scala 764:150] - wire _T_9813 = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h1; // @[ifu_mem_ctl.scala 765:63] - wire _T_9815 = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h0; // @[ifu_mem_ctl.scala 765:129] + reg _T_9799; // @[ifu_mem_ctl.scala 752:70] + reg _T_9800; // @[ifu_mem_ctl.scala 753:69] + reg _T_9801; // @[ifu_mem_ctl.scala 754:72] + wire _T_9802 = ~ifu_bus_arready_ff; // @[ifu_mem_ctl.scala 755:93] + wire _T_9803 = ifu_bus_arvalid_ff & _T_9802; // @[ifu_mem_ctl.scala 755:91] + reg _T_9805; // @[ifu_mem_ctl.scala 755:71] + reg _T_9806; // @[ifu_mem_ctl.scala 756:71] + wire _T_9809 = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h3; // @[ifu_mem_ctl.scala 763:84] + wire _T_9811 = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h2; // @[ifu_mem_ctl.scala 763:150] + wire _T_9813 = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h1; // @[ifu_mem_ctl.scala 764:63] + wire _T_9815 = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h0; // @[ifu_mem_ctl.scala 764:129] wire [3:0] _T_9818 = {_T_9809,_T_9811,_T_9813,_T_9815}; // @[Cat.scala 29:58] - reg _T_9826; // @[ifu_mem_ctl.scala 771:79] + reg _T_9826; // @[ifu_mem_ctl.scala 770:79] wire [31:0] _T_9836 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_9837 = _T_9836 | 32'h7fffffff; // @[ifu_mem_ctl.scala 774:65] - wire _T_9839 = _T_9837 == 32'h7fffffff; // @[ifu_mem_ctl.scala 774:96] - wire [31:0] _T_9843 = _T_9836 | 32'h3fffffff; // @[ifu_mem_ctl.scala 775:65] - wire _T_9845 = _T_9843 == 32'hffffffff; // @[ifu_mem_ctl.scala 775:96] - wire _T_9847 = _T_9839 | _T_9845; // @[ifu_mem_ctl.scala 774:162] - wire [31:0] _T_9849 = _T_9836 | 32'h1fffffff; // @[ifu_mem_ctl.scala 776:65] - wire _T_9851 = _T_9849 == 32'hbfffffff; // @[ifu_mem_ctl.scala 776:96] - wire _T_9853 = _T_9847 | _T_9851; // @[ifu_mem_ctl.scala 775:162] - wire [31:0] _T_9855 = _T_9836 | 32'hfffffff; // @[ifu_mem_ctl.scala 777:65] - wire _T_9857 = _T_9855 == 32'h8fffffff; // @[ifu_mem_ctl.scala 777:96] - wire ifc_region_acc_okay = _T_9853 | _T_9857; // @[ifu_mem_ctl.scala 776:162] - wire _T_9884 = ~ifc_region_acc_okay; // @[ifu_mem_ctl.scala 782:65] - wire _T_9885 = _T_3939 & _T_9884; // @[ifu_mem_ctl.scala 782:63] - wire ifc_region_acc_fault_memory_bf = _T_9885 & io_ifc_fetch_req_bf; // @[ifu_mem_ctl.scala 782:86] + wire [31:0] _T_9837 = _T_9836 | 32'h7fffffff; // @[ifu_mem_ctl.scala 773:65] + wire _T_9839 = _T_9837 == 32'h7fffffff; // @[ifu_mem_ctl.scala 773:96] + wire [31:0] _T_9843 = _T_9836 | 32'h3fffffff; // @[ifu_mem_ctl.scala 774:65] + wire _T_9845 = _T_9843 == 32'hffffffff; // @[ifu_mem_ctl.scala 774:96] + wire _T_9847 = _T_9839 | _T_9845; // @[ifu_mem_ctl.scala 773:162] + wire [31:0] _T_9849 = _T_9836 | 32'h1fffffff; // @[ifu_mem_ctl.scala 775:65] + wire _T_9851 = _T_9849 == 32'hbfffffff; // @[ifu_mem_ctl.scala 775:96] + wire _T_9853 = _T_9847 | _T_9851; // @[ifu_mem_ctl.scala 774:162] + wire [31:0] _T_9855 = _T_9836 | 32'hfffffff; // @[ifu_mem_ctl.scala 776:65] + wire _T_9857 = _T_9855 == 32'h8fffffff; // @[ifu_mem_ctl.scala 776:96] + wire ifc_region_acc_okay = _T_9853 | _T_9857; // @[ifu_mem_ctl.scala 775:162] + wire _T_9884 = ~ifc_region_acc_okay; // @[ifu_mem_ctl.scala 781:65] + wire _T_9885 = _T_3939 & _T_9884; // @[ifu_mem_ctl.scala 781:63] + wire ifc_region_acc_fault_memory_bf = _T_9885 & io_ifc_fetch_req_bf; // @[ifu_mem_ctl.scala 781:86] rvclkhdr rvclkhdr ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -5649,51 +5649,51 @@ module ifu_mem_ctl( .io_en(rvclkhdr_93_io_en), .io_scan_mode(rvclkhdr_93_io_scan_mode) ); - assign io_dec_mem_ctrl_ifu_pmu_ic_miss = _T_9799; // @[ifu_mem_ctl.scala 753:35] - assign io_dec_mem_ctrl_ifu_pmu_ic_hit = _T_9800; // @[ifu_mem_ctl.scala 754:34] - assign io_dec_mem_ctrl_ifu_pmu_bus_error = _T_9801; // @[ifu_mem_ctl.scala 755:37] - assign io_dec_mem_ctrl_ifu_pmu_bus_busy = _T_9805; // @[ifu_mem_ctl.scala 756:36] - assign io_dec_mem_ctrl_ifu_pmu_bus_trxn = _T_9806; // @[ifu_mem_ctl.scala 757:36] + assign io_dec_mem_ctrl_ifu_pmu_ic_miss = _T_9799; // @[ifu_mem_ctl.scala 752:35] + assign io_dec_mem_ctrl_ifu_pmu_ic_hit = _T_9800; // @[ifu_mem_ctl.scala 753:34] + assign io_dec_mem_ctrl_ifu_pmu_bus_error = _T_9801; // @[ifu_mem_ctl.scala 754:37] + assign io_dec_mem_ctrl_ifu_pmu_bus_busy = _T_9805; // @[ifu_mem_ctl.scala 755:36] + assign io_dec_mem_ctrl_ifu_pmu_bus_trxn = _T_9806; // @[ifu_mem_ctl.scala 756:36] assign io_dec_mem_ctrl_ifu_ic_error_start = _T_1200 | ic_rd_parity_final_err; // @[ifu_mem_ctl.scala 256:38] - assign io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err = _T_3911 & ifc_fetch_req_f; // @[ifu_mem_ctl.scala 613:46] + assign io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err = _T_3911 & ifc_fetch_req_f; // @[ifu_mem_ctl.scala 612:46] assign io_dec_mem_ctrl_ifu_ic_debug_rd_data = _T_1212; // @[ifu_mem_ctl.scala 263:40] - assign io_dec_mem_ctrl_ifu_ic_debug_rd_data_valid = _T_9826; // @[ifu_mem_ctl.scala 771:46] + assign io_dec_mem_ctrl_ifu_ic_debug_rd_data_valid = _T_9826; // @[ifu_mem_ctl.scala 770:46] assign io_dec_mem_ctrl_ifu_miss_state_idle = miss_state == 3'h0; // @[ifu_mem_ctl.scala 235:39] assign io_ifu_axi_ar_valid = ifu_bus_cmd_valid; // @[ifu_mem_ctl.scala 497:23] assign io_ifu_axi_ar_bits_id = bus_rd_addr_count & _T_2608; // @[ifu_mem_ctl.scala 498:25] assign io_ifu_axi_ar_bits_addr = _T_2610 & _T_2612; // @[ifu_mem_ctl.scala 499:27] assign io_ifu_axi_ar_bits_region = ifu_ic_req_addr_f[28:25]; // @[ifu_mem_ctl.scala 502:29] assign io_ifu_axi_r_ready = 1'h1; // @[ifu_mem_ctl.scala 504:22] - assign io_iccm_rw_addr = _T_3110 ? io_dma_mem_ctl_dma_mem_addr[15:1] : _T_3117; // @[ifu_mem_ctl.scala 600:19] + assign io_iccm_rw_addr = _T_3110 ? io_dma_mem_ctl_dma_mem_addr[15:1] : _T_3117; // @[ifu_mem_ctl.scala 599:19] assign io_iccm_buf_correct_ecc = iccm_correct_ecc & _T_2497; // @[ifu_mem_ctl.scala 395:27] assign io_iccm_correction_state = _T_2526 ? 1'h0 : _GEN_42; // @[ifu_mem_ctl.scala 430:28 ifu_mem_ctl.scala 442:32 ifu_mem_ctl.scala 449:32 ifu_mem_ctl.scala 456:32] - assign io_iccm_wren = _T_2710 | iccm_correct_ecc; // @[ifu_mem_ctl.scala 570:16] - assign io_iccm_rden = _T_2714 | _T_2715; // @[ifu_mem_ctl.scala 571:16] - assign io_iccm_wr_size = _T_2720 & io_dma_mem_ctl_dma_mem_sz; // @[ifu_mem_ctl.scala 573:19] - assign io_iccm_wr_data = _T_3092 ? _T_3093 : _T_3100; // @[ifu_mem_ctl.scala 577:19] + assign io_iccm_wren = _T_2710 | iccm_correct_ecc; // @[ifu_mem_ctl.scala 569:16] + assign io_iccm_rden = _T_2714 | _T_2715; // @[ifu_mem_ctl.scala 570:16] + assign io_iccm_wr_size = _T_2720 & io_dma_mem_ctl_dma_mem_sz; // @[ifu_mem_ctl.scala 572:19] + assign io_iccm_wr_data = _T_3092 ? _T_3093 : _T_3100; // @[ifu_mem_ctl.scala 576:19] assign io_ic_rw_addr = _T_340 | _T_341; // @[ifu_mem_ctl.scala 244:17] - assign io_ic_tag_valid = ic_tag_valid_unq & _T_9792; // @[ifu_mem_ctl.scala 748:19] - assign io_ic_wr_en = bus_ic_wr_en & _T_3974; // @[ifu_mem_ctl.scala 636:15] - assign io_ic_rd_en = _T_3966 | _T_3971; // @[ifu_mem_ctl.scala 627:15] + assign io_ic_tag_valid = ic_tag_valid_unq & _T_9792; // @[ifu_mem_ctl.scala 747:19] + assign io_ic_wr_en = bus_ic_wr_en & _T_3974; // @[ifu_mem_ctl.scala 635:15] + assign io_ic_rd_en = _T_3966 | _T_3971; // @[ifu_mem_ctl.scala 626:15] assign io_ic_wr_data_0 = ic_wr_16bytes_data[70:0]; // @[ifu_mem_ctl.scala 253:17] assign io_ic_wr_data_1 = ic_wr_16bytes_data[141:71]; // @[ifu_mem_ctl.scala 253:17] assign io_ic_debug_wr_data = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[ifu_mem_ctl.scala 254:23] - assign io_ic_debug_addr = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[9:0]; // @[ifu_mem_ctl.scala 760:20] - assign io_ic_debug_rd_en = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[ifu_mem_ctl.scala 762:21] - assign io_ic_debug_wr_en = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[ifu_mem_ctl.scala 763:21] - assign io_ic_debug_tag_array = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[16]; // @[ifu_mem_ctl.scala 761:25] - assign io_ic_debug_way = _T_9818[1:0]; // @[ifu_mem_ctl.scala 764:19] + assign io_ic_debug_addr = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[9:0]; // @[ifu_mem_ctl.scala 759:20] + assign io_ic_debug_rd_en = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[ifu_mem_ctl.scala 761:21] + assign io_ic_debug_wr_en = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[ifu_mem_ctl.scala 762:21] + assign io_ic_debug_tag_array = io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics[16]; // @[ifu_mem_ctl.scala 760:25] + assign io_ic_debug_way = _T_9818[1:0]; // @[ifu_mem_ctl.scala 763:19] assign io_ic_premux_data = ic_premux_data_temp[63:0]; // @[ifu_mem_ctl.scala 295:21] assign io_ic_sel_premux_data = fetch_req_iccm_f | sel_byp_data; // @[ifu_mem_ctl.scala 296:25] assign io_ifu_ic_mb_empty = _T_328 | _T_231; // @[ifu_mem_ctl.scala 234:22] assign io_ic_dma_active = _T_11 | io_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[ifu_mem_ctl.scala 97:20] - assign io_ic_write_stall = write_ic_16_bytes & _T_3988; // @[ifu_mem_ctl.scala 637:21] - assign io_iccm_dma_ecc_error = iccm_dma_ecc_error; // @[ifu_mem_ctl.scala 596:25] - assign io_iccm_dma_rvalid = iccm_dma_rvalid_temp; // @[ifu_mem_ctl.scala 594:22] - assign io_iccm_dma_rdata = iccm_dma_rdata_temp; // @[ifu_mem_ctl.scala 598:21] - assign io_iccm_dma_rtag = iccm_dma_rtag_temp; // @[ifu_mem_ctl.scala 589:20] - assign io_iccm_ready = _T_2706 & _T_2700; // @[ifu_mem_ctl.scala 568:17] - assign io_iccm_rd_ecc_double_err = iccm_dma_ecc_error_in & ifc_iccm_access_f; // @[ifu_mem_ctl.scala 614:29] + assign io_ic_write_stall = write_ic_16_bytes & _T_3988; // @[ifu_mem_ctl.scala 636:21] + assign io_iccm_dma_ecc_error = iccm_dma_ecc_error; // @[ifu_mem_ctl.scala 595:25] + assign io_iccm_dma_rvalid = iccm_dma_rvalid_temp; // @[ifu_mem_ctl.scala 593:22] + assign io_iccm_dma_rdata = iccm_dma_rdata_temp; // @[ifu_mem_ctl.scala 597:21] + assign io_iccm_dma_rtag = iccm_dma_rtag_temp; // @[ifu_mem_ctl.scala 588:20] + assign io_iccm_ready = _T_2706 & _T_2700; // @[ifu_mem_ctl.scala 567:17] + assign io_iccm_rd_ecc_double_err = iccm_dma_ecc_error_in & ifc_iccm_access_f; // @[ifu_mem_ctl.scala 613:29] assign io_iccm_dma_sb_error = _T_3 & dma_iccm_req_f; // @[ifu_mem_ctl.scala 95:24] assign io_ic_hit_f = _T_263 | _T_264; // @[ifu_mem_ctl.scala 195:15] assign io_ic_access_fault_f = _T_2492 & _T_319; // @[ifu_mem_ctl.scala 301:24] diff --git a/src/main/scala/ifu/ifu_mem_ctl.scala b/src/main/scala/ifu/ifu_mem_ctl.scala index c03d78db..98bbd025 100644 --- a/src/main/scala/ifu/ifu_mem_ctl.scala +++ b/src/main/scala/ifu/ifu_mem_ctl.scala @@ -506,7 +506,6 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset { val ifu_bus_arready_unq = io.ifu_axi.ar.ready val ifu_bus_rvalid_unq = io.ifu_axi.r.valid val ifu_bus_arvalid = io.ifu_axi.ar.valid - bus_ifu_bus_clk_en val ifu_bus_arready_unq_ff = withClock(busclk){RegNext(ifu_bus_arready_unq, false.B)} val ifu_bus_rvalid_unq_ff = withClock(busclk){RegNext(ifu_bus_rvalid_unq, false.B)} val ifu_bus_arvalid_ff = withClock(busclk){RegNext(ifu_bus_arvalid, false.B)} diff --git a/target/scala-2.12/classes/ifu/ifu_mem_ctl.class b/target/scala-2.12/classes/ifu/ifu_mem_ctl.class index 7172b21e66ef6f77fa6e1c3306399d085078d513..696751959654b21e3aaaeaec237d20d5fb7a5ff2 100644 GIT binary patch delta 9782 zcmZX4c|exM7B_R|1!aF;Hiehng^)#1a6v&(aaY6*mozQYYh{W{ZXj6Stu9(>mdDHm zODo*X1$RJ2z@@ZYTHSZlKyRtJeZP4I)cbvZ==|O@XJ*cvIor&`f}L)8JKb`(hzC2w zW8M@eyxD!H2;-s%a^c-^!ijtA6pcALl3exA|ES*Ok?76YiQa?wDeCHhau>R8?G!$o ztWc9(K-mh7R%oX}D;2s2B;56wxZR)z?glkep&<&bS7?z!l?t6y=%qbCbE0d7dL2K7 zub$#dg#$G{tJo^`V1WN#Acws`gB0qZ&_acB75Yh`Jqj5`7~MpV?g`8-i$Kj&)TWwR zrl^|~)lv*JYb|t?Tr6JV>e)cqKq5(V?o$1$iotmwNVMmab;6(9mVhHwb4)J*$H)?J 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