Bus Buffer Updated

dbg.anno.json

@@ -0,0 +1,81 @@
+[
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~dbg|dbg>io_dbg_dma_dbg_ib_dbg_cmd_valid",
+    "sources":[
+      "~dbg|dbg>io_dbg_dec_dbg_ib_dbg_cmd_valid",
+      "~dbg|dbg>io_dbg_dma_io_dma_dbg_ready"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~dbg|dbg>io_dbg_dec_dbg_ib_dbg_cmd_valid",
+    "sources":[
+      "~dbg|dbg>io_dbg_dma_io_dma_dbg_ready"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~dbg|dbg>io_dbg_dma_dbg_ib_dbg_cmd_addr",
+    "sources":[
+      "~dbg|dbg>io_dbg_dec_dbg_ib_dbg_cmd_addr"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~dbg|dbg>io_dbg_dma_dbg_dctl_dbg_cmd_wrdata",
+    "sources":[
+      "~dbg|dbg>io_dbg_dec_dbg_dctl_dbg_cmd_wrdata"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~dbg|dbg>io_dbg_dma_dbg_ib_dbg_cmd_type",
+    "sources":[
+      "~dbg|dbg>io_dbg_dec_dbg_ib_dbg_cmd_type"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~dbg|dbg>io_dbg_dma_dbg_ib_dbg_cmd_write",
+    "sources":[
+      "~dbg|dbg>io_dbg_dec_dbg_ib_dbg_cmd_write"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~dbg|dbg>io_dbg_resume_req",
+    "sources":[
+      "~dbg|dbg>io_dec_tlu_mpc_halted_only",
+      "~dbg|dbg>io_dec_tlu_debug_mode",
+      "~dbg|dbg>io_dbg_dec_dbg_ib_dbg_cmd_valid",
+      "~dbg|dbg>io_core_dbg_cmd_done",
+      "~dbg|dbg>io_dmi_reg_wr_en",
+      "~dbg|dbg>io_dmi_reg_en",
+      "~dbg|dbg>io_dbg_dma_io_dma_dbg_ready",
+      "~dbg|dbg>io_dmi_reg_addr",
+      "~dbg|dbg>reset"
+    ]
+  },
+  {
+    "class":"firrtl.EmitCircuitAnnotation",
+    "emitter":"firrtl.VerilogEmitter"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxResourceAnno",
+    "target":"dbg.gated_latch",
+    "resourceId":"/vsrc/gated_latch.v"
+  },
+  {
+    "class":"firrtl.options.TargetDirAnnotation",
+    "directory":"."
+  },
+  {
+    "class":"firrtl.options.OutputAnnotationFileAnnotation",
+    "file":"dbg"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
+    "targetDir":"."
+  }
+]

firrtl_black_box_resource_files.f

@@ -1,3 +1 @@
 /home/waleedbinehsan/Desktop/Quasar/gated_latch.v
-/home/waleedbinehsan/Desktop/Quasar/dmi_wrapper.sv
-/home/waleedbinehsan/Desktop/Quasar/mem.sv

lsu_bus_buffer.anno.json

@@ -0,0 +1,179 @@
+[
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_valid",
+    "sources":[
+      "~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_error"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_bus_buffer|lsu_bus_buffer>io_ld_fwddata_buf_lo",
+    "sources":[
+      "~lsu_bus_buffer|lsu_bus_buffer>io_ldst_byteen_ext_m",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_addr_m"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_bus_buffer|lsu_bus_buffer>io_ld_fwddata_buf_hi",
+    "sources":[
+      "~lsu_bus_buffer|lsu_bus_buffer>io_ldst_byteen_ext_m",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_end_addr_m"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_bus_buffer|lsu_bus_buffer>io_ld_byte_hit_buf_hi",
+    "sources":[
+      "~lsu_bus_buffer|lsu_bus_buffer>io_ldst_byteen_ext_m",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_end_addr_m"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_pmu_bus_busy",
+    "sources":[
+      "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_ar_valid",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_aw_valid",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_w_valid",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_ar_ready",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_aw_ready",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_w_ready"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_tag_m",
+    "sources":[
+      "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_r",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_r"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_bus_buffer|lsu_bus_buffer>io_ld_byte_hit_buf_lo",
+    "sources":[
+      "~lsu_bus_buffer|lsu_bus_buffer>io_ldst_byteen_ext_m",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_addr_m"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_buffer_full_any",
+    "sources":[
+      "~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_d",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_dec_lsu_valid_raw_d",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_m",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_r",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_r"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_valid_m",
+    "sources":[
+      "~lsu_bus_buffer|lsu_bus_buffer>io_ld_full_hit_m",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_pkt_m_bits_load",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_flush_m_up",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_pkt_m_valid"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_load_any",
+    "sources":[
+      "~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_error",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_store_any",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_clk_en_q"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_pmu_bus_misaligned",
+    "sources":[
+      "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_commit_r",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_r",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_r"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_pmu_bus_trxn",
+    "sources":[
+      "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_ar_valid",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_ar_ready",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_aw_valid",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_aw_ready",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_w_valid",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_w_ready"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_addr_any",
+    "sources":[
+      "~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_store_any",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_tag",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_clk_en_q"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_inv_r",
+    "sources":[
+      "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_commit_r"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_store_any",
+    "sources":[
+      "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_clk_en_q"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_pmu_bus_error",
+    "sources":[
+      "~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_load_any",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_store_any",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_error",
+      "~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_clk_en_q"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data",
+    "sources":[
+      "~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_tag"
+    ]
+  },
+  {
+    "class":"firrtl.EmitCircuitAnnotation",
+    "emitter":"firrtl.VerilogEmitter"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxResourceAnno",
+    "target":"lsu_bus_buffer.gated_latch",
+    "resourceId":"/vsrc/gated_latch.v"
+  },
+  {
+    "class":"firrtl.options.TargetDirAnnotation",
+    "directory":"."
+  },
+  {
+    "class":"firrtl.options.OutputAnnotationFileAnnotation",
+    "file":"lsu_bus_buffer"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
+    "targetDir":"."
+  }
+]

project/target/config-classes/$d9ddd45932fc49feab28.cache

@@ -0,0 +1 @@
+sbt.internal.DslEntry

project/target/config-classes/$de4b40bb5c010a8ed41c.cache

@@ -0,0 +1 @@
+sbt.internal.DslEntry

project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/inputs

@@ -1 +1 @@
-38779017
+-1177411650

project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/input_dsp

@@ -1 +1 @@
--1413115869
+23355001

project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp

@@ -1 +1 @@
-{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.10\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","startLine"],"path":"(sbt.Classpaths.jvmBaseSettings) Defaults.scala","startLine":2531},"type":"LinePosition"}}
+{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.10\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","startLine"],"path":"(sbt.Classpaths.jvmBaseSettings) Defaults.scala","startLine":2531},"type":"LinePosition"},"{\"organization\":\"org.jetbrains\",\"name\":\"sbt-structure-extractor\",\"revision\":\"2018.2.1+4-88400d3f\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/tmp/idea.sbt","range":{"$fields":["start","end"],"start":4,"end":10}},"type":"RangePosition"},"{\"organization\":\"org.jetbrains\",\"name\":\"sbt-idea-shell\",\"revision\":\"2018.3\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/tmp/idea.sbt","range":{"$fields":["start","end"],"start":4,"end":10}},"type":"RangePosition"},"{\"organization\":\"org.jetbrains\",\"name\":\"sbt-idea-compiler-indices\",\"revision\":\"0.1.3\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/tmp/idea.sbt","range":{"$fields":["start","end"],"start":4,"end":10}},"type":"RangePosition"}}

project/target/streams/_global/update/_global/streams/out

@@ -1,3 +1,3 @@
-[debug] "not up to date. inChanged = true, force = false
-[debug] Updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/Quasar/project/"), "quasar-build")...
-[debug] Done updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/Quasar/project/"), "quasar-build")
+[debug] "not up to date. inChanged = true, force = false
+[debug] Updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/Quasar/project/"), "quasar-build")...
+[debug] Done updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/Quasar/project/"), "quasar-build")

project/target/streams/runtime/dependencyClasspath/_global/streams/export

@@ -1 +1 @@
-/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes
+/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-shell/scala_2.12/sbt_1.0/2018.3/jars/sbt-idea-shell.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-compiler-indices/scala_2.12/sbt_1.0/0.1.3/jars/sbt-idea-compiler-indices.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/sugakandrey/scala-compiler-indices-protocol_2.12/0.1.1/scala-compiler-indices-protocol_2.12-0.1.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/spray/spray-json_2.12/1.3.4/spray-json_2.12-1.3.4.jar

project/target/streams/runtime/externalDependencyClasspath/_global/streams/export

@@ -1 +1 @@
-
+/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-shell/scala_2.12/sbt_1.0/2018.3/jars/sbt-idea-shell.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-compiler-indices/scala_2.12/sbt_1.0/0.1.3/jars/sbt-idea-compiler-indices.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/sugakandrey/scala-compiler-indices-protocol_2.12/0.1.1/scala-compiler-indices-protocol_2.12-0.1.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/spray/spray-json_2.12/1.3.4/spray-json_2.12-1.3.4.jar

project/target/streams/runtime/fullClasspath/_global/streams/export

@@ -1 +1 @@
-/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes
+/home/waleedbinehsan/Desktop/Quasar/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-shell/scala_2.12/sbt_1.0/2018.3/jars/sbt-idea-shell.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-compiler-indices/scala_2.12/sbt_1.0/0.1.3/jars/sbt-idea-compiler-indices.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/sugakandrey/scala-compiler-indices-protocol_2.12/0.1.1/scala-compiler-indices-protocol_2.12-0.1.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/spray/spray-json_2.12/1.3.4/spray-json_2.12-1.3.4.jar

project/target/streams/runtime/managedClasspath/_global/streams/export

@@ -1 +1 @@
-
+/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-shell/scala_2.12/sbt_1.0/2018.3/jars/sbt-idea-shell.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-compiler-indices/scala_2.12/sbt_1.0/0.1.3/jars/sbt-idea-compiler-indices.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/sugakandrey/scala-compiler-indices-protocol_2.12/0.1.1/scala-compiler-indices-protocol_2.12-0.1.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/spray/spray-json_2.12/1.3.4/spray-json_2.12-1.3.4.jar

src/main/scala/dbg/dbg.scala

@@ -103,23 +103,23 @@ class dbg extends Module with lib with RequireAsyncReset {
     ((io.dmi_reg_addr === "h39".U) | (io.dmi_reg_addr === "h3c".U) | (io.dmi_reg_addr === "h3d".U)))
 
   val sbcs_sbbusyerror_din = (~(sbcs_wren & io.dmi_reg_wdata(22))).asUInt()
-  val temp_sbcs_22 = withClockAndReset(sb_free_clk, !dbg_dm_rst_l) {
+  val temp_sbcs_22 = withClockAndReset(sb_free_clk, (!dbg_dm_rst_l).asAsyncReset()) {
     RegEnable(sbcs_sbbusyerror_din, 0.U, sbcs_sbbusyerror_wren)
   } // sbcs_sbbusyerror_reg
 
-  val temp_sbcs_21 = withClockAndReset(sb_free_clk, !dbg_dm_rst_l) {
+  val temp_sbcs_21 = withClockAndReset(sb_free_clk, (!dbg_dm_rst_l).asAsyncReset()) {
     RegEnable(sbcs_sbbusy_din, 0.U, sbcs_sbbusy_wren)
   } // sbcs_sbbusy_reg
 
-  val temp_sbcs_20 = withClockAndReset(sb_free_clk, !dbg_dm_rst_l) {
+  val temp_sbcs_20 = withClockAndReset(sb_free_clk, (!dbg_dm_rst_l).asAsyncReset()) {
     RegEnable(io.dmi_reg_wdata(20), 0.U, sbcs_wren)
   } // sbcs_sbreadonaddr_reg
 
-  val temp_sbcs_19_15 = withClockAndReset(sb_free_clk, !dbg_dm_rst_l) {
+  val temp_sbcs_19_15 = withClockAndReset(sb_free_clk, (!dbg_dm_rst_l).asAsyncReset()) {
     RegEnable(io.dmi_reg_wdata(19, 15), 0.U, sbcs_wren)
   } // sbcs_misc_reg
 
-  val temp_sbcs_14_12 = withClockAndReset(sb_free_clk, !dbg_dm_rst_l) {
+  val temp_sbcs_14_12 = withClockAndReset(sb_free_clk, (!dbg_dm_rst_l).asAsyncReset()) {
     RegEnable(sbcs_sberror_din(2, 0), 0.U, sbcs_sberror_wren)
   } // sbcs_error_reg
   sbcs_reg := Cat(1.U(3.W), 0.U(6.W), temp_sbcs_22, temp_sbcs_21, temp_sbcs_20, temp_sbcs_19_15, temp_sbcs_14_12, "h20".U(7.W), "b01111".U(5.W))
@@ -144,11 +144,11 @@ class dbg extends Module with lib with RequireAsyncReset {
   val sbdata1_din = Fill(32, sbdata1_reg_wren0) & io.dmi_reg_wdata |
     Fill(32, sbdata1_reg_wren1) & sb_bus_rdata(63, 32)
 
-  val sbdata0_reg = withReset(!dbg_dm_rst_l) {
+  val sbdata0_reg = withReset((!dbg_dm_rst_l).asAsyncReset()) {
     rvdffe(sbdata0_din, sbdata0_reg_wren, clock, io.scan_mode)
   } // dbg_sbdata0_reg
 
-  val sbdata1_reg = withReset(!dbg_dm_rst_l) {
+  val sbdata1_reg = withReset((!dbg_dm_rst_l).asAsyncReset()) {
     rvdffe(sbdata1_din, sbdata1_reg_wren, clock, io.scan_mode)
   } // dbg_sbdata1_reg
 
@@ -156,7 +156,7 @@ class dbg extends Module with lib with RequireAsyncReset {
   val sbaddress0_reg_wren = sbaddress0_reg_wren0 | sbaddress0_reg_wren1
   val sbaddress0_reg_din = Fill(32, sbaddress0_reg_wren0) & io.dmi_reg_wdata |
     Fill(32, sbaddress0_reg_wren1) & (sbaddress0_reg + Cat(0.U(28.W), sbaddress0_incr))
-  sbaddress0_reg := withReset(!dbg_dm_rst_l) {
+  sbaddress0_reg := withReset((!dbg_dm_rst_l).asAsyncReset()) {
     rvdffe(sbaddress0_reg_din, sbaddress0_reg_wren, clock, io.scan_mode)
   } // dbg_sbaddress0_reg
 
@@ -164,20 +164,20 @@ class dbg extends Module with lib with RequireAsyncReset {
   val sbreadondata_access = io.dmi_reg_en & !io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3c".U) & sbcs_reg(15)
   val sbdata0wr_access = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3c".U)
   val dmcontrol_wren = (io.dmi_reg_addr === "h10".U) & io.dmi_reg_en & io.dmi_reg_wr_en
-  val dm_temp = withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) {
+  val dm_temp = withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l).asAsyncReset()) {
     RegEnable(
       Cat(io.dmi_reg_wdata(31, 30), io.dmi_reg_wdata(28), io.dmi_reg_wdata(1)),
       0.U, dmcontrol_wren)
   } // dmcontrolff
 
-  val dm_temp_0 = withClockAndReset(dbg_free_clk, io.dbg_rst_l) {
+  val dm_temp_0 = withClockAndReset(dbg_free_clk, io.dbg_rst_l.asAsyncReset()) {
     RegEnable(io.dmi_reg_wdata(0), 0.U, dmcontrol_wren)
   } // dmcontrol_dmactive_ff
 
   val temp = Cat(dm_temp(3, 2), 0.U, dm_temp(1), 0.U(26.W), dm_temp(0), dm_temp_0)
   dmcontrol_reg := temp
 
-  val dmcontrol_wren_Q = withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) {
+  val dmcontrol_wren_Q = withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l).asAsyncReset()) {
     RegNext(dmcontrol_wren, 0.U)
   } // dmcontrol_wrenff
 
@@ -190,15 +190,15 @@ class dbg extends Module with lib with RequireAsyncReset {
   val temp_rst = reset.asBool()
   dmstatus_unavail := (dmcontrol_reg(1) | !(temp_rst)).asBool()
   dmstatus_running := ~(dmstatus_unavail | dmstatus_halted)
-  dmstatus_resumeack := withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) {
+  dmstatus_resumeack := withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l).asAsyncReset()) {
     RegEnable(dmstatus_resumeack_din, 0.U, dmstatus_resumeack_wren)
   } // dmstatus_resumeack_reg
 
-  dmstatus_halted := withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) {
+  dmstatus_halted := withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l).asAsyncReset()) {
     RegNext(io.dec_tlu_dbg_halted & !io.dec_tlu_mpc_halted_only, 0.U)
   } // dmstatus_halted_reg
 
-  dmstatus_havereset := withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) {
+  dmstatus_havereset := withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l).asAsyncReset()) {
     RegEnable(~dmstatus_havereset_rst, 0.U, dmstatus_havereset_wren)
   } // dmstatus_havereset_reg
 
@@ -222,11 +222,11 @@ class dbg extends Module with lib with RequireAsyncReset {
     (Fill(3, abstractcs_error_sel5) & (~io.dmi_reg_wdata(10, 8)).asUInt() & abstractcs_reg(10, 8)) |
     (Fill(3, (~abstractcs_error_selor).asUInt()) & abstractcs_reg(10, 8))
 
-  val abs_temp_12 = withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) {
+  val abs_temp_12 = withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l).asAsyncReset()) {
     RegEnable(abstractcs_busy_din, 0.U, abstractcs_busy_wren)
   } // dmabstractcs_busy_reg
 
-  val abs_temp_10_8 = withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) {
+  val abs_temp_10_8 = withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l).asAsyncReset()) {
     RegNext(abstractcs_error_din(2, 0), 0.U)
   } // dmabstractcs_error_reg
 
@@ -234,7 +234,7 @@ class dbg extends Module with lib with RequireAsyncReset {
 
   val command_wren = (io.dmi_reg_addr === "h17".U) & io.dmi_reg_en & io.dmi_reg_wr_en & (dbg_state === state_t.halted)
   val command_din = Cat(io.dmi_reg_wdata(31, 24), 0.U(1.W), io.dmi_reg_wdata(22, 20), 0.U(3.W), io.dmi_reg_wdata(16, 0))
-  val command_reg = withReset(!dbg_dm_rst_l) {
+  val command_reg = withReset((!dbg_dm_rst_l).asAsyncReset()) {
     RegEnable(command_din, 0.U, command_wren)
   } // dmcommand_reg
 
@@ -243,13 +243,13 @@ class dbg extends Module with lib with RequireAsyncReset {
 
   val data0_reg_wren = data0_reg_wren0 | data0_reg_wren1
   val data0_din = Fill(32, data0_reg_wren0) & io.dmi_reg_wdata | Fill(32, data0_reg_wren1) & io.core_dbg_rddata
-  val data0_reg = withReset(!dbg_dm_rst_l) {
+  val data0_reg = withReset((!dbg_dm_rst_l).asAsyncReset()) {
     RegEnable(data0_din, 0.U, data0_reg_wren)
   } // dbg_data0_reg
 
   val data1_reg_wren = (io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h5".U) & (dbg_state === state_t.halted))
   val data1_din = Fill(32, data1_reg_wren) & io.dmi_reg_wdata
-  data1_reg := withReset(!dbg_dm_rst_l) {
+  data1_reg := withReset((!dbg_dm_rst_l).asAsyncReset()) {
     rvdffe(data1_din, data1_reg_wren, clock, io.scan_mode)
   } // dbg_data1_reg
 
@@ -311,13 +311,13 @@ class dbg extends Module with lib with RequireAsyncReset {
     Fill(32, io.dmi_reg_addr === "h40".U) & haltsum0_reg | Fill(32, io.dmi_reg_addr === "h38".U) & sbcs_reg |
     Fill(32, io.dmi_reg_addr === "h39".U) & sbaddress0_reg | Fill(32, io.dmi_reg_addr === "h3c".U) & sbdata0_reg |
     Fill(32, io.dmi_reg_addr === "h3d".U) & sbdata1_reg
-
-  dbg_state := withClockAndReset(dbg_free_clk, !dbg_dm_rst_l & temp_rst) {
+0
+  dbg_state := withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l & temp_rst).asAsyncReset()) {
     RegEnable(dbg_nxtstate, 0.U, dbg_state_en)
   } // dbg_state_reg
 
 
-  io.dmi_reg_rdata := withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) {
+  io.dmi_reg_rdata := withClockAndReset(dbg_free_clk, (!dbg_dm_rst_l).asAsyncReset()) {
     RegEnable(dmi_reg_rdata_din, 0.U, io.dmi_reg_en)
   } // dmi_rddata_reg
 
@@ -394,7 +394,7 @@ class dbg extends Module with lib with RequireAsyncReset {
       sbaddress0_reg_wren1 := sbcs_reg(16)
     }}
 
-  sb_state := withClockAndReset(sb_free_clk, !dbg_dm_rst_l) {
+  sb_state := withClockAndReset(sb_free_clk, (!dbg_dm_rst_l).asAsyncReset()) {
     RegEnable(sb_nxtstate, 0.U, sb_state_en)
   } // sb_state_reg
 
@@ -450,3 +450,6 @@ class dbg extends Module with lib with RequireAsyncReset {
   io.dbg_dma.dbg_ib.dbg_cmd_write     := io.dbg_dec.dbg_ib.dbg_cmd_write
   io.dbg_dma.dbg_ib.dbg_cmd_type      := io.dbg_dec.dbg_ib.dbg_cmd_type
 }
+object dbg_top extends App {
+  println((new chisel3.stage.ChiselStage).emitVerilog(new dbg()))
+}

src/main/scala/dec/dec_tlu_ctl.scala

@@ -2119,7 +2119,7 @@ miccme_ce_req := (("hffffffff".U(32.W) << miccmect(31,27)) & Cat(0.U(5.W), miccm
 
  val dicad0h = rvdffe(dicad0h_ns,(wr_dicad0h_r | io.ifu_ic_debug_rd_data_valid).asBool,clock,io.scan_mode)
 
- if (ICACHE_ECC == true) {
+ if (ICACHE_ECC) {
  // ----------------------------------------------------------------------
  // DICAD1 (R/W) (Only accessible in debug mode)
  // [6:0]     : ECC
@@ -2152,7 +2152,7 @@ miccme_ce_req := (("hffffffff".U(32.W) << miccmect(31,27)) & Cat(0.U(5.W), miccm
  // DICAGO (R/W) (Only accessible in debug mode)
  // [0]     : Go
 
- if (ICACHE_ECC == true)  io.dec_tlu_ic_diag_pkt.icache_wrdata := Cat(dicad1(6,0), dicad0h(31,0), dicad0(31,0))
+ if (ICACHE_ECC)  io.dec_tlu_ic_diag_pkt.icache_wrdata := Cat(dicad1(6,0), dicad0h(31,0), dicad0(31,0))
  else    io.dec_tlu_ic_diag_pkt.icache_wrdata := Cat(0.U(2.W),dicad1(3,0), dicad0h(31,0), dicad0(31,0))
 
  io.dec_tlu_ic_diag_pkt.icache_dicawics := dicawics

src/main/scala/lib/lib.scala

@@ -86,7 +86,7 @@ trait lib extends param{
     matchvec(0)  :=  masken_or_fullmask | (mask(0) === data(0)).asUInt
     for(i <- 1 to data.getWidth-1)
     matchvec(i) := Mux(mask(i-1,0).andR & masken_or_fullmask,"b1".U,(mask(i) === data(i)).asUInt)
-    matchvec.asUInt.andR()
+    matchvec.asUInt
   }
 
   ///////////////////////////////////////////////////////////////////

src/main/scala/lsu/lsu_bus_buffer.scala

@@ -5,7 +5,6 @@ import lib._
 import include._
 import chisel3.experimental.{ChiselEnum, chiselName}
 import chisel3.util.ImplicitConversions.intToUInt
-import ifu._
 
 @chiselName
 class  lsu_bus_buffer extends Module with RequireAsyncReset with lib {
@@ -296,6 +295,7 @@ class  lsu_bus_buffer extends Module with RequireAsyncReset with lib {
   val obuf_merge_en = WireInit(Bool(), false.B)
   val obuf_merge_in = obuf_merge_en
   val obuf_tag0_in = Mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0)
+  //val Cmdptr1 = WireInit(UInt(DEPTH_LOG2.W), 0.U)
 
   val obuf_tag1_in = Mux(ibuf_buf_byp, WrPtr1_r, CmdPtr1)
   val obuf_cmd_done = WireInit(Bool(), false.B)
@@ -552,7 +552,7 @@ class  lsu_bus_buffer extends Module with RequireAsyncReset with lib {
   bus_addr_match_pending := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===resp_C)->
     (BUILD_AXI_NATIVE.B & obuf_valid & (obuf_addr(31,3)===buf_addr(i)(31,3)) & !((obuf_tag0===i.U) | (obuf_merge & (obuf_tag1===i.U))))))
 
-  bus_cmd_ready := Mux(obuf_write, Mux(obuf_cmd_done | obuf_data_done, Mux(obuf_cmd_done, io.lsu_axi.w.ready, io.lsu_axi.aw.ready), io.lsu_axi.aw.ready & io.lsu_axi.aw.ready), io.lsu_axi.ar.ready)
+  bus_cmd_ready := Mux(obuf_write, Mux(obuf_cmd_done | obuf_data_done, Mux(obuf_cmd_done, io.lsu_axi.w.ready, io.lsu_axi.aw.ready), io.lsu_axi.aw.ready & io.lsu_axi.w.ready), io.lsu_axi.ar.ready)
   bus_wcmd_sent := io.lsu_axi.aw.valid & io.lsu_axi.aw.ready
   bus_wdata_sent := io.lsu_axi.w.valid & io.lsu_axi.w.ready
   bus_cmd_sent := ((obuf_cmd_done | bus_wcmd_sent) & (obuf_data_done | bus_wdata_sent)) | (io.lsu_axi.ar.valid & io.lsu_axi.ar.ready)
@@ -616,3 +616,6 @@ class  lsu_bus_buffer extends Module with RequireAsyncReset with lib {
   io.lsu_busreq_r := withClock(io.lsu_c2_r_clk){RegNext(io.lsu_busreq_m & !io.flush_r & !io.ld_full_hit_m, false.B)}
   lsu_nonblock_load_valid_r := withClock(io.lsu_c2_r_clk){RegNext(io.dctl_busbuff.lsu_nonblock_load_valid_m, false.B)}
 }
+object bus_buffer extends App {
+  println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_bus_buffer()))
+}