IMC DONE

src/main/scala/ifu/el2_ifu_mem_ctl.scala

@@ -632,11 +632,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
   io.iccm_rden := (ifc_dma_access_q_ok & io.dma_iccm_req & !io.dma_mem_write) | (io.ifc_iccm_access_bf & io.ifc_fetch_req_bf)
   val iccm_dma_rden = ifc_dma_access_q_ok & io.dma_iccm_req & !io.dma_mem_write
   io.iccm_wr_size := Fill(3, io.dma_iccm_req) & io.dma_mem_sz
-  val m1 = Module(new rvecc_encode)
+  val dma_mem_ecc = Cat(rvecc_encode(io.dma_mem_wdata(63,32)), rvecc_encode(io.dma_mem_wdata(31,0)))
-  m1.io.din := io.dma_mem_wdata(31,0)
-  val m2 = Module(new rvecc_encode)
-  m2.io.din := io.dma_mem_wdata(63,32)
-  val dma_mem_ecc = Cat(m2.io.ecc_out, m1.io.ecc_out)
   val iccm_ecc_corr_data_ff = WireInit(UInt(39.W), 0.U)
   io.iccm_wr_data := Mux(iccm_correct_ecc & !(ifc_dma_access_q_ok & io.dma_iccm_req), Fill(2,iccm_ecc_corr_data_ff),
     Cat(dma_mem_ecc(13,7),io.dma_mem_wdata(63,32), dma_mem_ecc(6,0), io.dma_mem_wdata(31,0)))

src/main/scala/lib/el2_lib.scala

@@ -240,7 +240,7 @@ trait el2_lib extends param{
   }
 
   // Move rvecc_encode to a proper trait
-  def rvecc_encode(din:UInt) = {   //Done for verification and testing
+  def rvecc_encode(din:UInt):UInt = {
     val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0)
     val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1)
     val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1)
@@ -265,7 +265,8 @@ trait el2_lib extends param{
       if(mask5(i)==1) {w5(z) := din(i); z = z +1 }
     }
     val w6 = Cat((w5.asUInt.xorR),(w4.asUInt.xorR),(w3.asUInt.xorR),(w2.asUInt.xorR),(w1.asUInt.xorR),(w0.asUInt.xorR))
-    Cat(din.xorR ^ w6.xorR, w6)
+    val ecc_out = Cat(din.xorR ^ w6.xorR, w6)
+    ecc_out
   }
 
   class rvecc_encode extends Module{   //Done for verification and testing